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Lab-PC+ User Manual - scs.etti.tuiasi.ro

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2. Chapter 2 Configuration and Installation Table 2 4 Analog I O Jumper Settings Configuration Jumper Settings Output CHO Polarity Bipolar 5 V factory setting W1 A B Unipolar 0 to 10 V WI B C Output CH1 Polarity Bipolar 5 V factory setting W2 A B Unipolar 0 to 10 V W2 B Input Range Bipolar 5 V factory setting W3 A B Unipolar 0 to 10 V W3 B C Input Mode Referenced single ended RSE factory setting Nonreferenced single ended NRSE Differential DIFF Analog Output Configuration Two ranges are available for the analog outputs bipolar 5 V and unipolar 0 to 10 V Jumper W1 controls output Channel 0 and W2 controls output Channel 1 Bipolar Output Selection You can select the bipolar 5 V output configuration for either analog output channel by setting the following jumpers Analog Output Channel 0 WI A B Analog Output Channel 1 W2 A B This configuration 1s shown in Figure 2 7 Channel 0 Channel 1 Figure 2 7 Bipolar Output Jumper Configuration Factory Setting National Instruments Corporation 2 9 Lab PC User Manual Configuration and Installation Chapter 2 Unipolar Output Selection You can select the unipolar 0 V to 10 V output configuration for either analog output channel by setting the following jumpers Analog Output Channel 0 WI B C Analog Output Channel 1 W2 B C This configuration is shown in Figure 2 8 Channel 0 Channel 1 Figure 2 8 Unipolar Outp
3. Mode 1 Input RE IBF STBA INTRA STBg IBFBp INTRp Mode 1 Output OBF ACK jo fuo INTRA ACKp OBFp INTRB Indicates that the signal is active low Timing Specifications The handshaking lines STB and IBF are used to synchronize input transfers The handshaking lines OBF and ACK are used to synchronize output transfers The following signals are used in the timing diagrams shown later in this chapter Name Type STB Input IBF Output ACK Input Lab PC User Manual Description Strobe input A low signal on this handshaking line loads data into the input latch Input buffer full A high signal on this handshaking line indicates that data has been loaded into the input latch This is primarily an input acknowledge signal Acknowledge input A low signal on this handshaking line indicates that the data written from the specified port has been accepted This signal is primarily a response from the external device that it has received the data from the Lab PC 3 16 National Instruments Corporation Chapter 3 Name OBF INTR RD WR DATA Type Output Output Internal Internal Bidirectional Signal Connections Description continued Output buffer full A low signal on this handshaking line indicates that data has been written from the specified port Interrupt request This signal becomes high when the 8255A is requesting service during a data transfer The ap
4. Register Map and Descriptions Appendix D Timer Interrupt Clear Register Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the Counter A2 output or on EXTUPDATE line Address Base address OC hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Lab PC User Manual D 28 National Instruments Corporation Appendix D Register Map and Descriptions Counter BO Data Register The Counter BO Data Register is used for loading and reading back the contents of 8253 B Counter 0 Address Base address 18 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 ov w DS w p e DT DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter BO contents National Instruments Corporation D 29 Lab PC User Manual Register Map and Descriptions Appendix D Counter B1 Data Register The Counter B1 Data Register is used for loading and reading back the contents of 8253 B Counter 1 Address Base address 19 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 ov w DS w w R DT DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter B1 contents Lab PC User Manual D 30 National Instruments Corporation Appendix D Register Map and Descriptions Counter B2 Data Register The Counter B2 Data Register is used for loading and reading back the contents of 8253 B Counter 2 Ad
5. 2 Write the channel number and gain in Command Register 1 Write 0 to the SCANEN bit 3 Write 1 to the INTSCAN bit in Command Register 4 Configure the EOIRCV bit with the desired value 4 Configure the remainder of the data acquisition circuitry as specified in any of the previous outlines 5 After programming the sample interval counter Counter AO and the sample counter Counter A1 or configuring the circuitry to use EXTCONV configure the interval scanning counter Counter B1 if necessary Use the following sequence to program the interval scanning counter All writes are 8 bit write operations All values are hexadecimal a Write 74 to the Counter B Mode Register select Mode 2 b Write the least significant byte of the interval count to the Counter B1 Data Register c Write the most significant byte of the scan interval count to the Counter B1 Data Register 6 Use a software trigger to initiate the operation Note that you must program the sample counter Counter A1 for the total number of samples desired For example if you want to acquire 2 000 samples in batches of 100 load the Interval Counter with 100 and load the sample counter with 2 000 A D Interrupt Programming Two different interrupts are generated by the A D circuitry e An interrupt whenever a conversion is available to be read for FIFO e An interrupt whenever an error condition overflow or overrun is detected These two interrupts are enabled in
6. 5 to 5 V Hex Lab PC User Manual E 4 National Instruments Corporation Appendix E Register Level Programming Clearing the Analog Input Circuitry The analog input circuitry can be cleared by writing to the A D Clear Register which leaves the analog input circuitry in the following state e Analog input error flags OVERFLOW and OVERRUN are cleared e Pending interrupt requests are cleared e A D FIFO has one garbage word of data Empty the A D FIFO before starting any A D conversions by performing two 8 bit reads on the A D FIFO Register and ignoring the data read This operation guarantees that the A D conversion results read from the A D FIFO are the results from the initiated conversions rather than leftover results from previous conversions To clear the analog input circuitry and the A D FIFO complete these steps e Write 0 to the A D Clear Register 8 bit write e Read the A D FIFO Register twice and ignore the data 8 bit read Programming Multiple A D Conversions on a Single Input Channel A sequence of timed A D conversions is referred to in this manual as a data acquisition operation Two types of data acquisition operations are available on the Lab PC e Controlled acquisition mode e Freerun acquisition mode In controlled acquisition mode two counters Counters AO and A1 are required for a data acquisition operation Counter AQ is used as a sample interval counter while Counter A1 is used as a sample
7. Branch Offices Australia Austria Belgium Canada Ontario Canada Quebec Denmark Finland France Germany Hong Kong Italy Japan Korea Mexico Netherlands Norway Singapore Spain Sweden Switzerland Taiwan UK Phone Number 03 9 879 9422 0662 45 79 90 0 02 757 00 20 519 622 9310 514 694 8521 45 76 26 00 90 527 2321 1 48 14 24 24 089 741 31 30 2645 3186 02 413091 03 5472 2970 02 596 7456 95 800 010 0793 0348 433466 32 84 84 00 2265886 91 640 0085 08 730 49 70 056 200 51 51 02 377 1200 01635 523545 National Instruments Corporation F Fax Number 03 9 879 9179 0662 45 79 90 19 02 757 03 11 514 694 4399 45 76 26 02 90 502 2930 1 48 14 24 14 089 714 60 35 2686 8505 02 41309215 03 5472 2977 02 596 7455 5 520 3282 0348 430673 32 84 86 00 2265887 91 640 0533 08 730 43 70 056 200 51 55 02 737 4644 01635 523154 Lab PC User Manual Technical Support Form Photocopy this form and update it each time you make changes to your software or hardware and use the completed copy of this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently If you are using any National Instruments hardware or software products related to this problem include the configuration forms from their user manuals Include additional pages if necessa
8. Figure 3 1 Lab PC I O Connector Pin Assignments Signal Connection Descriptions The following list describes the connector pins on the Lab PC I O connector by pin number and gives the signal name and the significance of each signal connector pin Lab PC User Manual 3 2 National Instruments Corporation Chapter 3 Signal Name Signal Connections Description 1 8 ACHO through ACH7 Analog input Channels 0 through 7 single ended 9 AISENSE AIGND Analog input ground in RSE mode AISENSE in NRSE mode Bi directional 10 DACO OUT Voltage output signal for analog output Channel 0 11 AGND Analog ground Analog output ground for analog output mode Analog input ground for DIFF or NRSE mode Bi directional 12 DACI OUT Voltage output signal for analog output Channel 1 13 DGND Digital ground Output 14 21 PAO through PA7 Bidirectional data lines for Port A PA7 is the MSB PAO the LSB 22 29 PBO through PB7 Bidirectional data lines for Port B PB7 is the MSB PBO the LSB 30 37 PCO through PC7 Bidirectional data lines for Port C PC7 is the MSB PCO the LSB 38 EXTTRIG External control signal to start a timed conversion sequence Input 39 EXTUPDATE External control signal to update DAC outputs Input 40 EXTCONV External control signal to trigger A D conversions Bi directional 41 OUTBO Counter BO output 42 GATBO Counter BO gate Input 43 COUTBI
9. PC Bus Interface Factory Settings Lab PC Board Default Settings Hardware Implementation Hormrmwown Base I O Address LLL PT DMA Channel DMA Channel 3 W6 DRQ3 DACK 3 factory setting Interrupt Level Interrupt level 5 selected W5 Row 5 factory setting Note The shaded portion indicates the side of the switch that is pressed down Base I O Address Selection The base I O address for the Lab PC is determined by the switches at position U1 see Figure 2 1 The switches are set at the factory for the base I O address hex 260 This factory setting is used as the default base I O address value by National Instruments software packages for use with the Lab PC The Lab PC uses the base I O address space hex 260 through 27F with the factory setting Note Verify that this space is not already used by other equipment installed in your computer If any equipment in your computer uses this base I O address space you must change the base I O address of the Lab PC or of the other device If you change the Lab PC base I O address you must make a corresponding change to any software packages you use with the Lab PC For more information about your computer s I O refer to your computer s technical reference manual Each switch in U1 corresponds to one of the address lines A9 through A5 Press the side marked OFF to select a binary value of 1 for the corresponding address bit Press the other side of the switch to select a bi
10. PC bus interface 2 1 factory settings table 2 3 parts locator diagram 2 2 Configuration and Status Register Group D 4 to D 14 Command Register 1 channel scanning E 17 controlled acquisition mode E 6 posttrigger mode E 12 pretrigger mode E 14 description D 5 to D 6 freerun acquisition mode E 9 selecting analog input channel E 3 single channel interval acquisition mode E 19 Command Register 2 D 9 to D 10 Command Register 3 description D 11 to D 12 digital I O circuitry programming E 34 Command Register 4 description D 13 to D 14 single channel interval acquisition mode E 19 overview D 4 register map table D 2 Status Register analog input circuitry programming E 3 controlled data acquisition programming E 8 posttrigger mode E 13 pretrigger mode E 16 description D 7 to D 8 freerun data acquisition programming E 10 control word format control word flag set to 0 figure E 24 control word flag set to 1 figure E 24 control words Mode 0 operation E 25 to E 26 Mode 1 input E 27 Mode 1 output E 29 Mode 2 operation E 31 to E 32 controlled acquisition mode multiple A D conversions external timing E 12 to E 16 posttrigger mode E 12 to E 14 pretrigger mode E 14 to E 16 overview E 5 programming steps E 6 to E 8 National Instruments Corporation Index single input channel E 6 to E 8 CONVERT signal posttrigger data acquisition timing figure 3 22 Counter A Mode Register descript
11. for multiple A D conversions on a single input channel The Lab PC can also be programmed for scanning analog input channels during the data acquisition operation Analog channels N through 0 can be scanned where N can be through 7 Programming scanned multiple A D conversions involves the same sequence of steps as single channel data acquisition operations except that the SCANEN bit is set in Command Register 1 When the SCANEN bit is set in Command Register 1 the analog channel select bits MA lt 2 0 gt specify the highest numbered channel in the scan sequence For example if MA lt 2 0 gt is 011 binary that is Channel 3 is selected and the SCANEN bit is set the following scan sequence is used Channel 3 Channel 2 Channel 1 Channel 0 Channel 3 Channel 2 Channel 1 Channel 0 Channel 3 and so on Note Selecting the analog input channel and gain should be performed in the following order 1 Write the configuration value indicating the highest channel number in the scan sequence the gain and the input polarity to Command Register 1 The SCANEN bit must be cleared during this first write to Command Register 1 2 Write the same configuration value again to Command Register 1 The SCANEN bit however must be set during the second write to Command Register 1 Scanning can be enabled in either controlled or freerun acquisition mode Either Counter AO or EXTCONV can be used to control the scanning interval Programming Multip
12. 0to 0 1 V 45 V powered on 45 V powered off ACH lt 0 7 gt 512 samples DMA interrupts programmed I O Single transfer 1 0 LSB typ 1 5 LSB max 0 5 LSB typ 1 LSB max 12 bits guaranteed Adjustable to 0 V Adjustable to 0 V Adjustable to 0 0 76 of reading 7 600 ppm max 0 5 of reading 500 ppm max A 1 Lab PC User Manual Specifications Amplifier Characteristics Input impedance 5 secs este cent teenie tens en Input bias current CMRR CMRR at 60 Hz Appendix A 0 1 GQ in parallel with 45 pF 150 pA 1 75 dB 100 105 dB Dynamic Characteristics Bandwidth 3 dB cccccsesscccceceeeeeeserseceees Settling time to full scale step System noise 400 kHz for gain 1 40 kHz for gain 100 Accuracy 0 2 LSB 14 us 20 us 33 Us lt 10 20 50 100 5 V Range 1 0 3 LSB rms 100 0 6 LSB rms 15 minutes Stability Recommended warm up time Offset temperature coefficient P gase dis Nes ns POS IS AIRES ES Ni nc Gain temperature coefficient Lab PC User Manual 450 uV C 10 uV C 50 ppm C A 2 National Instruments Corporation Appendix A Specifications Explanation of Analog Input Specifications Relative accuracy is a measure of the linearity of an ADC However relative accuracy is a tighter specification than a nonlinearity specification Relative accuracy indicates the maximum deviation from a straight line for the analog input to digital outp
13. 1 data read transfer the status of the handshaking lines and interrupt signals can be obtained by reading Port C The Port C status word bit definitions for an input transfer are shown next National Instruments Corporation E 27 Lab PC User Manual Register Level Programming Appendix E Port C status word bit definitions for input Port A and Port B 7 6 5 4 3 2 1 0 IBFA INTEA INTRA INTEB IBFB INTRB Bit Name Description 7 6 VO Extra I O status lines when Port A is in Mode 1 input 5 IBFA Input buffer full for Port A High indicates that data has been loaded into the input latch for Port A 4 INTEA Interrupt enable bit for Port A Enables interrupts from the 8255A for Port A Controlled by bit set reset of PC4 3 INTRA Interrupt request status for Port A When INTEA is high and IBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B Enables interrupts from the 8255A for Port B Controlled by bit set reset of PC2 1 IBFB Input buffer full for Port B High indicates that data has been loaded into the input latch for Port B 0 INTRB Interrupt request status for Port B When INTEB is high and IBFB is high this bit is high indicating that an interrupt request is asserted At the digital I O connector Port C has the following pin assignments when in Mode 1 input Notice that the status of STBA and STBB is not provided in the Port C status word 1 0 1 0 IBFA
14. 11 illustrate two possible posttrigger data acquisition timing cases In Figure 3 10 the rising edge on EXTTRIG is sensed when the EXTCONV input is high Thus the first A D conversion occurs on the second falling edge of EXTCONV after the rising edge on EXTTRIG In Figure 3 11 the rising edge on EXTTRIG is sensed when the EXTCONV input is low In this case the first A D conversion occurs on the first falling edge of EXTCONV after the rising edge on EXTTRIG Notice that Figures 3 10 and 3 11 show a controlled acquisition mode data acquisition sequence that is Sample Counter A1 disables further A D conversions after the programmed count 3 in the examples shown in Figures 3 10 and 3 11 expires The counter is not loaded with the programmed count until the first falling edge following a rising edge on the clock input therefore two extra conversion pulses are generated as shown in Figures 3 10 and 3 11 EXTTRIG can also be used as an external trigger in freerun acquisition mode tw VH EXTTRIG lt 1 VIL tw 50 nsec minimum CONVERT Conte x __Kx fs 21 0 Figure 3 10 Posttrigger Data Acquisition Timing Case 1 gt w Vi EXTTRIG lt 1 Vit ty 50 nsec minimum i tq 50 nsec minimum CONVERT Sample Counter Figure 3 11 Posttrigger Data Acquisition Timing Case 2 Lab PC User Manual 3 22 National Instruments Corporation Chapter 3 Signal Connections If PRETRIG is set EXTTRIG serves as
15. 2 7 factory settings figure 2 6 NRSE input 2 13 PC bus interface factory settings table 2 3 RSE input 2 12 unipolar output figure 2 10 L Lab PC block diagram 4 1 initializing E 1 to E 2 optional equipment 1 4 overview 1 1 requirements 1 1 software programming choices LabVIEW and LabWindows CVI software 1 2 NI DAQ driver software 1 2 to 1 3 register level programming 1 3 unpacking 1 4 Lab PC instrumentation amplifier analog input signal connections 3 5 illustration 3 5 Lab PC PC bit D 7 LabVIEW and LabWindows CVI software 1 2 LDACO bit analog output circuitry programming E 20 to E 21 description D 9 LDAC1 bit analog output circuitry programming E 20 to E 21 data acquisition timing 3 23 description D 9 M MA lt 2 0 gt bits D 6 manual See documentation Mode 0 operation E 25 to E 26 control words E 25 to E 26 programming examples E 26 Mode 1 input E 27 to E 28 control words E 27 Port C pin assignments E 28 Lab PC User Manual Index 10 Port C status word bit definitions E 28 programming example E 29 timing 3 18 Mode 1 output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming example E 31 timing 3 19 Mode 2 bidirectional timing 3 20 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 32 programming example E 33 single bit s
16. 22 Figure 3 11 Posttrigger Data Acquisition Timing Case 2 cceecceeescecssececeseeeeeeeeeesteeeeaees 3 22 Figure 3 12 Pretrigger Data Acquisition Timing 3 23 Figure 3 13 EXTUPDATE Signal Timing for Updating DAC Output 3 24 Figure 3 14 EXTUPDATE Signal Timing for Generating Interrupts 3 24 Figure 3 15 Event Counting Application with External Switch Gating 3 25 Figure 3 16 Frequency Measurement Application ss 3 26 Figure 3 17 General Purpose Timing Signals 000 0 cece ceesceceesceceseeeceseeeceeceeceeeecseeeenaeeeeaees 3 27 Figure 4 1 Lab PC Block Diagrams civsgresesensvcsssavesengarenscesesdeeedseaybuessevehedaannsentasdenadteweboes 4 1 Figure 4 2 PC I O Interface Circuitry Block Diagram 0 eee eeeeeeeeeeeeeeeeeeteeeenteeeeaees 4 3 Figure 4 3 Analog Input and Data Acquisition Circuitry Block Diagram eee 4 4 Figure 4 4 Analog Output Circuitry Block Diagram eeeeeeeceeseecnseceseeeeeeeeneeesaeenes 4 9 Figure 4 5 Digital I O Circuitry Block Diagram ss 4 10 Figure 4 6 Timing I O Circuitry Block Diagram R 4 12 Figure 4 7 Two Channel Interval Scanning Timing 0 cee eeeeeceeeceeseceeceeeeeceeeeeeneeeenaees 4 13 Figure 4 8 Single Channel Interval Timing s 4 14 Figure 4 9 Counter Block Diagram is suis
17. 3 15 Mode 1 input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C pin connections 3 15 to 3 16 specifications and ratings 3 14 timing specifications 3 16 to 3 17 digital I O specifications A 5 DIOINTEN bit description D 12 digital I O circuitry programming E 34 DMA channel selection 2 6 to 2 7 factory settings table 2 3 jumper settings disabling DMA transfers figure 2 7 factory settings figure 2 6 jumper settings figure 2 6 signal lines table 2 6 DMA control circuitry programming E 20 theory of operation 4 4 DMAEN bit description D 12 DMA request generation E 20 DMATC bit description D 7 DMA request generation E 20 DMATC Interrupt Clear Register description D 20 DMA request generation E 20 documentation conventions used in manual xii National Instruments documentation xiii organization of manual xi xii National Instruments Corporation Index 7 Index E ECKDRYV bit D 14 ECLKRCYV bit D 13 environment specifications A 6 EOIRCV bit description D 14 multiple A D conversions interval scanning E 17 to E 18 single channel interval acquisition mode E 19 equipment optional 1 4 ERRINTEN bit A D interrupt programming E 20 description D 11 event counting 3 25 application with external switch gating figure 3 25 EXTCONV signal data acquisition timing 3 21 to 3 22 description table 3 3 external timing for multiple A D conversions E 12 co
18. AO Data Register Counter Al Data Register Counter A2 Data Register Counter A Mode Register Timer Interrupt Clear Register 8253 Counter Timer Register Group B Counter BO Data Register Counter B1 Data Register Counter B2 Data Register Counter B Mode Register 8255A Digital I O Register Group Port A Register Port B Register Port C Register Digital Control Register Interval Counter Register Group Interval Counter Data Register Interval Counter Strobe Register Lab PC User Manual D 2 Write only Read only Write only Write only Write only Read only Write only Write only Write only Write only Write only Write only Write only Read and write Read and write Read and write Write only Write only Read and write Read and write Read and write Write only Read and write Read and write Read and write Write only Write only Write only National Instruments Corporation Appendix D Register Map and Descriptions Register Sizes The Lab PC registers are 8 bit registers To transfer 16 bit data two consecutive I O readings or writings are needed For example to read the 16 bit A D conversion result two consecutive 8 bit readings of FIFO are needed The first reading returns the low byte of the 16 bit data and the second returns the high byte of the data Register Description Table D 1 divides the Lab PC registers into six different register groups A bit description of each of the registers making up
19. B Register D 35 Port C Register D 36 D lt 11 8 gt bits D 22 D lt 15 8 gt bits D 16 D 17 D lt 15 12 gt bits D 22 DACO Low Byte DACO High Byte Registers analog output circuitry programming E 20 description D 22 DACO OUT signal analog output circuitry programming E 20 description table 3 3 DACI Low Byte DAC1 High Byte Registers analog output circuitry programming E 20 description D 22 DACI OUT signal analog output circuitry programming E 20 description table 3 3 data acquisition modes See controlled acquisition mode freerun acquisition mode data acquisition operation E 5 data acquisition timing circuitry 4 5 to 4 8 block diagram 4 4 data acquisition rates 4 7 to 4 8 analog input settling time versus gain table 4 7 bipolar analog input signal range versus gain table 4 8 maximum recommended rates table 4 8 unipolar analog input signal range versus gain table 4 8 multiple channel scanned data acquisition 4 6 to 4 7 single channel data acquisition 4 6 Lab PC User Manual Index 6 data acquisition timing connections EXTCONV signal timing figure 3 21 EXTUPDATE signal timing generating interrupts figure 3 24 updating DAC output figure 3 24 posttrigger timing figure 3 22 pretrigger timing figure 3 23 DATA signal description 3 17 Mode 1 input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 DAVAIL bit A D interrupt programming E 19 descripti
20. Convert Register initiates an A D conversion Writing to the A D Clear Register clears the data acquisition circuitry Writing to the DMATC Clear Register clears the interrupt request generated by a DMA terminal count pulse Bit descriptions for the registers making up the Analog Input Register Group are given on the following pages National Instruments Corporation D 15 Lab PC User Manual Register Map and Descriptions Appendix D A D FIFO Register The 12 bit A D conversion results are sign extended to 16 bit data in either two s complement or straight binary format and are stored into a 512 word deep A D FIFO buffer Two consecutive 8 bit readings of the A D FIFO Register return an A D conversion value stored in the A D FIFO The first reading returns the low byte of the 16 bit value and the second reading returns the high byte The value read is removed from the A D FIFO thereby freeing space for another A D conversion value to be stored The A D FIFO is emptied when all values it contains are read The Status Register should be read before the A D FIFO Register is read If the A D FIFO contains one or more A D conversion values the DAVAIL bit is set in the Status Register and the A D FIFO Register can be read to retrieve a value If the DAVAIL bit is cleared the A D FIFO is empty in which case reading the A D FIFO Register returns meaningless information The values returned by reading the A D FIFO Register are available in two di
21. Counter AO Regardless of the timebase chosen the minimum sample period of 16 us must be observed for data integrity Programming in Controlled Acquisition Mode The following programming steps are required for a data acquisition operation in controlled acquisition mode 1 Select analog input channel gain and timebase source for Counter AO The analog input channel and gain are selected by writing to Command Register 1 The SCANEN bit must be cleared for data acquisition operations on a single channel See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns If Counter BO is being used as a timebase for Counter AO then the TBSEL bit in Command Register 2 should be set at this time Command Register 1 needs to be written to only when the analog input channel gain setting or other function needs to be changed 2 Program Counter BO if necessary The following sequence should be used to program Counter BO if it is being used If Counter BO is not being used skip to step 3 All writes are 8 bit write operations All values given are hexadecimal a Write 36 to the Counter B Mode Register select Mode 3 b Write the least significant byte of the timebase count to the Counter B Data Register c Write the most significant byte of the timebase count to the Counter B Data Register For example programming a timebase of 10 Us requires a timebase count of 10ps _ 0 5 Us
22. D conversion Counter AO output must be programmed to a high state This ensures that Counter AO does not cause any A D conversions Write 34 hex to the Counter A Mode Register select Counter AO Mode 2 to force OUTO to a high state This is an 8 bit operation 4 Clear the A D circuitry Before the data acquisition operation is started the A D FIFO must be emptied in order to clear any old A D conversion results This emptying must be performed after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 8 bit write and read from the A D FIFO 8 bit read twice Ignore the obtained data 5 Program Counter Al Counter Al of the 8253 A Counter Timer is used as a sample counter The sample counter counts the number of A D conversions and disable conversions when the programmed count is reached The sample count must be less than or equal to 65 535 The minimum sample count is three To program the counters use the following programming sequence a Write 70 hex to the Counter A Mode Register select Counter Al Mode 0 This step sets the output of Counter Al OUTA1 low b Write the least significant byte of M 2 where M is the sample count to the Counter Al Data Register c Write the most significant byte of M 2 where M is the sample count to the Counter Al Data Register 6 Select posttrigger mode and enable EXTCONV
23. D lt 15 8 gt D 16 D 17 D lt 15 12 gt D 22 DAVAIL D 8 E 3 to E 4 E 19 DIOINTEN D 12 E 34 DMAEN D 12 E 20 DMATC D 7 E 20 ECKDRV D 14 ECLKRCV D 13 EOIRCV D 14 E 17 to E 18 E 19 ERRINTEN D 11 E 20 EXTGATAO D 7 GAIN lt 2 0 gt D 5 GATAO D 7 E 12 E 16 Lab PC User Manual Index HWTRIG 3 21 D 10 E 11 E 13 E 14 INTSCAN D 14 E 17 to E 19 Lab PC PC D 7 LDACO D 9 E 20 to E 21 LDACI 3 23 D 9 E 20 to E 21 MA lt 2 0 gt D 6 OVERFLOW D 7 E 20 See also A D FIFO overflow condition OVERRUN D 8 E 20 See also A D FIFO overrun condition PRETRIG 3 21 D 10 E 11 E 12 E 14 SCANEN See SCANEN bit SE D D 13 SWTRIG See SWTRIG bit TBSEL D 9 E 6 TCINTEN D 11 TWOSCMP D 6 E 4 board configuration base I O address selection 2 3 to 2 5 DMA channel selection 2 6 to 2 7 interrupt selection 2 7 to 2 8 parts locator diagram 2 2 PC bus interface 2 1 factory settings table 2 3 bus interface specifications A 6 C cabling considerations 3 28 calibration analog input 5 3 to 5 6 bipolar input procedure 5 4 to 5 5 board configuration 5 4 unipolar input procedure 5 5 to 5 6 voltage values of ADC input table 5 4 analog output 5 6 to 5 8 bipolar output procedure 5 6 to 5 7 board configuration 5 6 unipolar output procedure 5 8 equipment requirements 5 1 trimpots 5 2 location diagram 5 2 CCLKB1 signal table 3 3 channel scanning for multiple A D conversions E 17 ch
24. DACOH DAC1 Low Byte DAC1L and DAC1 High Byte DAC1H Registers Writing to DACOL and then to DACOH loads the analog output Channel 0 Writing to DACIL and then to DAC1H loads the analog output Channel 1 The voltage generated by the analog output channels is updated immediately after the corresponding DACXH register is written to if the corresponding LDACx bit is cleared in Command Register 2 If the LDACx bit is set the analog output is updated when an active low pulse occurs on the output of Counter A2 or on the EXTUPDATE line on the I O connector Address Base address 04 hex Load DACO low byte Base address 05 hex Load DACO high byte Base address 06 hex Load DAC1 low byte Base address 07 hex Load DACI high byte Type Write only all Word Size 8 bit all Bit Map DACxH 6 5 4 3 1 a ec E E E a Sign Extension Bits DACxL 7 6 5 4 3 2 1 0 EE RS RE CE RE ER EE ER TES Bit Name Description DACxH 7 4 D lt 15 12 gt Zero in straight binary mode sign extension in two s complement mode 3 0 D lt 11 8 gt These four bits are loaded into the specified DAC high byte DACxL 7 0 D lt 7 0 gt These eight bits are loaded into the specified DAC low byte The low byte should be loaded first followed by corresponding high byte loading Lab PC User Manual D 22 National Instruments Corporation Appendix D Register Map and Descriptions 8253 Counter Timer Register Groups A and B The nine regi
25. E 28 Port C status word bit definitions E 28 programming example E 29 Mode 1 output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming example E 31 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Lab PC User Manual Index 12 Port C status word bit definitions E 32 programming example E 33 single bit set reset control words E 33 single bit set reset feature E 34 DMA operation E 20 initializing Lab PC E 1 to E 2 interrupt programming for analog output circuitry E 22 to E 23 multiple A D conversions channel scanning E 17 controlled acquisition mode overview E 5 programming steps E 6 to E 8 external timing E 11 to E 17 controlled acquisition mode E 12 to E 16 freerun acquisition mode E 16 to E 17 using EXTCONV signal E 12 using EXTTRIG signal E 11 freerun acquisition mode overview E 5 programming steps E 8 to E 10 interval scanning E 17 to E 18 single input channel E 5 to E 10 controlled acquisition mode E 6 to E 9 freerun acquisition mode E 8 to E 10 single channel interval acquisition mode E 18 to E 19 register programming considerations E 1 software programming choices LabVIEW and LabWindows CVI software 1 2 NI DAQ driver software 1 2 to 1 3 register level programming 1 3 pulse and square wave generation 3 25 pulse width measurement 3 25 R RD signal description 3 17 Mode 1 inpu
26. Event Counting Application with External Switch Gating Pulse width measurement is performed by level gating The pulse to be measured is applied to the counter GATE input The counter is loaded with the known count and is programmed to count down while the signal at the GATE input is high The pulse width equals the counter difference loaded value minus read value multiplied by the CLK period Time lapse measurement is performed by programming a counter to be edge gated An edge is applied to the counter GATE input to start the counter The counter can be programmed to start National Instruments Corporation 3 25 Lab PC User Manual Signal Connections Chapter 3 counting after receiving a low to high edge The time lapse since receiving the edge equals the counter value difference loaded value minus read value multiplied by the CLK period To perform frequency measurement program a counter to be level gated and count the number of falling edges in a signal applied to a CLK input The gate signal applied to the counter GATE input is of known duration In this case you program the counter to count falling edges at the CLK input while the gate is applied The frequency of the input signal then equals the count value divided by the gate period Figure 3 16 shows the connections for a frequency measurement application You can also use a second counter to generate the gate signal in this application In this case program the second counter for
27. Figure 3 4 Differential Input Connections for Floating Sources The 100 KQ resistors shown in Figure 3 4 create a return path to ground for the bias currents of the instrumentation amplifier If a return path is not provided the instrumentation amplifier bias currents charge up stray capacitances resulting in uncontrollable drift and possible saturation in the amplifier Typically values from 10 KQ to 100 KQ are used A resistor from each input to ground as shown in Figure 3 4 provides bias current return paths for an AC coupled input signal If the input signal is DC coupled then only the resistor connecting the negative signal input to ground is needed This connection does not lower the input impedance of the analog input channel National Instruments Corporation 3 9 Lab PC User Manual Signal Connections Chapter 3 Single Ended Connection Considerations Single ended connections are those in which all Lab PC analog input signals are referenced to one common ground The input signals are tied to the positive input of the instrumentation amplifier and their common ground point is tied to the negative input of the instrumentation amplifier When the Lab PC is configured for single ended input NRSE or RSE eight analog input channels are available Single ended input connections can be used when the following criteria are met by all input signals 1 Input signals are high level greater than 1 V 2 Leads connecting the
28. Selection 0 Mode 0 1 Mode 1 Figure E 1 Control Word Format with Control Word Flag Set to 1 Control Word Flag 0 Bit Set Reset HRNEC Bit Set Reset 1 set 0 reset Bit Select 000 001 010 111 Figure E 2 Control Word Format with Control Word Flag Set to 0 This section describes the Digital Control Register which is used to program the 8255A ports in any one of the three modes discussed earlier in this section Specific control words for each mode are described later in this section along with programming examples for each mode Lab PC User Manual E 24 National Instruments Corporation Appendix E Register Level Programming Modes of Operation for the 8255A The three basic modes of operation for the 8255A are as follows e Mode 0 Basic I O e Mode 1 Strobed I O e Mode 2 Bidirectional bus The 8255A also has a single bit set reset feature for Port C The 8 bit control word also programs this function For additional information refer to Appendix C OKI 82C55A Data Sheet Mode 0 This mode is for simple I O operations for each of the ports No handshaking is required data is simply written to or read from a specified port Mode 0 has the following features e Two 8 bit ports A and B and two 4 bit ports upper and lower nibble of Port C e Any port can be input or output e Outputs are latched but inputs are not latched Control Words Mode 0 provides simple I O func
29. TMINE siie en te a i a ua 3 19 Mode 2 Bidirectional Thin se A RE ST es 3 20 Timme Connections se nds Ne dete RE Re N e 3 21 Data Acquisition Timing Connections 3 21 General Purpose Timing Signal Connections and General Purpose Counter Timing Signals cceesceeeeeceeeseeeeeteeeenaees 3 24 Cabine aan inner ne rade din donna S T 3 28 Chapter 4 Theory of rer athO eyes peed ast 4 1 Punch Gna Overview RE SA aa E Eaa RI ein ess A 4 1 PC I O Channel Interface Circuitry sise etienne 4 2 Analog Input and Data Acquisition Circuitry ss 4 4 Analog Input Circuitry oricvcdsecictascebasisstacacushaceens agence saceense da sodedoansoad a 4 5 Data Acquisition Timing Circuitry 0 ceececeecceceeececssccecssecececeeeseeeesaeeeesaeeeenes 4 5 Single Channel Data Acquisition 4 6 Multiple Channel Scanned Data Acquisition 4 6 Data ACQUISIION RATES Senegal Drm eee ne orne nn To as 4 7 Analos Output Circ wey Keane ent ede Bene lene nan en attire 4 9 Digital VO CCM sce sll AEA ae i os esa Sane echt lacoste 4 10 Timne VO Cr Cur ysis Sateen A RS dea ends eaten Ass 4 11 Lab PC User Manual vi National Instruments Corporation Contents Chapter 5 ES TN 021 01 ieee ee nee AN A une era sn 5 1 Calibration Equipment Requirements ss 5 1 Calibration Trimpots iii antenne A ERES EEA E TEE Eais 5 2 Analogs Input Calibration seseriai a E e a E E 5 3 Board Configuration seniesiems teek E Ne iE ESEE E EE EEEa 5 4 Bipolar Input Calibration
30. V 1 5 LSB to the analog input circuitry and adjust a potentiometer until the ADC returns readings that flicker between its most positive count and the most positive count minus 1 The voltages corresponding to V and 1 LSB are given in Table 5 1 National Instruments Corporation 5 3 Lab PC User Manual Calibration Chapter 5 The voltages corresponding to V_ which is the most negative voltage that the ADC can read Vs 1 which is the most positive voltage the ADC can read and 1 LSB which is the voltage corresponding to one count of the ADC depend on the input range selected The value of these voltages for each input range is given in Table 5 1 Table 5 1 Voltage Values of ADC Input 5 to 5 V 5 V 4 99756 V 2 44 mV 1 22 mV Oto 10 V OV 9 99756 V 2 44 mV 1 22 mV Board Configuration The calibration procedure differs if you select either bipolar or unipolar input configuration A procedure for each configuration is given next Bipolar Input Calibration Procedure If your board is configured for bipolar input which provides the range 5 to 5 V then complete the following procedure in the order given This procedure assumes that ADC readings are in the range 2 048 to 2 047 that is the TWOSADC bit in Command Register 1 is set high The following should be performed with the input configuration set to RSE 1 Input Offset Calibration To adjust the amplifier input offset a Connect ACHO pin 1 on the I O connector
31. a one shot mode This scheme needs an external inverter to make the output pulse of the second counter active high Signal Source T O Connector Lab PC Board Figure 3 16 Frequency Measurement Application The GATE CLK and OUT signals for Counters B1 and B2 are available at the I O connector In addition the GATE and CLK pins are pulled up to 5 V through a 4 7 kQ resistor Figure 3 17 shows the timing requirements for the GATE and CLK input signals and the timing specifications for the OUT output signals of the 8253 Lab PC User Manual 3 26 National Instruments Corporation Chapter 3 Signal Connections The following specifications and ratings apply to the 8253 I O signals Absolute maximum voltage input rating 0 5 to 7 0 V with respect to DGND 8253 digital input specifications referenced to DGND Vi input logic high voltage 2 2 V minimum Vy input logic low voltage 0 8 V maximum Input load current 10 uA maximum 8253 digital output specifications referenced to DGND Vo output logic high voltage 3 7 V minimum Vor output logic low voltage 0 45 V maximum Iop Output source current at Voy 1 mA maximum IoL output sink current at VoL 4 mA maximum clock period 380 nsec minimum clock high level 230 nsec minimum clock low level 150 nsec minimum gate setup time 100 nsec minimum gate hold time 50 nsec minimum gate high level 150 nsec minimum gate low level 100 nsec minimum output delay from clock w 300 nsec maxi
32. a pretrigger signal In pretrigger mode A D conversions are enabled via software before a rising edge is sensed on the EXTTRIG input However the sample counter Counter A1 is not gated on until a rising edge is sensed on the EXTTRIG input Additional transitions on this line have no effect until a new data acquisition sequence is set up Conversions remain enabled for the programmed count after the trigger therefore data can be acquired before and after the trigger Pretrigger mode works only in controlled acquisition mode that is Counter Al is required to disable A D conversions after the programmed count expires Thus the maximum number of samples acquired after the trigger is limited to 65 535 The number of samples acquired before the trigger is limited only by the size of the memory buffer available for data acquisition Figure 3 12 shows a pretrigger data acquisition timing sequence tw Vin EXTTRIG lt Vit ty 50 nsec minimum CONVERT one a ee Eee Figure 3 12 Pretrigger Data Acquisition Timing Because both pretrigger and posttrigger modes use EXTTRIG input only one mode can be used at a time If neither PRETRIG nor HWTRIG is set high this signal has no effect The final external control signal EXTUPDATE is used to externally control the updating of the output voltage of the 12 bit DACs or to generate an externally timed interrupt If the LDACO or LDAC1 bit in the Command Register 2 is set the
33. and EXTTRIG input Set the HWTRIG bit in Command Register 2 This setting enables EXTTRIG and EXTCONV that is the first rising edge on EXTTRIG starts the data acquisition sequence 7 Service the data acquisition operation Once the data acquisition operation is started by a rising edge on the EXTTRIG input A D conversions are initiated by falling edges on the EXTCONV input The operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To service the data acquisition perform the following sequence until the desired number of conversion results have been read a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 read the A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation These topics are discussed in the A D Interrupt Programming and Programming DMA Operation sections later in this appendix National Instruments Corporation E 13 Lab PC User Manual Register Level Programming Appendix E Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO i
34. and a powerful graphical programming language The LabVIEW Data Acquisition VI Library a series of VIs for using LabVIEW with National Instruments DAQ hardware is included with LabVIEW The LabVIEW Data Acquisition VI Libraries are functionally equivalent to the NI DAQ software LabWindows CVI features interactive graphics a state of the art user interface and uses the ANSI standard C programming language The LabWindows CVI Data Acquisition Library a series of functions for using LabWindows CVI with National Instruments DAQ hardware is included with the NI DAQ software kit The LabWindows CVI Data Acquisition libraries are functionally equivalent to the NI DAQ software Using LabVIEW or LabWindows CVI software will greatly reduce the development time for your data acquisition and control application NI DAQ Driver Software The NI DAQ driver software is included at no charge with all National Instruments DAQ hardware NI DAQ is not packaged with signal conditioning or accessory products NI DAQ has an extensive library of functions that you can call from your application programming environment These functions include routines for analog input A D conversion buffered data acquisition high speed A D conversion analog output D A conversion waveform generation timed D A conversion digital I O counter timer operations SCXI RTSI calibration messaging and acquiring data to extended memory NI DAQ has both high level DAQ I O fun
35. changing the current state of the remaining bits in the register However writing to these registers affects all register bits simultaneously You cannot read these registers to determine which bits have been set or cleared in the past therefore you should maintain a software copy of the write only registers This software copy can then be read to determine the status of the write only registers To change the state of a single bit without disturbing the remaining bits set or clear the bit in the software copy and then write the software copy to the register Initializing the Lab PC Board The Lab PC hardware must be initialized in order for the Lab PC circuitry to operate properly To initialize the Lab PC hardware complete these steps 1 Write 00 hex to the Command Register 1 2 Write 00 hex to the Command Register 2 3 Write 00 hex to the Command Register 3 4 Write 00 hex to the Command Register 4 5 Write 34 hex to Counter A Mode Register 6 Write OA hex to Counter AO Data Register 7 Write 00 hex to Counter AO Data Register National Instruments Corporation E 1 Lab PC User Manual Register Level Programming Appendix E 8 Write 00 hex to the DMATC Interrupt Clear Register 9 Write 00 hex to the Timer Interrupt Clear Register 10 Write 00 hex to the A D Clear Register 11 Read the data from the A D FIFO Register twice Ignore the data 12 Write 00 hex to the DACOL and then write 00 he
36. channel to 9 99756 V by writing 4 095 to the DAC c Adjust trimpot R1 until the output voltage read is 9 99756 V For analog output Channel 1 a Connect the voltmeter between DACI OUT pin 12 on the I O connector and AGND pin 11 b Set the analog output channel to 9 99756 V by writing 4 095 to the DAC c Adjust trimpot R3 until the output voltage read is 9 99756 V Lab PC User Manual 5 8 National Instruments Corporation Appendix A Specifications This appendix lists the specifications of the Lab PC These specifications are typical at 25 C unless otherwise stated The operating temperature range is 0 to 70 C Analog Input Input Characteristics Number of channels Type of ADC Resolution Maximum sampling rate Input signal ranges Input coupling Overvoltage protection Inputs protected FIFO buffer size Data transfers DMA modes Transfer Characteristics Relative accuracy sin disnnsnininne DNE ses nt Le ins lat No missing codes Offset error Pregain error after calibration Postgain error after calibration Gain error relative to calibration reference After calibration Before calibration Gain 1 with gain error adjusted to 0 at gain 1 oe National Instruments Corporation 8 single ended 4 differential Successive approximation 12 bits 1 in 4 096 83 ksamples s Board Gain Board Range Software Jumper Selectable Selectable Oto 10 V Oto5 V Oto2 V Otol V Oto 0 5 V 0 to 0 2 V
37. channels driven by high impedance signal sources Table 4 3 Bipolar Analog Input Signal Range Versus Gain Gain Setting Input Signal Range 1 5 V to 4 99756 V 2 5 V to 2 49878 V 1 0 V to 0 99951 V 500 mV to 499 756 mV 250 mV to 249 877 mV 100 mV to 99 951 mV 50 mV to 49 975 mV 0 V to 9 99756 V 0 V to 4 99878 V 0 V to 1 99951 V 0 mV to 999 756 mV 0 mV to 499 877 mV 0 mV to 199 951 mV 0 mV to 99 975 mV Lab PC User Manual 4 8 National Instruments Corporation Chapter 4 Theory of Operation Analog Output Circuitry The Lab PC provides two channels of 12 bit D A output Each analog output channel can provide unipolar or bipolar output Figure 4 4 shows a block diagram of the analog output circuitry 2SDACO DACOWR DACO OUT o 5 V Internal 8 Reference DACIWR ied iz DAC1 OUT PC I O Channel T O Connector i Counter A2 EXTUPDATE Command Register 2 2SDACI 2SDACO LDACI LDACO Figure 4 4 Analog Output Circuitry Block Diagram Each analog output channel contains a 12 bit DAC The DAC in each analog output channel generates a voltage proportional to the input Vef multiplied by the digital code loaded into the DAC Each DAC can be loaded with a 12 bit digital code by writing to the DACO L and H and DAC L and H Registers on the Lab PC board The voltage output from the two DACs is available at the Lab PC I O connector DACO OUT and DAC1 OUT pins The DAC voltages can be updated in any
38. channels on the PC AT I O channel Each DMA channel consists of two signal lines as shown in Table 2 3 Table 2 3 DMA Channels for the Lab PC DMA DMA Channel Acknowledge ee DRQI DRQ2 DRQ3 Note In most personal computers DMA Channel 2 is reserved for the disk drives Therefore you should avoid using this channel Two jumpers must be installed to select a DMA channel The DMA Acknowledge and DMA Request lines selected must have the same number suffix for proper operation Figure 2 3 displays the jumper positions for selecting DMA Channel 3 Figure 2 3 DMA Jumper Settings for DMA Channel 3 Factory Setting If you do not want to use DMA for Lab PC transfers then place the configuration jumpers on W6 in the position shown in Figure 2 4 Lab PC User Manual 2 6 National Instruments Corporation Chapter 2 Configuration and Installation Figure 2 4 DMA Jumper Settings for Disabling DMA Transfers Interrupt Selection The Lab PC board can connect to any one of the six interrupt lines of the PC I O channel The interrupt line is selected by a jumper on one of the double rows of pins located above the I O slot edge connector on the Lab PC refer to Figure 2 1 To use the interrupt capability of the Lab PC you must select an interrupt line and place the jumper in the appropriate position to enable that particular interrupt line The Lab PC can share interrupt lines with other devices by using a tristate driv
39. corresponding DAC voltage is updated by a low level on the EXTUPDATE signal If the CNTINTEN bit in the Command Register 3 is set an interrupt is generated whenever a rising edge is detected on the EXTUPDATE bit Therefore externally timed interrupt driven waveform generation is possible on the Lab PC Figure 3 13 illustrates a waveform generation timing sequence using the EXTUPDATE signal Notice that the DACs are updated by a low level on the EXTUPDATE line Any writes to the DAC Data Registers while EXTUPDATE is low therefore result in immediate update of the DAC output voltages National Instruments Corporation 3 23 Lab PC User Manual Signal Connections Chapter 3 EXTUPDATE DAC OUTPUT J J UPDATE CNTINT Ag ey DACWRT es ES text Minimum 50 nsec Figure 3 13 EXTUPDATE Signal Timing for Updating DAC Output Since a rising edge on the EXTUPDATE signal always sets the CNTINT bit in the Status Register the EXTUPDATE signal can also be used for periodic interrupt generation timed by an external source The CNTINT bit is cleared by writing to the Timer Interrupt Clear Register Figure 3 14 illustrates a timing sequence where EXTUPDATE is being used to generate an interrupt EXTUPDATE CNTINT TMRINTCLR _ Figure 3 14 EXTUPDATE Signal Timing for Generating Interrupts The following rating applies to the EXTCONV EXTTRIG and EXTUPDATE signals Absolute maximum vol
40. disabled under software control Programming in Controlled Acquisition Mode Posttrigger Mode The following programming steps are required for a data acquisition operation in controlled acquisition mode using EXTCONV In the following programming sequence EXTTRIG is used as a posttrigger signal that is data acquisition is not started until a rising edge is detected on the EXTTRIG input 1 Disable EXTCONV and EXTTRIG input The EXTCONV bit can be disabled by setting the GATAO bit low The GATAO bit is low whenever OUTA1 is high regardless of the settings for the SWTRIG or HWTRIG bits in Command Register 1 or the EXTTRIG signal Writing 78 hex to the Counter A Mode Register sets OUTAI high This write disables EXTCONV and EXTTRIG input that is any transitions on these two inputs are ignored 2 Select analog input channel and gain and select posttrigger mode The analog input channel and gain are selected by writing to Command Register 1 The SCANEN bit must be cleared for data acquisition operations on a single channel See the bit description for Command Register 1 earlier in this chapter for gain and analog input channel bit descriptions To use posttrigger mode the PRETRIG bit and SWTRIG bit in Command Register 2 must be cleared Lab PC User Manual E 12 National Instruments Corporation Appendix E Register Level Programming 3 Program Counter AO Since a high to low transition on the Counter AO output initiates an A
41. if it is being used If Counter BO is not being used skip to step 3 All writes are 8 bit write operations All values given are hexadecimal a Write 36 to the Counter B Mode Register select Mode 3 b Write the least significant byte of the timebase count to the Counter B Data Register c Write the most significant byte of the timebase count to the Counter B Data Register For example programming a timebase of 10 Us requires a timebase count of 10us _ 0 5 Us 20 Program the sample interval counter Counter AO Counter AO of the 8253 A Counter Timer is used as the sample interval counter A high to low transition on OUTO Counter AO output initiates a conversion Counter AO can be programmed to generate a pulse once every N us N is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 535 The sample interval is equal to the period of the timebase clock used by Counter AO multiplied by N A 1 MHz clock is internally connected to CLKO the clock used by Counter AO Use the following programming sequence to program Counter AO the sample interval counter All writes are 8 bit write operations All values given are hexadecimal a Write 34 to the Counter A Mode Register select Counter AO Mode 2 b Write the least significant byte of the sample interval to the Counter AO Data Register c Write the most significant byte of the sample interval to the Counter A
42. in Appendix D Register Map and Descriptions You must also set the following jumper W4 B C Jumper is in standby position and negative input of instrumentation amplifier is tied to multiplexed output This configuration is shown in Figure 2 11 NRSE DIFF Figure 2 11 NRSE Input Configuration Considerations in using the NRSE configuration are discussed in Chapter 3 Signal Connections Note that in this mode the return path of the signal is through the negative terminal of the amplifier available at the connector through the pin AISENSE AIGND Analog Input Polarity Configuration Two ranges are available for the analog inputs bipolar 5 V and unipolar 0 to 10 V Jumper W3 controls the input range for all eight analog input channels Bipolar Input Selection You can select the bipolar 5 V input configuration by setting the following jumper Analog Input W3 A B This configuration 1s shown in Figure 2 12 National Instruments Corporation 2 13 Lab PC User Manual Configuration and Installation Chapter 2 W3 B A B U C Figure 2 12 Bipolar Input Jumper Configuration Factory Setting Unipolar Input Selection You can select the unipolar 0 to 10 V input configuration by setting the following jumper Analog Input W3 B C This configuration 1s shown in Figure 2 13 W3 B A B U C Figure 2 13 Unipolar Input Jumper Configuration Note Ifyou are using a software package such as NI DAQ or LabWindows CVI you m
43. is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is low The minimum recommended sampling interval on the Lab PC is 16 Us Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A D Clear Register Programming in Freerun Acquisition Mode Posttrigger Mode A posttrigger data acquisition in freerun acquisition mode using EXTCONV requires a programming sequence similar to controlled acquisition mode except that steps 5b and 5c are not performed The sample count is kept in software and conversions remain enabled until GATAO is set low GATAO can be set low by writing 34 hex to the Counter A Mode Register after the required number of samples is obtained This disables EXTCONV that is further transitions on EXTCONV are ignored Lab PC User Manual E 16 National Instruments Corporation Appendix E Register Level Programming Pretrigger Mode Pretriggering mode requires that the A D conversions be shut off at a programmed time by the hardware after the trigger on EXTTRIG Therefore pretriggered data acquisition is not possible in freerun acquisition mode Programming Multiple A D Conversions with Channel Scanning The data acquisition programming sequences given earlier in this chapter are for programming the Lab PC
44. lower for higher gains For multiple channel data acquisition observing the data acquisition rates given in Table 4 2 ensures 12 bit accuracy Table 4 1 Analog Input Settling Time Versus Gain Gain Setting Settling Time Recommended 1 12 us 2 5 10 20 50 16 us typical 18 us maximum 100 50 us National Instruments Corporation 4 7 Lab PC User Manual Theory of Operation Chapter 4 Table 4 2 Lab PC Maximum Recommended Data Acquisition Rates Single Channel 1 83 3 ksamples s 2 5 10 20 50 100 71 4 ksamples s Multiple Channel 1 83 3 ksamples s 2 5 10 20 50 62 5 ksamples s typical 55 5 ksamples s worst case 100 20 0 ksamples s The single channel acquisition rate decreases at higher gains because an offset error dependent on the sampling rate occurs at rates faster than 71 4 ksamples s This offset error is of the order of 1 LSB If you can tolerate the offset error the maximum sampling rate of 83 3 ksamples s applies at all gains The recommended data acquisition rates given in Table 4 2 assume that voltage levels on all the channels included in the scan sequence are within range for the given gain and are driven by low impedance sources The signal ranges for the possible gains are shown in Table 4 3 and Table 4 4 Signal levels outside the ranges shown in Table 4 3 on the channels included in the scan sequence adversely affect the input settling time Similarly greater settling time may be required for
45. of the instrumentation amplifier through input multiplexers on the Lab PC The instrumentation amplifier converts two input signals to a signal that is the difference between the two input signals multiplied by the gain setting of the amplifier The amplifier output voltage is referenced to the Lab PC ground The Lab PC ADC measures this output voltage when it performs A D conversions All signals must be referenced to ground either at the source device or at the Lab PC If you have a floating source you must use a ground referenced input connection at the Lab PC If you have a grounded source you must use a non referenced input connection at the Lab PC Types of Signal Sources When configuring the input mode of the Lab PC and making signal connections you should first determine whether the signal source is floating or ground referenced These two types of signals are described as follows Floating Signal Sources A floating signal source is one that is not connected in any way to the building ground system but rather has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolator outputs and isolation amplifiers The ground reference of a floating signal must be tied to the Lab PC analog input ground in order to establish a local or onboard reference for the signal Otherwise National Instruments Corporation 3 5 Lab PC User Ma
46. rising edge that occurs on OUTB1 after SCANEN is set Subsequent channel scanning cycles will then commence at the interval determined by the signal on OUTBI Programming Multiple A D Conversions in Single Channel Interval Acquisition Mode The Lab PC can perform interval sampling on a single input channel You enable single channel interval acquisition by setting the INTSCAN bit in Command Register 4 and clearing the SCANEN bit in Command Register 1 Counter B1 determines the interval just as in the interval scan mode You must program the number of samples to be taken between each interval in the Interval Counter The interval counter is armed when you write a count of N in the Interval Counter Data Register and strobe the count into the counter You must then program Counter B1 for the interval which should be greater than N sample interval A software trigger starts the sampling sequence The Lab PC takes N samples on the specified channel after which acquisition halts until the next interval pulse is generated on OUTB1 The Lab PC takes Lab PC User Manual E 18 National Instruments Corporation Appendix E Register Level Programming another N samples and the cycle repeats The operation stops when the sample counter Counter A1 decrements to 0 Use the following sequence to configure the Lab PC for single channel interval acquisition mode 1 Write the count to the Interval Counter Data Register and strobe it in the counter
47. semiconductor D A digital to analog DAC D A converter dB decibels DC direct current DIFF differential DIP dual inline package DMA direct memory access EISA Extended Industry Standard Architecture F farads FIFO first in first out ft feet hex hexadecimal Hz hertz VO input output in inches ksamples 1 000 samples LED light emitting diode LSB least significant bit M megabytes of memory m meters MSB most significant bit National Instruments Corporation Glossary 1 Lab PC User Manual Glossary NRSE non referenced single ended PPI programmable peripheral interface ppm parts per million PS 2 IBM Personal System 2 REXT external resistance RSE referenced single ended RTSI Real Time System Integration S seconds SCXI Signal Conditioning eXtensions for Instrumentation bus SDK System Development Kit STC system timing controller TTL transistor to transistor logic V volts VDC volts direct current VEXT external volts Vin volts input high VIL volts input low Vin volts in Vox volts output high VoL volts output low Vout output voltage Vief reference voltage Lab PC User Manual Glossary 2 National Instruments Corporation Index Numbers 2SDACO0 bit D 9 2SDACI bit D 9 5 V signal table 3 3 8253 Counter Timer Register Groups A and B D 23 to D 32 Counter A Mode Register description D 27 interrupt programming for analog output circuitry E 22 to E 23 Counter AO Data Register control
48. system noise A 3 T TBSEL bit controlled acquisition mode E 6 description D 9 TCINTEN bit D 11 technical support F 1 theory of operation analog input circuitry 4 5 block diagram 4 4 analog output circuitry 4 9 to 4 10 block diagram 4 9 block diagram 4 1 data acquisition timing circuitry 4 5 to 4 8 block diagram 4 4 data acquisition rates 4 7 to 4 8 multiple channel scanned data acquisition 4 6 to 4 7 single channel data acquisition 4 6 digital I O circuitry 4 10 to 4 11 block diagram 4 10 functional overview 4 1 to 4 2 PC I O channel interface circuitry 4 2 to 4 4 block diagram 4 3 timing I O circuitry 4 11 to 4 14 block diagram 4 12 counter block diagram 4 14 single channel interval timing figure 4 14 two channel interval scanning timing figure 4 13 time lapse measurement 3 25 to 3 26 Timer Interrupt Clear Register D 28 timing connections 3 21 to 3 28 data acquisition timing connections 3 21 to 3 24 EXTCONV signal timing figure 3 21 EXTUPDATE signal timing generating interrupts figure 3 24 updating DAC output figure 3 24 posttrigger timing figure 3 22 pretrigger timing figure 3 23 National Instruments Corporation general purpose timing connections 3 24 to 3 28 event counting application with external switch gating figure 3 25 frequency measurement application figure 3 26 pretrigger timing figure 3 23 specifications and ratings 3 27 timing requirements
49. 0 13F 140 15F 160 17F 180 19F 1A0 IBF 1C0 1DF 1E0 1FF 200 21F 220 23F 240 25F 260 27F 280 29F 2A0 2BF 2C0 2DF 2E0 2FF 300 31F 320 33F 340 35F 360 37F 380 39F 3A0 3BF 3C0 3DF 3E0 3FF se hr ee me ee De OO SO OS OS OO Om OF Or Or OF Or OF Or OF Or Or Or Or Or OF ae es SO OO Oo LL re Os Ss SS O0 As OO OS Ol HS eS SS OS SS SO Oo O0 m0 Oe O0 O0 EL oomen oomen SS OS SS nme O 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Note Base I O address values hex 000 through OFF are reserved for system use Base I O address values hex 100 through 3FF are available on the I O channel National Instruments Corporation 2 5 Lab PC User Manual Configuration and Installation Chapter 2 DMA Channel Selection The Lab PC uses the DMA channel selected by jumpers on W6 see Figure 2 1 The Lab PC is set at the factory to use DMA Channel 3 This is the default DMA channel used by the Lab PC software handler Verify that other equipment already installed in your computer does not use this DMA channel If any device uses DMA Channel 3 change the DMA channel used by either the Lab PC or the other device The Lab PC hardware can use DMA Channels 1 2 and 3 Notice that these are the three 8 bit channels on the PC I O channel The Lab PC does not use and cannot be configured to use the 16 bit DMA
50. 0 Port C signal assignments table 3 16 IBFA status word Port C Mode 1 input E 28 Mode 2 operation E 32 IBFB status word Port C E 28 initializing Lab PC E 1 to E 2 input configurations 3 7 to 3 27 National Instruments Corporation differential connection considerations 3 6 to 3 9 floating signal sources 3 8 to 3 9 ground referenced signal sources 3 7 to 3 8 recommended configurations for ground referenced and floating signal sources table 3 6 single ended connection considerations 3 10 to 3 12 floating signal sources RSE configuration 3 10 to 3 11 grounded signal sources NRSE configuration 3 11 to 3 12 input modes 2 10 to 2 11 DIFF input four channels 2 11 to 2 12 NRSE input eight channels 2 13 RSE input eight channels 2 12 input multiplexers 4 5 installation See also configuration hardware 2 15 unpacking the Lab PC 1 4 instrumentation amplifier 3 5 INTE status word Port C E 32 INTE2 status word Port C E 32 INTEA status word Port C Mode 1 input E 28 Mode 1 output E 30 INTEB status word Port C Mode 1 input E 28 Mode 1 output E 30 integral nonlinearity A 3 interrupt programming A D interrupt programming E 19 to E 20 analog output circuitry E 22 to E 23 digital I O circuitry E 34 interrupt selection 2 7 to 2 8 factory settings table 2 3 jumper settings disabling interrupts figure 2 8 factory setting of IRQS figure 2 7 interrupts control circuitry 4 3 gen
51. 20 Lab PC User Manual E 6 National Instruments Corporation Appendix E Register Level Programming 3 Program Counters AO and Al This step involves programming Counter AO the sample interval counter in rate generator mode Mode 2 and programming Counter A1 to interrupt on terminal count mode Mode 0 Counter AO of the 8253 A Counter Timer is used as the sample interval counter A high to low transition on the Counter AO output initiates a conversion Counter AO can be programmed to generate a pulse once every N us N is referred to as the sample interval that is the time between successive A D conversions N can be between 2 and 65 535 The sample interval is equal to the period of the timebase clock used by Counter AO multiplied by N Two timebases are available a 1 MHz clock and the output of Counter BO Counter A1 of the 8253 A Counter Timer is used as a sample counter The sample counter tallies the number of A D conversions initiated by Counter AO and stops Counter AO when the desired sample count is reached The sample count must be less than or equal to 65 535 The minimum sample count is 3 Use the following programming sequence to program the sample interval counter All writes are 8 bit write operations All values given are hexadecimal a Write 34 to the Counter A Mode Register select Counter AO Mode 2 b Write the least significant byte of the sample interval to the Counter AO Data Register c Write the most s
52. 4 096 The digital code in the preceding formula is a decimal value ranging from 0 to 4 095 Notice that straight binary coding is selected by clearing the 2SDAC bit in Command Register 2 Table E 3 Analog Output Voltage Versus Digital Code Unipolar Mode Straight Binary Coding Digital Code Voltage Output Decimal 0 1 OV 2 4414 mV 2 048 5 0 V 4 095 9 9976 V National Instruments Corporation E 21 Lab PC User Manual Register Level Programming Appendix E The following formula calculates the voltage output versus digital code for a bipolar analog output configuration and two s complement coding digital code Vout 5 0 Du 2 048 The digital code in the above formula is a decimal value ranging from 2 048 to 2 047 Notice that two s complement mode coding is selected by setting the 2SDAC bit high in Command Register 2 Table E 4 Analog Output Voltage Versus Digital Code Bipolar Mode Two s Complement Coding Digital Code Voltage Output Decimal Vrer 10 V 5 0 V 2 5 V 0 0 V 2 5 V 4 9976 V Interrupt Programming for the Analog Output Circuitry Interrupts can be used for writing successive values in a sequence to the DAC Data Registers during a waveform generation operation The CNTINTEN bit in Command Register 3 enables and disables Counter A2 and EXTUPDATE driven interrupts See Chapter 3 Signal Connections for timing requirements on the EXTUPDATE signal The following programmin
53. 4 096 different steps This resolution also provides a 12 bit digital word that represents the value of the input voltage level with respect to the converter input range The ADC itself has a single input range of 0 to 5 V Additional circuitry allows inputs of 5 V or 0 to 10 V When an A D conversion is complete the ADC clocks the result into the A D FIFO The A D FIFO is 16 bits wide and 512 words deep This FIFO serves as a buffer to the ADC and provides two benefits First any time an A D conversion is complete the value is saved in the A D FIFO for later reading and the ADC is free to start a new conversion Secondly the A D FIFO can collect up to 512 A D conversion values before any information is lost thus allowing software some extra time 512 times the sample interval to catch up with the hardware If more than 512 values are stored in the A D FIFO without the A D FIFO being read from an error condition called A D FIFO overflow occurs and A D conversion information is lost The A D FIFO generates a signal that indicates when it contains A D conversion data The state of this signal can be read from the Lab PC Status Register The output from the ADC can be interpreted as either straight binary or two s complement depending on which input mode you select unipolar or bipolar In unipolar mode the data from the ADC is interpreted as a 12 bit straight binary number with a range of 0 to 4 095 In bipolar mode the data from the ADC
54. 5 mA Output logic high voltage 3 7 V at output current 2 5 mA Darlington drive current 2 5 mA 4 0 mA REXT 700 Q Vext 1 7 V Figure 3 8 illustrates signal connections for three typical digital I O applications Lab PC User Manual 3 14 National Instruments Corporation Chapter 3 Signal Connections Port A PA lt 7 0 gt Port B PB lt 7 0 gt Port C Swiiteli PC lt 7 0 gt I O Connector Lab PC Board Figure 3 8 Digital I O Connections In Figure 3 8 Port A is configured for digital output and Ports B and C are configured for digital input Digital input applications include receiving TTL signals and sensing external device states such as the switch in Figure 3 8 Digital output applications include sending TTL signals and driving external devices such as the LED shown in Figure 3 8 Port C Pin Connections The signals assigned to Port C depend on the mode in which the 8255A is programmed In Mode 0 Port C is considered as two 4 bit I O ports In Modes 1 and 2 Port C is used for status and handshaking signals with two or three I O bits mixed in The following table summarizes the signal assignments of Port C for each programmable mode See Appendix E Register Level Programming for programming information National Instruments Corporation 3 15 Lab PC User Manual Signal Connections Programmable Mode Mode 0 Chapter 3 Table 3 2 Port C Signal Assignments Group A Group B
55. 8 programming example E 29 Mode 1 output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming example E 31 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 32 programming example E 33 single bit set reset control words E 33 single bit set reset feature E 34 register map table D 2 A ACH lt 0 7 gt signal description table 3 3 input ranges and maximum ratings 3 4 ACK signal description 3 16 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C signal assignments table 3 16 Lab PC User Manual Index A D Clear Register clearing A D FIFO E 7 description D 18 A D Configuration Register E 9 A D conversion See also multiple A D conversions programming initiating E 3 reading E 3 voltage versus A D conversion values table bipolar input mode E 4 unipolar input mode E 4 A D converter ADC 4 5 A D FIFO overflow condition analog input circuitry programming E 4 controlled acquisition programming E 8 posttrigger mode E 14 pretrigger mode E 16 freerun acquisition programming E 10 A D FIFO overrun condition clearing the analog input circuitry E 5 controlled acquisition programming E 8 posttrigger mode E 14 pretrigger mode E 16 freerun acquisition programming E 10 A D FIFO Register clearing analog input circuitry programming E 5 cont
56. ADC Inputt ccscccscccsiccssssscseanccegesecescteaveraceednbencenteasantesevsnceennns 5 4 Lab PC R sister Maps icssiccisussadscsaddaasssuetaccsdnvscecssdeeaaavangdacts snadaassdesdancasdsunatevess D 2 Unipolar Input Mode A D Conversion Values Straight Binary Coding E 4 Bipolar Input Mode A D Conversion Values Two s Complement Coding E 4 Analog Output Voltage Versus Digital Code Unipolar Mode Straight Binary Coding ss E 21 Analog Output Voltage Versus Digital Code Bipolar Mode Two s Complement Coding cceeecceeeseceeeteeeesteeeenteeeeaees E 22 Mode 0 I O Contig utapionsssiccssiscscnccesqsctaispseosassymuascinsesonsgnzecndieeecuieeiaeeians E 26 Port C Set Reset Control Words nent Ra nie E 33 National Instruments Corporation ix Lab PC User Manual About This Manual This manual describes the electrical and mechanical aspects of the Lab PC and contains information concerning its operation and programming The Lab PC is a low cost multifunction analog digital and timing I O board for PC compatible computers Organization of the Lab PC User Manual The Lab PC User Manual is organized as follows Chapter 1 Introduction describes the Lab PC lists what you need to get started describes the optional software and optional equipment and explains how to unpack the Lab PC Chapter 2 Configuration and Installation describes the Lab PC jumper configuration and installation of the Lab PC boa
57. Appendix B Lab PC User Manual B 8 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 9 Lab PC User Manual OKI 82C53 Data Sheet Appendix B Lab PC User Manual B 10 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 11 Lab PC User Manual OKI 82C53 Data Sheet Appendix B Lab PC User Manual B 12 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 13 Lab PC User Manual Appendix C OKI 82C55A Data Sheet This appendix contains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Microprocessor Data Book 1990 1991 National Instruments Corporation C 1 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 2 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 3 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 4 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 5 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 6 National Instrumen
58. B2 Il l 7 A10104 LE MANU ne tn ca600000000 bs NATIONAL S8 410 oat orb INSTRUMENTS CORP oocogogoo J i D Batas 0000000 00000000 oui 5000000000 EU zg ma pctaoios OF ane ki jadana amp cltoaneno Se cs40 0 ues foaona fhosgoaad fooongod gt oonga g LUS drini eT S73 U lon Lis DS u26 50 LS OX 0000000 Pi siee 0000000 32 x 0000000000 a 00000000000000000 g 10000000 C71 0 C670 0 0000000 Sue a Fi pL S04 Sh 39 R Q ASSY182095C 01 dinoana 0000000 u38 BAER 00000000 0000000000 u3 JU Oo O ol 4 Assembly Number Spare Fuse U1 wi Lab PC User Manual ae Q lo A is ol 7 rus PA Q 50000000 F0 6 8 H HCT273 Re ge a UIS ooaag isortW G L00 T47 Se 3 20000 07 A pge Du oe e5 000 00000000 10K 00000008 0000000000 _ 000000 oo 0000000000 t all HCT273 0000000000 g ee ae i 5 Lse45 FS gag000c00 8 9 Ji 10 Fuse Figure 2 1 Parts Locator Dia 2 2 Serial Number 11 W6 12 W5 13 Product Name gram National Instruments Corporation Chapter 2 Configuration and Installation Table 2 1
59. Corporation D 35 Lab PC User Manual Register Map and Descriptions Appendix D Port C Register Port C is special in the sense that it can be used as an 8 bit I O port like Port A and Port B if neither Port A nor Port B is used in handshaking latched mode If either Port A or Port B is configured for latched I O some of the bits in Port C are used for handshaking signals See Programming the Digital I O Circuitry in Appendix E Register Level Programming for a description of the individual bits in the Port C Register Address Base address 12 hex Type Read and write Word Size amp bit Bit Map 7 6 5 4 3 2 1 0 CR PR OR RE So OR D CR RE Bit Name Description 7 0 D lt 7 0 gt 8 bit Port C data Lab PC User Manual D 36 National Instruments Corporation Appendix D Register Map and Descriptions Digital Control Register The Digital Control Register can be used to configure Port A Port B and Port C as inputs or outputs as well as selecting simple mode basic I O or handshaking mode strobed I O for transfers See Programming the Digital I O Circuitry in Appendix E Register Level Programming for a description of the individual bits in the Digital Control Register Address Base address 13 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Bit Name Description 7 0 CW lt 7 0 gt 8 bit control word National Instruments Corporation D 37 Lab PC User Manual Register Map and Description
60. Counter B1 output or pulled high selectable 44 GATB1 Counter B1 gate Input 45 CCLKB1 Counter B1 clock selectable Input 46 OUTB2 Counter B2 output 47 GATB2 Counter B2 gate Input 48 CLKB2 Counter B2 clock Input 49 5V 5 V out 1 A maximum Output 50 DGND Digital ground Output Indicates that the signal is active low National Instruments Corporation 3 3 Lab PC User Manual Signal Connections Chapter 3 The connector pins can be grouped into analog input signal pins analog output signal pins digital I O signal pins and timing I O signal pins Signal connection guidelines for each of these groups are included later in this chapter Analog Input Signal Connections Pins 1 through 8 are analog input signal pins for the 12 bit ADC Pin 9 AISENSE AIGND is an analog common signal This pin can be used for a general analog power ground tie to the Lab PC in RSE mode or as a return path in DIFF or NRSE mode Pins 1 through 8 are tied to the eight single ended analog input channels of the input multiplexer through 4 7 kQ series resistances Pins 2 4 6 and 8 are also tied to an input multiplexer for DIFF mode Pin 40 is EXTCONV and can be used to trigger conversions A conversion occurs when this signal makes a high to low transition The following input ranges and maximum ratings apply to inputs ACH lt 0 7 gt Input signal range Bipolar input 5 gain V Unipolar input O to 10 gain V Maximum inp
61. D TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation Trademarks LabVIEW NI DAQ RTSI and SCXI are trademarks of National Instruments Corporation Product and company names
62. Instruments Corporation D 33 Lab PC User Manual Register Map and Descriptions Appendix D Port A Register Reading the Port A Register returns the logic state of the eight digital I O lines constituting Port A that is PA lt 0 7 gt If Port A is configured for output the Port A Register can be written to in order to control the eight digital I O lines constituting Port A See Programming the Digital I O Circuitry in Appendix E Register Level Programming for information on how to configure Port A for input or output Address Base address 10 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CR PR OR RE So OR D CR RE Bit Name Description 7 0 D lt 7 0 gt 8 bit Port A data Lab PC User Manual D 34 National Instruments Corporation Appendix D Register Map and Descriptions Port B Register Reading the Port B Register returns the logic state of the eight digital I O lines constituting Port B that is PB lt 0 7 gt If Port B is configured for output the Port B Register can be written to in order to control the eight digital I O lines constituting Port B See Programming the Digital I O Circuitry in Appendix E Register Level Programming for information on how to configure Port B for input or output Address Base address 11 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 CR PR OR RE So OR D CR RE Bit Name Description 7 0 D lt 7 0 gt 8 bit Port B data National Instruments
63. KB1 1 MHz Source Scan Interval General Purpose Counter CCLKB1 OUTBO GATEBO Timebase Extension General Purpose Counter CLKBO CLKAO 8253 Counter Timer GATEAO Group B Sample 2 MHz Interval Source Counter COUTBI i EXTCONV Counter A D Conversion Logic GATEAI T O Connector 3 S S g Q Q EXTTRIG GATEA2 DAC Timing OUTA2 D A Conversion Timing 8253 Counter Timer Group A EXTUPDATE Figure 4 6 Timing I O Circuitry Block Diagram Lab PC User Manual 4 12 National Instruments Corporation Chapter 4 Theory of Operation Each 8253 contains three independent 16 bit counter timers and one 8 bit Mode Register As shown in Figure 4 6 Counter Group A is reserved for data acquisition timing and Counter Group B is free for general use The output of Counter BO can be used in place of the 1 MHz clock source on Counter AO to allow clock periods greater than 65 536 us All six counter timers can be programmed to operate in several useful timing modes The programming and operation of the 8253 is presented in detail both in Appendix E Register Level Programming and Appendix B OKI 82C53 Data Sheet The 8253 for Counter Group A uses either a 1 MHz clock generated from the onboard 10 MHz oscillator or the output from Counter BO which has a 2 MHz clock source for its timebase Optionally Counter B1 can be used to provide interval scanning timing In the interval scanning mode the CLK pin o
64. Lab PC User Manual Low Cost Multifunction 1 0 Board for ISA June 1996 Edition Part Number 320502B 01 Copyright 1992 1996 National Instruments Corporation All Rights Reserved National Instruments Corporate Headquarters 6504 Bridge Point Parkway Austin TX 78730 5039 512 794 0100 Technical support fax 512 794 5678 Branch Offices Australia 03 9 879 9422 Austria 0662 45 79 90 0 Belgium 02 757 00 20 Canada Ontario 519 622 9310 Canada Qu bec 514 694 8521 Denmark 45 76 26 00 Finland 90 527 2321 France 1 48 14 24 24 Germany 089 741 31 30 Hong Kong 2645 3186 Italy 02 413091 Japan 03 5472 2970 Korea 02 596 7456 Mexico 95 800 010 0793 Netherlands 0348 433466 Norway 32 84 84 00 Singapore 2265886 Spain 91 640 0085 Sweden 08 730 49 70 Switzerland 056 200 51 51 Taiwan 02 377 1200 U K 01635 523545 Warranty The Lab PC board is warranted against defects in materials and workmanship for a period of one year from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation
65. Level Programming Appendix E Port C status word bit definitions for output Port A and Port B 7 6 1 0 5 4 3 2 OBFA INTEA INTRA INTEB OBFB INTRB Bit Name Description 7 OBFA Output buffer full for Port A Low indicates that the CPU has written data out to Port A 6 INTEA Interrupt enable bit for Port A If this bit is high interrupts are enabled from the 8255A for Port A Controlled by bit set reset of PCO 5 4 TO Extra I O status line when Port A is in Mode 1 output 3 INTRA Interrupt request status for Port A When INTEA is high and OBFA is high this bit is high indicating that an interrupt request is asserted 2 INTEB Interrupt enable bit for Port B If this bit is high interrupts are enabled from the 8255A for Port B Controlled by bit set reset of PC2 1 OBFB Output buffer full for Port B Low indicates that the CPU has written data out to Port B 0 INTRB Interrupt request status for Port B When INTEB is high and OBFB is high this bit is high indicating that an interrupt request is asserted At the digital I O connector Port C has the following pin assignments when in Mode output Notice that the status of ACKA and ACKB is not provided when Port C is read Lab PC User Manual E 30 National Instruments Corporation Appendix E Register Level Programming Programming Example Example 1 Configure Port A as an output port in Mode 1 e Write AO hex to the Digital Control Register e Wait for
66. National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this manual is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographical errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITE
67. O Data Register National Instruments Corporation E 9 Lab PC User Manual Register Level Programming Appendix E 4 Program Counter Al to force OUTI low If OUT is high Counter AO is disabled Write 70 hex to the Counter A Mode Register select Counter Al Mode 0 to force OUT1 low Counter AO can be used as the Sample Interval Counter 5 Clear the A D circuitry Before you start the data acquisition operation the A D FIFO must be emptied in order to clear out any old A D conversion results This emptying must be performed after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 8 bit write followed by two 8 bit reads from the A D FIFO Ignore the data obtained in the read 6 Start and service the data acquisition operation To start the data acquisition operation set the SWTRIG bit in Command Register 2 This enables Counter AO to start counting Once the data acquisition operation is started the operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do this perform the following sequence until the desired number of conversion results have been read a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 then read the A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation
68. OVERRUN bit in the Status Register is set The minimum recommended sampling interval on the Lab PC is 16 us Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A D Clear Register Programming in Freerun Acquisition Mode Freerun acquisition mode uses only Counter AO as the sample interval counter The number of A D conversions that have occurred that is the sample count is maintained by software in this case With this arrangement data acquisition operations can acquire more than 65 535 samples The following programming steps are required for a data acquisition operation in freerun acquisition mode Lab PC User Manual E 8 National Instruments Corporation Appendix E Register Level Programming 1 Select analog input channel gain and timebase for Counter AO The analog input channel and gain are selected by writing to the A D Configuration Register The SCANEN bit must be cleared for data acquisition operations on a single channel See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns If Counter BO is being used as a timebase for Counter AO then the TBSEL bit in Command Register 1 should be set at this time Command Register 1 needs to be written to only when the analog input channel gain setting or other function needs to be changed Program Counter BO if necessary The following sequence should be used to program Counter BO
69. OW bit is set in the Status Register to indicate that one or more A D conversion results have been lost because of FIFO overflow Writing to the A D Clear Register resets this error flag Two 8 bit dummy reads must be performed on the FIFO after an A D Clear to reset the FIFO A D FIFO Output Binary Modes The A D conversion result can be returned from the A D FIFO as a 16 bit two s complement or straight binary value by setting or clearing the TWOSCMP bit in Command Register 1 If the analog input circuitry is configured for the input range 0 to 10 V straight binary mode should be used clear the TWOSCMP bit Straight binary mode returns numbers between 0 and 4 095 decimal when the A D FIFO Register is read If the analog input circuitry is configured for the input range 5 to 5 V two s complement mode is more appropriate set the TWOSCMP bit Two s complement mode returns numbers between 2 048 and 2 047 decimal when the A D FIFO Register is read Table E 1 shows input voltage versus A D conversion values for the 0 to 10 V input range Table E 2 shows input voltage versus A D conversion values for two s complement mode and 5 to 5 V input range Table E 1 Unipolar Input Mode A D Conversion Values Straight Binary Coding Input Voltage A D Conversion Result Gain 1 Range 0 to 10 V Table E 2 Bipolar Input Mode A D Conversion Values Two s Complement Coding Input Voltage A D Conversion Result Gain 1 Range
70. PC4 STBA PC3 INTRA PC2 PCI PCO Pc3 IPC2 STBB PCI IBFB PCO INTRB Lab PC User Manual E 28 National Instruments Corporation Appendix E Register Level Programming Programming Example Example 1 Configure Port A as an input port in Mode 1 e Write BO hex to the Digital Control Register e Wait for bit 5 of Port C IBFA to be set indicating that data has been latched into Port A e Read data from Port A Example 2 Configure Port B as an input port in Mode 1 e Write 86 hex to the Digital Control Register e Wait for bit 1 of Port C IBFB to be set indicating that data has been latched into Port B e Read data from Port B Output The control word written to the Digital Control Register to configure Port A for output in Mode 1 is shown here Bits PC4 and PCS of Port C can be used as extra input or output lines when Port A uses Mode 1 output Port C bits PC4 and PCS 1 input 0 output The control word written to the Digital Control Register to configure Port B for output in Mode 1 is shown here Notice that Port B is not provided with extra input or output lines from Port C 7 6 5 4 3 2 1 0 Fara ERE eae During a Mode 1 data write transfer the status of the handshaking lines and interrupt signals can be obtained by reading Port C Notice that the bit definitions are different for a write and a read transfer National Instruments Corporation E 29 Lab PC User Manual Register
71. Procedure sesseeeeeseeesseeesseesresressessrerreesersresreesresese 5 4 Unipolar Input Calibration Procedure 5 5 Analog Output Calibration isseire sn e E E EEN R csa ss 5 6 Board CONG SUC AtO i isian Ste E ESS En 5 6 Bipolar Output Calibration Procedure ss 5 6 Unipolar Output Calibration Procedure ss 5 8 Appendix A Specifications EEE hk A BE LEI BL ees AI AE A 1 Appendix B OKI 82C53 Data Sheet ss B 1 Appendix C OKI 82C55A Data Sheet ooo ccccccesceecssessessesecsecevsecsaesecsasssessesaeveesnaeeees C 1 Appendix D Register Map and Descriptions D 1 Appendix E Register Level Programming 0 0 0 c ccc cs csssssesesesesesesesescecscsesesescseseseseseseseseass E 1 Appendix F Customer Communication F 1 GTOSS REV sess adopt asl Saat esac tise thc nn nn Glossary 1 MVR ENEE EAEE Mics Somes es ascot EE ON EEE E E EEN Index 1 National Instruments Corporation vii Lab PC User Manual Contents Figures Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware rs eitnertiis Sacer te eeai tine ue aitieas 1 3 Figure 2 1 Parts Locator Diagram sine nt tt ne nn th nent 2 2 Figure 2 2 Example Base I O Address Switch Settings 00 0 0 ceeceeescecseceeceeeeeceneeeeseeeenaees 2 4 Figure 2 3 DMA Jumper Settings for DMA Channel 3 Factory Setting eee 2 6 Figure 2 4 DMA Jumper Settings for Disabling DMA Transfers 2 7 Figure 2 5 Interrupt Jumper Sett
72. S ee nt ee 2 14 ERAT Wake Sion en er ne en D Ahead ee 2 15 National Instruments Corporation v Lab PC User Manual Contents Chapter 3 Signal Connections sachsen inde ee OS 3 1 VO Connector Pin DEscripta Om ier viesedva ciesk irisito e nf haleine 3 1 Signal Connection Descriptions 3 2 Analog Input Signal Connections ss one minime ln 3 4 Types of Signal Sources nee Ann et Men anid NS tes in Medias ne 3 5 Ploating Signal SOULCES ennemie Ne en eE E E eaa T ESENES 3 5 Ground Referenced Signal Sources ss 3 6 Input Configuration Seain aut cates LR A sata R Re 3 6 Differential Connection Considerations DIFF Configuration 3 6 Differential Connections for Grounded Signal Sources eescceesseeeeseeeeeees 3 7 Differential Connections for Floating Signal Sources ecceesceeeeseeeeeteeeeees 3 8 Single Ended Connection Considerations 3 10 Single Ended Connections for Floating Signal Sources RSECOni Curation en a dedi eed ee Nts ee BA EE 3 10 Single Ended Connections for Grounded Signal Sources NRSE Configuration escoire n a ii i 3 11 Common Mode Signal Rejection Considerations 3 12 Analog Output Signal Connections 3 12 Digital I O Signal Connections na on ann a enter 3 13 Port C Pin Connections seuils sine easier cede 3 15 Timing Sp cificati hS stent Ge erase Messe ts eds 3 16 Mode 1 mp t TIMMINS inira en el St a R S 3 18 Mode 1 Output
73. SE Rae A a en 1 1 Abo t the ab POT se RES Es EINE TR AE A 1 1 What You Need to Get Started jii 018 ee cia ented ene ea 1 1 Software Programming Choices x ssi inansn ii een ne RS nee ia ent 1 2 LabVIEW and LabWindows CVI Application Software ceceeesseeesteeeees 1 2 NI DAQ Driver Software sisi 1 2 Register Level Programming issus ethnies 1 3 Optional Equipment aac es Tes ee nn ne tt pees ne RS eee 1 4 Unpacking secinu nna r e a e du nnntinn sh daim 1 4 Chapter 2 Configuration and Installation 2 1 Board Configurations a a e e a a e daa tanta 2 1 PC Bus Interface 28 en nn NN Rs ee in SAS acces 2 1 Base W O Address Selection soso te AS ne ee Ad en 2 3 DNS Channel Selection see Re Re eee ne nt nt Gs 2 6 Interruptselection ASS a a a Sc ns er ae 2 7 Ana lo Uy OC aint eur OW ESS a nn ELES EENS 2 8 Analog Output Configuration 22e er nn nt Na wate 2 9 Bipolar Output Selecti n niin en eee 2 9 Unipolar Output Selection cited eee ea esta 2 10 Analog Input Confieuration s ruse een sente tent tie 2 10 Input Mode sn n n A a n a S 2 10 DIFF Input Four Channels sinus israel 2 11 RSE Input Eight Channels Factory Setting 0 eee eeeeceeeeseeeenteeeenes 2 12 NRSE Input Eight Chaminels s sis hentai 2 13 Analog Input Polarity Configuration ss 2 13 Bipolar Imput SElECHOM sey a dscsierales acasansatovsyncsbonespenceeaghadeurnavcedactyoodtiea des 2 13 Unipolar Input Selection LR R
74. These topics are discussed in the A D Interrupt Programming and Programming DMA Operation sections later in this appendix Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if a second A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is set The minimum recommended sampling interval on the Lab PC is 16 Us Both the OVERFLOW and OVERRUN bits in the Status Register are cleared by writing to the A D Clear Register Lab PC User Manual E 10 National Instruments Corporation Appendix E Register Level P
75. This bit enables and disables the generation of an interrupt when an A D error condition is detected If an A D error condition occurs either OVERFLOW or OVERRUN is set in the Status Register The interrupt is serviced by writing to the A D Clear Register If ERRINTEN is cleared no error interrupts are generated 3 CNTINTEN This bit enables the Counter A2 output or the EXTUPDATE signal to cause interrupts If this bit is set an interrupt occurs when either EXTUPDATE or Counter A2 output makes a low to high transition This interrupt is cleared by writing to the Timer Interrupt Clear Register This interrupt allows waveform generation on the analog output because the same signal that sets the interrupt also updates the DAC output if the corresponding LDAC bit in Command Register 2 is set If this bit is cleared interrupts from EXTUPDATE and Counter A2 output are ignored 2 TCINTEN This bit enables and disables the generation of an interrupt when a DMA terminal count pulse is received If TCINTEN is set an interrupt request is generated when the DMA Controller Transfer Count Register decrements from 0 to FFFF hex The interrupt is serviced by writing to the DMATCINT Clear Register National Instruments Corporation D 11 Lab PC User Manual Register Map and Descriptions Bit Name 1 DIOINTEN 0 DMAEN Lab PC User Manual Appendix D Description continued This bit enables or disables generation of an interrupt when either P
76. User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 22 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 23 Lab PC User Manual Appendix D Register Map and Descriptions This appendix describes in detail the address and function of each of the Lab PC registers Note If you plan to use a programming software package such as NI DAQ NI DSP LabVIEW or LabWindows CVI with your Lab PC you need not read this appendix Refer to your software documentation for programming information Register Map The register map for the Lab PC is given in Table D 1 This table gives the register name the register address offset from the board s base address the type of the register read only write only or read and write and the size of the register in bits National Instruments Corporation D 1 Lab PC User Manual Register Map and Descriptions Table D 1 Lab PC Register Map Appendix D Register Name Offset Address Type Size Hex Configuration and Status Register Group Command Register 1 Status Register Command Register 2 Command Register 3 Command Register 4 Analog Input Register Group A D FIFO Register A D Clear Register Start Convert Register DMATC Interrupt Clear Register Analog Output Register Group DACO Low Byte Register DACO High Byte Register DACI Low Byte Register DACI High Byte Register 8253 Counter Timer Register Group A Counter
77. V input Counter Al of the 8253 A Counter Timer is used as a sample counter The sample counter counts the number of A D conversions and disable conversions when the programmed count is reached The sample count must be less than or equal to 65 535 The minimum sample count is 2 To program the counters use the following programming sequence a Write 70 hex to the Counter A Mode Register select Counter Al Mode 0 This step sets the output of Counter Al OUTA1 low which in turn enables EXTCONV that is falling edges on EXTCONV initiate A D conversions b Write the least significant byte of M where M is the sample count after the trigger to the Counter Al Data Register c Write the most significant byte of M where M is the sample count after the trigger to the Counter Al Data Register After you complete this programming sequence counter A1 is configured to count A D conversion pulses and EXTTRIG input is enabled National Instruments Corporation E 15 Lab PC User Manual Register Level Programming Appendix E 5 Start and service the data acquisition operation To start the data acquisition operation set the SWTRIG bit in Command Register 2 After this setting A D conversions are initiated by a falling edge on EXTCONV input but the sample counter Counter A1 is not gated on until a rising edge on EXTTRIG input After a rising edge on EXTTRIG input is sensed A D conversions remain enabled for the program
78. Vin 2 2 V Output low voltage lout 2 5 mA Output high voltage out 2 5 mA Darlington drive output current Ports B and C only Rext 700 Q Vext 1 7 V 2 5 mA min 4 mA max Lan SHARIN oor i Css AN ete 3 wire requires 1 port Poweron Stale 3 3 a0 se tan te et or Configured as input Data transfers nm RNA AN Enr Bae Interrupt programmed I O Timing I O Number of channels eesceceeseeeeseeeeeees 3 counter timers IRESONMLION ss Lie nes see 16 bits Compatibility sa esanissanneninenns TTL gate and source pulled high with 4 7 KQ resistors Base clocks available ceeeceeeseceeeseeeeees 2 MHz Base Clock ACTA rs sonia en 0 01 Max source frequency 8 MHZ Min source pulse duration 60 ns Min gate pulse duration 50 ns D ta tr nsfers LS ne en a ne se Programmed I O National Instruments Corporation A 5 Lab PC User Manual Specifications Appendix A Digital logic levels Level Input low voltage 0 3 V 0 8 V Input high voltage 2 2 V 5 3 V Output low voltage lout 4 mA 0 45 V Output high voltage ou 1 mA 3 7 V Triggers Digital Trigger Compatibility Aisne ceases TTL Responsen a Rising edge PUSS widths eranan ai 250 ns Bus Interface 10 101210 Slave Power Requirements from PC 5 VDG l0 sisi Sees 180 mA BLD MID C2 se cheaters din Tran nie Mare 80 mA NOV IDC Aiea ET et sheen t
79. al list and description of terms used in this manual including abbreviations acronyms metric prefixes mnemonics and symbols e The Index contains an alphabetical list of key terms and topics used in this manual including the page where each one can be found Conventions Used in This Manual The following conventions appear in this manual 8253 lt gt bold bold italic italic italic monospace monospace monospace NI DAQ paths 8253 refers to the OKI Semiconductor 82C53 System Timing Controller integrated circuit Angle brackets containing numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example BDIO lt 3 0 gt Bold text denotes the names of menus menu items parameters dialog boxes dialog box buttons or options icons windows Windows OS Windows 95 tabs or pages or LEDs Bold italic text denotes a note caution or warning Italic text denotes emphasis a cross reference or an introduction to a key concept This text denotes text for which you supply the appropriate word or value such as in Windows 3 x Italic text in this font denotes that you must supply the appropriate words or values in the place of these items Bold text in this font denotes the messages and responses that the computer automatically prints to the screen This font also emphasizes lines of code that are unique from the other examples Text in this font den
80. and Register 2 EXTTRIG functions as a start trigger for a multiple A D conversion data acquisition operation In this mode referred to as posttriggering the sample interval counter is gated off until a low to high edge is sensed on EXTTRIG No samples are collected until EXTTRIG makes its low to high transition Transitions on the EXTCONV line are also ignored until a low to high edge is sensed on EXTRIG followed by a low to high edge on EXTCONV input Using the EXTTRIG Signal to Terminate a Multiple A D Conversion Data Acquisition Operation Pretrigger Mode If the PRETRIG bit is set and the HWTRIG bit is cleared in Command Register 2 EXTTRIG functions as a stop trigger for a multiple A D conversion data acquisition operation In this mode referred to as pretriggering the sample counter is gated off until a low to high edge is sensed on EXTTRIG Counter AO the sample interval counter starts as soon as the SWTRIG bit is set However Counter Al the sample counter does not start counting until the first rising edge on EXTTRIG In this way data is collected before the actual trigger rising edge After the rising edge occurs the number of points specified in Counter A1 are collected and the acquisition stops You must allocate sufficient array space for all of the data and specify both the number of points and the indeterminate number of points that may be collected before the pretrigger signal arrives Alternatively a circular buffer can be
81. annel scanning cycle E 17 circuitry See theory of operation circular buffer E 11 Lab PC User Manual Index 4 CLK signal See GATE CLK and OUT signals CLKB2 signal table 3 3 CNTINT bit data acquisition timing 3 24 description D 7 interrupt programming for analog output circuitry E 23 CNTINTEN bit data acquisition timing 3 23 description D 11 interrupt programming for analog output circuitry E 23 Command Register 1 channel scanning E 17 controlled acquisition mode E 6 posttrigger mode E 12 pretrigger mode E 14 description D 5 to D 6 freerun acquisition mode E 9 selecting analog input channel E 3 single channel interval acquisition mode E 19 Command Register 2 D 9 to D 10 Command Register 3 description D 11 to D 12 digital I O circuitry programming E 34 Command Register 4 description D 13 to D 14 single channel interval acquisition mode E 19 common mode signal rejection considerations 3 12 configuration analog input 2 10 to 2 14 DIFF input four channels 2 11 to 2 12 input mode 2 10 to 2 11 input polarity and range 2 13 to 2 14 jumper settings table 2 9 NRSE input eight channels 2 13 RSE input eight channels 2 12 analog output 2 9 to 2 10 bipolar output selection 2 9 jumper settings table 2 9 unipolar output selection 2 10 board base I O address selection 2 3 to 2 5 DMA channel selection 2 6 to 2 7 interrupt selection 2 7 to 2 8 National Instruments Corporation
82. ay need to reconfigure your software to reflect any changes in jumper or switch settings Lab PC User Manual 2 14 National Instruments Corporation Chapter 2 Configuration and Installation Hardware Installation The Lab PC can be installed in any available 8 bit or 16 bit expansion slot in your computer After you have changed if necessary verified and recorded the switches and jumper settings you are ready to install the Lab PC The following are general installation instructions but consult your PC user manual or technical reference manual for specific instructions and warnings 1 Turn off your computer 2 Remove the top cover or access port to the I O channel 3 Remove the expansion slot cover on the back panel of the computer 4 Insert the Lab PC into an 8 bit or a 16 bit slot 5 Screw the mounting bracket of the Lab PC to the back panel rail of the computer 6 Check the installation 7 Replace the cover The Lab PC board is installed You are now ready to install and configure your software If you are using NI DAQ refer to your NI DAQ release notes Find the installation and system configuration section for your operating system and follow the instructions given there If you are using LabVIEW the software installation instructions are in your LabVIEW release notes If you are using LabWindows CVI the software installation instructions are in your LabWindows CVI release notes If you are a register
83. bit 7 of Port C OBFA to be cleared indicating that the data last written to Port A has been read e Write new data to Port A Example 2 Configure Port B as an output port in Mode 1 e Write 84 hex to the Digital Control Register e Wait for bit 1 of Port C OBFB to be cleared indicating that the data last written to Port B has been read e Write new data to Port A Mode 2 This mode is for communication over a bidirectional 8 bit bus Handshake signals can be used in a manner similar to Mode 1 Interrupt generation and enable disable functions are also available Other features of this mode include the following e Used in Group A only Port A and upper nibble of Port C e One 8 bit bidirectional port Port A and a 5 bit control status port Port C e Both inputs and outputs are latched Control Words In Mode 2 an 8 bit bus can be used for both input and output transfers without changing the configuration The data transfers are synchronized with handshaking lines in Port C This mode uses only Port A however Port B can be used in either Mode 0 or Mode 1 while Port A is configured for Mode 2 The control word written to the Digital Control Register to configure Port A as a bidirectional data bus in Mode 2 is shown below Because Mode 2 is for Port A only Port B can be programmed to operate in Mode 0 or Mode 1 If Port B is configured for Mode 0 then PC2 PC1 and PCO of Port C can be used as extra input or output lin
84. counter In this mode a specified number of conversions are performed after which the hardware shuts off the conversions Counter AO generates the conversion pulses and Counter Al gates off Counter AO after the programmed count has expired The number of conversions in a single data acquisition operation in this case is limited to a 16 bit count on 65 535 In freerun acquisition mode only one counter is required for a data acquisition operation Counter AO continuously generates the conversion pulses as long as GATEAO is held at a high logic level The software keeps track of the number of conversions that have occurred and turns off Counter AO after the required number of conversions have been obtained The number of conversions in a single data acquisition operation in this case is unlimited Counter AO is clocked by a 1 MHz clock on start up National Instruments Corporation E 5 Lab PC User Manual Register Level Programming Appendix E Alternatively a programmable timebase for Counter AO is available through the use of Counter BO If the TBSEL bit in Command Register 1 is set then the timebase for Counter AO is Counter BO Counter BO has a fixed unalterable 2 MHz clock as its own timebase so its period is the value stored in it multiplied by 500 ns The minimum period that can be selected for Counter BO is 1 us The period of Counter AO or the sample period is then equal to the period of Counter BO multiplied by the value stored in
85. ctions for maximum ease of use and low level DAQ I O functions for maximum flexibility and performance Examples of high level functions are streaming data to disk or acquiring a certain number of data points An example of a low level function is writing directly to registers on the DAQ device NI DAQ does not sacrifice the performance of National Instruments DAQ devices because it lets multiple devices operate at their peak performance Lab PC User Manual 1 2 National Instruments Corporation Chapter 1 Introduction NI DAQ also internally addresses many of the complex issues between the computer and the DAQ hardware such as programming interrupts and DMA controllers NI DAQ maintains a consistent software interface among its different versions so that you can change platforms with minimal modifications to your code Whether you are using conventional programming languages LabVIEW or LabWindows CVI your application uses the NI DAQ driver software as illustrated in Figure 1 1 Conventional Programming Environment PC Macintosh or Sun SPARCstation LabVIEW LabWindows CVI PC Macintosh or PC or Sun Sun SPARCstation SPARCstation NI DAQ Driver Software Personal Computer or Workstation DAQ or SCXI Hardware Figure 1 1 The Relationship between the Programming Environment NI DAQ and Your Hardware You can use your Lab PC board together with other PC AT EISA DAQCard a
86. dividually To use the conversion interrupt set the FIFOINTEN bit in Command Register 3 If this bit is set an interrupt is generated whenever the DAVAIL bit in the Status Register is set This interrupt condition is cleared when the FIFO is emptied by reading its contents National Instruments Corporation E 19 Lab PC User Manual Register Level Programming Appendix E To use the error interrupt set the ERRINTEN bit in the Command Register 3 If this bit is set an interrupt is generated whenever the OVERFLOW or the OVERRUN bit in the Status Register is set This interrupt condition is cleared by writing to the A D Clear Register Programming DMA Operation The Lab PC can be programmed so that the FIFO generates a DMA request signal every time one or more A D conversion values are stored in the FIFO To program the DMA operation perform the following steps after the A D circuitry is set up for a data acquisition operation and before the data acquisition operation begins 1 Set the DMAEN bit in Command Register 3 to enable DMA request generation 2 Program the DMA controller to service DMA requests from the Lab PC board Because the DMA transfer is an 8 bit operation the transfer number written to the DMA Controller Count Register should be twice the number of conversions 3 If a DMA terminal count is received after the DMA service writing to the DMATC Clear Register clears the DMATC bit in the Status Register Once step a
87. dress Base address 1A hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 ov w DS w p e DT DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter B2 contents National Instruments Corporation D 31 Lab PC User Manual Register Map and Descriptions Appendix D Counter B Mode Register The Counter B Mode Register determines the operation mode for each of the three counters on the 8253 B chip The Counter B Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter Mode Register is an 8 bit register Bit descriptions for each of these bits are given in Appendix B OKI 82C53 Data Sheet of this manual Address Base address 1B hex Type Write only Word Size 8 bit Bit Map 6 5 0 7 4 3 2 1 Lab PC User Manual D 32 National Instruments Corporation Appendix D Register Map and Descriptions 8255A Digital I O Register Group Digital I O on the Lab PC uses an 8255A integrated circuit The 8255A is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports Bit descriptions for the registers in the Digital I O Register Group are given on the following pages National
88. e E 7 posttrigger mode E 13 pretrigger mode E 15 freerun acquisition mode E 10 description D 16 to D 17 output binary modes E 4 reading E 3 analog input circuitry programming E 3 controlled data acquisition programming E 8 freerun data acquisition programming E 10 theory of operation 4 5 voltage versus A D conversion values table bipolar input mode E 4 unipolar input mode E 4 DMATC Interrupt Clear Register D 20 overview D 15 register map table D 2 Start Convert Register D 19 analog input signal connections 3 4 to 3 5 exceeding input ranges warning 3 4 input ranges and maximum ratings 3 4 National Instruments Corporation input signals 3 4 Lab PC instrumentation amplifier figure 3 5 analog input specifications A 1 to A 2 amplifier characteristics A 2 dynamic characteristics A 2 explanation A 3 input characteristics A 1 stability A 2 transfer characteristics A 1 analog output calibration 5 6 to 5 8 bipolar output procedure 5 6 to 5 7 board configuration 5 6 unipolar output procedure 5 8 analog output circuitry block diagram 4 9 theory of operation 4 9 to 4 10 analog output circuitry programming E 20 to E 22 voltage output versus digital code E 21 to E 22 bipolar mode two s complement coding table E 22 unipolar mode straight binary coding table E 21 analog output configuration 2 9 to 2 10 bipolar output selection 2 9 jumper settings table 2 9 unipolar output sel
89. e parts locator diagram 2 2 G gain amplifier programmable 4 5 GAIN lt 2 0 gt bit D 5 GATAO bit description D 7 posttrigger mode controlled acquisition mode E 12 freerun acquisition mode E 16 GATBO signal table 3 3 GATBI signal table 3 3 GATB2 signal table 3 3 GATE CLK and OUT signals counter block diagram 4 14 event counting application figure 3 25 frequency measurement application figure 3 26 Lab PC User Manual Index 8 general purpose timing 3 24 to 3 27 timing requirements figure 3 27 general purpose timing connections event counting 3 25 application with external switch gating figure 3 25 frequency measurement 3 26 application figure 3 26 pretrigger timing figure 3 23 pulse and square wave generation 3 25 pulse width measurement 3 25 specifications and ratings 3 27 time lapse measurement 3 25 to 3 26 timing requirements for GATE and CLK signals figure 3 27 ground referenced signal sources definition 3 6 signal connection considerations differential connections 3 7 to 3 8 recommended configurations table 3 6 single ended connections 3 11 to 3 12 H hardware installation 2 15 HWTRIG bit controlled acquisition mode posttrigger mode E 13 pretrigger mode E 14 data acquisition timing 3 21 description D 10 multiple A D conversions using EXTTRIG signal E 11 I IBF signal description 3 16 Mode input timing 3 18 Mode 2 bidirectional timing 3 2
90. e Counter AO output OUT AO of the 8253 A Counter Timer chip on the Lab PC or by a high to low transition on EXTCONV input During data acquisition the onboard sample interval counter Counter 0 of 8253 A is used to generate pulses that initiate A D conversions The sample interval timer is a 16 bit down counter that uses the 1 MHz clock onboard to generate sample intervals from 2 us to 65 535 us see Timing 1 0 Circuitrylater in this chapter Alternatively the sample interval timer can use the output from Counter BO OUTBO of the 8253 B Counter Timer chip on the Lab PC Each time the sample interval timer reaches 0 it generates a pulse and reloads with the programmed sample interval count This operation continues until the counter is reprogrammed As stated in Appendix E Register Level Programming only Counter AO is required for data acquisition operations in freerun acquisition mode The software must keep track of the number of conversions that have occurred and turn off Counter AO after the required number of conversions have been obtained In controlled acquisition mode two counters Counters AO and A1 are required for a data acquisition operation Counter AO generates the conversion pulses and Counter Al gates off Counter AO after the programmed count has expired Single Channel Data Acquisition During single channel data acquisition the channel select and gain bits in Command Register 1 select the gain and analog input chan
91. e bits select the gain setting as follows GAIN lt 2 0 gt Selected Gain National Instruments Corporation D 5 Lab PC User Manual Register Map and Descriptions Appendix D Bit Name Description continued 3 TWOSCMP This bit selects the format of the coding of the output of the ADC If this bit is set the 12 bit data from the ADC is sign extended to 16 bits If this bit is cleared bits 12 through 15 return 0 2 0 MA lt 2 0 gt These three bits select which of the eight input channels are read The analog input multiplexers depend on these bits and also on SCANEN and SE D bit 3 of Command Register 4 Input channels are selected as follows Selected Analog Input Channels MA lt 2 0 gt Single Ended DIFF Scan Disabled Scan Enabled 0 1 1 1 1 2 3 2 3 5 3 3 7 4 5 1 5 5 3 6 7 5 7 7 7 In single ended mode RSE or NRSE if SCANEN is set analog channels MA lt 2 0 gt through 0 are sampled alternatively If SCANEN is cleared a single analog channel specified by MA lt 2 0 gt is sampled during the entire data acquisition operation In DIFF mode if SCANEN is set the analog channel pair corresponding to MA lt 2 0 gt specified in the table through 0 1 are sampled alternately In DIFF mode if SCANEN is cleared then a single analog channel pair specified by MA lt 2 0 gt is sampled during the entire data acquisition operation Note that in this mode MA lt 2 0 gt can hold the channel nu
92. e is used for transferring data with handshake signals Ports A and B use the eight lines of Port C to generate or receive the handshake signals This mode divides the ports into two groups Group A and Group B e Each group contains one 8 bit data port Port A or Port B and one 4 bit control data port upper or lower nibble of Port C e The 8 bit data ports can be either input or output both of which are latched e The 4 bit ports are used for control and status of the 8 bit data ports e Interrupt generation and enable disable functions are available Input In Mode 1 the digital I O bits are divided into two groups Group A and Group B Each of these groups contains one 8 bit port and one 4 bit control data port The 8 bit port can be either an input port or an output port and the 4 bit port is used for control and status information for the 8 bit port The transfer of data is synchronized by handshaking signals in the 4 bit port The control word written to the Digital Control Register to configure Port A for input in Mode 1 is shown here Bits PC6 and PC7 of Port C can be used as extra input or output lines 7 6 5 4 3 2 1 0 ae is fica a aio ee Toe Port C bits PC6 and PC7 1 input 0 output The control word written to the Digital Control Register to configure Port B for input in Mode 1 is shown here Notice that Port B is not provided with extra input or output lines from Port C 7 6 5 4 3 2 1 0 During a Mode
93. ection 2 10 Analog Output Register Group D 21 to D 22 DACO Low Byte DACO High Byte Registers D 22 E 20 DACI Low Byte DACI High Byte Registers D 22 E 20 overview D 21 register map table D 2 analog output signal connections 3 12 to 3 13 analog output specifications A 4 to A 5 dynamic characteristics A 4 explanation A 4 to A 5 output characteristics A 4 stability A 4 transfer characteristics A 4 voltage output A 4 B base I O address selection 2 3 to 2 5 National Instruments Corporation Index 3 Index example switch settings figure 2 4 factory settings table 2 3 possible settings with corresponding base I O address and base address I O space table 2 5 bipolar input mode bipolar input signal range versus gain table 4 8 configuration 2 13 to 2 14 voltage versus A D conversion values table E 4 bipolar output mode configuration 2 9 voltage output versus digital code table E 22 bits 2SDACO D 9 2SDACI D 9 CNTINT 3 24 D 7 E 23 CNTINTEN 3 23 D 11 E 23 D lt 7 0 gt A D FIFO Register D 17 Counter AO Data Register D 24 Counter Al Data Register D 25 Counter A2 Data Register D 26 Counter BO Data Register D 29 Counter B1 Data Register D 30 Counter B2 Data Register D 31 DACO Low Byte and DACI Low Byte Registers D 22 Digital Control Register D 37 Interval Counter Data Register D 39 Port A Register D 34 Port B Register D 35 Port C Register D 36 D lt 11 8 gt D 22
94. ed Straight binary is useful if a unipolar output range is selected 4 2SDACO This bit selects the binary coding scheme used for the DACO data If this bit is set a two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is useful if a bipolar output range is selected If this bit is cleared a straight binary coding scheme is used Straight binary is useful if a unipolar output range is selected 3 TBSEL This bit is used to select the clock source for A D conversions If this bit is cleared an internal 1 MHz clock drives the counter Counter AQ and the interval between samples is the value loaded into Counter AO multiplied by 1 us If this bit is set then the output of user programmable Counter BO is used as a clock source The timebase for Counter BO is fixed at 2 MHz and cannot be changed The interval between acquired samples is the value loaded into Counter AO multiplied by the period of the output signal from Counter BO National Instruments Corporation D 9 Lab PC User Manual Register Map and Descriptions Bit Name 2 SWTRIG 1 HWTRIG 0 PRETRIG Lab PC User Manual Appendix D Description continued This bit enables and disables a data acquisition operation that is controlled by Counter AO and Counter Al If Counter AO is programmed for data acquisition writing 1 to this bit enables Counter AO and thus starts a data acquisition operation A data acquisition process is ter
95. ee 450 mA Power available on rear connector 5 V at 1 A max Physical DiIMENSIONS 35 2cadsassavaavaseserecessncedesceesdeadeatens 16 5 by 9 9 cm 6 5 by 3 9 in VO COMMSC EOE iranienne 50 pin male Environment Operating temperature 0 to 70 C Storage temperature sc ete 55 to 150 C Relative B umidity s usines 5 to 90 noncondensing Lab PC User Manual A 6 National Instruments Corporation Appendix B OKI 82C53 Data Sheet This appendix contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit OKI Semiconductor This circuit is used on the Lab PC Copyright OKI Semiconductor 1991 Reprinted with permission of copyright owner All rights reserved OKI Semiconductor Microprocessor Data Book 1990 1991 National Instruments Corporation B 1 Lab PC User Manual OKI 82C53 Data Sheet Appendix B Lab PC User Manual B 2 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 3 Lab PC User Manual OKI 82C53 Data Sheet Appendix B Lab PC User Manual B 4 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 5 Lab PC User Manual OKI 82C53 Data Sheet Appendix B Lab PC User Manual B 6 National Instruments Corporation Appendix B OKI 82C53 Data Sheet National Instruments Corporation B 7 Lab PC User Manual OKI 82C53 Data Sheet
96. ee individual 8 bit ports The following paragraphs include programming information for the Lab PC The three 8 bit ports are divided into two groups Group A and Group B two groups of 12 signals One 8 bit configuration or control word specifies the mode of operation for each group The control bits of Group A configure Port A AO through A7 and the upper 4 bits nibble of Port C C4 through C7 The control bits of Group B configure Port B BO through B7 and the lower nibble of Port C CO through C3 These configuration bits are defined later in this chapter Register Descriptions and Programming Examples The following figures show the two control word formats used to completely program the 8255A The control word flag determines which control word format is being programmed When the control word flag is 1 bits O through 6 specify the I O characteristics of the 8255A s ports and the mode in which they are operating that is Mode 0 Mode 1 or Mode 2 When the control word flag is 0 bits 3 through 0 specify the bit set reset format of Port C National Instruments Corporation E 23 Lab PC User Manual Register Level Programming Control Word Mode Selection 00 Mode 0 01 Mode 1 1X Mode 2 Port A 1 input 0 output Port C high nibble 1 input 0 output 2o a a a D7 ps ns p4 3 p2 Di Do Appendix E Port C low nibble 1 input 0 output Port B 1 input 0 output Mode
97. ent on the OUTB1 line on the I O Connector drives the interval scanning circuitry If INTSCAN is clear EOIRCV does nothing more than disconnect the output of Counter B1 from the I O Connector if INTSCAN is clear always clear EOIRCV This bit is cleared on reset This bit selects the DAQ mode When you set this bit the Lab PC performs interval data acquisition If you clear this bit continuous channel scanning is selected If interval channel scanning is selected scan sequences occur during a programmed time interval called a scan interval The duration of the scan interval is determined by the output of Counter B1 or by the signal present on the OUTB1 line on the I O Counter as determined by EOIRCV This bit also selects the clock source for Counter B1 If interval scanning is disabled INTSCAN 0 then Counter B1 is available for user applications You can then drive CLKB1 externally at the VO Connector If interval scanning is enabled INTSCAN 1 the clock source for Counter AO also drives CLKB1 The source can be further selected by using the TBSEL bit in command register 2 This bit is cleared on reset D 14 National Instruments Corporation Appendix D Register Map and Descriptions Analog Input Register Group The four registers making up the Analog Input Register Group control the analog input circuitry and can be used to read the FIFO Reading the FIFO Register returns stored A D conversion results Writing to the Start
98. eptable Four times the accuracy of the Lab PC is 0 003 You need the following equipment to calibrate the Lab PC board For analog input calibration you need a precision variable DC voltage source usually a calibrator with these features Accuracy 0 001 standard 0 003 sufficient Range Greater than 10 V Resolution 100 uV in 10 V range 51 2 digits For analog output calibration you need a voltmeter with these features Accuracy 0 001 standard 0 003 sufficient Range Greater than 10 V Resolution 100 uV in 10 V range 51 2 digits National Instruments Corporation 5 1 Lab PC User Manual Calibration Chapter 5 Calibration Trimpots The Lab PC has six trimpots for calibration The location of these trimpots on the Lab PC board is shown in the partial diagram of the board in Figure 5 1 O 0C1 I G Lune 0000000U an CRE t gene siib PORTO 00000000000000 00000000000009 a o BO R ay S ersova t89va S 00000000000000 00000000000000 00000000000000 FE ocaco000 gt HOT 4 9 Googagga ka OMSM82C54 El crs7s die 236 DS Do BOSSES 020 Fit sane CE 5 OO oo ce Sogge A2 INSTRUMENTS CORP oocogogoo El ro O Guta PEPEE 5 m mi 4 5 SWITCH s oe a 9 00000 8 NESEZDIEF O e o atdala PELIEN 0000000000 SZN ul o a
99. er to drive its selected interrupt line The Lab PC hardware supports interrupt lines IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 and IRQ9 Note Do not use interrupt line 6 Interrupt line 6 is used by the diskette drive controller on most IBM PC and compatible computers Once you have selected an interrupt level place the interrupt jumper on the appropriate pins to enable the interrupt line The interrupt jumper set is W5 The default interrupt line is IRQ5 which you select by placing the jumper on the pins in row 5 Figure 2 5 shows the default interrupt jumper setting IRQ5 To change to another line remove the jumper from IRQ5 and place it on the new pins Figure 2 5 Interrupt Jumper Setting IRQ5 Factory Setting National Instruments Corporation 2 7 Lab PC User Manual Configuration and Installation Chapter 2 If you do not want to use interrupts place the jumper on W5 in the position shown in Figure 2 6 This setting disables the Lab PC from asserting an interrupt line on the PC I O channel Figure 2 6 Interrupt Jumper Setting for Disabling Interrupts Analog I O Configuration The Lab PC is shipped from the factory with the following configuration e Referenced single ended input mode e 5 V input range e Bipolar analog output e 5 V output range Table 2 4 lists all the available analog I O jumper configurations for the Lab PC with the factory settings noted Lab PC User Manual 2 8 National Instruments Corporation
100. erating with EXTUPDATE signal figure 3 24 types of interrupts 4 3 to 4 4 Interval Counter Register Group D 38 to D 40 Interval Counter Data Register National Instruments Corporation Index description D 39 single channel interval acquisition mode E 19 Interval Counter Strobe Register D 40 overview D 38 register map table D 2 interval scanning for multiple A D conversions E 17 to E 18 INTR signal description 3 17 Mode 1 input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C signal assignments table 3 16 INTRA status word Port C Mode 1 input E 28 Mode 1 output E 30 Mode 2 operation E 32 INTRB status word Port C Mode 1 input E 28 Mode 1 output E 30 INTSCAN bit description D 14 multiple A D conversions interval scanning E 17 to E 18 single channel interval acquisition mode E 18 to E 19 I O connector exceeding maximum ratings warning 3 1 pin assignments figure 3 2 signal connection descriptions table 3 3 I O status word Port C Mode 1 input E 28 Mode 1 output E 30 Mode 2 operation E 32 J jumper and switch settings analog I O table 2 9 base I O address selection 2 3 to 2 4 example switch settings figure 2 4 possible settings with corresponding base T O address and base address I O space table 2 5 bipolar output figure 2 9 DIFF input 2 11 to 2 12 DMA channel Index 9 Lab PC User Manual Index disabling DMA transfers figure
101. eria for use 3 10 floating signal sources RSE configuration 3 10 to 3 11 Lab PC User Manual Index grounded signal sources NRSE configuration 3 11 to 3 12 software programming choices LabVIEW and LabWindows CVI software 1 2 NI DAQ driver software 1 2 to 1 3 register level programming 1 3 specifications analog input A 1 to A 2 amplifier characteristics A 2 dynamic characteristics A 2 explanation A 3 input characteristics A 1 stability A 2 transfer characteristics A 1 analog output A 4 to A 5 dynamic characteristics A 4 explanation A 4 to A 5 output characteristics A 4 stability A 4 transfer characteristics A 4 voltage output A 4 bus interface A 6 digital I O A 5 environment A 6 physical A 6 power requirements A 6 timing I O A 5 to A 6 triggers A 6 Start Convert Register D 19 Status Register analog input circuitry programming E 3 controlled data acquisition programming E 8 posttrigger mode E 13 pretrigger mode E 16 description D 7 to D 8 freerun data acquisition programming E 10 STB signal description 3 16 Mode input timing 3 18 Mode 2 bidirectional timing 3 20 Port C signal assignments table 3 16 switch settings See jumper and switch settings SWTRIG bit controlled acquisition mode E 7 posttrigger mode E 12 pretrigger mode E 16 Lab PC User Manual Index 14 description D 10 freerun acquisition mode E 10 multiple A D conversions using EXTTRIG signal E 11
102. erisk after the bit name indicates that the bit is inverted negative logic In many of the registers several bits are labeled with an X indicating don t care bits When a register is read these bits may appear set or cleared but should be ignored because they have no significance When a register is written to setting or clearing these bit locations has no effect on the Lab PC hardware The bit map field for some write only registers state not applicable no bits used Writing to these registers causes some event to occur on the Lab PC such as clearing the analog input circuitry The data is ignored when writing to these registers therefore any bit pattern will suffice National Instruments Corporation D 3 Lab PC User Manual Register Map and Descriptions Appendix D Configuration and Status Register Group The five registers making up the Configuration and Status Register Group allow general control and monitoring of the Lab PC A D and D A circuitry Command Register 1 and Command Register 2 contain bits that control the operation modes of the A D and D A circuitry Command Register 3 enables or disables the interrupt and DMA operations Command Register 4 is used to select the analog input mode and also allows certain analog input conversion signals to be externally driven or received at the I O connector The Status Register reports the status of the A D conversion A D conversion error and the status of the interrupts Whe
103. es National Instruments Corporation E 31 Lab PC User Manual Register Level Programming Appendix E 0 7 Port C bits PC2 PCO 1 input 0 output Port B direction 1 input 0 output Group B Mode 0 Mode 0 1 Mode 1 During a Mode 2 data transfer the status of the handshaking lines and interrupt signals can be obtained by reading Port C The Port C status word bit definitions for a Mode 2 transfer are shown next Port C status word bit definitions for bidirectional data path Port A only 7 6 5 4 3 2 1 0 OBFA _ INTE IBFA INTE2 INTRA Bit Name 7 OBFA 6 INTEI 5 IBFA 4 INTE2 3 INTRA 2 0 VO Lab PC User Manual Description Output buffer full Low indicates that the CPU has written data out to Port A Interrupt enable bit for output If this bit is set interrupts are enabled from the 8255A for OBF Controlled by bit set reset of PC6 Input buffer full High indicates that data has been loaded into the input latch of Port A Interrupt enable bit for input If this bit is set interrupts are enabled from the 8255A for IBF Controlled by bit set reset of PC4 Interrupt request status If INTE is high and IBFA is high this bit is high indicating that an interrupt request is asserted for input transfers If INTE2 is high and OBFA is high this bit is high indicating that an interrupt request is asserted for output transfers Extra I O status lines available if Port B is n
104. et reset control words E 33 single bit set reset feature E 34 multiple A D conversions programming channel scanning E 17 controlled acquisition mode overview E 5 programming steps E 6 to E 8 external timing E 11 to E 17 controlled acquisition mode E 12 to E 16 posttrigger mode E 12 to E 14 pretrigger mode E 14 to E 16 freerun acquisition mode E 16 to E 17 posttrigger mode E 16 pretrigger mode E 17 using EXTCONV signal E 12 using EXTTRIG signal E 11 freerun acquisition mode overview E 5 programming steps E 8 to E 10 interval scanning E 17 to E 18 single input channel E 5 to E 10 controlled acquisition mode E 6 to E 8 freerun acquisition mode E 8 to E 10 single channel interval acquisition mode E 18 to E 19 multiple channel scanned data acquisition 4 6 to 4 7 multiplexers analog input 4 5 National Instruments Corporation N NI DAQ driver software 1 2 to 1 3 NRSE input eight channels configuration 2 13 definition table 2 11 signal connection considerations recommended configurations table 3 6 single ended connections 3 11 to 3 12 O OBF signal description 3 17 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C signal assignments table 3 16 OBFA status word Port C Mode 1 output E 30 Mode 2 operation E 32 OBFB status word Port C E 30 OKI 82C53 data sheet B 1 to B 13 OKI 82C55A data sheet C 1 to C 23 operation of Lab PC See theory of operation OUT s
105. f Counter B1 is driven by the same signal that is driving CLKAO The OUTB1 pin on the I O connector initiates scan sequences that are separated by a programmable scan interval time The timebases for Counters B1 and B2 must be supplied externally through the 50 pin I O connector Figure 4 7 shows an example of interval scanning timing Scan Interval Sample Sample OUTAO j Interval Interval GATEAO a ADC CH CH1 CHO CHI CHO CONVERT eS E O ee Figure 4 7 Two Channel Interval Scanning Timing The single channel interval acquisition mode makes use of an additional 8 bit counter the Interval Counter In this mode Counter B1 initiates scan sequences that are separated by a programmable interval time The Interval Counter is programmed for the number of samples of the selected channel in each interval Figure 4 8 shows an example of single channel interval timing In this example Counter B1 is programmed for the sample interval and the Interval Counter is programmed to count three samples wait for the duration of the scan interval count three samples and so on The acquisition operation ends when the sample counter Counter A1 decrements to 0 National Instruments Corporation 4 13 Lab PC User Manual Theory of Operation Chapter 4 Scan Interval Sample Sample Interval Interval ee a CONVERT IL GATEAO M a aa a Interval Counter Figure 4 8 Single Channel Interval Timing The 16 bit coun
106. fer to Analog Input Signal Connections in Chapter 3 Signal Connections which contains diagrams showing the signal paths for the three configurations DIFF Input Four Channels DIFF input means that each input signal has its own reference and the difference between each signal and its reference is measured The signal and its reference are each assigned an input channel With this input configuration the Lab PC can monitor four differential analog input signals To select the DIFF mode you must set the SE D bit as described in the Command Register 4 bit description in Appendix D Register Map and Descriptions You must also set the following jumper W4 B C Jumper is in stand by position and negative input of instrumentation amplifier is tied to multiplexer output National Instruments Corporation 2 11 Lab PC User Manual Configuration and Installation Chapter 2 This configuration is shown in Figure 2 9 NRSE DIFF Figure 2 9 DIFF Input Configuration Considerations in using the DIFF configuration are discussed in Chapter 3 Signal Connections Note that the signal return path is through the negative terminal of the amplifier and through Channels 1 3 5 or 7 depending on which channel pair was selected RSE Input Eight Channels Factory Setting RSE input means that all input signals are referenced to a common ground point that is also tied to the analog input ground of the Lab PC The negative input of the differen
107. fferent binary formats straight binary or two s complement binary The binary format used is selected by the TWOSCMP bit in the Command Register 1 The bit pattern returned for either format is given below Address Base address OA hex Type Read only Word Size 8 bit Bit Map Straight binary mode High Byte 7 6 5 4 3 2 1 0 DIS DA fe Di i De pO DE Dw e Do gt Ds 0 0 0 0 Low Byte 7 6 5 4 3 2 1 0 Dv D6 DS D4 D3 D DM DO Bit Name Description High Byte 7 0 D lt 15 8 gt These bits contain the high byte of the straight binary result of a 12 bit A D conversion Bits D lt 15 12 gt are always 0 in straight binary mode Values made up of D lt 11 0 gt therefore range from 0 to 4 095 decimal 0000 to OFFF hex Straight binary mode is useful for unipolar analog input readings because all values read reflect a positive polarity input signal Lab PC User Manual D 16 National Instruments Corporation Appendix D Register Map and Descriptions Bit Name Description continued Low Byte 7 0 D lt 7 0 gt These bits contain the low byte of the straight binary result of a 12 bit A D conversion The first of two consecutive readings of the A D FIFO Register always return this byte Bit Map Two s complement binary mode High Byte 7 6 5 4 3 l D Sign Extension Bits Low Byte 7 6 5 4 3 2 1 0 D7 D Dds D DS De Db Do Bit Name Description High Byte 7 0 D lt 15 8 gt These bi
108. for GATE and CLK signals figure 3 27 timing I O circuitry 4 11 to 4 14 block diagram 4 12 counter block diagram 4 14 single channel interval timing figure 4 14 two channel interval scanning timing figure 4 13 timing I O specifications A 5 to A 6 trigger specifications A 6 two channel interval scanning timing figure 4 13 TWOSCMP bit description D 6 returning A D conversion result E 4 National Instruments Corporation Index 15 Index U unipolar input mode configuration 2 14 unipolar input signal range versus gain table 4 8 voltage versus A D conversion values table E 4 unipolar output mode configuration 2 10 voltage output versus digital code table E 21 unpacking the Lab PC 1 4 W waveform generation operation E 22 to E 23 WR signal description 3 17 Mode output timing 3 19 Mode 2 bidirectional timing 3 20 Lab PC User Manual
109. g steps are required for waveform generation using interrupts 1 Set up Command Register 2 The LDACO bit must be set high for enabling OUTA2 or EXTUPDATE driven updates on DACO LDAC 1 bit must be set high for enabling OUTA2 or EXTUPDATE driven updates on DACI 2 Program Counter A2 If EXTUPDATE is being used to update the DACs Counter A2 output OUTA2 must be set high by writing B8 hex to the Counter A Mode Register If OUTA2 is being used to update the DACs EXTUPDATE must be left unconnected or driven to a TTL high level Counter A2 must be programmed in Mode 2 with the appropriate update interval Lab PC User Manual E 22 National Instruments Corporation Appendix E Register Level Programming 3 Enable timer interrupts Timer interrupts refer to the interrupts generated by rising edges on OUTA2 or EXTUPDATE A rising edge on OUTA2 or EXTUPDATE sets the CNTINT bit high in the Status Register A timer interrupt is generated whenever the CNTINT bit in the Status Register and the CNTINTEN bit in Command Register 3 are set high Set the CNTINTEN bit in Command Register 3 high to enable timer interrupts Programming the Digital I O Circuitry The digital I O circuitry is designed around an 8255A integrated circuit The 8255A is a general purpose PPI containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A These ports can be programmed as two groups of 12 signals or as thr
110. g to the ADCLR Register this bit is set Two 8 bit readings of FIFO are needed to clear this bit D 8 National Instruments Corporation Appendix D Register Map and Descriptions Command Register 2 Command Register 2 contains eight bits that control Lab PC analog input trigger modes and analog output modes Address Base address 01 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 LDACI LDACO 2SDACI 2SDACO TBSEL SWTRIG HWTRIG PRETRIG Bit Name Description 7 LDACI This bit is used to enable timer waveform generation from DACI If this bit is set DACI updates its output at regular intervals as determined by Counter A2 or the EXTUPDATE signal at the I O connector If this bit is cleared then the voltage output of DACI is updated as soon as the data is loaded into its data register 6 LDACO This bit is used to enable timer waveform generation from DACO If this bit is set DACO updates its output at regular intervals as determined by Counter A2 or the EXTUPDATE signal at the I O connector If this bit is cleared then the voltage output of DACO is updated as soon as the data is loaded into its data register 5 2SDACI This bit selects the binary coding scheme used for the DACI data If this bit is set a two s complement binary coding scheme is used for interpreting the 12 bit data Two s complement is useful if a bipolar output range is selected If this bit is cleared a straight binary coding scheme is us
111. g to the DACO Data Register loads DACO and writing to the DACI Data Register loads DAC1 The analog output on pins DACO OUT or DACI OUT can be updated in one of three ways immediately when the DACO or the DAC1 Data Register is written to when a low level is detected on the EXTUPDATE pin or when a low level is detected on the output of Counter A OUTA2 The LDAC bits in Command Register 2 determine which update method is used If LDACO is set high the analog output from DACO is Lab PC User Manual E 20 National Instruments Corporation Appendix E Register Level Programming updated when a low level is detected on either EXTUPDATE or OUTA2 If LDACO is set low the analog output from DACO is updated as soon as the DACO Data Register is written to LDACI controls the updating of DAC analog output in a similar manner The output voltage generated from the digital code depends on the configuration unipolar or bipolar of the associated analog output channel Unipolar or bipolar configuration is determined by jumper settings described in Chapter 2 Configuration and Installation Table E 3 shows the output voltage versus digital code for a unipolar analog output configuration Table E 4 shows the voltage versus digital code for a bipolar analog output configuration The following formula calculates the voltage output versus digital code for a unipolar analog output configuration and straight binary coding digital code Vou 10 0 SA
112. gister 4 Lab PC User Manual E 2 National Instruments Corporation Appendix E Register Level Programming Analog Input Circuitry Programming Sequence Programming the analog input circuitry for a single A D conversion involves selecting the analog input channel and gain initiating an A D conversion and reading the A D conversion result 1 Select analog input channel and gain The analog input channel and gain are selected by writing to Command Register 1 See the Command Register 1 bit description earlier in this chapter for gain and analog input channel bit patterns Set up the bits as given in the Command Register 1 bit description and write to the Command Register 1 Command Register 1 needs to be written to only when the analog input channel gain setting input mode unipolar bipolar or scanning mode need to be changed 2 Initiate an A D conversion An A D conversion can be initiated by an active low pulse on the Counter AO output OUT AO or on the EXTCONV line To enable Counter AO and the EXTCONV the SWTRIG bit in Command Register 2 must be set and OUTAI must be low Alternatively a conversion can be performed by writing to the Start Convert Register Once an A D conversion is initiated the ADC stores the result in the A D FIFO at the end of its conversion cycle or after a rising edge on OUTAO whichever occurs later In case of EXTCONV initiating the conversion OUTAO must be set high 3 Read the A D conver
113. hem To make it easy for you to contact us this manual contains comment and configuration forms for you to complete These forms are in Appendix F Customer Communication at the end of this manual National Instruments Corporation xiii Lab PC User Manual Chapter 1 Introduction This chapter describes the Lab PC lists what you need to get started describes the optional software and optional equipment and explains how to unpack the Lab PC About the Lab PC The Lab PC is a low cost multifunction analog digital and timing I O board for the PC The Lab PC contains a 12 bit successive approximation ADC with eight analog inputs which can be configured as eight single ended or four differential channels The Lab PC also has twol2 bit DACs with voltage outputs 24 lines of TTL compatible digital I O and six 16 bit counter timer channels for timing I O The low cost of a system based on the Lab PC makes it ideal for laboratory work in industrial and academic environments The multichannel analog input is useful in signal analysis and data logging The 12 bit ADC is useful in high resolution applications such as chromatography temperature measurement and DC voltage measurement The analog output channels can be used to generate experiment stimuli and are also useful for machine and process control and analog function generation The 24 TTL compatible digital I O lines can be used for switching external devices such as transistors and
114. ignal See GATE CLK and OUT signals OUTA signal controlled acquisition mode E 12 OUTA2 signal interrupt programming E 22 to E 23 OUTBO signal table 3 3 OUTB1 signal interval scanning E 18 OUTB2 signal table 3 3 OVERFLOW bit A D FIFO overflow condition analog input circuitry programming E 4 controlled acquisition programming E 8 posttrigger mode E 14 pretrigger mode E 16 freerun acquisition programming E 10 A D interrupt programming E 20 description D 7 OVERRUN bit A D FIFO overrun condition clearing the analog input circuitry E 5 controlled acquisition programming E 8 posttrigger mode E 14 National Instruments Corporation Index 11 Index pretrigger mode E 16 freerun acquisition programming E 10 A D interrupt programming E 20 description D 8 P PAO lt 0 7 gt signal table 3 3 PBO lt 0 7 gt signal table 3 3 PC bus interface 2 1 factory settings table 2 3 PC I O channel interface circuitry block diagram 4 3 theory of operation 4 2 to 4 4 PCO lt 0 7 gt signal table 3 3 physical specifications A 6 polarity configuration analog input bipolar 2 13 to 2 14 unipolar 2 14 analog output bipolar 2 9 unipolar 2 10 Port A Register D 34 Port B Register D 35 Port C Register description D 36 pin assignments Mode 1 input E 28 Mode 1 output E 30 Mode 2 operation E 33 pin connections 3 15 to 3 16 signal assignments table 3 16 timing specifications 3 16 to 3 17
115. ignals and read write signals The data buffers control the direction of data transfer on the bidirectional data lines based on whether the transfer is a read or write The interrupt control circuitry routes any enabled interrupts to the selected interrupt request line The interrupt requests are tristate output signals allowing the Lab PC board to share the interrupt lines with other devices Six interrupt request lines are available for use by the Lab PC IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 and IRQ9 Five different interrupts can be generated by the Lab PC e When an A D conversion is available to be read from FIFO e When either an OVERFLOW or an OVERRUN error occurs e When DMA terminal count pulse is received National Instruments Corporation 4 3 Lab PC User Manual Theory of Operation Chapter 4 e When a digital I O port is ready to transfer data e When arising edge signal is detected on Counter A2 output or on the EXTUPDATE line Each one of these interrupts is individually enabled and cleared The DMA control circuitry generates DMA requests whenever an A D conversion result is available from FIFO if the DMA transfer is enabled The Lab PC supports 8 bit DMA transfers DMA Channels 1 2 and 3 of the PC I O channel are available for such transfers Analog Input and Data Acquisition Circuitry The Lab PC provides eight channels of analog input with software programmable gain and 12 bit A D conversion Using the timing circuitry
116. ignificant byte of the sample interval to the Counter AO Data Register Use the following sequence to program the sample counter Write 70 to the Counter A Mode Register select Counter Al Mode 0 b Write the least significant byte of M 2 where M is the sample count to the Counter Al Data Register c Write the most significant byte of M 2 where M is the sample count to the Counter Al Data Register After you complete this programming sequence Counter A1 is configured to count A D conversion pulses and Counter AO output is in a high state 4 Clear the A D circuitry Before the data acquisition operation is started the A D FIFO must be emptied in order to clear out any old A D conversion results This emptying must be performed after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 8 bit write followed by two 8 bit reads from the A D FIFO Ignore the data obtained in the read 5 Start and service the data acquisition operation To start the data acquisition operation set the SWTRIG bit in Command Register 2 This enables Counter AO to start counting National Instruments Corporation E 7 Lab PC User Manual Register Level Programming Appendix E Once the data acquisition operation is started the operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To do th
117. in greater detail how the module works and contain application hints Your DAQ hardware user manuals These manuals have detailed information about the DAQ hardware that plugs into or is connected to your computer Use these manuals for hardware installation and configuration instructions specification information about your DAQ hardware and application hints Software documentation Examples of software documentation you may have are the LabVIEW and LabWindows CVI documentation sets and the NI DAQ documentation After you set up your hardware system use either the application software LabVIEW or LabWindows CVI or the NI DAQ documentation to help you write your application If you have a large and complicated system it is worthwhile to look through the software documentation before you configure your hardware Accessory installation guides or manuals If you are using accessory products read the terminal block and cable assembly installation guides They explain how to physically connect the relevant pieces of the system Consult these guides when you are making your connections SCXI chassis manuals If you are using SCXI read these manuals for maintenance information on the chassis and installation instructions Customer Communication National Instruments wants to receive your comments on our products and manuals We are interested in the applications you develop with our products and we want to help if you have problems with t
118. ing IRQS Factory Setting ee eee eeeeceseeeeeeeeeeenseeees 2 7 Figure 2 6 Interrupt Jumper Setting for Disabling Interrupts 000 eee eeeeeeeeereeeneeeees 2 8 Figure 2 7 Bipolar Output Jumper Configuration Factory Setting eee eeeeeeeeeeeees 2 9 Figure 2 8 Unipolar Output Jumper Configuration ss 2 10 Figure 2 9 DIFF Input Configuration ssh 2 12 Figure 2 10 RSE Input Configuration signe cine nn Re Ent int sense 2 12 Figure 2 11 NRSE Input Configurations uit lesdadeasdacacvenens 2 13 Figure 2 12 Bipolar Input Jumper Configuration Factory Setting eeeeeeseeeeeteeeenees 2 14 Figure 2 13 Unipolar Input Jumper Configuration 2 14 Figure 3 1 Lab PC I O Connector Pin Assignments ccc ceeceeeceeseeceeeeeseceeeeeeaeeesaeenes 3 2 Figure 3 2 Lab PC Instrumentation Amplifier eee eeseceseceseeeeseecnseceeeseeeseneesnaeenes 3 5 Figure 3 3 Differential Input Connections for Grounded Signal Sources 0 0 0 eee 3 8 Figure 3 4 Differential Input Connections for Floating Sources 3 9 Figure 3 5 Single Ended Input Connections for Floating Signal Sources 3 11 Figure 3 6 Single Ended Input Connections for Grounded Signal Sources eee 3 12 Figure 3 7 Analog Output Signal Connections 3 13 Figure 3 8 Digital I O Connections ss agit del paar miantnis nee 3 15 Figure 3 9 EXTCONV Signal TIM nant nn nr s 3 21 Figure 3 10 Posttrigger Data Acquisition Timing Case 1 ooo ceeeeeecceeeeeeceteeeeeteeeenneeeeaees 3
119. ion D 27 interrupt programming for analog output circuitry E 22 to E 23 Counter AO Data Register controlled acquisition mode E 6 E 7 posttrigger mode E 13 pretrigger mode E 15 description D 24 freerun acquisition mode 4 6 E 9 used as sample interval counter E 9 Counter Al Data Register controlled acquisition mode E 7 posttrigger mode E 13 pretrigger mode E 15 description D 25 freerun acquisition mode E 10 single channel interval acquisition mode E 19 Counter A2 Data Register D 26 Counter B Mode Register description D 32 multiple A D conversions using interval scanning E 18 single channel interval acquisition mode E 19 Counter BO Data Register description D 29 programming controlled acquisition mode E 6 freerun acquisition mode E 9 Counter B1 Data Register description D 30 multiple A D conversions using interval scanning E 18 single channel interval acquisition mode E 19 Counter B2 Data Register D 31 counter block diagram 4 14 COUTB1 signal table 3 3 customer communication xiii F 1 Index 5 Lab PC User Manual Index D D lt 7 0 gt bits A D FIFO Register D 17 Counter AO Data Register D 24 Counter Al Data Register D 25 Counter A2 Data Register D 26 Counter BO Data Register D 29 Counter B1 Data Register D 30 Counter B2 Data Register D 31 DACO Low Byte and DAC1 Low Byte Registers D 22 Digital Control Register D 37 Interval Counter Data Register D 39 Port A Register D 34 Port
120. iplexer 2 selects AISENSE AIGND If W4 is configured in SE mode AISENSE AIGND gets tied to analog ground This is the RSE mode If W4 is configured as DIFF AISENSE AIGND does not get tied to analog ground This is the NRSE mode When this bit is set the differential mode of input is selected Now W4 must be in the DIFF setting This is the DIFF mode In this mode Mux 1 and Mux 2 select channel pairs 0 1 2 3 4 5 or 6 7 depending on the channel selection bits This bit defaults to zero on reset thus choosing the single ended mode Refer to the following table for choosing the appropriate mode W4 Configuration SE D Bit 3 Input Mode RSE A B RSE factory setting NRSE DIFF B C NRSE NRSE DIFF B C DIFF National Instruments Corporation D 13 Lab PC User Manual Register Map and Descriptions Bit Name 2 ECKDRV 1 EOIRCV 0 INTSCAN Lab PC User Manual Appendix D Description continued This bit controls the direction of the EXTCONV line on the I O Connector If this bit is clear EXTCONV is driven from the I O Connector into the conversion circuitry If this bit is set a conditioned version of the output of counter AO is driven onto the I O Connector Under most circumstances this bit should be clear This bit is cleared on reset This bit is used to select the clock source for interval scanning If this bit is clear Counter B1 drives the interval scanning circuitry If this bit is set the signal pres
121. is perform the following sequence until the desired number of conversion results have been read a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 then read the A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation These topics are discussed in the A D Interrupt Programming and Programming DMA Operation sections later in this appendix Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is set An overrun condition occurs if a second A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the
122. is interpreted as a 12 bit two s complement number with a range of 2 048 to 2 047 In this mode the MSB of the ADC result is inverted to make it two s complement The output from the ADC is then sign extended to 16 bits causing either a leading 0 or a leading F hex to be added depending on the coding and the sign Thus data values read from the FIFO are 16 bits wide Data Acquisition Timing Circuitry A data acquisition operation refers to the process of taking a sequence of A D conversions with the sample interval the time between successive A D conversions carefully timed The data acquisition timing circuitry consists of various clocks and timing signals that perform this timing The Lab PC board can perform both single channel data acquisition and multiple channel National Instruments Corporation 4 5 Lab PC User Manual Theory of Operation Chapter 4 scanned data acquisition in two modes continuous and interval The Lab PC uses a counter to switch between analog input channels automatically during scanned data acquisition Data acquisition timing consists of signals that initiate a data acquisition operation initiate individual A D conversions gate the data acquisition operation and generate scanning clocks Sources for these signals are supplied mainly by timers on the Lab PC board One of the two 8253 integrated circuits is reserved for this purpose An A D conversion can be initiated by a high to low transition on th
123. l Timing The timing specifications for bidirectional transfers in Mode 2 are as follows Name Description Minimum Maximum Tl WR 1 to OBF 0 650 T2 Data before STB 1 0 T3 STB pulse width 500 T4 STB 0 to IBF 1 300 T5 Data after STB 1 180 T6 ACK 0 to OBF 1 350 T7 ACK pulse width 300 z T8 ACK 0 to output 300 T9 ACK 1 to output float 20 250 T10 RD 1 to IBF 0 300 All timing values are in nanoseconds Lab PC User Manual 3 20 National Instruments Corporation Chapter 3 Signal Connections Timing Connections Pins 38 through 48 of the I O connector are connections for timing I O signals The timing I O of the Lab PC is designed around the 8253 Counter Timer integrated circuit Two of these integrated circuits are employed in the Lab PC One designated 8253 A is used exclusively for data acquisition timing and the other 8253 B is available for general use Pins 38 through 40 carry external signals that can be used for data acquisition timing in place of the dedicated 8253 A These signals are explained in the next section Data Acquisition Timing Connections Pins 41 through 48 carry general purpose timing signals from 8253 B These signals are explained under General Purpose Timing Signal Connections and General Purpose Counter Timing Signals later in this chapter Data Acquisition Timing Connections Counter 0 on the 8253 A Counter Timer referred to as AO is u
124. le A D Conversions with Interval Scanning In addition to scanning multiple channels the Lab PC can also use interval scanning if more than one channel is being scanned If the INTSCAN bit in the Configuration Register is set interval scanning is enabled and a single channel scanning cycle is performed for every pulse received on the OUTB1 line on the I O connector This signal may be driven by Counter B1 or by an external source A channel scanning cycle consists of the sequence of back to back conversions performed while channels N through 0 are sampled the duration of a channel scanning cycle is N 1 times the sample interval determined by Counter AO or EXTCONV An interval scanning cycle consists of a channel scanning cycle followed by a time period in which no conversions are performed The duration of an interval scanning cycle is equal to the period of the signal present on the OUTB1 line The period of this signal must be at least as long as the channel scanning cycle While using the interval scanning mode the SCANEN bit in the Analog Configuration Register is used to gate the operation of the INTSCAN bit until the data National Instruments Corporation E 17 Lab PC User Manual Register Level Programming Appendix E acquisition operation is fully configured Use the following sequence to configure the Lab PC for interval scanning 1 Write the configuration value indicating the highest channel number in the scan sequence the gai
125. led acquisition mode E 6 E 7 posttrigger mode E 13 pretrigger mode E 15 description D 24 freerun acquisition mode 4 6 E 9 used as sample interval counter E 9 Counter Al Data Register controlled acquisition mode E 7 posttrigger mode E 13 pretrigger mode E 15 description D 25 freerun acquisition mode E 10 single channel interval acquisition mode E 19 Counter A2 Data Register D 26 Counter B Mode Register description D 32 multiple A D conversions using interval scanning E 18 single channel interval acquisition mode E 19 Counter BO Data Register description D 29 programming controlled acquisition mode E 6 freerun acquisition mode E 9 Counter B1 Data Register description D 30 multiple A D conversions using interval scanning E 18 single channel interval acquisition mode E 19 Counter B2 Data Register D 31 overview D 23 National Instruments Corporation Index 1 register map D 2 Timer Interrupt Clear Register D 28 8255A Digital I O Register Group D 33 to D 37 Digital Control Register D 37 overview D 33 Port A Register D 34 Port B Register D 35 Port C Register D 36 programming E 23 to E 34 control word format control word flag set to 0 figure E 24 control word flag set to 1 figure E 24 Mode 0 operation E 25 to E 26 control words E 25 to E 26 programming examples E 26 Mode 1 input E 27 to E 28 control words E 27 Port C pin assignments E 28 Port C status word bit definitions E 2
126. level programmer refer to Appendix E Register Level Programming National Instruments Corporation 2 15 Lab PC User Manual Chapter 3 Signal Connections This chapter describes how to make input and output signal connections to your Lab PC board via the board I O connector T O Connector Pin Description Figure 3 1 shows the pin assignments for the Lab PC I O connector This connector is located on the back panel of the Lab PC board and is accessible at the rear of the PC after the board has been properly installed Warning Connections that exceed any of the maximum ratings of input or output signals on the Lab PC may result in damage to the Lab PC board and to the computer This includes connecting any power signals to ground and vice versa National Instruments is NOT liable for any damages resulting from any such signal connections National Instruments Corporation 3 1 Lab PC User Manual Signal Connections Chapter 3 ACHO ACH2 ACH4 ACH6 AISENSE AIGND ACH1 ACH3 ACHS ACH7 DACO OUT AGND DGND PAI PA3 PAS PA7 DACI OUT PAO PA2 PA4 PA6 PBO PB2 PB4 PB6 PCO PC2 PC4 PC6 EXTTRIG EXTCONV GATBO PB1 PB3 PBS PB7 PCI PC3 PCS PC7 D D wa D amp Uo Lo CE EE jo Alojo Olja RR Ww ow NIN nine wo AJN RIS AlILRIW oOlolaslaRlrutito A EXTUPDATE OUTBO COUTBI GATB1 CCLKB1 OUTB2 GATB2 CLKB2 5 V DGND g z 29 35 37 39 n EN O
127. listed are trademarks or trade names of their respective companies WARNING REGARDING MEDICAL AND CLINICAL USE OF NATIONAL INSTRUMENTS PRODUCTS National Instruments products are not designed with components and testing intended to ensure a level of reliability suitable for use in treatment and diagnosis of humans Applications of National Instruments products involving medical or clinical treatment can create a potential for accidental injury caused by product failure or by errors on the part of the user or application designer Any use or application of National Instruments products for or involving medical or clinical treatment must be performed by properly trained and qualified medical personnel and all traditional medical safeguards equipment and procedures that are appropriate in the particular situation to prevent serious injury or death should always continue to be used when National Instruments products are being used National Instruments products are NOT intended to be a substitute for any form of established process procedure or equipment used to monitor or safeguard human health and safety in medical or clinical treatment Contents About This Manual 88 anna nent nt tn dns en xi Organization of the Lab PC User Manual ss xi Conventions Used in This MARUAL ESS ne tn dde xii National Instruments Documentation SRE SR re nee etes delete xiii Customer Communication ss issiinannnannmennitaianiienaitientes xiii Chapter 1 Introduction
128. mber of either of the channels that make the differential pair See Programming Multiple A D Conversions with Channel Scanning in Appendix E Register Level Programming for the correct sequence involved in setting the SCANEN bit Lab PC User Manual D 6 National Instruments Corporation Appendix D Register Map and Descriptions Status Register The Status Register indicates the status of the current A D conversion The bits in this register determine if a conversion is being performed or if data is available whether any errors have been found and the interrupt status Address Base address 00 hex Type Read only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Lab PC PC EXTGATAO GATAO DMATC CNTINT OVERFLOW OVERRUN DAVAIL Bit Name Description 7 Lab PC PC This bit indicates whether the board is a Lab PC or a Lab PC If this bit is 0 a Lab PC is present If this bit is 1 a Lab PC is present 6 EXTGATAO This bit indicates the status of the external trigger If this bit is set the external trigger signal has been received to trigger a data acquisition operation This bit is cleared by writing to ADCLR Register 5 GATAO This bit indicates the status of the GATE 0 input on the counter timer chip Counter Group A This bit can be used as a busy indicator for data acquisition operations because conversions are enabled as long as GATE 0 is high and Counter AO is programmed appropriately 4 DMATC This bit
129. med count after which GATAO is set low and EXTCONV input is disabled The operation must be serviced by reading the A D FIFO Register every time an A D conversion result becomes available To service the data acquisition perform the following sequence until GATAO bit in the Status Register is set low a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 read the A D FIFO Register to obtain the result DMA or interrupts can also be used to service the data acquisition operation These topics are discussed in the A D Interrupt Programming and Programming DMA Operation sections later in this appendix Two error conditions may occur during a data acquisition operation an overflow error or an overrun error These error conditions are reported through the Status Register and should be checked every time the Status Register is read to check the DAVAIL bit An overflow condition occurs if more than 16 A D conversions have been stored in the A D FIFO without the A D FIFO being read that is the A D FIFO is full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is cleared An overrun condition occurs if a second A D conversion is initiated before the previous conversion
130. minated either by the terminal count signal of Counter Al or by clearing SWTRIG If SWTRIG is cleared the Counter AO is disabled except when the HWTRIG mode is used Setting this bit allows the external EXTTRIG signal to start a data acquisition operation that is controlled by Counter AO and Counter Al If this bit is set a low to high transition on EXTTRIG enables Counter AO and thus starts a data acquisition operation To use this mode the SWTRIG and PRETRIG bits should be cleared This bit is used to set the pretriggering feature on the Lab PC If this bit is set a data acquisition operation is initialized by setting SWTRIG but the Counter A1 the sample counter does not begin decrementing until a rising edge is detected on EXTTRIG To use this mode the HWTRIG bit should be cleared D 10 National Instruments Corporation Appendix D Register Map and Descriptions Command Register 3 The Command Register 3 contains six bits that enable and disable the interrupts and DMA operation Address Base address 02 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 FIFOINTEN ERRINTEN CNTINTEN TCINTEN DIOINTEN DMAEN Bit Name Description 7 6 X Don t care bits 5 FIFOINTEN This bit enables and disables the generation of an interrupt when A D conversion results are available If FIFOINTEN is set an interrupt is generated whenever an A D conversion is available to be read from the FIFO 4 ERRINTEN
131. mum output delay from gate W 400 nsec maximum Figure 3 17 General Purpose Timing Signals National Instruments Corporation 3 27 Lab PC User Manual Signal Connections Chapter 3 The GATE and OUT signals in Figure 3 17 are referenced to the rising edge of the CLK signal Cabling National Instruments currently offers a cable termination accessory the CB 50 for use with the Lab PC board This kit includes a terminated 50 conductor flat ribbon cable and a connector block Signal input and output wires can be attached to screw terminals on the connector block and thereby connected to the Lab PC I O connector The CB 50 is useful for initially prototyping an application or in situations where Lab PC interconnections are frequently changed When you develop a final field wiring scheme however you may want to develop your own cable This section contains information and guidelines for designing custom cables The Lab PC I O connector is a 50 pin male ribbon cable header The manufacturer part numbers used by National Instruments for this header are as follows e Electronic Products Division 3M part number 3596 5002 e T amp B Ansley Corporation part number 609 500 The mating connector for the Lab PC is a 50 position polarized ribbon socket connector with strain relief National Instruments uses a polarized keyed connector to prevent inadvertent upside down connection to the Lab PC Recommended manufacturer part number
132. n and the input polarity to the Analog Configuration Register The SCANEN bit must be clear during this first write to the Analog Configuration Register Immediately write a 0 to the INTSCAN bit in the Command Register 4 The EOIRCV bit should be configured with the desired value These two writes should be performed prior to any other configuration steps 2 Configure the remainder of the data acquisition circuitry as specified in any of the previous outlines 3 After programming the sample interval counter Counter AO or configuring the circuitry to use EXTCONV configure the interval scanning counter Counter B1 if necessary Use the following sequence to program this counter All writes are 8 bit write operations All values given are hexadecimal a Write 74 to the Counter B Mode Register select Mode 2 b Write the least significant byte of the scan interval count to the Counter B1 Data Register c Write the most significant byte of the scan interval count to the Counter B1 Data Register If you intend to use Counter B1 to generate your scan interval pulses remember to connect a source to the CLKB1 line on the I O connector 4 Finally take the Analog Configuration Register bit pattern used in step 1 set the SCANEN bit and write the value to the Analog Configuration Register As soon as this value is written the interval scanning circuitry is gated on A channel scanning cycle will commence immediately following the first
133. n are selected by writing to Command Register 1 The SCANEN bit must be cleared for data acquisition operations on a single channel See the bit description for Command Register earlier in this chapter for gain and analog input channel bit descriptions To select pretrigger mode set the PRETRIG bit and clear the HWTRIG bit in Command Register 2 Lab PC User Manual E 14 National Instruments Corporation Appendix E Register Level Programming 2 Program Counter AO Since a high to low transition on the Counter AO output initiates an A D conversion Counter AO output must be programmed to a high state This ensures that Counter AO does not cause any A D conversions Write 34 hex to the Counter A Mode Register select Counter AO Mode 2 to force OUTO to a high state This is an 8 bit operation 3 Clear the A D circuitry Before the data acquisition operation is started the A D FIFO must be emptied in order to clear any old A D conversion results This emptying must be performed after the counters are programmed in case any spurious edges were caused while programming the counters Write 0 to the A D Clear Register to empty the FIFO 8 bit write and to read from the A D FIFO 8 bit read twice Ignore the data obtained In pretrigger mode a write to the A D Clear Register also sets the GATA1 bit low A D conversions are not counted until GATA1 is set high by a rising edge on the EXTTRIG input 4 Program Counter Al and enable EXTCON
134. n you start up your PC all bits of the Command Registers are cleared Bit descriptions for the registers in the Configuration and Status Register Group are given on the following pages Lab PC User Manual D 4 National Instruments Corporation Appendix D Register Map and Descriptions Command Register 1 Command Register 1 indicates the input channel to be read the gain for the analog input circuitry and the range of the input signal unipolar or bipolar Address Base address 00 hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 SCANEN GAIN2 GAINI GAINO TWOSCMP Bit Name Description 7 SCANEN This bit enables or disables multiple channel scanning during data acquisition If this bit is set analog channels MA lt 2 0 gt through 0 are sampled alternately If this bit is cleared a single analog channel specified by MA lt 2 0 gt is sampled during the entire data acquisition operation See Programming Multiple A D Conversions with Channel Scanning in Appendix E Register Level Programming for the correct sequence involved in setting this bit For example in the RSE or NRSE mode of operation if MA lt 2 0 gt is 011 and SCANEN is set analog input Channels 3 through 0 are sampled alternately during subsequent data conversions If SCANEN is then cleared with MA lt 2 0 gt still set to 011 only analog input Channel 3 is sampled during the subsequent data conversions 6 4 GAIN lt 2 0 gt These thre
135. nary value of 0 for the corresponding address bit Figure 2 2 shows two possible switch settings National Instruments Corporation 2 3 Lab PC User Manual Configuration and Installation Chapter 2 This side down for 0 This side down for 1 A Switches Set to Base I O Address of Hex 000 o Q w LL lt lt lt lt lt This side down for 0 This side down for 1 B Switches Set to Base I O Address of Hex 260 Factory Setting Figure 2 2 Example Base I O Address Switch Settings The five least significant bits of the address A4 through AO are decoded by the Lab PC to select the appropriate Lab PC register To change the base I O address remove the plastic cover on U1 press each switch to the desired position check each switch to make sure the switch is pressed down all the way and replace the plastic cover Record the new Lab PC base I O address in Appendix F Customer Communication for use when configuring the Lab PC software Table 2 2 lists the possible switch settings the corresponding base I O address and the base I O address space used for that setting Lab PC User Manual 2 4 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 2 Switch Settings with Corresponding Base I O Address and Base I O Address Space A9 A8 A7 A6 AS hex Space Used hex 000 O1F 020 03F 040 05F 060 07F 080 09F OAO OBF OCO ODF OEO OFF 100 11F 12
136. natively you can calibrate the input offset at gain 1 and note the offset errors for all other gains You can then apply a software correction to the readings at gains higher than one by subtracting the offset errors With this method you can use the board at all available gain levels without recalibrating the input The maximum offset at the gain amplifier is specified at 0 5 mV The maximum possible contribution of the gain amplifier to the total offset is therefore 0 5 mV multiplied by the gain To find the error in LSBs divide this voltage by the voltage of 1 LSB Hence with a large gain change such as from 1 to 100 the number of LSBs offset from this source changes from about 0 2 to almost 20 Clearly an adjustment that is acceptable for a 0 2 LSB error is probably not suitable when the error is multiplied by 100 For small changes in the gain the error that accompanies changes in gain is much less If the gain is changed from 1 to 2 or 5 the offset probably does not need to be recalibrated Likewise changes between gains of 20 50 or 100 probably do not require recalibration All the stages up to and including the input to the ADC contribute to the gain error of the analog input circuitry With the amplifier set to a gain of 1 the gain of the analog input circuitry is ideally 1 The gain error is the deviation of the gain from and appears as a multiplication of the input voltage being measured To calibrate this offset you must apply
137. nd 2 047 Alternatively you can average a number of readings approximately 100 and adjust trimpot R10 until the average reading is 2 046 5 Unipolar Input Calibration Procedure If your board is configured for unipolar input which has an input range of 0 to 10 V then complete the following steps in sequence This procedure assumes that ADC readings are in the range 0 to 4 095 that is the TWOSADC bit in Command Register is cleared The following should be performed with the input configuration set to RSE 1 Input Offset Calibration To adjust the amplifier input offset a Connect ACHO pin 1 on the I O connector to AISENSE AIGND pin 9 b Take analog input readings from Channel 0 at gains of 1 and 50 c Adjust trimpot R7 until the readings match to within one count at both gain settings 2 Output Offset Calibration To adjust the amplifier output offset a Connect ACHO pin 1 on the I O connector to AISENSE AIGND pin 9 b Take analog input readings from Channel 0 at the gain at which the system will be used c Adjust trimpot R6 until the readings flicker between 0 and 1 Care must be taken to avoid setting the potentiometer too low in the unipolar mode If the potentiometer is set too low the ADC then simply outputs 0 because its input is below the lower limit National Instruments Corporation 5 5 Lab PC User Manual Calibration Chapter 5 3 Gain Calibration Adjust the analog input gain by applying an input v
138. nd DAQPad Series DAQ and SCXI hardware with NI DAQ software for PC compatibles Register Level Programming The final option for programming any National Instruments DAQ hardware is to write register level software Writing register level programming software can be very time consuming and inefficient and is not recommended for most users Even if you are an experienced register level programmer consider using NI DAQ LabVIEW or LabWindows CVI to program your National Instruments DAQ hardware Using the NI DAQ LabVIEW or LabWindows CVI software is as easy and as flexible as register level programming and can save weeks of development time National Instruments Corporation 1 3 Lab PC User Manual Introduction Chapter 1 Optional Equipment National Instruments offers a variety of products to use with your Lab PC board including cables connector blocks and other accessories as follows e Cables and cable assemblies shielded and ribbon e Connector blocks shielded and unshielded 50 68 and 100 pin screw terminals e Real Time System Integration RTSI bus cables e Signal Condition eXtension for Instrumentation SCXI modules and accessories for isolating amplifying exciting and multiplexing signals for relays and analog output With SCXI you can condition and acquire up to 3072 channels e Low channel count signal conditioning modules boards and accessories including conditioning for strain gauges and RTDs simultane
139. nd step 2 are completed the DMA controller automatically reads the FIFO Register whenever an A D conversion result is available and then stores the result in a buffer in memory the data type of the buffer can be 16 bit data A DMATC interrupt can be generated by a Lab PC board To use the DMA terminal count interrupt set the DMAEN and TCINTEN bits in Command Register 3 If these bits are set an interrupt is generated and the DMATC bit in the Status Register is set whenever the DMATC pulse is detected Writing to the DMATC Clear Register clears this interrupt condition Programming the Analog Output Circuitry The analog output circuitry on the Lab PC uses double buffered DACs Thus the voltage at the output pins pins DACO OUT and DAC1 OUT on the Lab PC I O connector does not have to be updated immediately with each write to the DAC Data Registers The analog output can be updated in synchronization with Counter A2 output or the external update control signal EXTUPDATE This ability is useful for waveform generation applications because the timed update pulses eliminate the timing jitter associated with software writes to the DAC Data Registers The voltage at the analog output circuitry pins pins DACO OUT and DACI OUT on the Lab PC I O connector is controlled by loading the DAC in the analog output channel with a 12 bit digital code The DACs can be loaded by writing the digital code to the DACO and DACI Data Registers L and H Writin
140. nel before data acquisition is initiated These gain and multiplexer settings remain constant during the entire data acquisition process therefore all A D conversion data is read from a single channel Multiple Channel Scanned Data Acquisition Multiple channel data acquisition is performed by enabling scanning during data acquisition Multiple channel scanning is controlled by a scan counter For scanning operations the scan counter decrements from the highest numbered channel specified by the user through Channel 0 and then repeats the sequence Thus any number of channels from two to eight can be scanned Notice that the same gain setting is used for all channels in the scan sequence In single channel continuous acquisition mode the Lab PC samples a single channel continuously without delays In scanned continuous acquisition mode the Lab PC scans the selected channels repeatedly without delays and samples them Lab PC User Manual 4 6 National Instruments Corporation Chapter 4 Theory of Operation You must initialize two additional counters to operate in interval acquisition mode In single channel interval acquisition mode the Lab PC samples a single channel a programmable number of times waits for the duration of the scan interval and repeats this cycle In the scanned interval acquisition mode the Lab PC scans the selected samples waits for the duration of the scan interval and repeats the cycle Data Acquisi
141. ntrolled acquisition mode posttrigger mode E 12 to E 13 pretrigger mode E 14 to E 15 freerun acquisition mode posttrigger mode E 16 initiation of A D conversions E 12 overview E 11 posttrigger data acquisition timing figure 3 22 external timing for multiple A D conversions See multiple A D conversions programming EXTGATAO bit D 7 EXTTRIG signal data acquisition timing 3 21 to 3 23 description table 3 3 external timing for multiple A D conversions E 12 controlled acquisition mode posttrigger mode E 12 to E 13 pretrigger mode E 14 to E 15 initiation posttrigger mode E 11 overview E 11 termination pretrigger mode E 11 posttrigger data acquisition timing figure 3 22 Lab PC User Manual Index EXTUPDATE signal analog output circuitry programming E 20 to E 21 data acquisition timing 3 23 to 3 24 generating interrupts figure 3 24 updating DAC output figure 3 24 description table 3 3 interrupt programming for analog output circuitry E 22 to E 23 F fax technical support F 1 FIFOINTEN bit A D interrupt programming E 19 description D 11 floating signal sources definition 3 5 to 3 6 signal connection considerations differential connections 3 8 to 3 9 recommended configurations table 3 6 single ended connections 3 10 to 3 11 freerun acquisition mode multiple A D conversions overview E 5 programming steps E 8 to E 10 frequency measurement 3 26 application figure 3 26 fus
142. nts Corporation Index 13 Index illustration 3 15 Mode input timing 3 18 Mode 1 output timing 3 19 Mode 2 bidirectional timing 3 20 Port C pin connections 3 15 to 3 16 timing specifications 3 16 to 3 17 input configurations 3 6 to 3 28 common mode signal rejection considerations 3 12 differential connection considerations 3 6 to 3 9 floating signal sources 3 8 to 3 9 ground referenced signal sources 3 7 to 3 8 recommended configurations for ground referenced and floating signal sources table 3 6 single ended connection considerations 3 10 to 3 12 floating signal sources RSE configuration 3 10 to 3 11 grounded signal sources NRSE configuration 3 11 to 3 12 VO connector pin assignments figure 3 2 VO connector signal connection descriptions table 3 3 timing connections 3 21 to 3 28 data acquisition timing connections 3 21 to 3 24 general purpose timing connections 3 24 to 3 28 types of signal sources 3 5 to 3 6 floating signal sources 3 5 to 3 6 ground referenced signal sources 3 6 signal sources See floating signal sources ground referenced signal sources single bit set reset control words Mode 2 operation E 33 single bit set reset feature Mode 2 operation E 34 single channel data acquisition 4 6 single channel interval acquisition mode for multiple A D conversions E 18 to E 19 single channel interval timing figure 4 14 single ended connection considerations 3 10 to 3 12 crit
143. nual Signal Connections Chapter 3 the measured input signal varies or appears to float An instrument or device that provides an isolated output falls into the floating signal source category Ground Referenced Signal Sources A ground referenced signal source is one that is connected in some way to the building system ground and is therefore already connected to a common ground point with respect to the Lab PC assuming that the PC is plugged into the same power system Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between 1 mV and 100 mV but can be much higher if power distribution circuits are not properly connected The connection instructions that follow for grounded signal sources are designed to eliminate this ground potential difference from the measured signal Input Configurations The Lab PC can be configured for one of three input modes NRSE RSE or DIFF The following sections discuss the use of single ended and differential measurements and considerations for measuring both floating and ground referenced signal sources Table 3 1 summarizes the recommended input configurations for both types of signal sources Table 3 1 Recommended Input Configurations for Ground Referenced and Floating Signal Sources Type of Signal Recommended Input Config
144. oat within the common mode limits of the input instrumentation amplifier Differential Connections for Grounded Signal Sources Figure 3 3 shows how to connect a ground referenced signal source to a Lab PC board configured for DIFF input Configuration instructions are included under Analog Input Configuration in Chapter 2 Configuration and Installation National Instruments Corporation 3 7 Lab PC User Manual Signal Connections Chapter 3 Grounded Signal Source Measured Common Vliage Mode o Noise Ground Potential and so on 9 AISENSE AIGND not connected 1 O Connector Lab PC Board in DIFF Configuration Figure 3 3 Differential Input Connections for Grounded Signal Sources With this type of connection the instrumentation amplifier rejects both the common mode noise in the signal and the ground potential difference between the signal source and the Lab PC ground shown as Vem in Figure 3 3 Differential Connections for Floating Signal Sources Figure 3 4 shows how to connect a floating signal source to a Lab PC board configured for DIFF input Configuration instructions are included under Analog Input Configuration in Chapter 2 Configuration and Installation Lab PC User Manual 3 8 National Instruments Corporation Chapter 3 Signal Connections Floating Signal Measured m Voltage 100 kQ e Bias Current Return Paths T O Connector Lab PC Board in DIFF Configuration
145. of three ways depending on the setting of the LDAC bit If this bit is cleared the DAC output voltage is updated as soon as the corresponding DAC Data Register is written to If the LDAC bit is set the DAC output voltage does not change until a falling edge is detected either from Counter A2 or from EXTUPDATE National Instruments Corporation 4 9 Lab PC User Manual Theory of Operation Chapter 4 Each DAC channel can be jumper programmed for either a unipolar voltage output or a bipolar voltage output range A unipolar output gives an output voltage range of 0 0000 V to 9 9976 V A bipolar output gives an output voltage range of 5 0000 V to 4 9976 V For unipolar output 0 0000 V output corresponds to a digital code word of 0 For bipolar output 5 0000 V output corresponds to a digital code word of F800 hex One LSB is the voltage increment corresponding to a LSB change in the digital code word For both unipolar and bipolar output one LSB corresponds to 10 V 4 096 Digital I O Circuitry The digital I O circuitry is designed around an 8255A integrated circuit Figure 4 5 shows a block diagram of the digital I O circuitry The 8255A is a general purpose PPI containing 24 programmable I O pins These pins represent the three 8 bit I O ports A B and C of the 8255A as well as PA lt 0 7 gt PB lt 0 7 gt and PC lt 0 7 gt on the Lab PC I O connector The 8255A also has a control register to configure each of the three I O
146. oltage across ACHO and AISENSE AIGND This input voltage is 9 99634 V or Vi 1 5 LSB a Connect the calibration voltage 9 99634 V across ACHO pin 1 on the I O connector and AISENSE AIGND pin 9 b Take analog input readings from Channel 0 at a gain of 1 and adjust trimpot RS until the ADC readings flicker evenly between 4 094 and 4 095 Alternately you can average a number of readings approximately 100 and adjust trimpot R10 until the average reading is 4 094 5 Analog Output Calibration To null out error sources that affect the accuracy of the output voltages generated you must calibrate the analog output circuitry by adjusting the following potential sources of error e Analog output offset error e Analog output gain error Offset error in the analog output circuitry is the total of the voltage offsets contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated and is independent of the D A setting To correct this offset gain error set the D A to negative full scale and adjust a trimpot until the output voltage is the negative full scale value 0 5 LSB Gain error in the analog output circuitry is the product of the gains contributed by each component in the circuitry This error appears as a voltage difference between the desired voltage and the actual output voltage generated which depends on the D A setting This gain e
147. on D 8 programming analog input circuitry E 3 to E 4 DGND signal table 3 3 DIFF input four channels configuration 2 11 to 2 12 definition table 2 11 signal connection considerations ground referenced signal sources 3 7 to 3 8 nonreferenced or floating signal sources 3 8 to 3 9 recommended configurations table 3 6 differential nonlinearity analog input A 3 analog output A 4 Digital Control Register D 37 digital I O circuitry block diagram 4 10 theory of operation 4 10 to 4 11 digital I O circuitry programming E 23 to E 24 control word format control word flag set to 0 figure E 24 control word flag set to 1 figure E 24 interrupt programming E 34 Mode 0 operation E 25 to E 26 control words E 25 to E 26 programming examples E 26 Mode 1 input E 27 to E 28 control words E 27 Port C pin assignments E 28 Port C status word bit definitions E 28 programming example E 29 National Instruments Corporation Mode output E 29 to E 31 control words E 29 Port C pin assignments E 30 Port C status word bit definitions E 30 programming example E 30 Mode 2 operation E 31 to E 34 control words E 31 to E 32 Port C pin assignments E 33 Port C status word bit definitions E 32 programming example E 33 single bit set reset control words E 33 single bit set reset feature E 34 Digital I O Register Group See 8255A Digital T O Register Group digital I O signal connections 3 13 to 3 20 illustration
148. operating in Mode 1 or Mode 2 Interrupt Programming for the Digital I O Circuitry Interrupts can be enabled on PCO PC3 or both PCO and PC3 by setting the DIOINTEN bit in Command Register 3 See the Command Register 3 description earlier in this chapter for corresponding bit positions An external signal can be used to generate an interrupt when Port A or B is in Mode 0 Program PCO or PC3 for input and connect the external signal that should trigger an interrupt to PCO or PC3 When the external signal becomes logic high an interrupt request occurs To negate the interrupt request the external signal must become logic low Lab PC User Manual E 34 National Instruments Corporation Appendix F Customer Communication For your convenience this appendix contains forms to help you gather the information necessary to help us solve technical problems you might have as well as a form you can use to comment on the product documentation Filling out a copy of the Technical Support Form before contacting National Instruments helps us help you better and faster National Instruments provides comprehensive technical assistance around the world In the U S and Canada applications engineers are available Monday through Friday from 8 00 a m to 6 00 p m central time In other countries contact the nearest branch office You may fax questions to us at any time Corporate Headquarters 512 795 8248 Technical support fax 512 794 5678
149. ort A or Port B is ready to transfer data and an interrupt request is set via PC3 or PCO of 8255A See Appendix C OKI 82C55A Data Sheet for details If DIOINTEN is cleared the interrupts from PC3 or PCO are disabled This bit enables and disables the generation of DMA requests If DMAEN is set a DMA request is generated whenever an A D conversion result is available to be read from the FIFO If DMAEN is cleared no DMA request is generated D 12 National Instruments Corporation Appendix D Register Map and Descriptions Command Register 4 This register allows multiplexing of certain A D conversion logic signals This enables the interval scanning and A D conversion signals to be available at the I O connector and allows the I O connector pins to externally drive these signals Address Base address OF hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 ECLKRCV ECLKDRV EOIRCV INTSCAN Bit Name Description 7 5 X Don t care bits 4 ECLKRCV When cleared this bit enables EXTCONV pulses applied at the EXTCONV pin on the connector to cause conversions when ECLKDRYV is cleared When set ECLKRCV inhibits EXTCONV pulses from causing conversions This bit is cleared on board reset 3 SE D This bit along with jumper W4 selects the analog input mode of the Lab PC When clear it selects the single ended mode In this case multiplexer 1 selects Channels 0 7 specified by the channel select bits and mult
150. ory Setting Bipolar W3 A B e NI DAQ LabVIEW or LabWindows CVI Version Other Products e Microprocessor e Clock Frequency e Computer Make and Model e Type of Video Board Installed e Operating System and Version e Programming Language e Programming Language Version e Other Boards in System e Base I O Address of Other Boards e DMA Channels of Other Boards e Interrupt Level of Other Boards Documentation Comment Form National Instruments encourages you to comment on the documentation supplied with our products This information helps us provide quality products to meet your needs Title Lab PC User Manual Edition Date June 1996 Part Number 320502B 01 Please comment on the completeness clarity and organization of the manual If you find errors in the manual please record the page numbers and describe the errors Thank you for your help Name Title Company Address Phone Mail to Technical Publications Fax to Technical Publications National Instruments Corporation National Instruments Corporation 6504 Bridge Point Parkway MS 53 02 512 794 5678 Austin TX 78730 5039 Glossary k degrees Q ohms percent A amperes A D analog to digital AC alternating current ADC A D converter AWG American Wire Gauge BCD binary coded decimal C Celsius CMOS complementary metallic oxide
151. ot configured for Mode 1 E 32 National Instruments Corporation Appendix E Register Level Programming At the digital I O connector Port C has the following pin assignments when in Mode 2 Programming Example Example Configure Port A in Mode 2 e Write CO hex to the Digital Control Register e Wait for bit 7 of Port C OBFA to be cleared indicating that the data last written to Port A has been read e Write new data to Port A e Wait for bit 5 of Port C BFA to be set indicating that data is available in Port A to be read e Read data from Port A Single Bit Set Reset Control Words Table E 6 shows the control words for setting or resetting each bit in Port C Notice that bit 7 of the control word is cleared for programming the set reset option for the bits of Port C Oxxx0001 Oxxx0011 Oxxx0101 Oxxx0111 Oxxx1001 Oxxx1011 Oxxx1101 Oxxx1111 National Instruments Corporation Oxxx0000 Oxxx0010 Oxxx0100 Oxxx0110 Oxxx1000 Oxxx1010 Oxxx1100 Oxxx1110 Table E 6 Port C Set Reset Control Words Bit Set Bit Reset The Bit Set or Control Word Control Word Reset in Port C XXXXXXXN XXXXXXNX XXXXXNXX XXXXNXXX XXXNXXXX XXNXXXXX XNXXXXXX NXXXXXXX Lab PC User Manual Register Level Programming Appendix E Single Bit Set Reset Feature Any of the 8 bits of Port C can be set or reset with one control word This feature is used to generate status and control for Port A and Port B when
152. otes text or characters that you should literally enter from the keyboard sections of code programming examples and syntax examples This font also is used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions and for statements and comments taken from program code NI DAQ refers to the NI DAQ software for PC compatibles unless otherwise noted Paths are denoted using backslashes to separate drive names directories folders and files Square brackets enclose optional items for example response The Glossary lists abbreviations acronyms metric prefixes mnemonics symbols and terms Lab PC User Manual xii National Instruments Corporation About this Manual National Instruments Documentation The Lab PC User Manual is one piece of the documentation set for your DAQ system You could have any of several types of manuals depending on the hardware and software in your system Use the manuals you have as follows Getting Started with SCXI TIf you are using SCX this is the first manual you should read It gives an overview of the SCXI system and contains the most commonly needed information for the modules chassis and software Your SCXI hardware user manuals If you are using SCXI read these manuals next for detailed information about signal connections and module configuration They also explain
153. ous sample and hold and relays For more specific information about these products refer to your National Instruments catalogue or call the office nearest you Unpacking Your Lab PC board is shipped in an antistatic package to prevent electrostatic damage to the board Electrostatic discharge can damage several components on the board To avoid such damage in handling the board take the following precautions e Ground yourself via a grounding strap or by holding a grounded object e Touch the antistatic package to a metal part of your computer chassis before removing the board from the package e Remove the board from the package and inspect the board for loose components or any other sign of damage Notify National Instruments if the board appears damaged in any way Do not install a damaged board into your computer Lab PC User Manual 1 4 National Instruments Corporation Chapter 2 Configuration and Installation This chapter describes the Lab PC jumper configuration and installation of the Lab PC board in your computer Board Configuration The Lab PC contains six jumpers and one DIP switch to configure the PC bus interface and analog I O settings The DIP switch is used to set the base I O address Two jumpers are used as interrupt channel and DMA selectors The remaining four jumpers are used to change the analog input and analog output circuitry The parts locator diagram in Figure 2 1 shows the Lab PC jumper setting
154. plicable no bits used Note A D conversions can be initiated in one of two ways by writing to the Start Convert Register or by detecting an active low signal on either the Counter AO output or the EXTCONV signal If the Start Convert Register is to initiate an A D conversion the Counter AO output should be initialized to high state which must be followed by an ADCLEAR operation by writing to the ADCLEAR Register National Instruments Corporation D 19 Lab PC User Manual Register Map and Descriptions Appendix D DMATC Interrupt Clear Register Writing to the DMA Terminal Count DMATC Clear Register clears the interrupt request asserted when a DMA terminal count pulse is detected Address Base address OA hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Lab PC User Manual D 20 National Instruments Corporation Appendix D Register Map and Descriptions Analog Output Register Group The four registers making up the Analog Output Register Group are used for loading the two 12 bit DACs in the two analog output channels DACO controls analog output Channel 0 DAC controls analog output Channel 1 These DACs should be written to individually Bit descriptions of the registers making up the Analog Output Register Group are given on the following pages National Instruments Corporation D 21 Lab PC User Manual Register Map and Descriptions Appendix D DAC0 Low Byte DACOL DACO High Byte
155. pm max 5 V or 0 to 10 V jumper selectable DC 0 2 Q max 2 mA max Short to AGND 0 V for 5 V range 5 V for 0 to 10 V range 5 us 10 V us 30 uV C 10 ppm C Explanation of Analog Output Specifications Relative accuracy in a D A system is the same as nonlinearity because no uncertainty is added due to code width Unlike an ADC every digital code in a D A system represents a specific analog value rather than a range of values The relative accuracy of the system is therefore limited to the worst case deviation from the ideal correspondence a straight line excepting noise If a D A system has been calibrated perfectly then the relative accuracy specification reflects its worst case absolute error Lab PC User Manual A 4 National Instruments Corporation Appendix A Specifications Differential nonlinearity DNL in a D A system is a measure of deviation of code width from 1 LSB In this case code width is the difference between the analog values produced by consecutive digital codes A specification of 1 LSB differential nonlinearity ensures that the code width is always greater than 0 LSBs guaranteeing monotonicity and is always less than 2 LSBs Digital O Number of channels ccccceeeececeeccceeeeee eee 24 Compatibility s scccssdescsacasvsecacvendccacsnoadensedeseens Digital logic levels Input low voltage Input high voltage Input low current Vin 0 8 V Input high current
156. ports on the chip These ports can be programmed as two groups of 12 signals or as three individual 8 bit ports In addition the board can be programmed in one of the three modes of operation basic I O strobed I O or bidirectional bus The programming of the digital I O circuitry is covered in Appendix E Register Level Programming PA lt 0 7 gt PB lt 0 7 gt DATA lt 0 7 gt 8255A PC lt 0 7 gt Programmable DIO RD WR Peripheral Interface 3 El Ss Q T O Connector To Interrupt Control Figure 4 5 Digital I O Circuitry Block Diagram Lab PC User Manual 4 10 National Instruments Corporation Chapter 4 Theory of Operation All three ports on the 8255A are TTL compatible When enabled the digital output ports are capable of sinking 2 4 mA of current and sourcing 2 6 mA of current on each digital I O line When the ports are not enabled the digital I O lines act as high impedance inputs Timing I O Circuitry The Lab PC uses two 8253 Counter Timer integrated circuits for data acquisition timing and for general purpose timing I O functions One of these is used internally for data acquisition timing and the other is available for general use Figure 4 6 shows a block diagram of both groups of timing I O circuitry counter groups A and B National Instruments Corporation 4 11 Lab PC User Manual Theory of Operation Chapter 4 GATEB2 GATEB2 CLKB2 CLKB2 OUTB2 GATEB 1 GATEB 1 CL
157. propriate interrupt enable signals must be set to generate this signal Read signal This signal is the read signal generated from the control lines of the PC I O channel Write signal This signal is the write signal generated from the control lines of the PC I O channel Data lines at the specified port This signal indicates when the data on the data lines at a specified port is or should be available National Instruments Corporation 3 17 Lab PC User Manual Signal Connections Chapter 3 Mode 1 Input Timing The timing specifications for an input transfer in Mode 1 are as follows Name Description Minimum Maximum T1 STB pulse width 500 T2 STB 0 to IBF 1 300 T3 Data before STB 1 0 T4 STB 1 to INTR 1 300 T5 Data after STB 1 180 T6 RD 0 to INTR 0 400 T7 RD 1 to IBF 0 300 All timing values are in nanoseconds Lab PC User Manual 3 18 National Instruments Corporation Chapter 3 Signal Connections Mode 1 Output Timing The timing specifications for an output transfer in Mode 1 are as follows Name Description Minimum Maximum Tl WR 0 to INTR 0 450 T2 WR 1 to output 350 T3 WR 1 to OBF 0 650 T4 ACK 0 to OBF 1 350 T5 ACK pulse width 300 T6 ACK 1 to INTR 1 350 All timing values are in nanoseconds National Instruments Corporation 3 19 Lab PC User Manual Signal Connections Chapter 3 Mode 2 Bidirectiona
158. r is used for loading and reading back contents of 8253 A Counter 1 Address Base address 15 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Dv w ps as B vR Mm DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter Al contents National Instruments Corporation D 25 Lab PC User Manual Register Map and Descriptions Appendix D Counter A2 Data Register The Counter A2 Data Register is used for loading and reading back contents of 8253 A Counter A2 Address Base address 16 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Dv w ps as B vR Mm DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter A2 contents Lab PC User Manual D 26 National Instruments Corporation Appendix D Register Map and Descriptions Counter A Mode Register The Counter A Mode Register determines the operation mode for each of the three counters on the 8253 A chip The Counter A Mode Register selects the counter involved its read load mode its operation mode that is any of the 8253 s six operation modes and the counting mode binary or BCD counting The Counter A Mode Register is an 8 bit register Bit descriptions for each of these bits are given in Appendix B OKI 82C53 Data Sheet Address Base address 17 hex Type Write only Word Size 8 bit Bit Map 6 5 0 7 4 3 2 1 National Instruments Corporation D 27 Lab PC User Manual
159. rd in your computer Chapter 3 Signal Connections describes how to make input and output signal connections to your Lab PC board via the board I O connector Chapter 4 Theory of Operation contains a functional overview of the Lab PC and explains the operation of each functional unit making up the Lab PC This chapter also explains the basic operation of the Lab PC circuitry Chapter 5 Calibration discusses the calibration procedures for the Lab PC analog input and analog output circuitry Appendix A Specifications lists the specifications of the Lab PC Appendix B OKI 82C53 Data Sheet contains the manufacturer data sheet for the OKI 82C53 System Timing Controller integrated circuit OKI Semiconductor This circuit is used on the Lab PC Appendix C OKI 82C55A Data Sheet contains the manufacturer data sheet for the OKI 82C55A Programmable Peripheral Interface integrated circuit OKI Semiconductor This circuit is used on the Lab PC Appendix D Register Map and Descriptions describes in detail the address and function of each of the Lab PC registers Appendix E Register Level Programming contains important information about programming the Lab PC Appendix F Customer Communication contains forms you can use to request help from National Instruments or to comment on our products and manuals National Instruments Corporation xi Lab PC User Manual About This Manual e The Glossary contains an alphabetic
160. re already referenced to some ground point with respect to the Lab PC In these cases the instrumentation amplifier can reject any voltage due to ground potential differences between the signal source and the Lab PC In addition with differential input connections the instrumentation amplifier can reject common mode noise pickup in the leads connecting the signal sources to the Lab PC The common mode input range of the Lab PC instrumentation amplifier is defined as the magnitude of the greatest common mode signal that can be rejected The common mode input range for the Lab PC depends on the size of the differential input signal Var VF V in and the gain setting of the instrumentation amplifier In unipolar mode the differential input range is 0 to 10 V In bipolar mode the differential input range is 5 to 5 V Inputs should remain within a range of 5 to 10 V in both bipolar and unipolar modes Analog Output Signal Connections Pins 10 through 12 of the I O connector are analog output signal pins Pins 10 and 12 are the DACO OUT and DAC1 OUT signal pins DACO OUT is the voltage output signal for Analog Output Channel 0 DAC1 OUT is the voltage output signal for Analog Output Channel 1 Lab PC User Manual 3 12 National Instruments Corporation Chapter 3 Signal Connections Pin 11 AGND is the ground reference point for both analog output channels as well as analog input The following output ranges are available O
161. reflects the status of the DMA terminal count If this bit is set and if the TCINTEN bit is set in Command Register 3 then the current interrupt is due to the detection of a DMA terminal counter pulse This bit is cleared by writing to the DMATC Interrupt Clear Register 3 CNTINT This bit reflects the status of the interrupt caused by Counter A2 output or the EXTUPDATE signal If the CNTINTEN bit in Command Register 3 is set a low to high transition on Counter A2 output or on EXTUPDATE sets this bit and generates an interrupt request This bit is cleared by writing to the CNTINTCLR Register 2 OVERFLOW This bit indicates if an overflow error has occurred If this bit is cleared no error was encountered If this bit is set the A D FIFO has overflowed because the data acquisition servicing operation could not keep up with the sampling rate National Instruments Corporation D 7 Lab PC User Manual Register Map and Descriptions Bit Name 1 OVERRUN 0 DAVAIL Lab PC User Manual Appendix D Description continued This bit indicates if an overrun error has occurred If this bit is cleared no error occurred This bit is set if a convert command is issued to the ADC while the last conversion is still in progress This bit indicates whether conversion output is available If this bit is set the ADC is finished with the last conversion and the result can be read from the FIFO This bit is cleared if the FIFO is empty After writin
162. rogramming External Timing Considerations for Multiple A D Conversions Two external timing signals EXTTRIG and EXTCONV can be used for multiple A D conversions EXTTRIG can be used to initiate a conversion sequence posttrigger mode or to terminate an ongoing conversion sequence pretrigger mode and the EXTCONV signal can be used to time the individual A D conversions from an external timing source Chapter 3 Signal Connections contains the EXTTRIG and EXTCONV signal specifications The posttrigger and pretrigger modes are described later in this appendix EXTCONV is available on the 50 pin I O connector to allow conversion to be controlled by an external source A conversion occurs whenever an active low pulse the pulse width is 250 ns minimum is detected on this TTL level line EXTCONV can be used for both single channel conversion sequences and multiple channel scanning sequences The programming steps are similar to internal timing conversions except that Counter AO is not used and its output should be high and OUT 1 of Counter Al must be forced low After setting the SWTRIG bit the first EXTCONV pulse starts the external conversion operation but does not cause the A D conversion the second pulse starts the first A D conversion Using the EXTTRIG Signal to Initiate a Multiple A D Conversion Data Acquisition Operation Posttrigger Mode If both the PRETRIG bit and the SWTRIG bit are cleared and the HWTRIG bit is set in Comm
163. rolled acquisition mode E 7 posttrigger mode E 13 pretrigger mode E 15 freerun acquisition mode E 10 description D 16 to D 17 output binary modes E 4 reading E 3 analog input circuitry programming E 3 controlled data acquisition programming E 8 freerun data acquisition programming E 10 theory of operation 4 5 voltage versus A D conversion values table bipolar input mode E 4 unipolar input mode E 4 A D interrupt programming E 19 to E 20 AGND signal table 3 3 AISENSE AIGND signal table 3 3 Analog Configuration Register E 18 analog input calibration 5 3 to 5 6 bipolar input procedure 5 4 to 5 5 Lab PC User Manual Index 2 board configuration 5 4 unipolar input procedure 5 5 to 5 6 voltage values of ADC input figure 5 4 analog input circuitry block diagram 4 4 theory of operation 4 5 analog input circuitry programming A D FIFO output binary modes E 4 clearing analog input circuitry E 5 programming sequence E 3 to E 4 voltage versus A D conversion values table bipolar input mode E 4 unipolar input mode E 4 analog input configuration DIFF input four channels 2 11 to 2 12 input mode 2 10 to 2 11 input polarity and range 2 13 to 2 14 jumper settings table 2 9 NRSE input eight channels 2 13 RSE input eight channels 2 12 Analog Input Register Group D 15 to D 20 A D Clear Register D 18 A D FIFO Register clearing analog input circuitry programming E 5 controlled acquisition mod
164. rror is corrected by setting the D A to positive full scale and adjusting a trimpot until the output voltage corresponds to the positive full scale value 0 5 LSB Board Configuration The calibration procedure differs if you select either bipolar or unipolar output configuration A procedure for each configuration is given next Bipolar Output Calibration Procedure If your board is configured for bipolar output which provides an output range of 5 to 5 V then complete the following procedures in the order given Lab PC User Manual 5 6 National Instruments Corporation Chapter 5 Calibration 1 Adjust the Analog Output Offset Adjust the analog output offset by measuring the output voltage generated with the DAC set at negative full scale 0 This output voltage should be V_s 0 5 LSB For bipolar output V_fs 5 V and 0 5 LSB 1 22 mV For analog output Channel 0 a Connect the voltmeter between DACO OUT pin 10 on the I O connector and AGND pin 11 b Set the analog output channel to 5 V by writing 2 048 to the DAC c Adjust trimpot R2 until the output voltage read is 5 V For analog output Channel 1 a Connect the voltmeter between DACI OUT pin 12 on the I O connector and AGND pin 11 b Set the analog output channel to 5 V by writing 2 048 to the DAC c Adjust trimpot R4 until the output voltage read is 5 V 2 Adjust the Analog Output Gain Adjust the analog output gain by measuring the outpu
165. ry Name Company Address Fax Phone Computer brand Model Processor Operating system include version number Clock Speed MHz RAM MB Display adapter Mouse yes no Other adapters installed Hard disk capacity MB Brand Instruments used National Instruments hardware product model Revision Configuration National Instruments software product Version Configuration The problem is List any error messages The following steps will reproduce the problem Lab PC Hardware and Software Configuration Form Record the settings and revisions of your hardware and software on the line to the right of each item Complete a new copy of this form each time you revise your software or hardware configuration and use this form as a reference for your current configuration Completing this form accurately before contacting National Instruments for technical support helps our applications engineers answer your questions more efficiently National Instruments Products e Base I O Address of Lab PC Factory Setting Hex 260 e DMA Channel of Lab PC Factory Setting 3 e Interrupt Level of Lab PC Factory Setting IRQS e Analog Output Channel 0 Configuration Factory Setting Bipolar W1 A B e Analog Output Channel 1 Configuration Factory Setting Bipolar W2 A B e Analog Input Configuration Fact
166. s Jumpers W3 and W4 configure the analog input circuitry Jumpers W1 and W2 configure the analog output circuitry Jumpers W6 and W5 select the DMA channel and the interrupt level respectively PC Bus Interface The Lab PC is configured at the factory to a base I O address of hex 260 to use DMA Channel 3 and to use interrupt level 5 These settings shown in Table 2 1 are suitable for most systems If your system however has other hardware at this base I O address DMA channel or interrupt level you will need to change these settings on the other hardware or on the Lab PC as described in the following pages Record your settings in the Lab PC Hardware and Software Configuration Form in Appendix F National Instruments Corporation 2 1 Lab PC User Manual Configuration and Installation Chapter 2 O 00000 O C 0 0C1 5 SWITCH oooo0o0 a ocoooa u4 HLY 0000000 Pa o li cs co Grgo 00 i HO oR1e ae 00000000000009 00000000000000 Ruse Los d vLLISOY 1 ni cle ove Emma ooosooocooocog EE2 o000000g T89va 00000000000000 lo 0000000000 0000000000 Il CS en fe 4 copyRIGHT 1998 0000000000 YS faot 40
167. s Appendix D Interval Counter Register Group The 8 bit Interval Counter is used only in the single channel interval mode SCANEN 0 and INTSCAN 1 and consists of two 8 bit registers the Interval Counter Data Register and the Interval Counter Strobe Register The Interval Counter Data Register is loaded with the count Writing to the Interval Counter Strobe Register loads this count into the Interval Counter The Interval Counter decrements with each conversion When the count reaches 0 the Interval Counter autoinitializes restoring the original count value Bit descriptions for the registers in the Interval Counter Register Group are given on the following pages Lab PC User Manual D 38 National Instruments Corporation Appendix D Register Map and Descriptions Interval Counter Data Register The Interval Counter Data Register is loaded with the desired number of samples of a single channel that will be acquired between intervals See Programming Multiple A D Conversions in Single Channel Interval Acquisition Mode in Appendix E Register Level Programming for a description of the programming sequence Address Base address 1E hex Type Write only Word Size 8 bit Bit Map 7 6 3 4 3 2 1 0 v w DS mwm wB v m DO Bit Name Description 7 0 D lt 7 0 gt Interval Counter count National Instruments Corporation D 39 Lab PC User Manual Register Map and Descriptions Appendix D Interval Counter Strobe Regi
168. s for this mating connector are as follows e Electronic Products Division 3M part number 3425 7650 e T amp B Ansley Corporation part number 609 5041CE The following are the standard ribbon cables 50 conductor 28 AWG stranded that can be used with these connectors e Electronic Products Division 3M part number 3365 50 e T amp B Ansley Corporation part number 171 50 Lab PC User Manual 3 28 National Instruments Corporation Chapter 4 Theory of Operation This chapter contains a functional overview of the Lab PC and explains the operation of each functional unit making up the Lab PC This chapter also explains the basic operation of the Lab PC circuitry Functional Overview The block diagram in Figure 4 1 shows a functional overview of the Lab PC board Data Address Channel Interface ro 1 Control Signals 8253 8255A Ctr Timer Digital Group A Interface Timebase 10 MHz Oscillator 2 MHz Timebase i S Q Q S m vo S Aa a 9 3 a PC I O Channel Ctr Timer Group B Figure 4 1 Lab PC Block Diagram National Instruments Corporation 4 1 Lab PC User Manual Theory of Operation Chapter 4 The following are the major components making up the Lab PC board e PC I O channel interface circuitry e Analog input and data acquisition circuitry e Analog output circuitry e Digital I O circuitry e Timing I O circuitry Data acquisition functions can be e
169. s full and cannot accept any more data This condition occurs if the software loop reading the A D FIFO Register is not fast enough to keep up with the A D conversion rate When an overflow occurs at least one A D conversion result is lost An overflow condition has occurred if the OVERFLOW bit in the Status Register is cleared An overrun condition occurs if a second A D conversion is initiated before the previous conversion is finished This condition may result in one or more missing A D conversions This condition occurs if the sample interval is too small sample rate is too high An overrun condition has occurred if the OVERRUN bit in the Status Register is low The minimum recommended sampling interval on the Lab PC is 16 us Both the OVERFLOW and OVERRUN bits in the Status Register are reset by writing to the A D Clear Register Pretrigger Mode The following programming steps are required for a data acquisition operation in controlled acquisition mode using EXTCONV In the following programming sequence EXTTRIG is used as a pretrigger signal that is A D conversions are enabled but the sample count is not started until a rising edge is detected on the EXTTRIG input Data acquisition remains enabled for the programmed count after the rising edge on the EXTTRIG input Thus data can be acquired before and after the trigger EXTTRIG 1 Select analog input channel and gain and select pretrigger mode The analog input channel and gai
170. se Rs te ence wis NS TN 4 14 Figure 5 1 Calibration Trimpot Location Diagram 0 ei eeiceeceeeeeeeneeeeseceeeceeneeeneesaeenes 5 2 Figure E 1 Control Word Format with Control Word Flag Set to 1 E 24 Figure E 2 Control Word Format with Control Word Flag Set to 0 oo ee eeeeeeeeeteeeeneees E 24 Lab PC User Manual vill National Instruments Corporation Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table Table 0 3 2 4 2 5 34 35 4 1 4 2 43 44 5 1 D 1 E 1 E 2 E 3 E 4 E6 Contents Tables PC Bus Interface Factory Settings na nn nes nds 2 3 Switch Settings with Corresponding Base I O Address and Base O Address Spaces ne Le SR A ne 2 5 DMA Channels for the Lab PC 12 0 22cs c ane ee angel 2 6 Analog VO Jumper Settini gsc nec ii En RTS 2 9 Input Configurations Available for the Lab PC sssssesssessseeessseesseesserssessseee 2 11 Recommended Input Configurations for Ground Referenced and Floating Signal Sourc S 005 104 jwcsaswede rset nn net tt ne een Rte 3 6 Port C Srenal ASSINE Senesi occ sic saaseee une en a ae o nae E E ri diie 3 16 Analog Input Settling Time Versus Gain 4 7 Lab PC Maximum Recommended Data Acquisition Rates eeeeeseeeees 4 8 Bipolar Analog Input Signal Range Versus Gain 4 8 Unipolar Analog Input Signal Range Versus Gain 4 8 Voltage Values of
171. sed as a sample interval counter in timed A D conversions Counter 1 on the 8253 A Counter Timer referred to as A1 is used as a sample counter in conjunction with Counter O for data acquisition These counters are not available for general use In addition to counter AO EXTCONV can be used to externally time conversions See Appendix E Register Level Programming for the programming sequence needed to enable this input Figure 3 9 shows the timing requirements for the EXTCONV input An A D conversion is initiated by a falling edge on the EXTCONV EXTCONV tw 250 nsec minimum A D Conversion starts within 125 nsec from this point Figure 3 9 EXTCONV Signal Timing Another external control EXTTRIG is used for either starting a data acquisition sequence or terminating an ongoing data acquisition sequence depending on the settings of the HWTRIG and PRETRIG bits in the Command Registers If HWTRIG is set EXTTRIG serves as an external trigger to start a data acquisition sequence In this mode posttrigger mode the sample interval counter is gated off until a rising edge is sensed on the EXTTRIG line EXTCONV however is enabled on the first rising edge of EXTCONV following the rising edge on the EXTTRIG line Further transitions on the EXTTRIG line have no effect until a new data acquisition sequence is established Figures 3 10 National Instruments Corporation 3 21 Lab PC User Manual Signal Connections Chapter 3 and 3
172. set up by the acquisition software so that data is repeatedly loaded into the same section of memory Although this method does not require an indeterminate amount of memory you can examine only samples acquired during a limited time period before and after the trigger occurs Pretriggering is set up by setting PRETRIG in Command Register 2 PRETRIG supersedes HWTRIG if both bits are set then pretriggering is enabled National Instruments Corporation E 11 Lab PC User Manual Register Level Programming Appendix E Using the EXTCONV Signal to Initiate A D Conversions As mentioned earlier A D conversions can be initiated by a falling edge on either OUTAO or EXTCONV Setting the GATAO bit low disables conversions from both OUTAO and EXTCONV Setting the GATAO bit high enables conversions from both OUTAO and EXTCONV The GATAO bit is set low whenever OUTA 1 is high or SWTRIG in Command Register 1 is cleared If OUTA1 is low GATAO can be set high at any time by either setting the SWTRIG bit or initiating a rising edge on EXTTRIG if the HWTRIG bit in Command Register 1 is set Programming Multiple A D Conversions Using External Timing A data acquisition operation using the external timing signals EXTCONV or EXTTRIG can be in either controlled acquisition mode or freerun acquisition mode In controlled acquisition mode Counter Al shuts off A D conversions after the programmed count expires In freerun acquisition mode A D conversions are
173. signals to the Lab PC are less than 15 ft 3 All input signals share a common reference signal at the source If any of the preceding criteria are not met using DIFF input configuration is recommended You can jumper configure the Lab PC for two different types of single ended connections RSE configuration and NRSE configuration The RSE configuration is used for floating signal sources in this case the Lab PC provides the reference ground point for the external signal The NRSE configuration is used for ground referenced signal sources in this case the external signal supplies its own reference ground point and the Lab PC should not supply one Single Ended Connections for Floating Signal Sources RSE Configuration Figure 3 5 shows how to connect a floating signal source to a Lab PC board configured for single ended input The Lab PC analog input circuitry must be configured for RSE input to make these types of connections Configuration instructions are included under Analog Input Configuration in Chapter 2 Configuration and Installation Lab PC User Manual 3 10 National Instruments Corporation Chapter 3 Signal Connections Floating Signal Source Measured Voltage I O Connector Lab PC Board in RSE Configuration Figure 3 5 Single Ended Input Connections for Floating Signal Sources Single Ended Connections for Grounded Signal Sources NRSE Configuration If a grounded signal source is to be measured
174. sion result A D conversion results are obtained by reading the A D FIFO Register Before you read the A D FIFO however you must read the Status Register to determine whether the A D FIFO contains any results To read the A D conversion results complete these steps a Read the Status Register 8 bit read b Ifthe DAVAIL bit is set bit 0 then read the A D FIFO Register twice to obtain the result The first reading returns the low byte of 16 bit data and the second reading returns the high byte Reading the A D FIFO Register removes the A D conversion result from the A D FIFO The binary modes of the A D FIFO output are explained in the next section A D FIFO Output Binary Modes National Instruments Corporation E 3 Lab PC User Manual Register Level Programming Appendix E The DAVAIL bit indicates whether one or more A D conversion results are stored in the A D FIFO If the DAVAIL bit is cleared the A D FIFO is empty and reading the A D FIFO Register returns meaningless data Once an A D conversion is initiated the DAVAIL bit should be set after 12 us or after a rising edge on OUTAO whichever occurs later If EXTCONV is being used for A D timing the DAVAIL bit should be set after 12 us or after a rising edge in EXTCONV whichever occurs later An A D FIFO overflow condition occurs if more than 16 conversions are initiated and stored in the A D FIFO before the A D FIFO Register is read If this condition occurs the OVERFL
175. solid state relays for reading the status of external digital logic and for generating interrupts The counter timers can be used to synchronize events generate pulses and measure frequency and time The Lab PC used in conjunction with the PC is a versatile cost effective platform for laboratory test measurement and control Detailed specifications of the Lab PC are in Appendix A Specifications What You Need to Get Started To set up and use your Lab PC board you will need the following LJ Lab PC board Ly Lab PC User Manual Ly One of the following software packages and documentation NI DAQ for PC compatibles LabVIEW LabWindows CVI Ly Your computer National Instruments Corporation 1 1 Lab PC User Manual Introduction Chapter 1 Software Programming Choices There are several options to choose from when programming your National Instruments DAQ and SCXI hardware You can use LabVIEW LabWindows CVI NI DAQ or register level programming LabVIEW and LabWindows CVI Application Software LabVIEW and LabWindows CVI are innovative program development software packages for data acquisition and control applications LabVIEW uses graphical programming whereas LabWindows CVI enhances traditional programming languages Both packages include extensive libraries for data acquisition instrument control data analysis and graphical data presentation LabVIEW features interactive graphics a state of the art user interface
176. status word bit definitions Mode 1 input E 28 Mode 1 output E 30 Mode 2 operation E 32 posttrigger data acquisition timing figure 3 22 posttrigger mode controlled acquisition mode programming E 12 to E 14 freerun acquisition mode programming E 16 initiation of multiple A D conversions using EXTTRIG signal E 11 power requirement specifications A 6 Lab PC User Manual Index PRETRIG bit controlled acquisition mode posttrigger mode E 12 pretrigger mode E 14 data acquisition timing 3 21 description D 10 multiple A D conversions using EXTTRIG signal E 11 pretrigger data acquisition timing figure 3 23 pretrigger mode controlled acquisition mode programming E 14 to E 16 freerun acquisition mode programming E 17 termination of multiple A D conversions using EXTTRIG signal E 11 programmable gain amplifier 4 5 programming A D interrupt programming E 19 to E 20 analog input circuitry A D FIFO output binary modes E 4 clearing analog circuitry E 5 input voltage versus A D conversion values table bipolar input mode E 4 unipolar input mode E 4 programming sequence E 3 to E 4 analog output circuitry E 20 to E 22 digital I O circuitry E 23 to E 24 control word format control word flag set to 0 figure E 24 control word flag set to 1 figure E 24 Mode 0 operation E 25 to E 26 control words E 25 to E 26 programming examples E 26 Mode 1 input E 27 to E 28 control words E 27 Port C pin assignments
177. ster Writing to Interval Counter Strobe Register strobes the contents of the Interval Counter Data Register into the Interval Counter This action arms the Interval Counter which then decrements with each conversion pulse Address Base address 1F hex Type Write only Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 A OSS Oh 0 E Bit Name Description 7 1 0 Each of these bits must be 0 for proper operation of the Lab PC 0 1 This bit must be 1 for proper operation of the Lab PC Lab PC User Manual D 40 National Instruments Corporation Appendix E Register Level Programming This appendix contains important information about programming the Lab PC Programming the Lab PC involves writing to and reading from the various registers on the board The programming instructions included here list the sequence of steps to take The instructions are language independent that is they tell you to write a value to a given register to set or clear a bit in a given register or to detect whether a given bit is set or cleared without presenting the actual code Register Programming Considerations The Lab PC can only be used for 8 bit I O transfers thus all the I O read and write operations are 8 bit operations Several write only registers on the Lab PC contain bits that control several independent pieces of the onboard circuitry In the set or clear instructions provided specific register bits should be set or cleared without
178. sters making up the two Counter Timer Register Groups access the two onboard 8253 Counter Timers Each 8253 has three counters For convenience the two Counter Timer Groups and their respective 8253 integrated circuits have been designated A and B The three counters of Group A control onboard data acquisition timing and waveform generation The three counters of Group B are available for general purpose timing functions Each 8253 has three independent 16 bit counters and one 8 bit Mode Register The Mode Register is used to set the mode of operation for each of the three counters Writing to the Timer Interrupt Clear Register clears the interrupt request asserted when a low pulse is detected on the output of Counter A2 or on the EXTUPDATE line Bit descriptions for the registers in the Counter Timer Register Groups are given in the following pages National Instruments Corporation D 23 Lab PC User Manual Register Map and Descriptions Appendix D Counter A0 Data Register The Counter AO Data Register is used for loading and reading back contents of 8253 A Counter 0 Address Base address 14 hex Type Read and write Word Size 8 bit Bit Map 7 6 5 4 3 2 1 0 Dv w ps as B vR Mm DO Bit Name Description 7 0 D lt 7 0 gt 8 bit Counter AO contents Lab PC User Manual D 24 National Instruments Corporation Appendix D Register Map and Descriptions Counter A1 Data Register The Counter A1 Data Registe
179. t timing 3 18 Mode 2 bidirectional timing 3 20 referenced single ended input See RSE input eight channels registers D 1 to D 40 See also specific register groups and individual registers National Instruments Corporation 8253 Counter Timer Register Groups A and B D 23 to D 32 8255A Digital I O Register Group D 33 to D 37 Analog Input Register Group D 15 to D 20 Analog Output Register Group D 21 to D 22 Configuration and Status Register Group D 4 to D 14 Interval Counter Register Group D 38 to D 40 programming considerations E 1 register map table D 2 sizes D 3 relative accuracy analog input A 3 analog output A 4 RSE input eight channels configuration 2 12 definition table 2 11 signal connection considerations recommended configurations table 3 6 single ended connections 3 10 to 3 11 S sample interval counter See Counter AO Data Register sample interval timer 4 6 SCANEN bit channel scanning E 17 controlled acquisition mode E 6 posttrigger mode E 12 pretrigger mode E 14 description D 5 freerun acquisition mode E 9 multiple A D conversions interval scanning E 17 to E 18 single channel interval acquisition mode E 18 to E 19 scanned multiple channel data acquisition 4 6 to 4 7 SE D bit D 13 signal connections analog input connections 3 4 to 3 5 analog output connections 3 12 to 3 13 cabling considerations 3 28 digital I O connections 3 13 to 3 20 National Instrume
180. t voltage generated with the DAC set at positive full scale 4 095 This output voltage should be Vf 0 5 LSB For bipolar output Vt 4 99756 V and 0 5 LSB 1 22 mV For analog output Channel 0 a Connect the voltmeter between DACO OUT pin 10 on the I O connector and AGND pin 11 b Set the analog output channel to 4 99756 V by writing 2 047 to the DAC c Adjust trimpot R1 until the output voltage read is 4 99756 V For analog output Channel 1 a Connect the voltmeter between DACI OUT pin 12 on the I O connector and AGND pin 11 b Set the analog output channel to 4 99756 V by writing 2 047 to the DAC c Adjust trimpot R3 until the output voltage read is 4 99756 V National Instruments Corporation 5 7 Lab PC User Manual Calibration Chapter 5 Unipolar Output Calibration Procedure If your analog output channel is configured for unipolar output which has an output range of 0 to 10 V then offset calibration is not needed Calibrate your board by completing the following procedures for gain calibration Adjust the Analog Output Gain Adjust the analog output gain by measuring the output voltage generated with the DAC set at positive full scale 4 095 This output voltage should be Vf 0 5 LSB For unipolar output V its 9 99756 V and 0 5 LSB 1 22 mV For analog output Channel 0 a Connect the voltmeter between DACO OUT pin 10 on the I O connector and AGND pin 11 b Set the analog output
181. tage input rating 0 5 to 7 0 V with respect to DGND General Purpose Timing Signal Connections and General Purpose Counter Timing Signals The general purpose timing signals include the GATE CLK and OUT signals for the three 8253 B counters The 8253 Counter Timers can be used for general purpose applications such as pulse and square wave generation event counting and pulse width time lapse and frequency Lab PC User Manual 3 24 National Instruments Corporation Chapter 3 Signal Connections measurement For these applications CLK and GATE signals are sent to the counters and the counters are programmed for various operations The single exception is counter BO which has an internal 2 MHz clock The 8253 Counter Timer is described briefly in Chapter 4 Theory of Operation For detailed programming information consult Appendix B OKI 82C53 Data Sheet Pulse and square wave generation are performed by programming a counter to generate a timing signal at its OUT output pin Event counting is performed by programming a counter to count rising or falling edges applied to any of the 8253 CLK inputs The counter value can then be read to determine the number of edges that have occurred Counter operation can be gated on and off during event counting Figure 3 15 shows connections for a typical event counting operation where a switch is used to gate the counter on and off Signal Source T O Connector Lab PC Board Figure 3 15
182. ters in the 8253 can be diagrammed as shown in Figure 4 9 Counter OUT Figure 4 9 Counter Block Diagram Each counter has a CLK input pin a GATE input pin and an output pin labeled OUT The 8253 counters are numbered 0 through 2 and their GATE CLK and OUT pins are labeled GATE N CLK N and OUT N where N is the counter number Lab PC User Manual 4 14 National Instruments Corporation Chapter 5 Calibration This chapter discusses the calibration procedures for the Lab PC analog input and analog output circuitry The Lab PC is calibrated at the factory before shipment In order to maintain the 12 bit accuracy of the Lab PC analog input and analog output circuitry recalibration at six month intervals is recommended Recalibration is also recommended whenever the input or output configuration is changed Factory calibration is performed with the Lab PC in its default factory configuration e 5to 5 V analog input range bipolar e 5to 5 V analog output range bipolar Calibration Equipment Requirements For best measurement results you should calibrate the Lab PC so that its measurement accuracy is Within 0 012 of its input range 40 5 LSB According to standard practice the equipment used to calibrate the Lab PC should be 10 times as accurate that is have 0 001 rated accuracy Practically speaking calibration equipment with four times the accuracy of the item under calibration is generally considered acc
183. the Lab PC can also automatically time multiple A D conversions Figure 4 3 shows a block diagram of the analog input and data acquisition circuitry grammable ene d Gain Amp AER Command Registers PC I O Channel Ye v S Data Acquisition Timing External Trigger Counter Timer Signals Figure 4 3 Analog Input and Data Acquisition Circuitry Block Diagram Lab PC User Manual 4 4 National Instruments Corporation Chapter 4 Theory of Operation Analog Input Circuitry The analog input circuitry consists of two CMOS analog input multiplexers a software programmable gain amplifier a 12 bit ADC and a 12 bit FIFO memory that is sign extended to 16 bits One of the input multiplexers has eight analog input channels Channels 0 through 7 The other multiplexer is connected to Channels 1 3 5 and 7 for differential mode The input multiplexers provide input overvoltage protection of 45 V powered on or off The programmable gain amplifier applies gain to the input signal allowing an input analog signal to be amplified before being sampled and converted thus increasing measurement resolution and accuracy The gain of the instrumentation amplifier is selected under software control The Lab PC board provides gains of 1 2 5 10 20 50 and 100 The Lab PC uses a 12 bit successive approximation ADC The 12 bit resolution of the converter allows the converter to resolve its input range into
184. these groups is included later in this chapter The Configuration and Status Register Group controls the overall operation of the Lab PC and the D A circuitry The Analog Input Register Group is used to read output from the 12 bit successive approximation ADC The Analog Output Register Group accesses the two 12 bit DACs The two Counter Timer Register Groups A and B access each of the two onboard 8253 Counter Timer integrated circuits The Digital I O Register Group consists of the four registers of the onboard 8255A PPI integrated circuit used for digital I O The Interval Counter registers are used in the single channel interval acquisition mode Register Description Format The remainder of this register description chapter discusses each of the Lab PC registers in the order shown in Table D 1 Each register group is introduced followed by a detailed bit description of each register on the Lab PC For a detailed bit description of each register concerning the 8253 A or B chip on the Lab PC refer to Appendix B OKI 82C53 Data Sheet later in this manual The individual register description gives the address type word size and bit map of the register followed by a description of each bit The register bit map shows a diagram of the register with the MSB bit 7 for an 8 bit register shown on the left and the LSB bit 0 shown on the right A square is used to represent each bit Each bit is labeled with a name inside its square An ast
185. thus the ADC would have a relative accuracy of that amount National Instruments tests its boards to ensure that they meet all three linearity specifications defined in this appendix specifications for integral nonlinearity are included primarily to maintain compatibility with a convention of specifications used by other board manufacturers Relative accuracy however is much more useful Differential nonlinearity is a measure of deviation of code widths from their theoretical value of 1 LSB The width of a given code is the size of the range of analog values that can be input to produce that code ideally 1 LSB A specification of 1 LSB differential nonlinearity ensures that no code has a width of 0 LSBs that is no missing codes and that no code width exceeds 2 LSBs System noise is the amount of noise seen by the ADC when there is no signal present at the input of the board The amount of noise that is reported directly without any analysis by the ADC is not necessarily the amount of real noise present in the system unless the noise is 2 0 5 LSB rms Noise that is less than this magnitude produces varying amounts of flicker and the amount of flicker seen is a function of how near the real mean of the noise is to a code transition If the mean is near or at a transition between codes the ADC flickers evenly between the two codes and the noise is seen as very nearly 0 5 LSB If the mean is near the center of a code and the noise is relativel
186. tial amplifier is tied to analog ground This configuration is useful when measuring floating signal sources See Types of Signal Sources in Chapter 3 Signal Connections With this input configuration the Lab PC can monitor eight different analog input channels To select the RSE input configuration clear the SE D bit as described in the Command Register 4 bit description in Appendix D Register Map and Descriptions You must also set the following jumper W4 A B Jumper connects the negative input of the instrumentation amplifier to analog ground This configuration is shown in Figure 2 10 NRSE DIFF Figure 2 10 RSE Input Configuration Considerations in using the RSE configuration are discussed in Chapter 3 Signal Connections Note that in this mode the return path of the signal is analog ground available at the connector through pin AISENSE AIGND Lab PC User Manual 2 12 National Instruments Corporation Chapter 2 Configuration and Installation NRSE Input Eight Channels NRSE input means that all input signals are referenced to the same common mode voltage which is allowed to float with respect to the analog ground of the Lab PC board This common mode voltage is subsequently subtracted out by the input instrumentation amplifier This configuration is useful when measuring ground referenced signal sources To select the NRSE input configuration clear the SE D bit as described in the Command Register 4 bit description
187. tion Rates Maximum data acquisition rates number of samples per second are determined by the conversion period of the ADC plus the sample and hold acquisition time During multiple channel scanning the data acquisition rates are further limited by the settling time of the input multiplexers and programmable gain amplifier After the input multiplexers are switched the amplifier must be allowed to settle to the new input signal value to within 12 bit accuracy before an A D conversion is performed or else 12 bit accuracy will not be achieved The settling time is a function of the gain selected The Lab PC data acquisition timing circuitry detects when data acquisition rates are high enough to cause A D conversions to be lost If this is the case this circuitry sets an overrun error flag in the Lab PC Status Register If the recommended data acquisition rates in Table 4 2 are exceeded an error flag is not automatically set the analog input circuitry may not perform at 12 bit accuracy If these rates are exceeded by more than a few microseconds A D conversions may be lost Table 4 1 shows the recommended multiplexer and gain settling times for different gain settings Table 4 2 shows the maximum recommended data acquisition rates for both single channel and multiple channel data acquisition Notice that for a single channel data acquisition the data can be acquired at the maximum rate at any gain setting The analog input bandwidth however is
188. tions for each of the three ports with no handshaking Each port can be assigned as an input port or as an output port The 16 possible I O configurations are shown in Table E 5 Notice that bit 7 of the control word is set when programming the mode of operation for each port National Instruments Corporation E 25 Lab PC User Manual Register Level Programming Appendix E Table E 5 Mode 0 I O Configurations Port A Port C Port B Port C 76543210 10000000 10000001 10000010 10000011 10001000 10001001 10001010 10001011 10010000 10010001 10010010 10010011 10011000 10011001 10011010 10011011 1 Upper nibble of Port C 2 Lower nibble of Port C Programming Examples Example 1 Configure all three ports A B and C as output ports in Mode 0 e Write 80 hex to the Digital Control Register e Write 8 bit data to the Port A Port B or Port C Register as appropriate Example 2 Configure Port A for input Port B and Port C for output e Write 90 hex to the Digital Control Register e Write 8 bit data to Port B or Port C Read 8 bit data from Port A as appropriate Example 3 Configure Port A and Port C for output Port B for input e Write 82 hex to the Digital Control Register Example 4 Configure Port A and B for output Port C for input e Write 89 hex to the Digital Control Register Lab PC User Manual E 26 National Instruments Corporation Appendix E Register Level Programming Mode 1 This mod
189. to AISENSE AIGND pin 9 b Take analog input readings from Channel 0 at gains of 1 and 50 c Adjust trimpot R7 until the readings match to within one count at both gain settings 2 Output Offset Calibration To adjust the amplifier output offset a Connect ACHO pin 1 on the I O connector to AISENSE AIGND pin 9 b Take analog input readings from Channel 0 at the gain at which the system will be used c Adjust trimpot R6 until the readings are 0 0 5 LSB Alternatively the above offset calibration procedure can be carried out with the input gain set at 1 followed by recording the average reading at all other gains These readings can be used Lab PC User Manual 5 4 National Instruments Corporation Chapter 5 Calibration later for software offset correction of the data at gains other than 1 thus eliminating the need to perform the input offset recalibration when a different gain is used The software correction consists of subtracting the recorded reading at gain G from every A D conversion value obtained at gain G 3 Gain Calibration Adjust the analog input gain by applying an input voltage across ACHO and AISENSE AIGND This input voltage is 4 99634 V or Vf 1 5 LSB a Connect the calibration voltage 4 99634 V across ACHO pin 1 on the T O connector and AISENSE AIGND pin 9 Take analog input readings from Channel 0 at a gain of 1 and adjust trimpot R5 until the ADC readings flicker evenly between 2 046 a
190. tput circuitry e R3 Gain trim analog output Channel 1 e R4 Offset trim analog output Channel 1 e RI Gain trim analog output Channel 0 e R2 Offset trim analog output Channel 0 Lab PC User Manual 5 2 National Instruments Corporation Chapter 5 Calibration Analog Input Calibration To null out error sources that compromise the quality of measurements you must calibrate the analog input circuitry by adjusting the following potential sources of error e Offset errors e Gain error of the analog input circuitry You must perform the calibration if you change the input configuration from bipolar the factory setting to unipolar Offsets at the input to the instrumentation amplifier contribute gain dependent offset error to the analog input circuitry This offset is multiplied by the gain instrumentation amplifier Other sources of offset error include the track and hold amplifier and the ADC On the Lab PC two trimpots are used to null out all of these offset sources The first trimpot is used to null out the input offset up to and including the instrumentation amplifier To null out this offset ground the input channel and adjust R7 until the readings at gains of 1 and 50 are the same Then to null out the output offset adjust R6 until the readings are 0 5 LSB Because one of these error sources 1s gain dependent you should check and recalibrate the offset if necessary whenever the gain is changed significantly Alter
191. ts Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 7 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 8 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 9 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 10 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 11 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 12 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 13 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 14 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 15 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 16 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 17 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 18 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 19 Lab PC User Manual OKI 82C55A Data Sheet Appendix C Lab PC User Manual C 20 National Instruments Corporation Appendix C OKI 82C55A Data Sheet National Instruments Corporation C 21 Lab PC
192. ts contain the high byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion Values made up of D lt 15 0 gt therefore range from 2 048 to 2 047 decimal F800 to O7FF hex Two s complement mode is useful for bipolar analog input readings because the values read reflect the polarity of the input signal Low Byte 7 0 D lt 7 0 gt These bits contain the low byte of the 16 bit sign extended two s complement result of a 12 bit A D conversion The first of two consecutive readings of A D FIFO Register always returns this byte National Instruments Corporation D 17 Lab PC User Manual Register Map and Descriptions Appendix D A D Clear Register The ADC can be reset by writing to this register This operation clears the FIFO and loads the last conversion value into the FIFO All error bits in the Status Register are cleared as well Notice that the FIFO contains one data word after reset so two consecutive FIFO readings are necessary after reset to empty the FIFO The data that is read should be ignored Address Base address 08 hex Type Write only Word Size 8 bit Bit Map Not applicable no bits used Lab PC User Manual D 18 National Instruments Corporation Appendix D Register Map and Descriptions Start Convert Register Writing to the Start Convert Register location initiates an A D conversion Address Base address 03 hex Type Write only Word Size 8 bit Bit Map Not ap
193. uration Ground Referenced DIFF non isolated outputs NRSE plug in instruments Floating DIFF with bias resistors batteries thermocouples RSE isolated outputs Differential Connection Considerations DIFF Configuration Differential connections are those in which each Lab PC analog input signal has its own reference signal or signal return path These connections are available when the Lab PC is configured in the DIFF mode Each input signal is tied to the positive input of the instrumentation amplifier and its reference signal or return is tied to the negative input of the instrumentation amplifier Lab PC User Manual 3 6 National Instruments Corporation Chapter 3 Signal Connections When the Lab PC is configured for DIFF input each signal uses two of the multiplexer inputs one for the signal and one for its reference signal Therefore only four analog input channels are available when using the DIFF configuration The DIFF input configuration should be used when any of the following conditions are present e Input signals are low level less than 1 V e Leads connecting the signals to the Lab PC are greater than 15 ft e Any of the input signals requires a separate ground reference point or return signal e The signal leads travel through noisy environments Differential signal connections reduce picked up noise and increase common mode signal and noise rejection With these connections input signals can fl
194. ut Jumper Configuration Analog Input Configuration You can select different analog input configurations by using the jumper and register bit software settings as shown in Table 2 4 The following sections describe each of the analog input categories in detail Input Mode The Lab PC features three different input modes referenced single ended RSE input non referenced single ended NRSE input and differential DIFF input The single ended input configurations use eight channels The DIFF input configuration uses four channels These configurations are described in Table 2 5 Lab PC User Manual 2 10 National Instruments Corporation Chapter 2 Configuration and Installation Table 2 5 Input Configurations Available for the Lab PC DIFF Differential configuration provides four differential inputs with the positive input of the instrumentation amplifier tied to Channels 0 2 4 or 6 and the negative input tied to Channels 1 3 5 or 7 respectively thus choosing channel pairs 0 1 2 3 4 5 or 6 7 Non referenced single ended configuration provides eight single ended inputs with the negative input of the instrumentation amplifier tied to AISENSE AIGND and not connected to ground Referenced single ended configuration provides eight single ended inputs with the negative input of the instrumentation amplifier referenced to analog ground While reading the following paragraphs you may find it helpful to re
195. ut transfer curve If an ADC has been calibrated perfectly then this straight line is the ideal transfer function and the relative accuracy specification indicates the worst deviation from the ideal that the ADC permits A relative accuracy specification of 1 LSB is roughly equivalent to but not the same as a 2 LSB nonlinearity or integral nonlinearity specification because relative accuracy encompasses both nonlinearity and variable quantization uncertainty a quantity often mistakenly assumed to be exactly 2 LSB Although quantization uncertainty is ideally 2 LSB it can be different for each possible digital code and is actually the analog width of each code Thus it is more specific to use relative accuracy as a measure of linearity than it is to use what is normally called nonlinearity because relative accuracy ensures that the sum of quantization uncertainty and A D conversion error does not exceed a given amount Integral nonlinearity in an ADC is an often ill defined specification that is supposed to indicate a converter s overall A D transfer linearity The manufacturers of the ADC chips used by National Instruments specify their integral nonlinearity by stating that the analog center of any code will not deviate from a straight line by more than 2 LSB This specification is misleading because although the center of a particularly wide code may be found within 2 LSB of the ideal one of its edges may be well beyond 1 LSB
196. ut voltage rating 45 V powered on or off Exceeding the input signal range for gain settings greater than 1 will not damage the input circuitry as long as the maximum input voltage rating of 45 V is not exceeded For example with a gain of 10 the input signal range is 0 5 V for bipolar input and 0 to 1V for unipolar input but the Lab PC is guaranteed to withstand inputs up to the maximum input voltage rating Warning Exceeding the input signal range results in distorted input signals Exceeding the maximum input voltage rating may cause damage to the Lab PC board and to the computer National Instruments is NOT liable for any damages resulting from such signal connections Connection of analog input signals to the Lab PC depends on the configuration of the Lab PC analog input circuitry and the type of input signal source With the different Lab PC configurations the Lab PC instrumentation amplifier can be used in different ways Figure 3 2 shows a diagram of the Lab PC instrumentation amplifier Lab PC User Manual 3 4 National Instruments Corporation Chapter 3 Signal Connections Instrumentation Amplifier Vm Measured Voltage Vin Vint Vin GAIN Figure 3 2 Lab PC Instrumentation Amplifier The Lab PC instrumentation amplifier applies gain common mode voltage rejection and high input impedance to the analog input signals connected to the Lab PC board Signals are routed to the positive and negative inputs
197. utput signal range Bipolar input 5 V Unipolar input 0 to 10 V Maximum load current 2 mA for 12 bit linearity Figure 3 7 shows how to make analog output signal connections DACO OUT Channel 0 Channel 1 Analog Output Channels Lab PC Board Figure 3 7 Analog Output Signal Connections Digital I O Signal Connections Pins 13 through 37 of the I O connector are digital I O signal pins Digital I O on the Lab PC is designed around the 8255A integrated circuit The 8255A is a general purpose peripheral interface containing 24 programmable I O pins These pins represent the three 8 bit ports PA PB and PC of the 8255A Pins 14 through 21 are connected to the digital lines PA lt 0 7 gt for digital I O Port A Pins 22 through 29 are connected to the digital lines PB lt 0 7 gt for digital I O Port B Pins 30 through 37 National Instruments Corporation 3 13 Lab PC User Manual Signal Connections Chapter 3 are connected to the digital lines PC lt 0 7 gt for digital I O Port C Pin 13 DGND is the digital ground pin for all three digital I O ports The following specifications and ratings apply to the digital I O lines Absolute maximum voltage input rating 5 5 V with respect to DGND 0 5 V with respect to DGND Logical Inputs and Outputs Digital I O lines Minimum Maximum Input logic low voltage 0 3 V 0 8 V Input logic high voltage 2 2 V 5 3 V Output logic low voltage 0 4 V at output current 2
198. with a single ended configuration then the Lab PC must be configured in the NRSE input configuration The signal is connected to the positive input of the Lab PC instrumentation amplifier and the signal local ground reference is connected to the negative input of the Lab PC instrumentation amplifier The ground point of the signal should therefore be connected to the AISENSE pin Any potential difference between the Lab PC ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the instrumentation amplifier and is therefore rejected by the amplifier On the other hand if the input circuitry of the Lab PC is referenced to ground such as in the RSE configuration this difference in ground potentials appears as an error in the measured voltage Figure 3 6 shows how to connect a grounded signal source to a Lab PC board configured in the NRSE configuration Configuration instructions are included under Analog Input Configuration in Chapter 2 Configuration and Installation National Instruments Corporation 3 11 Lab PC User Manual Signal Connections Chapter 3 Ground Referenced Signal Source Common Measured Mode m Wltage Noise o and so on T O Connector Lab PC Board in NRSE Input Configuration Figure 3 6 Single Ended Input Connections for Grounded Signal Sources Common Mode Signal Rejection Considerations Figures 3 3 and 3 6 show connections for signal sources that a
199. x to the DACOH if DACO is configured for unipolar output Write 00 hex to the DACOL and then write 08 hex to the DACOH if DACO is configured for bipolar output 13 Write 00 hex to the DACIL and then write 00 hex to the DAC1H if DAC 1 is configured for unipolar output Write 00 hex to the DACIL and then write 08 hex to the DACIH if DAC is configured for bipolar output This sequence leaves the Lab PC circuitry in the following state e Counter AO output is high e Counter Al output is high This disables EXTCONV e All interrupts are disabled e EXTTRIG is disabled e The timebase for Counter AO is the onboard 1 MHz source e Analog input circuitry is initialized to RSE mode with a gain of 1 and Channel 0 selected e The A D FIFO is cleared e The Command Registers are initialized to 00 hex on power up Thus straight binary coding is selected for both DACs e The analog output circuitry is initialized to 0 0 V on both channels For additional details concerning the 8253 Counter Timer see Appendix B OKI 82C53 Data Sheet For information about the 8255A PPI see Appendix C OKI 82C55A Data Sheet Programming the Analog Input Circuitry This section describes the analog input circuitry programming sequence how to program the binary mode of the A D conversion result and how to clear the analog input circuitry Ensure that you have selected the appropriate analog input mode through jumper W4 and bit 3 of Command Re
200. xecuted by using the analog input circuitry and some of the timing I O circuitry The internal data and control buses interconnect the components The theory of operation for each of these components is explained in the remainder of this chapter The theory of operation for the data acquisition circuitry is included with the discussion of the analog input circuitry PC I O Channel Interface Circuitry The PC I O channel consists of an address bus a data bus a DMA arbitration bus interrupt lines and several control and support signals The components making up the Lab PC PC I O channel interface circuitry are shown in Figure 4 2 Lab PC User Manual 4 2 National Instruments Corporation Chapter 4 Theory of Operation Address Bus Address Address Latches Decoder Register Selects Timing Interface Read and Write Signals Control Lines Data Bus Data Buffers Internal Data Bus 3 I g a Q p Q DMA REQ DMA DMA Request DMA ACK Control DMA ACK and DMATC Interrupt Interrupt Requests Control Figure 4 2 PC I O Interface Circuitry Block Diagram The circuitry consists of address latches address decoders data buffers I O channel interface timing control circuitry interrupt control circuitry and DMA control circuitry The circuitry monitors the address lines SA5 through SA9 to generate the board enable signal and uses lines SAO through SA4 plus timing signals to generate the onboard register select s
201. y small very little or no flicker is seen and the noise is reported by the ADC as nearly 0 LSB From the relationship between the mean of the noise and the measured rms magnitude of the noise the character of the noise can be determined National Instruments has determined that the character of the noise in the Lab PC is fairly Gaussian and so the noise specifications given are the amounts of pure Gaussian noise required to produce our readings National Instruments Corporation A 3 Lab PC User Manual Specifications Analog Output Output Characteristics Number of channels Resolution Type of DAC Data transfers Transfer Characteristics Relative accuracy INL bipolat PANGS csiis te eist DND enaa a aT A EREE Monotonicity Offset error After calibration Before calibration Gain error relative to internal reference After calibration Before calibration fa ssh mie die Voltage Output IRANB CS E EEE ete er Output coupling Output impedance ss semaine Current drives Protection Power on state Dynamic Characteristics Settling time to FSR for 10 V step Slew rate Stability Offset temperature coefficient ee Gain temperature coefficient internal references siens sens Appendix A 12 bits 1 in 4 096 Double buffered multiplying Interrupts programmed I O 0 25 LSB typ 0 5 LSB max 0 25 LSB typ 0 75 LSB max 12 bits guaranteed Adjustable to 0 V 37 mV max Adjustable to 0 0 5 of reading 3 900 p

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