ECT_16B8C Block User Guide V01.06
Contents
1. BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tco tco teo tco tco tco tco tco teo teo tco tco tco teo tco teo Ww 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC1 Timer Input Capture Output Compare Register 1 Register offset 12 5 13 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc1 te tei tei tot tei tei tei tot tei tei tei tei tct tei tct W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC2 Timer Input Capture Output Compare Register 2 Register offset 14 5 15 BITI5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc2 tee tee te tea tee tee tee tee tee tee tee tc2 tc2 tc2 tc2 Ww 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC3 Timer Input Capture Output Compare Register 3 Register offset 16 5 17 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc3 tea tc3 tea tea tea tc3 tc3 tea tea tc3 tc3 tc3 tc3 tc3 tc3 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC4 Timer Input Capture Output Compare Register 4 Register offset 18 5 19 BITI5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc4 tc4 tea tc4 tc4 tea tc4 tc4 tea to4 tc4 tc4 tc4 tc4 tc4 tc4 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC5 Timer Input Capture2. 41 Modulus Down Counter Count Register MCCNT 42 Timer Input Capture Holding Register 0 TCOH 43 Timer Input Capture Holding Register 1 TC1H 43 Timer Input Capture Holding Register 2 TC2H 43 Timer Input Capture Holding Register 3 TC3H 43 Detailed Timer Block Diagram in Latch mode 46 Detailed Timer Block Diagram in Queue mode 47 8 Bit Pulse Accumulators Block Diagram 48 16 Bit Pulse Accumulators Block Diagram 49 Block Diagram for Port7 with Output compare Pulse Accumulator A50 Channel Input validity with delay counter feature 52 For More Information On This Product Go to www freescale com M MOTOROLA Freescale SemiconductotrIn sac Block User Guide VO1 06 List of Tables Table 3 1 Module Memory Map azo those hal Tapa PEK PANDA ane ER ee ow LAG 17 Table 3 2 Compare Result Output Action 0 00 EE Ek se ee ee 24 Table 3 3 Edge Detector Circuit Configuration lille 24 Table 3 4 Prescaler Selection ss sd oa ears ooa Dowd ae a Ea he Bas ea ee ae 26 Table 3 5 Pim AENBRG SE afc Gon DEERE Ee EE ra as AE a arth oe GP end aS BS we 30 Table 320 gt Clock Selection ve creais RNE oe Si RATA ROC BA ERE ee Ea 30 Table 3 7 Modulus Counter Prescaler Select 0 0 0 0 cece ens 34 Table 3 8 Delay Counter Select EER badd EDE RD e EG AS GER kk EDE eevee et ay 37 Table 6 1 EGT Inte
3. A full access for the counter register should take place in one clock cycle A separate read any mode write test mode for high byte and low byte will give a different result than accessing them as a word Read anytime Write has no meaning or effect in the normal mode only writable in special modes test_mode 1 The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescaler clock M MOTOROLA 21 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 3 3 6 TSCR1 Timer System Control Register 1 Register offset 06 BIT7 6 5 4 3 2 1 BITO R 0 0 W TEN TSWAI TSFRZ TFFCA RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 6 Timer System Control Register 1 TSCR1 Read or write anytime TEN Timer Enable 0 Disables the main timer including the counter Can be used for reducing power consumption 1 Allows the timer to function normally If for any reason the timer is not active there is no 64 clock for the pulse accumulator since the 64 is generated by the timer prescaler TSWAI Timer Module Stops While in Wait 0 Allows the timer module to continue running during wait 1 Disables the timer module when the MCU is in the wait mode Timer interrupts cannot be used to get the MCU out of wait TSWAI also
4. Pulse Accumulator Mode This bit is active only when the Pulse Accumulator A is enabled PAEN 1 0 event counter mode 1 gated time accumulation mode PEDGE Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator A is enabled PAEN 1 For PAMOD bit 0 event counter mode 0 falling edges on PT7 pin cause the count to be incremented 1 rising edges on PT7 pin cause the count to be incremented For PAMOD bit 1 gated time accumulation mode 0 PT7 input pin high enables bus clock divided by 64 to Pulse Accumulator and the trailing falling edge on PT7 sets the PAIF flag 1 PT7 input pin low enables bus clock divided by 64 to Pulse Accumulator and the trailing rising edge on PT7 sets the PAIF flag Table 3 5 Pin Action Pin Action Falling edge Rising edge Div by 64 clock enabled with pin high level Div by 64 clock enabled with pin low level If the timer is not active TEN 0 in TSCR there is no divide by 64 since the 64 clock is generated by the timer prescaler CLK1 CLKO Clock Select Bits Table 3 6 Clock Selection Clock Source Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK 256 as timer counter clock frequency Use PACLK 65536 as timer counter clock frequency For the description of PACLK please refer Figure 4 4 If the pulse accumulator is disabled PAEN 0 the pre
5. Go to www freescale com Freescale Semiconductabrihesc Block User Guide VO1 06 DLYn Delay Counter Select Table 3 8 Delay Counter Select DLY1 DLYO Delay Disabled bypassed 256 bus clock cycles 512 bus clock cycles 1024 bus clock cycles 0 1 1 al ol a 3 3 23 ICOVW Input Control Overwrite Register Register offset 2A BIT7 6 5 4 3 2 1 BITO R W NOVW7 NOVW6 NOVW5 NOVW4 NOVW3 NOVW2 NOVW1 NOVWO RESET 0 0 0 0 0 0 0 0 Figure 3 25 Input Control Overwrite Register ICOVW Read or write any time An IC register is empty when it has been read or latched into the holding register A holding register is empty when it has been read NOVWn No Input Capture Overwrite 0 The contents of the related capture register or holding register can be overwritten when a new input capture or latch occurs 1 The related capture register or holding register cannot be written by an event unless they are empty see 4 2 1 IC Channels This will prevent the captured value to be overwritten until it is read or latched in the holding register 3 3 24 ICSYS Input Control System Control Register Register offset 2B BIT7 6 5 4 3 2 1 BITO R W SH37 SH26 SH15 SH04 TFMOD PACMX BUFEN LATQ RESET 0 0 0 0 0 0 0 0 Figure 3 26 Input Control System Register ICSYS Read any time Write Can be written once test_mode 0 Writes are always permitted when test_mode 1 SHxy Share Input a
6. M MOTOROLA 3 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 4 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 Table of Contents Section 1 Introduction MAD OV GIVIGW ii cin aay ene kes ON s 13 du RCAC ace se aris qul MI AE cM hans eames DR EE tinea atte 13 Ls Modes OF ODOLAtlonr ss EE REED YE DE RES ote nese Senda A EE 13 4 Block Diagrami a EE EE shat a o T a po E a DO ETD GE AD 14 Section 2 Signal Description Bok QVGIWIOW 45 940 EE ORE EE KI OE OE EER IE TE ORE EN 15 2 2 Detailed Signal Descriptions iS EE ds BED RD NAI EE eoe ve 15 2 2 1 IOC7 Input capture and Output compare channel 7 EE EE EE eee 15 2 2 2 IOC6 Input capture and Output compare channel 6 EE EE EE Eie 15 2 2 3 IOC5 Input capture and Output compare channel 5 a 15 2 2 4 IOC4 Input capture and Output compare channel 4 aeann 15 2 2 5 IOC3 Input capture and Output compare channel 3 20000 eee 15 2 2 6 IOC2 Input capture and Output compare channel 2 22000 eee 15 2 2 7 IOC1 Input capture and Output compare channel 1 15 2 2 8 IOCO Input capture and Output compare channel 0 a 15 Section 3 Memory Map and Registers S OVILLO rud B a UE UR tea ae 17 3 2 Module Memory Map Zsa
7. 16 bit Free running AMES main timer 1 4 8 16 1 2 128 bus clock Prescaler PO 0 Ly RESET P1 Pinlogic umm 5 y C1 capture compare register p PACI 5 TC1H hold register PA1H hold register E ma isa 0 Lg RESE P2 Pinlogic um Y PAC2 P4 P5 pce ae 01 RESET a P za o o e ie pi 3 a oO Q 2 amp at Ol LATCH PAOH hold register PA2H hold register 0 4 RESE Y PAC3 C4 capture compare registe PA3H hold register LATQ BUFEN queue mode Comparator C5 capture compare registe P6 Comparator C6 capture compare registel rH Read TC3H hold register D Read TC2H hold register P7 M MOTOROLA Comparator C7 capture compare registe H Read TC1H gt hold register Ly Read TCOH hold register For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc Figure 4 3 8 Bit Pulse Accumulators Block Diagram Load holding register and reset pulse accumulator A 8 bit PACO PACNO Edge detector Delay counter PAOH holding register Interrupt 8 bit PAC1 PACN1 De
8. 3 3 16 PAFLG Pulse Accumulator A Flag Register eee eee eee 31 3 3 17 PACN3 PACN2 Pulse Accumulators Count Registers 32 3 3 18 PACN1 PACNO Pulse Accumulators Count Registers 33 3 3 19 MCCTL 16 Bit Modulus Down Counter Control Register 33 3 3 20 MCFLG 16 Bit Modulus Down Counter FLAG Register 35 3 3 21 ICPAR Input Control Pulse Accumulators Register 36 3 3 22 DLYCT Delay Counter Control Register 02 EE Ee ee de 36 3 3 23 ICOVW Input Control Overwrite Register 0c eee eee 37 3 3 24 ICSYS Input Control System Control Register 0 0 Aa 37 3 3 25 TIMTST Timer Test Register 1x uud nee tect head latas EDE OER AURA 39 3 3 26 PBCTL 16 Bit Pulse Accumulator B Control Register 39 3 3 27 PBFLG Pulse Accumulator B Flag Register oo o oooocooooooo 40 3 3 28 8PA3H PAOH 8 Bit Pulse Accumulators Holding Registers 41 3 3 29 MCCNT Modulus Down Counter Count Register EE ee de 42 3 3 30 Timer Input Capture Holding Registers 0 3 EE Ee eee ee 43 Section 4 Functional Description 4 1 Generals EE AE GE EE ta AA 45 4 2 Enhanced Capture Timer Modes of Operation 0c eee eee ee eee 50 4 2 1 IG GRANNIES 0 ese as o Olt thie apis oe AE hte SRSA OR e o tat Man ahd AE aia 50 4
9. DOCUMENT NUMBER Freescale Semiconductor Inc S12ECTIGBSCV1 D ECT 16B8C Block User Guide V01 06 Original Release Date 2 Sep 1999 Revised Jul 05 2004 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA For More Information On This Product Go to www freescale com ECT 16B
10. TFLG2 27 Timer Input Capture Output Compare Registers 0 7 29 16 Bit Pulse Accumulator Control Register PACTL 29 Pulse Accumulator A Flag Register PAFLG 31 Pulse Accumulators Count Register 3 PACN3 32 Pulse Accumulators Count Register 2 PACN2 32 Pulse Accumulators Count Register 1 PACN1 33 Pulse Accumulators Count Register 0 PACNO 33 16 Bit Modulus Down Counter Control Register MCCTL 33 16 Bit Modulus Down Counter FLAG Register MCFLG 35 Input Control Pulse Accumulators Register ICPAR 36 Delay Counter Control Register DLYCT 36 Input Control Overwrite Register ICOVW 37 Input Control System Register ICSYS 37 Timer Test Register TIMTST a 39 16 Bit Pulse Accumulator B Control Register PBCTL 39 Pulse Accumulator B Flag Register PBFLG 40 8 Bit Pulse Accumulators Holding Register 3 PA3H 41 8 Bit Pulse Accumulators Holding Register 2 PA2H 41 8 Bit Pulse Accumulators Holding Register 1 PA1H 41 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc Figure 3 33 Figure 3 34 Figure 3 35 Figure 3 36 Figure 3 37 Figure 3 38 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 8 Bit Pulse Accumulators Holding Register 0 PAOH
11. 2 1 1 Non Buttered IG CGhannel8 so EER RE RES dee ag EE EIE eee ees d 51 4 2 1 2 Buffered IC Channels e 46 ELE dh SO ARE EE ED oe uti dur o See Bel 51 4 2 1 3 Delayed IC channels weston EERS ote toe wc ee ea ee ese ed 54 51 4 2 2 Pulse AC CUIMUIATONS uera Ru DE ences ER de det ance PR ERU ERE ee ee A Ua E ee dad ESE E ace 52 4 2 2 1 Pulse Accumulator latch modes oar EE RE ER RR DRR E GE EE dan LAAN 53 4 2 2 2 Pulse Accumulator queue mode 000 ee ees 53 4 2 3 Modulus Down Counter tas ac aca sree SE hs a 53 4 2 4 Channel Configurations lt a cue dk oY oe p Sd uuu Ki See OE EE ee aa do Dis 53 Section 5 Reset 5 1 General a Sete ESE RE EE dents ida a es back awa Ben DR DE SEE te areas 55 6 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 Section 6 Interrupts MEEL RE EIE cacy se Ooh IS ON OR sae eee fe 57 6 2 Description of Interrupt Operation 4 sews ia bebe dad Kha eee ede oes 57 6 2 1 Enamora CERE dc ese EN 57 6 2 2 Modulus Counter Interrupt 2 MES NAG NG SES EE Ee ES 57 6 2 3 Pulse Accumulator B Overflow Interrupt EE EE Ee eee eee 57 6 2 4 Pulse Accumulator A Input Interrupt siste EE EER RR ER RR SE IE eee ees 57 6 2 5 Pulse Accumulator A Overflow Interrupt aasan EE EE EE eee eee eee 58 6 2 6 Timer Overflow nter HIDE ves nece ct AE AE ES eene tan 58 M MOTOROLA 7 For More Information On This Product Go to w
12. 5 3C 3D BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TCO W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 37 Timer Input Capture Holding Register 2 TC2H Register offset 3E 3F BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TCO W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 38 Timer Input Capture Holding Register 3 TC3H M MOTOROLA 43 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc Read any time Write has no effect These registers are used to latch the value of the input capture registers TCO TC3 The corresponding IOSn bits in TIOS 00 should be cleared see 4 2 1 IC Channels 44 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductabrihesc Block User Guide VO1 06 Section 4 Functional Description 4 1 General This section provides a complete functional description of the ECT block detailing the operation of the design from the end user perspective in a number of subsections M MOTOROLA 45 For More Information On This Product Go to www freescale com
13. na Pa EE ATA See e ERE CE ee ees 17 3 3 Register DosclHpHOlSmaoams iae Benes RON ere IO EAR RO RR GAN D ah AENEID qiia De he 19 3 3 1 TIOS Timer Input Capture Output Compare Select Register 19 3 3 2 CFORC Timer Compare Force Register Es eee eee 20 3 3 3 OC7M Output Compare 7 Mask Register 000 cece ee eee 20 3 3 4 OC7D Output Compare 7 Data Register o oooooooooooooooo 21 3 3 5 TENT Timer Count Register EE DEERE a3 AA Boe da Be Song GER GR 21 3 3 6 TSCR1 Timer System Control Register 1 EE EE eee eee ee eee 22 3 3 7 TTOV Timer Toggle On Overflow Register 1 oooooccooooooo 23 3 3 8 TCTL1 TCTL2 Timer Control Register 1 Timer Control Register 2 23 3 3 9 TCTL3 TCTL4 Timer Control Register 3 Timer Control Register 4 24 3 3 10 TIE Timer Interrupt Enable Register 2 eee eee eee 25 3 3 11 TSCR2 Timer System Control Register 2 is EE Es EE eee 25 M MOTOROLA 5 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidekge scale Semiconductor Inc 3 3 12 TFLG1 Main Timer Interrupt Flag 1 0 EE se ee ee ee 26 3319 TELG2 Main Timer Interrupt Flag 2 2 es xr etr REDE E EE ER 27 3 3 14 Timer Input Capture Output Compare Registers 0 7 28 3 3 15 PACTL 16 Bit Pulse Accumulator A Control Register 29
14. 8C Block User Guidekge scale Semiconductor Inc Revision History Version Revision Effective inti Number Date Date Author Description of Changes 0 1 2 Sep 99 2 Sep 99 Original draft Distributed only within Motorola 0 2 24 Sep 99 24 Sep 99 QS9000 Verified Changed the specs as per MSRS format Modified ECT16b8c Block diagram Modified IP Bus signal names and their description Modified ECT output signal names Deleted bits 3 0 of TSCR1 register in Register Map Sheet 1 of 2 Modified register addresses in the description of TSFRZ WAIT NORMAL mode Modes of Operation In Figure 1 6 changed text font to Halvetica Renamed TMSK1 and TMSK2 register as TIE and TSCR2 also renamed TSCR as TSCRI Modified TFLG2 bit setting sentence Added explanation about the abbreviation M clock PACLK used Removed duplication of lines at the end of register description of PACN3 PACN2 Corrected the reset value of MCCNT from FF to FFFF in the description of register MCCTL Corrected Table format for delay counter select and Modulus counter Prescalar Select Corrected all the cross references used in section 3 of the document Deleted and added some module specific signals Changed all interrupts from active LOW to active HIGH Added description about successful output comapre and forced output compare taking place simultaneously and their effect on flag Added abbreviation section In Fig 1 3 changed host dat
15. ECT 16B8C Block User Guidelwe sscale Semiconductor Inc Refer to the Timer Block Diagrams from Figure 4 1 to Figure 4 5 as necessary N PO P1 P2 P3 P4 P5 P6 P7 46 TIMCLK 1 2 128 16 bit Free running main timer Delay counte EDGI 1 4 8 16 bit modulus Figure 4 1 Detailed Timer Block Diagram in Latch mode 16 bit load register 01 RESET 0 Comparator EE sn EN Y Underflow PAOH ho d register RESET PACI C2 capture compare registe ME PA1H hold register RESET PAG2 TC2H hold register Comparator C3 capture compare registe ye PA2H hold register 0 RESET M PAC3 TC3H hold register EDG0 SH04 EDG1 39 SH15 MUX Comparator C4 capture compare registe ye PA3H hold register ICLAT LATQ BUFEN force latch Comparator C5 capture compare registe EDG2 Comparator C6 capture compare registe Comparator Write 0000 to modulus counter LATQ MDC latch enable M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 Figure 4 2 Detailed Timer Block Diagram in Queue mode 16 bit load register
16. NOTE When clocking pulse and write to the registers occurs simultaneously write takes priority and the register is not incremented 3 3 19 MCCTL 16 Bit Modulus Down Counter Control Register Register offset 26 BIT7 6 5 4 3 2 1 BITO R 0 0 MCZI MODMC RDMCL MCEN MCPR1 MCPRO W ICLAT FLMC RESET 0 0 0 0 0 0 0 0 Figure 3 21 16 Bit Modulus Down Counter Control Register MCCTL Read or write any time MCZI Modulus Counter Underflow Interrupt Enable 0 Modulus counter interrupt is disabled M MOTOROLA 33 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 1 Modulus counter interrupt is enabled MODMC Modulus Mode Enable 0 The counter counts once from the value written to it and will stop at 0000 1 Modulus mode is enabled When the counter reaches 0000 the counter is loaded with the latest value written to the modulus count register NOTE For proper operation the MCEN bit should be cleared before modifying the MODMC bit in order to reset the modulus counter to F FFF RDMCL Read Modulus Down Counter Load 0 Reads of the modulus count register will return the present value of the count register 1 Reads of the modulus count register will return the contents of the load register ICLAT Input Capture Force Latch Action When input capture latch mode is enabled LATQ and BUFEN bit in ICSYS 2B are
17. O R 0 0 0 0 W PASEN PA2EN PA1EN PAOEN RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 23 Input Control Pulse Accumulators Register ICPAR The 8 bit pulse accumulators PAC3 and PAC2 can be enabled only if PAEN in PATCL 20 is cleared If PAEN is set PA3EN and PA2EN have no effect The 8 bit pulse accumulators PACI and PACO can be enabled only if PBEN in PBTCL 30 is cleared If PBEN is set PAIEN and PAOEN have no effect Read or write any time PAnEN 8 Bit Pulse Accumulator Enable 0 8 Bit Pulse Accumulator is disabled 1 8 Bit Pulse Accumulator is enabled 3 3 22 DLYCT Delay Counter Control Register Register offset 29 BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 0 0 DLY1 DLYO W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 24 Delay Counter Control Register DLYCT Read or write any time If enabled after detection of a valid edge on input capture pin the delay counter counts the pre selected number of bus clock cycles then it will generate a pulse on its output The pulse is generated only if the level of input signal after the preset delay is the opposite of the level before the transition This will avoid reaction to narrow input pulses After counting the counter will be cleared automatically Delay between two active edges of the input signal period should be longer than the selected counter delay 36 M MOTOROLA For More Information On This Product
18. OLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 Section 5 Reset 5 1 General The reset state of each individual bit is listed within the Register Description section Section 3 Memory Map and Registers which details the registers and their bit fields 55 M MOTOROLA For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 56 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductagrin sc Block User Guide VO1 06 Section 6 Interrupts 6 1 General This section describes interrupts originated by the ECT_16B8C block The MCU must service the interrupt requests Table 6 1 lists the interrupts generated by the ECT to communicate with the MCU Table 6 1 ECT Interrupts Interrupt Source Description Timer Channel 7 0 Active high timer channel interrupts 7 0 Modulus counter underflow Active high modulus counter interrupt Pulse Accumulator B Overflow Active high pulse accumulator B interrupt Pulse Accumulator A Active high pulse accumulator A input Input interrupt Pulse Aecumulatar Pulse accumulator overflow interrupt Overflow Timer Overflow Timer Overflow interrupt l 6 2 Description of Interrupt Operation The ECT_16B8C only originates interrupt requests The following is a description of how the module mak
19. OV Read or write anytime TOVn Toggle On Overflow Bits TOVn toggles output compare pin on overflow This feature only takes effect when in output compare mode When set it takes precedence over forced output compare but not channel 7 override events 0 Toggle output compare pin on overflow feature disabled 1 Toggle output compare pin on overflow feature enabled 3 3 8 TCTL1 TCTL2 Timer Control Register 1 Timer Control Register 2 Register offset 5 08 BIT7 6 5 4 3 2 1 BITO RESET 0 0 0 0 0 0 0 0 Register offset 5 09 BIT7 6 5 4 3 2 1 BITO de OM3 OL3 OM2 OL2 OM1 OL1 OMO OLO RESET 0 0 0 0 0 0 0 0 Figure 3 8 Timer Control Register 1 Timer Control Register 2 TCTL1 TCTL2 Read or write anytime OMn Output Mode OLn Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCn n varies from 0 to 7 compare When either OMn or OLn is one the port associated with OCn becomes an output tied to OCn when the corresponding IOSn bit of TIOS register is set and TEN bit of TSCR1 register is set Refer to the note on Section 4 2 4 for more insight M MOTOROLA 23 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe sscale Semiconductor Inc NOTE To enable output action by OMn and OLn bits on timer port the corresponding bit in OC7M should be cleared Table 3 2 Compare Result
20. Output Action Action Timer disconnected from output pin logic Toggle OCn output line Clear OCn output line to zero Set OCn output line to one 0 1 0 1 To operate the 16 bit pulse accumulators A and B PACA and PACB independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSn 1 OMn 0 and OLn 0 OC7M7 or OC7MO in the OC7M register must also be cleared 3 3 9 TCTL3 TCTL4 Timer Control Register 3 Timer Control Register 4 Register offset 0A BIT7 6 5 4 3 2 1 BITO EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A RESET 0 0 0 0 0 0 0 0 Register offset 0B BIT7 6 5 4 3 2 1 BITO RESET 0 0 0 0 0 0 0 0 Figure 3 9 Timer Control Register 3 Timer Control Register 4 TCTL3 TCTL4 Read or write anytime EDGnB EDGnA Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits The four pairs of control bits of TCTL4 also configure the 8 bit pulse accumulators PACO 3 For 16 bit pulse accumulator PACB EDGE0B amp EDGEOA control bits of TCTL4 will decide the active edge Table 3 3 Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 Capture on rising edges only 1 0 Capture on falling edges only 1 Capture on any edge rising or falling 24 M MOTOROLA For More Information On This Product G
21. Output Compare Register 5 Register offset 1A 1B BITI5 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc5 tes tes tes tes tes tes tes tes tes tes tes tc5 tc5 tc5 tc5 W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 TC6 Timer Input Capture Output Compare Register 6 Register offset 5 1C 1D BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 Ww 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28 For More Information On This Product Go to www freescale com M MOTOROLA Freescale SemiconductotrIn sac Block User Guide VO1 06 TC7 Timer Input Capture Output Compare Register 7 Register offset 1E 1F BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 tc7 Ww 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 14 Timer Input Capture Output Compare Registers 0 7 Depending on the TIOS bit for the corresponding channel these registers are used to latch the value of the free running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare Read anytime Write anytime for output compare function Writes to these registers have no meaning or effect during input capture All timer input capture output c
22. PT7 input pin In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the PT7 input pin triggers PAIF This bit is cleared by a write to the PAFLG register with bit 0 set Any access to the PACN3 PACN 2 registers will clear all the flags in this register when TFFCA bit in register TSCR 06 is set M MOTOROLA 31 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwwe sscale Semiconductor Inc 3 3 17 PACN3 PACN2 Pulse Accumulators Count Registers Register offset 22 BIT7 6 5 4 3 2 1 BITO R W pacnt7 15 pacnt6 14 pacnt5 13 pacnt4 12 pacnt3 11 pacnt2 10 pacnt1 9 pacnt0 8 RESET 0 0 0 0 0 0 0 0 Figure 3 17 Pulse Accumulators Count Register 3 PACN3 Register offset 23 BIT7 6 5 4 3 2 1 BITO R W pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacntO RESET 0 0 0 0 0 0 0 0 Figure 3 18 Pulse Accumulators Count Register 2 PACN2 Read or write any time The two 8 bit pulse accumulators PAC3 and PAC2 are cascaded to form the PACA 16 bit pulse accumulator When PACA in enabled PAEN 1 in PACTL 20 the PACN3 and PACN registers contents are respectively the high and low byte of the PACA When PACN3 overflows from FF to 00 the Interrupt flag PAOVF in PAFLG 21 is set Full count register access should take place in one clock cy
23. Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 16 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductotrin sac Block User Guide VO1 06 Section 3 Memory Map and Registers 3 1 Overview This section provides a detailed description of all memory and registers 3 2 Module Memory Map The memory map for the ECT module is given below in Table 3 1 The Address listed for each register is the address offset The total address for each register is the sum of the base address for the ECT module and the address offset for each register Table 3 1 Module Memory Map Offset Use Access _00 Timer Input Capture Output Compare Select TIOS Read Write 01 Timer Compare Force Register CFORC Read Write 02 Output Compare 7 Mask Register OC7M Read Write 03 Output Compare 7 Data Register OC7D Read Write 04 Timer Count Register High TCNT Read Write 05 Timer Count Register Low TCNT Read Write S 06 Timer System Control Register1 TSCR1 Read Write 07 Timer Toggle Overflow Register TTOV Read Write S 08 Timer Control Register1 TCTL1 Read Write 09 Timer Control Register2 TCTL2 Read Write 0A Timer Control Register3 TCTL3 Read Write OB Timer Control Registerd TCTL4 Read Write 0C Timer Interrupt Enable Register TIE Read Write 0D Timer System Control Register2 TSCR2
24. Read Write _0E Main Timer Interrupt Flag1 TFLG1 Read Write OF Main Timer Interrupt Flag2 TFLG2 Read Write 10 Timer Input Capture Output Compare Register0 High Read Write TCO 11 Timer Input Capture Output Compare Register0 Low Read Write TCO 12 Timer Input Capture Output Compare Register1 High Read Write TC1 13 Timer Input Capture Output Compare Register1 Low Read Write TC1 14 Timer Input Capture Output Compare Register2 High Read Write TC2 15 Timer Input Capture Output Compare Register2 Low Read Write TC2 16 Timer Input Capture Output Compare Register3 High Read Write TC3 M MOTOROLA 17 For More Information On This Product Go to www freescale com ECT 16B8C Block User GuidetefRSCale Semiconductor Inc Table 3 1 Module Memory Map 18 17 Timer Input Capture Output Compare Register3 Low Read Write TC3 18 Timer Input Capture Output Compare Registerd High Read Write TC4 19 Timer Input Capture Output Compare Register4 Low Read Write TC4 i Regi High 1A Timer Input Capture Output Compare Register5 Hig Read Write TC5 1B Timer Input Capture Output Compare Register5 Low Read Write TC5 1C Timer Input Capture Output Compare Register6 High Read Write TC6 1D Timer Input Capture Output Compare Register6 Low Read Write TC6 1E Timer Input Capture Output Compare Register7 High Read Write TC7 1F Timer In
25. Read or write anytime Setting the OC7Mn n ranges from 0 to 6 bit of OC7M register configures the corresponding port to be an output port when the IOS7 bit and the corresponding IOSn n ranges from 0 to 6 bit of TIOS register are set to be an output compare Refer to the note on Section 4 2 4 for more insight NOTE A successful channel 7 output compare overrides any channel 6 0 compares For each OC7M bit that is set the output compare action reflects the corresponding OC7D bit 20 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 3 3 4 OC7D Output Compare 7 Data Register Register offset 03 BIT7 6 5 4 3 2 1 BITO OC7D7 OC7D6 OC7D5 OC7D4 OC7D3 OC7D2 OC7D1 OC7D0 RESET 0 0 0 0 0 0 0 0 Figure 3 4 Output Compare 7 Data Register OC7D Read or write anytime A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register 3 3 5 TCNT Timer Count Register Register offset 5 04 5 05 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R tent tent tent tent tent tent tent tent tent tent tent tent tent tent tent tent W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Figure 3 5 Timer Count Register TCNT The 16 bit main timer is an up counter
26. a bus to IPbus 0 3 25 Oct 99 0 4 11 Nov 99 25 Oct 99 11 Nov 99 Changed block name in Section 2 Removed signals ipp ect ic ibe and ipp ect ic offval from port list Removed signal ipb read amp ipb write from portlist ipb_rwb added M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductotrin sac Block User Guide VO1 06 Version Revision Effective Number Date Date Author Description of Changes e Incorporated feedback received from Joachim Kruecken on 0 5 1 Dec 99 1 Dec 99 30 Nov 99 e CLAT and FLMC Eliminated all references of n to x e g IOSn to IOSx e Changed the register bit information of MCCTL on bits 01 03 18 Jul 02 18 Jul 02 01 04 11 Nov 02 11 Nov 02 e Description of OC7M and TCTLI registers modified note on OC added in section 4 e Included description about delay counter in section 4 2 1 3 01 05 12 Mar 04 12 Mar 04 01 06 05 Jul 04 05 Jul 04 Modified the description about TCNT in section 3 3 5 e formal changes for SRS compliance cover master pages paragraph formats register templates GAP el HENAY DI e updated cross references e marked TIMTST register description with non cust tag Document names have been added 01 01 19 July 01 e Names and Variable definitions have been hidden 01 02 10 Jan 02 10 Jan 02 e Note added in Section 3 3 18 for PACNI PACNO
27. affects pulse accumulators and modulus down counters TSFRZ Timer and Modulus Counter Stop While in Freeze Mode 0 Allows the timer and modulus counter to continue running while in freeze mode 1 Disables the timer and modulus counter whenever the MCU is in freeze mode This is useful for emulation TSFRZ does not stop the pulse accumulator TFFCA Timer Fast Flag Clear All 0 Allows the timer flag clearing to function normally 1 For TFLGI SOE a read from an input capture or a write to the output compare channel 10 1F causes the corresponding channel flag CnF to be cleared For TFLG2 0F any access to the TCNT register 04 05 clears the TOF flag Any access to the PACN3 and PACNG registers 22 23 clears the PAOVF and PAIF flags in the PAFLG register 21 Any access to the PACNI and PACNO registers 24 25 clears the PBOVF flag in the PBFLG register 31 This has the advantage of eliminating software overhead in a separate clear sequence Extra care is required to avoid accidental flag clearing due to unintended accesses 22 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 3 3 7 TTOV Timer Toggle On Overflow Register 1 Register offset _07 BIT7 6 5 4 3 2 1 BITO R W TOV7 TOV6 TOV5 TOV4 TOV3 TOV2 TOV1 TOVO RESET 0 0 0 0 0 0 0 0 Figure 3 7 Timer Toggle On Overflow Register 1 TT
28. cle A separate read write for high byte and low byte will give a different result than accessing them as a word NOTE When clocking pulse and write to the registers occurs simultaneously write takes priority and the register is not incremented 32 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductabrihesc Block User Guide VO1 06 3 3 18 PACN1 PACNO Pulse Accumulators Count Registers Register offset 24 BIT7 6 5 4 3 2 1 BITO R W pacnt7 15 pacnt6 14 pacnt5 13 pacnt4 12 pacnt3 11 pacnt2 10 pacnt1 9 pacnt0 8 RESET 0 0 0 0 0 0 0 0 Figure 3 19 Pulse Accumulators Count Register 1 PACN1 Register offset 5 25 BIT7 6 5 4 3 2 1 BITO R W pacnt7 pacnt6 pacnt5 pacnt4 pacnt3 pacnt2 pacnt1 pacnt0 RESET 0 0 0 0 0 0 0 0 Figure 3 20 Pulse Accumulators Count Register 0 PACNO Read or write any time The two 8 bit pulse accumulators PAC1 and PACO are cascaded to form the PACB 16 bit pulse accumulator When PACB in enabled PBEN 1 in PBCTL 30 the PACNI and PACNO registers contents are respectively the high and low byte of the PACB When PACNI overflows from FF to 00 the Interrupt flag PBOVF in PBFLG 31 is set Full count register access should take place in one clock cycle A separate read write for high byte and low byte will give a different result than accessing them as a word
29. ction of Input Capture Channels x and y M MOTOROLA 37 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe sscale Semiconductor Inc 0 Normal operation 1 The channel input x causes the same action on the channel y The port pin x and the corresponding edge detector is used to be active on the channel y TFMOD Timer Flag setting Mode Use of the TFMOD bit in the ICSYS register 2B in conjunction with the use of the ICOVW register 2A allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture By setting TFMOD in queue mode when NOVW bit is set and the corresponding capture and holding registers are emptied an input capture event will first update the related input capture register with the main timer contents At the next event the TCn data is transferred to the TCnH register The TCn is updated and the CnF interrupt flag is set In all other input capture cases the interrupt flag is set by a valid external event on PTn 0 The timer flags C3F COF in TFLG1 0E are set when a valid input capture transition on the corresponding port pin occurs 1 If in queue mode BUFEN 1 and LATQ 0 the timer flags C3F COF in TFLG1 0E are set only when a latch on the corresponding holding register occurs If the queue mode is not engaged the timer flags C3F COF are set
30. ding register At the same time the pulse accumulator is cleared 4 2 3 Modulus Down Counter The modulus down counter can be used as a time base to generate a periodic interrupt It can also be used to latch the values of the IC registers and the pulse accumulators to their holding registers The action of latching can be programmed to be periodic or only once 4 2 4 Channel Configurations Timer Channels can be configured as input capture channels or output compare channels Following are the ways a port can be configured as an output for OC The pin associated with channel 7 becomes output tied to OC7 when e TEN 1 IOS7 1 and either or both of OM7 and OL7 are set or e OC7M7 1 and IOS7 1 When masking the timer does not have to be enabled so that the pin associated with OCn becomes an output tied to OCn The pins associated with channels 0 6 become output tied to OCn n 0 6 when e TEN 1 IOSn 1 and either or both of OMn and OL n are set or e OC7Mn 1 IOS7 1 and JOSn 1 Once the pin is configured as OC its initial state is zero and its status is changed if needed on consecutive clock cycles following the write which enabled the ECT to drive the pin In other words after a pin starts to be driven by ECT OC logic it is forced low for at least one clock cycle M MOTOROLA 53 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 54 M MOTOR
31. e com Freescale SemiconductotrIn sac Block User Guide VO1 06 User Guide End Sheet M MOTOROLA 59 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc FINAL PAGE OF 60 PAGES 60 M MOTOROLA For More Information On This Product Go to www freescale com
32. en TCNT is reset from FFFF to 0000 PR2 PR1 PRO Timer Prescaler Select M MOTOROLA 25 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc These three bits specify the number of 2 stages that are to be inserted between the bus clock and the main timer counter Table 3 4 Prescaler Selection The newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero 3 3 12 TFLG1 Main Timer Interrupt Flag 1 Register offset 0E BIT7 6 5 4 3 2 1 BITO R w RESET 0 0 0 0 0 0 0 0 Figure 3 12 Main Timer Interrupt Flag 1 TFLG1 TFLGI indicates when interrupt conditions have occurred To clear a bit in the flag register write a one to the bit Use of the TFMOD bit in the ICSYS register 2B in conjunction with the use of the ICOVW register 2A allows a timer interrupt to be generated after capturing two values in the capture and holding registers instead of generating an interrupt for every capture Read anytime Write used in the clearing mechanism set bits cause corresponding bits to be cleared Writing a zero will not affect current status of the bit When TFFCA bit in TSCR register is set a read from an input capture or a write into an output compare channel 10 1F will cause the corresponding channel flag CnF to be cleared C7F COF Input Ca
33. es a request and how the MCU should acknowledge that request The interrupt vector offset and interrupt number are chip dependent 6 2 1 Channel 7 0 Interrupt This active high output will be asserted by the module to request a timer channel 7 0 interrupt to be serviced by the system controller 6 2 2 Modulus Counter Interrupt This active high output will be asserted by the module to request a modulus counter underflow interrupt to be serviced by the system controller 6 2 3 Pulse Accumulator B Overflow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator B overflow interrupt to be serviced by the system controller 6 2 4 Pulse Accumulator A Input Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A input interrupt to be serviced by the system controller M MOTOROLA 57 For More Information On This Product Go to www freescale com ECT_16B8C Block User Guidehwe scale Semiconductor Inc 6 2 5 Pulse Accumulator A Overflow Interrupt This active high output will be asserted by the module to request a timer pulse accumulator A overflow interrupt to be serviced by the system controller 6 2 6 Timer Overflow Interrupt This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller 58 M MOTOROLA For More Information On This Product Go to www freescal
34. in transition See Figure 4 2 If the corresponding NOVWn bit of the ICOVW register is cleared with a new occurrence of a capture the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value If the corresponding NOVWn bit of the ICOVW register is set the capture register or its holding register cannot be written by an event unless they are empty see 4 2 1 In queue mode reads of holding register will latch the corresponding pulse accumulator value to its holding register 4 2 1 3 Delayed IC channels There are four delay counters in this module associated with IC channels 0 3 The use of this feature is M MOTOROLA 51 For More Information On This Product Go to www freescale com ECT_16B8C Block User GuidetefRSCale Semiconductor Inc explained in the diagram and notes below maar LP LELI LI LILI LL DLY_CNT INPUT ON CHO 3 INPUT ON CHO 3 INPUT ON CHO 3 INPUT ON CHO 3 Figure 4 6 Channel Input validity with delay counter feature JAR 253 X 254 X 255 OO 256 A 256 cycles In the diagram above a delay counter value of 256 bus cycles is considered rejected rejected accepted accepted 1 Input pulses with a duration of DLY_CNT 1 cycles or shorter are rejected 2 Input pulses with a duration between DLY CNT 1 and DLY_CNT cycles may be rejected or accepted depending on their relat
35. ive alignment with the sample points 3 Input pulses with a duration between DLY_CNT 1 and DLY_CNT cycles may be rejected or accepted depending on their relative alignment with the sample points 4 Input pulses with a duration of DLY_CNT or longer are accepted 4 2 2 Pulse Accumulators There are four 8 bit pulse accumulators with four 8 bit holding registers associated with the four IC buffered channels A pulse accumulator counts the number of active edges at the input of its channel The user can prevent 8 bit pulse accumulators counting further than FF by PACMX control bit in ICSYS 2B In this case a value of FF means that 255 counts or more have occurred Each pair of pulse accumulators can be used as a 16 bit pulse accumulator See Figure 4 4 There are two modes of operation for the pulse accumulators 52 For More Information On This Product Go to www freescale com M MOTOROLA Freescale Semiconductabrihesc Block User Guide VO1 06 4 2 2 1 Pulse Accumulator latch mode The value of the pulse accumulator is transferred to its holding register when the modulus down counter reaches zero a write 0000 to the modulus counter or when the force latch control bit ICLAT is written At the same time the pulse accumulator is cleared 4 2 2 2 Pulse Accumulator queue mode When queue mode is enabled reads of an input capture holding register will transfer the contents of the associated pulse accumulator to its hol
36. lag in MCFLG register If modulus mode is enabled MODMC 1 a write to this address will update the load register with the value written to it The count register will not be updated with the new value until the next counter underflow The FLMC bit in MCCTL 26 can be used to immediately update the count register with the new value if an immediate load is desired If modulus mode is not enabled MODMC 0 a write to this address will clear the prescaler and will immediately update the counter register with the value written to it and down counts once to 0000 42 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 3 3 30 Timer Input Capture Holding Registers 0 3 Register offset 38 5 39 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TCO W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 35 Timer Input Capture Holding Register 0 TCOH Register offset 3A 3B BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R TC15 TC14 TC13 TC12 TC11 TC10 TC9 TC8 TC7 TC6 TC5 TC4 TC3 TC2 TC1 TCO W RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 36 Timer Input Capture Holding Register 1 TC1H Register offset
37. lay counter Edge detector PA1H holding register 8 bit PAC2 PACN2 Delay counter Edge detector PA2H holding register Interrupt 8 bit PAC3 PACN3 Delay counter Edge detector PA3H holding register 48 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 Figure 4 4 16 Bit Pulse Accumulators Block Diagram TIMCLK Timer clock CLK1 CLKO Clock select PAMOD Prescaled clock PCLK Interrupt CA Edge detector PACLK 65536 PACLK 256 PACLK Divide by 64 amp bus clock Interrupt Delay counter ri Edge detector PO M MOTOROLA 49 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc Figure 4 5 Block Diagram for Port7 with Output compare Pulse Accumulator A 16 bit Main Timer Edge detector Delay counter Set CnF Interrupt TCn Input Capture Reg TCnH LC Holding Reg BUFEN LATQ e TFMOD 4 2 Enhanced Capture Timer Modes of Operation The Enhanced Capture Timer has 8 Input Capture Output Compare IC OC channels same as on the HC12 standard timer timer channels TCO to TC7 When channels are selected as input capture by selecting the IOSn bit in TIOS register they are called Inpu
38. n sac Block User Guide VO1 06 Table 3 1 Module Memory Map 37 Modulus me Fecha Register Low Read Write 38 Timer Input Capture Holding Register0 High TCOH Read Write _39 Timer Input Capture Holding RegisterO Low TCOH Read Write 3A Timer Input Capture Holding Register1 High TC1H Read Write 3B Timer Input Capture Holding Register1 Low TC1H Read Write 3C Timer Input Capture Holding Register2 High TC2H Read Write 3D Timer Input Capture Holding Register2 Low TC2H Read Write GE Timer Input Capture Holding Register3 High TC3H Read Write _3F Timer Input Capture Holding Register3 Low TC3H Read Write 1 Always read 00 2 Only writable in special modes test_mode 1 3 Write to these registers have no meaning or effect during input capture 4 May be written once test_mode 0 but writes are always permitted when test_mode 0 5 Write has no effect 3 3 Register Descriptions This section consists of register descriptions in address order Each description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register diagrams in bit order 3 3 1 TIOS Timer Input Capture Output Compare Select Register Register offset _00 BIT7 6 5 4 3 2 1 BITO de 10S7 lose 10S5 10S4 10S3 10S2 10S1 1OSO RESET 0 0 0 0 0 0 0 0 Figure 3 1 Timer Input Capture Output Compare Register TIOS Read or write an
39. o www freescale com Freescale Semiconductotrin sac Block User Guide VO1 06 Table 3 7 Modulus Counter Prescaler Select 3 3 20 MCFLG 16 Bit Modulus Down Counter FLAG Register Register offset 27 BIT7 6 5 4 3 2 1 BITO R 0 0 0 POLF3 POLF2 POLF1 POLFO MCZF W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 22 16 Bit Modulus Down Counter FLAG Register MCFLG Read any time Write Only for clearing bit 7 MCZF Modulus Counter Underflow Flag The flag is set when the modulus down counter reaches 0000 A write one to this bit clears the flag Write zero has no effect Any access to the MCCNT register will clear the MCZF flag in this register when TFFCA bit in register TSCR 06 is set POLF3 POLFO First Input Capture Polarity Status This are read only bits Write to these bits has no effect Each status bit gives the polarity of the first edge which has caused an input capture to occur after capture latch has been read Each POLFn corresponds to a timer PORTn input 0 The first input capture has been caused by a falling edge 1 The first input capture has been caused by a rising edge M MOTOROLA 35 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwweg sscale Semiconductor Inc 3 3 21 ICPAR Input Control Pulse Accumulators Register Register offset 28 BIT7 6 5 4 3 2 1 BIT
40. o to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 3 3 10 TIE Timer Interrupt Enable Register Register offset 5 OC BIT7 6 5 4 3 2 1 BITO R W C71 Cel C5l Cal Cal C2l cil Col RESET 0 0 0 0 0 0 0 0 Figure 3 10 Timer Interrupt Enable Register TIE Read or write anytime The bits in TIE correspond bit for bit with the bits in the TFLG1 status register If cleared the corresponding flag is disabled from causing a hardware interrupt If set the corresponding flag is enabled to cause a interrupt 6699 C7I COI Input Capture Output Compare n Interrupt Enable 3 3 11 TSCR2 Timer System Control Register 2 Register offset OD BIT7 6 5 4 3 2 1 BITO R 0 0 0 W TOI TCRE PR2 PR1 PRO RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 11 Timer System Control Register 2 TSCR2 Read or write anytime TOI Timer Overflow Interrupt Enable 0 Interrupt inhibited 1 Hardware interrupt requested when TOF flag set TCRE Timer Counter Reset Enable This bit allows the timer counter to be reset by a successful output compare 7 event This mode of operation is similar to an up counting modulus counter 0 Counter reset inhibited and counter free runs 1 Counter reset by a successful output compare 7 If TC7 0000 and TCRE 1 TCNT will stay at 0000 continuously If TC7 FFFF and TCRE 1 TOF will never be set wh
41. ompare YA Figure 1 1 Timer Block Diagram For More Information On This Product Go to www freescale com 10C2 10C3 10C4 IOC5 IOC6 IOC7 M MOTOROLA Freescale Semiconductabrihesc Block User Guide VO1 06 Section 2 Signal Description 2 1 Overview The ECT_16B8C module has a total 8 external pins 2 2 Detailed Signal Descriptions 2 2 1 10C7 Input capture and Output compare channel 7 This pin serves as input capture or output compare for channel 7 2 2 2 lOC6 Input capture and Output compare channel 6 This pin serves as input capture or output compare for channel 6 2 2 3 lOC5 Input capture and Output compare channel 5 This pin serves as input capture or output compare for channel 7 2 2 4 10C4 Input capture and Output compare channel 4 This pin serves as input capture or output compare for channel 4 2 2 5 10C3 Input capture and Output compare channel 3 This pin serves as input capture or output compare for channel 3 2 2 6 10C2 Input capture and Output compare channel 2 This pin serves as input capture or output compare for channel 2 2 2 7 10C1 Input capture and Output compare channel 1 This pin serves as input capture or output compare for channel 1 2 2 8 IOCO Input capture and Output compare channel 0 This pin serves as input capture or output compare for channel 0 NOTE For the description of interrupts see Section 6 Interrupts M MOTOROLA 15 For More Information On This
42. ompare registers are reset to 0000 3 3 15 PACTL 16 Bit Pulse Accumulator A Control Register Register offset 20 BIT7 6 5 4 3 2 1 BITO R 0 W PAEN PAMOD PEDGE CLK1 CLKO PAOVI PAI RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 15 16 Bit Pulse Accumulator Control Register PACTL 16 Bit Pulse Accumulator A PACA is formed by cascading the 8 bit pulse accumulators PAC3 and PAC2 When PAEN is set the PACA is enabled The PACA shares the input pin with IC7 Read any time Write any time PAEN Pulse Accumulator A System Enable 0 16 Bit Pulse Accumulator A system disabled 8 bit PAC3 and PAC2 can be enabled when their related enable bits in ICPAR 28 are set Pulse Accumulator Input Edge Flag PAIF function is disabled 1 16 Bit Pulse Accumulator A system enabled The two 8 bit pulse accumulators PAC3 and PAC are cascaded to form the PACA 16 bit pulse accumulator When PACA in enabled the PACNG and PACN2 registers contents are respectively the high and low byte of the PACA PA3EN and PA2EN control bits in ICPAR 28 have no effect Pulse Accumulator Input Edge Flag PAIF function is enabled PAEN is independent from TEN With timer disabled the pulse accumulator can still function unless pulse accumulator is disabled M MOTOROLA 29 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidekge scale Semiconductor Inc PAMOD
43. pture Output Compare Channel n Flag COF can also be set by 16 bit Pulse Accumulator B PACB C3F COF can also be set by 8 bit pulse accumulators PAC3 PACO 26 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductotrin sac Block User Guide VO1 06 3 3 13 TFLG2 Main Timer Interrupt Flag 2 Register offset 5 OF BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 0 0 0 TOF W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 13 Main Timer Interrupt Flag 2 TFLG2 TFLG2 indicates when interrupt conditions have occurred To clear a bit in the flag register write the bit to one Read anytime Write used in clearing mechanism set bits cause corresponding bits to be cleared Any access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set TOF Timer Overflow Flag Set when 16 bit free running timer overflows from FFFF to 0000 This bit is cleared automatically by a write to the TFLG2 register with bit 7 set See also TCRE control bit explanation M MOTOROLA 27 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidekge scale Semiconductor Inc 3 3 14 Timer Input Capture Output Compare Registers 0 7 TCO Timer Input Capture Output Compare Register 0 Register offset 10 5 11
44. put Capture Output Compare Register7 Low Read Write TC7 16 Bit Pulse Accumulator A Control Register i 20 PACTL Read Write 21 Pulse Accumulator A Flag Register PAFLG Read Write 22 Pulse Accumulator Count Register3 PACN3 Read Write 23 Pulse Accumulator Count Register2 PACN2 Read Write 24 Pulse Accumulator Count Register1 PACN1 Read Write 25 Pulse Accumulator Count Register0 PACNO Read Write 26 16 Bit Modulus Down Counter Register MCCTL Read Write 16 Bit Modulus Down Counter Flag Register 27 MCFLG Read Write 28 Input Control Pulse Accumulator Register ICPAR Read Write 29 Delay Counter Control Register DLYCT Read Write 2A Input Control Overwrite Register ICOVW Read Write 2B Input Control System Control Register ICSYS Read Write 2C Reserved 2D Timer Test Register TIMTST Read Write 2E Reserved 2F Reserved 16 Bit Pulse Accumulator B Control Register 30 PBCTL Read Write 31 16 Bit Pulse Accumulator B Flag Register PBFLG Read Write 32 8 Bit Pulse Accumulator Holding Register3 PA3H Read Write _33 8 Bit Pulse Accumulator Holding Register2 PA2H Read Write 34 8 Bit Pulse Accumulator Holding Register1 PA1H Read Write 35 8 Bit Pulse Accumulator Holding Register0 PAOH Read Write Modulus Down Counter Count Register High c 36 MCCNT Read Write M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrI
45. r 0 PAOH M MOTOROLA 41 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidekfe amp scale Semiconductor Inc Read any time Write has no effect These registers are used to latch the value of the corresponding pulse accumulator when the related bits in register ICPAR 28 are enabled see 4 2 2 Pulse Accumulators 3 3 29 MCCNT Modulus Down Counter Count Register Register address 5 36 5 37 BIT15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 BITO R mcent mccnt meent mee nt meent meent mec nt meent mee nt meent meent mee nt meent meent meent meent W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Figure 3 34 Modulus Down Counter Count Register MCCNT Read or write any time A full access for the counter register should take place in one clock cycle A separate read write for high byte and low byte will give different result than accessing them as a word If the RDMCL bit in MCCTL register is cleared reads of the MCCNT register will return the present value of the count register If the RDMCL bit is set reads of the MCCNT will return the contents of the load register If a 0000 is written into MCCNT and modulus counter while LATQ and BUFEN in ICSYS 2B register are set the input capture and pulse accumulator registers will be latched With a 0000 write to the MCCNT the modulus counter will stay at zero and does not set the MCZF f
46. rrupts a AAA ER aud Mee Rete ee et 57 M MOTOROLA 11 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 12 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductagrln sc Block User Guide VO1 06 Section 1 Introduction 1 1 Overview The HCS12 Enhanced Capture Timer module has the features of the HCS12 Standard Timer module enhanced by additional features in order to enlarge the field of applications in particular for automotive ABS applications This design specification describes the standard timer as well as the additional features The basic timer consists of a 16 bit software programmable counter driven by a prescaler This timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform Pulse widths can vary from microseconds to many seconds A full access for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 1 2 Features e 16 Bit Buffer Register for four Input Capture IC channels e Four 8 Bit Pulse Accumulators with 8 bit buffer registers associated with the four buffered IC channels Configurable also as two 16 Bit Pulse Accumulators e 16 Bit Modulus Do
47. s down counter reaches zero or a zero is written into the count register MCCNT see 4 2 1 2 Buffered IC Channels With a latching event the contents of IC registers and 8 bit pulse accumulators are transferred to their holding registers 8 bit pulse accumulators are cleared 38 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductabrihesc Block User Guide VO1 06 3 3 25 TIMTST Timer Test Register Register offset 2D BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 0 0 0 TCBYP W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 27 Timer Test Register TIMTST Read any time Write only in special mode test_mode 1 TCB YP Main Timer Divider Chain Bypass 0 Normal operation 1 For testing only The 16 bit free running timer counter is divided into two 8 bit halves and the prescaler is bypassed The clock drives both halves directly When the high byte of timer counter TCNT 04 overflows from FF to 00 the TOF flag in TFLG2 S0F will be set 3 3 26 PBCTL 16 Bit Pulse Accumulator B Control Register Register offset 30 BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 PBEN PBOVI W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 28 16 Bit Pulse Accumulator B Control Register PBCTL Read or write any time 16 Bit Pulse Accumulator B PACB is formed by cascading the 8 bit pulse accumulators PAC1 and PACO When PBEN is se
48. scaler clock from the timer is always used as an input clock to the timer counter The change from one selected clock to the other happens immediately after these bits are written PAOVI Pulse Accumulator A Overflow Interrupt enable 0 interrupt inhibited 1 interrupt requested if PAOVF is set PAI Pulse Accumulator Input Interrupt enable 0 interrupt inhibited 1 interrupt requested if PAIF is set 30 M MOTOROLA For More Information On This Product Go to www freescale com Freescale Semiconductotrin sac Block User Guide VO1 06 3 3 16 PAFLG Pulse Accumulator A Flag Register Register offset 5 21 BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 0 0 PAOVF PAIF W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 16 Pulse Accumulator A Flag Register PAFLG Read or write anytime When the TFFCA bit in the TSCR register is set any access to the PACNT register will clear all the flags in the PAFLG register PAOVF Pulse Accumulator A Overflow Flag Set when the 16 bit pulse accumulator A overflows from FFFF to 0000 or when 8 bit pulse accumulator 3 PAC3 overflows from FF to 00 When PACMX 1 PAOVF bit can also be set if 8 bit pulse accumulator 3 PAC3 reaches FF followed by an active edge on PT3 This bit is cleared automatically by a write to the PAFLG register with bit 1 set PAIF Pulse Accumulator Input edge Flag Set when the selected edge is detected at the
49. set a write one to this bit immediately forces the contents of the input capture registers TCO to TC3 and their corresponding 8 bit pulse accumulators to be latched into the associated holding registers The pulse accumulators will be automatically cleared when the latch action occurs Writing zero to this bit has no effect Read of this bit will return always zero FLMC Force Load Register into the Modulus Counter Count Register This bit is active only when the modulus down counter is enabled MCEN 1 A write one into this bit loads the load register into the modulus counter count register This also resets the modulus counter prescaler Write zero to this bit has no effect When MODMC2 0 counter starts counting and stops at 0000 Read of this bit will return always zero MCEN Modulus Down Counter Enable 0 Modulus counter disabled 1 Modulus counter is enabled When MCEN O the counter is preset to FFFF This will prevent an early interrupt flag when the modulus down counter is enabled MCPRI MCPRO Modulus Counter Prescaler select These two bits specify the division rate of the modulus counter prescaler The newly selected prescaler division rate will not be effective until a load of the load register into the modulus counter count register occurs Table 3 7 Modulus Counter Prescaler Select MCPR1 MCPRO Prescaler division rate 0 0 1 34 M MOTOROLA For More Information On This Product Go t
50. t the PACB is enabled The PACB shares the input pin with ICO PBEN Pulse Accumulator B System Enable 0 16 bit Pulse Accumulator system disabled 8 bit PAC1 and PACO can be enabled when their related enable bits in ICPAR 28 are set M MOTOROLA 39 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwwe sscale Semiconductor Inc 1 Pulse Accumulator B system enabled The two 8 bit pulse accumulators PACI and PACO are cascaded to form the PACB 16 bit pulse accumulator When PACB in enabled the PACNI and PACNO registers contents are respectively the high and low byte of the PACB PAIEN and PAOEN control bits in ICPAR 28 have no effect PBEN is independent from TEN With timer disabled the pulse accumulator can still function unless pulse accumulator is disabled PBOVI Pulse Accumulator B Overflow Interrupt enable 0 interrupt inhibited 1 interrupt requested if PBOVF is set 3 3 27 PBFLG Pulse Accumulator B Flag Register Register offset 31 BIT7 6 5 4 3 2 1 BITO R 0 0 0 0 0 0 0 PBOVF W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 29 Pulse Accumulator B Flag Register PBFLG Read or write any time PBOVF Pulse Accumulator B Overflow Flag This bit is set when the 16 bit pulse accumulator B overflows from FFFF to 0000 or when 8 bit pulse accumulator 1 PAC1 overflows from FF to 00 This bit is cleared by a wri
51. t Capture IC channels Four IC channels are the same as on the standard timer with one capture register each which memorizes the timer value captured by an action on the associated input pin Four other IC channels in addition to the capture register have also one buffer each called holding register This permits to memorize two different timer values without generation of any interrupt Four 8 bit pulse accumulators are associated with the four buffered IC channels Each pulse accumulator has a holding register to memorize their value by an action on its external input Each pair of pulse accumulators can be used as a 16 bit pulse accumulator The 16 bit modulus down counter can control the transfer of the IC registers contents and the pulse accumulators to the respective holding registers for a given period every time the count reaches zero The modulus down counter can also be used as a stand alone time base with periodic interrupt capability 4 2 1 IC Channels The IC channels are composed of four standard IC registers and four buffered IC channels An IC register is empty when it has been read or latched into the holding register A holding register is empty when it has been read 50 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 4 2 1 1 Non Buffered IC Channels The main timer value is memorized in the IC register by a valid input pin
52. te to the PBFLG register with bit 1 set Any access to the PACNI and PACNO registers will clear the PBOVF flag in this register when TFFCA bit in register TSCR 06 is set When PACMX 1 PBOVF bit can also be set if 8 bit pulse accumulator 1 PAC1 reaches FF and followed an active edge comes on PT1 40 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 3 3 28 PAS3H PAOH 8 Bit Pulse Accumulators Holding Registers Register offset 32 BIT7 6 5 4 3 2 1 BITO R PA3H7 PAS3H6 PA3H5 PA3H4 PA3H3 PA3H2 PA3H1 PA3HO W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 30 8 Bit Pulse Accumulators Holding Register 3 PA3H Register offset 33 BIT7 6 5 4 3 2 1 BITO R PA2H7 PA2H6 PA2H5 PA2H4 PA2H3 PA2H2 PA2H1 PA2H0 W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 31 8 Bit Pulse Accumulators Holding Register 2 PA2H Register offset 34 BIT7 6 5 4 3 2 1 BITO R PA1H7 PA1H6 PA1H5 PA1H4 PA1H3 PA1H2 PA1H1 PA1HO W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 32 8 Bit Pulse Accumulators Holding Register 1 PA1H Register offset 35 BIT7 6 5 4 3 2 1 BITO R PAOH7 PAOH6 PAOH5 PAOH4 PAOH3 PAOH2 PAOH1 PAOHO W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 33 8 Bit Pulse Accumulators Holding Registe
53. the same way as for TFMOD 0 PACMX 8 Bit Pulse Accumulators Maximum Count 0 Normal operation When the 8 bit pulse accumulator has reached the value FF with the next active edge it will be incremented to 00 1 When the 8 bit pulse accumulator has reached the value FF it will not be incremented further The value FF indicates a count of 255 or more BUFEN IC Buffer Enable 0 Input Capture and pulse accumulator holding registers are disabled 1 Input Capture and pulse accumulator holding registers are enabled The latching mode is defined by LATQ control bit Write one into ICLAT bit in MCCTL 26 when LATQ is set will produce latching of input capture and pulse accumulators registers into their holding registers LATQ Input Control Latch or Queue Mode Enable The BUFEN control bit should be set in order to enable the IC and pulse accumulators holding registers Otherwise LATQ latching modes are disabled Write one into ICLAT bit in MCCTL 26 when LATQ and BUFEN are set will produce latching of input capture and pulse accumulators registers into their holding registers 0 Queue Mode of Input Capture is enabled The main timer value is memorized in the IC register by a valid input pin transition With a new occurrence of a capture the value of the IC register will be transferred to its holding register and the IC register memorizes the new timer value 1 Latch Mode is enabled Latching function occurs when modulu
54. transition If the corresponding NOVWx bit of the ICOVW register is cleared with a new occurrence of a capture the contents of IC register are overwritten by the new value If the corresponding NOV Wx bit of the ICOVW register is set the capture register cannot be written unless it is empty This will prevent the captured value to be overwritten until it is read 4 2 1 2 Buffered IC Channels There are two modes of operations for the buffered IC channels IC Latch Mode When enabled LATQ 1 the main timer value is memorized in the IC register by a valid input pin transition See Figure 4 1 The value of the buffered IC register is latched to its holding register by the Modulus counter for a given period when the count reaches zero by a write 0000 to the modulus counter or by a write to ICLAT in the MCCTL register If the corresponding NOVWn bit of the ICOVW register is cleared with a new occurrence of a capture the contents of IC register are overwritten by the new value In case of latching the contents of its holding register are overwritten If the corresponding NOVWn bit of the ICOVW register is set the capture register or its holding register cannot be written by an event unless they are empty see 4 2 1 This will prevent the captured value to be overwritten until it is read or latched in the holding register IC queue mode When enabled LATQ 0 the main timer value is memorized in the IC register by a valid input p
55. wn Counter with 4 bit Prescaler e Four user selectable Delay Counters for input noise immunity increase 1 3 Modes of Operation STOP Timer and modulus counter are off since clocks are stopped FREEZE Timer and modulus counter keep on running unless TSFRZ in TSCR 06 is set to one WAIT Counters keep on running unless TSWAI in TSCR 06 is set to one NORMAL Timer and modulus counter keep on running unless TEN in TSCR 06 respectively MCEN in MCCTL 26 are cleared M MOTOROLA 13 For More Information On This Product Go to www freescale com 1 4 Block Diagram Bus clock gt Modulus counter lt __ Interrupt Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt PA overflow interrupt PA input interrupt PB overflow interrupt 14 ECT 16B8C Block User Guidelwe scale Semiconductor Inc Prescaler 16 bit Counter 16 bit Modulus Counter HN Registers 16 bit Pulse accumulator A 16 bit Pulse accumulator B m Channel 0 Input capture Output compare Channel 1 Input capture lOCO OC1 Output compare YA Channel 2 Input capture Output compare Channel 3 Input capture Output compare Channel 4 Input capture Output compare Channel 5 Input capture YA Output compare YA Channel 6 Input capture Output compare Channel 7 Input capture YA Output c
56. ww freescale com ECT 16B8C Block User Guidelwe scale Semiconductor Inc 8 M MOTOROLA For More Information On This Product Go to www freescale com Freescale SemiconductotrIn sac Block User Guide VO1 06 List of Figures Figure 1 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 3 13 Figure 3 14 Figure 3 15 Figure 3 16 Figure 3 17 Figure 3 18 Figure 3 19 Figure 3 20 Figure 3 21 Figure 3 22 Figure 3 23 Figure 3 24 Figure 3 25 Figure 3 26 Figure 3 27 Figure 3 28 Figure 3 29 Figure 3 30 Figure 3 31 Figure 3 32 M MOTOROLA Timer Block Diagram c us keel i cad py ota Dc EE E Roue 14 Timer Input Capture Output Compare Register TIOS 19 Timer Compare Force Register CFORC 20 Output Compare 7 Mask Register OC7M 20 Output Compare 7 Data Register OC7D 21 Timer Count Register TCNT 200 00ee 21 Timer System Control Register 1 TSCR1 22 Timer Toggle On Overflow Register 1 TTOV 23 Timer Control Register 1 Timer Control Register 2 TCTL1 TCTL2 23 Timer Control Register 3 Timer Control Register 4 TCTL3 TCTL4 24 Timer Interrupt Enable Register TIE 25 Timer System Control Register 2 TSCR2 25 Main Timer Interrupt Flag 1 TFLG1 26 Main Timer Interrupt Flag 2
57. ytime IOS 7 0 Input Capture or Output Compare Channel Configuration 0 The corresponding channel acts as an input capture 1 The corresponding channel acts as an output compare M MOTOROLA 19 For More Information On This Product Go to www freescale com ECT 16B8C Block User Guidelwe sscale Semiconductor Inc 3 3 2 CFORC Timer Compare Force Register Register offset 01 BIT7 6 5 4 3 2 1 BITO Pe EK Ed AA es had RA MES ai a UB w RESET 0 0 0 0 0 0 0 0 Figure 3 2 Timer Compare Force Register CFORC Read anytime but will always return 00 1 state is transient Write anytime FOC 7 0 Force Output Compare Action for Channel 7 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output compare n to occur immediately The action taken is the same as if a successful comparison had just taken place with the TCn register except the interrupt flag does not get set NOTE A successful channel 7 output compare overrides any channel 6 0 compares If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won t get set 3 3 3 OC7M Output Compare 7 Mask Register Register offset 02 BIT7 6 5 4 3 2 1 BITO R W OC7M7 OC7M6 OC7M5 OC7M4 OC7M3 OC7M2 OC7M1 OC7MO RESET 0 0 0 0 0 0 0 0 Figure 3 3 Output Compare 7 Mask Register OC7M
Download Pdf Manuals
Related Search