IBIS Model User Guide for Z-One Devices Application Note - Digi-Key
Contents
1. voltage time V T curves as well as package resistance inductance and capacitance information The simulator changes state 1 or 0 according to the source waveform set by the user As the state changes the behavioral model for the driver and V T curves interacts with the circuit topology and receivers and a voltage versus time response is generated The response is usually presented to the user aS a waveform similar to oscilloscope waveform For more information see 1 The IBIS models are intended to be used to simulate the rise and fall waveforms for user created topologies For example the Z One system uses bidirectional open drain driver receivers for its SD Sync Data 2 serial communication buses The SD bus 16 running at a 500 KHz pulse rate while the I2C runs at up to 400 KHz The signal integrity of these signals can be affected by the PCB layout and the choice of pull ups For details regarding Power One parts see the data sheets at 2 The IBIS models are intended to help the user with PCB layout signal integrity issues and aid in choosing the proper pull up 1 Model Details Single Pin Models The ZY series Point Of Load modules POLS 2 7100 DPM are represented by simple single pin models that include only the SD pin These models contain only typical data no min max data This is sufficient for basic SD bus simulation Multi Pin Model The 2 7300 DPM is a comp2. Visit digikey com TM 1 POWEl ONe 2 Application Note SA Changing the Shape of Power IBIS Model User Guide for Z One Devices Application Note REV 1 2 MAY 14 2007 WWwwW power one com 103 2 lt 7 gt lt 1 Visit digikey com ey POWEr ONE 2 Application Note S Changing the Shape of Power TABLE OF CONTENTS OVERVIEW 3 1 MODELDETAILS Reeser 3 2 SIMULATION RECOMMENDATIONS 3 3 AVOIDING SIMULATOR CONVERGENCE ISSUES nennen 3 4 2 seo ee 3 REV 1 2 MAY 14 2007 www power one com 2of3 Visit digikey com ey power one Z One Application Note S Changing the Shape of Power Overview IBIS models are behavioral circuit models typically used for simulating the detailed signal integrity of a digital I O buffer with specific PCB loading conditions The models may be used with various commercially available simulators that have IBIS capabilities IBIS models contain current voltage l V
3. lete model that includes every device pin as well as min max data 2 Simulation Recommendations To simulate the SD waveform inject a 500 kHz pulse with a 0 75 duty cycle at the device that is the master clock for the system the DPM or the POL with the IM pin tied low Observe the simulated SD REV 1 2 MAY 14 2007 www power one com waveform at various points along the SD line Verify that the logic levels rise and fall times are meeting the data sheet requirements Note that the receivers have hysteresis as called out in the data sheets so the SD waveform does not have to be monotonic is recommended that the user begin with realistic values for trace lengths and transmission line properties A pull up resistor may be used in larger systems to improve the rise time The pull up is tied to the 3 3 V pin of the DPM Typically a 2 kOhms resistor is adequate For the 2 7300 the I2C bus be simulated by injecting a 400 KHz square wave on the SCL and SDA pins and again verifying that the data sheet values for rise and fall times and logic levels are met Per the data sheet the ZM 300 requires a typical pull up of 2 5 on the SCL and SDA lines 3 Avoiding Simulator Convergence Issues Circuits with insufficient pull up strength and or excessively large or small trace impedance are likely to cause a simulator to have convergence issues Following the simulation recommendation above will help elimi
4. nating this problem Should you have any questions please contact Rick D Newell Signal Integrity Engineer Sedona International Inc Tel 603 546 0106 e mail rnewell sedonaii com 4 References 1 IBIS I O Buffer Information Specification ANSI EIA 656 A Homepage http www eigroup org IBIS 2 Power One data sheets are available at http www power one com 30f3 5
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