TIM_16B8C Block User Guide
Contents
1. 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Depending on the TIOS bit for the corresponding channel these registers are used to latch the value of the free running counter when a defined transition is sensed by the corresponding input capture edge detector or to trigger an output action for output compare Read anytime Write anytime for output compare function Writes to these registers have no meaning or effect during input capture All timer input capture output compare registers are reset to 0000 NOTE Read Write access in byte mode for high byte should takes place before low byte otherwise it will give a different result 3 3 15 16 Bit Pulse Accumulator Control Register PACTL Register offset 0 7 6 5 4 3 2 1 0 R 0 W PAEN PAMOD PEDGE CLK1 CLKO PAOVI PAI RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved When is set the PACT is enabled The PACT shares the input pin with IOC7 Read any time Write any time PAEN Pulse Accumulator System Enable 1 Pulse Accumulator system enabled 0 16 Bit Pulse Accumulator system disabled PAEN is independent from TEN With timer disabled the pulse accumulator can still function unless pulse accumulator is disabled PAMOD Pulse Accumulator Mode This bit is active only when the Pulse Accumulator is enabled PAEN 1 1 gated time2. 1686 Block User Guide 01 08 Section 1 Introduction 1 1 Overview The basic timer consists of a 16 bit software programmable counter driven by a seven stage programmable prescaler This timer can be used for many purposes including input waveform measurements while simultaneously generating an output waveform Pulse widths can vary from microseconds to many seconds This timer contains 8 complete input capture output compare channels and one pulse accumulator The input capture function 15 used to detect a selected transition edge and record the time The output compare function is used for generating output signals or for timer software delays The 16 bit pulse accumulator is used to operate as a simple event counter or a gated time accumulator The pulse accumulator shares timer channel 7 when in event mode A full access for the counter registers or the input capture output compare registers should take place in one clock cycle Accessing high byte and low byte separately for all of these registers may not yield the same result as accessing them in one word 1 2 Features The TIM 16B8C includes these distinctive features e Eight input capture output compare channels e Clock prescaling e 16 bit counter e 16 bit pulse accumulator 1 3 Modes of Operation STOP Timer is off since clocks are stopped FREEZE Timer counter keep on running unless TSFRZ in TSCR 06 is set to one WAIT Counters keep on running unless TSW
3. 3 3 1 Timer Input Capture Output Compare Select TIOS 3 3 2 Timer Compare Force Register 3 3 3 Output Compare 7 Mask Register 7 3 3 4 Output Compare 7 Data Register 7 3 3 5 Timer Count Register 3 3 6 Timer System Control Register 1 75 1 3 3 7 Timer Toggle On Overflow Register 1 3 3 8 Timer Control Register 1 Timer Control Register 2 TCTL1 TCTL2 3 3 9 Timer Control Register 3 Timer Control Register 4 TCTL3 TCTL4 3 3 10 Timer Interrupt Enable Register 3 3 11 Timer System Control Register 2 5 2 MOTOROLA TIM 16B8C Block User Guide V01 08 3 3 12 Main Timer Interrupt Flag 1 TFLG1 3 3 13 Main Timer Interrupt Flag 2 TFLG2 3 3 14 Timer Input Capture Output Compare Registers 0 7 3 3 15 16 Pulse Accumulator Control Register 3 3 16 Pulse Accumulator Flag Register PAFLG 3 3 17 Pulse Accumulators Count Registers Section 4 Functional Description 4 1 General sibs cub 4 2 PreScalers Da 4 3 1 4 4 Output 4 5 Pulse
4. 4 5 1 Event Counter Mode 4 5 2 Gated Time Accumulation Mode Section 5 Resets 5 1 General eese nae TP A Section 6 Interrupts 6 1 6 2 Description of Interrupt Operation 6 2 1 Channel 7 0 Interrupt C 7 0 F 6 2 2 Pulse Accumulator Input Interrupt PAOVI 6 2 3 Pulse Accumulator Overflow Interrupt PAOVF 6 2 4 Timer Overflow Interrupt TOF 4 1686 Block User Guide 01 08 List of Figures Figure 1 1 Timer Block 10 Figure 4 1 Detailed Timer Block 29 MOTOROLA 5 16086 Block User Guide V01 08 6 MOTOROLA 1686 Block User Guide 01 08 List of Tables Table 3 1 Module Memory sas cote deo tence opened EE DEOR 13 Table 3 2 Compare Result Output Action 19 Table 3 3 Edge Detector Circuit Configuration 20 Table 3 4 1Prescaler Selection as eu DDS 0 bs ee os ant 21 do ou B 25 Table 3 6 Timer Clock 5 25 Table 6 1 16286 35 MOTOROLA 7 16086 Block User Guide V01 08 8 MOTOROLA
5. 1686 Block User Guide 01 08 37 User Guide End Sheet MOTOROLA 16886 Block User Guide V01 08 FINAL PAGE OF 38 PAGES 38 MOTOROLA
6. 19 Mar 2001 27 Apr 2001 03 Aug 2001 11 Oct 2001 11 Nov 2002 Revision History Version Number 01 00 01 01 01 02 01 03 01 04 01 05 01 06 01 07 01 08 MOTOROLA TIM 16B8C Block User Guide V01 08 Table of Contents Section 1 Introduction TAS SE an A ee oe dd PECADOS coe NEIN RR RSEN RENTE Beads 13 Modes oFODOratlonrs Ee SEE REPE AE 1 4 Diagrams qae do ee Section 2 Signal Description 2212 QVGIWIOW ess i Dr Ed 2 2 Detailed Signal 2 2 1 IOC7 Input capture and Output compare channel 7 2 2 2 IOC6 Input capture and Output compare channel 6 2 2 3 5 Input capture and Output compare 5 2 2 4 Input capture and Output compare channel 4 2 2 5 Input capture and Output compare channel3 2 2 6 2 Input capture and Output compare 2 2 2 7 IOC1 Input capture and Output compare channel1 2 2 8 Input capture and Output compare channelO Section 3 Memory and Registers 3 2 Module Memory 3 3 Register Descriptions ERES REGE
7. registers TCx The minimum pulse width for the input capture input is greater than two bus clocks An input capture on channel x sets the CxF flag The bit enables the CxF flag to generate interrupt requests 4 4 Output Compare Setting the I O select bit configures channel x as an output compare channel The output compare function can generate a periodic pulse with a programmable polarity duration and frequency When the timer counter reaches the value in the channel registers of an output compare channel the timer can set clear or toggle the channel pin An output compare on channel sets the CxF flag The CxI bit enables the CxF flag to generate interrupt requests The output mode level bits OMx and select set clear toggle on output compare Clearing both and OLx disconnects the pin from the output logic Setting a force output compare bit FOCx causes an output compare on channel x A forced output compare does not set the channel flag A successful output compare on channel 7 overrides output compares on all other output compare channels The output compare 7 mask register masks the bits in the output compare 7 data register The timer counter reset enable bit TCRE enables channel 7 output compares to reset the timer counter A channel 7 output compare can reset the timer counter even if the IOC7 pin is being used as the pulse accumulator input Writing to the timer port bit of a
8. 8 Bus Clock 16 Bus Clock 32 Bus Clock 64 Bus Clock 128 ajaj l oO oj oj newly selected prescale factor will not take effect until the next synchronized edge where all prescale counter stages equal zero MOTOROLA 21 16886 Block User Guide V01 08 3 3 12 Main Timer Interrupt Flag 1 TFLG1 Register offset OE Bit 7 6 5 4 3 2 1 Bit 0 R w C6F C5F C4F C3F C2F RESET 0 0 0 0 0 0 0 0 These flags are set when an input capture or output compare event occurs Clear channel flag by writing one to it Read anytime Write used in the clearing mechanism set bits cause corresponding bits to be cleared Writing a zero will not affect current status of the bit When TFFCA bit in TSCR register is set a read from an input capture or a write into an output compare channel 10 1F will cause the corresponding channel flag to be cleared C7F COF Input Capture Output Compare Channel x Flag 3 3 13 Main Timer Interrupt Flag 2 TFLG2 Register offset OF Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 0 0 0 TOF 0 RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved TFLG2 indicates when interrupt conditions have occurred To clear a bit in the flag register write the bit to one Read anytime Write used clearing mechanism set bits cause corresponding bits to be cleared Any
9. accumulation mode 0 event counter mode PEDGE Pulse Accumulator Edge Control This bit is active only when the Pulse Accumulator is enabled PAEN 1 24 MOTOROLA 1686 Block User Guide 01 08 For PAMOD bit 0 event counter mode 1 rising edges on IOC7 pin cause the count to be incremented 0 falling edges IOC7 pin cause the count to be incremented For PAMOD bit 1 gated time accumulation mode 1 IOC7 input pin low enables M bus clock divided by 64 clock to Pulse Accumulator and the trailing rising edge IOC7 sets the PAIF flag O IOC7 input pin high enables bus clock divided by 64 clock to Pulse Accumulator and the trailing falling edge IOC7 sets the PAIF flag Table 3 5 Pin Action PEDGE Pin Action 0 Falling edge Rising edge Div by 64 clock enabled with pin high level Div by 64 clock enabled with pin low level PAMOD 4 If the timer is not active TEN 0 in there is no divide by 64 since the 64 clock is generated by the timer prescaler CLK1 CLKO Clock Select Bits Table 3 6 Timer Clock Selection Timer Clock Use timer prescaler clock as timer counter clock Use PACLK as input to timer counter clock Use PACLK 256 as timer counter clock frequency Use PACLK 65536 as timer counter clock frequency For the description of PACLK please refer Figure 1 2 16 Bit Pulse Accumulator Block Diagram If the pulse accumulato
10. timer port the corresponding bit in OC7M should be cleared Table 3 2 Compare Result Output Action Action Timer disconnected from output pin logic Toggle OCx output line Clear OCx output line to zero O Set output line to To operate the 16 bit pulse accumulator independently of input capture or output compare 7 and 0 respectively the user must set the corresponding bits IOSx 1 OMx 0 and OLx 0 OC7M7 in the OC7M register must also be cleared MOTOROLA 19 16886 Block User Guide V01 08 3 3 9 Timer Control Register 3 Timer Control Register 4 TCTL3 TCTL4 Register offset 0A Bit 7 6 5 4 3 2 1 Bit 0 EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A RESET 0 0 0 0 0 0 0 0 Register offset _0B Bit 7 6 5 4 3 2 1 Bit 0 R Ww EDG3B EDG3A EDG2B EDG2A EDG1B EDGIA EDGOB EDGOA RESET 0 0 0 0 0 0 0 0 Read write anytime EDGnB EDGnA Input Capture Edge Control These eight pairs of control bits configure the input capture edge detector circuits Table 3 3 Edge Detector Circuit Configuration EDGnB EDGnA Configuration 0 0 Capture disabled 0 1 Capture on rising edges only 1 0 Capture on falling edges only 1 1 Capture on any edge rising or falling 3 3 10 Timer Interrupt Enable Register TIE Register offset Bit 7 6 5 4 3 2 1 Bit 0 R Ww RESET 0 0 0 0 0 0 0 0 Read or write anytime The bits i
11. 0 0 0 0 0 0 0 4 Timer Input Capture Output Compare Register 4 Register offset 18 9 Bitt5 14 13 12 11 10 9 8 7 6 R tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 tc4 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0 0 0 0 0 0 0 0 TC5 Timer Input Capture Output Compare Register 5 Register offset 1 1B Bit15 14 13 2 11 10 9 8 7 6 R tc5 tc5 5 5 5 5 5 5 5 5 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0 0 0 0 0 0 0 0 TC6 Timer Input Capture Output Compare Register 6 Register offset 1C 1D 5 4 3 2 1 BItO tco tco 00 tco tco 00 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit O 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit O tc2 tc2 2 2 2 2 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit O tc3 tc3 tc3 tc3 tc3 tc3 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit 0 tc4 tc4 tc4 tc4 tc4 tc4 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit 0 tc5 tc5 tc5 tc5 tc5 tc5 5 4 3 2 1 0 0 0 0 0 0 0 5 4 3 2 1 Bit O tc6 tc6 tc6 tc6 tc6 tc6 5 4 3 2 1 0 0 0 0 0 0 0 23 Bit15 14 13 12 11 10 9 8 7 6 R tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 tc6 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0 0 0 0 0 0 0 0 MOTOROLA 16886 Block User 00060 8 TC7 Timer Input Capture Output Compare Register 7 Register offset 1E Bit15 14 13 2 11 0 9 8 7 6 5 4 3 2 1 Bit O R
12. AI in TSCR 06 is set to one NORMAL Timer counter keep on running unless TEN in TSCR 06 is cleared MOTOROLA 9 1 2 5 IOC6 7 For more information see the respective functional descriptions in Section 4 of this document MOTOROLA Y vA vA vA vA TIM_16B8C Block User Guide V01 08 1 4 Block Diagrams Figure 1 1 Timer Block Diagram Channel 0 Input capture Output compare Channel 1 Input capture Output compare Channel 2 Input capture Output compare Channel 3 Input capture Output compare Channel 4 Input capture Output compare Channel 5 Input capture Output compare Channel 6 Input capture Output compare Channel 7 Input capture Output compare Prescaler 16 bit Counter Registers 16 bit Pulse accumulator Bus clock Timer overflow interrupt Timer channel 0 interrupt Timer channel 7 interrupt PA overflow interrupt PA input interrupt NOTE 10 1686 Block User Guide 01 08 Section 2 Signal Description 2 1 Overview The TIM 16 8 module has a total 8 external pins 2 2 Detailed Signal Descriptions 2 2 1 1 7 Input capture and Output compare channel 7 This pin serves as input capture or output compare for channel 77 This can also be configured as pulse accumulator input 2 2 2 lOC6 Input capture and Output co
13. C Ie TOF CH 0 CAPTURE PIN IOCO PIN LOGIC CH OCOMPARE CH 7 CAPTURE INTERRUPT LOGIC CHANNEL 1 CH 1 CAPTURE OMNES PIN LOGIC cH 1 COMPARE CHANNEL2 CHANNEL7 OM 073 7 PIN PA INPUT IOC7 PIN cu 7 compare Bus Clock PACLK PACLK 256 PACLK 65536 PRESCALER TCNT hi TCNT lo 16 BIT COUNTER CLEAR COUNTER CHANNEL 0 16 BIT COMPARATOR TCO EDGOA EDGOB COF 16 7 Een DETECT 29 PACNT hi PACNT lo 4 pg EET DETECT Bus Clock DIVIDE BY 64 Y PAOVF Y PAOVI PACLK 65536 16 BIT COUNTER EHI PACLK 256 PACLK PAMOD INTERRUPT INTERRUPT REQUEST LOGIC PAIE MOTOROLA 16886 Block User Guide V01 08 4 2 Prescaler The prescaler divides the bus clock by 1 2 4 8 16 32 64 or 128 The prescaler select bits PR 2 0 select the prescaler divisor PR 2 0 are in timer system control register 2 TSCR2 4 3 Input Capture Clearing the input output select bit configures channel x as an input capture channel The input capture function captures the time at which an external event occurs When an active edge occurs on the pin of an input capture channel the timer transfers the value in the timer counter into the timer channel
14. DOCUMENT NUMBER S12TIM16B8CV1 D TIM 16B8C Block User Guide Original Release Date 28 Jul 2000 Revised 11 Oct 2001 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part MOTOROLA Description of Changes This specification draft has been generated using BARRACUDA ECT Ref 0 5 as the referenc
15. access to TCNT will clear TFLG2 register if the TFFCA bit in TSCR register is set TOF Timer Overflow Flag Set when 16 bit free running timer overflows from FFFF to 0000 This bit is cleared automatically by a write to the TFLG2 register with bit 7 set See also TCRE control bit explanation 22 MOTOROLA 1686 Block User Guide 01 08 3 3 14 Timer Input Capture Output Compare Registers 0 7 TCO Timer Input Capture Output Compare Register O Register offset 10 1 Bit15 14 13 12 11 10 9 8 7 6 R 0 tcO tcO 0 0 tcO 0 tcO 0 0 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0 0 0 0 0 0 0 0 TC1 Timer Input Capture Output Compare Register 1 Register offset 12 3 6 1 6 0 7 7 0 8 8 0 9 9 0 10 10 0 11 11 0 12 12 0 13 13 0 14 14 0 Bit 5 1 15 0 R RESET 2 Timer Input Capture Output Compare Register 2 Register offset 14 15 15 14 13 12 11 10 9 8 7 6 R tc tc tc tc tc tc tc tc tc2 tc2 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0 0 0 0 0 0 0 0 TC3 Timer Input Capture Output Compare Register 3 Register offset 16 7 Bitt5 14 13 12 11 10 9 8 7 6 R tc3 tc3 tc13 3 tc3 tc3 tc3 tc3 tc3 tc3 15 14 13 12 11 10 9 8 7 6 RESET 0 0 0
16. e spec Changed the specs as per MSRS format Stripped the ECT functionality The timer now has only one 16 bit Pulse Accumulator compared to four 8 bit PACs in ECT As per the 5 52 0 format the specification draft has been modified using MAKO TIMER 0 1 as the reference spec and the feedback from Munich on MAKO TIMER 0 1 incorporated Gated clock ipg_tim_core_clk and its enable signal ipg_tim_core_clk_en is added for reducing power consumption Removed Block Diagram in section Signal Description Removed all internal signal description Removed Signal Properties table in the Signal Description section Removed Reset Summary table in the Resets section A new and simple block diagram has been added in place of Time Block Diagram in Introduction section Headings of all register descriptions have been changed to sub sections from figure Prescale Factor column has been modified in Table 3 4 All the pin name occurances PTx and OCx have been replaced by IOCx Module clock has been changed to bus clock Replaced references of with eg TnC to TxC MOTOROLA Author TIM 16B8C Block User Guide V01 08 Effective Date 04 Jul 2000 28 Jul 2000 16 Oct 2000 23 Feb 2001 19 Mar 2001 27 Apr 2001 03 Aug 2001 11 Oct 2001 11 Nov 2002 Revision Dates 04 Jul 2000 28 Jul 2000 16 Oct 2000 23 Feb 2001
17. ead Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Write has no effect Return 0 on read Read Write Write has no effect Return 0 on read TIM_16B8C Block User Guide V01 08 Table 3 1 Module Memory Map 17 Timer Input Capture Output Compare Register3 TC3 lo 18 Timer Input Capture Output Compare Register4 TC4 hi 19 Timer Input Capture Output Compare Register4 1A Timer Input Capture Output Compare Register5 TC5 hi 1B Timer Input Capture Output Compare Register5 5 1C Timer Input Capture Output Compare Register6 TC6 hi 1D Timer Input Capture Output Compare Register6 TC6 lo 1E Timer Input Capture Output Compare Register7 TC7 hi 1F Timer Input Capture Output Compare Register7 TC7 lo 20 16 Bit Pulse Accumulator Control Register PACTL 21 Pulse Accumulator Flag Register PAFLG 22 Pulse Accumulator Count Register PACNT hi 23 Pulse Accumulator Count Register 24 2 Reserved 2D Timer Test Register TIMTST 2E 2F Reserved NOTE 1 Always read 00 2 Only writable in special modes test mode 1 3 Write to these registers have no meaning or effect during input capture 3 3 Register Descriptions This section consists of register descriptions in address
18. et Use Access _00 Timer Input Capture Output Compare Select TIOS Read Write 01 Timer Compare Force Register CFORC Read Write 02 Output Compare 7 Mask Register OC7M Read Write 3 Output Compare 7 Data Register OC7D Read Write 04 Timer Count Register TCNT hi Read Write 05 Timer Count Register TCNT lo Read Write 6 Timer System Control Register1 TSCR1 Read Write 07 Timer Toggle Overflow Register TTOV Read Write 08 Timer Control Register1 TCTL1 Read Write 09 Timer Control Register2 TCTL2 Read Write 0A Timer Control Register3 TCTL3 Read Write 8 Timer Control Register4 TCTL4 Read Write 0C Timer Interrupt Enable Register TIE Read Write 00 Timer System Control Register2 TSCR2 Read Write 5 Main Timer Interrupt Flag1 TFLG1 Read Write 5 Main Timer Interrupt 02 TFLG2 Read Write Timer Input Capture Output Compare RegisterO 10 TCO hi Read Write Timer Input Capture Output Compare RegisterO Md 11 TCO lo Read Write Timer Input Capture Output Compare Register1 4 3 12 TC1 hi Read Write Timer Input Capture Output Compare Register1 4 3 13 TC1 lo Read Write Timer Input Capture Output Compare Register2 4 3 14 TC2 hi Read Write Timer Input Capture Output Compare Register 4 3 15 TC2 lo Read Write Timer Input Capture Output Compare Register3 3 16 TC3 hi Read Write MOTOROLA 13 Read Write R
19. g to generate interrupt requests NOTE The pulse accumulator counter can operate in event counter mode even when the timer enable bit TEN is clear 4 5 2 Gated Time Accumulation Mode Setting the PAMOD bit configures the pulse accumulator for gated time accumulation operation An active level on the PACNT input pin enables a divided by 64 clock to drive the pulse accumulator The PEDGE bit selects low levels or high levels to enable the divided by 64 clock The trailing edge of the active level at the IOC7 pin sets PAIF The PAI bit enables the PAIF flag to generate interrupt requests The pulse accumulator counter register reflect the number of pulses from the divided by 64 clock since the last reset NOTE The timer prescaler generates the divided by 64 clock If the timer is not active there is no divided by 64 clock M MOTOROLA 31 16086 Block User Guide V01 08 32 MOTOROLA 1686 Block User Guide 01 08 Section 5 Resets 5 1 General The reset state of each individual bit is listed within the Register Description section see Section 3 Memory Map and Registers which details the registers and their bit fields MOTOROLA 33 16086 Block User Guide V01 08 34 MOTOROLA 1686 Block User Guide 01 08 Section 6 Interrupts 6 1 General This section describes interrupts originated by the TIM 16B8C block Table 6 1 lists the interrupts generated by the TIM_16B8C to comm
20. gister OC7M Register offset _02 Bit 7 Bit 0 Read or write anytime Setting the OC7Mx x ranges from 0 to 6 will set the corresponding port to be an output port when the corresponding TIOSx x ranges from 0 to 6 bit is set to be an output compare MOTOROLA 15 16886 Block User Guide V01 08 NOTE A successful channel 7 output compare overrides any channel 6 0 compares For each OC7M bit that is set the output compare action reflects the corresponding OC7D bit 3 3 4 Output Compare 7 Data Register OC7D Register offset _03 Bit 7 Bit O Read or write anytime RESET A channel 7 output compare can cause bits in the output compare 7 data register to transfer to the timer port data register depending on the output compare 7 mask register 3 3 5 Timer Count Register TCNT Register of set 04 05 15 14 11 Bit O R tent tent tent tent tent ne a p get ie E Es 14 13 12 11 10 RESET 0 16 bit main timer is up counter A full access for the counter register should take place in one clock cycle A separate read write for high byte and low byte will give a different result than accessing them as a word Read anytime Write has no meaning or effect in the normal mode only writable in special modes test mode 1 The period of the first count after a write to the TCNT registers may be a different size because the write is not synchronized with the prescale
21. mpare channel 6 This pin serves as input capture or output compare for channel 6 2 2 3 5 Input capture and Output compare channel 5 This pin serves as input capture or output compare for channel 7 2 2 4 4 Input capture and Output compare channel 4 This pin serves as input capture or output compare for channel 4 2 2 5 Input capture and Output compare channel This pin serves as input capture or output compare for channel 3 2 2 6 2 Input capture and Output compare channel 2 This pin serves as input capture or output compare for channel 2 2 2 7 1 Input capture and Output compare channel 1 This pin serves as input capture or output compare for channel 1 2 2 8 Input capture and Output compare channel 0 This pin serves as input capture or output compare for channel 0 NOTE For the description of interrupts see Section 6 Interrupts MOTOROLA 11 16086 Block User Guide V01 08 12 MOTOROLA 1686 Block User Guide V01 08 Section 3 Memory Map and Registers 3 1 Overview This section provides a detailed description of all memory and registers 3 2 Module Memory Map The memory map for the TIM_16B8C module is given below in Table 3 1 The Address listed for each register is the address offset The total address for each register is the sum of the base address for the TIM_16B8C module and the address offset for each register Table 3 1 Module Memory Map Offs
22. n TIE correspond bit for bit with the bits in the status register If cleared the corresponding flag is disabled from causing a hardware interrupt If set the corresponding flag is enabled to cause a interrupt C7I COI Input Capture Output Compare x Interrupt Enable 20 MOTOROLA 16886 Block User Guide V01 08 3 3 11 Timer System Control Register 2 TSCR2 Register offset 00 Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 TCRE PR2 RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Read or write anytime TOI Timer Overflow Interrupt Enable 1 Hardware interrupt requested when TOF flag set O Interrupt inhibited TCRE Timer Counter Reset Enable This bit allows the timer counter to be reset by a successful output compare 7 event This mode of operation is similar to an up counting modulus counter 1 Counter reset by a successful output compare 7 O Counter reset inhibited and counter free runs If TC7 0000 and 1 TCNT will stay at 0000 continuously If TC7 and TCRE 1 TOF will never be set when TCNT is reset from FFFF to 0000 PR2 PRO Timer Prescaler Select These three bits select the frequency of the timer prescaler clock derived from the Bus Clock as shown Table 3 4 Table 3 4 Timer Clock Selection PRO Timer Clock Bus Clock 1 Bus Clock 2 Bus Clock 4 Bus Clock
23. n output compare pin does not affect the pin state The value written is stored in an internal latch When the pin becomes available for general purpose output the last value written to the bit appears at the pin 4 5 Pulse Accumulator The pulse accumulator PACNT is a 16 bit counter that can operate in two modes Event counter mode Counting edges of selected polarity on the pulse accumulator input pin PAI 30 MOTOROLA 1686 Block User Guide 8 Gated time accumulation mode Counting pulses from divide by 64 clock The PAMOD bit selects the mode of operation The minimum pulse width for the PAI input is greater than two bus clocks 4 5 1 Event Counter Mode Clearing the PAMOD bit configures PACNT for event counter operation An active edge on the pin increments the pulse accumulator counter The PEDGE bit selects falling edges or rising edges to increment the count NOTE The PACNT input and timer channel 7 use the same To use the IOC7 disconnect it from the output logic by clearing the channel 7 output mode and output level bits OL7 Also clear the channel 7 output compare 7 mask bit OC7M7 The Pulse Accumulator counter register reflect the number of active input edges on the PACNT input pin since the last reset The PAOVF bit when the accumulator rolls over from FFFF to 0000 The pulse accumulator overflow interrupt enable PAOVI enables the PAOVF fla
24. n this register when TFFCA bit in register TSCR 06 is set 3 3 17 Pulse Accumulators Count Registers PACNT Register offset 22 23 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 Bit 0 R pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt pacnt W 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESET 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Read or write any time These registers contain the number of active input edges on its input pin since the last reset When PACNT overflows from FFFF to 0000 the Interrupt flag PAOVF in PAFLG 521 is set Full count register access should take place in one clock cycle A separate read write for high byte and low byte will give a different result than accessing them as a word NOTE Reading the pulse accumulator counter registers immediately after an active edge on the pulse accumulator input pin may miss the last count since the input has to be synchronized with the bus clock first 26 MOTOROLA 16886 Block User Guide V01 08 27 MOTOROLA 16086 Block User Guide V01 08 28 MOTOROLA 1686 Block User Guide V01 08 Section 4 Functional Description 4 1 General This section provides a complete functional description of the timer TIM 16B8C block Please refer to the detailed timer block diagram in Figure 4 1 as necessary Figure 4 1 Detailed Timer Block Diagram channel 7 output compare
25. order Each description includes a standard register diagram with an associated figure number Details of register bit and field function follow the register M MOTOROLA diagrams in bit order 14 1686 Block User Guide V01 08 3 3 1 Timer Input Capture Output Compare Select TIOS Register offset 5 00 Bit 7 Bit O cece Read or write anytime IOS 7 0 Input Capture or Output Compare Channel Configuration 1 The corresponding channel acts as an output compare 0 The corresponding channel acts as an input capture 3 3 2 Timer Compare Force Register CFORC Register offset _01 Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 0 0 0 0 W FOC7 FOC6 5 FOC4 FOC3 FOC2 FOC1 FOCO RESET 0 0 0 0 0 0 0 0 Read anytime but will always return 00 1 state is transient Write anytime FOC 7 0 Force Output Compare Action for Channel 7 0 A write to this register with the corresponding data bit s set causes the action which is programmed for output compare x to occur immediately The action taken is the same as if a successful comparison had just taken place with the TCx register except the interrupt flag does not get set NOTE successful channel 7 output compare overrides any channel 6 0 compares If forced output compare on any channel occurs at the same time as the successful output compare then forced output compare action will take precedence and interrupt flag won t get set 3 3 3 Output Compare 7 Mask Re
26. r clock 16 MOTOROLA 1686 Block User Guide 01 08 3 3 6 Timer System Control Register 1 TSCR1 Register offset 06 Bit 7 6 5 4 3 2 1 Bit 0 R 0 0 0 0 T TEN TSWAI TSFRZ TFFCA RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Read or write anytime TEN Timer Enable 1 Allows the timer to function normally 0 Disables the main timer including the counter Can be used for reducing power consumption If for any reason the timer is not active there is no 64 clock for the pulse accumulator since the 64 is generated by the timer prescaler TSWAI Timer Module Stops While in Wait 1 Disables the timer module when the MCU is in the wait mode Timer interrupts cannot be used to get the MCU out of wait 0 Allows the timer module to continue running during wait TSWAI also affects pulse accumulator TSFRZ Timer Stops While in Freeze Mode 1 Disables the timer counter whenever the MCU is in freeze mode This is useful for emulation 0 Allows the timer counter to continue running while in freeze mode TSFRZ does not stop the pulse accumulator TFFCA Timer Fast Flag Clear 1 For TFLGI SOE a read from an input capture or write to the output compare channel 10 1F causes the corresponding channel flag CnF to be cleared For TFLG2 0F any access to the TCNT register 04 05 clears the TOF flag Any access to the PACNT registers 22 23 clears
27. r is disabled PAEN 0 the prescaler clock from the timer is always used as an input clock to the timer counter The change from one selected clock to the other happens immediately after these bits are written PAOVI Pulse Accumulator Overflow Interrupt enable 1 interrupt requested if PAOVF is set O interrupt inhibited PAI Pulse Accumulator Input Interrupt enable 1 interrupt requested 11 PAIF is set O interrupt inhibited MOTOROLA 25 16886 Block User Guide V01 08 3 3 16 Pulse Accumulator Flag Register PAFLG Register offset 21 BIT 7 6 5 4 3 2 1 BIT 0 R 0 0 0 0 0 0 PAOVF PAIF W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Read or write anytime When the TFFCA bit in the TSCR register is set any access to the PACNT register will clear all the flags in the PAFLG register PAOVF Pulse Accumulator Overflow Flag Set when the 16 bit pulse accumulator overflows from to 0000 This bit is cleared automatically by a write to the PAFLG register with bit 1 set PAIF Pulse Accumulator Input edge Flag Set when the selected edge is detected at the IOC7 input pin In event mode the event edge triggers PAIF and in gated time accumulation mode the trailing edge of the gate signal at the IOC7 input pin triggers PAIF This bit is cleared by a write to the PAFLG register with bit O set Any access to the PACNT register will clear all the flags i
28. the PAOVF and PAIF flags in the PAFLG register 21 This has the advantage of eliminating software overhead in a separate clear sequence Extra care is required to avoid accidental flag clearing due to unintended accesses 0 Allows the timer flag clearing to function normally M MOTOROLA 17 16886 Block User Guide V01 08 3 3 7 Timer Toggle On Overflow Register 1 TTOV Register offset 07 Bit 7 6 5 4 3 2 1 Bit 0 R TOV7 TOV6 TOV5 4 2 TOVO RESET 0 0 0 0 0 0 0 0 Read or write anytime TOVx Toggle On Overflow Bits toggles output compare pin on overflow This feature only takes effect when in output compare mode When set it takes precedence over forced output compare but not channel 7 override events 1 Toggle output compare pin on overflow feature enabled O Toggle output compare pin on overflow feature disabled 3 3 8 Timer Control Register 1 Timer Control Register 2 TCTL1 TCTL2 Register 08 Bit O Register offset 09 Bit 7 Bit 0 Read or write anytime RESET RESET OMx Output Mode OLx Output Level These eight pairs of control bits are encoded to specify the output action to be taken as a result of a successful OCx compare When either OMx or OLx 18 one the pin associated with OCx becomes an output tied to OCx 18 M MOTOROLA 1686 Block User Guide 01 08 NOTE enable output action by OMx and OLx bits on
29. unicate with the MCU Table 6 1 16B8C Interrupts Interrupt Offset Vector Priority Source Description C 7 0 F E Timer Channel 7 0 Active high timer channel interrupts 7 0 PAOVI Pulse ar Active high pulse accumulator input interrupt PAOVF Accumulator Pulse overflow interrupt Overflow TOF E Timer Overflow Timer Overflow interrupt NOTES 1 Chip Dependent 6 2 Description of Interrupt Operation The TIM_16B8C uses a total of 11 interrupt vectors The interrupt vector offsets and interrupt numbers are chip dependent 6 2 1 Channel 7 0 Interrupt C 7 0 F This active high outputs will be asserted by the module to request a timer channel 7 0 interrupt to be serviced by the system controller 6 2 2 Pulse Accumulator Input Interrupt This active high output will be asserted by the module to request a timer pulse accumulator input interrupt to be serviced by the system controller 6 2 3 Pulse Accumulator Overflow Interrupt PAOVF This active high output will be asserted by the module to request a timer pulse accumulator overflow interrupt to be serviced by the system controller 6 2 4 Timer Overflow Interrupt TOF This active high output will be asserted by the module to request a timer overflow interrupt to be serviced by the system controller MOTOROLA 35 16086 Block User Guide V01 08 36 MOTOROLA
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