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MSP430x2xx Family User's Guide (Rev. E

1. y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 98 7 6 5 4 3 2 OSR 256 LSBACC 1 SD16UNI 1 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 16 5 4 3 2 OSR 256 LSBACC 0 SD16UNI 0 Y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 98 7 6 5 4 3 2 OSR 256 LSBACC 1 SD16UNI 0 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 16 5 4 3 2 OSR 128 LSBACC 0 SD16UNI 1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113112111 10 9 8 7 6 5 4 3 2 OSR 128 LSBACC 1 SD16UNI 1 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 16 5 4 3 2 OSR 128 LSBACC 0 SD16UNI 0 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 OSR 128 LSBACC 1 SD16UNI 0 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 OSR 64 LSBACC 0 SD16UNI 1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 98 7 6 5 4 3 2 OSR 64 LSBACC 1 SD16UNI 1 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 87 6 5 4 3 2 O
2. REFON INCHx 0Ah x VeREF VREF on 15Vor2 5V AVcc VREF VEREF Reference gt AVoc INCHx SREF1 i avss K 20O SREFO ADC120SC AO SREF2 1 of ADC120N ADC12SSELx A1 AS ADC12DIVx A3 00 Pes 01 ACLK A5 Divider AS 12 bit SAR Meda o ee rt 11 SMCLK Conve gt ADC12CLK BUSY GND SHSx GND SHP SHTOx ISSH GND y ENC GND ad 00 Ha ADC12SC Sample Timer 01 TA 4 11024 x AVoo SAMPCON 7 dl Be a 1 TB1 SHT1x MSC L INCHx 0Bh Ref_x ADC12MEMO ADC12MCTLO R CSTARTADDx z L 16x12 16x8 i Memory Memory el Buffer Control s a CONSEQx i n ni i VW v ADC12MEM15 ADC12MCTL15 AVss ADC12 21 3 ADC12 Operation 21 2 ADC12 Operation The ADC12 module is configured with user software The setup and operation of the ADC12 is discussed in the following sections 21 2 1 12 Bit ADC Core The ADC core converts an analog input to its 12 bit digital representation and stores the result in conversion memory The core uses two programmable selectable voltage levels Vp and Vp_ to define the upper and lower limits of the conversion The digital output Napc is full scale OFFFh when the input signal is equal to or higher than Vp and zero when the input signal is equal to or lower than Vp The input channel and the reference voltage levels Vp and Vp_ are defined in the conversion control memory The conversion formula for the ADC result Napc is Vin V MA RSs PS Na
3. UCMSB UC7BIT UCSSELx Bit Clock Generator UCxBRx UCCKPH UCCKPL N A LK AGR Prescaler Divider Clock Direction S SMCLK Phase and Polarity SMCLK UCMSB UC7BIT o n UCxSIMO Transmit Shift Register o gt lt gt UCMODEx T it Buffer UCxTXBUF DAR ransmit Buffer x Transmit Enable lt 9 Control Set UCFE Transmit State Machine 16 4 Universal Serial Communication Interface SPI Mode gt gt Set UCXTXIFG 16 3 USCI Operation SPI Mode USCI Operation SPI Mode In SPI mode serial data is transmitted and received by multiple devices using a shared clock provided by the master An additional pin UCxSTE is provided to enable a device to receive and transmit data and is controlled by the master Three or four signals are used for SPI data exchange OU UCxSIMO Y UCxSOMI Y UCxCLK Y UCxSTE Table 16 1 UCxSTE Operation UCMODEx 01 10 low Slave in master out Master mode UCxSIMO is the data output line Slave mode UCxSIMO is the data input line Slave out master in Master mode UCxSOM is the data input line Slave mode UCxSOMI is the data output line USCI SPI clock Master mode UCxCLK is an output Slave mode UCxCLK is an input Slave transmit enable Used in 4 pin mode to allow multiple masters on a single bus Not used in 3 pin mode Table 16 1 describes the UCxSTE operation UCxSTE Active State UCxSTE Slave Master 0 inactive active high
4. PC 6 eco PC 4 Interrupt Request PC 2 a PC Interrupt Accepted PC 2 PC 2 is Stored PC PCi eco Onto Stack PC 4 PCi 2 PC 6 PCi 4 PC 8 e v PCi n 4 PCi n 2 PCi n RETI RISC 16 Bit CPU 3 57 Instruction Set RLA W RLA B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 3 14 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt OCOOOh before operation is performed the result has changed sign Figure 3 14 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 AAA Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multi
5. EQUO i i 1 UP DOWN I i i I i I i OUTE6 Signal Timer_B 13 3 Timer_B Operation 13 2 Timer_B Operation The Timer_B module is configured with user software The setup and operation of Timer_B is discussed in the following sections 13 2 1 16 Bit Timer Counter TBR Length The 16 bit timer counter register TBR increments or decrements depending on mode of operation with each rising edge of the clock signal TBR can be read or written with software Additionally the timer can generate an interrupt when it overflows TBR may be cleared by setting the TBCLR bit Setting TBCLR also clears the clock divider and count direction for up down mode AAA A AA A Y E aos w _w oaaouo_w_ ss Note Modifying Timer_B Registers It is recommended to stop the timer before modifying its operation with exception of the interrupt enable interrupt flag and TBCLR to avoid errant operating conditions When the timer clock is asynchronous to the CPU clock any read from TBR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TBR will take effect immediately Timer_B is configurable to operate as an 8 10 12 or 1
6. USISTTIFG i USISSELx a SCLK ACLK SMCLK SMCLK SWCLK TAO TA1 TA2 E USISCLREL O e USIMSTH 0 af USIDIVx HOLD Clock Divider USICLK 1 2 4 8 128 14 4 Universal Serial Interface USI Operation 14 2 USI Operation The USI module is a shift register and bit counter that includes logic to support SPI and IC communication The USI shift register USISR is directly accessible by software and contains the data to be transmitted or the data that has been received The bit counter counts the number of sampled bits and sets the USI interrupt flag USIIFG when the USICNTx value becomes zero either by decrementing or by directly writing zero to the USICNTx bits Writing USICNTx with a value gt 0 automatically clears USIIFG when USIIFGCC 0 otherwise USIIFG is not affected The USICNTx bits stop decrementing when they become 0 They will not underflow to OFFh Both the counter and the shift register are driven by the same shift clock On a rising shift clock edge USICNTx decrements and USISR samples the next bit input The latch connected to the shift register s output delays the change of the output to the falling edge of shift clock It can be made transparent by setting the USIGE bit This setting will immediately output the MSB or LSB of USISR to the SDO pin depending on the USILSB bit 14 2 1 USI Initialization While the USI software reset bit USISWRST is set the flags USIIFG USI
7. 15 0 O 31 20 19 0 fH E 16 Bit MSP430X CPU 4 143 Extended Instructions RRUM A RRUM W Syntax Operation Description Status Bits Mode Bits Example Example Rotate Right Unsigned the 20 bit CPU register content Rotate Right Unsigned the 16 bit CPU register content RRUM A n Rdst 1 lt n lt 4 RRUM W n Rdst or RRUM n Rdst 1 lt n lt 4 O MSB gt MSB 1 gt LSB 1 gt LSB gt C The destination operand is shifted right by one two three or four bit positions as shown in Figure 4 53 Zero is shifted into the MSB the LSB is shifted into the carry bit RRUM works like an unsigned division by 2 4 8 or 16 The word instruction RRUM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The unsigned address word in R5 is divided by 16 RRUM A 4 R5 R5 R5 4 R5 16 The word in R6 is shifted right by one bit The MSB R6 15 is loaded with 0 RRUM W 1 R6 R6 R6 2 R6 19 15 0 Figure 4 53 Rotate Right Unsigned RRUM W and RRUM A 16 19 15 19 0 e E 4 144 16 Bit MSP430X CPU RRUX A RRUX W RRUX B Syntax Operation Descript
8. 1 UCTR 0 Receiver 2 UCTXSTT 1 3 UCBxTXIFG 0 UCTXSTP 0 1 UCTR 1 Transmitter 2 UCTXSTT 1 UCBxTXIFG 1 UCBxTXBUF discarded 1 UCTR 0 Receiver 2 UCTXSTT 1 UCNACKIFG 1 UCBxTXIFG 0 UCBxTXBUF discarded UCALIFG 1 UCMST 0 UCSTTIFG 0 UCALIFG 1 UCMST 0 UCSTTIFG 0 UCALIFG 1 UCMST 0 VOTRO peeved UCSTT Wena if I call UCBxTXIFG 0 UCSTPIFG 0 USCI continues as Slave Receiver Universal Serial Communication Interface 1 C Mode USCI Operation C Mode 12C Master Receiver Mode After initialization master receiver mode is initiated by writing the desired slave address to the UCBxI2CSA register selecting the size of the slave address with the UCSLA10 bit clearing UCTR for receiver mode and setting UCTXSTT to generate a START condition The USCI module checks if the bus is available generates the START condition and transmits the slave address As soon as the slave acknowledges the address the UCTXSTT bit is cleared After the acknowledge of the address from the slave the first data byte from the slave is received and acknowledged and the UCBxRXIFG flag is set Data is received from the slave ss long as UCTXSTP or UCTXSTT is not set If UCBxRXBUF is not read the master holds the bus during reception of the last data bit and until the UCBxRXBUF is read If the slave does not acknowledge th
9. 4 8 16 64 x ADC10CLK If x 0 then x INCH else x x 1 Sample Input Channel Ax If x 0 then x INCH 12 x ADC10CLK ENC 0 else x x 1 ana x 0 MSC 1 and ENC 1 1 x ADC10CLK or x 0 Conversion Completed Result to ADC10MEM ADC10IFG is Set x input channel Ax ADC10 20 13 ADC10 Operation Using the MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible a multiple sample and convert function is available When MSC 1 and CONSEQx gt 0 the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC10 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are O Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the ADC10BUSY bit until reset before clearing ENC Y Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion Lj Resetti
10. Last byte is not acknowledged Reception of the general call address UCTR 0 Receiver UCSTTIFG 1 UCGC 1 Arbitration lost as master and addressed as slave 12C Slave Receiver Mode UCBxRXIFG 1 USCI Operation C Mode Bus stalled SCL held low if UCBxRXBUF not read Read data from UCBxRXBUF Refer to Slave Transmitter Timing Diagram UCALIFG 1 UCMST 0 UCTR 0 Receiver UCSTTIFG 1 UCGC 1 if general call UCBxTXIFG 0 UCSTPIFG 0 UCTXNACK 1 UCTXNACK 0 Bus not stalled even if UCBxRXBUF not read Universal Serial Communication Interface C Mode 17 13 USCI Operation 2C Mode 12C Slave 10 bit Addressing Mode The 10 bit addressing mode is selected when UCA10 1 and is as shown in Figure 17 11 In 10 bit addressing mode the slave is in receive mode after the full address is received The USCI module indicates this by setting the UCSTTIFG flag while the UCTR bit is cleared To switch the slave into transmitter mode the master sends a repeated START condition together with the first byte of the address but with the R W bit set This will set the UCSTTIFG flag if it was previously cleared by software and the USCI modules switches to transmitter mode with UCTR 1 Figure 17 11 12C Slave 10 bit Addressing Mode 17 14 Slave Receiver Reception o
11. Mid Scale Output 0 DAC Data 0800h 2048 0 07FFh 2047 23 6 DAC12 DAC12 Operation 23 2 5 DAC12 Output Amplifier Offset Calibration The offset voltage of the DAC12 output amplifier can be positive or negative When the offset is negative the output amplifier attempts to drive the voltage negative but cannot do so The output voltage remains at zero until the DAC12 digital input produces a sufficient positive output voltage to overcome the negative offset voltage resulting in the transfer function shown in Figure 23 4 Figure 23 4 Negative Offset Output Voltage 0 Negative Offset a DAC Data When the output amplifier has a positive offset a digital input of zero does not result in a zero output voltage The DAC12 output voltage reaches the maximum output level before the DAC12 data reaches the maximum code This is shown in Figure 23 5 Figure 23 5 Positive Offset Output Voltage o DAC Data Full Scale Code The DAC12 has the capability to calibrate the offset voltage of the output amplifier Setting the DAC12CALON bit initiates the offset calibration The calibration should complete before using the DAC12 When the calibration is complete the DAC12CALON bit is automatically reset The DAC12AMPx bits should be configured before calibration For best calibration results port and CPU activity should be minimized during calibration DAC12 23 7 DAC12 Operation 23 2 6 Grouping Multiple D
12. 16 Bit MSP430X CPU 4 67 MSP430 Instructions BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination in lower 64K address space BR dst dst gt PC MOV dst PC An unconditional branch is taken to an address anywhere in the lower 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR EXEC Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC _ Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting
13. CMPA Rsrc Rdst Compare source to destina Himm20 Rdst tion register SUBA Rsrc Rdst Subtract source from des SS imm20 Rdst tination register 16 Bit MSP430X CPU 4 53 MSP430X Extended Instructions MSP430X Instruction Execution The number of CPU clock cycles required for an MSP430X instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to MCLK MSP430X Format II Single Operand Instruction Cycles and Lengths Table 4 17 lists the length and the CPU cycles for all addressing modes of the MSP430X extended single operand instructions Table 4 17 MSP430X Format II Instruction Cycles and Length Execution Cycles Length of Instruction Words Instruction Rn Rn Rn N X Rn EDE amp EDE RRAM n 1 Z E E F RRCM n 1 5 E RRUM n 1 2 5 z E RLAM n 1 2 z E E 2 a PUSHM 2 n 1 z z E E PUSHM A 2 2n 1 as z POPM 2 n 1 gt 7 E 2 POPM A 2 2n1 E z CALLA 4 1 5 1 5 1 4 2 6t 2 6 2 6 2 RRAX B 14n 2 4 2 4 2 z 5 3 5 3 5 3 RRAX A 1 n 2 6 2 6 2 7 3 7 3 7 3 RRCX B 14n 2 4 2 4 2 z 5 3 5 3 5 3 RRCX A 1 n 2 6 2 6 2 z 7 3 7 3 7 3 PUSHX B 4 2 4 2 4 2 4 3 5t 3 5 3 5 3 PUSHX A 5 2 6 2 6 2 6 3 71 3 7 3 7 3 POPX B 3 2 A 5 3 5 3 5 3 POPX A 4 2 2 2 7 3 7 3 7 3 T Add one cycle when Rn SP MSP430X Format l Double Operand Instruction Cycles and Lengths Table 4 18 lists the length and CPU cyc
14. Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 gt dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte STATUS of a process is incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMP B 11 STATUS JEQ OVFL 16 Bit MSP430X CPU 4 81 MSP430 Instructions INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 gt dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or O7FFFh reset otherwise Set if dst contained 07Eh or 07Fh re
15. Indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 BR R5 Branch to the address contained in the word pointed to by R5 and increment pointer in R5 afterwards The next time S W flow uses R5 pointer it can alter program execution due to access to next address in a table pointed to by R5 Core instruction MOV R5 PC Indirect indirect R5 with autoincrement BR X R5 Branch to the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X 3 28 RISC 16 Bit CPU CALL Syntax Operation Description Status Bits Example Instruction Set Subroutine CALL dst dst gt tmp dst is evaluated and stored SP 2 gt SP PC gt SP PC updated to TOS tmp gt PC dst saved to PC A subroutine call is made to an address anywhere in the 64K address space All addressing modes can be used The return address the address of the following instruction is stored on the stack The call instruction is a word instruction Status bits are not affected Examples for all addressing modes are given CALL CALL CALL CALL CALL CALL CALL EXEC _ Call on label EXEC or immediate address e g 0A4h SP 2 gt SP PC 2 gt SP PC gt PC EXEC Call on the address contai
16. OAPx OAPMx OAADCx rw 0 Bits 7 6 Bits 5 4 Bits 3 2 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Inverting input select These bits select the input signal for the OA inverting input 00 OAxI0 01 OAxli 10 OAxIA see the device specific data sheet for connected signal 11 OAxIB see the device specific data sheet for connected signal Non inverting input select These bits select the input signal for the OA non inverting input 00 OAxI0 01 OAOI1 10 OAxIA see the device specific data sheet for connected signal 11 OAxIB see the device specific data sheet for connected signal Slew rate select These bits select the slew rate vs current consumption for the OA 00 Off output high Z 01 Slow 10 Medium 11 Fast OA output select These bits together with the OAFCx bits control the routing of the OAx output when OAPMx gt 0 When OAFCx 0 00 OAxOUT connected to external pins and ADC input A1 A3 or A5 01 OAxOUT connected to external pins and ADC input A12 A13 or A14 10 OAxOUT connected to external pins and ADC input A1 A3 or A5 11 OAxOUT connected to external pins and ADC input A12 A13 or A14 When OAFCx gt 0 00 OAxOUT used for internal routing only 01 OAxOUT connected to external pins and ADC input A12 A13 or A14 10 OAxOUT connected to external pins and ADC input A1 A3 or A5 11 OAxOUT connected internally to ADC input A12 A13 or A14 External A12 A13 or A14 pin connections are disconnect
17. RLA W RLA B Syntax Operation Emulation Description Rotate left arithmetically Rotate left arithmetically RLA dst or RLA W dst RLA B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADD dst dst ADD B dst dst The destination operand is shifted left one position as shown in Figure 4 38 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLA instruction acts as a signed multiplication by 2 An overflow occurs if dst gt 04000h and dst lt OCOOOh before operation is performed the result has changed sign Figure 4 38 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example Example Word 15 0 AAA Byte 7 0 An overflow occurs if dst gt 040h and dst lt OCOh before the operation is performed the result has changed sign N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Loaded from the MSB V Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R7 is multiplied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 RLA B R7 Shift left low byte of R7 x 4 ELA TAO AA IA IIA A Note RLA Substitution The assembler does not recognize the
18. SELS DCOCLK DCOCLK gt SYNC XT2CLK p DCO_Gen_on SCGO m p 1 on O off DCOCLK_on 5 6 Basic Clock Module Basic Clock Module Operation Adjusting the DCO frequency After a PUC RSELx 7 and DCOx 3 allowing the DCO to start at a mid range frequency MCLK and SMCLK are sourced from DCOCLK Because the CPU executes code from MCLK which is sourced from the fast starting DCO code execution typically begins from PUC in less than 2 us The typical DCOx and RSELx ranges and steps are shown in Figure 5 5 The frequency of DCOCLK is set by the following functions I The four RSELx bits select one of sixteen nominal frequency ranges for the DCO These ranges are defined for an individual device in the device specific data sheet JJ The three DCOx bits divide the DCO range selected by the RSELx bits into 8 frequency steps separated by approximately 10 JJ The five MODx bits switch between the frequency selected by the DCOx bits and the next higher frequency set by DCOx 1 When DCOx 07h the MODx bits have no effect because the DCO is already at the highest setting for the selected RSELx range Figure 5 5 Typical DCOx Range and RSELx Steps foco RSEL 15 20000 kHz RSEL 7 1000 kHz RSEL 0 100 kHz DCO 0 DCO 1 DCO 2 DCO 3 DCO 4 DCO 5 DCO 6 DCO 7 Basic Clock Module 5 7 Basic Clock Module Operation Each MSP430F2xx device has calibrated DCOCTL and BCSCTL1 registe
19. Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 4 78 16 Bit MSP430X CPU DINT Syntax Operation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Disable general interrupts DINT 0 gt GIE or OFFF7h AND SR gt SR NOT src AND dst gt dst BIC 8 SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled TS Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction 16 Bit MSP4
20. The ADC12 module supports fast 12 bit analog to digital conversions The module implements a 12 bit SAR core sample select control reference generator and a 16 word conversion and control buffer The conversion and control buffer allows up to 16 independent ADC samples to be converted and stored without any CPU intervention ADC12 features include Y Greater than 200 ksps maximum conversion rate J Monotonic 12 bit converter with no missing codes 1 Sample and hold with programmable sampling periods controlled by software or timers Conversion initiation by software Timer_A or Timer_B Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight individually configurable external input channels E E A oO Conversion channels for internal temperature sensor AVcc and external references E Independent channel selectable reference sources for both positive and negative references Y Selectable conversion clock source Li Single channel repeat single channel sequence and repeat sequence conversion modes 3 ADC core and reference voltage can be powered down separately 1 Interrupt vector register for fast decoding of 18 ADC interrupts _j 16 conversion result storage registers The block diagram of ADC12 is shown in Figure 21 1 Figure 21 1 ADC12 Block Diagram ADC12 Introduction REF2_5V
21. Timer_B 13 9 Timer_B Operation Changing the Value of Period Register TBCLO Use of the Up Down When changing TBCLO while the timer is running and counting in the down direction and when the TBCLO load event is immediate the timer continues its descent until it reaches zero The value in TBCCRO is latched into TBCLO immediately however the new period takes effect after the counter counts down to zero If the timer is counting in the up direction when the new period is latched into TBCLO and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value when TBCLO is loaded the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals see section Timer_B Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 13 9 the tggagq is tdead timer X TBCL1 TBCL3 With tgeag Time during which both outputs need to be inactive ttimer Cycle time of the timer clock TBCLx Content of compare latch x The ability to simultaneously load grouped compare latches assures the dead times Fig
22. 011 100 101 110 111 13 14 Timer_B Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated The output is set when the timer counts to the TBCLx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value The output is set when the timer counts to the TBCLx value It is reset when the timer counts to the TBCLO value The output is toggled when the timer counts to the TBCLx value The output period is double the timer period The output is reset when the timer counts to the TBCLx value It remains reset until another output mode is selected and affects the output The output is toggled when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value The output is reset when the timer counts to the TBCLx value It is set when the timer counts to the TBCLO value Timer_B Operation Output Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TBCLx value and rolls from TBCLO to zero depending on the output mode An example is shown in Figure 13 12 using TBCLO and TBCL1 Figure 13 12 Output Example Timer in Up M
23. 1 Generate START condition Software reset enable 0 Disabled USCI reset released for operation 1 Enabled USCI logic held in reset state Universal Serial Communication Interface C Mode 17 27 USCI Registers 2C Mode UCBxBRO USCI_Bx Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx low byte rw rw rw rw rw rw rw rw UCBxBR1 USCI_Bx Baud Rate Control Register 1 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCBRx Bit clock prescaler setting The 16 bit value of UCBxBRO UCBxBR1 x 256 forms the prescaler value 17 28 Universal Serial Communication Interface 12C Mode USCI Registers C Mode UCBxSTAT USCI_Bx Status Register 7 rw 0 Unused UC SCLLOW UCGC UCBBUSY UCNACK IFG UCSTPIFG UCSTTIFG UCALIFG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O mises sotn ucac ucesusy UCNACK ucstpiFa ucsTTIFG rw 0 r 0 rw 0 rw 0 rw 0 rw 0 SCL r 5 4 3 2 1 0 Unused SCL low 0 SCL is not held low 1 SCL is held low General call address received UCGC is automatically cleared when a START condition is received 0 No general call address received 1 General call address received Bus busy 0 Bus inactive 1 Bus busy Not acknowledge received interrupt flag UCNACKIFG is automatically cleared when a START condition is received 0 No interrupt pending 1 Interrupt pending Stop condition interrupt flag UCSTPIFG is automatically cleared when a START co
24. 2 UCTXSTT 1 UCBxTXIFG 1 Figure 17 14 12C Master 10 bit Addressing Mode Master Transmitter UCTXSTT 0 UCBxTXIFG 1 Deo UCTXSTP 0 UCTXSTP 1 A 1 UCTR 0 Receiver 2 UCTXSTT 1 UCTXSTT 0 UCBxRXIFG 1 DATA P A UCTXSTP 0 UCTXSTP 1 Universal Serial Communication Interface C Mode 17 19 USCI Operation C Mode Arbitration If two or more master transmitters simultaneously start a transmission on the bus an arbitration procedure is invoked Figure 17 15 illustrates the arbitration procedure between two devices The arbitration procedure uses the data presented on SDA by the competing transmitters The first master transmitter that generates a logic high is overruled by the opposing master generating a logic low The arbitration procedure gives priority to the device that transmits the serial data stream with the lowest binary value The master transmitter that lost arbitration switches to the slave receiver mode and sets the arbitration lost flag UCALIFG If two or more devices send identical first bytes arbitration continues on the subsequent bytes Figure 17 15 Arbitration Procedure Between Two Master Transmitters Bus Line SCL Data From Device 1 Data From Device 2 Bus Line SDA oe Ae ee NO NN Device 1 Lost Arbitration pe and Switches Off If the arbitratio
25. DAC12_10UT DAC12RES DAC12DF DAC12 23 3 DAC12 Operation 23 2 DAC12 Operation 23 2 1 DAC12 Core The DAC12 module is configured with user software The setup and operation of the DAC12 is discussed in the following sections The DAC12 can be configured to operate in 8 or 12 bit mode using the DAC12RES bit The full scale output is programmable to be 1x or 3x the selected reference voltage via the DAC12IR bit This feature allows the user to control the dynamic range of the DAC12 The DAC12DF bit allows the user to select between straight binary data and 2s compliment data for the DAC When using straight binary data format the formula for the output voltage is given in Table 23 1 Table 23 1 DAC12 Full Scale Range Vref Vorgr OF VREF Resolution DAC12RES DAC12IR Output Voltage Formula 12 bit 0 0 DAC12_xDAT Vout Vref x 3 x os 12 bit 0 1 DAC12_xDAT Vout Vref x 006 it 1 8 bi 0 Voit WER DAC12_xDAT 256 8 bit 1 1 DAC12_xDAT Vout Vref x 356 7 In 8 bit mode the maximum useable value for DAC12_xDAT is OFFh and in 12 bit mode the maximum useable value for DAC12_xDAT is OFFFh Values greater than these may be written to the register but all leading bits are ignored DAC12 Port Selection 23 4 DAC12 The DAC12 outputs are multiplexed with the port P6 pins and ADC12 analog inputs and also the VeREF pins When DAC12AMPx gt 0 the DAC12 function is automatically selected for the pin regardless of
26. Jump if no carry Carry occurred 16 Bit MSP430X CPU 4 115 Extended Instructions ANDX A ANDX W ANDX B Syntax Operation Description Status Bits Mode Bits Example Example Logical AND of source address word with destination address word Logical AND of source word with destination word Logical AND of source byte with destination byte ANDX A src dst ANDX src dst or ANDX W src dst ANDX B src dst src and dst gt dst The source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 20 bit data are used as a mask AAA55h for the address word TOM located in two words If the result is zero a branch is taken to label TONI MOVA AAA55h R5 Load 20 bit mask to R5 ANDX A R5 TOM TOM and R5 gt TOM JZ TONI Jump if result O Result gt 0 or shorter ANDX A AAA55h TOM TOM and AAA55h gt TOM JZ TONI Jump if result 0 A table byte pointed to by R5 20 bit address is logically ANDed with R6 R6 19 8 0 The table pointer is auto incremented by 1 ANDX B R5 R6 AND table byte with R6 R5 1 4 116
27. Mode Bits Example Example Example Exclusive OR source address word with destination address word Exclusive OR source word with destination word Exclusive OR source byte with destination byte XORX A src dst XORX src dst or XORX W src dst XORX B src dst src xor dst gt dst The source and destination operands are exclusively ORed The result is placed into the destination The source operand is not affected The previous contents of the destination are lost Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise carry not Zero V Set if both operands are negative before execution reset otherwise OSCOFF CPUOFF and GIE are not affected Toggle bits in address word CNTR 20 bit data with information in address word TONI 20 bit address XORX A TONI amp CNTR Toggle bits in CNTR A table word pointed to by R5 20 bit address is used to toggle bits in R6 XORX W R5 R6 Toggle bits in R6 R6 19 16 0 Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE 20 bit address XORX B EDE R7 Set different bits to 1 in R7 INV B R7 Invert low byte of R7 R7 19 8 0 4 154 16 Bit MSP430X CPU Address Instructions 4 6 4 Address Instructions MSP430X address instructions are instructions that support 20 bi
28. Rsrc z16 Rdst Reg Indexed MOVA symb16 Rdst Symbolic Reg MOVA Rsrc symb16 Reg Symbolic POPM A POPM W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Restore n CPU registers 20 bit data from the stack Restore n CPU registers 16 bit data from the stack POPM A n Rdst 1 lt n lt 16 POPM W_ n Rdst or POPM n Rdst 1 lt n lt 16 POPM A Restore the register values from stack to the specified CPU registers The stack pointer SP is incremented by four for each register restored from stack The 20 bit values from stack 2 words per register are restored to the registers POPM W Restore the 16 bit register values from stack to the specified CPU registers The stack pointer SP is incremented by two for each register restored from stack The 16 bit values from stack one word per register are restored to the CPU registers Note This does not use the extension word POPM A The CPU registers pushed on the stack are moved to the extended CPU registers starting with the CPU register Rdst n 1 The stack pointer is incremented by n x 4 after the operation POPM W The 16 bit registers pushed on the stack are moved back to the CPU registers starting with CPU register Rdst n 1 The stack pointer is incremented by n x 2 after the instruction The MSBs Rdst 19 16 of the restored CPU registers are cleared Not affected except SR is included in the
29. ane aaa ete a ee ee O Wenn O O LEED O GSEs ae Whys SVS_IT MB_IT WC start A A o o a a cc es BEBE LO y Oi na sa Lada Brownout gt Out gt Brownout Region Region 1 A 0 t t pene d BOR a S8VSCircuit Active d BOR E 0 l qea ta svSon Set SVS_POR 1 0 eee E TR undefined 9 6 Supply Voltage Supervisor SVS Registers 9 3 SVS Registers The SVS registers are listed in Table 9 1 Table 9 1 SVS Registers Register Short Form Register Type Address Initial State SVS Control Register SVSCTL Read write 056h Reset with BOR SVSCTL SVS Control Register 7 6 5 4 3 2 1 0 rw ot rw 0t rw 0t rw ot rw ot rw ot T Reset by a brownout reset only not by a POR or PUC VLDx Bits Voltage level detect These bits turn on the SVS and select the nominal SVS 7 4 threshold voltage level See the device specific data sheet for parameters 0000 SVS is off 0001 1 9V 0010 2 1V 0011 2 2V 0100 2 3V 0101 2 4V 0110 2 5V 0111 2 65V 1000 2 8 V 1001 2 9V 1010 3 05 1011 3 2 V 1100 3 35 V 1101 3 5 V 1110 3 7 V 1111 Compares external input voltage SVSIN to 1 25 V PORON Bit 3 POR on This bit enables the SVSFG flag to cause a POR device reset 0 SVSFG does not cause a POR 1 SVSFG causes a POR SVSON Bit 2 SVS on This bit reflects the status of SVS operation This bit DOES NOT turn on the SVS The SVS is turned on by setting VLDx gt O 0 SVS is Off 1 SVS is On
30. m DU vo O O O 7 or 8 bit data with odd even or non parity Independent transmit and receive shift registers Separate transmit and receive buffer registers LSB first or MSB first data transmit and receive Built in idle line and address bit communication protocols for multiprocessor systems Receiver start edge detection for auto wake up from LPMx modes Programmable baud rate with modulation for fractional baud rate support Status flags for error detection and suppression Status flags for address detection Independent interrupt capability for receive and transmit Figure 15 1 shows the USCI_Ax when configured for UART mode Universal Serial Communication Interface UART Mode 15 3 USCI Introduction UART Mode Figure 15 1 USCI_Ax Block Diagram UART Mode UCSYNC 0 UCRXEIE UCMODEx UCSPB UCDORM Error Flags A UCRXBRKIE Receive State Machine Set Flags Set RXIFG Set UCBRK Set UCADDR UCIDLE UCIRRXPL UCIRRXFLx UCIRRXFE Receive Buffer Ed UCIREN 6 IrDA Decoder O Receive Shift Register UCPEN UCPAR UCMSB UC7BIT UCABEN Receive Baudrate Generator UCOBRx UCOCLK 16 ACLK i Prescaler Divider Recsivea Clock SMCLK UCBRFx UCBRSx UCOS16 UCPEN UCPAR UCMSB UC7BIT UCIREN E Transmit Shift Register Transmit Buffer UCOTXBUF UCIRTXPLx Transmit State Machine Set UCOTXIFG IrDA Encoder 6 UCTXBRK UCTXADDR UCMODEx UCSPB 15 4 Universal Seria
31. s E 1 active inactive 0 active inactive 1 inactive active Universal Serial Communication Interface SPI Mode 16 5 USCI Operation SPI Mode 16 3 1 USCI Initialization and Reset The USCI is reset by a PUC or by the UCSWRST bit After a PUC the UCSWRST bit is automatically set keeping the USCI in a reset condition When set the UCSWRST bit resets the UCxRXIE UCxTXIE UCxRXIFG UCOE and UCFE bits and sets the UCxTXIFG flag Clearing UCSWRST releases the USCI for operation AN Note Initializing or Re Configuring the USCI Module The recommended USCI initialization re configuration process is 1 Set UCSWRST BIS B UCSWRST amp UCxCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCXCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST amp UCxCTL1 5 Enable interrupts optional via UCxRXIE and or UCxTXIE ee 16 3 2 Character Format 16 6 The USCI module in SPI mode supports 7 and 8 bit character lengths selected by the UC7BIT bit In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset The UCMSB bit controls the direction of the transfer and selects LSB or MSB first gt er SS Ss SS MM Note Default Character Format The default SPI character transmission is LSB first For communication with other SPI interfaces it MSB first mode may be required ee acca Note Character Format for Figures Figures throughout this chapter use
32. 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 rw rw 0 4 3 2 1 0 DAC12 DAC12AMPx DAC12DF DAC12IE DAC12IFG DAC12ENC rw 0 0 rw 0 rw 0 rw 0 rw 0 _ Modifiable only when DAC12ENC 0 DAC120PS Bit 15 DAC12 SREFx DAC12 RES DAC12 LSELx DAC12 CALON DAC12IR Bits 14 13 Bit 12 Bits 11 10 Bit 9 Bit 8 DAC12 output select 0 DAC12_0 output on P6 6 DAC12_1 output on P6 7 1 DAC12_0 output on VeREF DAC12_1 output on P6 5 DAC12 select reference voltage 00 VREF 01 VREF 10 Verer 11 VeREF DAC12 resolution select 0 12 bit resolution 1 8 bit resolution DAC12 load select Selects the load trigger for the DAC12 latch DAC12ENC must be set for the DAC to update except when DAC12LSELx 0 00 DAC12 latch loads when DAC12_xDAT written DAC12ENC is ignored 01 DAC12 latch loads when DAC12_xDAT written or when grouped when all DAC12_xDAT registers in the group have been written 10 Rising edge of Timer_A OUT1 TA1 11 Rising edge of Timer_B OUT2 TB2 DAC 12 calibration on This bit initiates the DAC12 offset calibration sequence and is automatically reset when the calibration completes 0 Calibration is not active 1 Initiate calibration calibration in progress DAC 12 input range This bit sets the reference input and voltage output range 0 DAC 12 full scale output 3x reference voltage 1 DAC12 full scale output 1x reference voltage DAC12 23 11 DAC12 R
33. 0 The output is low Bit 1 The output is high If the pin s pull up down resistor is enabled the corresponding bit in the PxOUT register selects pull up or pull down Bit 0 The pin is pulled down Bit 1 The pin is pulled up 8 2 3 Direction Registers PxDIR Each bit in each PxDIR register selects the direction of the corresponding I O pin regardless of the selected function for the pin PxDIR bits for I O pins that are selected for other functions must be set as required by the other function Bit 0 The port pin is switched to input direction Bit 1 The port pin is switched to output direction 8 2 4 Pullup Pulldown Resistor Enable Registers PXREN Each bit in each PxREN register enables or disables the pullup pulldown resistor of the corresponding I O pin The corresponding bit in the PXOUT register selects if the pin is pulled up or pulled down Bit 0 Pullup pulldown resistor disabled Bit 1 Pullup pulldown resistor enabled Digital I O 8 3 Digital I O Operation 8 2 5 Function Select Registers PxSEL and PxSEL2 8 4 Digital I O Port pins are often multiplexed with other peripheral module functions See the device specific data sheet to determine pin functions Each PxSEL and PxSEL2 bit is used to select the pin function I O port or peripheral module function PxSEL2 PxSEL Pin Function 0 0 I O function is selected 0 1 Primary peripheral module function is selected 1 0 Reserved See device
34. 0 1 5V 1 2 5V Reference generator on 0 Reference off 1 Reference on ADC10 on 0 ADC10 off 1 ADC10 on ADC10 interrupt enable 0 Interrupt disabled 1 interrupt enabled ADC10 interrupt flag This bit is set if ADC10MEM is loaded with a conversion result It is automatically reset when the interrupt request is accepted or it may be reset by software When using the DTC this flag is set when a block of transfers is completed 0 No interrupt pending 1 Interrupt pending Enable conversion 0 ADC10 disabled 1 ADC10 enabled Start conversion Software controlled sample and conversion _ start ADC10SC and ENC may be set together with one instruction ADC10SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC10 Registers ADC10CTL1 ADC10 Control Register 1 15 14 13 12 11 10 9 8 A o oos face ssa rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 Modifiable only when ENC 0 INCHx Bits Input channel select These bits select the channel for a single conversion or 15 12 the highest channel for a sequence of conversions 0000 AO 0001 Atl 0010 A2 0011 A3 0100 A4 0101 A5 0110 A6 0111 A7 1000 VeREF 1001 VREF VeREF 1010 Temperature sensor 1011 Vcc Vss 2 1100 Vcc Vss 2 A12 on MSP430x22xx devices 1101 Vcc Vss 2 A13 on MSP430x22xx devices 1110 Vcc Vss 2 A14 on MSP430x22xx devices
35. 1 5 When UCIRTXCLK 0 the pulse length tpyLse is based on BRCLK and is calculated as follows UCIRTXPLX tpurse 2 fare 1 When the pulse length is based on BRCLK the prescaler UCBRx must to be set to a value greater or equal to 5 The decoder detects high pulses when UCIRRXPL 0 Otherwise it detects low pulses In addition to the analog deglitch filter an additional programmable digital filter stage can be enabled by setting UCIRRXFE When UCIRRXFE is set only pulses longer than the programmed filter length are passed Shorter pulses are discarded The equation to program the filter length UCIRRXFLx is UCIRRXFLX tpuse twake 2 fercin 4 where truLse Minimum receive pulse width twakE Wake time from any low power mode Zero when MSP430 is in active mode 15 12 Universal Serial Communication Interface UART Mode USCI Operation UART Mode 15 3 6 Automatic Error Detection Glitch suppression prevents the USCI from being accidentally started Any pulse on UCAxRXD shorter than the deglitch time t approximately 150 ns will be ignored See the device specific data sheet for parameters When a low period on UCAxRXD exceeds t a majority vote is taken for the start bit If the majority vote fails to detect a valid start bit the USCI halts character reception and waits for the next low period on UCAxRXD The majority vote is also used for each bit in a character to prevent bit errors The USCI modu
36. 1 Otherwise the current transaction might be affected Universal Serial Communication Interface C Mode 17 17 USCI Operation C Mode Figure 17 13 1 C Master Receiver Mode Successful reception from a slave transmitter 2 UCTXSTT 1 UCTXSTP 1 UCTXSTP 0 Next transfer started with a repeated start condition Not acknowledge received after slave address UCTXSTT 0 UCNACKIFG 1 Arbitration lost in slave address or data byte 1 UCTR 0 gonen UCTXSTT 0 UCBxRXIFG 1 1 UCTR 1 Transmitter 2 UCTXSTT 1 A UCTXSTP 1 1 UCTR 0 Receiver 2 UCTXSTT 1 UCTXSTP 0 1 UCTR 1 Transmitter 2 UCTXSTT 1 UCBxTXIFG 1 1 UCTR 0 Receiver 2 UCTXSTT 1 UCALIEG 1 UCMST 0 UCSTTIFG 0 UCALIFG 1 MST 0 UC UCSTTIFG 0 Arbitration lost and addressed as slave UCALIFG 1 UCMST 0 UCTR 1 Transmitter UCSTTIFG 1 UCBxTXIFG 1 UCSTPIFG 0 USCI continues as Slave Transmitter 17 18 Universal Serial Communication Interface 1 C Mode Successful transmission to a slave receiver Master Receiver Successful reception from a slave transmitter 12C Master 10 bit Addressing Mode USCI Operation C Mode The 10 bit addressing mode is selected when UCSLA10 1 and is shown in Figure 17 14 1 UCTR 1 Transmitter
37. 1 8 6 4 16 000 000 460800 3 2 2 1 4 8 2 5 7 3 15 24 Universal Serial Communication Interface UART Mode USCI Operation UART Mode 15 3 14 Using the USCI Module in UART Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low power modes When SMCLK is the USCI clock source and is inactive because the device is in a low power mode the USCI module automatically activates it when needed regardless of the control bit settings for the clock source The clock remains active until the USCI module returns to its idle condition After the USCI module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic clock activation is not provided for ACLK When the USCI module activates an inactive clock source the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected For example a timer using SMCLK will increment while the USCI module forces SMCLK active 15 3 15 USCI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception USCI Transmit Interrupt Operation The UCAxTXIFG interrupt flag is set by the transmitter to indicate that UCAxTXBUF is ready to accept another character An interrupt request is generated if UCAxTXIE and GIE are also set UCAxTXIFG is automatically reset if a character is written to UCAxTXBUF UCAxTXIFG is
38. 101 110 111 Transfer Mode Single transfer Block transfer Burst block transfer Repeated single transfer Repeated block transfer Repeated burst block transfer Description Each transfer requires a trigger DMAEN is automatically cleared when DMAxSZ transfers have been made A complete block is transferred with one trigger DMAEN is automatically cleared at the end of the block transfer CPU activity is interleaved with a block transfer DMAEN is automatically cleared at the end of the burst block transfer Each transfer requires a trigger DMAEN remains enabled A complete block is transferred with one trigger DMAEN remains enabled CPU activity is interleaved with a block transfer DMAEN remains enabled DMA Controller 6 5 DMA Operation Single Transfer In single transfer mode each byte word transfer requires a separate trigger The single transfer state diagram is shown in Figure 6 3 The DMAxSZ register is used to define the number of transfers to be made The DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer The DMAxSZ register is decremented after each transfer When the DMAxSZ register decrem
39. 25 2 EEM Building Blocks 25 2 1 Triggers The event control in the EEM of the MSP430 system consists of triggers which are internal signals indicating that a certain event has happened These triggers may be used as simple breakpoints but it is also possible to combine two or more triggers to allow detection of complex events and trigger various reactions besides stopping the CPU In general the triggers can be used to control the following functional blocks of the EEM Y Breakpoints CPU stop Y State storage Y Sequencer There are two different types of triggers the memory trigger and the CPU register write trigger Each memory trigger block can be independently selected to compare either the MAB or the MDB with a given value Depending on the implemented EEM the comparison can be gt or lt The comparison can also be limited to certain bits with the use of a mask The mask is either bit wise or byte wise depending upon the device In addition to selecting the bus and the comparison the condition under which the trigger is active can be selected The conditions include read access write access DMA access and instruction fetch Each CPU register write trigger block can be independently selected to compare what is written into a selected register with a given value The observed register can be selected for each trigger independently The comparison can be gt or lt The comparison can also be limited
40. 3 4 2 Single Operand Format ll Instructions Instruction Set Figure 3 10 illustrates the single operand instruction format Figure 3 10 Single Operand Instruction Format 15 14 13 12 10 9 8 7 6 5 4 3 2 1 0 Table 3 12 lists and describes the single operand instructions Table 3 12 Single Operand Instructions Mnemonic S Reg D Reg RRC B dst RRA B dst PUSH B sre SWPB dst CALL dst RETI SXT dst Operation C gt MSB gt LSB gt C MSB gt MSB LSB gt C SP 2 gt SP src gt SP Swap bytes SP 2 gt SP PC 2 gt SP dst gt PC TOS gt SR SP 2 gt SP TOS gt PC SP 2 gt SP Bit 7 gt Bit 8 Bit 15 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set Status Bits Vv N Z Cc All addressing modes are possible for the CALL instruction If the symbolic mode ADDRESS the immediate mode N the absolute mode amp EDE or the indexed mode x RN is used the word that follows contains the address information RISC 16 Bit CPU 3 19 Instruction Set 3 4 3 Jumps Figure 3 11 shows the conditional jump instruction format Figure 3 11 Jump Instruction Format 155 1 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 3 13 lists and describes the jump instructions Table 3 13 Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JN
41. A O JL ho AAA AAA pM MOV MOV B SUBC SUBC B SUB SUB B PMP MP PADD DADDB S O BIT BIB PBI BIB PIS BIB po XOR XORB S O PAN AND ADD ADD B ADDC ADDC B 16 Bit MSP430X CPU 4 57 Instruction Set Description 4 6 1 Extended Instruction Binary Descriptions Detailed MSP430X instruction binary descriptions are shown below Instruction src or Instruction Group data 19 16 Identifier dst Instruction 15 12 11 8 7 4 3 0 MOVA 0 0 0 0 src 0 0 0 0 dst MOVA Rsrc Rdst 0 0 0 0 src 0 0 0 1 dst MOVA QORsrc Rdst 0 O O 0 amp abs 19 16 0 0 1 0 dst MOVA amp abs20 Rdst amp abs 15 0 0 0 0 0 src 0 0 1 1 dst MOVA x Rsrc Rdst x 15 0 15 bit index x 0 0 0 0 src 0 1 1 0 amp abs 19 16 MOVA Rsrc amp abs20 amp abs 15 0 0 0 0 0 src 0 1 1 1 dst MOVA Rsrc X Rdst x 15 0 15 bit index x 0 0 0 0 imm 19 16 1 0 0 0 dst MOVA imm20 Rdst imm 15 0 CMPA 0 0 0 0 imm 19 16 11101011 dst CMPA timm20 Rdst imm 15 0 ADDA 0 0 O 0O imm 19 16 1 0 1 0 dst ADDA timm20 Rdst imm 15 0 SUBA o o joj o imm 19 16 11101111 dst SUBA timm20 Rdst imm 15 0 MOVA 0 o 0oJjo0 src 1 1 00 dst MOVA Rsrc Rdst CMPA 01 10 100 src 1 O OS dst CMPA Rsrc Rdst ADDA 0 0 0 0 src Lf ud a dst ADDA Rsrc Rdst SUBA 0 0 0 0 src Wy ab a a dst SUBA Rsrc Rast Instruction Bit Inst Instruction
42. Because other bits in IFG1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending This bit may be used by other modules See device specific data sheet Basic Clock Module 5 17 5 18 Basic Clock Module Chapter 6 DMA Controller The DMA controller module transfers data from one address to another without CPU intervention This chapter describes the operation of the DMA controller of the MSP430x2xx device family Topic Page 6 1 DMA Introduction lt eeens ao 6 2 6 2 DMA Operation ar o ola 6 4 6 3 DMA Registers ee aaa aaa a eres 6 19 6 1 DMA Introduction 6 1 DMA Introduction The direct memory access DMA controller transfers data from one address to another without CPU intervention across the entire address range For example the DMA controller can move data from the ADC12 conversion memory to RAM Devices that contain a DMA controller may have one two or three DMA channels available Therefore depending on the number of DMA channels available some features described in this chapter are not applicable to all devices Using the DMA controller can increase the throughput of peripheral modules It can also reduce system power consumption by allowing the CPU to remain in a low power mode without having to awaken to move data to or from a peripheral The DMA
43. Channel Defined in ADC12MCTLx SAMPCON y 12 x ADC12CLK MSC 1 and SHP 1 and ENC 1 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set x pointer to ADC12MCTLx ADC12 21 13 ADC12 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The ADC results are written to the conversion memories starting with the ADC12MEMx defined by the CSTARTADDx bits The sequence ends after the measurement of the channel with a set EOS bit and the next trigger signal re starts the sequence Figure 21 9 shows the repeat sequence of channels mode Figure 21 9 Repeat Sequence of Channels Mode CONSEQx 11 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 ord and ADC12SC 4 Wait for Trigger SAMPCON 4 SAMPCON 1 Sample Input Channel Defined in If EOS x 1 then x ADC12MCTLx CSTARTADDx else if x lt 15 then x x 1 else SAMPCON x 0 If EOS x 1 then x 2 x ADC12CLK CSTARTADDx else if x lt 15 then x x 1 else MSC 0 x 0 or SHP 0 sheer and SHP 1 1 x ADC12CLK ENC 1 and Conversion or ENC 1 Completed EOS x 0 or Result Stored Into ADC12MEMx EOS x 0 ADC12IFG x is Set x pointer to ADC12MCTLx 21 14 ADC12 ENC 0 EOS x 1 ADC12 Operation
44. ENS UCB1TXIE UCB1RXIE UCA1TXIE UCA1RXIE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused 7 4 UCB1TXIE Bit3 USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCBIRXIE Bit 2 USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCAITXIE Biti USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCAIRXIE Bito USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled 16 24 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UC1IFG USCI_A1 USCI_B1 Interrupt Flag Register 7 3 2 1 0 UCB1 UCB1 UCA1 UCA1 TXIFG RXIFG TXIFG RXIFG rw 0 rw 1 rw 0 5 4 rw 0 rw 0 rw 0 rw 0 rw 1 Unused UCB1 TXIFG UCB1 RXIFG UCA1 TXIFG UCA1 RXIFG Bits 7 4 Bit 3 Bit 2 Bit 1 Bit O Unused USCI_B1 transmit interrupt flag UCB1TXIFG is set when UCB1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_B1 receive interrupt flag UCB1RXIFG is set when UCB1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USCI_A1 transmit interrupt flag UCA1TXIFG is set when UCA1TXBUF empty 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag UCA1RXIFG is set when UCA1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface SPI Mode 16 25 16 26 Universal Serial
45. Extended Format ll Instruction Format Exceptions Exceptions for the Format Il instruction formats are shown below Figure 4 32 PUSHM POPM Instruction Format Op code n 1 Rdst n 1 al T I o o Figure 4 33 RRCM RRAM RRUM and RLAM Instruction Format 11 10 9 4 a O N 4 50 16 Bit MSP430X CPU MSP430X Extended Instructions Figure 4 34 BRA Instruction Format imm15 0 amp abs15 0 index15 0 Figure 4 35 CALLA Instruction Format 15 4 3 0 index15 0 imm15 0 index15 0 amp abs15 0 16 Bit MSP430X CPU 4 51 MSP430X Extended Instructions Extended Emulated Instructions Table 4 15 Extended Emulated Instructions Instruction Explanation The extended instructions together with the constant generator form the extended Emulated instructions Table 4 15 lists the Emulated instructions Emulation ADCX B A dst BRA dst RETA CLRA Rdst CLRX B A dst DADCX B A dst DECX B A dst DECDA Rdst DECDX B A dst INCX B A dst INCDA Rdst INCDX B A dst INVX B A dst RLAX B A dst RLCX B A dst SBCX B A dst TSTA Rdst TSTX B A dst POPX dst Add carry to dst Branch indirect dst Return from subroutine Clear Rdst Clear dst Add carry to dst decimally Decrement dst by 1 Decrement dst by 2 Decrement dst by 2 Increment dst by 1 Increment Rdst by 2 Increment dst by 2 Invert dst Shift left dst arithmetically Shift left dst logically
46. N is set Status Bits N Set Z Not affected C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected 4 104 16 Bit MSP430X CPU MSP430 Instructions SETZ Set zero bit Syntax SETZ Operation 1 gt Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected 16 Bit MSP430X CPU 4 105 MSP430 Instructions SUB W SUB B Syntax Operation Description Status Bits Mode Bits Example Example Example Subtract source word from destination word Subtract source byte from destination byte SUB src dst or SUB W src dst SUB B src dst not src 1 dst dst or dst src gt dst The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source 1 to the destination The source operand is not affected the result is written to the destination operand Set if result is negative src gt dst reset if positive src lt dst Set if result is zero src dst reset otherwise src dst Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OS
47. POP B LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is OOh The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah Mem R7 low byte of system stack POP SR Last word on stack moved to the SR E a ETS Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix Cd 3 54 RISC 16 Bit CPU PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Push word onto stack Push byte onto stack PUSH src or PUSH W srce PUSH B src SP 2 gt SP src gt SP The stack pointer is decremented by two then the source operand is moved to the RAM word addressed by the stack pointer TOS Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of the status register and R8 are saved on the stack PUSH SR save status register PUSH R8 save R8 The contents of the peripheral TCDAT is saved on the stack PUSH B amp TCDAT save data from 8 bit peripheral module address TCDAT onto stack TTT GGG Note The System Stack Pointer The
48. Please refer to the device specific datasheet for further details For these devices software must check the DMAIFG and respective module flags to determine the source of the interrupt The DMAIFG flags are not reset automatically and must be reset by software Additionally some devices utilize the DMAIV register All DMAIFG flags are prioritized with DMAOIFG being the highest and combined to source a single interrupt vector The highest priority enabled interrupt generates a number in the DMAIV register This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled DMA interrupts do not affect the DMAIV value Any access read or write of the DMAIV register automatically resets the high est pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example as sume that DMAO has the highest priority If the DMAOIFG and DMA2IFG flags are set when the interrupt service routine accesses the DMAIV register DMAOIFG is reset automatically After the RETI instruction of the interrupt ser vice routine is executed the DMA2IFG will generate another interrupt 6 16 DMA Controller DMA Operation DMAIV Software Example The following software example shows the recommended use of DMAIV and the handling overhead The DMAIV value is added to the PC to automatically jump to the appropriate routine
49. R5 Start address at R5 R5 2 Indexed mode Call a subroutine at the 16 bit address contained in the 20 bit address pointed to by register R5 X e g a table with addresses starting at X The address is within the lower 64 KB X is within 32 KB CALL X R5 Start address at R5 X z16 R5 16 Bit MSP430X CPU 4 73 MSP430 Instructions CMP W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source word and destination word Compare source byte and destination byte CMP src dst or CMP W src dst CMP B src dst not src 1 dst or dst src The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source 1 to the destination The result affects only the status bits in SR Register Mode the register bits Rdst 19 16 W resp Rdst 19 8 B are not cleared N Set if result is negative src gt dst reset if positive src dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected Compare word EDE with a 16 bit constant
50. SPI Mode 16 15 USCI Registers SPI Mode Table 16 3 USCI_A1 and USCI_B1 Control and Status Registers Register Short Form Register Type Address Initial State USCI_A1 control register O UCA1CTLO Read write ODOh Reset with PUC USCI_A1 control register 1 UCA1CTL1 Read write 0Dih 001h with PUC USCI_A1 baud rate control register O UCA1BRO Read write 0D2h Reset with PUC USCI_A1 baud rate control register 1 UCA1BR1 Read write 0D3h Reset with PUC USCI_A1 modulation control register UCA10MCTL Read write 0D4h Reset with PUC USCI_A1 status register UCA1STAT Read write OD5h Reset with PUC USCI_A1 receive buffer register UCA1RXBUF Read OD6h Reset with PUC USCI_A1 transmit buffer register UCA1TXBUF Read write 0D7h Reset with PUC USCI_B1 control register O UCB1CTLO Read write OD8h 001h with PUC USCI_B1 control register 1 UCB1CTL1 Read write OD9h 001h with PUC USCI_B1 bit rate control register O UCB1BRO Read write ODAh Reset with PUC USCI_B1 bit rate control register 1 UCB1BR1 Read write ODBh Reset with PUC USCI_B1 status register UCB1STAT Read write ODDh Reset with PUC USCI_B1 receive buffer register UCB1iRXBUF Read ODEh Reset with PUC USCI_B1 transmit buffer register UCB1TXBUF Read write ODFh Reset with PUC USCI_A1 B1 interrupt enable register UC1IE Read write 006h Reset with PUC USCI_A1 B1 interrupt flag register UCI1IFG Read write 007h 00Ah with PUC 16 16 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UCAxCTLO USCI_Ax C
51. SUBCX A SUBCX W SUBCX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 148 Subtract source address word with carry from destination address word Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBCX A src dst SUBCX src dst or SUBCX W src dst SUBCX B src dst not src C dst gt dst or dst src 1 C gt dst The source operand is subtracted from the destination operand This is made by adding the 1 s complement of the source carry to the destination The source operand is not affected the result is written to the destination operand Both operands may be located in the full address space Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 20 bit constant 87654h is subtracted from R5 with the carry from the previous instruction SUBCX A 87654h R5 Subtract 87654h C from R5 A 48 bit number 3 words pointed to by R5 20 bit address is subtracted from a 48 bit counter in RAM pointe
52. The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself Interrupt handler for DMAOIFG DMA1IFG DMA2IFG Cycles DMA_HND a s Interrupt latency 6 ADD amp DMAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP DMAO_HND Vector 2 DMA channel 0 2 JMP DMA1_HND Vector 4 DMA channel 1 2 JMP DMA2 HND Vector 6 DMA channel 2 2 RETI Vector 8 Reserved 5 RETI Vector 10 Reserved 5 RETI Vector 12 Reserved 5 RETI Vector 14 Reserved 5 DMA2_HND Vector 6 DMA channel 2 Task starts here RETI Back to main program 5 DMA1_HND Vector 4 DMA channel 1 Task starts here RETI Back to main program 5 DMAO_HND Vector 2 DMA channel 0 Task starts here RETI Back to main program 5 6 2 9 Using the USCI_B I2C Module with the DMA Controller The USCI_B I C module provides two trigger sources for the DMA controller The USCI_B I C module can trigger a transfer when new 12C data is received and when data is needed for transmit A transfer is triggered if UCBORXIFG is set The UCBORXIFG is cleared automatically when the DMA controller acknowledges the transfer If UCBORXIE is set UCBORXIFG will not trigger a transfer A transfer is triggered if UCBOTXIFG is set The UCBOTXIFG is cleared automatically when the DMA controller acknowledges
53. These bits may be used by other modules see the device specific data sheet USCI_BO transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_BO receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_AO transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_AO receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCBO UCBO UCAO UCAO TXIFG RXIFG TXIFG RXIFG rw 1 rw 0 rw 1 rw 0 UCBO TXIFG UCBO RXIFG UCAO TXIFG UCAO RXIFG Bits 7 4 Bit 3 Bit 2 Bit 1 Bit O These bits may be used by other modules see the device specific data sheet USCI_BO transmit interrupt flag UCBOTXIFG is set when UCBOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_BO receive interrupt flag UCBORXIFG is set when UCBORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending USCI_AO transmit interrupt flag UCAOTXIFG is set when UCAOTXBUF empty 0 No interrupt pending 1 Interrupt pending USCI_AO receive interrupt flag UCAORXIFG is set when UCAORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface SPI Mode 16 23 USCI Registers SPI Mode UC1IE USCI_A1 USCI_B1 Interrupt Enable Register 7 6 5 4 3 2 1 0
54. USCI_AO control register O UCAOCTLO Read write 060h Reset with PUC USCI_AO control register 1 UCAOCTL1 Read write 061h 001h with PUC USCI_AO baud rate control register 0 UCAOBRO Read write 062h Reset with PUC USCI_AO baud rate control register 1 UCAOBR1 Read write 063h Reset with PUC USCI_AO modulation control register UCAOMCTL Read write 064h Reset with PUC USCI_AO status register UCAOSTAT Read write 065h Reset with PUC USCI_AO receive buffer register UCAORXBUF Read 066h Reset with PUC USCI_AO transmit buffer register UCAOTXBUF Read write 067h Reset with PUC USCI_BO control register O UCBOCTLO Read write 068h 001h with PUC USCI_BO control register 1 UCBOCTL1 Read write 069h 001h with PUC USCI_BO bit rate control register O UCBOBRO Read write O6Ah Reset with PUC USCI_BO bit rate control register 1 UCBOBR1 Read write 06Bh Reset with PUC USCI_BO status register UCBOSTAT Read write 06Dh Reset with PUC USCI_BO receive buffer register UCBORXBUF Read O6Eh Reset with PUC USCI_BO transmit buffer register UCBOTXBUF Read write O6Fh Reset with PUC SFR interrupt enable register 2 1E2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h 00Ah with PUC r A Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B or CLR B instructions SSS_ ___a E_ gt Universal Serial Communication Interface
55. Using the Multiple Sample and Convert MSC Bit To configure the converter to perform successive conversions automatically and as quickly as possible a multiple sample and convert function is available When MSC 1 CONSEQx gt 0 and the sample timer is used the first rising edge of the SHI signal triggers the first conversion Successive conversions are triggered automatically as soon as the prior conversion is completed Additional rising edges on SHI are ignored until the sequence is completed in the single sequence mode or until the ENC bit is toggled in repeat single channel or repeated sequence modes The function of the ENC bit is unchanged when using the MSC bit Stopping Conversions Stopping ADC12 activity depends on the mode of operation The recommended ways to stop an active conversion or conversion sequence are OU Resetting ENC in single channel single conversion mode stops a conversion immediately and the results are unpredictable For correct results poll the busy bit until reset before clearing ENC Y Resetting ENC during repeat single channel operation stops the converter at the end of the current conversion UY Resetting ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence _j Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting ENC bit Conversion data are unreliable AAAA L Note No EOS Bit Set For Sequence If no EOS bit is set
56. dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is shifted left one position RLCX A R5 R5 x 2 C gt R5 The RAM byte LEO is shifted left one position PC is pointing to upper memory RLCX B LEO RAM LEO x 2 C gt RAM LEO 16 Bit MSP430X CPU 4 137 Extended Instructions RRAM A RRAM W Syntax Operation Description Status Bits Mode Bits Example Example Rotate Right Arithmetically the 20 bit CPU register content Rotate Right Arithmetically the 16 bit CPU register content RRAM A n Rdst 1 lt n lt 4 RRAM W n Rdst or RRAM n Rdst 1 lt n lt 4 MSB gt MSB gt MSB 1 LSB 1 gt LSB gt C The destination operand is shifted right arithmetically by one two three or four bit positions as shown in Figure 4 47 The MSB retains its value sign RRAM operates equal to a signed division by 2 4 8 16 The MSB is retained and shifted into MSB 1 The LSB 1 is shifted into the LSB and the LSB is shifted into the carry bit C The word instruction RRAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LS
57. go to error routine Result ok The two digit BCD number contained in 20 bit address BCD is added decimally to a two digit BCD number contained in R4 CLRC Clear carry DADDX B BCD R4 Add BCD to R4 decimally R4 000ddh 16 Bit MSP430X CPU 4 123 Extended Instructions DECX A DECX W DECX B Syntax Operation Emulation Description Status Bits Mode Bits Example 4 124 Decrement destination address word Decrement destination word Decrement destination byte DECX dst DECX dst DECX B dst dst 1 gt dst SUBX A 1 dst SUBX 1 dst SUBX B 1 dst or DECX W dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected RAM address word TONI is decremented by 1 DECX A TONI 16 Bit MSP430X CPU Decrement TONI DECDX A DECDX W DECDX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Double decrement destination address word Double decrement destination word Double decrement destination byte DECDX A dst DECDX dst DECDX B dst dst 2 gt dst SUBX A 2 dst SUBX 2 dst SUBX B 2 dst or DECDX W dst The destination operand is decremen
58. grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 21 11 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design using separate analog and digital ground planes with a single point connection is recommend to achieve high accuracy Figure 21 11 ADC12 Grounding and Noise Considerations DVcc Digital Power Supply 5 Decoupling Dz DVss 10uF 100nF Analog n AVcc Power Supply 75 Decoupling AVss 10uF 100nF Using an External Ve REF Positive 7N e Reference 10uF 100nF Using the Internal de VREF Reference 7N Generator 10 uF 100 nF Using an External VREF VeREF Negative 7N TE Reference 10 uF 100 nF ADC12 21 17 ADC12 Operation 21 2 9 ADC12 Interrupts The ADC12 has 18 interrupt sources YY ADC12IFGO ADC12IFG15 Y ADC120V ADC12MEMx overflow Ly ADC12TOV ADC12 conversion time overflow The ADC12IFGx bits are set when their correspond
59. or input with pullup pulldown enabled DVcc or Vcc 47 KQ pullup with 10 nF 2 2 nFt pulldown Open Open Open Open Open 20xx 21xx 22xx devices t The pulldown capacitor should not exceed 2 2 nF when using devices with Spy Bi Wire interface in Spy Bi Wire mode or in 4 wire JTAG mode with Tl tools like FET interfaces or GANG programmers System Resets Interrupts and Operating Modes 2 17 2 18 System Resets Interrupts and Operating Modes Chapter 3 RISC 16 Bit CPU This chapter describes the MSP430 CPU addressing modes and instruction set Topic Page cle CPU tod Vitel iP toa tattoos 3 2 3 2 CPU Registers loas jane ise sete 3 4 SIMA CAES MOE a a a E 3 9 3 45 NINStFUCTIOMISEt sven a oer E E e oa ein rc E 3 17 3 1 CPU Introduction 3 1 CPU Introduction 3 2 The CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The CPU can address the complete address range without paging The CPU features include Lj a a a RISC architecture with 27 instructions and 7 addressing modes Orthogonal architecture with every instruction usable with every addressing mode Full register access including program counter status registers and stack pointer Single cycle register operations Large 16 bit register file reduces fetches to memory 16 bit address bus allows direct
60. rw 0 UCSSELx UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST 5 4 3 2 1 0 UCSSELx UCRXEIE UCBRKIE UCDORM UCTXADDR UCTXBRK UCSWRST rw 0 rw 0 rw 0 rw 0 rw 0 1 rw 0 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O rw USCI clock source select These bits select the BRCLK source clock 00 UCLK 01 ACLK 10 SMCLK 11 SMCLK Receive erroneous character interrupt enable 0 Erroneous characters rejected and UCAxRXIFG is not set 1 Erroneous characters received will set UCAxRXIFG Receive break character interrupt enable 0 Received break characters do not set UCAxRXIFG 1 Received break characters set UCAxRXIFG Dormant Puts USCI into sleep mode 0 Not dormant All received characters will set UCAxRXIFG 1 Dormant Only characters that are preceded by an idle line or with address bit set will set UCAxRXIFG In UART mode with automatic baud rate detection only the combination of a break and synch field will set UCAxRXIFG Transmit address Next frame to be transmitted will be marked as address depending on the selected multiprocessor mode 0 Next frame transmitted is data 1 Next frame transmitted is an address Transmit break Transmits a break with the next write to the transmit buffer In UART mode with automatic baud rate detection 055h must be written into UCAxTXBUF to generate the required break synch fields Otherwise Oh must be written into the transmit buffer 0 Next frame transmitted is
61. s TEXAS INSTRUMENTS MSP430x2xx Family User s Guide 2008 Mixed Signal Products SLAU144E About This Manual Preface Read This First This manual discusses modules and peripherals of the MSP430x2xx family of devices Each discussion presents the module or peripheral in a general sense Not all features and functions of all modules or peripherals are present on all devices In addition modules or peripherals may differ in their exact implementation between device families or may not be fully implemented on an individual device or device family Pin functions internal signal connections and operational paramenters differ from device to device The user should consult the device specific datasheet for these details Related Documentation From Texas Instruments FCC Warning For related documentation see the web site http www ti com msp430 This equipment is intended for use in a laboratory test environment only It generates uses and can radiate radio frequency energy and has not been tested for compliance with the limits of computing devices pursuant to subpart J of part 15 of FCC rules which are designed to provide reasonable protection against radio frequency interference Operation of this equipment in other environments may cause interference with radio communications in which case the user at his own expense will be required to take whatever measures may be required to correct this interference Notational Conv
62. sampling time for ADC12MCTL8 to 15 Figure 21 4 Pulse Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete SHI tsample gt lt tconvert gt tsync 21 8 ADC12 ADC12 Operation Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsampie as Shown below in Figure 21 5 An internal MUX on input resistance R maximum of 2 KQ in series with capacitor C maximum of 40 pF is seen by the source The capacitor C voltage Vc must be charged to within 1 2 LSB of the source voltage Vs for an accurate 12 bit conversion Figure 21 5 Analog Input Equivalent Circuit Vs Rs MSP430 V Input voltage at pin Ax Vs External source voltage Ri Vi Rs External source resistance Ve R Internal MUX on input resistance C Input capacitance Ci Vc Capacitance charging voltage Ji The resistance of the source Rg and R4 affect tsample The following equation can be used to calculate the minimum sampling time tsample for a 12 bit conversion 13 tsample gt Rs Ri x In 2 x C 800ns Substituting the values for R and C given above the equation becomes t gt Rg 2kQ x 9 011 x 40pF 800ns sample For example if Rg is 10 KQ tsampie Must be greater than 5 13 us ADC12 21 9 ADC12 Operation 21 2 5 Co
63. the counter rolls to zero Timer_A Operation Continuous Mode In the continuous mode the timer repeatedly counts up to OFFFFh and restarts from zero as shown in Figure 12 4 The capture compare register TACCRO works the same way as the other capture compare registers Figure 12 4 Continuous Mode OFFFFh Oh The TAIFG interrupt flag is set when the timer counts from OFFFFh to zero Figure 12 5 shows the flag set cycle Figure 12 5 Continuous Mode Flag Setting e S AA Ne O O NAS NS ROE FFFEh Y FFFFh Y on Set TAIFG Timer Timer_A 12 7 Timer_A Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TACCRx register in the interrupt service routine Figure 12 6 shows two separate time intervals ty and t4 being added to the capture compare registers In this usage the time interval is controlled by hardware not software without impact from interrupt latency Up to three independent time intervals or output frequencies can be generated using all three capture compare registers Figure 12 6 Continuous Mode Time Intervals 12 8 TACCR1b TACCR1c TACCROb TACCROc TACCRO a A a Timer_A TACCROa TACCRta TACCRId Time intervals can be produced with other modes as well where TACCRO is used as the
64. two four six or eight bytes and the PC is incremented accordingly Instruction accesses are performed on word boundaries and the PC is aligned to even addresses Figure 4 3 shows the program counter Figure 4 3 Program Counter PC 19 16 15 1 0 Program Counter Bits 19 to 1 g The PC can be addressed with all instructions and addressing modes A few examples MOV W LABEL PC Branch to address LABEL lower 64 KB MOVA LABEL PC Branch to address LABEL 1MB memory MOV W LABEL PC Branch to address in word LABEL lower 64 KB MOV W R14 PC Branch indirect to address in R14 lower 64 KB ADDA 4 PC Skip two words 1 MB memory The BR and CALL instructions reset the upper four PC bits to 0 Only addresses in the lower 64 KB address range can be reached with the BR or CALL instruction When branching or calling addresses beyond the lower 64 KB range can only be reached using the BRA or CALLA instructions Also any instruction to directly modify the PC does so according to the used addressing mode For example MOV W value PC will clear the upper four bits of the PC because it is a w instruction 16 Bit MSP430X CPU 4 5 CPU Registers The program counter is automatically stored on the stack with CALL or CALLA instructions and during an interrupt service routine Figure 4 4 shows the storage of the program counter with the return address after a CALLA instruction A CALL instruction stores only
65. 0 rw 0 rw 0 rw 0 rw 0 ADC10AE1x Bits ADC10 analog enable These bits enable the corresponding pin for analog 7 4 input BIT4 corresponds to A12 BIT5 corresponds to A13 BIT6 corresponds to A14 and BIT7 corresponds to A15 0 Analog input disabled 1 Analog input enabled ADC10 20 29 ADC10 Registers ADC10MEM Conversion Memory Register Binary Format 15 14 13 12 11 10 9 8 ro rO rO ro ro rO r r 7 6 5 4 3 2 1 0 eee r r r r r r r r Conversion Bits The 10 bit conversion results are right justified straight binary format Bit 9 Results 15 0 is the MSB Bits 15 10 are always 0 ADC10MEM Conversion Memory Register 2s Complement Format 15 14 13 12 11 10 9 8 e r r r r r r r r 7 6 5 4 3 2 1 0 r r rO ro ro rO rO ro Conversion Bits The 10 bit conversion results are left justified 2s complement format Bit 15 Results 15 0 is the MSB Bits 5 0 are always O 20 30 ADC10 ADC10 Registers ADC10DTCO Data Transfer Control Register 0 7 ro Reserved ADC10TB ADC10CT ADC10B1 ADC10 FETCH 6 3 2 1 0 ADC10 0 0 rw 0 ro Bits 7 4 Bit 3 Bit 2 Bit 1 Bit 0 5 4 ro rO rw rw r 0 Reserved Always read as 0 ADC10 two block mode 0 One block transfer mode 1 Two block transfer mode ADC10 continuous transfer 0 Data transfer stops when one block one block mode or two blocks two block mode have completed 1 Data is transferred continuously DTC operation is stopped only if
66. 0 transfer size DMAOSZ Read write 01DAh Unchanged DMA channel 1 control DMA1CTL Read write 01DCh Reset with POR DMA channel 1 source address DMA1SA Read write 01DEh Unchanged DMA channel 1 destination address DMA1DA Read write 01E2h Unchanged DMA channel 1 transfer size DMA1SZ Read write 01E6h Unchanged DMA channel 2 control DMA2CTL Read write 01E8h Reset with POR DMA channel 2 source address DMA2SA Read write 01EAh Unchanged DMA channel 2 destination address DMA2DA Read write 01EEh Unchanged DMA channel 2 transfer size DMA2SZ Read write 01F2h Unchanged DMA Controller 6 19 DMA Registers DMACTLO DMA Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved Bits Reserved 15 12 DMA2 Bits DMA trigger select These bits select the DMA transfer trigger TSELx 11 8 0000 DMAREA bit software trigger 0001 TACCR2 CCIFG bit 0010 TBCCR2 CCIFG bit 0011 Serial data received UCAORXIFG 0100 Serial data transmit ready UCAOTXIFG 0101 DAC12_OCTL DAC12IFG bit 0110 ADC12 ADC12IFGx bit 0111 TACCRO CCIFG bit 1000 TBCCRO CCIFG bit 1001 Serial data received UCA1RXIFG 1010 Serial data transmit ready UCA1TXIFG 1011 Multiplier ready 1100 Serial data received UCBORXIFG 1101 Serial data transmit ready UCBOTXIFG 1110 DMAOIFG bit triggers DMA channel 1 DMA1IFG bit triggers DMA channel 2 DMA2IFG bit triggers DMA channel 0 1111 E
67. 00000 ccc cee eee eens 7 3 1 Flash Memory Timing Generator 00 0c eee eee eee eee 7 3 2 Erasing Flash Memory 0 ccc eee teens 7 3 3 Writing Flash Memory 0 0 eee 7 3 4 Flash Memory Access During Write or Erase 005 7 3 5 Stopping a Write or Erase Cycle 2 000 eee eee 7 3 6 Marginal Read Mode 0 eects 7 3 7 Configuring and Accessing the Flash Memory Controller 7 3 8 Flash Memory Controller Interrupts 00000 cece eee eee 7 3 9 Programming Flash Memory Devices 00 cece eee ees 7 4 Flash Memory Registers ooooccoocccccccorcc teens 8 Digital VO 220 tide seth A Lora oie ed weet 8 1 Digital I O Introduction 0 eet eens 8 2 Digital O Operation 0 2c teens 8 2 1 Input Register PXIN 0 eee ete 8 2 2 Output Registers PXOUT 0 cc eee eee 8 2 3 Direction Registers PXDIR 00 cece 8 2 4 Pull Up Down Resistor Enable Registers PXREN 8 2 5 Function Select Registers PXSEL and PxSEL2 2 4 8 2 66 Pl1andP2 Interrupts ui a a E ees 8 2 7 Configuring Unused Port Pins 600 aneen aaee 8 3 Digital O Registers 0 ccc rn 6 1 6 2 6 4 6 4 6 5 6 12 6 14 6 14 6 15 6 16 6 16 6 17 6 18 6 18 6 18 6 19 7 1 7 2 7 3 7 4 7 5 7 5 7 7 7 10 7 16 7 17 7 17 7 17 7 18 7 18 7 20 8 1 8 2 8 3
68. 1 o OSR 512 LSBACC 1 SD16UNI 1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14f13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR 512 LSBACC 0 SD16UNI 0 29 28 aa 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 0 OSR 512 LSBACC 1 SD16UNI 0 29 28 27 26 25 24 23 22 21 20 19 118 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SD16_A 24 9 SD16_A Operation OSR 256 LSBACC 0 SD16UNI 1
69. 1 1 LPM4 System Resets Interrupts and Operating Modes CPU and Clocks Status CPU is active all enabled clocks are active CPU MCLK are disabled SMCLK ACLK are active CPU MCLK are disabled DCO and DC generator are disabled if the DCO is not used for SMCLK ACLK is active CPU MCLK SMCLK DCO are disabled DC generator remains enabled ACLK is active CPU MCLK SMCLK DCO are disabled DC generator disabled ACLK is active CPU and all clocks disabled 2 15 Operating Modes 2 3 1 2 16 Entering and Exiting Low Power Modes An enabled interrupt event wakes the MSP430 from any of the low power operating modes The program flow is Lj Enter interrupt service routine m The PC and SR are stored on the stack m The CPUOFF SCG1 and OSCOFF bits are automatically reset U Options for returning from the interrupt service routine m The original SR is popped from the stack restoring the previous operating mode m The SR bits stored on the stack can be modified within the interrupt service routine returning to a different operating mode when the RETI instruction is executed Enter LPMO Example BIS GIE CPUOFF SR Enter LPMO Program stops here Exit LPMO Interrupt Service Routine BIC CPUOFF 0 SP Exit LPMO on RETI RETI Enter LPM3 Example BIS GIE CPUOFF SCG1 SCG0O SR Enter LPM3 Program stops here Exit LPM3 Interrupt Service Routine BIC HCPUOFF SCG1 SCGO 0 SR Exit LPM3 on RETI RETI S
70. 1 USCI Initialization and Reset 0 cece eee 1733 2 120 S rial Data una ets 17 3 3 12C Addressing Modes 0 00 c cece eee teens 17 3 4 12C Module Operating Modes cece cece eee 17 3 5 12C Clock Generation and Synchronization ococooocccccooo 17 3 6 Using the USCI Module in 12C Mode with Low Power Modes 17 3 7 USCI Interrupts in 12C Mode 0 cece eee USCI Registers 120 Mode 0 c cece eee eens OA INtrOCUCTION sise duaia nei A eee ee fio ods nea OA Operatoria a ed aie ie bee ee a DE NS 18 21 OA AMplifiet vocacion cae weigh ioe dl eed epee raisin ee areas es 18 22 OA INPUT escorias rar Ada 18 2 3 OA Output and Feedback Routing 6 cece eee eee eee 18 2 4 OA Configurations 0 eens OA SR QISterS wc cidad ARA 19 COMParator AF veisut A a te ai ie xii 19 1 19 2 19 3 Comparator_A Introduction ae cee eect eee eae Comparator_A Operation oooooccccccncccc eee eae 19 21 Comparator ti entiation a ean Mace BEER a aig ae ea Se wee pa 19 2 2 Input Analog Switches 0 00 cee eee 19 2 3 Input Short Switch 0 0 0 ects 19 24 QOUTOUE FINED so esate detec ae BA Tauern Peete Bleed 19 2 5 Voltage Reference Generator 0 ae cece eee 19 2 6 Comparator_A Port Disable Register CAPD 19 2 7 Comparator_A Interrupts 0 0 cee eee eee 19 2 8 Comparator_A Use
71. 1001 1010 1011 1100 1101 A transfer is triggered when the DMAREQ bit is set The DMAREQ bit is automatically reset when the transfer starts A transfer is triggered when the TACCR2 CCIFG flag is set The TACCR2 CCIFG flag is automatically reset when the transfer starts If the TACCR2 CCIE bit is set the TACCR2 CCIFG flag will not trigger a transfer A transfer is triggered when the TBCCR2 CCIFG flag is set The TBCCR2 CCIFG flag is automatically reset when the transfer starts If the TBCCR2 CCIE bit is set the TBCCR2 CCIFG flag will not trigger a transfer A transfer is triggered when serial interface receives new data Devices with USCI_AO module A transfer is triggered when USCI_AO receives new data UCAORXIFG is automatically reset when the transfer starts If UCAORXIE is set the UCAORXIFG flag will not trigger a transfer A transfer is triggered when serial interface is ready to transmit new data Devices with USCI_AO module A transfer is triggered when USCI_AO is ready to transmit new data UCAOTXIFG is automatically reset when the transfer starts If UCAOTXIE is set the UCAOTXIFG flag will not trigger a transfer A transfer is triggered when the DAC12_OCTL DAC12IFG flag is set The DAC12_OCTL DAC12IFG flag is automatically cleared when the transfer starts If the DAC12_OCTL DAC12IE bit is set the DAC12_OCTL DAC12IFG flag will not trigger a transfer A transfer is triggered by an ADC12IFGx flag When single channel co
72. 140 180 1CO 200 240 280 2C0 300 340 380 3C0 Pt Y py tp pp ESEE AE ESE E E E A E O E E O E E E pl pas el Ae SEE E A ES AE OS o FSA AE EE EA A E ee S E S arc arc swes ama amas sxr eusm pusHel cat revi J f OOS ST ETA PA S T S Re M a EP A E pao il ae lt ls e A Me o S le e AH 3 74 RISC 16 Bit CPU Table 3 17 MSP430 Instruction Set Mnemonic apc B t dst ADD B src dst ADDC B src dst AND B src dst BIC B src dst BIS B src dst BIT B src dst BR dst CALL dst CLR B t dst CLRC cLRNt CLRZ CMP B src dst papc B t dst DADD B src dst DEC B dst DEcD B t dst pintt EINT INC B dst INCD B t dst INV B t dst JC JHS abe JEQ JZ abe JGE abe JL abe JMP abe JN abe JNC JLO abe JNE JNZ abe MOV B src dst Nopt POP B t dst PUSH B src RET RETI RLA B t dst RLC B t dst RRA B dst RRC B dst spc B t dst setct SETNT SETZ SUB B src dst SUBC B src dst SWPB dst SXT dst TsT B t dst XOR B src dst 1 Emulated Instruction Description Add C to destination Add source to destination Add source and C to destination AND source and destination Clear bits in destination Set bits in destination Test bits in destination Branch to destination Call destination Clear destination Clear C Clear N Clear Z Compare source and destination Add C decimally to destination Add so
73. 16 000 000 128000 125 0 0 0 0 0 8 0 16 000 000 256000 62 4 0 0 8 0 1 2 1 2 Universal Serial Communication Interface UART Mode 15 23 USCI Operation UART Mode Table 15 5 Commonly Used Baud Rates Settings and Errors UCOS16 1 BRCLK Baud frequency Rate UCBRx UCBRSx UCBRFx Max TX Error Max RX Error Hz Baud 1 048 576 9600 6 0 13 2 3 0 2 2 0 8 1 048 576 19200 3 1 6 4 6 3 2 5 0 4 7 1 000 000 9600 6 0 8 1 8 0 2 2 0 4 1 000 000 19200 3 0 4 1 8 0 2 6 0 9 1 000 000 57600 1 7 0 34 4 0 33 4 0 4 000 000 9600 26 0 1 0 0 9 0 1 1 4 000 000 19200 13 0 0 1 8 0 1 9 0 2 4 000 000 38400 0 8 1 8 0 2 2 0 4 4 000 000 57600 5 3 3 5 3 2 1 8 6 4 4 000 000 115200 2 3 2 2 1 4 8 2 5 7 3 4 000 000 230400 7 0 34 4 0 33 4 0 8 000 000 9600 52 0 1 0 4 0 0 4 0 1 8 000 000 19200 26 0 1 0 0 9 0 1 1 8 000 000 38400 13 0 0 1 8 0 1 9 0 2 8 000 000 57600 0 11 0 0 88 0 1 6 8 000 000 115200 5 3 3 5 3 2 1 8 6 4 8 000 000 230400 2 3 2 2 1 4 8 2 5 7 3 8 000 000 460800 7 0 34 4 0 33 4 0 12 000 000 9600 78 0 2 0 0 0 05 0 05 12 000 000 19200 39 0 1 0 0 0 0 2 12 000 000 38400 19 0 8 1 8 0 1 8 0 1 12 000 000 57600 13 0 0 1 8 0 1 9 0 2 12 000 000 115200 6 0 8 1 8 0 2 2 0 4 12 000 000 230400 3 0 4 1 8 0 2 6 0 9 16 000 000 9600 104 0 3 0 0 2 0 0 3 16 000 000 19200 52 0 1 0 4 0 0 4 0 1 16 000 000 38400 26 0 1 0 0 9 0 1 1 16 000 000 57600 17 0 6 0 0 9 0 1 1 0 16 000 000 115200 0 11 0 0 9 0 1 6 16 000 000 230400 5 3 3 5 3 2
74. 16 Bit MSP430X CPU BICX A BICX W BICX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Clear bits set in source address word in destination address word Clear bits set in source word in destination word Clear bits set in source byte in destination byte BICX A src dst BICX src dst or BICX W src dst BICX B src dst not src and dst gt dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The bits 19 15 of R5 20 bit data are cleared BICX A 0F8000h R5 Clear R5 19 15 bits A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BICX W R5 R7 Clear bits in R7 A table byte pointed to by R5 20 bit address is used to clear bits in output Porti BICX B R5 amp P10UT Clear I O port P1 bits 16 Bit MSP430X CPU 4 117 Extended Instructions BISX A BISX W BISX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 118 Set bits set in source address word in destination address word Set bits set in source word in destination word Set bits set in source byte in destination byte BISX A
75. 5 V reference voltage is used during a conversion _j Conversion result 0x0100 Y Reference voltage calibration factor CAL_ADC_15VREF_FACTOR 0x7BBB The following steps show an example of how the ADC12 conversion result can be corrected by using the hardware multiplier 4 Multiply the conversion result by 2 this step simplifies the final division Y Multiply the result by CAL_ADC_15VREF_FACTOR 1 Divide the result by 216 use the upper word of the 32 bit multiplication result RESHI In the example LJ 0x0100 x 0x0002 0x0200 Lj 0x0200 x Ox7BBB 0x00F7_7600 LJ 0x00F7_7600 0x0001_0000 0x0000_00F7 247 The code example using the hardware multiplier follows The ADC conversion result is stored in ADC12MEMO It is assumed that R9 contains the address of the TAG ADC12 1 The corrected value is available in ADC COR MOV W amp ADC12MEM0 R10 move result to R10 RLA W R10 R10 x 2 MOV W R10 amp MPY unsigned multiply OP1 MOV W CAL ADC_15VREF_FACTOR R9 amp OP2 Calibration value OP2 MOV W amp RESHI amp ADC_COR result upper 16 bit MPY TLV Structure 22 5 Supported Tags Offset and Gain Calibration Data The offset of the ADC12 is determined and stored as a twos complement number in SegmentA The offset error correction is done by adding the CAL_ADC_OFFSET to the conversion result ADC offset_corrected ADC raw CAL_ADC_OFFSET The gain of the ADC12 stored at offset 0x0
76. 8 3 8 3 8 3 8 3 8 4 8 5 8 6 8 7 Contents 9 Supply Voltage Supervisor o oooocoocccor eee 9 1 9 1 SVS Introduction ra rra laos 9 2 9 2 gt SVS OperatiON awi werd ew io a A E amp 9 4 9 2 1 Configuring the SVS 2 tees 9 4 9 2 2 SVS Comparator Operation aaen aeee 9 4 9 2 3 Changing the VLDx Bits 0 0 cece 9 5 9 2 4 SVS Operating Range 2 cece eens 9 6 93 SVS ReGisSters cece are A A ae ee 9 7 10 Watchdog TiMer oococoocccn eee eee eee e eee eeeeeeee 10 1 10 1 Watchdog Timer Introduction 0 cece eee teens 10 2 10 2 Watchdog Timer Operation 000 eee 10 4 10 2 1 Watchdog timer Counter 0 0 neunana 10 4 10 2 2 Watchdog Mode rod reru E KEA EPERE ARAE EEEREN teens 10 4 10 2 3 Interval Timer Mode nasir raa E a e a e AEN 10 4 10 2 4 Watchdog Timer Interrupts ooccooccococccoocccrr eee 10 5 10 2 5 Watchdog Timer Clock Fail Safe Operation 0005 10 5 10 2 6 Operation in Low Power Modes 00ec cece tence erences 10 6 10 2 7 Software Examples 0 0 c eee eee 10 6 10 3 Watchdog Timer Registers 0 ccc te ete 10 7 11 Hardware Multiplier 000 e eee eee eee e eee en eeeneeee 11 1 11 1 Hardware Multiplier Introduction 0 00 eects 11 2 11 2 Hardware Multiplier Operation 0oocooocccconncccccorarra 11 3 11 2 1 Operand Registers 0 cece
77. C gt dst The source operand and the carry bit C are added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 32 bit counter pointed to by R13 is added to a 32 bit counter eleven words 20 2 2 2 above the pointer in R13 ADD R13 20 R13 ADD LSDs with no carry in ADDC R13 20 R13 ADD MSDs with carry resulting from the LSDs The 24 bit counter pointed to by R13 is added to a 24 bit counter eleven bytes above the pointer in R13 ADD B R13 10 R13 ADD LSDs with no carry in ADDC B R13 10 R13 ADD medium Bits with carry ADDC B R13 10 R13 ADD MSDs with carry resulting from the LSDs RISC 16 Bit CPU 3 23 Instruction Set AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Source AND destination Source AND destination AND src dst or AND W src dst AND B src dst src AND dst gt dst The source operand and the destination operand are logically ANDed The result is placed into the destination N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if result is not zero reset
78. Cs Sampling capacitance Cs AS eo AVcc 2 LE Cs Rs Vs gt ome t Not implemented in MSP430x20x3 devices 1 kQ When the buffers are used Rs does not affect the sampling frequency fs However when the buffers are not used or are not present on the device the maximum sampling frequency fs may be calculated from the minimum settling time tsettling Of the sampling circuit given by GAIN x 2 x V4 Usenting Z Rs 1kQ X Cs x In Vrer where _ 1 _ Lee ES fs Ixi oak and V4 man 7 Vo Voc gt E 2 Vs with Vs and Vs referenced to AVss Cg varies with the gain setting as shown in Table 24 2 Table 24 2 Sampling Capacitance PGA Gain Sampling Capacitance Cs 1 1 25 pF 2 4 2 5 pF 8 5 pF 16 32 10 pF 24 6 SD16_A 24 2 7 Digital Filter SD16_A Operation The digital filter processes the 1 bit data stream from the modulator using a SINC3 comb filter The transfer function is described in the z Domain by OSR 3 H z ok 3 4 TE and in the frequency domain by 3 3 sinc OSRa sin OSR x a X H f lose i OSR f sinc a sin m X fm fu where the oversampling rate OSR is the ratio of the modulator frequency fy to the sample frequency fs Figure 24 3 shows the filter s frequency response for an OSR of 32 The first filter notch is at fg fy OSR The notch s frequency can be adjusted by changing the modulators frequency fm using S
79. DMAxSZ DMAEN 1 DMADTx 1 DMAxSZ gt T_Size DMAxSA gt T_SourceAdd AND ii 0 DMAxDA gt T_DestAdd DMAEN 0 DMAABORT 1 DMAREQ 0 T_Size gt DMAxSZ DMAxSA gt T_SourceAdd DMAABORT 0 DMAxDA gt T_DestAdd Wait for Trigger DMADTx 5 AND DMAxSZ 0 Trigger AND DMALEVEL 0 ANDDMAEN SN OR Trigger 1 AND DMALEVEL 1 2 x MCLK Trigger l Hold CPU Transfer one word byte ENNMI 1 AND NMI event OR DMALEVEL 1 AND Trigger 0 DMAxSZ gt 0 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMA Controller 6 9 DMA Operation Burst Block Transfers In burst block mode transfers are block transfers with CPU activity interleaved The CPU executes 2 MCLK cycles after every four byte word transfers of the block resulting in 20 CPU execution capacity After the burst block CPU execution resumes at 100 capacity and the DMAEN bit is cleared DMAEN must be set again before another burst block transfer can be triggered After a burst block transfer has been triggered further trigger signals occurring during the burst block transfer are ignored The burst block transfer state diagram is shown in Figure 6 5 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 n
80. Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst POP B dst SP gt temp SP 2 gt SP temp gt dst MOV SP dst or MOV W SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack POP B LEO The low byte of the stack is moved to LEO The contents of R7 is restored from the stack POP B R7 The low byte of the stack is moved to R7 the high byte of R7 is OOh The contents of the memory pointed to by R7 and the status register are restored from the stack POP B 0 R7 The low byte of the stack is moved to the the byte which is pointed to by R7 Example R7 203h Mem R7 low byte of system stack Example R7 20Ah Mem R7 low byte of system stack POP SR Last word on stack moved to the SR E a ETS Note The System Stack Pointer The system stack pointer SP is always incremented by two independent of the byte suffix Cd 4 94 16 Bit MSP430X CPU PUSH W PUSH B Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Save a word on the stack Save a
81. FCTL1 in block write mode when WAIT 0 is an access violation and sets ACCVIFG Any write to FCTL2 when the BUSY 1 is an access violation Any FCTLx register may be read when BUSY 1 A read will not cause an access violation Flash Memory Controller 7 17 Flash Memory Operation 7 3 8 Flash Memory Controller Interrupts The flash controller has two interrupt sources KEYV and ACCVIFG ACCVIFG is set when an access violation occurs When the ACCVIE bit is re enabled after a flash write or erase a set ACCVIFG flag will generate an interrupt request ACCVIFG sources the NMI interrupt vector so it is not necessary for GIE to be set for ACCVIFG to request an interrupt ACCVIFG may also be checked by software to determine if an access violation occurred ACCVIFG must be reset by software The key violation flag KEYV is set when any of the flash control registers are written with an incorrect password When this occurs a PUC is generated immediately resetting the device 7 3 9 Programming Flash Memory Devices There are three options for programming an MSP430 flash device All options support in system programming Lj Program via JTAG Y Program via the Bootstrap Loader Y Program via a custom solution Programming Flash Memory via JTAG MSP430 devices can be programmed via the JTAG port The JTAG interface requires four signals 5 signals on 20 and 28 pin devices ground and optionally Vcc and RST NMI The JTAG port
82. Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Port Select 2 Resistor Enable Input Output Direction Interrupt Flag Interrupt Edge Select Interrupt Enable Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Short Form P1IN P1OUT P1DIR P1IFG P1IES P11E P1SEL P1SEL2 P1REN P2IN P20UT P2DIR P2IFG P2IES P2lE P2SEL P2SEL2 P2REN P3IN P3OUT P3DIR P3SEL P3SEL2 P3REN P4IN P4OUT P4DIR P4SEL P4SEL2 P4REN P5IN P5OUT P5DIR P5SEL P5SEL2 P5REN Address 020h 021h 022h 023h 024h 025h 026h 041h 027h 028h 029h 02Ah 02Bh 02Ch 02Dh 02Eh 042h 02Fh 018h 019h 01Ah 01Bh 043h 010h 01Ch 01Dh 01Eh 01Fh 044h 011h 030h 031h 032h 033h 045h 012h Register Type Read only Read write Read write Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Digital I O Registers Initial State Unchanged Reset with PUC Reset with PUC Unchanged Re
83. JMP ADMO Vector 6 ADC12IFGO 2 ae Vectors 8 32 2 JMP ADM14 Vector 34 ADC12IFG14 2 Handler for ADC12IFG15 starts here No JMP required ADM15 MOV amp ADC12MEM15 xxx Move result flag is reset Rees Other instruction needed JMP INT _ADC12 Check other int pending ADC12IFG14 ADC12IFG1 handlers go here ADMO MOV amp ADC12MEM0 xxx Move result flag is reset Other instruction needed RETI Return 5 ADTOV ria Handle Conv time overflow RETI Return 5 ADOV Hana Handle ADCMEMx overflow RETI Return 5 ADC12 21 19 ADC12 Registers 21 3 ADC12 Registers The ADC12 registers are listed in Table 21 2 Table 21 2 ADC12 Registers Register Short Form Register Type Address Initial State ADC12 control register O ADC12CTLO Read write 01A0h Reset with POR ADC 12 control register 1 ADC12CTL1 Read write 01A2h Reset with POR ADC12 interrupt flag register ADC12IFG Read write 01A4h Reset with POR ADC12 interrupt enable register ADC12IE Read write 01A6h Reset with POR ADC12 interrupt vector word ADC12IV Read 01A8h Reset with POR ADC12 memory 0 ADC12MEMO Read write 0140h Unchanged ADC12 memory 1 ADC12MEM1 Read write 0142h Unchanged ADC12 memory 2 ADC12MEM2 Read write 0144h Unchanged ADC12 memory 3 ADC12MEM3 Read write 0146h Unchanged ADC12 memory 4 ADC12MEM4 Read write 0148h Unchanged ADC12 memory 5 ADC12MEM5 Read write 014Ah Unchanged ADC12 memory 6 ADC12MEM6 Read write 014Ch Unchanged ADC12 memory 7 ADC12MEM7 Read wri
84. LSBs The MSBs have the address R5 2 Indirect indirect R5 BRA R5 MOVA R5 PC Indirect Auto Increment Mode Branch to the 20 bit address contained in the words pointed to by register R5 and increment the address in R5 afterwards by 4 The next time the S W flow uses R5 as a pointer it can alter the program execution due to access to the next address in the table pointed to by R5 Indi rect indirect R5 BRA R5 MOVA R5 PC R5 4 Indexed Mode Branch to the 20 bit address contained in the address pointed to by register R5 X e g a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the address X is within R5 32 K Indirect indirect R5 X BRA X R5 MOVA z16 R5 PC Note if the 16 bit index is not sufficient a 20 bit index X may be used with the following instruction MOVX A X R5 PC 1M byte range with 20 bit index 4 158 16 Bit MSP430X CPU CALLA Syntax Operation Description Status Bits Mode Bits Examples Address Instructions Call a Subroutine CALLA dst dst tmp 20 bit dst is evaluated and stored SP 2 gt SP PC 19 16 gt SP_ updated PC with return address to TOS MSBs SP 2 gt SP PC 15 0 gt SP updated PC to TOS LSBs tmp gt PC saved 20 bit dst to PC A subroutine call is made to a 20 bit address anywhere in the full address space All seven source addressing modes can be used The call instruction is an
85. Mode 0 cece eee nes 4 18 4 4 3 Symbolic Mode oococccccccnncccc eee 4 24 4 4 4 Absolute Mode cceeaei eed RARA A RRA 4 29 4 4 5 Indirect Register Mode 0 cece cece ees 4 32 4 4 6 Indirect Autoincrement Mode 0 00 c cece ee eee eee 4 33 4 4 7 Immediate Mode 0 00 cece ees 4 34 4 5 MSP430 and MSP430X Instructions 00 cece ees 4 36 4 5 1 MSP430 Instructions 0 00 cece eens 4 37 4 5 2 MSP430X Extended Instructions 00 0c eee eee 4 44 4 6 Instruction Set Description ooooocccccccccccnnncrrn eens 4 58 4 6 1 Extended Instruction Binary Descriptions o ooooooooom ooo 4 59 4 6 2 MSP430 Instructions 00 eects 4 61 4 6 3 Extended Instructions 0 cece cee 4 113 4 6 4 Address Instructions 0 cece cette 4 156 Basic Clock Module to is 5 1 5 1 Basic Clock Module Introduction 0 00 cece eee ees 5 2 5 2 Basic Clock Module Operation 000 ccc e eee eee eens 5 4 5 2 1 Basic Clock Module Features for Low Power Applications 5 4 5 2 2 Internal Very Low Power Low Frequency Oscillator 5 4 52 3 LEXT T Oscillator cu ct teiae pts la ds 5 5 5 2 4 XTZ Oscillator coo eee Gs ate eet ede Siege 5 6 5 2 5 Digitally Controlled Oscillator DCO 0 0 0 cece ee eee 5 6 5 2 66 DCO Modulator 0 0 cee eee 5 9 5 2 7 Basic Clock
86. Module Fail Safe Operation 20 0000e 5 10 5 2 8 Synchronization of Clock Signals 0066 e cece eee eee 5 12 5 3 Basic Clock Module Registers 00 cece eee etnies 5 13 Contents 6 DMA Controller a A A e 6 1 DMA Introduction s sista eeir aaa ete n etnies 6 2 DMA Operations since esc li id eae Gh ae 6 2 1 DMA Addressing Modes 0 00 cece 6 2 2 DMA Transfer Modes cece eee eee nes 6 2 3 Initiating DMA Transfers 0 ccc eee 6 2 4 Stopping DMA Transfers 00 cee 6 2 5 DMA Channel Priorities 0c cece eee 6 2 6 DMA Transfer Cycle Time ooocccccccccccc 6 2 7 Using DMA with System Interrupts 0600 cece eee eee ee 6 2 8 DMA Controller Interrupts 000 e eects 6 2 9 Using the USCI_B 12C Module with the DMA Controller 6 2 10 Using ADC12 with the DMA Controller 0 cece ee eee 6 2 11 Using DAC12 With the DMA Controller 0000 sees 6 2 12 Writing to Flash With the DMA Controller 0000000e ee 6 3 DMARegisters E E A a O EAE eee eee ees 7 Flash Memory Controller oooooooocccccocnncrr eee eee eee 7 1 Flash Memory Introduction cooccoocccocccnrccrrc ene 7 2 Flash Memory Segmentation 0 00 cece eee eee tenes L210 SCOMENA eisai ities tytaniadeslnd Voce eeee nde dee atigheanased 7 3 Flash Memory Operation
87. Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not used for MCLK or SMCLK CPUOFF CPU off This bit when set turns off the CPU GIE General interrupt enable This bit when set enables maskable inter rupts When reset all maskable interrupts are disabled N Negative bit This bit is set when the result of an operation is negative and cleared when the result is positive Z Zero bit This bit is set when the result of an operation is zero and cleared when the result is not zero C Carry bit This bit is set when the result of an operation produced a carry and cleared when no carry occurred 16 Bit MSP430X CPU 4 9 CPU Registers 4 3 4 The Constant Generator Registers CG1 and CG2 Six commonly used constants are generated with the constant generator registers R2 CG1 and R3 CG2 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 4 2 Table 4 2 Values of Constant Generators CG1 CG2 Register As Constant Remarks R2 00 Register mode R2 01 0 Absolute address mode R2 10 00004h 4 bit processing R2 11 00008h 8 bit processing R3 00 00000h 0 word processing R3 01 00001h 1 R3 10 00002h 2 bit processing R3 11 FFh FFFFh FFFFFh 1 word processing The constant generator advantages are Lj No special instructions required Li No additional code word f
88. PC If N xor V 1 execute following instruction The negative bit N and the overflow bit V in the status register are tested If both bits are set or both are reset the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in full Memory range If only one bit is set the instruction after the jump is executed JGE is used for the comparison of signed operands also for incorrect results due to overflow the decision made by the JGE instruction is correct Note JGE emulates the non implemented JP jump if positive instruction if used after the instructions AND BIT RRA SXTX and TST These instructions clear the V bit Status bits are not affected OSCOFF CPUOFF and GIE are not affected If byte EDE lower 64 K contains positive data go to Label1 Software can run in the full memory range TST B amp EDE Is EDE positive V lt 0 JGE Label1 Yes JGE emulates JP No 80h lt EDE lt FFh If the content of R6 is greater than or equal to the memory pointed to by R7 the program continues a Label5 Signed data Data and program in full memory range CMP R7 R6 ls R6 gt R7 JGE Label5 Yes go to Label5 No continue here If R5 gt 12345h signed operands the program continues at Label2 Program in full memory range CMPA 12345h R5 Is R5 gt 12345h JG
89. R10 LP1 ADD W 2 R10 Skip two bytes CMP W 0x10FF R10 SegmentA end reached JGE DONE Yes done CMP B TAG EMPTY 0 R10 TAG EMPTY JNZ T1 No continue JMP LP2 Yes done with TAG_EMPTY T1 CMP B TAG_ADC12_1 0 R10 TAG_ADC12_1 JNZ T2 No continue Yes found TAG ADC12 1 JMP LP2 Done with TAG ADC12 1 T2 CMP B DCO_30 0 R10 TAG_DCO 30 JNZ T3 No continue CLR B amp DCOCTL Select lowest DCOx MOV B 7 R10 amp BCSCTL1 Yes use e g 8MHz data and MOV B 6 R10 amp DCOCTL set DCOx and MODx JMP LP2 Done with TAG_DCO 30 T3 bibs Test for next tag JMP LP2 Done with next tag LP2 MOV B 1 R10 R11 Store LENGTH in R11 ADD W R11 R10 Add LENGTH to R10 JMP LP1 Jump to continue analysis DONE i 22 8 TLV Structure Chapter 23 DAC12 The DAC12 module is a 12 bit voltage output digital to analog converter This chapter describes the operation of the DAC12 module of the MSP430 2xx device family Topic Page 23 1 DACI2 Introduction e a pa 23 2 23 2BDAC12 OOO ia 23 4 23 3 DAGC12 Registers oo al 23 10 23 1 DAC12 Introduction 23 1 DAC12 Introduction 23 2 DAC12 The DAC12 module is a 12 bit voltage output DAC The DAC12 can be configured in 8 or 12 bit mode and may be used in conjunction with the DMA controller When multiple DAC12 modules are present they may be grouped together for synchronous update operation Features of the DAC12 include
90. R11 The registers are not modified Comment Valid only for source operand The substitute for destination operand is O Ra Example MOV B R10 0 R11 Before After Address Register Address Register Space Space Oxxxxh Oxxxxh PC OFF16h 0000h R10 OFA33h OFF16h 0000h R10 OFA33h OFF14h OFF12h O4AEBh PC R11 002A7h OFF14h 04AEBh R11 002A7h OFA32h 05BC1h OFA32h 05BC1h 002A8h 002A8h 002A7h 002A7h 002A6h 002A6h 3 14 RISC 16 Bit CPU Indirect Autoincrement Mode Addressing Modes The indirect autoincrement mode is described in Table 3 9 Table 3 9 Indirect Autoincrement Mode Description Assembler Code MOV R10 0 R11 Content of ROM MOV R10 0 R11 Move the contents of the source address contents of R10 to the destination address contents of R11 Register R10 is incremented by 1 for a byte operation or 2 for a word operation after the fetch it points to the next address without any overhead This is useful for table processing Valid only for source operand The substitute for destination operand is 0 Rd plus second instruction INCD Rd Length One or two words Operation Comment Example MOV R10 0 R11 Before Address Register Space OFF18h OFF16h OFF14h OFF12h OFA34h OFA32h OFA30h 010AAh 010A8h 010A6h Address Space boon Pc Register OFF18h OFF16h OFF 14h OFF12h R10 OFA34h R11 010A8h OFA34h OFA32h OFA30h 010A
91. SR All interrupts are disabled The constant 08h is inverted and logically ANDed with the status register SR The result is placed into the SR Status bits are not affected GIE is reset OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is cleared to allow a nondisrupted move of a 32 bit counter This ensures that the counter is not modified during the move by any interrupt DINT All interrupt events using the GIE bit are disabled NOP MOV COUNTHI R5 Copy counter MOV COUNTLO R6 EINT All interrupt events using the GIE bit are enabled TS Note Disable Interrupt If any code sequence needs to be protected from interruption the DINT should be executed at least one instruction before the beginning of the uninterruptible sequence or should be followed by a NOP instruction RISC 16 Bit CPU 3 39 Instruction Set EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable general interrupts EINT 1 gt GIE or 0008h OR SR gt SR src OR dst gt dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the r
92. SVSOP Bit 1 SVS output This bit reflects the output value of the SVS comparator 0 SVS comparator output is low 1 SVS comparator output is high SVSFG Bit O SVS flag This bit indicates a low voltage condition SVSFG remains set after a low voltage condition until reset by software 0 No low voltage condition occurred 1 A low condition is present or has occurred Supply Voltage Supervisor 9 7 9 8 Supply Voltage Supervisor Chapter 10 Watchdog Timer The watchdog timer WDT is a 16 bit timer that can be used as a watchdog or as an interval timer This chapter describes the WDT The WDT is implemented in all MSP430x2xx devices Topic Page 10 1 Watchdog Timer Introduction o oooooooccocnnnoooo 10 2 10 2 Watchdog Timer Operation 0c eee eee eee 10 4 10 3 Watchdog Timer Registers ccc cece eee eee eee 10 7 10 1 Watchdog Timer Introduction 10 1 Watchdog Timer Introduction 10 2 The primary function of the watchdog timer WDT module is to perform a controlled system restart after a software problem occurs If the selected time interval expires a system reset is generated If the watchdog function is not needed in an application the module can be configured as an interval timer and can generate interrupts at selected time intervals Features of the watchdog timer module include Four software selectable time intervals Watchdog mode Interval mode Access to W
93. Status Bits Mode Bits Example Instruction Set Clear zero bit CLRZ 0 gt Z or NOT src AND dst gt dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ RISC 16 Bit CPU 3 33 Instruction Set CMP W CMP B Syntax Operation Description Status Bits Mode Bits Example Example Example Compare source and destination Compare source and destination CMP src dst or CMP W src dst CMP B src dst dst NOT src 1 or dst src The source operand is subtracted from the destination operand This is accomplished by adding the 1s complement of the source operand plus 1 The two operands are not affected and the result is not stored only the status bits are affected N Set if result is negative reset if positive src gt dst Z Set if result is zero reset otherwise src dst C Set if there is a carry from the MSB of the result reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 and R6 are compared If they are equal the program continues at the label EQUAL CMP R5 R6 R5 R6 JEQ EQUAL YES JUMP Tw
94. Transmitter Mode Reception of own s address and transmission of data bytes Repeated start continue as slave transmitter Repeated start continue as slave receiver master and addressed as slave SLA R A DATA A DATA x 222 UCTR 1 Transmitter Write data to UCBxTXBUF UCBxTXIFG 0 UCSTTIFG 1 VEBERG UCSTPIFG 0 UCBxTXIFG 1 UCSTPIFG 1 UCBxTXBUF discarded UCSTTIFG 0 Bus stalled SCL held low until data available Write data to UCBxTXBUF UCBxTXIFG 0 UCTR 1 Transmitter UCSTTIFG 1 UCBxTXIFG 1 UCBxTXBUF discarded UCBxTXIFG 0 Arbitration lost as ns A UCTR 0 Receiver r UCSTTIFG 1 UCALIFG 1 UCMST 0 UCTR 1 Transmitter UCSTTIFG 1 UCBxTXIFG 1 UCSTPIFG 0 USCI Operation C Mode Universal Serial Communication Interface C Mode 17 11 USCI Operation C Mode 12C Slave Receiver Mode Slave receiver mode is entered when the slave address transmitted by the master is identical to its own address and a cleared R W bit is received In slave receiver mode serial data bits received on SDA are shifted in with the clock pulses that are generated by the master device The slave device does not generate the clock but it can hold SCL low if intervention of the CPU is required after a byte has been received If the slave should receive data from the master the
95. USCI module is automatically configured as a receiver and UCTR is cleared After the first data byte is received the receive interrupt flag UCBxRXIFG is set The USCI module automatically acknowledges the received data and can receive the next data byte If the previous data wasn not read from the receive buffer UCBxRXBUF at the end of a reception the bus is stalled by holding SCL low As soon as UCBxRXBUF is read the new data is transferred into UCBxRXBUF an acknowledge is sent to the master and the next data can be received Setting the UCTXNACK bit causes a NACK to be transmitted to the master during the next acknowledgment cycle A NACK is sent even if UCBxRXBUF is not ready to receive the latest data If the UCTXNACK bit is set while SCL is held low the bus will be released a NACK is transmitted immediately and UCBxRXBUF is loaded with the last received data Since the previous data was not read that data will be lost To avoid loss of data the UCBxRXBUF needs to be read before UCTXNACK is set When the master generates a STOP condition the UCSTPIFG flag is set If the master generates a repeated START condition the USCI I C state machine returns to its address reception state Figure 17 10 illustrates the the 12C slave receiver operation 17 12 Universal Serial Communication Interface 12C Mode Figure 17 10 Reception of own address and data bytes All are acknowledged UCTR 0 Receiver UCSTTIFG 1 UCSTPIFG 0
96. Wait until ADC10MEM is written Write to ADC10MEM completed Write to ADC10SA Wait for CPU ready Synchronize with MCLK DTC operation Write to ADC10SA 1 x MCLK cycle Transfer data to Address AD AD AD 2 ADC10TB 0 and x 0 ADC10CT 1 ADC10TB 0 and ADC10CT 0 ADC10 20 17 ADC10 Operation Two Block Transfer Mode The two block mode is selected if the ADC10TB bit is set The value n in ADC10DTC1 defines the number of transfers for one block The address range of the first block is defined anywhere in the MSP430 address range with the 16 bit register ADC10SA The first block ends at ADC10SA 2n 2 The address range for the second block is defined as SA 2n to SA 4n 2 The two block transfer mode is shown in Figure 20 11 Figure 20 11 Two Block Transfer 20 18 ADC10 TB 1 2 x r th transfer ADC10SA 4n 2 ADC10SA 4n 4 DTC n th transfer ADC10SA 2n 2 ADC10SA 2n 4 2nd transfer ADC10SA 2 1st transfer ADC10SA The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC
97. While BUSY 1 Flash Flash WAIT Result Operation Access Read 0 ACCVIFG 0 O3FFFh is the value read Any erase or Write O ACCVIFG 1 Write is ignored Byte word write inetuction 0 ACCVIFG 0 CPU fetches 03FFFh This fetch is the JMP PC instruction Any 0 ACCVIFG 1 LOCK 1 Read 1 ACCVIFG 0 O3FFFh is the value read Block write Write 1 ACCVIFG 0 Write is written Instruction 1 ACCVIFG 1 LOCK 1 fetch Interrupts are automatically disabled during any flash operation when EEl O and EEIEX 0 and on MSP430x20xx devices where EEI and EEIEX are not present After the flash operation has completed interrupts are automatically re enabled Any interrupt that occurred during the operation will have its associated flag set and will generate an interrupt request when re enabled When EEIEX 1 and GIE 1 an interrupt will immediately abort any flash operation and the FAIL flag will be set When EEl 1 GIE 1 and EEIEX 0 a segment erase will be interrupted by a pending interrupt every 32 frtg cycles After servicing the interrupt the segment erase is continued for at least 32 frre cycles or until it is complete During the servicing of the interrupt the BUSY bit remains set but the flash memory can be accessed by the CPU without causing an access violation occurs Nested interrupts and using the RETI instruction inside interrupt service routines are not supported The watchdog timer in watchdog mode should be disabled before a
98. a byte or word is written for 27 of the 30 frre cycles With each byte or word write the amount of time the block is subjected to the programming voltage accumulates The cumulative programming time tcpy must not be exceeded for any block If the cumulative programming time is met the block must be erased before performing any further writes to any address within the block See the device specific data sheet for specifications Initiating a Byte Word Write from Within Flash Memory The flow to initiate a byte word write from flash is shown in Figure 7 8 Figure 7 8 Initiating a Byte Word Write from Flash Disable watchdog Setup flash controller and set WRT 1 Write byte or word Set WRT 0 LOCK 1 re enable watchdog Byte word write from flash 514 kHz lt SMCLK lt 952 kHz Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD amp WDTCTL Disable WDT MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY WRT FCTL1 Enable write MOV 0123h amp OFF1Eh 0123h gt OFF1Eh MOV FWKEY amp FCTL1 Done Clear WRT MOV FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT Flash Memory Controller 7 11 Flash Memory Operation Initiating a Byte Word Write from RAM The flow to initiate a byte word write from RAM is shown in Figure 7 9 Figure 7 9 Initiating a Byte Word Write from RAM Disable watchdog Set WRT 0 LOCK 1
99. access and branching throughout entire memory range 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides six most used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Word and byte addressing and instruction formats The block diagram of the CPU is shown in Figure 3 1 RISC 16 Bit CPU CPU Introduction Figure 3 1 CPU Block Diagram MDB Memory Data Bus Memory Address Bus MAB 15 0 RO PC Program Counter oE gt 16 16 Negative N RISC 16 Bit CPU 3 3 CPU Registers 3 2 CPU Registers The CPU incorporates sixteen 16 bit registers RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 3 2 1 Program Counter PC The 16 bit program counter PC RO points to the next instruction to be executed Each instruction uses an even number of bytes two four or six and the PC is incremented accordingly Instruction accesses in the 64 KB address space are performed on word boundaries and the PC is aligned to even addresses Figure 3 2 shows the program counter Figure 3 2 Program Counter 15 t0 Program Counter Bits 15 to 1 E3 The PC can be addressed with all instructions and addressing modes A few examples MOV LABEL PC Branch to address LABEL MOV LABEL PC Branch to address contained in LABEL MOV R14 PC Branch indirect to address in R14 3 4 RISC 16 Bit CP
100. accessible and contains the last received 7 0 character from the receive shift register Reading UCAxRXBUF resets the receive error bits the UCADDR or UCIDLE bit and UCAXRXIFG In 7 bit data mode UCAxRXBUF is LSB justified and the MSB is always reset UCAxTXBUF USCI_Ax Transmit Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to 7 0 be moved into the transmit shift register and transmitted on UCAxTXD Writing to the transmit data buffer clears UCAxTXIFG The MSB of UCAxTXBUF is not used for 7 bit data and is reset 15 32 Universal Serial Communication Interface UART Mode USCI Registers UART Mode UCAxIRTCTL USCI_Ax IrDA Transmit Control Register 5 4 3 2 1 0 UCIRTXPLx TEK UCIREN UCIRTXPLx UCIRTXCLK UCIREN Bits 7 2 Bit 1 Bit O rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Transmit pulse length Pulse Length TPULSE UCIRTXPLx 1 2 fiRTXCLK IrDA transmit pulse clock select 0 BRCLK 1 BITCLK16 when UCOS16 1 Otherwise BRCLK IrDA encoder decoder enable 0 IrDA encoder decoder disabled 1 IrDA encoder decoder enabled UCAxIRRCTL USCI_Ax IrDA Receive Control Register 5 4 3 2 1 0 UCIRRXFLx UCIRRXPL UCIRRXFE UCIRRXFLx UCIRRXPL UCIRRXFE Bits 7 2 Bit 1 Bit O rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Receive filter length The minimum pulse length for receive is given by twin UCIRRXFLx 4 2 f
101. address followed by the ACK bit and the 8 bit data Figure 17 6 I C Module 10 Bit Addressing Format Ei i ea ee i TAL T eae Slave Address 1st byte Slave Address 2nd bytel ACK Data ACK P 1 11 4 0X X Repeated Start Conditions The direction of data flow on SDA can be changed by the master without first stopping a transfer by issuing a repeated START condition This is called a RESTART After a RESTART is issued the slave address is again sent out with the new data direction specified by the R W bit The RESTART condition is shown in Figure 17 7 Figure 17 7 12C Module Addressing Format with Repeated START Condition 1 KTM 1 1 8 1 E TES CAES 1 1 H 8 1 1 Ls Slave Address RW Ack Data ACK S Slave Address RW ack Data Ack P k 1 ole Any k 1 rte Any Number gt Number 17 8 Universal Serial Communication Interface 12C Mode USCI Operation C Mode 17 3 4 12C Module Operating Modes In 12C mode the USCI module can operate in master transmitter master receiver slave transmitter or slave receiver mode The modes are discussed in the following sections Time lines are used to illustrate the modes Figure 17 8 shows how to interpret the time line figures Data transmitted by the master is represented by grey rectangles data transmitted by the slave by white rectangles Data transmitted by the USCI module either as master or slave is shown by rectangles that are taller
102. and VR Vss 010 VR VeREF and Vp Vss 011 Vp Buffered Verer and Vp Vss 100 Vp Vcc and Vp Vrer_ Verer 101 Vp Vprer and Vp Vrer VererF 110 Vpr Veper and Vp Vrer VererF 111 VR Buffered Verger and Vp VreF VererF ADC10 Bits ADC10 sample and hold time SHTx 12 11 00 4xADC10CLKs 01 8xADC10CLKs 10 16xADC10CLKs 11 64xADC10CLKs ADC10SR Bit10 ADC10 sampling rate This bit selects the reference buffer drive capability for the maximum sampling rate Setting ADC10SR reduces the current consumption of the reference buffer 0 Reference buffer supports up to 200 ksps 1 Reference buffer supports up to 50 ksps REFOUT Bit 9 Reference output 0 Reference output off 1 Reference output on REFBURST Bit 8 Reference burst 0 Reference buffer on continuously 1 Reference buffer on only during sample and conversion ADC10 20 25 ADC10 Registers MSC REF2_5V REFON ADC100N ADC10IE ADC10IFG ENC ADC10SC 20 26 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ADC10 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set
103. at X X can be an address or a label Core instruction MOV X R5 PC Indirect indirect R5 X 4 68 16 Bit MSP430X CPU CALL Syntax Operation Description Status Bits Mode Bits Examples MSP430 Instructions Call a Subroutine in lower 64 K CALL dst dst gt tmp 16 bit dst is evaluated and stored SP 2 gt SP PC SP updated PC with return address to TOS tmp PC saved 16 bit dst to PC A subroutine call is made from an address in the lower 64 K to a subroutine address in the lower 64 K All seven source addressing modes can be used The call instruction is a word instruction The return is made with the RET instruction Not affected PC 19 16 Cleared address in lower 64 K OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC lower 64 K or call directly to address CALL EXEC Start address EXEC CALL 0AA04h Start address OAA04h Symbolic Mode Call a subroutine at the 16 bit address contained in address EXEC EXEC is located at the address PC X where X is within PC 32 K CALL EXEC Start address at EXEC z16 PC Absolute Mode Call a subroutine at the 16 bit address contained in absolute address EXEC in the lower 64 K CALL amp EXEC Start address at EXEC Register Mode Call a subroutine at the 16 bit address contained in register R5 15 0 CALL R5 Start address at R5 Indirect Mode Call a subr
104. be triggered After a block transfer has been triggered further trigger signals occurring during the block transfer are ignored The block transfer state diagram is shown in Figure 6 4 The DMAxSZ register is used to define the size of the block and the DMADSTINCRx and DMASRCINCRx bits select if the destination address and the source address are incremented or decremented after each transfer of the block If DMAxSZ 0 no transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set During a block transfer the CPU is halted until the complete block has been transferred The block transfer takes 2 x MCLK x DMAxSZ clock cycles to complete CPU execution resumes with its previous state after the block transfer is complete In repeated block transfer mode the DMAEN bit remains set after completion of the block transfer The next trigger after the completion of a repeated block transfer triggers another block transfer 6 8 DMA Controller DMA Operation Figure 6 4 DMA Block Transfer State Diagram DMAEN 0 DMAEN 0 DMAREQ 0 y T_Size gt
105. before the conversion is completed immediately stops conversion of the channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMO can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMO be read prior to clearing SD16SC to avoid reading an invalid result 24 12 SD16_A SD16_A Operation Continuous Conversion When SD16SNGL 0 continuous conversion mode is selected Conversion of the channel will begin when SD16SC is set and continue until the SD16SC bit is cleared by software Clearing SD16SC immediately stops conversion of the selected channel the channel is powered down and the corresponding digital filter is turned off The value in SD16MEMO can change when SD16SC is cleared It is recommended that the conversion data in SD16MEMO be read prior to clearing SD16SC to avoid reading an invalid result Figure 24 7 shows conversion operation Figure 24 7 Single Channel Operation Conversion de SD16SNGL 1 SD16SC Set by SW Auto clear Conversion Y Cowersion Comersion com SD16SNGL 0 SD16SC 4 Set by SW Cleared by SW y gt O Result written to SD16MEMO Time SD16_A 24 13 SD16_A Operation 24 2 10 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input pair SD16INCHx 110 and sets SD16REFON 1 Any other configuration is done as if an external analog input pair wa
106. byte on the stack PUSH dst or PUSH W dst PUSH B dst SP 2 gt SP dst gt SP The 20 bit stack pointer SP is decremented by two The operand is then copied to the RAM word addressed by the SP A pushed byte is stored in the low byte the high byte is not affected Not affected OSCOFF CPUOFF and GIE are not affected Save the two 16 bit registers R9 and R10 on the stack PUSH R9 Save R9 and R10 XXXXh PUSH R10 YYYYh Save the two bytes EDE and TONI on the stack The addresses EDE and TONI are within PC 32 K PUSH B EDE Save EDE xxXXh PUSH BB TONI Save TONI xxYYh 16 Bit MSP430X CPU 4 95 MSP430 Instructions RET Syntax Operation Description Status Bits Mode Bits Example SUBR Return from subroutine RET SP gt PC 15 0 Saved PC to PC 15 0 PC 19 16 0 SP 2 gt SP The 16 bit return address lower 64 K pushed onto the stack by a CALL instruction is restored to the PC The program continues at the address following the subroutine call The four MSBs of the program counter PC 19 16 are cleared Not affected PC 19 16 Cleared OSCOFF CPUOFF and GIE are not affected Call a subroutine SUBR in the lower 64 K and return to the address in the lower 64K after the CALL CALL SUBR Call subroutine starting at SUBR EA Return by RET to here PUSH R14 Save R14 16 bit data Subroutine code POP R14 Restore R14 RET Return to lower 64 K Figure 4 37 The Stack After a RET Instruct
107. byte to word or word to byte When transferring word to byte only the lower byte of the source word transfers When transferring byte to word the upper byte of the destination word is cleared when the transfer occurs Figure 6 2 DMA Addressing Modes 6 4 DMA Cont Fixed Address To Fixed Address roller DMA Cont Block Of Addresses To Fixed Address roller DMA Address Space Address Space Fixed Address To Block Of Addresses DMA Address Space Address Space Block Of Addresses To Block Of Addresses DMA Controller 6 2 2 DMA Transfer Modes DMA Operation The DMA controller has six transfer modes selected by the DMADTx bits as listed in Table 6 1 Each channel is individually configurable for its transfer mode For example channel 0 may be configured in single transfer mode while channel 1 is configured for burst block transfer mode and channel 2 operates in repeated block mode The transfer mode is configured independently from the addressing mode Any addressing mode can be used with any transfer mode Two types of data can be transferred selectable by the DMAxCTL DSTBYTE and SRCBYTE fields The source and or destination location can be either byte or word data It is also possible to transfer byte to byte word to word or any combination Table 6 1 DMA Transfer Modes DMADTx 000 001 010 011 100
108. contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If Z is set the instruction after the jump is executed JNZ is used for the test of the Zero bit Z JNE is used for the comparison of operands Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte STATUS is tested If it is not zero the program continues at Label3 The address of STATUS is within PC 32 K TST B STATUS Ils STATUS 0 JNZ Label3 No proceed at Label3 Yes continue here If word EDE 1500 the program continues at Label2 Data in lower 64 K program in full memory range CMP 1500 amp 8EDE ls EDE 1500 Info to SR JNE Label2 No EDE 1500 Yes R5 1500 Continue R7 20 bit counter is decremented If its content is not zero the program continues at Label4 Program in full memory range SUBA 1 R7 Decrement R7 JNZ Label4 Zero not reached Go to Label4 Yes R7 0 Continue here 16 Bit MSP430X CPU 4 91 MSP430 Instructions MOV W MOV B Syntax Operation Description Status Bits Mode Bits Example Example Loop Example Loop Move source word to destination word Move source byte to destination byte MOV src dst or MOV W src dst MOV B src dst src gt dst The source operand is copied to the destination The source operand is n
109. data are right justified Bit 11 is the MSB 12 bit 2s complement The DAC 12 data are right justified Bit 11 is the MSB sign 8 bit binary The DAC 12 data are right justified Bit 7 is the MSB Bits 11 8 are don t care and do not effect the DAC12 core 8 bit 2s complement The DAC12 data are right justified Bit 7 is the MSB sign Bits 11 8 are don t care and do not effect the DAC 12 core DAC12 23 13 23 14 DAC12 Chapter 24 SD16 A The SD16_A module is a single converter 16 bit sigma delta analog to digital conversion module with high impedance input buffer This chapter describes the SD16_A The SD16_A module is implemented in the MSP430x20x3 devices Topic Page PA pa oDIOSAMINtroductionee ere eee CL LEE E TAA 24 2 24 2 SDI6 A Operation 225 22 2 nsec neces cece msn ose e dele cis ese 24 4 24 32 SD16 FA REGISLEMS e sate a e aie cteyesotieys alero else 24 16 24 1 SD16_A Introduction 24 1 SD16_A Introduction 24 2 SD16_A The SD16_A module consists of one sigma delta analog to digital converter with a high impedance input buffer and an internal voltage reference It has up to eight fully differential multiplexed analog input pairs including a built in temperature sensor and a divided supply voltage The converter is based on a second order oversampling sigma delta modulator and digital decimation filter The decimation filter is a comb type filter with selectable oversampling ratios of up to 1
110. eee eee 11 3 11 2 2 Result Registers 0 eee eens 11 4 11 2 3 Software Examples 000 c naeun annee 11 5 11 2 4 Indirect Addressing of RESLO 0 000 cece eee 11 6 11 2 5 Using Interrupts acue soak a ere sass eee pe A e 11 6 11 3 Hardware Multiplier Registers 0 0 cece ects 11 7 T2 TUMOR As aati NN 12 1 12 1 Timer_A Introduction 0 ccc cece eee ees 12 2 12 2 Timer_A Operation 0 0 cece ete eee 12 4 12 2 1 16 Bit Timer Counter 0 0 0 cece eens 12 4 12 2 2 Starting the Timer 0 cece teens 12 5 12 2 3 Timer Mode Control 0 0 0 cece eee 12 5 12 2 4 Capture Compare Blocks 000 cece eens 12 11 12 297 Output UNI darla wea dace 12 13 12 2 6 Timer_A Interrupts 0 0c cece ee teens 12 17 12 3 Timer A Registers oee 33 Nea been Gad cena eRe ed 12 19 Contents 13 Timer Bid dt 13 1 13 1 Timer_B Introduction 0 0 ccc eee e ne eee 13 2 13 1 1 Similarities and Differences From Timer_A 000000 c cease 13 2 13 2 Timer_B Operation ossi iee a da i E eee 13 4 13 2 1 16 Bit Timer Counter 0 00 13 4 13 2 2 Starting the Timer oooooccccccccccccno 13 5 13 2 3 Timer Mode Control 00 00 ccc cece teens 13 5 13 2 4 Capture Compare Blocks 000 e eee teens 13 11 13 2 5 Outout Unit iia arta dal Ai aii 13 14 13 2 6 Timer_B Interrupts 0ooocccocconncnnnrn Tana aeiee
111. ends normally 0 Unlocked 1 Locked Wait Indicates the flash memory is being written to 0 The flash memory is not ready for the next byte word write 1 The flash memory is ready for the next byte word write Access violation interrupt flag 0 No interrupt pending 1 Interrupt pending Flash Memory Controller 7 23 Flash Memory Registers KEYV Bit 1 Flash security key violation This bit indicates an incorrect FCTLx password was written to any flash control register and generates a PUC when set KEYV must be reset with software 0 FCTLx password was written correctly 1 FCTLx password was written incorrectly BUSY Bit O Busy This bit indicates the status of the flash timing generator 0 Not Busy 1 Busy 7 24 Flash Memory Controller Flash Memory Registers FCTLA Flash Memory Control Register FCTL4 optional refer to device specific data sheet 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as OA5h 7 5 4 3 2 1 0 0 r 0 r 0 r 0 r 0 rw 0 rw 0 r 0 r FWKEYx Reserved MRG1 MRGO Reserved Bit 4 Bits 3 0 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Reserved Always read as 0 Marginal read 1 mode This bit enables the marginal 1 read mode The marginal read 1 bit is cleared if the CPU starts execution from the flash memory If both MRG1 and MRGO are set MRG1 is active and MRGO is ignored 0 Marginal 1 read mode is disabled 1 Mar
112. from 1 to 0 individually but to reprogram from O to 1 requires an erase cycle The smallest amount of flash that can be erased is a segment There are three erase modes selected with the ERASE and MERAS bits listed in Table 7 1 Table 7 1 Erase Modes MERAS ERASE Erase Mode 0 1 Segment erase 1 0 Mass erase all main memory segments 1 1 LOCKA 0 Erase main and information flash memory LOCKA 1 Erase only main flash memory Any erase is initiated by a dummy write into the address range to be erased The dummy write starts the flash timing generator and the erase operation Figure 7 4 shows the erase cycle timing The BUSY bit is set immediately after the dummy write and remains set throughout the erase cycle BUSY MERAS and ERASE are automatically cleared when the cycle completes The erase cycle timing is not dependent on the amount of flash memory present on a device Erase cycle times are equivalent for all MSP430F2xx devices Figure 7 4 Erase Cycle Timing i TBB 4 ab gt lt gt Generate Erase Operation Active Remove Programming Voltage Programming Voltage Erase Time Vcc Current Consumption is Increased gt BUSY tmass erase 10593 fFTG tsegment erase 4819 fFTG A dummy write to an address not in the range to be erased does not start the erase cycle does not affect the flash memory and is not flagged in any way This errant dummy write is ignored Flash Memory Controller 7 7 Fl
113. if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 SBC 2 R12 Subtract LSDs Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B SBC B R13 0 R12 1 R12 Subtract LSDs Subtract carry from MSD Te Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 Cd 4 102 16 Bit MSP430X CPU SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB MSP430 Instructions Set carry bit SETC 1 gt C BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decimal subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h ADD 06666h R5 Move content R5 from 0 9 to 6 OFh R5 03987h 06666h O9FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h 16 Bit MSP430X CPU 4 103 MSP430 Instructions SETN Set negative bit Syntax SETN Operation 1 gt N Emulation BIS 4 SR Description The negative bit
114. if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 16 bit constant 7654h is subtracted from R5 with the carry from the previous instruction R5 19 16 0 SUBC W 7654h R5 Subtract 7654h C from R5 A 48 bit number 3 words pointed to by R5 20 bit address is subtracted from a 48 bit counter in RAM pointed to by R7 R5 points to the next 48 bit number afterwards The address R7 points to is in full memory range SUB R5 0 R7 Subtract LSBs R5 2 SUBC R5 2 R7 Subtract MIDs with C R5 2 SUBC R5 4 R7 Subtract MSBs with C R5 2 Byte CNT is subtracted from the byte R12 points to The carry of the previous instruction is used The address of CNT is in lower 64 K SUBC B amp CNT 0 R12 Subtract byte CNT from R12 16 Bit MSP430X CPU 4 107 MSP430 Instructions SWPB Swap bytes Syntax SWPB dst Operation dst 15 8 lt dst 7 0 Description The high and the low byte of the operand are exchanged PC 19 16 bits are cleared in register mode Status Bits Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected Example Exchange the bytes of RAM word EDE lower 64 K MOV 1234h amp EDE 1234h gt EDE SWPB amp EDE 3412h gt EDE Figure 4 42 Swa
115. if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is subtracted from R6 If a carry occurs the program continues at label TONI SUBA R5 R6 R6 R5 gt R6 JC TONI Carry occurred No carry 16 Bit MSP430X CPU 4 169 Chapter 5 Basic Clock Module The basic clock module provides the clocks for MSP430x2xx devices This chapter describes the operation of the basic clock module of the MSP430x2xx device family Topic Page 5 1 Basic Clock Module Introduction ooocoooccccc eee 5 2 5 2 Basic Clock Module Operation eee cece eee ee 5 4 5 3 Basic Clock Module Registers 0 ee eee eee eee 5 13 5 1 Basic Clock Module Introduction 5 1 Basic Clock Module Introduction 5 2 The basic clock module supports low system cost and ultralow power consumption Using three internal clock signals the user can select the best balance of performance and low power consumption The basic clock module can be configured to operate without any external components with one external resistor with one or two external crystals or with resonators under full software control The basic clock module incl
116. in Figure 20 2 The input multiplexer is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground Vss so that the stray capacitance is grounded to help eliminate crosstalk The ADC10 uses the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 20 2 Analog Multiplexer Ax Analog Port Selection R 1000hm INCHx o o ESD Protection The ADC10 external inputs Ax Verer and Vref share terminals with general purpose I O ports which are digital CMOS gates see device specific data sheet When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The ADC10AEx bits provide the ability to disable the port pin input and output buffers P2 3 on MSP430x22xx device configured for analog input BIS B 08h amp ADC10AEO P2 3 ADC10 function and enable ADC10 20 5 ADC10 Operation 20 2 3 Voltage Reference Generator The ADC10 module contains a built in voltage reference with two selectable voltage levels
117. is always read as zero TAIE Bit 1 Timer_A interrupt enable This bit enables the TAIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TAIFG Bit O Timer_A interrupt flag 0 No interrupt pending 1 Interrupt pending 12 20 Timer_A Timer_A Registers TAR Timer_A Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TARx Bits Timer_A register The TAR register is the count of Timer_A 15 0 TACCRx Timer_A Capture Compare Register x 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TACCRx Bits Timer_A capture compare register 15 0 Compare mode TACCRXx holds the data for the comparison to the timer value in the Timer_A Register TAR Capture mode The Timer_A Register TAR is copied into the TACCRx register when a capture is performed Timer_A 12 21 Timer_A Registers TACCTLx Capture Compare Control Register 15 14 13 rw 0 rw 0 rw 0 CMx Bit 15 14 CCISx Bit 13 12 scs Bit 11 SCCI Bit 10 Unused Bit 9 CAP Bit 8 OUTMODx Bits 7 5 12 22 Timer_A rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TACCRx input sig
118. is generated and the first data to be transmitted can be written into UCBxTXBUF As soon as the slave acknowledges the address the UCTXSTT bit is cleared The data written into UCBxTXBUF is transmitted if arbitration is not lost during transmission of the slave address UCBxTXIFG is set again as soon as the data is transferred from the buffer into the shift register If there is no data loaded to UCBxTXBUF before the acknowledge cycle the bus is held during the acknowledge cycle with SCL low until data is written into UCBxTXBUF Data is transmitted or the bus is held as long as the UCTXSTP bit or UCTXSTT bit is not set Setting UCTXSTP will generate a STOP condition after the next acknowledge from the slave If UCTXSTP is set during the transmission of the slave s address or while the USCI module waits for data to be written into UCBxTXBUF a STOP condition is generated even if no data was transmitted to the slave When transmitting a single byte of data the UCTXSTP bit must be set while the byte is being transmitted or anytime after transmission begins without writing new data into UCBxTXBUF Otherwise only the address will be transmitted When the data is transferred from the buffer to the shift register UCBxTXIFG will become set indicating data transmission has begun and the UCTXSTP bit may be set Setting UCTXSTT will generate a repeated START condition In this case UCTR may be set or cleared to configure transmitter or receiver and
119. negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS i Low byte of R7 is positive but not zero R7NEG sti Low byte of R7 is negative R7ZERO __ Low byte of R7 is zero 3 70 RISC 16 Bit CPU XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Exclusive OR of source with destination Exclusive OR of source with destination XOR src dst or XOR W src dst XOR B src dst src XOR dst gt dst The source and destination operands are exclusive ORed The result is placed into the destination The source operand is not affected N Set if result MSB is set reset if not set Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if both operands are negative OSCOFF CPUOFF and GIE are not affected The bits set in R6 toggle the bits in the RAM word TONI XOR R6 TONI Toggle bits of word TONI on the bits set in R6 The bits set in R6 toggle the bits in the RAM byte TONI XOR B R6 TONI Toggle bits of byte TONI on the bits set in low byte of R6 Reset to 0 those bits in low byte of R7 that are different from bits in RAM byte EDE XOR B EDE R7 Set different bit to 1s INV B R7 Invert Lowbyte Highbyte is Oh RISC 16 Bit CPU 3 71 I
120. of TAIV and the handling overhead The TAIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are 1 Capture compare block TACCRO 11 cycles Y Capture compare blocks TACCR1 TACCR2 16 cycles Li Timer overflow TAIFG 14 cycles Interrupt handler for TACCRO CCIFG Cycles CCIFG_0_HND r ses Start of handler Interrupt latency 6 RETI Interrupt handler for TAIFG TACCR1 and TACCR2 CCIFG TA_HND LER Interrupt latency 6 ADD amp TAIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG_1_HND Vector 2 TACCR1 2 JMP CCIFG_2_HND Vector 4 TACCR2 2 RETI Vector 6 Reserved 5 RETI Vector 8 Reserved 5 TAIFG_HND Vector 10 TAIFG Flag Pat Task starts here RETI 5 CCIFG 2 HND Vector 4 TACCR2 e Task starts here RETI Back to main program 5 CCIFG 1 HND Vector 2 TACCR1 st Task starts here RETI Back to main program 5 12 18 Timer_A 12 3 Timer_A Registers The Timer_A registers are listed in Table 12 3 Table 12 3 Timer_A Registers Register Timer_A control Timer_A counter Timer_A capture compare control O Timer_A capture compare O Timer_A capture compare control 1 Timer_A capture compare 1 Timer_A capture compar
121. of UCxCLK is transmitted on UCxSOMI Data on UCxSIMO is shifted into the receive shift register on the opposite edge of UCxCLK and moved to UCxRXBUF when the set number of bits are received When data is moved from the RX shift register to UCxRXBUF the UCxRXIFG interrupt flag is set indicating that data has been received The overrun error bit UCOE is set when the previously received data is not read from UCxRXBUF before new data is moved to UCxRXBUF Four Pin SPI Slave Mode In 4 pin slave mode UCXSTE is used by the slave to enable the transmit and receive operations and is provided by the SPI master When UCXSTE is in the slave active state the slave operates normally When UCxSTE is in the slave inactive state _j Any receive operation in progress on UCxSIMO is halted J UCxSOM1 is set to the input direction Y The shift operation is halted until the UCxSTE line transitions into the slave transmit active state The UCxSTE input signal is not used in 3 pin slave mode Universal Serial Communication Interface SPI Mode 16 9 USCI Operation SPI Mode 16 3 5 SPI Enable Transmit Enable Receive Enable When the USCI module is enabled by clearing the UCSWRST bit it is ready to receive and transmit In master mode the bit clock generator is ready but is not clocked nor producing any clocks In slave mode the bit clock generator is disabled and the clock is provided by the master A transmit or receive operation is indicat
122. operation OSCOFF CPUOFF and GIE are not affected except SR is included in the op eration Restore the 20 bit registers R9 R10 R11 R12 R13 from the stack POPM A 5 R13 Restore R9 R10 R11 R12 R13 Restore the 16 bit registers R9 R10 R11 R12 R13 from the stack POPM W 5 R13 Restore R9 R10 R11 R12 R13 16 Bit MSP430X CPU 4 131 Extended Instructions PUSHM A PUSHM W Syntax Operation Description Status Bits Mode Bits Example Example Save n CPU registers 20 bit data on the stack Save n CPU registers 16 bit words on the stack PUSHM A n Rdst 1 lt n lt 16 PUSHM W n Rdst or PUSHM n Rdst 1 lt n lt 16 PUSHM A Save the 20 bit CPU register values on the stack The stack pointer SP is decremented by four for each register stored on the stack The MSBs are stored first higher address PUSHM W Save the 16 bit CPU register values on the stack The stack pointer is decremented by two for each register stored on the stack PUSHM A The n CPU registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n x 4 after the operation The data Rn 19 0 of the pushed CPU registers is not affected PUSHM W The n registers starting with Rdst backwards are stored on the stack The stack pointer is decremented by n x 2 after the operation The data Rn 19 0 of the pushed CPU registers is not affected Note This instruction does not use the extensio
123. otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 are used as a mask 0AA55h for the word addressed by TOM If the result is zero a branch is taken to label TONI MOV 0AA55h R5 Load mask into register R5 AND R5 TOM mask word addressed by TOM with R5 JZ TONI a Result is not zero or AND 0AA55h TOM JZ TONI The bits of mask 0A5h are logically ANDed with the low byte TOM If the result is zero a branch is taken to label TONI AND B 0A5h TOM mask Lowbyte TOM with OA5h JZ TONI re Result is not zero 3 24 RISC 16 Bit CPU BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Clear bits in destination Clear bits in destination BIC src dst or BIC W src dst BIC B src dst NOT src AND dst gt dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six MSBs of the RAM word LEO are cleared BIC HOFCOOh LEO Clear 6 MSBs in MEM LEO The five MSBs of the RAM byte LEO are cleared BIC B 0F8h LEO Clear 5 MSBs in Ram location LEO RISC 16 Bit CPU 3 25 Instruction Set BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Set bits in destination Set bits in
124. output Comparator_A reference select This bit selects which terminal the Vcarer is applied to When CAEX 0 0 Vcarer is applied to the terminal 1 Vcarer is applied to the terminal When CAEX 1 0 Vcarer S applied to the terminal 1 Vcarer is applied to the terminal Comparator_A reference These bits select the reference voltage Vcarer 00 Internal reference off An external reference can be applied 01 0 25 Vcc 10 0 50 Vcc 11 Diode reference is selected Comparator_A on This bit turns on the comparator When the comparator is off it consumes no current The reference circuitry is enabled or disabled independently 0 Off 1 On Comparator_A interrupt edge select 0 Rising edge 1 Falling edge Comparator_A interrupt enable 0 Disabled 1 Enabled The Comparator_A interrupt flag 0 No interrupt pending 1 Interrupt pending Comparator_A 19 11 Comparator_A Registers CACTL2 Comparator_A Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 CASHORT Bit 7 Input short This bit shorts the and input terminals 0 Inputs not shorted 1 Inputs shorted P2CA4 Bit 6 Input select This bit together with P2CAO selects the terminal input when CAEX 0 and the terminal input when CAEX 1 P2CA3 Bits Input select These bits select the terminal input when CAEX 0 and the P2CA2 5 3 terminal input when CAEX 1 P2CA1 000 No connection 001 CA1
125. re enable watchdog Byte word write from RAM 514 kHz lt SMCLK lt 952 kHz Assumes OFF1Eh is already erased Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD amp WDTCTL Disable WDT L1 BIT BUSY amp FCTL3 Test BUSY JNZ L1 Loop while busy MOV FWKEY FSSEL1 FN0 amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY WRT FCTL1 Enable write MOV 0123h amp 0FF1Eh 0123h gt OFF1Eh L2 BIT BUSY amp FCTL3 Test BUSY JNZ L2 Loop while busy MOV FWKEY amp FCTL1 Clear WRT MOV FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT 7 12 Flash Memory Controller Block Write Flash Memory Operation The block write can be used to accelerate the flash write process when many sequential bytes or words need to be programmed The flash programming voltage remains on for the duration of writing the 64 byte block The cumulative programming time tcpy must not be exceeded for any block during a block write A block write cannot be initiated from within flash memory The block write must be initiated from RAM only The BUSY bit remains set throughout the duration of the block write The WAIT bit must be checked between writing each byte or word in the block When WAIT is set the next byte or word of the block can be written When writing successive blocks the BLKWRT bit must be cleared after the current block is complete BLKWRT can be set initiating the next block write after the required flash rec
126. right arithmetically by one bit position as shown in Figure 4 49 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All addressing modes with the exception of the Immediate Mode are possible in the full memory N Set if result is negative A dst 19 1 reset if dst 19 0 W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset OSCOFF CPUOFF and GIE are not affected 16 Bit MSP430X CPU 4 139 Extended Instructions Example The signed 20 bit number in R5 is shifted arithmetically right four positions RPT 4 RRAX A R5 R5 16 gt R5 Example The signed 8 bit value in EDE is multiplied by 0 5 RRAX B amp EDE EDE 2 gt EDE Figure 4 48 Rotate Right Arithmetically RRAX B A Register Mode 7 0 19 8 19 16 15 0 19 0 Figure 4 49 Rotate Right Arithmetically RRAX B A Non Register Mode 0 al 15 0 1 Sr 31 20 19 0 A 4 140 16 Bit MSP430X CPU RRCM A RRCM W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Rotate Right through carry the 20 bit CPU register content Rotate Right through carry the 16 bit CPU register content RRCM A n Rdst 1 lt n lt 4 RRCM W_ n Rdst or RRCM n Rdst 1 lt n lt 4 C gt MSB gt M
127. rw 0 MPY 130h a MPYS 132h MAC 134h MACS 136h Accessible Register MPY 0000 MACS MPYS MAC 32 bit Multiplexer RESHI 13Ch RESLO 13Ah 31 rw rw 0 SUMEXT 13Eh 15 r 0 11 2 Hardware Multiplier Hardware Multiplier Operation 11 2 Hardware Multiplier Operation The hardware multiplier supports unsigned multiply signed multiply unsigned multiply accumulate and signed multiply accumulate operations The type of operation is selected by the address the first operand is written to The hardware multiplier has two 16 bit operand registers OP1 and OP2 and three result registers RESLO RESHI and SUMEXT RESLO stores the low word of the result RESHI stores the high word of the result and SUMEXT stores information about the result The result is ready in three MCLK cycles and can be read with the next instruction after writing to OP2 except when using an indirect addressing mode to access the result When using indirect addressing for the result a NOP is required before the result is ready 11 2 1 Operand Registers The operand one register OP1 has four addresses shown in Table 11 1 used to select the multiply mode Writing the first operand to the desired address selects the type of multiply operation but does not start any operation Writing the second operand to the operand two register OP2 initiates the multiply operation Writing OP2 starts the selected operation with the values stored in OP
128. settle The user must assure the DAC12 settling time is not violated when using the DMA controller See the device specific data sheet for parameters E ooo DAC12 Operation 23 2 7 DAC12 Interrupts The DAC12 interrupt vector is shared with the DMA controller on some devices see device specific data sheet for interrupt assignment In this case software must check the DAC12IFG and DMAIFG flags to determine the source of the interrupt The DAC12IFG bit is set when DAC12LSELx gt 0 and DAC12 data is latched from the DAC12_xDAT register into the data latch When DAC12LSELx 0 the DAC12IFG flag is not set A set DAC12IFG bit indicates that the DAC12 is ready for new data If both the DAC12IE and GIE bits are set the DAC12IFG generates an interrupt request The DAC12IFG flag is not reset automatically It must be reset by software DAC12 23 9 DAC12 Registers 23 3 DAC12 Registers The DAC12 registers are listed in Table 23 2 Table 23 2 DAC12 Registers Register Short Form Register Type Address Initial State DAC12_0 control DAC12_0CTL Read write 01COh Reset with POR DAC12_0 data DAC12_ODAT Read write 01C8h Reset with POR DAC12_1 control DAC12_1CTL Read write 01C2h Reset with POR DAC12_1 data DAC12_1DAT Read write 01CAh Reset with POR 23 10 DAC12 DAC12 Registers DAC12_xCTL DAC12 Control Register 15 14 13 12 11 10 9 8 DAC120PS DAC12SREFx DAC12RES DAC12LSELx CANON DAC12IR rw 0 7 rw 0 6 rw
129. src dst BISX src dst or BISX W src dst BISX B src dst src or dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Bits 16 and 15 of R5 20 bit data are set to one BISX A 018000h R5 Set R5 16 15 bits A table word pointed to by R5 20 bit address is used to set bits in R7 BISX W R5 R7 Set bits in R7 A table byte pointed to by R5 20 bit address is used to set bits in output Port1 BISX B R5 amp P10UT Set I O port P1 bits 16 Bit MSP430X CPU BITX A BITX W BITX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Test bits set in source address word in destination address word Test bits set in source word in destination word Test bits set in source byte in destination byte BITX A src dst BITX src dst or BITX W src dst BITX B src dst src and dst The source operand and the destination operand are logically ANDed The result affects only the status bits Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset ot
130. system stack pointer SP is always decremented by two independent of the byte suffix a a RISC 16 Bit CPU 3 55 Instruction Set RET Return from subroutine Syntax RET Operation SP PC SP 2 gt SP Emulation MOV SP PC Description The return address pushed onto the stack by a CALL instruction is moved to the program counter The program continues at the code address following the subroutine call Status Bits Status bits are not affected 3 56 RISC 16 Bit CPU RETI Syntax Operation Description Status Bits Mode Bits Example Instruction Set Return from interrupt RETI TOS gt SR SP 2 SP TOS gt PC SP 2 gt SP The status register is restored to the value at the beginning of the interrupt service routine by replacing the present SR contents with the TOS contents The stack pointer SP is incremented by two The program counter is restored to the value at the beginning of interrupt service This is the consecutive step after the interrupted program flow Restoration is performed by replacing the present PC contents with the TOS memory contents The stack pointer SP is incremented N restored from system stack Z restored from system stack C restored from system stack V restored from system stack OSCOFF CPUOFF and GIE are restored from system stack Figure 3 13 illustrates the main program interrupt Figure 3 13 Main Program Interrupt
131. than the others Actions taken by the USCI module are shown in grey rectangles with an arrow indicating where in the the data stream the action occurs Actions that must be handled with software are indicated with white rectangles with an arrow pointing to where in the data stream the action must take place Figure 17 8 12C Time line Legend eee O peacscococo Other Master Oe eee occ eee peeccen Other Slave USCI Master USCI Slave Bits set or reset by software Bits set or reset by hardware Universal Serial Communication Interface C Mode 17 9 USCI Operation C Mode Slave Mode 12C Slave Transmitte The USCI module is configured as an 12C slave by selecting the I2C mode with UCMODEx 11 and UCSYNC 1 and clearing the UCMST bit Initially the USCI module must to be configured in receiver mode by clearing the UCTR bit to receive the 12C address Afterwards transmit and receive operations are controlled automatically depending on the R W bit received together with the slave address The USCI slave address is programmed with the UCBxl2COA register When UCA10 0 7 bit addressing is selected When UCA10 1 10 bit addressing is selected The UCGCEN bit selects if the slave responds to a general call When a START condition is detected on the bus the USCI module will receive the transmitted address and compare it against its own address stored in UCBxI2COA The UCSTTIFG flag is set
132. the operation of the asynchronous UART mode Topic Page 15 1 USCIOVErVIe Wo 15 2 15 2 USCI Introduction UART Mode ooooooooccnnnccncoo 15 3 15 3 USCI Operation UART Mode ooocoococcccccn 15 5 15 4 USCI Registers UART Mode ooooooocccccccccccnn 15 27 15 1 USCI Overview 15 1 USCI Overview The universal serial communication interface USCI modules support multiple serial communication modes Different USCI modules support different modes Each different USCI module is named with a different letter For example USCI_A is different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_AO and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support Y UART mode _j Pulse shaping for IrDA communications Automatic baud rate detection for LIN communications Lj SPI mode The USCI_Bx modules support g 12C mode Y SPI mode 15 2 Universal Serial Communication Interface UART Mode USCI Introduction UART Mode 15 2 USCI Introduction UART Mode In asynchronous mode the USCI_Ax modules connect the MSP430 to an external system via two external pins UCAXRXD and UCAxTXD UART mode is selected when the UCSYNC bit is cleared UART mode features include
133. the SVS The VLDx bits are used to enable disable the SVS and select one of 14 threshold levels V svg_1t for comparison with AVcc The SVS is off when VLDx 0 and on when VLDx gt 0 The SVSON bit does not turn on the SVS Instead it reflects the on off state of the SVS and can be used to determine when the SVS is on When VLDx 1111 the external SVSIN channel is selected The voltage on SVSIN is compared to an internal level of approximately 1 25 V 9 2 2 SVS Comparator Operation A low voltage condition exists when AVcc drops below the selected threshold or when the external voltage drops below its 1 25 V threshold Any low voltage condition sets the SVSFG bit The PORON bit enables or disables the device reset function of the SVS If PORON 1 a POR is generated when SVSFG is set If PORON 0 a low voltage condition sets SVSFG but does not generate a POR The SVSFG bit is latched This allows user software to determine if a low voltage condition occurred previously The SVSFG bit must be reset by user software If the low voltage condition is still present when SVSFG is reset it will be immediately set again by the SVS 9 4 Supply Voltage Supervisor SVS Operation 9 2 3 Changing the VLDx Bits When the VLDx bits are changed from zero to any non zero value there is a automatic settling delay ta svson implemented that allows the SVS circuitry to settle The tysvgon delay is approximately 50 us During this delay the S
134. the band gap voltage source remains enabled When REFOUT 1 the REFBURST bit controls the operation of the internal reference buffer When REFBURST 0 the buffer will be on continuously allowing the reference voltage to be present outside the device continuously When REFBURST 1 the buffer is automatically disabled when the ADC10 is not actively converting and automatically re enabled when needed The internal reference buffer also has selectable speed vs power settings When the maximum conversion rate is below 50 ksps setting ADC10SR 1 reduces the current consumption of the buffer approximately 50 20 2 4 Auto Power Down 20 6 ADC10 The ADC10 is designed for low power applications When the ADC10 is not actively converting the core is automatically disabled and automatically re enabled when needed The ADC10OSC is also automatically enabled when needed and disabled when not needed When the core or oscillator is disabled it consumes no current ADC10 Operation 20 2 5 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following Y The ADC10SC bit J The Timer_A Output Unit 1 Y The Timer_A Output Unit O J The Timer_A Output Unit 2 The polarity of the SHI signal source can be inverted with the ISSH bit The SHTx bits select the sample period tgampie to be 4 8 16 or 64 ADC
135. the cycle count by one for MOV BIT and CMP instructions Reduce the cycle count by two for MOV BIT and CMP instructions 1 Reduce the cycle count by one for MOV ADD and SUB instructions 16 Bit MSP430X CPU 4 55 MSP430X Extended Instructions MSP430X Address Instruction Cycles and Lengths Table 4 19 Address Instruction Cycles and Length 4 56 Table 4 19 lists the length and the CPU cycles for all addressing modes of the MSP430X address instructions Execution Length of Time MCLK Instruction Addressing Mode Words CMPA CMPA MOVA ADDA ADDA Source Destination BRA SUBA MOVA SUBA Example Rn Rn 1 1 1 1 CMPA R5 R8 PC 2 2 1 1 SUBA R9 PC x Rm 4 a 2 a MOVA R5 4 R6 EDE 4 2 MOVA R8 EDE SEDE 4 2 MOVA R5 amp EDE Rn Rm 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC Rn Rm 3 1 MOVA R5 R8 PC 3 1 MOVA R9 PC N Rm 2 3 2 2 CMPA 20 R8 PC 3 3 2 2 SUBA FE000h PC x Rn Rm 4 2 MOVA 2 R5 R8 PC 4 2 2 MOVA 2 R6 PC EDE Rm 4 2 MOVA EDE R8 PC 4 2 MOVA EDE PC SEDE Rm 4 2 MOVA amp EDE R8 PC 4 2 MOVA 8 EDE PC 16 Bit MSP430X CPU Instruction Set Description 4 6 Instruction Set Description The instruction map of the MSP430X shows all available instructions 000 040 080 OCO 100 140 180 1CO 200 240 280 2C0 300 340 380 3C0 Rec Rrc siswes RRA RRAB SxT rusmfrusHa CALL Reti cara Extension Word For Format and Format II Instructions JNE JNZ JEQ JZ ING O A O
136. the state of the associated PxSELx and PxDIRx bits The DAC12OPS bit selects between the P6 pins and the VeREF pins for the DAC outputs For example when DAC120PS 0 DAC12_0 outputs on P6 6 and DAC12_1 outputs on P6 7 When DAC120PS 1 DAC12_0 outputs on VeREF and DAC12_1 outputs on P6 5 See the port pin schematic in the device specific data sheet for more details DAC12 Operation 23 2 2 DAC12 Reference The reference for the DAC12 is configured to use either an external reference voltage or the internal 1 5 V 2 5 V reference from the ADC12 module with the DAC12SREFx bits When DAC12SREFx 0 1 the Vrer signal is used as the reference and when DAC12SREFx 2 3 the Verner signal is used as the reference To use the ADC12 internal reference it must be enabled and configured via the applicable ADC12 control bits DAC12 Reference Input and Voltage Output Buffers The reference input and voltage output buffers of the DAC12 can be configured for optimized settling time vs power consumption Eight combinations are selected using the DAC12AMPx bits In the low low setting the settling time is the slowest and the current consumption of both buffers is the lowest The medium and high settings have faster settling times but the current consumption increases See the device specific data sheet for parameters 23 2 3 Updating the DAC12 Voltage Output The DAC12_xDAT register can be connected directly to the DAC12 core or double buf
137. the transfer If UCBOTXIE is set UCBOTXIFG will not trigger a transfer DMA Controller 6 17 DMA Operation 6 2 10 Using ADC12 with the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data from any ADC12MEMx register to another location DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput of the ADC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur DMA transfers can be triggered from any ADC12IFGx flag When CONSEQx 0 2 the ADC12IFGx flag for the ADC12MEMx used for the conversion can trigger a DMA transfer When CONSEQx 1 3 the ADC12IFGx flag for the last ADC12MEMx in the sequence can trigger a DMA transfer Any ADC12IFGx flag is automatically cleared when the DMA controller accesses the corresponding ADC12MEMx 6 2 11 Using DAC12 With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the DAC12_xDAT register DMA transfers are done without CPU intervention and independently of any low power modes The DMA controller increases throughput to the DAC12 module and enhances low power applications allowing the CPU to remain off while data transfers occur Applications requiring periodic waveform generation can benefit from using the DMA controller with the DAC12 For example an application that produces a sinusoid
138. to LOCKA has no effect This allows existing flash programming routines to be used unchanged Unlock SegmentA BIT JZ MOV LOCKA amp FCTL3 SEGA UNLOCKED HEWKEY LOCKA amp FCTL3 SEGA UNLOCKED SegmentA is unlocked Lock SegmentA BIT JNZ MOV LOCKA amp FCTL3 SEGALOCKED FWKEY LOCKA amp FCTL3 SEGA LOCKED SegmentA is locked 7 4 Flash Memory Controller Test LOCKA Already unlocked No unlock SegmentA Yes continue Test LOCKA Already locked No lock SegmentA Yes continue Flash Memory Operation 7 3 Flash Memory Operation The default mode of the flash memory is read mode In read mode the flash memory is not being erased or written the flash timing generator and voltage generator are off and the memory operates identically to ROM MSP430 flash memory is in system programmable ISP without the need for additional external voltage The CPU can program its own flash memory The flash memory write erase modes are selected with the BLKWRT WRT MERAS and ERASE bits and are Y Byte word write Block write Segment Erase Mass Erase all main memory segments UO oO vo O All Erase all segments Reading or writing to flash memory while it is being programmed or erased is prohibited If CPU execution is required during the write or erase the code to be executed must be in RAM Any flash update can be initiated from within flash memory or RAM 7 3 1 Flash Memory T
139. to ADC1OMEM Figure 20 5 shows the flow of the single channel single conversion mode When ADC10SC triggers a conversion successive conversions can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 20 5 Single Channel Single Conversion Mode X input channel Ax t Conversion result is unpredictable 20 10 ADC10 CONSEQx 00 ADC100N 1 Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait for Trigger SAMPCON 4 eee 4 8 16 64 x ADC10CLK Sample Input Channel 12 x ADC10CLK 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set ADC10 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC1OMEM The sequence stops after conversion of channel AO Figure 20 6 shows the sequence of channels mode When ADC10SC triggers a sequence successive sequences can be triggered by the ADC10SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 20 6 Sequence of Channels Mode CONSEQx 01 If x gt 0 then x x 1 A MSC 1 and x 0 X input channel Ax and ENC 1 or_ 4 and ADC10SC 4 Wait for Trigger ADC100N 1 x IN
140. to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC B 1 R8 Add carry to MSDs RISC 16 Bit CPU 3 35 Instruction Set DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Source and carry added decimally to destination Source and carry added decimally to destination DADD src dst or DADD W src dst DADD B src dst src dst C gt dst decimally The source operand and the destination operand are treated as four binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers N Set if the MSB is 1 reset otherwise Z Set if result is zero reset otherwise C Set if the result is greater than 9999 Set if the result is greater than 99 V Undefined OSCOFF CPUOFF and GIE are not affected The eight digit BCD number contained in R5 and R6 is added decimally to an eight digit BCD number contained in R3 and R4 R6 and R4 contain the MSDs CLRC clear carry DADD R5 R3 add LSDs DADD R6 R4 add MSDs with carry JC OVERFLOW If carry occurs go to error handling routine The two digit decimal counter
141. to allow a timer to continue generating a PWM signal The clock control is flexible and supports both modules that need a running clock and modules that must be stopped when the CPU is stopped due to a breakpoint Embedded Emulation Module EEM 25 5 EEM Configurations 25 3 EEM Configurations Table 25 1 gives an overview of the EEM configurations in the MSP430 2xx family The implemented configuration is device dependent please refer to the device data sheet Table 25 1 2xx EEM Configurations 1 Low byte 2 High byte 1 4 No No 1 Low byte 2 High byte All 16 or 20 bits 2 8 Yes Yes In general the following features can be found on any 2xx device O Atleast two MAB MDB triggers supporting Mm Distinction between CPU DMA read and write accesses E 4 gt or lt comparison in XS only Y Atleast two trigger Combination registers Y Hardware breakpoints using the CPU Stop reaction Y Clock control with individual control of module clocks in some XS configurations the control of module clocks is hardwired Feature XS Memory Bus Triggers 2 4 only Memory Bus Trigger Mask for 1 Low byte 2 High byte CPU Register Write Triggers 0 Combination Triggers 2 Sequencer No State Storage No 25 6 Embedded Emulation Module EEM IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements
142. to destination BRA dst dst PC MOVA dst PC An unconditional branch is taken to a 20 bit address anywhere in the full address space All seven source addressing modes can be used The branch instruction is an address word instruction If the destination address is contained in a memory location X it is contained in two ascending words X LSBs and X 2 MSBs Not affected Not affected Not affected Not affected OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Branch to label EDE located anywhere in the 20 bit address space or branch directly to address BRA EDE MOVA imm20 PC BRA 01AA04h Symbolic Mode Branch to the 20 bit address contained in addresses EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing BRA EXEC MOVA z16 PC PC Note if the 16 bit index is not sufficient a 20 bit index may be used with the following instruction MOVX A EXEC PC 1M byte range with 20 bit index Absolute Mode Branch to the 20 bit address contained in absolute addresses EXEC LSBs and EXEC 2 MSBs Indirect addressing BRA amp EXEC MOVA amp abs20 PC Register Mode Branch to the 20 bit address contained in register R5 Indirect R5 BRA R5 MOVA R5 PC 16 Bit MSP430X CPU 4 157 Address Instructions Indirect Mode Branch to the 20 bit address contained in the word pointed to by register R5
143. to the output mode 13 12 Timer_B Timer_B Operation Compare Latch TBCLx The TBCCRx compare latch TBCLx holds the data for the comparison to the timer value in compare mode TBCLx is buffered by TBCCRx The buffered compare latch gives the user control over when a compare period updates The user cannot directly access TBCLx Compare data is written to each TBCCRx and automatically transferred to TBCLx The timing of the transfer from TBCCRx to TBCLx is user selectable with the CLLDx bits as described in Table 13 2 Table 13 2 TBCLx Load Events CLLDx Description 00 New data is transferred from TBCCRx to TBCLx immediately when TBCCRx is written to 01 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 10 New data is transferred from TBCCRx to TBCLx when TBR counts to 0 for up and continuous modes New data is transferred to from TBCCRx to TBCLx when TBR counts to the old TBCLO value or to 0 for up down mode 11 New data is transferred from TBCCRx to TBCLx when TBR counts to the old TBCLx value Grouping Compare Latches Multiple compare latches may be grouped together for simultaneous updates with the TBCLGRPx bits When using groups the CLLDx bits of the lowest numbered TBCCRx in the group determine the load event for each compare latch of the group except when TBCLGRP 3 as shown in Table 13 3 The CLLDx bits of the controlling TBCCRx must not be set to zero When the CLLDx bits of the controlling TBCCRx
144. transfer 011 Burst block transfer 100 Repeated single transfer 101 Repeated block transfer 110 Repeated burst block transfer 111 Repeated burst block transfer DMA destination increment This bit selects automatic incrementing or decrementing of the destination address after each byte or word transfer When DMADSTBYTE 1 the destination address increments decrements by one When DMADSTBYTE 0 the destination address increments decrements by two The DMAxDA is copied into a temporary register and the temporary register is incremented or decremented DMAxDA is not incremented or decremented 00 Destination address is unchanged 01 Destination address is unchanged 10 Destination address is decremented 11 Destination address is incremented DMA source increment This bit selects automatic incrementing or decrementing of the source address for each byte or word transfer When DMASRCBYTE 1 the source address increments decrements by one When DMASRCBYTE 0 the source address increments decrements by two The DMAXSA is copied into a temporary register and the temporary register is incremented or decremented DMAXSA is not incremented or decremented 00 Source address is unchanged 01 Source address is unchanged 10 Source address is decremented 11 Source address is incremented DMA destination byte This bit selects the destination as a byte or word 0 Word 1 Byte DMA Controller DMA SRCBYTE DMA LEVEL DMAEN DMAIFG DMAI
145. transmit control register UCAOIRTCTL Read write O5Eh Reset with PUC USCI_AO IrDA receive control register UCAOIRRCTL Read write O5Fh Reset with PUC SFR interrupt enable register 2 1E2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h 00Ah with PUC SS SS SS auqwcw wa_ aaaa anmaa_ M an 6 AAA AAA Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B or CLR B instructions SESSE EAER Table 15 7 USCI_A1 Control and Status Registers Register Short Form Register Type Address Initial State USCI_A1 control register O UCA1CTLO Read write ODOh Reset with PUC USCI_A1 control register 1 UCA1CTL1 Read write 0Dih 001h with PUC USCI_A1 baud rate control register O UCA1BRO Read write 0D2h Reset with PUC USCI_A1 baud rate control register 1 UCA1BR1 Read write OD3h Reset with PUC USCI_A1 modulation control register UCA1OMCTL Read write 0D4h Reset with PUC USCI_A1 status register UCA1STAT Read write OD5h Reset with PUC USCI_A1 receive buffer register UCA1RXBUF Read OD6h Reset with PUC USCI_A1 transmit buffer register UCA1TXBUF Read write 0D7h Reset with PUC USCI_A1 auto baud control register UCA1ABCTL Read write OCDh Reset with PUC USCI_A1 IrDA transmit control register UCA1IRTCTL Read write OCEh Reset with PUC USCI_A1 IrDA receive control register UCA1IRRCTL Read wri
146. two or three memory words _j To adjust software timing ae Note Emulating No Operation Instruction Other instructions can emulate the NOP function while providing different numbers of instruction cycles and code words Some examples are Examples MOV 0 R3 1 cycle 1 word MOV 0 R4 0 R4 6 cycles 3 words MOV R4 0 R4 5 cycles 2 words BIC 0 EDE R4 4 cycles 2 words JMP 2 2 cycles 1 word BIC 0 R5 1 cycle 1 word However care should be taken when using these examples to prevent unintended results For example if MOV 0 R4 0 R4 is used and the value in R4 is 120h then a security violation will occur with the watchdog timer address 120h because the security key was not used RISC 16 Bit CPU 3 53 Instruction Set POP W POP B Syntax Operation Emulation Emulation Description Status Bits Example Example Example Example Pop word from stack to destination Pop byte from stack to destination POP dst POP B dst SP gt temp SP 2 gt SP temp gt dst MOV SP dst or MOV W SP dst MOV B SP dst The stack location pointed to by the stack pointer TOS is moved to the destination The stack pointer is incremented by two afterwards Status bits are not affected The contents of R7 and the status register are restored from the stack POP R7 POP SR Restore R7 Restore status register The contents of RAM byte LEO is restored from the stack
147. with each rising SCL edge because the logic observes the external SCL and compares it to the internally generated SCL 17 3 6 Using the USCI Module in I2C Mode with Low Power Modes The USCI module provides automatic clock activation for SMCLK for use with low power modes When SMCLK is the USCI clock source and is inactive because the device is in a low power mode the USCI module automatically activates it when needed regardless of the control bit settings for the clock source The clock remains active until the USCI module returns to its idle condition After the USCI module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic clock activation is not provided for ACLK When the USCI module activates an inactive clock source the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected For example a timer using SMCLK will increment while the USCI module forces SMCLK active In 12C slave mode no internal clock source is required because the clock is provided by the external master It is possible to operate the USCI in 12C slave mode while the device is in LPM4 and all internal clock sources are disabled The receive or transmit interrupts can wake up the CPU from any low power mode 17 22 Universal Serial Communication Interface 12C Mode USCI Operation C Mode 17 3 7 USCI Interrupts in I2C Mode Their are tw
148. write mode A flash word low high byte must not be written more than twice between erasures Otherwise damage can occur The BUSY bit is set while a write operation is active and cleared when the operation completes If the write operation is initiated from RAM the CPU must not access flash while BUSY 1 Otherwise an access violation occurs ACCVIFG is set and the flash write is unpredictable A byte word write operation can be initiated from within flash memory or from RAM When initiating from within flash memory all timing is controlled by the flash controller and the CPU is held while the write completes After the write completes the CPU resumes code execution with the instruction following the write The byte word write timing is shown in Figure 7 7 Figure 7 7 Byte Word Write Timing Ly Z 4A Ds A 4 Pr Programming Operation Active de gt i Generate Remove Programming Voltage Programming Voltage Programming Time Vcc Current Consumption is Increased lt gt BUSY El tword Write 30 fFTG L When a byte word write is executed from RAM the CPU continues to execute code from RAM The BUSY bit must be zero before the CPU accesses flash again otherwise an access violation occurs ACCVIFG is set and the write result is unpredictable 7 10 Flash Memory Controller Flash Memory Operation In byte word mode the internally generated programming voltage is applied to the complete 64 byte block each time
149. 0 xiii Contents 2A OD O A A aN Seat Ne ah al 24 1 24 1 SD16_Alntroduction innere aaaea ie nets 24 2 24 2 SD16_A Operation 0 0 nett e ees 24 4 24 21 ADC Core sien ido Ser een 24 4 24 2 2 Analog Input Range and PGA oocccccccccccc eee 24 4 24 2 3 Voltage Reference Generator 02 0 cece eee eee 24 4 24 2 4 Auto Power DOWN 0 c cece cent etn 24 4 24 2 5 Analog Input Pair Selection 0 06 e cece eee eee 24 5 24 2 6 Analog Input Characteristics 00 00 cece eee 24 6 24 27 DRAPIRO dcir eee beep PR AA nee eee 24 7 24 2 8 Conversion Memory Register SD16GMEMO 2 000ee 24 11 24 2 9 Conversion Modes 00 cece eee eens 24 12 24 2 10 Using the Integrated Temperature Sensor 00000e eee eeee 24 14 24 211 Interrupt HANGING 055050300 deed be er OREA ees 24 15 24 3 SD16_A Registers o ooccccocccccocnccncc a ra a a E a a 24 16 25 Embedded Emulation Module EEM ooococcococccocn eee eee eee 25 1 25 1 EEM Introductio eon pi A A awe ARAA 25 2 25 2 EEM Building Blocks t nenia UE ERA E nee aa 25 4 20AT MOJO ar EEA TRINE slag dail EEEE EEEE 25 4 25 2 2 Trigger Sequencer 0 0 cece eee eee 25 5 25 2 3 State Storage Internal Trace Buffer 0 anean eee ee eee 25 5 25 2 4 Clock Control daien aioe wie at ed es ee a a 25 5 25 3 EEM Configurations 00 0 cece teens 25 6 xiv Chapter 1 Intr
150. 0 TBRx Bits Timer_B register The TBR register is the count of Timer_B 15 0 13 22 Timer_B Timer_B Registers TBCCRx Timer_B Capture Compare Register x 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 TBCCRx Bits Timer_B capture compare register 15 0 Compare mode Compare data is written to each TBCCRx and automatically transferred to TBCLx TBCLx holds the data for the comparison to the timer value in the Timer_B Register TBR Capture mode The Timer_B Register TBR is copied into the TBCCRx register when a capture is performed Timer_B 13 23 Timer_B Registers TBCCTLx Capture Compare Control Register 15 14 rw 0 CMx Bit 15 14 CCISx Bit 13 12 scs Bit 11 CLLDx Bit 10 9 CAP Bit 8 OUTMODx Bits 7 5 13 24 Timer_B 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 5 4 3 2 1 0 rw 0 r rw 0 0 rw 0 rw 0 rw rw 0 Capture mode 00 No capture 01 Capture on rising edge 10 Capture on falling edge 11 Capture on both rising and falling edges Capture compare input select These bits select the TBCCRx input signal See the device specific data sheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vec Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Comp
151. 0 is calculated by the following equation al 15 CAL_ADC_GAIN_FACTOR GAIN x2 The conversion result is gain corrected by multiplying it with the CAL_ADC_GAIN_FACTOR and dividing the result by 215 ADC gain_corrected ADC raw x CAL_ADC_GAIN_FACTOR x TE If both gain and offset are corrected the gain correction is done first ADC gain_corrected ADC raw x CAL_ADC_GAIN_FACTOR x 216 ADC final ADC gain_corrected CAL_ADC_OFFSET Example Using Gain and Offset Calibration 22 6 TLV Structure In the following example an external reference voltage is used during a conversion Y Conversion result 0x0800 2048 Y Gain calibration factor Ox7FEO gain error 2 LSB Y Offset calibration OxFFFE 2th complement of 2 The following steps show an example of how the ADC12 conversion result is corrected by using the hardware multiplier Multiply the conversion result by 2 this step simplifies the final division _j Multiply the result by CAL_ADC_GAIN_FACTOR Y Divide the result by 216 use the upper word of the 32 bit multiplication result RESHI Y Add CAL_ADC_OFFSET to the result In the example 0x0800 x 0x0002 0x1000 0x1000 x 0x8010 0x0801_0000 0x0801_0000 0x0001_0000 0x0000_0801 2049 0x801 OxFFFE 0x07FF 2047 O O O L Checking Integrity of SegmentA The code example using the hardware multiplier follows The ADC conversion result is stored in ADC12MEMO I
152. 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 0 1 1 1 1 1 1 1 1 1 1 0 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 0 1 1 1 1 1 1 1 1 1 1 1 1 0 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Universal Serial Communication Interface UART Mode 15 17 USCI Operation UART Mode 15 3 10 Setting a Baud Rate For a given BRCLK clock source the baud rate used determines the required division factor N ye faencik Baudrate The division factor N is often a non integer value thus at least one divider and one modulator stage is used to meet the factor as closely as possible If N is equal or greater than 16 the oversampling baud rate generation mode can be chosen by setting UCOS16 Low Frequency Baud Rate Mode Setting In the low frequency mode the integer portion of the divisor is realized by the prescaler UCBRx INT N and the fractional portion is realized by the modulator with the following nominal formula UCBRSx round N INT N 8 Incrementing or decrementing the UCBRSx setting by one count may give a lower maximum bit error for any given bit To determine if this is the case a detailed error calculation must be performed for each bit for each UCBRSx setting Oversampling B
153. 0 Interrupt disabled 1 Interrupt enabled Arbitration lost 0 No arbitration lost condition 1 Arbitration lost STOP condition received USISTP is automatically cleared if USICNTx is loaded with a value gt 0 when USIIFGCC 0 0 No STOP condition received 1 STOP condition received START condition interrupt flag 0 No START condition received No interrupt pending 1 START condition received Interrupt pending USI counter interrupt flag Set when the USICNTx 0 Automatically cleared if USICNTx is loaded with a value gt 0 when USIIFGCC 0 0 No interrupt pending 1 Interrupt pending Universal Serial Interface 14 15 USI Registers USICKCTL USI Clock Control Register 7 6 5 4 3 2 1 0 USIDIVx USISSELx USICKPL USISWCLK rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 USIDIVx Bits Clock divider select 7 5 000 Divide by 1 001 Divide by 2 010 Divide by 4 011 Divide by 8 100 Divide by 16 101 Divide by 32 110 Divide by 64 111 Divide by 128 USISSELx Bits Clock source select Not used in slave mode 4 2 000 SCLK Not used in SPI mode 001 ACLK 010 SMCLK 011 SMCLK 100 USISWCLK bit 101 TACCRO 110 TACCR1 111 TACCR2 Reserved on MSP430F20xx devices USICKPL Bit 1 Clock polarity select 0 Inactive state is low 1 Inactive state is high USISWCLK Bit O Software clock 0 Input clock is low 1 Input clock is high 14 16 Universal Serial Interface USI Registers USICNT USI Bit Counter Register 4 3 2 1 0 7 rw 0 rw USI
154. 0 bit destination register TSTA Rdst dst OFFFFFh 1 dst OFFFFh 1 dst OFFh 1 CMPA 0 Rdst The destination register is compared with zero The status bits are set according to the result The destination register is not affected N Set if destination register is negative reset if positive Z Set if destination register contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected The 20 bit value in R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TSTA R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS i R7 is positive but not zero R7NEG tia R7 is negative R7ZERO _ R7 is zero 4 168 16 Bit MSP430X CPU SUBA Syntax Operation Description Status Bits Mode Bits Example Address Instructions Subtract 20 bit source from 20 bit destination register SUBA Rsrc Rdst SUBA imm20 Rdst not src 1 Rdst gt Rdst or Rdst src gt Rast The 20 bit source operand is subtracted from the 20 bit destination register This is made by adding the 1 s complement of the source 1 to the destination The result is written to the destination register the source is not affected Set if result is negative src gt dst reset if positive src lt dst Set if result is zero src dst reset otherwise src dst Set if there is a carry from the MSB Rdst 19 reset otherwise Set
155. 0 user software Read write flash memory Flash Memory Controller 7 19 Flash Memory Registers 7 4 Flash Memory Registers The flash memory registers are listed in Table 7 4 Table 7 4 Flash Memory Registers Register Short Form Register Type Address Initial State Flash memory control register 1 FCTL1 Read write 0x0128 0x9600 with PUC Flash memory control register 2 FCTL2 Read write 0x012A 0x9642 with PUC Flash memory control register 3 FCTL3 Read write 0x012C 0x9658 with PUCT Flash memory control register 4 FCTL4 Read write 0x01BE 0x0000 with PUC Interrupt Enable 1 1E1 Read write 0x0000 Reset with PUC Interrupt Flag 1 IFG1 Read write 0x0002 t KEYV is reset with POR Not present in all MSP430x2xx devices See device specific data sheet 7 20 Flash Memory Controller Flash Memory Registers FCTL1 Flash Memory Control Register 15 14 13 12 11 10 9 8 FRKEY Read as 096h FWKEY Must be written as OA5h 6 5 4 3 2 1 0 ro rw 0 rw 0 rw 0 rw 0 rO rw 0 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Block write mode WRT must also be set for block write mode BLKWRT is automatically reset when EMEX is set 0 Block write mode is off 1 Block write mode is on Write This bit is used to select any write mode WRT is automatically reset when EMEX is set 0 Write mode is off 1 Write mode is on Reserved Always read as 0 Enable Emergency Interrupt Exit Setting this bi
156. 000 000 38400 26 0 0 1 8 0 3 6 1 8 1 000 000 56000 17 7 0 4 8 0 8 8 0 3 2 1 000 000 115200 8 6 0 7 8 6 4 9 7 16 1 1 000 000 128000 7 7 0 10 4 6 4 18 0 11 6 1 000 000 256000 3 7 0 29 6 0 43 6 5 2 4 000 000 9600 416 6 0 0 2 0 2 0 2 0 4 4 000 000 19200 208 3 0 0 2 0 5 0 3 0 8 4 000 000 38400 104 1 0 0 5 0 6 0 9 1 2 4 000 000 56000 71 4 0 0 6 1 0 1 7 1 3 4 000 000 115200 34 6 0 2 1 0 6 2 5 3 1 4 000 000 128000 31 2 0 0 8 1 6 3 6 2 0 4 000 000 256000 15 5 0 4 0 3 2 8 4 5 2 8 000 000 9600 833 2 0 0 1 0 0 2 0 1 8 000 000 19200 416 6 0 0 2 0 2 0 2 0 4 8 000 000 38400 208 3 0 0 2 0 5 0 3 0 8 8 000 000 56000 142 7 0 0 6 0 1 0 7 0 8 8 000 000 115200 69 4 0 0 6 0 8 1 8 1 1 8 000 000 128000 62 4 0 0 8 0 1 2 1 2 8 000 000 256000 31 2 0 0 8 1 6 3 6 2 0 15 22 Universal Serial Communication Interface UART Mode USCI Operation UART Mode Table 15 4 Commonly Used Baud Rates Settings and Errors UCOS16 0 Continued 12 000 000 9600 1250 0 0 0 0 0 05 0 05 12 000 000 19200 625 0 0 0 0 0 2 0 12 000 000 38400 312 4 0 0 2 0 0 2 0 2 12 000 000 56000 214 2 0 0 3 0 2 0 4 0 5 12 000 000 115200 104 1 0 0 5 0 6 0 9 1 2 12 000 000 128000 93 6 0 0 8 0 1 5 0 4 12 000 000 256000 46 7 0 1 9 0 2 0 2 0 16 000 000 9600 1666 6 0 0 05 0 05 0 05 0 1 16 000 000 19200 833 2 0 0 1 0 05 0 2 0 1 16 000 000 38400 416 6 0 0 2 0 2 0 2 0 4 16 000 000 56000 285 6 0 0 3 0 1 0 5 0 2 16 000 000 115200 138 7 0 0 7 0 0 8 0 6
157. 010 CA2 011 CA3 100 CA4 101 CA5 110 CA6 111 CA7 P2CAO Bit 2 Input select This bit together with P2CA4 selects the terminal input when CAEX 0 and the terminal input when CAEX 1 00 No connection 01 CAO 10 CA1 11 CA2 CAF Bit 1 Comparator_A output filter 0 Comparator_A output is not filtered 1 Comparator_A output is filtered CAOUT Bit 0 Comparator_A output This bit reflects the value of the comparator output Writing this bit has no effect 19 12 Comparator_A Comparator_A Registers CAPD Comparator_A Port Disable Register rw CAPDx Bits 7 0 rw 7 6 5 4 3 2 1 0 0 rw 0 rw 0 rw 0 0 rw 0 rw 0 rw 0 Comparator_A port disable These bits individually disable the input buffer for the pins of the port associated with Comparator_A For example if CAO is on pin P2 3 the CAPDx bits can be used to individually enable or disable each P2 x pin buffer CAPDO disables P2 0 CAPD1 disables P2 1 etc 0 The input buffer is enabled 1 The input buffer is disabled Comparator_A 19 13 19 14 Comparator_A Chapter 20 ADC10 The ADC10 module is a high performance 10 bit analog to digital converter This chapter describes the operation of the ADC10 module of the 2xx family Topic Page 20T ADCIO Introduction e risa a a e 20 2 20 2 ADC10 Operation oen eoe aeee ee a E aaa aa e aae 20 4 PAN ADCTO Registers a a 20 24 20 1 ADC10 Introduction 20 1 ADC10 Introd
158. 0108Ch 01094h 0006h 01092h 05555h grogan 01080h 01084h __ 0002h_ 01082h 01234h o1os2h RISC 16 Bit CPU 3 11 Addressing Modes 3 3 3 Symbolic Mode The symbolic mode is described in Table 3 6 Table 3 6 Symbolic Mode Description 3 12 Assembler Code MOV EDE TONI Content of ROM MOV X PC Y PC X EDE PC Y TONI PC Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OFO16h 0F014h 01116h 01114h 01112h RISC 16 Bit CPU Two or three words Move the contents of the source address EDE contents of PC X to the destination address TONI contents of PC Y The words after the instruction contain the differences between the PC and the source or destination addresses The assembler computes and inserts offsets X and Y automatically With symbolic mode the program counter PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV EDE TONI Source address EDE Dest After Address Register Space 011FEh OFF16h 0F102h 0FF14h 04090h PC OFF12h OFF14h 0F102h 0A123h OF016h OFF16h 011FEh 1114h 05555h 0 OFO018h OFO016h 0F014h 01116h 01114h 01112h Address Space Oxxxxh PC OF016h address TONI 01114h Register 3 3 4 Absolute Mode Addressing Modes The absolute mode is described in Table 3 7 Table 3 7 Absolute Mod
159. 024 Additional filtering can be done in software The high impedance input buffer is not implemented in MSP430x20x3 devices Features of the SD16_A include a Lj Ee be OO Q a 16 bit sigma delta architecture Up to eight multiplexed differential analog inputs per channel The number of inputs is device dependent see the device specific data sheet Software selectable on chip reference voltage generation 1 2V Software selectable internal or external reference Built in temperature sensor Up to 1 1 MHz modulator input frequency High impedance input buffer not implemented on all devices see the device specific data sheet Selectable low power conversion mode The block diagram of the SD16_A module is shown in Figure 24 1 SD16_A Introduction Figure 24 1 SD16_A Block Diagram SD16REFON Reference SD16SSELx 1 2V VREF Acc SD16XDIVx SD16DIVx 1 MCLK AVss Divider Divider SMCLK Reference fM 1 3 16 48 1 2 4 8 ACLK TACLK SD16VMIDON y y E s tart Conversion SD16SC AO A1 001 SD160SRx A2 010 A3 on A4 100 ZA Modulator A5 101 D16UNI SD16DF AB 110 SD16XOSR ea A7 Reference SD16LP AVCC Temp Sensor SD16INCHx 101 5R R 5R t Not Implemented in MSP430x20x3 devices SD16_A 24 3 SD16_A Operation 24 2 SD16_A Operation 24 2 1 ADC Core The SD16_A module is configured with user software The setup and oper
160. 0778h e Toum 16 Bit MSP430X CPU CPU Registers MSP430X Instruction with Symbolic Mode When using an MSP430X instruction with Symbolic mode the operand can be located anywhere in the range of PC 19 bits Length Three or four words Operation The operand address is the sum of the 20 bit PC and the 20 bit index The four MSBs of the index are contained in the extension word the 16 LSBs are contained in the word following the instruction Comment Valid for source and destination The assembler calculates the register index and inserts it Example ADDX B EDE TONI The instruction adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Source Byte EDE located at address 3579Ch pointed to by PC 14766h is the 20 bit result of 3579Ch 21036h 14766h Address 21036h is the address of the index in this example Destination Byte TONI located at address 77778h pointed to by PC 56740h is the 20 bit result of 77778h 21038h 56740h Address 21038h is the address of the index in this example Before Address Space After Address Space 2103Ah 2103Ah 21038h 21038h 21036h 21036h 21034h 21034h 21032h 21032h 21038h src 7777Ah 56740h__ 7777Ah dst 77778h MITTEN 7778h Sum 21036h 3579Eh 14766h__ 3579Eh 3579Ch 3579Ch 3579Ch 16 Bit MSP430X CPU 4 27 CPU Registers 4 4 4 Absolute Mode The Absolute mode uses the contents of the wor
161. 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected 20 bit content of R5 is negated twos complement INVX A R5 Invert R5 INCX A R5 R5 is now negated Content of memory byte LEO is negated PC is pointing to upper memory INVX B LEO Invert LEO INCX B LEO MEM LEO is negated 16 Bit MSP430X CPU MOVX A MOVX W MOVX B Syntax Operation Description Status Bits Mode Bits Example Example Loop Example Loop Extended Instructions Move source address word to destination address word Move source word to destination word Move source byte to destination byte MOVX A src dst MOVX src dst or MOVX W src dst MOVX B src dst src gt dst The source operand is copied to the destination The source operand is not affected Both operands may be located in the full address space N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Move a 20 bit constant 18000h to absolute address word EDE MOVX A 018000h amp EDE Move 18000h to EDE The contents of table EDE wo
162. 1 gt dst dst not src C gt dst dst OFFFFh 1 src xor dst gt dst oo I Instruction Set N Z c x x x 0 0 S 0 Ls a A 1 3 z 1 es 4 RISC 16 Bit CPU 3 75 3 76 RISC 16 Bit CPU Chapter 4 16 Bit MSP430X CPU This chapter describes the extended MSP430X 16 bit RISC CPU with 1 MB memory access its addressing modes and instruction set The MSP430X CPU is implemented in all MSP430 devices that exceed 64 KB of address space Topic Page AAC PU Ntro dC edo e 4 2 4 Qe MEA AO oroap an apacboo a apor cognd ado dao rada but 4 4 43I CPUREJIStErS ae tal sel dilo lalo ains dies 4 5 ATA Addressing Modes ia coil ica 4 14 4 5 MSP430 and MSP430X Instructions oooocoooocoommmmmo 4 35 4 6 Instruction Set Description ooooccccccconcrr eee eee 4 57 4 1 CPU Introduction 4 1 CPU Introduction 4 2 The MSP430X CPU incorporates features specifically designed for modern programming techniques such as calculated branching table processing and the use of high level languages such as C The MSP430X CPU can address a 1 MB address range without paging In addition the MSP430X CPU has fewer interrupt overhead cycles and fewer instruction cycles in some cases than the MSP430 CPU while maintaining the same or better code density tha
163. 1 and OP2 The result is written into the three result registers RESLO RESHI and SUMEXT Repeated multiply operations may be performed without reloading OP1 if the OP1 value is used for successive operations It is not necessary to re write the OP1 value to perform the operations Table 11 1 OP1 addresses OP1 Address Register Name Operation 0130h MPY Unsigned multiply 0132h MPYS Signed multiply 0134h MAC Unsigned multiply accumulate 0136h MACS Signed multiply accumulate Hardware Multiplier 11 3 Hardware Multiplier Operation 11 2 2 Result Registers The result low register RESLO holds the lower 16 bits of the calculation result The result high register RESHI contents depend on the multiply operation and are listed in Table 11 2 Table 11 2 RESHI Contents Mode MPY MPYS MAC MACS RESHI Contents Upper 16 bits of the result The MSB is the sign of the result The remaining bits are the upper 15 bits of the result Two s complement notation is used for the result Upper 16 bits of the result Upper 16 bits of the result Two s complement notation is used for the result The sum extension registers SUMEXT contents depend on the multiply operation and are listed in Table 11 3 Table 11 3 SUMEXT Contents MACS Underflow and Overflow 11 4 Mode MPY MPYS MAC MACS SUMEXT SUMEXT is always 0000h SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was
164. 10 contains the address of the TAG DCO_30 tag CLR B amp DCOCTL Select lowest DCOx and MODx settings MOV B 7 R10 amp BCSCTL1 Set RSEL MOV B 6 R10 amp DCOCTL Set DCOx and MODx 22 2 2 TAG_ADC12_1 Calibration TLV Structure The calibration data for the ADC12 module consists of eight words Table 22 4 TAG_ADC12_1 Calibration Data Device Specific CAL_ADC_15VREF_FACTOR VREF2_5 0 Ta 30 C 2K CAL_ADC_OFFSET Verer 2 5V Ta 85 C 2K fapci2cLk 5 MHz CAL_ADC_GAIN_FACTOR Verer 2 5V Ta 85 C 2K fapc12cLk 5 MHz CAL_ADC_15T30 VREF2_5 0 Ta 30 C 2K 12 bit conversion result Temperature Sensor Calibration Data The temperature sensor is calibrated using the internal voltage references At VREF2_5 0 and 1 the conversion result at 30 C and 85 C is written at the respective SegmentA location see Table 22 4 22 4 TLV Structure Supported Tags Integrated Voltage Reference Calibration Data The reference voltages VREF2_5 O and 1 are measured at room temperature The measured value is normalized by 1 5 2 5V before stored into the flash information memory SegmentA Ve CAL_ADC_15VREF_FACTOR gt x 915 The conversion result is corrected by multiplying it with the CAL_ADC_15VREF_FACTOR or CAL_ADC_25VREF_FACTOR and dividing the result by 215 ADC corrected ADC raw x CAL_ADC_15VREF_FACTOR x 218 Example Using the Reference Calibration In the following example the integrated 1
165. 10MEM until the internal transfer counter becomes equal to zero At this point block one is full and both the ADC10IFG flag the ADC10B1 bit are set The user can test the ADC10B1 bit to determine that block one is full The DTC continues with block two The internal transfer counter is automatically reloaded with n At the next load of the ADC10MEM the DTC begins transferring conversion results to block two After n transfers have completed block two is full The ADC10IFG flag is set and the ADC10B1 bit is cleared User software can test the cleared ADC10B1 bit to determine that block two is full Figure 20 12 shows a state diagram of the two block mode ADC10 Operation Figure 20 12 State Diagram for Data Transfer Control in Two Block Transfer Mode gt ADC10B1 0 ADC10TB 1 Write to ADC10SA or n 0 Write to ADC10SA Write to ADC10SA n 0 ADC10DTC1 DTC reset Wait for write to ADC10SA Initialize Start Address in ADC10SA Write to ADC10SA nis latched in counter x Wait until ADC10MEM is written Write to ADC10MEM completed 1 x MCLK cycle Transfer data to Address AD AD AD 2 ADC10IFG 1 ADC10B1 1 or ADC10CT 1 and Toggle ADC10B1 eee A ADC10B1 0 Prepare DTC DTC operation ADC10 20 19 ADC10 Operation Continuous Transfer A continuous transfer is selected if ADC10CT bit is set The DTC will not stop after bl
166. 1111 Veco Vgs 2 A15 on MSP430x22xx devices SHSx Bits Sample and hold source select 11 10 00 ADC10SC bit 01 Timer_A OUT1 10 Timer_A OUTO 11 Timer_A OUT2 Timer_A OUT1 on MSP430x20x2 devices ADC10DF Bit 9 ADC10 data format 0 Straight binary 1 2s complement ISSH Bit 8 Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC10 20 27 ADC10 Registers ADC10DIVx Bits ADC10 SSELx CONSEQx ADC10 BUSY 20 28 7 5 Bits 4 3 Bits 2 1 Bit O ADC10 ADC10 clock divider 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC10 clock source select 00 ADC100SC 01 ACLK 10 MCLK 11 SMCLK Conversion sequence mode select 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels ADC10 busy This bit indicates an active sample or conversion operation 0 No operation is active 1 A sequence sample or conversion is active ADC10 Registers ADC10AE0 Analog Input Enable Control Register 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC10AE0x Bits ADC10 analog enable These bits enable the corresponding pin for analog 7 0 input BITO corresponds to AO BIT1 corresponds to A1 etc 0 Analog input disabled 1 Analog input enabled ADC10AE1 Analog Input Enable Control Register 1 MSP430x22xx only 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw
167. 12 bit monotonic output 8 or 12 bit voltage output resolution Programmable settling time vs power consumption Internal or external reference selection Straight binary or 2s compliment data format Self calibration option for offset correction E 1 BD Q Synchronized update capability for multiple DAC12s Note Multiple DAC12 Modules Some devices may integrate more than one DAC12 module In the case where more than one DAC12 is present on a device the multiple DAC12 modules operate identically Throughout this chapter nomenclature appears such as DAC12_xDAT or DAC12_xCTL to describe register names When this occurs the x is used to indicate which DAC12 module is being discussed In cases where operation is identical the register is simply referred to as DAC12_xCTL LT a The block diagram of the 2xx DAC12 module is shown in Figure 23 1 Figure 23 1 DAC12 Block Diagram DAC12 Introduction VeREF 0 D To ADC12 module VREF e 2 5V or 1 5V reference from ADC12 DAC12SREFx DAC12AMPx DAC12IR e 00 3 o 10 11 AVss DAC12LSELx Latch Bypass DAC12GRP DAC12ENC DAC12_ODAT Updated lt DAC12_0DAT DAC12_00UT r DAC12RES DAC12DF DAC12SREFx DAC12AMPx DAC12IR 00 3 4 10 11 AVss DAC12LSELx DAC12GRP DAC12ENC lt DAC12_1DAT Updated DAC12_1DAT
168. 1800h Jump to label TONI if EDE equals the constant The address of EDE is within PC 32 K CMP 01800h EDE Compare word EDE with 1800h JEQ TONI EDE contains 1800h Not equal A table word pointed to by R5 10 is compared with R7 Jump to label TONI if R7 contains a lower signed 16 bit number R7 19 16 is not cleared The address of the source operand is a 20 bit address in full memory range CMP W 10 R5 R7 Compare two signed numbers JL TONI R7 lt 10 R5 R7 gt 10 R5 A table byte pointed to by R5 20 bit address is compared to the value in output Port1 Jump to label TONI if values are equal The next table byte is addressed CMP B R5 amp P1OUT Compare P1 bits with table R5 1 JEQ TONI Equal contents Not equal 4 74 16 Bit MSP430X CPU DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C gt dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is
169. 1OCLK cycles The sampling timer sets SAMPCON high for the selected sample period after synchronization with ADC10CLK Total sampling time is tsample plus tgync The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC10CLK cycles as shown in Figure 20 3 Figure 20 3 Sample Timing Start Stop Start Conversion Sampling Sampling Conversion Complete i SHI lt lt sample i teonvert gt ee isync Sample Timing Considerations When SAMPCON 0 all Ax inputs are high impedance When SAMPCON 1 the selected Ax input can be modeled as an RC low pass filter during the sampling time tsampie as Shown below in Figure 20 4 An internal MUX on input resistance R max 2 KQ in series with capacitor C max 27 pF is seen by the source The capacitor C voltage Vc must be charged to within Y LSB of the source voltage Vs for an accurate 10 bit conversion ADC10 20 7 ADC10 Operation Figure 20 4 Analog Input Equivalent Circuit 20 8 Vs MSP430 V Input voltage at pin Ax Rs Ri Vs External source voltage Vi Rg External source resistance Ve R Internal MUX on input resistance C Input capacitance Ci Vc Capacitance charging voltage NS The resistance of the source Rg and R4 affect tsample The following equations can be used to calculate the minimum sampling time for a 10 bit conversion 11 tsample gt Rg R x In 2 x C Substituting the value
170. 2 7 BIT B HOFIFG amp IFG1 A JNZ L1 BIS B SELM1 SELM0 amp BCSCTL2 LFXT1 HF mode for MCLK Turn on osc HF mode 1 3MHz Crystal Clear OFIFG Delay Re test OFIFG Repeat test if needed Select LFXT1CLK Basic Clock Module 5 11 Basic Clock Module Operation 5 2 8 Synchronization of Clock Signals When switching MCLK or SMCLK from one clock source to another the switch is synchronized to avoid critical race conditions as shown in Figure 5 8 1 The current clock cycle continues until the next rising edge 2 The clock remains high until the next rising edge of the new clock 3 The new clock source is selected and continues with a full high period Figure 5 8 Switch MCLK from DCOCLK to LFXT1CLK Select LFXT1CLK DCOCLK LFXT1CLK MCLK DCOCLK gt Wait for EXT CELE __ __ gt LFXT1CLK 5 12 Basic Clock Module 5 3 Basic Clock Module Registers The basic clock module registers are listed in Table 5 1 Table 5 1 Basic Clock module Registers Register Short Form DCO control register DCOCTL Basic clock system control 1 BCSCTL1 Basic clock system control 2 BCSCTL2 Basic clock system control 3 BCSCTL3 SFR interrupt enable register 1 1E1 SFR interrupt flag register 1 IFG1 Register Type Address Read write Read write Read write Read write Read write Read write t Some of the register bits are also PUC initialized See register summary B
171. 3 Symbolic Mode 0 0 cece eee eee 3 12 3 3 4 Absolute Mode os svars enert td un eee gies Gua pe ve de veer ey 3 13 3 3 5 Indirect Register Mode cece cece 3 14 3 3 6 Indirect Autoincrement Mode cece eee eens 3 15 3 3 7 Immediate Mode 0 0 cece eee eens 3 16 3 4 Instruction Set in a n a een eens 3 17 3 4 1 Double Operand Format I Instructions 0000 eee eens 3 18 3 4 2 Single Operand Format Il Instructions 0000e eee eee 3 19 JAI JUMPS 24 tan tohe aa ed ele eel a bose pede eed 3 20 3 4 4 Instruction Cycles and Lengths 2 00 cece eee eee eee 3 72 3 45 Instruction Set Description 0 c eects 3 74 vii Contents 4 viii 16 Bit MSP430X CPU o A eave ee ais 4 1 4 1 CPU Introduction os sna cecnieadce nite er de eae ede were tant 4 2 4 2 E 2 e kee tie dels Ged cm E A EA EE AA Saree hd ead Merde doy KSAT 4 4 4 3 CPU Registers 0 cc ee eee ies see ee et 4 5 4 3 1 Program Counter PC 0c cee eee eee eee 4 5 4 3 2 Stack Pointer SP 0 cece eee eee eee 4 7 4 3 3 Status Register SR 0 0 c eee eee 4 9 4 3 4 The Constant Generator Registers CG1 and CG2 4 11 4 3 5 General Purpose Registers R4 to R15 0 eee eee eee 4 12 4 4 Addressing Modes ise 14 ride thee te eb da age phi eee cess 4 15 44 1 Register Mode ira id ie Menge eee os 4 16 4 4 2 Indexed
172. 30X CPU 4 79 MSP430 Instructions EINT Syntax Operation Emulation Description Status Bits Mode Bits Example Enable general interrupts EINT 1 gt GIE or 0008h OR SR gt SR src OR dst gt dst BIS 8 SR All interrupts are enabled The constant 08h and the status register SR are logically ORed The result is placed into the SR Status bits are not affected GIE is set OSCOFF and CPUOFF are not affected The general interrupt enable GIE bit in the status register is set Interrupt routine of ports P1 2 to P1 7 P1IN is the address of the register where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1IN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI DT Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable 4 80 16 Bit MSP430X CPU INC W INC B Syntax Operation Emulation Description Status Bits Mode Bits Example MSP430 Instructions
173. 4 RLAM works as a multiplication signed and unsigned with 2 4 8 or 16 The word instruction RLAM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the MSB n 1 MSB 1 n 2 MSB 2 n 3 MSB 3 n 4 V Undefined OSCOFF CPUOFF and GIE are not affected The 20 bit operand in R5 is shifted left by three positions It operates equal to an arithmetic multiplication by 8 RLAM A 3 R5 R5 R5x8 Figure 4 44 Rotate Left Arithmetically RLAM W and RLAM A 16 19 15 19 0 16 Bit MSP430X CPU 4 135 Extended Instructions RLAX A RLAX W RLAX B Syntax Operation Emulation Description Rotate left arithmetically address word Rotate left arithmetically word Rotate left arithmetically byte RLAX B dst RLAX dst or RLAX W dst RLAX B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt 0 ADDX A dst dst ADDX dst dst ADDX B dst dst The destination operand is shifted left one position as shown in Figure 4 45 The MSB is shifted into the carry bit C and the LSB is filled with 0 The RLAX instruction acts as a signed multiplication by 2 Figure 4 45 Destination Operand Arithmetic Shift Left Status Bits Mode Bits Example MSB 0 o p Set if result is negative reset if positiv
174. 4 DMASRSBYTE L DMASRCINCRx DMAEN DMADSTINCRx DMADTx 4g DMADSTBYTE DMA Channel 1 DMA1SA DMA1DA DMA1SZ 2 DMASRSBYTE gg DMASRCINCRx DMAEN DMADSTINCRx DMADSTBYTE DMADTx DMA Channel 2 DMA2SA DMA2DA DMA2SZ 24 DMASRSBYTE DMASRCINCRx DMAEN DMAONFETCH Te Halt CPU JTAG Active DMA Introduction NMI Interrupt Request Address Space DMA Controller 6 3 DMA Operation 6 2 DMA Operation 6 2 1 The DMA controller is configured with user software The setup and operation of the DMA is discussed in the following sections DMA Addressing Modes The DMA controller has four addressing modes The addressing mode for each DMA channel is independently configurable For example channel 0 may transfer between two fixed addresses while channel 1 transfers between two blocks of addresses The addressing modes are shown in Figure 6 2 The addressing modes are Y Fixed address to fixed address Y Fixed address to block of addresses _j Block of addresses to fixed address Y Block of addresses to block of addresses The addressing modes are configured with the DMASRCINCRx and DMADSTINCRx control bits The DMASRCINCRx bits select if the source address is incremented decremented or unchanged after each transfer The DMADSTINCRx bits select if the destination address is incremented decremented or unchanged after each transfer Transfers may be byte to byte word to word
175. 4h 21032h 2103Ah 21038h 21036h 21034h 21032h PC 23456h src 7777Ah 7777Ah 12345h__ dst 3579Bh Sum 77778h 77778h 4 34 16 Bit MSP430X CPU MSP430 and MSP430X Instructions 4 5 MSP430 and MSP430X Instructions MSP430 instructions are the 27 implemented instructions of the MSP430 CPU These instructions are used throughout the 1 MB memory range unless their 16 bit capability is exceeded The MSP430X instructions are used when the addressing of the operands or the data length exceeds the 16 bit capability of the MSP430 instructions There are three possibilities when choosing between an MSP430 and MSP430X instruction Lj To use only the MSP430 instructions The only exceptions are the CALLA and the RETA instruction This can be done if a few simple rules are met m Placement of all constants variables arrays tables and data in the lower 64 KB This allows the use of MSP430 instructions with 16 bit addressing for all data accesses No pointers with 20 bit addresses are needed m Placement of subroutine constants immediately after the subroutine code This allows the use of the symbolic addressing mode with its 16 bit index to reach addresses within the range of PC 32 KB Y To use only MSP430xX instructions The disadvantages of this method are the reduced speed due to the additional CPU cycles and the increased program space due to the necessary extension word for any double operand instruction I Use the best f
176. 6 bit timer with the CNTLx bits The maximum count value TBR max for the selectable lengths is OFFh O3FFh OFFFh and OFFFFh respectively Data written to the TBR register in 8 10 and 12 bit mode is right justified with leading zeros Clock Source Select and Divider 13 4 Timer_B The timer clock can be sourced from ACLK SMCLK or externally via TBCLK TBCLK or inverted TBCLK The clock source is selected with the TBSSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The clock divider is reset when TBCLR is set Timer_B Operation 13 2 2 Starting the Timer The timer may be started or restarted in the following ways 3 The timer counts when MCx gt 0 and the clock source is active 1 When the timer mode is either up or up down the timer may be stopped by loading 0 to TBCLO The timer may then be restarted by loading a nonzero value to TBCLO In this scenario the timer starts incrementing in the up direction from zero 13 2 3 Timer Mode Control The timer has four modes of operation as described in Table 13 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 13 1 Timer Modes MCx Mode Description 00 Stop The timer is halted 01 Up The timer repeatedly counts from zero to the value of compare register TBCLO 10 Continuous The timer repeatedly counts from zero to the value selected by the CNTLx bits 11 U
177. 7 8 9 1 2 8 STOP R W ACK ACK Condition P START and STOP conditions are generated by the master and are shown in Figure 17 3 A START condition is a high to low transition on the SDA line while SCL is high A STOP condition is a low to high transition on the SDA line while SCL is high The bus busy bit UCBBUSY is set after a START and cleared after a STOP Data on SDA must be stable during the high period of SCL as shown in Figure 17 4 The high and low state of SDA can only change when SCL is low otherwise START or STOP conditions will be generated Figure 17 4 Bit Transfer on the I C Bus SDA SCL Data Line Stable Data A Vem Venom kt Change of Data Allowed Universal Serial Communication Interface C Mode 17 7 USCI Operation 2C Mode 17 3 3 12C Addressing Modes The 12C mode supports 7 bit and 10 bit addressing modes 7 Bit Addressing In the 7 bit addressing format shown in Figure 17 5 the first byte is the 7 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte Figure 17 5 12C Module 7 Bit Addressing Format MES E LPR e 10 8 q ME 8 e Slave Address ACK Data Ack P 10 Bit Addressing In the 10 bit addressing format shown in Figure 17 6 the first byte is made up of 11110b plus the two MSBs of the 10 bit slave address and the R W bit The ACK bit is sent from the receiver after each byte The next byte is the remaining 8 bits of the 10 bit slave
178. A interrupt priority and has a dedicated interrupt vector as shown in Figure 12 15 The TACCRO CCIFG flag is automatically reset when the TACCRO interrupt request is serviced Figure 12 15 Capture Compare TACCRO Interrupt Flag Capture IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TAIV Interrupt Vector Generator The TACCR1 CCIFG TACCR2 CCIFG and TAIFG flags are prioritized and combined to source a single interrupt vector The interrupt vector register TAIV is used to determine which flag requested an interrupt The highest priority enabled interrupt generates a number in the TAIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer_A interrupts do not affect the TAIV value Any access read or write of the TAIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TACCR1 and TACCR2 CCIFG flags are set when the interrupt service routine accesses the TAIV register TACCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TACCR2 CCIFG flag will generate another interrupt Timer_A 12 17 Timer_A Operation TAIV Software Example The following software example shows the recommended use
179. AC12 Modules Multiple DAC12s can be grouped together with the DAC12GRP bit to synchronize the update of each DAC12 output Hardware ensures that all DAC12 modules in a group update simultaneously independent of any interrupt or NMI event DAC12_0 and DAC12_1 are grouped by setting the DAC12GRP bit of DAC12_0 The DAC12GRP bit of DAC12_1 is don t care When DAC12_0 and DAC12_1 are grouped Ly The DAC12_1 DAC12LSELx bits select the update trigger for both DACs Li The DAC12LSELx bits for both DACs must be gt 0 Li The DAC12ENC bits of both DACs must be set to 1 When DAC12_0 and DAC12_1 are grouped both DAC12_xDAT registers must be written to before the outputs update even if data for one or both of the DACs is not changed Figure 23 6 shows a latch update timing example for grouped DAC12_0 and DAC12_1 When DAC12_0 DAC12GRP 1 and both DAC12_x DAC12LSELx gt 0 and either DAC12ENC 0 neither DAC 12 will update Figure 23 6 DAC 12 Group Update Example Timer_A3 Trigger 23 8 DAC12_0 DAC12GRP DAC12_0 DAC12ENC TimerA_OUT1 DAC12_ODAT New Data DAC12_1DAT New Data DAC12_0 Latch Trigger DAC12_0 and DAC12_1 Updated Simultaneously Na a PAC12_0 Updated DAC12_0 DAC12LSELx gt 0 AND DAC12_1 DAC12LSELx 2 DAC12_0 DAC12LSELx 2 DAC12 AAA A a G E o _ Note DAC12 Settling Time The DMA controller is capable of transferring data to the DAC12 faster than the DAC12 output can
180. ADC10CT cleared or ADC10SA is written to ADC10 block one This bit indicates for two block mode which block is filled with ADC10 conversion results ADC10B1 is valid only after ADC10IFG has been set the first time during DTC operation ADC10TB must also be set 0 Block 2 is filled 1 Block 1 is filled This bit should normally be reset ADC10 20 31 ADC10 Registers ADC10DTC1 Data Transfer Control Register 1 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 DTC Bits DTC transfers These bits define the number of transfers in each block Transfers 7 0 0 DTC is disabled 01h OFFh Number of transfers per block ADC10SA Start Address Register for Data Transfer 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 7 6 5 4 3 2 1 0 Te A rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rO ADC10SAx Bits ADC10 start address These bits are the start address for the DTC A write 15 1 to register ADC10SA is required to initiate DTC transfers Unused Bit O Unused Read only Always read as 0 20 32 ADC10 Chapter 21 ADC12 The ADC12 module is a high performance 12 bit analog to digital converter This chapter describes the ADC12 of the MSP430 2xx device family Topic Page Pala FADCIZ2INtroduction Gaeaasnaosocacponnnsapenoedonsedheasodaedr 21 2 21 2 ADC 120 perdon alas jaa 21 4 2IESRADC 12 Reg Ste 21 20 ADC12 Introduction 21 1 ADC12 Introduction 21 2 ADC12
181. Address Register 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAxSZx Bits DMA size The DMA size register defines the number of byte word data per 15 0 block transfer DMAxSZ register decrements with each word or byte transfer When DMAxSZ decrements to 0 it is immediately and automatically reloaded with its previously initialized value 00000h Transfer is disabled 00001h One byte or word to be transferred 00002h Two bytes or words have to be transferred OFFFFh 65535 bytes or words have to be transferred 6 26 DMA Controller DMA Registers DMAIV DMA Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 rO ro ro rO r 0 r 0 r 0 ro DMAIVx Bits DMA interrupt vector value 15 0 Interrupt DMAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h DMA channel 0 DMAOIFG Highest 04h DMA channel 1 DMAI1IFG 06h DMA channel 2 DMA2IFG 08h Reserved OAh Reserved OCh Reserved OEh Reserved Lowest DMA Controller 6 27 Chapter 7 Flash Memory Controller This chapter describes the operation of the MSP430x2xx flash memory controller Topic Page 7 1 Flash Memory Introduction cece cece eee e eee eee 7 2 7 2 Flash Memory Segmentation 0ceeeeeeeeee eee eee eee 7 3 7 3 Flash Memory Operation ceeeeeee cece cette eens 7 5 7 4 Flash Memory Registers oooooccoonocccoconarccn
182. Ah 010A8h 010A6h The autoincrementing of the register contents occurs after the operand is fetched This is shown in Figure 3 8 Figure 3 8 Operand Fetch Operation Instruction Address RISC 16 Bit CPU 3 15 Addressing Modes 3 3 7 Immediate Mode The immediate mode is described in Table 3 10 Table 3 10 Immediate Mode Description 3 16 Length Operation Comment Example Before OFF16h OFF14h OFF12h 010AAh 010A8h 010A6h RISC 16 Bit CPU Assembler Code MOV 45h TONI Two or three words Content of ROM MOV PC X PC 45 X TONI PC It is one word less if a constant of CG1 or CG2 can be used Move the immediate constant 45h which is contained in the word following the instruction to destination address TONI When fetching the source the program counter points to the word following the instruction and moves the contents to the destination Valid only for a source operand MOV 45h TONI Address Register Space Fo2080n Po OFF16h 01192h 01234h 010A8h ter OFF18h OFF16h OFF 14h OFF12h 010AAh 010A8h 010A6h Address Register Space Oxxxxh PC Instruction Set 3 4 Instruction Set The complete MSP430 instruction set consists of 27 core instructions and 24 emulated instructions The core instructions are instructions that have unique op codes decoded by the CPU The emulated instructions are instructions that make code e
183. B A src dst src dst C gt dst TS he ee g SUBX B A src dst dst not src 1 dst oe SUBCX B A src dst dst not src C gt dst SAR A CMPX B A src dst dst src we OT DADDX B A src dst src dst C gt dst decimal BITX B A src dst src and dst 0 Z BICX B A src dst not src and dst dst BISX B A src dst src or dst gt dst XORX B A src dst src xor dst gt dst EA EZ ANDX B A src dst src and dst dst 0 Z The status bit is affected The status bit is not affected The status bit is cleared The status bit is set 16 Bit MSP430X CPU 4 47 MSP430X Extended Instructions The four possible addressing combinations for the extension word for format instructions are shown in Figure 4 29 Figure 4 29 Extended Format Instruction Formats 15 14 13 12 311 10 9 8 7 6 5 4 3 0 src 19 16 src 15 0 Op code src As dst src 15 0 dst 15 0 If the 20 bit address of a source or destination operand is located in memory not in a CPU register then two words are used for this operand as shown in Figure 4 30 Figure 4 30 20 Bit Addresses in Memory 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 TIAS OEE Address Operand LSBs 15 0 4 48 16 Bit MSP430X CPU MSP430X Extended Instructions Extended Single Operand Format ll Instructions Extended MSP430X Format ll instructions are listed in Table 4 14 Table 4 14 Extended
184. B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS ia R7 is positive but not zero R7NEG ti R7 is negative R7ZERO oew R7 is zero The low byte of R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST B R7 Test low byte of R7 JN R7NEG Low byte of R7 is negative JZ R7ZERO Low byte of R7 is zero R7POS i Low byte of R7 is positive but not zero R7NEG sti Low byte of R7 is negative R7ZERO __ Low byte of R7 is zero 4 110 16 Bit MSP430X CPU XOR W XOR B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Exclusive OR source word with destination word Exclusive OR source byte with destination byte XOR dst or XOR W dst XOR B dst s
185. B 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The signed 20 bit number in R5 is shifted arithmetically right two positions RRAM A 2 R5 R5 4 gt R5 The signed 20 bit value in R15 is multiplied by 0 75 0 5 0 25 x R15 PUSHM A 1 R15 Save extended R15 on stack RRAM A 1 R15 R15 x 0 5 gt R15 ADDX A SP R15 R15 x 0 5 R15 1 5 x R15 gt R15 RRAM A 1 R15 1 5 x R15 x 0 5 0 75 x R15 gt R15 Figure 4 47 Rotate Right Arithmetically RRAM W and RRAM A 15 0 19 16 19 0 Cl el 4 138 16 Bit MSP430X CPU RRAX A RRAX W RRAX B Syntax Operation Description Status Bits Mode Bits Extended Instructions Rotate Right Arithmetically the 20 bit operand Rotate Right Arithmetically the 16 bit operand Rotate Right Arithmetically the 8 bit operand RRAX A Rdst RRAX W Rast RRAX Rdst RRAX B Rdst RRAX A dst RRAX W dst or RRAX dst RRAX B dst MSB gt MSB gt MSB 1 LSB 1 LSB gt C Register Mode for the destination the destination operand is shifted right by one bit position as shown in Figure 4 48 The MSB retains its value sign The word instruction RRAX W clears the bits Rdst 19 16 the byte instruction RRAX B clears the bits Rdst 19 8 The MSB retains its value sign the LSB is shifted into the carry bit RRAX here operates equal to a signed division by 2 All other modes for the destination the destination operand is shifted
186. BCCR1 CLLDx bits control the update TBCL4 TBCL5 TBCL6 TBCCR4 CLLDx bits control the update TBCLO independent 11 TBCLO TBCL1 TBCL2 TBCL3 TBCL4 TBCL5 TBCL6 TBCCR1 CLLDx bits control the update CNTLx Bits Counter Length 1211 00 16 bit TBR max OF FFFh 01 12 bit TBR max OFFFh 10 10 bit TBR max O3FFh 11 8 bit TBR max OF Fh Unused Bit10 Unused TBSSELx Bits Timer_B clock source select 9 8 00 TBCLK 01 ACLK 10 SMCLK 11 Inverted TBCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 MCx Bits Mode control Setting MCx 00h when Timer_B is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TBCLO 10 Continuous mode the timer counts up to the value set by CNTLx 11 Up down mode the timer counts up to TBCLO and down to 0000h Timer_B 13 21 Timer_B Registers Unused Bit 3 Unused TBCLR Bit 2 Timer_B clear Setting this bit resets TBR the clock divider and the count direction The TBCLR bit is automatically reset and is always read as zero TBIE Bit 1 Timer_B interrupt enable This bit enables the TBIFG interrupt request 0 Interrupt disabled 1 Interrupt enabled TBIFG Bit O Timer_B interrupt flag 0 No interrupt pending 1 Interrupt pending TBR Timer_B Register 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw
187. BCCRO CCIFG are prioritized and combined to source a single interrupt vector The interrupt vector register TBIV is used to determine which flag requested an interrupt The highest priority enabled interrupt excluding TBCCRO CCIFG generates a number in the TBIV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled Timer_B interrupts do not affect the TBIV value Any access read or write of the TBIV register automatically resets the highest pending interrupt flag If another interrupt flag is set another interrupt is immediately generated after servicing the initial interrupt For example if the TBCCR1 and TBCCR2 CCIFG flags are set when the interrupt service routine accesses the TBIV register TBCCR1 CCIFG is reset automatically After the RETI instruction of the interrupt service routine is executed the TBCCR2 CCIFG flag will generate another interrupt Timer_B Operation TBIV Interrupt Handler Examples The following software example shows the recommended use of TBIV and the handling overhead The TBIV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU clock cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies
188. Bits Mode Bits Example Loop Example Loop Move source to destination Move source to destination MOV src dst or MOV W src dst MOV B src dst src gt dst The source operand is moved to the destination The source operand is not affected The previous contents of the destination are lost Status bits are not affected OSCOFF CPUOFF and GIE are not affected The contents of table EDE word data are copied to table TOM The length of the tables must be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV R10 TOM EDE 2 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter 0 continue copying suites Copying completed The contents of table EDE byte data are copied to table TOM The length of the tables should be 020h locations MOV EDE R10 Prepare pointer MOV 020h R9 Prepare counter MOV B R10 TOM EDE 1 R10 Use pointer in R10 for both tables DEC R9 Decrement counter JNZ Loop Counter 0 continue copying As Copying completed 3 52 RISC 16 Bit CPU NOP Syntax Operation Emulation Description Status Bits Instruction Set No operation NOP None MOV 0 R3 No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status bits are not affected The NOP instruction is mainly used for two purposes _j To fill one
189. Bits 9 7 are ignored In 10 bit addressing mode Bit 9 is the MSB UCBxI2CSA USCI_Bx I2C Slave Address Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 12CSAx Bits 12C slave address The I2CSAx bits contain the slave address of the external 9 0 device to be addressed by the USCI_Bx module It is only used in master mode The address is right justified In 7 bit slave addressing mode Bit 6 is the MSB Bits 9 7 are ignored In 10 bit slave addressing mode Bit 9 is the MSB Universal Serial Communication Interface C Mode 17 31 USCI Registers C Mode UCBxI2CIE USCI_Bx I C Interrupt Enable Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved Bits Reserved 7 4 UCNACKIE Bit3 Not acknowledge interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCSTPIE Bit 2 Stop condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCSTTIE Bit 1 Start condition interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCALIE Bit O Arbitration lost interrupt enable 0 Interrupt disabled 1 Interrupt enabled 17 32 Universal Serial Communication Interface 1 C Mode USCI Registers C Mode 1E2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 Bits 7 4 UCBOTXIE Bit3 UCBORXIE Bit 2 Bits 1 0 These bits may be used by other modules see the device specific data sheet USCI_BO transmit interrupt enable 0
190. C 2 x offset gt PC If N XOR V 1 then execute the following instruction The status register negative bit N and overflow bit V are tested If both N and V are set or reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If only one is set the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is greater or equal to the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 gt R7 compare on signed numbers JGE EDE Yes R6 gt R7 Aion No proceed 3 46 RISC 16 Bit CPU JL Syntax Operation Description Status Bits Example Instruction Set Jump if less JL label If N XOR V 1 then jump to label PC 2 x offset gt PC If N XOR V 0 then execute following instruction The status register negative bit N and overflow bit V are tested If only one is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If both N and V are set or reset the instruction following the jump is executed This allows comparison of signed integers Status bits are not affected When the content of R6 is less than the memory pointed to by R7 the program continues at label EDE CMP R7 R6 R6 lt R7 compare on signed numbers JL EDE Yes R6 lt R7 TRE No proceed RISC 16 Bit CPU 3 47 Instruc
191. CADDR bit is set when a received character has its address bit set and is transferred to UCAxRXBUF The UCDORM bit is used to control data reception in the address bit multiprocessor format When UCDORN is set data characters with address bit O are assembled by the receiver but are not transferred to UCAXRXBUF and no interrupts are generated When a character containing a set address bit is received the character is transferred into UCAxRXBUF UCAXRXIFG is set and any applicable error flag is set wnen UCRXEIE 1 When UCRXEIE 0 and a character containing a set address bit is received but has a framing error or parity error the character is not transferred into UCAxRXBUF and UCAXxRXIFG is not set If an address is received user software can validate the address and must reset UCDORM to continue receiving data If UCDORM remains set only address characters with address bit 1 will be received The UCDORM bit is not modified by the USCI hardware automatically When UCDORM 0 all received characters will set the receive interrupt flag UCAXRXIFG If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is completed For address transmission in address bit multiprocessor mode the address bit of a character is controlled by the UCTXADDR bit The value of the UCTXADDR bit is loaded into the address bit of the character transferred from UCAxTXBUF to the transmit shift register UCTXA
192. CAxTXBUF must be ready for new data UCAXTXIFG 1 This generates a break field of 13 bits followed by a break delimiter and the synch character The length of the break delimiter is controlled with the UCDELIMx bits UCTXBRK is reset automatically when the synch character is transferred from UCAxTXBUF into the shift register 3 Write desired data characters to UCAxTXBUF UCAxTXBUF must be ready for new data UCAXTXIFG 1 The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data Universal Serial Communication Interface UART Mode 15 11 USCI Operation UART Mode 15 3 5 IrDA Encoding and Decoding IrDA Encoding When UCIREN is set the IrDA encoder and decoder are enabled and provide hardware bit shaping for IrDA communication The encoder sends a pulse for every zero bit in the transmit bit stream coming from the UART as shown in Figure 15 7 The pulse duration is defined by UCIRTXPLx bits specifying the number of half clock periods of the clock selected by UCIRTXCLK Figure 15 7 UART vs IrDA Data Format IrDA Decoding Start Stop Bit Data Bits Bit p gt lt gt UART IrDA To set the pulse time of 3 16 bit period required by the IrDA standard the BITCLK16 clock is selected with UCIRTXCLK 1 and the pulse length is set to 6 half clock cycles with UCIRTXPLx 6
193. CHx Wait for Enable SHS 0 SAMPCON 4 mer 4 8 16 64 x ADC10CLK Sample Input Channel Ax If x gt 0 then x x 1 12 x ADC10CLK 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC1OIFG is Set ADC10 20 11 X 20 12 ADC10 Operation Repeat Single Channel Mode A single channel selected by INCHx is sampled and converted continuously Each ADC result is written to ADC10MEM Figure 20 7 shows the repeat single channel mode Figure 20 7 Repeat Single Channel Mode x INCHx Wait for Enable SHS 0 and ENC 1 or 4 and ADC10SC 4 Wait for Trigger SAMPCON 4 ENC 0 4 8 16 64 x ADC10CLK Sample K Input Channel Ax 12 x ADC10CLK MSC 1 ENC 1 1 x ADC10CLK Conversion Completed Result to ADC10MEM ADC10IFG is Set input channel Ax ADC10 ADC10 Operation Repeat Sequence of Channels Mode A sequence of channels is sampled and converted repeatedly The sequence begins with the channel selected by INCHx and decrements to channel AO Each ADC result is written to ADC1OMEM The sequence ends after conversion of channel AO and the next trigger signal re starts the sequence Figure 20 8 shows the repeat sequence of channels mode Figure 20 8 Repeat Sequence of Channels Mode x INCHx Wait for Enable SHS 0 and ENC 1or 4 and ADC10SC 4 Wait for Trigger
194. CI Mode The UCMODEx bits select the synchronous mode when 2 1 UCSYNC 1 00 3 pin SPI 01 4 pin SPI master slave enabled if STE 1 10 4 pin SPI master slave enabled if STE 0 11 12 mode UCSYNC BitO Synchronous mode enable 0 Asynchronous mode 1 Synchronous mode 17 26 Universal Serial Communication Interface 12C Mode USCI Registers C Mode UCBxCTL1 USCI_Bx Control Register 1 7 rw 0 UCSSELx Unused UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST 5 4 3 2 1 0 UCSSELx ES UCTR UCTXNACK UCTXSTP UCTXSTT UCSWRST ro rw 0 rw 0 rw 0 rw 0 1 rw 0 Bits 7 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O rw USCI clock source select These bits select the BRCLK source clock 00 UCLKI 01 ACLK 10 SMCLK 11 SMCLK Unused Transmitter Receiver 0 Receiver 1 Transmitter Transmit a NACK UCTXNACK is automatically cleared after a NACK is transmitted 0 Acknowledge normally 1 Generate NACK Transmit STOP condition in master mode Ignored in slave mode In master receiver mode the STOP condition is preceded by a NACK UCTXSTP is automatically cleared after STOP is generated 0 No STOP generated 1 Generate STOP Transmit START condition in master mode Ignored in slave mode In master receiver mode a repeated START condition is preceded by a NACK UCTXSTT is automatically cleared after START condition and address information is transmitted Ignored in slave mode 0 Do not generate START condition
195. CLK LFXT1CLK 4 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 4 MCLK cycles 2 ust t The additional 2 us are needed to start the DCOCLK See the device specific data sheet for parameters ADC10 Operation 20 2 8 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 20 13 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error is large Deriving absolute temperature values in the application requires calibration See the device specific data sheet for the parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the Vrer output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 20 13 Typical Temperature Sensor Transfer Function Volts 1 300 1 200 1 100 1 000 0 900 0 800 0 700 Vtemp 0 00355 TEMPc 0 986 Celsius ADC10 20 21 ADC10 Operation 20 2 9 ADC10 Grounding and Noise Considerations As with any high resolution ADC appropriate
196. COFF CPUOFF and GIE are not affected A 16 bit constant 7654h is subtracted from RAM word EDE SUB 7654h amp EDE Subtract 7654h from EDE A table word pointed to by R5 20 bit address is subtracted from R7 Afterwards if R7 contains zero jump to label TONI R5 is then auto incremented by 2 R7 19 16 0 SUB R5 R7 Subtract table number from R7 R5 2 JZ TONI R7 R5 before subtraction R7 lt gt R5 before subtraction Byte CNT is subtracted from byte R12 points to The address of CNT is within PC 32 K The address R12 points to is in full memory range SUB B CNT 0 R12 Subtract CNT from R12 4 106 16 Bit MSP430X CPU SUBC W SUBC B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Subtract source word with carry from destination word Subtract source byte with carry from destination byte SUBC src dst or SUBC W src dst SUBC B src dst not src C dst gt dst or dst src 1 C dst The source operand is subtracted from the destination operand This is done by adding the 1 s complement of the source carry to the destination The source operand is not affected the result is written to the destination operand Used for 32 48 and 64 bit operands N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB reset otherwise V Set
197. Communication Interface SPI Mode Chapter 17 Universal Serial Communication Interface 12C Mode The universal serial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the I2C mode Topic Page 17 1 USC OVerview aaa 17 2 17 2 USCI Introduction I2C Mode 000e cece eens 17 3 17 3 USCI Operation I2C Mode 022eeee cece eee eee eens 17 5 17 4 USCI Registers I2C Mode 20eee cece eee eee eees 17 25 17 1 USCI Overview 17 1 USCI Overview The universal serial communication interface USCI modules support multiple serial communication modes Different USCI modules support different modes Each different USCI module is named with a different letter For example USCI_A is different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_AO and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices The USCI_Ax modules support Y UART mode _j Pulse shaping for IrDA communications Automatic baud rate detection for LIN communications Lj SPI mode The USCI_Bx modules support g 12C mode Y SPI mode 17 2 Universal Serial Communication Interface 12C Mode USCI Introduct
198. D B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 gt dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost Set if result is negative reset if positive Set if dst contained 2 reset otherwise Reset if dst contained 0 or 1 set otherwise Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location Starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE 0FEh Example MOV EDE R6 MOV 510 R10 L 1 MOV R6 TONI EDE 2 R6 DECD R10 JNZ L 1 Memory at location LEO is decremented by two DECD B LEO Decrement MEM LEO Decrement status byte STATUS by two DECD B STATUS 3 38 RISC 16 Bit CPU DINT Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Disable general interrupts DINT 0 gt GIE or OFFF7h AND SR gt SR NOT src AND dst gt dst BIC 8
199. D16DIVx SD16SSELx DON A SDIGOVIE rw 0 rw 0 rw 0 ro rw 0 rw 0 rw 0 Reserved SD16_A clock divider 000 1 001 3 010 16 011 48 1xx Reserved Low power mode This bit selects a reduced speed reduced power mode 0 Low power mode is disabled 1 Low power mode is enabled The maximum clock frequency for the SD16_A is reduced SD16_A clock divider oo A 01 2 10 4 11 8 SD16_A clock source select 00 MCLK 01 SMCLK 10 ACLK 11 External TACLK Vuip buffer on 0 Off 1 On Reference generator on 0 Reference off 1 Reference on SD16_A overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled Reserved SD16_A 24 17 SD16_A Registers SD16CCTLO SD16_A Control Register 0 15 14 13 12 11 10 9 8 ETE E E ro rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 atts ats att wor om owe rs Je rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 t Reserved in MSP430x20x3 devices Reserved Bit 15 Reserved SD16BUFx Bits High impedance input buffer mode 14 13 00 Buffer disabled 01 Slow speed current 10 Medium speed current 11 High speed current SD16UNI Bit12 Unipolar mode select 0 Bipolar mode 1 Unipolar mode SD16XOSR Bit 11 Extended oversampling ratio This bit along with the SD16OSRx bits select the oversampling ratio See SD16OSRx bit description for settings SDi6SNGL Bit10 Single conversion mode select 0 Continuou
200. D16SSELx and SD16DIVx and the oversampling rate using the SD160SRx and SD16XOSR bits The digital filter for each enabled ADC channel completes the decimation of the digital bit stream and outputs new conversion results to the SD16MEMO register at the sample frequency fs Figure 24 3 Comb Filter s Frequency Response with OSR 32 GAIN dB 100 120 140 Frequency fm SD16_A 24 7 SD16_A Operation Figure 24 4 24 8 VESR Figure 24 4 shows the digital filter step response and conversion points For step changes at the input after start of conversion a settling time must be allowed before a valid conversion result is available The SD16INTDLYx bits can provide sufficient filter settling time for a full scale change at the ADC input If the step occurs synchronously to the decimation of the digital filter the valid data will be available on the third conversion An asynchronous step will require one additional conversion before valid data is available Digital Filter Step Response and Conversion Points SD16_A Asynchronous Step Synchronous Step pT TTT TT TTT 7 Conversion Conversion Digital Filter Output SD16_A Operation The number of bits output by the digital filter is dependent on the oversampling ratio and ranges from 15 to 30 bits Figure 24 5 shows the digital filter output and their relation to SD16MEMO for each OSR LSBACC an
201. DDR is automatically cleared when the start bit is generated Universal Serial Communication Interface UART Mode USCI Operation UART Mode Figure 15 4 Address Bit Multiprocessor Format Blocks of a Characters OE UCAXTXD UCAxRXD _ ee Idle Periods of No Significance aes UCAxTXD UCAxRXD Expanded First Character Within Block AD Bit Is 0 for Is an Address AD Bit Is 1 Data Within Block Idle Time Is of No Significance Break Reception and Generation When UCMODEx 00 01 or 10 the receiver detects a break when all data parity and stop bits are low regardless of the parity address mode or other character settings When a break is detected the UCBRK bit is set If the break interrupt enable bit UCBRKIE is set the receive interrupt flag UCAxRXIFG will also be set In this case the value in UCAxRXBUF is Oh since all data bits were zero To transmit a break set the UCTXBRK bit then write Oh to UCAxTXBUF UCAxTXBUF must be ready for new data UCAxTXIFG 1 This generates a break with all bits low UCTXBRK is automatically cleared when the start bit is generated Universal Serial Communication Interface UART Mode 15 9 USCI Operation UART Mode 15 3 4 Automatic Baud Rate Detection When UCMODEx 11 UART mode with automatic baud rate detection is selected For automatic baud rate detection a data frame is preceded by a synchronization sequence that consists of a break and a synch field A break is de
202. DT control register is password protected Control of RST NMI pin function Selectable clock source Can be stopped to conserve power Clock fail safe feature E VE gt a i The WDT block diagram is shown in Figure 10 1 Note Watchdog Timer Powers Up Active After a PUC the WDT module is automatically configured in the watchdog mode with an initial 32768 clock cycle reset interval using the DCOCLK The user must setup or halt the WDT prior to the expiration of the initial reset interval Watchdog Timer Figure 10 1 Watchdog Timer Block Diagram Generator PUC 16 bit Counter MCLK SMCLK ACLK Watchdog Timer Introduction WDTCTL MSB Password Compare Write Enable Low Byte MDB 16 bit WDTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL WDTIS1 Clock Request Logic LSB WDTISO Watchdog Timer MCLK Active SMCLK Active ACLK Active 10 3 Watchdog Timer Operation 10 2 Watchdog Timer Operation The WDT module can be configured as either a watchdog or interval timer with the WDTCTL register The WDTCTL register also contains control bits to configure the RST NMI pin WDTCTL is a 16 bit password protected read write register Any read or write access must use word instructions and write accesses must include the write password O5Ah in the up
203. E Bits 7 5 Bit 4 Bits Bit O These bits may be used by other modules See device specific data sheet NMI interrupt enable This bit enables the NMI interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled These bits may be used by other modules See device specific data sheet Watchdog timer interrupt enable This bit enables the WDTIFG interrupt for interval timer mode It is not necessary to set this bit for watchdog mode Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled Watchdog Timer 10 9 Watchdog Timer Registers IFG1 Interrupt Flag Register 1 7 NMIIFG WDTIFG 10 10 6 5 4 3 2 1 0 rw 0 Bits 7 5 Bit 4 Bits 3 1 Bit O rw 0 These bits may be used by other modules See device specific data sheet NMI interrupt flag NMIIFG must be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear NMIIFG by using BIS B orBIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules See device specific data sheet
204. E DMA ABORT DMAREQ Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O DMA Registers DMA source byte This bit selects the source as a byte or word 0 Word 1 Byte DMA level This bit selects between edge sensitive and level sensitive triggers 0 Edge sensitive rising edge 1 Level sensitive high level DMA enable 0 Disabled 1 Enabled DMA interrupt flag 0 No interrupt pending 1 Interrupt pending DMA interrupt enable 0 Disabled 1 Enabled DMA Abort This bit indicates if a DMA transfer was interrupt by an NMI 0 DMA transfer not interrupted 1 DMA transfer was interrupted by NMI DMA request Software controlled DMA start DMAREQ is reset automatically 0 No DMA start 1 Start DMA DMA Controller 6 23 DMA Registers DMAxSA DMA Source Address Register 15 14 13 12 11 10 9 8 Reserved ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 O ee O ro ro ro ro rw rw rw rw 15 14 13 12 11 10 9 8 rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw DMAXSA Bits DMA source address The source address register points to the DMA source 15 0 address for single transfers or the first source address for block transfers The source address register remains unchanged during block and burst block transfers Devices that have addressable memory range 64 KB or below contain a single word for the DMAXSA The upper word is automatically cleared when writing using word operations Reads from this location
205. E amp USICTLO SDA output MOV B 0FFh amp USISRL MSB 1 MOV B 01h amp USICNT z USICNTX 1 TEST USIIFG BIT B USIIFG amp USICTL1 Test USIIFG JZ TEST USIIFG continue A START condition is a high to low transition on SDA while SCL is high The START condition can be generated by setting the MSB of the shift register to 0 Setting the USIGE and USIOE bits makes the output latch transparent and the MSB of the shift register is immediately presented to SDA and pulls the line low Clearing USIGE resumes the clocked latch function and holds the 0 on SDA until data is shifted out with SCL Generate START MOV B 000h amp USISRL MSB 0 BIS B USIGE USIOE amp USICTLO Latch SDA output enabled BIC B USIGE amp USICTLO Latch disabled continue 14 10 Universal Serial Interface STOP Condition Releasing SCL USI Operation A STOP condition is a low to high transition on SDA while SCL is high To finish the acknowledgment bit and pull SDA low to prepare the STOP condition generation requires clearing the MSB in the shift register and loading 1 into USICNTx This will generate a low pulse on SCL and during the low phase SDA is pulled low SCL stops in the idle or high state since the module is in master mode To generate the low to high transition the MSB is set in the shift register and USICNTx is loaded with 1 Setting the USIGE and USIOE bits makes the output latch transparent and the MSB of USISRL release
206. E Label2 Yes 12344h lt R5 lt 7FFFFh No 80000h lt R5 lt 12345h 4 86 16 Bit MSP430X CPU JL Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if Less signed JL label If N xor V 1 PC 2 x Offset gt PC If N xor V 0 execute following instruction The negative bit N and the overflow bit V in the status register are tested If only one is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in full memory range If both bits N and V are set or both are reset the instruction after the jump is executed JL is used for the comparison of signed operands also for incorrect results due to overflow the decision made by the JL instruction is correct Status bits are not affected OSCOFF CPUOFF and GIE are not affected If byte EDE contains a smaller signed operand than byte TONI continue at Label1 The address EDE is within PC 32 K CMP B amp TONI EDE ls EDE lt TONI JL Label1 Yes No TONI lt EDE If the signed content of R6 is less than the memory pointed to by R7 20 bit address the program continues at Label Label5 Data and program in full memory range CMP R7 R6 Is R6 lt R7 JL Label5 Yes go to Label5 No continue here If R5 lt 12345h sign
207. E and the GIE bits are set then the ADC10IFG flag generates an interrupt request The ADC1OIFG flag is automatically reset when the interrupt request is serviced or may be reset by software Figure 20 16 ADC10 Interrupt System Set ADC10IFG nv 0 ADC1O0IE IRQ Interrupt Service Requested ADC10CLK IRACC Interrupt Request Accepted ADC10 20 23 ADC10 Registers 20 3 ADC10 Registers The ADC10 registers are listed in Table 20 3 Table 20 3 ADC10 Registers Register Short Form Register Type Address Initial State ADC10 input enable register 0 ADC10AE0 Read write 04Ah Reset with POR ADC10 input enable register 1 ADC10AE1 Read write 04Bh Reset with POR ADC10 control register O ADC10CTLO Read write 01BOh Reset with POR ADC10 control register 1 ADC10CTL1 Read write 01B2h Reset with POR ADC10 memory ADC10MEM Read 01B4h Unchanged ADC10 data transfer control register O ADC10DTCO Read write 048h Reset with POR ADC10 data transfer control register 1 ADC10DTC1 Read write 049h Reset with POR ADC10 data transfer start address ADC10SA Read write 01BCh 0200h with POR 20 24 ADC10 ADC10 Registers ADC10CTLO ADC10 Control Register 0 15 14 13 12 11 10 9 8 sree a anctese nerour nerBuRST rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 _ Modifiable only when ENC 0 SREFx Bits Select reference 15 13 000 Va Vcc and Vg Vss 001 Vr VREF
208. Extended Instructions INCDX A Double increment destination address word INCDX W Double increment destination word INCDX B Double increment destination byte Syntax INCDX A dst INCDX dst or INCDX W dst INCDX B dst Operation dst 2 gt dst Emulation ADDX A_ 2 dst ADDX 2 dst ADDX B_ 2 dst Example The destination operand is incremented by two The original contents are lost Status Bits N Set if result is negative reset if positive Z Set if dst contained OFFFFEh reset otherwise Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFFEh or OFFFFFh reset otherwise Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFFEh or O7FFFFh reset otherwise Set if dst contained O7FFEh or O7FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise Mode Bits OSCOFF CPUOFF and GIE are not affected Example RAM byte LEO is incremented by two PC points to upper memory INCDX B LEO Increment LEO by two 16 Bit MSP430X CPU 4 127 Extended Instructions INVX A INVX W INVX B Syntax Operation Emulation Description Status Bits Mode Bits Example Example 4 128 Invert destination Invert destination Invert destination INVX A dst INVX dst or INVX W dst INVX B dst NOT dst gt dst XORX A HOFFFFFh dst XORX HOFFFFh dst XORX B
209. F VeREF R AVcc INCHx m SREF1 11 10 01 00 4 m SREFO CONSEQX peo ADC100SC AO SREF2 Xt of ADC100N ADC10SSELx po ADC10DIVx A3 0 V V 00 b Sample R R A and ra y Divider 01 ACLK AS dd i 1 18 10 MCLK H t 11 SMCLK Si Conver 9 gt ADC10CLK SHSx ISSH ar2t Eno A13t 00 ADC10SC Ata SAMPCON A15t lt Syne 01 Tat Sync 10 TAO 11 TA2t ADC10DF ADC10SHTx MSC ADC10MEM Y 4 Data Transfer i Controller 7 RAM Flash Peripherials ADC10SA 7 AVss ADC10CT ADC10TB ADC10B1 tMSP430x22xx devices only Channels A12 A15 tied to channel A11 in other devices FTA1 on MSP430x20x2 devices ADC10 20 3 ADC10 Operation 20 2 ADC10 Operation The ADC10 module is configured with user software The setup and operation of the ADC10 is discussed in the following sections 20 2 1 10 Bit ADC Core The ADC core converts an analog input to its 10 bit digital representation and stores the result in the ADC10MEM register The core uses two programmable selectable voltage levels Vp and Vp_ to define the upper and lower limits of the conversion The digital output Napc is full scale O3FFh when the input signal is equal to or higher than Vp and zero when the input signal is equal to or lower than Vp The input channel and the reference voltage levels Vp and Vp_ are defined in the conversion control memory Conversion results may be in straight binary format
210. FFFF 1 0 Unipolar ZERO 0000 800000 FSR 0000 000000 t Independent of SD16OSRx and SD16XOSR settings SD16LSBACC 0 a aS Note Offset Measurements and Data Format Any offset measurement done either externally or using the internal differential pair A7 would be appropriate only when the channel is operating under bipolar mode with SD16UNI 0 a eee SD16_A 24 11 SD16_A Operation Figure 24 6 shows the relationship between the full scale input voltage range from Vesr to Vfspr and the conversion result The data formats are illustrated Figure 24 6 Input Voltage vs Digital Output Bipolar Output Offset Binary Bipolar Output 2 s complement Unipolar Output ESDISMEMS A SD16MEMx A SD16MEMx a a EA 7FFFR FFFFR i l i Input Input Voltage Voltage l i gt t gt VFSR VFSR V FSR Input Voltage l VFSR V FSR 24 2 9 Conversion Modes The SD16_A module can be configured for two modes of operation listed in Table 24 4 The SD16SNGL bit selects the conversion mode Table 24 4 Conversion Mode Summary SD16SNGL Mode Operation 1 Single conversion The channel is converted once 0 Continuous conversion The channel is converted continuously Single Conversion Setting the SD16SC bit of the channel initiates one conversion on that channel when SD16SNGL 1 The SD16SC bit will automatically be cleared after conversion completion Clearing SD16SC
211. General Purpose Opamp Mode In this mode the feedback resistor ladder is isolated from the OAx and the OAXxCTLO bits define the signal routing The OAx inputs are selected with the OAPx and OANx bits The OAx output is connected to the ADC12 input channel as selected by the OAxCTLO bits Unity Gain Mode for Differential Amplifier Unity Gain Mode 18 6 OA In this mode the output of the OAx is connected to the inverting input of the OAx providing a unity gain buffer The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANx bits are don t care The output of the OAx is also routed through the resistor ladder as part of the three opamp differential amplifier This mode is only for construction of the three opamp differential amplifier In this mode the output of the OAx is connected to the inverting input of the OAx providing a unity gain buffer The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANx bits are don t care The OAx output is connected to the ADC12 input channel as selected by the OAxCTLO bits Comparator Mode OA Operation In this mode the output of the OAx is isolated from the resistor ladder Rtop is connected to AVss and Rgottom is connected to AVcc when OARRIP 0 When OARRIP 1 the connection of the resistor ladder is reversed Ryop is connected to AVcc and Rgottom is conne
212. Group loc ID Identifier dst Instruction 15 12 1110 9 8 7 4 3 0 RRCM A 0 0 OJO n 1 O O O 1 0 0 dst RRCM A n Rdst RRAM A 0 0 0 0 n 1 O 1 0 1 0 0 dst RRAM A n Rdst RLAM A 0 0 OJO n 1 1 O O 1 0 0 dst RLAM A n Rdst RRUM A 0 0 OJO n 1 1 1 0 1 0 0 dst RRUM A n Rdst RRCM W 0 0 0 0O n 1 0 0O 0 1 0 1 dst RRCM W n Rast RRAM W 0 0 0 0 n 1 0 1 0 1 O 1 dst RRAM W n Rdst RLAM W 0 0 0 0 n 1 1 O O 1 O 1 dst RLAM W n Rdst RRUM W 0 0 0 0 n 1 1 1 0 1 O 1 dst RRUM W n Rdst 4 58 16 Bit MSP430X CPU Instruction Set Description Instruction Identifier dst Instruction 15 12 11 8 76 5 4 3 0 RETI o0ojojo 1 0 0 1 1 0 0 0 0 00 0 0 CALLA 0 0 0 1 0 0 1 11 0 0 0 dst CALLA Rast Colello loti I EY 0 1 dst CALLA x Rdst x 15 0 ojojo 1 0 0 1 1 0 110 dst CALLA Rast ojojo j 1 0 0 1 1 0 111 dst CALLA Rdst 0ojojo 1 0 0 1 1 1 0 0 0 amp abs 19 16 CALLA amp abs20 amp abs 15 0 ojojo 1 0 0 1 1 1 0 0 1 x 19 16 CALLA EDE x 15 0 CALLA x PC o0pjoj o 1 0 0 1 1 1 0 1 1 imm 19 16 CALLA imm20 imm 15 0 Reserved 0 0jo0 1 0 0 1 1 1 0 1 O x x x x Reserved 0 0 0 1 0 0 1 1 1 X X X x xXx x PUSHM A 0 0 0 1 0 1 0 0 n 1 dst PUSHM A n Rdst PUSHM W 0 0 0 1 0 1 0 1 n 1 dst PUSHM W n Rdst POPM A 0 0 0 1 0 1 1 0 n 1 dst n 1 POPM A n Rdst POPM W 0 0 O0 1 0 1 1 41 n 1 dst n 1 POPM W n Rdst 16 Bit MSP430X CP
213. HF mode XTS 1 XCAPx 00 The high speed crystal or resonator connects to XIN and XOUT and requires external capacitors on both terminals These capacitors should be sized according to the crystal or resonator specifications When LFXT1 is in HF mode the LFXT1Sx bits select the range of operation LFXT1 may be used with an external clock signal on the XIN pin in either LF or HF mode when LFXT1Sx 11 OSCOFF 0 and XCAPx 00 When used with an external signal the external frequency must meet the data sheet parameters for the chosen mode When the input frequency is below the specified lower limit the LFXT10F bit may be set preventing the CPU from being clocked with LFXT1CLK Software can disable LFXT1 by setting OSCOFF if LFXT1CLK does not source SMCLK or MCLK as shown in Figure 5 2 Figure 5 2 Off Signals for the LFXT1 Oscillator XTS E ACLK_request OSCOFF MCLK_request CPUOFF 1 gt SELMO XSELM1 tr 7 ie XT2 SMCLK_request SCG1 SELS gt gt XT1 Off HH XT2 is an Internal Signal XT2 0 Devices without XT2 oscillator XT2 1 Devices with XT2 oscillator Note LFXT1 Oscillator Characteristics Low frequency crystals often require hundreds of milliseconds to start up depending on the crystal Ultralow power oscillators such as the LFXT1 in LF mode should be guarded from noise coupling from other sources The c
214. I 0 gt TONI 3 30 RISC 16 Bit CPU CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Clear carry bit CLRC 0 gt C BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter RISC 16 Bit CPU 3 31 Instruction Set CLAN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLAN 0 gt N or NOT src AND dst gt dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Resetto 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 3 32 RISC 16 Bit CPU CLRZ Syntax Operation Emulation Description
215. ISTEN bit selects loopback mode 0 Disabled 1 Enabled UCAxTXD is internally fed back to the receiver Framing error flag 0 No error 1 Character received with low stop bit Overrun error flag This bit is set when a character is transferred into UCAxRXBUF before the previous character was read UCOE is cleared automatically when UCxRXBUF is read and must not be cleared by software Otherwise it will not function correctly 0 No error 1 Overrun error occurred Parity error flag When UCPEN 0 UCPE is read as 0 0 No error 1 Character received with parity error Break detect flag 0 No break condition 1 Break condition occurred Receive error flag This bit indicates a character was received with error s When UCRXERR 1 on or more error flags UCFE UCPE UCOE is also set UCRXERR is cleared when UCAxRXBUF is read 0 No receive errors detected 1 Receive error detected Address received in address bit multiprocessor mode 0 Received character is data 1 Received character is an address Idle line detected in idle line multiprocessor mode 0 No idle line detected 1 Idle line detected USCI busy This bit indicates if a transmit or receive operation is in progress 0 USCI inactive 1 USCI transmitting or receiving Universal Serial Communication Interface UART Mode 15 31 USCI Registers UART Mode UCAxRXBUF USCI_Ax Receive Buffer Register 7 6 5 4 3 2 1 0 r r r r r r r r UCRXBUFx Bits The receive data buffer is user
216. IVx Bits 15 0 3 ro rO r 0 r 0 r 0 ro Timer_A Interrupt Vector value Interrupt TAIV Contents Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TACCR1 CCIFG Highest 04h Capture compare 2t TACCR2 CCIFG 06h Reserved 08h Reserved OAh Timer overflow TAIFG OCh Reserved OEh Reserved Lowest t Not Implemented in MSP430x20xx devices Timer_A 12 23 12 24 Timer_A Chapter 13 Timer_B Timer_B is a 16 bit timer counter with multiple capture compare registers This chapter describes the operation of the Timer_B of the MSP430 2xx device family Topic Page 13 1 Timer Bi INntrOdUCtION reece ecto aora aie slats 13 2 13 2 Timer B Operation aaa aca 13 4 13 3 Timers B Registers occ a a e see 13 20 13 1 Timer_B Introduction 13 1 Timer_B Introduction Timer_B is a 16 bit timer counter with three or seven capture compare registers Timer_B can support multiple capture compares PWM outputs and interval timing Timer_B also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer_B features include 1 Asynchronous 16 bit timer counter with four operating modes and four selectable lengths Selectable and configurable clock source Three or seven configurable capture compare registers Configurable outputs with PWM capability Double buffered compare
217. If UCBORXIE is set the UCBORXIFG flag will not trigger a transfer No transfer is triggered Devices with USCI_BO module A transfer is triggered when USCI_BO is ready to transmit new data UCBOTXIFG is automatically reset when the transfer starts If UCBOTXIE is set the UCBOTXIFG flag will not trigger a transfer DMA Controller 6 13 DMA Operation Table 6 2 DMA Trigger Operation continued DMAxTSELx Operation 1110 1111 A transfer is triggered when the DMAxIFG flag is set DMAOIFG triggers channel 1 DMA1IFG triggers channel 2 and DMA2IFG triggers channel 0 None of the DMAxIFG flags are automatically reset when the transfer starts A transfer is triggered by the external trigger DMAEO 6 2 4 Stopping DMA Transfers There are two ways to stop DMA transfers in progress _j A single block or burst block transfer may be stopped with an NMI interrupt if the ENNMI bit is set in register DMACTL1 _j A burst block transfer may be stopped by clearing the DMAEN bit 6 2 5 DMA Channel Priorities 6 14 The default DMA channel priorities are DMAO DMA1 DMAZ2 If two or three triggers happen simultaneously or are pending the channel with the highest priority completes its transfer single block or burst block transfer first then the second priority channel then the third priority channel Transfers in progress are not halted if a higher priority channel is triggered The higher priority channel waits until the trans
218. Interrupt disabled 1 Interrupt enabled USCI_BO receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled These bits may be used by other modules see the device specific data sheet IFG2 Interrupt Flag Register 2 UCBO TXIFG UCBO RXIFG 7 Bits 7 4 Bit 3 Bit 2 Bits 6 5 4 3 2 1 0 UCBO UCBO TXIFG RXIFG rw 0 rw 1 These bits may be used by other modules see the device specific data sheet USCI_BO transmit interrupt flag UCBOTXIFG is set when UCBOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_BO receive interrupt flag UCBORXIFG is set when UCBORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending These bits may be used by other modules see the device specific data sheet Universal Serial Communication Interface C Mode 17 33 USCI Registers C Mode UC1IE USCI_B1 Interrupt Enable Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused 7 4 UCB1TXIE Bit3 USCI_B1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled UCBIRXIE Bit 2 USCI_B1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled Bits These bits may be used by other USCI modules see the device specific data 1 0 sheet UC1IFG USCI_B1 Interrupt Flag Register 7 6 5 4 3 2 1 0 ES EE TXIFG RXIFG rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 Unused Bits Unused 7 4 UCB1 Bit 3 USCI_B1 transmit interrupt flag UCB1TXIFG is set
219. Invert destination Invert destination INV dst INV B dst NOT dst gt dst XOR OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV OOAEh R5 R5 OOOAEh INV R5 Invert R5 R5 OFF51h INC R5 R5 is now negated R5 O0FF52h Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO OAEh INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LEO is negated MEM LEO 052h RISC 16 Bit CPU 3 43 Instruction Set JC JHS Syntax Operation Description Status Bits Example Example Jump if carry set Jump if higher or same JC label JHS label If C 1 PC 2 x offset gt PC If C 0 execute following instruction The status register carry bit C is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is reset the next instruction following the jump is executed JC jump if carry higher or same is used for the comparison of unsigned numbers 0 to 65536 Status b
220. KB memory Y MSP430 instruction with symbolic mode addressing memory above the lower 64 KB memory Y MSP430X instruction with symbolic mode Symbolic Mode in Lower 64 KB If the PC points to an address in the lower 64 KB of the memory range the calculated memory address bits 19 16 are cleared after the addition of the PC and the signed 16 bit index This means the calculated memory address is always located in the lower 64 KB and does not overflow or underflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 19 Symbolic Mode Running in Lower 64 KB Lower 64 KB PC 19 16 0 lt gt 19 1615 0 FFFFF Program counter PC 16 bit signed 16 bit byte inde O PC index 10000 OFFFF 16 bit signed add PC 19 0 Lower 64 KB Memory address Operation The signed 16 bit index in the next word after the instruction is added temporarily to the PC The resulting bits 19 16 are cleared giving a truncated 16 bit memory address which points to an operand address in the range 00000h to OFFFFh The operand is the content of the addressed memory location Length Two or three words Comment Valid for source and destination The assembler calculates the PC index and inserts it Example ADD B EDE TONI 16 Bit MSP430X CPU 4 23 CPU Registers 4 24 The previous instruc
221. MIES WDTNMI Bits 15 8 Bit 7 Bit 6 Bit 5 WDTTMSEL Bit 4 WDTCNTCL Bit 3 WDTSSEL WDTISx 10 8 Bit 2 Bits rw 0 rw 0 Watchdog timer password Always read as 069h Must be written as O5Ah or a PUC will be generated Watchdog timer hold This bit stops the watchdog timer Setting WDTHOLD 1 when the WDT is not in use conserves power 0 Watchdog timer is not stopped 1 Watchdog timer is stopped Watchdog timer NMI edge select This bit selects the interrupt edge for the NMI interrupt when WDTNMI 1 Modifying this bit can trigger an NMI Modify this bit when WDTIE 0 to avoid triggering an accidental NMI 0 NMI on rising edge 1 NMI on falling edge Watchdog timer NMI select This bit selects the function for the RST NMI pin 0 Reset function 1 NMI function Watchdog timer mode select 0 Watchdog mode 1 Interval timer mode Watchdog timer counter clear Setting WDTCNTCL 1 clears the count value to 0000h WDTCNTCL is automatically reset 0 No action 1 WDTCNT 0000h Watchdog timer clock source select 0 SMCLK 1 ACLK Watchdog timer interval select These bits select the watchdog timer interval to set the WDTIFG flag and or generate a PUC 00 Watchdog clock source 32768 01 Watchdog clock source 8192 10 Watchdog clock source 512 11 Watchdog clock source 64 Watchdog Timer Watchdog Timer Registers 1E1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 NMIIE WDTI
222. MSB first format Eee eee eee nee Universal Serial Communication Interface SPI Mode 16 3 3 Master Mode USCI Operation SPI Mode Figure 16 2 USCI Master and External Slave Receive Buffer UCxRXBUF Receive Shift Register MSP430 USCI COMMON SPI MASTER SCLK Figure 16 2 shows the USCI as a master in both 3 pin and 4 pin configurations The USCI initiates data transfer when data is moved to the transmit data buffer UCxTXBUF The UCxTXBUF data is moved to the TX shift register when the TX shift register is empty initiating data transfer on UCxSIMO starting with either the most significant or least significant bit depending on the UCMSB setting Data on UCxSOMI is shifted into the receive shift register on the opposite clock edge When the character is received the receive data is moved from the RX shift register to the received data buffer UCxRXBUF and the receive interrupt flag UCxRXIFG is set indicating the RX TX operation is complete A set transmit interrupt flag UCxTXIFG indicates that data has moved from UCxTXBUF to the TX shift register and UCxTXBUF is ready for new data It does not indicate RX TX completion To receive data into the USCI in master mode data must be written to UCxTXBUF because receive and transmit operations operate concurrently Universal Serial Communication Interface SPI Mode 16 7 USCI Operation SPI Mode Four Pin SPI Master Mode In 4 pin master mode UCxSTE
223. O is negated MEM LEO 052h 16 Bit MSP430X CPU 4 83 MSP430 Instructions Jc JHS Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if carry Jump if Higher or Same unsigned JC label JHS label lfC 1 PC 2 x Offset gt PC If C 0 execute the following instruction The carry bit C in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If C is reset the instruction after the jump is executed JC is used for the test of the carry bit C JHS is used for the comparison of unsigned numbers Status bits are not affected OSCOFF CPUOFF and GIE are not affected The state of the port 1 pin P1IN 1 bit defines the program flow BITB 2 amp P1IN Port 1 bit 1 set Bit gt C JC Label1 Yes proceed at Label1 No continue If R5 gt R6 unsigned the program continues at Label2 CMP R6 R5 Is R5 gt R6 Info to C JHS Label2 Yes C 1 No R5 lt R6 Continue If R5 gt 12345h unsigned operands the program continues at Label2 CMPA 12345h R5 Is R5 gt 12345h Info to C JHS Label2 Yes 12344h lt R5 lt F FFFFh C 1 No R5 lt 12345h Continue 4 84 16 Bit MSP430X CPU JEQ JZ Syntax Operation Description S
224. ODx x tpco MODx x tpco 1 Because foco is lower than the effective frequency and fpco 1 is higher than the effective frequency the error of the effective frequency integrates to zero It does not accumulate The error of the effective frequency is zero every 32 DCOCLK cycles Figure 5 6 illustrates the modulator operation The modulator settings and DCO control are configured with software The DCOCLK can be compared to a stable frequency of known value and adjusted with the DCOx RSELx and MODx bits See http www msp430 com for application notes and example code on configuring the DCO Figure 5 6 Modulator Patterns MODx Lower DCO Tap Frequency fpco Upper DCO Tap Frequency fpco 1 Basic Clock Module 5 9 Basic Clock Module Operation 5 2 7 Basic Clock Module Fail Safe Operation The basic clock module incorporates an oscillator fault fail safe feature This feature detects an oscillator fault for LFXT1 and XT2 as shown in Figure 5 7 The available fault conditions are UY Low frequency oscillator fault LFXT10F for LFXT1 in LF mode UY High frequency oscillator fault LFXT1OF for LFXT1 in HF mode UY High frequency oscillator fault XT20F for XT2 The crystal oscillator fault bits LFXT1OF and XT2OF are set if the corresponding crystal oscillator is turned on and not operating properly The fault bits remain set as long as the fault condition exists and are automatically cleared if the enabled oscillators function nor
225. P4 SP3 SP The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 4 8 16 Bit MSP430X CPU CPU Registers 4 3 3 Status Register SR The 16 bit status register SR R2 used as a source or destination register can only be used in register mode addressed with word instructions The remaining combinations of addressing modes are used to support the constant generator Figure 4 9 shows the SR bits Do not write 20 bit values to the SR Unpredictable operation can result Figure 4 9 Status Register Bits 15 9 8 7 0 OSC CPU rw 0 Table 4 1 describes the status register bits Table 4 1 Description of Status Register Bits Bit Description Reserved Reserved V Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range ADD B ADDX B A Set when ADDC B ADDCX B A positive positive negative ADDA negative negative positive otherwise reset SUB B SUBX B A Set when SUBC B SUBCX B A positive negative negative SUBA CMP B negative positive positive CMPX B A CMPA otherwise reset SCG1 System clock generator 1 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK SCGO System clock generator 0 This bit when set turns off the FLL loop control OSCOFF
226. R Read UCBORXBUF clears UCBORXIFG RETI USCIAO RX_ISR Read UCAORXBUF clears UCAORXIFG RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIAO TX_USCIBO_TX_ISR BIT B UCAOTXIFG amp IFG2 USCI_AO Transmit Interrupt JNZ USCIAO_TX_ISR USCIBO_TX_ ISR Write UCBOTXBUF clears UCBOTXIFG RETI USCIAO_TX_ISR Write UCAOTXBUF clears UCAOTXIFG RETI Universal Serial Communication Interface UART Mode USCI Registers UART Mode 15 4 USCI Registers UART Mode The USCI registers applicable in UART mode are listed in Table 15 6 and Table 15 7 Table 15 6 USCI_AO Control and Status Registers Register Short Form Register Type Address Initial State USCI_AO control register O UCAOCTLO Read write 060h Reset with PUC USCI_AO control register 1 UCAOCTL1 Read write 061h 001h with PUC USCI_AO Baud rate control register 0 UCAOBRO Read write 062h Reset with PUC USCI_AO baud rate control register 1 UCAOBR1 Read write 063h Reset with PUC USCI_AO modulation control register UCAOMCTL Read write 064h Reset with PUC USCI_AO status register UCAOSTAT Read write 065h Reset with PUC USCI_AO receive buffer register UCAORXBUF Read 066h Reset with PUC USCI_AO transmit buffer register UCAOTXBUF Read write 067h Reset with PUC USCI_AO Auto baud control register UCAOABCTL Read write 05Dh Reset with PUC USCI_AO IrDA
227. RESLO Read write 013Ah Undefined Result high word RESHI Read write 013Ch Undefined Sum extension register SUMEXT Read 013Eh Undefined Hardware Multiplier 11 7 11 8 Hardware Multiplier Chapter 12 Timer_A Timer_A is a 16 bit timer counter with multiple capture compare registers This chapter describes the operation of the Timer_A of the MSP430 2xx device family Topic Page 12 1 Timer A IntrOodUCtION secs cere aras afana 12 2 12 22 Timer A Operation adas aia ato eat 12 4 12 3 Mimer A Registers occ e cere eee 12 19 12 4 Timer_A Introduction 12 1 Timer_A Introduction 12 2 Timer_A Timer_A is a 16 bit timer counter with three capture compare registers Timer_A can support multiple capture compares PWM outputs and interval timing Timer_A also has extensive interrupt capabilities Interrupts may be generated from the counter on overflow conditions and from each of the capture compare registers Timer_A features include Asynchronous 16 bit timer counter with four operating modes Selectable and configurable clock source Two or three configurable capture compare registers Configurable outputs with PWM capability Asynchronous input and output latching Lj E E E E m Interrupt vector register for fast decoding of all Timer_A interrupts The block diagram of Timer_A is shown in Figure 12 1 D eeN G a a a S E Note Use of the Word Count Countis used throughout this chapter It means the cou
228. Rx bits to provide programmable gain amplifier functionality Table 18 1 shows the OA output and feedback routing configurations When OAFCx 0 the OA is in general purpose mode and feedback is achieved externally to the device When OAFCx gt 0 and when OAADCx 00 or 11 the output of the OA is kept internal to the device When OAFCx gt 0 and OAADCx 01 or 10 the OA output is routed both internally and externally Table 18 1 0A Output Configurations OAFCx OAADCx OA Output and Feedback Routing 0 x0 OAxOUT connected to external pins and ADC input A1 A3 or A5 0 xi OAxOUT connected to external pins and ADC input A12 A13 or A14 gt 0 00 OAxOUT used for internal routing only gt 0 01 OAxOUT connected to external pins and ADC input A12 A13 or A14 gt 0 10 OAxOUT connected to external pins and ADC input A1 A3 or A5 gt 0 11 OAxOUT connected internally to ADC input A12 A13 or A14 External A12 A13 or A14 pin connections are disconnected from the ADC OA 18 5 OA Operation 18 2 4 OA Configurations The OA can be configured for different amplifier functions with the OAFCx bits as listed in Table 18 2 Table 18 2 OA Mode Select OAFCx OA Mode 000 General purpose opamp 001 Unity gain buffer for three opamp differential amplifier 010 Unity gain buffer 011 Comparator 100 Non inverting PGA amplifier 101 Cascaded non inverting PGA amplifier 110 Inverting PGA amplifier 111 Differential amplifier
229. S The SVS is implemented in selected MSP430x2xx devices Topic Page ARES AS Intro UC o o aio alot 9 2 9 2 SVS Operation lata a 9 4 9 3 ESVS ROI e a o lara ne 9 7 9 1 SVS Introduction 9 1 SVS Introduction The supply voltage supervisor SVS is used to monitor the AVcc supply voltage or an external voltage The SVS can be configured to set a flag or generate a POR reset when the supply voltage or external voltage drops below a user selected threshold The SVS features include AVcc monitoring Selectable generation of POR Output of SVS comparator accessible by software Low voltage condition latched and accessible by software 14 selectable threshold levels Coouvuo Oo External channel to monitor external voltage The SVS block diagram is shown in Figure 9 1 9 2 Supply Voltage Supervisor SVS Introduction Figure 9 1 SVS Block Diagram VCC Brownout Reset Ad SVSIN gt o SVS_POR mOn Dp He tReset 50us e SVSOUT gt G IS Y Set SVSFG SVSCTL Bits Supply Voltage Supervisor 9 3 SVS Operation 9 2 SVS Operation The SVS detects if the AVcc voltage drops below a selectable level It can be configured to provide a POR or set a flag when a low voltage condition occurs The SVS is disabled after a brownout reset to conserve current consumption 9 2 1 Configuring
230. SB 1 gt LSB 1 gt LSB gt C The destination operand is shifted right by one two three or four bit positions as shown in Figure 4 50 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit The word instruction RRCM W clears the bits Rdst 19 16 Note This instruction does not use the extension word N Set if result is negative A Rdst 19 1 reset if Rdst 19 0 W Rdst 15 1 reset if Rdst 15 0 Z Set if result is zero reset otherwise C Loaded from the LSB n 1 LSB 1 n 2 LSB 2 n 3 or LSB 3 n 4 V Reset OSCOFF CPUOFF and GIE are not affected The address word in R5 is shifted right by three positions The MSB 2 is loaded with 1 SETC Prepare carry for MSB 2 RRCM A 3 R5 R5 R5 3 20000h The word in R6 is shifted right by two positions The MSB is loaded with the LSB The MSB 1 is loaded with the contents of the carry flag RRCM W 2 R6 R6 R6 2 R6 19 16 0 Figure 4 50 Rotate Right Through Carry RRCM W and RRCM A 19 16 15 0 a 19 0 HT 16 Bit MSP430X CPU 4 141 Extended Instructions RRCX A Rotate Right through carry the 20 bit operand RRCX W Rotate Right through carry the 16 bit operand RRCX B Rotate Right through carry the 8 bit operand Syntax RRCX A Rdst RRCX W Rdst RRCX Rdst RRCX B Rdst RRCX A dst RRCX W dst or RRCX dst RRCX B dst Operation C gt MSB gt MSB 1 gt LSB 1 gt LSB gt C Descr
231. SCLREL Bit 7 USI16B Bit 6 USIIFGCC Bit5 USICNTx Bits 5 USIIFGCC 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SCL release The SCL line is released from low to idle USISCLREL is cleared if a START condition is detected 0 SCL line is held low if USIIFG is set 1 SCL line is released 16 bit shift register enable 0 8 bit shift register mode Low byte register USISRL is used 1 16 bit shift register mode Both high and low byte registers USISRL and USISRH are used USISR addresses all 16 bits simultaneously USI interrupt flag clear control When USIIFGCC 1 the USIIFG will not be cleared automatically when USICNTx is written with a value gt 0 0 USIIFG automatically cleared on USICNTx update 1 USIIFG is not cleared automatically USI bit count The USICNTx bits set the number of bits to be received or transmitted Universal Serial Interface 14 17 USI Registers USISRL USI Low Byte Shift Register 7 6 5 4 3 2 1 0 USISRLx rw rw rw rw rw rw rw rw USISRLx Bits Contents of the USI low byte shift register 7 0 USISRH USI High Byte Shift Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw USISRHx Bits Contents of the USI high byte shift register Ignored when USI16B 0 7 0 14 18 Universal Serial Interface Chapter 15 Universal Serial Communication Interface UART Mode The universal serial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses
232. SIPE6 and USIPE7 must be set to enable the SCL and SDA port functions To configure the USI module as an 12C master the USIMST bit must be set In master mode clocks are generated by the USI module and output to the SCL line while USIIFG 0 When USIIFG 1 the SCL will stop at the idle or high level Multi master operation is supported as described in the Arbitration section The master supports slaves that are holding the SCL line low only when USIDIVx gt 0 When USIDIVx is set to 1 clock division USIDIVx 0 connected slaves must not hold the SCL line low during data transmission Otherwise the communication may fail To configure the USI module as an 12C slave the USIMST bit must be cleared In slave mode SCL is held low if USIIFG 1 USISTTIFG 1 or if USICNTx 0 USISTTIFG must be cleared by software after the slave is setup and ready to receive the slave address from a master In transmitter mode data is first loaded into USISRL The output is enabled by setting USIOE and the transmission is started by writing 8 into USICNTx This clears USIIFG and SCL is generated in master mode or released from being held low in slave mode After the transmission of all 8 bits USIIFG is set and the clock signal on SCL is stopped in master mode or held low at the next low phase in slave mode To receive the I2C acknowledgement bit the USIOE bit is cleared with software and USICNTx is loaded with 1 This clears USIIFG and one bit is re
233. SR 64 LSBACC 0 SD16UNI 0 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 98 7 6 5 4 3 2 OSR 64 LSBACC 1 SD16UNI 0 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14113 12 11 10 9 8 7 6 5 41 3 2 OSR 32 LSBACC x SD16UNI 1 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 113 12 111 10 9 87 16 5 4 3 2 OSR 32 LSBACC x SD16UNI 0 y 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 113 12 11 10 9 87 16 5 4 3 2 24 10 SD16_A SD16_A Operation 24 2 8 Conversion Memory Register SD16MEMO The SD16MEMO register is associated with the SD16_A channel Conversion results are moved to the SD16MEMO register with each decimation step of the digital filter The SD16IFG bit is set when new data is written to SD16MEMO SD16IFG is automatically cleared when SD16MEMO is read by the CPU or may be cleared with software Output Data Format The output data format is configurable in two s complement offset binary or unipolar mode as shown in Table 24 3 The data format is selected by the SD16DF and SD16UNI bits Table 24 3 Data Format SD16UNI SD16DF Format Analog Input SD16MEMOt Digital Filter Output OSR 256 FSR FFFF FFFFFF Bipolar 0 0 Offset ZERO 8000 800000 Binary FSR 0000 000000 FSR 7FFF 7FFFFF Bipolar 0 1 Twos ZERO 0000 000000 compliment FSR 8000 800000 FSR FFFF FF
234. STTIFG USISTP and USIAL will be held in their reset state USISR and USICNTx are not clocked and their contents are not affected In I2C mode the SCL line is also released to the idle state by the USI hardware To activate USI port functionality the corresponding USIPEx bits in the USI control register must be set This will select the USI function for the pin and maintains the PxIN and PxIFG functions for the pin as well With this feature the port input levels can be read via the PxIN register by software and the incoming data stream can generate port interrupts on data transitions This is useful for example to generate a port interrupt on a START edge Universal Serial Interface 14 5 USI Operation 14 2 2 USI Clock Generation The USI clock generator contains a clock selection multiplexer a divider and the ability to select the clock polarity as shown in the block diagrams Figure 15 1 and Figure 14 2 The clock source can be selected from the internal clocks ACLK or SMCLK from an external clock SCLK as well as from the capture compare outputs of Timer_A In addition it is possible to clock the module by software using the USISWCLK bit when USISSELx 100 The USIDIVx bits can be used to divide the selected clock by a power of 2 up to 128 The generated clock USICLK is stopped when USIIFG 1 or when the module operates in slave mode The USICKPL bit is used to select the polarity of USICLK When USICKPL 0 the inactive l
235. Setting REFON 1 enables the internal reference When REF2_5V 1 the internal reference is 2 5 V When REF2_5V O the reference is 1 5 V The internal reference voltage may be used internally and when REFOUT 0 externally on pin VREF External references may be supplied for Vp and Vp_ through pins A4 and A3 respectively When external references are used or when Vcc is used as the reference the internal reference may be turned off to save power An external positive reference Verner can be buffered by setting SREFO 1 and SREF1 1 This allows using an external reference with a large internal resistance at the cost of the buffer current When REFBURST 1 the increased current consumption is limited to the sample and conversion period External storage capacitance is not required for the ADC10 reference source as on the ADC12 Internal Reference Low Power Features The ADC10 internal reference generator is designed for low power applications The reference generator includes a band gap voltage source and a separate buffer The current consumption of each is specified separately in the device specific data sheet When REFON 1 both are enabled and when REFON 0 both are disabled The total settling time when REFON becomes set is lt 30 us When REFON 1 but no conversion is active the buffer is automatically disabled and automatically re enabled when needed When the buffer is disabled it consumes no current In this case
236. Single Operand Instructions Operation Status Bits Mnemonic Operands n VNzc CALLA dst Call indirect to subroutine 20 bit address POPM A n Rdst Popn 20 bit registers from stack 1 16 POPM W n Rdst Pop n 16 bit registers from stack 1 16 PUSHM A n Rsrc Push n 20 bit registers to stack 1 16 PUSHM W n Rsrc Push n 16 bit registers to stack 1 16 PUSHX B A src Push 8 16 20 bit source to stack iS SS Su RRCM A n Rdst Rotate right Rdst n bits through carry 4 Qe 085 16 20 bit register RRUM A n Rdst Rotate right Rdst n bits unsigned 1 4 0 16 20 bit register RRAM A n Rdst Rotate right Rdst n bits arithmetically V4 2 E peir 16 20 bit register RLAM A n Rdst Rotate left Rdst n bits arithmetically la EF EZ 16 20 bit register RRCX B A dst Rotate right dst through carry 1 0 es 8 16 20 bit data RRUX B A dst Rotate right dst unsigned 8 16 20 bit 1 00 gt RRAX B A dst Rotate right dst arithmetically 1 Bete ORE ee SWPBX A dst Exchange low byte with high byte 1 SXTX A Rdst Bit7 gt bit8 bit19 1 oe ee SXTX A dst Bit7 gt bit8 MSB 1 AS 16 Bit MSP430X CPU 4 49 MSP430X Extended Instructions The three possible addressing mode combinations for format ll instructions are shown in Figure 4 31 Figure 4 31 Extended Format ll Instruction Format Op code 14 11 CODO EEE O Op code AAA A ee Op code dst 15 0
237. Size gt DMAxSZ DMAxSA gt T_SourceAdd DMALEVEL 1 DMAxDA gt T_DestAdd AND Trigger 0 DMAxSZ gt 0 Decrement DMAxSZ Modify T_SourceAdd Modify T_DestAdd DMAxSZ gt 0 AND a multiple of 4 words bytes were transferred DMAxSZ gt 0 DMADTx 6 7 AND DMAxSZ 0 2 x MCLK Burst State release CPU for 2xMCLK DMA Controller 6 11 DMA Operation 6 2 3 Initiating DMA Transfers Each DMA channel is independently configured for its trigger source with the DMAxTSELx bits as described in Table 6 2 The DMAxTSELx bits should be modified only when the DMACTLx DMAEN bit is O Otherwise unpredictable DMA triggers may occur When selecting the trigger the trigger must not have already occurred or the transfer will not take place For example if the TACCR2 CCIFG bit is selected as a trigger and it is already set no transfer will occur until the next time the TACCR2 CCIFG bit is set Edge Sensitive Triggers When DMALEVEL 0 edge sensitive triggers are used and the rising edge of the trigger signal initiates the transfer In single transfer mode each transfer requires its own trigger When using block or burst block modes only one trigger is required to initiate the block or burst block transfer Level Sensitive Triggers When DMALEVEL 1 level sensitive triggers are used For proper operation level sensitive triggers can only be used when external trigger DMAEO is selected as the trigg
238. Table 6 3 Table 6 3 Maximum Single Transfer DMA Cycle Time CPU Operating Mode Clock Source Maximum DMA Cycle Time _ Active mode MCLK DCOCLK 4 MCLK cycles Active mode MCLK LFXT1CLK 4 MCLK cycles Low power mode LPMO 1 MCLK DCOCLK 5 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 5 MCLK cycles 6 ust Low power mode LPMO0O 1 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM3 MCLK LFXT1CLK 5 MCLK cycles Low power mode LPM4 MCLK LFXT1CLK 5 MCLK cycles 6 ust t The additional 6 us are needed to start the DCOCLK It is the t LPMx Parameter in the data sheet DMA Controller 6 15 DMA Operation 6 2 7 Using DMA with System Interrupts DMA transfers are not interruptible by system interrupts System interrupts remain pending until the completion of the transfer NMI interrupts can interrupt the DMA controller if the ENNMI bit is set System interrupt service routines are interrupted by DMA transfers If an interrupt service routine or other routine must execute with no interruptions the DMA controller should be disabled prior to executing the routine 6 2 8 DMA Controller Interrupts Each DMA channel has its own DMAIFG flag Each DMAIFG flag is set in any mode when the corresponding DMAxSZ register counts to zero If the corresponding DMAIE and GIE bits are set an interrupt request is generated All DMAIFG flags source only one DMA controller interrupt vector and on some devices the interrupt vector may be shared with other modules
239. The 20 bit value in R5 is decremented by 2 DECDA R5 Decrement R5 by two 16 Bit MSP430X CPU 4 163 Address Instructions INCDA Syntax Operation Emulation Example Status Bits Mode Bits Example Double increment 20 bit destination register INCDA Rdst dst 2 gt dst ADDA 2 Rdst The destination register is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if Rdst contained OFFFFEh reset otherwise Set if Rdst contained OFFFEh reset otherwise Set if Rdst contained OFEh reset otherwise C Set if Rdst contained OFFFFEh or OFFFFFh reset otherwise Set if Rdst contained OFFFEh or OFFFFh reset otherwise Set if Rdst contained OFEh or OFFh reset otherwise V Set if Rdst contained O7FFFEh or O7FFFFh reset otherwise Set if Rdst contained O7FFEh or 07FFFh reset otherwise Set if Rdst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The 20 bit value in R5 is incremented by 2 INCDA R5 Increment R5 by two 4 164 16 Bit MSP430X CPU MOVA Syntax Operation Description Status Bits Mode Bits Examples Address Instructions Move the 20 bit source to the 20 bit destination MOVA Rsrc Rdst MOVA imm20 Rdst MOVA z16 Rsrc Rdst MOVA EDE Rdst MOVA amp abs20 Rdst MOVA O Rsrc Rdst MOVA O Rsrc Rdst MOVA Rsrc z16 Rdst MOVA Rsrc amp abs20 src gt Rast Rsrc gt dst The 20 bit source operand is moved to th
240. U 4 59 MSP430 Instructions 4 6 2 MSP430 Instructions The MSP430 instructions are listed and described on the following pages 4 60 16 Bit MSP430X CPU ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C gt dst ADDC 0 dst ADDC B_ 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD 16 Bit MSP430X CPU 4 61 MSP430 Instructions ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Example Add source word to destination word Add source byte to destination byte ADD src dst or ADD W src dst ADD B src dst src dst gt
241. U CPU Registers 3 2 2 Stack Pointer SP The stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts lt uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 3 3 shows the SP The SP is initialized into RAM by the user and is aligned to even addresses Figure 3 4 shows stack usage Figure 3 3 Stack Pointer 15 Lees Stack Pointer Bits 15 to 1 I cae MOV 2 SP R6 Item 12 gt R6 MOV R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h onto TOS POP R8 R8 0123h Figure 3 4 Stack Usage Address PUSH 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 SP Oxxxh 6 Oxxxh 8 The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 3 5 Figure 3 5 PUSH SP POP SP Sequence PUSH SP POP SP SPold SP SP4 SP2 SP4 The stack pointer is changed after The stack pointer is not changed after a POP SP a PUSH SP instruction instruction The POP SP instruction places SP1 into the stack pointer SP SP2 SP1 RISC 16 Bit CPU 3 5 CPU Registers 3 2 3 Status Register SR The status register SR R2 used as a source or destination register can be used in the register mode only addressed with word instructions The remain ing combinations of addressing modes are used to support the constant gen erator Figure 3 6 shows the SR
242. UC MCLK and SMCLK are sourced from DCOCLK at 1 1 MHz see the device specific data sheet for parameters and ACLK is sourced from LFXT1CLK in LF mode with an internal load capacitance of 6pF Status register control bits SCGO SCG1 OSCOFF and CPUOFF configure the MSP430 operating modes and enable or disable portions of the basic clock module See Chapter System Resets Interrupts and Operating Modes The DCOCTL BCSCTL1 BCSCTL2 and BCSCTL3 registers configure the basic clock module The basic clock module can be configured or reconfigured by software at any time during program execution for example BIS B RSEL2 RSEL1 RSELO amp BCSCTL1 Select range 7 BIS B DCO2 DCO1 DCO0 amp DCOCTL Select max DCO tap Basic Clock Module Features for Low Power Applications Conflicting requirements typically exist in battery powered applications Y Low clock frequency for energy conservation and time keeping Y High clock frequency for fast reaction to events and fast burst processing capability 3 Clock stability over operating temperature and supply voltage The basic clock module addresses the above conflicting requirements by allowing the user to select from the three available clock signals ACLK MCLK and SMCLK For optimal low power performance ACLK can be sourced from a low power 32 768 Hz watch crystal providing a stable time base for the system and low power stand by operation or from the internal low frequency oscil
243. VS will not flag a low voltage condition or reset the device and the SVSON bit is cleared Software can test the SVSON bit to determine when the delay has elapsed and the SVS is monitoring the voltage properly Writing to SVSCTL while SVSON 0 will abort the SVS automatic settling delay tysyson and switch the SVS to active mode immediately In doing so the SVS circuitry might not be settled resulting in unpredictable behavior When the VLDx bits are changed from any non zero value to any other non zero value the circuitry requires the time tsettle to settle The settling time tsettle is a maximum of 12 us See the device specific data sheet There is no automatic delay implemented that prevents SVSFG to be set or to prevent a reset of the device The recommended flow to switch between levels is shown in the following code Enable SVS for the first time MOV B 080h amp SVSCTL Level 2 8V do not cause POR Change SVS level MOV B 000h amp SVSCTL Temporarily disable SVS MOV B 018h amp SVSCTL Level 1 9V cause POR Supply Voltage Supervisor 9 5 SVS Operation 9 2 4 SVS Operating Range Each SVS level has hysteresis to reduce sensitivity to small supply voltage changes when AVcc is close to the threshold The SVS operation and SVS Brownout interoperation are shown in Figure 9 2 Figure 9 2 Operating Levels for SVS and Brownout Reset Circuit Software Sets VLD gt 0 Aoc SVS_IT svSstart Sta
244. Watchdog timer interrupt flag In watchdog mode WDTIFG remains set until reset by software In interval mode WDTIFG is reset automatically by servicing the interrupt or can be reset by software Because other bits in IFG1 may be used for other modules it is recommended to clear WDTIFG by using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 No interrupt pending 1 Interrupt pending Watchdog Timer Chapter 11 Hardware Multiplier This chapter describes the hardware multiplier The hardware multiplier is implemented in some MSP430x2xx devices Topic Page 11 1 Hardware Multiplier Introduction oooooooooommmoo 11 2 11 2 Hardware Multiplier Operation 0 cece eee eee 11 3 11 3 Hardware Multiplier Registers ooooooooccornmmmm o 11 7 Hardware Multiplier Introduction 11 1 Hardware Multiplier Introduction The hardware multiplier is a peripheral and is not part of the MSP430 CPU This means its activities do not interfere with the CPU activities The multiplier registers are peripheral registers that are loaded and read with CPU instructions The hardware multiplier supports Unsigned multiply Signed multiply Signed multiply accumulate E 0 _j Unsigned multiply accumulate E 0 16x16 bits 16x 8 bits 8x 16 bits 8x 8 bits The hardware multiplier block diagram is shown in Figure 11 1 Figure 11 1 Hardware Multiplier Block Diagram 15
245. X CPU 4 149 Extended Instructions Figure 4 56 Swap Bytes SWPBX A In Memory Before SWPBX A 31 20 19 16 15 gt gt After SWPBX A 31 20 19 16 15 gt N N o o o Figure 4 57 Swap Bytes SWPBX W Register Mode Before SWPBX 19 16 15 8 After SWPBX 19 16 15 8 Low Byte s N s o o o Figure 4 58 Swap Bytes SWPBX W In Memory Before SWPBX 15 8 High Byte After SWPBX 15 8 Low Byte 4 150 16 Bit MSP430X CPU 8 High Byte Low Byte 8 Low Byte High Byte Low Byte High Byte SXTX A SXTX W Syntax Operation Description Status Bits Mode Bits Example Extended Instructions Extend sign of lower byte to address word Extend sign of lower byte to word SXTX A dst SXTX W dst or SXTX dst dst 7 gt dst 15 8 Rdst 7 Rdst 19 8 Register Mode Register Mode The sign of the low byte of the operand Rdst 7 is extended into the bits Rdst 19 8 Other Modes SXTX A the sign of the low byte of the operand dst 7 is extended into dst 19 8 The bits dst 31 20 are cleared SXTX W the sign of the low byte of the operand dst 7 is extended into dst 15 8 N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The signed 8 bit data in EDE 7 0 is sign extended to 20 bits EDE 19 8 Bits 31 20 located in EDE 2 are cleared S
246. X src dst or ADDX W src dst ADDX B src dst src dst gt dst The source operand is added to the destination operand The previous contents of the destination are lost Both operands can be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Ten is added to the 20 bit pointer CNTR located in two words CNTR LSBs and CNTR 2 MSBs ADDX A H10 CNTR Add 10 to 20 bit pointer A table word 16 bit pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed on a carry ADDX W R5 R6 JC TONI Add table word to R6 Jump if carry No carry A table byte pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 ADDX B R5 R6 JNC TONI Add table byte to R6 R5 1 R6 OOOxxh Jump if no carry Carry occurred Note Use ADDA for the following two cases for better code density and execution ADDX A ADDX A Rsrc Rdst or imm20 Rdst 16 Bit MSP430X CPU ADDCX A ADDCX W ADDCX B Syntax Operation Description Status Bits Mode Bits Example E
247. XTX A amp EDE Sign extended EDE gt EDE 2 EDE Figure 4 59 Sign Extend SXTX A SXTX A Rdst 19 1615 87 6 0 SXTX A dst 31 2019 1615 87 6 0 16 Bit MSP430X CPU 4 151 Extended Instructions Figure 4 60 Sign Extend SXTX W SXTXLW Rdst 19 16 15 8 7 6 0 SXTXLW dst 15 8 4 152 16 Bit MSP430X CPU TSTX A TSTX W TSTX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Test destination address word Test destination word Test destination byte TSTX A dst TSTX dst or TST W dst TST B dst dst OFFFFFh 1 dst OFFFFh 1 dst OFFh 1 CMPX A 0 dst CMPX 0 dst CMPX B 0 dst The destination operand is compared with zero The status bits are set according to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected RAM byte LEO is tested PC is pointing to upper memory If it is negative continue at LEONEG if it is positive but not zero continue at LEOPOS TSTX B LEO Test LEO JN LEONEG LEO is negative JZ LEOZERO LEO is zero LEOPOS noo LEO is positive but not zero LEONEG LEO is negative LEOZERO LEO is zero 16 Bit MSP430X CPU 4 153 Extended Instructions XORX A XORX W XORX B Syntax Operation Description Status Bits
248. Z Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally Conditional jumps support program branching relative to the PC and do not affect the status bits The possible jump range is from 511 to 512 words relative to the PC value at the jump instruction The 10 bit program counter offset is treated as a signed 10 bit value that is doubled and added to the program counter PCnew PCold 2 PCoffset x 2 3 20 RISC 16 Bit CPU ADC W ADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry to destination Add carry to destination ADC dst or ADC W dst ADC B dst dst C gt dst ADDC 0 dst ADDC B_ 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if dst was incremented from OFFFFh to 0000 reset otherwise Set if dst was incremented from OFFh to 00 reset otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is added to a 32 bit counter pointed
249. _BO control register 1 UCBOCTL1 Read write 069h 001h with PUC USCI_BO bit rate control register O UCBOBRO Read write O6Ah Reset with PUC USCI_BO bit rate control register 1 UCBOBR1 Read write O6Bh Reset with PUC USCI_BO 12C interrupt enable register UCBOI2CIE Read write 06Ch Reset with PUC USCI_BO status register UCBOSTAT Read write 06Dh Reset with PUC USCI_BO receive buffer register UCBORXBUF Read O6Eh Reset with PUC USCI_BO transmit buffer register UCBOTXBUF Read write O6Fh Reset with PUC USCI_BO I2C own address register UCBOI2COA Read write 0118h Reset with PUC USCI_BO I2C slave address register UCBOI2CSA Read write 011Ah Reset with PUC SFR interrupt enable register 2 1E2 Read write 001h Reset with PUC SFR interrupt flag register 2 IFG2 Read write 003h O00Ah with PUC EE __ QKOK O0 qV O0_ER_ 5h e o 3 A O lt lt lt ON Note Modifying SFR bits To avoid modifying control bits of other modules it is recommended to set or clear the IEx and IFGx bits using BIS B or BIC B instructions rather than MOV B Or CLR B instructions Table 17 3 USCI_B1 Control and Status Registers Universal Serial Communication Interface C Mode Register Short Form Register Type Address Initial State USCI_B1 control register O UCB1CTLO Read write OD8h Reset with PUC USCI_B1 control register 1 UCB1CTL1 Read write OoD9h 001h with PUC USCI_B1 baud rate control register O UCB1BRO Read write ODAh Reset with PUC USCI_B1 baud rate
250. a 13 18 133 Timer BE Registers viii at ia 13 20 14 Universal Serial Interface 0 0c cece eee eee eens 14 1 14 1 USI Introduction 2 0 0 0 ene eet t nee neene 14 2 14 2 USI Operation vacios a aes ia Hera ae tity 14 5 14 2 1 USI Initialization 0 cence eens 14 5 14 2 2 USI Clock Generation 0 00 ccc eee eee 14 6 14 2 3 SP MOd6 3 25 fs d 5 ec Poaceae A a 14 6 14 24 126 MOG tc a A E E Ge ai 14 9 14 3 USHREGISIORS oidor a de AA eae 14 13 15 Universal Serial Communication Interface UART Mode 0200008 15 1 15 1 USCI Overview o o o oooccoc cece eect etn teen ee neeas 15 2 15 2 USCI Introduction UART Mode 0 ccc ccc tenes 15 3 15 3 USCI Operation UART Mode 0c cece teeta 15 5 15 3 1 USCI Initialization and Reset o oocoococooccnocnonnonoo no 15 5 15 3 2 Character Format o oooococcocnonnnn o 15 5 15 3 3 Asynchronous Communication Formats 0000 cece eee 15 6 15 3 4 Automatic Baud Rate Detection nannaa ccc ene 15 10 15 3 5 IrDA Encoding and Decoding 0c cece eet eee 15 12 15 3 6 Automatic Error Detection 0 c cee eee eens 15 13 15 3 7 USCI Receive Enable 0 ccc ccc eee ens 15 14 15 3 8 USCI Transmit Enable 0 00 ccc nes 15 15 15 3 9 UART Baud Rate Generation 0 0 0 c ccc ees 15 15 15 3 10 Setting a Baud Rate 0 2 tenes 15 18 15 3 11 Transmit Bit Timing
251. a different slave address may be written into UCBxl2CSA if desired If the slave does not acknowledge the transmitted data the not acknowledge interrupt flag UCNACKIFG is set The master must react with either a STOP condition or a repeated START condition If data was already written into UCBxTXBUF it will be discarded If this data should be transmitted after a repeated START it must be written into UCBxTXBUF again Any set UCTXSTT is discarded too To trigger a repeated start UCTXSTT needs to be set again Universal Serial Communication Interface C Mode 17 15 USCI Operation 2C Mode Figure 17 12 Successful transmission to a slave receiver Next transfer started with a repeated start condition Figure 17 12 illustrates the 12C master transmitter operation 12C Master Transmitter Mode S SLAW A DATA A DATA 1 UCTR 1 Transmitter 2 UCTXSTT 1 UCBxTXIFG 1 UCBxTXBUF discarded UCTXSTT 0 UCBxTXIFG 1 Bus stalled SCL held low until data available Write data to UCBxTXBUF UCTXSTT 0 UCTXSTP 0 UCTXSTP 1 UCBxTXIFG 0 1 er Janene 2 UCTXST 17 16 Not acknowledge received after slave address Not acknowledge received after a data byte Arbitration lost in slave address or data byte Arbitration lost and addressed as slave UCNACKIFG 1 UCBxTXIFG 0 UCBxTXBUF discarded UCTXSTP 1
252. a logic low The loss of arbitration is detected in the USI module by comparing the value presented to the bus and the value read from the bus If the values are not equal arbitration is lost and the arbitration lost flag USIAL is set This also clears the output enable bit USIOE and the USI module no longer drives the bus In this case user software must check the USIAL flag together with USIIFG and configure the USI to slave receiver when arbitration is lost The USIAL flag must be cleared by software To prevent other faster masters from generating clocks during the arbitration procedure SCL is held low if another master on the bus drives SCL low and USIIFG or USISTTIFG is set or if USICNTx 0 There is one interrupt vector associated with the USI module with two interrupt flags relevant for 12C operation USIIFG and USISTTIFG Each interrupt flag has its own interrupt enable bit USIIE and USISTTIE When an interrupt is enabled and the GIE bit is set a set interrupt flag will generate an interrupt request USIIFG is set when USICNTx becomes zero either by counting or by directly writing O to the USICNTx bits USIIFG is cleared by writing a value gt O to the USICNTx bits when USIIFGCC 0 or directly by software USISTTIFG is set when a START condition is detected The USISTTIFG flag must be cleared by software The reception of a STOP condition is indicated with the USISTP flag but there is no interrupt function associated with t
253. a no 7 20 7 1 Flash Memory Introduction 7 1 Flash Memory Introduction The MSP430 flash memory is bit byte and word addressable and programmable The flash memory module has an integrated controller that controls programming and erase operations The controller has four registers a timing generator and a voltage generator to supply program and erase voltages MSP430 flash memory features include Lj Internal programming voltage generation Bit byte or word programmable Ultralow power operation Segment erase and mass erase E E E 1 Marginal O and marginal 1 read mode optional please refer to device specific data sheet The block diagram of the flash memory and controller is shown in Figure 7 1 Note Minimum Vcc During Flash Write or Erase The minimum Vcc voltage during a flash write or erase operation is 2 2 V If Voc falls below 2 2 V during a write or erase the result of the write or erase will be unpredictable Figure 7 1 Flash Memory Module Block Diagram Enable Address Latch Flash Memory Array Timing Generator Enable Data Latch Programming Voltage Generator 7 2 Flash Memory Controller Flash Memory Segmentation 7 2 Flash Memory Segmentation MSP430 flash memory is partitioned into segments Single bits bytes or words can be written to flash memory but the segment is the smallest size of flash memory that can be erased The flash memory is
254. added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry to MSD The two digit decimal number contained in R5 is added to a four digit decimal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD B R5 0 R8 Add LSDs C DADC 1 R8 Add carry to MSDs 16 Bit MSP430X CPU 4 75 MSP430 Instructions DADD W DADD B Syntax Operation Description Status Bits Mode Bits Example Example Example Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADD src dst or DADD W src dst DADD B src dst src dst C gt dst decimally The source operand and the destination operand are treated as two B or four W binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous content of the destination is lost The result is not defined for non BCD numbers N Set if MSB of result is 1 word gt 7999h byte gt 79h reset if MSB is O Z Set if result is zero reset otherwise C Set if the BCD result is too large word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected Decimal 10 is added to the 16 bit BCD counte
255. address word instruction If the destination address is contained in a memory location X it is contained in two ascending words X LSBs and X 2 MSBs Two words on the stack are needed for the return address The return is made with the instruction RETA N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Examples for all addressing modes are given Immediate Mode Call a subroutine at label EXEC or call directly an address CALLA EXEC Start address EXEC CALLA 01AA04h Start address 01AA04h Symbolic Mode Call a subroutine at the 20 bit address contained in address es EXEC LSBs and EXEC 2 MSBs EXEC is located at the address PC X where X is within 32 K Indirect addressing CALLA EXEC Start address at EXEC z16 PC Absolute Mode Call a subroutine at the 20 bit address contained in absolute addresses EXEC LSBs and EXEC 2 MSBs Indirect addressing CALLA amp EXEC Start address at EXEC Register Mode Call a subroutine at the 20 bit address contained in register R5 Indirect R5 CALLA R5 Start address at R5 16 Bit MSP430X CPU 4 159 Address Instructions Indirect Mode Call a subroutine at the 20 bit address contained in the word pointed to by register R5 LSBs The MSBs have the address R5 2 Indi rect indirect R5 CALLA OR5 Start address at R5 Indirect Auto Increment Mode Call a subroutine at the 20 bit address con t
256. ained in the words pointed to by register R5 and increment the 20 bit address in R5 afterwards by 4 The next time the S W flow uses R5 as a pointer it can alter the program execution due to access to the next word address in the table pointed to by R5 Indirect indirect R5 CALLA R5 Start address at R5 R5 4 Indexed Mode Call a subroutine at the 20 bit address contained in the ad dress pointed to by register R5 X e g a table with addresses starting at X R5 X points to the LSBs R5 X 2 points to the MSBs of the word ad dress X is within R5 32 K Indirect indirect R5 X CALLA X R5 Start address at R5 X z16 R5 4 160 16 Bit MSP430X CPU CLRA Syntax Operation Emulation Description Status Bits Example Address Instructions Clear 20 bit destination register CLRA Rdst 0 gt Rast MOVA 0 Rdst The destination register is cleared Status bits are not affected The 20 bit value in R10 is cleared CLRA R10 0 gt R10 16 Bit MSP430X CPU 4 161 Address Instructions CMPA Compare the 20 bit source with a 20 bit destination register Syntax CMPA Rsrc Rdst CMPA imm20 Rdst Operation not src 1 Rdst or Rdst src Description The 20 bit source operand is subtracted from the 20 bit destination CPU register This is made by adding the 1 s complement of the source 1 to the destination register The result affects only the status bits Status Bits N Set if result is negative sr
257. al Communication Interface UART Mode 15 15 USCI Operation UART Mode Timing for each bit is shown in Figure 15 10 For each bit received a majority vote is taken to determine the bit value These samples occur at the N 2 1 2 N 2 and N 2 1 2 BRCLK periods where N is the number of BRCLKs per BITCLK Figure 15 10 BITCLK Baud Rate Timing with UCOS16 0 Majority Vote m NY y Bit Start l dy y A EA E E srek LI LI LI Counter N 2 N 2 1 N 2 2 S BITCLK 5 1 N 2 N 2 1 N 2 2 1 1 0 N2 N 21 INT N 2 m 0 ae NEVEN INT N 2 INT N 2 m 1 gt lt Bit Period 900 gt m corresponding modulation bit R Remainder from N 2 division Nopp INT N 2 R 1 gt i N 2 N 2 1 Modulation is based on the UCBRSx setting as shown in Table 15 2 A 1 in the table indicates that m 1 and the corresponding BITCLK period is one BRCLK period longer than a BITCLK period with m 0 The modulation wraps around after 8 bits but restarts with each new start bit Table 15 2 BITCLK Modulation Pattern Bit 0 UCBRSx Start Bit Bit 1 Bit2 Bit3 Bit4 0 NO oO FP WD O O0OoOo0OO0OOoOopo ss 2 2 2d 2 2 2 0 2 OOO O O 24 2322000 O O O O O O O 15 16 Universal Serial Communication Interface UART Mode Bit 5 A 2d 2 2 4 00 Bit 6 2 O O OOOO Bit 7 USCI Operation UART Mode Oversampling Baud Rate Generation The oversampling mode is selecte
258. al waveform may store the sinusoid values in a table The DMA controller can continuously and automatically transfer the values to the DAC12 at specific intervals creating the sinusoid with zero CPU execution The DAC12_xCTL DAC12IFG flag is automatically cleared when the DMA controller accesses the DAC12_xDAT register 6 2 12 Writing to Flash With the DMA Controller MSP430 devices with an integrated DMA controller can automatically move data to the Flash memory DMA transfers are done without CPU intervention and independent of any low power modes The DMA controller performs the move of the data word byte to the Flash The write timing control is done by the Flash controller Write transfers to the Flash memory succeed if the Flash controller set up is prior to the DMA transfer and if the Flash is not busy To set up the Flash controller for write accesses see Chapter 7 Flash Memory Controller 6 18 DMA Controller DMA Registers 6 3 DMA Registers The DMA registers are listed in Table 6 4 Table 6 4 DMA Registers Register Short Form Register Type Address Initial State DMA control O DMACTLO Read write 0122h Reset with POR DMA control 1 DMACTL1 Read write 0124h Reset with POR DMA interrupt vector DMAIV Read only 0126h Reset with POR DMA channel 0 control DMAOCTL Read write 01D0h Reset with POR DMA channel 0 source address DMAOSA Read write 01D2h Unchanged DMA channel 0 destination address DMAODA Read write 01D6h Unchanged DMA channel
259. an be higher than the TBCLO value When the sum of the previous TBCLx value plus tx is greater than the TBCLO data TBCLO 1 must be subtracted to obtain the correct time interval Up Down Mode Timer_B Operation The up down mode is used if the timer period must be different from TBR max counts and if a symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare latch TBCLO and back down to zero as shown in Figure 13 7 The period is twice the value in TBCLO Note TBCLO gt TBR max If TBCLO gt TBR max the counter operates as if it were configured for continuous mode It does not count down from TBR max to zero Figure 13 7 Up Down Mode TBCLO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TBCLR bit must be used to clear the direction The TBCLR bit also clears the TBR value and the clock divider In up down mode the TBCCRO CCIFG interrupt flag and the TBIFG interrupt flag are set only once during the period separated by 1 2 the timer period The TBCCRO CCIFG interrupt flag is set when the timer counts from TBCLO 1 to TBCLO and TBIFG is set when the timer completes counting down from 0001h to 0000h Figure 13 8 shows the flag set cycle Figure 13 8 Up Down Mode Flag Setting Timer Clock Timer Up Down Set TBIFG Set TBCCRO CCIFG
260. and a sequence mode is selected resetting the ENC bit does not stop the sequence To stop the sequence first select a single channel mode and then reset ENC O ooo ADC12 21 15 ADC12 Operation 21 2 7 Using the Integrated Temperature Sensor To use the on chip temperature sensor the user selects the analog input channel INCHx 1010 Any other configuration is done as if an external channel was selected including reference selection conversion memory selection etc The typical temperature sensor transfer function is shown in Figure 21 10 When using the temperature sensor the sample period must be greater than 30 us The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific datasheet for parameters Selecting the temperature sensor automatically turns on the on chip reference generator as a voltage source for the temperature sensor However it does not enable the Vrer output or affect the reference selections for the conversion The reference choices for converting the temperature sensor are the same as with any other channel Figure 21 10 Typical Temperature Sensor Transfer Function 21 16 ADC12 Volts 1 300 1 200 1 100 1 000 0 900 Vremp 0 00355 TEMP 0 986 0 800 0 700 Celsius ADC12 Operation 21 2 8 ADC12 Grounding and Noise Considerations As with any high resolution ADC appropriate printed circuit board layout and
261. and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability for applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a wa
262. annels is converted once channels 10 Repeat single A single channel is converted repeatedly channel 11 Repeat sequence A sequence of channels is converted of channels repeatedly 21 10 ADC12 ADC12 Operation Single Channel Single Conversion Mode A single channel is sampled and converted once The ADC result is written to the ADC12MEMx defined by the CSTARTADDx bits Figure 21 6 shows the flow of the Single Channel Single Conversion mode When ADC12SC triggers a conversion successive conversions can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each conversion Figure 21 6 Single Channel Single Conversion Mode CONSEQx 00 ADC120N 1 x CSTARTADDx Wait for Enable ra SHSx 0 I and ENC 1or4 and A ADC12SC 4 Wait for Trigger ENC 0 SAMPCON 4 i oe SAMPCON 1 Se Sample Input Channel Defined in ENC ot ADC12MCTLx AS SAMPCON y Se 12 x ADC12CLK N Ts ENC ot 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set x pointer to ADC12MCTLx t Conversion result is unpredictable ADC12 21 11 ADC12 Operation Sequence of Channels Mode A sequence of channels is sampled and converted once The ADC results are written to the conversion memories starting with the ADCMEMx defined by the CSTARTADDx bits The sequence stops after the measurement of the channel
263. are UY Capture compare block CCRO 11 cycles UY Capture compare blocks CCR1 to CCR6 16 cycles 1 Timer overflow TBIFG 14 cycles The following software example shows the recommended use of TBIV for Timer_B3 Interrupt handler for TBCCRO CCIFG Cycles CCIFG_0_HND Ss cae Start of handler Interrupt latency 6 RETI 5 Interrupt handler for TBIFG TBCCR1 and TBCCR2 CCIFG TB _HND eae Interrupt latency 6 ADD amp TBIV PC Add offset to Jump table 3 RETI Vector 0 No interrupt 5 JMP CCIFG_1 HND Vector 2 Module 1 2 JMP CCIFG 2 HND Vector 4 Module 2 2 RETI Vector 6 RETI Vector 8 RETI Vector 10 RETI Vector 12 TBIFG HND Vector 14 TIMOV Flag Task starts here RETI 5 CCIFG 2 HND Vector 4 Module 2 sect Task starts here RETI Back to main program 5 The Module 1 handler shows a way to look if any other interrupt is pending 5 cycles have to be spent but 9 cycles may be saved if another interrupt is pending CCIFG 1 HND Vector 6 Module 3 A ar Task starts here JMP TB_HND Look for pending ints 2 Timer_B 13 19 Timer_B Registers 13 3 Timer_B Registers The Timer_B registers are listed in Table 13 5 Table 13 5 Timer_B Registers Register Short Form Register Type Address Initial State Timer_B control TBCTL Read write 0180h Reset with POR Timer_B counter TBR Read write 0190h Reset with POR Timer_B capture compare control 0 TBCCTLO Read write 0182h Reset with POR Timer_B capture com
264. are always read as zero Devices that have addressable memory range beyond 64 KB contain an additional word for the source address Bits 15 4 of this additional word are reserved and always read as zero When writing to DMAxSA with word formats this additional word is automatically cleared Reads of this additional word using word formats are always read as zero 6 24 DMA Controller DMA Registers DMAXDA DMA Destination Address Register 15 14 13 12 11 10 9 8 Reserved ro ro 15 ro ro 14 ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro rw rw rw rw 13 12 11 10 9 8 DMAxDAx rw rw rw rw rw rw 5 4 3 2 1 0 DMAxDAx DMAxDA Bits 15 0 rw rw rw rw rw rw DMA destination address The destination address register points to the DMA destination address for single transfers or the first destination address for block transfers The destination address register remains unchanged during block and burst block transfers Devices that have addressable memory range 64 KB or below contain a single word for the DMAxDA Devices that have addressable memory range beyond 64 KB contain an additional word for the destination address Bits 15 4 of this additional word are reserved and always read as zero When writing to DMAxDA with word formats this additional word is automatically cleared Reads of this additional word using word formats are always read as zero DMA Controller 6 N al DMA Registers DMAxSZ DMA Size
265. are latch load These bits select the compare latch load event 00 TBCLx loads on write to TBCCRx 01 TBCLx loads when TBR counts to 0 10 TBCLx loads when TBR counts to O up or continuous mode TBCLx loads when TBR counts to TBCLO or to 0 up down mode 11 TBCLx loads when TBR counts to TBCLx Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TBCLO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set CCIE CCl OUT COV CCIFG Bit 4 Bit 3 Bit 2 Bit 1 Bit O Timer_B Registers Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending Timer_B 13 25 Timer_B Registers TBIV Timer_B Interrupt Vector Register 15 14 13 12 11 10 9 8 ro rO rO ro ro rO rO ro 7 6 5 4 3 2 1 0 ro rO rO ro r 0 r 0 r 0 ro TBIVx Bits Timer_B interrupt vector value 15 0 Interrupt TBIV Conte
266. are set to zero all compare latches update immediately when their corresponding TBCCRx is written no compare latches are grouped Two conditions must exist for the compare latches to be loaded when grouped First all TBCCRx registers of the group must be updated even when new TBCCRx data old TBCCRx data Second the load event must occur Table 13 3 Compare Latch Operating Modes TBCLGRPx Grouping Update Control 00 None Individual 01 TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCCR3 TBCL5 TBCL6 TBCCR5 10 TBCL1 TBCL2 TBCL3 TBCCR1 TBCL4 TBCL5 TBCL6 TBCCR4 11 TBCLO TBCL1 TBCL2 TBCCR1 TBCL3 TBCL4 TBCL5 TBCL6 Timer_B 13 13 Timer_B Operation 13 2 5 Output Unit Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals The TBOUTH pin function can be used to put all Timer_B outputs into a high impedance state When the TBOUTH pin function is selected for the pin and when the pin is pulled high all Timer_B outputs are in a high impedance state Output Modes The output modes are defined by the OUTMODx bits and are described in Table 13 4 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit O because EQUx EQUO Table 13 4 Output Modes OUTMODx 000 001 010
267. arry RLC R5 Carry P0in 1 gt LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C gt Mem LEO ee ee re Note RLC and RLC B Substitution The assembler does not recognize the instruction RLC OR5 RLC B R5 or RLC B R5 It must be substituted by ADDC R5 2 R5 ADDC B R5 1 R5 or ADDC B OR5 Lt ee RISC 16 Bit CPU 3 59 Instruction Set RRA W RRA B Syntax Operation Description Rotate right arithmetically Rotate right arithmetically RRA dst or RRA W dst RRA B dst MSB gt MSB MSB gt MSB 1 LSB 1 gt LSB LSB gt C The destination operand is shifted right one position as shown in Figure 3 16 The MSB is shifted into the MSB the MSB is shifted into the MSB 1 and the LSB 1 is shifted into the LSB Figure 3 16 Destination Operand Arithmetic Right Shift Word 15 0 Status Bits Mode Bits Example Example Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset OSCOFF CPUOFF and GIE are not affected R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA R5 R5 2 gt R5 The value in R5 is multiplied by 0 75 0 5 0 25 PUSH R5 Hold R5 temporarily using stack RRA R5 R5x0 5 gt R5 ADD SP R5 R5x0 5 R5 1 5x R5 gt R5 RRA R5 1 5 x R5 x 0 5 0 75 x R5 gt R5 The low by
268. ash Memory Operation Initiating an Erase from Within Flash Memory Any erase cycle can be initiated from within flash memory or from RAM When a flash segment erase operation is initiated from within flash memory all timing is controlled by the flash controller and the CPU is held while the erase cycle completes After the erase cycle completes the CPU resumes code execution with the instruction following the dummy write When initiating an erase cycle from within flash memory it is possible to erase the code needed for execution after the erase If this occurs CPU execution will be unpredictable after the erase cycle The flow to initiate an erase from flash is shown in Figure 7 5 Figure 7 5 Erase Cycle from Within Flash Memory mode Segment Erase from flash 514 kHz lt SMCLK lt 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV WDTPW WDTHOLD amp WDTCTL Disable WDT MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY ERASE FCTL1 Enable segment erase CLR amp 0FC10h Dummy write erase S1 MOV FWKEY LOCK amp FCTL3 Done set LOCK Re enable WDT 7 8 Flash Memory Controller Initiating an Erase from RAM Flash Memory Operation Any erase cycle may be initiated from RAM In this case the CPU is not held and can continue to execute code from RAM The BUSY bit must be polled to determine the end of the erase cycle before the CPU can access any flash a
269. asic Clock Module Registers 056h 057h 058h 053h 000h 002h Initial State 060h with PUC 087h with PORt Reset with PUC 005h with PUC Reset with PUC Reset with PUC Basic Clock Module 5 13 Basic Clock Module Registers DCOCTL DCO Control Register 7 6 5 4 3 2 1 0 E me rw 0 rw 1 rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 DCOx Bits DCO frequency select These bits select which of the eight discrete DCO 7 5 frequencies within the range defined by the RSELx setting is selected MODx Bits Modulator selection These bits define how often the fpco 1 frequency is 4 0 used within a period of 32 DCOCLK cycles During the remaining clock cycles 32 MOD the fpco frequency is used Not useable when DCOx 7 BCSCTL1 Basic Clock System Control Register 1 7 6 5 4 3 2 1 0 XT2OFF xTst DIVAx RSELx rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 1 rw 1 t XTS 1 is not supported in MSP430x20xx devices XT20FF Bit 7 XT2 off This bit turns off the XT2 oscillator 0 XT2 is on 1 XT2 is off if it is not used for MCLK or SMCLK XTS Bit 6 LFXT1 mode select 0 Low frequency mode 1 High frequency mode DIVAx Bits Divider for ACLK 5 4 00 A 01 2 10 4 11 1 8 RSELx Bits Range Select Sixteen different frequency ranges are available The lowest 3 0 frequency range is selected by setting RSELx 0 RSEL3 is ignored when DCOR 1 5 14 Basic Clock Module Basic Clock Module Registers BCSCTL2 Basic Clock System Control Register 2 rw 0 rw 0 r
270. asier to write and read but do not have op codes themselves instead they are replaced automatically by the assembler with an equivalent core instruction There is no code or performance penalty for using emulated instruction There are three core instruction formats _j Dual operand UY Single operand Lj Jump All single operand and dual operand instructions can be byte or word instructions by using B or W extensions Byte instructions are used to access byte data or byte peripherals Word instructions are used to access word data or word peripherals If no extension is used the instruction is a word instruction The source and destination of an instruction are defined by the following fields src The source operand defined by As and S reg dst The destination operand defined by Ad and D reg As The addressing bits responsible for the addressing mode used for the source src S reg The working register used for the source src Ad The addressing bits responsible for the addressing mode used for the destination dst D reg The working register used for the destination dst B W Byte or word operation 0 word operation 1 byte operation ae Note Destination Address Destination addresses are valid anywhere in the memory map However when using an instruction that modifies the contents of the destination the user must ensure the destination address is writable For example a masked ROM location would be a valid des
271. asure Resistive Elements The Comparator_A can be optimized to precisely measure resistive elements using single slope analog to digital conversion For example temperature can be converted into digital data using a thermistor by comparing the thermistor s capacitor discharge time to that of a reference resistor as shown in Figure 19 6 A reference resister Rref is compared to Rmeas Figure 19 6 Temperature Measurement System CAO CCHB Capture Input Of Timer_A lt b 0 25xVcc The MSP430 resources used to calculate the temperature sensed by Rmeas are Two digital I O pins to charge and discharge the capacitor I O set to output high Vcc to charge capacitor reset to discharge I O switched to high impedance input with CAPDx set when not in use One output charges and discharges the capacitor via Rref One output discharges capacitor via Rmeas The terminal is connected to the positive terminal of the capacitor The terminal is connected to a reference level for example 0 25 x Vcc The output filter should be used to minimize switching noise ct e q O O oe CAOUT used to gate Timer_A CCI1B capturing capacitor discharge time More than one resistive element can be measured Additional elements are connected to CAO with available I O pins and switched to high impedance when not being measured 19 8 Comparator_A Comparator_A Operation The thermistor measurement is based on a ratiometric
272. ation of the SD16_A is discussed in the following sections The analog to digital conversion is performed by a 1 bit second order sigma delta modulator A single bit comparator within the modulator quantizes the input signal with the modulator frequency fm The resulting 1 bit data stream is averaged by the digital filter for the conversion result 24 2 2 Analog Input Range and PGA The full scale input voltage range for each analog input pair is dependent on the gain setting of the programmable gain amplifier of each channel The maximum full scale range is VFsp where Vesp is defined by Vrer 2 Vise GAIN 504 For a 1 2V reference the maximum full scale input range for a gain of 1 is 1 2V 2 Vrsr 4 0 6V See the device specific data sheet for full scale input specifications 24 2 3 Voltage Reference Generator The SD16_A module has a built in 1 2V reference It is enabled by the SD16REFON bit When using the internal reference an external 100 nF capacitor connected from Vper to AVss is recommended to reduce noise The internal reference voltage can be used off chip when SD16VMIDON 1 The buffered output can provide up to 1mA of drive When using the internal reference off chip a 470 nF capacitor connected from VreF to AVsg is required See the device specific data sheet for parameters An external voltage reference can be applied to the Vprer input when SD16REFON and SD16VMIDON are both reset 24 2 4 Auto Power Dow
273. aud Rate Mode Setting 15 18 In the oversampling mode the prescaler is set to UCBRx INT N 16 and the first stage modulator is set to UCBRFx round N 16 INT N 16 16 When greater accuracy is required the UCBRSx modulator can also be implemented with values from O 7 To find the setting that gives the lowest maximum bit error rate for any given bit a detailed error calculation must be performed for all settings of UCBRSx from 0 7 with the initial UCBRFx setting and with the UCBRFx setting incremented and decremented by one Universal Serial Communication Interface UART Mode USCI Operation UART Mode 15 3 11 Transmit Bit Timing The timing for each character is the sum of the individual bit timings Using the modulation features of the baud rate generator reduces the cumulative bit error The individual bit error can be calculated using the following steps Low Frequency Baud Rate Mode Bit Timing In low frequency mode calculate the length of bit i Tpit rx i based on the UCBRx and UCBRSx settings Tondi UCBRx Mucsnsdil fercik where Mucsrsxl Modulation of bit i from Table 15 2 Oversampling Baud Rate Mode Bit Timing In oversampling baud rate mode calculate the length of bit i Tpit Tx i based on the baud rate generator UCBRx UCBRFx and UCBRSx settings Toirxli a fercik i vs Mucersxil UCBRx gt raed 0 where 15 gt MucesrexUl Sum of o
274. avoid unpredictable behavior Setting UCSWRST in 12C mode has the following effects 12 communication stops SDA and SCL are high impedance UCBxI2CSTAT bits 6 0 are cleared UCBxTXIE and UCBxRXIE are cleared UCBxTXIFG and UCBxRXIFG are cleared All other bits and registers remain unchanged O O O O O L Note Initializing or Reconfiguring the USCI Module The recommended USCI initialization re configuration process is 1 Set UCSWRST BIS B UCSWRST amp UCxCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B UCSWRST amp UCXCTL1 5 Enable interrupts optional via UCxRXIE and or UCxTXIE Lt ee Universal Serial Communication Interface 12C Mode USCI Operation C Mode 17 3 2 12C Serial Data One clock pulse is generated by the master device for each data bit transferred The 12C mode operates with byte data Data is transferred most significant bit first as shown in Figure 17 3 The first byte after a START condition consists of a 7 bit slave address and the R W bit When RW 0 the master transmits data to a slave When RW 1 the master receives data from a slave The ACK bit is sent from the receiver after each byte on the 9th SCL clock Figure 17 3 12C Module Data Transfer Acknowledgement Acknowledgement Signal From Receiver Signal From Receiver SOL A Ned SS PTT PPT 2 START Condition S
275. bits Figure 3 6 Status Register Bits 15 9 8 7 0 OSC CPU rw 0 Table 3 1 describes the status register bits Table 3 1 Description of Status Register Bits Bit V SCG1 SCGO OSCOFF CPUOFF GIE N 3 6 RISC 16 Bit CPU Description Overflow bit This bit is set when the result of an arithmetic operation overflows the signed variable range Set when Positive Positive Negative Negative Negative Positive otherwise reset ADD B ADDC B Set when Positive Negative Negative Negative Positive Positive otherwise reset SUB B SUBC B CMP B System clock generator 1 This bit when set turns off the SMCLK System clock generator 0 This bit when set turns off the DCO dc generator if DCOCLK is not used for MCLK or SMCLK Oscillator Off This bit when set turns off the LFXT1 crystal oscillator when LFXT1CLK is not use for MCLK or SMCLK CPU off This bit when set turns off the CPU General interrupt enable This bit when set enables maskable interrupts When reset all maskable interrupts are disabled Negative bit This bit is set when the result of a byte or word operation is negative and cleared when the result is not negative Word operation N is set to the value of bit 15 of the result N is set to the value of bit 7 of the result Byte operation Zero bit This bit is set when the result of a byte or word operation is O and cleared when the resul
276. bits Table 3 3 Source Destination Operand Addressing Modes As Ad Addressing Mode Syntax Description 00 0 Register mode Rn Register contents are operand 01 1 Indexed mode X Rn Rn X points to the operand X is stored in the next word 01 1 Symbolic mode ADDR PC X points to the operand X is stored in the next word Indexed mode X PC is used 01 1 Absolute mode amp ADDR The word following the instruction contains the absolute address X is stored in the next word Indexed mode X SR is used 10 Indirect register Rn Rn is used as a pointer to the mode operand 11 Indirect Rn Rnis used as a pointer to the autoincrement operand Rn is incremented afterwards by 1 for B instructions and by 2 for W instructions 11 Immediate mode N The word following the instruction contains the immediate constant N Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction koe oo o ___ gt ZS Note Use of Labels EDE TONI TOM and LEO Throughout MSP430 documentation EDE TONI TOM and LEO are used as generic labels They are only labels They have no special meaning baa RISC 16 Bit CPU 3 9 Addressing Modes 3 3 1 Register Mode The register mode is des
277. bits 15 0 of the PC Figure 4 4 Program Counter Storage on the Stack for CALLA SPold SP The RETA instruction restores bits 19 0 of the program counter and adds 4 to the stack pointer The RET instruction restores bits 15 0 to the program counter and adds 2 to the stack pointer 4 6 16 Bit MSP430X CPU CPU Registers 4 3 2 Stack Pointer SP The 20 bit stack pointer SP R1 is used by the CPU to store the return addresses of subroutine calls and interrupts lt uses a predecrement postincrement scheme In addition the SP can be used by software with all instructions and addressing modes Figure 4 5 shows the SP The SP is initialized into RAM by the user and is always aligned to even addresses Figure 4 6 shows the stack usage Figure 4 7 shows the stack usage when 20 bit address words are pushed Figure 4 5 Stack Pointer 19 1 0 Stack Pointer Bits 19 to 1 g MOV W 2 SP R6 Copy Item I2 to R6 MOV W R7 0 SP Overwrite TOS with R7 PUSH 0123h Put 0123h on stack POP R8 R8 0123h Figure 4 6 Stack Usage Address PUSH 0123h POP R8 Oxxxh Oxxxh 2 Oxxxh 4 SP Oxxxh 6 Oxxxh 8 Figure 4 7 PUSHX A Format on the Stack SPold Item n 1 SP Item 15 0 16 Bit MSP430X CPU 4 7 CPU Registers The special cases of using the SP as an argument to the PUSH and POP instructions are described and shown in Figure 4 8 Figure 4 8 PUSH SP POP SP Sequence PUSH SP POP SP SPold pa E gt SP S
278. busy MOV FWKEY FSSEL1 FNO amp FCTL2 SMCLK 2 MOV FWKEY amp FCTL3 Clear LOCK MOV FWKEY BLKWRT WRT amp FCTL1 Enable block write MOV Write Value 0 R6 Write location BIT WAIT amp FCTL3 Test WAIT JZ L3 Loop while WAIT 0 INCD R6 Point to next word DEC R5 Decrement write counter JNZ L2 End of block MOV FWKEY amp FCTL1 Clear WRT BLKWRT BIT BUSY amp FCTL3 Test BUSY JNZ L4 Loop while busy MOV FWKEY LOCK amp FCTL3 Set LOCK Re enable WDT if needed Flash Memory Controller 7 15 Flash Memory Operation 7 3 4 Flash Memory Access During Write or Erase When any write or any erase operation is initiated from RAM and while BUSY 1 the CPU may not read or write to or from any flash location Otherwise an access violation occurs ACCVIFG is set and the result is unpredictable Also if a write to flash is attempted with WRT 0 the ACCVIFG interrupt flag is set and the flash memory is unaffected When a byte word write or any erase operation is initiated from within flash memory the flash controller returns op code O3FFFh to the CPU at the next instruction fetch Op code O3FFFh is the JMP Pc instruction This causes the CPU to loop until the flash operation is finished When the operation is finished and BUSY 0 the flash controller allows the CPU to fetch the proper op code and program execution resumes The flash access conditions while BUSY 1 are listed in Table 7 3 Table 7 3 Flash Access
279. c gt dst reset if positive src lt dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow Mode Bits OSCOFF CPUOFF and GIE are not affected Example A 20 bit immediate operand and R6 are compared If they are equal the program continues at label EQUAL CMPA 12345h R6 Compare R6 with 12345h JEQ EQUAL R5 12345h Not equal Example The 20 bit values in R5 and R6 are compared If R5 is greater than signed or equal to R6 the program continues at label GRE CMPA R6 R5 Compare R6 with R5 R5 R6 JGE GRE R5 gt R6 R5 lt R6 4 162 16 Bit MSP430X CPU DECDA Syntax Operation Emulation Description Status Bits Mode Bits Example Address Instructions Double decrement 20 bit destination register DECDA Rdst Rdst 2 gt Rdst SUBA 2 Rdst The destination register is decremented by two The original contents are lost N Set if result is negative reset if positive Z Set if Rdst contained 2 reset otherwise C Reset if Rdst contained 0 or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected
280. c Page 2 1 System Reset and Initialization ooocoooonrnommmmmoo 2 2 272 ACM a oooorosadobosaron ceo op bona oobuo dado pasos aobada Ana 2 5 2 3 Operating Modest E a e 2 14 2 4 Principles for Low Power Applications oooooooo 2 17 2 5 Connection of Unused Pins ooccccococcccccon eee eee 2 17 2 1 System Reset and Initialization 2 1 System Reset and Initialization The system reset circuitry shown in Figure 2 1 sources both a power on reset POR and a power up clear PUC signal Different events trigger these reset signals and different initial conditions exist depending on which signal was generated Figure 2 1 Power On Reset and Power Up Clear Schematic Vec Brownout Reset POR S Latch POR R OV 50 us aae gt RST NMI WDTTMSEL 0 py ease ue Resetwd1 EQut Resetwd2 KEYV from flash module PUC Invalid instruction fetch MCLK t From watchdog timer peripheral module Devices with SVS only A POR is a device reset A POR is only generated by the following three events Y Powering up the device YU A low signal on the RST NMI pin when configured in the reset mode Li An SVS low condition when PORON 1 A PUC is always generated when a POR is generated but a POR is not generated by a PUC The following events trigger a PUC Y A POR signal Watchdog timer expiration whe
281. cccccc nenna a nenen aan 21 10 21 2 6 ADC12 Conversion Modes 00 cece cece eens 21 10 21 2 7 Using the Integrated Temperature Sensor 0000e eee eeee 21 16 21 2 8 ADC12 Grounding and Noise Considerations 2000 21 17 21 2 9 ADC12 Interrupts o reei noei pe Eai eee 21 18 21 3 ADCIZREJIStE Snie naa eiaa a e aT a e a a A E E E 21 20 TEV Str ct re arnan o ida 22 1 22 11 TLV MOUGU io a ae a A AA Soe E EE eae 22 2 22 2 Supported Tags 2 cece eee eee 22 3 22 2 1 DCO Calibration TLV Structure 0c cece eee 22 3 22 2 2 TAG_ADC12_1 Calibration TLV structure 0000 eee 22 4 22 3 Te Checking Integrity of SegmentA 22 4 Parsing TLV Structure of Segment A o cococccccccccccccc 22 8 D2 ea econ n dS ace hace tg ah cease hc alae atc E a E Tela at hate aar S 23 1 23 1 DAG12 IntroductiON viii rra dee dea cade 23 2 23 2 DACI2Z Operation ax coria rare 23 4 23 21 DACIZ Gore shuddceveteatadaniie soured deueaiide eee tedade idee 23 4 23 2 2 DAC12 Reference 0 oiana ect e ee 23 5 23 2 3 Updating the DAC12 Voltage Output 0 2 cee eee 23 5 23 2 4 DAC12_xDAT Data Format 000 cece eee 23 6 23 2 5 DAC12 Output Amplifier Offset Calibration ooo ooo ooo 23 7 23 2 6 Grouping Multiple DAC12 Modules 0200c cece eee eee 23 8 23 2 7 DAC12 Interrupts 0 0 23 9 23 3 DAC12 Registers 0 0 cece eee een ees 23 1
282. ce address word and carry decimally to destination address word Add source word and carry decimally to destination word Add source byte and carry decimally to destination byte DADDX A src dst DADDX src dst or DADDX W src dst DADDX B src dst src dst C gt dst decimally The source operand and the destination operand are treated as two B four W or five A binary coded decimals BCD with positive signs The source operand and the carry bit C are added decimally to the destination operand The source operand is not affected The previous contents of the destination are lost The result is not defined for non BCD numbers Both operands may be located in the full address space N Set if MSB of result is 1 address word gt 79999h word gt 7999h byte gt 79h reset if MSB is 0 Z Set if result is zero reset otherwise C Set if the BCD result is too large address word gt 99999h word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected Decimal 10 is added to the 20 bit BCD counter DECCNTR located in two words DADDX A 10h amp DECCNTR Add 10 to 20 bit BCD counter The eight digit BCD number contained in 20 bit addresses BCD and BCD 2 is added decimally to an eight digit BCD number contained in R4 and R5 BCD 2 and R5 contain the MSDs CLRC Clear carry DADDX W BCD R4 Add LSDs DADDX W BCD 2 R5 Add MSDs with carry JC OVERFLOW Result gt 99999999
283. ce specific OFFC8h 4 device specific OFFC6h 3 device specific OFFC4h 2 device specific OFFC2h 1 device specific OFFCOh 0 lowest System Resets Interrupts and Operating Modes 2 13 Operating Modes 2 3 Operating Modes The MSP430 family is designed for ultralow power applications and uses different operating modes shown in Figure 2 9 The operating modes take into account three different needs _j Ultralow power Y Speed and data throughput _j Minimization of individual peripheral current consumption The MSP430 typical current consumption is shown in Figure 2 8 Figure 2 8 Typical Current Consumption of 21x1 Devices vs Operating Modes 300 270 Ico uA at 1 MHz PE al AM LPMO LPM2 LPM3 LPM4 Operating Modes The low power modes 0 to 4 are configured with the CPUOFF OSCOFF SCGO and SCG1 bits in the status register The advantage of including the CPUOFF OSCOFF SCGO and SCG1 mode control bits in the status register is that the present operating mode is saved onto the stack during an interrupt service routine Program flow returns to the previous operating mode if the saved SR value is not altered during the interrupt service routine Program flow can be returned to a different operating mode by manipulating the saved SR value on the stack inside of the interrupt service routine The mode control bits and the stack can be accessed with any instruction When setting any of the mode control bits the selected operatin
284. ceived into USISRL When USIIFG becomes set again the LSB of USISRL is the received acknowledge bit and can be tested in software Receive ACK NACK BIC B USIOE amp USICTLO SDA input MOV B 01h USICNT y USICNTx 1 TEST_USIIFG BIT B USIIFG amp USICTL1 Test USIIFG JZ TEST_USIIFG BIT B 01h amp USISRL Test received ACK bit JNZ HANDLE NACK Handle if NACK Else handle ACK Universal Serial Interface 14 9 USI Operation 12C Receiver START Condition In 12C receiver mode the output must be disabled by clearing USIOE and the USI module is prepared for reception by writing 8 into USICNTx This clears USIIFG and SCL is generated in master mode or released from being held low in slave mode The USIIFG bit will be set after 8 clocks This stops the clock signal on SCL in master mode or holds SCL low at the next low phase in slave mode To transmit an acknowledge or no acknowledge bit the MSB of the shift register is loaded with 0 or 1 the USIOE bit is set with software to enable the output and 1 is written to the USICNTx bits As soon as the MSB bit is shifted out USIIFG will be become set and the module can be prepared for the reception of the next 12C data byte Generate ACK BIS B USIOE amp USICTLO SDA output MOV B 00h amp USISRL MSB 0 MOV B 01h amp USICNT USICNTX 1 TEST USIIFG BIT B USIIFG amp USICTL1 Test USIIFG JZ TEST USIIFG continue Generate NACK BIS B USIO
285. cks of ae Characters Idle Periods of 10 Bits or More gt UCAxTXD RXD Expanded First Character Within Block Character Within Block Character Within Block Is Address It Follows Idle Period of 10 Bits or More Idle Period Less Than 10 Bits 15 6 Universal Serial Communication Interface UART Mode Transmitting an Idle USCI Operation UART Mode The UCDORM bit is used to control data reception in the idle line multiprocessor format When UCDORM 1 all non address characters are assembled but not transferred into the UCAxRXBUF and interrupts are not generated When an address character is received the character is transferred into UCAxRXBUF UCAXRXIFG is set and any applicable error flag is set when UCRXEIE 1 When UCRXEIE 0 and an address character is received but has a framing error or parity error the character is not transferred into UCAxRXBUF and UCAXRXIFG is not set If an address is received user software can validate the address and must reset UCDORM to continue receiving data If UCDORM remains set only address characters will be received When UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception completed The UCDORM bit is not modified by the USCI hardware automatically For address transmission in idle line multiprocessor format a precise idle period can be generated by the USCI to generate address character identifiers on UCAxTXD The double buf
286. control register 1 UCB1BR1 Read write ODBh Reset with PUC USCI_B1 12C Interrupt enable register UCB1I2ClIE Read write ODCh Reset with PUC USCI_B1 status register UCB1STAT Read write ODDh Reset with PUC USCI_B1 receive buffer register UCB1RXBUF Read ODEh Reset with PUC USCI_B1 transmit buffer register UCB1TXBUF Read write ODFh Reset with PUC USCI_B1 12C own address register UCB1I2COA Read write 017Ch Reset with PUC USCI_B1 12C slave address register UCB1I2CSA Read write 017Eh Reset with PUC USCI_A1 B1 interrupt enable register UC1IE Read write 006h Reset with PUC USCI_A1 B1 interrupt flag register UC1IFG Read write 007h O0Ah with PUC 17 25 USCI Registers I7C Mode UCBxCTLO USCI_Bx Control Register 0 7 6 5 4 3 2 1 0 UCA10 UCSLA10 UCMM ENS UCMST UCMODEx 11 UCSYNC 1 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 1 UCA10 Bit 7 Own addressing mode select 0 Own address is a 7 bit address 1 Own address is a 10 bit address UCSLA10 Bit 6 Slave addressing mode select 0 Address slave with 7 bit address 1 Address slave with 10 bit address UCMM Bit 5 Multi master environment select 0 Single master environment There is no other master in the system The address compare unit is disabled 1 Multi master environment Unused Bit 4 Unused UCMST Bit 3 Master mode select When a master looses arbitration in a multi master environment UCMM 1 the UCMST bit is automatically cleared and the module acts as slave 0 Slave mode 1 Master mode UCMODEx Bits US
287. controller features include Up to three independent transfer channels Configurable DMA channel priorities Requires only two MCLK clock cycles per transfer Byte or word and mixed byte word transfer capability Block sizes up to 65535 bytes or words Configurable transfer trigger selections Selectable edge or level triggered transfer Four addressing modes Do 50 000 oo Q Single block or burst block transfer modes The DMA controller block diagram is shown in Figure 6 1 6 2 DMA Controller Figure 6 1 DMA Controller Block Diagram DMAOTSELx DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USCI AO data receive USCI AO data transmit DAC12_0IFG ADC12_IFGx TACCRO_CCIFG TBCCRO_CCIFG USCI A1 data Rx USCI A1 data Tx Multiplier ready USCI BO data receive USCI BO data transmit DMA2IFG DMAEO DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USCI AO data receive USCI AO data transmit DAC12_0IFG ADC12_IFGx TACCRO_CCIFG TBCCRO_CCIFG USCI A1 data Rx USCI A1 data Tx Multiplier ready USCI BO data receive USCI BO data transmit DMAOIFG DMAEO DMAREQ TACCR2_CCIFG TBCCR2_CCIFG USCI AO data receive USCI AO data transmit DAC12_0IFG ADC12_IFGx TACCRO_CCIFG TBCCRO_CCIFG USCI A1 data Rx USCI A1 data Tx Multiplier ready USCI BO data receive USCI BO data transmit DMA1IFG DMAEO DMA Priority And Controll ai col ENNMI ROUNDROBIN DMADSTINCRx DMADTx 2 DMADSTBYTE aac DMA Channel 0 DMAOSA DMAODA DMAOSZ 2
288. conversion principle The ratio of two capacitor discharge times is calculated as shown in Figure 19 7 Figure 19 7 Timing for Temperature Measurement Systems Vo Voc 0 25 x Vcc ae re 4 Phase l gt Phase ll gt Phase III Phase IV t Charge Discharge Charge Discharge te tmeas gt The Vcc voltage and the capacitor value should remain constant during the conversion but are not critical since they cancel in the ratio V f Rmeas X C x In E Nmeas ES Vec Nret Rio X C X In Vret re V CC Nmeas 2 Rmeas Nef Fret Nmeas Rmeas Fret N ref Comparator_A 19 9 Comparator_A Registers 19 3 Comparator_A Registers The Comparator_A registers are listed in Table 19 1 Table 19 1 Comparator_A Registers Register Short Form Register Type Address Comparator_A control register 1 CACTL1 Read write 059h Comparator_A control register 2 CACTL2 Read write O5Ah Comparator_A port disable CAPD Read write O5Bh 19 10 Comparator_A Initial State Reset with POR Reset with POR Reset with POR Comparator_A Registers CACTL1 Comparator_A Control Register 1 7 CAEX CARSEL CAREF CAON CAIES CAIE CAIFG 3 2 rw 0 rw 0 Bit 7 Bit 6 Bits Bit 3 Bit 2 Bit 1 Bit O 5 4 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Comparator_A exchange This bit exchanges the comparator inputs and inverts the comparator
289. cribed in Table 3 4 Table 3 4 Register Mode Description Assembler Code Content of ROM MOV R10 R11 MOV R10 R11 Length One or two words Operation Move the content of R10 to R11 R10 is not affected Comment Valid for source and destination Example MOV R10 R11 Before After Note Data in Registers The data in the register can be accessed using word or byte instructions If byte instructions are used the high byte is always 0 in the result The status bits are handled according to the result of the byte instruction 3 10 RISC 16 Bit CPU 3 3 2 Indexed Mode Addressing Modes The indexed mode is described in Table 3 5 Table 3 5 Indexed Mode Description Assembler Code MOV 2 R5 6 R6 Content of ROM MOV X R5 Y R6 X 2 Y 6 Move the contents of the source address contents of R5 2 to the destination address contents of R6 6 The source and destination registers R5 and R6 are not affected In the program counter is incremented automatically so that program execution continues with the After Address Register Space Oxxxxh PC OFF16h 00006h R5 01080h OFF14h 00002h R6 0108Ch OFF12h 04596h 01092h 01234h 01082h 01080h Length Two or three words Operation indexed mode next instruction Comment Valid for source and destination Example MOV 2 R5 6 R6 Before Address Register Space OFF16h 00006h R5 01080h OFF14h 00002h R6 0108Ch OFF12h 04596h PC
290. cription Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if Negative JN label lf N 1 PC 2 x Offset PC If N 0 execute following instruction The negative bit N in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If N is reset the instruction after the jump is executed Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte COUNT is tested If it is negative program execution continues at Label0 Data in lower 64 K program in full memory range TST B amp COUNT Is byte COUNT negative JN LabelO Yes proceed at LabelO COUNT 0 R6 is subtracted from R5 If the result is negative program continues at Label2 Program in full memory range SUB R6 R5 R5 R6 gt R5 JN Label2 R5 is negative R6 gt R5 N 1 R5 0 Continue here R7 20 bit counter is decremented If its content is below zero the program continues at Label4 Program in full memory range SUBA 1 R7 Decrement R7 JN Label4 R7 lt 0 Go to Label4 R7 0 Continue here 16 Bit MSP430X CPU 4 89 MSP430 Instructions JNC JLO Syntax Operation Description Status Bits Mode Bits Example Example Jump if No carry Jump if lowe
291. cted to AVss The OAxTAP signal is connected to the inverting input of the OAx providing a comparator with a programmable threshold voltage selected by the OAFBRx bits The non inverting input is selected by the OAPx bits Hysteresis can be added by an external positive feedback resistor The external connection for the inverting input is disabled and the OANx bits are don t care The OAx output is connected to the ADC12 input channel as selected by the OAxCTLO bits Non Inverting PGA Mode In this mode the output of the OAx is connected to Rrop and Rgorttom is connected to AVss The OAXTAP signal is connected to the inverting input of the OAx providing a non inverting amplifier configuration with a programmable gain of 1 OAxTAP ratio The OAxTAP ratio is selected by the OAFBRx bits If the OAFBRx bits 0 the gain is unity The non inverting input is selected by the OAPx bits The external connection for the inverting input is disabled and the OANx bits are don t care The OAx output is connected to the ADC12 input channel as selected by the OAxCTLO bits Cascaded Non Inverting PGA Mode Inverting PGA Mode This mode allows internal routing of the OA signals to cascade two or three OA in non inverting mode In this mode the non inverting input of the OAx is connected to OA20UT OA0 OAOOUT OA1 or OA1OUT OA2 when OAPx 11 The OAx outputs are connected to the ADC12 input channel as selected by the OAxCTLO bits In this mode the outp
292. d R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE OFEh L 1 MOV EDE R6 MOV 255 R10 MOV B 2 R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 4 36 Figure 4 36 Decrement Overlap EDE gt TONI EDE 254 TONI 254 16 Bit MSP430X CPU 4 77 MSP430 Instructions DECD W DECD B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Double decrement destination Double decrement destination DECD dst or DECD W dst DECD B dst dst 2 gt dst SUB 2 dst SUB B 2 dst The destination operand is decremented by two The original contents are lost Set if result is negative reset if positive Set if dst contained 2 reset otherwise Reset if dst contained 0 or 1 set otherwise Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08001 or 08000h otherwise reset Set if initial value of destination was 081 or 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 2 DECD R10 Decrement R10 by two Move a block of 255 words from memory location starting with EDE to memory location Starting with TONI
293. d Carry to dst ADDC B 0 dst A s BR dst Branch indirectly dst MOV dst PC CLR B dst Clear dst MOV B 0 dst CLRC Clear Carry bit BIC 1 SR 0 CLRN Clear Negative bit BIC 4 SR CLRZ Clear Zero bit BIC 2 SR DADC B dst Add Carry to dst decimally DADD B 0 dst ki E DEC B dst Decrement dst by 1 SUB B 1 dst y DECD B dst Decrement dst by 2 SUB B 2 dst ia vj DINT Disable interrupt BIC 8 SR EINT Enable interrupt BIS 8 SR INC B dst Increment dst by 1 ADD B 1 dst INCD B dst Increment dst by 2 ADD B 2 dst dd il INV B dst Invert dst XOR B 1 dst E ig NOP No operation MOV R3 R3 POP dst Pop operand from stack MOV SP dst RET Return from subroutine MOV SP PC RLA B dst Shift left dst arithmetically ADD B dst dst RLC B dst Shift left dst ADDC B dst dst il logically through Carry SBC B dst Subtract Carry from dst SUBC B 0 dst hi SETC Set Carry bit BIS 1 SR 1 SETN Set Negative bit BIS 4 SR SETZ Set Zero bit BIS 2 SR TST B dst Test dst CMP B 0 dst 0 1 compare with 0 16 Bit MSP430X CPU 4 39 MSP430 and MSP430X Instructions MSP430 Instruction Execution The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to MCLK Instruction Cycles and Length for Interrupt Reset and Subroutines Table 4 8 lists the len
294. d SD16UNI setting For example for OSR 1024 LSBACC 0 and SD16UNI 1 the SD16MEMO register contains bits 28 13 of the digital filter output When OSR 32 the one SD16UNI 0 or two SD16UNI 1 LSBs are always zero The SD16LSBACC and SD16LSBTOG bits give access to the least significant bits of the digital filter output When SD16LSBACC 1 the 16 least significant bits of the digital filters output are read from SD16MEMO using word instructions The SD16MEMO register can also be accessed with byte instructions returning only the 8 least significant bits of the digital filter output When SD16LSBTOG 1 the SD16LSBACC bit is automatically toggled each time SD16MEMO is read This allows the complete digital filter output result to be read with two reads of SD16MEMO Setting or clearing SD16LSBTOG does not change SD16LSBACC until the next SD16MEMO access Figure 24 5 Used Bits of Digital Filter Output OSR 1024 LSBACC 0 SD16UNI 1 y 29 28 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OSR 1024 LSBACC 1 SD16UNI 1 OSR 1024 LSBACC 0 SD16UNI 0 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 10 OSR 1024 LSBACC 1 SD16UNI 0 OSR 512 LSBACC 0 SD16UNI 1 29 28 27 la 24 23 22 21 20 19 18 17116 15 14 13 12 11 Da 8 716 5 4 3 2
295. d destination address word Compare source word and destination word Compare source byte and destination byte CMPX A src dst CMPX src dst or CMPX W src dst CMPX B src dst not src 1 dst or dst src The source operand is subtracted from the destination operand by adding the 1 s complement of the source 1 to the destination The result affects only the status bits Both operands may be located in the full address space N Set if result is negative src gt dst reset if positive src lt dst Z Set if result is zero src dst reset otherwise src dst C Set if there is a carry from the MSB reset otherwise V Set if the subtraction of a negative source operand from a positive destination operand delivers a negative result or if the subtraction of a positive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected Compare EDE with a 20 bit constant 18000h Jump to label TONI if EDE equals the constant CMPX A 018000h EDE Compare EDE with 18000h JEQ TONI EDE contains 18000h Not equal A table word pointed to by R5 20 bit address is compared with R7 Jump to label TONI if R7 contains a lower signed 16 bit number CMPX W R5 R7 Compare two signed numbers JL TONI R7 lt R5 gt R7 gt R5 A table byte pointed to by R5 20 bit address is compared to the input in I O Port1 Jump to label TONI if t
296. d following the instruction as the address of the operand The Absolute mode has two addressing possibilities _j Absolute mode in lower 64 KB memory lL MSP430X instruction with Absolute mode 4 28 16 Bit MSP430X CPU CPU Registers Absolute Mode in Lower 64 KB If an MSP430 instruction is used with Absolute addressing mode the absolute address is a 16 bit value and therefore points to an address in the lower 64 KB of the memory range The address is calculated as an index from 0 and is stored in the word following the instruction The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications Length Two or three words Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from O and inserts it Example ADD W amp EDE amp TONI This instruction adds the 16 bit data contained in the absolute source and destination addresses and places the result into the destination Source Word at address EDE Destination Word at address TONI Before Address Space After Address Space 2103Ah 2103Ah PC 21038h 21038h 21036h 21036h 21034h 21034h 5432h src 0777Ah 0777Ah 2345h _ dst 7777h Sum 07778h 07778h 0579Eh 0579Ch 0579Eh 0579Ch 16 Bit MSP430X CPU 4 29 CPU Registers MSP430X Instruction with Absolute Mode If an MSP430X instruction is used with Abs
297. d to Measure Resistive Elements Comparator_A Registers ooooocccccccncccc etna 20 21 22 23 Contents ADC A E Nee le io ole eae 20 1 20 1 ADG10 Introduction ci shes e ie teed sae eat Peas eee 20 2 20 2 ADG10 Operation io cs varie ide i tee es te ee a Ee 20 4 20 2 1 10 Bit ADG Core ri sss nee ON ened nities Sv a ed a a 20 4 20 2 2 ADC10 Inputs and Multiplexer 0 00 eee eee eee 20 5 20 2 3 Voltage Reference Generator 02 0 cece eee eee eee 20 6 20 2 4 Auto Power Down 0 cece ee tenets 20 6 20 2 5 Sample and Conversion Timing 00 cece e eee eres 20 7 20 2 6 Conversion Modes 00 cece eects 20 9 20 2 7 ADC10 Data Transfer Controller 000 cece eee 20 15 20 2 8 Using the Integrated Temperature Sensor 0000 c cece eens 20 21 20 2 9 ADC10 Grounding and Noise Considerations 0005 20 22 20 2 10 ADC10 Interrupts 20 eee eee 20 23 20 3 ADC10 Registers a aa Aa E eee teens 20 24 PDC A O 21 1 21 1 ADC12 Introduction diii e a eaa eenaa a Ka eens 21 2 21 2 ADC Operation rica oe ended aed na a dais 21 4 21 21 A2 Bit ADO COS iia A A dba 21 4 21 2 2 ADC12 Inputs and Multiplexer 000 cece eee eee 21 5 21 2 3 Voltage Reference Generator 0000 cece eee eee eee 21 6 21 2 4 Sample and Conversion Timing 00 cece cece eee eee 21 7 21 2 5 Conversion Memory ooocccccc
298. d to by R7 R5 auto increments to point to the next 48 bit number SUBX W R5 0 R7 SUBCX W R5 2 R7 SUBCX W R5 4 R7 Subtract LSBs R5 2 Subtract MIDs with C R5 2 Subtract MSBs with C R5 2 Byte CNT is subtracted from the byte R12 points to The carry of the previous instruction is used 20 bit addresses SUBCX B amp CNT 0 R12 Subtract byte CNT from R12 16 Bit MSP430X CPU SWPBX A SWPBX W Syntax Operation Description Status Bits Mode Bits Example Example Extended Instructions Swap bytes of lower word Swap bytes of word SWPBX A dst SWPBX W dst or SWPBX dst dst 15 8 dst 7 0 Register Mode Rn 15 8 are swapped with Rn 7 0 When the A extension is used Rn 19 16 are unchanged When the W extension is used Rn 19 16 are cleared Other Modes When the A extension is used bits 31 20 of the destination address are cleared bits 19 16 are left unchanged and bits 15 8 are swapped with bits 7 0 When the W extension is used bits 15 8 are swapped with bits 7 0 of the addressed word Not affected OSCOFF CPUOFF and GIE are not affected Exchange the bytes of RAM address word EDE MOVX A 23456h amp EDE 23456h gt EDE SWPBX A EDE 25634h gt EDE Exchange the bytes of R5 MOVA 23456h R5 23456h gt R5 SWPBX W R5 05634h gt R5 Figure 4 55 Swap Bytes SWPBX A Register Mode Before SWPBX A 19 16 15 8 7 0 After SWPBX A 19 16 15 8 7 0 16 Bit MSP430
299. d when UCOS16 1 This mode supports sampling a UART bit stream with higher input clock frequencies This results in majority votes that are always 1 16 of a bit clock period apart This mode also easily supports IrDA pulses with a 3 16 bit time when the IrDA encoder and decoder are enabled This mode uses one prescaler and one modulator to generate the BITCLK16 clock that is 16 times faster than the BITCLK An additional divider and modulator stage generates BITCLK from BITCLK16 This combination supports fractional divisions of both BITCLK16 and BITCLK for baud rate generation In this mode the maximum USCI baud rate is 1 16 the UART source clock frequency BRCLK When UCBRx is set to 0 or 1 the first prescaler and modulator stage is bypassed and BRCLK is equal to BITCLK16 Modulation for BITCLK16 is based on the UCBRFx setting as shown in Table 15 3 A 1 in the table indicates that the corresponding BITCLK16 period is one BRCLK period longer than the periods m 0 The modulation restarts with each new bit timing Modulation for BITCLK is based on the UCBRSx setting as shown in Table 15 2 as previously described Table 15 3 BITCLK16 Modulation Pattern UCBRFx 00h 01h 02h 03h 04h 05h 06h 07h 08h 09h 0Ah OBh OCh 0Dh OEh OFh O GOG QC OOG OO OO OGO O OoOOoOo o ojo 2 ld nd dl do do do do do do do do do do dl O 7 No of BITCLK16 Clocks after last falling BITCLK edge 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 0 0 0 0 0 0 0 0 0
300. ddress again If a flash access occurs while BUSY 1 it is an access violation ACCVIFG will be set and the erase results will be unpredictable The flow to initiate an erase from flash from RAM is shown in Figure 7 6 Figure 7 6 Erase Cycle from Within RAM Disable watchdog Set LOCK 1 re enable Segment Erase from RAM Assumes ACCVIE MOV BIT JNZ MOV MOV MOV CLR L2 BIT JNZ MOV L1 watchdog NMIIE OFIE WDTPW WDTHOLD amp WDTCTL BUSY amp FCTL3 L1 514 kHz lt 0 Y FWKEY FSSEL1 FNO amp FCTL2 FWKEY amp FCTL3 FWKEY ERASE FCTL1 amp 0FC10h BUSY amp FCTL3 L2 FWKEY LOCK amp FCTL3 Flash Memory Controller SMCLK lt 952 kHz Disable WDT Test BUSY Loop while busy SMCLK 2 Clear LOCK Enable erase Dummy write erase S1 Test BUSY Loop while busy Done set LOCK Re enable WDT 7 9 Flash Memory Operation 7 3 3 Writing Flash Memory The write modes selected by the WRT and BLKWRT bits are listed in Table 7 1 Table 7 2 Write Modes Byte Word Write BLKWRT WRT Write Mode 0 1 Byte word write 1 1 Block write Both write modes use a sequence of individual write instructions but using the block write mode is approximately twice as fast as byte word mode because the voltage generator remains on for the complete block write Any instruction that modifies a destination can be used to modify a flash location in either byte word mode or block
301. destination BIS src dst or BIS W src dst BIS B src dst src OR dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected Status bits are not affected OSCOFF CPUOFF and GIE are not affected The six LSBs of the RAM word TOM are set BIS 003Fh TOM set the six LSBs in RAM location TOM The three MSBs of RAM byte TOM are set BIS B 0E0h TOM set the 3 MSBs in RAM location TOM 3 26 RISC 16 Bit CPU BITLW BIT B Syntax Operation Description Status Bits Mode Bits Example Example Example Instruction Set Test bits in destination Test bits in destination BIT src dst or BIT W src dst src AND dst The source and destination operands are logically ANDed The result affects only the status bits The source and destination operands are not affected N Set if MSB of result is set reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected If bit 9 of R8 is set a branch is taken to label TOM BIT 0200h R8 bit 9 of R8 set JNZ TOM Yes branch to TOM No proceed If bit 3 of R8 is set a branch is taken to label TOM BIT B 8 R8 JC TOM A serial communication receive bit RCV is tested Because the carry bit is equal to the state of the tested bit while using the BIT instruct
302. destination addresses and places the result into the destination Source Byte pointed to by R5 R5 contains address 3 579Ch for this example Destination Byte pointed to by R6 Oh which results in address 0778h for this example Before After Address Register Address Register Space Space 21038h 21036h 21034h ns esrar ne Coor7an 00778h 0077Ah 00778h 00778h 3579Dh 3579Ch 4 32 16 Bit MSP430X CPU 0000h 21038h 21036h 21034h PC R5 3579Dh R6 00778h 32h src 0077Ah 45h_ dst 77h Sum 00778h 3579Dh 3579Ch CPU Registers 4 4 7 Immediate Mode The Immediate mode allows accessing constants as operands by including the constant in the memory location following the instruction The program counter PC is used with the Indirect Autoincrement mode The PC points to the immediate value contained in the next word After the fetching of the immediate operand the PC is incremented by 2 for byte word or address word instructions The Immediate mode has two addressing possibilities J 8 or 16 bit constants with MSP430 instructions LJ 20 bit constants with MSP430X instruction MSP430 Instructions with Immediate Mode If an MSP430 instruction is used with Immediate addressing mode the constant is an 8 or 16 bit value and is stored in the word following the instruction Length Two or three words One word less if a constant of the constant generator can be used for the immediate o
303. devices 11 Digital external clock source When XTS 1 Not applicable for MSP430x20xx devices 00 0 4 1 MHz crystal or resonator 01 1 3 MHz crystal or resonator 10 3 16 MHz crystal or resonator 11 Digital external 0 4 16 MHz clock source XCAPx Bits Oscillator capacitor selection These bits select the effective capacitance 3 2 seen by the LFXT1 crystal when XTS 0 If XTS 1 or if LFCT1Sx 11 XCAPx should be 00 00 1pF 01 6pF 10 10pF 11 125pF xT20F Bit 1 XT2 oscillator fault 0 No fault condition present 1 Fault condition present LFXT10F Bit 0 LFXT1 oscillator fault 0 No fault condition present 1 Fault condition present 5 16 Basic Clock Module Basic Clock Module Registers 1E1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 OFIE Bits 7 2 Bit 1 Bits O These bits may be used by other modules See device specific data sheet Oscillator fault interrupt enable This bit enables the OFIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled This bit may be used by other modules See device specific data sheet IFG1 Interrupt Flag Register 1 7 6 5 4 3 2 1 0 rw 1 OFIFG Bits 7 2 Bit 1 Bits O These bits may be used by other modules See device specific data sheet Oscillator fault interrupt flag
304. dressing RESLO address in R5 for indirect MOV RESLO R5 MOV amp OPER1 amp MPY MOV amp OPER2 0P2 NOP MOV R5 amp XXX MOV R5 amp XXX 11 2 5 Using Interrupts 11 6 1 1 1 1 Load Load Need Move Move lst operand 2nd operand one cycle RESLO RESHI If an interrupt occurs after writing OP1 but before writing OP2 and the multiplier is used in servicing that interrupt the original multiplier mode selection is lost and the results are unpredictable To avoid this disable interrupts before using the hardware multiplier or do not use the multiplier in interrupt service routines Disable interrupts DINT NOP MOV xxh amp MPY MOV xxh amp OP2 EINT Hardware Multiplier 1 1 F 1 before using the hardware multiplier Disable interrupts Required for DINT Load 1st operand Load 2nd operand Interrupts may be enable before Process results Hardware Multiplier Registers 11 3 Hardware Multiplier Registers The hardware multiplier registers are listed in Table 11 4 Table 11 4 Hardware Multiplier Registers Register Short Form Register Type Address Initial State Operand one multiply MPY Read write 0130h Unchanged Operand one signed multiply MPYS Read write 0132h Unchanged Operand one multiply accumulate MAC Read write 0134h Unchanged Operand one signed multiply accumulate MACS Read write 0136h Unchanged Operand two OP2 Read write 0138h Unchanged Result low word
305. dst The source operand is added to the destination operand The previous content of the destination is lost N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Ten is added to the 16 bit counter CNTR located in lower 64 K ADD W 10 amp CNTR Add 10 to 16 bit counter A table word pointed to by R5 20 bit address in R5 is added to R6 The jump to label TONI is performed on a carry ADD W R5 R6 JC TONI Add table word to R6 R6 19 16 0 Jump if carry No carry A table byte pointed to by R5 20 bit address is added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 R6 19 8 0 ADD B R5 R6 JNC TONI Add byte to R6 R5 1 R6 000xxh Jump if no carry Carry occurred 4 62 16 Bit MSP430X CPU ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Add source word and carry to destination word Add source byte and carry to destination byte ADDC src dst or ADDC W src dst ADDC B src dst src dst C gt dst The source operand and the carry bit C are added to the destinati
306. e Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 040000h lt dst lt OCOOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected The 20 bit value in R7 is multiplied by 2 RLAX A R7 Shift left R7 20 bit 4 136 16 Bit MSP430X CPU RLCX A RLCX W RLCX B Syntax Operation Emulation Description Extended Instructions Rotate left through carry address word Rotate left through carry word Rotate left through carry byte RLCX A dst RLCX dst or RLCX W dst RLCX B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDCX A dst dst ADDCX dst dst ADDCX B dst dst The destination operand is shifted left one position as shown in Figure 4 46 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 4 46 Destination Operand Carry Left Shift MSB 0 Status Bits Mode Bits Example Example Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 040000h lt dst lt OCOOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 04000h lt
307. e 20 bit destination The source operand is not affected The previous content of the destination is lost Not affected OSCOFF CPUOFF and GIE are not affected Copy 20 bit value in R9 to R8 MOVA R9 R8 R9 gt R8 Write 20 bit immediate value 12345h to R12 MOVA 12345h R12 12345h gt R12 Copy 20 bit value addressed by R9 100h to R8 Source operand in ad dresses R9 100h LSBs and R9 102h MSBs MOVA 100h R9 R8 Index 32 K 2 words transferred Move 20 bit value in 20 bit absolute addresses EDE LSBs and EDE 2 MSBs to R12 MOVA amp EDE R12 amp EDE gt R12 2 words transferred Move 20 bit value in 20 bit addresses EDE LSBs and EDE 2 MSBs to R12 PC index 32 K MOVA EDE R12 EDE gt R12 2 words transferred Copy 20 bit value R9 points to 20 bit address to R8 Source operand in addresses R9 LSBs and R9 2 MSBs MOVA R9 R8 R9 gt R8 2 words transferred 16 Bit MSP430X CPU 4 165 Address Instructions Copy 20 bit value R9 points to 20 bit address to R8 R9 is incremented by four afterwards Source operand in addresses R9 LSBs and R9 2 MSBs MOVA R9 R8 R9 gt R8 R9 4 2 words transferred Copy 20 bit value in R8 to destination addressed by R9 100h Destination operand in addresses R9 100h LSBs and R9 102h MSBs MOVA R8 100h R9 Index 32 K 2 words transferred Move 20 bit value in R13 to 20 bit absolute addresses EDE LSBs a
308. e Description Length Operation Comment Example Before OFF16h OFF14h OFF12h OF018h OFO016h OF014h 01116h 01114h 01112h Assembler Code Content of ROM amp EDE TONI MOV X 0 Y 0 X EDE Y TONI Two or three words Move the contents of the source address EDE to the destination address TONI The words after the instruction contain the absolute address of the source and destination addresses With absolute mode the PC is incremented automatically so that program execution continues with the next instruction Valid for source and destination MOV amp EDE amp TONI Source address EDE 0F016h dest address TONI 01114h After Address Register Address Register Space Space Oxxxxh PC 01114h OFF16h 01114h 0FO16h OFF14h 0FO16h 04292h PC OFF12h 04292h 0A123h OFO16h 0A123h 01234h 01114h 0A123h This address mode is mainly for hardware peripheral modules that are located at an absolute fixed address These are addressed with absolute mode to ensure software transportability for example position independent code RISC 16 Bit CPU 3 13 Addressing Modes 3 3 5 Indirect Register Mode The indirect register mode is described in Table 3 8 Table 3 8 Indirect Mode Description Assembler Code Content of ROM MOV R10 0 R11 MOV R10 0 R11 Length One or two words Operation Move the contents of the source address contents of R10 to the destination address contents of
309. e Example The following software example shows an extract of the interrupt service routine to handle data receive interrupts from USCI_AO in either UART or SPI mode and state change interrupts from USCI_BO in 12C mode USCIAO_ RX USCIBO_12C STATE ISR BIT B UCAORXIFG amp IFG2 USCI_AO Receive Interrupt JNZ USCIAO RX ISR USCIBO_I2C STATE ISR Decode I2C state changes Decode I2C state changes RETI USCIAO_ RX ISR Read UCAORXBUF clears UCAORXIFG RETI The following software example shows an extract of the interrupt service routine that handles data transmit interrupts from USCI_AO in either UART or SPI mode and the data transfer interrupts from USCI_BO in 12C mode USCIAO TX USCIBO I2C DATA_ISR BIT B UCAOTXIFG amp IFG2 USCI_AO Transmit Interrupt JNZ USCIAO TX ISR USCIB0_12C_DATA ISR BIT B UCBORXIFG amp IFG2 JNZ USCIBO I2C RX USCIBO_12C_TX Write UCBOTXBUF clears UCBOTXIFG RETI USCIBO_I2C_RX Read UCBORXBUF clears UCBORXIFG RETI USCIAO_TX_ ISR Write UCAOTXBUF clears UCAOTXIFG RETI 17 24 Universal Serial Communication Interface 12C Mode USCI Registers C Mode 17 4 USCI Registers 12C Mode The USCI registers applicable in 12C mode for USCI_BO are listed in Table 17 2 and for USCI_B1 in Table 17 3 Table 17 2 USCI_BO Control and Status Registers Register Short Form Register Type Address Initial State USCI_BO control register O UCBOCTLO Read write 068h 001h with PUC USCI
310. e ISSH bit The SAMPCON signal controls the sample period and start of conversion When SAMPCON is high sampling is active The high to low SAMPCON transition starts the analog to digital conversion which requires 13 ADC12CLK cycles Two different sample timing methods are defined by control bit SHP extended sample mode and pulse mode Extended Sample Mode The extended sample mode is selected when SHP 0 The SHI signal directly controls SAMPCON and defines the length of the sample period tsample When SAMPCON is high sampling is active The high to low SAMPCON transition starts the conversion after synchronization with ADC12CLK See Figure 21 3 Figure 21 3 Extended Sample Mode Start Stop Start Conversion Sampling Sampling Conversion Complete a SHI SAMPCON 13 x ADC12CLK sample gt lt tconvert gt gt tsynci ADC12 21 7 ADC12 Operation Pulse Sample Mode The pulse sample mode is selected when SHP 1 The SHI signal is used to trigger the sampling timer The SHTOx and SHT1x bits in ADC12CTLO control the interval of the sampling timer that defines the SAMPCON sample period tsample The sampling timer keeps SAMPCON high after synchronization with AD12CLK for a programmed interval tsample The total sampling time is tsample plus tsync See Figure 21 4 The SHTx bits select the sampling time in 4x multiples of ADC12CLK SHTOx selects the sampling time for ADC12MCTLO to 7 and SHT1x selects the
311. e Loven 01778h FO00h 00778h 0479Ch 1000h 0579Ch After 1103Ah 11038h 11036h 11034h 0077Ah 00778h 0579Eh 0579Ch PC R5 0479Ch R6 01778h 32h 45h 77h The byte pointed to by R5 1000h results in address 0479Ch 1000h 0579Ch after truncation to a 16 bit address The byte pointed to by R6 FOOOh results in address 01778h FOOOh 00778h after truncation to a 16 bit address Register src dst Sum CPU Registers MSP430 Instruction with Indexed Mode in Upper Memory If the CPU register Rn points to an address above the lower 64 KB memory the Rn bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range Rn 32 KB because the index X is a signed 16 bit value In this case the address of the operand can overflow or underflow into the lower 64 KB memory space See Figure 4 16 and Figure 4 17 Figure 4 16 Indexed Mode in Upper Memory Upper Memory Rn 19 16 gt 0 19 1615 0 CPU Register Rn 16 bit signed index sign extended to 10000 20 bits OFFFF Lower 64 KB Memory address FFFFF Rn 19 0 10000 0 FFFF Rn 19 0 Rn 19 0 Lower 64 KB 16 Bit MSP430X CPU 4 19 CPU Registers Length Operation Comment Example Two or three words The sign extended 16 bit index in the next word after the instruction is added to the 20 bits of the CPU register Rn This deli
312. e USCI_Ax modules support Y UART mode _j Pulse shaping for IrDA communications Automatic baud rate detection for LIN communications Lj SPI mode The USCI_Bx modules support g 12C mode Y SPI mode 16 2 Universal Serial Communication Interface SPI Mode USCI Introduction SPI Mode 16 2 USCI Introduction SPI Mode In synchronous mode the USCI connects the MSP430 to an external system via three or four pins UCxSIMO UCxSOMI UCxCLK and UCxSTE SPI mode is selected when the UCSYNC bit is set and SPI mode 3 pin or 4 pin is selected with the UCMODEx bits SPI mode features include 7 or 8 bit data length LSB first or MSB first data transmit and receive 3 pin and 4 pin SPI operation Master or slave modes Independent transmit and receive shift registers Continuous transmit and receive operation Selectable clock polarity and phase control Programmable clock frequency in master mode Independent interrupt capability for receive and transmit E E E E E 1 Separate transmit and receive buffer registers E E E E E Slave operation in LPM4 Figure 16 1 shows the USCI when configured for SPI mode Universal Serial Communication Interface SPI Mode 16 3 USCI Introduction SPI Mode Figure 16 1 USCI Block Diagram SPI Mode Receive State Machine B gt Set UCOE UCLISTEN UCMST Receive Buffer UCx RXBUF Receive Shift Register gt gt Set UCXRXIFG UCxSOMI
313. e control 2 Timer_A capture compare 2 Timer_A interrupt vector t Not present on MSP430x20xx Devices Short Form TACTL TAR TACCTLO TACCRO TACCTL1 TACCR1 TACCTL2t TACCR2t TAIV Register Type Address Read write Read write Read write Read write Read write Read write Read write Read write Read only 0160h 0170h 0162h 0172h 0164h 0174h 0166h 0176h 012Eh Timer_A Registers Initial State Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Reset with POR Timer_A 12 19 Timer_A Registers TACTL Timer_A Control Register 15 14 13 12 11 10 9 8 ss rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 oo oOo rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bits Unused 15 10 TASSELx Bits Timer_A clock source select 9 8 00 TACLK 01 ACLK 10 SMCLK 11 INCLK IDx Bits Input divider These bits select the divider for the input clock 7 6 00 A 01 2 10 4 11 8 MCx Bits Mode control Setting MCx 00h when Timer_A is not in use conserves 5 4 power 00 Stop mode the timer is halted 01 Up mode the timer counts up to TACCRO 10 Continuous mode the timer counts up to OFFFFh 11 Up down mode the timer counts up to TACCRO then down to 0000h Unused Bit 3 Unused TACLR Bit 2 Timer_A clear Setting this bit resets TAR the clock divider and the count direction The TACLR bit is automatically reset and
314. e transmitted address the not acknowledge interrupt flag UCNACKIFG is set The master must react with either a STOP condition or a repeated START condition Setting the UCTXSTP bit will generate a STOP condition After setting UCTXSTP a NACK followed by a STOP condition is generated after reception of the data from the slave or immediately if the USCI module is currently waiting for UCBxRXBUF to be read If a master wants to receive a single byte only the UCTXSTP bit must be set while the byte is being received For this case the UCTXSTT may be polled to determine when it is cleared BIS B UCTXSTT amp UCBOCTL1 Transmit START cond POLL STT BIT B UCTXSTT amp UCBOCTL1 Poll UCTXSTT bit JC POLL STT When cleared BIS B HUCTXSTP UCBOCTL1 transmit STOP cond Setting UCTXSTT will generate a repeated START condition In this case UCTR may be set or cleared to configure transmitter or receiver and a different slave address may be written into UCBxl2CSA if desired Figure 17 13 illustrates the 12C master receiver operation gt EP oe eg ee SS Note Consecutive Master Transactions Without Repeated Start When performing multiple consecutive I2C master transactions without the repeated start feature the current transaction must be completed before the next one is initiated This can be done by ensuring that the transmit stop condition flag UCTXSTP is cleared before the next I2C transaction is initiated with setting UCTXSTT
315. ead mode copying to RAM erasing the flash segment and writing back to it from RAM The program checking the flash memory contents must be executed from RAM Executing code from flash will automatically disable the marginal read mode The marginal read modes are controlled by the MRGO and MRG1 register bits Setting MRG1 is used to detect insufficiently programmed flash cells containing a 1 erased bits Setting MRGO is used to detect insufficiently programmed flash cells containing a 0 programmed bits Only one of these bits should be set at a time Therefore a full marginal read check will require two passes of checking the flash memory content s integrity During marginal read mode the flash access speed MCLK must be limited to 1 MHz see the device specific data sheet 7 3 7 Configuring and Accessing the Flash Memory Controller The FCTLx registers are 16 bit password protected read write registers Any read or write access must use word instructions and write accesses must include the write password OA5h in the upper byte Any write to any FCTLx register with any value other than OA5h in the upper byte is a security key violation sets the KEYV flag and triggers a PUC system reset Any read of any FCTLx registers reads 096h in the upper byte Any write to FCTL1 during an erase or byte word write operation is an access violation and sets ACCVIFG Writing to FCTL1 is allowed in block write mode when WAIT 1 but writing to
316. ected V Not affected OSCOFF CPUOFF and GIE are not affected The bits 15 14 of R5 16 bit data are cleared R5 19 16 0 BIC 0C000h R5 Clear R5 19 14 bits A table word pointed to by R5 20 bit address is used to clear bits in R7 R7 19 16 0 BIC W R5 R7 Clear bits in R7 set in R5 A table byte pointed to by R5 20 bit address is used to clear bits in Port1 BIC B R5 amp P10OUT Clear I O port P1 bits set in R5 16 Bit MSP430X CPU 4 65 MSP430 Instructions BIS W BIS B Syntax Operation Description Status Bits Mode Bits Example Example Example Set bits set in source word in destination word Set bits set in source byte in destination byte BIS src dst or BIS W src dst BIS B src dst src or dst gt dst The source operand and the destination operand are logically ORed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Bits 15 and 13 of R5 16 bit data are set to one R5 19 16 0 BIS A000h R5 Set R5 bits A table word pointed to by R5 20 bit address is used to set bits in R7 R7 19 16 0 BIS W R5 R7 A table byte pointed to by R5 20 bit address is used to set bits in Port1 R5 is incremented by 1 afterwards Set bits in R7 BIS B R5 amp 8P1OUT Setl O port P1 bits R5 1 4 66 16 Bit MSP430X CPU BITLW BIT B Synta
317. ed 10 bit word offset of the jump instruction is multiplied by two sign extended to a 20 bit address and added to the 20 bit program counter This allows jumps in a range of 511 to 512 words relative to the program counter in the full 20 bit address space Jumps do not affect the status bits Table 4 6 lists and describes the eight jump instructions Figure 4 24 Format of the Conditional Jump Instructions 15 8 0 13 12 10 9 Op Code 10 Bit Signed PC Offset Table 4 6 Conditional Jump Instructions Mnemonic S Reg D Reg Operation JEQ JZ Label Jump to label if zero bit is set JNE JNZ Label Jump to label if zero bit is reset JC Label Jump to label if carry bit is set JNC Label Jump to label if carry bit is reset JN Label Jump to label if negative bit is set JGE Label Jump to label if N XOR V 0 JL Label Jump to label if N XOR V 1 JMP Label Jump to label unconditionally 4 38 16 Bit MSP430X CPU Emulated Instructions MSP430 and MSP430X Instructions In addition to the MSP430 and MSP430X instructions emulated instructions are instructions that make code easier to write and read but do not have op codes themselves Instead they are replaced automatically by the assembler with a core instruction There is no code or performance penalty for using emulated instructions The emulated instructions are listed in Table 4 7 Table 4 7 Emulated Instructions Instruction Explanation Emulation Vv C ADC B dst Ad
318. ed by UCBUSY 1 A PUC or set UCSWRST bit disables the USCI immediately and any active transfer is terminated In master mode writing to UCxTXBUF activates the bit clock generator and the data will begin to transmit In slave mode transmission begins when a master provides a clock and in 4 pin mode when the UCxSTE is in the slave active state The SPI receives data when a transmission is active Receive and transmit operations operate concurrently 16 10 Universal Serial Communication Interface SPI Mode USCI Operation SPI Mode 16 3 6 Serial Clock Control UCxCLK is provided by the master on the SPI bus When UCMST 1 the bit clock is provided by the USCI bit clock generator on the UCXCLK pin The clock used to generate the bit clock is selected with the UCSSELx bits When UCMST 0 the USCI clock is provided on the UCxCLK pin by the master the bit clock generator is not used and the UCSSELx bits are don t care The SPI receiver and transmitter operate in parallel and use the same clock source for data transfer The 16 bit value of UCBRx in the bit rate control registers UCxxBR1 and UCxxBRO is the division factor of the USCI clock source BRCLK The maximum bit clock that can be generated in master mode is BRCLK Modulation is not used in SPI mode and UCAxMCTL should be cleared when using SPI mode for USCI_A The UCAxCLK UCBxCLK frequency is given by BRCLK FBitClock UCBRx Serial Clock Polarity and Phase The
319. ed from the ADC OA 18 13 OA Registers OAxCTL1 Opamp Control Register 1 7 6 5 4 3 2 1 0 OAFBRx OAFCx OANEXT OARRIP rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 OAFBRx Bits OAx feedback resistor select 7 5 000 Tap O OR 16R 001 Tap 1 4R 12R 010 Tap 2 8R 8R 011 Tap 3 10R 6R 100 Tap 4 12R 4R 101 Tap 5 13R 3R 110 Tap 6 14R 2R 111 Tap 7 15R 1R OAFCx Bits OAx function control This bit selects the function of OAx 4 2 000 General purpose opamp 001 Unity gain buffer for three opamp differential amplifier 010 Unity gain buffer 011 Comparator 100 Non inverting PGA amplifier 101 Cascaded non inverting PGA amplifier 110 Inverting PGA amplifier 111 Differential amplifier OANEXT Bit 1 OAx inverting input externally available This bit when set connects the inverting OAx input to the external pin when the integrated resistor network is used 0 OAx inverting input not externally available 1 OAx inverting input externally available OARRIP Bit 0 OAx reverse resistor connection in comparator mode 0 Rtop is connected to AVss and Rgottom is connected to AVcc when OAFCx 3 1 Rrop is connected to AVcc and Rgottom is connected to AVss when OAFCx 3 18 14 OA Chapter 19 Comparator_A Comparator_A is an analog voltage comparator This chapter describes the operation of the Comparator_A of the 2xx family Topic Page 19 1 Comparator_A Introduction ooooccccocnrccor eee 19 2 19 2 Comparator_A Operatio
320. ed operands the program continues at Label2 Data and program in full memory range CMPA 12345h R5 Is R5 lt 12345h JL Label2 Yes 80000h lt R5 lt 12345h No 12344h lt R5 lt 7FFFFh 16 Bit MSP430X CPU 4 87 MSP430 Instructions JMP Syntax Operation Description Status Bits Mode Bits Example Example Jump unconditionally JMP label PC 2 x Offset PC The signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means an unconditional jump in the range 511 to 512 words relative to the PC in the full memory The JMP instruction may be used as a BR or BRA instruction within its limited range relative to the program counter Status bits are not affected OSCOFF CPUOFF and GIE are not affected The byte STATUS is set to 10 Then a jump to label MAINLOOP is made Data in lower 64 K program in full memory range MOV B 10 amp 8STATUS Set STATUS to 10 JMP MAINLOOP Go to main loop The interrupt vector TAIV of Timer_A3 is read and used for the program flow Program in full memory range but interrupt handlers always starts in lower 64K ADD amp TAIV PC Add Timer_A interrupt vector to PC RETI No Timer_A interrupt pending JMP IHCCR1 Timer block 1 caused interrupt JMP IHCCR2 Timer block 2 caused interrupt RETI No legal interrupt return 4 88 16 Bit MSP430X CPU JN Syntax Operation Des
321. egister where all port bits are read P1IFG is the address of the register where all interrupt events are latched MaskOK PUSH B amp P1IN BIC B SP amp P1IFG Reset only accepted flags EINT Preset port 1 interrupt flags stored on stack other interrupts are allowed BIT Mask SP JEQ MaskOK Flags are present identically to mask jump BIC Mask SP INCD SP Housekeeping inverse to PUSH instruction at the start of interrupt subroutine Corrects the stack pointer RETI DT Note Enable Interrupt The instruction following the enable interrupt instruction EINT is always executed even if an interrupt service request is pending when the interrupts are enable 3 40 RISC 16 Bit CPU INC W INC B Syntax Operation Emulation Description Status Bits Mode Bits Example Instruction Set Increment destination Increment destination INC dst or INC W dst INC B dst dst 1 gt dst ADD 1 dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The status byte STATUS of a process is
322. egisters DAC12 AMPx DAC12DF DAC12IE DAC12IFG DAC12 ENC DAC12 GRP 23 12 Bits 7 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DAC12 DAC12 amplifier setting These bits select settling time vs current consumption for the DAC12 input and output amplifiers DAC12AMPx Input Buffer 000 Off 001 Off 010 Low speed current 011 Low speed current 100 Low speed current 101 Medium speed current 110 Medium speed current 111 High speed current DAC 12 data format 0 Straight binary 1 2s complement DAC12 interrupt enable 0 Disabled 1 Enabled DAC12 Interrupt flag 0 No interrupt pending 1 Interrupt pending Output Buffer DAC12 off output high Z DAC12 off output 0 V Low speed current Medium speed current High speed current Medium speed current High speed current High speed current DAC12 enable conversion This bit enables the DAC12 module when DAC12LSELx gt 0 when DAC12LSELx 0 DAC12ENC is ignored 0 DAC12 disabled 1 DAC12 enabled DAC12 group Groups DAC12_x with the next higher DAC12_x Not used for DAC12_1 0 Not grouped 1 Grouped DAC12 Registers DAC12_xDAT DAC12 Data Register 15 14 13 12 11 10 9 8 r 0 r 0 r 0 r 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused Bits Unused These bits are always O and do not affect the DAC12 core 15 12 DAC12 Data Bits DAC12 data 11 0 DAC12 Data Format DAC12 Data 12 bit binary The DAC12
323. eikean isea ARNEE EAEE eee 15 19 15 3 12 Receive Bit Timing 0 cece ete 15 20 15 3 13 Typical Baud Rates and Errors 02 nunana annee 15 21 15 3 14 Using the USCI Module in UART Mode with Low Power Modes 15 25 15 315 USCUIINtEMUPTS coro os ic ade 15 25 15 4 USCI Registers UART Mode ooooccccccccccc ananena 15 27 xi Contents 16 Universal Serial Communication Interface SPI Mode 17 18 16 1 16 2 16 3 16 4 USCIOVEIVIEW 3 isis a A NA AA A lat USCI Introduction SPI Mode 0 0 ccc ete eee ene USCI Operation SPI Mode 0 0 ccc eect eens 16 3 1 USCI Initialization and Reset 0 0 cece eee 16 32 Character Format siii ra a a Bea daa a tans 16 3 3 Master Moderar y ieat ern 0 ccc cc eee ete ene nen eee 16 3 4 Slave MOd6 vases al geil eae eed eee ae hs ee 16 357 SPIMENMADI CO tiara Vice a anal had eR a Relea 16 3 6 Serial Clock Control 0 0 ccc ccc cee eet e enna 16 3 7 Using the SPI Mode with Low Power Modes o o ooooooooo 16 3 8 SPI Interrupts tie doe either ey wae el bare ee a N USCI Registers SPI Mode 00 cece eect eee teens Universal Serial Communication Interface I2C Mode 0020ee eens 17 1 17 2 17 3 17 4 OA 18 1 18 2 18 3 USCI Overview 0 0 cc eens USCI Introduction I2C Mode 0 0 cece eee eens USCI Operation I2C Mode 0 00 c cece tenet eens 17 3
324. entions Program examples are shown in a special typeface Glossary Glossary ACLK ADC BOR BSL CPU DAC DCO dst FLL GIE INT N 2 1 0 ISR LSB LSD LPM MAB MCLK MDB MSB MSD NMI PC POR PUC RAM SCG SFR SMCLK SP SR src TOS WDT Auxiliary Clock Analog to Digital Converter Brown Out Reset Bootstrap Loader Central Processing Unit Digital to Analog Converter Digitally Controlled Oscillator Destination Frequency Locked Loop General Interrupt Enable Integer portion of N 2 Input Output Interrupt Service Routine Least Significant Bit Least Significant Digit Low Power Mode Memory Address Bus Master Clock Memory Data Bus Most Significant Bit Most Significant Digit Non Maskable Interrupt Program Counter Power On Reset Power Up Clear Random Access Memory System Clock Generator Special Function Register Sub System Master Clock Stack Pointer Status Register Source Top of Stack Watchdog Timer See Basic Clock Module See System Resets Interrupts and Operating Modes See www ti com msp430 for application reports See RISC 16 Bit CPU See Basic Clock Module See RISC 16 Bit CPU See FLL in MSP430x4xx Family User s Guide See System Resets Interrupts and Operating Modes See Digital I O See System Resets Interrupts and Operating Modes See Basic Clock Module See System Resets Interrupts and Operating Modes See RISC 16 Bit CPU See System Resets Interrupts and Operating Modes See System R
325. ents to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set When DMADTx 0 the DMAEN bit is cleared automatically when DMAxSZ decrements to zero and must be set again for another transfer to occur In repeated single transfer mode the DMA controller remains enabled with DMAEN 1 and a transfer occurs every time a trigger occurs 6 6 DMA Controller Figure 6 3 DMA Single Transfer State Diagram DMAEN 0 DMAREQ 0 T_Size gt DMAxSZ DMADTx 0 AND DMAxSZ 0 OR DMAEN 0 ENNMI 1 OR DMAEN 0 DMAABORT 1 2 x MCLK AND NMI event DMALEVEL 1 AND Trigger 0 DMAEN 1 DMAxSZ gt T_Size DMAxSA gt T_SourceAdd DMAxDA gt T_DestAdd DMAABORT 0 Wait for Trigger Trigger AND DMALEVEL 0 OR Trigger 1 AND DMALEVEL 1 Hold CPU Transfer one word byte Decrement DMAxSZ Modify T_SourceAdd DMA Operation DMAREQ 0 A DMAxS T_Size gt DMAxSZ DMAxSA gt T_SourceAdd DMAxDA gt T_DestAdd DMADTx 4 AND DMAxSZ 0 AND DMAEN 1 Z gt 0 AND DMAEN 1 Modify T_DestAdd DMA Controller 6 7 DMA Operation Block Transfers In block transfer mode a transfer of a complete block of data occurs after one trigger When DMADTx 1 the DMAEN bit is cleared after the completion of the block transfer and must be set again before another block transfer can
326. equence SREFx Bits Select reference 6 4 000 VR AVcc and Vp AVss 001 010 011 100 101 110 111 INCHx Bits Input 3 0 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Vp Vrer and Vp AVss Vr Verer and Vp AVss Vr Veper and Vp AVss Vr AVcc and Vp Vrer_ Verer Vas Vrers and Vp Vrer Verer Vr Verer and Vp Vrer Verer Vr Verer and Vp Vrer Verer channel select AO Al A2 VeREF Vrer Verer Temperature diode AVcc AVgs 2 GND GND GND GND ADC12 21 25 ADC12 Registers ADC12IE ADC12 Interrupt Enable Register ADC12IE15 ADC12IE14 ADC12IE13 ADC12IE12 ADC12IE11 ADC12IE10 ADC12IFG9 ADC12IE8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 ADC12IEx Bits Interrupt enable These bits enable or disable the interrupt request for the 15 0 ADC12IFGx bits 0 Interrupt disabled 1 Interrupt enabled ADC12IFG ADC12 Interrupt Flag Register ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG15 IFG14 IFG13 IFG12 IFG11 IFG10 IFG9 IFG8 rw 0 rw 0 rw 0 rw 0 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 ADC12 IFG7 IFG6 IFG5 IFG4 IFG3 IFG2 IFG1 IFGO rw 0 rw 0 rw 0 ADC12IFGx Bits ADC12MEMx Interrupt flag These bits are set when corresponding 15 0 ADC12MEM x is loaded with a conversion result The ADC12IFGx bits are reset if the corresponding ADC12MEMx is accessed or may be
327. er Setting REFON 1 enables the internal reference When REF2_5V 1 the internal reference is 2 5 V the reference is 1 5 V when REF2_5V 0 The reference can be turned off to save power when not in use For proper operation the internal voltage reference generator must be supplied with storage capacitance across Vref and AVss The recommended storage capacitance is a parallel combination of 10 uF and 0 1 uF capacitors From turn on a maximum of 17 ms must be allowed for the voltage reference generator to bias the recommended storage capacitors If the internal reference generator is not used for the conversion the storage capacitors are not required o T Note Reference Decoupling Approximately 200 uA is required from any reference used by the ADC12 while the two LSBs are being resolved during a conversion A parallel combination of 10 uF and 0 1 uF capacitors is recommended for any reference used as shown in Figure 21 11 External references may be supplied for Va and Vp_ through pins Verger and Vrer_ Verer_ respectively ADC12 Operation 21 2 4 Sample and Conversion Timing An analog to digital conversion is initiated with a rising edge of the sample input signal SHI The source for SHI is selected with the SHSx bits and includes the following Y The ADC12SC bit J The Timer_A Output Unit 1 J The Timer_B Output Unit 0 J The Timer_B Output Unit 1 The polarity of the SHI signal source can be inverted with th
328. er DMA transfers are triggered as long as the trigger signal is high and the DMAEN bit remains set The trigger signal must remain high for a block or burst block transfer to complete If the trigger signal goes low during a block or burst block transfer the DMA controller is held in its current state until the trigger goes back high or until the DMA registers are modified by software If the DMA registers are not modified by software when the trigger signal goes high again the transfer resumes from where it was when the trigger signal went low When DMALEVEL 1 transfer modes selected when DMADTx 0 1 2 3 are recommended because the DMAEN bit is automatically reset after the configured transfer Halting Executing Instructions for DMA Transfers The DMAONFETCH bit controls when the CPU is halted for a DMA transfer When DMAONFETCH O the CPU is halted immediately and the transfer begins when a trigger is received When DMAONFETCH 1 the CPU finishes the currently executing instruction before the DMA controller halts the CPU and the transfer begins a A Pa BT rE Note DMAONFETCH Must Be Used When The DMA Writes To Flash If the DMA controller is used to write to flash memory the DMAONFETCH bit must be set Otherwise unpredictable operation can result Cd 6 12 DMA Controller DMA Operation Table 6 2 DMA Trigger Operation DMAxTSELx Operation 0000 0001 0010 0011 0100 0101 0110 0111 1000
329. er and selects LSB or MSB first LSB first is typically required for UART communication Figure 15 2 Character Format Mark ST DO cco D6 PA SP SP E l__J_ ______ Space 2nd Stop Bit UCSPB 1 Parity Bit UCPEN 1 Address Bit UCMODEx 10 8th Data Bit UC7BIT 0 Optional Bit Condition Universal Serial Communication Interface UART Mode 15 5 USCI Operation UART Mode 15 3 3 Asynchronous Communication Formats When two devices communicate asynchronously no multiprocessor format is required for the protocol When three or more devices communicate the USCI supports the idle line and address bit multiprocessor communication formats Idle Line Multiprocessor Format When UCMODEx 01 the idle line multiprocessor format is selected Blocks of data are separated by an idle time on the transmit or receive lines as shown in Figure 15 3 An idle receive line is detected when 10 or more continuous ones marks are received after the one or two stop bits of a character The baud rate generator is switched off after reception of an idle line until the next start edge is detected When an idle line is detected the UCIDLE bit is set The first character received after an idle period is an address character The UCIDLE bit is used as an address tag for each block of characters In idle line multiprocessor format this bit is set when a received character is an address Figure 15 3 Idle Line Format Blo
330. er is also a T switch to minimize the coupling between channels Channels that are not selected are isolated from the A D and the intermediate node is connected to analog ground AVgs so that the stray capacitance is grounded to help eliminate crosstalk The ADC12 uses the charge redistribution method When the inputs are internally switched the switching action may cause transients on the input signal These transients decay and settle before causing errant conversion Figure 21 2 Analog Multiplexer R 100 Ohm ADC12MCTLx 0 3 o gt Ax ESD Protection Analog Port Selection The ADC12 inputs are multiplexed with the port P6 pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The P6SELx bits provide the ability to disable the port pin input and output buffers P6 0 and P6 1 configured for analog input BIS B 3h amp P6SEL P6 1 and P6 0 ADC12 function ADC12 21 5 ADC12 Operation 21 2 3 Voltage Reference Generator 21 6 ADC12 The ADC12 module contains a built in voltage reference with two selectable voltage levels 1 5 V and 2 5 V Either of these reference voltages may be used internally and externally on pin Vr
331. errupt Source Interrupt Flag Priority 000h No interrupt pending 002h SD16MEMx overflow SD16CCTLx Highest SD160VIFG 004h SD16_A Interrupt SD16CCTLO SD16IFG 006h Reserved 008h Reserved 00Ah Reserved 00Ch Reserved 00Eh Reserved 010h Reserved Lowest 24 22 SD16_A Chapter 25 Embedded Emulation Module EEM This chapter describes the Embedded Emulation Module EEM that is implemented in all MSP430 flash devices Topic Page 25 1 EEM Introduction r aa a a a a e a 25 2 25 2 EEMiBullding BlockSs oe ne a a e a e s 25 4 253 EEM CONfig urationS oa a e ae E E a A E E ea E e yeti 25 6 25 1 EEM Introduction 25 1 EEM Introduction Every MSP430 flash based microcontroller implements an embedded emulation module EEM It is accessed and controlled through JTAG Each implementation is device dependent and is described in section 25 3 EEM Configurations and the device specific data sheet In general the following features are available Y Non intrusive code execution with real time breakpoint control Single step step into and step over functionality Full support of all low power modes Support for all system frequencies for all clock sources Cov O Up to eight device dependent hardware triggers breakpoints on memory address bus MAB or memory data bus MDB Up to two device dependent hardware triggers breakpoints on CPU register write accesses L Li MAB MDB and CPU register access trig
332. esets Interrupts and Operating Modes See System Resets Interrupts and Operating Modes See Basic Clock Module See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See RISC 16 Bit CPU See Watchdog Timer Register Bit Conventions Register Bit Conventions Each register is shown with a key indicating the accessibility of the each individual bit and the initial condition Register Bit Accessibility and Initial Condition Key Bit Accessibility Read write Read only Read as 0 Read as 1 Write only Write as 0 Write as 1 No register bit implemented writing a 1 results in a pulse The register bit is always read as 0 Cleared by hardware Set by hardware Condition after PUC Condition after POR vi Contents Contents INTOdUCION O EAE a a E 1 1 Tel vArchitecture rererere thee ra e tE 1 2 1 2 Flexible Clock System 0 0 ccc cece ett eee 1 2 1 3 Embedded Emulation 0 0 cece tenes 1 3 1 4 Address SPACE e5 n Lede a ceeded A Merle ae 1 4 1 41 Flash ROM ci coc e aa aa td da ee 1 4 A Celt et hatches ois sees a mack E AE REET 1 5 14 3 Peripheral Modules 0 cece eee neee 1 5 1 44 Special Function Registers SFRs 0 00 eee eee eee eee 1 5 1 4 5 Memory Organization 0 00 ccc eens 1 5 1 5 MSP430x2xx Family Enhancements 0 00 c cece eee 1 7 System Resets Interrupts and Operating Modes 0c cece eee ees 2 1 2 1 System Res
333. et and Initialization 0 0 cece tees 2 2 2 1 1 Brownout Reset BOR 0 cece eee eens 2 3 2 1 2 Device Initial Conditions After System Reset 2 0000 2 4 2 2 METUS sae cta a Sede eee et ate 2 5 2 2 1 Non Maskable Interrupts NMI 00 cece eee eee 2 6 2 2 2 Maskable Interrupts 0 0 0 cece ees 2 9 2 2 3 Interrupt Processing 0 cece ect ete tenes 2 10 2 2 4 Interrupt Vectors 00 eens 2 12 2 3 Operating Mod s cio eos gen de hated Pee ES eee ed ee 2 14 2 3 1 Entering and Exiting Low Power Modes 00 eee ee eaees 2 16 2 4 Principles for Low Power Applications 0 cee eee eee eee 2 17 2 5 Connection of Unused Pins 0 0 0 cece eee eens 2 17 RISG 16 Bit CPU is aiii A ak tain baa eae Laie 3 1 3 1 CPU Introduction aiaee raian aenn an E R ED E A es 3 2 3 2 CPU Registers dree eaea eal a a Eo io pEi ia ba 3 4 3 2 1 Program Counter PC 06 c eee eee 3 4 3 22 lt Stack Pointer SP A cass eae Gist data hee wee e 3 5 3 2 3 Status Register SR 0 0 cece eens 3 6 3 2 4 Constant Generator Registers CG1 and CG2 0005 3 7 3 2 5 General Purpose Registers R4 to R15 6 cece eee eee 3 8 3 3 Addressing Modes 00 c eee eee eee aa 3 9 3 3 1 Register Mode eta a das Ray bas decals RAS 3 10 3 32 ulndexed ModE uo coros peed eee pr Co eee ey Bide Ene E yee 3 11 3 3
334. etting the corresponding P1IFG or P2IFG flags Digital I O 8 5 Digital I O Operation Interrupt Edge Select Registers P11ES P2IES Each PxIES bit selects the interrupt edge for the corresponding I O pin Bit 0 The PxIFGx flag is set with a low to high transition Bit 1 The PxIFGx flag is set with a high to low transition SD aaa _ _ lt _ 1 Note Writing to PxIESx Writing to P1IES or P2IES can result in setting the corresponding interrupt flags PxIESx PxINx PxIFGx 0 gt 1 0 May be set 0 gt 1 1 Unchanged 1 0 0 Unchanged 1 0 1 May be set LT a Interrupt Enable P11E P2IE Each PxIE bit enables the associated PxIFG interrupt flag Bit 0 The interrupt is disabled Bit 1 The interrupt is enabled 8 2 7 Configuring Unused Port Pins Unused l O pins should be configured as l O function output direction and left unconnected on the PC board to prevent a floating input and reduce power consumption The value of the PxOUT bit is irrelevant since the pin is unconnected Alternatively the integrated pullup pulldown resistor can be enabled by setting the PXREN bit of the unused pin to prevent the floating input See chapter System Resets Interrupts and Operating Modes for termination of unused pins 8 6 Digital I O 8 3 Digital l O Registers Table 8 1 Digital I O Registers Port P1 P2 P3 P4 P5 The digital I O registers are listed in Table 8 1 Register Input Output Direction
335. evel of USICLK is low When USICKPL 1 the inactive level of USICLK is high 14 2 3 SPI Mode The USI module is configured in SPI mode when USII2C 0 Control bit USICKPL selects the inactive level of the SPI clock while USICKPH selects the clock edge on which SDO is updated and SDI is sampled Figure 14 3 shows the clock data relationship for an 8 bit MSB first transfer USIPE5 USIPE6 and USIPE7 must be set to enable the SCLK SDO and SDI port functions Figure 14 3 SPI Timing USI USI CKPH CKPL 0 0 0 1 1 0 1 1 0 X 1 X 14 6 Load USICNTx USICNTx0O 8i 7 6 5 4 3 2 4 0 SCLK SCLK SCLK SCLK USIIFG Universal Serial Interface SPI Master Mode SPI Slave Mode USI Operation The USI module is configured as SPI master by setting the master bit USIMST and clearing the 12C bit USII2C Since the master provides the clock to the slave s an appropriate clock source needs to be selected and SCLK configured as output When USIPE5 1 SCLK is automatically configured as an output When USIIFG 0 and USICNTx gt 0 clock generation is enabled and the master will begin clocking in out data using USISR Received data must be read from the shift register before new data is written into it for transmission In a typical application the USI software will read received data from USISR write new data to be transmitted to USISR and enable the module for the next transfer by wri
336. ex The four MSBs of the index are contained in the extension word the 16 LSBs are contained in the word following the instruction The CPU register is not modified Valid for source and destination The assembler calculates the register index and inserts it ADDX A 12346h R5 32100h R6 This instruction adds the 20 bit data contained in the source and the destination addresses and places the result into the destination Source Destination Two words pointed to by R5 12346h which results in address 23456h 12346h 3579Ch Two words pointed to by R6 32100h which results in address 45678h 32100h 77778h 16 Bit MSP430X CPU 4 21 CPU Registers The extension word contains the MSBs of the source index and of the destination index and the A L bit for 20 bit data The instruction word uses byte mode due to the 20 bit data length with bits A L B W 01 Before After Address Register Address Register Space Space 2103Ah 23456h 2103Ah PC R5 23456h 21038h 45678h 21038h R6 45678h 21036h 21036h 21034h 21034h 21032h 21032h 45678h 65432h src 7777Ah 32100h 7777Ah 12345h_ dst 77778h 77778h 77778h 77777h Sum 23456h 3579Eh 12346h 3579Eh 3579Ch 3579Ch 3579Ch 4 22 16 Bit MSP430X CPU CPU Registers 4 4 3 Symbolic Mode The Symbolic mode calculates the address of the operand by adding the signed index to the program counter The Symbolic mode has three addressing possibilities J Symbolic mode in lower 64
337. f own address and data bytes All are acknowledged Reception of the general call address Emap UCSTT UCSTPI FEO Ve THO Receive UCBxRXIFG 1 UCTR 0 Receiver UCSTTIFG 1 UCGC 1 Slave Transmitter Reception of own address and transmission of data bytes UCBxRXIFG 1 UCSTT UCSTPI FEO a SO UCSTTIFG 0 aed eransminer UCSTT Toe UCSTPIFG 0 Universal Serial Communication Interface 12C Mode Master Mode USCI Operation C Mode The USCI module is configured as an 12C master by selecting the 12C mode with UCMODEx 11 and UCSYNC 1 and setting the UCMST bit When the master is part of a multi master system UCMM must be set and its own address must be programmed into the UCBxl2COA register When UCA10 0 7 bit addressing is selected When UCA10 1 10 bit addressing is selected The UCGCEN bit selects if the USCI module responds to a general call 12C Master Transmitter Mode After initialization master transmitter mode is initiated by writing the desired slave address to the UCBxI2CSA register selecting the size of the slave address with the UCSLA10 bit setting UCTR for transmitter mode and setting UCTXSTT to generate a START condition The USCI module checks if the bus is available generates the START condition and transmits the slave address The UCBxTXIFG bit is set when the START condition
338. fer in progress completes before starting The DMA channel priorities are configurable with the ROUNDROBIN bit When the ROUNDROBIN bit is set the channel that completes a transfer becomes the lowest priority The order of the priority of the channels always stays the same DMAO DMA1 DMAZ2 for example DMA Priority Transfer Occurs New DMA Priority DMAO DMA1 DMA2 DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO DMA1 DMA2 DMAO When the ROUNDROBIN bit is cleared the channel priority returns to the default priority DMA Controller DMA Operation 6 2 6 DMA Transfer Cycle Time The DMA controller requires one or two MCLK clock cycles to synchronize before each single transfer or complete block or burst block transfer Each byte word transfer requires two MCLK cycles after synchronization and one cycle of wait time after the transfer Because the DMA controller uses MCLK the DMA cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DMA controller will use the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DMA controller will temporarily restart MCLK sourced with DCOCLK for the single transfer or complete block or burst block transfer The CPU remains off and after the transfer completes MCLK is turned off The maximum DMA cycle time for all operating modes is shown in
339. fered The trigger for updating the DAC 12 voltage output is selected with the DAC12LSELx bits When DAC12LSELx 0 the data latch is transparent and the DAC12_xDAT register is applied directly to the DAC12 core the DAC12 output updates immediately when new DAC12 data is written to the DAC12_xDAT register regardless of the state of the DAC12ENC bit When DAC12LSELx 1 DAC12 data is latched and applied to the DAC12 core after new data is written to DAC12_xDAT When DAC12LSELx 2 or 3 data is latched on the rising edge from the Timer_A CCR1 output or Timer_B CCR2 output respectively DAC12ENC must be set to latch the new data when DAC12LSELx gt 0 DAC12 23 5 DAC12 Operation 23 2 4 DAC12_xDAT Data Format The DAC12 supports both straight binary and 2s compliment data formats When using straight binary data format the full scale output value is OFFFh in 12 bit mode OFFh in 8 bit mode as shown in Figure 23 2 Figure 23 2 Output Voltage vs DAC12 Data 12 Bit Straight Binary Mode Output Voltage Full Scale Output DAC Data 0 OFFFh When using 2s compliment data format the range is shifted such that a DAC12_xDAT value of 0800h 0080h in 8 bit mode results in a zero output voltage 0000h is the mid scale output voltage and O7FFh 007Fh for 8 bit mode is the full scale voltage output as shown in Figure 23 3 Figure 23 3 Output Voltage vs DAC 12 Data 12 Bit 2s Compliment Mode Output Voltage Full Scale Output
340. fered UCTXADDR flag indicates if the next character loaded into UCAXTXBUF is preceded by an idle line of 11 bits UCTXADDR is automatically cleared when the start bit is generated Frame The following procedure sends out an idle frame to indicate an address character followed by associated data 1 Set UCTXADDR then write the address character to UCAxTXBUF UCAxTXBUF must be ready for new data UCAXTXIFG 1 This generates an idle period of exactly 11 bits followed by the address character UCTXADDR is reset automatically when the address character is transferred from UCAxTXBUF into the shift register 2 Write desired data characters to UCAxTXBUF UCAxTXBUF must be ready for new data UCAXTXIFG 1 The data written to UCAxTXBUF is transferred to the shift register and transmitted as soon as the shift register is ready for new data The idle line time must not be exceeded between address and data transmission or between data transmissions Otherwise the transmitted data will be misinterpreted as an address Universal Serial Communication Interface UART Mode 15 7 USCI Operation UART Mode Address Bit Multiprocessor Format 15 8 When UCMODEx 10 the address bit multiprocessor format is selected Each processed character contains an extra bit used as an address indicator shown in Figure 15 4 The first character in a block of characters carries a set address bit which indicates that the character is an address The USCI U
341. flash erase cycle A reset will abort the erase and the result will be unpredictable After the erase cycle has completed the watchdog may be re enabled 7 16 Flash Memory Controller Flash Memory Operation 7 3 5 Stopping a Write or Erase Cycle Any write or erase operation can be stopped before its normal completion by setting the emergency exit bit EMEX Setting the EMEX bit stops the active operation immediately and stops the flash controller All flash operations cease the flash returns to read mode and all bits in the FCTL1 register are reset The result of the intended operation is unpredictable 7 3 6 Marginal Read Mode The marginal read mode can be used to verify the integrity of the flash memory contents This feature is implemented in selected 2xx devices see the device specific data sheet for availability During marginal read mode marginally programmed flash memory bit locations can be detected Events that could produce this situation include improper fFre settings or violation of minimum Vcc during erase program operations One method for identifying such memory locations would be to periodically perform a checksum calculation over a section of flash memory for example a flash segment and repeating this procedure with the marginal read mode enabled If they do not match it could indicate an insufficiently programmed flash memory location It is possible to refresh the affected Flash memory segment by disabling marginal r
342. flow for the Symbolic Mode Program counter PC 16 bit signed PC index sign 10000 extended to OFFFF 20 bits Lower 64 KB Memory address SS PC 19 0 XX Y ae MAY PC 19 0 10000 PC 19 0 SS N g OFFFF F PC 19 0 Lower 64 KB SLY 16 Bit MSP430X CPU 4 25 CPU Registers 4 26 Length Operation Comment Example Two or three words The sign extended 16 bit index in the next word after the instruction is added to the 20 bits of the PC This delivers a 20 bit address which points to an address in the range O to FFFFFh The operand is the content of the addressed memory location Valid for source and destination The assembler calculates the PC index and inserts it ADD W EDE amp TONI This instruction adds the 16 bit data contained in source word EDE and destination word TONI and places the 16 bit result into the destination word TONI For this example the instruction is located at address 2 F034h Source Word EDE at address 3379Ch pointed to by PC 4766h which is the 16 bit result of 3379Ch 2FO36h 04766h Address 2F036h is the location of the index for this example Destination Word TONI located at address 00778h pointed to by the absolute address 00778h Before After Address Address Space Space 2F03Ah 2F03Ah 2F038h 2F038h 2F036h 2F036h 2F034h 2F034h 2F036h 3379Eh 04766h 3379Eh 3379Ch aero 3379Ch 5432h src 0077Ah 0077Ah 2345h_ dst 00778h 0
343. follows the signal at the pin However if the PxSELx 0 the input to the peripheral maintains the value of the input signal at the device pin before the PxSELx bit was reset Digital I O Operation 8 2 6 P1 and P2 Interrupts Each pin in ports P1 and P2 have interrupt capability configured with the PxIFG PxIE and PxIES registers All P1 pins source a single interrupt vector and all P2 pins source a different single interrupt vector The PxIFG register can be tested to determine the source of a P1 or P2 interrupt Interrupt Flag Registers P1IFG P2IFG Each PxIFGx bit is the interrupt flag for its corresponding I O pin and is set when the selected input signal edge occurs at the pin All PxIFGx interrupt flags request an interrupt when their corresponding PxIE bit and the GIE bit are set Each PxIFG flag must be reset with software Software can also set each PxIFG flag providing a way to generate a software initiated interrupt Bit 0 No interrupt is pending Bit 1 An interrupt is pending Only transitions not static levels cause interrupts If any PxIFGx flag becomes set during a Px interrupt service routine or is set after the RETI instruction of a Px interrupt service routine is executed the set PxIFGx flag generates another interrupt This ensures that each transition is acknowledged iS a on A A ee ee se A AAA Note PxIFG Flags When Changing PxOUT or PxDIR Writing to P10UT P1DIR P2OUT or P2DIR can result in s
344. g mode takes effect immediately Peripherals operating with any disabled clock are disabled until the clock becomes active The peripherals may also be disabled with their individual control register settings All I O port pins and RAM registers are unchanged Wake up is possible through all enabled interrupts 2 14 System Resets Interrupts and Operating Modes Figure 2 9 MSP430x2xx Operating Modes RST NMI Reset Active WDT Time Expired Overflow WDTIFG 1 WDTIFG 1 WDT Active Security Key Violation CPUOFF 1 SCGO 0 Peripheral SCG1 0 LPMO CPU Off MCLK Off SMCLK On ACLK On CPUOFF 1 SCGO 1 SCG1 0 CPUOFF 1 LPM1 CPU Off MCLK Off DCO off SMCLK On ACLK On SCG1 1 DC Generator Off if DCO not used for SMCLK Active Mode CPU Is Active SCGO 0 CPU Off MCLK Off SMCLK Off DCO Off ACLK On Operating Modes For Basic Clock System WDTIFG 0 Puc RST NMI is Reset Pin WDT is Active RST NMI NMI Active CPUOFF 1 OSCOFF 1 SCGO 1 SCG1 1 Modules Are Active LPM4 CPU Off MCLK Off DCO Off SMCLK Off ACLK Off DC Generator Off CPUOFF 1 SCGO 1 SCG1 1 LPM3 CPU Off MCLK Off SMCLK Off DCO Off ACLK On LPM2 DC Generator Off SCG1 SCGO OSCOFF CPUOFF Mode 0 Active 1 LPMO 0 1 0 1 LPM1 1 0 0 1 LPM2 1 1 0 1 LPM3 1 1
345. gers can be combined to form up to eight device dependent complex triggers breakpoints Lj Trigger sequencing device dependent Lj Storage of internal bus and control signals using an integrated trace buffer device dependent 3 Clock control for timers communication peripherals and other modules on a global device level or on a per module basis during an emulation stop Figure 25 1 shows a simplified block diagram of the largest currently available 2xx EEM implementation For more details on how the features of the EEM can be used together with the IAR Embedded Workbench debugger see the application report Advanced Debugging Using the Enhanced Emulation Module SLAA263 at www msp430 com Code Composer Essentials CCE and most other debuggers supporting MSP430 have the same or a similar feature set For details see the user s guide of the applicable debugger 25 2 Embedded Emulation Module EEM EEM Introduction Figure 25 1 Large Implementation of the Embedded Emulation Module EEM Trigger AND Matrix Combination Triggers Blocks q f HI HI e AAA AAA e Pe AAA AAA amp e Y O 000000 00 gt eHO MBO oto Ho MB2 CH OO MB4 LHO HHO HHO HO Ho Hale ES Trigger Sequencer HHHH HHHH CPU Stop O O OU O CI QO QO Q or gt StarvStop State Storage Embedded Emulation Module EEM 25 3 EEM Introduction
346. ginal 1 read mode is enabled Marginal read O mode This bit enables the marginal O read mode The marginal mode 0 is cleared if the CPU starts execution from the flash memory If both MRG1 and MRGO are set MRG1 is active and MRGO is ignored 0 Marginal 0 read mode is disabled 1 Marginal 0 read mode is enabled Reserved Always read as 0 Flash Memory Controller 7 25 Flash Memory Registers 1E1 Interrupt Enable Register 1 7 6 5 4 3 2 1 0 rw 0 Bits These bits may be used by other modules See the device specific data sheet 7 6 4 0 ACCVIE Bit 5 Flash memory access violation interrupt enable This bit enables the ACCVIFG interrupt Because other bits in IE1 may be used for other modules it is recommended to set or clear this bit using BIS B or BIC B instructions rather than MOV B or CLR B instructions 0 Interrupt not enabled 1 Interrupt enabled 7 26 Flash Memory Controller Chapter 8 Digital 1 O This chapter describes the operation of the digital I O ports Topic Page 8 1 Digital I O Introduction e re a e E e 8 2 8 2 Digital VO Operatiom m a a a e lentes 8 3 8 3 Digital VO Registers o onn eaae e e ele ieee e a lio 8 7 8 1 Digital I O Introduction 8 1 Digital I O Introduction 8 2 Digital I O MSP430 devices have up to eight digital I O ports implemented P1 to P7 Each port has eight I O pins Every I O pin is individually configurable for input or output direction and each I O li
347. gister TACCRO Use of the Up Down Figure 12 9 12 10 OFFFFh TACCRO TACCR1 TACCR2 Oh TAIFG EQUO TAIFG Timer_A When changing TACCRO while the timer is running and counting in the down direction the timer continues its descent until it reaches zero The value in TACCRO is latched into TACLO immediately however the new period takes effect after the counter counts down to zero When the timer is counting in the up direction and the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period before counting down When the timer is counting in the up direction and the new period is less than the current count value the timer begins counting down However one additional count may occur before the counter begins counting down Mode The up down mode supports applications that require dead times between output signals See section Timer_A Output Unit For example to avoid overload conditions two outputs driving an H bridge must never be in a high state simultaneously In the example shown in Figure 12 9 the tgeag is tdead timer X TACCR1 TACCR2 With tuead Time during which both outputs need to be inactive timer Cycle time of the timer clock TACCRx Content of capture compare register x The TACCRx registers are not buffered They update immediately when written to Therefore any required dead time will not be maintained automatically O
348. gister carry bit C is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If C is set the next instruction following the jump is executed JNC jump if no carry lower is used for the comparison of unsigned numbers 0 to 65536 Status bits are not affected The result in R6 is added in BUFFER If an overflow occurs an error handling routine at address ERROR is used ADD R6 BUFFER BUFFER R6 gt BUFFER JNC CONT No carry jump to CONT ots Error handler start ee Continue with normal program flow Branch to STL2 if byte STATUS contains 1 or 0 CMPB 2 STATUS JLO STL2 STATUS lt 2 weeds STATUS gt 2 continue here 3 50 RISC 16 Bit CPU JNE JNZ Syntax Operation Description Status Bits Example Instruction Set Jump if not equal Jump if not zero JNE label JNZ label If Z 0 PC 2 x offset gt PC If Z 1 execute following instruction The status register zero bit Z is tested If it is reset the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is set the next instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 and R8 have different contents CMP R7 R8 COMPARE R7 WITH R8 JNE TONI if different jump ae if equal continue RISC 16 Bit CPU 3 51 Instruction Set MOV W MOV B Syntax Operation Description Status
349. gnize the instruction RLC OR5 RLC B R5 or RLC B R5 It must be substituted by ADDC R5 2 R5 ADDC B R5 1 R5 or ADDC B R5 0 R5 Lt eo 16 Bit MSP430X CPU 4 99 MSP430 Instructions RRA W RRA B Syntax Operation Description Status Bits Mode Bits Example Example Rotate Right Arithmetically destination word Rotate Right Arithmetically destination byte RRA B dst or RRA W dst MSB gt MSB gt MSB 1 gt LSB 1 gt LSB gt C The destination operand is shifted right arithmetically by one bit position as shown in Figure 4 40 The MSB retains its value sign RRA operates equal to a signed division by 2 The MSB is retained and shifted into the MSB 1 The LSB 1 is shifted into the LSB The previous LSB is shifted into the carry bit C N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset OSCOFF CPUOFF and GIE are not affected The signed 16 bit number in R5 is shifted arithmetically right one position RRA R5 R5 2 gt R5 The signed RAM byte EDE is shifted arithmetically right one position RRA B EDE EDE 2 gt EDE Figure 4 40 Rotate Right Arithmetically RRA B and RRA W 19 15 7 0 fp gt 19 15 op Ly 4 100 16 Bit MSP430X CPU RRC W RRC B Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Rotate Rig
350. gth and the CPU cycles for reset interrupts and subroutines Table 4 8 Interrupt Return and Reset Cycles and Length Execution Time Length of Action MCLK Cycles Instruction Words Return from interrupt RETI 3t 1 Return from subroutine RET 3 1 Interrupt request service cycles 5 needed before 15 instruction WDT reset 4 Reset RST NMI 4 t The cycle count in MSP430 CPU is 5 The cycle count in MSP430 CPU is 6 4 40 16 Bit MSP430X CPU MSP430 and MSP430X Instructions Format II Single Operand Instruction Cycles and Lengths Table 4 9 lists the length and the CPU cycles for all addressing modes of the MSP430 single operand instructions Table 4 9 MSP430 Format ll Instruction Cycles and Length No of Cycles Length of Instruction Example Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL Instruction Example Rn 1 3 3t 1 SWPB R5 Rn 3 3t 4 1 RRC R9 Rn 3 3t 4t 1 SWPB R10 N n a 3t 4 2 CALL LABEL X Rn 4 4 4 2 CALL 2 R7 EDE 4 4t 4 2 PUSH EDE amp EDE 4 4t 4 2 SXT amp EDE t The cycle count in MSP430 CPU is 4 The cycle count in MSP430 CPU is 5 Also the cycle count is 5 for X Rn addressing mode when Rn SP Jump Instructions Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 16 Bit MSP430X CPU 4 41 MSP430 and MSP430X Instructions Format I Double Operand Instruction Cycle
351. h the next decimation step of the digital filter After these bits are modified the next three conversions may be invalid due to the settling time of the digital filter This can be handled automatically with the SD16INTDLYx bits When SD16INTDLY 00h conversion interrupt requests will not begin until the 4 conversion after a start condition On devices implementing the high impedance input buffer it can be enabled using the SD16BUFx bits The speed settings are selected based on the SD16_A modulator frequency as shown in Table 24 1 Table 24 1 High Input Impedance Buffer SD16BUFx Buffer SD16 Modulator Frequency fm 00 Buffer disabled 01 Low speed current fm lt 200kHz 10 Medium speed current 200kHz lt fm lt 700kHz 11 High speed current 700kHz lt fig lt 1 1MHz An external RC anti aliasing filter is recommended for the SD16_A to prevent aliasing of the input signal The cutoff frequency should be lt 10 kHz for a 1 Mhz modulator clock and OSR 256 The cutoff frequency may set to a lower frequency for applications that have lower bandwidth requirements SD16_A 24 5 SD16_A Operation 24 2 6 Analog Input Characteristics The SD16_A uses a switched capacitor input stage that appears as an impedance to external circuitry as shown in Figure 24 2 Figure 24 2 Analog Input Equivalent Circuit MSP430 Vs Positive external source voltage Rs 1kQ Vs Negative external source voltage v oo Rs External source resistance at
352. he USISTP flag USISTP is cleared by writing a value gt O to the USICNTx bits when USIIFGCC 0 or directly by software 14 12 Universal Serial Interface 14 3 USI Registers The USI registers are listed in Table 14 1 Table 14 1 USI Registers Register USI control register 0 USI control register 1 USI clock control USI bit counter USI low byte shift register USI high byte shift register Short Form USICTLO USICTL1 USICKCTL USICNT USISRL USISRH The USI registers can be Table 14 2 Table 14 2 Word Access to USI Registers Register USI control register USI clock and counter control register USI shift register Short Form USICTL USICCTL USISR Register Type Read write Read write Read write Read write Read write Read write Address 078h 079h 07Ah 07Bh 07Ch 07Dh USI Registers Initial State 01h with PUC 01h with PUC Reset with PUC Reset with PUC Unchanged Unchanged accessed with word instructions as shown in High Byte Register USICTL1 USICNT USISRH Universal Serial Interface Low Byte Register USICTLO USICKCTL USISRL Address 078h 07Ah 07Ch 14 13 USI Registers USICTLO USI Control Register 0 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 USIPE7 Bit 7 USI SDI SDA port enable Input in SPI mode input or open drain output in 12 mode 0 USI function disabled 1 USI function enabled USIPE6 Bit 6 USI SDO SCL port enable Output in SPI mode i
353. he values are equal The next table byte is addressed CMPX B OR5 8P1IN JEQ TONI Compare P1 bits with table R5 1 Equal contents Not equal Note Use CMPA for the following two cases for better density and execution CMPA Rsrc Rdst or CMPA imm20 Radst 16 Bit MSP430X CPU 4 121 Extended Instructions DADCX A DADCX W DADCX B Syntax Operation Emulation Description Status Bits Mode Bits Example 4 122 Add carry decimally to destination address word Add carry decimally to destination word Add carry decimally to destination byte DADCX A dst DADCX dst or DADCX W src dst DADCX B dst dst C gt dst decimally DADDX A 0 dst DADDX 0 dst DADDX B 0 dst The carry bit C is added decimally to the destination N Set if MSB of result is 1 address word gt 79999h word gt 7999h byte gt 79h reset if MSB is O Z Set if result is zero reset otherwise C Set if the BCD result is too large address word gt 99999h word gt 9999h byte gt 99h reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The 40 bit counter pointed to by R12 and R13 is incremented decimally DADDX A DADCX A 1 0 R12 0 R13 Increment lower 20 bits Add carry to upper 20 bits 16 Bit MSP430X CPU DADDX A DADDX W DADDX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Add sour
354. herwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected Test if bit 16 or 15 of R5 20 bit data is set Jump to label TONI if so BITX A 018000h R5 JNZ TONI Test R5 16 15 bits At least one bit is set Both are reset A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set BITX W R5 R7 JC TONI Test bits in R7 C not Z At least one is set Both are reset A table byte pointed to by R5 20 bit address is used to test bits in input Port1 Jump to label TONI if no bit is set The next table byte is addressed BITX B R5 amp P1IN JNC TONI Test input P1 bits R5 1 No corresponding input bit is set At least one bit is set 16 Bit MSP430X CPU 4 119 Extended Instructions CLRX A CLRX W CLRX B Syntax Operation Emulation Description Status Bits Example Clear destination address word Clear destination word Clear destination byte CLRX A CLRX CLRX B 0 gt dst MOVX A MOVX MOVX B dst dst or CLRX W dst dst 0 dst 0 dst 0 dst The destination operand is cleared Status bits are not affected RAM address word TONI is cleared CLRX A 4 120 16 Bit MSP430X CPU TONI 0 gt TONI CMPX A CMPX W CMPX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Compare source address word an
355. ht through carry destination word Rotate Right through carry destination byte RRC dst or RRC W dst RRC B dst C gt MSB gt MSB 1 gt LSB 1 gt LSB gt C The destination operand is shifted right by one bit position as shown in Figure 4 41 The carry bit C is shifted into the MSB and the LSB is shifted into the carry bit C N Set if result is negative MSB 1 reset otherwise MSB 0 Z Set if result is zero reset otherwise C Loaded from the LSB V Reset OSCOFF CPUOFF and GIE are not affected RAM word EDE is shifted right one bit position The MSB is loaded with 1 SETC Prepare carry for MSB RRC EDE EDE EDE 1 8000h Figure 4 41 Rotate Right through Carry RRC B and RRC W 19 15 7 0 19 15 E Lp 16 Bit MSP430X CPU 4 101 MSP430 Instructions SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst or SBC B dst SBC W dst dst OFFFFh C gt dst dst OFFh C gt dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1
356. iRTXCLK IrDA receive input UCAxRXD polarity 0 IrDA transceiver delivers a high pulse when a light pulse is seen 1 IrDA transceiver delivers a low pulse when a light pulse is seen IrDA receive filter enabled 0 Receive filter disabled 1 Receive filter enabled Universal Serial Communication Interface UART Mode 15 33 USCI Registers UART Mode UCAxABCTL USCI_Ax Auto Baud Rate Control Register 7 r 0 Reserved UCDELIMx UCSTOE UCBTOE Reserved UCABDEN 15 34 6 5 4 3 2 1 0 r 0 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 Bits Reserved 7 6 Bits Break synch delimiter length 5 4 00 1 bit time 01 2bit times 10 3bittimes 11 4 bit times Bit 3 Synch field time out error 0 No error 1 Length of synch field exceeded measurable time Bit 2 Break time out error 0 No error 1 Length of break field exceeded 22 bit times Bit 1 Reserved Bit O Automatic baud rate detect enable 0 Baud rate detection disabled Length of break and synch field is not measured 1 Baud rate detection enabled Length of break and synch field is measured and baud rate settings are changed accordingly Universal Serial Communication Interface UART Mode USCI Registers UART Mode 1E2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 UCAOTXIE UCAORXIE Bits 7 2 Bit 1 Bit O These bits may be used by other modules see the device specific data sheet USCI_AO transmit interrupt enable 0 Interrupt disabled 1 Inter
357. imer_A 12 2 5 Output Unit Timer_A Operation Each capture compare block contains an output unit The output unit is used to generate output signals such as PWM signals Each output unit has eight operating modes that generate signals based on the EQUO and EQUx signals Output Modes The output modes are defined by the OUTMODx bits and are described in Table 12 2 The OUTx signal is changed with the rising edge of the timer clock for all modes except mode 0 Output modes 2 3 6 and 7 are not useful for output unit O because EQUx EQUO Table 12 2 Output Modes OUTMODx 000 001 010 011 100 101 110 111 Mode Output Set Toggle Reset Set Reset Toggle Reset Toggle Set Reset Set Description The output signal OUTx is defined by the OUTx bit The OUTx signal updates immediately when OUTx is updated The output is set when the timer counts to the TACCRx value It remains set until a reset of the timer or until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRXx value It is reset when the timer counts to the TACCRO value The output is set when the timer counts to the TACCRx value It is reset when the timer counts to the TACCRO value The output is toggled when the timer counts to the TACCRXx value The output period is double the timer period The output is reset when the timer counts to the TACCRx value It remain
358. iming Generator Write and erase operations are controlled by the flash timing generator shown in Figure 7 3 The flash timing generator operating frequency fere must be in the range from 257 kHz to 476 kHz see device specific data sheet Figure 7 3 Flash Memory Timing Generator Block Diagram ACLK MCLK SMCLK SMCLK FSSELx NI FNO PUC EMEX 00 01 Reset 10 Flash Timing Generator 11 BUSY WAIT Flash Memory Controller 7 5 Flash Memory Operation Flash Timing Generator Clock Selection The flash timing generator can be sourced from ACLK SMCLK or MCLK The selected clock source should be divided using the FNx bits to meet the frequency requirements for frrg If the fera frequency deviates from the specification during the write or erase operation the result of the write or erase may be unpredictable or the flash memory may be stressed above the limits of reliable operation If a clock failure is detected during a write or erase operation the operation is aborted the FAIL flag is set and the result of the operation is unpredictable While a write or erase operation is active the selected clock source can not be disabled by putting the MSP430 into a low power mode The selected clock source will remain active until the operation is completed before being disabled 7 6 Flash Memory Controller Flash Memory Operation 7 3 2 Erasing Flash Memory The erased level of a flash memory bit is 1 Each bit can be programmed
359. in the RAM byte CNT is incremented by one CLRC clear carry DADD B 1 CNT increment decimal counter or SETC DADD B 0 CNT DADC B CNT 3 36 RISC 16 Bit CPU DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Instruction Set Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 gt dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF CPUOFF and GIE are not affected R10 is decremented by 1 DEC R10 Decrement R10 Move a block of 255 bytes from memory location starting with EDE to memory location starting with TONI Tables should not overlap start of destination address TONI must not be within the range EDE to EDE OFEh L 1 MOV EDE R6 MOV 255 R10 MOV B 2 R6 TONI EDE 1 R6 DEC R10 JNZ L 1 Do not transfer tables using the routine above with the overlap shown in Figure 3 12 Figure 3 12 Decrement Overlap EDE gt TONI EDE 254 TONI 254 RISC 16 Bit CPU 3 37 Instruction Set DECD W DEC
360. inals If the terminal is more positive than the terminal the comparator output CAOUT is high The comparator can be switched on or off using control bit CAON The comparator should be switched off when not in use to reduce current consumption When the comparator is switched off the CAOUT is always low Switches The analog input switches connect or disconnect the two comparator input terminals to associated port pins using the P2CAx bits Both comparator terminal inputs can be controlled individually The P2CAx bits allow UU Application of an external signal to the and terminals of the comparator 3 Routing of an internal reference voltage to an associated output port pin Internally the input switch is constructed as a T switch to suppress distortion in the signal path h Note Comparator Input Connection When the comparator is on the input terminals should be connected to a signal power or ground Otherwise floating levels may cause unexpected interrupts and increased current consumption laa e The CAEX bit controls the input multiplexer exchanging which input signals are connected to the comparator s and terminals Additionally when the comparator terminals are exchanged the output signal from the comparator is inverted This allows the user to determine or compensate for the comparator input offset voltage 19 4 Comparator_A Comparato
361. incremented When it is equal to 11 a branch to OVFL is taken INC B STATUS CMP B 11 STATUS JEQ OVFL RISC 16 Bit CPU 3 41 Instruction Set INCD W INCD B Syntax Operation Emulation Emulation Example Status Bits Mode Bits Example Example Double increment destination Double increment destination INCD dst or INCD W dst INCD B dst dst 2 gt dst ADD 2 dst ADD B 2 dst The destination operand is incremented by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFEh reset otherwise Set if dst contained OFEh reset otherwise C Set if dst contained OFFFEh or OFFFFh reset otherwise Set if dst contained OFEh or OFFh reset otherwise V Set if dst contained O7FFEh or O7FFFh reset otherwise Set if dst contained 07Eh or 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two 3 42 RISC 16 Bit CPU INV W INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example Instruction Set
362. ing ADC12MEMx memory register is loaded with a conversion result An interrupt request is generated if the corresponding ADC12IEx bit and the GIE bit are set The ADC120V condition occurs when a conversion result is written to any ADC12MEMx before its previous conversion result was read The ADC12TOV condition is generated when another sample and conversion is requested before the current conversion is completed The DMA is triggered after the conversion in single channel modes or after the completion of a sequence of chamnel modes ADC12IV Interrupt Vector Generator 21 18 ADC12 All ADC12 interrupt sources are prioritized and combined to source a single interrupt vector The interrupt vector register ADC12IV is used to determine which enabled ADC12 interrupt source requested an interrupt The highest priority enabled ADC12 interrupt generates a number in the ADC12IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled ADC12 interrupts do not affect the ADC12IV value Any access read or write of the ADC12IV register automatically resets the ADC120V condition or the ADC12TOV condition if either was the highest pending interrupt Neither interrupt condition has an accessible interrupt flag The ADC12IFGx flags are not reset by an ADC12IV access ADC12IFGx bits are reset automatically by accessing their associated ADC12MEMx registe
363. instruction RLA R5 RLA B R5 or RLA B R5 It must be substituted by ADD R5 2 RK5 ADD B R5 1 R5 or ADD B R5 0 R5 t e 4 98 16 Bit MSP430X CPU RLC W RLC B Syntax Operation Emulation Description MSP430 Instructions Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure 4 39 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 4 39 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example 0 a Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5x2 C gt R5 The input P1IN 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information gt Carry RLC R5 Carry P0in 1 gt LSB of R5 The MEM LEO content is shifted left one position RLC B LEO Mem LEO x 2 C gt Mem LEO ee ee ere Note RLC and RLC B Substitution The assembler does not reco
364. interval timer mode at expiration of the selected timer interval and the WDTIFG enable bit WDTIE remains unchanged When the WDTIE bit and the GIE bit are set the WDTIFG flag requests an interrupt The WDTIFG interrupt flag is automatically reset when its interrupt request is serviced or may be reset by software The interrupt vector address in interval timer mode is different from that in watchdog mode Watchdog Timer Watchdog Timer Operation Note Modifying the Watchdog timer The WDT interval should be changed together with WDTCNTCL 1 ina single instruction to avoid an unexpected immediate PUC or interrupt The WDT should be halted before changing the clock source to avoid a possible incorrect interval 10 2 4 Watchdog Timer Interrupts The WDT uses two bits in the SFRs for interrupt control Y The WDT interrupt flag WDTIFG located in IFG1 0 _ The WDT interrupt enable WDTIE located in IE1 0 When using the WDT in the watchdog mode the WDTIFG flag sources a reset vector interrupt The WDTIFG can be used by the reset interrupt service routine to determine if the watchdog caused the device to reset If the flag is set then the watchdog timer initiated the reset condition either by timing out or by a security key violation If WDTIFG is cleared the reset was caused by a different source When using the WDT in interval timer mode the WDTIFG flag is set after the selected time interval and reque
365. into UCAxRXBUF When UCRXEIE 1 characters are received into UCAxRXBUF and any applicable error bit is set When UCFE UCPE UCOE UCBRK or UCRXERR is set the bit remains set until user software resets it or UCAxRXBUF is read UCOE must be reset by reading UCAxRXBUF Otherwise it will not function properly To detect overflows reliably the following flow is recommended After a character is received and UCAXRXIFG is set first read UCAXSTAT to check the error flags including the overflow flag UCOE Read UCAxRXBUF next This will clear all Universal Serial Communication Interface UART Mode 15 13 USCI Operation UART Mode error flags except UCOE if UCAxRXBUF was overwritten between the read access to UCAXSTAT and to UCAxRXBUF The UCOE flag should be checked after reading UCAxRXBUF to detect this condition Note that in this case the UCRXERR flag is not set 15 3 7 USCI Receive Enable The USCI module is enabled by clearing the UCSWRST bit and the receiver is ready and in an idle state The receive baud rate generator is in a ready state but is not clocked nor producing any clocks The falling edge of the start bit enables the baud rate generator and the UART state machine checks for a valid start bit If no valid start bit is detected the UART state machine returns to its idle state and the baud rate generator is turned off again If a valid start bit is detected a character will be received When the idle line multiprocessor mode
366. ion C Mode 17 2 USCI Introduction I2C Mode In 12C mode the USCI module provides an interface between the MSP430 and 12C compatible devices connected by way of the two wire 12C serial bus External components attached to the 12C bus serially transmit and or receive serial data to from the USCI module through the 2 wire 12C interface The 12C mode features include Y Compliance to the Philips Semiconductor I C specification v2 1 7 bit and 10 bit device addressing modes General call START RESTART STOP Multi master transmitter receiver mode Slave receiver transmitter mode Standard mode up to100 kbps and fast mode up to 400 kbps support Programmable UCxCLK frequency in master mode Designed for low power Slave receiver START detection for auto wake up from LPMx modes DUDO O Slave operation in LPM4 Figure 17 1 shows the USCI when configured in 12C mode Universal Serial Communication Interface C Mode 17 3 USCI Introduction I7C Mode Figure 17 1 USCI Block Diagram I C Mode UC1CLK ACLK SMCLK SMCLK 17 4 UCA10 UCGCEN Own Address UC10A UCxSDA Receive Shift Register Receive Buffer UC1RXBUF 12C State Machine Transmit Buffer UC1TXBUF Transmit Shift Register Slave Address UC1SA UCSLA10 UCxSCL Bit Clock Generator UCxBRx 16 gt Prescaler Divider Universal Serial Communication Interface 12C Mode USCI Operation C M
367. ion Item n SP SP PCretun Stack before RET Stack after RET instruction instruction 4 96 16 Bit MSP430X CPU RETI Syntax Operation Description Status Bits Mode Bits Example MSP430 Instructions Return from interrupt RETI SP gt SR 15 0 Restore saved status register SR with PC 19 16 SP 2 gt SP SP gt PC 15 0 Restore saved program counter PC 15 0 SP 2 gt SP House keeping The status register is restored to the value at the beginning of the interrupt service routine This includes the four MSBs of the program counter PC 19 16 The stack pointer is incremented by two afterwards The 20 bit PC is restored from PC 19 16 from same stack location as the status bits and PC 15 0 The 20 bit program counter is restored to the value at the beginning of the interrupt service routine The program continues at the address following the last executed instruction when the interrupt was granted The stack pointer is incremented by two afterwards N restored from stack Z restored from stack C restored from stack V restored from stack OSCOFF CPUOFF and GIE are restored from stack Interrupt handler in the lower 64 K A 20 bit return address is stored on the stack INTRPT PUSHM A 2 R14 Save R14 and R13 20 bit data A Interrupt handler code POPM A 2 R14 Restore R13 and R14 20 bit data RETI Return to 20 bit address in full memory range 16 Bit MSP430X CPU 4 97 MSP430 Instructions
368. ion Status Bits Mode Bits Example Extended Instructions Rotate Right unsigned the 20 bit operand Rotate Right unsigned the 16 bit operand Rotate Right unsigned the 8 bit operand RRUX A Rdst RRUX W Rast RRUX Rdst RRUX B Radst C 0 MSB gt MSB 1 gt LSB 1 LSB gt C RRUX is valid for register Mode only the destination operand is shifted right by one bit position as shown in Figure 4 54 The word instruction RRUX W clears the bits Rdst 19 16 The byte instruction RRUX B clears the bits Rdst 19 8 Zero is shifted into the MSB the LSB is shifted into the carry bit N Set if result is negative A dst 19 1 reset if dst 19 0 W dst 15 1 reset if dst 15 0 B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset OSCOFF CPUOFF and GIE are not affected The word in R6 is shifted right by twelve positions RPT 12 RRUX W R6 R6 R6 12 R6 19 16 0 Figure 4 54 Rotate Right Unsigned RRUX B A Register Mode 19 8 7 0 er ee 0 19 16 15 19 0 T 16 Bit MSP430X CPU 4 145 Extended Instructions SBCX A SBCX W SBCX B Syntax Operation Emulation Description Status Bits Mode Bits Example 4 146 Subtract source and borrow NOT carry from destination address word Subtract source and borrow NOT carry from destination word Subtract source and borrow NOT carry from destination b
369. ion to test a single bit the carry bit is used by the subsequent instruction the read information is shifted into register RECBUF Serial communication with LSB is shifted first gt XXXX XXXX XXXX XXXX BIT B RCV RCCTL Bit info into carry RRC RECBUF Carry gt MSB of RECBUF CXXX XXXX raii repeat previous two instructions ERA 8 times gt cccc CCCC z A A MSB LSB Serial communication with MSB shifted first BIT B RCV RCCTL Bit info into carry RLC B RECBUF Carry gt LSB of RECBUF XXXX XXXC wastes repeat previous two instructions SRA 8 times gt CCCC cccc LSB MSB RISC 16 Bit CPU 3 27 Instruction Set BR BRANCH Syntax Operation Emulation Description Status Bits Example Branch to destination BR dst dst gt PC MOV dst PC An unconditional branch is taken to an address anywhere in the 64K address space All source addressing modes can be used The branch instruction is a word instruction Status bits are not affected Examples for all addressing modes are given BR HEXEC Branch to label EXEC or direct branch e g 0A4h Core instruction MOV PC PC BR EXEC Branch to the address contained in EXEC Core instruction MOV X PC PC Indirect address BR amp EXEC _ Branch to the address contained in absolute address EXEC Core instruction MOV X 0 PC Indirect address BR R5 Branch to the address contained in R5 Core instruction MOV R5 PC
370. iption Register Mode for the destination the destination operand is shifted right by one bit position as shown in Figure 4 51 The word instruction RRCX W clears the bits Rdst 19 16 the byte instruction RRCX B clears the bits Rdst 19 8 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All other modes for the destination the destination operand is shifted right by one bit position as shown in Figure 4 52 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit All addressing modes with the ex ception of the Immediate Mode are possible in the full memory Status Bits N Set if result is negative A dst 19 1 reset if dst 19 O W dst 15 1 reset if dst 15 O B dst 7 1 reset if dst 7 0 Z Set if result is zero reset otherwise C Loaded from LSB V Reset Mode Bits OSCOFF CPUOFF and GIE are not affected 4 142 16 Bit MSP430X CPU Extended Instructions Example The 20 bit operand at address EDE is shifted right by one position The MSB is loaded with 1 SETC Prepare carry for MSB RRCX A EDE EDE EDE 1 80000h Example The word in R6 is shifted right by twelve positions RPT 12 RRCX W R6 R6 R6 12 R6 19 16 0 Figure 4 51 Rotate Right Through Carry RRCX B A Register Mode 19 8 7 0 CA O e 19 16 15 19 0 fH E Figure 4 52 Rotate Right Through Carry RRCX B A Non Register Mode 7 0
371. is protected with a fuse Blowing the fuse completely disables the JTAG port and is not reversible Further access to the device via JTAG is not possible For more details see the Application report Programming a Flash Based MSP430 Using the JTAG Interface at www msp430 com Programming Flash Memory via the Bootstrap loader BSL Most MSP430 flash devices contain a bootstrap loader Refer to the device specific data sheet for implementation details The BSL enables users to read or program the flash memory or RAM using a UART serial interface Access to the MSP430 flash memory via the BSL is protected by a 256 bit user defined password For more details see the Application report Features of the MSP430 Bootstrap Loader at www ti com msp430 7 18 Flash Memory Controller Flash Memory Operation Programming Flash Memory via a Custom Solution The ability of the MSP430 CPU to write to its own flash memory allows for in system and external custom programming solutions as shown in Figure 7 12 The user can choose to provide data to the MSP430 through any means available UART SPI etc User developed software can receive the data and program the flash memory Since this type of solution is developed by the user it can be completely customized to fit the application needs for programming erasing or updating the flash memory Figure 7 12 User Developed Programming Solution Flash Memory Commands data etc CPU executes Host a MSP43
372. is recommended This is illustrated in Figure 12 10 Figure 12 10 Capture Signal SCS 1 CCl 7 Capture Set TACCRx CCIFG l Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 12 11 COV must be reset with software Timer_A 12 11 Timer_A Operation Figure 12 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TACCTLx Second Capture Taken COV 1 Idle Capture Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TACCTLx Setup TACCTLx XOR CCISO amp TACCTLx TACCTLx TAR Compare Mode The compare mode is selected when CAP 0 The compare mode is used to generate PWM output signals or interrupts at specific time intervals When TAR counts to the value in a TACCRx Y Interrupt flag CCIFG is set Y Internal signal EQUx 1 Y EQUx affects the output according to the output mode J The input signal CCI is latched into SCCI 12 12 T
373. is selected with UCMODEx 01 the UART state machine checks for an idle line after receiving a character If a start bit is detected another character is received Otherwise the UCIDLE flag is set after 10 ones are received and the UART state machine returns to its idle state and the baud rate generator is turned off Receive Data Glitch Suppression Glitch suppression prevents the USCI from being accidentally started Any glitch on UCAxRXD shorter than the deglitch time t approximately 150 ns will be ignored by the USCI and further action will be initiated as shown in Figure 15 8 See the device specific data sheet for parameters Figure 15 8 Glitch Suppression USCI Receive Not Started 15 14 URXDx URXS S JERE When a glitch is longer than t or a valid start bit occurs on UCAxRXD the USCI receive operation is started and a majority vote is taken as shown in Figure 15 9 If the majority vote fails to detect a start bit the USCI halts character reception Universal Serial Communication Interface UART Mode USCI Operation UART Mode Figure 15 9 Glitch Suppression USCI Activated Majority Vote Taken 15 3 8 USCI Transmit Enable The USCI module is enabled by clearing the UCSWRST bit and the transmitter is ready and in an idle state The transmit baud rate generator is ready but is not clocked nor producing any clocks A transmission is initiated by writing data to UCAxTXBUF When this occurs the baud rate ge
374. is used to prevent conflicts with another master and controls the master as described in Table 16 1 When UCxSTE is in the master inactive state 1 UCxSIMO and UCxCLK are set to inputs and no longer drive the bus 3 The error bit UCFE is set indicating a communication integrity violation to be handled by the user _j The internal state machines are reset and the shift operation is aborted If data is written into UCxTXBUF while the master is held inactive by UCxSTE it will be transmit as soon as UCxSTE transitions to the master active state If an active transfer is aborted by UCXSTE transitioning to the master inactive state the data must be re written into UCxTXBUF to be transferred when UCxSTE transitions back to the master active state The UCxSTE input signal is not used in 3 pin master mode 16 8 Universal Serial Communication Interface SPI Mode 16 3 4 Slave Mode USCI Operation SPI Mode Figure 16 3 USCI Slave and External Master MASTER COMMON SPI SPI Receive Buffer Receive Buffer UCxRXBUF Data Shift Register DSR Receive Shift Register UCxCLK MSP430 USCI Figure 16 3 shows the USCI as a slave in both 3 pin and 4 pin configurations UCxCLK is used as the input for the SPI clock and must be supplied by the external master The data transfer rate is determined by this clock and not by the internal bit clock generator Data written to UCxTXBUF and moved to the TX shift register before the start
375. itial MSP430 conditions are Lj a Software Initialization 2 4 The RST NMI pin is configured in the reset mode I O pins are switched to input mode as described in the Digital I O chapter Other peripheral modules and registers are initialized as described in their respective chapters in this manual Status register SR is reset The watchdog timer powers up active in watchdog mode Program counter PC is loaded with address contained at reset vector location OFFFEh If the reset vectors content is OFFFFh the device will be disabled for minimum power consumption After a system reset user software must initialize the MSP430 for the application requirements The following must occur E m a Initialize the SP typically to the top of RAM Initialize the watchdog to the requirements of the application Configure peripheral modules to the requirements of the application Additionally the watchdog timer oscillator fault and flash memory flags can be evaluated to determine the source of the reset System Resets Interrupts and Operating Modes System Reset and Initialization 2 2 Interrupts The interrupt priorities are fixed and defined by the arrangement of the modules in the connection chain as shown in Figure 2 3 The nearer a module is to the CPU NMIRS the higher the priority Interrupt priorities determine what interrupt is taken when more than one interrupt is pending simultaneously There are three
376. its are not affected The P1IN 1 signal is used to define or control the program flow BIT B 02h amp P1IN State of signal gt Carry JC PROGA If carry 1 then execute program routine A aio Carry 0 execute program here R5 is compared to 15 If the content is higher or the same branch to LABEL CMP 15 R5 JHS LABEL Jump is taken if R5 gt 15 sien Continue here if R5 lt 15 3 44 RISC 16 Bit CPU JEQ JZ Syntax Operation Description Status Bits Example Example Example Instruction Set Jump if equal jump if zero JEQ label JZ label If Z 1 PC 2x offset gt PC If Z 0 execute following instruction The status register zero bit Z is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If Z is not set the instruction following the jump is executed Status bits are not affected Jump to address TONI if R7 contains zero TST R7 Test R7 JZ TONI if zero JUMP Jump to address LEO if R6 is equal to the table contents CMP R6 Table R5 Compare content of R6 with content of MEM table address content of R5 JEQ LEO Jump if both data are equal pete No data are not equal continue here Branch to LABEL if R5 is O TST R5 JZ LABEL RISC 16 Bit CPU 3 45 Instruction Set JGE Syntax Operation Description Status Bits Example Jump if greater or equal JGE label If N XOR V 0 then jump to label P
377. itting instruction where needed The following sections list and describe the MSP430 and MSP430X instructions 16 Bit MSP430X CPU 4 35 MSP430 and MSP430X Instructions 4 5 1 MSP430 Instructions The MSP430 instructions can be used regardless if the program resides in the lower 64 KB or beyond it The only exceptions are the instructions CALL and RET which are limited to the lower 64 KB address range CALLA and RETA instructions have been added to the MSP430X CPU to handle subroutines in the entire address range with no code size overhead MSP430 Double Operand Format I Instructions Figure 4 22 shows the format of the MSP430 double operand instructions Source and destination words are appended for the Indexed Symbolic Absolute and Immediate modes Table 4 4 lists the twelve MSP430 double operand instructions Figure 4 22 MSP430 Double Operand Instruction Format 15 12 11 8 7 6 5 4 0 Source or Destination 15 0 Destination 15 0 Table 4 4 MSP430 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg V N Zz C MOV B src dst src gt dst ADD B src dst src dst dst s i 7 ADDC B src dst src dst C gt dst dl z SUB B src dst dst not src 1 gt dst Es j SUBC B src dst dst not src C gt dst E 7 7 CMP B src dst dst src i i E DADD B src dst src dst C gt dst decimally j i ES BIT B src dst src and dst 0 E Z BIC B src dst not src and d
378. ivider These six bits select the divider for the flash 5 0 controller clock The divisor value is FNx 1 For example when FNx 00h the divisor is 1 When FNx O3Fh the divisor is 64 7 22 Flash Memory Controller Flash Memory Registers FCTL3 Flash Memory Control Register FCTL3 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as OA5h FAIL LOCKA EMEX LOCK WAIT ACCVIFG KEYV BUSY r w 0 r w r w 0 FWKEYx FAIL LOCKA EMEX LOCK WAIT ACCVIFG Bits 15 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 FCTLx password Always read as 096h Must be written as OA5h or a PUC will be generated Operation failure This bit is set if the fera clock source fails or a flash operation is aborted from an interrupt when EEIEX 1 FAIL must be reset with software 0 No failure 1 Failure SegmentA and Info lock Write a 1 to this bit to change its state Writing O has no effect 0 Segment A unlocked and all information memory is erased during a mass erase 1 Segment A locked and all information memory is protected from erasure during a mass erase Emergency exit 0 No emergency exit 1 Emergency exit Lock This bit unlocks the flash memory for writing or erasing The LOCK bit can be set anytime during a byte word write or erase operation and the operation will complete normally In the block write mode if the LOCK bit is set while BLKWRT WAIT 1 then BLKWRT and WAIT are reset and the mode
379. k is provided by the external master It is possible to operate the USCI in SPI slave mode while the device is in LPM4 and all clock sources are disabled The receive or transmit interrupt can wake up the CPU from any low power mode Universal Serial Communication Interface SPI Mode USCI Operation SPI Mode 16 3 8 SPI Interrupts The USCI has one interrupt vector for transmission and one interrupt vector for reception SPI Transmit Interrupt Operation The UCxTXIFG interrupt flag is set by the transmitter to indicate that UCxTXBUF is ready to accept another character An interrupt request is generated if UCxTXIE and GIE are also set UCxTXIFG is automatically reset if a character is written to UCxTXBUF UCxTXIFG is set after a PUC or when UCSWRST 1 UCxTXIE is reset after a PUC or when UCSWRST 1 _ ooo zz A E OO OO lt lt a Note Writing to UCxTXBUF in SPI Mode Data written to UCxTXBUF when UCxTXIFG 0 may result in erroneous data transmission a ee SPI Receive Interrupt Operation The UCxRXIFG interrupt flag is set each time a character is received and loaded into UCxRXBUF An interrupt request is generated if UCxRXIE and GIE are also set UCxRXIFG and UCXxRXIE are reset by a system reset PUC signal or when UCSWRST 1 UCxRXIFG is automatically reset when UCxRXBUF is read Universal Serial Communication Interface SPI Mode 16 13 USCI Operation SPI Mode USCI Interrupt Usage USCI_Ax and USCI_B
380. l Communication Interface UART Mode UCRXERR UCPE UCFE UCOE Set UCORXIFG UCLISTEN UCORX C UCOTX USCI Operation UART Mode 15 3 USCI Operation UART Mode In UART mode the USCI transmits and receives characters at a bit rate asynchronous to another device Timing for each character is based on the selected baud rate of the USCI The transmit and receive functions use the same baud rate frequency 15 3 1 USCI Initialization and Reset The USCI is reset by a PUC or by setting the UCSWRST bit After a PUC the UCSWRST bit is automatically set keeping the USCI in a reset condition When set the UCSWRST bit resets the UCAxRXIE UCAxTXIE UCAxRXIFG UCRXERR UCBRK UCPE UCOE UCFE UCSTOE and UCBTOE bits and sets the UCAxTXIFG bit Clearing UCSWRST releases the USCI for operation Note Initializing or Re Configuring the USCI Module The recommended USCI initialization re configuration process is 1 Set UCSWRST BIS B UCSWRST UCAXCTL1 2 Initialize all USCI registers with UCSWRST 1 including UCAxCTL1 3 Configure ports 4 Clear UCSWRST via software BIC B HUCSWRST UCAXCTL1 5 Enable interrupts optional via UCAXRXIE and or UCAXTXIE 15 3 2 Character Format The UART character format shown in Figure 15 2 consists of a start bit seven or eight data bits an even odd no parity bit an address bit address bit mode and one or two stop bits The UCMSB bit controls the direction of the transf
381. l changes when the timer equals TACCRx in either count direction and when the timer equals TACCRO depending on the output mode An example is shown in Figure 12 14 using TACCRO and TACCR2 Figure 12 14 Output Example Timer in Up Down Mode OFFFFh TACCRO TACCR2 Oh EQU2 EQU2 EQU2 EQU2 TAIFG EQUO TAIFG EQUO Interrupt Events a Note Switching Between Output Modes When switching between output modes one of the OUTMODx bits should remain set during the transition unless switching to mode O Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS OUTMOD_7 amp TACCTLx Set output mode 7 BIC HOUTMODx amp TACCTLx Clear unwanted bits ee 12 16 Timer_A Timer_A Operation 12 2 6 Timer_A Interrupts TACCRO Interrupt Two interrupt vectors are associated with the 16 bit Timer_A module Y TACCRO interrupt vector for TACCRO CCIFG 1 TAIV interrupt vector for all other CCIFG flags and TAIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TACCRx register In compare mode any CCIFG flag is set if TAR counts to the associated TACCRx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set The TACCRO CCIFG flag has the highest Timer_
382. l legal regulatory and safety related requirements concerning their products and any use of TI products in such safety critical applications notwithstanding any applications related information or support that may be provided by TI Further Buyers must fully indemnify TI and its representatives against any damages arising out of the use of TI products in such safety critical applications TI products are neither designed nor intended for use in military aerospace applications or environments unless the TI products are specifically designated by TI as military grade or enhanced plastic Only products designated by TI as military grade meet military specifications Buyers acknowledge and agree that any such use of TI products which TI has not designated as military grade is solely at the Buyer s risk and that they are solely responsible for compliance with all legal and regulatory requirements in connection with such use TI products are neither designed nor intended for use in automotive applications or environments unless the specific TI products are designated by TI as compliant with ISO TS 16949 requirements Buyers acknowledge and agree that if they use any non designated products in automotive applications Tl will not be responsible for any failure to meet such requirements Following are URLs where you can obtain information on other Texas Instruments products and application solutions Products Applications Amplifiers amplifier ti c
383. l subtraction Subtract R5 from R6 decimally Assume that R5 03987h and R6 04137h ADD 06666h R5 Move content R5 from 0 9 to 6 OFh R5 03987h 06666h O9FEDh INV R5 Invert this result back to 0 9 R5 NOT R5 06012h SETC Prepare carry 1 DADD R5 R6 Emulate subtraction by addition of 010000h R5 1 R6 R6 R5 1 R6 0150h RISC 16 Bit CPU 3 63 Instruction Set SETN Syntax Operation Emulation Description Status Bits Mode Bits Set negative bit SETN 1 gt N BIS 4 SR The negative bit N is set N Set Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected 3 64 RISC 16 Bit CPU Instruction Set SETZ Set zero bit Syntax SETZ Operation 1 gt Z Emulation BIS 2 SR Description The zero bit Z is set Status Bits N Not affected Z Set C Not affected V Not affected Mode Bits OSCOFF CPUOFF and GIE are not affected RISC 16 Bit CPU 3 65 Instruction Set SUB W SUB B Syntax Operation Description Status Bits Mode Bits Example Example Subtract source from destination Subtract source from destination SUB src dst or SUB W src dst SUB B src dst dst NOT src 1 gt dst or dst src gt dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the constant 1 The source operand is not affected The previous contents of the desti
384. latches with synchronized loading Oo ee oO Interrupt vector register for fast decoding of all Timer_B interrupts The block diagram of Timer_B is shown in Figure 13 1 ___ Note Use of the Word Count Count is used throughout this chapter It means the counter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action does not take place 13 1 1 Similarities and Differences From Timer_A 13 2 Timer_B Timer_B is identical to Timer_A with the following exceptions _j The length of Timer_B is programmable to be 8 10 12 or 16 bits Lj Timer_B TBCCRx registers are double buffered and can be grouped _j All Timer_B outputs can be put into a high impedance state J The SCCI bit function is not implemented in Timer_B Figure 13 1 Timer_B Block Diagram Timer_B Introduction i i Timer Block TBSSELx D Timer Clock MCx 15 0 i Ez i TBCLK 00 ivi 16 bit Timer 1 a Hs KP ren ac mods eoo i a Clear 8 10 12 16 SMCLK 10 CNTLx i Do 11 TBCLR 00 i TBCLGRPx 1 01 ie Set TBIFG Li Group 11 Load Logic CCRO CCR1 CCR2 CCR3 CCR4 CCR5 CCR6 CCI6A 00 Capture CCI6B 01 Mode GND 10 Timer Clock gt Sync al VCC 11 CLLDx CCl Group Load Logic TBR 0 EQUO y Compare Latch TBCL6 Ly EQU6 CAP e Set TBCCR6 CCIFG OUT Output Unit
385. lator when crystal accurate time keeping is not required The MCLK can be configured to operate from the on chip DCO that can be activated when requested by interrupt driven events The SMCLK can be configured to operate from a crystal or the DCO depending on peripheral requirements A flexible clock distribution and divider system is provided to fine tune the individual clock requirements Internal Very Low Power Low Frequency Oscillator The internal very low power low frequency oscillator VLO provides a typical frequency of 12kHz see device specific data sheet for parameters without requiring a crystal VLOCLK source is selected by setting LFXT1Sx 10 when XTS 0 The OSCOFF bit disables the VLO for LPM4 The LFXT1 crystal oscillators are disabled when the VLO is selected reducing current consumption The VLO consumes no power when not being used Basic Clock Module Basic Clock Module Operation 5 2 3 LFXT1 Oscillator The LFXT1 oscillator supports ultralow current consumption using a 32 768 Hz watch crystal in LF mode XTS 0 A watch crystal connects to XIN and XOUT without any other external components The software selectable XCAPx bits configure the internally provided load capacitance for the LFXT1 crystal in LF mode This capacitance can be selected as 1pF 6pF 10pF or 12 5pF typical Additional external capacitors can be added if necessary The LFXT1 oscillator also supports high speed crystals or resonators when in
386. le automatically detects framing errors parity errors overrun errors and break conditions when receiving characters The bits UCFE UCPE UCOE and UCBRK are set when their respective condition is detected When the error flags UCFE UCPE or UCOE are set UCRXERR is also set The error conditions are described in Table 15 1 Table 15 1 Receive Error Conditions Error Condition Error Description Flag A framing error occurs when a low stop bit is detected When two stop bits are used both stop bits are checked for framing error When a framing error is detected the UCFE bit is set A parity error is a mismatch between the number of 1s in a character and the value of the parity bit When an address bit is included in the character it is included in the parity calculation When a parity error is detected the UCPE bit is set An overrun error occurs when a character is loaded into UCAxRXBUF before the prior character has been read When an overrun occurs the UCOE bit is set When not using automatic baud rate detection a break is detected when all data parity and stop bits are low When a break condition is Break condition UCBRK detected the UCBRK bit is set A break condition can also set the interrupt flag UCAXxRXIFG if the break interrupt enable UCBRKIE bit is set Framing error UCFE Parity error UCPE Receive overrun UCOE When UCRXEIE O and a framing error or parity error is detected no character is received
387. les for all addressing modes of the MSP430X extended format l instructions 4 54 16 Bit MSP430X CPU MSP430X Extended Instructions Table 4 18 MSP430X Format 1 Instruction Cycles and Length No of Length of Addressing Mode Cycles Instruction Source Destination B W A B W A Examples Rn Rmt 2 2 2 BITX B R5 R8 PC 3 3 2 ADDX R9 PC X Rm 5t 78 3 ANDX A R5 4 R6 EDE 5H 78 3 XORX R8 EDE amp EDE 5 78 3 BITX W R5 amp EDE Rn Rm 3 4 2 BITX R5 R8 PC 3 4 2 ADDX R9 PC X Rm 6t 9S 3 ANDX A R5 4 R6 EDE 6t gS 3 XORX R8 EDE amp EDE 6t gS 3 BITX B R5 amp EDE Rn Rm 3 4 2 BITX R5 R8 PC 4 5 2 ADDX A R9 PC X Rm 6t gS 3 ANDX R5 4 R6 EDE 6t gS 3 XORX B R8 EDE amp EDE 6t 9S 3 BITX R5 amp EDE N Rm 3 3 3 BITX 20 R8 Pct 4 4 3 ADDX A FE000h PC X Rm 6t gs 4 ANDX 1234 4 R6 EDE 6t gs 4 XORX A5A5h EDE amp EDE 6t g 4 BITX B 12 8EDE X Rn Rm 4 5 3 BITX 2 R5 R8 Pci 5 6 3 SUBX A 2 R6 PC X Rm 7 108 4 ANDX 4 R7 4 R6 EDE 7 108 4 XORX B 2 R6 EDE amp EDE 7 108 4 BITX 8 SP amp EDE EDE Rm 4 5 3 BITX B EDE R8 PC 5 6 3 ADDX A EDE PC X Rm 7 108 4 ANDX EDE 4 R6 EDE 7 108 4 ANDX EDE TONI 8 TONI 7 108 4 BITX EDE amp TONI amp EDE Rm 4 5 3 BITX amp EDE R8 Pct 5 6 3 ADDX A amp EDE PC X Rm 7 108 4 ANDX B amp EDE 4 R6 TONI 7 108 4 XORX amp EDE TONI amp TONI 7 108 4 BITX amp EDE amp TONI T Repeat instructions require n 1 cycles where n is the number of times the instruction is executed Reduce
388. lted 01 Up The timer repeatedly counts from zero to the value of TACCRO 10 Continuous The timer repeatedly counts from zero to OFFFFh 11 Up down The timer repeatedly counts from zero up to the value of TACCRO and back down to zero Timer_A 12 5 Timer_A Operation Up Mode The up mode is used if the timer period must be different from OFFFFh counts The timer repeatedly counts up to the value of compare register TACCRO which defines the period as shown in Figure 12 2 The number of timer counts in the period is TACCRO 1 When the timer value equals TACCRO the timer restarts counting from zero If up mode is selected when the timer value is greater than TACCRO the timer immediately restarts counting from zero Figure 12 2 Up Mode OFFFFh TACCRO Oh The TACCRO CCIFG interrupt flag is set when the timer counts to the TACCRO value The TAIFG interrupt flag is set when the timer counts from TACCRO to zero Figure 12 3 shows the flag set cycle Figure 12 3 Up Mode Flag Setting Timer Clock Timer Set TAIFG i l l Set TACCRO CCIFG r l Changing the Period Register TACCRO 12 6 Timer_A When changing TACCRO while the timer is running if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before
389. mally The OFIFG oscillator fault flag is set and latched at POR or when an oscillator fault LFXT1OF or XT2OF is detected When OFIFG is set MCLK is sourced from the DCO and if OFIE is set the OFIFG requests an NMI interrupt When the interrupt is granted the OFIE is reset automatically The OFIFG flag must be cleared by software The source of the fault can be identified by checking the individual fault bits If a fault is detected for the crystal oscillator sourcing the MCLK the MCLK is automatically switched to the DCO for its clock source This does not change the SELMx bit settings This condition must be handled by user software Figure 5 7 Oscillator Fault Logic 5 10 LF_OscFault XTS B gt LFXT10F XT2OF Set OFIFG Flag 2 XT1_OscFault XT2_OscFault Basic Clock Module Sourcing MCLK from a Crystal Basic Clock Module Operation After a PUC the basic clock module uses DCOCLK for MCLK If required MCLK may be sourced from LFXT1 or XT2 The sequence to switch the MCLK source from the DCO clock to the crystal clock LFXT1CLK or XT2CLK is 1 Switch on the crystal oscillator and select appropriate mode 2 Clear the OFIFG flag 3 Wait at least 50 us 4 Test OFIFG and repeat steps 1 4 until OFIFG remains cleared BIC W OSCOFF SR j BIS B XTS amp BCSCTL1 MOV B LFXT1S0 amp BCSCTL3 L1 BIC B OFIFG amp IFG1 j MOV W 0FFh R15 L2 DEC W R15 j JNZ L
390. matically when UCxRXBUF is read and must not be cleared by software Otherwise it will not function correctly 0 No error 1 Overrun error occurred Unused Bits Unused 4 1 UCBUSY Bit 0 USCI busy This bit indicates if a transmit or receive operation is in progress 0 USCI inactive 1 USCI transmitting or receiving 16 20 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UCAxRXBUF USCI_Ax Receive Buffer Register UCBxRXBUF USCI_Bx Receive Buffer Register 7 6 5 4 3 2 1 0 r r r r r r r r UCRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UCxRXBUF resets the receive error bits and UCxRXIFG In 7 bit data mode UCxRXBUF is LSB justified and the MSB is always reset UCAxTXBUF USCI_Ax Transmit Buffer Register UCBxTXBUF USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to 7 0 be moved into the transmit shift register and transmitted Writing to the transmit data buffer clears UCXTXIFG The MSB of UCxTXBUF is not used for 7 bit data and is reset Universal Serial Communication Interface SPI Mode 16 21 USCI Registers SPI Mode 1E2 Interrupt Enable Register 2 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 UCBOTXIE UCBORXIE UCAOTXIE UCAORXIE 16 22 Bits 7 4 Bit 3 Bit 2 Bit 1 Bit O
391. mber of transfers for a block The block start address is defined anywhere in the MSP430 address range using the 16 bit register ADC10SA The block ends at ADC10SA 2n 2 The one block transfer mode is shown in Figure 20 9 Figure 20 9 One Block Transfer 20 16 ADC10 TB 0 n th transfer ADC10SA 2n 2 ADC10SA 2n 4 km 2nd transfer ADC10SA 2 1st transfer ADC10SA DTC The internal address pointer is initially equal to ADC10SA and the internal transfer counter is initially equal to n The internal pointer and counter are not visible to software The DTC transfers the word value of ADC10MEM to the address pointer ADC10SA After each DTC transfer the internal address pointer is incremented by two and the internal transfer counter is decremented by one The DTC transfers continue with each loading of ADC10MEM until the internal transfer counter becomes equal to zero No additional DTC transfers will occur until a write to ADC10SA When using the DTC in the one block mode the ADC10IFG flag is set only after a complete block has been transferred Figure 20 10 shows a state diagram of the one block mode ADC10 Operation Figure 20 10 State Diagram for Data Transfer Control in One Block Transfer Mode n 0 ADC10DTC1 n 0 Wait for write to ADC10SA Initialize Prepare Start Address in ADC10SA DTC 5 ll o 1 Write to ADC10SA n is latched in counter x Write to ADC10SA or n 0
392. mode for the source and destination but any valid combination of source and destination addressing modes is possible in an instruction iv es pees gg Bas A ST Sse te E Note Use of Labels EDE TONI TOM and LEO Throughout MSP430 documentation EDE TONI TOM and LEO are used as generic labels They are only labels They have no special meaning 4 14 16 Bit MSP430X CPU CPU Registers 4 4 1 Register Mode Operation The operand is the 8 16 or 20 bit content of the used CPU register Length One two or three words Comment Valid for source and destination Byte operation Byte operation reads only the 8 LSBs of the source register Rsrc and writes the result to the 8 LSBs of the destination register Rdst The bits Rdst 19 8 are cleared The register Rsrc is not modified Word operation Word operation reads the 16 LSBs of the source register Rsrc and writes the result to the 16 LSBs of the destination register Rdst The bits Rdst 19 16 are cleared The register Rsrc is not modified Address Word operation Address word operation reads the 20 bits of the source register Rsrc and writes the result to the 20 bits of the destination register Rdst The register Rsrc is not modified SXT Exception The SXT instruction is the only exception for register operation The sign of the low byte in bit 7 is extended to the bits Rdst 19 8 Example BIS W R5 R6 This instruction logically ORs the 16 bit data contained in R5 wi
393. mple Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SBC dst or SBC W dst SBC B dst dst OFFFFh C gt dst dst OFFh C gt dst SUBC 0 dst SUBC B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 16 bit counter pointed to by R13 is subtracted from a 32 bit counter pointed to by R12 SUB R13 0 R12 SBC 2 R12 Subtract LSDs Subtract carry from MSD The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUB B R13 0 R12 SBC B 1 R12 Subtract LSDs Subtract carry from MSD Te Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 LT a 3 62 RISC 16 Bit CPU SETC Syntax Operation Emulation Description Status Bits Mode Bits Example DSUB Instruction Set Set carry bit SETC 1 gt C BIS 1 SR The carry bit C is set N Not affected Z Not affected C Set V Not affected OSCOFF CPUOFF and GIE are not affected Emulation of the decima
394. n ocooccocccccncnnnn 19 4 19 3 Comparator_A Registers aa e E 19 10 19 1 Comparator_A Introduction 19 1 Comparator_A Introduction 19 2 The Comparator_A module supports precision slope analog to digital conversions supply voltage supervision and monitoring of external analog signals Features of Comparator_A include a E m a E m m m Inverting and non inverting terminal input multiplexer Software selectable RC filter for the comparator output Output provided to Timer_A capture input Software control of the port input buffer Interrupt capability Selectable reference voltage generator Comparator and reference generator can be powered down Input Multiplexer The Comparator_A block diagram is shown in Figure 19 1 Comparator_A Comparator_A Introduction Figure 19 1 Comparator_A Block Diagram P2CA4 P2CAO 00 CAO 01 CA1 10 caex Yt 0 a caon CA2 11 E CAF iam e E pco IN Dt Heal Haan ae CA1 CA2 CA3 CA4 CA5 CA6 CA7 Set_CAIFG Tau 2 0ns OV CAREFx 5 0 5xVCC 01 op JL 0 25xVCC 11 P2CA3 P2CA2 P2CA1 CARSEL Comparator_A 19 3 Comparator_A Operation 19 2 Comparator_A Operation 19 2 1 Comparator 19 2 2 Input Analog The Comparator_A module is configured with user software The setup and operation of Comparator_A is discussed in the following sections The comparator compares the analog voltages at the and input term
395. n 24 4 SD16_A The SD16_A is designed for low power applications When the SD16_A is not actively converting it is automatically disabled and automatically re enabled when a conversion is started The reference is not automatically disabled but can be disabled by setting SD16REFON O When the SD16_A or reference are disabled they consume no current SD16_A Operation 24 2 5 Analog Input Pair Selection Analog Input Setup The SD16_A can convert up to 8 differential input pairs multiplexed into the PGA Up to five analog input pairs AO A4 are available externally on the device A resistive divider to measure the supply voltage is available using the A5 multiplexer input An internal temperature sensor is available using the A6 multiplexer input Input A7 is a shorted connection between the and input pair and can be used to calibrate the offset of the SD16_A input stage The analog input is configured using the SD16INCTLO and the SD16AE registers The SD16INCHx bits select one of eight differential input pairs of the analog multiplexer The gain for the PGA is selected by the SD16GAINx bits A total of six gain settings are available The SD16AEx bits enable or disable the analog input pin Setting any SD16AEx bit disables the multiplexed digital circuitry for the associated pin See the device specific data sheet for pin diagrams During conversion any modification to the SD16INCHx and SD16GAINx bits will become effective wit
396. n Description Status Bits Mode Bits Example Example Save a single address word on the stack Save a single word on the stack Save a single byte on the stack PUSHX A src PUSHX src or PUSHX W src PUSHX B src Save the 8 16 20 bit value of the source operand on the TOS 20 bit addresses are possible The stack pointer SP is decremented by two byte and word operands or by four address word operand before the write operation The stack pointer is decremented by two byte and word operands or by four address word operand Then the source operand is written to the TOS All seven addressing modes are possible for the source operand Note This instruction does not use the extension word Not affected OSCOFF CPUOFF and GIE are not affected Save the byte at the 20 bit address amp EDE on the stack PUSHX B amp EDE Save byte at address EDE Save the 20 bit value in R9 on the stack PUSHX A R9 Save address word in R9 4 134 16 Bit MSP430X CPU RLAM A RLAM W Syntax Operation Description Status Bits Mode Bits Example Extended Instructions Rotate Left Arithmetically the 20 bit CPU register content Rotate Left Arithmetically the 16 bit CPU register content RLAM A n Rdst 1 lt n lt 4 RLAM W _ n Rdst or RLAM n Rdst 1 lt n lt 4 C lt MSB lt MSB 1 LSB 1 LSB 0 The destination operand is shifted arithmetically left one two three or four positions as shown in Figure 4 4
397. n the MSP430 CPU The MSP430X CPU is completely backwards compatible with the MSP430 CPU The MSP430X CPU features include Lj a a E RISC architecture Orthogonal architecture Full register access including program counter status register and stack pointer Single cycle register operations Large register file reduces fetches to memory 20 bit address bus allows direct access and branching throughout the entire memory range without paging 16 bit data bus allows direct manipulation of word wide arguments Constant generator provides the six most often used immediate values and reduces code size Direct memory to memory transfers without intermediate register holding Byte word and 20 bit address word addressing The block diagram of the MSP430X CPU is shown in Figure 4 1 16 Bit MSP430X CPU Figure 4 1 MSP430X CPU Block Diagram 16 MDB Memory Data Bus Zx 19 16 15 y RO PC Program Counter E MU O a R1 SP Pointer Stack o gt R2 SR Status Register R3 CG2 Constant Generator gt SESE DC AH R5 General Purpose M E a AH R7 General Purpose SEE O IS R9 General Purpose arm f gt A _ _ R11 General Purpose ee R12 General Purpose OI lt 7 R13 General a A 4 R14 General Pa E ae General a gt Memory Address Bus MAB ZN j ee Zero Z Carry C A Overtlow V 16 20 bit ALU K MCLK Negative N NY CPU Int
398. n in watchdog mode only A Flash memory security key violation E Y Watchdog timer security key violation E E A CPU instruction fetch from the peripheral address range Oh 01FFh 2 2 System Resets Interrupts and Operating Modes System Reset and Initialization 2 1 1 Brownout Reset BOR The brownout reset circuit detects low supply voltages such as when a supply voltage is applied to or removed from the Vcc terminal The brownout reset circuit resets the device by triggering a POR signal when power is applied or removed The operating levels are shown in Figure 2 2 The POR signal becomes active when Vcc crosses the Vcc stan level It remains active until Vcc crosses the V g_ r threshold and the delay t gor elapses The delay t gor is adaptive being longer for a slow ramping Vcc The hysteresis Vhys B_1Tr ensures that the supply voltage must drop below V B_IT to generate another POR signal from the brownout reset circuitry Figure 2 2 Brownout Timing V B_IT V B_IT Vec start Set Signal for POR circuitry A UBOR As the Vig t level is significantly above the Vmin level of the POR circuit the BOR provides a reset for power failures where Vcc does not fall below Vmin See device specific data sheet for parameters System Resets Interrupts and Operating Modes 2 3 System Reset and Initialization 2 1 2 Device Initial Conditions After System Reset After a POR the in
399. n procedure is in progress when a repeated START condition or STOP condition is transmitted on SDA the master transmitters involved in arbitration must send the repeated START condition or STOP condition at the same position in the format frame Arbitration is not allowed between 1 A repeated START condition and a data bit LJ A STOP condition and a data bit Y A repeated START condition and a STOP condition 17 20 Universal Serial Communication Interface 1 C Mode USCI Operation C Mode 17 3 5 12C Clock Generation and Synchronization The 12C clock SCL is provided by the master on the 12C bus When the USCI is in master mode BITCLK is provided by the USCI bit clock generator and the clock source is selected with the UCSSELx bits In slave mode the bit clock generator is not used and the UCSSELx bits are don t care The 16 bit value of UCBRx in registers UCBxBR1 and UCBXxBRO is the division factor of the USCI clock source BRCLK The maximum bit clock that can be used in single master mode is fgrcLK 4 In multi master mode the maximum bit clock is fgrcLk 8 The BITCLK frequency is given by BRCLK FBitClock UCBRx The minimum high and low periods of the generated SCL are UCBRx 2 tLowmn tHicHmin 7 When UCBRx is even and BRCLK UCBRx 1 2 tLowmin tHiGH MIN a S when UCBRx is odd BRCLK The USCI clock source frequency and the prescaler setting UCBRx must to be chosen such that the minimum low and high period time
400. n word Not affected OSCOFF CPUOFF and GIE are not affected Save the five 20 bit registers R9 R10 R11 R12 R13 on the stack PUSHM A 5 R13 Save R13 R12 R11 R10 R9 Save the five 16 bit registers R9 R10 R11 R12 R13 on the stack PUSHM W 5 R13 Save R13 R12 R11 R10 R9 4 132 16 Bit MSP430X CPU POPX A POPX W POPX B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Extended Instructions Restore single address word from the stack Restore single word from the stack Restore single byte from the stack POPX A dst POPX dst or POPX W dst POPX B dst Restore the 8 16 20 bit value from the stack to the destination 20 bit addresses are possible The stack pointer SP is incremented by two byte and word operands and by four address word operana MOVX B A SP dst The item on TOS is written to the destination operand Register Mode Indexed Mode Symbolic Mode and Absolute Mode are possible The stack pointer is incremented by two or four Note the stack pointer is incremented by two also for byte operations Not affected OSCOFF CPUOFF and GIE are not affected Write the 16 bit value on TOS to the 20 bit address amp EDE POPX W amp EDE Write word to address EDE Write the 20 bit value on TOS to R9 POPX A R9 Write address word to R9 16 Bit MSP430X CPU 4 133 Extended Instructions PUSHX A PUSHX W PUSHX B Syntax Operatio
401. nal See the device specific data sheet for specific signal connections 00 CCIxA 01 CCIxB 10 GND 11 Vec Synchronize capture source This bit is used to synchronize the capture input signal with the timer clock 0 Asynchronous capture 1 Synchronous capture Synchronized capture compare input The selected CCI input signal is latched with the EQUx signal and can be read via this bit Unused Read only Always read as 0 Capture mode 0 Compare mode 1 Capture mode Output mode Modes 2 3 6 and 7 are not useful for TACCRO because EQUx EQUO 000 OUT bit value 001 Set 010 Toggle reset 011 Set reset 100 Toggle 101 Reset 110 Toggle set 111 Reset set CCIE Bit 4 CCl Bit 3 OUT Bit 2 COV Bit 1 CCIFG Bit O Timer_A Registers Capture compare interrupt enable This bit enables the interrupt request of the corresponding CCIFG flag 0 Interrupt disabled 1 Interrupt enabled Capture compare input The selected input signal can be read by this bit Output For output mode 0 this bit directly controls the state of the output 0 Output low 1 Output high Capture overflow This bit indicates a capture overflow occurred COV must be reset with software 0 No capture overflow occurred 1 Capture overflow occurred Capture compare interrupt flag 0 No interrupt pending 1 Interrupt pending TAIV Timer_A Interrupt Vector Register 15 ro 7 14 13 12 11 10 9 8 ro ro ro ro ro ro ro 5 4 2 1 0 ro ro TA
402. nation are lost N Set if result is negative reset if positive Z Setif result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected See example at the SBC instruction See example at the SBC B instruction A 68 mie bo A ANA Note Borrow Is Treated as a NOT The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 ee 3 66 RISC 16 Bit CPU SUBC W SBB W SUBC B SBB B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Subtract source and borrow NOT carry from destination Subtract source and borrow NOT carry from destination SUBC src dst or SUBC W sre dst or SBB src dst or SBB W src dst SUBC B src dst or SBB B src dst dst NOT src C gt dst or dst src 1 C gt dst The source operand is subtracted from the destination operand by adding the source operand s 1s complement and the carry bit C The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs rese
403. nd Process results 8x8 Unsigned Multiply Absolute addressing MOV B 012h amp 0130h Load first operand MOV B 034h amp 0138h Load 2nd operand Process results 16x16 Signed Multiply MOV 01234h amp MPYS Load first operand MOV 05678h amp OP2 Load 2nd operand Process results 8x8 Signed Multiply Absolute addressing MOV B 012h amp 0132h Load first operand MOV B 034h amp 0138h Load 2nd operand Process results 16x16 Unsigned Multiply Accumulate MOV 01234h amp MAC Load first operand MOV 05678h amp OP2 Load 2nd operand Process results 8x8 Unsigned Multiply Accumulate Absolute addressing MOV B 012h amp 0134h Load first operand MOV B 034h amp 0138h Load 2nd operand Process results 16x16 Signed Multiply Accumulate MOV 01234h amp MACS Load first operand MOV 05678h amp OP2 Load 2nd operand Process results 8x8 Signed Multiply Accumulate Absolute addressing MOV B 012h amp 0136h Load first operand MOV B 034h R5 Temp location for 2nd operand MOV R5 0P2 Load 2nd operand Process results Hardware Multiplier 11 5 Hardware Multiplier Operation 11 2 4 Indirect Addressing of RESLO When using indirect or indirect autoincrement addressing mode to access the result registers At least one instruction is needed between loading the second operand and accessing one of the result registers Access multiplier results with indirect ad
404. nd EDE 2 MSBs MOVA R13 amp EDE R13 gt EDE 2 words transferred Move 20 bit value in R13 to 20 bit addresses EDE LSBs and EDE 2 MSBs PC index 32 K MOVA R13 EDE R13 gt EDE 2 words transferred 4 166 16 Bit MSP430X CPU RETA Syntax Operation Emulation Description Status Bits Mode Bits Example Address Instructions Return from subroutine RETA OSP gt PC 15 0 LSBs 15 0 of saved PC to PC 15 0 SsP 2 gt SP SP gt PC 19 16 MSBs 19 16 of saved PC to PC 19 16 SsP 2 gt SP MOVA SP PC The 20 bit return address information pushed onto the stack by a CALLA instruction is restored to the program counter PC The program continues at the address following the subroutine call The status register bits SR 11 0 are not affected This allows the transfer of information with these bits N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Call a subroutine SUBR from anywhere in the 20 bit address space and return to the address after the CALLA CALLA SUBR Call subroutine starting at SUBR q Return by RETA to here SUBR PUSHM A 2 R14 Save R14 and R13 20 bit data e Subroutine code POPM A 2 R14 Restore R13 and R14 20 bit data RETA Return to full address space 16 Bit MSP430X CPU 4 167 Address Instructions TSTA Syntax Operation Emulation Description Status Bits Mode Bits Example Test 2
405. ndition is received 0 No interrupt pending 1 Interrupt pending Start condition interrupt flag UCSTTIFG is automatically cleared if a STOP condition is received 0 No interrupt pending 1 Interrupt pending Arbitration lost interrupt flag 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface C Mode 17 29 USCI Registers C Mode UCBxRXBUF USCI_Bx Receive Buffer Register 7 6 5 4 3 2 1 0 r r r r r r r r UCRXBUFx Bits The receive data buffer is user accessible and contains the last received 7 0 character from the receive shift register Reading UCBxRXBUF resets UCBxRXIFG UCBxTXBUF USCI_Bx Transmit Buffer Register 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCTXBUFx Bits The transmit data buffer is user accessible and holds the data waiting to 7 0 be moved into the transmit shift register and transmitted Writing to the transmit data buffer clears UCBxTXIFG 17 30 Universal Serial Communication Interface 12C Mode USCI Registers C Mode UCBxI2COA USCIBx I2C Own Address Register 15 14 13 12 11 10 9 8 rw 0 ro ro ro ro ro rw 0 rw 0 7 6 5 4 3 2 1 0 Pm rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCGCEN Bit15 General call response enable 0 Do not respond to a general call 1 Respond to a general call 12COAx Bits 12C own address The I2COAx bits contain the local address of the USCI_Bx 9 0 12C controller The address is right justified In 7 bit addressing mode Bit 6 is the MSB
406. ne can be individually read or written to Ports P1 and P2 have interrupt capability Each interrupt for the P1 and P2 I O lines can be individually enabled and configured to provide an interrupt on a rising edge or falling edge of an input signal All P1 I O lines source a single interrupt vector and all P2 I O lines source a different single interrupt vector The digital I O features include UY Independently programmable individual I Os Any combination of input or output Individually configurable P1 and P2 interrupts Independent input and output data registers m m m E Individually configurable pullup or pulldown resistors Digital I O Operation 8 2 Digital l O Operation The digital I O is configured with user software The setup and operation of the digital I O is discussed in the following sections 8 2 1 Input Register PxIN Each bit in each PxIN register reflects the value of the input signal at the corresponding I O pin when the pin is configured as I O function Bit 0 The input is low Bit 1 The input is high Te Note Writing to Read Only Registers PxIN Writing to these read only registers results in increased current consumption while the write attempt is active 8 2 2 Output Registers PXOUT Each bit in each PXOUT register is the value to be output on the corresponding I O pin when the pin is configured as I O function output direction and the pull up down resistor is disabled Bit
407. ned in EXEC SP 2 gt SP PC 2 gt SP X PC gt PC Indirect address amp EXEC Call on the address contained in absolute address EXEC SP 2 gt SP PC 2 gt SP X 0 PC Indirect address R5 Call on the address contained in R5 SP 2 SP PC 2 gt SP R5 gt PC Indirect R5 R5 Call on the address contained in the word pointed to by R5 SP 2 gt SP PC 2 gt SP R5 gt PC Indirect indirect R5 R5 Call on the address contained in the word pointed to by R5 and increment pointer in R5 The next time S W flow uses R5 pointer it can alter the program execution due to access to next address in a table pointed to by R5 SP 2 gt SP PC 2 gt SP R5 gt PC Indirect indirect R5 with autoincrement X R5 Call on the address contained in the address pointed to by R5 X e g table with address starting at X X can be an address or a label SP 2 gt SP PC 2 gt SP X R5 gt PC Indirect indirect R5 X RISC 16 Bit CPU 3 29 Instruction Set CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst or CLR W dst CLR B dst 0 gt dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 gt TONI Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TON
408. negative SUMEXT contains the carry of the result 0000h No carry for result 0001h Result has a carry SUMEXT contains the extended sign of the result 00000h Result was positive or zero OFFFFh Result was negative The multiplier does not automatically detect underflow or overflow in the MACS mode The accumulator range for positive numbers is O to 7FFF FFFFh and for negative numbers is OFFFF FFFFh to 8000 0000h An underflow occurs when the sum of two negative numbers yields a result that is in the range for a positive number An overflow occurs when the sum of two positive numbers yields a result that is in the range for a negative number In both of these cases the SUMEXT register contains the sign of the result OFFFFh for overflow and 0000h for underflow User software must detect and handle these conditions appropriately Hardware Multiplier Hardware Multiplier Operation 11 2 3 Software Examples Examples for all multiplier modes follow All 8x8 modes use the absolute address for the registers because the assembler will not allow B access to word registers when using the labels from the standard definitions file There is no sign extension necessary in software Accessing the multiplier with a byte instruction during a signed operation will automatically cause a sign extension of the byte within the multiplier module 1 16x16 Unsigned Multiply MOV 01234h amp MPY Load first operand MOV 05678h amp OP2 Load second opera
409. nerator is enabled and the data in UCAxTXBUF is moved to the transmit shift register on the next BITCLK after the transmit shift register is empty UCAXTXIFG is set when new data can be written into UCAxTXBUF Transmission continues as long as new data is available in UCAxTXBUF at the end of the previous byte transmission If new data is not in UCAxTXBUF when the previous byte has transmitted the transmitter returns to its idle state and the baud rate generator is turned off 15 3 9 UART Baud Rate Generation The USCI baud rate generator is capable of producing standard baud rates from non standard source frequencies It provides two modes of operation selected by the UCOS16 bit Low Frequency Baud Rate Generation The low frequency mode is selected when UCOS16 0 This mode allows generation of baud rates from low frequency clock sources e g 9600 baud from a 32768Hz crystal By using a lower input frequency the power consumption of the module is reduced Using this mode with higher frequencies and higher prescaler settings will cause the majority votes to be taken in an increasingly smaller window and thus decrease the benefit of the majority vote In low frequency mode the baud rate generator uses one prescaler and one modulator to generate bit clock timing This combination supports fractional divisors for baud rate generation In this mode the maximum USCI baud rate is one third the UART source clock frequency BRCLK Universal Seri
410. nes from the corresponding row in Table 15 3 j 0 Mucerexl l Modulation of bit i from Table 15 2 This results in an end of bit time tpit tx i equal to the sum of all previous and the current bit times toirxlil E Sill To calculate bit error this time is compared to the ideal bit time tpit idear Txlil i 1 7 1 boitidea xli Baudrate This results in an error normalized to one ideal bit time 1 baudrate Erroryi tonrxlil tonidea rxli Baudrate 100 Universal Serial Communication Interface UART Mode 15 19 USCI Operation UART Mode 15 3 12 Receive Bit Timing Receive timing error consists of two error sources The first is the bit to bit timing error similar to the transmit bit timing error The second is the error between a start edge occurring and the start edge being accepted by the USCI module Figure 15 11 shows the asynchronous timing errors between data on the UCAxRXD pin and the internal baud rate clock This results in an additional synchronization error The synchronization error tsync is between 0 5 BRCLKs and 0 5 BRCLKs independent of the selected baud rate generation mode Figure 15 11 Receive Error i 0 1 2 ty tideal to 11 213 4 5le 7 8 9 10 1 1218114 1121314 516 1718 l 9 0 11 12 8 14 11 2131 415 6 7 UCAxXRXD st DO D1 ST RXD synch DO D1 tactual to t bb ed amp Synchronization Error 0 5x BRCLK Sample RXD synch LIA PA LIA Majo
411. ng ENC during a sequence or repeat sequence mode stops the converter at the end of the sequence Lj Any conversion mode may be stopped immediately by setting the CONSEQx 0 and resetting the ENC bit Conversion data is unreliable 20 14 ADC10 ADC10 Operation 20 2 7 ADC10 Data Transfer Controller The ADC10 includes a data transfer controller DTC to automatically transfer conversion results from ADC10MEM to other on chip memory locations The DTC is enabled by setting the ADC10DTC1 register to a nonzero value When the DTC is enabled each time the ADC10 completes a conversion and loads the result to ADC10MEM a data transfer is triggered No software intervention is required to manage the ADC10 until the predefined amount of conversion data has been transferred Each DTC transfer requires one CPU MCLK To avoid any bus contention during the DTC transfer the CPU is halted if active for the one MCLK required for the transfer A DTC transfer must not be initiated while the ADC10 is busy Software must ensure that no active conversion or sequence is in progress when the DTC is configured ADC10 activity test BIC W ENC amp ADC1O0CTLO busy_test BIT W BUSY amp ADC10CTL1 JNZ busy_test 7 MOV W XXxx amp ADC10SA Safe MOV B xx amp ADC10DTC1 continue setup ADC10 20 15 ADC10 Operation One Block Transfer Mode The one block mode is selected if the ADC10TB is reset The value n in ADC10DTC1 defines the total nu
412. ngth extension bit Together with the B W bits of the following MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 0 Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte Reserved Repetition Count 0 These four bits set the repetition count n These bits contain n 1 1 These four bits define the CPU register whose bits 3 0 set the number of repetitions Rn 3 0 contain n 1 4 44 16 Bit MSP430X CPU MSP430X Extended Instructions Non Register Mode Extension Word The extension word for non register modes is shown in Figure 4 26 and described in Table 4 12 An example is shown in Figure 4 28 Figure 4 26 The Extension Word for Non Register Modes 15 12 11 10 7 6 5 4 3 0 0 0 0 1 Source bits 19 16 ao o Destination bits 19 16 Table 4 12 Description of the Extension Word Bits for Non Register Modes Bit Description 15 11 Extension word op code Op codes 1800h to 1FFFh are exten sion words Source Bits The four MSBs of the 20 bit source Depending on the source 19 16 addressing mode these four MSBs may belong to an immedi ate operand an index or to an absolute address A L Data length extension bit Together with the B W bits of the fol lowing MSP430 instruction the AL bit defines the used data length of the instruction A L B W Comment 0 0 Reserved 0 1 20 bit address word 1 0 16 bit word 1 1 8 bit byte 5 4 Reserved Destination Bi
413. not a break 1 Next frame transmitted is a break or a break synch Software reset enable 0 Disabled USCI reset released for operation 1 Enabled USCI logic held in reset state Universal Serial Communication Interface UART Mode 15 29 USCI Registers UART Mode UCAxBRO USCI_Ax Baud Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx rw rw rw rw rw rw rw rw 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCBRx Clock prescaler setting of the Baud rate generator The 16 bit value of UCAxBRO UCAxBR1 x 256 forms the prescaler value UCAxMCTL USCI_Ax Modulation Control Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCBRFx Bits First modulation stage select These bits determine the modulation pattern 7 4 for BITCLK16 when UCOS16 1 Ignored with UCOS16 0 Table 15 3 shows the modulation pattern UCBRSx Bits Second modulation stage select These bits determine the modulation 3 1 pattern for BITCLK Table 15 2 shows the modulation pattern UCOS16 Bit 0 Oversampling mode enabled 0 Disabled 1 Enabled 15 30 Universal Serial Communication Interface UART Mode USCI Registers UART Mode UCAxSTAT USCI_Ax Status Register 7 6 5 4 3 2 1 0 UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADOR ucsusy rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 rw 0 UCLISTEN UCFE UCOE UCPE UCBRK UCRXERR UCADDR UCIDLE UCBUSY Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O Listen enable The UCL
414. nput or open drain output in 12C mode 0 USI function disabled 1 USI function enabled USIPE5 Bit 5 USI SCLK port enable Input in SPI slave mode or I2C mode output in SPI master mode 0 USI function disabled 1 USI function enabled USILSB Bit 4 LSB first select This bit controls the direction of the receive and transmit shift register 0 MSB first 1 LSB first USIMST Bit 3 Master select 0 Slave mode 1 Master mode USIGE Bit 2 Output latch control 0 Output latch enable depends on shift clock 1 Output latch always enabled and transparent USIOE Bit 1 Data output enable 0 Output disabled 1 Output enabled USISWRST Bito USI software reset 0 USI released for operation 1 USI logic held in reset state 14 14 Universal Serial Interface USI Registers USICTL1 USI Control Register 1 7 6 5 4 3 2 1 0 USICKPH USII2C USISTTIE ES USIAL USISTP USISTTIFG USIIFG rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 1 rw 0 USICKPH USII2C USISTTIE USIIE USIAL USISTP USISTTIFG USIIFG Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O rw Clock phase select 0 Data is changed on the first SCLK edge and captured on the following edge 1 Data is captured on the first SCLK edge and changed on the following edge 12C mode enable 0 12C mode disabled 1 12C mode enabled START condition interrupt enable 0 Interrupt on START condition disabled 1 Interrupt on START condition enabled USI counter interrupt enable
415. nstruction Set 3 4 4 Instruction Cycles and Lengths The number of CPU clock cycles required for an instruction depends on the instruction format and the addressing modes used not the instruction itself The number of clock cycles refers to the MCLK Interrupt and Reset Cycles Table 3 14 lists the CPU cycles for interrupt overhead and reset Table 3 14 Interrupt and Reset Cycles No of Length of Action Cycles Instruction Return from interrupt RETI 5 1 Interrupt accepted 6 WDT reset 4 Reset RST NMI 4 Format ll Single Operand Instruction Cycles and Lengths Table 3 15 lists the length and CPU cycles for all addressing modes of format Il instructions Table 3 15 Format ll Instruction Cycles and Lengths No of Cycles Addressing RRA RRC Length of Mode SWPB SXT PUSH CALL instruction Example Rn 1 3 4 1 SWPB R5 Rn 3 4 4 1 RRC R9 Rn 3 5 5 1 SWPB R10 N See note 4 5 2 CALL 0F000h X Rn 4 5 5 2 CALL 2 R7 EDE 4 5 5 2 PUSH EDE amp EDE 4 5 5 2 SXT amp EDE E Note Instruction Format Il Immediate Mode Do not use instructions RRA RRC SWPB and SXT with the immediate mode in the destination field Use of these in the immediate mode results in an unpredictable program operation Format 11 Jump Instruction Cycles and Lengths All jump instructions require one code word and take two CPU cycles to execute regardless of whether the jump is taken or not 3 72 RISC 16 Bit CPU Forma
416. nt device specific absolute address 22 2 Supported Tags Each device contains a subset of the tags shown in Table 22 2 See the device specific data sheet for details Table 22 2 Supported Tags Device Specific TAG_EMPTY Identifies an unused memory area TAG_DCO_30 Calibration values for the DCO at room temperature and DVcc 3 V TAG_ADC12_1 Calibration values for the ADC12 module 22 2 1 DCO Calibration TLV Structure For DCO calibration the BCS registers BCSCTL1 and DCOCTL are used The values stored in the flash information memory SegmentA are written to the BCS registers Table 22 3 DCO Calibration Data Device Specific anar espinosa TLV Structure 22 3 Supported Tags Code Example Using Absolute Addressing Mode The calibration data for the DCO is available in all 2xx devices and is stored at the same absolute addresses The device specific SegmentA content is applied using the absolute addressing mode if the following code is used Calibrate the DCO to 1 MHz CLR B amp DCOCTL Select lowest DCOx and MODx settings MOV B amp CALBC1 1MHZ amp BCSCTL1 Set RSELx MOV B amp CALDCO_1MHZ amp DCOCTL Set DCOx and MODX The TLV structure allows use of the address of the TAG_DCO_30 tag to address the DCO registers The code example shows how to address the DCO calibration data using the TAG_DCO_30 tag Code Example Using the TLV Structure Calibrate the DCO to 8 MHz It is assumed that R
417. nter must be in the process of counting for the action to take place If a particular value is directly written to the counter then an associated action will not take place o Timer_A Introduction Figure 12 1 Timer_A Block Diagram Li Timer Block TASSELx MCx TACLK 00 16 bit Timer ean i TAR EQUO i ACLK 01 la mode SMCLK 10 i INCLK 11 SetTAIFG AA A A AAA SOE ee E EAE E ere Sane l CCRO CCR1 CCR2 l i CCISx 1 I i i i SCS CCI2A 00 Capture E cci28 o1 Mode S i TACCR2 i al creck Aeon E moon U U i vec 11 p i CCI EQU2 CAP I 1 i SCCI Y i Set TACCR2 CCIFG i i i OUT i i OUT2 Signal l L I i Timer_A 12 3 Timer_A Operation 12 2 Timer_A Operation The Timer_A module is configured with user software The setup and operation of Timer_A is discussed in the following sections 12 2 1 16 Bit Timer Counter The 16 bit timer counter register TAR increments or decrements depending on mode of operation with each rising edge of the clock signal TAR can be read or written with software Additionally the timer can generate an interrupt when it overflows TAR may be cleared by setting the TACLR bit Setting TACLR also clears the clock divider and count direction for up down mode OSRE DH AAA A Note Modifying Timer_A Registers It is recommended to stop the timer before modifying its operation with excepti
418. nts Interrupt Source Interrupt Flag Priority 00h No interrupt pending 02h Capture compare 1 TBCCR1 CCIFG Highest 04h Capture compare 2 TBCCR2 CCIFG 06h Capture compare 3t TBCCR3 CCIFG 08h Capture compare 44 TBCCR4 CCIFG OAh Capture compare 5t TBCCR5 CCIFG OCh Capture compare 6t TBCCR6 CCIFG OEh Timer overflow TBIFG Lowest t Not available on all devices 13 26 Timer_B Chapter 14 Universal Serial Interface The Universal Serial Interface USI module provides SPI and I2C serial communication with one hardware module This chapter discusses both modes The USI module is implemented in the MSP430x20xx devices Topic Page AUS Ntro UC OO a a a a 14 2 142 US Operation ios 14 5 14 3 USIRegisters oa e aio 14 13 14 1 USI Introduction 14 1 USI Introduction The USI module provides the basic functionality to support synchronous serial communication In its simplest form it is an 8 or 16 bit shift register that can be used to output data streams or when combined with minimal software can implement serial communication In addition the USI includes built in hardware functionality to ease the implementation of SPI and 1 C communication The USI module also includes interrupts to further reduce the necessary software overhead for serial communication and to maintain the ultralow power capabilities of the MSP430 The USI module features include Three wire SPI mode support 12C mode support Variable data length Sla
419. nversion Memory There are 16 ADC12MEMx conversion memory registers to store conversion results Each ADC12MEMx is configured with an associated ADC12MCTLx control register The SREFx bits define the voltage reference and the INCHx bits select the input channel The EOS bit defines the end of sequence when a sequential conversion mode is used A sequence rolls over from ADC12MEM15 to ADC12MEMO when the EOS bit in ADC12MCTL15 is not set The CSTARTADDx bits define the first ADC12MCTLx used for any conversion If the conversion mode is single channel or repeat single channel the CSTARTADDx points to the single ADC12MCTLx to be used If the conversion mode selected is either sequence of channels or repeat sequence of channels CSTARTADDx points to the first ADC12MCTLx location to be used in a sequence A pointer not visible to software is incremented automatically to the next ADC12MCTLx in a sequence when each conversion completes The sequence continues until an EOS bit in ADC12MCTL is processed this is the last control byte processed When conversion results are written to a selected ADC12MEMx the corresponding flag in the ADC12IFGx register is set 21 2 6 ADC12 Conversion Modes The ADC12 has four operating modes selected by the CONSEQx bits as discussed in Table 21 1 Table 21 1 Conversion Mode Summary CONSEQx Mode Operation 00 Single channel A single channel is converted once single conversion 01 Sequence of A sequence of ch
420. nversions are performed the corresponding ADC12IF Gx is the trigger When sequences are used the ADC12IFGx for the last conversion in the sequence is the trigger A transfer is triggered when the conversion is completed and the ADC12IFGx is set Setting the ADC12IFGx with software will not trigger a transfer All ADC12IFGx flags are automatically reset when the associated ADC12MEMXx register is accessed by the DMA controller A transfer is triggered when the TACCRO CCIFG flag is set The TACCRO CCIFG flag is automatically reset when the transfer starts If the TACCRO CCIE bit is set the TACCRO CCIFG flag will not trigger a transfer A transfer is triggered when the TBCCRO CCIFG flag is set The TBCCRO CCIFG flag is automatically reset when the transfer starts If the TBCCRO CCIE bit is set the TBCCRO CCIFG flag will not trigger a transfer A transfer is triggered when the UCA1RXIFG flag is set UCA1RXIFG is automatically reset when the transfer starts If URXIE1 is set the UCA1RXIFG flag will not trigger a transfer A transfer is triggered when the UCA1TXIFG flag is set UCA1TXIFG is automatically reset when the transfer starts If UTXIE1 is set the UCA1TXIFG flag will not trigger a transfer A transfer is triggered when the hardware multiplier is ready for a new operand No transfer is triggered Devices with USCI_BO module A transfer is triggered when USCI_BO receives new data UCBORXIFG is automatically reset when the transfer starts
421. o RAM blocks are compared If they are not equal the program branches to the label ERROR MOV NUM R5 number of words to be compared MOV BLOCK1 R6 BLOCK1 start address in R6 MOV BLOCK2 R7 BLOCK2 start address in R7 L 1 CMP R6 0 R7 Are Words equal R6 increments JNZ ERROR No branch to ERROR INCD R7 Increment R7 pointer DEC R5 Are all words compared JNZ L 1 No another compare The RAM bytes addressed by EDE and TONI are compared If they are equal the program continues at the label EQUAL CMP B EDE TONI MEM EDE MEM TONI JEQ EQUAL YES JUMP 3 34 RISC 16 Bit CPU DADC W DADC B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Instruction Set Add carry decimally to destination Add carry decimally to destination DADC dst or DADC W src dst DADC B dst dst C gt dst decimally DADD 0 dst DADD B 0 dst The carry bit C is added decimally to the destination N Set if MSB is 1 Z Set if dst is 0 reset otherwise C Set if destination increments from 9999 to 0000 reset otherwise Set if destination increments from 99 to 00 reset otherwise V Undefined OSCOFF CPUOFF and GIE are not affected The four digit decimal number contained in R5 is added to an eight digit deci mal number pointed to by R8 CLRC Reset carry next instruction s start condition is defined DADD R5 0 R8 Add LSDs C DADC 2 R8 Add carry
422. o form differential amplifiers The output slew rate of the OA can be configured for optimized settling time vs power consumption with the OAPMx bits When OAPMx 00 the OA is off and the output is high impedance When OAPMx gt 0 the OA is on See the device specific data sheet for parameters 18 2 2 OA Input The OA has configurable input selection The signals for the and inputs are individually selected with the OANx and OAPx bits and can be selected as external signals or internal signals OAxIO and OAxl1 are external signals provided for each OA module OAOI1 provides a non inverting input that is tied together internally for all OA modules OAxIA and OAxIB provide device dependent inputs Refer to the device data sheet for signal connections When the external inverting input is not needed for a mode setting the OANEXT bit makes the internal inverting input externally available 18 4 OA OA Operation 18 2 3 OA Output and Feedback Routing The OA has configurable output selection controlled by the OAADCx bits and the OAFCx bits The OA output signals can be routed to ADC12 inputs A12 OAO A13 OA1 or A14 OA2 internally or can be routed to these ADC inputs and their external pins The OA output signals can also be routed to ADC inputs A1 OAO A3 OA1 or A5 OA2 and the corresponding external pin The OA output is also connected to an internal R ladder with the OAFCx bits The R ladder tap is selected with the OAFB
423. o interrupt vectors for the USCI module in 12C mode One interrupt vector is associated with the transmit and receive interrupt flags The other interrupt vector is associated with the four state change interrupt flags Each interrupt flag has its own interrupt enable bit When an interrupt is enabled and the GIE bit is set the interrupt flag will generate an interrupt request DMA transfers are controlled by the UCBxTXIFG and UCBxRXIFG flags on devices with a DMA controller 12C Transmit Interrupt Operation The UCBxTXIFG interrupt flag is set by the transmitter to indicate that UCBxTXBUF is ready to accept another character An interrupt request is generated if UCBxTXIE and GIE are also set UCBxTXIFG is automatically reset if a character is written to UCBxTXBUF or if a NACK is received UCBxTXIFG is set when UCSWRST 1 and the I2C mode is selected UCBxTXIE is reset after a PUC or when UCSWRST 1 12C Receive Interrupt Operation The UCBxRXIFG interrupt flag is set when a character is received and loaded into UCBxRXBUF An interrupt request is generated if UCBxRXIE and GIE are also set UCBxRXIFG and UCBxRXIE are reset after a PUC signal or when UCSWRST 1 UCxRXIFG is automatically reset when UCXRXBUF is read 12C State Change Interrupt Operation Table 17 1 Describes the 12C state change interrupt flags Table 17 1 1 C State Change Interrupt Flags Interrupt Flag Interrupt Condition UCALIFG Arbitration lost Arbitration can be l
424. o transfers occur The DMAxSA DMAxDA and DMAxSZ registers are copied into temporary registers The temporary values of DMAxSA and DMAxDA are incremented or decremented after each transfer in the block The DMAxSZ register is decremented after each transfer of the block and shows the number of transfers remaining in the block When the DMAxSZ register decrements to zero it is reloaded from its temporary register and the corresponding DMAIFG flag is set In repeated burst block mode the DMAEN bit remains set after completion of the burst block transfer and no further trigger signals are required to initiate another burst block transfer Another burst block transfer begins immediately after completion of a burst block transfer In this case the transfers must be stopped by clearing the DMAEN bit or by an NMI interrupt when ENNMI is set In repeated burst block mode the CPU executes at 20 capacity continuously until the repeated burst block transfer is stopped 6 10 DMA Controller DMA Operation Figure 6 5 DMA Burst Block Transfer State Diagram DMAEN 0 DMAEN 0 i DMAREQ 0 0 T_Size gt DMAxSZ DMEM DMAxSZ gt T_Size DMADTx 2 3 DMAxSA gt T_SourceAdd AND DMAxSZ 0 DMAxDA gt T_DestAdd OR DMAEN 0 DMAABORT 1 DMAABORT 0 Wait for Trigger Trigger AND DMALEVEL 0 OR Tri 1 AND DMALEVEL 1 2 x MCLK Trigger l Hold CPU Transfer one word byte ENNMI 1 AND pe event T_
425. ock one in one block mode or block two two block mode has been transferred The internal address pointer and transfer counter are set equal to ADC10SA and n respectively Transfers continue starting in block one If the ADC10CT bit is reset DTC transfers cease after the current completion of transfers into block one in the one block mode or block two in the two block mode have been transfer DTC Transfer Cycle Time For each ADC10MEM transfer the DTC requires one or two MCLK clock cycles to synchronize one for the actual transfer while the CPU is halted and one cycle of wait time Because the DTC uses MCLK the DTC cycle time is dependent on the MSP430 operating mode and clock system setup If the MCLK source is active but the CPU is off the DTC uses the MCLK source for each transfer without re enabling the CPU If the MCLK source is off the DTC temporarily restarts MCLK sourced with DCOCLK only during a transfer The CPU remains off and after the DTC transfer MCLK is again turned off The maximum DTC cycle time for all operating modes is show in Table 20 2 Table 20 2 Maximum DTC Cycle Time 20 20 ADC10 CPU Operating Mode Clock Source Maximum DTC Cycle Time _ Active mode MCLK DCOCLK 3 MCLK cycles Active mode MCLK LFXT1CLK 3 MCLK cycles Low power mode LPMO 1 MCLK DCOCLK 4 MCLK cycles Low power mode LPM3 4 MCLK DCOCLK 4 MCLK cycles 2 ust Low power mode LPMO 1 MCLK LFXT1CLK 4 MCLK cycles Low power mode LPM3 M
426. ock system is designed specifically for battery powered applications A low frequency auxiliary clock ACLK is driven directly from a common 32 kHz watch crystal The ACLK can be used for a background real time clock self wake up function An integrated high speed digitally controlled oscillator DCO can source the master clock MCLK used by the CPU and high speed peripherals By design the DCO is active and stable in less than 2 us at 1 Mhz MSP430 based solutions effectively use the high performance 16 bit RISC CPU in very short bursts Y Low frequency auxiliary clock Ultralow power stand by mode UY High speed master clock High performance signal processing 1 2 Introduction Embedded Emulation Figure 1 1 MSP430 Architecture ACLK Flash 4 RAM suck ROM LL LIS gt MAB 16 Bit I risccru 3 16 Bit S y MDB 16 Bit Bus MDB 8 Bit JTAG 4 1 3 Embedded Emulation Dedicated embedded emulation logic resides on the device itself and is accessed via JTAG using no additional system resources The benefits of embedded emulation include _j Unobtrusive development and debug with full speed execution breakpoints and single steps in an application are supported UY Development is in system subject to the same characteristics as the final application UY Mixed signal integrit
427. ode 17 3 USCI Operation I2C Mode The IC mode supports any slave or master I2C compatible device Figure 17 2 shows an example of an I C bus Each 12C device is recognized by a unique address and can operate as either a transmitter or a receiver A device connected to the 12C bus can be considered as the master or the slave when performing data transfers A master initiates a data transfer and generates the clock signal SCL Any device addressed by a master is considered a slave 12C data is communicated using the serial data pin SDA and the serial clock pin SCL Both SDA and SCL are bidirectional and must be connected to a positive supply voltage using a pullup resistor Figure 17 2 1 C Bus Connection Diagram Serial Data SDA Vcc MSP430 Device A Serial Clock SCL Note SDA and SCL Levels The MSP430 SDA and SCL pins must not be pulled up above the MSP430 Voc level Universal Serial Communication Interface C Mode 17 5 USCI Operation C Mode 17 3 1 USCI Initialization and Reset 17 6 The USCI is reset by a PUC or by setting the UCSWRST bit After a PUC the UCSWRST bit is automatically set keeping the USCI in a reset condition To select 12C operation the UCMODEx bits must be set to 11 After module initialization it is ready for transmit or receive operation Clearing UCSWRST releases the USCI for operation Configuring and reconfiguring the USCI module should be done when UCSWRST is set to
428. ode TBR max TBCLO TBCL1 Output Mode 1 Set Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQU1 EQUO EQU1 EQUO TBIFG TBIFG TBIFG Interrupt Events Timer_B 13 15 Timer_B Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TBCLx and TBCLO values depending on the output mode An example is shown in Figure 13 13 using TBCLO and TBCL1 Figure 13 13 Output Example Timer in Continuous Mode TBR max TBCLO TBCL1 Oh TBIFG EQU1 EQUO TBIFG EQU1 EQUO Interrupt Events 13 16 Timer_B Timer_B Operation Output Example Timer in Up Down Mode The OUTx signal changes when the timer equals TBCLx in either count direction and when the timer equals TBCLO depending on the output mode An example is shown in Figure 13 14 using TBCLO and TBCL3 Figure 13 14 Output Example Timer in Up Down Mode TBR max TBCLO TBCL3 Oh Pees Output Mode 1 Set fee Output Mode 2 Toggle Reset Output Mode 3 Set Reset C a O utput Mode 4 Toggle Output Mode 5 Reset a Output Mode 6 Toggle Set SS Output Mode 7 Reset Set EQU3 EQU3 EQU3 EQU3 TBIFG EQUO TBIFG EQUO Interrupt Events ee eee P 2 Note Switching Between Output Modes When switching between output mode
429. oduction This chapter describes the architecture of the MSP430 Topic Page IRA checa a 1 2 122 Flexible Clock Systemi aen ee ae a e aai 1 2 123 Embedded Emulation a eee a E crelarsye 1 3 NAR Address Space me e cae a a E AE E e EE eeevey aie 1 4 1 5 MSP430x2xx Family Enhancements o o ooooccncccccnccs 1 7 Architecture 1 1 Architecture The MSP430 incorporates a 16 bit RISC CPU peripherals and a flexible clock system that interconnect using a von Neumann common memory address bus MAB and memory data bus MDB Partnering a modern CPU with modular memory mapped analog and digital peripherals the MSP430 offers solutions for demanding mixed signal applications Key features of the MSP430x2xx family include Lj Ultralow power architecture extends battery life E 0 1 uA RAM retention ME 0 8 uA real time clock mode mM 250 uA MIPS active Lj High performance analog ideal for precision measurement m Comparator gated timers for measuring resistive elements Y 16 bit RISC CPU enables new applications at a fraction of the code size m Large register file eliminates working file bottleneck Compact core design reduces power consumption and cost Optimized for modern high level programming Only 27 core instructions and seven addressing modes m Extensive vectored interrupt capability O In system programmable Flash permits flexible code changes field upgrades and data logging 1 2 Flexible Clock System The cl
430. olute addressing mode the absolute address is a 20 bit value and therefore points to any address in the memory range The address value is calculated as an index from 0 The four MSBs of the index are contained in the extension word and the 16 LSBs are contained in the word following the instruction Length Three or four words Operation The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the index from O and inserts it Example ADDX A amp EDE amp TONI This instruction adds the 20 bit data contained in the absolute source and destination addresses and places the result into the destination Source Two words beginning with address EDE Destination Two words beginning with address TONI Before After Address Address Space Space 2103Ah PC 21038h 21036h 21034h 21032h 2103Ah 21038h 21036h 21034h 21032h 65432h src 7777Ah 7777Ah 12345h__ dst 77777h Sum 77778h 77778h 3579Eh 3579Ch 3579Eh 3579Ch 4 30 16 Bit MSP430X CPU 4 4 5 Indirect Register Mode CPU Registers The Indirect Register mode uses the contents of the CPU register Rsrc as the source operand The Indirect Register mode always uses a 20 bit address Length Operation Comment Example One two or three words The operand is the content the addressed memory location The source register Rsrc is not modified Valid only for the source ope
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432. on of the interrupt enable interrupt flag and TACLR to avoid errant operating conditions When the timer clock is asynchronous to the CPU clock any read from TAR should occur while the timer is not operating or the results may be unpredictable Alternatively the timer may be read multiple times while operating and a majority vote taken in software to determine the correct reading Any write to TAR will take effect immediately Clock Source Select and Divider 12 4 Timer_A The timer clock can be sourced from ACLK SMCLK or externally via TACLK or INCLK The clock source is selected with the TASSELx bits The selected clock source may be passed directly to the timer or divided by 2 4 or 8 using the IDx bits The timer clock divider is reset when TACLR is set Timer_A Operation 12 2 2 Starting the Timer The timer may be started or restarted in the following ways Y The timer counts when MCx gt 0 and the clock source is active I When the timer mode is either up or up down the timer may be stopped by writing O to TACCRO The timer may then be restarted by writing a nonzero value to TACCRO In this scenario the timer starts incrementing in the up direction from zero 12 2 3 Timer Mode Control The timer has four modes of operation as described in Table 12 1 stop up continuous and up down The operating mode is selected with the MCx bits Table 12 1 Timer Modes MCx Mode Description 00 Stop The timer is ha
433. on operand The previous content of the destination is lost N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Constant value 15 and the carry of the previous instruction are added to the 16 bit counter CNTR located in lower 64 K ADDC W 15 amp CNTR Add 15 C to 16 bit CNTR A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label TONI is performed on a carry R6 19 16 0 ADDC W R5 R6 Add table word C to R6 JC TONI Jump if carry No carry A table byte pointed to by R5 20 bit address and the carry bit C are added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 R6 19 8 0 ADDCB R5 R6 Add table byte C to R6 R5 1 JNC TONI Jump if no carry Carry occurred 16 Bit MSP430X CPU 4 63 MSP430 Instructions AND W AND B Syntax Operation Description Status Bits Mode Bits Example Example Logical AND of source word with destination word Logical AND of source byte with destination byte AND src dst or AND W src dst AND B src dst src and dst gt dst The source operand and the destinati
434. on operand are logically ANDed The result is placed into the destination The source operand is not affected N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The bits set in R5 16 bit data are used as a mask AA55h for the word TOM located in the lower 64 K If the result is zero a branch is taken to label TONI R5 19 16 0 MOV AA55h R5 Load 16 bit mask to R5 AND R5 amp TOM TOM and R5 gt TOM JZ TONI Jump if result 0 Result gt 0 or shorter AND AA55h amp TOM TOM and AA55h gt TOM JZ TONI Jump if result 0 A table byte pointed to by R5 20 bit address is logically ANDed with R6 R5 is incremented by 1 after the fetching of the byte R6 19 8 0 AND B R5 R6 AND table byte with R6 R5 1 4 64 16 Bit MSP430X CPU BIC W BIC B Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Clear bits set in source word in destination word Clear bits set in source byte in destination byte BIC src dst or BIC W src dst BIC B src dst not src and dst dst The inverted source operand and the destination operand are logically ANDed The result is placed into the destination The source operand is not affected N Not affected Z Not affected C Not aff
435. ontrol Register 0 UCBxCTLO USCI_Bx Control Register 0 7 6 5 4 3 CCKPH UCCKPL UCMSB UC7BIT UCMST rw 0 rw 0 rw 0 rw 0 rw 0 UCCKPH UCCKPL UCMSB UC7BIT UCMST UCMODEx UCSYNC Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bits 2 1 Bit O 2 1 0 rw 0 rw 0 Clock phase select 0 Data is changed on the first UCLK edge and captured on the following edge 1 Data is captured on the first UCLK edge and changed on the following edge Clock polarity select 0 The inactive state is low 1 The inactive state is high MSB first select Controls the direction of the receive and transmit shift register 0 LSB first 1 MSB first Character length Selects 7 bit or 8 bit character length 0 8 bit data 1 7 bit data Master mode select 0 Slave mode 1 Master mode USCI mode The UCMODEx bits select the synchronous mode when UCSYNC 1 00 3 Pin SPI 01 4 Pin SPI with UCxSTE active high slave enabled when UCxSTE 1 10 4 Pin SPI with UCxSTE active low slave enabled when UCXSTE 0 11 12C Mode Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode Universal Serial Communication Interface SPI Mode 16 17 USCI Registers SPI Mode UCAxCTL1 USCI_Ax Control Register 1 UCBxCTL1 USCI_Bx Control Register 1 7 6 5 4 3 2 1 0 ot rw 0 rw 0 pes rw 0 rw 0 rw 0 rw 0 rw 1 t UCAXCTL1 USCI_Ax UCBxCTL1 USCI_Bx UCSSELx Bits USCI clock source select These bits select the BRCLK source clock in 7 6 maste
436. or 2s complement format The conversion formula for the ADC result when using straight binary format is Vp N Vp c 1023 x AD V R The ADC10 core is configured by two control registers ADC10CTLO and ADC10CTL1 The core is enabled with the ADC100N bit With few exceptions the ADC10 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 20 4 ADC10 The ADC10CLK is used both as the conversion clock and to generate the sampling period The ADC10 source clock is selected using the ADC10SSELx bits and can be divided from 1 8 using the ADC10DIVx bits Possible ADC10CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC100SC The ADC10OSC generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific data sheet for the ADC10OSC specification The user must ensure that the clock chosen for ADC10CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC10 Operation 20 2 2 ADC10 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown
437. or the six constants Y No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set 4 10 The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions For example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC dst is replaced by ADD 0 R3 dst 16 Bit MSP430X CPU CPU Registers 4 3 5 General Purpose Registers R4 to R15 The twelve CPU registers R4 to R15 contain 8 bit 16 bit or 20 bit values Any byte write to a CPU register clears bits 19 8 Any word write to a register clears bits 19 16 The only exception is the SXT instruction The SXT instruction extends the sign through the complete 20 bit register The following figures show the handling of byte word and address word data Note the reset of the leading MSBs if a register is the destination of a byte or word instruction Figure 4 10 shows byte handling 8 bit data B suffix The handling is shown for a source register and a des
438. ost when two or more transmitters start a transmission simultaneously or when the USCI operates as master but is addressed as a slave by another master in the system The UCALIFG flag is set when arbitration is lost When UCALIFG is set the UCMST bit is cleared and the 12C controller becomes a slave UCNACKIFG Not acknowledge interrupt This flag is set when an acknowledge is expected but is not received UCNACKIFG is automatically cleared when a START condition is received UCSTTIFG Start condition detected interrupt This flag is set when the 12C module detects a START condition together with its own address while in slave mode UCSTTIFG is used in slave mode only and is automatically cleared when a STOP condition is received UCSTPIFG Stop condition detected interrupt This flag is set when the I2C module detects a STOP condition while in slave mode UCSTPIFG is used in slave mode only and is automatically cleared when a START condition is received Universal Serial Communication Interface C Mode 17 23 USCI Operation C Mode Interrupt Vector Assignment USCI_Ax and USCI_Bx share the same interrupt vectors In 12C mode the state change interrupt flags UCSTTIFG UCSTPIFG UCIFG UCALIFG from USCI_Bx and UCAxRXIFG from USCI_Ax are routed to one interrupt vector The 12C transmit and receive interrupt flags UCBxTXIFG and UCBxRXIFG from USCI_Bx and UCAxTXIFG from USCI_Ax share another interrupt vector Shared Interrupt Vectors Softwar
439. ot affected N Not affected Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected Move a 16 bit constant 1800h to absolute address word EDE lower 64 K MOV 01800h amp EDE Move 1800h to EDE The contents of table EDE word data 16 bit addresses are copied to table TOM The length of the tables is 030h words Both tables reside in the lower 64K MOV EDE R10 Prepare pointer 16 bit address MOV R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMP EDE 60h R10 End of table reached JLO Loop Not yet Copy completed The contents of table EDE byte data 16 bit addresses are copied to table TOM The length of the tables is 020h bytes Both tables may reside in full memory range but must be within R10 32 K MOVA EDE R10 Prepare pointer 20 bit MOV 20h R9 Prepare counter MOV B R10 TOM EDE 1 R10 R10 points to both tables R10 1 DEC R9 Decrement counter JNZ Loop Not yet done Copy completed 4 92 16 Bit MSP430X CPU MSP430 Instructions NOP No operation Syntax NOP Operation None Emulation MOV 0 R3 Description No operation is performed The instruction may be used for the elimination of instructions during the software check or for defined waiting times Status Bits Status bits are not affected 16 Bit MSP430X CPU 4 93 MSP430 Instructions POP W POP B Syntax Operation Emulation Emulation Description Status Bits
440. ounts up to TBR max and restarts from zero as shown in Figure 13 4 The compare latch TBCLO works the same way as the other capture compare registers Figure 13 4 Continuous Mode TBR max Oh The TBIFG interrupt flag is set when the timer counts from TBR max to Zero Figure 13 5 shows the flag set cycle Figure 13 5 Continuous Mode Flag Setting Timer Set TBIFG l l Timer_B 13 7 Timer_B Operation Use of the Continuous Mode The continuous mode can be used to generate independent time intervals and output frequencies Each time an interval is completed an interrupt is generated The next time interval is added to the TBCLx latch in the interrupt service routine Figure 13 6 shows two separate time intervals ty and t4 being added to the capture compare registers The time interval is controlled by hardware not software without impact from interrupt latency Up to three Timer_B3 or 7 Timer_B7 independent time intervals or output frequencies can be generated using capture compare registers Figure 13 6 Continuous Mode Time Intervals 13 8 TBR max TBCLOa Oh EQUO Interrupt EQU1 Interrupt Timer_B TBCLib TBCLic TBCLOb TBCLOc TBCLOd TBCLia TBCLid o om v i ty i t1 Time intervals can be produced with other modes as well where TBCLO is used as the period register Their handling is more complex since the sum of the old TBCLx data and the new period c
441. ource if the user wants to use low power mode 3 because the WDT will keep SMCLK enabled for its clock source increasing the current consumption of LPM3 When the watchdog timer is not required the WDTHOLD bit can be used to hold the WDTCNT reducing power consumption 10 2 7 Software Examples Any write operation to WDTCTL must be a word operation with O5Ah WDTPW in the upper byte Periodically clear an active watchdog MOV WDTPW WDTCNTCL amp WDTCTL Change watchdog timer interval MOV WDTPW WDTCNTL WDTSSEL amp WDTCTL Stop the watchdog MOV WDTPW WDTHOLD amp WDTCTL Change WDT to interval timer mode clock 8192 interval MOV WDTPW WDTCNTCL WDTTMSEL WDTISO amp WDTCTL 10 6 Watchdog Timer Watchdog Timer Registers 10 3 Watchdog Timer Registers The WDT registers are listed in Table 10 1 Table 10 1 Watchdog timer Registers Register Short Form Register Type Address Initial State Watchdog timer control register WDTCTL Read write 0120h 06900h with PUC SFR interrupt enable register 1 1E1 Read write 0000h Reset with PUC SFR interrupt flag register 1 IFG1 Read write 0002h Reset with PUCt t WDTIFG is reset with POR Watchdog Timer 10 7 Watchdog Timer Registers WDTCTL Watchdog Timer Register 15 14 13 12 11 10 9 8 Read as 069h WDTPW must be written as 05Ah 1 0 7 6 5 4 3 2 DTHOLD WDTNMIES WDTNMI WDTTMSEL WDTCNTCL WDTSSEL rw 0 rw 0 rw 0 rw 0 r0 w rw 0 WDTPW WDTHOLD WDTN
442. outine at the 16 bit address contained in the word pointed to by register R5 20 bit address CALL R5 Start address at R5 16 Bit MSP430X CPU 4 69 MSP430 Instructions CLR W CLR B Syntax Operation Emulation Description Status Bits Example Example Example Clear destination Clear destination CLR dst or CLR W dst CLR B dst 0 gt dst MOV 0 dst MOV B 0 dst The destination operand is cleared Status bits are not affected RAM word TONI is cleared CLR TONI 0 gt TONI Register R5 is cleared CLR R5 RAM byte TONI is cleared CLR B TONI 0 gt TONI 4 70 16 Bit MSP430X CPU CLRC Syntax Operation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Clear carry bit CLRC 0 gt C BIC 1 SR The carry bit C is cleared The clear carry instruction is a word instruction N Not affected Z Not affected C Cleared V Not affected OSCOFF CPUOFF and GIE are not affected The 16 bit decimal counter pointed to by R13 is added to a 32 bit counter pointed to by R12 CLRC C 0 defines start DADD R13 0 R12 add 16 bit counter to low word of 32 bit counter DADC 2 R12 add carry to high word of 32 bit counter 16 Bit MSP430X CPU 4 71 MSP430 Instructions CLAN Syntax Operation Emulation Description Status Bits Mode Bits Example SUBR SUBRET Clear negative bit CLAN 0 gt N or NOT src AND dst g
443. overy time given by teng BUSY is cleared following each block write completion indicating the next block can be written Figure 7 10 shows the block write timing Figure 7 10 Block Write Cycle Timing BLKWRT bit Programming Voltage BUSY fd y tBlock o 25 FTG tBlock 1 63 18 fFTG tBlock 1 63 18 fFTG tend S FTG gt WAIT Write to flash e g MOV 123h amp Flash y Generate lt Cumulative Programming Time tcpy lt 4ms Vcc Current Consumption is Increased gt Programming Operation Active 14 Remove ie ai Programming Voltage Flash Memory Controller 7 13 Flash Memory Operation Block Write Flow and Example A block write flow is shown in Figure 7 8 and the following example Figure 7 11 Block Write Flow Disable watchdog yes Setup flash controller Set BLKWRT WRT 1 Write byte or word il yes Block Border H Set BLKWRT 0 yes Another Block H Set WRT 0 LOCK 1 re enable WDT 7 14 Flash Memory Controller L1 L2 L3 L4 Flash Memory Operation Write one block starting at OFOOOh Must be executed from RAM Assumes Flash is already erased 514 kHz lt SMCLK lt 952 kHz Assumes ACCVIE NMIIE OFIE 0 MOV 32 R5 Use as write counter MOV 0F000h R6 Write pointer MOV WDTPW WDTHOLD amp WDTCTL Disable WDT BIT BUSY amp FCTL3 Test BUSY JNZ L1 Loop while
444. ower 64 KB and does not overflow or underflow out of the lower 64 KB memory space The RAM and the peripheral registers can be accessed this way and existing MSP430 software is usable without modifications as shown in Figure 4 15 Figure 4 15 Indexed Mode in Lower 64 KB Lower 64 KB Rn 19 16 0 19 1615 0 FFFFF CPU Register Rn S 16 bit byte index 16 bit signed index 10000 OFFFF a Res Ly x 16 bit signed add Rn 19 0 S o z O Memory address Length Two or three words Operation The signed 16 bit index is located in the next word after the instruction and is added to the CPU register Rn The resulting bits 19 16 are cleared giving a truncated 16 bit memory address which points to an operand address in the range 00000h to OFFFFh The operand is the content of the addressed memory location Comment Valid for source and destination The assembler calculates the register index and inserts it 16 Bit MSP430X CPU 4 17 CPU Registers 4 18 Example The previous instruction adds the 8 bit data contained in source byte 1000h R5 and the destination byte OFOOOh R6 and places the result into the destination byte Source and destination bytes are both located in the lower 64 KB due to the cleared bits 19 16 of registers R5 and R6 Source Destination Before 1103Ah 11038h 11036h 11034h 0077Ah 00778h 0579Eh 0579Ch 16 Bit MSP430X CPU 1000h R5 OFOOOh R6 Register as _oa7acn n
445. p Bytes in Memory Before SWPB 15 8 7 0 After SWPB 15 8 7 0 Low Byte High Byte Figure 4 43 Swap Bytes in a Register Before SWPB 19 16 15 8 7 0 After SWPB 19 16 15 8 7 0 4 108 16 Bit MSP430X CPU SXT Syntax Operation Description Status Bits Mode Bits Example Example MSP430 Instructions Extend sign SXT dst dst 7 gt dst 15 8 dst 7 gt dst 19 8 Register Mode Register Mode the sign of the low byte of the operand is extended into the bits Rdst 19 8 Rdst 7 0 Rdst 19 8 000h afterwards Rdst 7 1 Rdst 19 8 FFFh afterwards Other Modes the sign of the low byte of the operand is extended into the high byte dst 7 0 high byte 00h afterwards dst 7 1 high byte FFh afterwards N Set if result is negative reset otherwise Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected The signed 8 bit data in EDE lower 64 K is sign extended and added to the 16 bit signed data in R7 MOV B amp EDE R5 EDE gt R5 00XXh SXT R5 Sign extend low byte to R5 19 8 ADD R5 R7 Add signed 16 bit values The signed 8 bit data in EDE PC 32 K is sign extended and added to the 20 bit data in R7 MOV B EDE R5 EDE gt R5 00XXh SXT R5 Sign extend low byte to R5 19 8 ADDA R5 R7 Add signed 20 bit values 16 Bit MSP430X CPU 4 109 MSP430 Instructions TST W TST
446. p down The timer repeatedly counts from zero up to the value of TBCLO and then back down to zero Timer_B 13 5 Timer_B Operation Up Mode The up mode is used if the timer period must be different from TBR max counts The timer repeatedly counts up to the value of compare latch TBCLO which defines the period as shown in Figure 13 2 The number of timer counts in the period is TBCLO 1 When the timer value equals TBCLO the timer restarts counting from zero If up mode is selected when the timer value is greater than TBCLO the timer immediately restarts counting from zero Figure 13 2 Up Mode TBR max TBCLO Oh The TBCCRO CCIFG interrupt flag is set when the timer counts to the TBCLO value The TBIFG interrupt flag is set when the timer counts from TBCLO to zero Figure 13 3 shows the flag set cycle Figure 13 3 Up Mode Flag Setting Timer Set TBIFG i l Set TBCCRO CCIFG Changing the Period Register TBCLO 13 6 Timer_B When changing TBCLO while the timer is running and when the TBCLO load event is immediate CLLDO 00 if the new period is greater than or equal to the old period or greater than the current count value the timer counts up to the new period If the new period is less than the current count value the timer rolls to zero However one additional count may occur before the counter rolls to zero Timer_B Operation Continuous Mode In continuous mode the timer repeatedly c
447. pare O TBCCRO Read write 0192h Reset with POR Timer_B capture compare control 1 TBCCTL1 Read write 0184h Reset with POR Timer_B capture compare 1 TBCCR1 Read write 0194h Reset with POR Timer_B capture compare control 2 TBCCTL2 Read write 0186h Reset with POR Timer_B capture compare 2 TBCCR2 Read write 0196h Reset with POR Timer_B capture compare control 3 TBCCTL3 Read write 0188h Reset with POR Timer_B capture compare 3 TBCCR3 Read write 0198h Reset with POR Timer_B capture compare control 4 TBCCTL4 Read write 018Ah Reset with POR Timer_B capture compare 4 TBCCR4 Read write 019Ah Reset with POR Timer_B capture compare control 5 TBCCTL5 Read write 018Ch Reset with POR Timer_B capture compare 5 TBCCR5 Read write 019Ch Reset with POR Timer_B capture compare control 6 TBCCTL6 Read write 018Eh Reset with POR Timer_B capture compare 6 TBCCR6 Read write 019Eh Reset with POR Timer_B interrupt vector TBIV Read only 011Eh Reset with POR 13 20 Timer_B Timer_B Registers Timer_B Control Register TBCTL 15 14 13 12 11 10 9 8 ENE rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 oom os ee rw 0 rw 0 rw 0 rw 0 rw 0 w 0 rw 0 rw 0 Unused Bit15 Unused TBCLGRP Bit TBCLx group 14 13 00 Each TBCLx latch loads independently 01 TBCL1 TBCL2 TBCCR1 CLLDx bits control the update TBCL3 TBCL4 TBCCR3 CLLDx bits control the update TBCL5 TBCL6 TBCCR5 CLLDx bits control the update TBCLO independent 10 TBCL1 TBCL2 TBCL3 T
448. partitioned into main and information memory sections There is no difference in the operation of the main and information memory sections Code or data can be located in either section The differences between the two sections are the segment size and the physical addresses The information memory has four 64 byte segments The main memory has two or more 512 byte segments See the device specific data sheet for the complete memory map of a device The segments are further divided into blocks Figure 7 2 shows the flash segmentation using an example of 32 KB flash that has eight main segments and four information segments Figure 7 2 Flash Memory Segments 32 KB Example Segmento Segmenti Segmentz O01 OF F F ia b 00100 tomato Memor Seqmentet Semen tez Segmented OXOF FFF xO FOF F wiro wi Odo OxOF EGF OxOF Ged OxOF Er F Flash Memory Controller 7 3 Flash Memory Segmentation 7 2 1 SegmentA SegmentA of the information memory is locked separately from all other segments with the LOCKA bit When LOCKA 1 SegmentA cannot be written or erased and all information memory is protected from erasure during a mass erase or production programming When LOCKA 0 SegmentA can be erased and written as any other flash memory segment and all information memory is erased during a mass erase or production programming The state of the LOCKA bit is toggled when a 1 is written to it Writing a O
449. per byte Any write to WDTCTL with any value other than O5Ah in the upper byte is a security key violation and triggers a PUC system reset regardless of timer mode Any read of WDTCTL reads 069h in the upper byte The WDT counter clock should be slower or equal than the system MCLK frequency 10 2 1 Watchdog timer Counter The watchdog timer counter WDTCNT is a 16 bit up counter that is not directly accessible by software The WDTCNT is controlled and time intervals selected through the watchdog timer control register WDTCTL The WDTCNT can be sourced from ACLK or SMCLK The clock source is selected with the WDTSSEL bit 10 2 2 Watchdog Mode After a PUC condition the WDT module is configured in the watchdog mode with an initial 32768 cycle reset interval using the DCOCLK The user must setup halt or clear the WDT prior to the expiration of the initial reset interval or another PUC will be generated When the WDT is configured to operate in watchdog mode either writing to WDTCTL with an incorrect password or expiration of the selected time interval triggers a PUC A PUC resets the WDT to its default condition and configures the RST NMI pin to reset mode 10 2 3 Interval Timer Mode 10 4 Setting the WDTTMSEL bit to 1 selects the interval timer mode This mode can be used to provide periodic interrupts In interval timer mode the WDTIFG flag is set at the expiration of the selected time interval A PUC is not generated in
450. perand Operation The 16 bit immediate source operand is used together with the 16 bit destination operand Comment Valid only for the source operand Example ADD 3456h amp TONI This instruction adds the 16 bit immediate operand 3456h to the data in the destination address TONI Source 16 bit immediate value 3456h Destination Word at address TONI Before After Address Address Space Space 2103Ah 21038h 21036h 21034h 2103Ah 21038h 21036h 21034h 3456h src 0077Ah 0077Ah 2345h__ dst 579Bh Sum 00778h 00778h 16 Bit MSP430X CPU 4 33 CPU Registers MSP430X Instructions with Immediate Mode If an MSP430X instruction is used with immediate addressing mode the constant is a 20 bit value The 4 MSBs of the constant are stored in the extension word and the 16 LSBs of the constant are stored in the word following the instruction Length Three or four words One word less if a constant of the constant generator can be used for the immediate operand Operation The 20 bit immediate source operand is used together with the 20 bit destination operand Comment Valid only for the source operand Example ADDX A 23456h amp TONI This instruction adds the 20 bit immediate operand 23456h to the data in the destination address TONI Source 20 bit immediate value 23456h Destination Two words beginning with address TONI Before After Address Address Space Space 2103Ah 21038h 21036h 2103
451. period register Their handling is more complex since the sum of the old TACCRx data and the new period can be higher than the TACCRO value When the previous TACCRx value plus tx is greater than the TACCRO data TACCRO 1 must be subtracted to obtain the correct time interval Timer_A Operation Up Down Mode The up down mode is used if the timer period must be different from OFFFFh counts and if a symmetrical pulse generation is needed The timer repeatedly counts up to the value of compare register TACCRO and back down to zero as shown in Figure 12 7 The period is twice the value in TACCRO Figure 12 7 Up Down Mode OFFFFh TACCRO Oh The count direction is latched This allows the timer to be stopped and then restarted in the same direction it was counting before it was stopped If this is not desired the TACLR bit must be set to clear the direction The TACLR bit also clears the TAR value and the timer clock divider In up down mode the TACCRO CCIFG interrupt flag and the TAIFG interrupt flag are set only once during a period separated by 1 2 the timer period The TACCRO CCIFG interrupt flag is set when the timer counts from TACCRO 1 to TACCRO and TAIFG is set when the timer completes counting down from 0001h to 0000h Figure 12 8 shows the flag set cycle Figure 12 8 Up Down Mode Flag Setting Up Down Set TAIFG i i Set TACCRO CCIFG Timer_A 12 9 Timer_A Operation Changing the Period Re
452. plement of the source 1 to the destination The source operand is not affected The result is written to the destination operand Both operands may be located in the full address space Set if result is negative src gt dst reset if positive src lt dst Set if result is zero src dst reset otherwise src dst Set if there is a carry from the MSB reset otherwise Set if the subtraction of a negative source operand from a positive des tination operand delivers a negative result or if the subtraction of a posi tive source operand from a negative destination operand delivers a positive result reset otherwise no overflow OSCOFF CPUOFF and GIE are not affected A 20 bit constant 87654h is subtracted from EDE LSBs and EDE 2 MSBs SUBX A 87654h EDE Subtract 87654h from EDE 2 EDE A table word pointed to by R5 20 bit address is subtracted from R7 Jump to label TONI if R7 contains zero after the instruction R5 is auto incremented by 2 R7 19 16 0 SUBX W R5 R7 Subtract table number from R7 R5 2 JZ TONI R7 R5 before subtraction R7 lt gt R5 before subtraction Byte CNT is subtracted from the byte R12 points to in the full address space Address of CNT is within PC 512 K SUBX B CNT 0 R12 Subtract CNT from R12 Note Use SUBA for the following two cases for better density and execution SUBX A Rsrc Rdst or SUBX A imm20 Rdst 16 Bit MSP430X CPU 4 147 Extended Instructions
453. plied by 2 RLA R7 Shift left R7 x 2 The low byte of R7 is multiplied by 4 RLA B R7 Shift left low byte of R7 x 2 RLA B R7 Shift left low byte of R7 x 4 MAA AA ALTA aT Note RLA Substitution The assembler does not recognize the instruction RLA R5 RLA B R5 or RLA B OR5 It must be substituted by ADD R5 2 R5 ADD B R5 1 R5 or ADD B R5 3 58 RISC 16 Bit CPU RLC W RLC B Syntax Operation Emulation Description Instruction Set Rotate left through carry Rotate left through carry RLC dst or RLC W dst RLC B dst C lt MSB lt MSB 1 LSB 1 lt LSB lt C ADDC dst dst The destination operand is shifted left one position as shown in Figure 3 15 The carry bit C is shifted into the LSB and the MSB is shifted into the carry bit C Figure 3 15 Destination Operand Carry Left Shift Status Bits Mode Bits Example Example Example 0 a Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the MSB Set if an arithmetic overflow occurs the initial value is 04000h lt dst lt OCOOOh reset otherwise Set if an arithmetic overflow occurs the initial value is 040h lt dst lt OCOh reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is shifted left one position RLC R5 R5x2 C gt R5 The input P1IN 1 information is shifted into the LSB of R5 BIT B 2 amp P1IN Information gt C
454. po 4095 x R The ADC12 core is configured by two control registers ADC12CTLO and ADC12CTL1 The core is enabled with the ADC120N bit The ADC12 can be turned off when not in use to save power With few exceptions the ADC12 control bits can only be modified when ENC 0 ENC must be set to 1 before any conversion can take place Conversion Clock Selection 21 4 ADC12 The ADC12CLK is used both as the conversion clock and to generate the sampling period when the pulse sampling mode is selected The ADC12 source clock is selected using the ADC12SSELx bits and can be divided from 1 8 using the ADC12DIVx bits Possible ADC12CLK sources are SMCLK MCLK ACLK and an internal oscillator ADC120SC The ADC12O0SC generated internally is in the 5 MHz range but varies with individual devices supply voltage and temperature See the device specific datasheet for the ADC12OSC specification The user must ensure that the clock chosen for ADC12CLK remains active until the end of a conversion If the clock is removed during a conversion the operation will not complete and any result will be invalid ADC12 Operation 21 2 2 ADC12 Inputs and Multiplexer The eight external and four internal analog signals are selected as the channel for conversion by the analog input multiplexer The input multiplexer is a break before make type to reduce input to input noise injection resulting from channel switching as shown in Figure 21 2 The input multiplex
455. polarity and phase of UCxCLK are independently configured via the UCCKPL and UCCKPH control bits of the USCI Timing for each case is shown in Figure 16 4 Figure 16 4 USCI SPI Timing with UCMSB 1 UC UC i i i i i i i i cKPH cKBL let 1 j 2 3 p 4 5 6 7 8 o 0 UCxCLK oo 1 UCXCLK Y 1 0 UCxXCLK 1 1 UCxCLK Move to UCxTXBUF TX Data Shifted Out j j j j j j j RX Sample Points Universal Serial Communication Interface SPI Mode 16 11 USCI Operation SPI Mode 16 3 7 Using the SPI Mode with Low Power Modes 16 12 The USCI module provides automatic clock activation for SMCLK for use with low power modes When SMCLK is the USCI clock source and is inactive because the device is in a low power mode the USCI module automatically activates it when needed regardless of the control bit settings for the clock source The clock remains active until the USCI module returns to its idle condition After the USCI module returns to the idle condition control of the clock source reverts to the settings of its control bits Automatic clock activation is not provided for ACLK When the USCI module activates an inactive clock source the clock source becomes active for the whole device and any peripheral configured to use the clock source may be affected For example a timer using SMCLK will increment while the USCI module forces SMCLK active In SPI slave mode no internal clock source is required because the cloc
456. printed circuit board layout and grounding techniques should be followed to eliminate ground loops unwanted parasitic effects and noise Ground loops are formed when return current from the A D flows through paths that are common with other analog or digital circuitry If care is not taken this current can generate small unwanted offset voltages that can add to or subtract from the reference or input voltages of the A D converter The connections shown in Figure 20 14 help avoid this In addition to grounding ripple and noise spikes on the power supply lines due to digital switching or switching power supplies can corrupt the conversion result A noise free design is important to achieve high accuracy Figure 20 14 ADC10 Grounding and Noise Considerations internal Vref Digital Power Supply Deo oupling WuF 1 nF Figure 20 15 ADC10 Grounding and Noise Considerations external Vref Dig tal Power Supply Decoupling WuF 1 nF Ling an Esteal Pont Petare noe Ling an Ertenal Hagai w Reference 20 22 ADC10 ADC10 Operation 20 2 10 ADC10 Interrupts One interrupt and one interrupt vector are associated with the ADC10 as shown in Figure 20 16 When the DTC is not used ADC10DTC1 0 ADC10IFG is set when conversion results are loaded into ADC1O0MEM When DTC is used ADC10DTC1 gt 0 ADC1OIFG is set when a block transfer completes and the internal transfer counter n O If both the ADC10I
457. r or may be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the ADC120V and ADC12IFG3 interrupts are pending when the interrupt service routine accesses the ADC12IV register the ADC120V interrupt condition is reset automatically After the RETI instruction of the interrupt service routine is executed the ADC12IFG3 generates another interrupt ADC12 Operation ADC12 Interrupt Handling Software Example The following software example shows the recommended use of ADC12IV and the handling overhead The ADC12IV value is added to the PC to automatically jump to the appropriate routine The numbers at the right margin show the necessary CPU cycles for each instruction The software overhead for different interrupt sources includes interrupt latency and return from interrupt cycles but not the task handling itself The latencies are LJ ADC12IFGO ADC12IFG14 ADC12TOV and ADC120V 16 cycles JJ ADC12IFG15 14 cycles The interrupt handler for ADC12IFG15 shows a way to check immediately if a higher prioritized interrupt occurred during the processing of ADC12IFG15 This saves nine cycles if another ADC12 interrupt is pending Interrupt handler for ADC12 INT _ADC12 Enter Interrupt Service Routine 6 ADD amp ADC121IV PC Add offset to PC 3 RETI Vector 0 No interrupt 5 JMP ADOV Vector 2 ADC overflow 2 JMP ADTOV Vector 4 ADC timing overflow 2
458. r settings for specific frequencies stored in information memory segment A To use the calibrated settings the information is copied into the DCOCTL and BCSCTL1 registers The calibrated settings affect the DCOx MODx and RSELx bits and clear all other bits except XT20FF which remains set The remaining bits of BCSCTL1 can be set or cleared as needed with BIS B or BIC B instructions Set DCO to 1 MHz MOV B amp CALBC1 1MHZ amp BCSCTL1 Set range MOV B amp CALDCO_1MHZ amp DCOCTL Set DCO step modulation Using an External Resistor Rosc for the DCO 5 8 Some MSP430F2xx devices provide the option to source the DCO current through an external resistor Rosc tied to DVcc when DCOR 1 In this case the DCO has the same characteristics as MSP430x1xx devices and the RSELx setting is limited to 0 to 7 with the RSEL3 ignored This option provides an additional method to tune the DCO frequency by varying the resistor value See the device specific data sheet for parameters Basic Clock Module Basic Clock Module Operation 5 2 6 DCO Modulator The modulator mixes two DCO frequencies fpco and fpco 1 to produce an intermediate effective frequency between fpco and fpco 1 and spread the clock energy reducing electromagnetic interference EMI The modulator mixes foco and fpco 1 for 32 DCOCLK clock cycles and is configured with the MODx bits When MODx 0 the modulator is off The modulator mixing formula is t 32 M
459. r unsigned JNC label JLO label lf C 0 PC 2 x Offset PC If C 1 execute following instruction The carry bit C in the status register is tested If it is reset the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If C is set the instruction after the jump is executed JNC is used for the test of the carry bit C JLO is used for the comparison of unsigned numbers Status bits are not affected OSCOFF CPUOFF and GIE are not affected If byte EDE lt 15 the program continues at Label2 Unsigned data Data in lower 64 K program in full memory range CMP B 15 amp EDE Is EDE lt 15 Info to C JLO Label2 Yes EDE lt 15 C 0 No EDE gt 15 Continue The word TONI is added to R5 If no carry occurs continue at Label0 The address of TONI is within PC 32 K ADD TONI R5 TONI R5 gt R5 Carry gt C JNC LabelO No carry Carry 1 continue here 4 90 16 Bit MSP430X CPU JNZ JNE Syntax Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Jump if Not Zero Jump if Not Equal JNZ label JNE label If Z 0 PC 2 x Offset gt PC lfZ 1 execute following instruction The zero bit Z in the status register is tested If it is reset the signed 10 bit word offset
460. r DECCNTR DADD 10h amp DECCNTR Add 10 to 4 digit BCD counter The eight digit BCD number contained in 16 bit RAM addresses BCD and BCD 2 is added decimally to an eight digit BCD number contained in R4 and R5 BCD 2 and R5 contain the MSDs The carry C is added and cleared CLRC Clear carry DADD W amp BCD R4 Add LSDs R4 19 16 0 DADD W amp BCD 2 R5 Add MSDs with carry R5 19 16 0 JC OVERFLOW Result gt 9999 9999 go to error routine Result ok The two digit BCD number contained in word BCD 16 bit address is added decimally to a two digit BCD number contained in R4 The carry C is added also R4 19 8 0 CLRC Clear carry DADD B amp BCD R4 Add BCD to R4 decimally R4 0 00ddh 4 76 16 Bit MSP430X CPU DEC W DEC B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Decrement destination Decrement destination DEC dst or DEC W dst DEC B dst dst 1 gt dst SUB 1 dst SUB B 1 dst The destination operand is decremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 1 reset otherwise C Reset if dst contained 0 set otherwise V Set if an arithmetic overflow occurs otherwise reset Set if initial value of destination was 08000h otherwise reset Set if initial value of destination was 080h otherwise reset OSCOFF CPUOFF and GIE are not affecte
461. r example the single operand instruction CLR dst is emulated by the double operand instruction with the same length MOV R3 dst where the 0 is replaced by the assembler and R3 is used with As 00 INC is replaced by ADD dst 0 R3 dst RISC 16 Bit CPU 3 7 CPU Registers 3 2 5 General Purpose Registers R4 to R15 The twelve registers R4 to R15 are general purpose registers All of these registers can be used as data registers address pointers or index values and can be accessed with byte or word instructions as shown in Figure 3 7 Figure 3 7 Register Byte Byte Register Operations Register Byte Operation Byte Register Operation High Byte Low Byte High Byte Low Byte Example Register Byte Operation Example Byte Register Operation R5 0A28Fh R5 01202h R6 0203h R6 0223h Mem 0203h 012h Mem 0223h O5Fh ADD B R5 0 R6 ADD B R6 R5 08Fh O5Fh 012h 002h 0A1h 00061h Mem 0203h OAth R5 00061h C 0 Z 0 N 1 C 0 Z 0 N 0 Low byte of register Addressed byte Addressed byte Low byte of register gt Addressed byte gt Low byte of register zero to High byte 3 8 RISC 16 Bit CPU Addressing Modes 3 3 Addressing Modes Seven addressing modes for the source operand and four addressing modes for the destination operand can address the complete address space with no exceptions The bit numbers in Table 3 3 describe the contents of the As source and Ad destination mode
462. r mode UCxCLK is always used in slave mode 00 NA 01 ACLK 10 SMCLK 11 SMCLK Unused Bits Unused 5 1 UCSWRST_ Bito Software reset enable 0 Disabled USCI reset released for operation 1 Enabled USCI logic held in reset state 16 18 Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode UCAxBRO USCI_Ax Bit Rate Control Register 0 UCBxBRO USCI_Bx Bit Rate Control Register 0 7 6 5 4 3 2 1 0 UCBRx low byte rw rw rw rw rw rw rw rw UCAxBR1 USCI_Ax Bit Rate Control Register 1 UCBxBR1 USCI_Bx Bit Rate Control Register 1 7 6 5 4 3 2 1 0 rw rw rw rw rw rw rw rw UCBRx Bit clock prescaler setting The 16 bit value of UCxxBRO UCxxBR1 x 256 forms the prescaler value Universal Serial Communication Interface SPI Mode 16 19 USCI Registers SPI Mode UCAxSTAT USCI_Ax Status Register UCBxSTAT USCI_Bx Status Register 7 6 5 4 3 2 1 0 ot rw 0 rw 0 rw 0 i rw 0 rw 0 rw 0 r 0 t UCAxSTAT USCI_Ax UCBxSTAT USCI_Bx UCLISTEN Bit 7 Listen enable The UCLISTEN bit selects loopback mode 0 Disabled 1 Enabled The transmitter output is internally fed back to the receiver UCFE Bit 6 Framing error flag This bit indicates a bus conflict in 4 wire master mode UCFE is not used in 3 wire master or any slave mode 0 No error 1 Bus conflict occurred UCOE Bit 5 Overrun error flag This bit is set when a character is transferred into UCxRXBUF before the previous character was read UCOE is cleared auto
463. r on 0 Reference off 1 Reference on ADC12 on 0 ADC 12 off 1 ADC12 on ADC12MEMxX overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Overflow interrupt disabled 1 Overflow interrupt enabled ADC 12 conversion time overflow interrupt enable The GIE bit must also be set to enable the interrupt 0 Conversion time overflow interrupt disabled 1 Conversion time overflow interrupt enabled Enable conversion 0 ADC 12 disabled 1 ADC 12 enabled Start conversion Software controlled sample and conversion _ start ADC12SC and ENC may be set together with one instruction ADC12SC is reset automatically 0 No sample and conversion start 1 Start sample and conversion ADC12 Registers ADC12CTL1 ADC12 Control Register 1 15 14 13 12 11 10 9 8 rw 0 rw 0 7 6 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 5 4 3 2 1 0 ADC12 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 r 0 _ Modifiable only when ENC 0 CSTART Bits ADDx 15 12 SHSx Bits 11 10 SHP Bit 9 ISSH Bit 8 ADC12DIVx Bits 7 5 Conversion start address These bits select which ADC12 conversion memory register is used for a single conversion or for the first conversion in a sequence The value of CSTARTADDx is O to OFh corresponding to ADC12MEMO to ADC12MEM15 Sample and hold source select 00 ADC12SC bit 01 Timer_A OUT1 10 Timer_B OUTO 11 Timer_B OUT1 Sample and hold pulse mode select This bit selects
464. r settings and are shown in Table 18 3 The gain for the amplifier is selected by the OAFBRx bits for OA1 and is shown in Table 18 4 The OAx interconnections are shown in Figure 18 3 Table 18 3 Two Opamp Differential Amplifier Control Register Settings Register Settings binary OAOCTLO XX XX XX 0 0 OAOCTL1 000 111 0x OA1CTLO 11 xx xx x x OA1CTL1 xxx 110 0 x Table 18 4 Two Opamp Differential Amplifier Gain Settings OA1 OAFBRx Gain 000 0 001 1 3 010 1 011 1 2 3 100 3 101 41 3 110 7 111 15 Figure 18 2 Two Opamp Differential Amplifier 18 8 OA V1 Vdiff V2 V1 xR2 R1 Figure 18 3 Two Opamp Differential Amplifier OAx Interconnections OAPx OAxI0 00 OAOI1 01 OAxIA 10 OAxIB 11 OAPx OAxI0 00 OAOI1 01 OAPMx OAxIA 10 OAxIB 11 001 else OAFBRx 000 else OA Operation OAPMx OAADCx OAXFB OA OA Operation Figure 18 4 shows an example of a three opamp differential amplifier using OAO OA1 and OA2 Three opamps are not available on all devices See device specific data sheet for implementation The control register settings are shown in Table 18 5 The gain for the amplifier is selected by the OAFBRx bits of OAO and OA2 The OAFBRx settings for both OAO and OA2 must be equal The gain settings are shown in Table 18 6 The OAx interconnections are shown in Figure 18 5 Table 18 5 Three Opamp Differen
465. r the destination operand use 16 bit or 20 bit addresses The MSP430 and MSP430X instructions are usable throughout the entire 1 MB memory range Table 4 3 Source Destination Addressing As Ad 00 0 01 1 01 1 01 1 10 11 11 Addressing Mode Syntax Register mode Rn Indexed mode X Rn Symbolic mode ADDR Absolute mode amp ADDR Indirect register Rn mode Indirect Rn autoincrement Immediate mode N Description Register contents are operand Rn X points to the operand X is stored in the next word or stored in combination of the preceding extension word and the next word PC X points to the operand X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X PC is used The word following the instruction contains the absolute address X is stored in the next word or stored in combination of the preceding extension word and the next word Indexed mode X SR is used Rn is used as a pointer to the operand Rn is used as a pointer to the operand Rn is incremented afterwards by 1 for B instructions by 2 for W instructions and by 4 for A instructions N is stored in the next word or stored in combination of the preceding extension word and the next word Indirect autoincrement mode PC is used The seven addressing modes are explained in detail in the following sections Most of the examples show the same addressing
466. r_A Operation 19 2 3 Input Short Switch The CASHORT bit shorts the comparator_A inputs This can be used to build a simple sample and hold for the comparator as shown in Figure 19 2 Figure 19 2 Comparator_A Sample And Hold Sampling Capacitor C y E Analog Inputs The required sampling time is proportional to the size of the sampling capacitor Cg the resistance of the input switches in series with the short switch Ri and the resistance of the external source Rs The total internal resistance Ry is typically in the range of 2 10 kQ The sampling capacitor Cs should be greater than 100pF The time constant Tau to charge the sampling capacitor Cs can be calculated with the following equation Tau R Rs x Cs Depending on the required accuracy 3 to 10 Tau should be used as a sampling time With 3 Tau the sampling capacitor is charged to approximately 95 of the input signals voltage level with 5 Tau it is charge to more than 99 and with 10 Tau the sampled voltage is sufficient for 12 bit accuracy Comparator_A 19 5 Comparator_A Operation 19 2 4 Output Filter The output of the comparator can be used with or without internal filtering When control bit CAF is set the output is filtered with an on chip RC filter Any comparator output oscillates if the voltage difference across the input terminals is small Internal and external parasitic effects and cross coupling on and between signal lines power
467. rand The substitute for the destination operand is O Rdst ADDX W R5 2100h R6 This instruction adds the two 16 bit operands contained in the source and the destination addresses and places the result into the destination Source Word pointed to by R5 R5 contains address 3 579Ch for this example Destination Word pointed to by R6 2100h which results in address 45678h 2100h 7778h Before After Address Register Address Register Space Space 21038h R5 3579Ch 21038h PC R5 3579Ch 21036h R6 45678h 21036h R6 45678h 21034h PC 21034h 45678h 5432h src 4777Ah 02100h 4777Ah 2345h__ dst eae 47778h oe 7777h Sum 3579Eh 3579Eh 3579Ch 3579Ch R5 16 Bit MSP430X CPU 4 31 CPU Registers 4 4 6 Indirect Autoincrement Mode The Indirect Autoincrement mode uses the contents of the CPU register Rsrc as the source operand Rsrc is then automatically incremented by 1 for byte instructions by 2 for word instructions and by 4 for address word instructions immediately after accessing the source operand If the same register is used for source and destination it contains the incremented address for the destination access Indirect Autoincrement mode always uses 20 bit addresses Length One two or three words Operation The operand is the content of the addressed memory location Comment Valid only for the source operand Example ADD B R5 0 R6 This instruction adds the 8 bit data contained in the source and the
468. rating frequency has been significantly increased The DCO temperature stability has been significantly improved Flash Memory The information memory has 4 segments of 64 bytes each Segmenta is individually locked with the LOCKA bit All information if protected from mass erase with the LOCKA bit Segment erases can be interrupted by an interrupt Flash updates can be aborted by an interrupt Flash programming voltage has been lowered to 2 2 V Program erase time has been reduced Clock failure aborts a flash update Digital I O All ports have integrated pullup pulldown resistors P2 6 and P2 7 functions have been added to 20 and 28 pin devices These are shared functions with XIN and XOUT Software must not clear the P2SELx bits for these pins if crystal operation is required Comparator_A Comparator_A has expanded input capability with a new input multiplexer Low Power Typical LPM3 current consumption has been reduced almost 50 at 3 V DCO startup time has been significantly reduced Operating The maximum operating frequency is 16 MHz at 3 3 V frequency BSL An incorrect password causes a mass erase BSL entry sequence is more robust to prevent accidental entry and erasure Introduction 1 7 Introduction Chapter 2 System Resets Interrupts and Operating Modes This chapter describes the MSP430x2xx system resets interrupts and operating modes Topi
469. rc xor dst gt dst The source and destination operands are exclusively ORed The result is placed into the destination The source operand is not affected The previous content of the destination is lost N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise C not Z V Set if both operands are negative before execution reset otherwise OSCOFF CPUOFF and GIE are not affected Toggle bits in word CNTR 16 bit data with information bit 1 in address word TONI Both operands are located in lower 64 K XOR amp TONI amp CNTR Toggle bits in CNTR A table word pointed to by R5 20 bit address is used to toggle bits in R6 R6 19 16 0 XOR R5 R6 Toggle bits in R6 Reset to zero those bits in the low byte of R7 that are different from the bits in byte EDE R7 19 8 0 The address of EDE is within PC 32 K XOR B EDE R7 Set different bits to 1 in R7 INV B R7 Invert low byte of R7 high byte is Oh 16 Bit MSP430X CPU 4 111 Extended Instructions 4 6 3 Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20 bit address space Some MSP430X instructions require an additional word of op code called the extension word All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word The MSP430X extended instructions are listed and de
470. rd data 20 bit addresses are copied to table TOM The length of the table is 030h words MOVA EDE R10 Prepare pointer 20 bit address MOVX W R10 TOM EDE 2 R10 R10 points to both tables R10 2 CMPA EDE 60h R10 End of table reached JLO Loop Not yet Copy completed The contents of table EDE byte data 20 bit addresses are copied to table TOM The length of the table is 020h bytes MOVA EDE R10 Prepare pointer 20 bit MOV 20h R9 Prepare counter MOVX B R10 TOM EDE 1 R10 R10 points to both tables R10 1 DEC R9 Decrement counter JNZ Loop Not yet done Copy completed 16 Bit MSP430X CPU 4 129 Extended Instructions 4 130 Ten of the 28 possible addressing combinations of the MOVX A instruction can use the MOVA instruction This saves two bytes and code cycles Examples for the addressing combinations are MOVX A MOVX A MOVX A MOVX A MOVX A MOVX A Rsrc Rdst imm20 Rdst amp abs20 Rdst O Rsrc Rast O Rsrc Rdst Rsrc amp abs20 MOVA MOVA MOVA MOVA MOVA MOVA Rsrc Rdst Reg Reg ttimm20 Rdst Immediate Reg amp abs20 Rdst Absolute Reg Rsrc Rdst __ Indirect Reg Rsrc Rdst Indirect Auto Reg Rsrc amp abs20 Reg Absolute The next four replacements are possible only if 16 bit indexes are sufficient for the addressing MOVX A MOVX A MOVX A MOVX A 16 Bit MSP430X CPU z20 Rsrc Rdst Rsrc z20 Radst symb20 Rdst Rsrc symb20 MOVA z16 Rsrc Rdst Indexed Reg MOVA
471. re listed in Table 15 4 and Table 15 5 for a 32768 Hz crystal sourcing ACLK and typical SMCLK frequencies Ensure that the selected BRCLK frequency does not exceed the device specific maximum USCI input frequency see the device specific data sheet The receive error is the accumulated time versus the ideal scanning time in the middle of each bit The worst case error is given for the reception of an 8 bit character with parity and one stop bit including synchronization error The transmit error is the accumulated timing error versus the ideal time of the bit period The worst case error is given for the transmission of an 8 bit character with parity and stop bit Universal Serial Communication Interface UART Mode 15 21 USCI Operation UART Mode Table 15 4 Commonly Used Baud Rates Settings and Errors UCOS16 0 BRCLK Baud frequency Rate UCBRx UCBRSx UCBRFx Max TX Error Max RX Error Hz Baud 32 768 1200 27 2 0 2 8 1 4 5 9 2 0 32 768 2400 13 6 0 4 8 6 0 9 7 8 3 32 768 4800 6 7 0 12 1 5 7 13 4 19 0 32 768 9600 3 3 0 21 1 15 2 44 3 21 3 1 048 576 9600 109 2 0 0 2 0 7 1 0 0 8 1 048 576 19200 54 5 0 1 1 1 0 1 5 2 5 1 048 576 38400 27 2 0 2 8 1 4 5 9 2 0 1 048 576 56000 18 6 0 3 9 1 1 4 6 5 7 1 048 576 115200 9 1 0 1 1 10 7 11 5 11 3 1 048 576 128000 8 1 0 8 9 7 5 13 8 14 8 1 048 576 256000 4 1 0 2 3 25 4 13 4 38 8 1 000 000 9600 104 1 0 0 5 0 6 0 9 1 2 1 000 000 19200 52 0 0 1 8 0 2 6 0 9 1
472. regular program code if necessary Some module enable bits interrupt enable bits and interrupt flags are located in the SFRs The SFRs are located in the lower address range and are implemented in byte format SFRs must be accessed using byte instructions See the device specific data sheet for the SFR configuration System Resets Interrupts and Operating Modes System Reset and Initialization Table 2 1 Interrupt Sources Flags and Vectors SYSTEM WORD INTERRUPT SOURCE INTERRUPT FLAG INTERRUPT ADDRESS PRIORITY Power up external reset watchdog aa is flash password WDTIEG Reset OFFFEh 31 highest illegal instruction KEYV fetch NMI oscillator fault NMIIFG non maskable flash memory access OFIFG non maskable OFFFCh 30 violation ACCVIFG non maskable device specific OFFFAh 29 device specific OFFF8h 28 device specific OFFF6h 27 Watchdog timer WDTIFG maskable OFFF4h 26 device specific OFFF2h 25 device specific OFFFOh 24 device specific OFFEEh 23 device specific OFFECh 22 device specific OFFEAh 21 device specific OFFE8h 20 device specific OFFE6h 19 device specific OFFE4h 18 device specific OFFE2h 17 device specific OFFEOh 16 device specific OFFDEh 15 device specific OFFDCh 14 device specific OFFDAh 13 device specific OFFD8h 12 device specific OFFD6h 11 device specific OFFD4h 10 device specific OFFD2h 9 device specific OFFDOh 8 device specific OFFCEh 7 device specific OFFCCh 6 device specific OFFCAh 5 devi
473. reset with software 0 No interrupt pending 1 Interrupt pending 21 26 ADC12 ADC12 Registers ADC12IV ADC12 Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 rO ro r 0 r 0 r 0 r 0 r 0 ro ADC12IVx Bits ADC 12 interrupt vector value 15 0 ADC12IV Contents 000h 002h 004h 006h 008h O00Ah 00Ch OOEh 010h 012h 014h 016h 018h 01Ah 01Ch 01Eh 020h 022h 024h Interrupt Source No interrupt pending ADC12MEM x overflow Conversion time overflow ADC12MEM60 interrupt flag ADC12MEM1 interrupt flag ADC12MEN2 interrupt flag ADC12MEMs3 interrupt flag ADC12MEM4 interrupt flag ADC12MEM5 interrupt flag ADC12MEM6 interrupt flag ADC12MEN7 interrupt flag ADC12MEMS8 interrupt flag ADC12MEMS 9 interrupt flag ADC12MEM10 interrupt flag ADC12MEM11 interrupt flag ADC12MEM12 interrupt flag ADC12MEM 13 interrupt flag ADC12MEM 14 interrupt flag ADC12MEM15 interrupt flag Interrupt Interrupt Flag Priority ADC12IFGO ADC12IFG1 ADC12IFG2 ADC12IFG3 ADC12IFG4 ADC12IFG5 ADC12IFG6 ADC12IFG7 ADC12IFG8 ADC12IFG9 ADC12IFG10 ADC12IFG11 ADC12IFG12 ADC12IFG13 ADC12IFG14 ADC12IFG15 ADC12 Highest Lowest 21 27 21 28 ADC12 Chapter 22 TLV Structure The Tag Length Value TLV structure is used in selected MSP430x2xx devices to provide device specific information in the device s flash memory SegmentA such as calibration data For the device dependent implemen
474. ress xxx5h Introduction 1 5 Address Space Figure 1 3 Bits Bytes and Words in a Byte Organized Memory xxxAh xxx9h xxx8h xxx7h xxx6h Word High Byte xxx5h Word Low Byte xxx4h 1 6 Introduction MSP430x2xx Family Enhancements 1 5 MSP430x2xx Family Enhancements Table 1 1 highlights enhancements made to the MSP430x2xx family The enhancements are discussed fully in the following chapters or in the case of improved device parameters shown in the device specific data sheet Table 1 1 MSP430x2xx Family Enhancements Subject Enhancement Reset Brownout reset is included on all MSP430x2xx devices PORIFG and RSTIFG flags have been added to IFG1 to indicate the cause of a reset An instruction fetch from the address range 0x0000 0x01FF will reset the device Watchdog All MSP430x2xx devices integrate the Watchdog Timer Timer module WDT The WDT ensures the clock source for the timer is never disabled Basic Clock The LFXT1 oscillator has selectable load capacitors in LF mode System The LFXT1 supports up to 16 MHz crystals in HF mode The LFXT1 includes oscillator fault detection in LF mode The XIN and XOUT pins are shared function pins on 20 and 28 pin devices The external Rosc feature of the DCO not supported on some devices Software should not set the LSB of the BCSCTL2 register in this case See the device specific data sheet for details The DCO ope
475. rity Vote Taken Majority Vote Taken Majority Vote Taken The ideal sampling time tyitiaeanxl is in the middle of a bit period titiga RxL saiel 0 5 The real sampling time tpt x i is equal to the sum of all previous bits according to the formulas shown in the transmit timing section plus one half BITCLK for the current bit i plus the synchronization error tsync This results in the following t x i for the low frequency baud rate mode it toitaxll tsyne gt Thal r INT UCBRY Mucensdil o BRCLK J where Toivaxli UCBRx F Mucsrsxlil fencik Modulation of bit i from Table 15 2 Mucersxli 15 20 Universal Serial Communication Interface UART Mode USCI Operation UART Mode For the oversampling baud rate mode the sampling time t axli of bit i is calculated by int toitaxll tsyne S Tori j 0 j 4 7 Mucgrsill 8 Mucersxlil UCBRx y Muesaral BRCLK 0 where 15 Toraxli vs Mycersuli UCBRx gt el j 0 j 7 Mycprsxlll J Mucarrali Sum of ones from columns 0 7 Mucsrsadil j 0 from the corresponding row in Table 15 3 Mucsrsxl Modulation of bit i from Table 15 2 This results in an error normalized to one ideal bit time 1 baudrate according to the following formula Erroraxlil toiaxlil tonidoa lil Baudrate 100 15 3 13 Typical Baud Rates and Errors Standard baud rate data for UCBRx UCBRSx and UCBRF x a
476. roduction 16 Bit MSP430X CPU 4 3 Interrupts 4 2 Interrupts The MSP430X uses the same interrupt structure as the MSP430 _j Vectored interrupts with no polling necessary Y Interrupt vectors are located downward from address OFFFEh Interrupt operation for both MSP430 and MSP430X CPUs is described in Chapter 2 System Resets Interrupts and Operating modes Section 2 Interrupts The interrupt vectors contain 16 bit addresses that point into the lower 64 KB memory This means all interrupt handlers must start in the lower 64 KB memory even in MSP430X devices During an interrupt the program counter and the status register are pushed onto the stack as shown in Figure 4 2 The MSP430X architecture efficiently stores the complete 20 bit PC value by automatically appending the PC bits 19 16 to the stored SR value on the stack When the RETT instruction is executed the full 20 bit PC is restored making return from interrupt to any address in the memory range possible Figure 4 2 Program Counter Storage on the Stack for Interrupts PC 15 0 SP PC 19 16 SR 11 0 4 4 16 Bit MSP430X CPU CPU Registers 4 3 CPU Registers The CPU incorporates sixteen registers RO to R15 Registers RO R1 R2 and R3 have dedicated functions R4 to R15 are working registers for general use 4 3 1 Program Counter PC The 20 bit program counter PC RO points to the next instruction to be executed Each instruction uses an even number of bytes
477. routine is requested Only the individual enable bit must be set for non maskable interrupts to be requested Interrupt Acceptance The interrupt latency is 5 cycles CPUx or 6 cycles CPU starting with the acceptance of an interrupt request and lasting until the start of execution of the first instruction of the interrupt service routine as shown in Figure 2 6 The interrupt logic executes the following 1 Any currently executing instruction is completed 2 The PC which points to the next instruction is pushed onto the stack 3 The SR is pushed onto the stack 4 The interrupt with the highest priority is selected if multiple interrupts occurred during the last instruction and are pending for service 5 The interrupt request flag resets automatically on single source flags Multiple source flags remain set for servicing by software 6 The SR is cleared This terminates any low power mode Because the GIE bit is cleared further interrupts are disabled 7 The content of the interrupt vector is loaded into the PC the program continues with the interrupt service routine at that address Figure 2 6 Interrupt Processing Before After Interrupt Interrupt SP gt TOS 2 10 System Resets Interrupts and Operating Modes System Reset and Initialization Return From Interrupt The interrupt handling routine terminates with the instruction RETI return from an interrupt service routine The return from the inter
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479. rresponding channel This feature delays the interrupt request for a completed conversion by up to four conversion cycles allowing the digital filter to settle prior to generating an interrupt request The delay is applied each time the SD16SC bit is set or when the SD16GAINx or SD16INCHx bits for the channel are modified SD16INTDLYx disables overflow interrupt generation for the channel for the selected number of delay cycles Interrupt requests for the delayed conversions are not generated during the delay SD16_A 24 15 SD16_A Registers 24 3 SD16_A Registers The SD16_A registers are listed in Table 24 5 Table 24 5 5D16_A Registers Register Short Form Register Type Address Initial State SD16_A control SD16CTL Read write 0100h Reset with PUC SD16_A interrupt vector SD16IV Read write 0110h Reset with PUC SD16_A channel 0 control SD16CCTLO Read write 0102h Reset with PUC SD16_A conversion memory SD16MEMO Read write 0112h Reset with PUC SD16_A input control SD16INCTLO Read write OBOh Reset with PUC SD16_A analog enable SD16AE Read write 0B7h Reset with PUC 24 16 SD16_A SD16_A Registers SD16CTL SD16_A Control Register 15 ro 7 rw 0 Reserved SD16XDIVx SD16LP SD16DIVx SD16SSELx SD16 VMIDON SD16 REFON SD160VIE Reserved 14 8 rw 0 ro 6 Bits 15 12 Bits 11 9 Bit 8 Bits 7 6 Bits 5 4 Bit 3 Bit 2 Bit 1 Bit O 13 12 11 10 9 ro ro rw 0 rw 0 rw 0 5 4 3 2 1 0 S
480. rupt enabled USCI_AO receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled IFG2 Interrupt Flag Register 2 7 6 5 4 3 2 1 0 UCAO UCAO TXIFG RXIFG rw 1 rw 0 UCAO TXIFG UCAO RXIFG Bits 7 2 Bit 1 Bit O These bits may be used by other modules see the device specific data sheet USCI_AO transmit interrupt flag UCAOTXIFG is set when UCAOTXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_AO receive interrupt flag UCAORXIFG is set when UCAORXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface UART Mode 15 35 USCI Registers UART Mode UC1IE USCI_A1 Interrupt Enable Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Unused UCA1TXIE UCA1RXIE Bits 7 4 Bits 3 2 Bit 1 Bit 0 Unused These bits may be used by other USCI modules see the device specific data sheet USCI_A1 transmit interrupt enable 0 Interrupt disabled 1 Interrupt enabled USCI_A1 receive interrupt enable 0 Interrupt disabled 1 Interrupt enabled UC1IFG USCI_A1 Interrupt Flag Register 7 6 5 4 3 2 1 0 UCA1 UCA1 TXIFG RXIFG rw 1 rw 0 rw 0 rw 0 rw 0 rw 0 Unused UCA1 TXIFG UCA1 RXIFG 15 36 Bits 7 4 Bits 3 2 Bit 1 Bit 0 Unused These bits may be used by other USCI modules see the device specific data sheet USCI_A1 transmit interrupt flag UCA1TXIFG is se
481. rupt takes 5 cycles CPU or 3 cycles CPUx to execute the following actions and is illustrated in Figure 2 7 1 The SR with all previous settings pops from the stack All previous settings of GIE CPUOFF etc are now in effect regardless of the settings used during the interrupt service routine 2 The PC pops from the stack and begins execution at the point where it was interrupted Figure 2 7 Return From Interrupt Before After Return From Interrupt Interrupt Nesting Interrupt nesting is enabled if the GIE bit is set inside an interrupt service routine When interrupt nesting is enabled any interrupt occurring during an interrupt service routine will interrupt the routine regardless of the interrupt priorities System Resets Interrupts and Operating Modes 2 11 System Reset and Initialization 2 2 4 2 12 Interrupt Vectors The interrupt vectors and the power up starting address are located in the address range OFFFFh to OFFCOh as described in Table 2 1 A vector is programmed by the user with the 16 bit address of the corresponding interrupt service routine See the device specific data sheet for the complete interrupt vector list It is recommended to provide an interrupt service routine for each interrupt vector that is assigned to a module A dummy interrupt service routine can consist of just the RETI instruction and several interrupt vectors can point to it Unassigned interrupt vectors can be used for
482. rystal should be placed as close as possible to the MSP430 with the crystal housing grounded and the crystal traces guarded with ground traces ee Basic Clock Module 5 5 Basic Clock Module Operation 5 2 4 XT2 Oscillator Some devices have a second crystal oscillator XT2 XT2 sources XT2CLK and its characteristics are identical to LFXT1 in HF mode The XT2Sx bits select the range of operation of XT2 The XT2OFF bit disables the XT2 oscillator if XT2CLK is not used for MCLK or SMCLK as shown in Figure 5 3 XT2 may be used with external clock signals on the XT2IN pin when XT2Sx 11 and XT2OFF 0 When used with an external signal the external frequency must meet the data sheet parameters for XT2 When the input frequency is below the specified lower limit the XT2OF bit may be set preventing the CPU from being clocked with XT2CLK Figure 5 3 Off Signals for Oscillator XT2 XT2OFF m MCLK_request ta O sm Y gt XT2off Internal Signal XSELM1 _ SMCLK_request SCG1 tits E X 5 2 5 Digitally Controlled Oscillator DCO The DCO is an integrated digitally controlled oscillator The DCO frequency can be adjusted by software using the DCOx MODx and RSELx bits Disabling the DCO Software can disable DCOCLK by setting SCGO when it is not used to source SMCLK or MCLK in active mode as shown in Figure 5 4 Figure 5 4 On Off Control of DCO MCLK_request CPUOFF XSELM1 SMCLK_request SCG1 P
483. s one of the OUTMODx bits should remain set during the transition unless switching to mode 0 Otherwise output glitching can occur because a NOR gate decodes output mode 0 A safe method for switching between output modes is to use output mode 7 as a transition state BIS BIC OUTMOD_7 amp TBCCTLx Set output mode 7 OUTMODx amp TBCCTLx Clear unwanted bits es Timer_B 13 17 Timer_B Operation 13 2 6 Timer_B Interrupts Two interrupt vectors are associated with the 16 bit Timer_B module Y TBCCRO interrupt vector for TBCCRO CCIFG Y TBIV interrupt vector for all other CCIFG flags and TBIFG In capture mode any CCIFG flag is set when a timer value is captured in the associated TBCCRx register In compare mode any CCIFG flag is set when TBR counts to the associated TBCLx value Software may also set or clear any CCIFG flag All CCIFG flags request an interrupt when their corresponding CCIE bit and the GIE bit are set TBCCRO Interrupt Vector The TBCCRO CCIFG flag has the highest Timer_B interrupt priority and has a dedicated interrupt vector as shown in Figure 13 15 The TBCCRO CCIFG flag is automatically reset when the TBCCRO interrupt request is serviced Figure 13 15 Capture Compare TBCCRO Interrupt Flag Capture EQUO IRQ Interrupt Service Requested IRACC Interrupt Request Accepted TBIV Interrupt Vector Generator 13 18 Timer_B The TBIFG flag and TBCCRx CCIFG flags excluding T
484. s SDA to the idle state Clearing USIGE stores the MSB in the output latch and the output is disabled by clearing USIOE SDA remains high until a START condition is generated because of the external pullup Generate STOP BIS B USIOE amp USICTLO SDA output MOV B 000H amp USISRL MSB 0 MOV B 001H amp USICNT USICNT 1 for one clock TEST_USIIFG BIT B USIIFG amp USICTL1 Test USIIFG JZ TEST USIIFG i MOV B 0FFH amp USISRL USISRL 1 to drive SDA high BIS B USIGE amp USICTLO Transparent latch enabled BIC B USIGE USIOE amp USICTL Latch SDA output disabled continue Setting the USISCLREL bit will release SCL if it is being held low by the USI module without requiring USIIFG to be cleared The USISCLREL bit will be cleared automatically if a START condition is received and the SCL line will be held low on the next clock In slave operation this bit should be used to prevent SCL from being held low when the slave has detected that it was not addressed by the master On the next START condition USISCLREL will be cleared and the USISTTIFG will be set Universal Serial Interface 14 11 USI Operation Arbitration 12C Interrupts The USI module can detect a lost arbitration condition in multi master 12C systems The 12C arbitration procedure uses the data presented on SDA by the competing transmitters The first master transmitter that generates a logic high loses arbitration to the opposing master generating
485. s and Lengths Table 4 10 lists the length and CPU cycles for all addressing modes of the MSP430 format instructions Table 4 10 MSP430 Format Instructions Cycles and Length Addressing Mode No of Length of Sre Dst Cycles Instruction Example Rn Rm 1 MOV R5 R8 PC 2 1 BR R9 x Rm 4t 2 ADD R5 4 R6 EDE 4t 2 XOR R8 EDE amp EDE 4t 2 MOV R5 amp EDE Rn Rm 2 1 AND R4 R5 PC 1 BR R8 x Rm 5t 2 XOR R5 8 R6 EDE 5t 2 MOV R5 EDE amp EDE 5t 2 XOR R5 amp EDE Rn Rm 2 1 ADD R5 R6 PC 1 BR R9 x Rm 5t 2 XOR R5 8 R6 EDE 5t 2 MOV R9 EDE amp EDE 5t 2 MOV R9 amp EDE N Rm 2 2 MOV 20 R9 PC 2 BR 2AEh x Rm 5t 3 MOV 0300h 0 SP EDE 5t 3 ADD 33 EDE amp EDE 5t 3 ADD 33 amp EDE x Rn Rm 3 2 MOV 2 R5 R7 PC 3 2 BR 2 R6 TONI 6t 3 MOV 4 R7 TONI x Rm 6t 3 ADD 4 R4 6 R9 amp TONI 6t 3 MOV 2 R4 amp TONI EDE Rm 3 2 AND EDE R6 PC 3 2 BR EDE TONI 6t 3 CMP EDE TONI x Rm 6t 3 MOV EDE 0 SP amp TONI 6t 3 MOV EDE amp TONI amp EDE Rm 3 2 MOV amp EDE R8 PC 3 2 BR amp EDE TONI 6t 3 MOV amp EDE TONI x Rm 6t 3 MOV amp EDE 0 SP amp TONI 6t 3 MOV amp EDE amp TONI t MOV BIT and CMP instructions execute in 1 fewer cycle 4 42 16 Bit MSP430X CPU MSP430X Extended Instructions 4 5 2 MSP430X Extended Instructions The extended MSP430X instructions give the MSP430X CPU full access to its 20 bit address space Most MSP430X instructions req
486. s conversion mode 1 Single conversion mode SD160SRx Bits Oversampling ratio 9 8 When SD16XOSR 0 00 256 01 128 10 64 11 32 When SD16XOSR 1 00 512 01 1024 10 Reserved 11 Reserved SD16 Bit 7 LSB toggle This bit when set causes SD16LSBACC to toggle each time LSBTOG the SD16MEMO register is read 0 SD16LSBACC does not toggle with each SD16MEMO read 1 SD16LSBACC toggles with each SD16MEMO read 24 18 SD16_A SD16 LSBACC SD160VIFG SD16DF SD16IE SD16IFG SD16SC Reserved Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit O SD16_A Registers LSB access This bit allows access to the upper or lower 16 bits of the SD16_A conversion result 0 SD16MEM x contains the most significant 16 bits of the conversion 1 SD16MEM x contains the least significant 16 bits of the conversion SD16_A overflow interrupt flag 0 No overflow interrupt pending 1 Overflow interrupt pending SD16_A data format 0 Offset binary 1 2 s complement SD16_A interrupt enable 0 Disabled 1 Enabled SD16_A interrupt flag SD16IFG is set when new conversion results are available SD16IFG is automatically reset when the corresponding SD16MEM x register is read or may be cleared with software 0 No interrupt pending 1 Interrupt pending SD16_A start conversion 0 No conversion start 1 Start conversion Reserved SD16_A 24 19 SD16_A Registers SD16INCTLO SD16_A Input Control Register 7 6 5 4 3 2 1 0 rw 0 r
487. s for R and C given above the equation becomes tsample gt Rs 2k x 7 625 x 27pF For example if Rg is 10 kQ tsample Must be greater than 2 47 us When the reference buffer is used in burst mode the sampling time must be greater than the sampling time calculated and the settling time of the buffer tREFBURST Rg R x In 211 x C Sam le 7 p tREFBURST For example if Vref is 1 5 V and Rs is 10 kQ tsample Must be greater than 2 47 us when ADC10SR 0 or 2 5 us when ADC10SR 1 See the device specific data sheet for parameters To calculate the buffer settling time when using an external reference the formula is trerpursT SR x Vret 0 545 Where SR Buffer slew rate 1 us V when ADC10SR 0 and 2 us V when ADC10SR 1 Vref External reference voltage ADC10 20 2 6 Conversion Modes ADC10 Operation The ADC10 has four operating modes selected by the CONSEQx bits as discussed in Table 20 1 Table 20 1 Conversion Mode Summary CONSEQx Mode 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels Operation A single channel is converted once A sequence of channels is converted once A single channel is converted repeatedly A sequence of channels is converted repeatedly ADC10 20 9 ADC10 Operation Single Channel Single Conversion Mode A single channel selected by INCHx is sampled and converted once The ADC result is written
488. s of the 12C specifi cation are met During the arbitration procedure the clocks from the different masters must be synchronized A device that first generates a low period on SCL overrules the other devices forcing them to start their own low periods SCL is then held low by the device with the longest low period The other devices must wait for SCL to be released before starting their high periods Figure 17 16 illustrates the clock synchronization This allows a slow slave to slow down a fast master Figure 17 16 Synchronization of Two I C Clock Generators During Arbitration SCL From Device 1 SCL From Device 2 Bus Line SCL Wait gt K Start HIGH State Period Universal Serial Communication Interface C Mode 17 21 USCI Operation C Mode Clock Stretching The USCI module supports clock stretching and also makes use of this feature as described in the operation mode sections The UCSCLLOW bit can be used to observe if another device pulls SCL low while the USCI module already released SCL due to the following conditions J USCI is acting as master and a connected slave drives SCL low Y USCI is acting as master and another master drives SCL low during arbitration The UCSCLLOW bit is also active if the USCI holds SCL low because it is wait ing as transmitter for data being written into UCBxTXBUF or as receiver for the data being read from UCBxRXBUF The UCSCLLOW bit might get set for a short time
489. s reset until another output mode is selected and affects the output The output is toggled when the timer counts to the TACCRXx value It is set when the timer counts to the TACCRO value The output is reset when the timer counts to the TACCRx value It is set when the timer counts to the TACCRO value Timer_A 12 13 Timer_A Operation Output Example Timer in Up Mode The OUTx signal is changed when the timer counts up to the TACCRx value and rolls from TACCRO to zero depending on the output mode An example is shown in Figure 12 12 using TACCRO and TACCR1 Figure 12 12 Output Example Timer in Up Mode OFFFFh TACCRO TACCRt Oh Output Mode 1 Set RES Output Mode 2 Toggle Reset Output Mode 3 Set Reset Output Mode 4 Toggle Output Mode 5 Reset Output Mode 6 Toggle Set Output Mode 7 Reset Set EQUO EQUI EQUO EQUI EQUO TAIFG TAIFG TAIFG interrupt Events 12 14 Timer_A Timer_A Operation Output Example Timer in Continuous Mode The OUTx signal is changed when the timer reaches the TACCRx and TACCRO values depending on the output mode An example is shown in Figure 12 13 using TACCRO and TACCR1 Figure 12 13 Output Example Timer in Continuous Mode OFFFFh TACCRO TACCR1 Oh TAIFG EQU1 EQUO TAIFG EQU1 EQUO Interrupt Events Timer_A 12 15 Timer_A Operation Output Example Timer in Up Down Mode The OUTx signa
490. s selected including SD16INTDLYx and SD16GAINx settings Because the internal reference must be on to use the temperature sensor it is not possible to use an external reference for the conversion of the temperature sensor voltage Also the internal reference will be in contention with any used external reference In this case the SD16VMIDON bit may be set to minimize the affects of the contention on the conversion The typical temperature sensor transfer function is shown in Figure 24 8 When switching inputs of an SD16_A channel to the temperature sensor adequate delay must be provided using SD16INTDLYx to allow the digital filter to settle and assure that conversion results are valid The temperature sensor offset error can be large and may need to be calibrated for most applications See device specific data sheet for temperature sensor parameters Figure 24 8 Typical Temperature Sensor Transfer Function 24 14 SD16_A Volts 0 500 0 450 0 400 0 350 0 300 Vsensor typ TCsensor 273 T C Vottset sensor MV 0 250 0 200 Celsius SD16_A Operation 24 2 11 Interrupt Handling The SD16_A has 2 interrupt sources for its ADC channel Y SD16IFG Y SD160VIFG The SD16IFG bit is set when the SD16MEMO memory register is written with a conversion result An interrupt request is generated if the corresponding SD16IE bit and the GIE bit are set The SD16_A overflow condition occurs when a conversion result is
491. scribed in the following pages For MSP430X instructions that do not require the extension word it is noted in the instruction description 4 112 16 Bit MSP430X CPU ADCX A ADCX W ADCX B Syntax Operation Emulation Description Status Bits Mode Bits Example Extended Instructions Add carry to destination address word Add carry to destination word Add carry to destination byte ADCX A dst ADCX dst or ADCX W dst ADCX B dst dst C gt dst ADDCX A 0 dst ADDCX 0 dst ADDCX B 0 dst The carry bit C is added to the destination operand The previous contents of the destination are lost Set if result is negative MSB 1 reset if positive MSB 0 Set if result is zero reset otherwise Set if there is a carry from the MSB of the result reset otherwise Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected The 40 bit counter pointed to by R12 and R13 is incremented INCX A R12 ADCX A R13 Increment lower 20 bits Add carry to upper 20 bits 16 Bit MSP430X CPU 4 113 Extended Instructions ADDX A ADDX W ADDX B Syntax Operation Description Status Bits Mode Bits Example Example Example 4 114 Add source address word to destination address word Add source word to destination word Add source byte to destination byte ADDX A src dst ADD
492. sed to indicate which OA module is being discussed In cases where operation is identical the register is simply referred to as OAXCTLO o The block diagram of the OA module is shown in Figure 18 1 Figure 18 1 OA Block Diagram OAxI0 OAOI1 OAxIA OAxIB OA20UT OA0 OAOOUT OA1 OA10UT OA2 SY OAFCx 5 OAxI0 OAxl1 OAxIA OAxIB O Ja x 01 OAFCx 6 OAPx D OANx 3 OAPMx 10 11 OANx 00 01 OAFCx 6 OANEXT OA1TAP OA0 OA2TAP OA1 OAOTAP OA2 10 11 OAFCx Bj V OA1RBorTomM 940 OA2RBOTTOM OA e ee e OAORBOTTOM OAxTAP OAFBRx gt 0 OAXRBOTTOM O 1 NS OAxIO OAxI1 OAxIA OA20UT OA0 OAOOUT OA1 OA1OUT OA2 OAxFB OA Introduction X lt o n x o Q L OAADCx OAFCx 0 OA A1 OAO A3 OA1 A5 OA2 A1 OA0O0 A3 OA10 A5 0A20 A12 OA0 A13 OA1 A14 OA2 A12 0A00 A13 0A10 A14 0A20 OAXOUT 18 3 OA Operation 18 2 OA Operation The OA module is configured with user software The setup and operation of the OA is discussed in the following sections 18 2 1 OA Amplifier The OA is a configurable low current rail to rail output operational amplifier It can be configured as an inverting amplifier or a non inverting amplifier or can be combined with other OA modules t
493. sent Rosc is not supported MSP430x21x1 Internal LP LF oscillator is not present XT2 is not present Rosc is not supported MSP430x21x2 XT2 is not present MSP430x22xx MSP430x23x0 XT2 is not present Cd Basic Clock Module Basic Clock Module Introduction Figure 5 1 Basic Clock Module Block Diagram Internal LP LF OSES DIVAx Oscillatort Min Pulse Filter OSCOFF Divider LFXT1CLK 1 2 4 8 ACLK Auxillary Clock LFXT1Sx XIN l XOUT SELMx LFXT1 Oscillator 7 Divider Min Pulse 11 2 4 8 Filter MCLK XT20FF XT2S XT2IN Connected only when XT2 not present on chip E XT2 Oscillatort MODx get Se St et ee J Modulator lt DCOx gt DC Min Puls Generator Filter Main System Clock DCOR SCGO RSELx Divider DCOCLK 11 2 4 8 Sub System Clock tNote Device Specific Clock Variations All clock features are not available on all MSP430x2xx devices MSP430x20xx LFXT1 does not support HF mode XT2 is not present Rosc is not supported MSP430x21x1 Internal LP LF oscillator is not present XT2 is not present Rosc is not supported MSP430x21x2 XT2 is not present MSP430x22xx MSP430x23x0 XT2 is not present SSR Basic Clock Module 5 3 Basic Clock Module Operation 5 2 Basic Clock Module Operation 5 2 1 5 2 2 5 4 After a P
494. set after a PUC or when UCSWRST 1 UCAxTXIE is reset after a PUC or when UCSWRST 1 USCI Receive Interrupt Operation The UCAxRXIFG interrupt flag is set each time a character is received and loaded into UCAxRXBUF An interrupt request is generated if UCAxRXIE and GIE are also set UCAxRXIFG and UCAxRXIE are reset by a system reset PUC signal or when UCSWRST 1 UCAxRXIFG is automatically reset when UCAxRXBUF is read Additional interrupt control features include 3 When UCAxRXEIE 0 erroneous characters will not set UCAxRXIFG J When UCDORM 1 non address characters will not set UCAxRXIFG in multiprocessor modes In plain UART mode no characters will set UCAxRXIFG Y When UCBRKIE 1 a break condition will set the UCBRK bit and the UCAXRXIFG flag Universal Serial Communication Interface UART Mode 15 25 USCI Operation UART Mode USCI Interrupt Usage USCI_Ax and USCI_Bx share the same interrupt vectors The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector Shared Interrupt Vectors Software Example 15 26 The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIAO RX USCIBO RX ISR BIT B UCAORXIFG amp IFG2 USCI_AO Receive Interrupt JNZ USCIAO_RX_ISR USCIBO_RX_IS
495. set otherwise OSCOFF CPUOFF and GIE are not affected The item on the top of the stack TOS is removed without using a register PUSH R5 R5 is the result of a calculation which is stored in the system stack INCD SP Remove TOS by double increment from stack Do not use INCD B SP is a word aligned register RET The byte on the top of the stack is incremented by two INCD B 0 SP Byte on TOS is increment by two 4 82 16 Bit MSP430X CPU INV W INV B Syntax Operation Emulation Emulation Description Status Bits Mode Bits Example Example MSP430 Instructions Invert destination Invert destination INV dst INV B dst NOT dst gt dst XOR OFFFFh dst XOR B 0FFh dst The destination operand is inverted The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if result is not zero reset otherwise NOT Zero Set if result is not zero reset otherwise NOT Zero V Set if initial destination operand was negative otherwise reset OSCOFF CPUOFF and GIE are not affected Content of R5 is negated twos complement MOV OOAEh R5 R5 OOOAEh INV R5 Invert R5 R5 OFF51h INC R5 R5 is now negated R5 O0FF52h Content of memory byte LEO is negated MOV B 0AEh LEO MEM LEO OAEh INV B LEO Invert LEO MEM LEO 051h INC B LEO MEM LE
496. set with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Unchanged Reset with PUC OCOh with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Digital I O 8 7 Digital I O Registers P6 P7 P8 8 8 Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Input Output Direction Port Select Port Select 2 Resistor Enable Digital I O P6IN P6OQUT P6DIR P6SEL P6SEL2 P6REN P7IN P7OUT P7DIR P7SEL P7SEL2 P7REN P8IN P80UT P8DIR P8SEL P8SEL2 P8REN 034h 035h 036h 037h 046h 013h 038h 03Ah 03Ch O3Eh 047h 014h 039h 03Bh 03Dh O3Fh 048h 015h Read only Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Read only Read write Read write Read write Read write Read write Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Unchanged Reset with PUC Reset with PUC Reset with PUC Reset with PUC Chapter 9 Supply Voltage Supervisor This chapter describes the operation of the SV
497. shifted out The data must be MSB or LSB aligned depending on USILSB Figure 14 4 shows an example of 7 bit data handling Figure 14 4 Data adjustments for 7 bit SPI Data 7 bit SPI Mode MSB first Transmit data in memory rc wh A a fo Shift with software ee TX a 7 bit SPI Mode LSB first Transmit data in memory ome 7 Move HR 7 TX RA Nex o AS N ji Shift with software B ee H ee Received data in memory Received data in memory When USI16B 1 all 16 bits are used for data handling When using USISR to access both USISRL and USISRH the data needs to be properly adjusted when lt 16 bits are used in the same manner as shown in Figure 14 4 SPI Interrupts There is one interrupt vector associated with the USI module and one interrupt flag USIIFG relevant for SPI operation When USIIE and the GIE bit are set the interrupt flag will generate an interrupt request USIIFG is set when USICNTx becomes zero either by counting or by directly writing O to the USICNTx bits USIIFG is cleared by writing a value gt O to the USICNTx bits when USIIFGCC 0 or directly by software 14 8 Universal Serial Interface 14 2 4 12C Mode 12C Master Mode 12C Slave Mode 12C Transmitter USI Operation The USI module is configured in 12 mode when USII2C 1 USICKPL 1 and USICKPH 0 For 12C data compatibility USILSB and USI16B must be cleared U
498. specific data sheet 1 1 Secondary peripheral module function is selected Setting PxSELx 1 does not automatically set the pin direction Other peripheral module functions may require the PxDIRx bits to be configured according to the direction needed for the module function See the pin schematics in the device specific data sheet tS gt Se TT etl Note Setting PxREN 1 When PxSEL 1 On some I O ports on the MSP430F261x and MSP430F2416 7 8 9 enabling the pullup pulldown resistor PXREN 1 while the module function is selected PXxSEL 1 does not disable the logic output driver This combination is not recommended and may result in unwanted current flow through the internal resistor See the device specific data sheet pin schematics for more information ee Output ACLK on P2 0 on MSP430F21x1 BIS B 01h amp P2SEL Select ACLK function for pin BIS B 01h amp P2DIR Set direction to output Required A _ _ _A KA Oe ee Se ee OOo Note P1 and P2 Interrupts Are Disabled When PxSEL 1 When any P1SELx or P2SELx bit is set the corresponding pin s interrupt function is disabled Therefore signals on these pins will not generate P1 or P2 interrupts regardless of the state of the corresponding P1IE or P2IE bit ss When a port pin is selected as an input to a peripheral the input signal to the peripheral is a latched representation of the signal at the device pin While PxSELx 1 the internal input signal
499. st dst BIS B src dst src or dst dst XOR B src dst src xor dst gt dst z be 3 Z AND B src dst src and dst gt dst 0 A 3 Z The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set 4 36 16 Bit MSP430X CPU MSP430 and MSP430X Instructions Single Operand Format ll Instructions Figure 4 23 shows the format for MSP430 single operand instructions except RETI The destination word is appended for the Indexed Symbolic Absolute and Immediate modes Table 4 5 lists the seven single operand instructions Figure 4 23 MSP430 Single Operand Instructions Destination 15 0 Table 4 5 MSP430 Single Operand Instructions Mnemonic S Reg Operation Status Bits peed Vo NZ Cc RRC B dst CMSB gt LSB gt C gt o RRA B dst MSB gt MSB LSB gt C 0 a ji PUSH B sre SP 2 gt SP src gt SP SWPB dst bit 15 bit 8 bit 7 bit O CALL dst Call subroutine in lower 64 KB RETI TOS gt SR SP 2 gt SP A a TOS gt PC SP 2 5 SP SXT dst Register mode 0 Z bit 7 gt bit 8 bit 19 Other modes bit 7 gt bit 8 bit 15 The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set 16 Bit MSP430X CPU 4 37 MSP430 and MSP430X Instructions Jumps Figure 4 24 shows the format for MSP430 and MSP430X jump instructions The sign
500. sts a WDT interval timer interrupt if the WDTIE and the GIE bits are set The interval timer interrupt vector is different from the reset vector used in watchdog mode In interval timer mode the WDTIFG flag is reset automatically when the interrupt is serviced or can be reset with software 10 2 5 Watchdog Timer Clock Fail Safe Operation The WDT module provides a fail safe clocking feature assuring the clock to the WDT cannot be disabled while in watchdog mode This means the low power modes may be affected by the choice for the WDT clock For example if ACLK is the WDT clock source LPM4 will not be available because the WDT will prevent ACLK from being disabled Also if ACLK or SMCLK fail while sourcing the WDT the WDT clock source is automatically switched to MCLK In this case if MCLK is sourced from a crystal and the crystal has failed the fail safe feature will activate the DCO and use it as the source for MCLK When the WDT module is used in interval timer mode there is no fail safe feature for the clock source Watchdog Timer 10 5 Watchdog Timer Operation 10 2 6 Operation in Low Power Modes The MSP430 devices have several low power modes Different clock signals are available in different low power modes The requirements of the user s application and the type of clocking used determine how the WDT should be configured For example the WDT should not be configured in watchdog mode with SMCLK as its clock s
501. supply lines and other parts of the system are responsible for this behavior as shown in Figure 19 3 The comparator output oscillation reduces accuracy and resolution of the comparison result Selecting the output filter can reduce errors associated with comparator oscillation Figure 19 3 RC Filter Response at the Output of the Comparator Terminal Terminal SS Comparator Inputs Comparator Output NII Unfiltered at CAOUT Comparator Output Filtered at CAOUT 19 2 5 Voltage Reference Generator The voltage reference generator is used to generate Vcarer which can be applied to either comparator input terminal The CAREFx bits control the output of the voltage generator The CARSEL bit selects the comparator terminal to which Vcarer is applied If external signals are applied to both comparator input terminals the internal reference generator should be turned off to reduce current consumption The voltage reference generator can generate a fraction of the device s Vcc or a fixed transistor threshold voltage of 0 55 V 19 6 Comparator_A Comparator_A Operation 19 2 6 Comparator_A Port Disable Register CAPD The comparator input and output functions are multiplexed with the associated I O port pins which are digital CMOS gates When analog signals are applied to digital CMOS gates parasitic current can flow from Vcc to GND This parasitic current occurs if the input voltage is near the
502. t dst BIC 4 SR The constant 04h is inverted OFFFBh and is logically ANDed with the destination operand The result is placed into the destination The clear negative bit instruction is a word instruction N Resetto 0 Z Not affected C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The Negative bit in the status register is cleared This avoids special treatment with negative numbers of the subroutine called CLRN CALL SUBR JN SUBRET If input is negative do nothing and return RET 4 72 16 Bit MSP430X CPU CLRZ Syntax Operation Emulation Description Status Bits Mode Bits Example MSP430 Instructions Clear zero bit CLRZ 0 gt Z or NOT src AND dst gt dst BIC 2 SR The constant 02h is inverted OFFFDh and logically ANDed with the destination operand The result is placed into the destination The clear zero bit instruction is a word instruction N Not affected Z Reset to 0 C Not affected V Not affected OSCOFF CPUOFF and GIE are not affected The zero bit in the status register is cleared CLRZ Indirect Auto Increment mode Call a subroutine at the 16 bit address con tained in the word pointed to by register R5 20 bit address and increment the 16 bit address in R5 afterwards by 2 The next time the software uses R5 as a pointer it can alter the program execution due to access to the next word ad dress in the table pointed to by R5 CALL
503. t I Double Operand Instruction Cycles and Lengths Instruction Set Table 3 16 lists the length and CPU cycles for all addressing modes of format instructions Table 3 16 Format 1 Instruction Cycles and Lengths Addressing Mode Src Rn Rn Rn N x Rn EDE amp EDE Dst Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC x Rm EDE amp EDE Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI Rm PC TONI x Rm amp TONI No of Cycles NPD DWWIDDDWWIDADA DMD wWWwWIT aA Awana 0 1 Y NOA aan NAA A A N Length of Instruction Ow wonNnNnNIWOW WN NIW Y Y N NO Y Y N NIM NN NY NN YB N ND DN NH MOV BR ADD XOR MOV AND BR XOR MOV XOR ADD BR XOR MOV MOV MOV BR MOV ADD ADD MOV BR MOV ADD MOV AND BR CMP MOV MOV MOV BR MOV MOV MOV Example R5 R8 R9 R5 4 R6 R8 EDE R5 amp EDE R4 R5 R8 R5 8 R6 R5 EDE R5 amp EDE R5 R6 R9 R5 8 R6 R9 EDE R9 EDE H20 R9 H2AEh 0300h 0 SP 33 EDE 33 amp EDE EDE TONI EDE 0 SP EDE TONI SEDE R8 SEDE SEDE TONI SEDE 0 SP SEDE TONI RISC 16 Bit CPU 3 73 Instruction Set 3 4 5 Instruction Set Description The instruction map is shown in Figure 3 20 and the complete instruction set is summarized in Table 3 17 Figure 3 20 Core Instruction Map 000 040 080 0CO 100
504. t enables an interrupt to cause an emergency exit from a flash operation when GIE 1 EEIEX is automatically reset when EMEX is set 0 Exit interrupt disabled 1 Exit on interrupt enabled Enable Erase Interrupts Setting this bit allows a segment erase to be interrupted by an interrupt request After the interrupt is serviced the erase cycle is resumed 0 Interrupts during segment erase disabled 1 Interrupts during segment erase enabled Mass erase and erase These bits are used together to select the erase mode MERAS and ERASE are automatically reset when EMEX is set MERAS ERASE Erase Cycle 0 0 No erase 0 1 Erase individual segment only 1 0 Erase all main memory segments 1 1 LOCKA 0 Erase main and information flash memory LOCKA 1 Erase only main flash memory 7 BLKWRT rw 0 t Not present on MSP430x20xx Devices FRKEY Bits FWKEY 15 8 BLKWRT Bit 7 WRT Bit 6 Reserved Bit 5 EEIEX Bit 4 EEI Bits 3 MERAS Bit 2 ERASE Bit 1 Reserved Bit O Reserved Always read as 0 Flash Memory Controller 7 21 Flash Memory Registers FCTL2 Flash Memory Control Register 15 14 13 12 11 10 9 8 FWKEYx Read as 096h Must be written as OA5h 7 6 5 4 3 2 1 0 rw 0 rw 1 rw 0 rw 0 rw 0 rw 0 rw 1 rw 0 FWKEYx Bits FCTLx password Always read as 096h Must be written as OA5h or a PUC 15 8 will be generated FSSELx Bits Flash controller clock source select 7 6 00 ACLK 01 MCLK 10 SMCLK 11 SMCLK FNx Bits Flash controller clock d
505. t is assumed that R9 TAG ADC12 1 contains the address of the The corrected value is available in ADC_COR W W MOV W W amp ADC12MEM0 R10 R10 ARTO 4 22 R10 amp MPY unsigned multiply OP1 CAL ADC GAIN FACTOR R9 amp OP2 calibration value OP2 amp RESHI amp ADC_COR use upper 16 bit MPY CAL ADC _OFFSET R9 amp ADC_ COR add offset correction move result to R10 22 3 Checking Integrity of SegmentA The 64 byte SegmentA contains a 2 byte checksum of the data stored at 0x10C2 up to Ox10FF at addresses 0x10C0 and 0x10C1 The checksum is a bit wise XOR of 31 words stored in the twos complement data format A code example to calculate the checksum follows Checking the SegmentA integrity by calculating the 2 s complement of the 31 words at 0x10C2 0x10FE It is assumed that the SegmentA Start Address is stored in R O ADD W XOR W CMP W JN ADD W JNZ LPO CSNOK R11 is initialized to 0x00 The label TLV_CHKSUM is set to 0x10C0 2 R10 Skip the checksum ER10 R11 Add a word to checksum HOx10FF R10 Last word included LPO No add more data amp TLV_CHKSUM R11 Add checksum CSNOK Checksum not ok Use SegmentA data Do not use SegmentA Data TLV Structure 22 7 Parsing TLV Structure of Segment A 22 4 Parsing TLV Structure of Segment A Example code to analyze SegmentA follows It is assumed that the SegmentA start address is stored in
506. t is not 0 Carry bit This bit is set when the result of a byte or word operation produced a carry and cleared when no carry occurred 3 2 4 Constant Generator Registers CG1 and CG2 CPU Registers Six commonly used constants are generated with the constant generator registers R2 and R3 without requiring an additional 16 bit word of program code The constants are selected with the source register addressing modes As as described in Table 3 2 Table 3 2 Values of Constant Generators CG1 CG2 Register R2 R2 R2 R2 R3 R3 R3 R3 The constant generator advantages are As 00 01 10 11 00 01 10 11 Constant 0 00004h 00008h 00000h 00001h 00002h OFFFFh Y No special instructions required Remarks Register mode Absolute address mode 4 bit processing 8 bit processing 0 word processing 1 2 bit processing 1 word processing Y No additional code word for the six constants Lj No code memory access required to retrieve the constant The assembler uses the constant generator automatically if one of the six constants is used as an immediate source operand Registers R2 and R3 used in the constant mode cannot be addressed explicitly they act as source only registers Constant Generator Expanded Instruction Set The RISC instruction set of the MSP430 has only 27 instructions However the constant generator allows the MSP430 assembler to support 24 additional emulated instructions Fo
507. t operands but have restricted addressing modes The addressing modes are restricted to the Register mode and the Immediate mode except for the MOVA instruction Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time The MSP430X address instructions are listed and described in the following pages 16 Bit MSP430X CPU 4 155 Address Instructions ADDA Syntax Operation Description Status Bits Mode Bits Example Add 20 bit source to a 20 bit destination register ADDA Rsrc Rdst ADDA imm20 Rdst src Rdst gt Rdst The 20 bit source operand is added to the 20 bit destination CPU register The previous contents of the destination are lost The source operand is not affected N Set if result is negative Rdst 19 1 reset if positive Rdst 19 0 Z Set if result is zero reset otherwise C Set if there is a carry from the 20 bit result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected R5 is increased by 0A4320h The jump to TONI is performed if a carry occurs ADDA 0A4320h R5 Add A4320h to 20 bit R5 JC TONI Jump on carry No carry occurred 4 156 16 Bit MSP430X CPU BRA Syntax Operation Emulation Description Status Bits Mode Bits Examples Address Instructions Branch
508. t otherwise OSCOFF CPUOFF and GIE are not affected Two floating point mantissas 24 bits are subtracted LSBs are in R13 and R10 MSBs are in R12 and R9 SUB W R13 R10 16 bit part LSBs SUBC B R12 R9 8 bit part MSBs The 16 bit counter pointed to by R13 is subtracted from a 16 bit counter in R10 and R11 MSD SUB B R13 R10 Subtract LSDs without carry SUBC B R13 R11 Subtract MSDs with carry resulting from the LSDs TTT GGG Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 RISC 16 Bit CPU 3 67 Instruction Set SWPB Syntax Operation Description Status Bits Mode Bits Swap bytes SWPB dst Bits 15 to 8 lt gt bits 7 to 0 The destination operand high and low bytes are exchanged as shown in Figure 3 18 Status bits are not affected OSCOFF CPUOFF and GIE are not affected Figure 3 18 Destination Operand Byte Swap Example Example 15 8 7 6 MOV 040BFh R7 0100000010111111 gt R7 SEB Ar 1011111101000000 in R7 The value in R5 is multiplied by 256 The result is stored in R5 R4 SWPB R5 5 MOV R5 R4 Copy the swapped value to R4 BIC HOFFOOh R5 Correct the result BIC 00FFh R4 Correct the result 3 68 RISC 16 Bit CPU SXT Syntax Operation Description Status Bits Mode Bits Instruction Set Extend Sign SXT dst Bit 7 gt Bit 8 Bit 15 The sign of the low byte is extended into the high b
509. t when UCA1TXBUF is empty 0 No interrupt pending 1 Interrupt pending USCI_A1 receive interrupt flag UCA1RXIFG is set when UCA1RXBUF has received a complete character 0 No interrupt pending 1 Interrupt pending Universal Serial Communication Interface UART Mode Chapter 16 Universal Serial Communication Interface SPI Mode The universal serial communication interface USCI supports multiple serial communication modes with one hardware module This chapter discusses the operation of the synchronous peripheral interface or SPI mode Topic Page 16 1 USCIOVerview inns cco cc ae 16 2 16 2 USCI Introduction SPI Mode 00e cece eee eee 16 3 16 3 USCI Operation SPI Mode 2 2 eeeee cece ee eee eens 16 5 16 4 USCI Registers SPI Mode 0eeeee eee eee eens 16 15 16 1 USCI Overview 16 1 USCI Overview The universal serial communication interface USCI modules support multiple serial communication modes Different USCI modules support different modes Each different USCI module is named with a different letter For example USCI_A is different from USCI_B etc If more than one identical USCI module is implemented on one device those modules are named with incrementing numbers For example if one device has two USCI_A modules they are named USCI_AO and USCI_A1 See the device specific data sheet to determine which USCI modules if any are implemented on which devices Th
510. tation see the device specific data sheet Topic Page 22 al ea Val MtrOGUCTION er sters E 22 2 22 2 Supported TagS ae a 22 3 22 3 Calculating the Checksum of SegmentA oooooooocooommmoo 22 7 22 4 Parsing the TLV Structure of SegmentA ooooooooommmmmo 22 8 22 1 TLV Introduction 22 1 TLV Introduction The TLV structure stores device specific data in SegmentA The SegmentA content of an example device is shown in Table 22 1 Table 22 1 Example SegmentA structure Address Offset Coo o oo oe o o Coo o o o oe S Coo A oo oe S Cow oe ooo oe A Coo A o e o e ar ICON oe EA Foden or ICON oe o e Comoe or Coce aer omoa o oo e S Coo rr Cowo o oo e S Coa oe o e The first two bytes of SegmentA 0x10C0 and 0x10C1 hold the checksum of the remainder of the segment addresses 0x10C2 to 0x10FF 22 2 TLV Structure Supported Tags The first tag is located at address 0x10C2 and in this example is the TAG_EMPTY tag The following byte 0x10C3 holds the length of the following structure The length of this TAG_EMPTY structure is 0x16 and therefore the next tag TAG_ADC12_1 is found at address 0x10DA Again the following byte holds the length of the TAG_ADC12_1 structure The TLV structure maps the entire address range 0x10C2 to Ox10FF of the SegmentA A program routine looking for tags starting at the SegmentA address 0x10C2 can extract all information even if it is stored at a differe
511. tatus Bits Mode Bits Example Example Example MSP430 Instructions Jump if equal Jump if zero JZ label JEQ label IfZ 1 PC 2 x Offset PC If Z 0 execute following instruction The Zero bit Z in the status register is tested If it is set the signed 10 bit word offset contained in the instruction is multiplied by two sign extended and added to the 20 bit program counter PC This means a jump in the range 511 to 512 words relative to the PC in the full memory range If Z is reset the instruction after the jump is executed JZ is used for the test of the Zero bit Z JEQ is used for the comparison of operands Status bits are not affected OSCOFF CPUOFF and GIE are not affected The state of the P2IN 0 bit defines the program flow BIT B 1 amp P2IN Port 2 bit O reset JZ Label1 Yes proceed at Label1 No set continue If R5 15000h 20 bit data the program continues at Label2 CMPA 15000h R5 Is R5 15000h Info to SR JEQ Label2 Yes R5 15000h Z 1 No R5 4 15000h Continue R7 20 bit counter is incremented If its content is zero the program continues at Label4 ADDA 1 R7 Increment R7 JZ Label4 Zero reached Go to Label4 R7 0 Continue here 16 Bit MSP430X CPU 4 85 MSP430 Instructions JGE Syntax Operation Description Status Bits Mode Bits Example Example Example Jump if Greater or Equal signed JGE label If N xor V 0 PC 2 x Offset gt
512. te 014Eh Unchanged ADC12 memory 8 ADC12MEM8 Read write 0150h Unchanged ADC12 memory 9 ADC12MEM9 Read write 0152h Unchanged ADC12 memory 10 ADC12MEM10 Read write 0154h Unchanged ADC12 memory 11 ADC12MEM11 Read write 0156h Unchanged ADC12 memory 12 ADC12MEM12 Read write 0158h Unchanged ADC12 memory 13 ADC12MEM13 Read write 015Ah Unchanged ADC12 memory 14 ADC12MEM14 Read write 015Ch Unchanged ADC12 memory 15 ADC12MEM15 Read write 015Eh Unchanged ADC12 memory control 0 ADC12MCTLO Read write 080h Reset with POR ADC12 memory control 1 ADC12MCTL1 Read write 081h Reset with POR ADC12 memory control 2 ADC12MCTL2 Read write 082h Reset with POR ADC12 memory control 3 ADC12MCTL3 Read write 083h Reset with POR ADC12 memory control 4 ADC12MCTL4 Read write 084h Reset with POR ADC12 memory control 5 ADC12MCTL5 Read write 085h Reset with POR ADC12 memory control 6 ADC12MCTL6 Read write 086h Reset with POR ADC12 memory control 7 ADC12MCTL7 Read write 087h Reset with POR ADC12 memory control 8 ADC12MCTL8 Read write 088h Reset with POR ADC12 memory control 9 ADC12MCTL9 Read write 089h Reset with POR ADC12 memory control 10 ADC12MCTL10 Read write 08Ah Reset with POR ADC12 memory control 11 ADC12MCTL11 Read write 08Bh Reset with POR ADC12 memory control 12 ADC12MCTL12 Read write 08Ch Reset with POR ADC12 memory control 13 ADC12MCTL13 Read write 08Dh Reset with POR ADC12 memory control 14 ADC12MCTL14 Read write 08Eh Reset with POR ADC12 memory control 15 ADC12MCTL15 Read wri
513. te 08Fh Reset with POR 21 20 ADC12 ADC12 Registers ADC12CTLO ADC12 Control Register 0 15 14 13 12 11 10 9 8 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 7 6 5 4 3 2 1 0 uso meras meron apcron avcrzowe 4802 ee ocio rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Modifiable only when ENC 0 SHT1x Bits Sample and hold time These bits define the number of ADC12CLK cycles in 15 12 the sampling period for registers ADC12MEM8 to ADC12MEM15 SHTOx Bits Sample and hold time These bits define the number of ADC12CLK cycles in 11 8 the sampling period for registers ADC12MEMO to ADC12MEM7 SHTx Bits ADC12CLK cycles 0000 4 0001 8 0010 16 0011 32 0100 64 0101 96 0110 128 0111 192 1000 256 1001 384 1010 512 1011 768 1100 1024 1101 1024 1110 1024 1111 1024 ADC12 21 21 ADC12 Registers MSC REF2_5V REFON ADC120N Bit 7 Bit 6 Bit 5 Bit 4 ADC120VIE Bit 3 ADC12 TOVIE ENC ADC12SC 21 22 Bit 2 Bit 1 Bit 0 ADC12 Multiple sample and conversion Valid only for sequence or repeated modes 0 The sampling timer requires a rising edge of the SHI signal to trigger each sample and conversion 1 The first rising edge of the SHI signal triggers the sampling timer but further sample and conversions are performed automatically as soon as the prior conversion is completed Reference generator voltage REFON must also be set 0 1 5V 1 2 5V Reference generato
514. te OCFh Reset with PUC USCI_A1 B1 interrupt enable register UC1IE Read write 006h Reset with PUC USCI_A1 B1 interrupt flag register UC1IFG Read write 007h O00Ah with PUC Universal Serial Communication Interface UART Mode 15 27 USCI Registers UART Mode UCAxCTLO USCI_Ax Control Register 0 7 6 5 4 3 2 1 0 UCPEN UCPAR UCMSB UC7BIT UCSPB UCMODEx UCSYNC 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 UCPEN Bit 7 Parity enable 0 Parity disabled 1 Parity enabled Parity bit is generated UCAxTXD and expected UCAxRXD In address bit multiprocessor mode the address bit is included in the parity calculation UCPAR Bit 6 Parity select UCPAR is not used when parity is disabled 0 Odd parity 1 Even parity UCMSB Bit 5 MSB first select Controls the direction of the receive and transmit shift register 0 LSB first 1 MSB first UC7BIT Bit 4 Character length Selects 7 bit or 8 bit character length 0 8 bit data 1 7 bit data UCSPB Bit 3 Stop bit select Number of stop bits 0 One stop bit 1 Two stop bits UCMODEx Bits USCI mode The UCMODEx bits select the asynchronous mode when 2 1 UCSYNC 0 00 UART Mode 01 Idle Line Multiprocessor Mode 10 Address Bit Multiprocessor Mode 11 UART Mode with automatic baud rate detection UCSYNC BitO Synchronous mode enable 0 Asynchronous mode 1 Synchronous Mode 15 28 Universal Serial Communication Interface UART Mode USCI Registers UART Mode UCAxCTL1 USCI_Ax Control Register 1 7
515. te of R5 is shifted right one position The MSB retains the old value It operates equal to an arithmetic division by 2 RRA B R5 R5 2 gt R5 operation is on low byte only High byte of R5 is reset PUSH B R5 R5x0 5 gt TOS RRA B SP TOS x 0 5 0 5 x R5 x 0 5 0 25 x R5 gt TOS ADD B SP R5 R5x0 5 R5x0 25 0 75 x R5 gt R5 3 60 RISC 16 Bit CPU RRC W RRC B Syntax Operation Description Instruction Set Rotate right through carry Rotate right through carry RRC dst or RRC W dst RRC dst C gt MSB gt MSB 1 LSB 1 gt LSB gt C The destination operand is shifted right one position as shown in Figure 3 17 The carry bit C is shifted into the MSB the LSB is shifted into the carry bit C Figure 3 17 Destination Operand Carry Right Shift Status Bits Mode Bits Example Example Word 15 0 a ly Byte 7 0 Set if result is negative reset if positive Set if result is zero reset otherwise Loaded from the LSB Reset OSCOFF CPUOFF and GIE are not affected R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC R5 R5 2 8000h gt R5 R5 is shifted right one position The MSB is loaded with 1 SETC Prepare carry for MSB RRC B R5 R5 2 80h gt R5 low byte of R5 is used RISC 16 Bit CPU 3 61 Instruction Set SBC W SBC B Syntax Operation Emulation Description Status Bits Mode Bits Example Exa
516. tected when 11 or more continuous zeros spaces are received If the length of the break exceeds 22 bit times the break timeout error flag UCBTOE is set The synch field follows the break as shown in Figure 15 5 Figure 15 5 Auto Baud Rate Detection Break Synch Sequence Break Delimiter Synch e gt lt gt lt For LIN conformance the character format should be set to 8 data bits LSB first no parity and one stop bit No address bit is available The synch field consists of the data 055h inside a byte field as shown in Figure 15 6 The synchronization is based on the time measurement between the first falling edge and the last falling edge of the pattern The transmit baud rate generator is used for the measurement if automatic baud rate detection is enabled by setting UCABDEN Otherwise the pattern is received but not measured The result of the measurement is transferred into the baud rate control registers UCAxBRO UCAxBR1 and UCAxMCTL If the length of the synch field exceeds the measurable time the synch timeout error flag UCSTOE is set Figure 15 6 Auto Baud Rate Detection Synch Field 15 10 a Synch 8 Bit Times e al Start Stop Bit 0 1 2 3 4 5 6 7 Bit The UCDORM bit is used to control data reception in this mode When UCDORM is set all characters are received but not transferred into the UCAxRXBUF and interrupts are not genera
517. ted When a break synch field is detected the UCBRK flag is set The character following the break synch field is transferred into UCAxRXBUF and the UCAxRXIFG interrupt flag is set Any applicable error flag is also set If the UCBRKIE bit is set reception of the break synch sets the UCAxRXIFG The UCBRK bit is reset by user software or by reading the receive buffer UCAxRXBUF Universal Serial Communication Interface UART Mode USCI Operation UART Mode When a break synch field is received user software must reset UCDORM to continue receiving data If UCDORM remains set only the character after the next reception of a break synch field will be received The UCDORM bit is not modified by the USCI hardware automatically When UCDORM 0 all received characters will set the receive interrupt flag UCAxRXIFG If UCDORM is cleared during the reception of a character the receive interrupt flag will be set after the reception is complete The automatic baud rate detection mode can be used in a full duplex communication system with some restrictions The USCI can not transmit data while receiving the break sync field and if a Oh byte with framing error is received any data transmitted during this time gets corrupted The latter case can be discovered by checking the received data and the UCFE bit Transmitting a Break Synch Field The following procedure transmits a break synch field 1 Set UCTXBRK with UMODEx 11 2 Write 055h to UCAxTXBUF U
518. ted by two The original contents are lost N Set if result is negative reset if positive Z Set if dst contained 2 reset otherwise C Reset if dst contained O or 1 set otherwise V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected RAM address word TONI is decremented by 2 DECDX A TONI Decrement TONI by two 16 Bit MSP430X CPU 4 125 Extended Instructions INCX A INCX W INCX B Syntax Operation Emulation Description Status Bits Mode Bits Example Increment destination address word Increment destination word Increment destination byte INCX A dst INCX dst INCX B dst dst 1 gt dst ADDX A 1 dst ADDX 1 dst ADDX B 1 dst or INCX W dst The destination operand is incremented by one The original contents are lost N Set if result is negative reset if positive Z Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise C Set if dst contained OFFFFFh reset otherwise Set if dst contained OFFFFh reset otherwise Set if dst contained OFFh reset otherwise V Set if dst contained O7FFFh reset otherwise Set if dst contained O7FFFh reset otherwise Set if dst contained 07Fh reset otherwise OSCOFF CPUOFF and GIE are not affected RAM address word TONI is incremented by 1 INCX A TONI 4 126 16 Bit MSP430X CPU Increment TONI 20 bits
519. th code and data 1 43 Peripheral Modules Peripheral modules are mapped into the address space The address space from 0100 to 01FFh is reserved for 16 bit peripheral modules These modules should be accessed with word instructions If byte instructions are used only even addresses are permissible and the high byte of the result is always 0 The address space from 010h to OFFh is reserved for 8 bit peripheral modules These modules should be accessed with byte instructions Read access of byte modules using word instructions results in unpredictable data in the high byte If word data is written to a byte module only the low byte is written into the peripheral register ignoring the high byte 1 4 4 Special Function Registers SFRs Some peripheral functions are configured in the SFRs The SFRs are located in the lower 16 bytes of the address space and are organized by byte SFRs must be accessed using byte instructions only See the device specific data sheets for applicable SFR bits 1 4 5 Memory Organization Bytes are located at even or odd addresses Words are only located at even addresses as shown in Figure 1 3 When using word instructions only even addresses may be used The low byte of a word is always an even address The high byte is at the next odd address For example if a data word is located at address xxx4h then the low byte of that data word is located at address xxx4h and the high byte of that word is located at add
520. th the 16 bit contents of R6 R6 19 16 is cleared Before After Address Register Address Register Space Space 21036h xoxh R5 AA550h 21036h PC R5 AA550h o1034h D506h PC R6 11111h 21034h D506h R6 0B551h A550h or 1111h B551h 16 Bit MSP430X CPU 4 15 CPU Registers Example BISX A R5 R6 This instruction logically ORs the 20 bit data contained in R5 with the 20 bit contents of R6 The extension word contains the A L bit for 20 bit data The instruction word uses byte mode with bits A L B W 01 The result of the instruction is Before After Address Register Address Register Space Space 21036h R5 AA550h 21036h 21034h 21032h PC R5 AA550h R6 11111h 21034h R6 BB551h 21032h AA550h or 11111h BB551h 4 16 16 Bit MSP430X CPU CPU Registers 4 4 2 Indexed Mode The Indexed mode calculates the address of the operand by adding the signed index to a CPU register The Indexed mode has three addressing possibilities Y Indexed mode in lower 64 KB memory Y MSP430 instruction with Indexed mode addressing memory above the lower 64 KB memory 1 MSP430X instruction with Indexed mode Indexed Mode in Lower 64 KB Memory If the CPU register Rn points to an address in the lower 64 KB of the memory range the calculated memory address bits 19 16 are cleared after the addition of the CPU register Rn and the signed 16 bit index This means the calculated memory address is always located in the l
521. the source of the sampling signal SAMPCON to be either the output of the sampling timer or the sample input signal directly 0 SAMPCON signal is sourced from the sample input signal 1 SAMPCON signal is sourced from the sampling timer Invert signal sample and hold 0 The sample input signal is not inverted 1 The sample input signal is inverted ADC 12 clock divider 000 1 001 2 010 3 011 4 100 5 101 6 110 7 111 8 ADC12 21 23 ADC12 Registers ADC12 Bits ADC12 clock source select SSELx 4 3 00 ADC120SC 01 ACLK 10 MCLK 11 SMCLK CONSEQx Bits Conversion sequence mode select 2 1 00 Single channel single conversion 01 Sequence of channels 10 Repeat single channel 11 Repeat sequence of channels ADC12 Bit O ADC12 busy This bit indicates an active sample or conversion operation BUSY O No operation is active 1 A sequence sample or conversion is active ADC12MEMx ADC12 Conversion Memory Registers 15 14 13 12 41 10 5 4 ee AS AAA ro rO ro ro ane iF a 7 6 5 4 3 2 E rw rw rw rw rw rw rw rw Conversion Bits The 12 bit conversion results are right justified Bit 11 is the MSB Bits 15 12 Results 15 0 are always O Writing to the conversion memory registers will corrupt the results 21 24 ADC12 ADC12 Registers ADC12MCTLx ADC12 Conversion Memory Control Registers pi Modifiable only when ENC 0 EOS Bit 7 End of sequence Indicates the last conversion in a sequence 0 Not end of sequence 1 End of s
522. through carry Subtract carry from dst Test Rdst compare with 0 Test dst compare with 0 Pop to dst ADDCX B A 0 dst MOVA dst PC MOVA SP PC MOV 0 Rdst ct MOVX B A 0 ds DADDX B A 0 dst ct SUBX B A 1 ds SUBA 2 Rdst SUBX B A 2 ds ct DDX B A 1 ds ct DDA 2 Rdst ORX B A 1 dst A A ADDX B A 2 dst X ADDX B A dst dst A DDCX B A dst dst SUBCX B A 0 dst CMPA 0 Rdst CMPX B A 0 dst MOVX B A SP dst 4 52 16 Bit MSP430X CPU MSP430X Extended Instructions MSP430X Address Instructions MSP430X address instructions are instructions that support 20 bit operands but have restricted addressing modes The addressing modes are restricted to the register mode and the Immediate mode except for the MOVA instruction as listed in Table 4 16 Restricting the addressing modes removes the need for the additional extension word op code improving code density and execution time Address instructions should be used any time an MSP430X instruction is needed with the corresponding restricted addressing mode Table 4 16 Address Instructions Operate on 20 bit Registers Data Status Bits Mnemonic Operands Operation VN ZC ADDA Rsrc Rdst Add source to destination FAR Se imm20 Rdst register MOVA Rsrc Rdst Move source to destination Himm20 Rdst z16 Rsrc Rdst EDE Rdst amp abs20 Rdst Rsrc Rdst Rsrc Rdst Rsrc z16 Rdst Rsrc amp abs20
523. tial Amplifier Control Register Settings Register OAOCTLO OAOCTL1 OA1CTLO OA1CTL1 OA2CTLO OA2CTL1 Settings binary XX XX Xx 0 0 xxx 001 0 x XX XX Xx 0 0 000 111 0x 1111 xx xx xxx 110 0 x Table 18 6 Three Opamp Differential Amplifier Gain Settings OA0 OA2 OAFBRx Gain 000 001 010 011 100 101 110 111 0 1 3 4 12 3 3 4 1 3 7 15 Figure 18 4 Three Opamp Differential Amplifier 18 10 OA v2 vi V2 VI xR2 Vaiff Ri Figure 18 5 Three Opamp Differential Amplifier OAx Interconnections OAPx OAFBRx OAPMx OAOTAP OA2 OAFBRx OAXFB 000 001 else OA Operation OAPMx 2 OAADCx OAPMx OA 18 11 OA Registers 18 3 OA Registers The OA registers are listed in Table 18 7 Table 18 7 OA Registers Register Short Form Register Type Address Initial State OAO control register O OAOCTLO Read write OCOh Reset with POR OAO control register 1 OAOCTL1 Read write OCth Reset with POR OA1 control register O OA1CTLO Read write 0C2h Reset with POR OA1 control register 1 OA1CTL1 Read write 0C3h Reset with POR OA2 control register O OA2CTLO Read write 0C4h Reset with POR OA2 control register 1 OA2CTL1 Read write OC5h Reset with POR 18 12 OA OA Registers OAxCTLO Opamp Control Register 0 7 5 4 3 2 1 0 rw 0 OANx
524. tination address but the contents are not modifiable so the results of the instruction would be lost a e e RISC 16 Bit CPU 3 17 Instruction Set 3 4 1 Double Operand Format I Instructions Figure 3 9 illustrates the double operand instruction format Figure 3 9 Double Operand Instruction Format 15 de 13 12 1 10 9 8 7 6 5 4 3 2 1 0 Table 3 11 lists and describes the double operand instructions Table 3 11 Double Operand Instructions Mnemonic S Reg Operation Status Bits D Reg V N zc MOV B src dst src gt dst ADD B src dst src dst dst il j i i ADDC B src dst src dst C gt dst i SUB B src dst dst not src 1 dst E s SUBC B src dst dst not src C dst E E gt j CMP B src dst dst src DADD B src dst src dst C gt dst decimally i j H BIT B src dst src and dst 0 i A A BIC B src dst not src and dst dst BIS B src dst src or dst dst XOR B src dst src xor dst dst E gi bi AND B src dst src and dst dst 0 bj AN A The status bit is affected The status bit is not affected 0 The status bit is cleared 1 The status bit is set _ Note Instructions CMP and SUB The instructions CMP and SUB are identical except for the storage of the result The same is true for the BIT and AND instructions Ta 3 18 RISC 16 Bit CPU
525. tination memory byte and for a source memory byte and a destination register Figure 4 10 Register Byte Byte Register Operation Register Byte Operation Byte Register Operation High Byte Low Byte High Byte Low Byte 19 16 15 87 0 Memory Register 16 Bit MSP430X CPU 4 11 CPU Registers Figure 4 11 and Figure 4 12 show 16 bit word handling W suffix The handling is shown for a source register and a destination memory word and for a source memory word and a destination register Figure 4 11 Register Word Operation Register Word Operation High Byte Low Byte 19 1615 87 0 Register Memory Memory Figure 4 12 Word Register Operation Word Register Operation High Byte Low Byte Register 4 12 16 Bit MSP430X CPU CPU Registers Figure 4 13 and Figure 4 14 show 20 bit address word handling A suffix The handling is shown for a source register and a destination memory address word and for a source memory address word and a destination register Figure 4 13 Register Address Word Operation Register Address Word Operation High Byte Low Byte 19 1615 87 0 Register Memory 2 Memory Figure 4 14 Address Word Register Operation Address Word Register Operation High Byte Low Byte 19 16 15 87 0 Memory 2 Memory Register Register 16 Bit MSP430X CPU 4 13 CPU Registers 4 4 Addressing Modes Seven addressing modes for the source operand and four addressing modes fo
526. ting the number of bits to be transferred to USICNTx The USI module is configured as SPI slave by clearing the USIMST and the USII2C bits In this mode when USIPE5 1 SCLK is automatically configured as an input and the USI receives the clock externally from the master If the USI is to transmit data the shift register must be loaded with the data before the master provides the first clock edge The output must be enabled by setting USIOE When USICKPH 1 the MSB will be visible on SDO immediately after loading the shift register The SDO pin can be disabled by clearing the USIOE bit This is useful if the slave is not addressed in an environment with multiple slaves on the bus Once all bits are received the data must be read from USISR and new data loaded into USISR before the next clock edge from the master In a typical application after receiving data the USI software will read the USISR register write new data to USISR to be transmitted and enable the USI module for the next transfer by writing the number of bits to be transferred to USICNTx Universal Serial Interface 14 7 USI Operation USISR Operation The 16 bit USISR is made up of two 8 bit registers USISRL and USISRH Control bit USI16B selects the number of bits of USISR that are used for data transmit and receive When USI16B 0 only the lower 8 bits USISRL are used To transfer lt 8 bits the data must be loaded into USISRL such that unused bits are not
527. tion Set JMP Jump unconditionally Syntax JMP label Operation PC 2 x offset gt PC Description The 10 bit signed offset contained in the instruction LSBs is added to the program counter Status Bits Status bits are not affected Hint This one word instruction replaces the BRANCH instruction in the range of 511 to 512 words relative to the current program counter 3 48 RISC 16 Bit CPU JN Syntax Operation Description Status Bits Example L 1 Instruction Set Jump if negative JN label if N 1 PC 2 x offset gt PC if N 0 execute following instruction The negative bit N of the status register is tested If it is set the 10 bit signed offset contained in the instruction LSBs is added to the program counter If N is reset the next instruction following the jump is executed Status bits are not affected The result of a computation in R5 is to be subtracted from COUNT If the result is negative COUNT is to be cleared and the program continues execution in another path SUB R5 COUNT COUNT R5 gt COUNT JN L 1 If negative continue with COUNT 0 at PC L 1 qa Continue with COUNT gt 0 CLR COUNT RISC 16 Bit CPU 3 49 Instruction Set JNC JLO Syntax Operation Description Status Bits Example ERROR CONT Example Jump if carry not set Jump if lower JNC label JLO label if C 0 PC 2 x offset gt PC if C 1 execute following instruction The status re
528. tion adds the 8 bit data contained in source byte EDE and destination byte TONI and places the result into the destination byte TONI Bytes EDE and TONI and the program are located in the lower 64 KB Source Byte EDE located at address 0 579Ch pointed to by PC 4766h where the PC index 4766h is the result of O579Ch 01036h 04766h Address 01036h is the location of the index for this example Destination Byte TONI located at address 00778h pointed to by PC F740h is the truncated 16 bit result of 00778h 1038h FF740h Address 01038h is the location of the index for this example Before After Address Address Space Space 0103Ah 0103Ah 01038h 01038h 01036h 01036h 01034h 01034h 01038h 32h src 0077Ah 0F740h 0077Ah 45h_ dst n 00778h javier 77h Sum 01036h 0579Eh 04766h 0579Eh 0579Ch 0S 9Eh 0579Ch 16 Bit MSP430X CPU CPU Registers MSP430 Instruction with Symbolic Mode in Upper Memory If the PC points to an address above the lower 64 KB memory the PC bits 19 16 are used for the address calculation of the operand The operand may be located in memory in the range PC 32 KB because the index X is a signed 16 bit value In this case the address of the operand can overflow or underflow into the lower 64 KB memory space as shown in Figure 4 20 and Figure 4 21 Figure 4 20 Symbolic Mode Running in Upper Memory Upper Memory PC 19 16 gt 0 E PC 19 0 PC 32 KB Figure 4 21 Overflow and Under
529. to by R12 ADD R13 0 R12 Add LSDs ADC 2 R12 Add carry to MSD The 8 bit counter pointed to by R13 is added to a 16 bit counter pointed to by R12 ADD B R13 0 R12 Add LSDs ADC B 1 R12 Add carry to MSD RISC 16 Bit CPU 3 21 Instruction Set ADD W ADD B Syntax Operation Description Status Bits Mode Bits Example Example Add source to destination Add source to destination ADD src dst or ADD W src dst ADD B src dst src dst gt dst The source operand is added to the destination operand The source operand is not affected The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the result cleared if not V Set if an arithmetic overflow occurs otherwise reset OSCOFF CPUOFF and GIE are not affected R5 is increased by 10 The jump to TONI is performed on a carry ADD 10 R5 JC TONI Carry occurred vee No carry R5 is increased by 10 The jump to TONI is performed on a carry ADD B 10 R5 Add 10 to Lowbyte of R5 JC TONI Carry occurred if R5 gt 246 OAh 0F6h SERN No carry 3 22 RISC 16 Bit CPU ADDC W ADDC B Syntax Operation Description Status Bits Mode Bits Example Example Instruction Set Add source and carry to destination Add source and carry to destination ADDC src dst or ADDC W src dst ADDC B src dst src dst
530. to certain bits with the use of a bit mask Both types of triggers can be combined to form more complex triggers For example a complex trigger can signal when a particular value is written into a user specified address 25 4 Embedded Emulation Module EEM EEM Introduction 25 2 2 Trigger Sequencer The trigger sequencer allows the definition of a certain sequence of trigger signals before an event is accepted for a break or state storage event Within the trigger sequencer it is possible to use the following features 3 Four states State O to State 3 _j Two transitions per state to any other state YU Reset trigger that resets the sequencer to State 0 The Trigger sequencer always starts at State O and must execute to State 3 to generate an action If State 1 or State 2 are not required they can be bypassed 25 2 3 State Storage Internal Trace Buffer The state storage function uses a built in buffer to store MAB MDB and CPU control signal information ie read write or instruction fetch in a non intrusive manner The built in buffer can hold up to eight entries The flexible configuration allows the user to record the information of interest very efficiently 25 2 4 Clock Control The EEM provides device dependent flexible clock control This is useful in applications where a running clock is needed for peripherals after the CPU is stopped e g to allow a UART module to complete its transfer of a character or
531. transition level of the gate Disabling the port pin buffer eliminates the parasitic current flow and therefore reduces overall current consumption The CAPDx bits when set disable the corresponding P2 input and output buffers as shown in Figure 19 4 When current consumption is critical any port pin connected to analog signals should be disabled with its CAPDx bit Selecting an input pin to the comparator multiplexer with the P2CAx bits automatically disables the input and output buffers for that pin regardless of the state of the associated CAPDx bit Figure 19 4 Transfer Characteristic and Power Dissipation in a CMOS Inverter Buffer Vec VI o Vo lcc loc v ES VI Vv or i 0 Vcc Lo e CAPD x 1 Vss 19 2 7 Comparator_A Interrupts One interrupt flag and one interrupt vector are associated with the Comparator_A as shown in Figure 19 5 The interrupt flag CAIFG is set on either the rising or falling edge of the comparator output selected by the CAIES bit If both the CAIE and the GIE bits are set then the CAIFG flag generates an interrupt request The CAIFG flag is automatically reset when the interrupt request is serviced or may be reset with software Figure 19 5 Comparator_A Interrupt System SET_CAIFG Voc CAIE IRQ Interrupt Service Requested IRACC Interrupt Request Accepted Comparator_A 19 7 Comparator_A Operation 19 2 8 Comparator_A Used to Me
532. ts The four MSBs of the 20 bit destination Depending on the des 19 16 tination addressing mode these four MSBs may belong to an index or to an absolute address 1 _____ a 5 _ Q ____ ee ee oo S Note B W and A L Bit Settings for SWPBX and SXTX The B W and A L bit settings for SWPBX and SXTX are A L B W 0 0 SWPBX A SXTX A 0 1 n a 1 0 SWPB W SXTX W 1 1 n a a ee 16 Bit MSP430X CPU 4 45 MSP430X Extended Instructions Figure 4 27 Example for an Extended Register Register Instruction 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 as few ss mas 1 Repetition count in bits 3 0 EEE ai aes 2 XORX A R9 R8 0 0 0 1 XORX instruction Source R9 Destination R8 Destination register mode g Source register mode Figure 4 28 Example for an Extended Immediate Indexed Instruction 10 9 8 7 15 14 13 12 11 6 5 4 3 2 1 0 XORX A 12345h 45678h R15 X Rn 01 Address PC ord 18xx extension word 12345h EAN A e Immediate operand LSBs 2345h Index destination LSBs 5678h 4 46 16 Bit MSP430X CPU MSP430X Extended Instructions Extended Double Operand Format l Instructions All twelve double operand instructions have extended versions as listed in Table 4 13 Table 4 13 Extended Double Operand Instructions Status Bits Mnemonic Operands Operation VN ZC MOVX B A src dst src gt dst ADDX B A src dst src dst gt dst oy ow ha 5y ADDCX
533. tting the SCS bit to synchronize the capture signal with the timer clock is recommended This is illustrated in Figure 13 10 Figure 13 10 Capture Signal SCS 1 CCl Capture Set TBCCRx CCIFG Overflow logic is provided in each capture compare register to indicate if a second capture was performed before the value from the first capture was read Bit COV is set when this occurs as shown in Figure 13 11 COV must be reset with software Timer_B 13 11 Timer_B Operation Figure 13 11 Capture Cycle Idle Capture Capture Read No Capture Taken Read Taken Capture Capture Taken Capture Capture Read and No Capture Capture Clear Bit COV in Register TBCCTLx Second Capture Taken COV 1 Idle Capture Capture Initiated by Software Captures can be initiated by software The CMx bits can be set for capture on both edges Software then sets bit CCIS1 1 and toggles bit CCISO to switch the capture signal between Vcc and GND initiating a capture each time CCISO changes state MOV CAP SCS CCIS1 CM_3 amp TBCCTLx Setup TBCCTLx XOR CCISO amp TBCCTLx TBCCTLx TBR Compare Mode The compare mode is selected when CAP 0 Compare mode is used to generate PWM output signals or interrupts at specific time intervals When TBR counts to the value in a TBCLx Y Interrupt flag CCIFG is set Y Internal signal EQUx 1 Y EQUx affects the output according
534. types of interrupts L System reset Lj Non maskable NMI Y Maskable Figure 2 3 Interrupt Priority Priority High PUC OSCfault Flash ACCV Circuit Reset NMI WDT Security Key a Flash Security Key ESA NZ MAB 5LSBs gt System Resets Interrupts and Operating Modes 2 5 System Reset and Initialization 2 2 1 Non Maskable Interrupts NMI Reset NMI Pin Non maskable NMI interrupts are not masked by the general interrupt enable bit GIE but are enabled by individual interrupt enable bits NMIIE ACCVIE OFIE When a NMI interrupt is accepted all NMI interrupt enable bits are automatically reset Program execution begins at the address stored in the non maskable interrupt vector OFFFCh User software must set the required NMI interrupt enable bits for the interrupt to be re enabled The block diagram for NMI sources is shown in Figure 2 4 A non maskable NMI interrupt can be generated by three sources J An edge on the RST NMI pin when configured in NMI mode Lj An oscillator fault occurs Lj An access violation to the flash memory At power up the RST NMI pin is configured in the reset mode The function of the RST NMI pins is selected in the watchdog control register WDTCTL If the RST NMI pin is set to the reset function the CPU is held in the reset state as long as the RST NMI pin is held low After the inp
535. uction 20 2 ADC10 The ADC10 module supports fast 10 bit analog to digital conversions The module implements a 10 bit SAR core sample select control reference generator and data transfer controller DTC The DTC allows ADC10 samples to be converted and stored anywhere in memory without CPU intervention The module can be configured with user software to support a variety of applications ADC10 features include BP El 10 EL E E DO Lj a Greater than 200 ksps maximum conversion rate Monotonic 10 bit converter with no missing codes Sample and hold with programmable sample periods Conversion initiation by software or Timer_A Software selectable on chip reference voltage generation 1 5 V or 2 5 V Software selectable internal or external reference Eight external input channels twelve on MSP430x22xx devices Conversion channels for internal temperature sensor Vcc and external references Selectable conversion clock source Single channel repeated single channel sequence and repeated sequence conversion modes ADC core and reference voltage can be powered down separately Data transfer controller for automatic storage of conversion results The block diagram of ADC10 is shown in Figure 20 1 ADC10 Introduction Figure 20 1 ADC 10 Block Diagram Ve REF REFBURST REFOUT gt E SREF1 REFON INCHx 0Ah on 1 5V or 2 5V AVCC Reference y ef_x x VRER VRE
536. udes three or four clock sources O LFXT1CLK Low frequency high frequency oscillator that can be used with low frequency watch crystals or external clock sources of 32 768 Hz or with standard crystals resonators or external clock sources in the 400 kHz to 16 MHz range Y XT2CLK Optional high frequency oscillator that can be used with standard crystals resonators or external clock sources in the 400 kHz to 16 MHz range Y DCOCLK Internal digitally controlled oscillator DCO J VLOCLK Internal very low power low frequency oscillator with 12 kHz typical frequency Three clock signals are available from the basic clock module QU ACLK Auxiliary clock ACLK is software selectable as LFXT1CLK or VLOCLK ACLK is divided by 1 2 4 or 8 ACLK is software selectable for individual peripheral modules Y MCLK Master clock MCLK is software selectable as LFXT1CLK VLOCLK XT2CLK if available on chip or DCOCLK MCLK is divided by 1 2 4 or 8 MCLK is used by the CPU and system Y SMCLK Sub main clock SMCLK is software selectable as LFXT1CLK VLOCLK XT2CLK if available on chip or DCOCLK SMCLK is divided by 1 2 4 or 8 SMCLK is software selectable for individual peripheral modules The block diagram of the basic clock module is shown in Figure 5 1 Note Device Specific Clock Variations All clock features are not available on all MSP430x2xx devices MSP430x20xx LFXT1 does not support HF mode XT2 is not pre
537. uest Accepted PUC System Reset Generator POR 3 gt NMIRS WDTTMSEL WDTNMIES WDTNMI WDTQn EQU PUC POR A A A A 9 o IRQ IFG1 0 WDT Counter POR IRQA WDTTMSEL WDTIE IE1 0 Clear Watchdog Timer Module PUC System Resets Interrupts and Operating Modes 2 7 System Reset and Initialization Flash Access Violation The flash ACCVIFG flag is set when a flash access violation occurs The flash access violation can be enabled to generate an NMI interrupt by setting the ACCVIE bit The ACCVIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by a flash access violation Oscillator Fault The oscillator fault signal warns of a possible error condition with the crystal oscillator The oscillator fault can be enabled to generate an NMI interrupt by setting the OFIE bit The OFIFG flag can then be tested by NMI the interrupt service routine to determine if the NMI was caused by an oscillator fault A PUC signal can trigger an oscillator fault because the PUC switches the LFXT1 to LF mode therefore switching off the HF mode The PUC signal also switches off the XT2 oscillator 2 8 System Resets Interrupts and Operating Modes System Reset and Initialization Example of an NMI Interrupt Handler The NMI interrupt is a multiple source interrupt An NMI interrupt automatically resets the NMIIE OFIE and ACCVIE interrupt enable bits The
538. uire an additional word of op code called the extension word Some extended instructions do not require an additional word and are noted in the instruction description All addresses indexes and immediate numbers have 20 bit values when preceded by the extension word There are two types of extension word YU Register register mode for Format l instructions and register mode for Format ll instructions _j Extension word for all other address mode combinations 16 Bit MSP430X CPU 4 43 MSP430X Extended Instructions Register Mode Extension Word The register mode extension word is shown in Figure 4 25 and described in Table 4 11 An example is shown in Figure 4 27 Figure 4 25 The Extension Word for Register Modes 15 12 3 0 11 10 9 8 7 6 5 4 Pe PEP e Table 4 11 Description of the Extension Word Bits for Register Mode Bit Description 15 11 10 9 ZC A L 5 4 3 0 Extension word op code Op codes 1800h to 1FFFh are extension words Reserved Zero carry bit 0 The executed instruction uses the status of the carry bit C 1 The executed instruction uses the carry bit as 0 The carry bit will be defined by the result of the final operation after instruction execu tion Repetition bit 0 The number of instruction repetitions is set by extension word bits 3 0 1 The number of instructions repetitions is defined by the value of the four LSBs of Rn See description for bits 3 0 Data le
539. urce and C decimally to dst Decrement destination Double decrement destination Disable interrupts Enable interrupts Increment destination Double increment destination Invert destination Jump if C set Jump if higher or same Jump if equal Jump if Z set Jump if greater or equal Jump if less Jump Jump if N set Jump if C not set Jump if lower Jump if not equal Jump if Z not set Move source to destination No operation Pop item from stack to destination Push source onto stack Return from subroutine Return from interrupt Rotate left arithmetically Rotate left through C Rotate right arithmetically Rotate right through C Subtract not C from destination Set C Set N Set Z Subtract source from destination Subtract source and not C from dst Swap bytes Extend sign Test destination Exclusive OR source and destination dst C gt dst src dst gt dst src dst C gt dst src and dst dst not src and dst gt dst src or dst gt dst src and dst dst gt PC PC 2 gt stack dst PC 0 gt dst 0 gt C 0 gt N 0 gt 3Z dst src dst C gt dst decimally src dst C gt dst decimally dst 1 gt dst dst 2 gt dst 05 GIE 15 GIE dst 1 gt dst dst 2 gt dst not dst gt dst PC 2 x offset gt PC src dst SP gt dst SP 2 gt SP SP 2 gt SP src gt SP SP gt PC SP 2 gt SP dst OFFFFh C gt dst 13C 1ON 13C dst not src
540. ure 13 9 Output Unit in Up Down Mode 13 10 TBR max TBCLO TBCL1 TBCL3 Oh TBIFG Timer_B Iq Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQU EQU1 pjrg EQUI EQUA Interrupt Events EQUO EQUO EQU3 EQU3 EQU3 EQU3 Timer_B Operation 13 2 4 Capture Compare Blocks Capture Mode Three or seven identical capture compare blocks TBCCRx are present in Timer_B Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIXA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture is performed Y The timer value is copied into the TBCCRx register Y The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x2xx family devices may have different signals connected to CCIxA and CCIxB Refer to the device specific data sheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Se
541. user NMI service routine resets the interrupt flags and re enables the interrupt enable bits according to the application needs as shown in Figure 2 5 Figure 2 5 NMI Interrupt Handler Start of NMI Interrupt Handler Reset by HW OFIE NMIIE ACCVIE Reset OFIFG Reset ACCVIFG Reset NMIIFG User s Software User s Software User s Software Oscillator Fault Flash Access External NMI Handler Violation Handler Handler Optional RETI End of NMI Interrupt Handler SP ae ae ee A A TT A SC Note Enabling NMI Interrupts with ACCVIE NMIIE and OFIE To prevent nested NMI interrupts the ACCVIE NMIIE and OFIE enable bits should not be set inside of an NMI interrupt service routine LT o 2 2 2 Maskable Interrupts Maskable interrupts are caused by peripherals with interrupt capability including the watchdog timer overflow in interval timer mode Each maskable interrupt source can be disabled individually by an interrupt enable bit or all maskable interrupts can be disabled by the general interrupt enable GIE bit in the status register SR Each individual peripheral interrupt is discussed in the associated peripheral module chapter in this manual System Resets Interrupts and Operating Modes 2 9 System Reset and Initialization 2 2 3 Interrupt Processing When an interrupt is requested from a peripheral and the peripheral interrupt enable bit and GIE bit are set the interrupt service
542. ut changes to a high state the CPU starts program execution at the word address stored in the reset vector OFFFEh and the RSTIFG flag is set If the RST NMI pin is configured by user software to the NMI function a signal edge selected by the WDTNMIES bit generates an NMI interrupt if the NMIIE bit is set The RST NMI flag NMIIFG is also set Note Holding RST NMI Low When configured in the NMI mode a signal generating an NMI event should not hold the RST NMI pin low If a PUC occurs from a different source while the NMI signal is low the device will be held in the reset state because a PUC changes the RST NMI pin to the reset function Note Modifying WOTNMIES When NMI mode is selected and the WDTNMIES bit is changed an NMI can be generated depending on the actual level at the RST NMI pin When the NMI edge select bit is changed before selecting the NMI mode no NMI is generated a a 2 6 System Resets Interrupts and Operating Modes System Reset and Initialization Figure 2 4 Block Diagram of Non Maskable Interrupt Sources ACCV ACCVIFG B FCTL3 2 ACCVIE 161 5 Clear PUC RST NMI POR PORIFG IFG1 2 Flash Module RSTIFG IFG1 3 POR PUG Clear KEYV SVS_POR BOR K NMIIFG IFG1 4 PUC NMIIE Wd 1E1 4 Clear PUC OSCFault OFIFG IFG1 1 A OFIE 161 1 Clear o NMI_IRQA PUC IRQA Interrupt Req
543. ut of the OAx is connected to Rrop and Rgottom is connected to an analog multiplexer that multiplexes the OAxl0 OAxI1 OAXIA or the output of one of the remaining OAs selected with the OANx bits The OAXTAP signal is connected to the inverting input of the OAx providing an inverting amplifier with a gain of OAXxTAP ratio The OAXTAP ratio is selected by the OAFBRx bits The non inverting input is selected by the OAPx bits The OAx output is connected to the ADC12 input channel as selected by the OAXCTLO bits Oe ES ee Note Using OAx Negative Input Simultaneously as ADC Input When the pin connected to the negative input multiplexer is also used as an input to the ADC conversion errors up to 5mV may be observed due to internal wiring voltage drops a OA 18 7 OA Operation Differential Amplifier Mode This mode allows internal routing of the OA signals for a two opamp or three opamp instrumentation amplifier Figure 18 2 shows a two opamp configuration with OAO and OA1 In this mode the output of the OAx is connected to Rrop by routing through another OAx in the Inverting PGA mode Rsottom is unconnected providing a unity gain buffer This buffer is combined with one or two remaining OAx to form the differential amplifier The OAx output is connected to the ADC12 input channel as selected by the OAxCTLO bits Figure 18 2 shows an example of a two opamp differential amplifier using OAO and OA1 The control registe
544. utput Unit in Up Down Mode gt id gt 4 Dead Time Output Mode 6 Toggle Set Output Mode 2 Toggle Reset EQU1 EQU EQU1 EQU Interrupt Events EQUO EQU2 EQU2 EQU2 EQU2 Timer_A Operation 12 2 4 Capture Compare Blocks Capture Mode Two or three identical capture compare blocks TACCRx are present in Timer_A Any of the blocks may be used to capture the timer data or to generate time intervals The capture mode is selected when CAP 1 Capture mode is used to record time events It can be used for speed computations or time measurements The capture inputs CCIXA and CCIxB are connected to external pins or internal signals and are selected with the CCISx bits The CMx bits select the capture edge of the input signal as rising falling or both A capture occurs on the selected edge of the input signal If a capture occurs JJ The timer value is copied into the TACCRx register Y The interrupt flag CCIFG is set The input signal level can be read at any time via the CCI bit MSP430x2xx family devices may have different signals connected to CCIxA and CCIxB See the device specific data sheet for the connections of these signals The capture signal can be asynchronous to the timer clock and cause a race condition Setting the SCS bit will synchronize the capture with the next timer clock Setting the SCS bit to synchronize the capture signal with the timer clock
545. ve operation in LPM4 no internal clock required Selectable MSB or LSB data order START and STOP detection for 12C mode with automatic SCL control Arbitration lost detection in master mode Programmable clock generation LI OE Selectable clock polarity and phase control Figure 14 1 shows the USI module in SPI mode Figure 14 2 shows the USI module in 12 mode 14 2 Universal Serial Interface Figure 14 1 USI Block Diagram SPI Mode USII2C 0 USIGE E USIOE USI Introduction USIPE6 D USH6B USILSB DO Q SDO USIPE7 8 16 Bit Shift Register 0 lt gt USISR USICNTx USIIFGCC gt Bit Counter q EN USICKPH A USICKPL i Shift Clock lt t USISWRST m Pogues SDI USIPE5 lan SCLK USISSELx SCLK ACLK USIDIVx SMCLK SMCLK Clock Divider 1 2 4 8 128 USISWCLK TAO TA1 TA2 HOLD USIIFG USIMST USICLK Universal Serial Interface 14 3 USI Introduction Figure 14 2 USI Block Diagram 12C Mode USIOE USII2C 1 a USICKPL 1 Set USIAL USICKPH 0 2 USILSB 0 ear USIOE USI16B 0 USIGE O ry USISWRST m USICKPL Shift Clock STOP USICKPH gt e ion ee USISTP o USIPE7 8 Bit Shift Register o e SL SDA lt lt USISRL gt E Az eo START Set USISTTIFG Detect USIPE6 Ce
546. vers a 20 bit address which points to an address in the range O to FFFFFh The operand is the content of the addressed memory location Valid for source and destination The assembler calculates the register index and inserts it ADD W 8346h R5 2100h R6 This instruction adds the 16 bit data contained in the source and the destination addresses and places the 16 bit result into the destination Source and destination operand can be located in the entire address range Source Destination The word pointed to by R5 8346h The negative index 8346h is sign extended which results in address 23456h F8346h 1B79Ch The word pointed to by R6 2100h results in address 15678h 2100h 17778h Figure 4 18 Example for the Indexed Mode 4 20 Before 1103Ah 11038h 11036h 11034h 1777Ah 17778h 1B79Eh 1B79Ch 16 Bit MSP430X CPU After Address Register Address Register Space Space PC R5 23456h R6 15678h R5 23456h 1103Ah R6 15678h 11038h 11036h 11034h 15678h 05432h src 02100h 1777Ah 02345h__ dst 17778h 47778h 07777h Sum 23456h F8346h 1B79Eh 1679601 1B79Ch CPU Registers MSP430X Instruction with Indexed Mode When using an MSP430X instruction with Indexed mode the operand can be located anywhere in the range of Rn 19 bits Length Operation Comment Example Three or four words The operand address is the sum of the 20 bit CPU register content and the 20 bit ind
547. w 0 rw 0 rw 0 rw 0 rw 0 rw 0 t Does not apply to MSP430x20xx or MSP430x21xx SELMx DIVMx SELS DIVSx DCOR Bits 7 6 BitS 5 4 Bit 3 BitS 2 1 Bit O Select MCLK These bits select the MCLK source 00 DCOCLK 01 DCOCLK 10 XT2CLK when XT2 oscillator present on chip LFXT1CLK or VLOCLK when XT2 oscillator not present on chip 11 LFXT1CLK or VLOCLK Divider for MCLK 00 1 01 2 10 4 11 8 Select SMCLK This bit selects the SMCLK source 0 DCOCLK 1 XT2CLK when XT2 oscillator present LFXT1CLK or VLOCLK when XT2 oscillator not present Divider for SMCLK oo A 01 2 10 4 11 8 DCO resistor select 0 Internal resistor 1 External resistor Basic Clock Module 5 15 Basic Clock Module Registers BCSCTL3 Basic Clock System Control Register 3 7 6 5 4 3 2 1 0 XT2Sx LFXT1Sx XCAPx XT20Ft LFXT10F rw 0 rw 0 rw 0 rw 0 rw 0 rw 1 ro r 1 t Does not apply to MSP430x2xx MSP430x21xx or MSP430x22xx devices XT2Sx Bits XT2 range select These bits select the frequency range for XT2 7 6 00 0 4 1 MHz crystal or resonator 01 1 3 MHz crystal or resonator 10 3 16 MHz crystal or resonator 11 Digital external 0 4 16 MHz clock source LFXT1Sx Bits Low frequency clock select and LFXT1 range select These bits select 5 4 between LFXT1 and VLO when XTS 0 and select the frequency range for LFXT1 when XTS 1 When XTS 0 00 32768 Hz Crystal on LFXT1 01 Reserved 10 VLOCLK Reserved in MSP430x21x1
548. w 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16 Bits Interrupt delay generation after conversion start These bits select the INTDLYx 7 6 delay for the first interrupt after conversion start 00 Fourth sample causes interrupt 01 Third sample causes interrupt 10 Second sample causes interrupt 11 First sample causes interrupt SD16GAINx Bits SD16_A preamplifier gain 5 3 000 x1 001 x2 010 x4 011 x8 100 x16 101 x32 110 Reserved 111 Reserved SD16INCHx Bits SD16_A channel differential pair input 2 0 000 AO 001 A1 010 A2 011 A3 100 A4 101 A5 AVcc AVsg 11 110 A6 Temperature Sensor 111 A7 Short for PGA offset measurement 24 20 SD16_A SD16_A Registers SD16MEMO SD16_A Conversion Memory Register 15 14 13 12 11 10 9 8 r r r r r r r r 7 6 5 4 3 2 1 0 r r r r r r r r Conversion Bits Conversion Results The SD16MEMx register holds the upper or lower Result 15 0 16 bits of the digital filter output depending on the SD16LSBACC bit SD16AE SD16_A Analog Input Enable Register 7 6 5 4 3 2 1 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 SD16AEx Bits SD16_A analog enable 7 0 0 External input disabled Negative inputs are internally connected to VSS 1 External input enabled SD16_A 24 21 SD16_A Registers SD16IV SD16_A Interrupt Vector Register 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ro ro ro r 0 r 0 r 0 r 0 ro SD16IVx Bits SD16_A interrupt vector value 15 0 SD16IV Interrupt Contents Int
549. when UCB1TXBUF is TXIFG empty 0 No interrupt pending 1 Interrupt pending UCB1 Bit 2 USCI_B1 receive interrupt flag UCB1RXIFG is set when UCB1RXBUF has RXIFG received a complete character 0 No interrupt pending 1 Interrupt pending Bits These bits may be used by other modules see the device specific data 1 0 sheet 17 34 Universal Serial Communication Interface 1 C Mode Chapter 18 OA The OA is a general purpose operational amplifier This chapter describes the OA Two OA modules are implemented in the MSP430x22x4 devices Topic Page 18 1 OAntroductiom a a ada 18 2 18 2 0A Operation een eea a a e 18 4 18 32 OAIReGISTErS eee e A AE erie E E E E ta 18 12 18 1 OA Introduction 18 1 OA Introduction 18 2 OA The OA operational amplifiers support front end analog signal conditioning prior to analog to digital conversion Features of the OA include Single supply low current operation Rail to rail output Software selectable configurations E E _j Programmable settling time vs power consumption E E Software selectable feedback resistor ladder for PGA implementations ee Oo _x_ __ Note Multiple OA Modules Some devices may integrate more than one OA module In the case where more than one OA is present on a device the multiple OA modules operate identically Throughout this chapter nomenclature appears such as OAxCTLO to describe register names When this occurs the x is u
550. when address received matches the USCI slave address r Mode Slave transmitter mode is entered when the slave address transmitted by the master is identical to its own address with a set R W bit The slave transmitter shifts the serial data out on SDA with the clock pulses that are generated by the master device The slave device does not generate the clock but it will hold SCL low while intervention of the CPU is required after a byte has been transmitted If the master requests data from the slave the USCI module is automatically configured as a transmitter and UCTR and UCBxTXIFG become set The SCL line is held low until the first data to be sent is written into the transmit buffer UCBxTXBUF Then the address is acknowledged the UCSTTIFG flag is cleared and the data is transmitted As soon as the data is transferred into the shift register the UCBxTXIFG is set again After the data is acknowledged by the master the next data byte written into UCBxTXBUF is transmitted or if the buffer is empty the bus is stalled during the acknowledge cycle by holding SCL low until new data is written into UCBxTXBUF If the master sends a NACK succeeded by a STOP condition the UCSTPIFG flag is set If the NACK is succeeded by a repeated START condition the USCI 12C state machine returns to its address reception state Figure 17 9 illustrates the slave transmitter operation 17 10 Universal Serial Communication Interface 1 C Mode Figure 17 9 12C Slave
551. with a set EOS bit Figure 21 7 shows the sequence of channels mode When ADC12SC triggers a sequence successive sequences can be triggered by the ADC12SC bit When any other trigger source is used ENC must be toggled between each sequence Figure 21 7 Sequence of Channels Mode CONSEQx 01 ADC120N 1 ENC 4 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 ord and ADC12SC A Wait for Trigger SAMPCON 4 EOS x 1 SAMPCON 1 Sample Input Channel Defined in ADC12MCTLx Ifx lt 15 then x xXx 1 else x 0 lfx lt 15 then x xXx 1 else x 0 SAMPCON _ 12 x ADC12CLK MSC 1 and SHP 1 and EOS x 0 1 x ADC12CLK Conversion Completed Result Stored Into ADC12MEMx ADC12IFG x is Set x pointer to ADC12MCTLx 21 12 ADC12 ADC12 Operation Repeat Single Channel Mode A single channel is sampled and converted continuously The ADC results are written to the ADC12MEMx defined by the CSTARTADDx bits It is necessary to read the result after the completed conversion because only one ADC12MEMx memory is used and is overwritten by the next conversion Figure 21 8 shows repeat single channel mode Figure 21 8 Repeat Single Channel Mode CONSEQx 10 ADC120N 1 x CSTARTADDx Wait for Enable SHSx 0 and ENC 1 or 4 and ADC12SC 4 Wait for Trigger SAMPCON 4 ENC 0 SAMPCON 1 Sample Input
552. written to SD16MEMO location before the previous conversion result was read SD16IV Interrupt Vector Generator All SD16_A interrupt sources are prioritized and combined to source a single interrupt vector SD16IV is used to determine which enabled SD16_A interrupt source requested an interrupt The highest priority SD16_A interrupt request that is enabled generates a number in the SD16IV register see register description This number can be evaluated or added to the program counter to automatically enter the appropriate software routine Disabled SD16_A interrupts do not affect the SD16IV value Any access read or write of the SD16IV register has no effect on the SD160VIFG or SD16IFG flags The SD16IFG flags are reset by reading the SD16MEMO register or by clearing the flags in software SD16OVIFG bits can only be reset with software If another interrupt is pending after servicing of an interrupt another interrupt is generated For example if the SD16OVIFG and one or more SD16IFG interrupts are pending when the interrupt service routine accesses the SD16IV register the SD16OVIFG interrupt condition is serviced first and the corresponding flag s must be cleared in software After the RETI instruction of the interrupt service routine is executed the highest priority SD16IFG pending generates another interrupt request Interrupt Delay Operation The SD16INTDLYx bits control the timing for the first interrupt service request for the co
553. x Operation Description Status Bits Mode Bits Example Example Example MSP430 Instructions Test bits set in source word in destination word Test bits set in source byte in destination byte BIT src dst or BITW src dst BIT B src dst src and dst The source operand and the destination operand are logically ANDed The result affects only the status bits in SR Register Mode the register bits Rdst 19 16 W resp Rdst 19 8 B are not cleared N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if the result is not zero reset otherwise C not Z V Reset OSCOFF CPUOFF and GIE are not affected Test if one or both of bits 15 and 14 of R5 16 bit data is set Jump to label TONI if this is the case R5 19 16 are not affected BIT C000h R5 Test R5 15 14 bits JNZ TONI At least one bit is set in R5 Both bits are reset A table word pointed to by R5 20 bit address is used to test bits in R7 Jump to label TONI if at least one bit is set R7 19 16 are not affected BIT W R5 R7 Test bits in R7 JC TONI At least one bit is set Both are reset A table byte pointed to by R5 20 bit address is used to test bits in output Port1 Jump to label TONI if no bit is set The next table byte is addressed BITB R5 amp P10OUT Test I O port P1 bits R5 1 JNC TONI No corresponding bit is set At least one bit is set
554. x share the same interrupt vectors The receive interrupt flags UCAxRXIFG and UCBxRXIFG are routed to one interrupt vector the transmit interrupt flags UCAxTXIFG and UCBxTXIFG share another interrupt vector Shared Interrupt Vectors Software Example 16 14 The following software example shows an extract of an interrupt service routine to handle data receive interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIAO RX USCIBO RX ISR BIT B UCAORXIFG amp IFG2 USCI_AO Receive Interrupt JNZ USCIAO_RX_ISR USCIBO_RX_ISR Read UCBORXBUF clears UCBORXIFG RETI USCIAO RX_ISR Read UCAORXBUF clears UCAORXIFG RETI The following software example shows an extract of an interrupt service routine to handle data transmit interrupts from USCI_AO in either UART or SPI mode and USCI_BO in SPI mode USCIAO TX_USCIBO_TX_ISR BIT B UCAOTXIFG amp IFG2 USCI_AO Transmit Interrupt JNZ USCIAO_TX_ISR USCIBO_TX_ ISR Write UCBOTXBUF clears UCBOTXIFG RETI USCIAO_TX_ISR Write UCAOTXBUF clears UCAOTXIFG RETI Universal Serial Communication Interface SPI Mode USCI Registers SPI Mode 16 4 USCI Registers SPI Mode The USCI registers applicable in SPI mode for USCI_AO and USCI_BO are listed in Table 16 2 Registers applicable in SPI mode for USCI_A1 and USCI_B1 are listed in Table 16 3 Table 16 2 USCI_AO and USCI_BO Control and Status Registers Register Short Form Register Type Address Initial State
555. xample Example Extended Instructions Add source address word and carry to destination address word Add source word and carry to destination word Add source byte and carry to destination byte ADDCX A src dst ADDCX src dst or ADDCX W src dst ADDCX B src dst src dst C gt dst The source operand and the carry bit C are added to the destination operand The previous contents of the destination are lost Both operands may be located in the full address space N Set if result is negative MSB 1 reset if positive MSB 0 Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise V Set if the result of two positive operands is negative or if the result of two negative numbers is positive reset otherwise OSCOFF CPUOFF and GIE are not affected Constant 15 and the carry of the previous instruction are added to the 20 bit counter CNTR located in two words ADDCX A 15 amp CNTR Add 15 C to 20 bit CNTR A table word pointed to by R5 20 bit address and the carry C are added to R6 The jump to label TONI is performed on a carry ADDCX W OR5 R6 JC TONI Add table word C to R6 Jump if carry No carry A table byte pointed to by R5 20 bit address and the carry bit C are added to R6 The jump to label TONI is performed if no carry occurs The table pointer is auto incremented by 1 ADDCX B R5 R6 JNC TONI Add table byte C to R6 R5 1
556. xternal trigger DMAEO DMA1 Bits Same as DMA2TSELx TSELx 7 4 DMAO Bits Same as DMA2TSELx TSELx 3 0 6 20 DMA Controller DMA Registers DMACTL1 DMA Control Register 1 15 14 13 12 11 10 9 8 ro ro ro ro ro ro ro ro 7 6 5 4 3 2 1 0 ONFETCH ROBIN ro ro ro ro ro rw 0 rw 0 rw 0 Reserved Bits Reserved Read only Always read as 0 15 3 DMA Bit 2 DMA on fetch ONFETCH O The DMA transfer occurs immediately 1 The DMA transfer occurs on next instruction fetch after the trigger ROUND Bit 1 Round robin This bit enables the round robin DMA channel priorities ROBIN O DMA channel priority is DMAO DMA1 DMA2 1 DMA channel priority changes with each transfer ENNMI Bit O Enable NMI This bit enables the interruption of a DMA transfer by an NMI interrupt When an NMI interrupts a DMA transfer the current transfer is completed normally further transfers are stopped and DMAABORT is set 0 NMI interrupt does not interrupt DMA transfer 1 NMI interrupt interrupts a DMA transfer DMA Controller 6 21 DMA Registers DMAxCTL DMA Channel x Control Register 15 rw 0 Reserved DMADTx DMA DSTINCRx DMA SRCINCRx DMA DSTBYTE 6 22 14 rw 0 Bit 15 Bits 14 12 Bits 11 10 Bits 9 8 Bit 7 13 12 11 10 o DMADTx DMADSTINCRx DMASRCINCRx rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 rw 0 Reserved DMA Transfer mode 000 Single transfer 001 Block transfer 010 Burst block
557. y is preserved and not subject to cabling interference Introduction 1 3 Address Space 1 4 Address Space The MSP430 von Neumann architecture has one address space shared with special function registers SFRs peripherals RAM and Flash ROM memory as shown in Figure 1 2 See the device specific data sheets for specific memory maps Code access are always performed on even addresses Data can be accessed as bytes or words The addressable memory space is currently 128 KB Figure 1 2 Memory Map Access 1FFFFh Flash ROM Word Byte 10000h OFFFFh Interrupt Vector Table Word Byte OFFEOh OFFDFh Flash ROM Word Byte 01FFh 16 Bit Peripheral Modules Word 0100h OFFh 8 Bit Peripheral Modules Byte 010h Word Byte OFh a f A Special Function Registers Byte 1 4 1 Flash ROM The start address of Flash ROM depends on the amount of Flash ROM present and varies by device The end address for Flash ROM is 0x1FFFF Flash can be used for both code and data Word or byte tables can be stored and used in Flash ROM without the need to copy the tables to RAM before using them The interrupt vector table is mapped into the upper 16 words of Flash ROM address space with the highest priority interrupt vector at the highest Flash ROM word address 0x1FFFF 1 4 Introduction Address Space 1 4 2 RAM RAM starts at 0200h The end address of RAM depends on the amount of RAM present and varies by device RAM can be used for bo
558. ystem Resets Interrupts and Operating Modes Principles for Low Power Applications 2 4 Principles for Low Power Applications Often the most important factor for reducing power consumption is using the MSP430 s clock system to maximize the time in LPM3 LPM3 power consumption is less than 2 A typical with both a real time clock function and all interrupts active A 32 kHz watch crystal is used for the ACLK and the CPU is clocked from the DCO normally off which has a 6 us wake up _j Use interrupts to wake the processor and control program flow _j Peripherals should be switched on only when needed _j Use low power integrated peripheral modules in place of software driven functions For example Timer_A and Timer_B can automatically generate PWM and capture external timing with no CPU resources L 2 5 Connection of Unused Pins Y Calculated branching and fast table look ups should be used in place of flag polling and long software calculations Avoid frequent subroutine and function calls due to overhead g For longer software routines single cycle CPU registers should be used The correct termination of all unused pins is listed in Table 2 2 Table 2 2 Connection of Unused Pins Pin AVcc AVss VREF VeREF Vrer Verer XIN XOUT XT2IN XT20UT Px 0 to Px 7 RST NMI Test TDO TDI TMS TCK Potential DVss Open DVss Open DVss Open Open Comment Switched to port function output direction
559. yte SBCX A dst SBCX dst or SBCX B dst SBCX W dst dst OFFFFFh C gt dst dst OFFFFh C gt dst dst OFFh C gt dst SUBCX A 0 dst SUBCX 0 dst SUBCX B 0 dst The carry bit C is added to the destination operand minus one The previous contents of the destination are lost N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if there is a carry from the MSB of the result reset otherwise Set to 1 if no borrow reset if borrow V Set if an arithmetic overflow occurs reset otherwise OSCOFF CPUOFF and GIE are not affected The 8 bit counter pointed to by R13 is subtracted from a 16 bit counter pointed to by R12 SUBX B SBCX B R13 0 R12 1 R12 Subtract LSDs Subtract carry from MSD AAA ARA AA TT gt E U4 fhe Note Borrow Implementation The borrow is treated as a NOT carry Borrow Carry bit Yes 0 No 1 16 Bit MSP430X CPU SUBX A SUBX W SUBX B Syntax Operation Description Status Bits Mode Bits Example Example Example Extended Instructions Subtract source address word from destination address word Subtract source word from destination word Subtract source byte from destination byte SUBX A src dst SUBX src dst or SUBX W src dst SUBX B src dst not src 1 dst gt dst or dst src dst The source operand is subtracted from the destination operand This is made by adding the 1 s com
560. yte as shown in Figure 3 19 N Set if result is negative reset if positive Z Set if result is zero reset otherwise C Set if result is not zero reset otherwise NOT Zero V Reset OSCOFF CPUOFF and GIE are not affected Figure 3 19 Destination Operand Sign Extension Example 15 8 7 0 R7 is loaded with the P1IN value The operation of the sign extend instruction expands bit 8 to bit 15 with the value of bit 7 R7 is then added to R6 MOV B amp P1IN R7 P1IN 080h a 1000 0000 SXT R7 R7 OFF80h 1111 1111 1000 0000 RISC 16 Bit CPU 3 69 Instruction Set TST W TST B Syntax Operation Emulation Description Status Bits Mode Bits Example Example Test destination Test destination TST dst or TST W dst TST B dst dst OFFFFh 1 dst OFFh 1 CMP 0 dst CMP B 0 dst The destination operand is compared with zero The status bits are set accord ing to the result The destination is not affected N Set if destination is negative reset if positive Z Set if destination contains zero reset otherwise C Set V Reset OSCOFF CPUOFF and GIE are not affected R7 is tested If it is negative continue at R7NEG if it is positive but not zero continue at R7POS TST R7 Test R7 JN R7NEG R7 is negative JZ R7ZERO R7 is zero R7POS ia R7 is positive but not zero R7NEG ti R7 is negative R7ZERO oew R7 is zero The low byte of R7 is tested If it is

MSP430x2xx Family User's Guide (Rev. E

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