CRG Block User Guide V04.05
Contents
1. 19 3 3 7 CRG PLL Control Register PLLCTL 21 3 3 8 CRG RTI Control Register RTICTL 23 3 3 9 CRG COP Control Register COPCTL 24 3 3 10 Reserved Register FORBYP 25 3 3 11 Reserved Register CTCTL 26 3 3 12 CRG COP Timer Arm Reset Register ARMCOP 26 Section 4 Functional Description 4 1 Generals ss ae de Mat hte Ph Seale ld e Bote ce otters afta ds 29 4 2 Eunctional BIOGKS 2 25 mn pa st ids Bae eee DUDE en old Notes oe es 29 M MOTOROLA 3 CRG Block User Guide V04 05 4 2 1 Phase Locked Loop PIE ot en see 29 4 2 2 SY SICHLGIOCKS Generator nko ae esr Bee ee ee See we ese ar 32 4 2 3 Clock Monitor CM mia ido weg anes ee ws beamed meld ate SOS 33 4 2 4 Glock Quality Checker 33 4 2 5 Computer Operating Properly Watchdog COP 35 4 2 6 Real TIME IMPAR css sas Get coast a den 36 ESO MOTOS sirene er GA PAA a O O KANA ES 37 4 3 1 Normal Mode prosa sr ed over Saget ne mini eee eee sees eos 37 4 3 2 Sel Clocks Mode ot ss kad LAN Ot oo olen ete Me bag Mah NG bi ns 37 4 4 OW POWER ODIOS a naan mng erde weine e 37 4 4 1 RUMMO a tes Cae eet RA ee q q ENDURO MUR NAWA CR dub 37 4 4 2 Walt ModE ia ed2. 16 Reserved Register CTFLG aea 17 CRG Flags Register CRGFLG 17 CRG Interrupt Enable Register CRGINT 19 CRG Clock Select Register CLKSEL 19 CRG PLE Control Register PLECTE 21 CRG RTI Control Register RTICTL 23 CRG COP Control Register COPCTL 24 Reserved Register FORBYP 26 Reserved Register CTCTL 26 ARMCOP Register Diagram 27 PLL Functional Diagram 29 System Clocks Generator eri dana ee 32 Core Clock and Bus Clock relationship 33 Check Window Erkample 34 Sequence for Clock Quality Check 34 Glock Cham for COP a E O 35 Clock Chain for RTI 36 Wait Mode Entry Exit Sequence 39 Stop Mode Entry Exit Sequence 43 RESET MINO 2322 2228028 fies ott abit ae da DE ool ehe 48 RESET pin tied to VDD by a pull up resistor 49 RESET pin held low externally 50 CRG Block User Guide
3. V04 05 6 AR MOTOROLA CRG Block User Guide V04 05 List of Tables Table 3 1 CRGMemoryMap 15 Table 3 2 RTI Frequency Divide Rates 23 Table 3 3 COPWatchdogRates 25 Table 4 1 MCU configuration during Wait Mode 38 Table 4 2 Outcome of Clock Loss in Wait Mode 40 Table 4 3 Outcome of Clock Loss in Pseudo Stop Mode 44 Table 5 1 Reset Summa sr E o Pr KANAN 47 Table 5 2 Reset Vector Selection 47 Table 6 1 CRG Interrupt Vectors 51 M MOTOROLA 7 CRG Block User Guide V04 05 8 AR MOTOROLA CRG Block User Guide V04 05 Section 1 Introduction 1 1 Overview This specification describes the function of the Clocks and Reset Generator CRG 1 2 Features The main features of this block are 1 3 Phase Locked Loop PLL frequency multiplier Reference divider Automatic bandwidth control mode for low jitter operation Automatic frequency lock detector CPU interrupt on entry or exit from locked condition Self Clock Mode in absence of reference clock System Clock Generator Clock Quality Check Clock switch for either Oscillator or PLL based system clocks User sele
4. 2xOSCCLKx Address Offset 00 7 6 5 4 3 2 1 0 E SYN5 SYN4 SYN3 SYN2 SYN1 SYNO RESET 0 0 0 0 0 0 0 0 ee Unimplemented or Reserved Figure 3 1 CRG Synthesizer Register SYNR Read anytime Write anytime except if PLLSEL 1 NOTE Write to this register initializes the lock detector bit and the track detector bit 3 3 2 CRG Reference Divider Register REFDV The REFDV register provides a finer granularity for the PLL multiplier steps The count in the reference divider divides OSCCLK frequency by REFDV 1 Address Offset 01 7 6 5 4 3 2 1 0 E 0 0 0 0 REFDV3 REFDV2 REFDV1 REFDVO RESET 0 0 0 0 0 0 E Unimplemented or Reserved Figure 3 2 CRG Reference Divider Register REFDV Read anytime Write anytime except when PLLSEL 1 NOTE Write to this register initializes the lock detector bit and the track detector bit 3 3 3 Reserved Register CTFLG This register is reserved for factory testing of the CRG module and is not available in normal modes 16 M MOTOROLA CRG Block User Guide V04 05 Address Offset 02 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 ga RESET 0 0 0 0 0 0 0 0 E Unimplemented or Reserved Figure 3 3 Reserved Register CTFLG Read always reads 00 in normal modes Write unimplemented in normal modes NOTE Writing to this register when in special mode can alter the CRG fucntionality 3 3 4 CRG Flags Regi
5. Continue w normal OP Figure 4 9 Stop Mode Entry Exit Sequence 4 4 3 1 Wake up from Pseudo Stop PSTP 1 Wake up from Pseudo Stop is the same as wake up from Wait Mode There are also three different scenarios for the CRG to restart the MCU from Pseudo Stop Mode M MOTOROLA 43 CRG Block User Guide V04 05 e External Reset e Clock Monitor Fail e Wake up Interrupt If the MCU gets an external reset during Pseudo Stop Mode active the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset generator After completing the reset sequence processing begins by fetching the normal reset vector Pseudo Stop Mode is left and the MCU is in Run Mode again If the clock monitor is enabled CME 1 the MCU is able to leave Pseudo Stop Mode when loss of oscillator external clock is detected by a clock monitor fail If the SCME bit is not asserted the CRG generates a clock monitor fail reset CMRESET The CRG s behavior for CMRESET is the same compared to external reset but another reset vector is fetched after completion of the reset sequence If the SCME bit is asserted the CRG generates a SCM interrupt if enabled SCMIE 1 After generating the interrupt the CRG enters Self Clock Mode and starts the clock quality checker see 4 2 4 Clock Quality Checker Then the MCU continues with normal operation If the SCM interrupt is blocked by SCMIE 0 the SCMIF flag will be asserted but the
6. RTIE 1 this interrupt will occur at the rate selected by the RTICTL register The RTI runs with a gated OSCCLK see Figure 4 7 Clock Chain for RTI At the end of the RTI time out period the RTIF flag is set to one and a new RTI time out period starts immediately A write to the RTICTL register restarts the RTI time out period If the PRE bit is set the RTI will continue to run in Pseudo Stop Mode WAIT RTIWAD STOP PSTP PRE RTI enable OSCCLK A 1024 RTR 6 4 gating condition Clock Gate RTI TIMEOUT 4 BIT MODULUS COUNTER RTR 3 0 Figure 4 7 Clock Chain for RTI 36 M MOTOROLA CRG Block User Guide V04 05 4 3 Operation Modes 4 3 1 Normal Mode The CRG block behaves as described within this specification in all normal modes 4 3 2 Self Clock Mode The VCO has a minimum operating frequency fscm If the external clock frequency is not available due to a failure or due to long crystal start up time the Bus Clock and the Core Clock are derived from the VCO running at minimum operating frequency this mode of operation is called Self Clock Mode This requires CME 1 and SCME 1 If the MCU was clocked by the PLL clock prior to entering Self Clock Mode the PLLSEL bit will be cleared If the external clock signal has stabilized again the CRG will automatically select OSCCLK to be the system clock and return to normal mode See 4 2 4 Clock Quality Checker for more information on entering and leaving Self C
7. The MCU requires an external interrupt or an external reset in order to wake up from Stop Mode If the MCU gets an external reset during Full Stop Mode active the CRG asynchronously restores all configuration bits in the register space to its default settings and will perform a maximum of 50 clock check_windows see 4 2 4 Clock Quality Checker After completing the clock quality check the CRG starts the reset generator After completing the reset sequence processing begins by fetching the normal reset vector Full Stop Mode is left and the MCU is in Run Mode again If the MCU is woken up by an interrupt the CRG will also perform a maximum of 50 clock check_windows see 4 2 4 Clock Quality Checker If the clock quality check is successful the CRG will release all system and core clocks and will continue with normal operation If all clock checks within the Timeout Window are failing the CRG will switch to Self Clock Mode or generate a clock monitor reset CMRESET depending on the setting of the SCME bit Because the PLL has been powered down during Stop Mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving Stop Mode The software must manually set the PLLSEL bit again in order to switch system and core clocks to the PLLCLK NOTE In Full Stop Mode the clock monitor is disabled and any loss of clock will not be detected 46 M MOTOROLA CRG Block User Guide V04 05 Section 5 Resets 5 1 General This section descr
8. 3 2 1 0 a RTIE 0 0 LOCKIE 0 0 SCMIE RESET O 0 0 0 0 0 0 0 uu Unimplemented or Reserved Figure 3 5 CRG Interrupt Enable Register CRGINT Read anytime Write anytime RTIE Real Time Interrupt Enable Bit 1 Interrupt will be requested whenever RTIF is set 0 Interrupt requests from RTI are disabled LOCKIE Lock Interrupt Enable Bit 1 Interrupt will be requested whenever LOCKIF is set 0 LOCK interrupt requests are disabled SCMIE Self Clock Mode Interrupt Enable Bit 1 Interrupt will be requested whenever SCMIF is set 0 SCM interrupt requests are disabled 3 3 6 CRG Clock Select Register CLKSEL This register controls CRG clock selection Refer to Figure 4 2 System Clocks Generator for more details on the effect of each bit Address Offset 05 7 6 5 4 3 2 1 0 la PLLSEL PSTP SYSWAI ROAWAI PLLWAI CWAI RTIWAI COPWAI RESET 0 0 0 0 0 0 0 0 ag Unimplemented or Reserved Figure 3 6 CRG Clock Select Register CLKSEL Read anytime Write refer to each bit for individual write conditions PLLSEL PLL Select Bit M MOTOROLA 19 CRG Block User Guide V04 05 Write anytime Writing a one when LOCK 0 and AUTO 1 or TRACK 0 and AUTO 0 has no effect This prevents the selection of an unstable PLLCLK as SYSCLK PLLSEL bit is cleared when the MCU enters Self Clock Mode Stop Mode or Wait Mode with PLLWAI bit set 1 System clocks are derived from PLLCLK Bus
9. ABA Den ceiver sake da Sa eter 37 4 4 3 GPU Stop MOSS NS ta hae Rae ey Naas ence ah re E 42 Section 5 Resets Slk CS TR CE Ramee oe ee ai ger a eee SERIE PAA 47 5 2 Description of Reset Operation 47 5 2 1 Clock Monitor Raser est IA tb ee SENS a De Se Bees 48 5 2 2 Computer Operating Properly Watchdog COP Reset 49 5 2 3 Power On Reset Low Voltage Reset 49 Section 6 Interrupts Bil General renes aean nn ne ng ae Me tn A 51 6 2 Description of Interrupt Operation 51 6 2 1 Real Time INGMUpE 2222042528232 ett Ot ets ae kA BAG ei dene 51 6 2 2 PEE OCR NICKEL sad Senet oe ee ae nern 51 6 2 3 Self Glock Mode Interrupt 51 4 M MOTOROLA CRG Block User Guide V04 05 List of Figures Figure 1 1 Figure 2 1 Figure 3 1 Figure 3 2 Figure 3 3 Figure 3 4 Figure 3 5 Figure 3 6 Figure 3 7 Figure 3 8 Figure 3 9 Figure 3 10 Figure 3 11 Figure 3 12 Figure 4 1 Figure 4 2 Figure 4 3 Figure 4 4 Figure 4 5 Figure 4 6 Figure 4 7 Figure 4 8 Figure 4 9 Figure 5 1 Figure 5 2 Figure 5 3 M MOTOROLA Block diagram of CRG eo Se esis ease cia ereignet 11 PLL Loop Filter Connections 13 CRG Synthesizer Register SYNR 16 CRG Reference Divider Register REFDV
10. Author Description of Changes 1 0 02 16 00 02 16 00 Initial Release 2 0 11 09 00 10 18 00 Initial SRS2 0 compliant release 2 01 Added RSBCK bit 2 02 3 00 Make the content SRS compliant usable as a customer document 03 03 01 03 03 01 03 22 01 Modified according to new Pierce Oscillator feature and different 10 May 10 May 2001 2001 PLLSEL bit write conditions V03 05 Corrected Cpe position in Colpitts Oscillator Connections diagram V03 06 V04 00 10 Oct 01 10 Oct 01 V04 01 5 Sept 01 5 Sept 01 1 Oct 01 1 Oct 01 Motorola internal spec tagging Added Low Voltage Reset feature Added Interrupts to Block Diagram Corrected LVRF flag 13 July 01 13 July 01 Minor corrections Enhanced Block diagram VREG POR Corrected register figure S0 uy On CRGINT to read and write 2 Aug 01 2 Aug 01 Enhanced Clock Quality Check Diagram Corrections in Reset section Improved description of exiting Wait and Pseudo Stop Mode 27 Aug OT 27 Aug 01 Enhanced SCME Bit description 21 Nov 01 21 Nov 01 description V04 02 22 Nov 01 22 Nov 01 Re Corrected LVRF flag description Removed document number from all pages except cover page Replaced fycomin by fscm V04 11 Mar 02 11 Mar 02 i aro are Added Bus Clock formulas close to PLLCLK formulas Spelling improvements Corrected in COPCTL register description RSBCK is write once V04 04 03 May 02
11. CRG will not wake up from Pseudo Stop Mode If any other interrupt source e g RTI triggers exit from Pseudo Stop Mode the MCU immediately continues with normal operation Because the PLL has been powered down during Stop Mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving Stop Mode The software must set the PLLSEL bit again in order to switch system and core clocks to the PLLCLK Table 4 3 summarizes the outcome of a clock loss while in Pseudo Stop Mode Table 4 3 Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions Clock failure gt No action clock loss not detected Clock failure gt CRG performs Clock Monitor Reset immediately 44 M MOTOROLA CRG Block User Guide V04 05 Table 4 3 Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions Clock Monitor failure gt Scenario 1 OSCCLK recovers prior to exiting Pseudo Stop Mode MCU remains in Pseudo Stop Mode VREG enabled PLL enabled SCM activated Start Clock Quality Check Set SCMIF interrupt flag Some time later OSCCLK recovers CM no longer indicates a failure 4096 OSCCLK cycles later Clock Quality Check indicates clock o k SCM deactivated PLL disabled VREG disabled MCU remains in Pseudo Stop Mode Some time later either a wakeup interrupt occurs no SCM interrupt Exit Pseudo Stop Mode using OSCCLK as system
12. Operating Properly watchdog Address Offset _08 7 6 5 4 3 2 1 0 WCOP RSBCK E CR2 CRI CRO RESET 0 5 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 9 CRG COP Control Register COPCTL Read anytime Write WCOP CR2 CRI CRO once in user mode anytime in special mode Write RSBCK once WCOP Window COP Mode Bit When set a write to the ARMCOP register must occur in the last 25 of the selected period A write during the first 75 of the selected period will reset the part As long as all writes occur during this window 55 can be written as often as desired Once AA is written after the 55 the time out logic restarts and the user must wait until the next window before writing to ARMCOP Table 3 3 shows the exact duration of this window for the seven available COP rates 1 Window COP operation 24 M MOTOROLA CRG Block User Guide V04 05 0 Normal COP operation RSBCK COP and RTI stop in Active BDM mode Bit 1 Stops the COP and RTI counters whenever the part is in Active BDM mode 0 Allows the COP and RTI to keep running in Active BDM mode CR 2 0 COP Watchdog Timer Rate select These bits select the COP time out rate see Table 3 3 The COP time out period is OSCCLK period divided by CR 2 0 value Writing a nonzero value to CR 2 0 enables the COP counter and starts the time out period A COP counter time out causes a system reset This can be avoided by per
13. Operation The oscillator output clock signal OSCCLK is fed through the reference programmable divider and is divided in a range of 1 to 16 REFDV 1 to output the REFERENCE clock The VCO output clock PLLCLK is fed back through the programmable loop divider and is divided in a range of 2 to 128 in increments of 2 x SYNR 1 to output the FEEDBACK clock See Figure 4 1 The phase detector then compares the FEEDBACK clock with the REFERENCE clock Correction pulses are generated based on the phase difference between the two signals The loop filter then slightly alters the DC voltage on the external filter capacitor connected to XFC pin based on the width and direction of the correction pulse The filter can make fast or slow corrections depending on its mode as described in the next subsection The values of the external filter network and the reference frequency determine the speed of the corrections and the stability of the PLL 4 2 1 2 Acquisition and Tracking Modes The lock detector compares the frequencies of the FEEDBACK clock and the REFERENCE clock Therefore the speed of the lock detector is directly proportional to the final reference frequency The circuit determines the mode of the PLL and the lock condition based on this comparison The PLL filter can be manually or automatically configured into one of two possible operating modes e Acquisition mode In acquisition mode the filter can make large frequency corrections to
14. 03 May 02 EXTAL signal description mentioning pull down resistor which is active in full stop mode 04 05 2 Aug 02 2 Aug 02 Removed oscillator specific information as separate Oscillator Block Guide is available now 2 M MOTOROLA CRG Block User Guide V04 05 Table of Contents Section 1 Introduction 11 ISI ar a hana vine re eB ihe AA 9 la 2 Featlifes spa redes done mon ade eee ani de eme panier Ce 9 1 3 MOSS O Operation oh o nes e an ei eee Aa e o el aie mA Mai 9 1 4 Block Diagramm Re RSS nt ani eee es ini 10 Section 2 Signal Description 2 OVGWICW 2 yr riot ea cdo et BULA hh 13 2 2 Detailed Signal Descriptions 13 2 2 1 VODPEE VOOR sane rosas 13 2 2 2 RIES ct ees eh O 13 2 2 3 RESET pple eh Sheers ee u S ea oa oh aN es as 13 Section 3 Memory Map and Registers Oo ONCE Wo toas pto toe tent as a nk AeA GE oe ee hehe ee e e a 15 32 iModule Memoy Map corta u san ae 15 33 Register Descriptions 15 3 3 1 CRG Synthesizer Register SYNR 15 3 3 2 CRG Reference Divider Register REFDV 16 3 3 3 Reserved Register GT FEG 2232332442222 2 Hs er dE DR eee ed 16 3 3 4 CRG Flags Register CRGFLG 17 3 3 5 CRG Interrupt Enable Register CRGINT 18 3 3 6 CRG Clock Select Register CLKSEL
15. 3 12 CRG COP Timer Arm Reset Register ARMCOP This register is used to restart the COP time out period 26 M MOTOROLA CRG Block User Guide V04 05 Address Offset 0B 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 W Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RESET 0 0 0 0 0 0 0 0 BE Unimplemented or Reserved Figure 3 12 ARMCOP Register Diagram Read always reads 00 Write anytime When the COP is disabled CR 2 0 000 writing to this register has no effect When the COP is enabled by setting CR 2 0 nonzero the following applies Writing any value other than 55 or AA causes a COP reset To restart the COP time out period you must write 55 followed by a write of AA Other instructions may be executed between these writes but the sequence 55 AA must be completed prior to COP end of time out period to avoid a COP reset Sequences of 55 writes or sequences of AA writes are allowed When the WCOP bit is set 55 and AA writes must be done in the last 25 of the selected time out period writing any value in the first 75 of the selected period will cause a COP reset M MOTOROLA 27 CRG Block User Guide V04 05 28 AR MOTOROLA CRG Block User Guide V04 05 Section 4 Functional Description 4 1 General This section gives detailed informations on the internal operation of the design 4 2 Functional Blocks 4 2 1 Phase Locked Loop PLL The PLL is used to run the M
16. CU from a different time base than the incoming OSCCLK For increased flexibility OSCCLK can be divided in a range of 1 to 16 to generate the reference frequency This offers a finer multiplication granularity The PLL can multiply this reference clock by a multiple of 2 4 6 126 128 based on the SYNR register SYNR 1 REFDV 1 PLLCLK 2x OSCCLK x CAUTION Although it is possible to set the two dividers to command a very high clock frequency do not exceed the specified bus frequency limit for the MCU If PLLSEL 1 Bus Clock PLLCLK 2 The PLL is a frequency generator that operates in either acquisition mode or tracking mode depending on the difference between the output frequency and the target frequency The PLL can change between acquisition and tracking modes either automatically or manually REFERENCE EXTAL REFDV lt 3 0 gt The VCO has a minimum operating frequency which corresponds to the self clock mode frequency fscm REDUCED y CONSUMPTION OSCCLK PROGRAMMABLE LOCK DETECTOR OSCILLATOR DIVIDER lt PDET XTAL PHASE DOWN CPUMP DETECTOR CRYSTAL MONITOR FEEDBACK REFERENCE VDDPLL VSSPLL VDDPLL LOOP PROGRAMMABLE DIVIDER LOOP a FILTER A SYN lt 5 0 gt supplied by E VDDPLL VSSPLL C VDD VSS Be Y Figure 4 1 PLL Functional Diagram M MOTOROLA 29 CRG Block User Guide V04 05 4 2 1 1 PLL
17. Clock PLLCLK 2 O System clocks are derived from OSCCLK Bus Clock OSCCLK 2 PSTP Pseudo Stop Bit Write anytime This bit controls the functionality of the oscillator during Stop Mode 1 Oscillator continues to run in Stop Mode Pseudo Stop The oscillator amplitude is reduced Refer to oscillator block description for availability of a reduced oscillator amplitude 0 Oscillator is disabled in Stop Mode NOTE Pseudo STOP allows for faster STOP recovery and reduces the mechanical stress and aging of the resonator in case of frequent STOP conditions at the expense of a slightly increased power consumption Lower oscillator amplitude exhibits lower power consumption but could have adverse effects during any Electro Magnetic Susceptibility EMS tests SYSWAI System clocks stop in Wait Mode Bit Write anytime 1 In Wait Mode the system clocks stop 0 In Wait Mode the system clocks continue to run NOTE RTI and COP are not affected by SYSWAI bit ROAWAI Reduced Oscillator Amplitude in Wait Mode Bit Refer to oscillator block description for availability of a reduced oscillator amplitude If no such feature exists in the oscillator block then setting this bit to one will not have any effect on power consumption Write anytime 1 Reduced oscillator amplitude in Wait Mode 0 Normal oscillator amplitude in Wait Mode NOTE Lower oscillator amplitude exhibits lower power consumption but could have adv
18. DOCUMENT NUMBER S12CRGV4 D CRG Block User Guide V04 05 Original Release Date 29 Feb 2000 Revised 2 August 2002 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA CRG Block User Guide V04 05 Revision History Version Revision Effective ati Number Date Date
19. E OF 54 PAGES 54 M MOTOROLA
20. Figure 5 3 show the power up sequence for cases when the RESET pin is tied to VDD and when the RESET pin is held low ug Clock Quality Check e RESET no Self Clock Mode Internal POR 128 SYSCLK Se ne Internal RESET 64 SYSCLK gt Figure 5 2 RESET pin tied to VDD by a pull up resistor M MOTOROLA 49 CRG Block User Guide V04 05 Ka a Clock Quality Check a RESET no Self Clock Mode by si Internal POR 128 SYSCLK gt aren Internal RESET 64 SYSCLK Figure 5 3 RESET pin held low externally 50 M MOTOROLA CRG Block User Guide V04 05 Section 6 Interrupts 6 1 General The interrupts reset vectors requested by the CRG are listed in Table 6 1 Refer to MCU specification for related vector addresses and priorities Table 6 1 CRG Interrupt Vectors Interrupt Source ce Local Enable Real time interrupt l bit CRGINT RTIE LOCK interrupt bit CRGINT LOCKIE SCM interrupt bit CRGINT SCMIE 6 2 Description of Interrupt Operation 6 2 1 Real Time Interrupt The CRG generates a real time interrupt when the selected interrupt time period elapses RTI interrupts are locally disabled by setting the RTIE bit to zero The real time interrupt flag RTIF is set tol when a timeout occurs and is cleared to 0 by writing a 1 to the RTIF bit The RTI continues to run during Pseudo Stop Mode if the PRE bit is set to 1 Th
21. LCLK as the source for system and core clocks PLLSEL 1 31 CRG Block User Guide V04 05 4 2 2 System Clocks Generator WAIT CWALSYSWAD STOP PLLCLK SYSCLK CLOCK PHASE GENERATOR Bus Clock WAIT RTIWAD STOP PSTP PRE RTI enable OSCCLK OSCILLATOR WAIT COPWAD STOP PSTP PCE COP enable COP Y Monitor WAIT SYSWAD STOP Oscillator Clock STOP PSTP Gating Oscillator Condition Clock running during Clock Gate Pseudo Stop Mode SA EEE En EMEA ES Ne AA AA a 4 Figure 4 2 System Clocks Generator The clock generator creates the clocks used in the MCU see Figure 4 2 The gating condition placed on top of the individual clock gates indicates the dependencies of different modes STOP WAIT and the setting of the respective configuration bits The peripheral modules use the Bus Clock Some peripheral modules also use the Oscillator Clock The memory blocks use the Bus Clock If the MCU enters Self Clock Mode see 4 3 2 Self Clock Mode Oscillator clock source is switched to PLLCLK running at its minimum frequency fscm The Bus Clock is used to generate the clock visible at the ECLK pin The Core Clock signal is the clock for the CPU The Core Clock is twice the Bus Clock as shown in Figure 4 3 But note that a CPU cycle corresponds to one Bus Clock PLL clock mode is selected with PLLSEL bit in the CLKSEL register When selected the PLL output cl
22. R W _01 CRG Reference Divider Register REFDV R W CRG Test Flags Register CTFLG RW 03 CRG Flags Register CRGFLG R W CRG Interrupt Enable Register CRGINT R W CRG Clock Select Register CLKSEL R W _06 CRG PLL Control Register PLLCTL R W _07 CRG RTI Control Register RTICTL R W CRG COP Control Register COPCTL R W _09 CRG Force and Bypass Test Register FORBYP R W _0A CRG Test Control Register CTCTL 3 R W CRG COP Arm Timer Reset ARMCOP R W NOTES 1 CTFLG is intended for factory test purposes only 2 FORBYP is intended for factory test purposes only 3 CTCTL is intended for factory test purposes only NOTE Register Address Base Address Address Offset where the Base Address is defined at the MCU level and the Address Offset is defined at the module level 3 3 Register Descriptions This section describes in address order all the CRG registers and their individual bits 3 3 1 CRG Synthesizer Register SYNR The SYNR register controls the multiplication factor of the PLL If the PLL is on the count in the loop divider SYNR register effectively multiplies up the PLL clock PLLCLK from the reference frequency by 2 x SYNR 1 PLLCLK will not be below the minimum VCO frequency fscm M MOTOROLA 15 CRG Block User Guide V04 05 SYNR 1 REFDV 1 NOTE IfPLLis selected PLLSEL 1 Bus Clock PLLCLK 2 Bus Clock must not exceed the maximum operating system frequency PLLCLK
23. alled osc ok Note that osc ok immediately terminates the current check window See Figure 4 4 as an example NOTES 1 VCO clock cycles are generated by the PLL when running at minimum frequency fscm M MOTOROLA 33 CRG Block User Guide V04 05 VCO clock check window ap 1 2 3 49999 50000 lol se ele 12345 4096 OSCCLK HUL ir W39 osc ok Figure 4 4 Check Window Example The Sequence for clock quality check is shown in Figure 4 5 34 Clock OK POR NE exit full stop Clock Monitor Reset check window Switch to OSCCLK Exit SCM Figure 4 5 Sequence for Clock Quality Check M MOTOROLA CRG Block User Guide V04 05 NOTE Remember that in parallel to additional actions caused by Self Clock Mode or Clock Monitor Reset handling the clock quality checker continues to check the OSCCLK signal NOTE The Clock Quality Checker enables the PLL and the voltage regulator VREG anytime a clock check has to be performed An ongoing clock quality check could also cause a running PLL fscm and an active VREG during Pseudo Stop Mode or Wait Mode 4 2 5 Computer Operating Properly Watchdog COP WAIT COPWAD STOP PSTP PCE COP enable OSCCLK A CR 2 0 0 0 0 gating condition Clock Gate COP TIMEOUT Figure 4 6 Clock Chain for COP The COP free running watchdog timer enables the user to check that a p
24. clock SYSCLK Continue normal operation or an External Reset is applied Exit Pseudo Stop Mode using OSCCLK as system clock Start reset sequence Scenario 2 OSCCLK does not recover prior to exiting Pseudo Stop Mode MCU remains in Pseudo Stop Mode VREG enabled PLL enabled SCM activated Start Clock Quality Check Set SCMIF interrupt flag Keep performing Clock Quality Checks could continue infinitely while in Pseudo Stop Mode Some time later either a wakeup interrupt occurs no SCM interrupt Exit Pseudo Stop Mode in SCM using PLL clock fscm as system clock Continue to perform additional Clock Quality Checks until OSCCLK is o k again or an External RESET is applied Exit Pseudo Stop Mode in SCM using PLL clock fscm as system clock Start reset sequence Continue to perform additional Clock Quality Checks until OSCCLK is o k again M MOTOROLA 45 CRG Block User Guide V04 05 Table 4 3 Outcome of Clock Loss in Pseudo Stop Mode CME SCME SCMIE CRG Actions Clock failure gt VREG enabled PLL enabled SCM activated Start Clock Quality Check SCMIF set SCMIF generates Self Clock Mode wakeup interrupt Exit Pseudo Stop Mode in SCM using PLL clock fscm as system clock Continue to perform a additional Clock Quality Checks until OSCCLK is o k again 4 4 3 2 Wake up from Full Stop PSTP 0
25. ctable disabling of clocks during Wait Mode for reduced power consumption Computer Operating Properly COP watchdog timer with time out clear window System Reset generation from the following possible sources Power on reset Low voltage reset Refer to device specification for availability of this feature COP reset Loss of clock reset External pin reset Real Time Interrupt RTI Modes of Operation This subsection lists and briefly describes all operating modes supported by the CRG M MOTOROLA Run Mode CRG Block User Guide V04 05 1 4 All functional parts of the CRG are running during normal Run Mode If RTI or COP functionality is required the individual bits of the associated rate select registers COPCTL RTICTL have to be set to a non zero value Wait Mode This mode allows to disable the system and core clocks depending on the configuration of the individual bits in the CLKSEL register Stop Mode Depending on the setting of the PSTP bit Stop Mode can be differentiated between Full Stop Mode PSTP 0 and Pseudo Stop Mode PSTP 1 Full Stop Mode The oscillator is disabled and thus all system and core clocks are stopped The COP and the RTI remain frozen Pseudo Stop Mode The oscillator continues to run and most of the system and core clocks are stopped If the respective enable bits are set the COP and RTI will continue to run else they remain frozen Self Clock Mode Se
26. cted 0 Low bandwidth filter is selected PRE RTI Enable during Pseudo Stop Bit PRE enables the RTI during Pseudo Stop Mode Write anytime 1 RTI continues running during Pseudo Stop Mode 0 RTI stops running during Pseudo Stop Mode NOTE Ifthe PRE bit is cleared the RTI dividers will go static while Pseudo Stop Mode is active The RTI dividers will not initialize like in Wait Mode with RTIWAI bit set PCE COP Enable during Pseudo Stop Bit PCE enables the COP during Pseudo Stop Mode Write anytime 1 COP continues running during Pseudo Stop Mode 0 COP stops running during Pseudo Stop Mode NOTE Ifthe PCE bit is cleared the COP dividers will go static while Pseudo Stop Mode is active The COP dividers will not initialize like in Wait Mode with COPWAI bit set SCME Self Clock Mode Enable Bit Normal modes Write once Special modes Write anytime SCME can not be cleared while operating in Self Clock Mode SCM 1 0 Detection of crystal clock failure causes clock monitor reset see 5 2 1 Clock Monitor Reset 1 Detection of crystal clock failure forces the MCU in Self Clock Mode see 4 3 2 Self Clock Mode 22 M MOTOROLA CRG Block User Guide V04 05 3 3 8 CRG RTI Control Register RTICTL This register selects the timeout period for the Real Time Interrupt Address Offset 07 7 6 5 4 3 2 1 0 ti RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTRO RESET 0 0 0 0 0 0 0 0 CS Unimplemented or Reserved F
27. ending on the application The following conditions apply when the PLL is in automatic bandwidth control mode AUTO 1 e The TRACK bit is a read only indicator of the mode of the filter 30 M MOTOROLA CRG Block User Guide V04 05 The TRACK bit is set when the VCO frequency is within a certain tolerance A and is clear when the VCO frequency is out of a certain tolerance The LOCK bit is a read only indicator of the locked state of the PLL The LOCK bit is set when the VCO frequency is within a certain tolerance Ay ck and is cleared when the VCO frequency is out of a certain tolerance A yn CPU interrupts can occur if enabled LOCKIE 1 when the lock condition changes toggling the LOCK bit The PLL can also operate in manual mode AUTO 0 Manual mode is used by systems that do not require an indicator of the lock condition for proper operation Such systems typically operate well below the maximum system frequency f and require fast start up The following conditions apply when in manual mode M MOTOROLA ACQ is a writable control bit that controls the mode of the filter Before turning on the PLL in manual mode the ACQ bit should be asserted to configure the filter in acquisition mode After turning on the PLL by setting the PLLON bit software must wait a given time tac before entering tracking mode ACQ 0 After entering tracking mode software must wait a given time t before selecting the PL
28. erse effects during any Electro Magnetic Susceptibility EMS tests PLLWAI PLL stops in Wait Mode Bit Write anytime If PLLW Al is set the CRG will clear the PLLSEL bit before entering Wait Mode The PLLON bit remains set during Wait Mode but the PLL is powered down Upon exiting Wait Mode the PLLSEL bit has to be set manually if PLL clock is required While the PLLWAI bit is set the AUTO bit is set to 1 in order to allow the PLL to automatically lock on the selected target frequency after exiting Wait Mode 20 M MOTOROLA CRG Block User Guide V04 05 1 PLL stops in Wait Mode 0 PLL keeps running in Wait Mode CWAI Core stops in Wait Mode Bit Write anytime 1 Core clock stops in Wait Mode 0 Core clock keeps running in Wait Mode RTIWAI RTI stops in Wait Mode Bit Write anytime 1 RTI stops and initializes the RTI dividers whenever the part goes into Wait Mode O RTI keeps running in Wait Mode COPWAI COP stops in Wait Mode Bit Normal modes Write once Special modes Write anytime 1 COP stops and initializes the COP dividers whenever the part goes into Wait Mode 0 COP keeps running in Wait Mode 3 3 7 CRG PLL Control Register PLLCTL This register controls the PLL functionality Address Offset 06 7 6 5 4 3 2 1 0 gt CME PLLON AUTO ACQ PRE PCE SCME RESET 1 1 1 1 0 0 0 1 Bi Unimplemented or Reserved Figure 3 7 CRG PLL Control Register PLLCTL Read anytime Write refer
29. etailed Signal Descriptions 2 2 1 VDDPLL VSSPLL These pins provides operating voltage VDDPLL and ground VSSPLL for the PLL circuitry This allows the supply voltage to the PLL to be independently bypassed Even if PLL usage is not required VDDPLL and VSSPLL must be connected to properly 2 2 2 XFC A passive external loop filter must be placed on the XFC pin The filter is a second order low pass filter to eliminate the VCO input ripple The value of the external filter network and the reference frequency determines the speed of the corrections and the stability of the PLL Refer to device specification for calculation of PLL Loop Filter XFC components If PLL usage is not required the XFC pin must be tied to VDDPLL VDDPLL ER Cs ale MCU 0 Rs XFC Figure 2 1 PLL Loop Filter Connections Cp 2 2 3 RESET RESET is an active low bidirectional reset pin As an input it initializes the MCU asynchronously to a known start up state As an open drain output it indicates that an system reset internal to MCU has been triggered M MOTOROLA 13 CRG Block User Guide V04 05 14 AR MOTOROLA CRG Block User Guide V04 05 Section 3 Memory Map and Registers 3 1 Overview This section provides a detailed description of all registers accessible in the CRG 3 2 Module Memory Map Table 3 1 gives an overview on all CRG registers Table 3 1 CRG Memory Map Address _00 CRG Synthesizer Register SYNR
30. etching the Clock Monitor Reset vector 5 2 2 Computer Operating Properly Watchdog COP Reset When COP is enabled the CRG expects sequential write of 55 and AA in this order to the ARMCOP register during the selected time out period Once this is done the COP time out period restarts If the program fails to do this the CRG will generate a reset Also if any value other than 55 or AA is written the CRG immediately generates a reset In case windowed COP operation is enabled writes 55 or AA to the ARMCOP register must occur in the last 25 of the selected time out period A premature write the CRG will immediately generate a reset As soon as the reset sequence is completed the reset generator checks the reset condition If no clock monitor failure is indicated and the latched state of the COP timeout is true processing begins by fetching the COP vector 5 2 3 Power On Reset Low Voltage Reset The on chip voltage regulator detects when VDD to the MCU has reached a certain level and asserts power on reset or low voltage reset or both As soon as a power on reset or low voltage reset is triggered the CRG performs a quality check on the incoming clock signal As soon as clock quality check indicates a valid Oscillator Clock signal the reset sequence starts using the Oscillator clock If after 50 check windows the clock quality check indicated a non valid Oscillator Clock the reset sequence starts using Self Clock Mode Figure 5 2 and
31. hanges This flag can only be cleared by writing a 1 Writing a O has no effect If enabled LOCKIE 1 LOCKIF causes an interrupt request 1 LOCK bit has changed 0 No change in LOCK bit LOCK Lock Status Bit LOCK reflects the current state of PLL lock condition This bit is cleared in Self Clock Mode Writes have no effect 1 PLL VCO is within the desired tolerance of the target frequency 0 PLL VCO is not within the desired tolerance of the target frequency TRACK Track Status Bit TRACK reflects the current state of PLL track condition This bit is cleared in Self Clock Mode Writes have no effect 1 Tracking mode status 0 Acquisition mode status SCMIF Self Clock Mode Interrupt Flag SCMIF is set to 1 when SCM status bit changes This flag can only be cleared by writing a 1 Writing a0 has no effect If enabled SCMIE 1 SCMIF causes an interrupt request 1 SCM bit has changed 0 No change in SCM bit SCM Self Clock Mode Status Bit SCM reflects the current clocking mode Writes have no effect 1 MCU is operating in Self Clock Mode with OSCCLK in an unknown state All clocks are derived from PLLCLK running at its minimum frequency fsem 0 MCU is operating normally with OSCCLK available 3 3 5 CRG Interrupt Enable Register CRGINT This register enables CRG interrupt requests 18 M MOTOROLA CRG Block User Guide V04 05 Address Offset 04 7 6 5 4
32. ibes how to reset the CRG and how the CRG itself controls the reset of the MCU It explains all special reset requirements Since the reset generator for the MCU is part of the CRG this section also describes all automatic actions that occur during or as a result of individual reset conditions The reset values of registers and signals are provided in Section 3 Memory Map and Registers All reset sources are listed in Table 5 1 Refer to MCU specification for related vector addresses and priorities Table 5 1Reset Summary Reset Source Local Enable Power on Reset None Low Voltage Reset None External Reset None Clock Monitor Reset PLLCTL CME 1 SCME 0 COP Watchdog Reset COPCTL CR 2 0 nonzero 5 2 Description of Reset Operation The reset sequence is initiated by any of the following events Low level is detected at the RESET pin External Reset e Power on is detected e Low voltage is detected e COP watchdog times out e Clock monitor failure is detected and Self Clock Mode was disabled SCME 0 Upon detection of any reset event an internal circuit drives the RESET pin low for 128 SYSCLK cycles see Figure 5 1 Since entry into reset is asynchronous it does not require a running SYSCLK However the internal reset circuit of the CRG cannot sequence out of current reset condition without a running SYSCLK The number of 128 SYSCLK cycles might be increased by n 3 to 6 additional SYSCLK cycles depending on
33. igure 3 8 CRG RTI Control Register RTICTL Read anytime Write anytime NOTE A write to this register initializes the RTI counter RTR 6 4 Real Time Interrupt Prescale Rate Select Bits These bits select the prescale rate for the RTI See Table 3 2 RTR 3 0 Real Time Interrupt Modulus Counter Select Bits These bits select the modulus counter target value to provide additional granularity Table 3 2 shows all possible divide values selectable by the RTICTL register The source clock for the RTI is OSCCLK Table 3 2 RTI Frequency Divide Rates RTR 3 0 RTR 6 4 0000 1 0001 2 0010 3 0011 4 0100 5 0101 6 0110 7 0111 8 M MOTOROLA 23 CRG Block User Guide V04 05 Table 3 2 RTI Frequency Divide Rates RTR 3 0 RTR 6 4 1000 9 9x210 9x211 9x212 9x213 9x214 9x215 9x216 1001 10 10x210 10x211 10x212 10x218 10x214 1010 11 11x210 11x2 11x212 11x218 11x214 10x215 11x215 10x216 11x216 1011 12 12x210 12x211 12x212 12x213 12x214 1100 13 12x215 12x216 1101 14 1110 15 1111 16 OFF 16x210 16x2 16x212 16x213 16x214 16x215 16x216 Denotes the default value out of reset This value should be used to disable the RTI to ensure future backwards com patibility 3 3 9 CRG COP Control Register COPCTL This register controls the COP Computer
34. iodically before time out reinitializing the COP counter via the ARMCOP register Table 3 3 COP Watchdog Rates OSCCLK CR2 CR1 CRO cycles to time out De do do maga 0 0 1 214 0 1 0 2 16 0 1 1 2 18 1 0 0 2 20 1 0 1 2 22 1 1 0 2 23 1 1 1 2 24 NOTES 1 OSCCLK cycles are referenced from the previous COP time out reset writing 55 AA to the ARMCOP register 3 3 10 Reserved Register FORBYP NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in special modes can alter the CRG s functionality M MOTOROLA 25 CRG Block User Guide V04 05 Address Offset 09 7 6 5 4 3 2 1 0 R 0 0 0 0 0 0 0 0 ga RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 10 Reserved Register FORBYP Read always read 00 except in special modes Write only in special modes 3 3 11 Reserved Register CTCTL NOTE This reserved register is designed for factory test purposes only and is not intended for general user access Writing to this register when in special test modes can alter the CRG s functionality Address Offset 0A 7 6 5 4 3 2 1 0 R 1 0 0 0 0 0 0 0 W RESET 0 0 0 0 0 0 0 0 Unimplemented or Reserved Figure 3 11 Reserved Register CTCTL Read always read 80 except in special modes Write only in special modes 3
35. is feature can be used for periodic wakeup from Pseudo Stop if the RTI interrupt is enabled 6 2 2 PLL Lock Interrupt The CRG generates a PLL Lock interrupt when the LOCK condition of the PLL has changed either from a locked state to an unlocked state or vice versa Lock interrupts are locally disabled by setting the LOCKIE bit to zero The PLL Lock interrupt flag LOCKIF is set tol when the LOCK condition has changed and is cleared to O by writing a 1 to the LOCKIF bit 6 2 3 Self Clock Mode Interrupt The CRG generates a Self Clock Mode interrupt when the SCM condition of the system has changed either entered or exited Self Clock Mode SCM conditions can only change if the Self Clock Mode enable bit SCME is set to 1 SCM conditions are caused by a failing clock quality check after power on reset POR or low voltage reset LVR or recovery from Full Stop Mode PSTP 0 or Clock Monitor failure For details on the clock quality check refer to 4 2 4 Clock Quality Checker If the clock monitor is enabled CME 1 a loss of external clock will also cause a SCM condition SCME 1 M MOTOROLA 51 CRG Block User Guide V04 05 SCM interrupts are locally disabled by setting the SCMIE bit to zero The SCM interrupt flag SCMIF is set tol when the SCM condition has changed and is cleared to 0 by writing a 1 to the SCMIF bit 52 M MOTOROLA AR MOTOROLA CRG Block User Guide V04 05 53 CRG Block User Guide V04 05 FINAL PAG
36. lf Clock Mode will be entered if the Clock Monitor Enable Bit CME and the Self Clock Mode Enable Bit SCME are both asserted and the clock monitor in the oscillator block detects a loss of clock As soon as Self Clock Mode is entered the CRG starts to perform a clock quality check Self Clock Mode remains active until the clock quality check indicates that the required quality of the incoming clock signal is met frequency and amplitude Self Clock Mode should be used for safety purposes only It provides reduced functionality to the MCU in case a loss of clock is causing severe system conditions Block Diagram Figure 1 1 shows a block diagram of the CRG 10 M MOTOROLA CRG Block User Guide V04 05 Voltage Power on Reset Regulator ovvotse hes X XCLKS s2EXTAL Oscil lator 7 XTAL ZA XEC VDDPLL VSSPLL M MOTOROLA Reset System Reset Generator os Te CM fail OSCCLK Clock Quality Checker Bus Clock El Core Clock El Oscillator Clock Clock and Reset Real Time Interrupt Control PLL Lock Interrupt COP timeout d PLL Self Clock Mode Interrupt 1 Refer to device specification for availability of the low voltage reset feature Figure 1 1 Block diagram of CRG 11 CRG Block User Guide V04 05 12 AR MOTOROLA CRG Block User Guide V04 05 Section 2 Signal Description 2 1 Overview This section lists and describes the signals that connect off chip 2 2 D
37. lock Mode NOTE In order to detect a potential clock loss the CME bit should be always enabled CME 1 If CME bit is disabled and the MCU is configured to run on PLL clock PLLCLK a loss of external clock OSCCLK will not be detected and will cause the system clock to drift towards the VCO s minimum frequency fscy As soon as the external clock is available again the system clock ramps up to its PLL target frequency If the MCU is running on external clock any loss of clock will cause the system to go Static 4 4 Low Power Options This section summarizes the low power options available in the CRG 4 4 1 Run Mode The RTI can be stopped by setting the associated rate select bits to zero The COP can be stopped by setting the associated rate select bits to zero 4 4 2 Wait Mode The WAI instruction puts the MCU in a low power consumption stand by mode depending on setting of the individual bits in the CLKSEL register All individual Wait Mode configuration bits can be superposed This provides enhanced granularity in reducing the level of power consumption during Wait M MOTOROLA 37 CRG Block User Guide V04 05 Mode Table 4 1 lists the individual configuration bits and the parts of the MCU that are affected in Wait Mode Table 4 1 MCU configuration during Wait Mode PLLWAI CWAI SYSWAI RTIWAI COPWAI ROAWAI PLL stopped 7 System stopped E An 7 COP stopped E NOTES 1 Refer to oscillator block descriptio
38. ltage regulator to enter their individual powersaving modes if available This is the main difference between Pseudo Stop Mode and Wait Mode After executing the STOP instruction the core requests the CRG to switch the MCU into Stop Mode If the PLLSEL bit is still set when entering Stop Mode the CRG will switch the system and core clocks to OSCCLK by clearing the PLLSEL bit Then the CRG disables the PLL disables the core clock and finally disables the remaining system clocks As soon as all clocks are switched off Stop Mode is active If Pseudo Stop Mode PSTP 1 is entered from Self Clock Mode the CRG will continue to check the clock quality until clock check is successful The PLL and the voltage regulator VREG will remain enabled If Full Stop Mode PSTP 0 is entered from Self Clock Mode an ongoing clock quality check will be stopped A complete timeout window check will be started when Stop Mode is left again Wake up from Stop Mode also depends on the setting of the PSTP bit 42 M MOTOROLA CRG Block User Guide V04 05 Core req s Stop Mode Clear PLLSEL Disable PLL Wait Mode left Exit Stop A due to external reset Enter ext RESET SS Stop Mode no Exit Stop w CMRESET Exit Stop w CMRESET Generate ALAS Yy v y SCM Interrupt Exit Exit Wakeup from Stop Exit Stop Mode Stop Mode Stop Mode
39. n for availability of a reduced oscillator amplitude After executing the WAI instruction the core requests the CRG to switch MCU into Wait Mode The CRG then checks whether the PLLWAI CWAI and SYSWAI bits are asserted see Figure 4 8 Wait Mode Entry Exit Sequence Depending on the configuration the CRG switches the system and core clocks to OSCCLK by clearing the PLLSEL bit disables the PLL disables the core clocks and finally disables the remaining system clocks As soon as all clocks are switched off Wait Mode is active 38 M MOTOROLA CRG Block User Guide V04 05 Core req s Wait Mode Clear WAI or Disable PLL YSWAI 1 2 Disable core clocks no Disable system clocks Enter Wait Mode Wait Mode left due to external reset 1 ES Exit Wait w CMRESET Generate Ki yes SCM Interrupt v Wakeup from Wait Exit Wait Mode Continue w normal OP Figure 4 8 Wait Mode Entry Exit Sequence There are five different scenarios for the CRG to restart the MCU from Wait Mode External Reset M MOTOROLA 39 CRG Block User Guide V04 05 e Clock Monitor Reset e COP Reset e Self Clock Mode Interrupt e Real Time Interrupt RTD If the MCU gets an external reset during Wait Mode active the CRG asynchronously restores all configuration bits in the register space to its default settings and starts the reset genera
40. ng Y 7 ZA CRG drives RESET pin low RESET T pin released fr SYSCLK ZETA Z anan nan non iasencycles cycles 64 cycles cycles we ith n being possibly u possibly syscik Mn3 max6 RESET not Y cies depending driven low running ma internal externally synchronization delay 5 2 1 Clock Monitor Reset The CRG generates a Clock Monitor Reset in case all of the following conditions are true e Clock monitor is enabled CME 1 Loss of clock is detected e Self Clock Mode is disabled SCME 0 The reset event asynchronously forces the configuration registers to their default settings see Section Section 3 Memory Map and Registers In detail the CME and the SCME are reset to logical 1 which doesn t change the state of the CME bit because it has already been set As a consequence the CRG 48 M MOTOROLA CRG Block User Guide V04 05 immediately enters Self Clock Mode and starts its internal reset sequence In parallel the clock quality check starts As soon as clock quality check indicates a valid Oscillator Clock the CRG switches to OSCCLK and leaves Self Clock Mode Since the clock quality checker is running in parallel to the reset generator the CRG may leave Self Clock Mode while still completing the internal reset sequence When the reset sequence is finished the CRG checks the internally latched state of the clock monitor fail circuit If a clock monitor fail is indicated processing begins by f
41. ock drives SYSCLK for the main system including the CPU and peripherals The PLL cannot be turned off by clearing the PLLON bit if the PLL clock is selected When PLLSEL is changed it takes a maximum 32 M MOTOROLA CRG Block User Guide V04 05 of 4 OSCCLK plus 4 PLLCLK cycles to make the transition During the transition all clocks freeze and CPU activity ceases BUS CLOCK ECLK Figure 4 3 Core Clock and Bus Clock relationship 4 2 3 Clock Monitor CM If no OSCCLK edges are detected within a certain time the clock monitor within the oscillator block generates a clock monitor fail event The CRG then asserts self clock mode or generates a system reset depending on the state of SCME bit If the clock monitor is disabled or the presence of clocks is detected no failure is indicated by the oscillator block The clock monitor function is enabled disabled by the CME control bit 4 2 4 Clock Quality Checker The clock monitor performs a coarse check on the incoming clock signal The clock quality checker provides a more accurate check in addition to the clock monitor A clock quality check is triggered by any of the following events e Power on reset POR e Low voltage reset LVR e Wake up from Full Stop Mode exit full stop e Clock Monitor fail indication CM fail A time window of 50000 VCO clock cycles is called check window A number greater equal than 4096 rising OSCCLK edges within a check window 1s c
42. rogram is running and sequencing properly The COP is disabled out of reset When the COP is being used software is responsible for keeping the COP from timing out If the COP times out it is an indication that the software is no longer being executed in the intended sequence thus a system reset is initiated see 5 2 2 Computer Operating Properly Watchdog COP Reset The COP runs with a gated OSCCLK see Figure 4 6 Clock Chain for COP Three control bits in the COPCTL register allow selection of seven COP time out periods When COP is enabled the program must write 55 and AA in this order to the ARMCOP register during the selected time out period Once this is done the COP time out period is restarted If the program NOTES 1 A Clock Monitor Reset will always set the SCME bit to logical 1 35 M MOTOROLA CRG Block User Guide V04 05 fails to do this and the COP times out the part will reset Also if any value other than 55 or AA is written the part is immediately reset Windowed COP operation is enabled by setting WCOP in the COPCTL register In this mode writes to the ARMCOP register to clear the COP timer must occur in the last 25 of the selected time out period A premature write will immediately reset the part If PCE bit is set the COP will continue to run in Pseudo Stop Mode 4 2 6 Real Time Interrupt RTI The RTI can be used to generate a hardware interrupt at a fixed periodic rate If enabled by setting
43. ster CRGFLG This register provides CRG status bits and flags Address Offset 03 7 6 5 4 3 2 1 0 E RTIF PORF LVRF LOCKIF BUGA JAG SCMIF RESET 0 0 0 0 0 0 Unimplemented or Reserved NOTES 1 PORF is set to 1 when a power on reset occurs Unaffected by system reset 2 LVRF is set to 1 when a low voltage reset occurs Unaffected by system reset Figure 3 4 CRG Flags Register CRGFLG Read anytime Write refer to each bit for individual write conditions RTIF Real Time Interrupt Flag RTIF is set to 1 at the end of the RTI period This flag can only be cleared by writing a 1 Writing a 0 has no effect If enabled RTIE 1 RTIF causes an interrupt request 1 RTI time out has occurred 0 RTI time out has not yet occurred PORF Power on Reset Flag M MOTOROLA 17 CRG Block User Guide V04 05 PORF is set to 1 when a power on reset occurs This flag can only be cleared by writing a 1 Writing a O has no effect 1 Power on reset has occurred 0 Power on reset has not occurred LVRF Low Voltage Reset Flag If low voltage reset feature is not available see device specification LVRF always reads 0 LVRF is set to 1 when a low voltage reset occurs This flag can only be cleared by writing a 1 Writing a O has no effect 1 Low voltage reset has occurred 0 Low voltage reset has not occurred LOCKIF PLL Lock Interrupt Flag LOCKIF is set to 1 when LOCK status bit c
44. the VCO This mode is used at PLL start up or when the PLL has suffered a severe noise hit and the VCO frequency is far off the desired frequency When in acquisition mode the TRACK status bit is cleared in the CRGFLG register e Tracking mode In tracking mode the filter makes only small corrections to the frequency of the VCO PLL jitter is much lower in tracking mode but the response to noise is also slower The PLL enters tracking mode when the VCO frequency is nearly correct and the TRACK bit is set in the CRGFLG register The PLL can change the bandwidth or operational mode of the loop filter manually or automatically In automatic bandwidth control mode AUTO 1 the lock detector automatically switches between acquisition and tracking modes Automatic bandwidth control mode also is used to determine when the PLL clock PLLCLK is safe to use as the source for the system and core clocks If PLL LOCK interrupt requests are enabled the software can wait for an interrupt request and then check the LOCK bit If CPU interrupts are disabled software can poll the LOCK bit continuously during PLL start up usually or at periodic intervals In either case only when the LOCK bit is set is the PLLCLK clock safe to use as the source for the system and core clocks If the PLL is selected as the source for the system and core clocks and the LOCK bit is clear the PLL has suffered a severe noise hit and the software must take appropriate action dep
45. the internal synchronization latency After 128 n SYSCLK cycles the RESET pin is released The reset generator of the CRG waits for additional 64 SYSCLK cycles and then samples the RESET pin to determine the originating source Table 5 2 shows which vector will be fetched Table 5 2 Reset Vector Selection sampled RESET pin Clock Monitor COP Reset Reset pending pending Vector fetch 64 cycles after release 1 0 POR LVR External Reset 1 1 Clock Monitor Reset 1 0 1 COP Reset M MOTOROLA 47 CRG Block User Guide V04 05 Table 5 2 Reset Vector Selection sampled RESET pin 64 cycles after release COP Reset pending Clock Monitor Reset pending Vector fetch POR LVR External Reset with rise of RESET pin 0 X X NOTE External circuitry connected to the RESET pin should not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one within 64 SYSCLK cycles after the low drive is released The internal reset of the MCU remains asserted while the reset generator completes the 192 SYSCLK long reset sequence The reset generator circuitry always makes sure the internal reset is deasserted synchronously after completion of the 192 SYSCLK cycles In case the RESET pin is externally driven low for more than these 192 SYSCLK cycles External Reset the internal reset remains asserted too Figure 5 1 RESET Timi
46. to each bit for individual write conditions CME Clock Monitor Enable Bit CME enables the clock monitor Write anytime except when SCM 1 1 Clock monitor is enabled Slow or stopped clocks will cause a clock monitor reset sequence or Self Clock Mode 0 Clock monitor is disabled NOTE Operating with CME 0 will not detect any loss of clock In case of poor clock quality this could cause unpredictable operation of the MCU M MOTOROLA 21 CRG Block User Guide V04 05 In Stop Mode PSTP 0 the clock monitor is disabled independently of the CME bit setting and any loss of clock will not be detected PLLON Phase Lock Loop On Bit PLLON turns on the PLL circuitry In Self Clock Mode the PLL is turned on but the PLLON bit reads the last latched value Write anytime except when PLLSEL 1 1 PLL is turned on If AUTO bit is set the PLL will lock automatically 0 PLL is turned off AUTO Automatic Bandwidth Control Bit AUTO selects either the high bandwidth acquisition mode or the low bandwidth tracking mode depending on how close to the desired frequency the VCO is running Write anytime except when PLLWAI 1 because PLLW AT sets the AUTO bit to 1 1 Automatic Mode Control is enabled and ACQ bit has no effect 0 Automatic Mode Control is disabled and the PLL is under software control using ACQ bit ACQ Acquisition Bit Write anytime If AUTO 1 this bit has no effect 1 High bandwidth filter is sele
47. tor After completing the reset sequence processing begins by fetching the normal reset vector Wait Mode is left and the MCU is in Run Mode again If the clock monitor is enabled CME 1 the MCU is able to leave Wait Mode when loss of oscillator external clock is detected by a clock monitor fail If the SCME bit is not asserted the CRG generates a clock monitor fail reset CMRESET The CRG s behavior for CMRESET is the same compared to external reset but another reset vector is fetched after completion of the reset sequence If the SCME bit is asserted the CRG generates a SCM interrupt if enabled SCMIE 1 After generating the interrupt the CRG enters Self Clock Mode and starts the clock quality checker see 4 2 4 Clock Quality Checker Then the MCU continues with normal operation If the SCM interrupt is blocked by SCMIE 0 the SCMIF flag will be asserted and clock quality checks will be performed but the MCU will not wake up from Wait Mode If any other interrupt source e g RTI triggers exit from Wait Mode the MCU immediately continues with normal operation If the PLL has been powered down during Wait Mode the PLLSEL bit is cleared and the MCU runs on OSCCLK after leaving Wait Mode The software must manually set the PLLSEL bit again in order to switch system and core clocks to the PLLCLK If Wait Mode is entered from Self Clock Mode the CRG will continue to check the clock quality until clock check is successful The PLL and voltage regula
48. tor VREG will remain enabled Table 4 2 summarizes the outcome of a clock loss while in Wait Mode Table 4 2 Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions Clock failure gt No action clock loss not detected Clock failure gt CRG performs Clock Monitor Reset immediately 40 M MOTOROLA CRG Block User Guide V04 05 Table 4 2 Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions Clock failure gt Scenario 1 OSCCLK recovers prior to exiting Wait Mode MCU remains in Wait Mode VREG enabled PLL enabled SCM activated Start Clock Quality Check Set SCMIF interrupt flag Some time later OSCCLK recovers CM no longer indicates a failure 4096 OSCCLK cycles later Clock Quality Check indicates clock o k SCM deactivated PLL disabled depending on PLLWAI VREG remains enabled never gets disabled in Wait Mode MCU remains in Wait Mode Some time later either a wakeup interrupt occurs no SCM interrupt Exit Wait Mode using OSCCLK as system clock SYSCLK Continue normal operation or an External Reset is applied 0 Exit Wait Mode using OSCCLK as system clock Start reset sequence Scenario 2 OSCCLK does not recover prior to exiting Wait Mode MCU remains in Wait Mode VREG enabled PLL enabled SCM activated Start Clock Quality Check Set SCMIF interr
49. upt flag Keep performing Clock Quality Checks could continue infinitely while in Wait Mode Some time later either a wakeup interrupt occurs no SCM interrupt Exit Wait Mode in SCM using PLL clock fscm as system clock Continue to perform additional Clock Quality Checks until OSCCLK is o k again or an External RESET is applied Exit Wait Mode in SCM using PLL clock fscm as system clock Start reset sequence Continue to perform additional Clock Quality Checks until OSCCLK is o k again M MOTOROLA 41 CRG Block User Guide V04 05 Table 4 2 Outcome of Clock Loss in Wait Mode CME SCME SCMIE CRG Actions Clock failure gt VREG enabled PLL enabled SCM activated Start Clock Quality Check SCMIF set SCMIF generates Self Clock Mode wakeup interrupt Exit Wait Mode in SCM using PLL clock fscm as system clock Continue to perform a additional Clock Quality Checks until OSCCLK is o k again 4 4 3 CPU Stop Mode All clocks are stopped in STOP mode dependent of the setting of the PCE PRE and PSTP bit The oscillator is disabled in STOP mode unless the PSTP bit is set All counters and dividers remain frozen but do not initialize If the PRE or PCE bits are set the RTI or COP continues to run in Pseudo Stop Mode In addition to disabling system and core clocks the CRG requests other functional units of the MCU e g vo
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