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TQMa53 User's Manual

1. 3 2 14 Overview eere lt 99 RR 3 2142 Module carrier board Power Up 27 3 2 14 3 Ee TAT LA 27 TABLE OF CONTENTS continued 3 3 3 3 1 3 3 2 3 3 3 4 1 4 2 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 3 5 6 1 6 2 6 3 6 4 6 5 6 6 6 6 1 6 6 2 6 7 6 8 7 1 7 User s Manual TOMa53 UM 200 1 2013 TQ Group Pageii Module ihteraces 27 ERS 27 Pinoutmodule connectol 28 Pinout module connector X2 MECHANICS 30 Module connectors 2 30 BIAD AOIN EAEE EEEE NRE EEEE RNE REENA AARE T 31 Component ielE Tet i1 RR 32 Adaptation to the environment c sssssssssssssessssscsssssscsssssecsssssscssccsscsssssucsasssscsucssscsusssscsuscsscsuccsscsusssscsuccascsuccuscsucsascsucsascsucsascesceasesees 33 Protection against external lt 33 IIT UO ENET I i MRRR snan 33 Str ct radlrequireelYts T TT TUM TT D MINUM 33 Nates OF treatmellb cem O PI NNNM EM IM 33 Ko RU Ji RR 33 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 34 34
2. Table 42 EREE Table 43 Pinout module connector X1 Table 44 Pinout module connector X2 m Table 45 Plug connectors used on the TOMAS3 csescsssssssccseecssecssecsseecssecssecessccssecssecsscessecssecsucssscessecsucceacesseesucessceeaseesseceuceeaeeessecseess 30 Table 46 Suitable carrier board mating plug 30 Table 47 CIONYMS EM 36 Table 48 Further applicable COCUMENTS ssssssssssecssecsseessecenscessecssecesscessecsuscssscesscessccssscesscessccsuscesscesscesueceascenscessecsuccesscesseceneceseenseesneets 38 ILLUSTRATION DIRECTORY Illustration 1 Illustration 2 Illustration 3 Illustration 4 Illustration 5 Illustration 6 Illustration 7 Illustration 8 Illustration 9 Illustration 10 Illustration 11 Illustration 12 Illustration 13 Illustration 14 Illustration 15 User s Manual TOMa53 UM 200 1 2013 TQ Group Page iv Block diagram TOMa53 simplified 4 Block diagram 53
3. 5 Block diagram i MX537 Block diagram DDR3 SDRAM COnne ction sesssssscssecssecsseccssecssecsscssasecssccssccssccesseessecsucceaseessecssccsucceasecsuecsucceseecaeecseeesaees 11 Block diagram eMMC flash connection 4 11 Block diagram EEPROM 2 12 Block diagram temperature sensor 4 12 NITE 13 Block diagram UART2 interface 23 T Te Le Ta Tile 1 E A V E 25 Block diagram power supply Carrier DOA essesssssecsesssescssecssecssessseecssecssecssesesecssecsscssacecsscessecsueceasecsuecsecssaeeeseeseeesaees 27 31 Overall dimensions bottom view ausssssesssssssnssnsnsnnenennenennennnnennnnenennennnnennnnenennensnnensnnensnnensnnensnnensnnensnnensnnensnnensnnensnnensnnensnne 31 32 Component placement DOLOID 5
4. 32 REVISION HISTORY Q User s Manual TQMa53 UM 200 2013 TQ Group Page v Rev Date Pos Modification 100 05 09 2012 Petz Document created 200 28 03 2013 Petz All Complete rework 10 User s Manual TOMa53 UM 200 2013 TQ Group Page 1 1 ABOUT THIS MANUAL 1 1 Copyright and licence expenses Copyright protected 2013 by TQ Systems GmbH This User s Manual may not be copied reproduced translated changed or distributed completely or partially in electronic machine readable or in any other form without the written consent of TO Systems GmbH The drivers and utilities for the used components as well as the BIOS are subject to the copyrights of the respective manufacturers The licence conditions of the respective manufacturer are to be adhered to Bootloader licence expenses are paid by TO Systems GmbH and are included in the price Licence expenses for the operating system and applications are not taken into consideration and must be separately calculated declared 1 2 Registered trademarks TQ Systems GmbH aims to adhere to the copyrights of all the graphics and texts used in all publications and strives to use original or license free graphics and texts All the brand names and trademarks mentioned in the publication including those protected by a third par
5. Illustration 4 Block diagram DDR3 SDRAM connection In the following table the possible variations of the TOMa53 using different types of memory chips are shown Table 6 DDR3 SDRAM Placement option Capacity 2 x DDR3 128M16 2 x TOP assembled 512 Mibyte 4 x DDR3 128M16 2 x TOP and 2 x BOTTOM assembled 1 Gibyte The SDRAM is mapped to the following address ranges Table 7 DDR3 SDRAM address range Start address Size Chip Select Remark 0x7000_0000 0x2000_0000 50 0 000 0000 0 2000 0000 CS1 DDR3 Bottom 3 2 2 2 eMMC NAND flash An eMMC NAND flash is provided to contain the boot loader and the application software In the BSP provided by TO Systems GmbH a clock rate of 50 MHz is supported The hardware reset of the eMMC is routed 0 resistors to the signals RESET IN and RESET DATA12 ball N5 These resistors are however not assembled The use of this function is currently not planned The following block diagram shows how the eMMC flash is connected to the processor ESDHCS3 ESDHC3 CMD ESDHC3 DAT 7 0 DAT 7 0 Illustration 5 Block diagram eMMC flash connection la User s Manual TQMa53 UM 200 2013 TQ Group Page 12 3 2 2 3 EEPROM A serial EEPROM is available for permanent storage of e g module characteristics or customers parameter
6. I2C2 bus is also used for components the TOMa53 The following devices connected to the 2 2 bus on the 53 Table 27 12C2 address distribution Component Chosen address EEPROM M24C64 0x50 061010000 Temperature sensor LM75A 0x48 061001000 PMIC MC34708VM 0x08 060001000 In case more devices are connected to the I2C2 bus on the carrier board the maximum capacitive bus load accordingly to the standard has to be adhered to If required additional pull ups should be provided on the carrier board at the bus la User s Manual TQMa53 UM 200 2013 TQ Group Page 21 3 2 12 4 125 Signals of the digital audio multiplexer 5 via SSI are available at the module connectors to connect an audio codec 125 The following table shows the signals used by the l S interface Table 28 125 signals Signal Direction Remark I2S DIN AUDMUX signal AUD5_RXD 125 DOUT AUDMUX signal AUD5 TXD 125 LRCLK AUDMUX signal AUD5 TXFS 125 SCLK O AUDMUX signal AUD5 TXC 125 MCLK O CCM signal SSI_EXT1_CLK Besides 125 the SSI interface also supports further synchronous modes Details can be taken from the Freescale Reference Manual of the CPU 1 Asynchronous SSI modes are not supported in the standard pin multiplexing 3 2 12 5 1 Wire The i MX53 provides a 1 Wire interface which is routed to the module connectors The following
7. 34 Operational safety and personal 34 Climatic and operational conditions useseessesssenssensssunssenssenssnnssenssnnssnnssunssenssenessnnssnnssnnsssnnssunssnnsssnsssnnssenssnsssnnssenssnnessnnssensen 34 Reliability and service life Rm 35 Environment PFOCECUON e 35 ROHS compliance 35 WEEE regulation 35 Batteries 35 Burgum 35 APPENDIX 36 Acronyms and definitions u CESSES 38 User s Manual TOMa53 UM 200 2013 TQ Group Page iii TABLE DIRECTORY Table 1 Terms and Conventions Table 2 Processor versions Table 3 BOE I MKS IS Table 4 Boot Mode register BIERUSE SE nennen 9 Table 5 Boot 10 Table 6 DDR3 SDRAM vl Table 7 DDR3 SDRAM address range 11 Table 8 EEPROM 12 Table 9 LSU TEL GETSIETS RM 12 Table 10 Current consumption RTC 13 Table 11 FEC signals 14 Table 12 SD card s
8. User s Manual TQMa53 UM 200 2013 TQ Group Page 28 3 3 2 Pinout module connector X1 Table 43 Pinout module connector X1 Ba O eve gna gna eve O Ba ov PO DGND 1 D DGND OV 2 3 3 V CSIO_HSYNC 3 4 CSIO_PIXCLK 3 3V 1 4 3 3 V CSIO_VSYNC 5 6 PO ov P P 0V PO DGND 7 8 CSIO_DATA_EN 3 3 RO1 3 3 V CSIO_D4 9 10 CSIO D5 3 3V R02 3 3 V 50 06 11 12 50 07 3 3V R03 01 3 3 V 50 08 13 14 50 09 3 3V 04 R05 3 3V CSIO D10 15 16 CSIO D11 3 3V 1 02 T03 3 3 V 50 012 17 18 510 D13 3 3V 06 001 3 3V CSIO D14 19 20 CSIO D15 3 3V 002 04 3 3V CSIO D16 21 22 CSIO D17 3 3V 1 T05 003 3 3V 50 D18 23 24 CSIO 019 3 3V 004 5 3 3 V CSIO PWDN 25 26 CSIO_MCLK 3 3V 14 6 3 3V CSIO_RST 27 28 DGND PO OV OV PO DGND 29 30 GPIO3 GPIO20 3 3V IO W01 1 IO 3 3 GPIO3_GPIO28 31 32 GPIO3_GPIO29 3 3 IO 02 wo2 IO 3 3 GPIO3_GPIO22 33 34 GPIO3_GPIO21 3 3 V03 04 IO 3 3 GPIO2_GPIO26 35 36 GPIO2_GPIO27 3 3 06 V08 IO 3 3 GPIO2_GPIO25 37 38 GPIO2_GPIO23 3 3 IO WO08 06 IO 3 3 GPIO3_GPIO11 39 40 GPIO3_GPIO13 3 3 ACO7 9 IO 3 3 V GPIO5 GPIOO 41 42 GPIO3 GPIO14 3 3V IO Y10 U05 3 3V ESPI_MISO 43 44 GPIO3_GPIO12 3 3V V10 V01 O 3 3 ESPI_MOSI 45 46 ESPI_SS1 3 3 O V02 Y02 3 3V ESPI 5528 47 48 550 3 3V Y03 ov PO DGND 49 50 ESPI_SS3 3 3V W03
9. A wake up by the touch is possible in principle The practical implementation and the question in which power modes this is possible depends on the respective software implementation 10 User s Manual 53 UM 200 2013 TQ Group Page 17 3 2 10 External Memory Bus Address and data bus as well as control signals of the external memory interface of the i MX53 are available at the module connectors The signals of the WEIM bus are mostly on the interfaces DISP1 and ECSPI1 DISP1 and ECSPI1 are not available if the WEIM bus is used The chip selects of the External Memory Bus are configurable Information is to be taken from the Freescale Reference Manual of the CPU 1 The following table shows the signals used as well as their characteristics on the EMI interface Table 17 WEIM signals Signal Remark WEIM DA 15 0 WEIM DAO Assigned to DISP1_DAT9 EMI NAND WEIM DA1 Assigned to DISP1_DAT8 EMI_NAND_WEIM_DA2 Assigned to DISP1_DAT7 EMI_NAND_WEIM_DA3 Assigned to DISP1_DAT6 EMI_NAND_WEIM_DA4 Assigned to DISP1_DAT5 EMI WEIM DA5 Assigned to DISP1 DATA WEIM DA6 Assigned to DISP1 DAT3 NAND WEIM Assigned to DISP1 DAT2 WEIM DA8 Assigned to DISP1 DATI EMI NAND WEIM DA9 Assigned to DISP1 DATO EMI NAND WEIM
10. SATA 71 72 SATA Hi 12 10 1 SATA TXM 73 74 SATA RXM ATA 1 1 12 OV POWER DGND 75 76 DGND POWER OV 5 3 3V FEC_INT 77 78 FEC RST4 3 3V K06 C10 O 3 3 79 80 RXDO 3 3V C11 F10 O 3 3V FEC TXDO 81 82 FEC RXD1 3 3V 1 11 D10 3 3V FEC TXD1 83 84 FEC RX DV 3 3V D11 E10 O 3 3 FEC_MDC 85 86 FEC_MDIO 3 3 012 F12 33V FEC_RX_ER 87 88 FEC_REF_CLK 3 3 V 12 OV DGND 89 90 DGND POWER OV C07 3 3V SD WP 91 92 SD DATO 3 3V IO D13 D08 33V SD_CD 93 94 SD_DATI 3 3 V IO C14 C15 IO 3 3 SD_CMD 95 96 SD_DAT2 3 3 IO D14 E14 O 3 3 SD_CLK 97 98 SD_DAT3 3 3 E13 P OV POWER DGND 99 100 DGND POWER OV 19 IO 2 05 101 102 USB H1 DN 21 IO B17 B19 IO 2 USB OTG DP 103 104 USB H1 DP 21 IO A17 OV POWER DGND 105 106 DGND POWER OV 16 3 3V USB OTG ID 107 108 USB 1 VBUS 5 0V 015 15 Al 5 0V USB_OTG_VBUS 109 110 O 2 775 V 18 2 775V VCC2V775 111 112 BOOT_MODE1 2 775 V Ipu B20 17 33V SPI 550 113 114 SPI 5528 3 V F16 A20 3 3 V SPI_MISO 115 116 SPI_SS1 3 3V 17 16 O 3 3 SPI_SCLK 117 118 SPI_MOSI 3 3 O F18 OV POWER DGND 119 120 DGND POWER OV PMIC ball 1 See Serial ATA Specification 2 6 See USB 2 0 Specification la User s Manual TQMa53 UM 200 2013 TQ Group Page 30 4 MECHANICS 4 1 Module connecto
11. Boot configuration eFuse BOOT_CFG1 EIM_A21 DISP1_DAT16 BOOT_CFG1 20 DISP1 DAT15 BOOT_CFG1 EIM_A19 DISP1_DAT14 BOOT_CFG1 User s Manual TQMa53 UM 200 2013 TQ Group Setting 0000 NOR OneNAND 0001 Reserved 0010 Hard Disk PATA SATA 0011 Serial ROM SPI 010x SD eSD 011x MMC eMMC 1xxx NAND Fast Boot Support 0 Normal Boot 1 Fast Boot la Page 10 Default 18 DISP1 DAT13 BOOT CFG1 SD MMC Speed Mode 0 Normal Speed Mode 1 High Speed Mode A17 DISP1 DAT12 BOOT CFG1 Reserved EIM A16 DISP1 CLK BOOT CFG1 BT_FREQ 0 ARM Frequency 800 MHz 1 ARM Frequency 400 MHz EIM_LBA GPIO2 GPIO27 BOOT CFG1 MMU ENABLE 0 MMU Cache is disabled by ROM during the boot 1 MMU Cache is enabled by ROM during the boot DISP1_DAT11 BOOT CFG2 Bus Width SD eSD xx0 1 Bit EB1 DISP1_DAT10 BOOT CFG2 DAO DISP1 DAT9 BOOT CFG2 xx1 4 Bit MMC eMMC 000 1 Bit 001 4 Bit 010 8 Bit 101 4 Bit DDR MMC 4 4 110 8 Bit DDR MMC 4 4 Else Reserved EIM_DA1 DISP1 DAT8 BOOT CFG2 AXI DDR Frequency 0 200 MHz AXI 400 MHz DDR 12166 MHz AXI 333 MHz DDR DA2 DISP1 DAT7 BOOT CFG2 OSC FREQ SEL 0 19 2 24 26 27 MHz Auto Detection 1 OSC F
12. 7 O 3 3 DISP1_DRDY_DE 51 52 DGND OV 8 O 3 3 DISP1 DAT1 53 54 ESPI SCLK 3 3V 006 09 O 3 3 DISP1_DAT3 55 56 DISP1_CLK 3 3 O 5 06 O 3 3 DISP1 DAT5 57 58 DGND OV 07 O 3 3 DISP1_DAT7 59 60 DISP1_HSYNC 3 3 O Y01 08 O 3 3 DISP1 DAT9 61 62 DISP1 VSYNC 3 3V 04 O 3 3 DISP1_DAT11 63 64 DGND PO ov P O 3 3 DISP1_DAT13 65 66 DISP1_DATO 3 3 O W10 06 3 3V DISP1 DAT15 67 68 DISP1 DAT2 3 3V 5 3 3V DISP1 DAT17 69 70 DISP1_DAT4 3 3V O V09 05 3 3V DISP1 DAT19 71 72 DISP1 DAT6 3 3V O Wo9 W04 O 3 3 DISP1 DAT21 73 74 DISP1 DAT8 3 3V 4 V04 3 3V DISP1 DAT23 75 76 DISP1 DAT1O 3 3V 5 0V PO DGND 77 78 DISP1 DAT12 3 3V O V07 09 3 3V HSYNC 79 80 DISP1 DAT14 3 3V W07 07 O 3 3 VGA_VSYNC 81 82 DISP1_DAT16 3 3 O 04 19 0 7V TVDAC IOB 83 84 DISP1 DAT18 3 3V V06 AB20 AO 0 7V TVDAC IOG 85 86 DISP1 DAT20 3 3V Wo5 AC21 AO 0 7V TVDAC_IOR 87 88 DISP1 DAT22 3 3V V05 P 0V PO DGND 89 90 DGND PO OV 16 1 2 LVDSO_CLK_P 91 92 LVDS1_CLK_P 1 2 O 1 16 O 1 2 LVDSO_CLK_N 93 94 LVDS1_CLK_N 1 2 O 1 OV PO DGND 95 96 DGND OV 17 O 1 2 LVDSO TXO P 97 98 LVDS1 TXO P 1 2V O AB14 17 1 2 V LVDSO TXO N 99 100 LVDS1 TXO N 1 2V 14 OV PO DGND 101 102 DGND 17 O 1 2 LVDSO TX1 P 103 104 LVDS1 TX1 P 1 2V O AB13 AB17 O 1 2 L
13. Middle grade connectors which guarantee at least 100 mating cycles were used for the module 6 6 Environment protection 6 6 1 RoHS compliance The TOMa53 is manufactured RoHS compliant All used components and assemblies are RoHS compliant RoHS compliant soldering processes used 6 6 2 WEEE regulation The company placing the product on the market is responsible for the observance of the WEEE regulation To be able to reuse the product it is produced in such a way a modular construction that it can be easily repaired and disassembled 6 7 Batteries No batteries are used on the TOMa53 6 8 Other entries By environmentally friendly processes production equipment and products we contribute to the protection of our environment The energy consumption of this subassembly is minimised by suitable measures Printed pc boards are delivered in reusable packaging Modules and devices are delivered in an outer packaging of paper cardboard or other recyclable material Due to the fact that at the moment there is still no technical equivalent alternative for printed circuit boards with bromine containing flame protection FR4 material such printed circuit boards are still used No use of PCB containing capacitors and transformers polychlorinated biphenyls These points are an essential part of the following laws e The law to encourage the circular flow economy and assurance of the environmentally acceptable remov
14. 3 1 1 System architecture block CiaQrarm sssssscsesscseserssesecsesessnssecsssessnseessseessnseessseessnseessseessnsesssseessnseessusessnseessesessnsesssssensneesssesessneeesses 5 3 12 6 3 2 yiii c 7 3 2 1 i MX53 processor details 3 2 1 1 i MX53 processor versions 3 2 1 2 CPU 3 2 1 3 edu M 3 2 1 4 Boot CONFIGUIATION ssessssescsescsseccsescsscessecssscesscessecssscesscessecssecesscessecssecesscessecsucesscesseesuecesscessecsuecssscesscesuecsucssecesseesuecesecesseesueceseeeseeesneets 3 2 1 5 BOE MIT 1a 32 16 eR 3 2 2 m 3221 5 3222 EMME NAND fl s 22232 eet 3 2 3 324 ROC 3 2 5 Ethernet 3 2 6 SD card 3 2 7 3 2 8 3 2 9 TOUGH 3 2 10 External Memory Bus 3 2 11 Graphics interfaces 3 2 11 1 3 2 11 2 3 2 11 3 3 2 11 4 3 2 11 5 3 2 12 3 2 12 1 3 2 12 2 3 2 12 3 3 2 12 4 3 2 12 5 3 2 12 6 3 2 12 7 3 2 12 8 3 2 12 9 i USB 3213 CCS 3 244
15. CompactFlash cards are to be taken note of They contain if applicable additional information that must be taken note of for safe and reliable operation These documents are stored at TQ Systems GmbH e Chip errata It is the user s responsibility to make sure all errata published by the manufacturer of each component are taken note of The manufacturer s advice should be followed e Software behaviour No warranty can be given nor responsibility taken for any unexpected software behaviour due to deficient components e General expertise Expertise in electrical engineering computer engineering is required for the installation and the use of the device The following documents are required to fully comprehend the following contents e Circuit diagram MBa53 e Manual IMX53RM User s Manual STK MBa53 e Documentation of boot loader U Boot http www denx de wiki U Boot Documentation e Documentation of PTXdist http www ptxdist de la User s Manual TQMa53 UM 200 2013 TQ Group Page 4 2 BRIEF DESCRIPTION The User s Manual describes the hardware of the TOMa53 and refers to some software settings It does not replace the Reference Manual of the CPU The TOMa53 is a universal Minimodule based on the Freescale ARM CPU MCIMX53 i MX53 The Cortex A8 core of this CPU works with up to 1 2 GHz The TOMa53 extends the TOC product range and offers an outstanding computing performance combined with high performan
16. DA10 Assigned to DISPI DRDY DE EMI NAND WEIM DA11 Assigned to GPIO11 EMI NAND WEIM DA12 Assigned to GPIO3_GPIO12 WEIM DA13 Assigned to GPIO3_GPIO13 EMI NAND WEIM DA14 Assigned to GPIO14 WEIM DA15 Assigned to HSYNC WEIM D 31 16 EMI WEIM D16 Assigned to ESPI SCLK EMI WEIM D17 Assigned to ESPI_MISO EMI_WEIM_D18 Assigned to ESPI_MOSI EMI_WEIM_D19 Assigned to ESPI_SS1 EMI_WEIM_D20 Assigned to GPIO3_GPIO20 EMI_WEIM_D21 Assigned to GPIO3_GPIO21 EMI WEIM D22 Assigned to GPIO22 EMI WEIM D23 Assigned to LCD HSYNC EMI WEIM 024 Assigned to 5528 EMI WEIM 025 Assigned to ESPI_SS3 WEIM 026 Assigned to DISP1_DAT22 EMI_WEIM_D27 Assigned to DISP1_DAT23 EMI_WEIM_D28 Assigned to GPIO3_GPIO28 EMI_WEIM_D29 Assigned to GPIO3 GPIO29 WEIM 030 Assigned to DISP1 DAT21 EMI WEIM D31 Assigned to DISP1_DAT20 WEIM CONTROL EMI WEIM CSO Assigned to GPIO2 GPIO23 WEIM CS1 Assigned to VSYNC EMI WEIM OE Assigned to GPIO2 GPIO25 EMI WEIM RW Assigned to 2 GPIO26 WEIM 2 Assigned to 550 WEIM Assigned to LCD VSYNC EMI WEIM Assigned to GPIO2 GPIO27 EMI WEIM WAIT Assigned to GPIO5 GPIOO la User s Manual TQMa53 UM 200 2013 TQ Group Page 18 3 2 11 Graphics interfaces 3 2 111 CSI The i MX53 has two identical Camera Sensor Interfaces max 8192 x 4096
17. ELDK Embedded Linux Development Kit EMC Electro Magnetic Compatibility EMI Electro Magnetic Interference eMMC embedded Multi Media Card EN Europ ische Norm ESD Electro Static Discharge eSD enhanced Secure Digital eSDHC enhanced Multi Media Card Secure Digital Host Controller 5 enhanced Serial Peripheral Interface ETS European Telecommunications Standards FEC Fast Ethernet Controller FIRI Fast Infrared Interface FR4 Flame Retardant 4 GND Ground GPIO General Purpose Input Output GPT General Purpose Timer HDD Hard Disk Drive 1 0 Input Output IEEE Institute of Electrical and Electronics Engineers IP Ingress Protection PC Inter Integrated Circuit PS Inter Integrated Circuit Sound JTAG Joint Test Action Group LAN Local Area Network LCD Liquid Crystal Display LED Light Emitting Diode LICELL Lithium Cell LVDS Low Voltage Differential Signal la User s Manual TQMa53 UM 200 2013 TQ Group Page 37 Table 2 Acronyms continued MISO Master In Slave Out MMC Multimedia Card MMU Memory Management Unit MOSI Master Out Slave In MOZI Module extractor Modulzieher MTBF Mean operating Time Between Failures NAND Not and NOR Not or OSC Oscillator OTG On The Go PATA Parallel ATA PCB Printed Circuit Board PD Pull down resistor PHY Physical interface PLL
18. O TSX1 13 14 TSY1 O 24V Al 107 05 Al 24V O TSX2 15 16 TSY2 O 24V Al 106 OV POWER DGND 17 18 DGND POWER OV 11 3 3V P LICELL 19 20 GLBRST 3 3V lipu G07 G08 lipu 1 5 V P PWRON 21 22 RESET_OUT 3 3V Oop 103 O 3 3 LCD LCD_BLT_EN 23 24 LCD_PWR_EN LCD 3 3 O M04 B07 O 3 3 LCD LCD_CONTRAST 25 26 LCD_RESET LCD 3 3 O 104 OV POWER DGND 27 28 DGND POWER OV 101 3 3V 2 TXD 29 30 UART1_RXD 3 3V 1 102 K04 33V UART2_RXD 31 32 UART1_TXD 3 3V 103 K03 3 3 V UART2_RTS 33 34 UART3_RXD 3 3V 102 5 3 3V UART2 CTS 35 36 TXD 3 3V 105 OV POWER DGND 37 38 DGND POWER 05 O 3 3 2_ 39 40 1_ 3 3V C04 E06 3 3 V CAN2_RX 41 42 CAN1_RX 3 3 V 05 006 3 3V 125 DIN 43 44 125 SCLK 3 3V O CO5 E07 O 3 3 12S_LRCLK 45 46 12S_DOUT 3 3V B03 P OV POWER DGND 47 48 DGND POWER C08 O 3 3 125 49 50 SPDIF OUT 3 3V O A03 OV POWER DGND 51 52 SPDIF IN 3 3V C06 B05 O 3 3 FIRI_TXD 53 54 FIRI_RXD 3 3 V 1 04 004 3 3V 2 2 SDA 55 56 2 SDA 3 3V IO B06 F06 lOpu 3 3 V 12C2_SCL 57 58 I2C3 SCL 3 3V IO A05 P OV POWER DGND 59 60 DGND POWER 06 1 0 3 3 V GPIO1_GPIO3 61 62 OWIRE 3 3 V 007 07 O 2 775 JTAG_TDO 63 64 RESET_IN O 3 3 Ipu 8 Ipu 2 775V JTAG_TMS 65 66 JTAG_TDI 2 775V Ipu B08 E09 Ipu 2 775V JTAG_TRST 67 68 JTAG_TCK 2 775V 009 OV POWER DGND 69 70 DGND POWER ov P A10 1
19. Phase Locked Loop PMIC Power Management IC PU Pull up resistor PWM Pulse Width Modulation RC Resistor Capacitor RF Radio Frequency RMII Reduced Media Independent Interface RoHS Restriction of the use of certain Hazardous Substances ROM Read Only Memory RTC Real Time Clock SATA Serial ATA SCL Serial Clock SD Secure Digital SDA Serial Data SDHC Secure Digital High Capacity SDIO Secure Digital Input Output SDRAM Synchronous Dynamic Random Access Memory SJC System JTAG Controller SMD Surface Mounted Device SPDIF Sony Philips Digital Interface Format SPI Serial Peripheral Interface SS Slave Select SSI Standard Serial Interface Controller SSI Synchronous Serial Interface SW Software TVE TV Encoder UART Universal Asynchronous Receiver Transmitter ULPI UTMI Low Pin count Interface USB Universal Serial Bus USB HS Universal Serial Bus High Speed USBOTG USB On The Go UTMI USB 2 0 Transceiver Macrocell Interface VGA Video Graphics Array 640 x 480 WDI Watchdog Input WDOG Watchdog WEEE Waste Electrical and Electronic Equipment WEIM Wireless External Interface Module la User s Manual TQMa53 UM 200 2013 TQ Group Page 38 7 2 References Table 48 Further applicable documents Date Company 1 i MX53 Multimedia Applications Processor Reference Manual 2 1 2012 06 Freescale 2 i MX53 Applications Processors for Industrial Products 4 2011 11 Freescale 3 i MX53xD Ap
20. cooling should be sufficient in most cases 434 Structural requirements The 53 is held in the module socket by the retention force of the pins a total of 240 For high requirements with respect to vibration and shock firmness an additional plastic module holder has to be provided in the final product to hold the module in its position For this purpose TQ Systems GmbH provides a standard solution As no heavy and big components are used further requirements are given The CPU belongs to a performance category in which a cooling system may be essential in certain applications It is the responsibility of the customer to define a suitable cooling method depending on the specific mode of operation e g dependence on clock frequency stack height airflow and software 4 3 5 Notes of treatment To avoid damage caused by mechanical stress the TOMa53 may only be extracted from the carrier board by using the extraction tool MOZI8XXL that can also be obtained separately 2 5 mm should be kept free on the carrier board along the longitudinal edges on both sides of the module for the extraction tool 5 SOFTWARE The TOMa53 comes with a preinstalled boot loader and a BSP for the Starterkit STK MBa53 More information can be found in the Support Wiki for the TOMa53 la User s Manual TQMa53 UM 200 2013 TQ Group Page 34 6 SAFETY REQUIREMENTS AND PROTECTIVE REGULATIONS 6 1 EMC The module was develo
21. shows the signals used by the PMIC which are made available at the module connectors as well as the signals which serve for the communication with the CPU Table 42 PMIC signals Signal name Description Power on off button connection 1 to PMIC PWRON Switch to GND Internal pull up to 1 5 V SYSTEM DOWN Indication of imminent system shutdown to processor PMIC INT Interrupt to processor WDOG Watchdog output to PMIC PMIC_STBY_REQ Standby output signal to PMIC PMIC_ON_REQ Power on off connection 2 to PMIC 3 3 Module interface 3 31 Pin assignment When using the processor signals the multiple pin configurations by different processor internal function units must be taken note of The pins assignment listed in sections 3 3 2 and 3 3 3 refer to the corresponding standard BSP of TQ Systems GmbH The electrical and pin characteristics are to be taken from the data sheets of CPU 2 3 and PMIC 5 Q
22. signals It is to be taken note of that in DTE as well as in DCE mode RTS is always an input and CTS is always an output See Freescale Reference Manual of the CPU 1 The UART2 interface with handshake signals provided by the processor is made available at the module connectors The following table shows the signals used by the UART2 interface Table 35 UART2 signals Signal name Direction Remark UART2_RXD UART2 O UART2_RTS UART2_CTS 0 The following table shows the signals used by the UART3 interface Table 36 UART3 signals Signal Direction Remark UART3_RXD UART3 TXD O gt and UARTS are available if the 5 interface is not used la User s Manual TQMa53 UM 200 2013 TQ Group Page 24 3 2 12 10 USB The i MX53 CPU provides three USB Host Cores and one USB OTG Core The Host1 Core and the OTG Core have an integrated High Speed PHY and are available at the module connectors The following table shows the signals used by the USB H1 interface Table 37 USB_H1 signals Signal name Direction Remark USB_H1_DP 1 0 USB_H1_DN 1 0 USB_H1_VBUS Al Series resistor 100 Q and capacitor 1 uF to GND on the TQMa53 The following table shows the signals used by the USB_OTG interface Table 38 USB_OTG signals Signal name Direction Remark USB_OTG_DP 1 0 USB_OTG_DN 1 0 USB_OTG_VBUS A
23. CPU 4 la User s Manual TQMa53 UM 200 2013 TQ Group Page 8 3 21 3 Boot mode The boot mode of the i MX53 is set with the pins BOOT MODEO and BOOT_MODE1 The following table shows the supported boot modes as well as the boot mode selected for the TOMa53 Table 3 Boot modes i MX53 BOOT MODET 1 0 Boot type TOMa53 Remark 00 Internal Boot Settings for boot configuration via GPIO pins 01 Reserved BOOT 10 10 Boot From Fuses X 10 kO PD 11 Serial Downloader Via USBOTG or UART2 Both signals BOOT_MODE 1 0 are additionally made available at the module connectors All possible boot modes can therefore be set by alternative placement of resistor combinations on the carrier board gt enable reading of the boot configuration via the GPIO pins BOOT 01 has to be set to 00 For that purpose the pin BOOT MODE has to be pulled low on the carrier board gt The reference voltage for BOOT_MODE 1 0 is VCC2V775 which is also available at the module connectors 3 2 1 4 Boot configuration A total of 21 GPIO pins are available for the boot configuration gt Freescale recommends overriding the eFuses by GPIO pins only during development and to burn the necessary eFuses in the final product The TOMa53 is delivered with no preset boot configuration gt On TOMa53 none of the 21 boot configuration pins are connected g
24. IC provides a pin LICELL which is routed to the module connector For the RTC to work reliably the voltage at the pin LICELL has to be in the range of 2 3 V to 3 6 V The i MX53 as well as the PMIC MC34708 provide an RTC Additionally the PMIC provides an SRTC support for the i MX53 The choice of RTC used depends on the software implementation More details are to be taken from the Freescale Reference Manual of the CPU and the PMIC The accuracy the RTC is mainly determined by the characteristics of the quartz used The type 135 used on the 53 has a standard frequency tolerance of 20 ppm at 25 C Parabolic coefficient max 0 04 x 1075 C The manufacturer of the RTC provides the following values for the typical current consumption Table 10 Current consumption RTC RTC Typical current consumption Remark PMIC RTC 4 0 uA Mode RTC Power Cut CPU SRTC 10 uA PMIC provides the necessary supply voltage and clock signal for the SRTC of the CPU The following block diagram shows the implementation on the TOMa53 CLK32KMCU CKIL Coin Cell 2032 PMIC CPU VSRTC NVCC_SRTC_POW Illustration 8 Block diagram RTC The RTC domain of the PMIC on the 53 offers the possibility of a backup supply It supports simple coin cells but also Lithium coin cells or a SuperCap which can also be charged by the PMIC Charging methods and electrical characteristics of the pin LICELL are to
25. O Signal i MX53 CSPI_SCLK SPI MOSI O Signal i MX53 CSPI_MOSI SPI MISO Signal i MX53 CSPI_MISO SPI_SS 2 0 O Signal i MX53 CSPI_SS 2 0 The signals of the ECSPI1 module provided by the processor are made available as SPI interface 2 at the module connectors The signals of the ECSPI1 interface are multiplexed with those of the WEIM bus ECSPI1 is not available if the WEIM bus is used Alternatively five signals can be used to connect a serial display to the display interface 1 The following table shows the signals used by the ECSPI interface Table 33 ECSPI signals Signal Direction Remark ESPI_SCLK O Signal i MX53 ECSPI1 SCLK ESPI_MOSI O Signal i MX53 ECSPI1_MOSI ESPI MISO Signal i MX53 ECSPI1_MISO ESPI_SS 3 0 Signal i MX53 ECSPI1_SS 3 0 gt When required the port ECSPI1 can be configured as a boot device Therefore the signal SS1 has to be used as slave select User s Manual TOMa53 UM 200 2013 TO Group Page 23 3 2 12 9 UART The i MX53 provides five UART interfaces UARTI UART2 and UART3 are available at the module connectors UART2 TX UART2 RX UART2 UART2_CTS Illustration 9 Block diagram UART2 interface The following table shows the signals used by the UART1 interface Table 34 UART1 signals Signal Direction Remark UART1_RXD UART1_TXD O UART2 also provides handshake
26. Reset of the CPU On the module PU 28 to 2 775 V Low active signal RESET IN Ipu Reset output ofthe PMIC RESET_OUT Oop Can be used for reset inputs of external periphery Open Drain requires pull up on the carrier board max 3 3 V Global reset input of the Generates cold start of the PMIC GLBRST lieu Internal pull up to 1 5 V To activate GLBRST apply low level for preset time according to PMIC register GLBRSTTMR 1 0 see Data sheet PMIC 5 la User s Manual TQMa53 UM 200 2013 TQ Group Page 26 3 2 14 Supply 3 2 14 1 Overview module supply The following table shows some technical parameters of the module supply The given current consumption has to be seen as an approximate value To estimate the power consumption of the system the Freescale Application Note AN4270 should be heeded as the current consumption of the TQMa53 strongly depends on the application the mode of operation and the operating system The input voltage of the TQMa53 is 5 V 10 to 5 This results in an input voltage range of 4 5 V to 5 25 V Table 41 Parameter module supply Parameter Value typ Remark Supply voltage Vin 5V 10 96 to 5 96 Current consumption Linux idle 420 mA CPU 800 MHz BSP without power management Current consumption Linux 100 96 580 mA CPU 800 MHz BSP without power management In principle the CPU supports besides the Dynamic Voltage
27. Scaling the following Power Modes e RUN e WAIT STOP The implementation of the modes depends on the BSP and is not considered here All requirements according to hardware are created by using an intelligent PMIC The PMIC itself also has different power modes whose implementation depends on the software The voltages generated by the PMIC and the DC DC converters on the TOMa53 are not monitored On the TOMa53 the following mechanisms or possibilities to monitor the voltage exist VCC3V8 BP function BP lower than TKRL gt switch to Off mode if BP 3 0 V for more information see Data sheet PMIC 5 e VCC3V8 BP PMIC ADC channel 2 gt monitoring of undervoltage or overvoltage in software for more information see Data sheet PMIC 5 e VCCIV1 SW VDDGP CPU function Brown Out Detection gt Power Fail if VDDGP 0 8 V for more information see Reference Manual CPU 1 VCC2V775 Voltage is routed to module connector and can be monitored on the carrier board e VCC3V2 Optional monitoring on the carrier board can be done with an unused I2C3 pin Therefore the pin has to be configured accordingly and a pull up resistor has to be assembled on the TOMa53 la User s Manual TQMa53 UM 200 2013 TQ Group Page 27 3 2 14 2 Module carrier board Power Up sequence The chronological behaviour of the voltages generated on the carrier board are required for its design because the TQMa53 requires a sup
28. TOMa53 UM 200 28 03 2013 User s Manual TOMa53 UM 200 2013 TQ Group Pagei TABLE OF CONTENTS 1 1 1 1 Copyright and licence 1 1 2 Registered trademarks 1 3 Bier 1 4 555 5 1 1 5 2 1 6 Symbols and typographic CONVENTIONS ssssssscssesseceseeesseccnecescesscessecescesscessecsssceascesseccsecesscesseessecesscesseesueceascesseesueesseceaeesseeeneeesees 2 1 7 Handling and ESD tipS RR 2 1 8 Sce 3 1 9 Further applicable documents presumed 3 2 DRIEEJOESCRIP TIONI AEEA 4 2 1 Key functions and 4 3 ELECTRONICS SREGIFICAMON 5 3 1 SVS LCMV ET VIG 5
29. VDSO_TX1_N 105 106 LVDS1 TX1 N 1 2V 1 OV PO DGND 107 108 DGND ov P AA16 O 1 2 LVDSO TX2 P 109 110 LVDS1 TX2 P 1 2V 12 16 O 1 2 LVDSO_TX2_N 111 112 LVDS1_TX2_N 1 2 O AC12 OV PO DGND 113 114 DGND PO oV P 15 O 1 2 LVDSO TX3 P 115 116 LVDS1 TX3 P 1 2V 12 15 O 1 2 LVDSO TX3 N 117 118 LVDS1 TX3 N 1 2V 12 0V PO DGND 119 120 DGND PO la User s Manual TQMa53 UM 200 2013 TQ Group Page 29 333 Pinout module connector X2 Table 44 Pinout module connector X2 Ba O eve oup oup eve 5V POWER VCC5V 1 2 VCC5V POWER 5V P 5V POWER VCC5V 3 4 VCC5V POWER 5V P 5V POWER VCC5V 5 6 VCC5V POWER 5V P OV POWER DGND 7 8 POWER OV OV POWER DGND 9 10 DGND POWER OV OV POWER DGND 11 12 DGND POWER K04 Al 24V
30. al of waste as at 27 9 94 source of information BGBI 1994 2705 Regulation with respect to the utilization and proof of removal as at 1 9 96 source of information BGBI 1996 1382 1997 2860 Regulation with respect to the avoidance and utilization of packaging waste as at 21 8 98 source of information BGBI 1998 2379 Regulation with respect to the European Waste Directory as at 1 12 01 source of information BGBI 2001 3379 This information is to be seen as notes Tests or certifications were not carried out in this respect la User s Manual TQMa53 UM 200 2013 TQ Group Page 36 7 APPENDIX 7 1 Acronyms and definitions The following acronyms and abbreviations are used in this document Table 47 Acronyms Acronym Meaning Al Analog Input ARM Advanced RISC Machine ATA Advanced Technology Attachment AXI Advanced eXtensible Interface bus BIOS Basic Input Output System BSP Board Support Package CAN Controller Area Network CF CompactFlash CPU Central Processing Unit CSI Camera Sensor Interface CSPI Configurable SPI DC Direct Current DDR Double Data Rate DIN Deutsche Industrie Norm DISP Display DLL Delay Locked Loop eCSPI enhanced Configurable SPI EEPROM Electrically Erasable Programmable Read only Memory EIM External Interface Module
31. be taken from the data sheet of the PMIC MC34708 5 15 to be taken note of that the typical charging current is only 60 pA gt Concerning the RTC the errata sheet of the PMIC 6 contains two errata number 5 and 23 which describe a failure of the RTC or the backup supply which can occur under certain circumstances No workaround was provided with regard to these errata on the TQMa53 To avoid these errata on the target system the use of an on the carrier board is recommended la User s Manual TQMa53 UM 200 2013 TQ Group Page 14 3 2 5 Ethernet The i MX53 provides a 10 100 Mbit Fast Ethernet Controller FEC with whose signals are routed to the module connectors The following table shows the signals used by the FEC Table 11 FEC signals Signal name Direction Remark FEC_REF_CLK Ethernet Input Transmit Reference Clock FEC TX EN O Ethernet Output Transmit Enable FEC TXD 1 0 O Ethernet Output Transmit Data FEC_RX_DV Ethernet Input Receive Data Valid FEC RXD 1 0 Ethernet Input Receive Data FEC RX ER Ethernet Input Receive Error FEC MDC O Ethernet Output Management Data Clock FEC_MDIO Opu Ethernet Management Data PU 1 5 FEC_RST Ethernet Output Reset GPIO FEC INT Ethernet Input Interrupt GPIO 3 2 6 SDcard An SD card can be connected to the TOMa53 The Enhanced Secured Digital Host Controller 2 version 2 ESDHCV2 2 is routed to th
32. card 1 x ECSPI SPI 1 x Ethernet 10 100 Mbit 1 x FIRI Fast Infrared 2 1 15 2 x LVDS display 1 x 1 Wire 1x SATA 1 x SPDIF 3 x UART 1 with handshake 2 x USB 2 0 Hi Speed 1x VGA 1 x Touch GPIOs JTAG Boot mode As an alternative to the factory configuration further interfaces of the i MX53 can also be used USB 2 0 Hi Speed ULPI interface WEIM bus ESDHC1 SDIO MMC SD card General Purpose Timer PWM More UARTs Page 6 la User s Manual TQMa53 UM 200 2013 TQ Group Page7 3 2 System components 3 2 1 i MX53 processor details The following illustration shows the block diagram of the i MX53 derivative i MX537 System Control Timers er Power Mgmt and Analog Standard Connectivity External Storage I F Lee Security System Debug je Illustration 3 Block diagram i MX537 Source Freescale 3 2 1 1 i MX53 processor versions Depending on the version of the TOMa53 one of the following versions of the CPU is assembled Table 2 Processor versions Manufacturer Part number Features estate Temperature Package Freescale MCIMX537CVV8C 800 MHz N78C 40 to 85 C 19 x 19 mm BGA Freescale MCIMX535DVV1C 1GHz N78C 20to 85 C 19 x 19 mm BGA Freescale MCIMX535DVV2C 1 2GHz 78 20to 85 C 19 x 19 mm BGA 3 2 1 2 CPU errata Please take note of the current errata of the Freescale
33. ce graphics power gt A RTC DDR3 SDRAM CENE Er EEPROM i MX535 i MX537 eMMC S Power PMIC Temperature sensor Illustration 1 Block diagram TOMa53 simplified The TOMa53 provides the following key functions and characteristics 2 1 Key functions and characteristics e Freescale CPU i MX53 i MX537 or i MX535 e Upto 1 Gibyte DDR3 SDRAM e Up to 16 Gibyte eMMC NAND flash 64 Kbit EEPROM Temperature sensor Real time clock e Freescale Power Management Integrated Circuit e All essential CPU pins are routed to the module connectors Extended temperature range e Single power supply 5 V la User s Manual TQMa53 UM 200 2013 TQ Group Page 5 3 ELECTRONICS SPECIFICATION 3 1 System overview 3 1 1 System architecture block diagram DDR3 SDRAM eMMC EEPROM d N Temperature sensor 4 Illustration 2 Block diagram TOMa53 Q User s Manual TQMa53 UM 200 2013 TQ Group 3 1 2 Functionality The following key functions are implemented on the TQMa53 i MX53 processor DDR3 SDRAM eMMC NAND flash EEPROM Temperature sensor PMIC DC DC converter The following interfaces are provided at the module connectors of the TOMa53 2x CAN 1 x Camera Sensor Interface 1 x CSPI SPI 1 x parallel display DISP 1 x ESDHC2 SDIO MMC SD
34. e module connectors for this purpose The following table shows the signals used by the SD card interface Table 12 SD card signals Signal name Direction Remark ESDHC2_CLK SD Card Output Clock ESDHC2 DAT 3 0 1 0 SD Card Data ESDHC2 CMD 1 0 SD Card Command ESDHC2_WP SD Card Write Protect ESDHC2 CD SD Card Card Detect The supported modes of operation as well as MMC specifications are to be taken from the Freescale Reference Manual of the CPU 1 gt When required the port ESDHC2 can be configured as a boot device 227 GPIO 10 User s Manual TOMa53 UM 200 2013 TQ Group Page 15 Besides their interface function most of the pins of the i MX53 can also be used as GPIOs All these GPIOs interrupt and therefore wake up capable Details are to be taken from the Freescale Reference Manual of the CPU 1 Moreover several pins marked as GPIO are already available at the module connectors The following table shows the signals which can be used as GPIOs Table 13 signals Signal name Direction Remark GPIO1_GPIO3 1 0 x GPIO2 GPIO23 1 0 GPIO2 GPIO25 1 0 GPIO2 GPIO26 1 0 GPIO2 GPIO27 1 0 GPIO3 GPIO11 1 0 GPIO3 GPIO12 1 0 GPIO3 GPIO13 1 0 GPIO3 GPIO14 1 0 GPIO3 GPIO20 1 0 GPIO3 GPIO21 1 0 GPIO3 GPIO22 1 0 GPIO3 GPIO28 1 0 GPIO3 GPIO29 1 0 GPIO5 GPIOO 1 0 The electrical charact
35. eristics of the GPIOs are to be taken from the respective data sheet provided by Freescale 2 3 3 2 8 JTAG User s Manual TQMa53 UM 200 2013 TQ Group la The i MX53 provides two JTAG modes which be set with the signal at the pin MOD The following table shows the available modes as well as the mode set on the TOMa53 With the assembly option R43 and R45 the mode can be changed Page 16 Table 14 JTAG modes JTAG_MODE Default Name Remark 0 X Daisy Chain All For common SW debug high speed and production 1 SJC only IEEE 1149 1 JTAG compliant mode gt TheJTAG port works in the power domain 2 775 V The voltage VCC2V775 is routed to the plug connectors and can be used as a reference voltage for a JTAG adaptor The following table shows the signals used by the JTAG interface Table 15 JTAG signals Signal name Direction Remark JTAG_TCK PD 10 on TOMa53 JTAG TMS leu PU 10 kO to 2 775 V on TOMa53 JTAG TDI Ipu PU 10 to 2 775 V on TOMa53 JTAG TDO JTAG_TRST leu PU 10 kO to 2 775 V on TOMa53 3 2 9 Touch The PMIC used on the TOMa53 provides a touch interface which is routed to the module connectors A 4 wire touch can be connected here The following table shows the signals used by the touch interface Table 16 Touch signals Signal Direction Remark TSX1 Al Left TSX2 Al Right TSY1 Al Top TSY2 Al Bottom
36. ideline may result in damage destruction of the module and be dangerous to your health Improper handling of your TO product would render the guarantee invalid gt Proper ESD handling The electronic components of your TQ product are sensitive to electrostatic discharge ESD Always wear antistatic clothing use ESD safe tools packing materials etc and operate your TQ product in an ESD safe environment Especially when you switch modules on change jumper settings or connect other devices P Q User s Manual TQMa53 UM 200 2013 TQ Group Page 3 1 8 Naming of signals A hash mark at the end of the signal name indicates a low active signal Example RESET If a signal can switch between two functions and if this is noted in the name of the signal the low active function is marked with a hash mark and shown at the end Example C D If a signal has multiple functions the individual functions are separated by slashes when they are important for the wiring The identification of the individual functions follows the above conventions Example WE2 OE 1 9 Further applicable documents presumed knowledge e Specifications and manual of the used modules These documents describe the service functionality and special characteristics of the used module incl BIOS e Specifications of the used components The manufacturer s specifications of the used components for example
37. ignals 14 Table 13 GPC SIC E 15 Table 14 MIOQES 16 Table 15 SIGMA IEEE MIENNE 16 Table 16 TOUCH signals M 16 Table 17 WEIM signals Table 18 Camera SensorInterface signals testet tette He HHHEHPEHTEHEHE HEU HUE ERE TE HE EVER TERR EEHL OUR 18 Table 19 Parallel display signals sssssssssscssscssecsssssssecsecsscssasecssecsseessccessecssecssecessccssecsucceaeessecsucesseceaseessecsucceasecssecsucceaeeeaseesseesaceeaeeseeess 18 Table 20 Display control Signals m 18 Table 21 LVDSO 19 Table 22 LVDS1 signals 19 Table 23 VGA signals 19 Table 24 CANI CAN2 signals 20 Table 25 EIR 57 H m 20 Table 26 2C2 SION P E 20 Table 27 I2C2 address distribution 20 Table 28 125 Table 29 1 Wire signal Table 30 SATA E TERIS Table 31 SB a o YE Table 32 CSPI signals Table 33 ECSPI signals Table 34 UARTI signals Table 35 UL VIPEISnEI Table 36 UARTS3 signals Table 37 MS Bes SUCHIN AS Table 38 USB_OTG CEIS TAT CIA Table 39 USB Port Power Control Table 40 Reset nc Table 41 Parameter module supply
38. ignals are available at the module connectors for control of the displays The following table shows the signals used Table 20 Display control signals Signal name Direction Remark LCD_POWER_EN O LCD Power Enable Output GPIO LCD_RESET O LCD Reset Output GPIO LCD_BLT_EN O LCD Backlight Enable GPIO LCD_CONTRAST O LCD Contrast Output PWM la User s Manual TQMa53 UM 200 2013 TQ Group Page 19 3 2 11 4 LVDS The i MX53 has two integrated LVDS display bridges which are routed to the module connectors The following table shows the signals used by the LVDSO interface Table 21 LVDSO signals Signal name Direction Remark LVDSO CLK P LVDSO LVDSO TX 3 0 P O LVDSO TX 3 0 N 0 The following table shows the signals used by the LVDS1 interface Table 22 LVDS1 signals Signal name Direction Remark LVDS1_CLK_P O 1051 0 LVDS1 TX 3 0 P LVDS1 TX 3 0 6 3 2 11 5 VGA The i MX53 has a VGA port which is routed to the module connectors The following table shows the signals used by the VGA interface Table 23 VGA signals Signal Direction Remark TVDAC_IOR AO TVDAC IOG AO TVDAC_IOB AO HSYNC i MX53 signal IPU_DI1_PIN4 VGA_VSYNC O i MX53 signal IPU_DI1_PIN6 la User s Manual TQMa53 UM 200 2013 TQ Group Page 20 3 2 12 Serial
39. interfaces The supported standards transmission modes and rates of the following interfaces are to be taken from the Freescale Reference Manual 1 3 2 12 1 CAN The i MX537 provides two integrated CAN controller The signals of both CAN controllers are made available at the module connectors The drivers have to be integrated on the carrier board The i MX535 does not provide CAN For this reason the CAN functionality is not available in the pin multiplexing The following table shows the signals used as well as their characteristics Table24 CAN1 CAN2 signals Signal Direction 1_ 1_ O CAN2_RXCAN 2_ O 3 2 12 2 FIRI The i MX53 provides a Fast Infrared Interface which is routed to the module connectors The following table shows the signals used as well as their characteristics of the Fast Infrared Interface FIRI Table 25 FIRI signals Signal name Direction Remark FIRI_RXD FIRI_TXD 0 32 123 2C The i MX53 provides three interfaces The interfaces 2 2 and I2C3 are available at the module connectors The following table shows the signals used as well as their characteristics Table 26 12 2 signals Signal name Direction Remark I2C2 SCL 1 4 7 PU to 3 2 V TOMa53 2 2 SDA 1 4 7 to 3 2 V TOMa53 12C3_SCL 2 SDA
40. l Series resistor 100 Q and capacitor 1 uF to GND on the TQMa53 USB_OTG_ID A third USB High Speed interface can be implemented with ULPI PHY provided by the carrier board The USB HOST3 ULPI signals are multiplexed with signals of the Camera Sensor Interface 0 CSIO These are only available if CSIO is not used The TQ BSP does not support Port Power Control If Port Power Control should be used the signals can be provided by pin multiplexing The following table shows the possible pin multiplexing Table 39 USB Port Power Control Signal Connector Signal name i MX53 ball X2 39 CAN2 TX E5 USBOTG OC X1 34 GPIO3 GPIO21 V3 X2 41 CAN2_RX E6 USBOTG_PWR X1 33 GPIO3 GPIO21 W2 X2 61 GPIO1 GPIO3 A6 USBH1_OC X1 73 DISP1_DAT21 W4 X2 49 125 C8 UBH1_PWR X1 86 DISP1_DAT20 W5 la User s Manual TQMa53 UM 200 2013 TQ Group Page 25 3 213 Reset The following reset inputs or outputs are available at the module connectors of the TQMa53 The following block diagram shows the wiring of the reset signals MC34708 NVCC_RESET RESETMCU RESET Illustration 10 Block diagram Reset The following table describes the reset signals which are available at the module connectors Table 40 Reset signals Signal name Direction Remark Reset input of the i MX53 System Reset Controller Generates WARM
41. ntive measures were planned on the TOMa53 Following measures are recommended for a carrier board Generally applicable Shielding of the inputs shielding connected well to ground housing on both ends e Supply voltages Protection by suppressor diode s e Slow signal lines RC filtering perhaps Zener diode s e signal lines Integrated protective devices e g suppressor diode arrays 6 3 Operational safety and personal security Due to the occurring voltages lt 5 V DC tests with respect to the operational and personal safety haven t been carried out 6 4 Climatic and operational conditions Permitted component temperature 0 70 C commercial 25 C to 85 C industrial MCIMX537 20 C to 85 C industrial MCIMX535 e Permitted storage temperature 40 C to 85 C Relative air humidity operation storing 10 96 to 90 96 not condensing e Protection class IPOO The CPU belongs to a performance category in which a cooling system may be essential in certain applications It is the responsibility of the customer to define a suitable cooling method depending on the specific mode of operation e g dependence on clock frequency stack height airflow and software User s Manual TOMa53 UM 200 2013 TQ Group Page 35 6 5 Reliability and service life No detailed MTBF calculation has been done for the TOMa53 The TOMa53 is designed to be insensitive to vibration and impact
42. ped according to the requirements of electromagnetic compatibility EMC Depending on the target system anti interference measures may still be necessary to guarantee the adherence to the limits for the overall system Following measures are recommended e Robust ground planes adequate ground planes on the printed circuit board sufficient number of blocking capacitors in all supply voltages e Fastor permanent clocked lines e g clock should be kept short avoid interference of other signals by distance and or shielding besides take note of not only the frequency but also the signal rise times e Filtering of all signals which can be connected externally also slow signals and DC can radiate RF indirectly Because the TOMa53 is a module which is used on an application specific carrier board EMC or ESD tests only make sense for the whole device The TOMa53 it designed to pass the following test e EMCnterference radiation Measurement of the electrically radiated emission for standard residential commercial and light industrial environments in the range of 30 MHz to 1 GHz according to DIN EN 61000 6 3 respective DIN EN 55022 6 2 ESD In order to avoid interspersion on the signal path from the input to the protection circuit in the system the protection against electrostatic discharge should be arranged directly at the inputs of a system As these measures always have to be implemented on the carrier board no special preve
43. pixel CSIO is routed to the module connectors The following table shows the signals used as well as their characteristics of the Camera Sensor Interface CSI Table 18 Camera Sensor Interface signals Signal name Direction Remark IPU_CSIO_PIXCLK Camera Sensor Input Clock IPU CSIO HSYNC Camera Sensor Input Horizontal Sync IPU CSIO VSYNC Camera Sensor Input Vertical Sync IPU CSIO D19 4 Camera Sensor Input Data CSIO DATA EN Camera Sensor Input Data Enable CCM CSIO MCLK Camera Sensor Output Master Clock CSIO_PWDN Camera Sensor Output Power Down GPIO CSIO_RST O Camera Sensor Output Reset GPIO 32112 DISP1 The i MX53 has two parallel Display Interfaces max 4096 x 2048 pixel DISP1 is routed to the module connectors Information to different types of displays and supported formats can be taken from the Freescale Reference Manual 1 The following table shows the signals used by the DISP1 Table 19 Parallel display signals Signal name Direction Remark DISP1_DAT 23 0 O Display Output RGB Data DISP1_HSYNC O Display Output Horizontal Sync i MX53 Signal PIN2 DISP1 VSYNC O Display Output Vertical Sync i MX53 Signal IPU_DI1_PIN3 DISP1 CLK O Display Output Clock i MX53 Signal IPU_DI1_DISP_CLK DISP1 DRDY DE 6 Display Output Data Enable i MX53 Signal PIN15 3 2 11 3 LCD control The following additional s
44. plications Processors for Consumer Products 4 1 2012 02 Freescale 4 Chip Errata for the i MX53 2 2012 01 Freescale 5 Power Management Integrated Circuit PMIC for i MX50 53 Families 7 0 2011 10 Freescale 6 MC34708 Silicon Errata 5 0 2012 04 Freescale 7 i MX53 System Development User s Guide 1 2011 03 Freescale 8 4270 Supply Current Measurements 0 2011 07 Freescale TQ Systems GmbH A hlstra amp e 2 Gut Delling 82229 Seefeld ata group com www tg group com Technology in Quality
45. ply voltage of 5 V and the 3 2 V I O voltage of the CPU signals is generated on the TQMa53 One of following two possibilities must be implemented on the carrier board 1 The supply voltage of 5 V for the TOMa53 and the carrier board supply of 3 3 V are applied at the same time 2 The 5V supply voltage for the TOMa53 is present and the carrier board supply of 3 3 V is activated via module pin VCC2V775 After activation the voltage must be stable within 12 ms The following illustration shows the control of a voltage regulator on a carrier board using VCC2V775 Carrier board DCDC 3V3 12ms VIN 5 V ENA 5 VCC2V775 Illustration 11 Block diagram power supply carrier board With the procedure described above it is certified that the pull ups on the carrier board are already supplied with voltage when the boot configuration pins are read gt In case the LCD bus signals or the matching multiplexed signals representing the boot configurations pins are not used the reference voltage VCC2V775 available at the module connector can also be used as a pull up voltage for the configuration resistors No I O pins of external components may be driven during the boot process to avoid cross supply and errors in the power up sequence 3 2 14 3 signals CPU communicates with the via I2C2 gt Thel Caddress of the PMIC is 0x08 050001000 The following table
46. requency 24 MHz DA3 DISP1 DAT6 BOOT CFG2 Reserved n a n a BOOT CFG2 n a n a BOOT_CFG2 Security Configuration 00 Reserved 01 Open 1x Closed EIM_DA4 DISP1_DAT5 BOOT_CFG3 Reserved EIM_DA5 DISP1_DAT4 BOOT_CFG3 Reserved EIM_DA6 DISP1_DAT3 BOOT_CFG3 EIM_DA7 DISP1_DAT2 BOOT_CFG3 Port Select 00 ESDHCV2 1 01 ESDHCV2 2 10 ESDHCV3 3 11 ESDHCV2 4 EIM_DA8 DISP1_DAT1 BOOT_CFG3 DLL Override 0 Boot ROM default 1 Apply value per fuse field MMC DLL DLY 3 0 DA9 DISP1 DATO BOOT CFG3 Boot Acknowledge Disable 0 Boot Acknowledge Enabled 1 Boot Acknowledge Disabled DA10 DISP1 DRDY DE BOOT CFG3 Reserved n a n a BOOT_CFG3 Direct External Memory Boot Disable 0 Direct boot from external memory is allowed 1 Direct boot from external memory is not allowed la User s Manual TQMa53 UM 200 2013 TQ Group 11 3 2 2 Memory 3 2 21 DDR3 SDRAM On the TQMa53 DDR3 SDRAM is used Up to four DDR3 128M16 memory chips are assembled Each pair of chips has one common chip select and is together connected to the CPU with a bus width of 32 bit The 53 can also be equipped with smaller 64M16 memory chips The following block diagram shows how the DDR3 SDRAM is connected to the processor 13 0 D 31 16
47. rs The 53 is connected to the carrier board with 240 pins on two module connectors The following table shows details of the plug connector used Table 45 Plug connectors used on the TQMa53 Manufacturer number Description Package tyco Electronics 5353999 5 e 120 plug connector receptacle SMD120 e 0 8 mm pitch Vertical e Plating Gold 30 0 2 um e 40 10125 The module is held in the plug connectors with a considerable retention force To avoid damaging the modules plug connectors as well as the carrier board plug connectors while removing the module the use of an extraction tool is strongly recommended The following table shows some suitable mating plug connectors for the carrier board Table 46 X Suitable carrier board mating plug connectors Manufacturer Part number Stack Height X tyco Electronics 5177984 5 m Receptacle 7 A tyco Electronics 5179029 5 6mm 5179030 5 7mm tyco Electronics Plug tyco Electronics 5179031 5 DL A 4 2 5 e Board dimensions w x h e Stack height e Mass User s Manual TOMa53 UM 200 2013 TQ Group 55 0 x 44 0 mm see Illustration 12 15 gram 1 gram ue Ul la Page 31 oo pem Illus
48. s The EEPROM is controlled via bus 2 of the processor The write protection WP of the EEPROM is not available The following block diagram shows how the EEPROM is connected to the processor 12C2_SCL l2C2 SDA Illustration 6 Block diagram EEPROM connection The following table shows the EEPROM used Table 8 EEPROM Manufacturer Part number Capacity Temperature range STM M24C64 WDWE6TP 64 kbit 40 to 85 C gt The address of the EEPROM is 0x50 01010000 3 2 3 Temperature sensor A temperature sensor LM75A from for supervision of the module temperature is provided on the TOMa53 The sensor is placed on the top side of the module D8 in Illustration 14 The temperature sensor is connected to the bus 2 of the processor The overtemperature detection output of the sensor is not connected to the CPU The following block diagram shows how the temperature sensor is connected to the processor 1262 SCL l2C2 SDA Illustration 7 Block diagram temperature sensor connection The following table shows the temperature sensor used Table 9 Temperature sensor Manufacturer Part number Remark Temperature range NXP LM75ADP 11 bit ADC Max 3 C 55 to 125 C gt The address of the temperature sensor is 0x48 0b1001000 la User s Manual TQMa53 UM 200 2013 TQ Group Page 13 3 2 4 RTC The PMIC used provides an RTC For the backup supply of the RTC the PM
49. s the handling of electrostatic sensitive modules and or components These components are often damaged destroyed by the transmission of a voltage higher than about 50 V A human body usually only experiences electrostatic discharges above approximately 3 000 V This symbol indicates the possible use of voltages higher than 24 V Please note the relevant statutory regulations in this regard Non compliance with these regulations can lead to serious damage to your health and also cause damage destruction of the component This symbol indicates a possible source of danger Acting against the procedure described can lead to possible damage to your health and or cause damage destruction of the material used This symbol represents important details or aspects for working with TQ products gt PPP Command A font with fixed width is used to denote commands file names menu items 1 7 Handling and ESD tips General handling of your TQ products The TQ product may only be used and serviced by certified personnel who have taken note of the information the safety regulations in this document and all related rules and regulations A general rule is do not touch the TQ product during operation This is especially important when switching on changing jumper settings or connecting other devices without ensuring beforehand that the power supply of the system has been switched off Violation of this gu
50. set via different boot mode registers Therefore the i MX53 provides two possibilities Toburn internal eFuses and or To read dedicated GPIO pins The exact behaviour during booting depends on the value of the register BT FUSE SEL Default 0 FUSE SEL 0 The values in the eFuses overwritten by GPIO pins FUSE SEL 1 All boot options are defined exclusively by the values the eFuses The following table shows the behaviour of the bit BT FUSE SEL in dependence of the chosen boot mode Boot modes see section 3 2 1 3 Table 4 Boot Mode register BT FUSE SEL Boot Mode Setting BT_FUSE_SEL Recommended for 0 Boot mode configuration is taken from GPIOs Default 00 Development 1 Boot mode configuration is taken from fuses 0 Boot using Serial Loader UART USB Default 10 mE Series production 1 Boot mode configuration is taken from fuses 3 2 1 6 Pin multiplexing Depending on the configuration the pin multiplexing permits the usage of different pins for different purposes This document describes the configuration in the Standard BSP of TO Systems GmbH Many of the CPU pins permit the usage of several different configurations Please heed the notes in the i MX53 Reference Manual 1 concerning the wiring of these pins before integration start up of your carrier board Starterkit Table 5 22 Signal TOMa53 DISP1 DAT17
51. t Attention in the initial state the voltage FUSE is deactivated on the TOMa53 to prevent eFuses from being burnt by mistake Before the eFuses can be burnt the signal FUSE on GPIO2_GPIO4 must be pulled low gt The bus signals have to be separated with resistors because the GPIO pins to read the boot configuration on these bus signals See Freescale System Development Users Guide 7 gt See also section 3 2 14 2 for notes on the wiring of the configuration resistors The following table shows the pins of the boot configuration or the corresponding eFuses To boot from the internal eMMC the recommended settings are blue highlighted in the right column The settings for other boot devices are to be taken from the Freescale Reference Manual of the processor 1 la User s Manual TQMa53 UM 200 2013 TQ Group Page 9 3 2 1 5 Boot interfaces The i MX53 contains a ROM with integrated boot loader After the start the boot code initializes the hardware and then loads the program image from the selected boot device The eMMC integrated on the TQMa53 can for example be selected as the standard boot device As an alternative to booting from the integrated eMMC it is also possible to boot from one of the following interfaces e ESDHC2 e g SD card ECSPI1 e g serial NOR flash e SATA e g NOR flash The boot device and its configuration as well as different CPU settings have to be
52. table shows the signal used by the 1 Wire interface Table 29 1 Wire signal Signal name Direction Remark OWIRE_LINE 3 2 12 6 SATA The i MX53 provides a SATA controller with integrated PHY The following table shows the signals used by the SATA interface Table 30 SATA signals Signal name Direction Remark SATA RXP SATA RXM SATA_TXP SATA gt When required the SATA interface be configured as a boot device 3 2 12 7 SPDIF The i MX53 provides an SPDIF interface with transmit and receive functionality The following table shows the signals used by the SPDIF interface Table 31 SPDIF signals Signal name Direction Remark SPDIF_IN SPDIF OUT O la User s Manual TQMa53 UM 200 2013 TQ Group Page 22 3 2 12 8 SPI The i MX53 provides CSPI Configurable Serial Peripheral Interface and two ECSPIs Enhanced Configurable SPI Primarily CSPI and ECSPI1 are thereof available at the module connectors Via multiplexing the signals of the ECSPI2 are also available on other signals The signals of the module provided by the processor are made available as SPI interface 1 at the module connectors Furthermore the three Slave Selects SS 2 0 are available at the module connectors The following table shows the signals used by CSPI interface Table 32 CSPI signals Signal name Direction Remark SPI_SCLK
53. tration 12 Stack height Im 53 V 41 119 7 Illustration 13 3 For 5 mm board to board distance V EETNENETENENTEEEETENEETENEETENEETENENTEENETTNENTEEEETENEETT EI Overall dimensions bottom view User s Manual TOMa53 UM 200 2013 TO Group 4 3 Component placement MD eio We o8 MP40 Reap ng g wig m MBAS f L9 ts JJ TQMa53 0200 Illustration 14 Component placement top Pin 119 Pin 1 Pin 120 Pin 2 Illustration 15 Component placement bottom Page 32 la User s Manual TQMa53 UM 200 2013 TQ Group Page 33 4 31 Adaptation to the environment The overall dimensions length x width x height of the Minimodule 55 x 44 x 6 6 mm The maximum height of the TQMa53 above the carrier board is approximately 8 mm 4 3 2 Protection against external effects As an embedded module the 53 is not protected against dust external impact and contact 00 Adequate protection has to be guaranteed by the surrounding system 4 33 Thermal management To cool the TQMa53 a maximum of 3 W have to be dissipated as described in section 3 2 14 1 The power dissipation originates primarily in the processor the DDR3 SDRAM and the PMIC The customer is responsible for cooling the TQMa53 in his application With sufficient airflow a passive
54. ty unless specified otherwise in writing are subjected to the specifications of the current copyright laws and the proprietary laws of the present registered proprietor without any limitation One should conclude that brand and trademarks are rightly protected by of a third party 1 3 Disclaimer TO Systems GmbH does not guarantee that the information in this User s Manual is up to date correct complete or of good quality Nor does TQ Systems GmbH assume guarantee for further usage of the information Liability claims against TO Systems GmbH referring to material or non material related damages caused due to usage or non usage of the information given in the User s Manual or due to usage of erroneous or incomplete information are exempted as long as there is no proven intentional or negligent fault of TO Systems GmbH TQ Systems GmbH explicitly reserves the rights to change or add to the contents of this User s Manual or parts of it without special notification 1 4 Imprint TQ Systems GmbH Gut Delling M hlstra e 2 82229 Seefeld Tel 49 0 8153 9308 0 Fax 49 0 8153 9308 134 Email info tgs de Web http www tq group com Q User s Manual TQMa53 UM 200 2013 TQ Group 2 1 5 Tips safety Improper or incorrect handling of the product can substantially reduce its life span 1 6 Symbols and typographic conventions Table 1 Terms and Conventions Symbol Meaning This symbol represent

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