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1. 2 49 414 0 89 0 89 top_xsr34x22 x1165 aa a arises 2 0 031295 0 00 0 00 top_xsr34x22 x1170 2 0 0 00 0 00 top_xsr34x22 x1168 2 0 0 00 0 00 top_xsr34x22 x1159 BLOCK top RMS POWER LEVEL POWER PERCENT OF PERCENT OF CHILD BLOCK NAME uW PARENT TOP 0 25053 100 00 100 00 top SF aoe 1 25053 100 00 100 00 top xsr34x22 ka 2 14856 59 30 59 30 top xsr34x22 x1161 2 8329 2 33 25 33 25 top xsr34x22 x1164 a nm 2 6077 24 26 24 26 top xsr34x22 x1166 a eae 2 5702 9 22 76 22 76 top_xsr34x22 x1162 SE sees 2 4995 3 19 94 19 94 top xsr34x22 x1163 AKA 2 4796 9 19 15 19 15 top xsr34x22 x1158 Ba ere eee gt 2787 9 T143 11 13 top xsr34x22 x1167 KABA 2 2331 9 Foal 9 3 top xsr34x22 x1157 2 PAT 39 5 88 5 88 top_xsr34x22 x1160 2 1141 1 4 55 4 55 top_xsr34x22 x1169 See eee ee 2 602 31 2 40 2 40 top xsr34x22 x1165 PIE 2 9 3168 0 04 0 04 top xsr34x22 x1170 2 0 0 00 0 00 top_xsr34x22 x1168 2 0 0 00 0 00 top_xsr34x22 x1159 Appendix B Using Shared Memory Many 32 bit machines limit the virtual memory space to 2GB If you need to simulate a very large circuit that requires more than 2GB of memory you need to set the EPIC USE SHM environment variable before running PowerMill EXAMPLE setenv EPIC_USE_SHM This setting causes the simulator to allocate memory from a region that is shared by all the processes running on your ma
2. 2 81 777 5 32 Bb 32 xsr34x22 x1163 top a aa 2 57 569 3 74 3 74 xsr34x22 x1157 top a a 2 52 966 3 44 3 44 xsr34x22 x1160 top 2 42 359 2 75 2 75 xsr34x22 x1169 top 2 5 8502 0 38 0 36 xsr34x22 x1167 top Ca SETA 2 0 0086932 0300 0 00 xsr34x22 x1170 top kA ERE 2 0 0 00 0 00 xsr34x22 x1165 top a 2 0 0 00 0 00 xsr34x22 x1168 top LA 2 0 0 00 0 00 xsr34x22 x1159 top Figure 4 Sample supply current report from the power file In addition you can generate a block level waveform and current histogram for each of the sub block reports For details see the PowerMill Reference Guide and Working with Probes on page 100 Assigning Power Budgets You can use PowerMill to assign power current budgets to blocks created with the report_block_powr command and monitor those blocks for violations You will need to use the set_block_budget command to do this EXAMPLE 17 report_block_powr top set block budget max_avg_src 100uUA max_inst_src 1mA top PowerMill User Guide 94 Chapter4 Power Analysis This pair of commands creates a block labeled top which consists of the entire circuit and assigns current budgets of 100 uA for the average supply current and 1 mA for the instantaneous supply current Violations of the assigned budgets are reported as errors to the err file and reported to the power file See Appendix A for a sample power file You can assign budgets to the instan
3. Access display Access to of netlist pa analysis tools Error amp Warning messages hierarchy Figure1 PowerMill GA main window Setting Up for a Simulation 207 Setting Up for a Simulation Your next set of steps involves specifying the design data setting up multiple supply nodes and specifyi ng the blocks you want to simulate First click the Simulation Setup button to bring up a dialog box that lists a set of simulation setup forms see Figure 2 H Simulation Setu p Design Data Setup Power Diagnosis Setup Dismiss Figure 2 Simulation setup form Specifying Design Data To start specifying design data click the Design Data Setup button in the Simulation Setup form The Design Data Setup form appears Enter the following information either manually or using the Browse button when applicable Work File powrmill wrk Netlist Files adder4 ntl adder4 cmd Tech File tech typ 25c 5v Simulation Time 300 Figure 3 shows the completed form PowerMill User Guide 208 Chapter8 PowerMill Graphical Analyst Tutorial To save your changes and close the Design Data Setup form dick OK NN aaa adderd ntladderacmd Browsen Tar CE HY Cy aaa EE Give any other command line options and filenames You may use this to provide your own configuration files Figure 3 Design data setup form Setting Up the Power Supply and Blocks The next step is to set up the power supplies and sp
4. 1 Enable GAP customization by specifying the fit 3 or fit 4 option with the guide gap search configuration command Fit 3 applies a function based on the peak average value per clock cycle while fit 4 applies a function based on peak instantaneous value 2 Inan ADFMI C file create a regular C function with type double and void argument Using the GAP Feature to Estimate Maximum Power 109 The GAP estimation will use the value returned by this C function as the objective to be maximized The following table lists the types of arguments you can use to define the fitness measure in your C function Number Type Argument Name 1 Node Voltage v node_name 2 Node Logic I node name 3 Node Current inode node name 4 Pin Current ipin pin_name 5 Branch Current ibranch_num elem_name 6 Block Power p block label 7 Probe Current iprobe probe_ name 8 Math Signal m signal label EXAMPLE fmRegisterGap 1 cinl ipin xll ain v cinl p x11 m dot fitness This example specifies that a total of five arguments 1 cinl ipin x11 ain v cinl p x11 andm dot to be used in the customized objective function for PowerMill s GAP feature It also specifies fitness as the function pointer to the customized obj ecti ve function defined in the ADFMI C file You can access the value of an argument either by name usi ng the fmGapGetValueByName API function or by ID usi ng the fmGapGetValueB yl D fun
5. PowerMill s GAP Genetic Algorithm for maximum Power estimation feature combines a genetic algorithm with advanced circuit simulation techniques to efficiently search for input vectors to maximize the power dissipation of a given circuit You can use the GAP feature to generate a tight lower bound on the maximum power of a given circuit which you can use to analyze various design issues power management for example The GAP feature is able to maximize four objective functions m Average power per clock cycle of the circuit m Instantaneous power of the circuit m Average value per clock cycle of the customized fitness function m Instantaneous value of the customized fitness function The usage model for GAP customization which involves the last two object functions is illustrated in tutorial 7 For combinational circuits the maximum power instantaneous or average is produced by two vectors referred to as a vector pair applied in two consecutive clock cycles The first vector sets up states of the internal nodes of the circuit The power is measured in clock cycle ll The GAP feature keeps a specific group of vector pairs as candidates for maximizing power dissipation The quality of each vector pair is measured by the power consumption it produces Using a genetic algorithm the GAP feature repeatedly improves the quality of the vector pairs in the group that was kept generation by generation until the result is recognized b
6. Specifying Design Data 0 0 0 cc ee 207 Setting Up the Power Supply and Blocks 208 Specifying Diagnosis Checks 0 00 000 ees 213 Running the Simulation 4 0 0 00 e ee 214 Analyzing Results ea aiae ia i aa te 215 Viewing Histogram Information 216 Viewing the DC Paths 2 0 0 218 Viewing the Power Diagnostics a 219 Appendix A Sample Power Reports 223 Appendix B Using Shared Memory 229 Combined Index 22222000 000 231 NAX aaa naan ha AN r ee aa an ee 241 PowerMill User Guide X Table of Contents About This Manual The PowerMill User Guide describes how to use the PowerMill simulator to do power simulations on and analysis of integrated circuit designs For information on See A general overview of the Chapter 1 Introduction to features and capabilities of PowerMill the PowerMill simulator The basic steps for preparing Chapter 2 Getting Started initial files running a simulation and viewing the results of a PowerMill simulation Tutorials that give detailed Chapter 3 PowerMill instructions and scenarios of Tutorials how to use PowerMill Procedures for doing different Chapter 4 Power Analysis types of power analyses General information on using Chapter 5 Using the ACE the ACE feature to simulate Feature analog and mix
7. fmConfigCmd report block powr blocki1 track power 1 od AA 8 fmConfigCmd report block powr block2 track power 1 K2 Register arguments and function pointer of customized objective function fmRegisterGap p blockl p block2 fitness Figure 7 Sample custoomized objective function Performing a Dynamic Power Consumption Analysis 111 This example uses report block powr configuration command to create two block power signals which it then uses to define the customized fitness function See the following tutorials in Chapter 3 PowerMill Tutorials for more information on using the GAP feature e Tutorial 5 Estimating Maximum Power for Combinational Circuits on page 41 e Tutorial 6 Estimating Maximum Power for Sequential Circuits on page 50 e Tutorial 7 Customizing a GAP Objective Function using an ADFMI Code File on page 69 Performing a Dynamic Power Consumption Analysis This section provides an overview of the PowerMill features that can be used to identify and diagnose during the dynamic simulation conditions in your circuits that could lead to excessive power consumption Information is included on the following subjects m Dynamic Rise Fall Time Checking Detecting Dynamic Floating Nodes Z State N odes Detecting Excessive Branch Currents Analyzing Hot Spot Node Currents Detecting Dynamic DC Paths Checking Dynamic Rise and Fall Times U State Nodes There
8. leakage current wattage report creating U 90 waveform display changing R 451 waveform viewers SimWave R 418 turboWave R 418 ViewTrace R 418 239 waveforms block analysis simulation U 34 DC paths U 40 full chip power simulation U 31 maximum instantaneous power U 49 U 62 U 67 waveforms print resolution U 130 wirecap adding R 42 X X state printing R 288 Z Zstate printing R 288 reporting R 187 R 338 PowerMill User Guide 240 Combined Index PowerMill User Guide Index Symbols SEPIC HOME 13 21 137 205 dcpath file sample 39 epicrc file description 10 keywords 14 sample 15 A A command line option 132 ACE tutorials CV curve generation 139 differentiator simulation 149 integrator simulation 147 PLL SPICE macro modeling 151 156 step input simulation 145 voltage follower simulation 143 ADF MI See ADF MI Manual analog circuit simulation 125 134 137 158 aspd 129 autodetection selection 125 automatic memory 229 automatic techfile generation 12 automatic vector generation 103 Seealso GAP feature batch mode 10 block power analysis 31 87 88 90 91 branch Seedement BSIM1 models 13 BSIM2 models 13 BSIM3 v3 models 13 C chip level power analysis 85 command line options A 132 comment line in epicrc file 15 configuration commands assign_branch_i 100 122 assign_node_i 100 122 limit_dcpath_search 115 242 Index print branch i 122 print node i 86
9. limit PowerMill User Guide 108 Chapter4 Power Analysis e Usethep size option to specify the population size used by the genetic algorithm Acceptable val ues for population size are any integers between 20 and 50 A larger population size tends to generate a better larger estimate with a longer CPU time The default valueis 20 4 During the estimation you can use the report gap progress interactive command to retrieve information on the progress of the simulation and display it in either a table or a graph At the end of the GAP estimation PowerMill automatically generates a gap summary file and one or more history files gav The input vectors used during the simulation are kept in the history files which can then be used as normal vector files in another simulation using the nvec PowerMill command line option 5 You can use the report gap parameters interactive command to show the current settings for all of the GAP commands Creating a Customized Fitness Function For a GAP estimation you can specify one of four types of fitness functions using the fit option of the guide gap search command Types 1 and 2 are based on the peak average power per clock cycle and peak instantaneous power respectively of the whole circuit These functions are built into the software In addition you can use types 3 and 4 to apply a customized objecti ve function defined in an ADFMI C file To create a customized objective function
10. nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys the Synopsys logo AMPS Arcadia CMOS CBA COSSAP Cyclone DelayMill DesignPower DesignSource DesignWare dont use Eagle Design Automation Eaglei EPIC ExpressModel Formality in Sync Logic Automation Logic Modeling Memory Architect ModelAccess ModelTools PathBlazer PathMill PowerArc PowerMill PrimeTime RailMill SmartLicense SmartModel SmartModels SNUG SOLV IT SolvNET Stream Driven Simulator Synthetic Designs TestBench Manager and TimeMill are registered trademarks of Synopsys Inc Trademarks ACE Behavioral Compiler BOA BRT CBA CBAII CBA Design System CBA Frame Cedar Chip Architect Chronologic CoreMill DAVIS DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus Design Advisor Design Analyzer DESIGN ARROWS Design Compiler DesignTime DesignWare Developer Direct RTL Direct Silicon Access dont_touch dont_touch_network DW 8051 DWPCIl Eagle EagleV ECL Compiler ECO Compiler Falcon Interfaces Floorplan Manager Foundation FoundryModel FPGA Comp
11. spi SPICE netlist of the sequential circuit a segment of a datapath with two pipelined stages to be estimated max seq power vec Vector file to be used for maximum power estimation run max seq power Run script for maximum power estimation of sequential circuits tech typ 25c 5v Technology file runpm Run script for latch detection by PathMill cfgpm Configuration file for latch detection using PathMill Advanced PowerMill Simulations 55 Procedure Use the following procedure to run the tutorial on estimating maximum power for sequential circuits 1 Open and study the cfg_max_power configuration file The following file sample shows the contents of this configuration file use_vec_gap vec max_seq_power vec set_gap_opt period 40ns save_history on vec_history 1 guide_gap_search fit 2 level 7 set_ckt_cmd d ff mark_node_latch no q print_probe_i inst gap total_power report block powr stagel track_power 1 x1 report_block_powr stage2 track power 1 x2 report block powr ff array track power 1 xd report probe i avg stagel total power report probe i avg stage2 total power report probe i avg ff array total power report probe i avg gap total power Each linein this fileis critical to the function of the GAP feature E use vec gap vec max seq power vec This line specifies the vector files for the GAP simulation The GAP function generates a history file as the simulation progresses
12. transistor IOBUFFO P1 type PMOS current 119 91 uA gate IOBUFFO INGATE voltage 0 00 V drain IOBUFFO OUT1 voltage 5 2010 y source IOBUFFO DP1 voltage 5 00 V transistor IOBUFFO P2 type PMOS current 119 93 uA gate IOBUFFO PGATE voltage 0 00 V drain IOBUFFO DP1 voltage 5 00 Vv source EVDD voltage 5 00 V inductor IOBUFFO L1 current 119 93 uA voltage 5 00 V Figure 9 Sample DC path report Performing a Static Power Consumption Diagnosis This section provides an overview of the static power diagnosis features available in PowerMill You can use these features to analyze your circuit based on its topology and look for conditions that might lead to excessive power use They are intended to provide an alternative to the dynamic power diagnosis when dynamic simulation requires too much simulation time and you want to scale down power consumption These analyses are Performing a Static Power Consumption Diagnosis 117 performed before the dynamic simulation begins and generally require significantly less simulation time than a full dynamic simulation This section includes information on the followi ng subjects m Detecting Static DC Paths m Static Excessive Rise Fall Time Detection Detecting Static DC Paths A static DC short circuit path exists if a node has a static conducting path to VDD and a static conducting path to GND Each node in both paths are in a fighting condition at all times Use the report_c
13. wasted power 88 See also leakage current wattage report creating 90 waveforms block analysis simulation 34 DC paths 40 full chip power simulation 31 maximum instantaneous power 49 62 67 waveforms print resolution 130 245 PowerMill User Guide 246 Index
14. 340 power R 147 R 152 R 161 R 172 R 176 R 181 R 185 R 187 diode modeling R 368 double precision mode R 4 U 132 dynamic power analysis U 111 E EDIF netlist format R 8 edisplay utility R 417 element current printing U 98 excessive current check R 161 getting status R 61 R 65 name R 97 printing branch currents U 98 printing current R 109 R 119 reporting current R 145 See BJ T Seediode See MOSFET simulating R 369 R 371 R 374 element names listing by index R 97 environment parameters R 3 environment variables command R 215 EPIC netlist format R 8 PowerMill User Guide 234 Combined Index EPIC HOME environment variable U 21 U 205 epicrc file See epicrc file U 15 errors ckt handling R 82 errors simulation suppressing R 92 R 93 R 237 estimating max power See maximum power estimation esv for analog simulations See a6sv setting node R 251 setting simulation R 297 event generation changing R 451 event resolution voltage analog See a6sv digital See esv event resolution voltage esv setting U 128 Eview utility R 418 evp event points setting R 308 F file samples epicrc file U 15 powrmill act file R 422 powrmill cnt file R 434 powrmill dcpath file R 407 R 446 powrmill gap file R 444 powrmill gav file R 445 powrmill hist file R 412 R 447 powrmill log file R 423 powrmill log file block power report R 438 powrmill nad file R 422 powrmill nodealias file R 436 powrmill out file
15. 5 BP PH AD Sook D Figure 8 Excerpt from block power reports in block1 log file block2 log Figure 9 shows a portion of the block power reports printed in the block2 1 0g file This particular excerpt provides a block power report for the x1 block and was generated by the following command report block powr xl track src 1 track gnd 1 x1 The report generated by this command lists the contents of and partitioning information for the reported block This information consists of the number of stages used the number of nodesin the block and the total number of elements in the block PowerMill User Guide 36 Chapter3 PowerMill Tutorials This report also provides a detailed analysis of the current contributions from different parts of the circuit inputs outputs and bidirectional ports etc Block x1 Number of nodes in block 18 Number of elements in block 41 Number of block supply nodes 1 Number of block ground nodes 1 Number of block biput nodes 1 Number of block input nodes w 2 Number of block output nodes 5 0 Number of block stages 1 Number of block partial stages I Average supply current 59 873924 uA RMS supply current 313 624995 uA Average ground current 61 049494 uA RMS ground current 311 347667 uA Average input current 0 000000 uA RMS input current 0 000000 uA Average output current 0 000000 uA RMS output current 0 000000 uA Average biput current 1 172278 uA RMS biput cu
16. GAP s time window with the clock you need to specify the delay option with a value of 100 ns with the set gap opt command In addition to address the clock to Q time you would have to set the delay option of the set_vec_opt command to 0 5 ns Open and study the max seq power vec vector file Notice that this file contains only the PI signals therefore the mark node latch command is used to generate a vector file containing PPIs and add it to the GAP estimation automatically Run the simulation using the run_max_seq_power script The autodetection simulation stops and restarts with the following message Reading configuration files PPI dumping has been completed Adding vec file maxpower ppi vec to GAP and restarting GAP estimation When you see that the simulation has progressed somewhere beyond generation 4 type Cont rol c to stop the simulator in interactive mode 6 Type quit to quit the simulation List the directory contents 10 Advanced PowerMill Simulations 59 Notice that the GAP feature automatically saved a file with a name for similar to maxpower save 7200 000000ns Z for generation 3 which improved the maximum power You can use this compressed file to restart the GAP run from where you stopped it Torestart restore the simulation from where you stopped it add the following command to the configuration file restore_ckt_state 7200ns Start the simulation again using the run_max_seq_
17. GAP vector file can have one of three different input output types i input b biput and p pseudo primary input Open the cfg max power file Comment out the following line set ckt cmd d ff mark node latch no q Add the pathmill ppi vec file generated by PathMill to the PowerMill GAP simulation using the vec option of the use vec gap command use vec gap vec max seq power vec vec pathmill ppi vec Add the following command to the cfg_max_power file to verify the functionality of the FFs or latches print node logic s1 d Add the max gen 1 option to the end of the guide gap search command specification guide gap search fit 2 level 7 max gen 1 Setting themax gen option to 1 forces the GAP simulation to stop after one generation This circuit contains only one type of FF and the s1 and d nodes are the inputs and outputs for the FFs Run the simulation using the run_max_seq_power script After the simulation stops type quit to get out of interactive mode and the simulation Advanced PowerMill Simulations 67 10 Load the maxpower out file in turboWave and view the two bus signals d 3 0 and s1 3 0 File Signal View Waveform Analog Tools Window Help 2 5 8 DE _ es3 Ca v2 Figure 19 Waveform of bus signals d 3 0 and s1 3 0 in the maxpower out file For the first vector triplet the value of s1 3 0 at the end of clock cycle c is equal to the value of
18. GN DL In addition its substrate is connected to a voltage source of voltage GN DH where GN DH is greater than GNDL PowerMill reports any problems it detects to the err file For details of the syntax of these reports see Chapter 7 Utilities for Dynamic EPIC Tools in the EPIC Tools Reference Guide Static Excessive Rise Fall Time Detection A large transient short circuit current might occur if the voltage rise fall transition time for a node is excessive You can use the report node maxrf command to report nodes with worst case transition times that exceed a specified threshold time The node rise fall time is the time taken for the node to make the transition between its high and low logic thresholds This time is estimated based on the lumped capacitance for the node and the maxi mum impedance driving it By default the logic high and low thresholds are set to 70 and 30 respectively of the node s high voltage You can adjust these default levels using the set node thresh command PowerMill reports any problems it detects to the err file For details on the syntax of these reports see Chapter 7 Utilities for Dynamic EPIC Tools in the EPIC Tools Reference Guide Analyzing Power Using the RC and UD Simulation Modes TheRC and UD modes provide a fast power estimation for digital CMOS circuits In most digital circuits major power contributions come from switching activities Therefore the RC and UD modes wh
19. Hierarchy Browser to exit the Hierarchy Browser 5 Click OK in the Power Supply amp Block Setup form to save your changes and exit the form Specifying Diagnosis Checks PowerMill will check only those conditions you specify To set the diagnosis checks click the Power Diagnosis Setup button in the Simulation Setup form The Power Diagnosis Setup form appears see Figure 7 Power Diagnosis Setup Static Power Checks Report static paths Report nodes whose rise fall time exceeds 5ns Excessive Current Find DC paths at times l report paths gt 0 05mA W Find DC paths starting at Ons and every 50ns W Show transistors whose current is greater than 5mA and lasts longer than 2ns Tristate Check W Report nodes that are undriven longer than 5ns Report Hazards W Report nodes with multiple transitions within any 40ns period Power Distribution Report power histogram starting from Dns to 300ns generate 10 segments Help Message Show Clear Default Cancel Figure 7 Power Diagnosis Setup form PowerMill User Guide 214 Chapter8 PowerMill Graphical Analyst Tutorial By default all the checks on the form are sel ected However in order to check for DC paths you must specify the appropriate time segments Enter the following value in the Static Power Checks area Report nodes whose rise fall time exceeds 8ns Next activate the Excessive Current chec
20. Power Diagnostics Browser appears see Figure 12 To display a particular set of errors you ll first need to select an error type in the form For this design select the following error categories e Excessive Rise Fall Time e Undriven Nodes e Excessive Transistor Current e Multiple Transitions Click the Show Errors button to display the errors you selected To view Specific nodes you can copy and paste node names from the list at the bottom of the window Use the left mouse button to select the ADDERO XOR2A N 4 node Next use the middle mouse button to drag the node name to the text field above the Show Errors button Click the Show Errors button to list only the errors that occurred on that node To exit the Power Diagnostics Browser select File Close Power Diagnostics Browser PowerMill User Guide 220 Chapter8 PowerMill Graphical Analyst Tutorial Power Diagnostics Browser File Help Static Paths W Excessive Rise Fall Time 0 6 W Node Does Not Settle To Rails 0 W Undriven Nodes 6 2 M Excessive Transistor Current W Multiple Transitions 28 Show errors beginning at time 2 00 and ending at time 300 00 and onlyon nodes Show Errors Reset Node Error E ADDERO XORZB NA a Rise Fall time of node exceeds limit ADDER1 XORZA N 4 Estimated Rise Fall time of node exceeds limit 0 ADDER1 XORZ2B N 4 Estimated Rise Fall
21. R 281 J J FET models U 13 K keepers removing R 204 Kirchhoff s Current Law U 99 L latch nodes R 101 leakage current detecting DC paths U 115 235 finding cause R 147 R 152 measuring R 140 U 88 listing R 100 log file closing R 47 opening R 108 logic diagrams adder circuit with four bit output register U 27 cell of four bit adder circuit U 20 four bit adder circuit U 19 xor2 cell U 20 logic states forcing R 51 printing R 128 releasing R 138 logical display R 418 maximum power estimation R 78 R 163 R 164 R 165 R 232 R 336 U 41 U 103 Seealso GAP feature memory freeing R 54 merging parallel transistors R 104 MESFET models U 13 messages limiting by index R 92 limiting by phase R 93 mixed signal simulation U 125 model swapping R 324 Seealso ADF MI Manual models directly supported BSIM1 U 13 BSIM2 U 13 BSIM3 v3 U 13 J FET U 13 MESFET U 13 MOS9 U 13 MOSFET changing size R 199 R 200 R 240 PowerMill User Guide 236 Combined Index R 241 R 243 R 244 R 246 R 247 getting status R 65 modeling R 364 R 366 R 369 R 370 R 371 R 373 R 374 R 381 R 397 R 398 R 399 R 400 R 401 partitioning R 88 R 89 R 204 R 245 R 396 simulating R 242 multirate simulations ACE U 130 N netlist file compressed R 8 formats U 11 specifying R 8 specifying format R 8 types of stimulus U 13 netlist file setting text case R 335 NMOS U 118 NMOS transistors R 88 node active
22. U 94 in hierarchical netlists U 91 measuring true power in watts U 90 power analysis accuracy R 275 R 285 R 290 block level R 43 R 45 R 140 block level U 31 estimating maximum power U 41 full chip U 29 U 85 max power estimation R 78 node level R 126 R 180 printing branch currents U 98 RC UD mode U 119 static leakage paths U 79 power diagnosis dynamic U 111 static U 116 power estimation max R 78 R 163 R 164 R 165 R 232 R 336 PowerMill environment graphic U 9 powrmill command U 10 U 23 command line options R 3 R 11 PPI detection R 101 print resolution of waveforms U 130 printing command descriptions R 55 current waveforms R 119 R 126 R 134 digital state printing options R 288 stage information R 76 voltage waveforms R 131 printing command descriptions R 121 printing windows R 286 R 292 probes creating R 43 R 45 R 140 U 87 U 88 237 U 90 U 91 U 100 printing current R 134 U 100 reporting current R 72 R 189 prompt interactive setting R 215 PWL simulation mode R 256 R 295 R 300 R RC full delay simulation mode R 257 U 119 reporting U state R 185 Z state R 187 resistor setting value of R 296 resolution current R 299 return codes R 11 S saving partition information R 198 scripts creating U 16 separator hierarchical setting R 298 short circuit current See leakage current simulation control R 34 R 369 R 371 R 374 R 380 global time step control R 391 global voltage sens
23. and x1 x2 but not the first level sub blocks In each case the specified level refers to the absolute level in the circuit hierarchy and is not relative to the level of the specified pattern EXAMPLE 3 report block powr my block at level 4 x1 x2 This command generates a power report for thex1 x2 x sub block and its fourth level hierarchal sub blocks such as X1 x2 x3 x4 For each sub block generated using the level or at_level options PowerMill writes a standard block power report to the Jog file In each case the reporting options will be the same as the top level block In addition when either option is used the simulator writes a hierarchical power report for the specified block hierarchy to the power file The file sample in Figure 4 shows a report for the total supply current as printed tothe power file PowerMill generates a similar report for the ground supply biput wasted currents and the power if those quantities are being tracked Analyzing Power Consumption 93 BLOCK top AVERAGE SUPPLY CURRENT LEVEL CURRENT PERCENT OF PERCENT OF CHILD BLOCK NAME uA PARENT TOP aaa 0 1537 8 100 00 100 00 top 1 1537 8 100 00 100 00 xsr34x22 top HA aa 2 35983 23 40 23 40 xsr34x22 x1161 top maa a 2 322 71 20 98 20 98 xsr34x22 x1164 top ka 2 214 54 13 95 13 95 xsr34x22 x1166 top 2 207 33 13 48 13 48 xsr34x22 x1158 top ta aaa 2 192 92 12 55 t255 xsr34x22 x1162 top
24. any time 2 Click the Clear button if you want toclear all information on the form 3 Click the Cancel button if you want to close the form without saving your changes Power Supply Setup 173 Power Supply Setup Use the Power Supply amp Block Setup form to assign alternate voltages to the supply nets 1 Inthe Simulation Setup form click the Power Supply amp Block Setup button Figure 5 shows the Power Supply amp Block Setup form Power Supply amp Block Setup Form O IT aaa OO O a o o m rove ADDER IT a OO a o o Pover Supply Setup Use this form to indicate the different power supplies i e VCC VDD GND etc their voltages and whether or not they are Power or Ground nodes Use the right mouse button to bring up a popup which allows you to select between power ground Note that only the power supplies listed here are read as a default The interface makes an effort to identify some of the power supplies for you but it may not be a comprehensive list Figure 5 Power supply amp block setup form Thetop section of the Power Supply amp Block Setup form identifies the supply nets and voltages for each block of the circuit you want to simulate T he setti ngs that appear in the PowerMill User Guide 174 Chapter7 Using the PowerMill Graphical Analyst Voltage column are specified in the technology file or from a previously saved modification You can modify the voltage for any net The GND is automatically
25. apply the Synchronous Matrix Solver SMS model to specified elements m set elem sync Use this command to apply the synchronous simulation algorithm to specified elements Both the set elem sync command and the set elem sms command apply the synchronous mode However they use different models the set elem sync command uses a simplified region dependent gate capacitance model for MOS transistors at linear saturation and cut off regions while the set elem sync command uses a voltage dependent gate capacitance model In addition the set elem sms command PowerMill User Guide 132 Chapter5 Using the ACE Feature models the crosstalk Miller effect between gate and drain or source terminals Usually the autodetection algorithm applies these commands as needed However there are situations when you might want to apply them manually for example when you need precise accuracy in digital circuits You could use this technique for example when simulating an inverter ring oscillator Activating Double Precision Mode You can start the double precision version of PowerMill for voltage and current using the A command line option Under normal conditions you won t need to use double precision H owever in some cases double precision could be necessary F or example highly damped PLLs with slow lock times low static phase error and low jitter requirements usually need to be simulated in the double precision mode Very high gain
26. at 0 jreport ckt leak el partial off n partial off p report ckt leak el n path p path j report ckt leak el nc vdd nc gnd ireport ckt leak el forward bias n forward bias p report ckt leak el set node thresh 0 5 2 5 v 1 gnd vdd Figure 27 Contents of the cfg static file 2 Run the simulation using the run static script 3 When the simulation is finished list the directory contents Notice that the directory now contains several output files with the static prefix 4 Open the static log file and notice the number of errors reported in the err file 5 Usethe viewerror utility to view the errors reported in the staticerr file Viewerror i static err o all error Theall error file should list 25 errors This file lists the type of error followed by a brief description of why the error occurred It also lists the transistors that are present in the static leakage path 6 Study each type of error and go back to the netlist and figure out why they are occurring Also try to match the topologies PowerMill User Guide 82 Chapter3 PowerMill Tutorials present in the netlist with those detailed in the reference guide NOTE The set node thresh command is important and should be used while doing static leakage analysis This is because the static analysis uses the node voltages and logic thresholds for the constant voltage source nodes to identify which nodes are ground and which nodes are supply VDD Althou
27. cat cfg3 bl 1 ock ock ock cat cfg_dcpath cat cfg max power Tutorial 2 Performing a Full Chip Power Analysis This tutorial shows you how to determine the power consumption of a complete circuit or full chip In this case the full chip is a small adder circuit with an output register A small circuit is used in these tutorials so that simulations finish quickly Files Needed for this Tutorial The followi ng table lists the input files needed for this tutorial These files are located in the pw advanced full chip subdirectory in your working directory Filename adder cmd Description EPIC format netlist file that describes the filename for the vector file and the node names and port ordering for the vector file adder vec Tabular digital vector file used as the digital stimulus for the simulation cfg full Configuration file for full chip power analysis full spi SPICE netlist for full chip power analysis PowerMill User Guide 30 Chapter 3 PowerMill Tutorials Filename Description run full Run script for full chip power analysis tech typ 25c 5v Technology file Procedure Use the following procedure to run the full chip analysis tutorial 1 Using the UNIX cat command look at the contents of the cfg full configuration file The following file sample shows the contents of this configuration file print node logic print node v Power reports fo
28. command to apply the trapezoidal integration This command is intended for use with LC circuits and inductors where free oscillations should not be suppressed or damped This is critical for crystal oscillator models that use an RLC model Theset sim trap command allows these to start up normally If the default Euler integration method is used the crystal oscillator will not start because the free oscillations are damped out The set_sim_trap command will not work for very high Q crystals such as a 32 KHz crystal model This is due to the very high equivalent inductance very small equivalent capacitance and high equivalent series resistance Files Needed for this Tutorial The following table lists the files needed for this tutorial They are located in the crystal_osc directory You were instructed at the beginning of this chapter to copy this directory from SEPIC HOME tutorials ACE Filename Description cfg1 cfg2 cfg3 Batch run configuration files crystal_oscspi SPICE netlist for the crystal oscillation simulation run1 run2 run3 Run scripts for the crystal oscillator simulation cmos35 mod BSIM3 v 3 model file Procedure Use the following procedure to run the crystal oscillator tutorial 1 Run the simulation using the run1 script Getting the Input Files 157 This case uses the default mode and will run very fast because the oscillator will not start You will see the normal biasing curve as the inv
29. current tristate hazard and power distribution checks for the simulation PowerMill will check only those conditions you set see Figure 6 Enter threshold values in text fields Enter default setting in form mz Figure 6 Power diagnosis setup form The followi ng steps provide the basic procedure for using the Power Diagnostics Setup form 1 Click on the Power Diagnosis button in the Simulation Setup form The Power Diagnostics Setup form will appear Power Diagnosis Setup 177 2 Select the checks you want by clicking the appropriate toggle buttons located on the left side of the form Thecheck is active when the button is red and contains a black check mark Many checks require you to enter threshold values in text fields 3 Click the Default button at the bottom of the form to select the default power diagnosis checks The Clear button de selects all checks Static Power Checks There are two buttons you can click in the Static Power Checks section of the Power Diagnosis Setup form These buttons have the following functions m Report static DC paths checks for circuit topologies that are likely to cause unwanted power consumption For example the settings in Figure 9 will catch circuits with no paths to VDD or GND m Report node whose rise fall time exceeds checks for nodes with rise fall times that exceed a specified time Excessive Current The Excessive Current section lets you specif
30. eek ee pe be ee ee ed 183 View Menu 2 riist En ean BANNER ERA weed 183 Options Menu 0 00 es 185 DC Path Browser eiie a a he ma eh a ee Sed 186 File Menu perentorio 2a et etee ade e eee oi aes 187 Option Menu 2 0 0c es 187 Analyzing DC Paths a 187 Standalone Version of DC Path Browser 189 Power Diagnostics BrowSer 00 0000 a 189 Selecting Checks 0 0 00 cee eee 191 HileMETU na pawa iat See eet ee Ga i ace we aed 193 Waveform Tool 2 2 es 193 Hierarchy Browser 0 00000 cece eee 193 File MENU ahh Glee a a oe Se 194 Hierarchy Display 0 000 194 Panning Display 0 0 0 0 cee eee ee 195 Thee Display kaaa sete sek wey ead ede oes 195 SHOW ATO sas paaa haa eaa eS ee beatae ads Belay 196 OPtlOnS ska Panaad Bd dal eG alee nek ERROR RAHE 196 Show Internal Nets 0 0a 196 Show Instructions 0 0 0 cece eee eee eens 196 Ordering Instance Information 00000 196 Set Expansion Threshold a 197 Select Instances to Display 0005 198 Displaying Connectivity eee 199 Dragand Drop is son Gaia en NG NARRA ha eb wie eect 200 8 PowerMill Graphical Analyst Tutorial OVERVIEW kak pons tae hi Wi id ee re ee ace de chew ae Beta 205 Getting the Input Files 2 0 ee 205 Starting the Graphical Analyst 0 00000 cc eee ee 205 Setting Up for a Simulation 0 000000 ee 207
31. for each vector file You can specify multiple vector files to be used with the GAP feature E set gap opt period 40ns save_history on vec_history 1 This command sets the following parameters for the GAP algorithm Theperiod 40ns argument sets the clock period for the circuit to 40 ns Thesave_history on argument saves the simulation history which allows you to stop the simulation and PowerMill User Guide 56 Chapter 3 PowerMill Tutorials restart it from where you left off This feature can come in handy when simulating large circuits which can be very CPU intensive and often require a long simulation time This option saves both the circuit state and vector stimuli which allows you to do further power analysis on a specific generation without having to run the simulation again Thevec history 1 option saves the vector history for only those generations that improve increase the maxi mum power estimation guide gap search fit 2 level 7 This command sets up the fitness function and the search level The fit 2 option tells the simulator to maximize the instantaneous power fit 1 maximizes average power per clock cycle NOTE To ensure the quality of the resulting estimate this tutorial uses a larger search level 7 than that used in tutorial 5 because the size of the solution space to be searched is larger than it is in tutorial 5 set_ckt_cmd d ff mark_node_latch no q This command enables the automatic
32. gt E xit to exit the program Advanced PowerMill Simulations This section illustrates some of the power analyses you can do with the PowerMill simulator Figure 5 shows the adder circuit used for these advanced simulations This circuit is the same as that used in tutorial 1 except that here a 4 bit register has been added to the output PowerMill User Guide 26 Chapter 3 PowerMill Tutorials Tutorials 2 6 illustrate the use of configuration commands related to different types and levels of power analyses Once you understand how these commands work in separate simulations you can combi ne them into a single run Tutorials 2 4 cover only digital simulation Tutorials 2 6 are written with the assumption that you know how to run vi or another text editor and turboWave therefore the specific steps needed to open and reopen files using these tools are not described Advanced PowerMill Simulations 27 Figure 5 Logic diagram of the circuit for the advanced tutorials Before You Begin Before beginning any of the following tutorials we recommend that you examine the run scripts and the configuration files for each tutorial in which you are interested 1 Usethe UNIX cat command to display the contents of each run script as needed PowerMill User Guide 28 Chapter 3 PowerMill Tutorials cat full chip run full cat block powr runl block cat block powr run2 block cat block powr run3 block cat dc path run dcep
33. node reporting R 168 capacitance R 41 R 42 R 123 changing connectivity R 105 current printing R 126 U 99 current reporting R 174 dangling node reporting R 171 forcing logic state R 51 voltage R 53 getting connectivity R 66 hot spot reporting R 172 hotspot checking U 112 index number R 98 initial conditions R 253 logic state R 128 marking latches R 101 name R 99 partitioning R 381 R 382 R 385 R 387 releasing R 138 R 139 sensitivity R 251 simulating R 251 R 258 R 380 R 384 U 129 skipping wirecap estimate R 107 tracing fanin R 329 U state checking U 111 U state reporting R 185 voltage R 131 X state reporting R 187 Z state checking U 112 Z state reporting R 187 node names listing by index R 99 node sensitivity control U 128 notation bus R 210 O online help printing to file R 121 printing to the screen R 55 output files compressing R 278 contents of R 405 R 417 FSDB format R 281 ISDB format R 281 prefix specification R 8 splitting R 322 output filter selecting R 215 p parameter R 64 parasitic printing node voltage R 131 partition information saving R 198 partitioning R 369 R 371 R 374 R 380 R 385 analog R 356 at high connectivity nodes R 382 R 387 charge pump R 357 memories R 358 mixed signal R 359 pattern matching R 102 R 271 R 454 phases simulation R 74 PMOS U 118 power assigning power budgets U 93 estimating maximum power U 103 getting power information interactively
34. now contains several output files with the dcpath prefix Advanced PowerMill Simulations 39 4 Open at the dcpath dcpath file and study the messages This file contains time stamps for when violations occur and lists the transistor at fault Figure 11 shows the first DC path reported in the dcpath dcpath file transistor x2 x2 xl mn1l type NMOS current 345 30 uA gate n2 voltage 2 60 9 drain x2 x2 n4 voltage O61 source gnd voltage 0 00 V transistor x2 x2 x1 mp1 type PMOS current 343 63 uA gate n2 voltage DEEN drain x2 x2 n4 voltage Dx6L Vy source vdd voltage 5 00 V Figure 11 First DC path reported to dcpath dcpath file The report_ckt_dcpath command has other syntax options This particular option with no arguments finds all DC paths that violate the 200 microamp threshold In this case the checks are triggered by any signal change 5 Load the dcpath out file in turboWave and display the cout v cout n2 and v n2 signals see Figure 12 PowerMill User Guide 40 Chapter 3 PowerMill Tutorials File Signal View Waveform Analog Tools Window Help 2 mle fe EL e By mi fv cout 140 Ony angal TIM EC Figure 12 Waveform of DC path output file Advanced PowerMill Simulations 41 Tutorial 5 Estimating Maximum Power for Combinational Circuits This tutorial shows you how to estimate the maximum power of combinational circuits at the full chip level
35. power is synonymous with current Analyzing Power Consumption This section provides an overview of the features and methods available in PowerMill for the analysis of power use in your circuits at the full chip block and individual node or element levels This section includes information on the followi ng subjects Analyzing Power at Full Chip Level Analyzing Power Block by Block Measuring Wasted Power Measuring True Power in Watts Measuring Power Hierarchically Assigning Power Budgets Retrieving Power Information I nteractively Controlling Power Reporting Resolution and Accuracy Printing and Reporting Branch Currents PowerMill User Guide 86 Chapter4 Power Analysis m Printing and Reporting Internal Node Currents m Working with Probes m Current Histograms and Tracking Windows Analyzing Power at Full Chip Level Full chip power analysis is the simplest type of power analysis At this level the power usage of the chip can be characterized by the current statistics and waveforms of the main power nodes such as VDD and GND These can be obtained by using the node current printing and reporting configuration commands print_node i print node didt print node iavg report node i print node irms report node powr When used for any voltage source node the current reported is the current being supplied by the source see Printing and Reporting Internal Node Currents on page 99 The print node i7 commands are
36. producing the maximum power are kept in the history files gav files At the end of the estimation GAP generates a history file corresponding to each vector file In this configuration file the fit 1 option default of guide gap search command instructs GAP to maximize the average power per clock cycle You can choose to set up PowerMill User Guide 44 Chapter3 PowerMill Tutorials various stopping criteria for GAP using the guide gap search command for example CPU time number of generations and number of pairs See the command definition for the guide gap search command in the Power Mill Reference Guide Theleve1 5 option is the default search level Each search level from 1 to 10 defines a corresponding parameter set used in the genetic algorithm Selecting a larger search level generally produces a better larger estimate of the maxi mum power but increases the CPU time Run the simulation using therun max power script Type Control c to switch into the interactive mode In this mode you can use the interactive GAP commands Type report gap progress at the interactive prompt This command shows the progress of the GAP estimation in a tabular format default to the screen This table contains the maximum power corresponding vector pair and CPU time Type report gap progress mode 2 at the interactive prompt Maximum Power So Far watts Advanced PowerMill Simulations 45 This command displays GAP progr
37. searching and identification of latches and flip flops in the circuit Thed ff subcircuit is identified and the mark_node_latch no q command is applied to all instances of the d ff subcircuit If you have a circuit with FFs that have many different subcircuit names you have to apply a separate set_ckt_cmd command to each subcircuit Specifying the mark node latch command causes the PPI vector file maxpower ppi vec to be generated and added to the simulation automatically print_probe_i inst gap total_power report block powr stagel track_power 1 x1 report block powr stage2 track power 1 x2 j report block powr ff array track power 1 xd Advanced PowerMill Simulations 57 report_probe_i avg stagel total power report_probe_i avg stage2 total_power report probe i avg ff_array total_power report probe i avg gap total power This section of the configuration file controls power reporting All but the first line are commented out See Analyzing Generations with Saved State Files on page 63 for information on using these power reporting commands NOTE You can reduce the size of the resulting output file by using the F SDB or ISDB output format To do so simply add the set print format for isdb or for fsdb command to the configuration file This setting does make the simulation run more slowly Open and study the max_seq_powerspi netlist file The described circuit contains four PPIs which are the output o
38. size using thep size option of the guide gap search configuration command In general a larger population size generates higher quality vector sets while increasing the CPU time needed for the estimation You can use the GAP result when analyzing various reliability issues For example if the lower bound of maximum power generated by GAP exceeds your power budget you will probably need to redesign the block The following PowerMill configuration and interactive commands are part of the GAP feature for estimating maximum power consumption guide gap search set gap opt report gap prediction report gap parameters report gap progress use vec gap Running a Basic GAP Estimation This section provides a general procedure for using the GAP commands It is strongly recommended that you run the following tutorials in Chapter 3 PowerMill Tutorials before running the GAP feature m Tutorial 5 Estimating Maximum Power for Combinational Circuits on page 41 Using the GAP Feature to Estimate Maximum Power 105 m Tutorial 6 Estimating Maximum Power for Sequential Circuits on page 50 m Tutorial 7 Customizing a GAP Objective F unction using an ADFMI Code File on page 69 NoTE Searching for the optimum pairs or triplets to maximize power consumption is a time consuming optimization process even for small circuits For example it might take about 10 minutes of CPU time to estimate a small sequential circuit wit
39. that autodetection command that is the default search ckt msx is not applied to that portion of the circuit If you apply more than one autodetection command to the same block in a circuit the simulator combi nes the rules for both commands and applies them to the specifi ed block EXAMPLE 1 search ckt mem el xdram This command applies search ckt mem rules to the xdram block The default search ckt msx is applied to the remainder of the circuit EXAMPLE 2 search ckt mem el xmemory search ckt msx el xmemory xsubcircuit search ckt analog el xanalog PowerMill User Guide 128 Chapter5 Using the ACE Feature Using this example the simulator combines the rules for search ckt memand search ckt msx and applies them to the xmemory xsubcircuit block while applying search ckt mem to the remainder of the circuit in xmemory In addition the simulator applies the search ckt analog rule tothe xanalog block and search ckt msx to the remaining portions of the circuit See Chapter 3 ACE Configuration Commands in the PoweM ill Reference Guide for more information on the search ckt mem and search ckt analog configuration commands For information on search ckt logic see Chapter 2 Configuration and Interactive Commands in the PowerMill Reference Guide Controlling Node Sensitivity Both the speed control and event sensitivity can be applied on a global basis to the entire circuit either all digital or all ana
40. tools Figure 1 PowerMill GA main window Starting the Graphical Analyst 165 File Menu You can use the File menu to start setting up a simulation run send feedback via e mail to Synopsys save the window settings or to exit PowerMill m Tostart setting up a run select File Design Data Setup See the Setting Up a Run on page 167 for more information on this process m Tosend feedback to Synopsys select File Send Feedback This pops open an e mail window that allows you to enter your comments m Tosavethe size and placement of the PowerMill GA windows you can select File gt Save Window m Toexit the PowerMill Graphical Analyst select File Exit Options Menu The Options menu lets you either choose the measurement unit you want to use for your analysis or select your preferred waveform viewer Select Options u micro to view data in micro units or select m milli to view data in milli units in the Results Display area of the PowerMill GA main window as well as the Power Histogram Display Select turboWave to use the turboWave viewer or SimWave to use the SimWave viewer Help Menu The Help menu gives you access to help information on the PowerMill Graphical Analyst Simulation Setup Button The Simulation Setup button located on the middle left side of the PowerMill GA main window is one of two ways you can PowerMill User Guide 166 Chapter 7 Using the PowerMill Graphical Analyst begin sett
41. used to print the instantaneous average RMS and didt waveforms of the requested nodes to the out file The report node i command can be used to request the reporting of the average RMS or peak currents to the log file at the conclusion of the simulation You can also useit to request a current histogram to be generated for the specified nodes see Current Histograms and Tracking Windows on page 101 The report node powr command is a macro and can be used to request all of the above information except the didt waveform and current histogram with one command The simplest approach is to use the report node powr command without specifying any arguments This automatically selects all the supply and ground nodes as well as all current probes for current reporting Figure 1 shows a sample report generated by the report node powr command This report is first printed to the Analyzing Power Consumption 87 screen and then printed in the log file at the end of the simulation The instantaneous average and RMS current waveforms for these nodes are also recorded in the out file Current information calculated over the intervals 0 00000e 00 6 00000e 03 ns Node gnd Average current 7 11217e 02 uA RMS current 26582e 03 uA Current peak 1 1 49260e 04 uA at 4 40180e 03 ns Current peak 2 40570e 04 uA at 4 20180e 03 ns Current peak 3 32660e 04 uA at 4 00180e 03 ns Current peak 4 1 32540e 04 uA at 3 80180e 03 ns C
42. with the lowercase letter L argument specified will be set as the default This is because HSPICE is case insensitive and sets all characters to lowercase See Chapter 1 The PowerMill Command in the PowerMill Reference Guide for details on all of the PowerMill command line options Batch Versus Interactive Mode PowerMill can be run in batch mode or interactive mode The default is batch mode In this mode PowerMill runs to completion without intervention To use PowerMill interactively you must specify the i option or type Control c while the simulation is running that is after netlist compilation The interactive commands are descri bed in Chapter 2 Configuration and Interactive Commands in the Power Mill Reference Guide Environment File PowerMill lets you define certain simulation environment parameters in the epicrc file The PowerMill simulator uses these parameters but they can be overridden with options on the command line The syntax description and example of this file Netlist Files 11 are included in the section Creating the Environment epicrc File on page 13 Netlist Files The netlist file describes the system or circuit to be simulated and is required torun a simulation The following formats are accepted by PowerMill EPIC HSPICE SPICE EDIF LSIM Verilog and Cadence SPF Morethan one netlist with the same or different formats can be specified simultaneously for exampl
43. 0 c eee 168 Using the File Finder Form 20000005 170 Importing Existing Run Scripts 0000e eee eee 171 Specifying Netlist and Technology Files 04 171 Setting the Simulation Time 00 0000 cee ee 172 Design LIBParys niche ka maan Be ed Bae ae DD 172 Command Line Options 0 0000 ee 172 Saving Clearing or Cancelling Your Changes 172 Power Supply Setup 0 000 ee 173 Block Setup ua saeenieict ace a ma a Granite ase dat eee yen do wa LY NANANA 174 Selecting BIOCKS lea i a aae aE eee 175 PowerMill User Guide Vill Table of Contents Saving Clearing or Cancelling Your Changes 175 Power Diagnosis Setup 4 te 176 Static Power Checks 0 ee 177 Excessive CUT enU nei mikrora daa ki pa e OER Kee Da UAR 177 Tristate Check os en iener bk reai eee ew a a 178 Report Hazards uk a maa AD KAG pa die eG eed ete eek 178 Power Distribution 0 000002 cece eee 178 Showing or Hiding Help Messages 0 a 178 Saving or Clearing Checks 0 000000 cee eee 178 Running a Simulation sacia s ea aeaa a a E E aE ae EN t a aE 179 Analyzing a GCITOIEnn Na ma DA Ea iae e a anna e fea I Gee 180 Power Consumption 180 S rt By MENU ss aan dank Ada eae a Na AN 181 Hierarchical View of Power Consumption 182 Results Analysis 000 c eee ee 182 Power Histogram 0 000 e ee 182 PIl MO NU 20 nee ee
44. 01101110011 10001101011000zzzz 11101011110111zzzz 40 0 000759248 101101111000110111 01000101100110zzzz 10010010111111zzzz 0 000938212 101101110001110101 01000101011000zzzz 10010011110111zzzz 120 0 00111505 001101110111000010 01000101010011zzzz 10010010111101zzzz Current CPU Time 33 47 secs Maximum power so far 0 00111505 watts Current number of generations 8 Figure 24 Report of GAP parameter settings The simulator generates an entry in this file for each generation that improves the maximum value of the fitness function Each file entry lists the time number of triplets current value of the fitness function and the stimuli 11 12 13 14 15 Advanced PowerMill Simulations 77 In addition the current CPU time maximum value and number of generations are printed at the bottom of the report You can also use the guide_gap_search command to set various criteria for stopping GAP at the interactive mode command line See the command definition for the guide_gap_search command in the PowerMill Reference Guide Type cont to continue the GAP simulation When the simulation finishes type quit to quit the simulation Open and study the custom gap file see Figure 25 The simulator creates an entry in this summary file for each generation that improves the maximum value Open and study the max seq power gav and custom ppi gav files These two files are the vector history files for max_se
45. 122 print node logic 23 30 print node v 23 30 print probe i 30 100 122 report block leakage 89 report block powr 30 88 122 report ckt dcpath 38 39 115 report ckt leak 117 118 report ckt phist 101 report elem exi 112 122 report elem i 101 report node hotspot 112 report node i 86 101 122 report node maxrf 119 report node powr 23 86 100 report node quick 112 report node u 112 report node z 112 report probe i 100 101 122 search ckt analog 126 128 search ckt cpump 126 search ckt logic 126 128 search ckt mem 126 128 search ckt msx 126 127 search ckt rc 127 search ckt ud 127 set dcpath thresh 38 115 set elem acc 131 set elem pwl 131 set elem sms 131 set elem sync 131 set hotspot factor 114 set node aspd 129 set node spd 129 set node thresh 112 119 set print ires 131 set print iwindow 102 set print tres 131 set print vres 131 set sim aspd 130 set sim spd 130 set sim subgroup 130 set sim trap 156 set sim tres 129 use sim case 10 configuration files 12 current printing and reporting block 87 element 98 histogram 101 node 99 probes 100 current resolution controlling 132 D DC paths finding tutorial 37 static 117 diagnosing power problems dynamic 111 static 116 double precision mode 132 dynamic power analysis 111 E element current printing 98 printing branch currents 98 EPIC HOME environment variable 21 205 EPIC USE SHM environment variable 229 epicrc file See epicr
46. 2 3000e102 70006102 1000e102 BWWNNNH H OW Start ns 0000e 01 0000e 01 3000e102 7000e102 1000e 02 5000e 02 9000e102 3000e 02 7000e 02 1000e102 BS WWNNNH H OW SBWWNNNH RH O Element IOBUFF0 P1 Branch 1 BSBWWNNNEH EO Stop ns Avg UA RMS uA Peak uA Time ns 0000e 01 2 8779e 01 5 3431e 0 1 0100e 02 6 0400e 01 3000e 02 7 0781e 01 8 4014e 0 1 1700e 02 1 0245e 02 7000e 02 5 3766e 01 7 3174e 0 1 0100e 02 1 5040e 02 1000e 02 2 1036e 01 4 5936e 0 1 3500e 02 2 0232e 02 5000e 02 1 0000e 02 1 0000e 02 1 0000e 02 2 1000e 02 9000e 02 9 0790e 01 9 0970e 0 1 0100e 02 2 5040e 02 3000e 02 7 3625e 01 7 3732e 0 8 2000e 01 2 9000e 02 7000e 02 6 1875e 01 6 1934e 0 6 8000e 01 3 3000e 02 1000e 02 5 4000e 01 5 4032e 0 5 8000e 01 3 7000e 02 5000e 02 4 9000e 01 4 9015e 0 5 1000e 01 4 1000e 02 Stop ns Avg uA RMS uA Peak uA Time ns 0000e 01 1 0304e 03 4 9851e 03 3 3619e 04 6 2000e 01 3000e 02 1 4845e 03 7 0174e 03 5 1510e 04 1 0190e 02 7000e402 1 0614e 03 4 9601e 03 3 3150e 04 1 5200e 02 1000e 02 8 5798e102 5 1421e 03 4 3718e 04 2 0181e 02 5000e 02 1 2009e 02 1 2009e 02 1 2100e 02 2 1000e 02 9000e 02 2 9633e 01 5 0674e 01 3 2600e 02 2 5214e 02 3000e 02 1 1750e 01 1 1874e 01 1 5000e 01 2 9000e 02 7000e402 7 2500e 00 7 3144e 00 9 0000e 00 3 3000e 02 1000e 02 4 6250e 00 4 6771e 00 6 0000e 00 3 7000e 02 5000e 02 2 7500e 00 2 7839e 00 4 0000e 00 4 1000e 02 Figure 6 Sample current histogram
47. 2_powr return sum Figure 21 Excerpt from execution function Thefirst section of this function checks to see if the simulator is in the DC initialization phase prior to the start of the transient simulation If so it sets the ID pointers If it is not in the DC initialization phase the transient simulation has already started The second section calculates the sum variable by adding up the power from both blocks Notice that the power number you get is much lower than in the previous tutorial in which you calculated the maximum PowerMill User Guide 74 Chapter 3 PowerMill Tutorials power for the entire circuit In contrast this tutorial only covers two blocks of the circuit see Figure 22 COUT 1 COUT2 t gt S2 3 gt S2 2 gt S2 1 gt S2 0 CINI CLK CIN2 Block 1 Block 2 Figure 22 Block diagram of the circuit 5 Open and study the run custom script 6 Locate the following option fm gap customize c This option identifies the gap customizec file as an ADF MI C file In addition to describi ng and registering ADF MI models an ADF MI C file can also descri be and register a GAP customized fitness function Specifying the ADF MI C file on the command line is required for GAP customization 7 Run the simulation using the run custom script Advanced PowerMill Simulations 75 The simulation performs PPI detection first After it generates the custom ppi vec PPI vector f
48. 5971 uW Figure 10 Excerpt from block power reports in block3 log file Tutorial 4 Finding DC Paths This tutorial illustrates how you can use the PowerMill simulator to find DC paths The following table lists the fil es PowerMill User Guide 38 Chapter3 PowerMill Tutorials needed for this tutorial These files are located in the pw advanced dc path subdirectory in your working directory Filename adder cmd Description EPIC format netlist file that describes the filename for the vector file and the node names and port ordering for the vector file adder vec Tabular digital vector file used as the digital stimulus for the simulation cfg_dcpath Configuration file for DC path checks dcpath spi SPICE netlist of the circuit for DC path checks run_dcpath Run script for DC path checks tech typ 25c 5v Technology file Procedure Use the following procedure to run the DC path check tutorial 1 Open and examine the cfg dcpath configuration file The following file sample shows the contents of this configuration file print node logic print node v report node powr vdd gnd report ckt dcpath set dcpath thresh 200u 2 Run the simulation using the run dcpath script Watch the on screen messages as they scroll by during the simulation These messages are included in the dcpath file 3 When the simulation is finished list the directory contents The directory
49. Applying report branch i print_branch_i print node v report elem exi assign branch i or assign node i causes the given elements to be PWL which defeats the fast power estimation feature for elements intended to be RC or UD elements Chapter 5 Using the ACE Feature 124 Chapter5 Using the ACE Feature Overview 125 Overview The Analog Circuit Engine ACE is a built in feature that extends PowerMill s capability to simulate analog and mixed signal circuit designs The default autodetection algorithms can simulate most analog CMOS circuits such as bandgap references and PLLs in mixed signal designs with no additional configuration commands If you are simulating sophisticated or complex designs you might want to apply some additional configuration commands to improve the accuracy of a simulation Since output printing and other controls are usually induded in the SPICE netlist you will most likely not need a configuration file when running ACE Included in this Chapter This chapter highlights some of the capabilities of the ACE option The following sections are included Selecting Autodetection Rules Controlling Node Sensitivity Controlling the Simulation Time Resolution Applying Multiple Time Steps Multi Rate Simulations Controlling Waveform Print Resolution Applying Multiple Simulation Modes Simulating BJ Ts Selecting Autodetection Rules TheACE option provides a group of autodetection command
50. CK top MAXIMUM INSTANTANEOUS SUPPLY CURRENT OF 157249 uA EXCEEDS BUDGET OF 30000 uA BLOCK top AVERAGE SUPPLY CURRENT OF 1537 84 uA EXCEEDS BUDGET OF 1000 uA BLOCK top MAXIMUM INSTANTANEOUS POWER OF 566098 uW EXCEEDS BUDGET OF 100000 uW BLOCK top AVERAGE POWER OF 5536 21 uW EXCEEDS BUDGET OF 3000 uW KKKKKKKKKKKKKKKKKKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKKKKKKKKKKKKK BLOCK HIERARCHICAL POWER ANALYSIS KKKKKKKKKKKKKK KKK KKK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKKKKKKKKKKKKK BLOCK top AVERAGE SUPPLY CURRENT LEVEL CURRENT PERCENT OF PERCENT OF CHILD BLOCK NAME uA PARENT TOP Ka 0 1537 8 100 00 100 00 top SS RS 1 So lt 8 100 00 100 00 top xsr34x22 SEKTA 2 2359 83 23 40 23 40 top xsr34x22 x1161 2 322 71 20 98 20 98 top xsr34x22 x1164 2 214 54 13 95 L395 top_xsr34x22 x1166 Paa See 2 207 38 13 48 13 48 top_xsr34x22 x1158 2 92 92 125255 12 55 top xsr34x22 x1162 2 SOL PEL S232 5 32 top_xsr34x22 x1163 Ser ea 2 567 2669 3 74 3 74 top xsr34x22 x1157 CAN 2 52 966 3 44 3 44 top_xsr34x22 x1160 ma 2 42 359 2 75 2235 top xsr34x22 x1169 EG 2 8502 0 38 0 38 top_xsr34x22 x1167 2 0 0086932 0 00 0 00 top_xsr34x22 x1170 2 0 0 00 r00 top xsr34x22 x1165 2 0 0 00 0 00 top xsr34x22 x1168 2 0 0 00 0 00 top xsr34x22 x1159 BLOCK top RMS SUPPLY CURRENT LEVEL CURRENT PERC
51. DC Path Browser by selecting Close DC Path Browser from the File menu Option Menu Select Option Search to bring up the Search DC Paths form This form allows you to specify a particular time period of the simulation for viewing DC paths This is useful if you are interested in seeing DC path for a particular time of the simulation or if you cannot display all the DC pathsin a single window see Figure 15 eas Option re 0 58 bow Search DC Paths Find DC Path at time ns iI v Starting at time ns for every ns ending at time ns w for all OK Cancel Figure 15 Search DC paths form Analyzing DC Paths The DC Path Browser automatically loads the dcpath file for the current run A series of time blocks are displayed at the top of the window You can view detailed DC path information for a PowerMill User Guide 188 Chapter 7 Using the PowerMill Graphical Analyst particular time period by clicking on any time segment see Figure 16 DC Path Browser 4150 4250 4550 4750 4850 5150 5250 5550 5750 5850 6150 6250 6550 6750 6850 Simulation Time ns 1 core dff 121 P5 gt core 1 core dff 121 P5 gt core dff 121 P5 gt core o Figure 16 Detail view of DC path browser When you ve clicked a particular time segment all the DC paths that occurred at that time are displayed in the DC Paths text field located at the bottom left corner of the window By default the
52. ENT OF PERCENT OF CHILD BLOCK NAME uA PARENT TOP Kz 0 6959 2 100 00 100 00 top aiid pean ale 1 69592 100 00 100 00 top_xsr34x22 AE ce AN 2 31741 53 41 53 41 top xsr34x22 x1161 a Pan 2 2966 7 42 63 42 63 top xsr34x22 x1164 paa 2 1785 1 25 65 256i top xsr34x22 x1166 AG 2 1584 1 22 716 22 16 top xsr34x22 x1162 ma Waaa See 2 133253 19 18 13 15 top xsr34x22 x1158 a eo teed ts 2 1202 1 1721 11484 top xsr34x22 x1163 2 647 76 9 3 1 9 31 top xsr34x22 x1157 a a aa 2 408 87 5 88 5 88 top xsr34x22 x1160 Hei SG 2 316 96 4 55 4 55 top xsr34x22 x1169 PowerMill User Guide 228 Sample Power Reports ma E 2 1275 03 1 65 1x65 top xsr34x22 x1167 Soken 2 2 588 0 04 0 04 top_xsr34x22 x1170 2 0 0 00 0 00 top xsr34x22 x1165 2 0 0 00 0 00 top_xsr34x22 x1168 2 0 0 00 0 00 top_xsr34x22 x1159 BLOCK top AVERAGE POWER LEVEL POWER PERCENT OF PERCENT OF CHILD BLOCK NAME uW PARENT TOP 0 55362 100 00 100 00 top AR AA I 5536 2 100 00 100 00 top xsr34x22 AA 2 1467 9 26 51 26 51 top_xsr34x22 x1161 GA 2 746 39 13 48 13 48 top_xsr34x22 x1158 2 722 92 13 06 13 06 top xsr34x22 x1166 a 2 694 52 LE OS 12 55 top xsr34x22 x1162 BET ee eee 2 639 25 LL lt 55 LG top xsr34x22 x1164 kan 2 430 29 De TT TESTES top_xsr34x22 x1163 SRS SSeS 2 258 27 4 67 4 67 top_xsr34x22 x1167 SRS SES 2 207 25 3 74 3 74 top xsr34x22 x1157 KAB AA acne 2 190 68 3 44 3 44 top xsr34x22 x1160 Fr a 2 152 49 275 2 75 top_xsr34x22 x1169
53. Generation 22 Maximum power 0 00653965 Vec 0 000000000 Vec 1 110101101 Generation 125 Maximum power 0 00653967 Vec 0 000000000 Vec 1 110101101 watts watts watts watts Total number of generations 152 Total CPU time 144 29 secs Figure 14 Contents of the maxpower gap file PowerMill User Guide 48 Chapter 3 PowerMill Tutorials 12 13 This file contains a summary of the GAP estimation The maxpower gap file contains an entry for each generation that improves the maximum power Each entry contains the following three fields generation ID maximum power induced and the input vector pair producing the maximum power The total CPU time and total number of generations are printed at the end of the file Open and examine the max com power1 gav and max com power2 gav files These are history files that save the input vectors used during the estimation GAP produces a separate gav file for each input vector file The max com powerl1 gav and max com power2 gav files generated by this tutorial contain only the vectors of the generation producing the maximum power You can specify which vectors you want GAP to keep using the vec history option of the set gap opt command See the PowerMill Reference Guide for details on all of the GAP configuration and interactive commands NOTE You can use the gav files generated by GAP as vector files for a regular PowerMill simulatio
54. Measuring Wasted Power 00 e eee eee eens 88 Measuring True Power in Watts cc eee eee ees 90 Measuring Power Hierarchically 0000 eee eae 91 Assigning Power Budgets 0 00 cece eee 93 Retrieving Power Information Interadively 94 Controlling Power Reporting Resolution and Accuracy 97 Printing and Reporting Branch Currents 4 98 Printing and Reporting Internal Node Currents 99 Working with Probes 0 00 ee 100 Current Histograms and Tracking Windows 101 Using the GAP Feature to Estimate Maximum Power 103 Running a Basic GAP Estimation a s a sasaaa aan 104 Procedure Tanada aiia a eho ie Na 2 ed kd 105 Creating a Customized Fitness Function 108 Performing a Dynamic Power Consumption Analysis 111 Checking Dynamic Rise and Fall Times U State Nodes 111 Detecting Dynamic Floating Nodes Z State Nodes 112 Detecting Excessive Branch Currents 00 cee eens 112 Analyzing Hot Spot Node Currents 0000 cee eee 112 Detecting Dynamic DC Paths 20000 eee 115 Performing a Static Power Consumption Diagnosis 116 Detecting Static DC Paths 0 0 0 0 22 eeeeeeeee 117 Static Excessive Rise Fall Time Detection 119 PowerMill User Guide Vi Table of Contents Analyzing Power Using the RC
55. OS transfer gate on node Single NMOS transfer gate on node Node is floating Node is floating Node is floating Node is floating Node is floating Node is floating Static Power Diagnosis Single NMOS transfer gate on node 15 net9 Figure 17 Power diagnostics browser Analyzing a Circuit 191 Selecting Checks The numbers that appear in the upper part of the browser indicate the number of messages in each error category Select the type of errors you want to view by clicking the appropriate buttons at the top of the form The button will turn red when a check is active see Figure 18 Power Diagnostics Browser Click here for aa E Static Paths 18 E No Path To VDD 5 No Path To GND 7 j Path To VDD 0 W Path To GND 3 E Leakage Path 3 Figure 18 Selecting static paths Use the following buttons related to selecting checks m Static Checks causes additional selections to appear m Show Errors shows a list of errors corresponding to the error types you selected Select a particular error to get a detailed information on that error at the bottom of the browser m Reset clears your selections You can use your middle mouse button to drag and drop node names from the Error List to other parts of the window You can also drag and drop node names from other sources in the PowerMill User Guide 192 Chapter 7 Using the PowerMill Graphical Analyst PowerMill GA suc
56. PowerMill User Guide Release 5 4 J anuary 2000 Comments E mail your comments about Synopsys documentation to doc synopsys com SYNOPSYS Copyright Notice and Proprietary Information Copyright 2000 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks service marks and proprietary rights notices if any Licensee must assign sequential numbers to all copies These copies shall contain the following legend on the cover page This document is duplicated with the permission of Synopsys Inc for the exclusive use of and its employees This is copy number Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to
57. R 430 powrmill power file R 441 powrmill stat file R 437 powrmill sum file R 417 R 435 files output R 405 R 417 See epicrc files Seeinput files See output files FSDB format R 281 functional model Seealso ADF MI Manual functional model specifying R 333 G GAP feature U 103 guiding R 78 predicting convergence R 164 printing a progress report R 165 reporting parameters R 163 selecting a clock period R 232 specifying vector files R 336 tutorials U 41 U 50 U 69 Gentech utility U 12 graphical analyst child cells U 198 path tracing U 199 power diagnostics browser error list U 191 show info about box U 196 H help command R 55 printing R 121 See also online hap R 19 hierarchical delimiter R 298 separator setting R 298 hierarchy browser options menu U 196 panning display U 195 path tracing U 199 select instances to display U 198 set expansion threshold U 197 show instructions U 196 tree display U 195 histogram current R 145 R 160 R 174 R 189 U 101 HSPICE SPICE netlists U 11 i index command prefix R 19 index numbers listing R 19 R 98 initial conditions R 253 input files configuration R 4 U 12 netlist R 8 U 11 stimulus U 13 technology R 9 U 12 input netlist R 8 instance parameter R 64 interactive mode accessing R 19 command line option i R 7 interactive log file closing R 47 interactive log file opening R 108 R 405 tracing signal events R 36 R 327 R 328 R 330 ISDB format
58. T FROM 21 4 TO 21 5 ns BLOCK top DRAWS EXCESSIVE POWER FROM 21 4 TO 21 5 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 21 6 TO 21 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 21 6 TO 21 9 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 22 2 TO 22 5 ns BLOCK top DRAWS EXCESSIVE POWER FROM 22 2 TO 22 5 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 50 4 TO 50 5 ns BLOCK top DRAWS EXCESSIVE POWER FROM 50 4 TO 50 5 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 61 4 TO 61 5 ns BLOCK top DRAWS EXCESSIVE POWER FROM 61 4 TO 61 5 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 61 6 TO 62 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 61 6 TO 62 4 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 101 6 TO 101 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 101 6 TO 101 8 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 102 2 TO 102 3 ns BLOCK top DRAWS EXCESSIVE POWER FROM 102 2 TO 102 3 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 141 6 TO 141 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 141 6 TO 141 8 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 142 2 TO 142 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 142 2 TO 142 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 170 8 TO 170 9 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 181 4 TO 181 5 ns BLOCK top DRAWS EXCESSIVE POWER FROM 181 4 TO 181 5 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 181 6 TO 181 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 181 6 TO 181 8 n
59. adder circuit This circuit contains 164 transistors and is simulated with 150 vectors Figure 2 and Figure 3 further illustrate the adder circuit used in this tutorial PowerMill User Guide 20 Chapter 3 PowerMill Tutorials 40 1 40 1 ADDER 40 1 40 1 10 1 bn b SUM 20 1 20 1 a 5 1 mn1 AIN 10 1 10 1 20 1 20 1 Figure 2 Logic diagram of the adder cell 10 1 IN XI N4 5 1 5 1 10 1 df 10 1 Figure3 Logic diagram of an XOR2 cell Getting the Input Files 21 Tutorials Included in this Chapter This chapter includes the followi ng tutorials Tutorial 1 Running a Basic Simulation Tutorial 2 Performing a Full Chip Power Analysis Tutorial 3 Performing a Block Level Power Analysis Tutorial 4 Finding DC Paths Tutorial 5 Estimating Maximum Power for Combinational Circuits Tutorial 6 Estimating Maximum Power for Sequential Circuits Tutorial 7 Customizing a GAP Objective Function using an ADFMI Code File Tutorial 8 Finding Static Leakage Paths NOTE The turboWave screens in this chapter are displayed with altered colors and signal height to improve readability Therefore the waveforms you actually seein turboWave will look significantly different from the screens in this chapter Getting the Input Files Before you can run any of the tutorials in this chapter you need to copy the required input files to your current working directory The follow
60. amplifiers or analog to digital circuits and digital to analog circuits beyond 12 bits might also require double precision Simulation Speed and Double Precision Using double precision mode will slow down the simulation by approximately 10 while increasing memory consumption by approximately 30 Therefore it is recommended that you do not use double precision mode unless absolutely necessary Controlling Voltage and Current Resolution There are no limits on the voltage and current resolution settings except those imposed by the floating point float data type The float data type is the default in single precision which is an 8 bit mantissa and a 3 digit exponent This means that the absolute lowest resolution available depends on the absolute value of a stored number Simulating BJTs 133 For small voltages and currents there are more significant digits available at lower values For example if you have 1 00000000 V and you need to maintain accuracy to 1 nV the nanovolt level will be lost that is 1 000000000 V 0 000000001 V 1 000000000 V However if you have 1 mV instead the 1 nV can be retained that is 0 001000000 V 0 000000001 V 0 001000001 V Therefore if you have large signals that require nanovolt accuracy and precision you will need to use the double precision data storage CAUTION The higher precision printing has a direct impact on the size of the output file If you try to print every node voltage i
61. and UD Simulation Modes 119 Technical Background sssaaa cece eee 120 Running a Simulation in RC or UD Mode 121 5 Using the ACE Feature OVERNTEN na LE Un BAND DA Pba BRP PALAG PRN 125 Included in this Chapter 0 0000 125 Selecting Autodetection Rules ee 125 Applying Multiple Autodetection Rules 127 Controlling Node Sensitivity 0 0 00 ee 128 Controlling the Simulation Time Resolution 129 Changing the Time Step Selection Parameter 129 Applying Multiple Time Steps Multi Rate Simulations 130 Controlling Waveform Print Resolution 000000 aes 130 Applying Multiple Simulation Modes 220 0c eee eae 131 Activating Double Precision Mode 0000 132 Simulation Speed and Double Precision 132 Controlling Voltage and Current Resolution 132 Simulating BJ TS eers na ei BANA ee ee ees BUNGAD nee Se ee 133 Procedure for Simulating BJ Ts 2s eee eae 134 6 ACE Tutorials OVERVIGW aa Mestad watt Sipa we aii eaten thoes 137 Getting the Input Files 2 0 0 00 0c ees 137 Tutorial 1 CV Curve Generation 02000 eee 139 Files Needed for this Tutorial 0 00 140 Procedure freo dreara eet Ra PG Ue ed eee 140 Tutorial 2 Operational Amplifier Simulations 142 Voltage Follower Simulati
62. applies a more conservative autodetection algorithm m search ckt mem Usethis set of rules for embedded DRAMs PLDs and ROMs You can also use the default search ckt msx for these circuits but the simulation will likely take longer to run m search ckt cpump Use this set of rules for charge pump circuits flash memory circuits etc Flash memory circuits can usually be simulated with the default search ckt msx set of detection rules however some circuits might require the more conservative search ckt cpump rules m search ckt logic Selecting Autodetection Rules 127 Use this set of rules for digital circuits This set of rules is more aggressive and can greatly improve the simulation speed for digital circuits m search ckt rc Use this set of rules for digital only blocks If you use the set sim mode rc command this set of rules is applied to the entire circuit by default m search ckt ud Use this set of rules for digital only blocks If you use the set sim mode ud command this set of rules is applied to the entire circuit by default Applying Multiple Autodetection Rules TheACE option allows you to apply different autodetection rules to individual portions of a circuit If you do not specify an autodetection command by default the search ckt msx rules are applied to the entire circuit However if you apply an autodetection command to a portion a block of the circuit that portion is searched with rules set by
63. are a couple of reasons why a circuit could end up consuming an unexpectedly large amount of power If a node spends an excessive amount of time in a U state it could create a large short circuit current PowerMill User Guide 112 Chapter4 Power Analysis Thereport node u and report node quick configuration commands provide a mechanism to check for excessively long and excessively short rise fall times respectively during the dynamic simulation Each command checks the time taken by the node to transition between its logic high and low threshold and reports violations to the err file By default the logic high and low thresholds are set to 70 and 30 of the nodes high voltage respectively You can use the set node thresh command to adjust the default voltage Detecting Dynamic Floating Nodes Z State Nodes If a node is left floating Z state for an excessive time the node voltage could drift into an intermediate voltage level due to sub threshold short circuit currents in the associated elements This can lead to unexpected DC paths in logic blocks that arein the node fanout The report node z configuration command provides a mechanism to report any node that stays in the Z state longer than a user specified time during the dynamic simulation Violations are reported to the err file Detecting Excessive Branch Currents When attempting to diagnose excessive power in a circuit it is often helpful to determine which circuit e
64. ath cat max powrl run max power cat max powr2 run max seq power cat max powr3 run custom The preceding scripts contain the following command lines respectively powrmill n full spi adder cmd c cfqg full o full p tech powrmill n block spi adder cmd c cfg1 block o blockl p tech powrmill n block spi adder cmd c cfg2 block 0o block2 p tech powrmill n block spi adder cmd c cfg3 block 0o block3 p tech powrmill n dcpath spi adder cmd c cfg_dcpath o dcpath p tech powrmill n max com power spi c cfg max power o maxpower p tech powrmill n max seq power spi c cfg max power o maxpower p tech powrmill n max seq power spi c cfg max power fm gap customize c 0 custom All of the run scripts contain the powrmill command with the n c p and o options specified See Chapter 1 The PowerMill Command in the PowerMill Reference Guide for more information on command line options Although all of the simulations in this chapter use SPICE netlists you can combine SPICE EPIC Verilog and EDIF in Advanced PowerMill Simulations 29 the same run If a netlist file with a sp or spi extension is used the parser assumes it isan HSPICE netlist and sets all nodes and elements to lowercase by default 2 Usethe UNIX cat command to display the contents of the confi guration files as needed cat Cfg ful cat cfg1 bl cat cfg2 bl
65. ation and inversion regions Normally the exact flat band voltage point is in the negative voltage region below zero Vgs and is not critical to most simulations A large area square transistor of 50 um by 50 um is used to avoid short channel effects and give a large enough capacitance to give a measurable current A 1 ohm series resistor is used as the monitoring element The current through this resistor is plotted to produce the CV curve PowerMill User Guide 140 Chapter6 ACE Tutorials Files Needed for this Tutorial The following table lists the files needed for this tutorial They are located in the ACE cv curve directory Filename Description cfg_cv Batch run configuration file CV_curvespi SPICE netlist for this tutorial runcv Run script for this tutorial cmos35 mod BSIM3 v3 model file Procedure Use the following procedure to run the CV curve tutorial 1 Using vi or another text editor open and study the CV curvespi netlist file Notice that this is a very simple short netlist Notice that the PWL voltage source sweep is over 4 us This is done so that the time scale corresponds to the voltage scale The full voltage sweep is 4 V from 2 V to 2 V The 2 us point will be the zero volt point of the sweep since the time starts at zero You can subtract 2 from the time to get the voltage at any given point 2 Run the simulation using the runcv script Getting the Input Files 141 3 UsingturboWave l
66. axrf U 119 report node powr U 23 U 86 U 100 report node quick U 112 report node u U 112 report node z U 112 report probe i U 100 U 101 U 122 search ckt analog U 126 U 128 search ckt cpump U 126 search ckt logic U 126 U 128 search ckt mem U 126 U 128 search ckt msx U 126 U 127 search ckt rc U 127 search ckt ud U 127 See Command Index on page R 457 set_dcpath_thresh U 38 U 115 set_elem_acc U 131 set_elem_pwl U 131 set_elem_sms U 131 set_elem_sync U 131 set_hotspot_factor U 114 set_node_aspd U 129 set node spd U 129 set node thresh U 112 U 119 set print ires U 131 set print iwindow U 102 set print tres U 131 set print vres U 131 set sim aspd U 130 set sim spd U 130 set sim subgroup U 130 set sim trap U 156 set sim tres U 129 use sim case U 10 configuration files U 12 configuration files specifying R 4 connectivity changing R 105 to nodes R 66 tracing R 327 R 328 current reporting R 145 R 174 R 189 resolution setting R 299 waveforms printing R 111 R 119 R 126 R 134 current printing and reporting block U 87 element U 98 histogram U 101 node U 99 probes U 100 current resolution controlling U 132 233 D dangling nodes reporting R 171 DC current R 119 DC initialization R 30 DC paths dynamic R 147 finding tutorial U 37 static R 152 U 117 threshold setting R 224 delimiter hierarchical R 298 diagnosing power problems dynamic U 111 static U 116 diagnostics functionality R 337 R 338 R
67. be the first bank of 4 adders and block2 the second bank of 4 adders fmConfigCmd report block powr blockl track_power 1 x1 fmConfigCmd report block powr block2 track power 1 x27 Register arguments and function pointer of customized objective function fmRegisterGap p blockl p block2 fitness Figure 20 Excerpt from registration function The first two lines use the fmConfigCmd function to specify a PowerMill configuration command that maps the x1 and x2 blocks to the block1 and block2 power tracking variables They also tell the simulator what to track by setting the track power argument to 1 Next the fmRegisterGap function maps the power of block1 and block2 variables into the GAP algorithm They are used in the fitness function NoTE The asterisk 4 wild card specifies that all four adders in each bank are to be included in the block specifications Advanced PowerMill Simulations 73 Find the execution function at the top of the file see Figure 21 double fitness static int id_4_blockl_powr id_4_block2_powr double sum 0 if fmSimPhase FMDCINITPHASE get id for signals which can be used later to access their value id_4_blockl_powr fmGapGetSignalld p block1l id 4 block2 powr fmGapGetSignallId p block2 return 0 else calculate fitness measure sum fmGapGetValueById id_4_block1_powr fmGapGetValueById id_4 _block
68. cfile 15 event resolution voltage esv setting 128 F file samples epicrc file 15 block power report 229 files See epicrc files See input files G GAP feature 103 tutorials 41 50 69 Gentech utility 12 graphical analyst child cells 198 path tracing 199 power diagnostics browser error list 191 show info about box 196 H hierarchy browser options menu 196 panning display 195 path tracing 199 select instances to display 198 set expansion threshold 197 show instructions 196 tree display 195 histogram current 101 HSPICE SPICE netlists 11 input files configuration 12 netlist 11 stimulus 13 technology 12 J J FET models 13 243 K Kirchhoff s Current Law 99 L leakage current detecting DC paths 115 measuring 88 logic diagrams adder drcuit with four bit output register 27 call of four bit adder circuit 20 four bit adder circuit 19 xor2 cell 20 maximum power estimation 41 103 Seealso GAP feature memory shared 229 MESFET models 13 mixed signal simulation 125 models directly supported BSIM1 13 BSIM2 13 BSIM3 v3 13 J FET 13 MESFET 13 MOS9 13 multirate simulations ACE 130 N netlist file formats 11 types of stimulus 13 NMOS 118 node current printing 99 hotspot checking 112 PowerMill User Guide 244 Index simulating 129 U state checking 111 Z state checking 112 node sensitivity control 128 p PMOS 118 power assigning power budgets 93 estimating maximum p
69. chine This feature is only available on HP UX and Solaris platforms 230 Using Shared Memory PowerMill User Guide Combined Index Symbols SEPIC HOME U 13 U 21 U 137 U 205 dcpath file sample U 39 epicrc file description U 10 keywords U 14 sample U 15 A A command line option U 132 ACE configuration commands See Command Index on page R 457 ACE tutorials CV curve generation U 139 differentiator simulation U 149 integrator simulation U 147 PLL SPICE macro modeling U 151 U 156 step input simulation U 145 voltage follower simulation U 143 ADFMI model debugging DFM R 5 model swapping R 324 see also ADFMI Manual specifying R 333 using the FM fm command line op tions R 6 aesv default value R 380 R 390 setting simulation R 390 aliases R 100 creating R 19 R 100 deleting R 49 for pattern matching R 102 analog circuit simulation U 125 U 134 U 137 U 158 aspd U 129 aspd setting for simulation R 391 autodetection rules applying analog circuit detection R 356 charge pump circuit detection R 357 memory circuit detection R 358 mixed signal circuit detection R 359 autodetection selection U 125 automatic techfile generation U 12 232 Combined Index automatic vector generation U 103 Seealso GAP feature batch mode U 10 BJ T modeling R 355 R 365 R 367 block power analysis U 31 U 87 U 88 U 90 U 91 block level power See power analysis branch currents excessive R 161 printing R 109 re
70. clock period to be used by the GAP estimation For sequential circuits the period should be the same as the clock signal defined in the netlist file or cmd file If you do not specify a period the GAP estimation will use the default period of 20 ns e Usethedelay option to synchronize GAP with the signal dock if it is not started from time 0 e Usethe vec history option specify which vectors will be kept in the history files At the end of the simulation GAP produces a history file corresponding to each vector file used during the estimation If you do not specify a history option GAP keeps only the vector pairs or triplets from the generation producing the maximum power e Usethe save history option to save the circuit state during a GAP simulation You can use the save history option in conjunction with the vec history option to specify how the state files of the circuit will be saved You can use the saved state files to either resume the GAP estimation from a saved time or do advanced power analysis for specific generations under GAP Therange of the saved state information is dependent on the setting for the vec history option vec history 1 saves only the state at the beginning of the generation that produces the maximum power vec history 2 saves the state at the beginning of all the generations that improve the maximum power estimation Using the GAP Feature to Estimate Maximum Power 107 vec history 3 saves
71. cmd d ff mark_node_latch no q print_probe_i inst customize_gap_fitness Each linein this fileis critical to the function of the GAP feature use vec gap vec max_seq_power vec As in tutorial 6 the vector file max seq power vec contains only the PIs This command registers this vector file to GAP estimation A vector history is tracked for this vector file as the simulation progresses set gap opt delay 100ns period 40ns vec_history 2 This command synchronizes GAP s time window with the clock driving the circuit by specifying a delay of 100ns anda period of 40ns This command also uses the vec_history option to tell the simulator to track the vector history for all generations that improve the maximum value of the fitness function Notice that the save history option is disabled therefore no state files printed with a Z extension are generated for this GAP simulation NOTE The clock to Q time is not considered for the circuit in this tutorial since delay through the combi national part of it can satisfy thehold time of theFF s Otherwise you would need to set Advanced PowerMill Simulations 71 the delay option of the set vec opt command to be equal to the clock to Q time E guide gap search fit 3 level 7 This command enables GAP customization by setting the fit option to 3 which notifies GAP that the average value of the fitness function defined in an ADFMI C file should be the objective to maximize This c
72. command could overwrite that file or directory 3 Verify that your newly copied ACE directory contains the following subdirectories crystal osc cv curve op amps and pll Each of these directories corresponds to and contains the files needed for a tutorial in this chapter SPICE Netlists All tutorials in this chapter use SPICE format netlists Conversion to EPIC format is not necessary Getting the Input Files 139 Tutorial 1 CV Curve Generation This tutorial demonstrates the procedure for checking the voltage dependent gate capacitance CV curve Figure 1 provides a schematic of the CV curve test circuit proportional to C of MN1 Cdv dt O RIN 1 ohm MN1 PWL voltage source 38 4 38 4 2v to 2v over 4ms to set dv dt constant The current through RIN is monitored and is proportional to C of MN1 because dv dt is constant as supplied by VIN This results in a current waveform that is the CV curve of the voltage dependent gate capacitance of MN1 The time sweep of VIN is set so that Tus corresponds to 1 volt of change Figure 1 Schematic of CV curve test circuit Checking the voltage dependent gate capacitance CV curve is done using the relation i C dv dt In the example circuit used in this tutorial the current i is made proportional to the capacitance C by the input of a linear voltage ramp so that dv dt is a constant The voltage is swept from 2 V to 2 V to cover the depletion accumul
73. commended that you not simulate crystal oscillators in the full chip configuration It is better to drive the input side of the inverter with a SPICE style sinewave source This produces realistic behavior of the oscillator input clock buffers to the interior of the circuit and accurate power consumption numbers L eave the external load capacitors in place and remove the crystal model to prevent the simulator from trying to handle the RLC model and slow the simulation down unnecessarily Chapter 7 Using the PowerMill Graphical Analyst 160 Chapter 7 Using the PowerMill Graphical Analyst Overview 161 Overview The PowerMill simulator s Graphical Analyst GA provides an integrated approach to simulating circuits and analyzing results using the PowerMill simulator We value your comments and encourage you to give us feedback You can give us direct feedback by selecting Feedback from the File menu of the PowerMill GA main window See File Menu on page 165 for details This chapter explains how you can use the PowerMill Graphical Analyst to do the following tasks Running a Basic PowerMill Simulation Starting the Graphical Analyst Setting Up a Run Running a Simulation Analyzing a Circuit The followi ng tools are available for circuit analysis Power Consumption Power Histogram DC Path Browser Power Diagnostics Browser Hierarchy Browser Running a Basic PowerMill Simulation This section describes the proce
74. ction see the ADF MI Manual for more information If you are using arguments of type 6 or 7 you first need to create the corresponding blocks or probes using the appropriate configuration commands for example report block powr assign node i etc Likewise to use arguments of type 8 you need to define the math signals using HSPICE print probe or plot control lines PowerMill User Guide 110 Chapter4 Power Analysis 3 Register the objective fitness function In the ADFMI registration function RegisterUserModel invokethe GAP registration function fmR egisterUserGap see Figure 7 To it you need to provide a the function pointer of the objective C function and b a string containing the names of all the arguments used in defining the fitness measure In the string the space character serves as the delimiter to separate argument names Customized objective function to be maximized F double fitness static int id_4_blockl_powr id_4_block2_powr double sum 0 if fmSimPhase FMDCINITPHASE get id for signals which can be used later to access their value id_4_blockl_powr fmGapGetSignalId p block1 id_4_block2_powr fmGapGetSignalld p block2 return 0 else calculate fitness measure sum fmGapGetValueById id_4_block1l_powr fmGapGetValueById id 4 block2 powr return sum void RegisterUserModel f Specify block power for blockl and block2
75. d They are shown in italic text to distinguish them from commands and keywords tag Tags can be followed by either a value or a keyword value Tags and keywords are in the base font Argument keyword values are in italics to distinguish them from commands keywords and tags Symbol Definition A pipe symbol represents the word or and separates choices between two or more arguments An ellipsis indicates that more than one argument can be specified Ellipses are used only for multiple arguments with tags PowerMill User Guide XIV About This Manual Symbol Definition Open and closed square brackets indicate that the enclosed arguments are optional Open and closed parenthesis indicate that there is a choice between the enclosed arguments two or more These are used only when a command has several groups of argument choices multiple pipe symbols in this case would result in ambiguous syntax SYNTAX report node i a vg r ms pleak h ist node name s For this command a vg r ms p eak and h ist are keywords choose one of these The node name s are user determined EXAMPLE 1 report node i a VDD GND In this example a is a keyword and VDD and GND are values SYNTAX report node ic a ll qluoted for epic spice ti me s For this command a ll and q uoted are optional keywords The tag for is part of an optional argument for which you can choo
76. d 3 0 at the beginning of dock cycle Il This is also true for the second and third vector triplets which verifies the functionality of the FFs or latches as described in the section Testing Latch Functionality for Flip Flops with Non Buffered Outputs on page 53 11 Open the cfg_max_powe file 12 Remove the following line print node logic s1 d PowerMill User Guide 68 Chapter 3 PowerMill Tutorials NOTE 13 Remove the max gen 1 argument from the guide gap search command specification 14 Run the regular GAP simulation using the run max seg power script At this point you can resume the regular GAP procedure starting with step 5 on page 58 When you use PathMill instead of PowerMill to detect the PPIs the maxpower ppi vec file is replaced by the pathmil ppi vec file therefore the corresponding maxpower ppi gav is replaced by the pathmill ppi gav file Advanced PowerMill Simulations 69 Tutorial 7 Customizing a GAP Objective Function using an ADFMI Code File This tutorial illustrates an advanced GAP feature which allows you to customize the objective function using an ADF MI C file Using this feature you can create your own objective function to be maximized by GAP instead of using the two default objective functions A customized objective function is a regular C function in an ADFMI C file You can use various circuit parameters for example node voltage node current element branch cu
77. d Reporting Branch Currents Using PowerMill you can print many different types of branch currents There are commands that print instantaneous average and RMS currents as waveforms to the out file PowerMill also provides commands to report average RMS and peak current summaries to the log file The branch current printing commands follow the HSPICE conventions for i1 i2 i3 and i4 currents The following list shows the branch current mapping for MOS transistors i1 drain current i2 gate current Analyzing Power Consumption 99 i3 source current i4 bulk current PowerMill also provides commands for printing and reporting DC current for specifi ed elements Use the following commands to print all types of branch currents print branch didt1 print branch i3 print branch didt2 print branch i3avg print branch didt3 print branch i3rms print branch didt4 print branch i4 print branch didtdc print branch i4avg print branch il print branch i4rms print branch ilavg print branch idc print branch ilrms print branch idcavg print branch i2 print branch idcrms print branch i2avg report branch i print branch i2rms report branch powr For more specific information on each command see Chapter 2 Configuration and Interactive Commands in the Power Mill Reference Guide Printing and Reporting Internal Node Currents It is sometimes useful to be able to measure the amount of current flowing through an internal non voltage so
78. dify the simulation time resolution EXAMPLE set sim tres 0 0lps This example sets the minimum time resolution to 0 01 ps Once you choose the appropriate time resolution you can apply additional time step control commands to control the time step Changing the Time Step Selection Parameter You can use the set node spd and set node aspd for analog commands to change the size of the time step for a particular node EXAMPLE 1 set node spd VCO IN 0 05 PowerMill User Guide 130 Chapter5 Using the ACE Feature This command sets the time step size parameter spd at node VCO INto 0 05 V With this setting the maximum voltage change each time step at node VCO IN cannot exceed 0 05 V Additionally you can use the set sim spd and set sim aspd for analog to change the size of the time step selection parameter spd for the entire simulation EXAMPLE 2 set sim spd 0 3 This example sets the simulation step size parameter spd to 0 3 V With this setting the maximum voltage change at each time step cannot exceed 0 3 V Applying Multiple Time Steps Multi Rate Simulations In mixed speed systems such as DSPs or other discrete sampled circuits with a high clock speed sampling low frequency signals it might be necessary to use the multi rate simulation capability The ability to do multi rate simulations means that you can apply different time steps to different parts of the circuit Using multiple time steps helps yo
79. dure for running a basic PowerMill simulation using the Graphical Analyst 1 Set up your environment so that you can access the directory containing the current PowerMill release see Chapter 2 Getting Started for details Have the following input files in your current directory PowerMill User Guide 162 Chapter7 Using the PowerMill Graphical Analyst Anetlist filein SPICE HSPICE xxx spi or EPIC format xxx ntl Oneor more technology files xxx tech A vector file optional e Any additional configuration files optional 3 Start the Graphical Analyst by typing one of the following commands at the UNIX prompt pwga powrmill ga 4 Select Simulation Setup Design Data Setup 5 Select the applicable netlist technology and configuration files 6 Click OK This will create a wrk file by default After it is created you can specify it when invoking the Graphical Analyst and the Setup Information will be automatically entered by PowerMill 7 Click the Start Simulation button This invokes the simulation in the powrmill pwga directory This directory contains the confi guration files automatically created by the GUI as well as the following output files powrmill log powrmill err and powrmil out 8 Click the Result Analysis button to access the analysis tools 9 When you are finished viewing the results close the window Starting the Graphical Analyst As stated previously you can start
80. e 7600 00 a mo 7 Figure 13 Supply net histogram To return to the block histogram select Options Show Block Histogram Using the Histogram You can view the average or peak current for each time segment displayed in the histogram To view the average current for a particular time segment click your left mouse button on a time segment block in the histogram A time marker along with the average current for the selected segment will appear To view the peak current for a segment use your middle mouse button to click on a segment or move the marker to another segment PowerMill User Guide 186 Chapter7 Using the PowerMill Graphical Analyst You can access the histogram for lower level blocks if they have been specified in the Supply and Block Setup form To dothis double click on a block with your left mouse button To come up a level double click on a block with the right mouse DC Path Browser The DC Path Browser graphically displays transistors from DC paths at predefined intervals To open the DC Path Browser click the DC Path Browser button in the Result Analysis form see Figure 14 No of dc paths 8 5 ia STITT 0 293 313 333 353 373 393 413 433 453 473 493 513 533 553 573 Simulation Time ns 2 ADDER1 XOR2B 3 ADDER1 3NOR F 4 ADDER1 P1 gt A Figure 14 DC path browser Analyzing a Circuit 187 File Menu After you ve completed your DC path analysis you can dose the
81. e vbfe Average current RMS current e vnbl Average current RMS current e vsc Average current RMS current e gnd Average current RMS current e currents e vbwe Average current RMS current 9764 697468 uA 13 538631 179937 712787 uW 259344 959596 uW 1292 744780 uA 2689 379684 uA 13 113817 uA 60 555783 uA 1 306000 uA 1 306000 uA 0 000000 uA 0 000000 uA 0 096472 uA 125 248341 uA 0 000000 uA 0 000000 uA 3254 654260 uA 6735 633010 uA 46 280923 uA 65 944698 uA 48 694494 uA 65 990722 uA 22 313620 uA 35 782504 uA 40465 456275 uA 62012 343945 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 45127 965926 uA 64878 957946 uA 0 001269 uA 0 014343 uA Node vbcas Average current RMS current Node vbras Average current RMS current Biput node currents Node Node Node Node Node Node Node Node Node Node Node Node Node Node Node Node Node vdin Average current RMS current vdq0 Average current RMS current vdql Average current RMS current vdq2 Average current RMS current vdg3 Average current RMS current vainl Average current RMS current vaino Average current RMS current vain2 Average current RMS current vain3 Average current RMS current vain4 Average current RMS current vaind Average current RMS curr
82. e you can combine SPICE EPIC Verilog and EDIF in the same run If a format is not specified PowerMill uses the file extension to determine the format For information on supported netlist formats and their corresponding extensions see Chapter 3 Netlist Compiler and Translators in the EPIC Tools Reference Guide Using HSPICE SPICE Format If a netlist file with a sp or spi extension is used the parser assumes the netlist is in an HSPICE format and sets all nodes and elements to lowercase Don t use case sensitive node names and element names if you are going to use SPICE netlists If a SPICE netlist is not specified the netlist input by default is case sensitive You can override this default setting with the use_sim_case configuration command HSPICE Netlist Compatibility PowerMill is capable of recognizing measure commands in HSPICE netlists For more information about HSPICE netlist commands see HSPICE Netlist Syntax in Chapter 3 of the EPIC Tools Reference Guide PowerMill User Guide 12 Chapter2 Getting Started Using Other Formats For information on supported netlist formats see Chapter 3 Netlist Compiler and Translators in the EPIC Tools Reference Guide Configuration Files The configuration file contains information that tells PowerMill how to perform the simulation Any number of configuration files including none can be used The configuration file contains run parameters data N
83. e Hierarchy Browser by clicking the Hierarchy Browser button in the Powermill GA main window Setting Up fora Simulation 211 The Hierarchy Browser appears see Figure 5 ADDERO ADDER ADDERZ ADDERS Figure 5 Hierarchy Browser You can use the procedure outlined below to view the power consumption for lower level blocks within the design hierarchy This process shows you how to drag and drop blocks from the Hierarchy Browser to the Power Supply amp Block Setup form PowerMill User Guide 212 Chapter8 PowerMill Graphical Analyst Tutorial 1 In the top display area of the Hierarchy Browser Hold down the Shift key and use the left mouse button to expand the hierarchy for the block identified as ADDE R3 See Figure 6 for a sample Hierarchy Browser Jo Instance Name ADDER __ Instance Type ADDER _ Name And Type ADDERZ 2NOR INVI INV2 INV3 INV4 ADDER3 Selected Instance JADDER3 3NOR Figure 6 Expanding the ADDERS block 2 Inthe Hierarchy Browser select the 3NOR instance with the left mouse button This highlights the instance 3 Usethe middle mouse button to drag it into the empty Block Setup field in the Power Supply amp Block Setup form To add additional blocks click the Add Block button in the form to create another empty field and use the drag and drop feature to include them Setting Up for a Simulation 213 4 Select File Close
84. eal AG ge dee eine KAN aati eg aaa ect 9 The PowerMill Environment 0 0 0 a 9 The PowerMill Command a 10 Batch Versus Interactive Mode 0 0 0 0 cc eee 10 Environment File deserere aaee a ee ee eee 10 Netlist FISS ce ele mil ae ack Bayan Balad hacen ood el AREE DAA mpa 11 Using HSPICE SPICE Format 00000 e eae 11 HSPICE Netlist Compatibility 11 Using Other Formats 0 00000 cee eee 12 Configuration Files rriad ewak nie a i a E E 12 Technology PINES ma pana meha penai BG a a dite SG a ies ANA 12 Table of Contents Stim l s Files uban Daan hee LA Da a ae Ghee tebe eats 13 Creating the Environment epicrc File aa 13 Running a Basic Simulation 0 000 15 PowerMill Tutorials OVEIVIEW soc naa ae td Vas daw dea wits vos ead SG haa Wwe to 19 Tutorials Included in this Chapter 00000005 21 Getting the Input Files 2 2 0 0 0 cece 21 A Basic PowerMill Simulation 0 0 0 0 2 cee eee 22 Tutorial 1 Running a Basic Simulation 22 Procedure HA eh mar tA e dle Ue Nee Git the oe 22 Advanced PowerMill Simulations 0 000 25 Before Y o BEGIN po pins cued dete ag DP Da See ba a 27 Tutorial 2 Performing a Full Chip Power Analysis 29 Files Needed for this Tutorial 004 29 Procedure aa Wie KNANG ee eke Bea Gea AA 30 Tutorial 3 Performing a Block Level Power A
85. ecify the blocks you want to use in the simulation To do this click the Supply Block Power Setup button in the Simulation Setup Setting Up for a Simulation 209 dialog box The Power Supply amp Block Setup form will appear see Figure 4 Power Supply amp Block Setup Form i VDD CdS OO power GND ground Kia aaa PODER fer li a Power Supply Setup Use this form to indicate the different power supplies i e VCC VDD GND etc their voltages and whether or not they are Power or Ground nodes Use the right mouse Sutton to bring up a popup which allows you to select between power ground Note that only the power supplies listed here are read as a default The interface makes an effort to identify some of the power supplies for you but it may not be a comprehensive list OK Cancel Figure 4 Power Supply amp Block Setup form Normally at this point you would set up multiple power supplies However because the circuit used for this tutorial contains only one supply node power supply set up is not necessary Your next step is to specify the blocks for which you want power consumption information By default all the blocks at the top level of the design are selected PowerMill User Guide 210 Chapter8 PowerMill Graphical Analyst Tutorial To get the power information for lower level blocks you can add additional blocks by dragging and dropping them from the Hierarchy Browser First bring up th
86. ecifying Netlist and Technology Files You can either select the netlist and technology files manually or use the File Finder form 1 To reopen the File Finder form click the appropriate Browse button located next to the Netlist Files or Tech File text fields in the Design Data Setup form Click the OK button to save your settings and close the form PowerMill User Guide 172 Chapter7 Using the PowerMill Graphical Analyst NOTE To automatically generate technology files you can specify the z or r options in the Others field of the Design Data Setup form Setting the Simulation Time Enter the number of nanoseconds you want the simulation to run for in the Simulation Time text field of the Design Data Setup form The default is 1000 ns Design Library Specify the path to your design library in the Design Library text field this is optional Command Line Options The Others text field of the Design Data Setup form is used to specify powrmill command line options Saving Clearing or Cancelling Your Changes 1 After you ve filled in the appropriate fields of the Design Data Setup form click the OK button This saves your settings compiles the design and closes the form It also created a batch run script with a batch extension The batch run script can be run from the UNIX command line It automatically places the results in the appropriate directory so that you can view the results of a batch simulation at
87. ed signal designs xii About This Manual Audience For information on Tutorials that give detailed instructions and scenarios of how to use the Analog Circuit Engine ACE option of the PowerMill simulator See Chapter 6 ACE Tutorials Instructions for using the PowerMill Graphical Analyst Chapter 7 Using the PowerMill Graphical Analyst A tutorial on the PowerMill Graphical Analyst Chapter 8 PowerMill Graphical Analyst Tutorial Sample output files Appendix A Sample Power Reports Using shared memory Appendix B Using Shared Memory This manual is for integrated circuit engi neers and designers performing power simulations to test and verify integrated circuit designs Knowledge of UNIX high level design techniques and circuit description tools such as SPICE is assumed Related Manuals The following Synopsys manuals in the EPIC tool set provide additional information on using PowerM ill m PoweMill Reference Guide m EPIC Tools Reference Guide m ADFMI Manual xiii Conventions This manual uses certain style conventions to indicate commands menus examples and filenames Commands SYNTAX command name argument s argument types keyword value tag value tag keyword Command Definition Argument keyword Keywords are identifiers that must be used as they appear They are shown in base font value Values are user determine
88. effect of applying a hot spot factor of 0 5 As you can see the node with the largest currents is X1 4 which has a charging current of 503 21 pA anda discharging current of 510 44 uA Applying the 0 5 hotspot factor the sum of the charging and discharging currents multiplied by the hotspot factor equals 506 83 uA The sum of any other node s charging and discharging current would have to be greater than this number to be included in the individual node report In this case all nodes below x1 3 are excluded from the report The summation of charge currents for all nodes within a block represents the average charge current for the block Conversely the summation of discharge currents for all node within a block represents the average discharge current for the block The difference between the total average block current and the charge current should be the average short circuit current from DC short circuit or the short circuit short circuit current during the transition period when both NMOS and PMOS Performing a Dynamic Power Consumption Analysis 115 transistors were conducting This is one way of estimating the circuit short circuit current Detecting Dynamic DC Paths In CMOS circuits any DC current flowing in the circuit between power and ground is considered to be wasted power Therefore wasted power can come from crowbar or short circuit current caused by both P channel and N channel devices being on during a transi
89. enerates a report of the total power consumption of the block The power reported includes contributions from all sources and biputs for the block Average block power 179937 712787 uW RMS block power 259344 959596 uW Figure 3 Sample information provided by the track power option of the report block powr command You can also produce block level waveforms and current histograms For more details seethePoweMill ReferenceGuide and Working with Probes on page 100 Measuring Power Hierarchically The level and at level options of the report block powr command allow you to do an analysis of block level power in a hierarchical netlist You can use these options to request power reports for all hierarchical sub blocks of the specified circuit block with a single command The level option automatically generates power reports for all sub blocks of the specified subcircuit down to the specified level EXAMPLE 1 report block powr top level 2 This command generates a power report for the entire circuit and automatically generates reports for all sub blocks down to level 2 such as x1 x2 x1 x1 and x1 x2 Theat level option generates power reports only for the sub blocks at the specified level EXAMPLE 2 report block powr top at level 2 PowerMill User Guide 92 Chapter4 Power Analysis NOTE This command generates power reports for the entire circuit and the second level sub blocks x1 x1
90. ent vainb Average current RMS current vain7 Average current RMS current vain8 Average current RMS current vain9 Average current RMS current vainlo Average current RMS current vainll Average current RMS current Sample Block Power Report 225 0 001368 uA 23 447023 uA 0 001682 uA 30 281411 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 000000 uA 0 095737 uA 44 265948 uA 3 260720 uA 38 813769 uA 3 260651 uA 38 813809 uA 0 095980 uA 44 266041 uA 3 260651 uA 38 813809 uA 3 260651 uA 38 813809 uA 0 095980 uA 44 266041 uA 0 095979 uA 44 266041 uA 0 001632 uA 1 129229 uA 3 263539 UA 39 380620 uA 0 001632 uA 1 129229 uA 0 001632 uA 1 129229 uA PowerMill User Guide 226 Sample Power Reports Sample power File power file format 5 4 PowerMill Version 5 4 SN P0O81899 Sun0s 5 Copyright c 1999 Synopsys Inc All Rights Reserved KIKKIKKIKKKKKKKKKKKAKKAKKAKKKKKAKKKKKAKKKKKAKKAKKAKKKKKAKKAKKAKKKKKAKKAKKAKKAKKAKK RUN TIME POWER BUDGET VIOLATIONS KIKKIKKIKKKKKIKKKKKIKKAKKAKKAKKIKKKKKAKKKKKKKKAKKKKKKKKKKKAKKAKKAKKAKKAKKAKKAKKKKK BLOCK top DRAWS EXCESSIVE POWER FROM 10 8 TO 10 9 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 20 9 TO 21 ns BLOCK top DRAWS EXCESSIVE POWER FROM 20 8 TO 21 1 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURREN
91. ent so you can access the directory that contains the current PowerMill release 2 Havethe following input files in your current directory PowerMill User Guide 16 Chapter2 Getting Started e A epicrc file optional e Netlist files in any supported format including SPICE xxx spi HSPICE xxx spi and EPIC format xxx ntl Technology files optional e Configuration files optional Stimulus files optional Create a run script for your simulation This script should contain the powrmill command with the appropriate options specifying your input files EXAMPLE powrmill n adder spi c cfg p techfil o adder Give the script a meaningful name such as runpw or runpw scr Run the simulation by entering the name of the run script EXAMPLE runpw These output files will be generated adder log adder err and adder out For more information on output files see Chapter 4 PowerMill Output Files in the PowerMill Reference Guide View the output files with the turboWave or SimWave waveform viewer To do so type in the name of the viewer followed by the name of the output file you want to view EXAMPLE turboWave f adder out Chapter 3 PowerMill Tutorials 18 Chapter 3 PowerMill Tutorials Overview 19 Overview This tutorial demonstrates both basic and advanced PowerMill simulations using the 4 bit adder shown in Figure 1 Figure1 Logic diagram of the four bit
92. ent voltages All supplies constant voltage sources with voltages above the logic high threshold and grounds constant voltage sources below the logic high threshold are assumed equivalent For circuits that have multiple supplies or grounds report ckt leak also searches for the following conditions which can lead to unintended DC paths m Partial off PMOS A PMOS transistor with a source or drain that has a possible channel connected path to a supply or input node with high voltage VDDH In addition its gate has a possible channel connected path to a supply or input node with high voltage VDDL where the voltage of VDDH is greater than VDDL m Partial off NMOS An NMOS transistor with a source or drain that has a possi ble channel connect path to a ground or input node with low voltage GNDL In addition its gate has a possible channel connect path to ground or input node with low voltage GNDH where the voltage of GN DH is greater than GNDL m Forward bias PMOS A PMOS transistor with a source or drain terminal that has a possible channel connected path to a supply or input node with high voltage VDDH In addition its substrate is connected to a voltage source of voltage VDDL where VDDH is greater than VDD m Forward bias NMOS Analyzing Power Using the RC and UD Simulation Modes 119 An NMOS transistor with a source or drain terminal that has a possible channel connected path to a ground or input node with high voltage
93. er Guide 90 Chapter4 Power Analysis Figure 2 shows a sample of the additional information provided by the track wasted option This report provides the following information about the block m Average and RMS capacitive current Thetotal current expended in charging block capacitances m Average and RMS wasted current Thetotal DC current consumed by the block and not used to charge the block capacitances m Leakage Percentage The fraction of current consumed by the block from all sources that is not used to charge block capacitances Average capacitive current 39057 934468 uA RMS capacitive current 56567 265346 uA Average wasted current 6115 921641 uA RMS wasted current 9764 697468 uA Wasted current percentage 13 538631 a U U E Figure 2 Sample information provided by the track_wasted option of the report_block_powr command You can also produce a block level waveforms and current histograms for the capacitive and wasted currents For more details see the PowerMill Reference Guide and Working with Probes on page 100 Measuring True Power in Watts Using PowerMill you can obtain the true power consumption in watts for a given circuit block To do this you need to specify the track power option when using the report block powr command EXAMPLE report block powr my block track power 1 x1 x1 Analyzing Power Consumption 91 In addition to the basic current reports this command g
94. erent options to produce reports specifically tailored to your needs This section details the differences between the reports produced by the three block power runs in this tutorial block1 log Figure 8 shows a portion of the block power reports printed in the block1 log file These condensed reports provide information Advanced PowerMill Simulations 35 on the basic current consumption for each block This information includes the average and RMS current for the block as well as the reported current peaks and the times at which they occurred By default the simulator provides the five highest peaks over the reporting interval In this case the reporting interval is the entire simulation You can use the set_print_ipeak command to request the printing of additional current peaks Node x1 vdd Average current 5 98305et01 uA RMS current 3 13568et02 uA Current peak 1 4 90200e 03 uA at 2 50100e 02 ns Current peak 2 4 89100e 03 uA at 4 10100e 02 ns Current peak 3 4 89000e 03 uA at 5 70100e 02 ns Current peak 4 4 82500e 03 uA at 9 01000e 01 ns Current peak 5 4 82500e 03 uA at 7 30100e 02 ns Node xl_gnd Average current 6 10597e 01 uA RMS current 3 11328e 02 uA 90200e 03 uA at 89100e 03 uA at 89000e 03 uA at 82500e 03 uA at 82500e 03 uA at 50100e402 ns 10100e102 ns 70100e 02 ns 01000e 01 ns 30100e102 ns Current peak 1 Current peak 2 Current peak 3 Current peak 4 Current peak
95. erter biases to the operating point View the contents of the cfg2 file and notice the addition of the set sim trap command Run the next simulation using the run script You will see the oscillator start up at about the 200 us point The oscillations grow exponentially until they are about full amplitude around the simulation end time of 400 us This simulation does not run particularly fast duetothe use of the default time resolution tres of 10 ps View the contents of the cfg3 file and notice the addition of the set_sim_tres 1n command This relaxes the minimum event time resolution to 1ns from 10 ps Run the simulation using the run3 script Notice that this simulation runs much faster than that run with the run 2 script Using turboWave load the following files xtal1 out xtal2 out and xtal3 out Load the signals you want to see see Figure 15 PowerMill User Guide 158 Chapter6 ACE Tutorials File Signal View Waveform Analog Tools Window Help sla asjale Jam Jo fame zB e Ay fu Figure 15 Waveforms of signals from out files Discussion Normally it is not necessary to simulate crystal oscillators because their behavior is well known The small signal transconductance of the inverter required for start up can be easily calculated and the MOS devices sized accordingly You can effectively simulate crystal models in the megahertz range using the set_sim_trap configuration command It is re
96. es 5 umber of block biput nodes 17 umber of block input nodes 3 umber of block output nodes 0 umber of block stages s 1 5 9 7 umber of block partial stages 0 Average supply current 45144 660642 uA RMS supply current 64875 016572 uA Average ground current 45127 965926 uA RMS ground current f 64878 957946 uA Average input current 0 004319 uA RMS input current 46 694417 uA Average output current s 0 000000 uA RMS output current 0 000000 uA Average biput current 16 694782 uA RMS biput current 293 473489 uA Average capacitive current 39057 934468 uA RMS capacitive current f 56567 265346 uA Average wasted current 6115 921641 uA 224 Sample Power Reports RMS waste d current Wasted current percentage Average block power RMS block power Supply node currents oq oq oq oa oa oa oa oa oa oa oa e vdq Average current RMS current e vext Average current RMS current e vr2k Average current RMS current e vbprst Average current RMS current e vrad Average current RMS current e vref Average current RMS current e vecex Average current RMS current e Vbbex Average current RMS current e vplex Average current RMS current e vblex Average current RMS current e vdd Average current RMS current Ground node currents oa oq oa oa oq Input nod Nod e vwpb Average current RMS current
97. ess information as a graph of the curve of the maximum power vs the number of applied input vector pairs see Figure 13 Maximum Power Estimation T T T T T E 1 1 1 1 1 a 16 56 66 26 30 46 Number of Yector Pairs Applied Figure 13 Graphical format of GAP estimation progress report 6 Close the window containing the graph 7 Specify thereport gap parameters command at the interactive prompt PowerMill User Guide 46 Chapter 3 PowerMill Tutorials This command shows the current settings of various GAP options In this tutorial the following information is printed to the screen Current settings of parameters options for GAP Fitness function is peak average power History option nd Population size S 2G Search level 5 Clock period 20 ns No upper limit on CPU time No upper limit on number of generations No upper limit on number of vector pairs No upper limit on value of fitness function 8 Specify the report_gap_prediction command at the interactive prompt This command predicts a cut off point for the estimation that you can use to reduce the total CPU time of the GAP estimation The number returned is a prediction of the total number of vector pairs that need to be applied before the estimation converges From this number you can subtract the number of pairs already applied as reported by the report_gap_progress command to determine the number of additional pairs that need to be appl
98. ess you probably need to determine how much power is consumed by each block This information allows you to optimize blocks using the most power PowerMill provides some configuration commands useful for retrieving information on power consumption at the block level See Analyzing Power Block by Block on page 87 for details on the PowerMill User Guide 32 Chapter 3 PowerMill Tutorials configuration commands for block analysis This tutorial illustrates how you can use the PowerMill simulator to analyze power block by block Files Needed for this Tutorial The following table lists the files needed for this tutorial These files are located in thepw advanced block powr subdirectory in your working directory Filename Description adder cmd EPIC format netlist file that describes the filename for the vector file and the node names and port ordering for the vector file adder vec Tabular digital vector file used as the digital stimulus for the simulation cfg1_block Configuration files for block power analysis cfg2_block cfg3_ block block spi SPICE netlist of the circuit for block power analysis run1 block Run scripts for block power analysis run2 block run3 block tech typ 25c 5v Technology file Procedure Use the following procedure to run the block level power analysis tutorial 1 Open each of the configuration files and study the commands used Each configuration file illustrates a dif
99. etect ckt latch configuration command to detect latches See Using PathMill to Detect PPIs on page 64 for details Testing Latch Functionality for Flip Flops with Non Buffered Outputs If FFs or latches within the circuit are not buffered at the output you have to perform an experimental GAP run to determine whether or not you can apply the vector triplet method 1 Use the print node logic command to print the logic waveform of the inputs and outputs of two or three FFs for each type used in the circuit for a few vector triplets PowerMill User Guide 54 Chapter 3 PowerMill Tutorials 2 For each triplet verify that the values at the inputs by the end of clock cycle are equal to the values at the outputs at the beginning of clock cycle II This test verifies that the FFs or latches correctly latch the state driven by the first vector in the triplet and that the state is not contaminated by the PPI stimulus itself This procedure is illustrated in Using PathMill to Detect PPIs on page 64 If you cannot verify this it is suggested that you run GAP on the sequential design using the vector pair approach see tutorial 5 Files Needed for this Tutorial The following table lists the files needed for this tutorial These files are located in the pw_advanced max_powr2 subdirectory in your working directory Filename Description cfg_max_power Configuration file for maximum power estimation max seq power
100. f the four DFFs Notice that these DFFs are 1 positive edge triggered 2 buffered at the output and 3 instances defined by the subcircuit definition d The clock signal has a delay of O ns a period of 40 ns and a 5096 duty cycle as described by the PULSE independent source function Towork properly using the vector tripl et method GAP needs to be synchronized with the clock signal driving the circuit To achieve synchronization you need to perform the following procedure Apply theperiod option with theset gap opt command to specify the period for the GAP estimation which should be equal to the clock period 40 ns in this tutorial and Apply the delay option with the set gap opt command to specify the delay for the GAP time window which should be equal to the delay of the clock O ns in this tutorial PowerMill User Guide 58 Chapter 3 PowerMill Tutorials NOTE You don t have to use the delay option with the set gap opt command for this circuit since the default starting time for GAP is O TheFF s dock to Q time is not considered in this tutorial delay through the combinational part of the circuit is used to satisfy the hold time If you have a circuit for which the clock to Q time needs to be taken into consideration you would need to specify the values correctly before running GAP For example suppose the clock signal starts from 100 ns and the clock to Q time of the FFs is 0 5 ns To synchronize
101. ferent way to get block power information The information returned is different for Advanced PowerMill Simulations 33 each file Each command separates the VDD and GND current for each block by assigning unique probe names Run the simulation three times once for each run script When the simulation is finished list the directory contents The directory now contains several output files with the block1 block2 and block3 prefixes Open and examine the block1 l0g block2 10g and block3 log files Notice the differences between the block level reports in the different log files In this case only the current for each adder cell is reported therefore the blocks are small The block power reporting principle applies to large blocks of a chip See Differences Between the Resulting Block Power Reports on page 34 for a detailed analysis of each report PowerMill User Guide 34 Chapter 3 PowerMill Tutorials 5 Load the block3 out file in turboWave and display the average power waveforms for gnd and srcin each block see Figure 7 File Signal View Waveform Analog Tools Window Help sf elele js Jo al izi fy fo 900 Bp Tengo NU i Em bA NG NG PG PA BANNA mananan Figure 7 Waveforms of block analysis of output file block3 out selected signals Differences Between the Resulting Block Power Reports As this tutorial demonstrates you can use the report_block_powr command with diff
102. first path is displayed in the Path Schematic area at the bottom right corner of the browser To view a particular path click a path name in the DC Paths text field The schematic for the path you selected is displayed in the Path Schematic area Analyzing a Circuit 189 Standalone Version of DC Path Browser TheDC Path Browser can be run as a standalone tool To invoke this version use the dcpviewer command EXAMPLE dcpviewer dcpth filename The DC Path Browser will appear and display the DC paths contained in the particular dcpath file you specified In standalone mode you can open any Powermill dcpath file by selecting File Open Log File Power Diagnostics Browser You can use the Power Diagnostics Browser to graphically view and sort diagnostic information including static configuration checks multiple toggles and dynamic rise fall times To load the Power Diagnostics Browser click the Power Diagnostics Browser button in the Result Analysis form see Figure 17 PowerMill User Guide 190 Chapter7 Using the PowerMill Graphical Analyst Power Diagnostics Browser Static Paths Excessive Rise Fall Time Click these buttons to JE Node Does Not Settle To Rails set error report below W Undriven Nodes Excessive Transistor Current _ Multiple Transitions Include or exclude nodes Click here to show error report below 113 mx1 N1 Node is floating Single NMOS transfer gate on node Single NM
103. for the subcircuit x1 x1 under the label my block The block power report provides a statistical analysis of the block including the number of elements internal nodes source nodes and biput nodes By default it also lists the average and RMS source ground input output and biput currents for the block See Sample Power Reports on page 223 in Appendix A for a sample block power report This report is first printed to the screen and then reported in the log file at the end of the simulation Using optional arguments the report block powr command can report the average and RMS ground current and produce a list of the current supplied by each individual supply ground input output and biput node You can also produce a block level waveform and current histogram For more details see the PowerMill Reference Guide and Working with Probes on page 100 Measuring Wasted Power PowerMill defines wasted power also called short circuit current for a circuit block as any DC current consumed by the circuit block that is not used to charge block capacitances or capacitances driven by the block Specifically PowerMill defines the total current consumed by the block as the sum of the total supply current and the current from the bi puts that are acting as supplies The current from biputs acting as ground is not included Analyzing Power Consumption 89 consumed current total supply X biput currents ix 0 The con
104. for example a sibling instance the hierarchy browser display will change to refl ect the new hierarchy context Again only the parent children and sibling instances of the selected instance will be highlighted in blue see Figure 24 Children of new L ldp selected instance New selected instance 1 Former selected instance becomes a sibling instance Figure 24 Context shift after selecting a related instance Drag and Drop You can drag and drop text from the panning display area or the instance information fields located at the bottom of the Hierarchy Browser Analyzing a Circuit 201 1 Click the middle mouse button on the text you want to drag then move the mouse cursor 2 Release the middle mouse button when the cursor is in the appropriate position The text will appear in the new location PowerMill User Guide 202 Chapter7 Using the PowerMill Graphical Analyst Chapter 8 PowerMill Graphical Analyst Tutorial 204 Chapter8 PowerMill Graphical Analyst Tutorial Overview 205 Overview This chapter gives you step by step instructions for running the PowerMill Graphical Analyst tutorial The following tasks are covered Getting the Input Files Starting the Graphical Analyst Setting Up for a Simulation Running the Simulation Analyzing Results Getting the Input Files Before you can run the graphical analyst tutorial in this chapter you need to copy the required input fil es t
105. gh the voltage in the technology file is 5 0 V and the VDD is 3 0 V the simulator sets the thresholds to more reasonable values by checking the neighboring connection However it is good practice to always use the set node thresh command to set appropriate threshol ds Comment out all the last report ckt leak command report ckt leak Uncomment each of the other report ckt leak commands one by one and rerun the simulation each time This process allows you to see the error messages that are particular to different types of topologies NOTE The report_ckt_leak command is set up so that if one possible error presumes others only the most serious error is reported For example if a node is stuck_at_1 it is equivalent to saying that it has a static path to VDD and no path to gnd If the stuck at 1 error is reported the nc gnd and to vdd errors are not reported since they are redundant Chapter 4 Power Analysis 84 Chapter4 Power Analysis Overview Overview 85 This chapter addresses the various features provided by PowerMill for the analysis and diagnosis of power use for your circuits and includes information on the following subjects Analyzing Power Consumption Using the GAP Feature to Estimate Maximum Power Performing a Dynamic Power Consumption Analysis Performing a Static Power Consumption Diagnosis Analyzing Power Using the RC and UD Simulation M odes In discussing PowerMill simulation results the term
106. grator Simulation e Differentiator Simulation m Tutorial 3 PLL SPICE Macro Modeling m Tutorial 4 Crystal Oscillator Simulation These tutorials are written with the assumption that you know how to run vi or another editor and turboWave or another waveform viewer Therefore the specific steps for opening and reopening files loading signals are not explicitly stated NOTE The turboWave screens in this chapter were captured with altered colors and signal height This was done to make the screens more readable in print format The waveforms you will see in turboWave will look significantly different from the screens in this chapter Getting the Input Files Before you can run any of the tutorials in this chapter you need to locate and copy the required input files to your current working directory The following procedure shows you how to do this 1 Set the correct path to which the EPIC HOME environment variable is set If you need assistance see your Systems Administrator PowerMill User Guide 138 Chapter6 ACE Tutorials CAUTION 2 Copy recursively the complete contents of SEPIC HOME tutorials ACE to your local working directory cp R SEPIC HOME tutorials ACE This command copies the ACE directory into the current working directory the period tells the cp command to copy to the current directory If thereis an existing file or directory called ACE already in your current working directory this
107. h approximately 200 CM OS transistors In general the GAP estimation is more efficient in results and CPU time than a random simulation Procedure 1 Usethe configuration command use vec gap to specify the vector file with type vec to be used for the maximum power estimation For sequential circuits you can only provide the primary input vector file You can automatically generate a vector file containing all the pseudo primary inputs PPIs by applying the mark node latch command See Tutorial 6 Estimating Maximum Power for Sequential Circuits on page 50 a detailed description of PPI detection In the vector file inputs biputs and pseudo primary inputs output of memory elements should be distinguished by character i b and p If no io command is specified all the signals are considered to be inputs You can specify one or more vector files The following sample configuration file shows how multiple vector files are specifi ed use vec gap vec sepl vec vec sep2 vec set gap opt period 10ns vec_history 3 guide gap search time 30 pattern 20000 fit 2 The vector files can contain vectors to be used by the genetic algorithm as part of the first generation PowerMill User Guide 106 Chapter4 Power Analysis 2 Usethe set gap opt command to set various GAP options for controlling the estimation flow This command has two parameters that you can set e Usethe period option to set the
108. h as the Hierarchy Browser see Figure 19 Bo al N3 mx1 N1 E i A E F 113 mx1 N1 a Single NMOS transfer gate on node Single NMOS transfer gate on node Single NMOS transfer gate on node Figure 19 Dragging and dropping a node name The Power Diagnostics Browser provides wild card support For example if you want to see the errors on nodes in block A you can select the following only on nodes A or A or Ar By default selected errors on all nodes are displayed H owever to help in filtering the errors you can use wild cards to filter nodes for particular blocks For example you can select only on nodes a or A if you only want to see the errors on the nodes in block A Another option is to drag the block A from the Hierarchy Browser Analyzing a Circuit 193 To view detailed information select an Error in the display area A detailed description is printed in the Detailed Error Description window File Menu After you have completed your diagnostic information analysis you can close the Power Diagnostic Browser by selecting File Close Power Diagnostics Browser Waveform Tool The Powermill Graphical Analyst supports two waveform tools Simwave and turboWave The default tool is turboWave Use the Options menu of the PowerMill GA main window to select a particular waveform tool Based on your selection the Results Analysis window will display and invoke either turboWave or Simwave H
109. he solution space to minimize maxi mize a specified objective function called a fitness function Part of this work is based on the Synopsys sponsored university research project led by Professor Kwang Ting Cheng and Ph D Candidate Yi Min J iang from the Department of Electrical and Computer Engineering at the University of California Santa Barbara The GAP feature is able to maximize four objective functions m Average power per clock cycle of the circuit m Instantaneous power of the circuit m Average value per clock cycle of the customized fitness function m Instantaneous value of the customized fitness function The GAP feature generates a tight lower bound on the maximum power of a given circuit At the beginning of the estimation GAP selects a specific group of vector sets to be kept These vector sets PowerMill User Guide 104 Chapter4 Power Analysis are comprised of either vector pairs or triplets depending on the circuit type see tutorials 5 6 and 7 in Chapter 3 for details The GAP feature measures the quality of each vector pair based on the power consumption it produces when applied to the circuit At each generation GAP performs operations on the vector files in the kept group to improve their quality The concept of the quality of vector pairs improvi ng with every generation is analogous to the biological concept of natural selection You can control the size of the specific group called the population
110. his tutorial you will learn how to model the system behavior of a PLL by using controlled sources to model the different sections of the system The phase detector and charge pump are modeled with a voltage controlled current source The 1 s integrator term is modeled with a voltage controlled current source with a gain of 1 driving a 1 farad cap The output of this cap drives a voltage control led voltage source This voltage source has all the gain terms of the loop lumped together except for the charge pump current and the loop filter The loop filter components are used as they are in the RC network Files Needed for this Tutorial The followi ng table lists the files needed for this tutorial They are located in the ACE pll directory Filename Description cfg Batch run configuration file pll2gm spi SPICE netlist for the PLL macro model simulation runpllm Run script for the PLL macro model simulation Procedure Use the following procedure to run the PLL SPICE macro modeling tutorial 1 Study the schematic in Figure 12 This schematic shows the controlled sources as triangle symbols similar to op amp symbols There are two voltage controlled current sources and two voltage controll ed voltage sources The loop filter components are entered as they would normally appear in the transistor level netlist Getting the Input Files 153 Loop Gain K Kp Kvco n 1p 4r Af AV 1 n Where Kp 2zlp Kvco 2rAf AV
111. hreshold TheSet Expansion Threshold form will appear 2 Click on the sliding bar and move it until the appropriate setting appears above the bar 3 Click OK when you are done adjusting the bar PowerMill User Guide 198 Chapter 7 Using the PowerMill Graphical Analyst Select Instances to Display If an instance contains more child cells than the expansion threshold the Select Instances to Display form will appear see Figure 22 a Select Instances To Display q Undisplayed Displayed 3 120 121 122 123 128 129 131 gt gt lt lt OK Cancel Help Figure 22 Select instances to display window This form allows you to choose the child cells you want to display in the instance tree Choosing Child Cells to Display in the Instance Tree 1 Select the child cells you want to display 2 Press the 55 button to move them to the Displayed column 3 Ifyou do not want child cells to display select them from the Displayed column and press the lt lt button The child cells will move to the Undisplayed column Analyzing a Circuit 199 Choosing Multiple Instances at one Time 1 Select an instance 2 Hold down the Shift key and click on the last selection you want in the list All the names from the first selection to the last are selected To de select an instance press the control key and dick on an instance When the Select Instances to Display form is complete the selected child cells wil
112. ich use switch level simulation techniques produce a faster average power estimation with reasonable accuracy aS compared to the default PWL mode RC mode PowerMill User Guide 120 Chapter4 Power Analysis provides full delay information for CMOS circuits while UD mode only provides fixed unit delay information Technical Background The power dissipation in digital CMOS circuits consists of two major parts capacitive power and short circuit power see Figure 10 T l total leap qu C percent short circuit _ x 100 Itotal leap lsc Figure 10 Short circuit sc current calculation Switching current usually plays a major role in most digital circuits When runningin RC or UD mode the simulator calculates the average power based on the charging and discharging of node capacitances That is the charging or discharging current due to a voltage change dV at a node is C dv dt wherec isthe capacitance and at is the transition time of the node This can accurately estimate the average switching power in circuits For CMOS circuits short circuit current estimation in the RC or UD mode is based on the input and output slopes and is less accurate than PWL mode In RC or UD mode the simulator estimates the short circuit current Isc using the switching Analyzing Power Using the RC and UD Simulation Modes 121 capacitive current I cap and the ratio of the input
113. ied before the estimation converges For example if the report_gap_prediction command returns 1000 and the report_gap_progress command reports that 700 vector pairs have already been applied it is likely that the estimation will converge produce the best result after applying an additional 300 vector pairs You can then apply the guide_gap_search max_vec 300 command to cut off the estimation appropriately NoTeE As with other extrapolation processes the accuracy of the prediction from this command is limited Although this command might reduce the CPU time for the simulation it might also reduce the accuracy Advanced PowerMill Simulations 47 of the result Therefore you should only follow the prediction from report gap prediction command when reducing the CPU time is critical 9 Specify cont sim at the interactive prompt This restarts the GAP estimation 10 When the estimate is done list the contents of the current directory This directory contains output files with a maxpower prefix 11 Open and examine the maxpowe gap file see Figure 14 Estimates of maximum average power from the GAP feature only those generations increasing maximum power are listed Generation 0 Maximum power 0 00540997 Vec 0 010000000 Vec 1 101011011 Generation 1 Maximum power 0 00559405 Vec 0 101011001 Vec 1 110100101 Generation 6 Maximum power 0 00640677 Vec 0 010010100 Vec 1 101101001
114. ierarchy Browser TheHierarchy Browser provides you with a visual display of the netlist hierarchy To open the Hierarchy Browser click PowerMill User Guide 194 Chapter7 Using the PowerMill Graphical Analyst the Hierarchy Browser button located at the middle left side of the PowerMill GA main window see Figure 20 Hierarchy Browser Help instructions w Instance Name core main w Instance Type 4 Name And Type io driver Panning display Tree display 4 Selected Instance w Selected Net List of pins in selected Instance Figure 20 Hierarchy browser File Menu After you are done using the Hierarchy Browser you can close it by selecting File Close Hierarchy Browser located at the top left corner of the window Hierarchy Display The Hierarchy Browser contains the following display areas Analyzing a Circuit 195 m Panning display located on the left side of the window this shows you what portion of the tree is currently being displayed in the tree display m Treedisplay located on the upper right side of the window this shows a portion of the netlist s instance hierarchy Panning Display The panning display shows the layout of the tree The rectangle in the tree layout indicates the portion of the tree that is currently visible in the tree display You can update the portion of the tree displayed by clicking on the rectangle and draggi ng it Tree Display Initially the hierarchy in the tree di
115. ile it registers it with GAP simulation The following messages appears on the screen Reading configuration files PPI dumping has been completed Adding vec file custom ppi vec to GAP and restarting GAP estimation The simulation resumes automatically in GAP mode 8 When you see that the simulation has progressed somewhere beyond generation 8 type Cont rol c to stop the simulator in interactive mode 9 Type report gap parameters at the interactive prompt This interactive command prints a status report of GAP parameters to the screen see Figure 23 Current settings of parameters options for GAP Fitness function is peak average power History option Population size Search level Clock period upper limit CPU time upper limit number of generations upper limit number of vector triplets upper limit value of fitness function Figure 23 Report of GAP parameter settings This command allows you to view and check the current setting of the GAP parameters including the vector history option population size search level and various stopping criteria for example CPU time number of generations and number of triplets PowerMill User Guide 76 Chapter 3 PowerMill Tutorials 10 Typereport gap progress at theinteractive prompt This command prints a progress report for the GAP simulation to the screen see Figure 24 GAP result so far time secs of triplets max power watts 0 000714735 0100001
116. iler FRGA Compiler Il FRGA Express Frame Compiler Fridge General Purpose Post Processor GPP HDL Advisor HDL Compiler Integrator Interactive Waveform Viewer Liberty Library Compiler Logic Model MAX ModelSource Module Compiler MS 3200 MS 3400 Nanometer Design Experts Nanometer IC Design Nanometer Ready Odyssey PowerCODE PowerGate Power Compiler ProFPGA ProMA Protocol Compiler RMM RoadRunner RTL Analyzer Schematic Compiler Shadow Debugger Silicon Architects SmartModel Library Source Level Design SWIFT Synopsys Graphical Environment Synopsys ModelFactory Test Compiler Test Compiler Plus Test Manager TestGen TestSim TetraMAX TimeTracker Timing Annotator Trace On Demand VCS VCS Express VCSi VERA VHDL Compiler VHDL System Simulator Visualyze VMC and VSS are trademarks of Synopsys Inc Service Marks TAP in is a service mark of Synopsys Inc All other product or company names may be trademarks of their respective owners Printed in the U S A Document Order Number 32647 014 HB PowerMill User Guide Release 5 4 PowerMill User Guide Table of Contents About This Manual xi Introduction to PowerMill OVErVIOW a iy Setter ae Nh BY bot ee we Vda ap oe Ea hn Mey Gok ee dea 3 Major Functions and Features 0 00 cee eee eens 3 Inputs Outputs and Interfaces 00 002 4 Getting Started ONE EN TEN lise ced coe ote and shack a Wags w
117. ing procedure shows you how to do this 1 Set the correct path for the EPIC HOME environment variable If SEPIC HOME is not set see your system administrator Copy recursively the files from SEPIC HOME tutorials pw basic and pw advanced to your local working directory The files in these directories and their subdirectories are needed for the tutorials in this chapter cp R SEPIC HOME tutorials pw basic cp R SEPIC HOME tutorials pw advanced PowerMill User Guide 22 Chapter 3 PowerMill Tutorials These commands copy the pw basic and pw advanced directori es respectively into the current directory the period tells the cp command to copy to the current directory 3 Verify that your newly copied pw advanced directory contains the following subdirectories block powr dc path full chip max powr1 and max powr2 Each of these directories corresponds to and contains the files needed for an advanced tutorial in this chapter SPICE Netlists All tutorials in this chapter use SPICE format netlists Conversion to EPIC format is not necessary A Basic PowerMill Simulation The tutorial in this section demonstrates a basic PowerMill simulation using the UNIX batch mode Tutorial 1 Running a Basic Simulation The following table lists the files needed for this tutorial These files are located in the pw_basic directory Filename Description cfg Batch run configuration file adder spi SPICE net
118. ing the PPIs You can manually specify the PPIs along with Pls in the GAP vector files The vector files used for a GAP simulation which use the same format as the EPIC vector files provide information regarding the signals to be stimulated for example name io and radix Advanced PowerMill Simulations 53 This approach is only feasible for small sequential designs since identifying PPIs manually can be time consuming and error prone Using GAP s Built in Mechanism In hierarchical designs FFs or latches might have subcircuit definitions For these designs you can use the mark_node_latch command together with the set_ckt_cmd command to identify their output automatically see the command definition for mark node latch in the PowerMill Reference Guide Similarly you can use the mark node latch command and the set pattern cmd together to identify PPIs if FFs or latches are defined as patterns Using this approach you only need to provide GAP with vector files that include the Pls GAP automatically generates and adds a vector file containing all the PPIs identified by the mark node latch command to the GAP estimation This tutorial illustrates this method of PPI detection Using PathMill s Latch Detection Feature If you havea circuit description that does not contain subcircuit or pattern definitions for flip flops and latches and you own a copy of the PathMill simulator you can use PathMill on the circuit with the pw d
119. ing up for a simulation run You can alsoselect Design Data Setup from the File menu Both of these actions cause the Design Data Setup form to appear See Setting Up a Run on page 167 for more information on this process Start Simulation Button The Start Simulation button is used to invoke a simulation run See Running a Simulation on page 179 for more information Result Analysis Button The Result Analysis button is used to access the PowerMill GA analysis tools after you have completed a simulation run See Result Analysis Button on page 166 for more information Hierarchy Browser Button The Hierarchy Browser button gives you access to a visual display of the netlist hierarchy See Hierarchy Browser on page 193 for more information Simulation Log Display The Simulation Log text field located near the top of the main window displays log information as the simulation progresses It will notify you when a simulation is finished Error Warning Display The Error Warning display shows you error and warning messages as a simulation progresses Result Display The Result Display located near the bottom of the main window gives you visual power consumption information See Analyzing a Circuit on page 180 for more information Setting Upa Run 167 Sort By Menu The Sort By menu located above the Result Display allows you to sort the kind of power consumption you want to display Setting U
120. ion Period 800 00ns aa ORA Displays instances o 4 78uA Displays peak or average current value Displays histogram Simulation time marker average current Figure 11 Power histogram browser File Menu After you ve completed your hierarchical power analysis you can close the Power Histogram Browser by selecting Close Power Histogram Browser from the File menu View Menu You can analyze power consumption data in the Power Histogram Browser from a variety of views including zoomed out and zoomed in views and block and supply net views PowerMill User Guide 184 Chapter 7 Using the PowerMill Graphical Analyst To see a zoomed out view of the display select Zoom Out from the View menu see Figure 12 File View Option Curre Fit Into Window Zoom Out Power Histogram Browser File View Option Current Instance 7600 00 Figure 12 Zoom out view of power histogram browser Select Zoom In from the View menu to return to the original view To fit the entire power consumption display into the window select Fit Into Window from the View menu Analyzing a Circuit 185 Options Menu The Options menu lets you view either the supply net or block net histogram To see the supply net histogram select Options Show Supply Net Histogram see Figure 13 Fle View Option Current Inst Show Supply Net Histogram Shaw Glock Histogran Power Histogram Browser File View Option Current Instanc
121. ional and io optional Vector files for the GAP estimation differ from normal vector files in the following ways e A normal vector file must contain at least one vector However as you can see by examining the max com powerl vec and max_com_power2 vec files a vector file for a GAP simulation can contain O vectors e Normal vector files have four valid io types i input o output b biput and u unused Vector files for a GAP simulation have three valid io types i input p pseudo primary input PPI and b biput If no io statement is specified all signals in the file are considered inputs Vector files for the GAP estimation can contain vector pairs to be used as part of the first generation for the genetic algorithm All other first generation vectors are randomly generated You can use the guide_gap_seach command to specify the population size to control the number of input vector pairs applied in a generation The GAP estimation does not work on circuits in a wave pipelining design the clock period used in a GAP simulation must be longer than the delay along the critical path of the circuit The default clock period is 20 ns However you can use the set_gap_opt command to override the default with the period option In the cfg_max_power configuration file the set_gap_opt command specifies a clock period of 20 ns and a history option of 1 the default value therefore only the vector pairs of the generation
122. is red Click the Set All button at the bottom of the form to activate all blocks By default all blocks at the top level of the design are selected Specify the budget violation threshold for each block in the Budget text fields The Add Block button at the bottom of the form adds a set of text fields for a new block You can type in lower level block names or drag and drop names from the Hierarchy Browser Saving Clearing or Cancelling Your Changes NOTE m Saving After you ve made your changes click the OK button to save your settings and close the Block Setup form Clearing Click the Clear button to clear all information on the form Cancelling Click the Cancel button to close the form without saving your changes If you do not invoke the Power Supply amp Block Power Setup form default values are automatically assumed The supply node voltages default to the values specified in the technology file The power for the top level blocks is automatically calculated if there are less than 100 blocks in the design The configuration commands needed to calculate the power for the selected blocks are placed in a file called suppl ybl ock cfg in the Powermill GA run directory by default powermill pwga and are automatically applied to the run PowerMill User Guide 176 Chapter7 Using the PowerMill Graphical Analyst Power Diagnosis Setup You can use the Power Diagnosis Setup form to set static power excessive
123. it to end the simulation and exit PowerMill User Guide 64 Chapter 3 PowerMill Tutorials 7 Open and examine the maxpower log file Current information calculated over the intervals 0 00000e 00 2 40010e 03 ns Node stagel total_power Average power 7 03574et02 uW Node stage2 total_power Average power 7 8741let02 uW Node ff_array total_power Average power 9 66177e 03 uW Node gap total_power Average power 1 11595e 04 uW This file contains power reports for the following four blocks The 4 bit adder at the first stage stagel total power e The4 bit adder at the second stage stage2 total power Theflip flops ff array total power Thewhole circuit gap total power This report also includes various current statistics for example average and RMS supply current and average and RMS input current for individual blocks Using PathMill to Detect PPIs In this tutorial the circuit description in the max_seq_power ppi file contains a subcircuit definition for FFs therefore you can use the mark node latch and set ckt cmd commands to do PPI detection automatically However if your circuit does not contain a subcircuit or pattern definition for FFs or latches and you havea copy of the PathMill simulator you can use PathMill s latch detection feature to generate a PPI vector file that you can use with a GAP estimation NOTE Advanced PowerMill Simulations 65 If you
124. itivity R 390 printing the phase R 74 printing the time R 75 time step R 331 R 360 simulation execution deleting interactive breakpoi nts R 50 listing interactive breakpoints R 95 setting simulation breakpoints R 225 R 248 simulation mode U 119 PWL mode R 256 R 295 RC mode R 257 R 300 UD mode R 265 R 266 R 300 R 315 simulation modes U 131 simulation time resolution U 129 PowerMill User Guide 238 Combined Index SimWave R 418 sinusoidal stimulus setting the points in a period R 308 spd setting for analog simulations see aspd for simulation R 301 on nodes R 258 U 129 spf printing node voltage R 131 SPICE model level 37 model R 239 level 41 model R 239 using charge conservation R 239 SPICE netlist format R 8 stage getting information R 76 printing R 76 state tracing connectivity R 330 static power analysis U 116 step size control R 331 stimulus descriptions See netlist file stimulus files U 13 stimulus options R 318 subthreshold current R 366 R 373 swapping ADF MI models R 324 T technology files automatic generation R 9 U 12 specifying R 9 technology files controlling grid size R 137 threshold voltage R 261 time resolution control U 129 output R 290 simulation R 303 time step control R 331 control tres U 129 selection parameter spd changing U 129 time simulation R 75 tracing connectivity R 327 R 328 tracking intervals setting R 286 R 292 U 101 transistors NMOS R 88 transistors
125. ks area by clicking the toggle button located to the right of the Find DC paths at times line Then enter the values as shown below Find DC paths starting at 253ns and every 20ns report paths gt 04mA Enter the following values in the Report Hazards area Report nodes with multiple transitions within any ins period Click OK to save your changes and exit the Power Diagnosis Setup form Then click Dismiss in the Simulation Setup form You are now finished with the set up process Running the Simulation Torun the simulation click the Start Simulation button in the Powermill GA main window Notice that the simulation messages are displayed in the Simulation Log text field Note also that error and warning messages appear in the Error Warning text field When the simulation is finished the Result Display area of the window displays power consumption of the first level of the design hierarchy Analyzing Results 215 Figure 8 shows the Results Display area of the PowerMill GA main window Result Display Present Instance Sort By 8 Average Current uA ADDERO 360 40uA ADDER1 190 10ua 116 54uA 56 50ua Fl Ig FI The Total Current 723 58uA Figure 8 Results Display area of the PowerMill GA main window Note that you can use the Sort By menu to select various display options Select Wasted Current from the menu and notice how the display changes Use your left mouse button t
126. kt_leak command to flag such nodes However a static DC short circuit path which is independent of the external stimulus rarely exists in CMOS circuits A dynamic short circuit path is more likely however it requires a specific input condition that might not occur The report_ckt_leak command can find a static DC path as well as detect several unusual topological conditions in regular CMOS designs These conditions although insufficient to confirm a definite DC short circuit path might uncover potential short circuit paths The report_ckt_leak command searches for the following conditions m Partial Swing Detection A node is driven by NMOS PMOS transistors only and it drives at least one PMOS NMOS transistor s gate m No Path to VDD GND T here is no possible conducting path to the node from a supply ground node m Static Path to VDD GND T here exists a static conducting path from a supply ground node to the node m Nodeis Stuck at High low Voltage A static conducting path exists between the node and a supply ground node In PowerMill User Guide 118 Chapter4 Power Analysis addition there is no possible conducting path between the node and any ground supply node m Static DC Path There exists a static conducting path between two voltage source nodes For the conditions mentioned above the report ckt leak command does not take into account difficulties due to multiple supplies or grounds with differ
127. l appear in the tree display A file cabinet icon represents those child cells not displayed To expand the file cabinet press the Shift key and click your left mouse button This re opens the selection form so you can add or remove child cells from the display If you select an instance inside a file cabinet it will appear in the tree display If the display of the instance s children exceeds the expansion threshold the Select Instances to Display window will appear Save Options You can save the current option states by selecting Save Options from the Options menu This causes the Hierarchy Browser to use the current option states the next time the current design is opened Displaying Connectivity To start tracing a path dick on an instance name in the tree display hierarchy Then select a pin from the list at the bottom of the browser To trace a path you must select both an instance and a pin You can select only one instance and one pin at a time PowerMill User Guide 200 Chapter7 Using the PowerMill Graphical Analyst When you select a pin the parent children and sibling instances connected in the net to the selected instance are highlighted in blue in the tree display see Figure 23 Sibling of selected instance Parent of selected instance Selected instance Children of selected instance Figure 23 Example of a selected instance and related instances If you click another connected instance
128. lements might be carryi ng unexpectedly large currents You can use the report elem exi command monitor the currents of specified elements and report those elements that have currents exceeding a specified threshold for a specified time during the dynamic simulation PowerMill reports violations to the err file Analyzing Hot Spot Node Currents When you are redesigning for lower power consumption it s helpful to know how each circuit node contributes to the total power consumption The report_node_hotspot command lists Performing a Dynamic Power Consumption Analysis 113 the average current statistics for the specified nodes in the sum file A sample hot spot report is shown in Figure 5 KKEKKKKKKKKKKKKKKKKKKKKKKKKK KKK HOt Spot Statistics KKEKKKKKKKKKKKKKKKKKKKKKKKKK Node Name Cap fF Toggle Icin uA Icout uA X1 4 4150 91 6 503 21 510 44 1 45 6150 91 6 455 08 496 35 x19 4150 91 6 354 64 450 23 X1 3 2150 91 6 27999 270 87 X1 8 650 91 6 81 96 81 85 Khat 650 91 6 81 80 81 77 X12 150 91 6 18 96 19 00 X1 7 150 91 6 18 88 18 90 X1 6 150 91 6 Loe LG 18 09 1 69 23 6 8 66 7 96 Total non input nodes H 10 Total node toggles 60 Total charging current 1821 34 uA discharging current Figure 8 Sample hot spot report The hot spot report provides the following information for each node m Average Node Capacitance umped from netlist wiring and transistor gate and diffusion capacitances m T
129. list for adder circuit adder vcd Verilog description file adder vtran Control file for changing Verilog into EPIC format run Run script for this tutorial tech typ 25c 5v Technology file Procedure Use the following procedure to run the basic tutorial A Basic PowerMill Simulation 23 1 Usethe UNIX cat command to display the contents of the run script cat run This script contains the following line powrmill n adder spi adder cmd c cfg o adder p tech The run script specifies the SPICE netlist adder spi and the command file for processing the netlist adder cmd It also specifies the cfg and tech configuration and technology files In addition the o option setting instructs PowerMill to use a prefix of adder for all output files resulting from this run See Chapter 1 The PowerMill Command in the PowerMill Reference Guide for more information on command line options NOTE Thereis no e in the powrmill command 2 Usethe UNIX cat command to display the contents of the configuration file cat cfg This file contains the following configuration commands print_node_logic print_node_v report_node_powr gnd vdd The first command prints all nodes in a digital format The second command prints all nodes as voltage waveforms The last command creates a report in the adder 0g file of the average RMS and the five highest peak currents in the circuit Average and RMS waveforms are a
130. log nodes using the set sim esv set_sim_aesv set sim spd and set sim aspd commands EXAMPLE 1 set sim esv 0 01 This example sets the event resolution voltage of all digital nodes to be 0 01 V EXAMPLE 2 set sim aesv 0 01 This example sets the event resolution voltage of all analog nodes to 0 01 V Any voltage change from its last event voltage higher than 0 01 V will schedule an event provided there is no local esv setting In some cases different parts of the circuit could have different sensitivity requirements In this case you can apply the set node spd and set node esv commands to individual nodes Controlling the Simulation Time Resolution 129 EXAMPLE 3 set node esv vco in 0 01 This example sets the event resolution voltage at node vco_into 0 01 V Any voltage change from its last event voltage higher than 0 01 V schedules an event at node vco in EXAMPLE 4 set node spd VCO IN 0 05 This command sets the spd value at node vco IN to 0 05 V Controlling the Simulation Time Resolution Normally you will not need to modify the default simulation time resolution 10 ps However when simulating low frequency audio applications you might need to increase the time resolution the minimum time step to perhaps to 1 ns If all nodes move slowly a simulation time resolution of 10 ns or even 100 ns could provide sufficient accuracy with a high simulation speed You can use the set_sim_tres command to mo
131. lso be printed to the adder out file PowerMill User Guide 24 Chapter3 PowerMill Tutorials See Chapter 2 Configuration and Interactive Commands in the PowerM ill Reference Guide for more information on these commands Use the VTRAN program to create the vector stimulus file for this simulation vtran adder vtran M essages indicating the execution of the vtran command are displayed VTRAN generates two files adder cmd and adder vec The adder vec file contains the tabular vectors for this simulation The adder cmd file contains the following line is vec en adder vec ot cin a 3 0 b 3 0 This line calls the adder vec file and provides the signal order for the vector file to the simulator See the VTRAN 3 5 User Manual for more information Run the simulation with the run script When the simulation is finished list the directory contents Several output files with the prefix adder are created Use turboWave to view the waveforms turboWave amp From the turboWave main window select File Open to open the adde out file Advanced PowerMill Simulations 25 8 Usethe Signal pull down menu to select the signals to view see Figure 4 File Signal View Waveform Analog Tools Window Help pf PAA PANN NN JA v an nana Aaa I_rms gnd I_rms vdd Figure 4 Waveform of basic adder circuit selected signals 9 When finished viewing the waveforms select File
132. lus types see Chapter 5 Stimuli and State Checking in the EPIC Tools Reference Guide Creating the Environment epicrc File A file named epicrc can be used to specify most of the command line options for the powrmill command Although not required it is recommended for specifying options that are used frequently F or detailed information on PowerMill command line options see Chapter 1 The PowerMill Command in the PowerMill Reference Guide PowerMill searches for the epicrc file in three directories in the following order 1 Your current working directory 2 Your home directory 3 TheEPIC installation directory as defined by EPIC_HOME PowerMill User Guide 14 Chapter2 Getting Started CAUTION If there are multiple epicrc files in these directories and or command line options to control the settings the precedence in descending order is 1 Command line option settings 2 The epicrc file settings in your current working directory 3 The epicrc file settings in your home directory 4 The epicrc file settings in S5EPIC HOME If a file named epicrc already exists in your home directory for a different simulator a warning message is printed when PowerMill is run The following table lists PowerMill command line options and their corresponding keywords in the epicrc file Command Line Corresponding Keyword in the epicrc File Option A analog mode C c
133. m the blocks are sorted according to how much they exceed the budget Blocks displayed in red exceed the budget Blocks displayed in yellow are under budget Density select to view density information Power Supply select to view the power consumption for each power supply node PowerMill User Guide 182 Chapter7 Using the PowerMill Graphical Analyst Hierarchical View of Power Consumption You can view power consumption information for lower level blocks if they are specified in the Power Supply and Block Setup form To push down into a hierarchical block double click with the left mouse button on the desired block To pop back up a level double dick on a lower level block with the right mouse button Results Analysis To continue analyzing the circuit dick the Results Analysis button located on the left side of the PowerMill GA main window The Results Analysis form will appear see Figure 10 H Result Analysis DC Path Browser Power Diagnositics Browser turboWave Dismiss Figure 10 Result analysis form To open a particular results analysis tool in the Result Analysis form click the appropriate button Power Histogram The Power Histogram allows you to hierarchically view power consumption information for selected blocks To open the Power Analyzing a Circuit 183 Histogram click the Power Histogram button in the Result Analysis form see F igure 11 Power Histogram Browser File View Opt
134. mation requested for the command to work See Analyzing Power at Full Chip Level and Printing and Reporting Internal Node Currents in this chapter You can use the following commands to obtain element and current information get_elem_i get_elem_iavg get_elem_irms get_elem_ipeak These commands report the current value of the instantaneous average RMS and peak currents respectively In each case the simulator reports the values for all element branches being tracked You can track the current for an element branch using the commands discussed in Printing and Reporting Branch Currents You can use the following commands to get interactive information on blocks created with report_block_powr command get_block_info get_block_i get_block_icont The get_block_info command supplies a statistical description of the block essentially identical to the header in the report_block_powr report in the log file In addition if the block was generated using the level or at_level options it will show the block s hierarchical parent block as well the number and names of its children The get_block_i command reports the instantaneous average and RMS values of all quantities tracked by the block PowerMill User Guide 96 Chapter 4 Power Analysis The get block icont command generates hierarchical power information for blocks created using the report block powr level or at level options This consists of a so
135. mulation 1 Using vi load the integr spi netlist file Figure 8 provides the schematic of this circuit CINT 20p RIN 50K T OUT Figure 8 Schematic of Integrator circuit This circuit is a simple integrator using a 50K resistor and a 20 pF capacitor The input waveform is a 250K hz square wave between 2 V and 2 V 2 Run the simulation using the runint script 3 Using turboWave load the integr out file Getting the Input Files 149 4 Load the in and out signals see Figure 9 File Signal Edit Format View Search Option Window Group Compare Messages ojaleae O 108157 v in AN AE 2 126e 00V 2 131e 00 lt n Figure 9 Waveforms of signals in integr out file As expected the out signal is a triangle wave There is some initialization error at the beginning of the simulation where the waveform is not tracking as it should As you can see this clears out after short time Differentiator Simulation The following table lists the files needed for this simulation They are located in the ACE op amps directory Filename Description cfg Batch run configuration file diff spi SPICE netlist for the differentiator simulation PowerMill User Guide 150 Chapter6 ACE Tutorials Filename rundiff Description Run script for the differentiator simulation typ_tech_nchan typ_tech_pchan Technology files Procedure Use the follo
136. n g1 Ifin gnd vref vco out 23u g2 s1 gnd Ifin gnd 1e1 vco out gnd s1 gnd 15783e6 gt vref VCCS fin VCCS s1 VCVS vco out cot R1 Lint ae 8k LICE aed Es C1 Ya 47 Af AV e2 db8n gnd vco out gnd 0 125 db8n VCVS Figure 12 Schematic of PLL SPICE macro model This schematic includes the loop gain equation and a representation of each piece of the loop gain parameters Since the total loop gain is the product of each contributing segment you can separate terms and place them anywhere in the loop To make the circuit easy to modify the charge pump current is placed by itself as the gain for the phase detector model in the first VCCS element The feedback divide ratio is placed in the second VCVS element as 1 n In this case it is 1 8 or 0 125 The balance of the loop gain is put into the first VCVS that models the VCO Using vi look at pll2gm spi netlist file Notice that the r1 resistor has a value of 1k PowerMill User Guide 154 Chapter6 ACE Tutorials This is the incorrect value used for the first run in this tutorial The result is an underdamped system response to a step input 3 Run the simulation using the runpllm script 4 Using turboWave load the pll2gm out file 5 Display the vref and db8n signals The vref signal is the input voltage and the db8n signal is the feedback You will see that db8n shows underdamped or ringing behavior See Figure 13 f
137. n achieving convergence both at DC initialization and transient simulation since they limit the current through BJ Ts when the pn junction is forward biased However expanding those resistors and internal nodes significantly slows down the simulation m Next ACE performs circuit partitioning on the BJ Ts as with an accurate MOS transistor which includes its gate drain and source in the same stage channel connected subcircuit The base of a BJ T is included in the same stage with its collector and emitter This partitioning scheme is necessary since base emitter and base collector junctions are strongly coupled This effectively connects two channel connected regions that would usually be separated when a normal MOS device is used If a circuit contains only BJ Ts all channel connected and base terminal connected BJ Ts will forma large stage which makes the simulation very inefficient The BJ Ts are simulated in the accurate element mode which uses a different time step control and error control to assure simulation accuracy and stability Chapter 6 ACE Tutorials 136 Chapter6 ACE Tutorials Overview 137 Overview Thetutorials in this chapter are intended to exercise features and algorithms in the ACE simulation engine The following tutorials are included in this chapter m Tutorial 1 CV Curve Generation m Tutorial 2 Operational Amplifier Simulations e Voltage Follower Simulation e Step Input Simulation e Inte
138. n by specifying the nvec command line option However if you want to fully reproduce the GAP result for a specific generation you have to consider the state of the circuit therefore you need to use the save and restore mechanism described in tutorial 6 Load the maxpower out file in turboWave and view the mathematical signal gap total_ power This signal represents the instantaneous power in watts of the combinational circuit used in this tutorial Advanced PowerMill Simulations 49 File Signal View Waveform Analog Tools Window Help m total power 0 00 zr r M it Figure 15 Waveform of m gap total_power signal in maxpower out file PowerMill User Guide 50 Chapter 3 PowerMill Tutorials Tutorial 6 Estimating Maximum Power for Sequential Circuits This tutorial shows you how to estimate the maximum power of sequential circuits using PowerMill s GAP feature This tutorial illustrates the following GAP features m Detection of pseudo primary inputs PPIs using the mark node latch and set ckt cmd commands Here PPIs are defined as the output of the memory elements for example latches and flip fl ops m PPI detection using the PathMill latch detection feature m Thesaveand restore feature using the save history option of the set vec opt command It is recommended that you first read the section Using the GAP Feature to Estimate Maximum Power on page 103 in Chapter 3 before r
139. n file follower spi SPICE netlist for the voltage follower simulation runfoll Run script for the voltage follower simulation cmos35 mod BSIM3 v 3 SPICE model Procedure Use the following procedure to run the follower simulation 1 Using vi open the follower spi netlist file Go to the bottom of the netlist and you will see the instantiation of the bias circuit block and the voltage follower connection of the op amp PowerMill User Guide 144 Chapter6 ACE Tutorials See Figure 4 for the voltage follower schematic NBIAS X1 BIAS PBIAS X2 SIN IN OPAMP SIN_OUT Figure 4 Schematic of voltage follower circuit 2 Run the simulation using the runfoll script 3 Using turboWave load the follower out file 4 Load the sine in and sine out signals see Figure 5 Getting the Input Files 145 File Signal Edit Format View Search Option Window Group Compare Messages 5 059e D1V sin cut RUSSIA semen eng d Figure 5 Waveforms of signals in follower out file Step Input Simulation The following table lists the files needed for this simulation They are located in the ACE op amps directory Filename Description cfg Batch run configuration file step spi SPICE netlist for the step input simulation runstep Run script for the step input simulation typ tech nchan Technology files typ tech pchan PowerMill User Guide 146 Chapter6 ACE Tutorials Procedure Use
140. n the circuit at the microvolt or nanovolt resolution level you could easily fill up your disk Simulating BJTs The ACE option extends PowerMill s capability to simulate BiCMOS circuits with bipolar junction transistors BJ Ts The BJ T model is an implementation of the Gummel Poon model used in SPICE Both NPN and PNP transistors are supported as well as diodes and diode connected bipolar transistors Both vertical and lateral BJ Ts are supported ACE is best suited for circuits containing sparse BJ Ts as drivers or interface circuits Simulation of circuits containing large blocks of BJ Ts will be slow since those BJ Ts are simulated as a whole subcircuit The simulation speed of small to medium sized pure BJ T circuits isin the same order as SPICE If the circuit does not have large blocks of BJ Ts the overall speed is faster than SPICE PowerMill User Guide 134 Chapter5 Using the ACE Feature Procedure for Simulating BJTs This section describes the process by which ACE simulates BJ Ts This procedure includes several steps some in preprocessing and some during run time m First ACE reads the model from the netlist It calculates some variables used during simulation and calculates the temperature effect if the operating temperature is given m Next ACE expands internal nodes and internal resistors if base collector and emitter resistors are specified The base collector and emitter resistors are important i
141. nalysis 31 Files Needed for this Tutorial 0 0 32 Procedure seis cpx hve pe eda ese PUNA ee ne DADA 32 Differences Between the Resulting Block Power Reports sia Bees hw Gate es Cae ANN we dis ee NG 34 Tutorial 4 Finding DC Paths eee eae 37 Procedure rier pa ga a dee A a E 2k a ie Sei cee 38 Tutorial 5 Estimating Maximum Power for Combinational CIRCUS 442 aae search A ABA Gana BM AOR fang uit BRIN tance atid abe de ete ha 41 Files Needed for this Tutorial 00 42 Procedure MA AA 42 Tutorial 6 Estimating Maximum Power for Sequential Aa Aa 50 Identifying the Pseudo Primary Inputs 52 Testing Latch Functionality for Flip Flops with Non Buffered Outputs 00000 53 Files Needed for this Tutorial 0000 54 PrOCCdUle nh ieee ea ees Ga ele pyr S GE eee byes SE 55 Using PathMill to Detect PPIs 64 Tutorial 7 Customizing a GAP Objective F unction using an ADFMI Gode File enter aco Pa nd BP Pe he RoR ed 69 Procedure Seesar Bea adit BOM aw Gane 69 Tutorial 8 Finding Static Leakage Paths 79 Procedure auceu ia arid ban nal aa Ala aan a NG a Bang 81 4 Power Analysis OVERYIEN an AG orien Apa Awe tn Gale ed a a aay Da 85 Analyzing Power Consumption 00000 cece eee eee eens 85 Analyzing Power at Full ChipLevel 00000 86 Analyzing Power Block by BlOck 0 A0 eee eens 87
142. nd period Analyzing Results 217 H Power Histogram Browser E ial File View Options Help Present Instance Period 30 00ns A ADDER3 ADDER2 ADDER1 ADDERO ri Bita hi ee average current lt 81 0uA lt 162 1uA lt 243 1uA 2324JuA BSA _ Figure 10 Power histogram browser Select File Close Power Histogram Browser to exit the Power Histogram Browser PowerMill User Guide 218 Chapter8 PowerMill Graphical Analyst Tutorial Viewing the DC Paths Next you ll view the DC paths in the circuit Click the DC Path Browser button in the Results Analysis form The DC Path Browser appears see Figure 11 cath Browser No of dc paths 213 Simulation Time ns t1 ADDERO XORZA 1 8 2 ADDERO P1 gt AL 3 ADDER3 XORZB I Figure 11 DC Path Browser Thetop portion of the DC Path Browser graphs the number of DC paths that occur at particular time blocks To view the paths that occur at a time block click on a time block using your left mouse button Analyzing Results 219 Notice that a list of DC paths is displayed in the DC Paths text field located at the bottom left corner of the window A schematic of the selected path appears in the display area located at the bottom right corner of the window To close the DC Path Browser select File Close DC Path Browser Viewing the Power Diagnostics 1 Click the Power Diagnostics button in the Results Analysis form The
143. o not want to save your changes click the Cancel button to close the form without saving If you do not use the Power Diagnosis Setup form default values are automatically assumed These values are visible when you bring up the form Running a Simulation 179 NoTE The configuration commands needed to perform the checks are placedin a file called diag cfg in the Powermill GA run directory by default powermill pwga and are automatically applied to the run Running a Simulation To start the simulator dick the Start Simulation button located on the upper left side of the PowerMill GA main window See Chapter 2 for information on what you need to run a basic simulation As the simulation progresses log and warning messages appear in the Simulation Log and Error Warning fields of the main window see Figure 7 PowerMill Graphical Analyst Power Hill 5 0 real 1 0 user 0 0 sys Total number of errors reported in the err file pownnill_pwga pownnill err Please use the viewerror utility to view the detailed error messages Summary of Errors Simulation Se pa tup Start Simulation Resukt PRAYSIS Hierarchy Browser T CODE 8 D CODE 10 8 Figure 7 Example log information in main window To stop the simulation at any time click the Stop Simulation button the Start Simulation button becomes the Stop PowerMill User Guide 180 Chapter 7 Using the PowerMill Graphical Analyst Sim
144. o view the lower levels of the hierarchy Double click with the left mouse button on the ADDER3 block Notice the power consumption for the NoR3 instance is displayed Togo back up a level in the hierarchy double click with the right mouse button on the Nor3 instance Notice that the top level blocks are displayed Analyzing Results The PowerMill Graphical Analyst provides you with several tools for viewing the results of a simulation You can access these tools by clicking the Result Analysis button in the Powermill GA main window PowerMill User Guide 216 Chapter8 PowerMill Graphical Analyst Tutorial The Result Analysis form appears see Figure 9 H Result Analysis DC Path Browser Power Diagnositics Browser turboWave Dismiss Figure9 Result Analysis form Viewing Histogram Information First you ll view a hierarchical display of power consumption information for selected blocks To do this click the Power Histogram Browse button in the Result Analysis form The Power Histogram Browser will appear see Figure 10 This tool displays the per cycle current consumption for the blocks you previously selected in the Power Diagnostics Setup form In this case 30 ns was specified To view the average current consumption per block and period use your left mouse button to click any block in the display Use your middle mouse button to click on a block and view the peak current consumption per block a
145. o your current working directory The following procedure shows you how to do this 1 Set the correct path to which the EPIC HOME environment variable is set If you re not sure of the path you can ask your system administrator 2 Copy recursively the files from SEPIC HOME tutorials pwga to your local working directory The files in this directory are needed for this tutorial cp R SEPIC HOME tutorials pwga This command copies pwga directory into the current directory the period tells the cp command to copy to the current directory Starting the Graphical Analyst Start the Graphical Analyst by typing one of the following commands at the UNIX prompt in your pwga directory PowerMill User Guide 206 Chapter8 PowerMill Graphical Analyst Tutorial pwga powrmill ga The Powermill GA main window appears see F igure 1 Exit PowerMill Open Design Start and stop or access Data Setup simulation design data form toggle button Log information PowerMill Graphical Analyst BE File Options Help Work File powmill wrk Path home gdwyer 5 4Env tutorials jpwga Simulation Log Simulation Setup Start Simulation hey Result a STEVES cop Error Waming Hierarchy Browser Result Display Present Instance Sort By Average Current uA ADDERO 360 4DuA ADDER1 190 10ua ADDER2 116 54uA ADDERS r fcua EJ ja E The Total Current 723 58uA
146. oad the file CV curveoutt file and then the i1 rin current waveform and the v in voltage signal You should see the curves shown in Figure 2 File Signal View Waveform Analog Tools Window Help aja Lhe jem jo eso 212 ilf rin Figure 2 Waveforms of signals in CV curve out file 4 Calculate the capacitance at the minimum and maximum points using thei C dv dt relation Since you know the current I and dv dt you only need to calculate C Notice that the cursor position in Figure 2 shows 1 96 pF minimum poi nt PowerMill User Guide 142 Chapter6 ACE Tutorials Tutorial 2 Operational Amplifier Simulations This tutorial utilizes a transistor level op amp of very high gain in different configurations The following configurations are used Voltage follower m Step input m Integrator m Differentiator Figure 3 provides the op amp schematic used for this tutorial This op amp has an open loop gain of approximately 116 db PBias 5V MP2 p q q MP1 MP3 NBias O D In4 MP5 MP6 LO MN1 MN2 In gt unr HH ne MN7a MN8a MN3 MN6 5V _ MP3 Out Figure 3 Schematic of op amp circuit Getting the Input Files 143 Voltage Follower Simulation The following table lists the files needed for this simulation They are located in the ACE op amps directory Filename Description cfg Batch run configuratio
147. odes to display during simulation analog or digital values Power analysis to be performed Circuit modification Simulation accuracy control The configuration commands are fully documented in Chapter 2 Configuration and Interactive Commands and Chapter 3 ACE Configuration Commands in the PowerMill Reference Guide Technology Files The technology file describes the key features of the process technology that PowerMill uses to predict the transistor behavior in the circuit This technology file is created using a utility called Gentech It can be created automatically or manually For information on how to automatically create a technology file see the Automatic Technology File Generation section in Chapter 4 of the EPIC Tools Reference Guide For more information on manually running the Gentech utility see the Gentech section in Chapter 4 of the EPIC Tools Reference Guide Stimulus Files 13 Directly Supported Models If you are using BSIM1 BSIM2 BSIM3 v 3 MOS9 HSPICE level 50 MESFET or J FET models you don t need to specify a technology file The technology data lookup tables are created internally at run time Stimulus Files Stimulus information can be placed inside the netlist or included on the command line as a separate file Types of stimulus incl ude SPICE piecewise linear PWL or PULSE waveforms EPIC clk or tgl patterns and digital vector files Tolearn more about stimu
148. oggle Count total number of logic toggles for the node m Average Charging Current average current flowing into the capacitances connected to the node m Average Discharge Current average current flowing out of the capacitances connected to the node If a node toggle count is as expected the charge and discharge currents represent the mandatory current consumption to support the necessary circuit operation PowerMill User Guide 114 Chapter4 Power Analysis Ideally the product of the node capacitance toggle count and supply voltage will equal the sum of the charging and discharging current multiplied by the simulation period Thus if toggle count node capacitance Vdd charge discharge simulation time is greater than O some toggles cross the logic threshold but never reach the ful l swi ng value either VDD or 0 Conversely if the difference is less than O the node voltage waveform could show some glitches either above or below the logic threshold voltage for which no toggle is counted A large circuit with a large number of nodes could produce a huge volume of data in the sum file which would be too complicated to analyze You can use the set_hotspot_factor command to suppress those nodes for which the sum of the charging and discharging current is less than a specified factor multiplied by the sum for the node with the largest currents The report in Figure 8 can be used to illustrate the
149. ommand also sets the search level option level to 7 E set ckt cmd d ff mark node latch no q This line enables GAP s built in latch detection mechanism to generate and register the PPI vector file with the GAP feature The mark node latch command searches nodes that have the name q under all instances of subcircuit d ff Notice that the name of the output of subcircuit d ff is q A PPI vector file containing these nodes is automatically generated and registered with the GAP simulation E print probe i inst customize gap fitness This command instructs GAP to generate the waveform of the value of the customized objective function vs time and print it to the output file The name customize gap fitness is the default name for the math signal representing the value of the customized objective function You can also choose to print out the average and RMS values of this signal see the definition of the print probe i command in the PoweMill Reference Guide 3 Open the gap customizec file This is the ADF MI C filein which you define and register your customized fitness function See Creating a Customized F itness F unction on page 108 in Chapter 4 for instructions on creating this file PowerMill User Guide 72 Chapter 3 PowerMill Tutorials 4 Locate the lines that are part of the RegisterUserModel function at the bottom of the file see Figure 20 Specify block power for blockl and block2 block1 will
150. on 0 00 143 Step Input Simulation 00 0002 eee 145 Integrator Simulation 00 002 147 Differentiator Simulation 20000005 149 Tutorial 3 PLL SPICE MacroModeling 151 Files Needed for this Tutorial 152 Procedure ARA 152 Tutorial 4 Crystal Oscillator Simulation 156 Files Needed for this Tutorial 156 Procedure a maa AK ob ed NAA aa bib han ah bha NG 156 Using the PowerMill Graphical Analyst OVET VI SW ag Aman NANA NG ALNG Edges aa ee dyes Saeed ge RO 161 Running a Basic PowerMill Simulation 020000005 161 Starting the Graphical Analyst 0 000000 cece ee 162 Main Window 0 a EE E A EE 163 File Menun nre a PRN bE hae LANA NARRA 165 Options MENU Na Ga 4 eed lege eee deities wee paha 165 Help MENU nune She dee Deed bee KANONG cade Bee ANG 165 Simulation Setup Button 0 000002 ee 165 Start Simulation Button 0 0 00 000 eee 166 Result Analysis Button 0c eee eee 166 Hierarchy Browser Button 0 0000 166 Simulation Log Display 0 000000 cee eee eee 166 Error Warning Display 00 000 c eee eee 166 Result Display reri niun AA cies Be een aie eee et at AY eee 166 Sort BY MENU kanan hana Saad Pad ee See eine es Ba ate 167 Setting Upa RUN iiri ranea E eae ane Aelia Eee 167 Specifying a Work File 0 0 0
151. onfig_files default_config_files d delay_mode F no_ace fm user_adfm_obj_modules FM user_adfm_obj_modules_force L cell_lib_path m top cell n netlist files 0 output_pefix_name out print_format p technology t running_time u user_obj_modules Running a Basic Simulation 15 Command Line Option Corresponding Keyword in the epicrc File U user_obj_modules_force user_libraries NOTE The c command line option will not override the default_config_files keyword instead they are concatenated NOTE You can usetheuser_libraries keyword which does not have a corresponding command line option to specify the full path to the libF uncM ode library used with built in ADF MI models See Chapter 7 Built in Models in the 5 4 ADF MI Manual for more information on the libF uncM odel library Sample epicrc File This is a sample epicre file powrmill netlist_files dram net powrmill config_files cfg powrmill running_time 1000 powrmill output_root_name dram powrmill technology techfile powrmill user_adfm_obj_modules dram o powrmill analog_mode The semicolon begins a comment linein the epicrc file Running a Basic Simulation This section describes the procedure for running a basic PowerMill simulation in batch mode For information on running a simulation using the Graphical Analyst see Chapter 7 Using the PowerMill Graphical Analyst 1 Set up your environm
152. ons Options The Options menu located at the top of the Hierarchy Browser lets you change how information is displayed If you select the dashed line at the top of the Options menu the menu becomes a dialog box Show Internal Nets Normally when you click on an instance name in the tree display a list of nets connected to the instance s external pins appears at the bottom of the display If you select Options Show internal Nets from the menu the instance s internal nets will also appear in the list Show Instructions Select Show Instructions from the Options menu to display instructions for using the Hierarchy Browser This is a toggle option clicking it will either display or remove the instructions Theinstructions appear at the top of the window Ordering Instance Information You can sort the data displayed in the text fields at the bottom of the Hierarchy Browser three different ways Select one of the following buttons from the Options menu Analyzing a Circuit 197 m Pin Name lists information sorted by pin name m Pin Direction lists information by the pin direction m Net Name lists information sorted by net name Set Expansion Threshold You can set the maximum number of child cells that the browser will display when you are expanding an instance in the tree display into its child components see Figure 21 Figure 21 Set expansion threshold form Procedure 1 Select Options Set Expansion T
153. or the expected waveforms File Signal Edit Format View Search Option Window Group Compare Messages s mj ssa2 73877 v vref AE 1 990e 00V 1 010e 00 Figure 13 Waveforms of signals in pll2gm out file underdamped 6 Using vi to edit the pll2gm spi file comment out the r1 line with the 1k resistor 7 Uncomment the other r1 line containing the 8k resistor 8 9 Getting the Input Files 155 With this change the damping factor is now near critical damping Run the simulation again using the same runplIm script In turboWave select File Reload Figure 14 shows the new waveforms File Signal Edit Format View Search Option Window Group Compare Messages Figure 14 Waveforms of signals in pll2gm out file critically damped 10 This will reload the previously selected signals The db8n signal now shows a well behaved smoothly settling waveform and the ringing behavior is gone Continue entering different values for r1 and C1 and rerun the simulation You will see how quickly a macro model of a PLL can give indications of system response This provides a fast easy way to doa sanity check on PLL parameters such as loop filter PowerMill User Guide 156 Chapter6 ACE Tutorials values charge pump current and the effects of different feedback divider ratios Tutorial 4 Crystal Oscillator Simulation This tutorial demonstrates the effect of the set sim trap configuration
154. ore all commands that affect the accuracy of the timing or voltage also affect power In addition the following commands control different aspects of the simulation specific to power reporting set_sim_ires set_print_ires set_print_tres set_power_acc The set_sim_ires and set_print_ires commands control the current resolution of the current power reporting PowerMill ignores currents that are smaller than the values set by these commands The set print ires command affects only the current power output and reporting it does not affect the underlying simulation engine In contrast the set_sim_ires command does modify certain simulation parameters to ensure that the underlying simulation is done with sufficient accuracy to support the specified current resolution In general it is recommended that you use the set_sim_ires command instead of set_print_ires when you need to achieve a greater current resolution otherwise the reported current values might not be accurate The default current resolution is 1 uA The set_print_ires command typically does not impact performance but does affect the size of the out file The set_sim_ires command can have a significant effect on the speed of the simulation The set_print_tres command controls the time resolution of all simulation output printed to the out file as well as the time resolution used in calculating the reported average and RMS power numbers The time resolution is set by defaul
155. otal CPU 12 13 Advanced PowerMill Simulations 61 time and total number of generations are printed at the end of the file Open and examine the max_seq_power gav and maxpower ppi gav files These are the history files for the max_seq_power vec and maxpower ppi vec vector files respectively The two gav files contain the vectors for all generations that increased the maxi mum power You can use the vec history option of the set gap opt command to specify which vectors should be kept See the PowerMill Reference Guide for details on all of the GAP configuration and interactive commands NOTE You can use the gav files generated by GAP as vector files for a regular PowerMill simulation by specifying the nvec command line option However if you want to fully reproduce the GAP result for a specific generation you have to consider the state of the circuit therefore you need to use the save and restore mechanism previously described in this procedure Load the maxpower out file in turboWave and view the mathematical signal m gap total power which represents PowerMill User Guide 62 Chapter 3 PowerMill Tutorials the instantaneous power in watts of the sequential circuit used in this tutorial see Figure 18 File Signal View Waveform Analog Tools Window Help 2 xfefe Jo eae alo BAK AY m total power 0 00 QC a Ca Hi Figure 18 Waveform of m gap total power signal in maxp
156. ower 103 getting power information interactively 94 in hierarchical netlists 91 measuring true power in watts 90 power analysis block level 31 estimating maximum power 41 full chip 29 85 printing branch currents 98 RC UD mode 119 static leakage paths 79 power diagnosis dynamic 111 static 116 PowerMill environment graphic 9 powrmill command 10 23 print resolution of waveforms 130 probes creating 87 88 90 91 100 printing current 100 R RC full delay simulation mode 119 S scripts creating 16 shared memory 229 simulation mode 119 simulation modes 131 simulation time resolution 129 spd setting on nodes 129 static power analysis 116 stimulus files 13 T technology files automatic generation 12 time resolution control 129 time step control tres 129 selection parameter spd changing 129 tracking intervals setting 101 tres control 129 true power in watts measuring 90 turboWave screens 21 137 tutorials basic PowerMill simulation 22 block level power analysis 31 finding DC paths 37 Finding Static Leakage Paths 79 full chip power analysis 29 maximum power estimation combinational circuits 41 customizing objective functions with ADFMI 69 sequential circuits 50 U UD unit delay simulation mode 119 UNIX commands cat 27 cp 22 138 205 V vector files 13 automatic vector generation 41 103 See also GAP feature voltage resol ution controlling 132 limits 132 VTRAN program 24 W
157. ower out file 14 After a GAP estimation you can use the generated state files which have a Z extension in two ways You can resume a GAP estimation from the time the state file was saved e You can perform further analysis on those generations with saved state files without re running the whole simulation see Analyzing Generations with Saved State Files on page 63 Advanced PowerMill Simulations 63 Analyzing Generations with Saved State Files The following procedure shows you how to analyze the average power for different blocks within the two stage pipeline circuit for generation 3 with a state file named maxpower save 7200 000000ns Z 1 Verify that the following command has been added to the configuration file restore_ckt_state 7200ns 2 In the configuration file uncomment the last seven commands which are currently commented out These commands create three blocks within the circuit the 4 bit adder at the first stage the 4 bit adder at the second stage and the FFs and report the average power for individual blocks 3 Run the simulation using therun max seq power script When you see that the si mulation has progressed somewhere beyond generation 3 type Cont rol c to stop the simulator in the interactive mode 4 Type guide gap search max gen 1 at the interactive prompt 5 Resume the simulation by typing cont sim The simulation stops right after generation 3 is finished 6 Type qu
158. p a Run Before running a simulation you must specify the netlist and technology files PowerMill will use You ll also need to specify power supply information for the run block set up variables and the power diagnosis checks you want to perform 1 Tostart the set up process click the Simulation Setup button located at the middle left side of the PowerMill GA main window TheSimulation Setup form will appear Figure 2 is an example of the Simulation Setup form Simulation Setup Design Data Setup Supply Block Power Setup Power Diagnosis Setup Dismiss Figure 2 Simulation setup form 2 Click either Design Data Setup in the Simulation Setup form or select Design Data Setup from the File menu PowerMill User Guide 168 Chapter7 Using the PowerMill Graphical Analyst Specify work file Specify netlist files Specify technology files Simulation time in nanoseconds Design library path Specify command line options The Design Data Setup form as shown in Figure 3 will appear ware ang other coassa line options aco filepasas Por N pour cen configuration flea Hide Help Click to save values Click to clear values Click to exit form Figure 3 Design data setup form You can get to this form from either the File menu or the Simulation Setup form Specifying a Work File A work file is used to store information associated with a particular simulation run After a run is comple
159. parallel merging R 104 transition times reporting R 181 tres control U 129 true power in watts measuring U 90 turboWave R 418 turboWave screens U 21 U 137 tutorials basic PowerMill simulation U 22 block level power analysis U 31 finding DC paths U 37 Finding Static Leakage Paths U 79 full chip power analysis U 29 maximum power estimation combinational circuits U 41 customizing objective functions with ADFMI U 69 sequential circuits U 50 U UD unit delay simulation mode R 265 R 266 R 300 R 315 U 119 units argument units R 20 changing units R 23 UNIX commands cat U 27 cp U 22 U 138 U 205 U state printing R 215 reporting R 185 R 338 utilities edisplay R 417 Eview R 418 V VCVS R 270 vector applying R 318 vector checking options R 338 setting comparison windows R 340 setting vector drive resistance R 318 setting vector high low voltages R 260 R 318 setting vector slope rise fall times R 318 skipping vector comparison for given nodes R 337 vector files U 13 automatic vector generation U 41 U 103 Seealso GAP feature Verilog netlist format R 8 ViewTrace R 418 voltage forcing R 53 voltage resolution controlling U 132 limits U 132 voltage source R 270 voltage waveforms printing R 131 VSRC R 270 VTRAN program U 24 W warning messages limiting by index R 92 limiting by phase R 93 printing control R 237 w command line option R 237 wasted power R 140 U 88 See also
160. ple assign statements to build up the desired sum Oncethe probe is constructed the commands print probe i and report probe i can be used to obtain out file waveforms and Jog file current summaries for the probe identical to those created for the node currents In addition the report_node_powr command requests current information for Analyzing Power Consumption 101 all probe nodes if used without specifying any nodes These commands can also be used with the report block powr command to obtain waveform information from those commands Current Histograms and Tracking Windows PowerMill can generate a current histogram for each node branch and probe The current histogram report consists of a report of the average RMS and peak currents over a set of user defined intervals printed to the hist file A sample current histogram report for nodes VDD and GND is shown in Figure 6 You can print a histogram using the report node i report elem exi and report probe i configuration commands Alternatively you can use the report ckt phist command which automatically generates current histograms for each constant voltage source node as well as all user defined probe nodes This automatically generates histograms for all power nodes including probes created by report block powr PowerMill User Guide 102 Chapter4 Power Analysis Node XGND Start ns 0000e 01 0000e 01 3000e102 7000e102 1000e102 5000e102 9000e10
161. porting R 145 R 146 branch Seedenent breakpoints interactive R 36 deleting R 50 listing R 95 setting element breakpoints R 225 setting node breakpoints R 248 setting time breakpoints R 314 BSIM1 models U 13 BSIM2 models U 13 BSIM3 v3 models U 13 bus notation R 210 C Cadence SPF netlist format R 8 capacitance adding R 41 adding wirecap R 42 modeling R 375 nodes with high cap value R 384 setting R 250 case sensitivity controlling R 335 charge conservation model R 239 charge pump R 357 R 396 chip level power analysis U 85 circuit connectivity modifying R 105 circuit errors handling R 82 command alias R 100 environment variables R 215 interpreter R 217 reading files R 136 translation from 3 x R 317 command arguments argument tag R 23 argument unit R 20 changing units R 23 specifying arguments R 20 command line options R 3 R 11 A U 132 comment character defining R 215 comment line in epicrc file U 15 configuration commands assign_branch_i U 100 U 122 assign_node i U 100 U 122 limit_dcpath_search U 115 print_branch_i U 122 print node i U 86 U 122 print node logic U 23 U 30 print node v U 23 U 30 print probe i U 30 U 100 U 122 report block leakage U 89 report block powr U 30 U 88 U 122 report ckt dcpath U 38 U 39 U 115 report ckt leak U 117 U 118 report ckt phist U 101 report elem exi U 112 U 122 report elem i U 101 report node hotspot U 112 report node i U 86 U 101 U 122 report node m
162. power run script When the estimate is done list the contents of the current directory The GAP estimation produces several output files with a maxpower prefix PowerMill User Guide 60 Chapter 3 PowerMill Tutorials 11 Open and examine the maxpower gap file which contains a summary of the GAP simulation see Figure 17 Estimates of maximum instantaneous power from the GAP feature only those generations increasing maximum power are listed Generation 0 Maximum power 0 080511 watts Vec 1 010000101101110011 Vec 2 10001101011000zzzz Vec 3 11101011110111zzzz Generation 3 Maximum power 0 082563 watts Vec 1 101000001100110000 Vec 2 00100010010010zzzz Vec 3 10011001101001zzzz Generation 92 Maximum power 0 120024 watts Vec 1 000110100110111011 Vec 2 00000000010000zzzz Vec 3 11111111101111zzzz Generation 93 Maximum power 0 121689 watts Vec 1 000110100010110001 Vec 2 00000000000000zzzz Vec 3 2 111111 1111111z27z2 Total number of generations 256 Total CPU time 1244 61 secs Figure 17 Contents partial of the maxpower gap file Each generation of the GAP estimation simulates the circuit with 20 input vector triplets by default The maxpower gap file contains an entry for each generation that improved the maxi mum power Each entry consists of the following fields generation ID maximum power produced and the input vector triplet producing the maximum power The t
163. q_power vec and custom ppi vec respectively The custom ppi vec file is the PPI vector file generated by the mark node latch command Since the vec_history option of the set gap opt command is specified as 2 stimuli of all the generations that improved the maximum value are tracked in the two gav file PowerMill User Guide 78 Chapter 3 PowerMill Tutorials Estimates of maximum average power from the GAP feature only those generations increasing maximum power are listed Generation 0 Maximum power 0 000714735 Vec 1 010000101101110011 Vec 2 10001101011000zzzz Vec 3 11101011110111zzzz Generation 1 Maximum power 0 000759248 Vec 1 101101111000110111 Vec 2 01000101100110zzzz Vec 3 10010010111111zzzz Generation 2 Maximum power 0 000882713 Vec 1 101101111000110111 Vec 2 01000101000110zzzz Vec 3 10010010111111zzzz Generation 3 Maximum power 0 000904537 Vec 1 101101111111000110 Vec 2 01000101010011zzzz Vec 3 10010010111101zzzz watts watts watts watts Ar gD Figure 25 Contents partial of the custom gap file Advanced PowerMill Simulations 79 Tutorial 8 Finding Static Leakage Paths This tutorial illustrates how you can use PowerM ill to find static DC short circuit paths A static DC short circuit path existsif a node has a static conducting path to VDD and a static conducting path to GND The report_ckt_leak command finds static DC path
164. r average capacitive percent wasted power report block powr top track gnd 1 track wasted 1 Print instantaneous average and rms waveforms to out file print_probe_i inst top print probe i avg top print probe i rms top The commands as set in this configuration file perform the following functions e print node logic prints all nodes in digital format e print node v prints all nodes as voltage waveforms e report block powr provides the averages for supply ground input output and biput as well as instantaneous waveforms in the out file It also provides a report on the percent of wasted power short circuit current print probe i prints the instantaneous average and RMS current waveforms 2 Run the simulation using the run full script Advanced PowerMill Simulations 31 3 Examine the full log file Notice the reports at the end of the file 4 Load the full out file in turboWave and display the average power waveforms in each block which are preceded by an upper case see Figure 6 File Signal View Waveform Analog Tools Window Help 2s asf L_ 7478 jo L_ 7478 I total src aang AA pug pe a an PANA a ANA j PANAY PAYOLA Va pte I total gnd I total cap EEEE kai PAN A ang a AA ee PAA _ a Figure 6 Waveform of advanced adder circuit selected signals Tutorial 3 Performing a Block Level Power Analysis As part of the design proc
165. report You can specify the histogram intervals using the set_print_iwindow command EXAMPLE 17 set_print_iwindow period 100ns start 25n end 238ns on_time 30ns This example specifies the following current windows 1 from 25 ns to 55 ns 2 from 125 ns to 155 ns 3 from 225 ns to 238 ns When a set of current tracking intervals is created by the set_print_iwindow command the simulation only tracks current during the specified intervals Therefore waveforms Using the GAP Feature to Estimate Maximum Power 103 printed to the out file are limited in time to the specified intervals Also the average RMS and peak currents and waveforms are only computed based on the periods when tracking is enabled This can be useful when you want to ignore part of the simulation run when calculating the current statistics Using the GAP Feature to Estimate Maximum Power PowerMill s GAP Genetic Algorithm for maximum Power estimation feature searches input vector pairs or triplets to maximize the power dissipation of a given circuit The GAP feature combines a genetic algorithm with advanced circuit simulation technol ogy to efficiently generate a tight lower bound on the maximum power estimation of a given circuit The power computed is the summation of the power dissipated and the power stored in the circuit A genetic algorithm is a general purpose optimization algorithm Through a mechanism analogous to natural selection it can search t
166. rrent 30 454213 uA Figure 9 Excerpt from block power reports in block2 log file block3 log Figure 10 shows a portion of the block power reports printed in the block3 log file This excerpt shows the block power report for the x1 block and was generated by the following command report_block_powr x1 track_wasted 1 track_power 1 track gnd 1 x1 Advanced PowerMill Simulations 37 This report is the same as that in the block2 log file with the addition of reports on capacitive contributions wasted current and power in watts Block x1 Number of nodes in block ee Number of elements in block 41 Number of block supply nodes i 1 Number of block ground nodes J Number of block biput nodes nG Number of block input nodes got 2 Number of block output nodes 0 Number of block stages 1 Number of block partial stages 1 Average supply current 59 873924 uA RMS supply current y 313 624995 uA Average ground current 61 049494 uA RMS ground current 311 347667 uA Average input current 0 000000 uA RMS input current 0 000000 uA Average output current 0 000000 uA RMS output current 0 000000 uA Average biput current 1 172278 uA RMS biput current 30 454213 uA Average capacitive current 41 307089 uA RMS capacitive current 263 016049 uA Average wasted current 21 971519 uA RMS wasted current 79 569210 uA Wasted current percentage g 34 721875 Average block power gt 302 205535 uw RMS block power 1565 24
167. rrent and block power to calculate the fitness measure The following table lists the files needed for this tutorial These files are located in the pw_advanced max_powr3 subdirectory in your working directory Filename Description cfg_max_power Configuration file for maximum power estimation max_seq_power spi SPICE netlist of the sequential circuit a segment of a datapath with two pipelined stages to be estimated max_seq_power vec Vector file to be used for maximum power estimation cmos35t mod A BSIM3 v3 SPICE model used to run the simulation in direct mode gap_customizec An ADFMI C file used to customize the objective function for the GAP simulation run_custom Run script for GAP customization Procedure Use the following procedure to customize the objective function for a GAP simulation PowerMill User Guide 70 Chapter 3 PowerMill Tutorials 1 Open and study the max seq power spi file Notice that the clock is defined at the bottom of the file as a pulse signal with a delay of 100ns and a period of 40ns The circuit contains four FFs positive edge triggered which are instances defined by the subcircuit d f f The output of the subcircuit d ff is buffered Open and study the cfg_max_powr configuration file The following file sample shows the contents of this file use_vec_gap vec max_seq_power vec set_gap_opt delay 100ns period 40ns vec_history 2 guide_gap_search fit 3 level 7 set_ckt_
168. rted list of the block s hierarchical children and their contributions to the specified currents EXAMPLE get block icont current src type inst xsr34x22 top This command returns the contribution of each child block of the parent block 34x22 to the block s total supply current See Figure 5 for a sample of the output of this command Block xsr34x22 top Total instantaneous source current 16054 265763 uA Contributions from children Figure 5 xsr34x22 x1158 top 7026 176334 uA xsr34x22 67 to 3376 436160 uA xsr34x22 66 to 2848 805135 uA xsr34x22 61 to 2100 318100 uA xsr34x22 69 to 691 675033 uA xsr34x22 64 to 7 744000 uA xsr34x22 60 to 5 689000 uA xsr34x22 63 to 4 136000 uA xsr34x22 62 to 2 858000 uA xsr34x22 70 to 1 320000 uA xsr34x22 65 0 000000 xsr34x22 68 0 000000 xsr34x22 5 95 0 000000 xsr34x22 57 0 000000 KOKO KKM KM MM MX oo o o ro ro ro iro ro ro ro Bro iro Sample output from get block icont command You can use the following interactive commands to get current information on individual probe nodes generated by the report block powr command or the assign node i and assign branch i commands get probe i get probe iavg get probe irms get probe ipeak Analyzing Power Consumption 97 Controlling Power Reporting Resolution and Accuracy The accuracy of the reported current and power values is dependent on the accuracy of the underlying simulation engine Theref
169. rview Overview 9 This chapter provides the basic information you need to start using the PowerMill simulator It lists the required and optional input files and provides a basic procedure for running a PowerMill simulation You can learn to run both basic and advanced PowerMill simulations by performing the tutorials provided in Chapter 3 PowerMill Tutorials The PowerMill Environment Figure 1 graphically represents the PowerMill environment Vector f Stimulus Files m Model Libraries Technology Files Configuration Files PowerMill Simulator PowerMill Output Files Display Figure 1 The PowerMill Environment In this figure solid arrows indicate the necessary input files for PowerMill Arrows with dashed lines indicate optional files Netlist files technology files and stimulus functions are fully described in the EPIC Tools Reference Guide PowerMill User Guide 10 Chapter2 Getting Started The PowerMill Command PowerMill is executed by typing the powrmill command followed by a series of command line options The n command line option is the only required option The p to specify the technology file and c to specify a configuration file options are optional but frequently used EXAMPLE powrmill n netlist spi c cfg o test p typ_tech If no configuration file is specified and a SPICE or HSPICE netlist is used the use_sim_case configuration command
170. s BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 182 2 TO 182 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 182 2 TO 182 4 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 221 6 TO 221 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 221 6 TO 221 8 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 222 2 TO 222 3 ns BLOCK top DRAWS EXCESSIVE POWER FROM 222 2 TO 222 3 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 261 6 TO 261 7 ns BLOCK top DRAWS EXCESSIVE POWER FROM 261 6 TO 261 8 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 262 2 TO 262 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 262 2 TO 262 4 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 301 6 TO 301 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 301 6 TO 301 8 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 302 2 TO 302 3 ns BLOCK top DRAWS EXCESSIVE POWER FROM 302 2 TO 302 3 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 341 6 TO 341 8 ns BLOCK top DRAWS EXCESSIVE POWER FROM 341 6 TO 341 8 ns Sample power File 227 BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 342 2 TO 342 4 ns BLOCK top DRAWS EXCESSIVE POWER FROM 342 2 TO 342 4 ns BLOCK top DRAWS EXCESSIVE SUPPLY CURRENT FROM 381 6 TO 381 7 ns BLOCK top DRAWS EXCESSIVE POWER FROM 381 6 TO 381 7 ns KIKKIKKIKKIKKIKKKKKKKKAKKAKKAKKIKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKKAKK POWER BUDGET VIOLATION SUMMARY KIKKIKKIKKAKKKKKAKKAKKAKKAKKAKKAKKKKKAKKKKKAKKAKKAKKKKKAKKAKKAKKKKKAKKAKKAKKAKKAKK BLO
171. s and detects several unusual topological conditions in regular CMOS designs Various topologies are listed in the PowerMill Reference Guide under the description of the report ckt leak command This tutorial highlights the effect of each of these topologies The following table lists the files needed for this tutorial These files are located in the pw_advanced static_leak subdirectory in your working directory Filename Description cfg_static Configuration files for static leak analysis static_powr spi SPICE netlist of the circuit for block power analysis See Figure 26 run_static Run scripts for static leak tutorial tech typ 25c 5v Technology file PowerMill User Guide 80 Chapter3 PowerMill Tutorials Pinag pa artial Swing Checks xpsl nps vopy gt 5 0v1 mn22 kk nc gnd 2 0V mn21 nc vdd BUS VDDH C mp23 mp25 mp26 km kn ko mn23 mn25 mn26 bus static leak stuck at 1 stuck at O forward bias p Figure 26 Schematic of the static powr spi netlist clk GNDL forward_bias_n xps2 QUTF ff Advanced PowerMill Simulations 81 Procedure Use the following procedure to run the static leakage path check tutorial 1 Open and examine the cfg_static configuration file see Figure 27 set sim case 1l print node v report ckt leak el to vdd to gnd report ckt leak el static leak ireport ckt leak el stuck at 1 stuck
172. s effective power and current simulation and diagnosis capabilities not only enable you to successfully engi neer the design of an integrated circuit but also significantly improve its reliability Major Functions and Features The PowerMill simulator can perform the following functions m Run transistor level simulations with SPICE like accuracy with a run time 10 to 1000 times faster than SPICE Display instantaneous current waveforms Display first derivative di dt waveforms Report peak average and RMS currents Report DC leakage paths Perform static power diagnosis Provide block power statistics that identify hot spots blocks with excessive power dissipation Run in batch mode with different parameters Automatic vector generation for maximum power estimation PowerMill also provides the following features m An Analog Circuit Engine ACE feature that allows you to perform accurate SPICE like circuit simulation on much PowerMill User Guide 4 Chapter 1 Introduction to PowerMill larger designs than those traditionally handled by SPICE This feature supports bipolar transistors An algorithm to efficiently handle node to node coupling capacitance and crosstalk Two graphical analysts one for the base simulator and the other for ACE for setting up simulation runs and analyzing results Interactive debuggi ng tool Technology migration requiring limited technol ogy related data Automatic technol og
173. s you can use to create a simulation that is balanced in terms of accuracy and performance It includes a default set of rules as well as several sets of rules that can be applied as needed to improve either the accuracy or speed of a simulation PowerMill User Guide 126 Chapter5 Using the ACE Feature The default autodetection rules controlled by the search ckt msx command provide acceptable accuracy and speed for most mixed signal circuits such as PLLs ADCs DACs switched capacitors etc However some circuits might require a more accurate simulation in which case you could apply the search ckt analog command This command applies a more extensive set of rules and is more accurate However a simulation using search ckt analog command will run somewhat slower as compared to a simulation using the default search ck msx rules The actual effect on speed will depend on the type of circuit the amount searched and how much the search ckt analog rule changes settings from the search ckt msx rule You can use the following configuration commands to apply different sets of autodetection rules as needed m search ckt msx default Use this set of rules for mixed signal circuits This is the default rule setting except when running in RC or UD simulation modes It includes most of rules used by search ckt analog but is less conservative and runs faster m search ckt analog Use this set of rules for analog circuits This command
174. se the keyword epic or spice The time s are user determi ned and in this case optional EXAMPLE 2 report node ic all for spice lu In this example a11 is a keyword for is a tag spiceisa keyword and 1u is a value Menu Text Filenames and Examples Menu text appears in bold as shown in the following example EXAMPLE 1 To start setting up a run select File Design Data Setup XV Filenames are shown in the same font as the surrounding text but in italics EXAMPLE 2 This is an example of the file fil name out being shown in text Examples are shown in courier font as they might appear on your screen Sometimes explanations follow examples and in such cases anything shown in the example that appears in the explanation is shown in the same courier font used in the example EXAMPLE 3 add node cap RS100 275 In the example the capacitance value of node Rs100 is increased by 275 femtofarads PowerMill User Guide XVi About This Manual Chapter 1 Introduction to PowerMill 2 Chapter 1 Introduction to PowerMill Overview Overview 3 PowerMill is a transistor level power simulator and analyzer for CMOS and BiCMOS circuit designs As more components are integrated into smaller silicon chips power consumption becomes a major concern Detailed current information about each circuit component is critically important to the designer Designs must be optimized for minimum power consumption PowerMill
175. set to OV The Power Ground column allows you to specify whether the supply net is a power net or a ground net By default supply nets greater than 0 V are assumed to be power nets Nets that are less than or equal to O V are assumed to be ground nodes 1 Tospecify whether a net is a ground or power node click the right mouse button in the power ground field A popup dialog box appears Select either power or ground Click the Add Supply button to add supply nets The Clear button clears all the voltage values and any new power supply nets you added The supply nets derived from the netlist remain in the form but are nolonger assigned voltage values Block Setup You can also use the Power Supply amp Block Setup to specify the blocks you want to monitor and set up power budgeting checks The text fields in the bottom section of the form list the top level blocks in the circuit and related information If there are more than 100 blocks at the top level no blocks will be displayed In this case you must manually select the blocks you want to include in the power calculation Transistors are not displayed in the form If the design is flat that is no hierarchy then no blocks are selected A popup warning will inform you that there are no top level blocks Selecting Blocks 1 Toselect blocks click the toggle button located to the left of Block Setup 175 the Block Name text fields A block is active when the button
176. sions in directories Select a directory name Select a file name Selected file name Activates Filter text field Figure 4 File finder form Using the File Finder Form TheFile Finder form gives you easy access to the fil es you need to run your simulation TheFilter text field located at the top of the form lets you designate files with specific extensions 1 Type wrk at the end of the path 2 Click the Filter button located at the bottom of the form to see all files in the directory that have a wrk extension Setting Upa Run 171 The Directories column is used to select a directory containing the file you want to use You can change the directory being viewed by double clicking on a directory name A list of files in the directory you selected appears in the Files column The Selection field at the bottom of the File Finder form shows you the full path and name of the file you sel ected Click the OK button to save your selection and close the File Finder form Importing Existing Run Scripts The Graphical Analyst accepts existing PowerMill run scripts 1 Click thelmport RunScript button 3 The File Finder dialog box will appear Typein the name of an existing run script in the Selection dialog box The options specified in the run script are automatically entered into the appropriate fields and a work file is created Click OK button to save your settings and close the form Sp
177. slope and output slope There will always be some discrepancy between the estimated short circuit current calculated in the RC and UD modes and the actual short circuit current calculated in PWL mode If the short circuit current is small this discrepancy is negligible However if a circuit contains a large short circuit current if the input slope is much slower than the output slope the discrepancy between RC and UD mode results and PWL mode results could increase significantly In this case a power analysis using RC or UD mode would be inaccurate Another source of discrepancy of average power between PWL and RC modes is derived from the application of different timing models which could cause new glitches or existing glitches to change width and height or even disappear Running a Simulation in RC or UD Mode You can instruct the simulator to run in RC mode in two places You can either usethe d rc command line option when starting the simulator or you can use the use set_sim_mode rc command in the configuration file Likewise you can use the a ud command line option or the set_sim_mode ud command to run in the UD power analysis mode Power analysis in RC and UD modeis based on switching capacitive power in each stage which generally corresponds toa gate Therefore only the average power of a stage is meaningful and as aresult the instantaneous power is displayed based on the average power You can combine RC and UD stages wi
178. splay consists only of top level design components You can expand portions of the instance tree by pressi ng the shift key and clicking your left mouse button on instances You can collapse the hierarchy by holdi ng down the shift key and clicking a previously expanded instance When you click on the instance name it becomes red Pin information for the selected instance is displayed in the text fields at the bottom of the Hierarchy Browser The instance name is also displayed in the Selected Instance text field You can choose to view the tree display by instance name or type or both by clicking the Instance Name Instance Type or Name and Type buttons located at the top left corner of the Hierarchy Browser You can view the attributes of a net in the tree display by clicking the Selected Net button located at the bottom right corner of the window then selecting a net name from the list below PowerMill User Guide 196 Chapter 7 Using the PowerMill Graphical Analyst Show Info The data displayed in the instance information fields depends on the button you click in the Show Info About box If you click the Selected Instance button a list of pins on the selected instance is displayed including direction information and the name of the net the pins connect to If you click the Selected Net button the displayed information includes instances connected to the selected net the instance pin connecting to the net and the pin directi
179. sumed current is comprised of two types of current capacitive current and wasted current m Capacitive Current any current for which its conductive path terminates or originates at a circuit capacitance This current is essential in carrying out the switching functions of the circuit m Wasted Current any current for which both ends of the conducting path are voltage sources This current does not contribute to the changing of circuit voltages and therefore is considered wasted Usually wasted power consists of the DC current flowi ng from power to ground This wasted power can come from crowbar or short circuit current caused by both P channel and N channel devices being on the during a transition It can originate from floating inputs or from DC paths that are unintended It can also come from floating inputs or from DC path that are unintended such as device leakage currents It can also come from analog bias circuits and current mirrors in operational amplifiers that cannot be avoided but will be reported as wasted power Using the report_block_powr Command You can measure wasted power using the track wasted option of the report_block_powr command EXAMPLE report block powr my block track wasted 1 x1 x1 This command generates a power analysis report for the subcircuit x1 x1 that includes both the standard block power report see Analyzing Power Block by Block and a wasted power report PowerMill Us
180. t to be ten times the value of the simulation time resolution see set_sim_tres This setting should be adequate for most PowerMill User Guide 98 Chapter4 Power Analysis situations however if you want to get the maximum accuracy in the current calculation you should set the print time resolution to be the same as the simulation time resolution This setting will create a larger output file and possibly reduce the simulation performance since the output handles a larger number of points The set power acc command allows you to set the level of detail used in the accounting of circuit capacitances when doing element and node current calculations Typically the simplified models provide a high level of accuracy and a significant improvement in simulation performance when used to calculate the average and RMS current values However you might want to use the more accurate models if you need to get the detailed shape of the instantaneous waveforms Specifically you should apply the most accurate settings when comparing instantaneous waveforms of small circuits with another simulator such as a SPICE simulation Results for large circuits typically are not very sensitive to the capacitance model The default settings usually provide a reasonable balance of accuracy and performance For more specific information on each command see Chapter 2 Configuration and Interactive Commands in the PowerMill Reference Guide Printing an
181. taneous average and RMS values of the block supply current ground current biput current wasted current and power as well as to the block s leakage percent Ordinarily PowerMill only checks for budget violations at the conclusion of the dynamic simulation However if you specify the run_time_check 1 option PowerMill will monitor the instantaneous current and power values during the dynamic simulation In this case PowerMill writes a message to the err file each time the budget is violated and a prints a summary of each violation in the power file You can use the handle ckt error command with the run time check option to drop the simulation into the interactive mode whenever a budget violation occurs Finally you can specify the check dcpath 1 option to trigger a DC path check each time an instantaneous current power budget violation occurs Retrieving Power Information Interactively You can interactively retrieve most power information during the dynamic simulation that is reported to the output files if you have previously instructed PowerMill to track that information You can use the following commands to obtain node current information get_node i get node iavg get node irms get node ipeak Analyzing Power Consumption 95 These commands report the current value of the instantaneous average RMS and peak currents respectively In each case you must have requested the simulator to track the relevant infor
182. ted the data can be read directly from the work file without having to enter information again Work file names always end with a wrk extension After each simulation a results directory with the same name as the work file with a _pwga extension is created All simulation output files as well as files generated by the Graphical Analyst are placed in the results directory Setting Upa Run 169 By default the PowerMill GA assumes a work file called powrmill wrk The results of the simulation are placed in the powrmill pwga directory Tostorethe results of multiple runs you can change the wrk file name This will create a directory with a corresponding name The directory contains the results of a particular simulation All paths specified in the Design Data Setup form are assumed to be relative to the directory containing the work file You can create a work file or select an existing work file in the Design Data Setup form using one of the following methods m Typea new work file name in the Work File text field m Usean existing work file nameif it already appears in the Work File text field m Click the Browser button located to the right of the Work File text field PowerMill User Guide 170 Chapter7 Using the PowerMill Graphical Analyst This pops up the File Finder form You can use this form to select an existing work file Figure 4is a snapshot of the File Finder form Specify files with particular exten
183. th PWL stages to achieve a balance between speed and accuracy PowerMill s RC and UD modes apply a few basic circuit detection rules to the circuits and mark portions of the circuit to use the PWL mode PowerMill User Guide 122 Chapter4 Power Analysis CAUTION You can apply the following power diagnosis commands to RC and UD stages report block powr Use this command to analyze power use for specified stages If the specified elements cover only a partial stage this command forces the whole stage into PWL mode EXAMPLE 1 report block powr blk2 xadder blkl This command reports the average power dissipation for a circuit block in this case an adder circuit report_probe i and print_probe i Use these commands to report or print current information for probes created by the report_block_powr command EXAMPLE 2 print probe i avg blkl_vdd print probe i avg total src bik2 This example prints the average VDD current waveform of the adder block specified in Example 1 report node i and print node i Use these commands to get the total power dissipation of RC and UD stages by applying them to power nodes VDD GND connected to these stages Applying them to non power nodes forces the stages into PWL mode EXAMPLE 3 report node i avg VDD report block powr bikli track wasted 1 report block powr bik2 These commands report the power dissipation for the whole circuit assuming VDD is the only power source
184. the PowerMill Graphical Analyst GA by typing one of the following commands at the UNIX prompt Main Window Starting the Graphical Analyst 163 pwga powrmill ga If you have previously simulated a circuit using the GA the next time you start pwga it will by default load the last run work file and display the results of the most recent simulation EXAMPLE pwga run_script wrk PowerMill uses the work file to determine the location of the PowerMill results After you invoke the PowerMill Graphical Analyst the Power Mill GA main window appears This window is used to set up start and stop a simulation and access analysis tools It also displays log warning and power consumption information see Figure 1 PowerMill User Guide 164 Chapter 7 Using the PowerMill Graphical Analyst Exit PowerMill Open Design Start and stop or access Data Setup simulation design data form toggle button Log information u z PowerMill Graphical Analyst J File Options Help Work File powmill wrk Path home gdwyer 5 4Env tutoriaals jpwga Simulation Log Simulation Setup Start Simulation Result Analysis Error aming Hierarchy Browser Result Display Present Instance Sort By Average Current uA ADDERO ADDER1 a I I The Total Current 723 58uA Access display Access to Error amp Warning messages of netlist hierarchy analysis
185. the following procedure to run the step input simulation 1 Using vi open the step spi netlist file You will see that the connection is the same as the voltage follower The difference is in the input waveform In this case the step response will be observed The important parameters are the slew rate going up and down the settling time any ringing effects and the accuracy of the final value or gain error The schematic is shown in Figure 6 5 Figure 6 Schematic of step input circuit STEP_OUT Run the simulation using the runstep script Using turboWave load the step out file Load the in and step out signals see Figure 7 Getting the Input Files 147 There are three steps to the waveform 1 5 to 1 5 to zero to 1 5 V File Signal Edit Format View Search Option Window Group Compare Messages ajae 2aco1o v in S00e 00V 1 500e 00 Za Figure 7 Waveforms of signals in the step input simulation Integrator Simulation The following table lists the files needed for this simulation They are located in the ACE op_amps directory Filename Description cfg Batch run configuration file integr spi SPICE netlist for the integrator simulation runint Run script for the integrator simulation typ_tech_nchan Technology files typ_tech_pchan PowerMill User Guide 148 Chapter6 ACE Tutorials Procedure Use the following procedure to run the integrator si
186. the state at the beginning of all generations The save history option is disabled by default 3 Usethe guide gap search command to specify additional parameters for the GAP estimation You can use this command to set the following parameters Use the level option to select the search level to be applied to the GAP estimation The search level is an integer between 1 and 10 that defines a set of parameters to be applied to the genetic algorithm A higher search level generally produces a better result but requires more CPU time The default valueis 5 Use the fit option to specify the objective to be maximized that is the fitness function Currently the GAP feature supports two objective functions instantaneous power fit 2 and average power per clock cycle fit 1 default Use the max_vec option to limit the number of applied input vector pairs or triplets during the estimation The estimation stops when it reaches this limit The default value is positive infinity Use the max_value option to limit the value of the fitness function The estimation stops if the value of the fitness function exceeds this threshold This value uses MKS units and has a default value of positive infinity Use the max gen option to limit the number of generations applied The default value for this option is positive infinity Use the time option to limit the CPU time used by the simulation The simulation stops when it reaches this
187. time of node exceeds limit 0 ADDER2 XORZA N 4 Estimated Rise Fall time of node exceeds limit 0 ADDER2 XOR2B N 4 Estimated Rise Fall time of node exceeds limit 0 ADDER3 XORZA N 4 Estimated Rise Fall time of node exceeds limit 0 ADDER3 XORZB N_4 Estimated Rise Fall time of node exceeds limit 227 ADDER1 XORZB N_4 Node has multiple toggles 22 64 ADDER1 XOR2B N 5 Node has multiple toggles 23 04 s i Node has multiple toggles 32 84 ADDER2 XOR2B N 4 Node has multiple toggles EI fe Fel fey 44 items displayed Detailed Error Description Static Power Diagnosis Estimated Rise Fall time of node ADDER0 XOR2A N 4 exceeds limit 0 87ns EI IG Figure 12 Power Diagnostics Browser Analyzing Results 221 Displaying Waveforms for Power and Ground Nodes Use the following procedure to display waveforms for power and ground nodes 1 Select the waveform display tool Simwave or turbowave from the Options menu in the main window 2 Select the name of the waveform display tool from the Result Analysis menu The waveform tool is started and the appropriate output file is loaded 3 From the waveform tool select the signals you want to view PowerMill User Guide 222 Chapter8 PowerMill Graphical Analyst Tutorial Appendix A Sample Power Reports Sample Block Power Report Block total umber of nodes in block 3953 umber of elements in block 9752 umber of block supply nodes f 11 umber of block ground nod
188. tion Wasted power can come from mismatched supply voltages a failure to reach full swing timing errors or other unintended sources It can also come from unavoidable analog bias circuits and current mirrors in operational amplifiers The report_ckt_dcpath command provides a method of detecting DC paths that occur during the dynamic simulation You can use the set_dcpath_thresh command to prevent the reporting of DC paths with small currents A DC path is reported only if the DC current through each element in the path exceeds the threshold You can use this to exclude paths for bias circuits from the report if they are sufficiently small Alternatively you can use the limit_dcpath_search command to exclude certain blocks from the search or to limit the search to specific blocks The detected DC paths are reported to the screen and to the dcpath file A sample DC path report is shown in Figure 9 PowerMill User Guide 116 Chapter4 Power Analysis Nonzero dc path s found at time 200 ns Path 1 resistor IOBUFF0 RI current 0 02 uA from XGND voltage 0 00 V to DATAOUTO voltage 0 00 V resistor IOBUFFO R2 current 79 98 uA from IOBUFFO VR voltage 4 00 V to DATAOUTO voltage 0 00 V Path 2 resistor IOBUFFO R1 current 99 97 uA from XGND voltage 0 00 V to DATAOUTO voltage 5 00 V inductor IOBUFFO OUTBOND current 119 93 uA from DATAOUTO voltage 5 00 V to IOBUFFO OUT1 voltage 5 00 V
189. u to obtain the maximum simulation speed from each circuit block The simulation will speed up 2 3 times for some circuits depending on the actual configuration of the circuit when doing a multi rate simulation Use the set_sim_subgroup ACE configuration command to enable a multi rate simulation You can use this command only when running in SMS or synchronous mode Controlling Waveform Print Resolution The PowerMill simulator allows you to change the time voltage or current resolution to the output file For ACE it is important to be able to alter the print resolution settings to get sufficient precision for post processing functions such as measure command processing or FFT processing Applying Multiple Simulation Modes 131 You can use the following commands to change the output print resolution m set print tres m set print vres m set print ires For complete reference information on these print resolution commands see Chapter 2 Configuration and Interactive Commands in the Powe Mill Reference Guide Applying Multiple Simulation Modes NOTE You can apply different simulation modes on a local or block level using the following commands m set elem acc Use this command to apply a more accurate model and algorithm to specified MOSFETs m set node pwl Use this command to force the channel connected stage containing a specified node to be simulated usi ng the PWL algorithm m set elem sms Use this command to
190. ulation button once simulation has begun and reverts to Start Simulation when it is completed Analyzing a Circuit Power Consumption When a simulation is complete average current information for the first level of the circuit hierarchy appears in the Result Display area of the PowerMill GA main window see Figure 8 Result Display Current Instance Block names Average current data AE p a Q hr Simulation Completed Figure 8 Average current information In the example the left column of the Result Display area shows the block names The right column shows the average current consumption Analyzing a Circuit 181 Sort By Menu You can view other power consumption information using the Sort By menu located on the top right side of the Result Display area see F igure 9 Sort By Average Current uA Average Power uw Wasted Current Capacitive Current Number of Toggles Budget Density powerftransistor Power Supply uA Figure 9 Sort by menu Select the following menu items to get different types of power information Average Power Information select to view average power information Wasted Current select to view information on short circuit current Capacitive Current Information select to view capacitive current information Budget select to view power budget information If you specified a budget in the Power Supply amp Block Setup for
191. unning this tutorial The GAP feature allows you to maximize four different objective fitness functions m Average power per clock cycle of the circuit m Instantaneous power of the circuit m Average value per clock cycle of the customized fitness function m Instantaneous value of the customized fitness function The usage model for GAP customization which encompasses the last two bulleted items is illustrated in tutorial 7 For sequential circuits such as the one shown in Figure 16 each measured power number is induced by three vectors known as a vector triplet that are applied in three consecutive clock cycles The first vector which stimulates both primary inputs PIs and pseudo primary inputs PPIs drives the circuit into a reachable state The second and third vectors stimulate only PIs and leave Advanced PowerMill Simulations 51 all PPIsin a floating state The power is measured in clock cycle 111 This method allows both the primary input vectors and the state of the circuit to evolve through the use of a genetic algorithm to maximize the objective function Figure 16 Schematic of the max_seq_power spi netlist For the vector triplet method to work correctly on a sequential design it must meet the following requirements m FFs or latches should be buffered at the output so that the GAP stimuli on the PPIs won t accidentally overwrite the content of the FFs If the FFs are not buffered at the o
192. urce node Since according to Kirchhoff s Current Law the algebraic sum of all currents at a node is zero internal nodes must be treated differently from voltage source nodes For this reason PowerMill defines the internal node current to be the sum of the positive currents flowing into the node PowerMill User Guide 100 Chapter4 Power Analysis Use the followi ng commands to print and report internal node currents see Analyzing Power at Full Chip Level on page 86 print node i print node didt print node iavg report node i print node irms report node powr For more specific information on each command see the PowerMill Reference Guide Working with Probes Under some circumstances the standard block level power reporting commands see Analyzing Power Block by Block on page 87 and Measuring Wasted Power on page 88 might not provide sufficient flexibility For these cases PowerMill provides the commands assign node i and assign branch i Together these commands allow you to construct a completely arbitrary sum of element branch currents EXAMPLE 1 assign branch i drain d sum mosl mos2 mos3 mos4 This example constructs a sum of drain current for several MOS transistors and assigns it to the d sum probe EXAMPLE 2 assign_node_i any_node n_sum mosl mos2 mos3 mos4 This example obtains the sum of all currents from these transistors into the node any_node The same probe name can be used in multi
193. urrent peak 5 31900e 04 uA at 2 86860e 03 ns Node vdd Average current 7 09839e 02 uA RMS current 26431e 03 uA Current peak 1 54890e 04 uA at 4 40181e403 ns Current peak 2 1 46190e 04 uA at 4 20181le 03 ns Current peak 3 1 38260e 04 uA at 4 00181e403 ns Current peak 4 38160e 04 uA at 3 80181e403 ns Current peak 5 1 32800e 04 uA at 2 86860e 03 ns Figure 1 Sample power report generated by report_node_powr If you prefer to monitor power consumption during the simulation you can use either the turboWave and SimWave waveform viewer to watch the power consumption during the simulation For more specific information on each command see Chapter 2 Configuration and Interactive Commands in the PowerMill Reference Guide Analyzing Power Block by Block Block level power analysis allows the you to find out where most of the power is being consumed within a circuit With this information you can optimize power within blocks that consume too much power Using a hierarchical netlist a flat netlist will not work you can isolate power to portions of blocks if PowerMill User Guide 88 Chapter4 Power Analysis necessary This type of analysis should be done in the design phase prior to finishing the layout A block level power analysis is most easily done using the report block powr configuration command EXAMPLE report block powr my block x1 x1 This example generates a block power report to the l 0g file
194. use PathMill for PPI detection you must verify the functionality of the latches by running an additional GAP simulation see Testing Latch Functionality for Flip Flops with Non Buffered Outputs on page 53 Use the following procedure to generate a ppi vec file using the PathMill simulator 1 Open and study the cfgpm configuration file The file contains only one PathMill configuration command pw_detect_ckt_latch This command instructs PathMill to perform latch detection on the circuit and generate a vector file containing the output of all the detected latches See the command definition for pw_detect_ckt_latch in the PathMill Reference Guide 2 Run PathMill using the runpm script which consists of the following PathMill command line pathmill n max_seq_power spi c cfgpm The latch detection simulation starts and stops with the following messages Start Latch Detection Latch Detection completed 3 Open and study the pathmill ppi vec file The following file sample shows its contents signal XDl c XD1 XDZ c XDZ f XD3 c XD3 f XD4 c XD4 type VEC io pppppppp The circuit described in max seq power spi contains four DFFs Since each flip flop in this circuit is comprised of two cascaded latches the pathmil ppi vec file includes eight signals Notice that the io type for all eight signals is p pseudo primary input PowerMill User Guide 66 Chapter3 PowerMill Tutorials NOTE The signals in any
195. utput you need to verify some information about the circuit and perform an PowerMill User Guide 52 Chapter 3 PowerMill Tutorials NOTE experimental GAP run to determine whether you should apply the vector tri plet method m FFs latches in the circuit should be universally positive edge tri ggered positive sensitive or negative edge tri ggered negative sensitive m Clock skew in the estimated circuit or block should be optimized and negligible If the sequential circuit does not satisfy each of these requirements the vector triplet method might produce an unrealistic result You can run the GAP feature on this type of circuit using the vector pair method described in tutorial 5 The vector pair method requires only PI information and estimates the design as a combinational circuit The only drawback is that the quality of the result can be degraded especially for large circuits since there is no control over the state of the circuit during the GAP search Identifying the Pseudo Primary Inputs Before running the GAP feature usi ng the vector triplet method the power estimation algorithm needs to identify the output of flip flops and latches the PPIs so that they can be stimulated appropriately during the searching of optimal stimuli There are three different methods for identifying the PPIs manual identification automatic detection using PowerMill detection using the PathMill simulator Manually Specify
196. wing procedure to run the differentiator simulation 1 Using vi open the diff spi netlist file Figure 10 provides the schematic for this circuit NBIAS X1 ar aaa BIAS PBIAS CDIFF 20p RIN 50K NAL OUT Figure 10 Schematic of differentiator circuit This circuit is the opposite of the integrator As in the integrator this circuit uses a 50K ohm resistor and 20 pF capacitor The compensation for the op amp was changed to allow this circuit to function a differentiator configuration can oscillate more easily if the op amp is not properly Getting the Input Files 151 compensated for the task Check the compensation capacitor in the subcircuit definition 2 Run the simulation using the rundiff script 3 Using turboWave load the diff out file 4 Load the in and out signals see Figure 11 File Signal Edit Format View Search Option Window Group Compare Messages viin TS eee cg v out ENE a LT AA Figure 11 Waveforms of signals in diff out file You will notice slew rate limiting effects and settling time limit effects The slope of the input triangle waveform is 0 5 V per microsecond and should give plus and minus 0 5 V on the output after it settles Tutorial 3 PLL SPICE Macro Modeling This tutorial uses a PLL SPICE macro model It models frequency as voltage That is voltage is an analog of frequency PowerMill User Guide 152 Chapter6 ACE Tutorials In t
197. y file generation Standard MKS engineering units for all data Values for time voltage current capacitance resistance and inductance are represented as seconds volts amps farads ohms and henries respectively In addition PowerMill supports these modeling features Theuse of multi level models comprised of behavioral gate switch and transistor models The Analog Digital Functional Model Interface ADF MI for writing functional models using the C programming language see the ADF MI Manual Inputs Outputs and Interfaces PowerMill s inputs are a netlist configuration file technology file and stimulus See Chapter 2 Getting Started for more information on input files PowerMill s outputs can be textual or graphical The SimWave tool from System Science the turboWave from E Team Design Systems the waveform tools in Cadence Design Framework II or VIEWlogic PowerView can be used to view analog current and voltage waveforms Major Functions and Features 5 A PowerMill interface is available in Cadence Opus and Edge VIEWlogic System Science in addition to the PowerMill Graphical Analyst and the ACE Graphical Analyst PowerMill also reports the peak average di dt and RMS current statistics of individual components subcircuit blocks and global power supply pads PowerMill User Guide 6 Chapter 1 Introduction to PowerMill Chapter 2 Getting Started 8 Chapter2 Getting Started Ove
198. y frequency and current consumption thresholds for reporting wasted power paths from supply to ground If you do not specify a simulation time then paths are reported for all time points in the simulation You can also specify thresholds for reporting elements This allows you to find violations that are likely to affect device and wire current consumption limits PowerMill User Guide 178 Chapter7 Using the PowerMill Graphical Analyst Tristate Check TheTristate Check button checks for nodes that are undriven for a specified time This allows you to keep track of nodes that leak above a specified voltage value Report Hazards The Report Hazards button checks for nodes that have multiple transitions within a specified time period This check is helpful for finding signal transitions that consume excessive power Power Distribution ThePower Distribution button creates a histogram of average and peak current for a particular time period For example if you specify a time window from 0 to 100 ns in four segments then a set of histograms will be created for the following time periods 0 25 26 50 51 75 and 76 100 ns Showing or Hiding Help Messages You can view or hide help messages using the Show Hide toggle button to the right of the Help Messages heading Saving or Clearing Checks When you finish specifying the checks click the OK button This saves your settings and closes the Power Diagnosis Setup form If you d
199. y the simulator as satisfactory PowerMill User Guide 42 Chapter 3 PowerMill Tutorials Files Needed for this Tutorial The following table lists the files needed for this tutorial These files are located in thepw advanced max powr 1 subdirectory in your working directory Filename Description cfg max power Configuration file for maximum power estimation max com powaerspi SPICE netlist of the combinational circuit a 4 bit ADDER to be estimated max com power 1 vec First vector file to be used for maximum power estimation max com power2 vec Second vector file to be used for maximum power estimation run max power Run script for maximum power estimation tech typ 25c 5v Technology file Procedure Use the following procedure to run the tutorial on estimating maximum power for combinational circuits 1 Open and examinethecfg max power configuration file The following file sample shows the contents of this configuration file use vec gap vec max com powerl vec vec max com power2 vec set gap opt period 20ns vec history 1 guide gap search fit 1 level 5 print probe i inst total power gap The use vec gap command starts the GAP feature and specifies two vector files with type vec to be used for the power estimation The two vector fil es for the GAP Advanced PowerMill Simulations 43 estimation contain the following statements signal names type radix opt

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