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Design Compiler® User Guide

1. 9 15 Analyzing Buffer Problems 9 15 Understanding Buffer Insertion 9 16 Correcting for Missing Buffers 9 22 Correcting for Extra Buffers 9 25 Correcting for Hanging Buffers 9 26 Correcting Modified Buffer Networks 9 26 Appendix A Design Example Design Description ze some ausasnt pee eee NAG ANNA A 2 Setup ile Soe ves yao eee wae ee ict gt oe eee oR es A 12 Default Constraints File A 13 Compile Scripts LES a yaa Sey eR A EU nahi ne me A 16 Appendix B Basic Commands Commands for Defining Design Rules B 2 Commands for Defining Design Environments B 2 xiii Commands for Setting Design Constraints Commands for Analyzing and Resolving Design Problems Appendix C Predefined Attributes Glossary Index xiv Preface This preface includes the following sections e What s New in This Release e About This Manual e Customer Support XV What s New in This Release Preface xvi This section describes the new features enhancements and changes included in Design Compiler version X 2005 09 Unless otherwise noted you can find additional information about these changes later in this book XG Mode Enabled by Default Starting with Design Compiler version X 2005 09 XG mode i
2. _ B Ce y 11 ns gt C 10ns Goal delay Assume that the clock period is 20 ns the maximum delay on each of these outputs is 10 ns and the path delays are as shown By default Design Compiler optimizes only the worst violator the path Performing Design Implementation 8 49 to output A To optimize all paths set the critical delay to 3 0 ns Table 8 3 shows the dcsh and dctcl command sequences for this example Table 8 3 Critical Range Examples dcsh Example dctcl Example create_clock period 20 clk create_clock period 20 clk set_critical_range 3 0 set_critical_range 3 0 current_design Scurrent design set max delay 10 A B C set max delay 10 A B C group path name groupl to A B C group path name group1 to A B C Optimizing All Paths You can optimize all paths by creating a path group for each endpoint in the design Creating a path group for each endpoint enables total negative slack optimization but results in long compile runtimes Table 8 4 shows dcsh and dctcl scripts that you can use to create a path group for each endpoint Table 8 4 Scripts to Create a Path Group for Each Endpoint dcsh Script dctcl Script endpoints N set endpoints add to collection N all outputs all outputs all registers data pins a11 registers data pins foreach endpt endpoints foreach in collection endpt Sendpoints group path name endpt t
3. Clock gating circuitry for power savings Asynchronous logic with potential hazards This functionality includes asynchronous logic and asynchronous signals that are valid during certain states Data path circuitry This functionality includes large multiplexers instantiated wide banks of multiplexers memory elements such as RAM or ROM and black box macro cells For more information about component implication see the HDL Compiler documentation Chapter 3 Preparing Design Files for Synthesis 3 32 Guidelines for Modules Observe these guidelines for modules e Avoid using logic expressions when you pass a value through ports The port list can include expressions but expressions complicate debugging In addition isolating a problem related to the bit field is difficult particularly if that bit field leads to internal port quantities that differ from external port quantities e Define local references as generics VHDL or parameters Verilog Do not pass generics or parameters into modules HDL Coding for Synthesis 3 33 Chapter 3 Preparing Design Files for Synthesis 3 34 4 Working With Libraries This chapter presents basic library information Design Compiler uses technology symbol and synthetic or DesignWare libraries to implement synthesis and to display synthesis results graphically You must know how to carry out a few simple library commands so that Design Compiler uses the library data corr
4. Specification type Operating condition Wire load model Clock frequency Input delay time Output delay time Input drive strength Output load Value WCCOM 20x20 40 MHz 3 ns 2ns drive_of IV 1 5 pF Chapter 8 Optimizing the Design 8 8 Example 8 1 dcsh Constraints File for Design TOP defaults con set_operating_conditions WCCOM set_wire_load_model 20x20 create_clock period 25 clk set_input_delay 3 clock clk all_inputs find port clk set_output_delay 2 clock clk all_outputs set_load 1 5 all_outputs set driving cell lib cell IV all inputs set drive 0 cik Example 8 2 dctcl Constraints File for Design TOP defaults con set operating conditions WCCOM set wire load model 20x20 create clock period 25 cik set input delay 3 clock clk remove from collection all inputs get ports cik set output delay 2 clock clk all outputs set load 1 5 all outputs set driving cell lib cell IV all inputs set drive 0 cik Note To prevent buffering of the clock network the script sets the input drive resistance of the clock port clk to O infinite drive strength Top Down Compile You can use the top down compile strategy for designs that are not memory or CPU limited Furthermore top level designs that are memory limited can often be compiled using the top down strategy if you first replace some of the subdesigns with interface logic model representations Rep
5. Cannot pass parameters must use directives in HDL Cannot specify the architecture to be elaborated Must use the 1ink command to resolve references VHDL Verilog Synthesize VHDL or Verilog Allows you to set parameter values on the elaborate command line Thus for parameterized designs you can use the analyze and elaborate commands to build a new design with nondefault values Allows you to specify architecture to be elaborated The elaborate command executes the 1ink command automatically to resolve references Reading Designs 5 13 Using the read_milkyway command In XG mode you can use the read_milkyway command to read design data from the Milkyway design library For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Reading HDL Designs Use one of the following methods to read HDL design files e The analyze and elaborate commands Follow these steps 1 Analyze the top level design and all subdesigns in bottom up order to satisfy any dependencies 2 Elaborate the top level design and any subdesigns that require parameters to be assigned or overwritten For example enter dc_shell xg t gt analyze format vhdl lib work RISCTYPES vhd dc_shell xg t gt analyze format vhdl lib work ALU vhd STACK TOP vhd STACK MEM vhd dc_shell xg t gt elaborate RISC CORE arch STRUCT lib WORK update e The read_file command For example enter
6. For more information about how your coding style affects architectural optimization see Chapter 3 Preparing Design Files for Synthesis Logic Level Optimization Logic level optimization works on the GTECH netlist It consists of the following two processes Structuring This process adds intermediate variables and logic structure to a design which can result in reduced design area Structuring is constraint based It is best applied to noncritical timing paths During structuring Design Compiler searches for subfunctions that can be factored out and evaluates these factors based on the size of the factor and the number of times the factor appears in the design Design Compiler turns the subfunctions that most reduce the logic into intermediate variables and factors them out of the design equations By default Design Compiler structures your design Use the set_structure command and the compile new boolean structure variable to control the structuring of your design The set structure command and its options set the following attributes structure structure boolean and structure timing The Optimization Process 8 3 Flattening The goal of this process is to convert combinational logic paths of the design to a two level sum of products representation Flattening is carried out independently of constraints It is useful for speed optimization because it leads to just two levels of combinational logic During flatte
7. Total 2 1816 Fall Delay computation fall_intrinsic 2 14 fall_slope Dt_fall O 0 0653 fall_resistance pin_cap wire_cap driver_count 0 0669 2 0 1 Total 2 2738 Finding Unmapped Cells All unmapped cells have the is_unmapped attribute You can use the dcsh filter and find commands or the dctcl get cells command to locate all unmapped components dc_shell xg t gt get cells hier filter is unmapped true Resolving Specific Problems 9 11 dc_shell gt filter find hier cell is unmapped true Finding Black Box Cells All black box cells have the is black box attribute You can use the dcsh filter and find commands or the dctcl get cells command to locate all black box cells dc_shell xg t gt get cells hier filter is black box true dc shell filter find hier cell is black box true Finding Hierarchical Cells All hierarchical cells have the is hierarchical attribute You can use the dcsh filter and find commands or the Tcl get designs command to locate all hierarchical cells dc_shell xg t gt get designs filter is hierarchical true dc shell filter find design is hierarchical true Disabling Reporting of Scan Chain Violations If your design contains scan chains it is likely that these chains are not designed to run at system speed This can cause false violation messages when you perform timing analysis To mask these messages use t
8. Avoid using references to nonlocal names within a function because the function might not be reevaluated if the nonlocal value changes This can cause a simulation mismatch between the HDL description and the gate level netlist For example the following Verilog function references the nonlocal name byte_sel function byte_compare input 15 0 vectorl vector2 input 7 0 length begin if byte_sel compare the upper byte else compare the lower byte end endfunction byte_compare HDL Coding for Synthesis 3 31 e Be aware that the local storage for tasks and functions is static Formal parameters outputs and local variables retain their values after a function has returned The local storage is reused each time the function is called This storage can be useful for debugging but storage reuse also means that functions and tasks cannot be called recursively e Be careful when using component implication You can map a function to a specific implementation by using the map to module and return port name compiler directives Simulation uses the contents of the function Synthesis uses the gate level module in place of the function When you are using component implication the RTL model and the gate level model might be different Therefore the design cannot be fully verified until simulation is run on the gate level design The following functionality might require component instantiation or functional implication
9. Loading Libraries 4 11 Reporting Library Contents Use the report_1ib command to report the contents of a library The report_1ib command can report the following data e Library units e Operating conditions e Wire load models e Cells including cell exclusions preferences and other attributes Specifying Library Objects Library objects are the vendor specific cells and their pins The Design Compiler naming convention for library objects is file library cell pin file The file name of a technology library followed by a colon If you have multiple libraries loaded in memory with the same name you must specify the file name library The name of a library in memory followed by a slash cell The name of a library cell pin The name of a cell s pin Chapter 4 Working With Libraries 4 12 For example to set the dont_use attribute on the AND4 cell in the my_lib library enter dc_shell xg t gt set dont use my_1ib AND4 1 To set the disable timing attribute on the Z pin of the AND4 cell in the my lib library enter one of the following commands depending on your command language dc_shell xg t gt set disable timing get pins my lib AND4 Z 1 dc shell set disable timing find pin my 1ib AND4 Z 1 Directing Library Cell Usage When Design Compiler maps a design to a technology library it selects components library cells from that library You can influence the choice of components
10. Use the report timing requirements command to list the timing exceptions in your design Specifying False Paths Design Compiler does not report false paths in the timing report or consider them during timing optimization Use the set false pathcommanad to specify a false path Use this command to ignore paths that are not timing critical that can mask other paths that must be considered during optimization or that never occur in normal operation For example Figure 7 5 shows a configuration register that can be written and read from a bidirectional bus DATA in a chip Figure 7 5 Configuration Register U2 DATA D B Ea U1 Phi 1 w e CONFIG RD The circuit has these timing paths 1 DATA to U1 D Chapter 7 Defining Design Constraints 7 18 2 RD to DATA 3 U1 G to CONFIG with possible time borrowing at U1 D 4 U1 G to DATA with possible time borrowing at U1 D 5 U1 G to U1 D through DATA with possible time borrowing The first four paths are valid paths The fifth path U1 G to U1 D isa functional false path because normal operation never requires simultaneous writing and reading of the configuration register In this design you can disable the false path by using this command dc_shell xg t gt set false path from U1 G to U1 D To undo a set_false path command use the reset_path command with similar options For example enter dc_shell xg t gt set false path
11. dc_shell xg t gt all_connected U8 A n66 dc_shell xg t gt all_connected U8 Z OUTBUS 10 dc_shell xg t gt remove_cell U8 Removing cell U8 in design top 1 dc_shell xg t gt create_cell U8 IVP Creating cell U8 in design top 1 dc_shell xg t gt connect_net n66 get_pins U8 A Connecting net nb6 to pin U8 A 1 dc_shell xg t gt connect_net OUTBUS 10 get_pins U8 Z Connecting net OUTBUS 10 to pin U8 Z 1 You can achieve the same result by using the change_link command instead of the series of commands listed in Table 5 6 For example the following command replaces the reference for cell U8 with a high power inverter dc_shell xg t gt change_link U8 IVP Editing Designs 5 49 Translating Designs From One Technology to Another You use the translate command to translate a design from one technology to another Designs are translated cell by cell from the original technology library to a new technology library preserving the gate structure of the original design The translator uses the functional description of each existing cell component to determine the matching component in the new technology library target library If no exact replacement exists for a component it is remapped with components from the target library You can influence the replacement cell selection by preferring or disabling specific library cells set_prefer and set_dont_use
12. e Enter dc shell and execute the script file using the source command dctcl or the include command desh A Design Compiler Session Example 2 27 For example if you are running Design Compiler and the script is in a file called run scr you can execute the script file by entering one of the following commands depending on your command language dc_shell xg t gt source run tcl dc_shell gt include run scr Run the script from the UNIX command line by using the option of the dc_shel1 command For example if the script is in a file called run scr you can invoke Design Compiler and execute the script file from the UNIX prompt by entering one of the following commands depending on your command language dc shell xg t f run tcl dc shell f run scr dc shell t f run scr Chapter 2 Design Compiler Basics 2 28 Preparing Design Files for Synthesis Designs that is design descriptions are stored in design files Design files must have unique names If a design is hierarchical each subdesign refers to another design file which must also have a unique name Note however that different design files can contain subdesigns with identical names This chapter contains the following sections e Managing the Design Data e Partitioning for Synthesis e HDL Coding for Synthesis 3 1 Managing the Design Data Use systematic organizational methods to manage the design data Two basic elements of managing
13. e General HDL constructs e Verilog macro definitions e VHDL port definitions General HDL Constructs The information in this section applies to both Verilog and VHDL Sensitivity Lists You should completely specify the sensitivity list for each Verilog always block or VHDL process Incomplete sensitivity lists shown in the following examples can result in simulation mismatches between the HDL and the gate level design Example 3 3 Incomplete Sensitivity List Verilog always A C lt A B Chapter 3 Preparing Design Files for Synthesis 3 22 Example 3 4 Incomplete Sensitivity List VHDL process A C lt A or B Value Assignments Both Verilog and VHDL support the use of immediate and delayed value assignments in the RTL code The hardware generated by immediate value assignments implemented by Verilog blocking assignments and VHDL variables is dependent on the ordering of the assignments The hardware generated by delayed value assignments implemented by Verilog nonblocking assignments lt and VHDL signals lt is independent of the ordering of the assignments For the most intuitive results e Use immediate value assignments within sequential Verilog always blocks or VHDL processes e Use delayed value assignments within combinational Verilog always blocks or VHDL processes if Statements When an if statement used in a Verilog always block or VHDL process as part of a continuous
14. end process infer end rtl Chapter 3 Preparing Design Files for Synthesis 3 20 Designing State Machines You can specify a state machine by using several different formats Verilog e VHDL e State table e PLA If you use the state vector and enum compiler directives in your HDL code Design Compiler can extract the state table from a netlist In the state table format Design Compiler does not retain the casex casez and parallel case information Design Compiler does not optimize invalid input combinations and mutually exclusive inputs Figure 3 11 shows the architecture for a finite state machine Figure 3 11 Finite State Machine Architecture Mealy machines only Clock Primar Next Next State Output Primary inputs state state vector logic outputs logic flip flops Present state Using an extracted state table provides the following benefits e State minimization can be performed e Tradeoffs between different encoding styles can be made HDL Coding for Synthesis 3 21 e Don t care conditions can be used without flattening the design e Don t care state codes are automatically derived For information about extracting state machines and changing encoding styles see the Design Compiler Reference Manual Optimization and Timing Analysis Using HDL Constructs The following sections provide information and guidelines about the following specific HDL constructs
15. 1 Find the feedback loop in your design by using the report timing loop option 2 Break the feedback loop by specifying the path as a false path Analyzing Buffer Problems Note This section uses the term buffer to indicate either a buffer or an inverter chain This section describes the following topics e Buffer insertion behavior e Missing buffer problems Resolving Specific Problems 9 15 e Extra buffer problems e Hanging buffer problems e Modified buffer network problems Understanding Buffer Insertion Design Compiler inserts buffers to correct maximum fanout load or maximum transition time violations If Design Compiler does not insert buffers during optimization the tool probably does not identify a violation For more information about the maximum fanout load and maximum transition time design rules see Setting Design Rule Constraints on page 7 3 Use the report_constraint command to get details on constraint violations Figure 9 1 shows a design containing the IV1 cell Figure 9 1 Buffering Example IN mAh OUT IV1 Chapter 9 Analyzing and Resolving Design Problems 9 16 Table 9 5 gives the attributes defined in the technology library for the IV1 cell Table 9 5 IV1 Library Attributes Pin Attribute Value direction input A capacitance 1 5 fanout_load 1 direction output Z rise_resistance 0 75 fall_resistance 0 75 max_fanout 3 max_transition 2 5 Example 9 3 shows the constra
16. 5 39 Preserving Hierarchical Pin Timing Constraints During Ungrouping 5 44 Merging Cells From Different Subdesigns 5 46 Editing Designs mma Kaawaan Casta kw hank BAN ne 5 47 Translating Designs From One Technology to Another 5 50 Procedure to Translate Designs 5 50 Restrictions on Translating Between Technologies 5 51 Removing Designs From Memory 5 52 Saving DESIGNS ass sense sommaires nee 5 53 Commands to Save Design Files 5 54 Using the write Command 5 54 Using the write milkyway Command 5 55 Saving Designs in ddc Format 5 55 Saving Designs in the db Format 5 56 Converting From db Format to ddc Format 5 57 Ensuring Name Consistency Between the Design Database and the Netlist 5 57 Naming Rules Section of the synopsys dc setup File 5 57 viii Using the define name rules map Command 5 58 Resolving Naming Problems in the Flow 5 59 Working With Attributes ssas ee 5 62 Setting Attribute Values 5 63 Using an Attribute Specific Command 5 64 Using the set attribute Command 5 64 Viewing Attribute Values 5 65 Saving Attribute Values cee es 5
17. A software process that generates an optimized gate level netlist which is based on a technology library from an input IC design Synthesis includes reading the HDL source code and optimizing the design from that description symbol library A library that contains the schematic symbols for all cells in a particular ASIC library Design Compiler uses symbol libraries to generate the design schematic You can use Design Vision to view the design schematic target library The technology library to which Design Compiler maps during optimization Target libraries contain the cells used to generate the netlist and definitions for the design s operating conditions technology library A library of ASIC cells that are available to Design Compiler during the synthesis process A technology library can contain area timing power and functional information on each ASIC cell The technology of each library is specific to a particular ASIC vendor timing exception An exception to the default single cycle timing behavior assumed by Design Compiler For Design Compiler to analyze a circuit correctly you must specify each timing path in the design that does not conform to the default behavior Examples of timing exceptions include false paths multicycle paths and paths that require a specific minimum or maximum delay time different from the default calculated time timing path A point to point sequence that dictates data propagation throug
18. Chapter 8 Optimizing the Design 8 56 Enabling Boolean Optimization Boolean optimization uses algorithms based on the basic rules of Boolean algebra Boolean optimization can use don t care conditions to minimize area This algorithm performs area optimization only do not use Boolean optimization for timing critical designs Use the compile new boolean structure variable and the boolean true option of the set_structure command to enable Boolean optimization Table 8 8 shows the commands you must run before you compile in both dcsh and dctcl syntax Table 8 8 Examples of Enabling Boolean Optimization dcsh Example dctcl Example compile_new_boolean_structure tru set compile_new_boolean_structure set_structure true boolean true true boolean_effort medium set_structure true boolean true boolean_effort medium Managing Resource Selection The decisions made during resource sharing can also significantly affect area Figure 8 10 shows that high level optimization can allocate the arithmetic operators in the same HDL code in two very different ways Performing Design Implementation 8 57 Figure 8 10 Resource Sharing Possibilities sel Late arriving signal K timing driven area driven The operator implementation also affects area For example in Figure 8 10 the timing driven version implements the adders as carry lookahead adders and the area driven example uses a ripple adder im
19. DSP Datapath extraction transforms arithmetic operators for example addition subtraction and multiplication into datapath blocks to be implemented by a datapath generator This transformation improves the quality of results QOR by utilizing the carry save arithmetic technique Carry save arithmetic does not fully propagate carries but instead stores results in an intermediate form For example a conventional implementation of the expression a b c d z would use three carry propagate adders CPAs whereas the carry save technique requires only one carry propagate adder and two carry save adders CSAs as shown in Figure 8 12 The carry save adders are faster than the conventional carry propagate adders because the carry save adder delay is independent of bit width These adders use significantly less area than carry propagate adders because they do not use full adders for the carry Using DC Ultra Datapath Optimization 8 63 Figure 8 12 Conventional Carry Propagate Adder and Faster Smaller Carry Save Adder Improved carry save b a b a adder implementation f Na ofat b c d z j Ne A CPAN a d CSA Na c p BE UN Conventional carry propagate r adder implementation of N 1 CPAN A a b c d zZ SRE NG Ne Z Z DC Ultra datapath optimization can extract the following components Chains of arithmetic operations Operators extracted as part of a datapath 5 lt lt gt N
20. block constraint files exist for each of the subblocks subdesigns in design TOP The compile scripts also use the default constraint file defaults con shown in Example 8 2 on page 8 9 Note This script shows only one pass through the bottom up compile procedure If the design requires further compilations you repeat the procedure from the point where the top level design TOP v is read in Selecting and Using a Compile Strategy 8 15 Example 8 5 Bottom Up Compile Script dcsh all blocks E D C B A compile each subblock independently foreach block all_blocks read in block block_source block v read_file format verilog block_source current_design block link apply global attributes and constraints include defaults con apply block attributes and constraints block_script block con include block_script compile the block compile read in entire compiled design read_file format verilog TOP v current_design TOP link write hierarchy output first_pass db apply top level constraints include defaults con include top_level con check for violations report_constraint characterize all instances in the design all instances U1 U2 U2 U3 U2 U4 U2 U5 characterize constraint all instances save characterize information foreach block all_blocks current_design block char block script block wscr write script gt char block
21. commands and by specifying the types of registers set_register_type command The target libraries are specified in the target_library variable The local link library Variable of the top level design is set to the target_library Value after the design is linked The translate command does not operate on cells or designs having the dont_touch attribute After the translation process Design Compiler reports cells that are not successfully translated Procedure to Translate Designs The following procedure works for most designs but manual intervention might be necessary for some complex designs To translate a design 1 Read in your mapped design Chapter 5 Working With Designs in Memory 5 50 dc_shell xg t gt read file design ddc or dc_shell gt read file design db Set the target library to the new technology library dc_shell xg t gt set target library target lib db or dc_shell gt target library target lib db Invoke the translate command dc_shell xg t gt translate After a design is translated you can optimize it using the compile command to improve the implementation in the new technology library Restrictions on Translating Between Technologies Keep the following restrictions in mind when you translate a design from one technology to another The translate command translates functionality logically but does not preserve drive strength during translation It always uses the lowest drive streng
22. compile if shell is in xg mode 0 write hier o S db path s design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl report timing requirements ignore gt gt Silog path s rpt file Compile Scripts A 21 Example A 22 muxmod tcl Script file for constraining MuxMod set rpt_file muxmod rpt set design muxmod current_design MuxMod source S script_path defaults con Define design environment set_load 2 2 Y_IN set_driving_cell lib_cell FD1 all_inputs Define design constraints set input delay 1 35 clock Sclk name D R F UPC set input delay 2 35 clock Sclk name MUX CNT set output delay 5 1 clock Sclk name Y IN set max area 0 compile if shell is in xg mode 0 write hier o S db path s design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl Appendix A Design Example A 22 Example A 23 pathseg tcl Script file for constraining path segment set rpt file pathseg rpt set design pathseg current design PathSegment source S script_path defaults con Define design environment set load 2 5 all outputs set driving cell lib cell FD1 all inputs set drive 0 Scilk name Define design rules set max fanout 6 S1 s2 Define design constraints set input delay 2 2 clock Sclk name R1 R2 set input delay 2 2 clock sclk name R3 R4 set input dela
23. dc_shell xg t gt read_file format verilog RISC_CORE v e The read_verilog Or read_vhdl command For example enter Chapter 5 Working With Designs in Memory 5 14 dc_shell xg t gt read verilog RISC_CORE v You can also use the read file format VHDL and read_file format verilog commands Reading ddc Files To read the design data from a ddc file use the read ddc command or the read_file format ddc command For example dc_shell xg t gt read ddc design file ddc Note Like the db format the ddc format is backward compatible you can read a ddc file that was generated with an earlier software version but not forward compatible you cannot read a ddc file that was generated with a later software version Reading db Files Although you can use the db format in XG mode it is not recommended To maximize the capacity and performance improvements offered in XG mode use the ddc format rather than the db format To read in a db file use the read db command or the read file format db command For example dc_shell xg t gt read db design file db The version of a db file is the version of Design Compiler that created the file For a db file to be read into Design Compiler its file version must be the same as or earlier than the version of Design Reading Designs 5 15 Compiler you are running If you attempt to read in a db file generated by a Design Compiler version that is later than the Design Compile
24. e Register the block outputs Chapter 3 Preparing Design Files for Synthesis 3 4 e Partition by design goal e Partition by compile technique e Keep sharable resources together e Keep user defined resources with the logic they drive e Isolate special functions such as pads clocks boundary scans and asynchronous logic The following sections describe each of these strategies Partitioning for Design Reuse Design reuse decreases time to market by reducing the design integration and testing effort When reusing existing designs partition the design to enable instantiation of the designs To enable designs to be reused follow these guidelines during partitioning and block design e Thoroughly define and document the design interface e Standardize interfaces whenever possible e Parameterize the HDL code Keeping Related Combinational Logic Together By default Design Compiler cannot move logic across hierarchical boundaries Dividing related combinational logic into separate blocks introduces artificial barriers that restrict logic optimization Partitioning for Synthesis 3 5 For best results apply these strategies e Group related combinational logic and its destination register together When working with the complete combinational path Design Compiler has the flexibility to merge logic resulting in a smaller faster design Grouping combinational logic with its destination register also simpli
25. using the set_cost_priority delay command Changing the priority prevents Design Compiler from fixing the maximum design rule violations if the fix results in a timing violation Correcting for Hanging Buffers A buffer that does not fan out to any cells is called a hanging buffer Hanging buffers often occur because the buffer cells have dont_touch attributes These attributes either can be set by you in the hope of retaining a buffer network or can be inherited from a library The dont_touch attribute on a cell signals to Design Compiler that the cell should not be touched during optimization Design Compiler follows these instructions by leaving the cell in the design But because the buffer might not be needed to meet the constraints that are set Design Compiler disconnects the net from the output The design meets your constraints but because the cell has the dont_touch attribute the cell cannot be removed Remove the dont_touch attribute to correct this problem Correcting Modified Buffer Networks Sometimes it appears that Design Compiler modifies a buffer network that has dont_touch attributes This problem usually occurs when you place the dont_touch attribute on a cell and expect the cells adjacent to that cell to remain in the design Chapter 9 Analyzing and Resolving Design Problems 9 26 Design Compiler does not affect the cell itself but modifies the surrounding nets and cells to attain the optimal structure If y
26. 10 Using the analyze and elaborate Commands 5 10 Using the read file Command 5 12 Using the read milkyway command annann 5 14 Reading HDL Designs eee eee 5 14 Reading ddc Fes asset NS Ana TERRE 5 15 R adind d6Files 2228 se semaines sea 5 15 Listing Designs in Memory sis ia ow aes adepte 5 16 Setting the Current Design 5 17 Using the current design Command 5 18 Linking Designs pce ALALA bag taob atan aa Bk fa Ala enr es 5 19 Locating Designs by Using a Search Path 5 21 Changing Design References 5 22 Listing Design Objects ox cc eb Beebe tax een ee BK nn dent 5 24 Specifying Design Objects 22 eue eed oe i eke pan 5 25 Using a Relative Path seems diem nets 5 25 Using an Absolute Path 5 27 Creating DESIGNS ESS ER thine woe bbe ce eee eae 5 28 Copying Designs 4 0 wre ee hee eee ee ee es 5 29 vii Renaming Designs aa AG en ana AG ends 5 30 Changing the Design Hierarchy 5 31 Adding Levels of Hierarchy 5 31 Grouping Cells Into Subdesigns 5 32 Grouping Related Components Into Subdesigns 5 34 Removing Levels of Hierarchy 5 35 Ungrouping Hierarchies Before Optimization 5 36 Ungrouping Hierarchies During Optimization
27. 2 8 interface logic model preserving as subdesign 8 29 top down compile 8 9 8 10 interfaces dc_ shell 2 8 is black box attribute 9 12 is hierarchical attribute 9 12 is unmapped attribute 9 11 L latches defined 3 15 inferring 3 15 leaf cell 5 5 libraries DesignWare 1 7 4 5 link 4 4 list of 6 9 list values of 6 9 6 17 listing names 4 11 main 4 9 power consumption 4 5 reading 4 11 removing from memory 4 16 reporting contents 4 12 saving 4 16 specifying 2 20 4 6 objects 4 12 symbol 4 5 synthetic 3 18 target 4 4 technology 4 3 timing values 4 5 library attributes C 5 library cell specifying 5 50 library cell attributes C 5 library objects defined 4 12 specifying 4 12 library registers specifying 5 50 license users command 2 17 licenses checking out 2 17 listing 2 17 releasing 2 17 using 2 16 working with 2 16 link library file extension 4 6 libraries cell references 4 4 specifying 4 6 target library and 4 9 link force case variable 5 20 link library variable 4 6 5 19 list command 6 12 list designs command 5 16 list duplicate designs command 5 16 list instances command 5 24 list libs command 4 11 6 9 load of command 9 24 log files command log file 2 15 filename log file 2 15 logic level optimization 8 3 M main library 4 9 man pages accessing 2 13 max_area attribute 7 26 max_capacitance attribute 7 8 9 25 max_fanout attribute 7 5 9 25 max_transition attribute 7 4 9 25 maximum delay ca
28. 3 30 functions 3 31 identifiers 3 28 modules 3 33 virtual clock creating 7 13 defined 7 13 W wire delays on ports 9 15 wire load defining 6 5 wire load mode default 6 12 reporting 6 13 specifying 6 12 wire load model IN 17 automatic selection wire load selection library function 6 11 described 6 11 worst negative slack defined 8 34 disabling 6 12 write command 5 54 a gt 2 write_lib command 4 16 hierarchical boundaries 6 7 Wile mukyway command rsy list of write_script command 5 66 technology libraries 6 9 removing 6 13 X report example 6 10 reporting 6 13 XG mode 2 7 specifying 6 12 starting Design Compiler 2 11 IN 18
29. 35 clk2 Design Compiler automatically derives a maximum path delay constraint of 35 20 library setup time of register at endpoint To specify a maximum path delay of 10 enter dc shell xg t5 set max delay 10 from regl to reg2 Design Compiler calculates the maximum path delay constraint as 10 library setup time of register at endpoint which overrides the original derived maximum path delay constraint Register to Port Paths Design Compiler uses the following equations to derive constraints for minimum and maximum path delays on register to port paths period output delay period output delay min delay max delay III Chapter 7 Defining Design Constraints 7 20 If you use the set_min_delay or set_max_delay commands the value specified in these commands replaces the period value in the constraint calculation For example assume you have a design with a clock period of 20 Output OUTPORTA has an output delay of 5 dc_shell xg t gt create_clock period 20 CLK dc_shell xg t gt set_output_delay 5 clock CLK OUTPORTA Design Compiler automatically derives a maximum path delay constraint of 15 20 5 To specify that you want a maximum path delay of 10 enter dc_shell xg t gt set max delay 10 to OUTPORTA Design Compiler calculates the maximum path delay constraint as 5 10 5 which overrides the original derived maximum path delay constraint Setting Optimization Constraints 7 21 Asynchr
30. 5 24 unmapped identifying 9 11 change link command 5 22 change names command 5 37 5 57 check design command 9 2 checkpointing automatically 9 6 defined 9 6 clock attributes C 1 clock network delay default 7 13 reporting 7 14 setting margin of error 7 13 specifying 7 13 clock uncertainty setting 7 10 clocks creating 7 10 defining 7 11 ideal 7 13 listing 5 25 multiple 7 12 removing 7 13 reporting 5 25 7 13 See also clock network delay specifying network delay 7 13 period 7 11 waveform 7 11 combinational logic partitioning 3 5 specifying delay requirements 7 16 command analyzing design problems B 5 design constraints setting B 3 design environment B 2 design rules B 2 resolving design problems B 5 command language dctcl and dcsh 2 8 command log files 2 15 command script 2 16 command_log_file variable 2 15 commands all clocks 5 25 all_ connected 5 48 all_fanin 8 52 all_outputs 5 24 all_registers 5 25 analyze 2 21 5 10 5 14 analyzing design 9 7 balance_buffer 8 51 change_link 5 22 change_names 5 37 5 57 check_design 9 2 compile auto_ungroup area 5 40 compile auto_ungroup delay 5 40 compile auto ungroup delay 8 54 compile ultra 8 43 8 45 connect net 5 47 copy design 5 29 create bus 5 47 create cell 5 47 create clock 7 10 7 11 8 35 create design 5 28 create multibit 3 18 create net 5 44 5 47 create port 5 45 5 47 current design 5 17 5 18 current instance 5 25 define name rules map 5 58 dis
31. 50 5 51 translating designs procedure for 5 50 restrictions 5 51 U ungroup command 5 36 8 27 ungroup design compile option 5 39 8 60 ungroup hierarchy examples 5 40 ungroup_preserve_constraints variable 5 44 ungrouping automatically cell count based 5 41 compile auto ungroup area num cells 5 41 compile auto ungroup count leaf cells 5 41 5 42 8 46 compile auto ungroup delay num cells 5 42 8 46 delay based 5 42 automatically during compile 5 40 8 54 automatically during compile ultra 8 45 removing hierarchy levels 5 36 5 39 8 60 uniquify command 8 22 uniquify method 8 21 V variables auto ungroup preserve constraints 5 43 8 47 command log file 2 15 compile assume fully decoded three stat e busses 5 52 compile auto ungroup area num cells 5 41 5 43 compile auto ungroup count leaf cells 5 41 5 42 8 46 compile auto ungroup delay num cells 5 42 5 43 8 46 compile autoungroup override wlm 5 43 8 46 compile fix cell degradation 8 34 compile log format 9 4 compile new boolean structure 8 57 current design 5 17 current instance 5 26 filename log file 2 16 hlo disable datapath optimization 8 62 8 76 link force case 5 20 link library 4 6 5 19 search path 4 10 sh command log file variable 2 15 symbol library 4 6 synthetic library 4 6 target library 4 6 ungroup preserve constraints 5 44 Verilog expressions 3 30 functions 3 31 identifiers 3 28 modules 3 33 VHDL expressions
32. 6 13 6 14 6 16 set false path 7 18 set fanout load 6 18 7 7 set flatten 8 4 set input delay 7 11 7 14 set input transition 6 14 set load 6 17 set max area 7 26 set max delay 7 16 7 19 set max fanout 7 7 set max transition 7 4 set min delay 7 16 7 19 IN 4 set multicycle path 7 22 set output delay 7 11 7 14 set resistance 9 15 set structure 8 3 8 57 set ultra optimization 8 76 set ungroup 5 39 8 60 set wire load 6 7 6 12 translate 5 50 5 51 ungroup 5 36 8 27 uniquify 8 22 write 5 54 write lib 4 16 write milkyway 5 55 write script 5 66 common base period defined 7 12 compile default 8 40 defined 2 2 directory structure bottom up 3 4 top down 3 3 high effort 8 54 incremental 8 55 compile auto ungroup area 5 40 compile auto ungroup delay 5 40 compile command automatically uniquified designs 8 21 default behavior 8 40 disabling design rule cost function 8 32 disabling optimization cost function 8 32 compile cost function 8 31 compile log customizing 9 3 compile option list of 8 5 compile script A 16 adder16 A 17 A 29 cascademod A 18 A 30 comparator A 19 A 31 multiply 8x8 A 20 A 32 multiply 16x16 A 21 A 33 muxmod A 22 A 34 pathseg A 23 A 35 compile scripts design example A 16 compile strategies 8 7 compile strategy bottom up 8 12 defined 2 23 mixed 8 19 top down 8 9 compile_assume_fully_decoded_three_state_ busses variable 5 52 compile auto ungroup area n
33. 66 Defining Attributes OR twee epee a en ant 5 66 Removing ATFIDUTeS ce seine s ova ede MNT ete 5 66 The Object Search Order 5 68 6 Defining the Design Environment Defining the Operating Conditions 6 3 Determining Available Operating Condition Options 6 4 Specifying Operating Conditions 6 5 Defining Wire Load Models 6 5 Hierarchical Wire Load Models 6 7 Determining Available Wire Load Models 6 9 Specifying Wire Load Models and Modes 6 11 Modeling the System Interface 6 13 Defining Drive Characteristics for Input Ports 6 13 The set_driving cell Command 6 14 The set_drive and set_input_transition Commands 6 15 Defining Loads on Input and Output Ports 6 17 Defining Fanout Loads on Output Ports 6 18 7 Defining Design Constraints Setting Design Rule Constraints 7 3 Setting Transition Time Constraints 7 4 Setting Fanout Load Constraints 7 5 Setting Capacitance Constraints 7 8 Setting Optimization Constraints 7 9 Setting Timing Constraints 7 10 Defihing a Clock aes renee ia oa eee en eee 7
34. Are there three state pins that require buffering e Have you considered that max transition takes precedence over max_fanout Incorrectly Specified Constraints A vendor might omit an attribute you want to use such as fanout_load If a vendor has not set this attribute in the library Design Compiler does not find any violations for the constraint You can check whether attributes have been assigned to cell pins by using the get_attribute command with the dcsh find or the Tcl get_pins command For example to determine whether a pin has a fanout_load attribute enter dc_shell xg t gt get_attribute get_pins library cell pin fanout_load dc_shell gt get_attribute find pin library cell pin fanout_load The vendor might have defined default_fanout_load in the library If this value is set to zero or to an extremely small number any pin that does not have an explicit fanout_load attribute inherits this value Improperly Constrained Designs Occasionally a vendor uses extremely small capacitance values on the order of 0 001 If your scripts do not take this into account you might not be constraining your design tightly enough Try setting an extreme value such as 0 00001 and run report_constraint to make sure a violation occurs Resolving Specific Problems 9 23 You can use the load of command with the dcsh find or the Tcl get_pins command to check the capacitance values in the technology library dc_shell xg t gt loa
35. R1 R2 set input delay 2 2 clock clk name R3 R4 set input delay 5 clock clk name S2 S1 OP set max area 0 Perform path segmentation for multiplier group design mult cell mult U100 set input delay 10 clock clk name mult product set output delay 5 clock clk name mult product set_multicycle path 2 to mult product compile write f db hierarchy o db path design db include script path report scr report timing requirements ignore gt gt log path rpt file Compile Scripts A 35 Example A 36 characterize scr Characterize and write script for all modules current design ChipLevel characterize ul current design Adder16 write script gt script path adder16 wscr current design ChipLevel characterize u2 current design CascadeMod write script gt script path cascademod wscr current design ChipLevel characterize u3 current design Comparator write script gt script path comp16 wscr current design ChipLevel characterize u4 current design Multiply8x8 write script gt script path mult8 wscr current design ChipLevel characterize u5 current_design Multiply16x16 write script gt script path mult16 wscr current design ChipLevel characterize ub current design MuxMod write script gt script path muxmod wscr current design ChipLevel characterize u7 current design PathSegment echo current design PathSegment gt N script path pathseg wscr echo g
36. Verilog and VHDL formats e The Mentor format requires schematics Working With Attributes Attributes describe logical electrical physical and other properties of objects in the design database An attribute is attached to a design object and is saved with the design database Design Compiler uses attributes on the following types of objects e Entire designs e Design objects such as clocks nets pins and ports e Design references and cell instances within a design e Technology libraries library cells and cell pins An attribute has a name a type and a value Attributes can have the following types string numeric or logical Boolean Some attributes are predefined and are recognized by Design Compiler other attributes are user defined Appendix C lists the predefined attributes Some attributes are read only Design Compiler sets these attribute values and you cannot change them Other attributes are read write You can change these attribute values at any time Chapter 5 Working With Designs in Memory 5 62 Most attributes apply to one object type for example the rise_drive attribute applies only to input and inout ports Some attributes apply to several object types for example the dont_touch attribute can apply to a net cell port reference or design You can get detailed information about the predefined attributes that apply to each object type by using the commands listed in Table 5 11 Table 5 1
37. a signal at a specified input port You use the set_input_delay command to set the input delay on a pin or input port relative to a specified clock signal instance An occurrence in a circuit of a reference a library component or design loaded in memory each instance has a unique name A design can contain multiple instances each instance points to the same reference but has a unique name to distinguish it from other instances An instance is also known as a cell leaf cell A fundamental unit of logic design A leaf cell cannot be broken into smaller logic units Examples are NAND gates and inverters link library A technology library that Design Compiler uses to resolve cell references Link libraries can contain technology libraries and design files Link libraries also contain the descriptions of cells library cells as well as subdesigns in a mapped netlist Link libraries include both local link libraries local link library attribute and system link libraries link_library variable multicycle path A path for which data takes more than one clock cycle to propagate from the startpoint to the endpoint You use the set_multicycle_path command to specify the number of clock cycles Design Compiler should use to determine when data is required at a particular endpoint GL 7 GL 8 netlist A file in ASCII or binary format that describes a circuit schematic the netlist contains a list of circuit elements and inter
38. accepting instance objects the all1 instances option allows you to set the size only attribute on a leaf cell when its parent design is instantiated multiple times For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Chapter 4 e Thechange link command In addition to accepting instance objects the all1 instances option allows you to make link changes for a leaf cell when its parent design is instantiated multiple times For more information see Chapter 5 of this manual Enhanced Formal Verification In Design Compiler version X 2005 09 the formal verification functionality provides the following e Enhanced automated setup file generation The default setup file default svf has been enhanced to record implicit ungrouping operations Implicit ungrouping operations can occur in the following cases When the compile ungroup all or compile auto_ungroup is executed If a design has an ungroup attribute set on it When DesignWare does auto ungrouping of DesignWare parts When certain user hierarchies are auto ungrouped for datapath optimization Third party formal verification link You can use the set_vsdc command to record setup information for third party formal verification tools The command records operations in the V SDC format which is an ASCII file The operations recorded are a subset of those recorded in the automated setup file Name change operations co
39. an argument dc_shell xg t gt current instance Current instance is the top level of the design Count 16 Thecurrent instance variable points to the current instance To display the current instance enter one of the following commands depending on your command language dc_shell xg t gt printvar current instance current instance Count 16 U1 dc shell list current instance current instance Count 16 U1 1 Chapter 5 Working With Designs in Memory 5 26 In DB mode dcsh command language the current_reference variable points to the reference of the current instance This variable is not supported in dctcl To display the reference of the current instance enter the following command dcsh only dc_shell gt list current_reference current_reference usr designs Count_16 db Count_4 1 Using an Absolute Path When you use an absolute path to specify a design object the object can be in any design in dc_shell memory Use the following syntax to specify an object by using an absolute path file design object file The path name of a memory file followed by a colon Use the file argument when multiple designs in memory have the same name design The name of a design in dc_shell memory object The name of the design object including its hierarchical path If several objects of different types have the same name and you do not specify the object type Design Compiler looks for the object by using the
40. and add 4 2 Note that the suffix of the operation names xxxx_4 represents the line number in the RTL code Example 8 10 on page 8 73 and if two adders appear in one line as in line 4 of the example the second adder is identified in the report asxxx 4 2 From the Datapath Report you see that the operators are merged into the single datapath module add 4 2 DP OP 245 8218 str The RTL datapath Connections table shows the input and output ports of the datapath and their connections to the actual RTL The Datapath Blocks table shows the datapath expression and operation type If you set the compile report dp variable to true the Datapath Report is printed to the screen and log file during compile Using DC Ultra Datapath Optimization 8 75 Commands Specific to DC Ultra Datapath Optimization Commands specific to DC Ultra datapath optimization are described in Table 8 11 Table 8 11 DC Ultra Datapath Optimization Commands Command Description set_ultra_optimization Set to true to enable DC Ultra the datapath optimization feature is one of the DC Ultra optimization techniques Also set the synlib_enable_dpgen variable to true to utilize optimal datapath generation If you do not specify the no_auto_dwlib option the dw_foundation sldb library is automatically added to the synthetic library list unless it is already listed If you do specify this option the dw_foundation sldb library is not used When DC Ultra datapath opti
41. be disabled DP 3 Use the report timing command to check timing and optimization results Use report resources to determine which operators were absorbed into the datapath block In the resource report shown in Example 8 9 the operators absorbed into the datapath are identified Using DC Ultra Datapath Optimization 8 71 Example 8 9 report resources Using DC Ultra Datapath Optimization for datapath1 Design Example 8 8 on page 8 67 report_resources KEK KK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKKEKK Report resources Design datapath1 Version W 2004 12 Date Fri Dec 3 17 15 46 2004 KREKKK KK KKK KKK KKK KKK KKK KKK KK KKK KK KKK KEKKEK Resource Sharing Report for design datapath1l in file usr home datapathl v Contained Resource Module Parameters Resources Contained Operations r262 mult_15_DP OP 246 3372 mult_11 r264 mult_15_DP_OP_246_3372 mult_15 r266 mult_15_DP_OP_246_3372 ada 19 Datapath Report for design datapathl in file usr home datapathl v RTL datapath Connections for mult_15_DP_OP_246_3372 str Bus RTL Wire Datapath Port Direction Width ac Il input 4 a I2 input 4 a I3 input 4 b I4 input 4 e I5 input 8 NO co control 1 NI 1 control 1 N26 N19 O1 output 8 Datapath Blocks i
42. can have Design Compiler retain user specified MUX_OP hierarchies by setting the compile create mux op hierarchy variable to true For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Chapter 3 High Effort Constant Register Removal In Design Compiler version X 2005 09 when the compile seqmap_ propagate high effort variable is set to true Design Compiler analyzes and removes constant registers that cannot escape their reset state This results in improved sequential area reduction For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Chapter 3 Automatic Sequential Area Recovery Design Compiler version X 2005 09 includes a fast back end sequential mapper that does automatic sequential area recovery It identifies clusters of registers with similar functionality and timing and optimizes the area of these register clusters as a whole In previous versions you used the compile sequential area recovery variable to achieve the same functionality when this variable was set to true the compile command attempted area reduction by remapping sequential elements In version X 2005 09 this variable is obsolete By default the compi le command always attempts area reduction by remapping sequential elements Advanced Datapath Transformations Design Compiler version X 2005 09 delivers the following enhancements in datapath extraction e Extraction o
43. cannot violate You can however specify stricter constraints Optimization constraints define the design goals for timing clocks clock skews input delays and output delays and area maximum area In the optimization process Design Compiler attempts to meet these goals but no design rules are violated by the process You define these constraints by using commands such as those listed under this step in Figure 2 2 To optimize a design correctly you must set realistic constraints Note Design constraint settings are influenced by the compile strategy you choose Flow steps 5 and 6 are interdependent Compile strategies are discussed in step 6 See Chapter 7 Defining Design Constraints Chapter 2 Design Compiler Basics 2 22 6 Select Compile Strategy The two basic compile strategies that you can use to optimize hierarchical designs are referred to as top down and bottom up In the top down strategy the top level design and all its subdesigns are compiled together All environment and constraint settings are defined with respect to the top level design Although this strategy automatically takes care of interblock dependencies the method is not practical for large designs because all designs must reside in memory at the same time In the bottom up strategy individual subdesigns are constrained and compiled separately After successful compilation the designs are assigned the dont_touch attribute to prevent
44. command with a default option specified to remove the attribute previously set by the command See the man page for a specific command to determine whether it has the default option or uses a corresponding remove command To remove all attributes from the current design use the reset_design command dc_shell xg t gt reset design Resetting current design EXAMPLE 1 The reset_design command removes all design information including clocks input and output delays path groups operating conditions timing ranges and wire load models The result of using reset design Is often equivalent to starting the design process from the beginning Working With Attributes 5 67 The Object Search Order When Design Compiler searches for an object the search order is command dependent Objects include designs cells nets references and library cells If you do not use a get dctcl or find dcsh command Design Compiler uses an implicit find to locate the object Commands that can set an attribute on more than one type of object use this search order to determine the object to which the attribute applies For example the set_dont_touch command operates on cells nets references and library cells If you define an object X with the set_dont_touch command and two objects such as the design and a cell are named X Design Compiler applies the attribute to the first object type found In this case the attribute is set on the des
45. commands from attempting to operate on nonexistent design objects Chapter 5 Working With Designs in Memory 5 52 Table 5 7 provides dcsh and dctcl examples that show the effects of the remove design command Table 5 7 remove design Examples dcsh Example dctcl Example dc_shell gt PORTS all inputs A2 A3 dc_shell gt list PORTS AO PORTS AL a AO AT A2 a dc shell remove design Removing design top il dc_shell gt list PORTS PORTS A3 dc_shel xg t gt set PORTS all inputs AO ALS A2 A3 dc_shel PORTS dc_shel xg t gt query objects SPORTS TAO Al A2 A3 xg t gt remove design Removing design top 1 dc_shel Error 1 xg t gt query objects SPORTS No such collection _sel2 SEL 001 Saving Designs You can save write to disk the designs and subdesigns of the design hierarchy at any time using different names or formats After a design is modified you should manually save it Design Compiler does not automatically save designs before it exits Table 5 8 lists the design file formats supported by Design Compiler Table 5 8 Supported Output Formats Format Description ddc Synopsys internal database format XG mode only Milkyway Format for writing a Milkyway database within Design Compiler XG mode only db Synopsys internal database f
46. compares the calculated capacitance value with the max_capacitance value of the pin driving the net For example to set a maximum capacitance of 3 for all nets in the design adder enter one of the following commands depending on your command language dc_shell xg t gt set max capacitance 3 get designs adder dc_shell gt set_max capacitance 3 find design adder Chapter 7 Defining Design Constraints 7 8 To undo a set_max_capacitance command use the remove_attribute command For example enter one ofthe following commands depending on your command language dc_shell xg t gt remove attribute get designs adder max capacitance dc shell remove attribute find design adder max capacitance You can also use the set min capacitance command to define the minimum capacitance for input ports or pins Design Compiler attempts to ensure that the load seen at the input port does not fall below the specified capacitance value but it does not specifically optimize for this constraint Setting Optimization Constraints This section discusses the most commonly specified optimization constraints e Timing constraints e Area constraints Design Compiler also supports power constraints For information about power constraints see the Power Compiler Reference Manual Figure 7 2 illustrates some of the common commands used to define the optimization constraints Setting Optimization Constraints 7 9 Figure 7 2 Com
47. constraints of the current design are preserved Timing constraints in other designs might be lost as a result of ungrouping hierarchy in the current design Merging Cells From Different Subdesigns To merge cells from different subdesigns into a new subdesign 1 Group the cells into a new design Chapter 5 Working With Designs in Memory 5 46 2 Ungroup the new design For example the following command sequence creates a new alu design that contains the cells that initially were in subdesigns u_add and u_mult dc_shell xg t gt group u_add u_mult design alu dc_shell xg t gt current_design alu dc_shell xg t gt ungroup all dc_shell xg t gt current_design top design Editing Designs Design Compiler provides commands for incrementally editing a design that is in memory These commands allow you to change the netlist or edit designs by using dc_shell commands instead of an external format Table 5 5 Design Editing Tasks and Commands Object Task Command Cells Create a cell create cel Delete a cell remove cell Nets Create a net create net Connect a net connect net Disconnect a net disconnect net Delete a net remove net Ports Create a port create port Delete a port remove port remove unconnected port Buses Create a bus create bus Delete a bus remove bus Editing Designs 5 47 For unique designs these netlist editing commands accept instance objects that is cells at a lower lev
48. db else write f ddc hier o S ddc_path design ddc source S script_path report tcl Compile Scripts A 19 Example A 20 mult8 tcl Script file for constraining Multiply8x8 set rpt_file mult8 rpt set design mult8 current design Multiply8x8 source S script_path defaults con Define design environment set load 2 2 res set driving cell lib cell FDIP all inputs set drive 0 Sclk name Define design constraints set input delay 1 35 clock Sclk name opl op2 set max area 0 compile if shell is in xg mode 0 write hier o S db path s design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl Appendix A Design Example A 20 Example A 21 mult16 tcl Script file for constraining Multiply16x16 set rpt file mult16 rpt set design mult16 current_design Multiply16x16 source S script_path defaults con Define design environment set_load 2 2 res set_driving_cell lib_cell FD1 all_inputs set_drive 0 clk_name Define design constraints set input delay 1 35 clock clk_name opl op2 set_max_area 0 Define multicycle path for multiplier set_multicycle_path 2 from all_inputs to all_registers data_pins edge_triggered Ungroup DesignWare parts set designware_cells get_cells filter is oper true if sizeof collection Sdesignware cells gt 0 set ungroup Sdesignware cells true
49. db rpt_file pathseg_wscr rpt include script_path report scr report timing requirements ignore gt gt log path rpt file Example A 38 report scr This script file creates reports for all modules maxpaths 15 check design gt log path rpt file report area gt gt log path rpt file report design gt gt log path rpt file report cell gt gt log path rpt file report reference gt gt log path rpt file report port verbose gt gt log path rpt file report net gt gt log path rpt file report compile options gt gt log path rpt file report constraint all violators verbose gt gt log path rpt file report timing path end gt gt log path rpt file report timing max path maxpaths gt gt log path rpt file report qor gt gt log path rpt file Appendix A Design Example A 38 Basic Commands This appendix lists the basic dc_shell commands for synthesis and provides a brief description for each command The commands are grouped in the following sections Commands for Defining Design Rules Commands for Defining Design Environments Commands for Setting Design Constraints Commands for Analyzing and Resolving Design Problems Within each section the commands are listed in alphabetical order B 1 Commands for Defining Design Rules The commands that define design rules are set_max_capacitance Sets a maximum capacitance for the nets attached to the specified ports
50. deep submicron ASIC and IC designs where maximum control over the optimization process is required In addition to the DC Expert capabilities DC Ultra provides the following features e Additional high effort delay optimization algorithms e Advanced arithmetic optimization e Integrated datapath partitioning and synthesis capabilities e Finite state machine FSM optimization e Advanced critical path resynthesis e Register retiming the process by which the tool moves registers through combinational gates to improve timing e Support for advanced cell modeling that is the cell degradation design rule e Location based optimization to enable faster timing closure by tightly linking the logical and physical environments e Advanced timing analysis HDL Compiler Tools The HDL compiler reads HDL files and performs translation and architectural optimization of the designs For more information about the HDL Compiler tools see the HDL Compiler documentation Chapter 1 Introduction to Design Compiler 1 6 DesignWare Library DesignWare library is a collection of reusable circuit design building blocks components that are tightly integrated into the Synopsys synthesis environment During synthesis Design Compiler selects the right component with the best speed and area optimization from the DesignWare Library For more information see the DesignWare Library documentation DFT Compiler The DFT Compiler tool is the Sy
51. delay cost calculations Each time you create a clock with the create_clock command Design Compiler creates a path group that contains all the paths associated with the clock You can also create path groups by using the group_path command see Creating Path Groups on page 8 47 for information about the group_path command Design Compiler places in the default group any paths that are not associated with any particular group or clock To see the path groups defined for your design run the report_path_group command Because the worst negative slack method does not optimize near critical paths this method requires fewer CPU resources than the critical negative slack method Because of the shorter runtimes the worst negative slack method is ideal for the exploration phase of the design Always use the worst negative slack method during default compile runs With the worst negative slack method the equation for the maximum delay cost is D V X W i 1 mis the number of path groups vis the worst violator in the ith path group w is the weight assigned to the th path group Design Compiler calculates the maximum delay violation for each path group as max 0 actual_path_delay max_delay Understanding the Compile Cost Function 8 35 Because only the worst violator in each path group contributes to the maximum delay violation how you group paths affects the maximum delay cost calculation e f only one path group
52. designs command 9 12 get license command 2 17 glue logic 3 6 group command 5 32 8 52 group path command 8 35 critical range option 8 49 features of 8 48 grouping adding hierarchy levels 5 31 IN 9 H HDL Compiler defined 1 6 HDL design reading analyze command 5 10 elaborate command 5 11 help accessing 2 13 hierarchical boundaries wire load model 6 7 hierarchical cells defined 5 5 identifying 9 12 hierarchical compile See top down compile hierarchical designs defined 5 3 hierarchical pin timing constraints preserving 5 44 hierarchical pins preserving timing constraints 5 44 hierarchy adding levels 5 31 changing 5 31 changing interactively 5 31 displaying 5 31 merging cells 5 46 removing levels 5 36 5 39 8 60 all 5 36 ungrouping automatically 5 40 high effort compile 8 54 hlo_disable_datapath_optimization variable 8 62 8 76 hold checks default behavior 7 22 overriding default behavior 7 22 7 24 timing arcs and 6 17 ideal clocks 7 13 IN 10 identifiers guidelines HDL 3 28 identifying black box cells 9 12 feedback loops 9 15 hierarchical cells 9 12 unmapped cells 9 11 if statement 3 23 incremental compile 8 55 infer_multibit compiler directive 3 18 infer_mux compiler directive 3 15 inferring registers 3 15 input arrival time default 7 14 removing 7 14 reporting 7 14 specifying 7 14 instances current 5 5 listing 5 24 reporting 5 24 interblock buffers 9 14 interface graphical user interface
53. e Synthesis Master Index About This Manual XXIX Conventions The following conventions are used in Synopsys documentation Convention Description Courier Indicates command syntax Courier italic Indicates a user defined value in Synopsys syntax such as object name A user defined value that is not Synopsys syntax such as a user defined value in a Verilog or VHDL statement is indicated by regular text font italic Courier bold Indicates user input text you type verbatim in Synopsys syntax and examples User input that is not Synopsys syntax such as a user name or password you enter in a GUI is indicated by regular text font bold Denotes optional parameters such as pinl pin2 pinN Indicates a choice among alternatives such as low medium high This example indicates that you can enter one of three possible values for an option low medium or high Connects terms that are read as a single term by the system such as set annotated delay Control c Indicates a keyboard combination such as holding down the Control key and pressing c N Indicates a continuation of a command line Indicates levels of directory structure Edit gt Copy Indicates a path to a menu command such as opening the Edit menu and choosing Copy Preface XXX Customer Support Customer support is available through SolvNet online customer support and through contacting the Synopsys Technical Support Cente
54. gt prompt e Adctcl DB mode is preceded by the dc_shell t gt prompt Running Design Compiler 2 7 e Adcsh DB mode example is preceded by the dc shells prompt Design Compiler Interfaces Design Compiler offers two interfaces for synthesis and timing analysis the dc_shell command line interface or shell and the graphical user interface GUI The dc shell command line interface is a text only environment in which you enter commands at the command line prompt Design Vision is the graphical user interface to the Synopsys synthesis environment use it for visualizing design data and analysis results For information on Design Vision see the Design Vision User Guide You can interact with the Design Compiler shell by using the following command languages e dctcl which is based on the tool command language Tcl and includes certain command extensions needed to implement specific Design Compiler functionality e dcsh which uses a command language specific to Synopsys and is available only in DB mode XG mode does not support this language The command languages provide capabilities similar to UNIX command shells including variables conditional execution of commands and control flow commands You can execute Design Compiler commands in the following ways e By entering single commands interactively in the shell e By running one or more command scripts which are text files of commands Chapter 2 Design Compiler Ba
55. input 7 0 din a din b input 1 0 sel input clk cin rst start input sl s2 op output 15 0 mux_out regout output 31 0 m32_out output cout1 cout2 comp out1 comp out2 wire 15 0 adl6 sout ad8 sout ml6 out cnt Adder16 ul ain datal6 a bin datal6 b cin cin cout cout1 sout ad16 sout clk clk CascadeMod u2 datal datal6 a data2 datal6_b cin cin s ad8 sout cout cout2 clk clk comp out comp out1 cnt cnt rst rst start start Comparator u3 ain ad16 sout bin ad8 sout cp_out comp_out2 Multiply8x8 u4 opl din a op2 din_b res m16 out clk clk Multiply16x16 u5 opl datal6_a op2 datal6_b res m32 out clk clk MuxMod u6 Y IN mux out MUX_CNT sel D ad16 sout R ad8 sout F m16 out UPC cnt PathSegment u7 R1 datal6 a R2 datal6_b R3 datal6_c R4 datal6_d S2 s2 S1 s1 OP op REGOUT regout clk clk endmodule Design Description A 5 Example A 2 Adder16 v module Adder16 ain bin cin sout cout clk 16 Bit Adder Module output 15 0 sout output cout input 15 0 ain bin input cin clk wire 15 0 sout_tmp ain bin wire cout_tmp reg 15 0 sout ain_tmp bin_tmp reg cout cin_tmp always posedge clk begin cout cout_tmp sout sout_tmp ain_tmp ain bin_tmp bin cin_tmp cin end assign cout_tmp sout_tmp ain_tmp bin_tmp cin_tmp en
56. lib Example 6 1 shows the resulting operating conditions report Example 6 1 Operating Conditions Report KKKIKKAKKKAKKAKKAKKKAKKAAKKAKKAKKKAKKKKK Report library Library my lib Version X 2005 09 Date Mon Jan 13 10 56 49 2005 KKKIKKAIKKKAKKAKKAKKKAKKAAKKAKKAKKKAKKkKKK Operating Conditions Name Library Process Temp Volt Interconnect Model WCCOM my lib 1 50 70 00 4 75 worst_case_tree WCIND my_lib 1 50 85 00 4 75 worst_case_tree WCMIL my_lib 1 50 125 00 4 50 worst case tree Chapter 6 Defining the Design Environment 6 4 Specifying Operating Conditions If the technology library contains operating condition specifications you can let Design Compiler use them as default conditions Alternatively you can use the set_operating_conditions command to specify explicit operating conditions which supersede the default library conditions For example to set the operating conditions for the current design to worst case commercial enter dc_shell xg t gt set_operating conditions WCCOM 1ib my lib Use the report_design command to see the operating conditions defined for the current design Defining Wire Load Models Wire load modeling allows you to estimate the effect of wire length and fanout on the resistance capacitance and area of nets Design Compiler uses these physical values to calculate wire delays and circuit speeds Semiconductor vendors develop wire load models based on statistical informat
57. library cells In Figure 5 1 the designs are TOP ENCODER and REGFILE The active design the design being worked on is called the current design Most commands are specific to the current design that is they operate within the context of the current design Chapter 5 Working With Designs in Memory 5 4 Reference A reference is a library component or design that can be used as an element in building a larger circuit The structure ofthe reference can be a simple logic gate or a more complex design a RAM core or CPU A design can contain multiple occurrences of a reference each occurrence is an instance References enable you to optimize every cell such as a NAND gate in a single design without affecting cells in other designs The references in one design are independent of the same references in a different design In Figure 5 1 the references are INV ENCODER and REGFILE Instance or Cell An instance is an occurrence in a circuit of a reference a library component or design loaded in memory each instance has a unique name design can contain multiple instances each instance points to the same reference but has a unique name to distinguish it from other instances An instance is also known as a cell A unique instance of a design within another design is called a hierarchical instance A unique instance of a library cell within a design is called a leaf cell Some commands work within the context of a hierarchic
58. max 0 actual power max leakage power For more information about the maximum power cost see the Power Compiler Reference Manual Chapter 8 Optimizing the Design 8 38 Calculating Maximum Area Cost Design Compiler computes the area of a design by summing the areas of each of its components cells on the design hierarchy s lowest level and the area of the nets Design Compiler ignores the following components when calculating circuit area e Unknown components e Components with unknown areas e Technology independent generic cells The cell and net areas are technology dependent Design Compiler obtains this information from the technology library Design Compiler calculates the maximum area cost as max 0 actual area max area Calculating Minimum Porosity Cost Design Compiler computes the porosity of a design by dividing the sum of the routing track area of each of its components on the design hierarchy s lowest level by the sum of all component areas Design Compiler ignores the following components when calculating porosity e Unknown components e Components with unknown routing track areas e Technology independent generic cells Understanding the Compile Cost Function 8 39 The routing track area of a cell and the cell area are technology dependent Design Compiler obtains this information from the technology library Design Compiler calculates the minimum porosity cost as max 0 min_porosity actua
59. obtains the following default values and settings from the main library e Unit definitions e Operating conditions e K factors e Wire load model selection e Input and output voltage e Timing ranges e RC slew trip points e Net transition time degradation tables If other libraries have units different from the main library units Design Compiler converts all units to those that the main library uses Specifying Libraries 4 9 Specifying DesignWare Libraries You do not need to specify the standard synthetic library standard sidb that implements the built in HDL operators The software automatically uses this library If you are using additional DesignWare libraries you must specify these libraries by using the synthetic_library variable for optimization purposes and the link library variable for cell resolution purposes For more information about using DesignWare libraries see the DesignWare User Guide Specifying a Library Search Path You can specify the library location by using either the complete path or only the file name If you specify only the file name Design Compiler uses the search path defined in the search_path variable to locate the library files By default the search path includes the current working directory and SYNOPSYS libraries syn Design Compiler looks for the library files starting with the leftmost directory specified in the search_path variable and uses the first matching library f
60. or to all the nets in a design set_max_fanout Sets the expected fanout load value for output ports set_max_transition Sets a maximum transition time for the nets attached to the specified ports or to all the nets in a design set_min_capacitance Sets a minimum capacitance for the nets attached to the specified ports or to all the nets in a design Commands for Defining Design Environments The commands that define the design environment are set_drive Sets the drive value of input or inout ports The set_drive command is superseded by the set driving cel1 command set driving cell Sets attributes on input or inout ports specifying that a library cell or library pin drives the ports This command associates a library pin with an input port so that delay calculators can accurately model the drive capability of an external driver Appendix B Basic Commands B 2 set_fanout_load Defines the external fanout load values on output ports set_load Defines the external load values on input and output ports and nets set_operating_conditions Defines the operating conditions for the current design set_wire_load_model Sets the wire load model for the current design or for the specified ports With this command you can specify the wire load model to use for the external net connected to the output port Commands for Setting Design Constraints The basic commands that set design constraints are create_clock Creates a cl
61. partitioning and your HDL coding style Partitioning and coding style directly affect the synthesis and optimization processes Note This step is included in the flow but it is not actually a Design Compiler step You do not create HDL files with the Design Compiler tools See Chapter 3 Preparing Design Files for Synthesis 2 Specify Libraries You specify the link target symbol and synthetic libraries for Design Compiler by using the link library target library symbol library and synthetic library commands The link and target libraries are technology libraries that define the semiconductor vendor s set of cells and related information such as cell names cell pin names delay arcs pin loading design rules and operating conditions The symbol library defines the symbols for schematic viewing of the design You need this library if you intend to use the Design Vision GUI Chapter 2 Design Compiler Basics 2 20 In addition you must specify any specially licensed DesignWare libraries by using the synthetic_library command You do not need to specify the standard DesignWare library See Chapter 4 Working With Libraries 3 Read Design Design Compiler can read both RTL designs and gate level netlists Design Compiler uses HDL Compiler to read Verilog and VHDL RTL designs It has a specialized netlist reader for reading Verilog and VHDL gate level netlists The specialized netlist reader reads netli
62. predefined wire load models Use the report 1ib command to list the wire load models defined in a technology library The library must be loaded in memory before you run the report 1ib command To see a list of libraries loaded in memory use the list_libs command The wire load report contains the following sections e Wire Loading Model section This section lists the available wire load models e Wire Loading Model Mode section This section identifies the default wire load mode If a library default does not exist Design Compiler uses top mode e Wire Loading Model Selection Group section The presence of this section indicates that the library supports automatic area based wire load model selection To generate a wire load report for the my_lib library enter dc_shell xg t gt read file my lib db Defining Wire Load Models 6 9 dc_shell xg t gt report lib my lib Example 6 2 shows the resulting wire load models report The library my lib contains three wire load models 05x05 10x10 and 20x20 The library does not specify a default wire load mode so Design Compiler uses top as the default wire load mode and it supports automatic area based wire load model selection Example 6 2 Wire Load Models Report KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KK KEKE Report Library my_lib Version Date library 1999 05 Mon Jan 4 10 56 49 1999 KEK KKK KKK KKK KKK KKK KKK KKK KKK KKK KEK KKK KK KEK Wire Loading M
63. preliminary compile when you want to get a quick idea of design area and performance you set map_effort to low In a default compile when you are performing design exploration you use the medium map effort option Because this option is the default you do not need to specify map effort in the compile command In a final design implementation compile you might want to set map effort to high You should use this option judiciously however because the resulting compile process is CPU intensive Often setting map effort to medium is sufficient See Chapter 8 Optimizing the Design 8 Analyze and Resolve Design Problems Design Compiler can generate numerous reports on the results of a design synthesis and optimization for example area constraint and timing reports You use reports to analyze and resolve any design problems or to improve synthesis results You can use the check design command to check the synthesized design for consistency Other check commands are available Chapter 2 Design Compiler Basics 2 24 See Chapter 9 Analyzing and Resolving Design Problems 9 Save the Design Database You use the write command to save the synthesized designs Remember that Design Compiler does not automatically save designs before exiting You can also save in a script file the design attributes and constraints used during synthesis Script files are ideal for managing your design attributes and constraints S
64. script recompile each block Chapter 8 Optimizing the Design 8 16 foreach block all blocks clear memory remove_design all read in previously characterized subblock block_source block v read_file format verilog block_source recompile subblock current_design block link apply global attributes and constraints include defaults con apply characterization constraints char_block_script block wscr include char_block_script apply block attributes and constraints block_script block con include block_script recompile the block compile Selecting and Using a Compile Strategy 8 17 Example 8 6 Bottom Up Compile Script dctcl set all blocks ED C B A compile each subblock independently foreach block Sall blocks read in block set block source Sblock v read file format verilog Sblock source current design Sblock link apply global attributes and constraints source defaults con apply block attributes and constraints set block script Sblock con source Sblock script compile the block compile read in entire compiled design read_file format verilog TOP v current_design TOP link write hierarchy format ddc output first pass dde apply top level constraints source defaults con source top_level con check for violations report_constraint characterize all instances in the design set all_instan
65. search_path variable Design Compiler looks for the design files starting with the leftmost directory specified in the search_path variable and uses the first design file it finds By default the search path includes the current working directory and SYNOPSYS libraries syn To see where Design Compiler finds a file when using the search path use the which command For example enter dc_shell xg t gt which my design ddc usr designers example my_design ddc To specify other directories in addition to the default search path use one of the following commands depending on your command language dc_shell xg t gt lappend search path project OR Linking Designs 5 21 dc_shell gt search path search path project Changing Design References Use the change _ link command to change the component or design to which a cell or reference is linked e Fora cell the link for that cell is changed e Fora reference the link is changed for all cells having that reference The link can be changed only to a component or design that has the same number of ports with the same size and direction as the original reference When you use change_link all link information is copied from the old design to the new design If the old design is a synthetic module all attributes of the old synthetic module are moved to the new link The change_link command accepts instance object that is cells at a lower level in the hierarchy A
66. setup from IN2 to FF12 D dc_shell xg t gt reset_path setup from IN2 to FF12 D Creating a false path differs from disabling a timing arc Disabling a timing arc represents a break in the path The disabled timing arc permanently disables timing through all affected paths Specifying a path as false does not break the path it just prevents the path from being considered for timing or optimization Specifying Minimum and Maximum Delay Requirements You can use the set min delay and set max delay commands described earlier in this chapter to specify path delay requirements that are more conservative than those derived by Design Compiler based on the clock timing Toundoa set min delayO0r set max delay command use the reset path command with similar options Setting Optimization Constraints 7 19 Register to Register Paths Design Compiler uses the following equations to derive constraints for minimum and maximum path delays on register to register paths min_delay Danes Tlaunch hold max delay T apture 7 Tiaunch 7 setup You can override the derived path delay T capture Tiaunch by using the set_min_delay and set_max_delay commands For example assume that you have a path launched from a register at time 20 that arrives at a register where the next active edge of the clock occurs at time 35 dc_shell xg t gt create clock period 40 waveform 0 20 c1k1 dc_shell xg t gt create clock period 40 waveform 15
67. shown in Example 9 6 Net IN max transition 2 50 Transition Time 3 75 Slack 1 25 VIOLATED When you compile this design Design Compiler adds buffering to correct the max_transition violations Resolving Specific Problems 9 21 Remember the following points when you work with buffers in Design Compiler e The max_fanout and max transition constraints control buffering be sure you understand how each is used e Design Compiler fixes only violations it detects e The report_constraint command identifies any violations Correcting for Missing Buffers Missing buffers present the most frequent buffering problem It usually results from one of the following conditions e Incorrectly specified constraints e Improperly constrained designs e Incorrect assumptions about constraint behavior To debug the problem generate a constraint report report constraint to determine whether Design Compiler recognized any violations If Design Compiler reports no max_fanout Or max transition violations check the following e Are constraints applied e Is the library modeled for the correct attributes e Are the constraints tight enough If Design Compiler recognizes a violation but compile does not insert buffers to remove the violation check the following e Does the violation exist after compile Chapter 9 Analyzing and Resolving Design Problems 9 22 e Are there dont touch or dont touch network attributes e
68. sizeof_collection get_ports clk gt 0 set clk_name clk create_clock period clk_period clk Create virtual clock if clock port is not found if sizeof_collection get_ports clk 0 set clk_name vclk create clock period clk period name vclk Apply default drive strengths and typical loads for I O ports set_load 1 5 all_outputs set_driving_cell lib_cell IV all_inputs If real clock set infinite drive strength if sizeof_collection get_ports clk gt 0 set_drive 0 clk Apply default timing constraints for modules set input delay 1 2 all inputs clock clk_ name set output delay 1 5 all outputs clock Scilk name set clock uncertainty setup 0 45 Scilk name Set operating conditions set operating conditions WCCOM Turn on auto wire load selection library must support this feature set auto wire load selection true Appendix A Design Example A 14 Example A 14 defaults con dcsh Define system clock period clk_period 20 Create real clock if clock port is found if find port clk clk clk_name clk create_clock period clk_period clk Create virtual clock if clock port is not found if find port clk 1 clk_name vclk create_clock period clk_period name vclk Apply default drive strengths and typical loads for I O ports set_load 1 5 all_outputs set driving cell lib cell IV all inputs If
69. timing path through combinational logic from the source to that pin or port Fanout tracing stops at the data pin of a register or at valid endpoints Fanout is also known as transitive fanout or timing fanout You use the report_transitive_fanout command to report the fanout of a specified source pin port or net fanout load A unitless value that represents a numerical contribution to the total fanout Fanout load is not the same as load which is a capacitance value Design Compiler models fanout restrictions by associating a fanout_load attribute with each input pin and a max_fanout attribute with each output driving pin on a cell and ensures that the sum of fanout loads is less than the max_fanout value flatten To convert combinational logic paths of the design to a two level sum of products representation During flattening Design Compiler removes all intermediate terms and therefore all associated logic structure from a design Flattening is constraint based You use the set_flatten command to control the flattening of your design Design Compiler does not perform flattening by default forward annotate To transfer data from the synthesis environment to other tools used later in the design flow For example delay and constraints data in Standard Delay Format SDF might be transferred from the synthesis environment to guide place and route tools GL 5 GL 6 generated clock A clock signal that is generated int
70. to the current command only The user specified synthetic library and link library lists are not affected In addition all DesignWare hierarchies are by default unconditionally ungrouped in the second pass of the compile You can prevent this ungrouping by setting the compile ultra ungroup dw variable to false the default is true To use the compile ultra command you will need a DC Ultra license and a DesignWare Foundation license For more information on this command see the man page Automatic Ungrouping Using the compile ultra command By default the compile ultra command performs automatic ungrouping of hierarchies both area based auto ungrouping and delay based auto ungrouping e The command performs area based auto ungrouping before initial mapping The tool estimates the area for unmapped hierarchies and removes small subdesigns the goal is to improve area and timing quality of results Because the tool performs auto ungrouping at an early stage it has a better optimization context Additionally datapath extraction is enabled across ungrouped hierarchies These factors improve the timing and area quality of results Performing Design Implementation 8 45 The command also performs delay based auto ungrouping Delay based auto ungrouping ungroups hierarchies along the critical path and is used essentially for timing optimization Use the compile auto ungroup delay num cells variable to specify a threshold belo
71. uP cell name UCELL Example 3 In the following example three cells bot1 foo1 and j are grouped into a new subdesign named SAMPLE with an instance name U1 The cells are at a lower level in the hierarchy and at the same hierarchical level the parent design is unique dc_shell xg t gt group mid1 bot1 midil fool mid1 j cell name U1 design name SAMPLE The preceding command is equivalent to issuing the following two commands dc_shell xg t gt current_design mid dc_shell xg t gt group bot1 fool j cell name U1 design name SAMPLE Changing the Design Hierarchy 5 33 Note In DB mode the group command cannot accept instance objects To group cells that are at a lower level of hierarchy enter dc_shell gt current design mid dc_shell gt group bot1 fool j cell name U1 design name SAMPLE Grouping Related Components Into Subdesigns You also use the group command but with different options to group related components into subdesigns To group related components use options to the group command as follows To do this Use this Specify one of the following component types Bused gates hdl_bussed Combinational logic logic Finite state machines fsm HDL blocks hdl_all_blocks hdl_block block name PLA specifications pla Specify the name of the new design name subdesign Chapter 5 Working With Designs in Memory 5 34 To do this Use this Optionally specify
72. where it is stored within GL 9 GL 10 the design and how it is transferred through the design RTL models circuit behavior at the level of data flow between a set of registers This level of abstraction typically contains little timing information except for references to a set of clock edges and features setup time The time that a signal on the data pin must remain stable before the active edge of the clock The setup time creates a maximum delay requirement for paths leading to the data pin of a cell You calculate the setup time by using the formula setup max data delay min clock delay slack A value that represents the difference between the actual arrival time and the required arrival time of data at the path endpoint in a mapped design Slack values can be positive negative or zero A positive slack value represents the amount by which the delay of a path can be increased without violating any timing constraints A negative slack value represents the amount by which the delay of a path must be reduced to meet its timing constraints structuring To add intermediate variables and logic structure to a design which can result in reduced design area Structuring is constraint based It is best applied to noncritical timing paths By default Design Compiler structures your design You use the set_structure command and the compile new boolean structure Variable to control the structuring of your design synthesis
73. without being verbose For example assume that you have a variable that represents the floating point opcode for rs1 A short name such as frs1 does not convey the meaning to the reader A long name such as floating_pt_opcode_rs1 conveys the meaning but its length might make the source code difficult to read Use a name such as fpop_rs1 which meets both goals Use aconsistent naming style for capitalization and to distinguish separate words in the name Commonly used styles include C Pascal and Modula C style uses lowercase names and separates words with an underscore for example packet_addr data_in and first_grant_enable Pascal style capitalizes the first letter of the name and first letter of each word for example PacketAddr Dataln and FirstGrantEnable Modula style uses a lowercase letter for the first letter of the name and capitalizes the first letter of subsequent words for example packetAddr dataln and firstGrantEnable Choose one convention and apply it consistently Avoid confusing characters Some characters letters and numbers look similar and are easily confused for example O and 0 zero and 1 one Avoid reserved words HDL Coding for Synthesis 3 29 e Use the noun or noun followed by verb form for names for example AddrDecode DataGrant PCI_ interrupt e Adda suffix to clarify the meaning of the name Table 3 2 shows common suffixes and their meanings Table 3 2 Si
74. 000000 END CASE An incomplete case statement results in the creation of a latch VHDL does not support incomplete case statements In Verilog you can avoid latch inference by using either the default clause or the full_case compiler directive Although both the full_case directive and the default clause prevent latch inference they have different meanings The full_ case directive asserts that all valid input values have been specified and no default clause is necessary The default clause specifies the output for any undefined input values For best results use the default clause instead of the full case directive If the unspecified input values are don t care conditions using the default clause with an output value of x can generate a smaller implementation HDL Coding for Synthesis 3 25 If you use the full case directive the gate level simulation might not match the RTL simulation whenever the case expression evaluates to an unspecified input value If you use the default clause simulation mismatches can occur only if you specified don t care conditions and the case expression evaluates to an unspecified input value Constant Definitions Use the Verilog define statement or the VHDL constant statement to define global constants Keep global constant definitions in a separate file Use parameters Verilog or generics VHDL to define local constants Example 3 9 shows a Verilog code fragment that includes a global
75. 1 Commands to Get Attribute Descriptions Object type Command All man attributes Designs man design_attributes Cells man cell_attributes Clocks man clock_attributes Nets man net_attributes Pins man pin_attributes Ports man port_attributes Libraries man library_attributes Library cells man library_cell_attributes References man reference_attributes Setting Attribute Values To set the value of an attribute use one of the following e An attribute specific command e Theset attribute command Working With Attributes 5 63 Using an Attribute Specific Command Use an attribute specific command to set the value of the command s associated attribute For example dc shell xg t5 set dont touch U1 Using the set attribute Command Use this command to set the value of any attribute or to define a new attribute and set its value For example to set the flatten attribute to false on the design named top enter dc_shell xg t gt set attribute top flatten false The set attribute command enforces the predefined attribute type and generates an error if you try to set an attribute with a value of an incorrect type Note In DB mode the set attribute command does not perform type checking To determine the predefined type for an attribute use the list attributes application command This command generates a list of all application attributes and their types To generate a smaller report you can use the class att
76. 11 Specifying I O Timing Requirements 7 14 Specifying Combinational Path Delay Requirements 7 16 Specifying Timing Exceptions 7 17 Setting Area Constraints 2 ohiewsce foes bike Re Rae 7 26 Verifying the Precompiled Design 7 27 8 Optimizing the Design The Optimization Process ares ou ees os seb 8 2 Architectural Optimization 8 2 Logic Level Optimization 8 3 Gate Level Optimization 8 6 Selecting and Using a Compile Strategy 8 7 Top Down Compile paaa mapiga eee penne ee te dde san 8 9 Bottom Up Compile swore rss teens DA RA RASE se 8 12 Mixed Compile Strategy 8 19 Resolving Multiple Instances of a Design Reference 8 20 Uniquify Method 4 ass eR den a Seer eee RATE 8 22 Compile Once Don t Touch Method 8 25 Ungroup MINOR ans sans semer asser 8 27 Preserving Subdesigns 8 28 Understanding the Compile Cost Function 8 31 Calculating Transition Time Cost 8 32 Calculating Fanout Cost 8 32 Calculating Capacitance Cost 8 33 Calculating Cell Degradation Cost 8 34 Calculating Maximum Delay Cost 8 34 Worst N
77. 2 wire load model 6 12 startpoints timing exceptions 7 17 state machine design 3 21 statements define 3 26 case 3 24 constant 3 26 if 3 23 structured logic optimization 8 43 structuring design optimization 8 3 subdesigns 5 3 preserving 8 28 symbol library defined 4 5 file extension 4 6 search path for 4 10 specifying 4 6 symbol_library variable 4 6 sync_set_reset directive 3 17 synchronous designs clock period 7 11 synopsys dc setup file 2 9 sample 2 10 synthesis defined 2 2 synthesis design flow figure 2 19 synthetic libraries 3 18 synthetic_library variable 4 6 T target library definition 4 4 file extension 4 6 link library and 4 9 IN 16 specifying 4 6 target_library variable 4 6 technology library creating 4 3 definition 4 3 required format 4 3 search path for 4 10 timing analyzing 9 8 reports 7 17 timing arcs hold checks and 6 17 setup checks and 6 17 timing constraints commands to set 7 10 timing exception commands listing 7 18 order of precedence 7 24 7 25 defined 7 17 ignored list of 7 17 reporting 7 17 valid endpoints 7 17 valid startpoints 7 17 timing path report 9 9 timing values link libraries 4 5 timing violations correcting 9 24 scan chain 9 12 top down compile 8 9 advantages 8 10 directory structure figure 3 3 total negative slack defined 8 36 transition time cost calculation 8 32 defined 7 4 setting 7 4 specifying maximum 7 4 translate command 5
78. 2 inv1i 1 Linking Designs 5 23 Listing Design Objects Design Compiler provides commands for accessing various design objects These commands refer to design objects located in the current design Each command in Table 5 3 performs one of the following actions e List Provides a listing with minimal information e Display Provides a report that includes characteristics of the design object e Return Returns a list dcsh or collection dctcl that can be used as input to another dc_ shell command Table 5 3 lists the commands and the actions they perform Table 5 3 Commands to Access Design Objects Object Command Action Instance list_instances Lists instances and their references report_cell Displays information about instances Reference report_reference Displays information about references Port report_port Displays information about ports report_bus Displays information about bused ports all_inputs Returns all input ports all_outputs Returns all output ports Chapter 5 Working With Designs in Memory 5 24 Table 5 3 Commands to Access Design Objects Continued Object Command Action Net report_net Displays information about nets report_bus Displays information about bused nets Clock report_clock Displays information about clocks all_clocks Returns all clocks Register all_registers Returns all registers Note In dctcl you can also use the get commands to create and list collections of ce
79. 24 report resources command 8 73 report timing command feedback loops 9 15 IN 14 wire load information 6 13 report timing requirements command delay requirements 7 17 ignored option 7 17 timing exceptions 7 18 reports analyzing design 9 7 analyzing timing 9 8 check design command 9 2 clock definition 7 13 delay calculation 9 9 library contents 4 12 operating condition 6 4 operating conditions 6 5 report hierarchy command 5 31 script file A 27 A 38 timing exceptions 7 17 ignored 7 17 timing path 9 9 wire load model example 6 10 reset path command 7 19 7 24 resistance output driver defining 6 13 See also drive characteristics resolving multiple instances of a design 8 20 resource allocation area driven 8 58 timing driven 8 58 resources shareable 3 10 user defined partitioning 3 11 routability cost See porosity cost RTL reading 2 21 S script files 2 16 adding comments 2 16 compile A 16 executing 2 16 generating 5 66 report A 27 A 38 return values 2 16 search path for libraries 4 10 search_path variable 4 10 semiconductor vendor selecting 4 2 sequential device initialize or control state 3 16 set_clock_latency command setting margin of error 7 13 set_clock_uncertainty command 7 10 set_cost_priority command 8 32 set_critical_range command 8 49 set_disable_timing command 9 13 set_dont_touch command 8 25 8 28 set_drive command 6 14 6 15 6 16 set_driving_cell command 6 13 6 14 6 16 set_f
80. 6 high speed designs 8 43 how it works 9 3 incremental 8 55 invoking 8 40 logic level 8 3 maximum performance 8 47 minimum area 8 56 random logic 8 41 structured logic 8 43 trials phase 9 3 optimization processes 8 2 output delay default constraint 7 14 removing 7 14 reporting 7 14 specifying 7 14 output formats supported 5 53 P partitioning by compile technique 3 9 combinational logic 3 5 design reuse considerations 3 5 glue logic 3 6 merge resources 3 10 modules by design goals 3 8 modules with different goals 3 8 random logic 3 9 sharable resources 3 10 structural logic 3 9 user defined resources 3 11 path delay specifying 7 19 path groups and delay cost 8 36 creating 8 35 defined 8 35 listing 8 35 paths multicycle 7 22 specifying false 7 11 using absolute 5 27 using relative 5 25 pin attributes C 6 pins 5 6 library cell specifying 4 12 relationship to ports 5 6 point to point exception See timing exception porosity cost calculating 8 39 port names changing 5 57 ports 5 5 capacitive load on setting 6 17 creating 5 45 5 47 deleting 5 47 listing output ports 5 24 relationship to pins 5 6 reporting 5 24 setting drive characteristics of 6 14 6 15 wire delays preventing 9 15 Power Compiler defined 1 7 preserved timing constraints in design hierarchies 5 46 preserving subdesigns 8 28 Q quit command 2 13 quitting Design Compiler 2 12 R random logic optimization 8 41 read_db command 5 15
81. By default Design Compiler works only on the worst violator in each group Set the path group priorities by assigning weights to each group the default weight is 1 0 The weight can be from 0 0 to 100 0 For example Figure 8 7 shows a design that has multiple paths to flip flop FF 1 Figure 8 7 Path Group Example WV To indicate that the path from input in3 to FF1 is the highest priority path use the following command to create a high priority path group dc_shell xg t gt group path name group3 from in3 to FF1 D weight 2 5 Chapter 8 Optimizing the Design 8 48 Optimizing Near Critical Paths When you add a critical range to a path group you change the maximum delay cost function from worst negative slack to critical negative slack Design Compiler optimizes all paths within the critical range Specifying a critical range can increase runtime To limit the runtime increase use critical range only during the final implementation phase of the design and use a reasonable critical range value A guideline for the maximum critical range value is 10 percent of the clock period Use one of the following methods to specify the critical range e Use the critical_range option of the group path command e Use the set critical range command For example Figure 8 8 shows a design with three outputs A B and C Figure 8 8 Critical Range Example Path A 13ns lt Worst violator CA B 12 ns in2
82. Design Compiler User Guide Version X 2005 09 September 2005 Comments Send comments on the documentation by going to http solvnet synopsys com then clicking Enter a Call to the Support Center SYNOPSYS Copyright Notice and Proprietary Information Copyright 2005 Synopsys Inc All rights reserved This software and documentation contain confidential and proprietary information that is the property of Synopsys Inc The software and documentation are furnished under a license agreement and may be used or copied only in accordance with the terms of the license agreement No part of the software and documentation may be reproduced transmitted or translated in any form or by any means electronic mechanical manual optical or otherwise without prior written permission of Synopsys Inc or as expressly provided by the license agreement Right to Copy Documentation The license agreement with Synopsys permits licensee to make copies of the documentation for its internal use only Each copy shall include all copyrights trademarks service marks and proprietary rights notices if any Licensee must assign sequential numbers to all copies These copies shall contain the following legend on the cover page This document is duplicated with the permission of Synopsys Inc for the exclusive use of and its employees This is copy number Destination Control Statement All technical data contained in this publication i
83. KKKKKKKKKKKKKKEKEXEXEKX KK Report library Library my lib Version 1999 05 Date Mon Jan 4 10 56 49 1999 KAAKKKKKKKKKKKKKKKKKKKKKKKKKAKKKAKAKAKAKAKKKKK Library Type Technology Tool Created 1999 05 Date Created February 7 1992 Library Version 1 800000 Time Unit Ins Capacitive Load Unit 0 100000ff Pulling Resistance Unit 1kilo ohm Voltage Unit 1V Current Unit luA Defining Fanout Loads on Output Ports You can model the external fanout effects by specifying the expected fanout load values on output ports with the set_fanout_load command For example enter dc_shell xg t gt set fanout load 4 out1 Design Compiler tries to ensure that the sum of the fanout load on the output port plus the fanout load of cells connected to the output port driver is less than the maximum fanout limit of the library library cell and design For more information about maximum fanout limits see Setting Design Rule Constraints on page 7 3 Chapter 6 Defining the Design Environment 6 18 Fanout load is not the same as load Fanout load is a unitless value that represents a numerical contribution to the total fanout Loadis a capacitance value Design Compiler uses fanout load primarily to measure the fanout presented by each input pin An input pin normally has a fanout load of 1 but it can have a higher value Modeling the System Interface 6 19 Chapter 6 Defining the Design Environment 6 20 Def
84. KKXEXX XXE Design is dont_touched To remove the dont_touch attribute use the remove_attribute command or the set dont touch command set to false Chapter 8 Optimizing the Design 8 30 Understanding the Compile Cost Function The compile cost function consists of design rule costs and optimization costs By default Design Compiler prioritizes costs in the following order 1 Design rule costs a Connection class b Multiple port nets c Maximum transition time d Maximum fanout e Maximum capacitance f Cell degradation 2 Optimization costs a Maximum delay b Minimum delay c Maximum power d Maximum area e Minimum porosity The compile cost function considers only those components that are active in your design Design Compiler evaluates each cost function component independently in order of importance When evaluating cost function components Design Compiler considers only violators positive difference between actual value and constraint and works to reduce the cost function to zero Understanding the Compile Cost Function 8 31 The goal of Design Compiler is to meet all constraints However by default it gives precedence to design rule constraints because design rule constraints are functional requirements for designs Using the default priority Design Compiler fixes design rule violations even at the expense of violating your delay or area constraints You can change the priority of the maximum de
85. REG Y IN R 7 STACKIN Y IN F UPCOUT Y IN UPC endcase end endmodule Appendix A Design Example A 10 Example A 11 PathSegment v module PathSegment R1 R2 R3 R4 S2 S1 OP REGOUT clk Example for path segmentation input 15 0 R1 R2 R3 R4 input S2 S1 clk input OP output 15 0 REGOUT reg 15 0 ADATA BDATA reg 15 0 REGOUT reg MODE wire 15 0 product always posedge clk begin selector_block case S1 1 b0 ADATA lt R1 1 b1 ADATA lt R2 default ADATA lt 16 bx endcase case S2 1 b0 BDATA lt R3 1 b1 BDATA lt R4 default ADATA lt 16 bx endcase end Only Lower Byte gets multiplied instantiate DW02 mult DWO2_mult 8 8 U100 A ADATA 7 0 B BDATA 7 0 TC 1 b0 PRODUCT product always posedge clk begin alu_block case OP 1 b0 begin REGOUT lt ADATA BDATA end 1 b1 begin REGOUT lt product end default REGOUT lt 16 bx endcase end endmodule Design Description A 11 Setup File When running the design example copy the project specific setup file in Example A 12 to your project working directory This setup file is written in the Tcl subset and can be used in both dctcl and desh command languages For more information about the Tcl subset see Using Tcl With Synopsys Tools and the Design Compil
86. able 8 9 illustrates the greater datapath extraction capabilities of DC Ultra datapath optimization The dashed line circles those operators that are extracted Table 8 9 DC Ultra Datapath Extraction Supports Bit Truncation DC Expert DC Ultra datapath optimization a 63 0 b 63 0 re veo bas XI 8 C c 63 0 fs el Pa N Sw ae a 63 0 CPA lt a 7 f CPAN Sue y d 127 64 ba Y N paisa aed K p CPN A N lt CPA Pa el63 0 aa alpa Using DC Expert no Using DC Ultra datapath datapath block is extracted optimization the extracted datapath includes the second adder QOR timing 21 4 QOR area 304746 42 timing 4 46 area 274332 44 When DC Ultra datapath optimization is used to compile design dp in Example 8 7 on page 8 65 the following improvements are realized e 350 percent timing improvement compared to DC Expert results for Example 8 7 Chapter 8 Optimizing the Design 8 66 e 10 percent area improvement compared to DC Expert results for Example 8 7 Two Different Datapath Optimization Methods To understand and contrast the two methods for handling datapaths consider the datapath example defined by the code in Example 8 8 Example 8 8 Design datapath module datapathil clk cond a b c d e z_out input clk input cond input 3 0 a b c d input 7 0 e output 7 0 z_out reg 7 0 z mult z_out always if cond begin mult a b end else begin mult c d
87. acterize the subdesign s instance that has the worst case environment 2 Compile the referenced subdesign 3 Use the set_dont_touch command to set the dont_touch attribute on all instances that reference the compiled subdesign 4 Compile the entire design For example the following command sequence resolves the multiple instances of design C in design TOP by using the compile once don t touch method assuming U2 U3 has the worst case environment In this case no copies of the original subdesign are loaded into memory Resolving Multiple Instances of a Design Reference 8 25 dc_shel dc_shel dc_shel dc_shel dc_shel dc_shel dc_shell 1 xg 1 xg 1 xg 1 xg 1 xg 1 xg xg t gt t gt t gt t gt t gt t gt t gt current design top characterize U2 U3 current design C compile current design top set dont touch U2 U3 U2 U4 compile Figure 8 5 shows the result of running this command sequence The X drawn over the C design which has already been compiled indicates that the dont touch attribute has been set This design is not modified when the top level design is compiled Figure 8 5 8 Compile Once Don t Touch Results TOP U2 Top level Design U1 With Instances B A No U3 U4 U5 D if 7 7 P 7 3 Pag Her Le 127 _ Design Compiler Memory A D Loaded Designs The compile once don t touch method has the foll
88. adable do not use nested define statements e Do not use define inside module definitions When you use a define statement inside a module definition the local macro and the global macro have the same reference name but different values Use parameters to define local constants HDL Coding for Synthesis 3 27 Using VHDL Port Definitions When defining ports in VHDL source code observe these guidelines Use the STD LOGIC and STD LOGIC VECTOR packages By using STD LOGIC you avoid the need for type conversion functions on the synthesized design Do not use the buffer port mode When you declare a port as a buffer the port must be used as a buffer throughout the hierarchy To simplify synthesis declare the port as an output then define an internal signal that drives the output port Writing Effective Code This section provides guidelines for writing efficient readable HDL source code for synthesis The guidelines cover Identifiers Expressions Functions Modules Guidelines for Identifiers A good identifier name conveys the meaning of the signal the value of a variable or the function of a module without this information the hardware descriptions are difficult to read Chapter 3 Preparing Design Files for Synthesis 3 28 Observe the following naming guidelines to improve the readability of your HDL source code Ensure that the signal name conveys the meaning of the signal or the value of a variable
89. ainty commands to specify timing information about the clock network delay You can use these commands to specify either estimated or actual delay information Use the set_propagated_clock command to specify that you want the clock latency to propagate through the clock network For example dc_shell xg t gt set_propagated_clock clk Use the setup or hold options of the set_clock_uncertainty command to add some margin of error into the system to account for variances in the clock network resulting from layout For example on the 20 megahertz clock mentioned previously to add a 0 2 margin on each side of the clock edge enter Setting Optimization Constraints 7 13 dc_shell xg t gt set_clock_uncertainty setup 0 2 clk dc_shell xg t gt set_clock_uncertainty hold 0 2 clk Use the skew option of the report_clock command to show clock network skew information Design Compiler uses the clock information when determining whether a path meets setup and hold requirements Specifying I O Timing Requirements If you do not assign timing requirements to an input port Design Compiler responds as if the signal arrives at the input port at time 0 In most cases input signals arrive at staggered times Use the set input delay command to define the arrival times for input ports You define the input delay constraint relative to the system clock and to the other inputs If you do not assign timing requirements to an output port Design Comp
90. al instance of the current design The current instance defines the active instance for these instance specific commands In Figure 5 1 the instances are U1 U2 U3 and U4 Ports Ports are the inputs and outputs of a design The port direction is designated as input output or inout Design Terminology 5 5 Pins Pins are the input and output of cells such as gates and flip flops within a design The ports of a subdesign are pins within the parent design Nets Nets are the wires that connect ports to pins and pins to each other Relationship Between Designs Instances and References Figure 5 2 shows the relationships among designs instances and references Figure 5 2 Instances and References ee de Designs loaded in memory references The EXREF design contains two references NAND2 and MULTIPLIER NAND2 is instantiated three times and MULTIPLIER is instantiated once The names given to the three instances of NAND2 are U1 U2 and U3 The references of NAND2 and MULTIPLIER in the EXREF design are independent of the same references in different designs Chapter 5 Working With Designs in Memory 5 6 For information about resolving references see Linking Designs on page 5 19 Using Reference Objects When you use the get_references command Design Compiler returns a collection of instances that have the specified reference and you operate on the instances For example the followi
91. alse_path command 7 18 undoing 7 19 uses for 7 18 set_fanout_load command 6 18 7 7 set_flatten command 8 4 minimize option 8 42 phase option 8 42 set_input_delay command 7 11 7 14 set_input_transition command 6 14 set_load command 6 17 set_max_area command 7 26 set_max_delay command for combinational paths 7 16 for timing exceptions 7 19 reset 7 19 set_max_fanout command 7 7 set_max_transition command 7 4 set_min_delay command for combinational paths 7 16 for timing exceptions 7 19 reset 7 19 set_multicycle_path command 7 22 default behavior 7 22 reset 7 24 set_output delay command 7 11 7 14 set resistance command 9 15 set_structure command 8 3 8 57 set_ultra optimization command 8 76 set_ungroup command 5 39 8 60 set_wire load command 6 7 6 12 setup checks default behavior 7 22 overriding default behavior 7 22 7 23 timing arcs and 6 17 setup files design example A 12 synopsys dc setup file 2 9 sh command log file variable 2 15 signal type attribute 9 13 signals edge detection 3 16 slack critical negative 8 36 total negative 8 36 worst negative 8 34 specifying clock network delay 7 13 period 7 11 waveform 7 11 libraries DesignWare 4 10 link 4 6 symbol 4 6 target 4 6 library objects 4 12 maximum transition time 7 4 timing exceptions false path 7 18 multicycle path 7 22 path delay 7 19 timing requirements IN 15 combinational paths 7 16 input ports 7 14 output ports 7 14 wire load mode 6 1
92. anout 3 50 Slack 0 50 VIOLATED Net IN max fanout 0 75 Fanout 1 00 Slack 0 25 VIOLATED This design now contains three violations e Maximum transition time violation at OUT Actual transition time is 4 00 0 75 3 00 which is greater than the maximum transition time of 2 50 e Maximum fanout load violation at OUT Actual fanout load is 3 5 which is greater than the maximum fanout load of 3 00 Chapter 9 Analyzing and Resolving Design Problems 9 20 e Maximum fanout load violation at IN Actual fanout load is 1 00 which is greater than the maximum fanout load of 0 75 There is no max_transition violation at IN even though the transition time on this net is 2 5 1 5 3 75 which is well above the max_transition requirement of 2 50 Design Compiler does not recognize this as a violation because the requirement of 2 50 is a design rule from the output pin of cell IV1 This requirement applies only to a net driven by this pin The IV1 output pin does not drive the net connected to port IN so the max_transition constraint does not apply to this net If you want to constrain the net attached to port IN to a maximum transition time of 2 50 enter one of the following commands depending on your command language dc_shell xg t gt set max transition 2 5 get ports IN dc shell set max transition 2 5 find port IN Thiscommand causes report constraint verbose all violators to add the following lines to the report
93. arguments and options to the ungroup command To do this Use this Specify a list of cells to be ungrouped Provide a list of cells as an argument to the ungroup When the parent design is unique the list can command include cells from a lower level in the hierarchy that is the ungroup command can accept instance objects Note In DB mode the ungroup command cannot accept instance objects Ungroup all cells in the current design or all current instance Ungroup each cell recursively until all levels of flatten hierarchy within the current design instance are removed Chapter 5 Working With Designs in Memory 5 36 To do this Use this Ungroup cells recursively starting at any start level number hierarchical level below the current design You must specify a number for this option 1 2 3 and so on A value of 1 indicates that cells from the current design are to be ungrouped The cells that are at the level specified by the start level option are included in the ungrouping Additionally when you use this option the ungroup command cannot accept instance objects Specify the prefix to use in naming ungrouped prefix prefix_name cells If you do not specify a prefix Design Compiler uses the prefix cell to be ungrouped old cell name number Ungroup subdesigns with fewer leaf cells than small number a specified number Note If you ungroup cells and then use the change names co
94. ariable simply to resolve multiple design references in a netlist The following command sequence resolves the multiple instances of design C in design TOP shown in Figure 8 3 on page 8 21 it uses the automatic uniquify method to create new designs C_0 and C_1 by copying design C and then replaces design C with the two copies in memory dc_shell xg t gt current_design top dc_shell xg t gt compile Figure 8 4 shows the result of running this command sequence Figure 8 4 Uniquify Results TOP U2 Top level Design U1 With Instances B A A U3 U4 U5 C 0 C_1 D Design Compiler Memory A c_o Ci D Loaded Designs Chapter 8 Optimizing the Design 8 24 Compared with the compile once don t touch method the uniquify method has the following characteristics e Requires more memory e Takes longer to compile Compile Once Don t Touch Method If the environments around the instances of a multiply referenced design are sufficiently similar use the compile once don t touch method In this method you compile the design using the environment of one of its instances and then you use the set_dont_touch command to preserve the subdesign during the remaining optimization For details about the set_dont_touch command see Preserving Subdesigns on page 8 28 To use the compile once don t touch method to resolve multiple instances follow these steps 1 Char
95. ass IV Removing Libraries From Memory The remove design command removes libraries from dc shell memory If you have multiple libraries with the same name loaded into memory you must specify the path as well as the library name Use the list 1ibs command to see the path for each library in memory Saving Libraries The write_lib command saves writes to disk a compiled library in Synopsys database EDIF or VHDL format Chapter 4 Working With Libraries 4 16 Working With Designs in Memory Design Compiler reads designs into memory from design files Many designs can be in memory at any time After a design is read in you can change it in numerous ways such as grouping or ungrouping its subdesigns or changing subdesign references This chapter contains the following sections e Design Terminology e Design Database Formats e Reading Designs e Listing Designs in Memory e Setting the Current Design e Linking Designs e Listing Design Objects 5 1 Specifying Design Objects Creating Designs Copying Designs Renaming Designs Changing the Design Hierarchy Editing Designs Translating Designs From One Technology to Another Removing Designs From Memory Saving Designs Working With Attributes Chapter 5 Working With Designs in Memory 5 2 Design Terminology Different companies use different terminology for designs and their components This section describes the terminology used in the Synopsys synthesis too
96. assignment does not include an else clause Design Compiler creates a latch The following examples show if statements that generate latches during synthesis Example 3 5 Incorrect if Statement Verilog if a 1 amp amp b 1 AO KG HDL Coding for Synthesis 3 23 Example 3 6 Incorrect if Statement VHDL if a 1 and b 1l then Tes Te end if case Statements If your if statement contains more than three conditions consider using the case statement to improve the parallelism of your design and the clarity of your code The following examples use the case statement to implement a 3 bit decoder Example 3 7 Using the case Statement Verilog case fa b c 3 b000 z 8 b00000001 3 b001 z 8 b00000010 3 b010 z 8 b00000100 3 b011 z 8 b00001000 3 b100 z 8 b00010000 3 b101 z 8 b00100000 3 b110 z 8 b01000000 3 b111 z 8 b10000000 default z 8 b00000000 endcase Chapter 3 Preparing Design Files for Synthesis 3 24 Example 3 8 Using the case Statement VHDL case value as b amp c CASE case value IS WHEN 000 gt z lt 00000001 WHEN 001 gt z lt 00000010 WHEN 010 gt z lt 00000100 WHEN 011 gt z lt 00001000 WHEN 100 gt z lt 00010000 WHEN 101 gt z lt 00100000 WHEN 110 gt z lt 01000000 WHEN 111 gt z lt 10000000 WHEN OTHERS gt z lt 00
97. at source Clock trees also known as clock networks are synthesized by vendors based on the physical placement data at registers in one clock domain or between clock domains clock uncertainty See clock skew core A predesigned block of logic employed as a building block for ASIC designs critical path The path through a circuit with the longest delay The speed of a circuit depends on the slowest register to register delay The clock period cannot be shorter than this delay or the signal will not reach the next register in time to be clocked datapath A logic circuit in which data signals are manipulated using arithmetic operators such as adders multipliers shifters and comparators current design The active design the design being worked on Most commands are specific to the current design that is they operate within the context of the current design You specify the current design with the current_design command current instance The instance in a design hierarchy on which instance specific commands operate by default You specify the current instance with the current_instance command GL 3 GL 4 design constraints The designers specification of design performance goals that is the timing and environmental restrictions under which synthesis is to be performed Design Compiler uses these constraints for example low power small area high speed or minimal cost to direct the optimization of a design to
98. ated especially setting the timing exceptions and includes the following tasks e Defining a Clock e Specifying I O Timing Requirements e Specifying Combinational Path Delay Requirements e Specifying Timing Exceptions Chapter 7 Defining Design Constraints 7 2 Setting Design Rule Constraints This section discusses the most commonly specified design rule constraints e Transition time e Fanout load e Capacitance Design Compiler also supports cell degradation and connection class constraints For information about these constraints see the Design Compiler Reference Manual Constraints and Timing Design Compiler uses attributes assigned to the design s objects to represent design rule constraints Table 7 1 provides the attribute name that corresponds to each design rule constraint Table 7 1 Design Rule Attributes Design rule constraint Attribute name Transition time max_transition Fanout load max_fanout Capacitance max_capacitance min_capacitance Cell degradation cell degradation Connection class connection_class Design rule constraints are attributes specified in the technology library and optionally specified by you explicitly Setting Design Rule Constraints 7 3 If a technology library defines these attributes Design Compiler implicitly applies them to any design using that library when it compiles the design or creates a constraint report You cannot remove the design rule attributes defined in th
99. block easily because e The drive strength on the inputs to an individual block always equals the drive strength of the average input drive Partitioning for Synthesis 3 7 e The input delays from the previous block always equal the path delay through the flip flop Because no combinational only paths exist when all outputs are registered time budgeting the design and using the set_output_delay command are easier Given that one clock cycle occurs within each module the constraints are simple and identical for each module This partitioning method can improve simulation performance With all outputs registered a module can be described with only edge triggered processes The sensitivity list contains only the clock and perhaps a reset pin A limited sensitivity list soeeds simulation by having the process triggered only once in each clock cycle Partitioning by Design Goal Partition logic with different design goals into separate blocks Use this method when certain parts of a design are more area and timing critical than other parts To achieve the best synthesis results isolate the noncritical speed constraint logic from the critical speed constraint logic By isolating the noncritical logic you can apply different constraints such as a maximum area constraint on the block Figure 3 6 shows how to separate logic with different design goals Chapter 3 Preparing Design Files for Synthesis 3 8 Figure 3 6 Blocks With Dif
100. cal 9 12 is unmapped 9 11 library C 5 library cell C 5 max area 7 26 max capacitance 7 8 9 25 max fanout 7 5 9 25 max transition 7 4 9 25 net C 5 pin C 6 reference C 6 signal type 9 13 auto ungroup preserve constraints variable 5 43 8 47 auto wire load selection attribute 6 12 automatic ungrouping 5 40 using compile 5 40 using compile ultra 8 45 IN 1 B balance buffer command 8 51 Boolean optimization defined 8 57 enabling 8 57 bottom up compile 8 12 advantages 8 12 directory structure figure 3 4 disadvantages 8 12 process 8 13 when to use 8 12 boundary optimization 8 59 breaking feedback loop 9 15 buffers extra 9 25 guidelines for working with 9 22 hanging 9 26 insertion process 9 16 interblock 9 14 missing 9 22 buses creating 5 47 deleting 5 47 C capacitance calculating 7 8 checking 9 24 controlling 7 8 cost calculation 8 33 removing attribute 7 9 capacitive load setting 6 17 case sensitive setting 5 20 case statement 3 24 latch inference 3 25 multiplexer inference 3 15 cell count based auto ungrouping 5 41 IN 2 cell degradation cost 8 34 cell delays finding source of 9 9 cell degradation attribute 7 3 cells black box identifying 9 12 creating 5 47 deleting 5 47 grouping from different subdesigns 5 46 from same subdesign 5 32 hierarchical defined 5 5 identifying 9 12 leaf 5 5 library specifying 4 12 listing 5 24 merging hierarchy 5 46 reporting
101. cal negative slack method the equation for the maximum delay cost is Sd i 1 j 1 mis the number of path groups nis the number of paths in the critical range in the path group vis a violator within the critical range of the ith path group w is the weight assigned to the ith path group Design Compiler calculates the maximum delay violation for each path within the critical range as max 0 actual path delay max delay Calculating Minimum Delay Cost The equation for the minimum delay cost is mis the number of paths affected by set min delay or set_fix_hold v is the ith minimum delay violation Understanding the Compile Cost Function 8 37 Design Compiler calculates the minimum delay violation for each path as max 0 min delay actual path delay The minimum delay cost for a design differs from the maximum delay cost Path groups do not affect the minimum delay cost In addition all violators not just the most critical path contribute to the minimum delay cost Calculating Maximum Power Cost Design Compiler computes the maximum power cost only if you have a Power Optimization license and your technology library is characterized for power The maximum power cost has two components e Maximum dynamic power Design Compiler calculates the maximum dynamic power cost as max 0 actual power max dynamic power e Maximum leakage power Design Compiler calculates the maximum leakage power cost as
102. can pins for cell get object name Sseq cel1 echo scan input get object name Ssi echo scan output get object name get pins Sseq ping N filter signal type test scan out Insulating Interblock Loading Design Compiler determines load distribution in the driving block If a single output port drives many blocks a huge incremental cell delay can result To insulate the interblock loading fan the heavily loaded net to multiple output ports in the driving block Evenly divide the total load among these output ports Preserving Dangling Logic By default Design Compiler optimizes away dangling logic Use one of the following methods to preserve dangling logic for example spare cells during optimization e Place the dont touch attribute on the dangling logic e Connect the dangling logic to a dummy port Chapter 9 Analyzing and Resolving Design Problems 9 14 Preventing Wire Delays on Ports If your design contains unwanted wire delays between ports and I O cells you can remove these wire delays by specifying zero resistance infinite drive strength on the net Use the set_resistance command to specify the net resistance For example enter one of the following commands depending on your command language dc_shell xg t gt set_resistance 0 get_ nets wire 104 dc_shell gt set resistance 0 find net wire ic4 Breaking a Feedback Loop Follow these steps to break a feedback loop in your design
103. ce value 1 bz in Verilog Z in VHDL to the output pin to have Design Compiler infer three state gates Three state logic reduces the testability of the design and makes debugging difficult Where possible replace three state buffers with a multiplexer Never use high impedance values in a conditional expression HDL Compiler always evaluates expressions compared to high impedance values as false which can cause the gate level implementation to behave differently from the RTL description For additional information about three state inference see the HDL Compiler documentation Inferring Multibit Components Multibit inference allows you to map multiplexers registers and three state drivers to regularly structured logic or multibit library cells Using multibit components can have the following results e Smaller area and delay due to shared transistors and optimized transistor level layout e Reduced clock skew in sequential gates e Lower power consumption by the clock in sequential banked components e Improved regular layout of the data path HDL Coding for Synthesis 3 17 Multibit components might not be efficient in the following instances e As state machine registers e n small bused logic that would benefit from single bit design You must weigh the benefits of multibit components against the loss of optimization flexibility when deciding whether to map to multibit or single bit components Attach the infer_mu
104. ces U1 U2 U2 U3 U2 U4 U2 U5 characterize constraint all_instances save characterize information foreach block all_blocks current_design Sblock set char block script sblock wscr write script gt Schar block script recompile each block Chapter 8 Optimizing the Design 8 18 foreach block Sall blocks clear memory remove_design all read in previously characterized subblock set block_source Sblock v read file format verilog Sblock source recompile subblock current design Sblock link apply global attributes and constraints source defaults con apply characterization constraints set char block script sblock wscr source Schar block script apply block attributes and constraints set block script Sblock con source Sblock script recompile the block compile Note When performing a bottom up compile if the top level design contains glue logic as well as the subblocks subdesigns you must also compile the top level design In this case to prevent Design Compiler from recompiling the subblocks you first apply the set dont touch command to each subdesign Mixed Compile Strategy You can take advantage of the benefits of both the top down and the bottom up compile strategies by using both e Use the top down compile strategy for small hierarchies of blocks Selecting and Using a Compile Strategy 8 19 e Use the bottom up compile strategy to tie small hierarchies together
105. command Use this command to set any design in dc shell memory as the current design dc_shell xg t gt current design ANY DESIGN Current design is ANY DESIGN ANY DESIGN To display the name of the current design enter one of the following commands depending on your command language dc_shell xg t gt printvar current design current design test Setting the Current Design 5 17 dc_shell gt list current design current design usr home designs my design db my design 1 Using the current design Command In XG mode it is recommended that you avoid writing scripts that use a large number of current design commands such asin a loop Using a large number of current design commands can increase runtime For more information see the Design Compiler Command Line Interface Guide Chapter 5 Additionally in XG mode several commands are enhanced to accept instance objects that is cells at a lower level of hierarchy You can operate on hierarchical designs from any level in the design without using the current design command The enhanced commands are listed below e Netlist editing commands For more information see Editing Designs on page 5 47 e The ungroup group and uniquify commands For more information see Removing Levels of Hierarchy on page 5 35 and Uniquify Method on page 8 22 e Theset size only command For more information see the Design Compiler Reference Manual Optimizati
106. connect net 5 47 elaborate 2 21 5 10 5 14 exit 2 13 filter 9 11 9 12 find 9 12 get attribute 5 65 9 23 9 25 get cells 9 11 9 12 get designs 9 12 get license 2 17 get references 5 7 group 5 32 8 52 group path 8 35 8 48 license users 2 17 list 6 12 list designs 5 16 list duplicate designs 5 16 list instances 5 24 list libs 4 11 6 9 load of 9 24 quit 2 13 read db 5 15 read ddc 5 15 read file 2 21 4 11 5 10 5 14 5 17 read lib 4 11 read milkyway 5 14 read verilog 2 21 read vhdl 2 21 remove attribute 7 5 7 8 7 9 remove bus 5 47 remove cell 5 47 remove clock 7 13 remove constraint 7 27 remove design 4 16 5 52 remove input delay 7 14 remove license 2 17 IN 3 remove multibit 3 18 remove net 5 47 remove output delay 7 14 remove port 5 47 remove wire load model 6 13 rename design 5 30 report attribute 5 65 report auto ungroup 5 41 report cell 9 25 report clock 5 25 7 13 report compile options 8 5 report constraint 9 16 report delay calculation 9 9 report design 6 5 8 30 report hierarchy 5 31 report lib 6 4 6 9 6 17 report net 5 25 report path group 8 35 report port 5 24 7 14 report reference 5 24 report resources 8 73 report timing 6 13 9 15 report timing requirements 7 17 7 18 reset path 7 19 7 24 set clock uncertainty 7 10 set cost priority 8 32 set critical range 8 49 set disable timing 9 13 set dont touch 8 25 8 28 set drive 6 14 6 15 6 16 set driving cell
107. connections in a design Netlist transfer is the most common way of moving design information from one design system or tool to another operating conditions The process voltage and temperature ranges a design encounters Design Compiler optimizes your design according to an operating point on the process voltage and temperature curves and scales cell and wire delays according to your operating conditions By default operating conditions are specfied in a technology library in an operating conditions group optimization The step in the logic synthesis process in which Design Compiler attempts to implement a combination of technology library cells that best meets the functional timing and area requirements of the design output delay A constraint that specifies the minimum or maximum amount of delay from an output port to the sequential element that captures data from the output port This constraint establishes the times at which signals must be available at the output port to meet the setup and hold requirements of the sequential element You use the set_output_delay command to set the output delay on a pin or output port relative to a specified clock signal pad cell A special cell at the chip boundaries that allows connection or communication with integrated circuits outside the chip path group A group of related paths grouped either implicitly by the create_clock command or explicitly by the group_path command By de
108. d of get_pins library cell pin dc_shell gt load of find pin library cell pin Incorrect Assumptions About Constraint Behavior Check to make sure you are not overlooking one of the following aspects of constraint behavior e Acommon mistake is the assumption that the default_max_transition or the default_max_fanout constraint in the technology library applies to input ports These constraints apply only to the output pins of cells within the library e Maximum transition time takes precedence over maximum fanout load within Design Compiler Therefore a maximum fanout violation might not be corrected if the correction affects the maximum transition time of a net e Design Compiler might have removed a violation by sizing gates or modifying the structure of the design Generate a constraint report after optimization to verify that the violation still exists e Design Compiler cannot correct violations if dont touch attributes exist on the violating path You might have inadvertently placed dont_touch attributes on a design or cell reference within the hierarchy If so Design Compiler reports violations but cannot correct them during optimization Chapter 9 Analyzing and Resolving Design Problems 9 24 Use the report _ cell command and the get attribute command to see whether these attributes exist Design Compiler cannot correct violations if dont_touch_network attributes exist on the violating path If you have set the
109. dditionally you can use the all_instances option to make link changes for a leaf cell when its parent design is instantiated multiple times The link change is applied on leaf cells for all instances of the parent design Therefore you can make link changes for such cells without using the current_design command Example 1 The following command shows how cells U1 and U2 are linked from the current design to MY_ADDER dc_shell xg t gt copy design ADDER MY ADDER dc_shell xg t gt change_link U1 U2 MY_ADDER Chapter 5 Working With Designs in Memory 5 22 Example 2 The following command changes the link for cell U1 which is at a lower level in the hierarchy dc_shell xg t gt change_link top sub_inst U1 1si_10k AN3 Note In DB mode you would enter the following set of commands to achieve the same result dc_shell gt current design sub dc_shell gt change link get cells U1 1si 10k AN3 dc shell current design top Example 3 This example shows how you can use the a11 instances option to change the link for leaf cell inv1 when its parent design bot is instantiated multiple times The design bot is instantiated twice mid1 bot1 and mid1 bot2 dc_shell xg t gt change link all instances mid1 bot1 invi lsi 10k AN3 Information Changed link for all instances of cell invl in subdesign bot UID 193 dc_shell xg t gt get cells hierarchical filter ref name AN3 midi bot1 invi midi bot
110. define statement and a local parameter Example 3 10 shows a VHDL code fragment that includes a global constant and a local generic Example 3 9 Using Macros and Parameters Verilog Define global constant in def_macro v define WIDTH 128 Use global constant in reg128 v reg regfile WIDTH 1 0 Define and use local constant in module foo module foo a b c parameter WIDTH 128 input WIDTH 1 0 a b output WIDTH 1 0 c Chapter 3 Preparing Design Files for Synthesis 3 26 Example 3 10 Using Global Constants and Generics VHDL Define global constant in synthesis def vhd constant WIDTH INTEGER 128 Include global constants library my lib USE my lib synthesis def al11 Use global constant in entity foo entity fool is port a b in std logic vector WIDTH 1 downto 0 c out std logic vector WIDTH 1 downto 0 end foo Define and use local constant in entity foo entity foo is generic WIDTH VAR INTEGER 128 port a b in std logic vector WIDTH 1 downto 0 c out std logic vector WIDTH 1 downto 0 end foo Using Verilog Macro Definitions In Verilog macros are implemented using the define statement Follow these guidelines for define statements e Use define statements only to declare constants e Keep define statements in a separate file e Do not use nested define statements Reading a macro that is nested more than twice is difficult To make your code re
111. dels 6 7 the design containing the segment If the design contains a segment that has no wire load model the tool traverses the design hierarchy upward until it finds a wire load model Use segmented mode if the wire load models in your technology have been characterized with net segments Figure 6 2 shows a sample design with a cross hierarchy net cross_net The top level of the hierarchy design TOP has a wire load model of 50x50 The next level of hierarchy design MID has a wire load model of 40x40 The leaf level designs A and B have wire load models of 20x20 and 30x30 respectively Figure 6 2 Comparison of Wire Load Mode mode top TOP X mode enclosed la mode segmented 40X40 20X20 40X40 30X30 In top mode Design Compiler estimates the wire length of net cross net using the 50x50 wire load model Design Compiler ignores the wire load models on designs MID A and B Chapter 6 Defining the Design Environment 6 8 In enclosed mode Design Compiler estimates the wire length of net cross_net using the 40x40 wire load model the net cross_net is completely enclosed by design MID In segmented mode Design Compiler uses the 20x20 wire load model for the net segment enclosed in design A the 30x30 wire load model for the net segment enclosed in design B and the 40x40 wire load model for the segment enclosed in design MID Determining Available Wire Load Models Most technology libraries have
112. design adder To undo a set max transition command use the remove attribute command For example enter one of the following commands depending on your command language dc_shell xg t gt remove attribute get designs adder max transition dc shell remove attribute find design adder max transition Setting Fanout Load Constraints The maximum fanout load for a net is the maximum number of loads the net can drive Design Compiler and Library Compiler model fanout restrictions by associating a fanout load attribute with each input pin and a max fanout attribute with each output driving pin on a cell The fanout load value does not represent capacitance it represents the weighted numerical contribution to the total fanout load The fanout load imposed by an input pin is not necessarily 1 0 Library developers can assign higher fanout load values to model internal cell fanout effects Setting Design Rule Constraints 7 5 Design Compiler calculates the fanout of a driving pin by adding the fanout_load values of all inputs driven by that pin To determine whether the pin meets the maximum fanout load restriction Design Compiler compares the calculated fanout load value with the pin s max_fanout value Figure 7 1 shows a small circuit in which pin X drives two loads pin A and pin B If pin A has a fanout_load value of 1 0 and pin B has a fanout_load value of 2 0 the total fanout load of pin X is 3 0 If pin X has a max
113. design constraints For information about how Design Compiler maps MUX_OPs to multiplexers see the Design Compiler Reference Manual Optimization and Timing Analysis Use the infer_mux compiler directive to control multiplexer inference When attached to a block the infer mux directive forces multiplexer inference for all case statements in the block When attached to a case statement the infer_mux directive forces multiplexer inference for that specific case statement Inferring Registers Register inference allows you to specify technology independent sequential logic in your designs A register is a simple 1 bit memory device either a latch or a flip flop A latch is a level sensitive memory device A flip flop is an edge triggered memory device HDL Compiler infers a D latch whenever you do not specify the resulting value for an output under all conditions as in an incompletely specified if or case statement HDL Compiler can also infer SR latches and master slave latches HDL Coding for Synthesis 3 15 HDL Compiler infers a D flip flop whenever the sensitivity list of a Verilog always block or VHDL process includes an edge expression a test for the rising or falling edge of a signal HDL Compiler can also infer JK flip flops and toggle flip flops Mixing Register Types For best results restrict each Verilog always block or VHDL process to a single type of register inferencing latch latch with asynchronous set or reset fli
114. design data are design data control and data organization Controlling the Design Data As new versions of your design are created you must maintain some archival and record keeping method that provides a history of the design evolution and that lets you restart the design process if data is lost Establishing controls for data creation maintenance overwriting and deletion is a fundamental design management issue Establishing file naming conventions is one of the most important rules for data creation Table 3 1 lists the recommended file name extensions for each design data type Table 3 1 File Name Extensions Design data type Extension Design source code NV vhd edif Synthesis scripts con SCr Reports and logs rpt Jog Design database ddc Description Verilog VHDL EDIF Constraints Script Report Log Synopsys internal database format 1 In DB mode db is the internal database format Chapter 3 Preparing Design Files for Synthesis 3 2 Organizing the Design Data Establishing and adhering to a method of organizing data are more important than the method you choose After you place the essential design data under a consistent set of controls you can create a meaningful data organization To simplify data exchanges and data searches designers should adhere to this data organization system You can use a hierarchical directory structure to address data organization issues Your compile strategy w
115. dmodule Example A 3 CascadeMod v module CascadeMod datal data2 s clk cin cout comp_out cnt rst start input 15 0 datal data2 output 15 0 s cnt input clk cin rst start output cout comp_out wire co Adder8 u10 ain datal 7 0 bin data2 7 0 cin cin clk clk sout s 7 0 cout co Adder8 u11 ain data1 15 8 bin data2 15 8 cin co clk clk sout s 15 8 cout cout Comparator u12 ain s bin cnt cp out comp_out Counter u13 count cnt start start clk clk rst rst endmodule Appendix A Design Example A 6 Example A 4 Adder8 v module Adder8 ain bin cin sout cout clk 8 Bit Adder Module output 7 0 sout output cout input 7 0 ain bin input cin clk wire 7 0 sout_tmp ain bin wire cout_tmp reg 7 0 sout ain_tmp bin_tmp reg cout cin_tmp always posedge clk begin cout cout_tmp sout sout_tmp ain_tmp ain bin_tmp bin cin tmp cin end assign cout tmp sout tmp ain tmp bin tmp cin tmp endmodule Design Description A 7 Example A 5 Counter v module Counter count start clk rst Counter module input clk input rst input start output 15 0 count wire clk reg 15 0 count N reg 15 0 count always posedge clk or posedge rst begin counter S if rst begin count 0 reset logic for the block end else begin count count N set specified re
116. dont touch network attribute on a port or pin in the design all elements in the transitive fanout of that port or pin inherit the attribute If this attribute is set Design Compiler reports violations but does not modify the network during optimization Use the remove_attribute command to remove this attribute from the port or net Design Compiler does not support additional buffering on three state pins For simple three state cells Design Compiler attempts to enlarge a three state cell to a stronger three state cell For complex three state cells such as sequential elements or RAM cells Design Compiler cannot build the logic necessary to duplicate the required functionality In such cases you must manually add the extra logic or rewrite the source HDL to decrease the fanout load of such nets Correcting for Extra Buffers Extremely conservative numbers for max_transition max_fanout Of max capacitance force Design Compiler to buffer nets excessively If your design has an excessive number of buffers check the accuracy of the design rule constraints applied to the design Resolving Specific Problems 9 25 If you have specified design rule constraints that are more restrictive than those specified in the technology library evaluate the necessity for these restrictive design rules You can debug this type of problem by setting the priority of the maximum delay cost function higher than the maximum design rule cost functions
117. e Design Compiler reports a design rule violation and attempts to correct the violation Understanding the Compile Cost Function 8 33 Calculating Cell Degradation Cost The cell degradation tables in the technology library provide a secondary maximum capacitance constraint based on the transition times at the cell inputs Design Compiler evaluates this cost only if you set the compile fix cell degradation variable to true If the compile fix cell degradation variable is true and the calculated capacitance is greater than the cell degradation value Design Compiler reports a design rule violation and attempts to correct the violation The maximum capacitance cost has a higher priority than the cell degradation cost Therefore Design Compiler fixes cell degradation violations only if it can do so without violating the maximum capacitance constraint Calculating Maximum Delay Cost Design Compiler supports two methods for calculating the maximum delay cost e Worst negative slack default behavior e Critical range negative slack The following sections describe these methods Worst Negative Slack Method By default Design Compiler uses the worst negative slack method to calculate the maximum delay cost With the worst negative slack method only the worst violator in each path group is considered Chapter 8 Optimizing the Design 8 34 A path group is a collection of paths that to Design Compiler represent a group in maximum
118. e The compile script for CascadeMod uses the compile once don t touch method to resolve the multiple instances The compile script specifies wire load model and mode instead of using automatic wire load selection Multiply8x8 Shows the basic timing and area constraints used for optimizing a design Multiply16x16 Ungroups DesignWare parts before compilation Ungrouping your hierarchical module might help achieve better synthesis results The compile script for this module defines a two cycle path at the primary ports of the module MuxMod Is a combinational block The script for this design uses the virtual clock concept PathSegment Uses path segmentation within a module The script uses the set_multicycle_path command for a two cycle path within the module and the group command to create a new level of hierarchy Example A 1 through Example A 11 provide the Verilog source code for the ChipLevel design Appendix A Design Example A 4 Example A 1 ChipLevel v Date May 11 1995 Example Circuit for Baseline Methodology for Synthesis Design does not show any real life application but rather it is used to illustrate the commands used in the Baseline Methodology module ChipLevel datal6 a datalb b datal6_c datal6_d clk cin din a din b sel rst start mux out coutl cout2 s1 s2 op comp out1 comp out2 m32 out regout input 15 0 datalb6 a datal6_b datal6_c datalb d
119. e design environment set load 2 2 sout set load 1 5 cout set driving cell lib cell FD1 all inputs set drive 0 cilk name Define design constraints set input delay 1 35 clock clik name ain bin set input delay 3 5 clock clk name cin set max area 0 compile write f db hierarchy o db path design db include script path report scr Compile Scripts A 29 Example A 30 cascademod scr Script file for constraining CascadeMod Constraints are set at this level and then a hierarchical compile approach is used rpt_file cascademod rpt design cascademod current_design CascadeMod include script_path defaults con Define design environment set_load 2 5 all_outputs set driving cell lib cell FD1 all inputs set drive 0 cilk name Define design constraints set input delay 1 35 clock clik name datal data2 set input delay 3 5 clock clik name cin set input delay 4 5 clock clk name rst start set output delay 5 5 clock clk name comp out set max area 0 Use compile once dont touch approach for Comparator set dont touch u12 compile write f db hierarchy o db path design db include script path report scr Appendix A Design Example A 30 Example A 31 comp16 scr Script file for constraining Comparator rpt file comp16 rpt design comp16 current design Comparator include script path defaults con Define design
120. e dr ice 4 5 DesignWare Libraries 4 5 Specifying LIDranles so aaa Nadaanan Me RAA EE Mie 4 6 Specifying Technology Libraries 4 6 Target Library Pata Am Ae ares en 4 7 LIK Dray swt ace see AA aye 4 7 Specifying DesignWare Libraries 4 10 Specifying a Library Search Path 4 10 Loading Be LAN 4 11 Listing Libraries oa ohne nee ve eae as Boece aie eG 4 11 Reporting Library Contents 4 12 Specifying Library Objects 4 12 Directing Library Cell Usage 4 13 Excluding Cells From the Target Library 4 13 Specifying Cell Preferences 4 14 Removing Libraries From Memory 4 16 Saving LIDIANGS ESS sreo oka te Se NE De nr PE RE 4 16 5 Working With Designs in Memory Design 18rMmINOlOg ses sr anses 5 3 ABOUT Designs LES ess be es s pannes se 5 3 Flat Designs st eve essaie ans ro rue ddr de 5 3 Hierarchical Designs 220 labang hha dar init 5 3 D SIgnObieCtS AA PAPA 5 4 Vi Relationship Between Designs Instances and References sation Couatien maine ane 5 6 Using Reference Objects 5 7 Design Database Formats 5 8 Reading DeSIONS Lin nn rt er ee ee ea Oued 5 9 Commands for Reading Design Files 5
121. e results and debug your design This chapter contains the following sections e Checking for Design Consistency e Analyzing Your Design During Optimization e Analyzing Design Problems e Analyzing Timing Problems e Resolving Specific Problems 9 1 Checking for Design Consistency design is consistent when it does not contain errors such as unconnected ports constant valued ports cells with no input or output pins mismatches between a cell and its reference multiple driver nets connection class violations or recursive hierarchy definitions Design Compiler runs the check_design summary command on all designs that are compiled however you can also use the command explicitly to verify design consistency The command reports a list of warning and error messages e lt reports an error if it finds a problem that Design Compiler cannot resolve You cannot compile a design that has check_design errors e Itreports a warning if it finds a problem that indicates a corrupted design or a design mistake not severe enough to cause the compile command to fail Use options to the check_design command as follows To do this Use this To perform checks at only the current level of one_level hierarchy by default the check_design command validates the entire design hierarchy Disable warnings no_warnings Display a summary of warning messages instead summary of one message per warning Display a list of all multiply
122. e slack critical 8 36 total 8 36 worst 8 34 nets 5 6 networks 5 6 optimization 2 2 parent design 5 3 pin 5 6 ports 5 5 subdesign 5 3 synthesis 2 2 delay calculation reporting 9 9 delay cost calculating maximum 8 34 minimum 8 37 delay based auto ungrouping 5 42 delays setting 7 11 7 14 design data management 3 2 in memory 5 1 organization 3 3 design attributes C 2 Design Compiler description 1 1 design flow 1 2 exiting 2 12 family of products 1 4 help 2 13 interfaces 2 8 modes 2 7 session example 2 25 starting 2 11 Design Compiler family DC Expert 1 5 DC FPGA 1 8 DC Ultra 1 6 Design Vision 1 8 DesignWare 1 7 DFT Compiler 1 7 HDL Compiler 1 6 Module Compiler 1 7 Power Compiler 1 7 design constraints commands setting B 3 design database formats 5 8 converting from db to ddc 5 57 db 5 8 ddc 5 8 Milkyway 5 9 design environment commands B 2 defining 6 3 See also operating conditions design example block diagram A 2 compile scripts A 16 compile strategies for A 3 constraints file A 13 hierarchy A 3 setup file A 12 design exploration 8 40 basic flow 2 18 invoking 8 40 design files reading 2 21 5 10 5 14 writing 5 53 design flow 1 2 high level figure 2 5 synthesis design exploration 2 18 design implementation 2 18 design function target libraries 4 4 design hierarchy changing 5 31 displaying 5 31 preserved timing constraints 5 46 removing levels 5 35 See also hierarchy design implementati
123. e technology library because they are requirements for the technology but you can make them more restrictive to suit your design If both implicit and explicit design rule constraints apply to a design or a net the more restrictive value takes precedence Setting Transition Time Constraints The transition time of a net is the time required for its driving pin to change logic values This transition time is based on the technology library data For the nonlinear delay model NLDM output transition time is a function of input transition and output load Design Compiler and Library Compiler model transition time restrictions by associating a max_transition attribute with each output pin on a cell During optimization Design Compiler attempts to make the transition time of each net less than the value of the max_transition attribute To change the maximum transition time restriction specified in a technology library use the set_max_transition command This command sets a maximum transition time for the nets attached to the identified ports or to all the nets in a design by setting the max_transition attribute on the named objects Chapter 7 Defining Design Constraints 7 4 For example to set a maximum transition time of 3 2 on all nets in the design adder enter one of the following commands depending on your command language dc_shell xg t gt set max transition 3 2 get designs adder dc shell set max transition 3 2 find
124. e the priority of the constraints by using the set_cost_priority command Also you can disable design rule fixing by specifying the no design rule option when you run the compile command However if you use this option your synthesized design might violate design rules Selecting and Using a Compile Strategy You can use various strategies to compile your hierarchical design The basic strategies are e Top down compile in which the top level design and all its subdesigns are compiled together e Bottom up compile in which the individual subdesigns are compiled separately starting from the bottom of the hierarchy and proceeding up through the levels of the hierarchy until the top level design is compiled e Mixed compile in which the top down or bottom up strategy whichever is most appropriate is applied to the individual subdesigns In the following sections the top down and bottom up compile strategies are demonstrated using the simple design shown in Figure 8 1 Selecting and Using a Compile Strategy 8 7 Figure 8 1 Design to Illustrate Compile Strategies TOP U1 U2 A U3 B U4 U5 C D E The top level or global specifications for this design given in Table 8 2 are defined by the script of Example 8 1 or Example 8 2 These specifications apply to TOP and all its subdesigns Table 8 2 Design Specifications for Design TOP
125. eck design command now generates warnings for the following cases e Constant driven outputs in the design that is an output that is driven by a logic constant cell or the check_design command is called post compile on an originally unused output e A multidriver net connecting VDD directly to VSS e A multidriver net with constant drivers e Designs with no child cells or nets Additionally the check_design command has a new option multiple_designs that you can use to display multiply instantiated designs By default warning messages related to such designs are not reported Usage of the current_design Command In XG mode several commands are enhanced to accept instance objects that is cells at a lower level of hierarchy You can operate on hierarchical designs from any level in the design without using the current_design command The enhanced commands are listed below What s New in This Release xxiii Preface XXIV e Netlist editing commands These commands are used for incrementally editing a design that is in memory Examples are create_cell create net connect_net disconnect_net create_port remove_cell remove_net remove_port remove_unconnected_ports create_bus remove_bus and report_bus For a list of enhanced commands see Chapter 5 of this manual e The ungroup group and uniquify commands For detailed information see Chapters 5 and 8 of this manual e Theset size only command In addition to
126. eck the top level design for constraint violations You should see improved results but you might need to iterate the entire process several times to remove all significant violations The bottom up compile strategy requires these steps 1 Develop both a default constraint file and subdesign specific constraint files The default constraint file includes global constraints such as the clock information and the drive and load estimates The subdesign specific constraint files reflect the time budget allocated to the subblocks 2 Compile the subdesigns independently Selecting and Using a Compile Strategy 8 13 Read in the top level design and any compiled subdesigns not already in memory Set the current design to the top level design link the design and apply the top level constraints If the design meets its constraints you are finished Otherwise continue with the following steps Apply the characterize command to the cell instance with the worst violations Use write_script to save the characterized information for the cell You use this script to re create the new attribute values when you are recompiling the cell s referenced subdesign Use remove design all to remove all designs from memory Read in the RTL design of the previously characterized cell Recompiling the RTL design instead of the cell s mapped design usually leads to better optimization Setcurrent design to the characterized cel
127. ecks for violations of the connection class rules displays a list of warning messages when violations exist check_timing Checks the timing attributes placed on the current design derive_clocks Automatically creates clocks for all clock sources in a design creates clock objects on ports and internal sources get_attribute Reports the value of the specified attribute link Locates the reference for each cell in the design report_area Provides area information and statistics on the current design report_attribute Lists the attributes and their values for the selected object An object can be a cell net pin port instance or design Commands for Analyzing and Resolving Design Problems B 5 report cell Lists the cells in the current design and their cell attributes reportce lock Displays clock related information on the current design report_constraint Lists the constraints on the current design and their cost weight and weighted cost report_delay_calculation Reports the details of a delay arc calculation report_design Displays the operating conditions wire load model and mode timing ranges internal input and output and disabled timing arcs defined for the current design report_hierarchy Lists the children of the current design report_net Displays net information for the design of the current instance if set otherwise displays net information for the current design report_path_group Lists a
128. ectives to implement a 32 bit carry lookahead adder Example 3 1 32 Bit Carry Lookahead Adder Verilog module add32 a b cin sum cout input 31 0 a b input cin output 31 0 sum output cout reg 33 0 temp always a or b or cin begin addl synopsys resource r0 ops AL map to module DWO1_ add implementation cla temp 1 b0 a cin synopsys label Al 1 b0 b 1 b1 end assign cout sum temp 33 1 endmodule HDL Coding for Synthesis 3 19 Example 3 2 32 Bit Carry Lookahead Adder VHDL library IEEE use I EEE std_logic_1164 all use IEEE std_logic_arith all library synopsys use synopsys attributes all entity add32 is port a b in std_logic_vector 31 downto 0 cin in std_logic sum out std_logic_vector 31 downto 0 cout out std logic end add32 architecture rtl of add32 is signal temp signed SIGNED 33 downto 0 signal opl op2 temp STD LOGIC VECTOR 33 downto 0 constant COUNT UNSIGNED 01 begin infer process a b cin constant r0 resource 0 attribute ops of r0 constant is Al attribute map to module of r0 constant is DW01_ ada attribute implementation of r0 constant is cla begin opl lt 0 amp a amp cin op2 lt 0 amp b amp 1 temp signed lt SIGNED op1 SIGNED op2 pragma label AT temp lt STD LOGIC VECTOR temp signed cout lt temp 33 sum lt temp 32 downto 1
129. ectly This chapter contains the following sections Selecting a Semiconductor Vendor Understanding the Library Requirements Specifying Libraries Loading Libraries Listing Libraries Reporting Library Contents 4 1 Specifying Library Objects Directing Library Cell Usage Removing Libraries From Memory Saving Libraries Selecting a Semiconductor Vendor One of the first things you must do when designing a chip is to select the semiconductor vendor and technology you want to use Consider the following issues during the selection process Maximum frequency of operation Physical restrictions Power restrictions Packaging restrictions Clock tree implementation Floorplanning Back annotation support Design support for libraries megacells and RAMs Available cores Available test methods and scan styles Chapter 4 Working With Libraries 4 2 Understanding the Library Requirements Design Compiler uses these libraries e Technology libraries e Symbol libraries e DesignWare libraries This section describes these libraries Technology Libraries Technology libraries contain information about the characteristics and functions of each cell provided in a semiconductor vendor s library Semiconductor vendors maintain and distribute the technology libraries Cell characteristics include information such as cell names pin names area delay arcs and pin loading The technology library also defines the conditions
130. ed with false path 7 19 disabling false violation messages 9 12 timing paths scan chains 9 12 disconnect net command 5 47 dont touch attribute 9 24 9 26 and dangling logic 9 14 9 26 and timing analysis 8 29 reporting designs 8 30 setting 8 28 drive characteristics removing 6 15 setting command to 6 14 example of 6 16 drive resistance setting 6 15 drive strength defining 6 13 E elaborate command 2 21 5 10 5 14 endpoints timing exceptions 7 17 examples of ungrouping hierarchy 5 40 exit command 2 13 exiting Design Compiler 2 12 expressions guidelines HDL 3 30 F false path compared with disabled timing arc 7 19 defined 7 18 specifying 7 11 7 18 false violation messages disabling 9 12 fanout specifying values of 6 18 fanout load calculating 7 6 controlling 7 5 cost calculation 8 32 defined 7 5 removing attribute of 7 8 fanout load constraints 7 5 fanout_load attribute 7 5 feedback loop breaking 9 15 identifying 9 15 file name extensions conventions 3 2 filename log files 2 15 filename log file variable 2 16 files command log file 2 15 filename log file 2 15 script 2 16 filter command 9 12 find command 9 12 flat design 5 3 flattening critical path logic 8 52 flattening design 8 4 flip flop defined 3 15 inferring 3 16 full case directive 3 25 functions guidelines HDL 3 31 G gate level optimization 8 6 get attribute command 5 65 9 23 9 25 get cells command 9 11 9 12 get
131. ee the section Exiting Design Compiler on page 2 12 and see the chapters on using script files in the Design Compiler Command Line Interface Guide A Design Compiler Session Example Example 2 2 on page 2 26 shows a simple dcsh script that performs a top down compile run Example 2 3 on page 2 27 shows the same script in dctcl syntax It uses the basic synthesis flow The script contains comments that identify each of the steps in the flow Some of the script command options and arguments have not yet been explained in this manual Nevertheless from the previous discussion of the basic synthesis flow you can begin to understand this example of a top down compile The remaining chapters will help you understand these commands in detail Note Only the set driving cel1 command is not discussed in the section on basic synthesis design flow The set driving cell command is an alternative way to set the external drives on the ports of the design to be synthesized A Design Compiler Session Example 2 25 Example 2 2 Top Down Compile Script in desh specify the libraries target_library my_lib db symbol library my_lib sdb link_library target_library read the design read_file format verilog Adder16 v define the design environment set_operating_conditions WCCOM set_wire_load_model 10x10 set_load 2 2 sout set_load 1 5 cout set driving cell lib cell FD1 all inputs set drive 0 cik se
132. eference option or you can specify specific cells by using the ce11 option Design Compiler makes unique copies for cells specified with the reference or the cells option even if they have a dont touch attribute The uniqui fy command accepts instance objects that is cells at a lower level of hierarchy When you use the ce11 option with an instance object the complete path to the instance is uniquified For example the following command uniquifies both instances mid1 and mid1 bot1 assuming that mid1 is not unique dc_shell xg t gt uniquify cell midi bot1 Note In DB mode the uni qui fy command does not accept instance objects When you use the ce11 option the cells that you specify must be in the current design Design Compiler uses the naming convention specified in the uniquify naming style Variable to generate the name for each copy of the subdesign The default naming convention is oe oe s Sd oe S The original name of the subdesign or the name specified in the base_name option oe d The smallest integer value that forms a unique subdesign name You can use the uniquify command simply to resolve multiple design references or you can recompile the current design after the multiple references to the subdesigns are resolved Resolving Multiple Instances of a Design Reference 8 23 Note Without recompiling the design you can use the uniquify command together with the uniquify_naming_style v
133. egative Slack Method 8 34 Critical Range Negative Slack Method 8 36 Calculating Minimum Delay Cost 8 37 Calculating Maximum Power Cost 8 38 Calculating Maximum Area Cost 8 39 Calculating Minimum Porosity Cost 8 39 Performing Design Exploration 8 40 Performing Design Implementation 8 41 Optimizing Random Logic 8 41 Optimizing Structured Logic 8 43 Optimizing High Performance Designs 8 43 Automatic Ungrouping Using the compile _ultra command 8 45 Optimizing for Maximum Performance 8 47 Creating Path GrOUbS 2 14 pente den etat een eee 8 47 Fixing Heavily Loaded Nets 8 51 Flattening Logic on the Critical Path 8 52 xi xii Automatically Ungrouping Hierarchies on the Critical Path anaana aaa 8 54 Performing a High Effort Compile 8 54 Performing a High Effort Incremental Compile 8 55 Optimizing for Minimum Area 8 56 Disabling Total Negative Slack Optimization 8 56 Enabling Boolean Optimization 8 57 Managing Resource Selection 8 57 Using Flattening aaahhh mana oy es
134. el of hierarchy You can operate on hierarchical designs from any level in the design without using the current_design command For example you can enter the following command to create a cell called foo in the design mid1 dc_shell xg t gt create cell midi foo my lib AND2 Note In DB mode the netlist editing commands do not accept instance objects You would issue the following commands to achieve the same result as in the previous example dc_shell gt current design midi dc shells create cell foo my lib AND2 When connecting or disconnecting nets use the a11 connected command to see the objects that are connected to a net port or pin Chapter 5 Working With Designs in Memory 5 48 In Table 5 6 the command sequences shown replace the reference for cell U8 with a high power inverter Table 5 6 Design Editing Examples dcsh Example dctcl Example dc_shell gt find pin U8 U8 A U8 Z dc_shell gt all_connected U8 A n66 dc_shell gt all connected U8 Z OUTBUS 10 dc_shell gt remove_cell U8 Removing cell U8 in design top 1 dc_shell gt create_cell U8 IVP Creating cell U8 in design top 1 dc_shell gt connect_net n66 find pin U8 A Connecting net nb6 to pin U8 A 1 dc_shell gt connect_net OUTBUS 10 find pin U8 Z Connecting net OUTBUS 10 to pin U8 Z 1 Note dc_shell xg t gt get_pins U8 U8 A U8 Z
135. ell libraries e Translate designs from one technology to another e Explore design tradeoffs involving design constraints such as timing area and power under various loading temperature and voltage conditions Chapter 1 Introduction to Design Compiler 1 4 e Synthesize and optimize finite state machines including automatic state assignment and state minimization e Integrate netlist inputs and netlist or schematic outputs into third party environments while still supporting delay information and place and route constraints e Create and partition hierarchical schematics automatically DC Expert At the core of the Synopsys RTL synthesis solution is the DC Expert DC Expert is applied to high performance ASIC and IC designs DC Expert provides the following features e Hierarchical compile top down or bottom up e Full and incremental compile techniques e Sequential optimization for complex flip flops and latches e Time borrowing for latch based designs e Timing analysis e Buffer balancing within hierarchical blocks e Command line interface and graphical user interface e Budgeting the process of allocating timing and environment constraints among blocks in a design e Automated chip synthesis a set of Design Compiler commands that fully automate the partitioning budgeting and distributed synthesis flow for large designs Design Compiler Family 1 5 DC Ultra The DC Ultra tool is applied to high performance
136. ences Use options to the elaborate command as follows To do this Use this Specify the name of the design to be built the design_name design can be a Verilog module a VHDL entity or a VHDL configuration Find the design in a library other than the work library library the default Specify the name of the architecture architecture Automatically reanalyze out of date intermediate update files if the source can be found Specify a list of design parameters parameters For more information about the analyze and elaborate commands see the man pages and HDL Compiler Presto Verilog Reference Manual or the HDL Compiler Presto VHDL Reference Manual Reading Designs 5 11 Using the read file Command The read file command does the following Reads several different formats Performs the same operations as analyze and elaborateina single step Creates mr and st intermediate files for VHDL Does not execute the link command automatically see Linking Designs on page 5 19 Does not create any intermediate files for Verilog However you can have the read file command create intermediate files by setting the hdalin auto save templates variable to true For designs in memory Design Compiler uses the naming convention path name design ddc The path name argument is the directory from which the original file was read and the design argument is the name of the design If you later read in a design that has t
137. end always posedge clk begin z out lt mult e end endmodule DC Expert Compile When you compile using DC Expert the design is optimized into the structure shown in Figure 8 13 Notice that the multipliers and adder in the design are mapped separately to DesignWare parts It would be advantageous if they were merged into one datapath block but this is not possible with DC Expert Using DC Ultra Datapath Optimization 8 67 Figure 8 13 DC Expert Optimization Multiplier Multiplier DW02_mult DW02 mult Adder DWO1 add z out DC Ultra Datapath Optimization If you compile using DC Ultra datapath optimization the design is optimized to the structure shown in Figure 8 14 Notice the dashed line around the multipliers adder and MUX this is meant to indicate that DC Ultra datapath optimization has created a single datapath block that includes the arithmetic components Chapter 8 Optimizing the Design 8 68 Figure 8 14 DC Ultra Datapath Optimization With Datapath Extraction a b c d Multiplier Multiplier Comparison of the Two Datapath Optimizations In many cases creating datapath blocks with shared arithmetic components produces better timing CPU time area and QOR Table 8 10 gives a comparison summary of the results for the design defined by Example 8 8 on page 8 67 Table 8 10 Summary of DC Ultra Datapath Optimization Improvements Item DC Exper
138. ents Several of the many factors affecting the optimization outcome are discussed in this chapter This chapter has the following sections The Optimization Process Selecting and Using a Compile Strategy Resolving Multiple Instances of a Design Reference Preserving Subdesigns Understanding the Compile Cost Function Performing Design Exploration 8 1 e Performing Design Implementation e Using DC Ultra Datapath Optimization The Optimization Process Design Compiler performs the following three levels of optimization e Architectural optimization e Logic level optimization e Gate level optimization The following sections describe these processes Architectural Optimization Architectural optimization works on the HDL description It includes such high level synthesis tasks as e Sharing common subexpressions e Sharing resources e Selecting DesignWare implementations e Reordering operators e Identifying arithmetic expressions for data path synthesis DC Ultra only Except for DesignWare implementations these high level synthesis tasks occur only during the optimization of an unmapped design DesignWare selection can recur after gate level mapping Chapter 8 Optimizing the Design 8 2 High level synthesis tasks are based on your constraints and your HDL coding style After high level optimization circuit function is represented by GTECH library parts that is by a generic technology independent netlist
139. environment set load 2 5 cp out set driving cell lib cell FD1 all inputs Override auto wire load selection set wire load model name 05x05 set wire load mode enclosed Define design constraints set input delay 1 35 clock clik name ain bin set output delay 5 1 clock clik name cp out set max area 0 compile write f db hierarchy o db path design db include script path report scr Compile Scripts A 31 Example A 32 mult8 scr Script file for constraining Multiply8x8 rpt_file mult8 rpt design mult8 current design Multiply8x8 include script path defaults con Define design environment set load 2 2 res set driving cell lib cell FDIP all inputs set drive 0 clk_ name Define design constraints set input delay 1 35 clock clk name opl op2 set max area 0 compile write f db hierarchy o db path design db include script path report scr Appendix A Design Example A 32 Example A 33 mult16 scr Script file for constraining Multiply16x16 rpt file mult16 rpt design mult16 current_design Multiply16x16 include script_path defaults con Define design environment set_load 2 2 res set driving cell lib_cell FD1 all inputs set drive 0 cilk name Define design constraints set input delay 1 35 clock clk name opl op2 set max area 0 Define multicycle path for multiplier set multicycle pa
140. er Command Line Interface Guide Important If you are using dcsh command language and the setup file in your home directory uses dcsh syntax instead of the Tcl subset this setup file will not work For details on the synthesis setup files see Setup Files on page 2 9 Example A 12 synopsys dc setup File Define the target technology library symbol library and link libraries set target library 1si 10k db set symbol library 1si 10k sdb set link library concat Starget library set search path concat ssearch path src set designer Your Name set company Synopsys Inc Define path directories for file locations set source path src set script path scr set log path log set ddc path ddc set db path db set netlist path netlist Appendix A Design Example A 12 Default Constraints File The file shown in Example A 13 dctcl command language and Example A 14 dctsh command language defines the default constraints for the design In the scripts that follow Design Compiler reads this file first for each module If the script for a module contains additional constraints or constraint values different from those defined in the default constraints file Design Compiler uses the module specific constraints Default Constraints File A 13 Example A 13 defaults con dctcl Define system clock period set clk_period 20 Create real clock if clock port is found if
141. er Basics 2 2 The High Level Design Flow In a basic high level design flow Design Compiler is used in both the design exploration stage and the final design implementation stage In the exploratory stage you use Design Compiler to carry out a preliminary or default synthesis In the design implementation stage you use the full power of Design Compiler to synthesize the design Figure 2 1 shows the high level design flow The shaded areas indicate where Design Compiler synthesis tasks occur in the flow The High Level Design Flow 2 3 Figure 2 1 Basic High Level Design Flow D HDL coding Paa pa Goal specification Functional simulation Y Design exploration Within 15 of timing Design implementation goals Met goals Yes Physical design No Chapter 2 Design Compiler Basics 2 4 Using the design flow shown in Figure 2 1 you perform the following steps 1 Start by writing an HDL description Verilog or VHDL of your design Use good coding practices to facilitate successful Design Compiler synthesis of the design Perform design exploration and functional simulation in parallel In design exploration use Design Compiler to a implement specific design goals design rules and optimization constraints and b carry out a preliminary default synthesis using only the Design Compiler default options If design exploration fai
142. ernally by the integrated circuit itself a clock that does not come directly from an external source An example of a generated clock is a divide by 2 clock generated from the system clock You define a generated clock with the create_generated_clock command hold time The time that a signal on the data pin must remain stable after the active edge of the clock The hold time creates a minimum delay requirement for paths leading to the data pin of the cell You calculate the hold time by using the formula hold max clock delay min data delay ideal clock A clock that is considered to have no delay as it propagates through the clock network The ideal clock type is the default for Design Compiler You can override the default behavior using the set_clock_latency and set_propagated_clock commands to obtain nonzero clock network delay and specify information about the clock network delays ideal net Nets that are assigned ideal timing conditions that is latency transition time and capacitance are assigned a value of zero Such nets are exempt from timing updates delay optimization and design rule fixing Defining certain high fanout nets that you intend to synthesize separately such as scan enable and reset nets as ideal nets can reduce runtime You use the set_ideal_net command to specify nets as ideal nets input delay A constraint that specifies the minimum or maximum amount of delay from a clock edge to the arrival of
143. es Design Compiler provides the following ways to read design files e The analyze and elaborate commands e The read_file command e The read_milkyway command Using the analyze and elaborate Commands The analyze command does the following e Reads an HDL source file e Checks it for errors without building generic logic for the design e Creates HDL library objects in an HDL independent intermediate format e Stores the intermediate files in a location you define If the analyze command reports errors fix them in the HDL source file and run analyze again After a design is analyzed you must reanalyze it only when you change it Use options to the analyze command as follows To do this Use this Store design elements in a library other than the library work library By default the analyze command stores all output in the work library Specify the format of the files to be analyzed vhdl or verilog Specify a list of files to be analyzed file_list Chapter 5 Working With Designs in Memory 5 10 The elaborate command does the following e Translates the design into a technology independent design GTECH from the intermediate files produced during analysis e Allows changing of parameter values defined in the source code e Allows VHDL architecture selection e Replaces the HDL arithmetic operators in the code with DesignWare components e Automatically executes the Link command which resolves design refer
144. es from cell names enter dc_shell xg t gt define name rules naming convention map _ type cell For more information about the define name rules command see the man page Chapter 5 Working With Designs in Memory 5 58 Resolving Naming Problems in the Flow You might encounter conflicts in naming conventions in design objects input and output files and tool sets In the design database file you can have many design objects such as ports nets cells logic modules and logic module pins all with their own naming conventions Furthermore you might be using several input and output file formats such as DEF PDEF Verilog and EDIF in your flow Each file format is different and has its own syntax definitions Using tool sets from several vendors can introduce additional naming problems To resolve naming issues use the change_names command to ensure that all the file names match Correct naming eliminates name escaping or mismatch errors in your design For more information about the change_names command see the man page Methodology for Resolving Naming Issues To resolve naming issues make the name changes in the design database file before you write any files Your initial flow is 1 Read in your design RTL and apply constraints No changes to your method need to be made here 2 Compile the design to produce a gate level description Compile or reoptimize your design as you normally wou
145. es that define your preferences for the Design Compiler working environment The variables in this file override the corresponding variables in the systemwide setup file This file contains project or design specific variables that affect the optimizations of all designs in this directory To use the file you must invoke Design Compiler from this directory Variables defined in this file override the corresponding variables in the user defined and systemwide setup files Example 2 1 shows a sample synopsys dc setup file Chapter 2 Design Compiler Basics 2 10 Example 2 1 synopsys dc setup File Define the target technology library symbol library and link libraries set set set set set set target library 1si 10k db symbol library 1si 10k sdb synthetic library dw_foundation sldb link library Starget library Ssynthetic library search path concat Ssearch path src designer Your Name Define aliases alias h history alias rc report constraint all violators Starting Design Compiler Table 2 2 lists the ways in which you can start Design Compiler and the resulting command prompt Table 2 2 Starting Design Compiler Mode Command Prompt XG mode the default dctcl command dc_shell xg t dc_shell xg t gt language only dc shell xg_mode dc shell tcl mode xg mode DB mode dctcl command dc shell db mode tcl mode dc shell t
146. esign Compiler does not move the latch during retiming To enable the retiming of these latches set the optimize_reg_retime_clock_gating_latches variable to true Additionally you can use the optimize_reg_max_time_borrow variable to limit the latch time borrowing globally For more information see the Design Compiler Register Retiming Manual Improved Design Modeling Design Compiler version X 2005 09 has the following improvements in design modeling e Frequency based maximum capacitance You can have Design Compiler consider the effect of clock frequency on the max_capacitance design rule constraint by setting the compile_enable_dyn_max_cap variable to true Your technology library should be characterized for multiple frequencies that is amax_capacitance value is associated with each driver pin for each frequency and this information is captured in a one dimensional lookup table e Clock based maximum transition You can have Design Compiler consider the effect of clock frequency on the max transition design rule constraint For designs with multiple clock domains use the set max transitioncommand to setthemax transition attribute on pins in a specific clock group For more information see the Design Compiler Reference Manual Constraints and Timing Chapter 2 Enhanced Usability Design Compiler version X 2005 09 delivers several enhancements to the user interface Improved check_design Command In XG mode the ch
147. et eee 8 59 Optimizing Across Hierarchical Boundaries 8 59 Optimizing Data PAS 2 64 cieve ee aaaea 8 61 Using DC Ultra Datapath Optimization 8 61 Datapath Extraction a aa pn tit Chee na ee eee Ace ed 8 63 Two Different Datapath Optimization Methods 8 67 Methodology Flow lt 2 anu as ete rears Ss KUNAN LAGA Ha 8 70 Datapath Report ER paa RER SNS seein 8 73 Commands Specific to DC Ultra Datapath Optimization 8 76 Analyzing and Resolving Design Problems Checking for Design Consistency 9 2 Analyzing Your Design During Optimization 9 3 Customizing the Compile Log 9 3 Saving Intermediate Design Databases 9 6 Analyzing Design Problems 9 7 Analyzing Timing Problems 9 8 Resolving Specific Problems 9 9 Analyzing Cell Delays 9 9 Finding Unmapped Cells 9 11 Finding Black Box CeliS 5 eee ou eae eR RG EEG EES 9 12 Finding Hierarchical Cells 9 12 Disabling Reporting of Scan Chain Violations 9 12 Insulating Interblock Loading 9 14 Preserving Dangling Logic aeaaaee 9 14 Preventing Wire Delays on Ports 9 15 Breaking a Feedback Loop
148. exists the maximum delay cost is the amount of the worst violation multiplied by the group weight e When multiple path groups exist the costs for all the groups are added to determine the maximum delay cost of the design During optimization the Design Compiler focus is on reducing the delay of the most critical path This path changes during optimization If Design Compiler minimizes the initial path s delay so that it is no longer the worst violator the tool shifts its focus to the path that is now the most critical path in the group Critical Range Negative Slack Method Design Compiler also supports the critical range negative slack method to calculate the maximum delay cost The critical range negative slack method considers all violators in each path group that are within a specified delay margin referred to as the critical range of the worst violator For example if the critical range is 2 0 ns and the worst violator has a delay of 10 0 ns Design Compiler optimizes all paths that have a delay between 8 0 and 10 0 ns The critical range negative slack is the sum of all negative slack values within the critical range for each path group When the critical range is large enough to include all violators the critical negative slack is equal to the total negative slack For information about specifying the critical range see Creating Path Groups on page 8 47 Chapter 8 Optimizing the Design 8 36 Using the criti
149. f mixed signed and unsigned operators Design Compiler version X 2005 09 performs datapath extraction if both signed and unsigned operators exist in a single datapath block when you use the compile_ultra flow This enhancement delivers better quality of results e Extraction of variable shift operators Design Compiler version X 2005 09 can extract variable shift operators lt lt gt gt lt lt lt gt gt gt for Verilog and s11 srl sla sra rol ror for VHDL and allow them to be optimized as part of the datapath when you use the compile_ultra command To enable this feature set the hdlin_use_syn_shifters variable to true This enhancement delivers better quality of results For more information see Chapter 8 of this manual Enhanced Auto Ungrouping in compile_ultra In XG mode Design Compiler version X 2005 09 the compile_ultra command has been enhanced to perform area based auto ungrouping before initial mapping The tool estimates the area for unmapped hierarchies and removes small subdesigns the goal is to improve area and timing quality of results For more information see Chapter 8 of this manual What s New in This Release xxi Preface xxii Support for Retiming Level Sensitive Latches In Design Compiler version X 2005 09 the optimize_registers command has a new option 1atch that allows you to retime level sensitive latches If a latch directly drives a cell that is identified as a clock gate D
150. fanin Reports fanin logic report_transitive_fanout Reports fanout logic Ports report_port Displays information about ports report_bus Displays information about bused ports report_transitive_fanin Reports fanin logic report_transitive_fanout Reports fanout logic Nets report_net Reports net characteristics report_bus Reports bused net characteristics report_transitive_fanin Reports fanin logic report_transitive_fanout Reports fanout logic Clocks report_clock Displays information about clocks Analyzing Design Problems 9 7 Analyzing Timing Problems Before you begin debugging timing problems verify that your design meets the following requirements You have defined the operating conditions You have specified realistic constraints You have appropriately budgeted the timing constraints You have properly constrained the paths You have described the clock skew If your design does not meet these requirements make sure it does before you proceed After producing the initial mapped netlist use the report_constraint command to check your design s performance Table 9 4 lists the timing analysis commands Table 9 4 Command Timing Analysis Commands Analysis task description report_desi check_timin report_port report_timi gn Shows operating conditions wire load model and mode timing ranges internal input and output and disabled timing arcs g Checks for unconstrained timing paths and cl
151. fault paths whose endpoints are clocked by the same clock are assigned to the same path group pin A part of a cell that provides for input and output connections Pins can be bidirectional The ports of a subdesign are pins within the parent design propagated clock A clock that incurs delay through the clock network Propagated clocks are used to determine clock latency at register clock pins Registers clocked by a propagated clock have edge times skewed by the path delay from the clock source to the register clock pin You use the set_propagated_clock command to specify that clock latency be propagated through the clock network real clock A clock that has a source meaning its waveform is applied to pins or ports in the design You create a real clock by using a create_clock command and including a source list of ports or pins Real clocks can be either ideal or propagated reference A library component or design that can be used as an element in building a larger circuit The structure of the reference may be a simple logic gate or a more complex design RAM core or CPU A design can contain multiple occurrences of a reference each occurrence is an instance See also instance RTL RTL or register transfer level is a register level description of a digital electronic circuit In a digital circuit registers store intermediate information between clock cycles thus RTL describes the intermediate information that is stored
152. ferent Constraints Goal Minimum area Non critical path si J Partitioning by Compile Technique Goal Maximum performance q Critical path A Partition logic that requires different compile techniques into separate blocks Use this method when the design contains highly structured logic along with random logic e Highly structured logic such as error detection circuitry which usually contains large exclusive OR trees is better suited to structuring e Random logic is better suited to flattening For more information on these two compile techniques see Logic Level Optimization on page 8 3 Figure 3 7 shows the logic separated into different blocks Partitioning for Synthesis 3 9 Figure 3 7 Blocks With Different Compile Techniques set_structure true set_flatten true Random Logic D Keeping Sharable Resources Together Design Compiler can share large resources such as adders or multipliers but resource sharing can occur only if the resources belong to the same VHDL process or Verilog always block For example if two separate adders have the same destination path and have multiplexed outputs to that path keep the adders in one VHDL process or Verilog always block This approach allows Design Compiler to share resources using one adder instead of two if the constraints allow sharin
153. fies the timing constraints and enables sequential optimization e Eliminate glue logic Glue logic is the combinational logic that connects blocks Moving this logic into one of the blocks improves synthesis results by providing Design Compiler with additional flexibility Eliminating glue logic also reduces compile time because Design Compiler has fewer logic levels to optimize For example assume that you have a design containing three combinational clouds on or near the critical path Figure 3 3 shows poor partitioning of this design Each of the combinational clouds occurs in a separate block so Design Compiler cannot fully exploit its combinational optimization techniques Figure 3 3 Poor Partitioning of Related Logic Critical path Po Pl Chapter 3 Preparing Design Files for Synthesis 3 6 Figure 3 4 shows the same design with no artificial boundaries In this design Design Compiler has the flexibility to combine related functions in the combinational clouds Figure 3 4 Keeping Related Logic in the Same Block L Registering Block Outputs To simplify the constraint definitions make sure that registers drive the block outputs as shown in Figure 3 5 Figure 3 5 Registering All Outputs set_driving_cell my_flop all_inputs set_input_delay 2 clock CLK aa ie aaa This method enables you to constrain each
154. files and libraries added to the beginning of the link 1ibrary variable during the linking process Design Compiler searches files in the local_link library attribute first when it resolves references search_path variable If Design Compiler does not find the reference in the link libraries it searches in the directories specified by the search_path variable described in Specifying a Library Search Path on page 4 10 For more information on resolving references see Linking Designs on page 5 19 The syntax for dctcl is set link_library my_tech db The syntax for dcsh is link_library my_tech db Chapter 4 Working With Libraries 4 8 Note that you specify the same value for the target library and the link library except when you are performing technology translation When you specify the files in the link 1ibrary variable consider that Design Compiler searches these files from left to right when it resolves references and it stops searching when it finds a reference If you specify the link library as Isi_10k db the designs in memory are searched before the Isi_ 10k library Design Compiler uses the first technology library found in the link library variable as the main library It uses the main library to obtain default values and settings used in the absence of explicit specifications for operating conditions wire load selection group wire load mode and net delay calculation Design Compiler
155. fining the Design Environment 6 16 4 An AN2 cell drives port 14 Because the different arcs of this cell have different transition times select the worst case arc to define the drive For checking setup violations the worst case arcisthe slowest arc For checking hold violations the worst case arc is the fastest arc For this example assume that you want to check for setup violations The slowest arc on the AN2 cell is the B to Z arc so define the drive as follows Enter dc_shell xg t gt set driving cell lib cell AN2 pin Z from pin B I4 Defining Loads on Input and Output Ports By default Design Compiler assumes zero capacitive load on input and output ports Use the set_load command to set a capacitive load value on input and output ports of the design This information helps Design Compiler select the appropriate cell drive strength of an output pad and helps model the transition delay on input pads For example to set a load of 30 on output pin out1 enter dc_shell xg t gt set load 30 out1 Make the units for the load value consistent with the target technology library For example if the library represents the load value in picofarads the value you set with the set 1oad command must be in picofarads Use the report 1ib command to list the library units Example 6 3 shows the library units for the library my lib Modeling the System Interface 6 17 Example 6 3 Library Units Report KKKKKKKKKKKKKKKKKKKK
156. further changes to them during subsequent compile phases Then the compiled subdesigns are assembled to compose the designs of the next higher level of the hierarchy any higher level design can also incorporate unmapped logic and these designs are compiled This compilation process is continued up through the hierarchy until the top level design is synthesized This method lets you compile large designs because Design Compiler does not need to load all the uncompiled subdesigns into memory at the same time At each stage however you must estimate the interblock constraints and typically you must iterate the compilations improving these estimates until all subdesign interfaces are stable Each strategy has its advantages and disadvantages depending on your particular designs and design goals You can use either strategy to process the entire design or you can mix strategies using the most appropriate strategy for each subdesign Following the Basic Synthesis Flow 2 23 Note The compile strategy you choose affects your choice of design constraints and the values you set Flow steps 5 and 6 are interdependent Design constraints are discussed in step 5 See Chapter 8 Optimizing the Design 7 Optimize the Design You use the compile command to invoke the Design Compiler synthesis and optimization processes Several compile options are available In particular the map_effort option can be set to low medium or high In a
157. fy any of the output formats listed in Table 5 8 except the Milkyway format use the write_milkyway command instead hierarchy output modified library Using the write_milkyway Command In XG mode you use the write_milkyway command within dc_shell to write to a Milkyway database The write_milkyway command creates a design file based on the netlist in memory and saves the design data for the current design in that file For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Saving Designs in ddc Format To save the design data in a ddc file use the write format ddc command Saving Designs 5 55 By default the write command saves just the top level design To save the entire design specify the hier option If you do not use the output option to specify the output file name the write format ddc command creates a file called top design ddc where top design is the name of the current design Example 1 The following command writes out all designs in the hierarchy of the specified design dc_shell xg t gt write hierarchy format ddc top Writing ddc file top ddc Writing ddc file A ddc Writing ddc file B ddc Example 2 The following command writes out multiple designs to a single file dc_shell xg t gt write format ddc output test ddc ADDER MULT 1 6 Writing ddc file test ddc Saving Designs in the db Format In XG m
158. g Figure 3 8 shows possible implementations of a logic example Chapter 3 Preparing Design Files for Synthesis 3 10 Figure 3 8 Keeping Sharable Resources in the Same Process Unshared Resources CTL i For more information about resource sharing see the HDL Compiler documentation Keeping User Defined Resources With the Logic They Drive User defined resources are user defined functions procedures or macro cells or user created DesignWare components Design Compiler cannot automatically share or create multiple instances of user defined resources Keeping these resources with the logic they drive however gives you the flexibility to split the load by manually inserting multiple instantiations of a user defined resource if timing goals cannot be achieved with a single instantiation Figure 3 9 illustrates splitting the load by multiple instantiation when the load on the signal PARITY_ERR is too heavy to meet constraints Partitioning for Synthesis 3 11 Figure 3 9 Duplicating User Defined Resources User Defined Resource User Defined Resource Isolating Special Functions Isolate special functions such as I O pads clock generation circuitry boundary scan logic and asynchronous logic from the core logic Figure 3 10 shows the recommended partitioning for the top level of the design Chapter 3 Preparing Design Files for Synthesis 3 12 Figure 3 10 Rec
159. g t gt list designs show file designs test ddc test test new test new 1 1 Chapter 5 Working With Designs in Memory 5 30 Note Renaming designs might cause unresolved references during linking Changing the Design Hierarchy When possible reflect the design partitioning in your HDL description If your HDL code is already developed Design Compiler enables you to change the hierarchy without modifying the HDL description The report_hierarchy command displays the design hierarchy Use this command to understand the current hierarchy before making changes and to verify the hierarchy changes Design Compiler provides the following hierarchy manipulation capabilities e Adding levels of hierarchy e Removing levels of hierarchy e Merging cells from different subdesigns The following sections describe these capabilities Adding Levels of Hierarchy Adding a level of hierarchy is called grouping You can create a level of hierarchy by grouping cells or related components into subdesigns Changing the Design Hierarchy 5 31 Grouping Cells Into Subdesigns You use the group command to group cells instances in the design into a new subdesign creating a new level of hierarchy The grouped cells are replaced by a new instance cell that references the new subdesign The ports of the new subdesign are named after the nets to which they are connected in the design The direction of each port of the new subdes
160. gh Effort Constant Register Removal e Improved sequential mapper e Advanced datapath transformations e Enhanced auto ungrouping in compile ultra e Support for retiming level sensitive latches Global Optimization Technology Design Compiler version X 2005 09 incorporates a global optimization technology that results in a better timing context During optimization Design Compiler has a global view of the timing of the entire design including black boxes Additionally the tool considers the complete critical path across hierarchical boundaries The tool can revert to abstract Boolean logic when necessary to apply aggressive timing strategies Improved XOR Sharing In previous versions of Design Compiler XOR operations were typically not shared leading to greater area than necessary Design Compiler version X 2005 09 includes a new sharing algorithm that collects trees of XORs and shares them the algorithm is delay sensitive This enhancement results in better area MUX_OP Inference and Optimization In Design Compiler version X 2005 09 the compile_mux_optimization variable set to true by default has been enhanced to automatically infer MUX_OPs for certain case What s New in This Release xix Preface XX statements This enhancement enables improved structuring and can result in improved area QoR with equal or better delay By default Design Compiler dissolves all MUX_OP hierarchies by the end of the compile flow You
161. gisters of the block end end always count or start begin counter C count N count initialize outputs of the block if start count N 1 user specified logic for the block else count N count 1 end endmodule Example A 6 Comparator v module Comparator cp out ain bin Comparator for 2 integer values Output cp out input 15 0 ain bin assign cp out ain x bin endmodule Appendix A Design Example A 8 Example A 7 Multiply8x8 v module Multiply8x8 opl op2 res clk 8 Bit multiplier input 7 0 opl op2 output 15 0 res input clk wire 15 0 res_tmp reg 15 0 res always posedge clk begin res res_tmp end assign res_tmp opl op2 endmodule Example A 8 Multiply16x16 v module Multiply16x16 opl op2 res clk 16 Bit multiplier input 15 0 opl op2 output 31 0 res input clk wire 31 0 res_tmp reg 31 0 res always posedge clk begin res res_tmp end assign res_tmp opl op2 endmodule Example A 9 def macro v define DATA 2 b00 define REG 2 b01 define STACKIN 2 b10 define UPCOUT 2 bi11 Design Description A 9 Example A 10 MuxMod v module MuxMod Y_IN MUX_CNT D R F UPC include def_macro v output 15 0 Y_IN input 1 0 MUX_CNT input 15 0 D F R UPC reg 15 0 Y_IN always MUX_CNT or D or R or F or UPC begin case MUX CNT DATA Y IN D
162. gnal Name Suffixes and Their Meanings Suffix _clk _ next Xi _XO _xod _XZ _xbio Meaning Clock signal Signal before being registered Active low signal Signal that connects to a three state output Register that uses an active falling edge Primary chip input Primary chip output Primary chip open drain output Primary chip three state output Primary chip bidirectional I O Guidelines for Expressions Observe the following guidelines for expressions e Use parentheses to indicate precedence Expression operator precedence rules are confusing so you should use parentheses to make your expression easy to read Unless you are using DesignWare resources parentheses have little effect on the generated logic An example of a logic expression without parentheses that is difficult to read is Chapter 3 Preparing Design Files for Synthesis 3 30 bus select a b amp c d b e amp 1 0 Replace repetitive expressions with function calls or continuous assignments If you use a particular expression more than two or three times consider replacing the expression with a function or a continuous assignment that implements the expression Guidelines for Functions Observe these guidelines for functions Do not use global references within a function In procedural code a function is evaluated when it is called Ina continuous assignment a function is evaluated when any of its declared inputs changes
163. h a design Data is launched by a clock edge at a startpoint propagated through combinational logic elements and captured at an endpoint GL 11 GL 12 by another clock edge The startpoint of a timing path is an input port or clock pin of a sequential element The endpoint of a timing path is an output port or a data pin of a sequential element transition delay A timing delay caused by the time it takes the driving pin to change voltage state ungroup To remove hierarchy levels in a design Ungrouping merges subdesigns of a given level of the hierarchy into the parent cell or design You use the ungroup command or the compile command with the auto_ungroup option to ungroup designs uniquify To resolve multiple cell references to the same design in memory The uniquify process creates unique design copies with unique design names for each instantiated cell that references the original design virtual clock A clock that exists in the system but is not part of the block A virtual clock does not clock any sequential devices within the current design and is not associated with a pin or port You use a virtual clock as a reference for specifying input and output delays relative to a clock outside the block You use the create_clock command without a list of associated pins or ports to create a virtual clock wire load model An estimate of a net s RC parasitics based on the net s fanout in the absence of placement and rou
164. h ungrouped hierarchy Cell Count Based Auto Ungrouping Cell count based auto ungrouping ungroups small hierarchies and is used essentially for area optimization You use this compile option if you want to control explicitly when the compile command ungroups the small hierarchies in the current design and its subdesigns Use the compile auto ungroup area num cells variable to specify the minimum number of child cells that a design hierarchy must have so that it is not ungrouped The default is 30 This threshold value of a hierarchy refers to the number of child cells in that hierarchy that is the cells are not counted recursively To include all leaf cells of the design hierarchy set the compile auto ungroup count leaf cells variable to true Changing the Design Hierarchy 5 41 Delay Based Auto Ungrouping Delay based auto ungrouping ungroups hierarchies along the critical path and is used essentially for timing optimization Use the compile auto ungroup delay num cells variable to specify the minimum number of child cells that a design hierarchy must have so that it is not ungrouped The default is 500 This threshold value of a hierarchy refers to the number of child cells in that hierarchy that is the cells are not counted recursively To include all leaf cells of the design hierarchy set the compile auto ungroup count leaf cells variable to true Note that DesignWare components are not ungrouped because they are already h
165. he cells MID1 BOT1 FOO1 and MID1 BOT1 FOO2 dc_shell xg t gt ungroup MID1 BOT1 FO0O1 MID1 BOT1 F002 The preceding command is equivalent to issuing the following two commands dc_shell xg t gt current_instance MID1 BOT1 dc_shell xg t gt ungroup FOO1 F002 Note In DB mode the ungroup command cannot accept instance objects For example to ungroup the cells MID1 BOT1 FOO1 and MID1 BOT1 FOO2 you would have to enter dc shell current instance MID1 BOT1 dc shells ungroup FOO1 F002 Ungrouping Hierarchies During Optimization You can ungroup designs during optimization either explicitly or automatically Ungrouping Hierarchies Explicitly During Optimization You can control which designs are ungrouped during optimization by using the set ungroup command followed by the compile command or the ungroup a11 compile option Changing the Design Hierarchy 5 39 e Use the set_ungroup command when you want to specify the cells or designs to be ungrouped This command assigns the ungroup attribute to the specified cells or referenced designs If you set the attribute on a design all cells that reference the design are ungrouped For example to ungroup cell U1 during optimization enter the following commands dc_shell xg t gt set_ungroup U1 dc_shell xg t gt compile To see whether an object has the ungroup attribute set use the get_attribute command dc_shell xg t gt get attribute object ungroup To remove an ung
166. he other has a period of 10 1 the common base period is 1010 0 The timing analyzer calculates the setup requirement for this path by expanding both clocks to the common base period and determining the tightest single cycle relationship for setup Internally for extreme cases such as this the timing analyzer only approximates the setup requirement because the paths are not really synchronous You can work around this problem by specifying a clock period without a decimal point and adjusting the clock period by inserting clock uncertainty dc_shell xg t gt create clock period 10 clk1 dc_shell xg t gt create clock period 10 cik2 dc_shell xg t gt set clock uncertainty setup 0 1 cik2 Chapter 7 Defining Design Constraints 7 12 Use the report clock command to show information about all clock sources in your design Use the remove clock command to remove a clock definition Creating a Virtual Clock In some cases a system clock might not exist in a block You can use the create clock name command to create a virtual clock for modeling clock signals present in the system but not in the block By creating a virtual clock you can represent delays that are relative to clocks outside the block dc_shell xg t gt create_clock period 30 waveform 10 25 name sys_clk Specifying Clock Network Delay By default Design Compiler assumes that clock networks have no delay ideal clocks Use the set_clock_latency and set_clock_uncert
167. he same file name Design Compiler overwrites the original design To prevent this use the single file Option with the read file command Use options to the read file command as follows To do this Use this Specify a list of files to be read file list Specify the format in which a design is read format You can specify any input format listed in Table 5 1 except the Milkyway format use the read milkyway command instead Chapter 5 Working With Designs in Memory 5 12 To do this Store design elements in a library other than the work library the default when reading VHDL design descriptions Specify that the design being read is a structural or gate level design when reading Verilog or VHDL designs Use this library netlist format verilog vhdl Specify that the design being read is an RTL rtl format design when reading Verilog or VHDL designs yer iiog vhal 1 The netlist option is optional when you read a Verilog design 2 The rtl option is optional when you read a Verilog design Table 5 2 summarizes the differences between using the read_file command and using the analyze and elaborate commands to read design files Table 5 2 read file Versus analyze and elaborate Commands Comparison read_file command analyze and elaborate commands Input formats When to use Generics Architecture Linking designs All formats Netlists precompiled designs and so forth
168. he same net that remain after ungrouping The constraints are moved forward or backward to other pins on the same net Note that the constraints can be moved backward only if the pin driving the given hierarchical pin drives no other pin Otherwise the constraints must be moved forward If the constraints are moved to a leaf cell that cell is assigned a size only attribute to preserve the constraints during a compile Thus the number of size only cells can increase which might limit the scope of the optimization process To counter this effect when both the forward and backward directions are possible Design Compiler chooses the direction that helps limit the number of newly assigned size only attributes to leaf cells When you apply ungrouping to an unmapped design the constraints on a hierarchical pin are moved to a leaf cell and the size_only attribute is assigned However the constraints are preserved through the compile process only if there is a one to one match between the unmapped cell and a cell from the target library Changing the Design Hierarchy 5 45 Only the timing constraints set with the following commands are preserved set_false_path set multicycle path set min delay set max delay set input delay set output delay set disable timing set case analysis create clock create generated clock set propagated clock set clock latency Note Theset rt1 load constraint is not preserved Also only the timing
169. he set disable timing command to break the scan related timing paths scan input to scan output and scan enable to scan output Chapter 9 Analyzing and Resolving Design Problems 9 12 dc_shell xg t gt set disable timing my lib scanf from TI to Q dc_shell xg t gt set disable timing my lib scanf from CP to TE This example assumes that scanf is the scan cell in your technology library e Tlis the scan input pin on the scanf cell TE is the scan enable on the scanf cell Q is the scan output pin on the scanf cell Example 9 3 and Example 9 4 show scripts that you can use to identify the scan pins in your technology library Example 9 3 Script to Identify Scan Pins dcsh filter find cell my_lib is sequential true seq cell list dc shell status foreach seq cell seq cell list seq pins seq cell filter find pin seq pins signal_type test_scan_in si dc_shell_status if si echo Scan pins for cell seq_cell echo scan input si filter find pin seq_pins signal_type test_scan_out echo scan output dc shell status Resolving Specific Problems 9 13 Example 9 4 Script to Identify Scan Pins dctcl set seq cell list get cells class filter is sequential true foreach in collection seq cell Sseq cell list set seq pins get object name Sseq cel1 set si get pins Sseq pins filter signal type test scan in if sizeof collection Ssi 5 0 then echo S
170. he technology library 3 Default mode in Design Compiler The following sections discuss the selection of wire load models for nets and designs Chapter 6 Defining the Design Environment 6 6 Hierarchical Wire Load Models Design Compiler supports three modes for determining which wire load model to use for nets that cross hierarchical boundaries Top Design Compiler models nets as if the design has no hierarchy and uses the wire load model specified for the top level of the design hierarchy for all nets in a design and its subdesigns The tool ignores any wire load models set on subdesigns with the set wire load model command Use top mode if you plan to flatten the design at a higher level of hierarchy before layout Enclosed Design Compiler uses the wire load model of the smallest design that fully encloses the net If the design enclosing the net has no wire load model the tool traverses the design hierarchy upward until it finds a wire load model Enclosed mode is more accurate than top mode when cells in the same design are placed in a contiguous region during layout Use enclosed mode if the design has similar logical and physical hierarchies Segmented Design Compiler determines the wire load model of each segment of a net by the design encompassing the segment Nets crossing hierarchical boundaries are divided into segments For each net segment Design Compiler uses the wire load model of Defining Wire Load Mo
171. hesis Test synthesis is the process by which designers can integrate test logic into a design during logic synthesis Test synthesis enables designers to ensure that a design is testable and resolve any test issues early in the design cycle Design Compiler and the Design Flow 1 3 The result of the logic synthesis process is an optimized gate level netlist which is a list of circuit elements and their interconnections 5 After test synthesis the design is ready for the place and route tools which place and interconnect cells in the design Based on the physical routing the designer can back annotate the design with actual interconnect delays Design Compiler can then resynthesize the design for more accurate timing analysis Design Compiler reads and writes design files in all the standard electronic design automation EDA formats including the Synopsys internal database ddc and db and equation eqn formats In addition Design Compiler provides links to other EDA tools such as place and route tools and to post layout resynthesis techniques such as in place optimization These links enable information sharing including forward directed constraints and delays between Design Compiler and external tools Design Compiler Family Synopsys provides an integrated RTL synthesis solution Using Design Compiler tools you can e Produce fast area efficient ASIC designs by employing user specified gate array FPGA or standard c
172. hesis information for users of the Design Compiler tools This manual describes synthesis concepts and commands and presents examples for basic synthesis strategies This manual does not cover asynchronous design I O pad synthesis test synthesis simulation physical design techniques such as floorplanning or place and route or back annotation of physical design information The information presented here supplements the Synopsys synthesis reference manuals but does not replace them See other Synopsys documentation for details about topics not covered in this manual This manual supports version X 2005 09 of the Synopsys synthesis tools whether they are running under the UNIX operating system or the Linux operating system The main text of this manual describes UNIX operation Unless otherwise specified all features discussed in this manual are available in both XG mode and DB mode Features that are available only in a particular mode are marked as such Additionally all examples presented in this manual work in both XG mode and DB mode When the command syntax is the same in both XG mode dctcl command language and DB mode dctcl command language or dcsh command language the manual provides a single example preceded with the dc_shell xg t gt prompt When the command syntax differs the manual provides different examples as appropriate e The XG mode dctcl command language example is preceded by the dc_shell xg t gt p
173. hich is the process of converting a design description written in a hardware description language such as Verilog or VHDL into an optimized gate level netlist mapped to a specific technology library The steps in the synthesis process are as follows 1 3 4 The input design files for Design Compiler are often written using a hardware description language HDL such as Verilog or VHDL Design Compiler uses technology libraries synthetic or DesignWare libraries and symbol libraries to implement synthesis and to display synthesis results graphically During the synthesis process Design Compiler translates the HDL description to components extracted from the generic technology GTECH library and DesignWare library The GTECH library consists of basic logic gates and flip flops The DesignWare library contains more complex cells such as adders and comparators Both the GTECH and DesignWare libraries are technology independent that is they are not mapped to a specific technology library Design Compiler uses the symbol library to generate the design schematic After translating the HDL description to gates Design Compiler optimizes and maps the design to a specific technology library known as the target library The process is constraint driven Constraints are the designer s specification of timing and environmental restrictions under which synthesis is to be performed After the design is optimized it is ready for test synt
174. iable to false For example enter one of the following commands depending on your command language dc_shell xg t gt set auto wire load selection false dc_shell gt auto wire load selection false The technology library can also define a default wire load mode The default wire load mode library attribute identifies the default mode If the current library does not define a default mode Design Compiler looks for the attribute in the libraries specified in the link library variable To see the link library use the list command In the absence of a library default and an explicit specification Design Compiler uses that top mode To change the wire load model or mode specified in a technology library use the set_wire_load_model and set_wire_load_mode commands The wire load model and mode you define override all defaults Explicitly selecting a wire load model also disables area based wire load model selection for that design For example to select the 10x10 wire load model enter dc_shell xg t gt set_wire_load_model 10x10 To select the 10x10 wire load model and specify enclosed mode enter dc_shell xg t gt set wire load mode enclosed The wire load model you choose for a design depends on how that design is implemented in the chip Consult your semiconductor vendor to determine the best wire load model for your design Chapter 6 Defining the Design Environment 6 12 Use the report design or report t
175. ies a design in memory and renames the copy The new design has the same path and memory file as the original design dc_shell xg t gt copy design test test_new Information Copying design designs test ddc to designs test ddc test_new 1 dc_shell xg t gt list designs show file designs test ddc test test new You can use the copy_design command with the change_link command to manually create unique instances For example assume that a design has two identical cells U1 and U2 both linked to COMP Enter the following commands to create unique instances Copying Designs 5 29 dc_shell xg t gt copy design COMP COMP1 Information Copying design designs COMP ddc COMP to designs COMP ddc COMP1 dc_shell xg t gt change_link U1 COMP1 Performing change link on cell U1 dc_shell xg t gt copy design COMP COMP2 Information Copying design designs COMP ddc COMP to designs COMP ddc COMP2 dc_shell xg t gt change_link U2 COMP2 Performing change link on cell U2 Renaming Designs Use the rename design command to rename a design in memory In the following example the list designs command is used to show the design before and after rename design is used dc_shell xg t gt list designs show file designs test ddc test test new 1 dc_shell xg t gt rename design test new test new 1 Information Renaming design designs test ddc test_new to designs test ddc test_new_1 1 dc_shell x
176. ighly optimized and significant improvements in area or timing are unlikely In addition if the design being ungrouped has no timing violations the tool issues a message to indicate that delay based auto ungrouping will not be performed Delay based auto ungrouping attempts to improve the overall timing of the design by ungrouping those hierarchies that are most likely to benefit from the extra boundary optimizations that ungrouping provides Such hierarchies contain paths that are either critical or likely to become critical after subsequent optimization steps Delay based auto ungrouping thus offers a less CPU intensive alternative to ungroup a11 for improving design timing Cases in Which Auto Ungrouping Is Not Performed For both types of auto ungrouping a hierarchy is not ungrouped in the following cases e The wire load model for the hierarchy is different from the wire load model of the parent hierarchy Chapter 5 Working With Designs in Memory 5 42 warning message is issued to indicate that the user has specified different wire loads and the hierarchy cannot be ungrouped You can override this behavior by setting the compile auto ungroup override wim variable to true the default is false The ungrouped child cells of the hierarchy then inherit the wire load model of the parent hierarchy Consequently the child cells might have a more pessimistic wire load model To ensure that the cells that are ungrouped into diffe
177. ign not on the cell Design Compiler searches until it finds a matching object or it displays an error message if it does not find a matching object You can override the default search order by using the dcsh find command or the dctel get_ command to specify the object For example assume that the current design contains both a cell and a net named critical The following command sets the dont touch attribute on the cell because of the default search order dc_shell xg t gt set dont touch critical 1 In DB mode dcsh command language Design Compiler echoes the type of object on which an attribute is set If you do not want the echo set verbose_messages to false Chapter 5 Working With Designs in Memory 5 68 dc_shell gt set dont touch x Performing set dont touch on design X 1 Note The status message is not displayed in dctcl For predictable results use the get command to specify the object in dctcl To place the dont touch attribute on the net instead use one of the following commands depending on your command language dc_shell xg t gt set dont touch get nets critical 1 dc shell set dont touch find net critical Performing set dont touch on net critical 1 Working With Attributes 5 69 Chapter 5 Working With Designs in Memory 5 70 Defining the Design Environment Before a design can be optimized you must define the environment in which the design is expected to operate Y
178. ign contains seven modules at the top level Adder16 CascadeMod Comparator Multiply8x8 Multiply16x16 MuxMod and PathSegment Figure A 1 Block Diagram for the Design Example CascadeMod Adder8 Adder8 Adder16 Comparator Counter Comparator POUR MuxMod PathSegment x Multiply 16x16 ChipLevel Figure A 2 shows the hierarchy for the design example Appendix A Design Example A 2 Figure A 2 Hierarchy for the Design Example Adder16 CascadeMod comparator Manay Mop MuxMod PathSegment Adder8 Adder8 Comparator Counter The top level modules and the compilation strategies for optimizing them are Adder16 Uses registered outputs to make constraining easier Because the endpoints are the data pins of the registers you do not need to set output delays on the output ports CascadeMod Uses a hierarchical compile strategy The compile script for this design sets the constraints at the top level of CascadeMod before compilation The CascadeMod design instantiates the Adder8 design twice The script uses the compile once don t touch method for the Comparator module Comparator Is a combinational block The compile script for this design uses the virtual clock concept to show the use of virtual clocks ina design Design Description A 3 The ChipLevel design instantiates Comparator twic
179. ign is determined from the pins of the corresponding net To create a new subdesign by using the group command use its arguments and options as follows To do this Use this Specify a list of cells to be grouped into the Provide a list of cells as an new subdesign argument to the group command When the parent design is unique the list can include cells from a lower level in the hierarchy however these cells should be at the same level of hierarchy in relation to one another To exclude cells from the specified list use the except option Note In DB mode all cells to be grouped must be children of the current instance Specify the name of the new subdesign design_name Specify the new instance name optional cell_name If you do not specify an instance name Design Compiler creates one for you The created instance name has the format Un where nis an unused cell number for example U107 Chapter 5 Working With Designs in Memory 5 32 Note Grouping cells might not preserve all the attributes and constraints of the original cells The following examples illustrate how to use the group command Example 1 To group two cells into a new design named SAMPLE with an instance name U enter dc_shell xg t gt group ul u2 design name SAMPLE cell_name U Example 2 To group all cells that begin with alu into a new design uP with cell name UCELL enter dc_shell xg t gt group alu design name
180. ign rule fixing pre DRC2 and before starting area optimization pre area Design Compiler saves each checkpoint in a separate file Table 9 2 lists the default file name for each phase and the variable used to control each file name You can turn off checkpointing for any phase by setting the corresponding variable to none Table 9 2 Phase Based Checkpoint Files Phase Default file name Variable Pre delay CHECKPOINT PRE DELAY db compile checkpoint pre delay filename Pre DRC1 CHECKPOINT PRE DRC1 db compile checkpoint pre drc1 filename Chapter 9 Analyzing and Resolving Design Problems 9 6 Table 9 2 Phase Based Checkpoint Files Continued Phase Pre DRC2 Pre area Default file name CHECKPOINT PRE DRC2 db CHECKPOINT PRE AREA db Variable compile checkpoint pre drc2 filename compile checkpoint pre area filename Analyzing Design Problems Table 9 3 shows the design analysis commands provided by Design Compiler For additional information about these commands see the man pages Table 9 3 Commands to Analyze Design Objects Object Command Description Design report_design Reports design characteristics report_area Reports design size and object counts report_hierarchy Reports design hierarchy report_resources Reports resource implementations Instances report_cell Displays information about instances References report_reference Displays information about references Pins report_transitive_
181. ile it finds For example assume that you have technology libraries named my lib db in both the lib directory and the vhal directory If the search path contains in order the lib directory the vhdl directory and the default search path Design Compiler uses the my lib db file found in the lib directory because it encounters the lib directory first You can use the which command to see which library files Design Compiler finds in order Chapter 4 Working With Libraries 4 10 dc_shell xg t gt which my lib db usr lib my_lib db usr vhdl my_lib db Loading Libraries Design Compiler uses binary libraries db format for technology libraries and sdb format for symbol libraries and automatically loads these libraries when needed If your library is not in the appropriate binary format use the read lib command to compile the library source The read_lib command requires a Library Compiler license To manually load a binary library use the read file command dc_shell xg t gt read file my lib db dc_shell xg t gt read file my lib sdb Listing Libraries Design Compiler refers to a library loaded in memory by its name The library statement in the library source defines the library name To list the names of the libraries loaded in memory use the list 1ibs command dc_shell xg t gt list libs Logical Libraries Library File Path my lib my lib db synopsys libraries my symbol lib my l1lib sdb synopsys libraries
182. iler does not constrain any paths which end at an output port Use the set output delay command to define the required output arrival time You define the output delay constraint relative to the system clock If an input or output port has multiple timing requirements because of multiple paths use the add delay option to specify the additional timing requirements Use the report port command to list input or output delays associated with ports Use the remove input delay command to remove input delay constraints Use the remove output delay command to remove output delay constraints Chapter 7 Defining Design Constraints 7 14 Figure 7 3 shows the timing relationship between the delay and the active clock edge the rising edge in this example Figure 7 3 Relationship Between Delay and Active Clock Edge CLK __ DATA OUT Block A DATA_IN CLK DATA IN DATA_OUT 20 ns 15ns In the figure block A has an input DATA IN and an output DATA OUT From the waveform diagram DATA IN is stable 20 ns after the clock edge and DATA OUT needs to be available 15 ns before the clock edge After you set the clock constraint by using the create clock command use the set input delay and set output delay commands to specify these additional requirements For example enter dc_shell xg t gt set input delay 20 clock CLK DATA IN dc shell xg t5 set output delay 15 c
183. ill influence your directory structure The following figures show directory structures based on the top down compile strategy Figure 3 1 and the bottom up compile strategy Figure 3 2 For details about compile strategies see Selecting and Using a Compile Strategy on page 8 7 Figure 3 1 Top Down Compile Directory Structure Design src syn sim vhd V Synopsys dc setup work script log unmapped mapped netlist con rpt ddc ddc V SCr log vhd edif Managing the Design Data 3 3 Figure 3 2 Bottom Up Compile Directory Structure Design src syn sim vhd V synopsys dc setup work pass1 pass2 script log unmapped mapped netlist script log unmapped mapped netlist con rpt ddc ddc V con rpt ddc ddc V SCr log vhd SCr log vhd edif edif Partitioning for Synthesis Partitioning a design effectively can enhance the synthesis results reduce compile time and simplify the constraint and script files Partitioning affects block size and although Design Compiler has no inherent block size limit you should be careful to control block size If you make blocks too small you can create artificial boundaries that restrict effective optimization If you create very large blocks compile runtimes can be lengthy Use the following strategies to partition your design and improve optimization and runtimes e Partition for design reuse e Keep related combinational logic together
184. iming commands to see the wire load model and mode defined for the current design To remove the wire load model use the remove wire load model command with no model name Modeling the System Interface Design Compiler supports the following ways to model the design s interaction with the external system e Defining drive characteristics for input ports e Defining loads on input and output ports e Defining fanout loads on output ports The following sections discuss these tasks Defining Drive Characteristics for Input Ports Design Compiler uses drive strength information to buffer nets appropriately in the case of a weak driver Note Drive strength is the reciprocal of the output driver resistance and the transition time delay at an input port is the product of the drive resistance and the capacitance load of the input port By default Design Compiler assumes zero drive resistance on input ports meaning infinite drive strength There are three commands for overriding this unrealistic assumption e set driving cell Modeling the System Interface 6 13 e set drive e set input transition Both the set driving cell and set input transition commands affect the port transition delay but they do not place design rule requirements such as max fanout and max transition on input ports However the set driving cel1 command does place design rules on input ports if the driving cell has DRCs Note For heavily loaded dri
185. imum fanout greater than 3 0 say 16 0 the pin meets the fanout constraints Figure 7 1 Fanout Constraint Example t gt _ During optimization Design Compiler attempts to meet the fanout load restrictions for each driving pin If a pin violates its fanout load restriction Design Compiler tries to correct the problem for example by changing the drive strength of the component The technology library might specify default fanout constraints on the entire library or fanout constraints for specific pins in the library description of an individual cell Chapter 7 Defining Design Constraints 7 6 To determine whether your technology library is modeled for fanout calculations you can search for the fanout_load attribute on the cell input pins by entering one of the following commands depending on your command language dc_shell xg t gt get_attribute get_pins my_lib fanout_load dc_shell gt get attribute find pin my lib fanout load To set a more conservative fanout restriction than that specified in the technology library use the set max fanout command on the design or on an input port Use the set fanout load command to set the expected fanout load value for output ports Theset max fanout command sets the maximum fanout load for the specified input ports or for all the nets in a design by setting the max fanout attribute on the specified objects For example to set a max fanout requirement of 16 on a
186. include design files The link libraries contain the descriptions of cells library cells as well as subdesigns in a mapped netlist Link libraries include both local link libraries local link library attribute and system link libraries link library variable For more information about resolving references see Linking Designs on page 5 19 Chapter 4 Working With Libraries 4 4 e Calculating timing values and path delays The link libraries define the delay models that are used to calculate timing values and path delays For information about the various delay models see the Library Compiler documentation e Calculating power consumed For information about calculating power consumption see the Power Compiler Reference Manual Symbol Libraries Symbol libraries contain definitions of the graphic symbols that represent library cells in the design schematics Semiconductor vendors maintain and distribute the symbol libraries Design Compiler uses symbol libraries to generate the design schematic You must use Design Vision to view the design schematic When you generate the design schematic Design Compiler performs a one to one mapping of cells in the netlist to cells in the symbol library DesignWare Libraries A DesignWare library is a collection of reusable circuit design building blocks components that are tightly integrated into the Synopsys synthesis environment Understanding the Library Requireme
187. ining Design Constraints In addition to specifying the design environment you must set design constraints before compiling the design There are two categories of design constraints e Design rule constraints e Design optimization constraints Design rule constraints are supplied in the technology library you specify They are referred to as the implicit design rules These rules are established by the library vendor and for the proper functioning of the fabricated circuit they must not be violated You can however specify stricter design rules if appropriate The rules you specify are referred to as the explicit design rules Design optimization constraints define timing and area optimization goals for Design Compiler These constraints are user specified Design Compiler optimizes the synthesis of the design in 7 1 accordance with these constraints but not at the expense of the design rule constraints That is Design Compiler attempts never to violate the higher priority design rules Note In this chapter setting explicit design rules and optimization constraints is discussed without reference to the particular compile strategy you choose But the compile strategy you choose does influence your constraint settings This chapter contains the following sections e Setting Design Rule Constraints e Setting Optimization Constraints e Verifying the Precompiled Design The task of setting timing constraints can be complic
188. instantiated designs multiple_designs along with instance names by default warning messages related to multiply instantiated designs are suppressed Chapter 9 Analyzing and Resolving Design Problems 9 2 Note The multiple_designs option is not available in DB mode Analyzing Your Design During Optimization Design Compiler provides the following capabilities for analyzing your design during optimization e It lets you customize the compile log e It lets you save intermediate design databases The following sections describe these capabilities Customizing the Compile Log The compile log records the status of the compile run Each optimization task has an introductory heading followed by the actions taken while that task is performed There are four tasks in which Design Compiler works to reduce the compile cost function e Delay optimization e Design rule fixing phase 1 e Design rule fixing phase 2 e Area optimization While completing these tasks Design Compiler performs many trials to determine how to reduce the cost function For this reason these tasks are collectively known as the trials phase of optimization Analyzing Your Design During Optimization 9 3 By default Design Compiler logs each action in the trials phase by providing the following information e Elapsed time e Design area e Worst negative slack e Total negative slack e Design rule cost e Endpoint being worked on You can custom
189. int report generated by the command sequences shown in Table 9 6 Table 9 6 report constraint Examples dcsh Command Sequence dctcl Command Sequence set_drive 0 find port IN set_drive 0 get_ports IN set_load 0 find port OUT set_load 0 get_ports OUT report_constraint report_constraint Resolving Specific Problems 9 17 Example 9 5 Constraint Report kkxkxkxkxkxkxkxkxkxkxkxkxkxkkkkkkkkkkkkxkkkkkkkkkkkkxkxk Report constraint Design buffer_example Version 1999 05 Date Mon Jan 4 10 56 49 1999 kkxkxkxkxkxkxkxk xkxkxkxk xkxkxkxkxkkxkkxkkxkkxkkxkkxkkxkkxkkkkxkxkxk Constraint Cost max_transition 0 00 MET max_fanout 0 00 MET To see the constraint cost functions used by Design Compiler specify the verbose option of the report_constraint command shown in Example 9 4 Example 9 6 Constraint Report verbose KEKEKEKKKEKKKKKKKKK KKK KKK KKK KKK KKK KKK KEKE Report constraint verbose Design buffer example Version 1999 05 Date Mon Jan 4 10 56 49 1999 KKIKKKKKKKKKKKKKKKKKKKKKKkKKkKAkkkkkkkkkkk Net OUT max transition 2 50 Transition Time 0 00 Slack 2 50 MET Net OUT max fanout 3 00 Fanout 0 00 Slack 3 00 MET Chapter 9 Analyzing and Resolving Design Problems 9 18 The verbose constraint report shows that two constraints are measured e Maximum transition time 2 50 e Maximum fanout load 3 00 Design Compiler derives the constraint values from the attribute values o
190. into larger blocks Figure 8 2 shows an example of the mixed compilation strategy Figure 8 2 Mixing Compilation Strategies Specification has detailed time budgets for first level of hierarchy A B C and D Li Top down compile is used for hierarchy below D Bottom up compile is used for hierarchy below B Resolving Multiple Instances of a Design Reference In a hierarchical design subdesigns are often referenced by more than one cell instance that is multiple references of the design can occur For example Figure 8 3 shows the design TOP in which design C is referenced twice U2 U3 and U2 U4 Chapter 8 Optimizing the Design 8 20 Figure 8 3 Multiple Instances of a Design Reference TOP U2 Top level design U1 with instances B A U3 U4 U5 7 C D 7 Pd a RE wwe a hi L7 Zo f Design Compiler memory A C D loaded designs The following methods are available for handling designs with multiple instances e The uniquify method In earlier releases you had manually to run the uniquify command to create a uniquely named copy of the design for each instance However beginning with version V 2004 06 the tool automatically uniquifies designs as part of the compile process Note that you can still manually force the tool to uniquify designs before compile by running the uni qui fy command but this step con
191. ints remove design all source S script_path recompile tcl current design ChipLevel if shell is in xg mode 0 write hier out S db path ChipLevel final db else write f ddc hier out S ddce path ChipLevel final ddc Appendix A Design Example A 16 Example A 16 initial compile tcl Initial compile with estimated constraints source S script_path read tcl current design ChipLevel source S script_path defaults con source S script path adder16 tcl source S script path cascademod tcl source S script_path comp16 tcl source S script_path mult8 tcl source S script path mult16 tcl source S script_path muxmod tcl source S script_path pathseg tcl Example A 17 adder16 tcl Script file for constraining Adder16 set rpt file adderl6 rpt set design adder16 current design Adder16 source S script_path defaults con Define design environment set load 2 2 sout set load 1 5 cout set driving cell lib cell FD1 all inputs set drive 0 Sclk name Define design constraints set input delay 1 35 clock Scilk name ain bin set input delay 3 5 clock Sclk name cin set max area 0 compile if shell is in xg mode 0 write hier o S db path s design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl Compile Scripts A 17 Example A 18 cascademod tcl Script file for constraining CascadeMod Constraints a
192. ion specific to the vendors process The models include coefficients for area capacitance and resistance per unit length and a fanout to length table for estimating net lengths the number of fanouts determines a nominal length Note You can also develop custom wire load models For more information about developing wire load models see the Library Compiler documentation Defining Wire Load Models 6 5 In the absence of back annotated wire delays Design Compiler uses the wire load models to estimate net wire lengths and delays Design Compiler determines which wire load model to use for a design based on the following factors listed in order of precedence 1 Explicit user specification 2 Automatic selection based on design area 3 Default specification in the technology library If none of this information exists Design Compiler does not use a wire load model Without a wire load model Design Compiler does not have complete information about the behavior of your target technology and cannot compute loading or propagation times for your nets therefore your timing information will be optimistic In hierarchical designs Design Compiler must also determine which wire load model to use for nets that cross hierarchical boundaries The tool determines the wire load model for cross hierarchy nets based on one of the following factors listed in order of precedence 1 Explicit user specification 2 Default specification in t
193. ipt_path report tcl source S script path mult16 wtcl compile ungroup all if shell is in xg mode 0 write hier o S db path mult16 wtcl db else write f ddc hier o S ddc_path mult16_wtcl ddc set rpt file mult16_wtcl rpt source S script_path report tcl report timing requirements ignore gt gt S log path s rpt file source S script path muxmod wtcl compile if shell is in xg mode 0 write hier o S db_path muxmod_wtcl db else write f ddc hier o S ddc_path muxmod_wtcl ddc set rpt file muxmod_wtcl rpt source S script_path report tcl Appendix A Design Example A 26 Example A 25 recompile tcl Continued source S script_path pathseg wtcl compile if shell is in xg mode 0 write hier o S db_path pathseg_wtcl db else write f ddc hier o S ddc_path pathseg_wtcl ddc set rpt file pathseg wtcl rpt source S script_path report tcl report timing requirements ignore gt gt Silog path s rpt file Example A 26 report tcl This script file creates reports for all modules set maxpaths 15 check design gt S log path s rpt file report area gt gt S log path s rpt file report design gt gt Silog path s rpt file report cell gt gt S log path s rpt file report reference gt gt Silog path s rpt file report port verbose gt gt S log path s rpt file report net gt gt Silog path s rpt file report com
194. ize the trials phase output by setting the compile log format variable Table 9 1 lists the available data items and the keywords used to select them For more information about customizing the compile log see the man page for the compile log format variable Table 9 1 Compile Log Format Keywords Column Column header Keyword Column description Area AREA area Shows the area of the design CPU seconds CPU SEC cpu Shows the process CPU time used in seconds Design rule DESIGN RULE COST drc Measures the difference cost between the actual results and user specified design rule constraints Elapsed time ELAPSED TIME elap_time Tracks the elapsed time since Chapter 9 Analyzing and Resolving Design Problems 9 4 the beginning of the current compile or reoptimization of the design Table 9 1 Compile Log Format Keywords Continued Column Column header Keyword Column description Endpoint ENDPOINT endpoint Shows the endpoint being worked on When delay violations are being fixed the endpoint is a cell or a port When design rule violations are being fixed the endpoint is anet When area violations are being fixed no endpoint is printed Maximum delay MAX DELAY COST max_delay Shows the maximum delay cost cost of the design Megabytes of MBYTES mem Shows the process memory memory used in MB Minimum delay MIN DELAY COST min_delay Shows the minimum delay cost cost of the design Path group PATH GROUP group_path Sho
195. l s subdesign and recompile using the saved script of characterization data 10 Read in all other compiled subdesigns 11 Link the current subdesign 12 Choose another subdesign and repeat steps 3 through 9 until you have recompiled all subdesigns using their actual environments Chapter 8 Optimizing the Design 8 14 When applying the bottom up compile strategy consider the following The read_file command runs most quickly with the ddc format or the db format in DB mode If you will not be modifying your RTL code after the first time you read or elaborate it save the unmapped design to a ddc or db file This will save time when you reread the design The compile command affects all subdesigns of the current design If you want to optimize only the current design you can remove or not include its subdesigns in your database or you can place the dont touch attribute on the subdesigns by using the set_dont_touch command In XG mode the subdesign constraints are not preserved after you perform a top level compile To ensure that you are using the correct constraints always reapply the subdesign constraints before compiling or analyzing a subdesign A bottom up compile script for the TOP design is shown in Example 8 5 on page 8 16 dcsh and Example 8 6 on page 8 18 dctcl Both scripts contain comments that identify each of the steps in the bottom up compile strategy In these scripts it is assumed that
196. l_porosity Performing Design Exploration In Design exploration you use the default synthesis algorithm to gauge the design performance against your goals To invoke the default synthesis algorithm use the compile command with no options dc_shell xg t gt compile The default compile uses the map effort medium option of the compile command and the default settings of the structuring and flattening attributes The default area effort of the area recovery phase of the compile is the specified value of the map_effort option You can change the area effort by using the area_effort option If the performance violates the timing goals by more than 15 percent you should consider whether to refine the design budget or modify the HDL code Chapter 8 Optimizing the Design 8 40 Performing Design Implementation The default compile generates good results for most designs If your design meets the optimization goals after design exploration you are finished If not try the techniques described in the following sections Optimizing Random Logic Optimizing Structured Logic Optimizing Structured Logic Optimizing for Maximum Performance Optimizing for Minimum Area Optimizing Data Paths Optimizing Random Logic If the default compile does not give the desired result for your random logic design try the following techniques If the first technique does not give the desired results use the second technique and so on until you
197. lacing a subdesign with an interface logic model can greatly reduce the memory requirements for the subdesign instantiation in the top level design For information about how to generate and use interface logic models see the Interface Logic Model User Guide Selecting and Using a Compile Strategy 8 9 The top down compile strategy has these advantages e Provides a push button approach e Takes care of interblock dependencies automatically On the other hand the top down compile strategy requires more memory and might result in longer runtimes for designs with over 100K gates To implement a top down compile carry out the following steps Note If your top level design contains one or more interface logic models use the compile flow described in the Interface Logic Model User Guide 1 Read in the entire design 2 Resolve multiple instances of any design references A design that is referenced by more than one instantiated block or cell must be resolved Otherwise Design Compiler cannot compute which environmental attributes and constraints to apply to the design during optimization To learn how to deal with this problem see Resolving Multiple Instances of a Design Reference on page 8 20 3 Apply attributes and constraints to the top level Attributes and constraints implement the design specification For information about attributes see Working With Attributes on page 5 62 For information about constrai
198. lculating cost 8 34 maximum performance optimization 8 47 messages control echoing to screen 5 68 disabling 9 12 Milkyway format 5 9 reading 5 14 Milkyway format saving 5 55 minimization defined 8 42 enabling 8 42 minimum area optimization 8 56 minimum delay calculating cost 8 37 minimum porosity calculating cost 8 39 mixed compile strategy 8 19 modes DB 2 7 IN 11 XG 2 7 Module Compiler defined 1 7 modules guidelines HDL 3 33 multicycle path 7 22 multiple clock considerations 7 12 multiple instances of a design resolving 8 20 multiple instances resolving compile command automatic uniquify 8 22 compile once don t touch method 8 25 ungroup method 8 27 uniquify method 8 22 multiplexers inferring 3 15 HDL Compiler 3 15 N name changing net or port 5 57 naming conventions file name extensions 3 2 library objects 4 12 signal name suffixes 3 30 naming translation 5 57 net attributes C 5 net capacitance See capacitance net names changing name rules 5 57 netlist editing 5 47 reading 2 21 netlist reader 2 21 nets 5 6 connecting 5 47 creating 5 44 5 47 IN 12 disconnecting 5 47 heavily loaded fixing 8 51 reporting 5 25 networks 5 6 O operating conditions defining 6 3 list of current design 6 5 technology library 6 4 optimization across hierarchical boundaries 8 59 architectural 8 2 Boolean 8 57 boundary 8 59 cost function 8 31 data paths 8 61 defined 2 2 gate level 8 6 gate level 8
199. ld using your standard set of scripts 3 Apply name changes and resolve naming issues Use the change_names command and its Verilog or VHDL switch before you write the design Saving Designs 5 59 Important Always use the change names rules verilog vhdl hierarchy command whenever you want to write out a Verilog or VHDL design because naming in the design database file is not Verilog or VHDL compliant For example enter change_names rules verilog hierarchy Important If you need to change the bus naming style you must first define the new bus naming style using the define_name_rules command and identify the bus naming style of the current design before you use the change_names command to define the new bus naming style rule For example to change the bus naming style from s d to S_ d enter one of the following command sequences depending on your command language dc_shell xg t gt define name rules new bus naming style N target bus naming style s_ Xd dc_shell xg t gt set bus naming style s d dc_shell xg t gt change names rule new bus naming style hierarchy or dc_shell gt define name rules new bus naming style target bus naming style s Xd dc shell bus naming style s d dc shell change names rule new bus naming style hierarchy Write files to disk Use the write format verilog command Look for reported name changes which indicate you need t
200. le dctcl Example all_fanin to all_critical_pins set cp_logic all_fanin only_cells to all critical pins cp logic dc shell status only cells group design critical block N group design critical block N cell name cp1 cp logic cel11 name cpl Scp logic characterize cpl characterize cpl current design critical block current design critical block set flatten true set flatten true compile compile set flatten false set flatten false current design current design ungroup simple names cpl ungroup simple names cpl Performing Design Implementation 8 53 Automatically Ungrouping Hierarchies on the Critical Path Automatically ungrouping hierarchies during compile can often improve performance Ungrouping removes hierarchy boundaries and allows Design Compiler to optimize over a larger number of gates generally improving timing You use delay based auto ungrouping to ungroup hierarchies along the critical path To use the auto ungroup capability you must use the compile command option auto_ungroup delay For more information on auto ungrouping See Ungrouping Hierarchies Automatically During Optimization on page 5 40 Performing a High Effort Compile The optimization result depends on the starting point Occasionally the starting point generated by the default compile results in a local minimum solution and Design Compiler quits before generating an optimal design A high effort compile might solve thi
201. library cells by Excluding cells from the target library e Specifying cell preferences Excluding Cells From the Target Library Use the set dont use command to exclude cells from the target library Design Compiler does not use these excluded cells during optimization Directing Library Cell Usage 4 13 This command affects only the copy of the library that is currently loaded into memory and has no effect on the version that exists on disk However if you save the library the exclusions are saved and the cells are permanently disabled For example to prevent Design Compiler from using the high drive inverter INV_HD enter dc_shell xg t gt set dont use MY LIB INV HD 1 Use the remove attribute command to reinclude excluded cells in the target library dc shel1 xg t5 remove attribute MY LIB INV HD dont use MY LIB INV HD Specifying Cell Preferences Use the set prefer command to indicate preferred cells You can issue this command with or without the min option Use the command without the min option if you want Design Compiler to prefer certain cells during the initial mapping of the design e Set the preferred attribute on particular cells to override the default cell identified by the library analysis step This step occurs at the start of compilation to identify the starting cell size for the initial mapping e Set the preferred attribute on cells if you know the preferred starting size of the complex cells
202. ling increased capacity Although you can use the db format in XG mode it is not What s New in This Release xvii Preface xviii recommended To maximize the capacity and performance improvements offered in XG mode use the ddc format rather than the db format Additionally to save a design in the db format you must use the xg force db option as shown in the following example dc_shell xg t gt write format db xg force db design file db Design Compiler then generates the db file but also displays a message that this capability will be removed in a future release If you do not use the xg_force_db option Design Compiler displays an error message For more information see Chapter 5 of this manual Reading and writing the Milkyway database In XG mode Design Compiler allows you to read and write a Milkyway database within Design Compiler for use with other Synopsys Galaxy platform tools such as JupiterXT and Astro You do this by using the read_milkyway and write_milkyway commands For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Chapter 7 Improvements in Quality of Results Design Compiler version X 2005 09 yields significant improvements in runtime and quality of results QoR compared to version W 2004 12 These improvements are a result of the following Global optimization technology e Improved XOR sharing e MUX OP inference and optimization e Hi
203. ll nets in the design adder enter one of the following commands depending on your command language dc_shell xg t gt set max fanout 16 get designs adder dc shell set max fanout 16 find design adder If you use the set max fanout command and a library max fanout attribute exists Design Compiler tries to meet the smaller more restrictive fanout limit Setting Design Rule Constraints 7 7 To undo a set_max_fanout command use the remove_attribute command For example enter one ofthe following commands depending on your command language dc_shell gt remove attribute find design adder max fanout dc_shell xg t gt remove attribute get designs adder max fanout Setting Capacitance Constraints The transition time constraints do not provide a direct way to control the actual capacitance of nets If you need to control capacitance directly use the set_max_capacitance command to set the maximum capacitance constraint on input ports or designs This constraint is completely independent so you can use it in addition to the transition time constraints Design Compiler and Library Compiler model capacitance restrictions by associating the max_capacitance attribute with the output ports or pins of a cell Design Compiler calculates the Capacitance on a net by adding the wire capacitance of the net to the capacitance of the pins attached to the net To determine whether a net meets the capacitance constraint Design Compiler
204. ll timing path groups in the current design report_port Lists information about ports in the current design report_qor Displays information about the quality of results and other statistics for the current design Appendix B Basic Commands B 6 report resources Displays information about the resource implementation report timing Lists timing information for the current design report timing requirements Lists timing path requirements and related information report transitive fanin Lists the fanin logic for selected pins nets or ports of the current instance report transitive fanout Lists the fanout logic for selected pins nets or ports of the current instance Commands for Analyzing and Resolving Design Problems B 7 Appendix B Basic Commands B 8 Predefined Attributes This appendix contains tables that list the Design Compiler predefined attributes for each object type Table C 1 Clock Attributes Attribute name Value dont_touch_network fall delay fix_hold max_time_borrow minus_uncertainty period plus uncertainty propagated_clock true false float true false float float float float true false Table C 1 Clock Attributes Continued Attribute name rise delay Table C 2 Design Attributes Attribute name Value actual max net capacitance actual min net capacitance boundary optimization default flip flop type default flip flop t
205. lls designs libraries library cells library cell pins nets pins and ports Specifying Design Objects You can specify design objects by using either a relative path or an absolute path Using a Relative Path If you use a relative path to specify a design object the object must be in the current design Specify the path relative to the current instance The current instance is the frame of reference within the current design By default the current instance is the top level of the current design Use the current_instance command to change the current instance For example to place a dont_touch attribute on hierarchical cell U1 U15 in the Count_16 design you can enter either dc_shell xg t gt current_design Count_16 Specifying Design Objects 5 25 Current design is Count _16 Count 16 dc shell xg t5 set dont touch U1 U15 or dc_shell xg t gt current design Count 16 Current design is Count 16 Count 16 dc_shell xg t gt current instance Ul Current instance is Count 16 U1 Count 16 U1 dc shell xg t5 set dont touch U15 1 In the first command sequence the frame of reference remains at the top level of design Count 16 In the second command sequence the frame of reference changes to instance U1 Design Compiler interprets all future object specifications relative to instance U1 To reset the current instance to the top level of the current design enter the current instance command without
206. lock CLK DATA OUT Figure 7 4 illustrates the timing requirements for the constrained design block my block Example 7 1 shows the script used to specify these timing requirements Setting Optimization Constraints 7 15 Figure 7 4 Timing Requirements for my block 10 4 ns 1 6ns min min_path hold qA 0 4 ns clka gt Thold in clk gt Q 1 4 ns Gi max max path setup NG 4 ns 0 8 ns clkb gt T setup Example 7 1 Timing Constraints for my block create clock period 20 waveform 5 15 clka create clock period 30 waveform 10 25 cikb set input delay 10 4 clock clka inl set input delay 6 4 clock clkb add delay inl set output delay 1 6 clock clka min outl set output delay 4 8 clock clka max out1 Specifying Combinational Path Delay Requirements For purely combinational delays that are not bounded by a clock period use the set max delay and set min delay commands to define the maximum and minimum delays for the specified paths A common way to produce this type of asynchronous logic in HDL code is to use asynchronous sets or resets on latches and flip flops Because the reset signal crosses several blocks constrain this signal at the top level For example to specify a maximum delay of 5 on the RESET signal enter dc shell xg t5 set max delay 5 from RESET Chapter 7 Defining Design Constraints 7 16 To specify a minimu
207. lowing characteristics e Requires more memory and takes longer to compile than the compile once don t touch method e Provides the best synthesis results The obvious drawback in using the ungroup method is that it removes the user defined design hierarchy Preserving Subdesigns The set_dont_touch command preserves a subdesign during optimization It places the dont_touch attribute on cells nets references and designs in the current design to prevent these objects from being modified or replaced during optimization Chapter 8 Optimizing the Design 8 28 Note Any interface logic model present in your design is automatically marked as dont_touch Also the cells of an interface logic model are marked as dont_touch For information about interface logic models see the nterface Logic Model User Guide Use the set_dont_touch command on subdesigns you do not want optimized with the rest of the design hierarchy The dont_touch attribute does not prevent or disable timing through the design When you use set_dont_touch remember the following points Setting dont touch on a hierarchical cell sets an implicit dont_touch on all cells below that cell Setting dont touch on a library cell sets an implicit dont_touch on all instances of that cell Setting dont touch on a net sets an implicit dont_touch only on mapped combinational cells connected to that net If the net is connected only to generic logic optimization might rem
208. ls About Designs Designs are circuit descriptions that perform logical functions Designs are described in various design formats such as VHDL Verilog HDL state machine and EDIF Logic level designs are represented as sets of Boolean equations Gate level designs such as netlists are represented as interconnected cells Designs can exist and be compiled independently of one another or they can be used as subdesigns in larger designs Designs are flat or hierarchical Flat Designs Flat designs contain no subdesigns and have only one structural level They contain only library cells Hierarchical Designs A hierarchical design contains one or more designs as subdesigns Each subdesign can further contain subdesigns creating multiple levels of design hierarchy Designs that contain subdesigns are called parent designs Design Terminology 5 3 Design Objects Figure 5 1 shows the design objects in a design called TOP Synopsys commands attributes and constraints are directed toward specific design objects Figure 5 1 Design Objects Design Port Instance or Net Pin Cell Ha UNG CIN C o1 BUSI D INV1 a gt DIN S ENCODER REGFILE AIN gt OUT 1 0 U3 Design TOP ENCODER REGFILE Reference ENCODER REGFILE INV Instance U1 U2 U3 U4 Design A design consists of instances nets ports and pins It can contain subdesigns and
209. ls to meet timing goals by more than 15 percent modify your design goals and constraints or improve the HDL code Then repeat both design exploration and functional simulation In functional simulation determine whether the design performs the desired functions by using an appropriate simulation tool If the design does not function as required you must modify the HDL code and repeat both design exploration and functional simulation Continue performing design exploration and functional simulation until the design is functioning correctly and is within 15 percent of the timing goals Perform design implementation synthesis by using Design Compiler to meet design goals The High Level Design Flow 2 5 4 After synthesizing the design into a gate level netlist verify that the design meets your goals If the design does not meet your goals generate and analyze various reports to determine the techniques you might use to correct the problems After the design meets functionality timing and other design goals complete the physical design either in house or by sending it to your semiconductor vendor Analyze the physical design s performance by using back annotated data If the results do not meet design goals return to step 3 If the results meet your design goals you are finished with the design cycle Running Design Compiler This section provides the basic information you need to run Design Compiler It includes
210. ltibit compiler directive to bused signals to infer multibit components You can also change between a single bit and a multibit implementation after optimization by using the create_multibit and remove_multibit commands For more information about how Design Compiler handles multibit components see the Design Compiler Reference Manual Optimization and Timing Analysis Using Synthetic Libraries To help you achieve optimal performance Synopsys supplies a synthetic library This library contains efficient implementations for adders incrementers comparators and signed multipliers Design Compiler selects a synthetic component to meet the given constraints After Design Compiler assigns the synthetic structure you can always change to another type of structure by modifying your constraints If you ungroup the synthetic cells or write the netlist to a text file however Design Compiler can no longer recognize the synthetic component and cannot perform implementation reselection Chapter 3 Preparing Design Files for Synthesis 3 18 The HDL Compiler documentation contains additional information about using compiler directives to control synthetic component use The DesignWare Foundation Library Databook volumes contain additional information about synthetic libraries and provide examples of how to infer and instantiate synthetic components Example 3 1 and Example 3 2 use the label ops map_to_module and implementation compiler dir
211. m delay of 10 on the path from IN1 to OUT1 enter dc_shell xg t gt set min delay 10 from IN1 to OUT1 Use the report_timing_requirements command to list the minimum delay and maximum delay requirements for your design Specifying Timing Exceptions Timing exceptions define timing relationships that override the default single cycle timing relationship for one or more timing paths Use timing exceptions to constrain or disable asynchronous paths or paths that do not follow the default single cycle behavior Note Specifying numerous timing exceptions can increase the compile runtime Nevertheless some designs can require many timing exceptions Design Compiler recognizes only timing exceptions that have valid reference points e The valid startpoints in a design are the primary input ports and the clock pins of sequential cells e The valid endpoints are the primary output ports of a design and the data pins of sequential cells Design Compiler does not generate a warning message if you specify invalid reference points You must use the ignored option of the report_timing_requirements command to find timing exceptions ignored by Design Compiler Setting Optimization Constraints 7 17 You can specify the following conditions by using timing exception commands e False paths set false path e Minimum delay requirements set min delay e Maximum delay requirements set max delay e Multicycle paths set multicycle path
212. mands Used to Define the Optimization Constraints for Sequential Blocks set_max_area set_input_delay set_output_delay create_clock set_clock_latency set_propagated_clock set_clock_uncertainty t Setting Timing Constraints Timing constraints specify the required performance of the design To set the timing constraints 1 Define the clocks 2 Specify the I O timing requirements relative to the clocks 3 Specify the combinational path delay requirements 4 Specify the timing exceptions Table 7 2 lists the most commonly used commands for these steps Table 7 2 Commands to Set Timing Constraints Command Description create_clock Defines the period and waveform for the clock set_clock_latency Defines the clock delay set_propagated_clock set_clock_uncertainty Chapter 7 Defining Design Constraints 7 10 Table 7 2 Commands to Set Timing Constraints Continued Command set_input_delay set_output_delay set_max_delay set_min_delay set_false_path set_multicycle_path Description Defines the timing requirements for input ports relative to the clock period Defines the timing requirements for output ports relative to the clock period Defines maximum delay for combinational paths This is a timing exception command Defines minimum delay for combinational paths This is a timing exception command Specifies false paths This is a timing exception command Specifies
213. mation about the search order see The Object Search Order on page 5 68 Saving Attribute Values Design Compiler does not automatically save attribute values when you exit dc_shell Use the write_script command to generate a dc_shell script that re creates the attribute values Note The write_script command does not support user defined attributes By default write_script prints to the screen Use the redirection operator gt to redirect the output to a file dc_shell xg t gt write_script gt attr scr Defining Attributes The set_attribute command enables you to create new attributes Use the set attribute command described in Using the set attribute Command on page 5 64 If you want to change the value of an attribute remove the attribute and then re create it to store the desired type Removing Attributes To remove a specific attribute from an object use the remove attribute command Chapter 5 Working With Designs in Memory 5 66 You cannot use the remove_attribute command to remove inherited attributes For example if a dont_touch attribute is assigned to a reference remove the attribute from the reference not from the cells that inherited the attribute For example to remove the max_fanout attribute from port OUT7 enter dc_shell xg t gt remove_attribute OUT7 max_fanout You can remove selected attributes by using the remove_ commands Note that some attributes still require the set_
214. mbinational true false is hierarchical true false is mapped true false is sequential true false is unmapped true false ungroup true false Appendix C Predefined Attributes C 6 Glossary annotation A piece of information attached to an object in the design such as a capacitance value attached to a net the process of attaching such a piece of information to an object in the design back annotate To update a circuit design by using extraction and other post processing information that reflects implementation dependent characteristics of the design such as pin selection component location or parasitic electrical characteristics Back annotation allows a more accurate timing analysis of the final circuit The data is generated by another tool after layout and passed to the synthesis environment For example the design database might be updated with actual interconnect delays these delays are calculated after placement and routing after exact interconnect lengths are known cell See instance clock A source of timed pulses with a periodic behavior A clock synchronizes the propagation of data signals by controlling sequential elements such as flip flops and registers in a digital circuit You define clocks with the create_clock command GL 1 GL 2 Clocks you create by using the create clock command ignore delay effects of the clock network Therefore for accurate timing analysis you describe the cl
215. meet area and timing goals There are two categories of design constraints design rule constraints and design optimization constraints e Design rule constraints are supplied in the technology library For proper functioning of the fabricated circuit they must not be violated e Design optimization constraints define timing and area optimization goals Design Compiler optimizes the synthesis of the design in accordance with both sets of constraints however design rule constraints have higher priority false path A path that you do not want Design Compiler to consider during timing analysis An example of such a path is one between two multiplexed blocks that are never enabled at the same time that is a path that cannot propagate a signal You use the set_false_path command to disable timing based synthesis on a path by path basis The command removes timing constraints on the specified path fanin The pins driving an endpoint pin port or net also called sink A pin is considered to be in the fanin of a sink if there is a timing path through combinational logic from the pin to the sink Fanin tracing starts at the clock pins of registers or valid startpoints Fanin is also known as transitive fanin You use the report_transitive_fanin command to report the fanin of a specified sink pin port or net fanout The pins driven by a source pin port or net A pin is considered to be in the fanout of a source if there is a
216. mes use the define name rules and change names commands Naming Rules Section of the synopsys dc setup File Table 5 9 shows sample naming rules as created by a specific layout tool vendor These naming rules do the following e Set the bus naming format to bus name N or bus namen N e Limit object names to alphanumeric characters Saving Designs 5 57 e Change DesignWare cell names to valid names changes cell to U and return to RET Your vendor might use different naming conventions Check with your vendor to determine the naming conventions you need to follow Table 5 9 Naming Rules Section of synopsys_dc setup File dcsh Syntax bus_naming_style s_ d define_name_rules simple names allowed A Za z0 9_ last_restricted _ first_restricted _ map cell U return RET dctcl Syntax set bus_naming_style s_ d define_name_rules simple_names allowed A Za z0 9_ last_restricted _ first_restricted _ map cell U return RET Using the define_name_rules map Command Example 5 1 shows how to use the map option with define name rules to avoid an error in the format of the string If you do not follow this convention an error appears Example 5 1 Using define name rules map define name rules naming convention map stringl string2 type cell For example to remove trailing underscor
217. mization is enabled your compile log displays the following message Information Datapath optimization is enabled DP 1 hlo_disable_datapath_ Set to true to disable only the DC Ultra datapath optimization optimization feature of DC Ultra The default is false Note DC Ultra datapath optimization requires both the DC Ultra Features license and the DesignWare Foundation license The foundation license is pulled when you compile To run DC Ultra if you do not have the foundation license you must set hlo_disable_datapath_optimization to true otherwise an error is returned For additional information on these commands see the man pages Chapter 8 Optimizing the Design 8 76 Table 8 12 summarizes the conditions that enable and disable DC Ultra datapath optimization Table 8 12 Conditions That Enable and Disable Datapath Optimization set_ultra_optimization hlo_disable_datapath_optimization Datapath optimization enabled yes or no true false yes true true no false false no false true no Using DC Ultra Datapath Optimization 8 77 Chapter 8 Optimizing the Design 8 78 Analyzing and Resolving Design Problems Use the reports generated by Design Compiler to analyze and debug your design You can generate reports both before and after you compile your design Generate reports before compiling to check that you have set attributes constraints and design rules properly Generate reports after compiling to analyze th
218. mmand to modify the hierarchy separator you might lose attribute and constraint information The following examples illustrate how to use the ungroup command Example 1 To ungroup a list of cells enter dc shel1 xg t5 ungroup high decoder cell low decoder cell Changing the Design Hierarchy 5 37 Example 2 To ungroup the cell U1 and specify the prefix to use when creating new cells enter dc_shell xg t gt ungroup U1 prefix Ul Example 3 To completely collapse the hierarchy of the current design enter dc_shell xg t gt ungroup all flatten Example 4 To recursively ungroup cells belonging to CELL_X which is three hierarchical levels below the current design enter dc_shell xg t gt ungroup start_level 3 CELL X Example 5 To recursively ungroup cells that are three hierarchical levels below the current design and belong to cells U1 and U2 U1 and U2 are child cells of the current design enter dc_shell xg t gt ungroup start_level 2 U1 U2 Example 6 To recursively ungroup all cells that are three hierarchical levels below the current design enter dc_shell xg t gt ungroup start_level 3 all Chapter 5 Working With Designs in Memory 5 38 Example 7 This example illustrates how the ungroup command can accept instance objects cells at a lower level of hierarchy when the parent design is unique In the example MID1 BOT1 is a unique instantiation of design BOT The command ungroups t
219. multicycle paths This is a timing exception command The following sections describe these steps in more detail Defining a Clock For synchronous designs the clock period is the most important constraint because it constrains all register to register paths in the design Defining the Period and Waveform for the Clock Use the create clock command to define the period period option and waveform waveform option for the clock If you do not specify the clock waveform Design Compiler uses a 50 percent duty cycle Setting Optimization Constraints 7 11 Use the create clock command on a pin or a port For example to specify a 25 megahertz clock on port clk with a 50 percent duty cycle enter dc_shell xg t gt create clock clk period 40 When your design contains multiple clocks pay close attention to the common base period of the clocks The common base period is the least common multiple of all the clock periods For example if you have clock periods of 10 15 and 20 the common base period is 60 Define your clocks so that the common base period is a small integer multiple of each of the clock periods The common base period requirement is qualitative no hard limit exists If the base period is more than 10 times larger than the smallest period however long runtimes and greater memory requirements can result As an extreme case if you have a register to register path where one register has a period of 10 and t
220. n 8 43 The command syntax is int compile ultra scan no_uniquify no boundary _ optimization no_autoungroup scan Enables test ready compile Use this option to replace all sequential elements during optimization no uniquify Allows you to specify that the uniquify process is not to be performed during compile Use this option when you want to carry out a first pass bottom up high effort compile no boundary optimization Allows you to specify that no hierarchical boundary optimization is performed on the current design By default if this option is not specified the tool performs hierarchical boundary optimization which can change design function such that the design operates properly only in its current environment If this behavior is undesirable use the option to disable boundary optimization no autoungroup Allows you to disable automatic ungrouping during compile By default the compile ultra command performs automatic ungrouping of hierarchies both area based auto ungrouping and delay based auto ungrouping For more information see Automatic Ungrouping Using the compile ultra command on page 8 45 Chapter 8 Optimizing the Design 8 44 By default if the dw foundation sldb library is not in the synthetic library list but the DesignWare license has been successfully checked out the dw foundation sldb library is automatically added to the synthetic library list This behavior applies
221. n input port Endpoint cout output port Path Group none Path Type max Point Incr Path input external delay 0 00 0 00 cin in 0 00 0 00 U19 Z AN2 0 87 0 87 f U18 Z EO 1 13 2 00 f add_8 U1_1 CO FAIA 2 27 4 27 E add_8 U1_2 CO FAIA 1 17 5 45 f add_8 U1_3 CO FAIA LT 6 62 f add 8 U1 4 CO FAIA 1 17 7 80 f add 8 U1 5 CO FAIA 1 17 8 97 f add 8 U1 6 CO FAIA 1 17 10 14 f add 8 U1 7 CO FAIA 1 17 11 32 f U2 Z EO 1 06 12 38 f cout out 0 00 12 38 f data arrival time 12 38 f Path is unconstrained The delay from port cin through cell FA1A seems large 2 27 ns Enter the following command to determine how Design Compiler calculated this delay dc_shell xg t gt report delay calculation from add 8 U1 1 A to add 8 U1 1 co Chapter 9 Analyzing and Resolving Design Problems 9 10 Example 9 2 shows the results of this command Example 9 2 Delay Calculation Report KEK K KKK KKK KKK KKK KKK KK KKK KKK KKK KK KKKKEKKEKK Report delay_calculation Design Adder8 Version 1997 01 Date Mon Apr 7 13 23 12 1997 KKKKKKKKKKKKKXKKKKKKKEKKKXKKKKXKKKKKXKXKXXX EX XX From pin add_8 U1_1 A To pin add 8 U1 1 CO arc sense unate arc type cell Input net transition times Dt rise 0 1458 Dt fall 0 0653 Rise Delay computation rise intrinsic 1 89 rise slope Dt rise 0 0 1458 rise resistance pin cap wire cap driver count 0 1458 2 0 1
222. n mult 15 DP OP 246 3372 str Out Contained Operation Port Width Datapath Block Operation_Line Type Chapter 8 Optimizing the Design 8 72 Fanout_2 8 I1 12 mult_15 UNSIGNED Fanout_4 8 CO C1 Fanout_3 Fanout_2 op4 MUX OP op5 MUX OP Fanout_3 8 I3 14 mult_11 UNSIGNED 01 8 Fanout_4 I5 add_19 UNSIGNED mplementation Report Current Set Cell Module Implementation Implementation mult 15 DP OP 246 3372 1 mult 15 DP OP 246 3372 str No multiplexors to report 1 Notice in this example that when components are absorbed into a datapath block the resources report report resources command also includes a datapath report Datapath Report To further understand how to read the datapath report contained in the resources report consider the code in Example 8 10 Example 8 10 Design add Code 1 module add a b c d z 2 input 7 0 a b c d 3 output 15 0 z 4 assign z a b c d 5 endmodule When this code is compiled using DC Ultra datapath optimization the report_resources command generates the report shown in Example 8 11 Using DC Ultra Datapath Optimization 8 73 Example 8 11 Datapath Report for Design add KEK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK EK Report resources Design add Version W 2004 12 Da
223. n rare cases hierarchical structure might disable Design Compiler from fixing design rules In the sample design shown in Figure 8 9 net O1 is overloaded To reduce the load group as many of the loads 11 through In as possible in one level of hierarchy by using the group command or by changing the HDL Then you can apply one of the approaches Figure 8 9 Heavily Loaded Net D z 01 Flattening Logic on the Critical Path Flattening improves performance by representing the design as a two level sum of products However flattening requires considerable CPU resources and it might not be possible to flatten the entire design In this case you can improve the performance by flattening just the logic on the critical path To flatten the logic on the critical path 1 Identify the logic associated with the critical path using the all_fanin command Chapter 8 Optimizing the Design 8 52 2 Group the critical path logic Note The group command groups cells only in the context of the current design hence you cannot use this flow if the critical path spans across hierarchies 3 Characterize the critical path logic 4 Flatten the critical path logic 5 Ungroup the block of critical path logic Table 8 7 shows examples of this procedure using both dcsh and dctcl syntax Table 8 7 Examples of Flattening Critical Path Logic dcsh Examp
224. n the output pin of the IV1 cell When you compile this design Design Compiler does not modify the design because the design meets the specified constraints To list all constraint violations use the al1_violators option of the report_constraint command shown in Example 9 7 Example 9 7 Constraint Report all_violators KEKEKEKEKKKKKKEKK KKK KKK KKK KKK KKK KKK KKK KKK EKEKK Report constraint all_violators Design buffer_example Version 1999 05 Date Mon Jan 4 10 56 49 1999 KKEKEKKKKKKKEKKKEK KKK KKK KKK KKK KKK KKK KKK KKKEKSEK This design has no violated constraints This design does not have any constraint violations Changing the port attributes however can cause constraint violations to occur Example 9 6 shows the result of the following command sequence dc_shell xg t gt set_drive 2 5 IN dc_shell xg t gt set max fanout 0 75 IN dc_shell xg t gt set_load 4 OUT dc_shell xg t gt set_fanout_load 3 5 OUT dc_shell xg t gt report_constraint all_violators verbose Resolving Specific Problems 9 19 Example 9 8 Constraint Report After Port Attributes Are Modified KKEKKKEKKKKKEKKKEK KKK KKK KKK KKK KKK KKKKKKKEKKEKSK Report constraint all_violators verbose Design buffer example Version 1999 05 Date Mon Jan 4 10 56 49 1999 KKIKKKKAKKKKKKAKkKKkKKkKKkKkKkkAkkkkkkkkkkk Net OUT max transition 2 50 Transition Time 3 00 Slack 0 50 VIOLATED Net OUT max fanout 3 00 F
225. n this manual where you can find more information Chapter 2 Design Compiler Basics 2 18 Figure 2 2 Basic Synthesis Flow 7 Ss Develop HDL files Specify libraries Library objects link_library target_library symbol_library synthetic_library Read design analyze elaborate read_file Define design environment set_operating_conditions set_wire_load_model set_drive set_driving_cell set_load set_fanout_load set_min_library Set design constraints Design rule constraints set_max_transition set_max_fanout set_max_capacitance Design optimization constraints create_clock set_clock_latency set_propagated_clock set_clock_uncertainty set_clock_transition set_input_delay set_output_delay set_max_area Select compile strategy Top down Bottom up Optimize the design compile Analyze and resolve design problems check_design report_area report_constraint report_timing Save the design database write Following the Basic Synthesis Flow 2 19 The basic synthesis flow consists of the following steps 1 Develop HDL Files The input design files for Design Compiler are often written using a hardware description language HDL such as Verilog or VHDL These design descriptions need to be written carefully to achieve the best synthesis results possible When writing HDL code you need to consider design data management design
226. ne AGA er oN eee D pos AA N 1 8 Design Compiler FPGA 2 1 8 2 Design Compiler Basics The High Level Design Flow 2 3 Running Design Compiler 2 6 Design Compiler Modes 2 7 Design Compiler Interfaces 2 8 SETUP SA ott nana OLA AE Cee saa ngaa lata ed oe tad da inadd 2 9 Starting Design Compiler 0 000 c eee ee 2 11 Exiting Design COMmpIlel sss essais ais eee ee Ree 2 12 Getting Command Help 2 13 Using Command Log Files 2 15 Using the Filename Log File 2 15 Using SCliPUFICSs 2 sourds een nager 2 16 Working with Licenses 2 16 Listing the Licenses in Use 2 17 Getting License Sahara ak Tatanda data era ser 2 17 Rel asing Licenses sn BANA HIDWAAN KABA LA 2 17 Following the Basic Synthesis Flow 2 18 A Design Compiler Session Example 2 25 Preparing Design Files for Synthesis Managing the Design Data 0202 e eee 3 2 Controlling the Design Data 3 2 Organizing the Design Data 3 3 Partitioning for Synthesis mana tales Pale MEANING 3 4 Partitioning for Design Reuse 3 5 Keeping Related Combinati
227. ng command returns a collection of instances in the current design that have the reference AN2 dc_shell xg t gt get references AN2 U2 U3 U4 To see the reference names use the following command dc_shell xg t gt report_cell get_references AN Cell Reference Library Area Attributes U2 AN2 Isi 10k 2 000000 U3 AN2 1si_10k 2 000000 U4 AN2 Isi 10k 2 000000 U8 AN3 1si_10k 2 000000 Note In DB mode the get_references command returns a collection of references For example the following command returns a collection containing the reference AN2 dc_shell t gt get references AN2 AN2 LU Design Terminology 5 7 Design Database Formats Design Compiler stores design data in the Synopsys internal database format In XG mode Design Compiler supports two design database formats ddc and Milkyway In DB mode Design Compiler supports the db format Note XG mode also supports the db format however to maximize the capacity and performance improvements offered in XG mode use the ddc format rather than the db format The database formats are described below e db format This format is the older internal database format It is a binary format that can represent RTL code mapped gate level designs or libraries It can also contain any constraints that have been applied to the design e ddc format The ddc format is similar to the db format in that it is a single file binary format The ddc format s
228. ning Design Compiler removes all intermediate variables and therefore all its associated logic structure from a design Flattening is not always practical however because it requires a large amount of CPU time and can increase area By default Design Compiler does not flatten your design Use the set flatten command to control flattening of your design The set_flatten command and its options set the following attributes flatten flatten effort flatten minimize and flatten phase Note Flattening does not collapse design hierarchy In Design Compiler you remove levels of design hierarchy by using the ungroup command or the compile command with the ungroyp all or auto_ungroup option Chapter 8 Optimizing the Design 8 4 The structuring and flattening attributes enable fine tuning of the optimization techniques used for each design in the design hierarchy Table 8 1 shows the default values for these attributes Table 8 1 Structuring and Flattening Attributes Attribute Default setting structure true structure_boolean false structure_timing true flatten false Use the report_compile_options command to display these attributes for the current design Note Do not change these default settings unless you understand clearly the impact of structuring and flattening on optimization If you do choose to change these settings change them on a design by design basis in the hierarchy do not set these attributes globall
229. nopsys test synthesis solution DFT Compiler provides integrated design for test capabilities including constraint driven scan insertion during compile The DFT Compiler tool is applied to high performance ASIC and IC designs that utilize scan test techniques For more information see the DFT Compiler documentation Module Compiler The Module Compiler tool facilitates high performance ASIC datapath design For more information see the Module Compiler User Guide Power Compiler The Power Compiler tool offers a complete methodology for power including analyzing and optimizing designs for static and dynamic power consumption For more information about these power capabilities see the Power Compiler User Guide Design Compiler Family 1 7 Design Vision The Design Vision is a graphical user interface GUI to the Synopsys synthesis environment and an analysis tool for viewing and analysing designs at the generic technology GTECH level and gate level Design Vision provides menus and dialog boxes for implementing Design Compiler command s It also provides graphical displays such as design schematics For more information see the Design Vision User Guide and Design Vision Help Design Compiler FPGA The Design Compiler FPGA tool enables input of FPGA technology libraries and data formats It provides FPGA specific optimization algorithms with features for high performance FPGA implementations For more information see the De
230. nstant register removal finite state machine FSM recording and the group ungroup uniquify and ununiquify operations For more information see the Design Compiler Reference Manual Optimization and Timing Analysis Chapter 6 New Command Line Editor Options In Design Compiler version X 2005 09 the command line editor includes new functionality You can press the Tab key to complete nested commands and aliases automatically The command line editor is enabled by default Anew command set cle options What s New in This Release XXV allows you to control the settings of the command line editor For more information see the Design Compiler Command Line Interface Guide Appendix B Known Limitations and Resolved STARS Information about known problems and limitations as well as about resolved Synopsys Technical Action Requests STARS is available in the Design Compiler Release Notes in SolvNet To see the Design Compiler Release Notes 1 Go to the Synopsys Web page at htip www synopsys com and click SolvNet 2 If prompted enter your user name and password If you do not have a Synopsys user name and password follow the instructions to register with SolvNet 3 Click Release Notes in the Main Navigation section on the left click Design Compiler then click the release you want in the list that appears at the bottom About This Manual Preface Xxvi The Design Compiler User Guide provides basic synt
231. nt persistent pins that is pins on the same net that remain after ungrouping For more information on preserving timing constraints see Preserving Hierarchical Pin Timing Constraints During Ungrouping on page 5 44 The hierarchy has user specified constraints such as dont touch size only Or set_ungroup attributes Optimizing for Maximum Performance If your design does not meet the timing constraints you can try the following methods to improve performance Create path groups Fix heavily loaded nets Flatten logic on the critical path Auto ungroup hierarchies on the critical path Perform a high effort incremental compile Perform a high effort compile Creating Path Groups By default Design Compiler groups paths based on the clock controlling the endpoint all paths not associated with a clock are in the default path group If your design has complex clocking Performing Design Implementation 8 47 complex timing requirements or complex constraints you can create path groups to focus Design Compiler on specific critical paths in your design Use the group_path command to create path groups The group_path command allows you to e Control the optimization of your design e Optimize near critical paths e Optimize all paths Controlling the Optimization of Your Design You can control the optimization of your design by creating and prioritizing path groups which affect only the maximum delay cost function
232. nts 4 5 DesignWare components that implement many of the built in HDL operators are provided by Synopsys These operators include lt gt lt gt and the operations defined by if and case statements You can develop additional DesignWare libraries at your site by using DesignWare Developer or you can license DesignWare libraries from Synopsys or from third parties To use licensed DesignWare components you need a license key Specifying Libraries You use dc shell variables to specify the libraries used by Design Compiler Table 4 1 lists the variables for each library type as well as the typical file extension for the library Table 4 1 Library Variables Library type Variable Default File extension Target library target_library your_library db db Link library link library your library db db Symbol library symbol library your library sdb sdb DesignWare library synthetic library f sldb Specifying Technology Libraries To specify technology libraries you must specify the target library and link library Chapter 4 Working With Libraries 4 6 Target Library Design Compiler uses the target library to build a circuit During mapping Design Compiler selects functionally correct gates from the target library It also calculates the timing of the circuit using the vendor supplied timing data for these gates Use the target_library variable to specify the target lib
233. nts see Chapier 6 Defining the Design Environment and Chapter 7 Defining Design Constraints Chapter 8 Optimizing the Design 8 10 Note You can assign local attributes and constraints to subdesigns provided that those attributes and constraints are defined with respect to the top level design 4 Compile the design top down compile script for the TOP design is shown in Example 8 3 dcsh command language and Example 8 4 dctcl command language Both scripts contain comments that identify each of the steps The constraints are applied by including the constraint file defaults con shown in Example 8 2 on page 8 9 Example 8 3 Top Down Compile Script dcsh read in the entire design read_file format verilog E v read_file format verilog D v read_file format verilog C v read_file format verilog B v read_file format verilog A v read_file format verilog TOP v current_design TOP link apply constraints and attributes include defaults con compile the design compile Selecting and Using a Compile Strategy 8 11 Example 8 4 Top Down Compile Script dctcl read in the entire design read_verilog E v read_verilog D v read_verilog C v read_verilog B v read_verilog A read_verilog TOP v current_design TOP link apply constraints and attributes source defaults con compile the design compile Bottom Up Compile Use the bottom up compile strateg
234. o repeat step 3 and refine your name rules Chapter 5 Working With Designs in Memory 5 60 5 If all the appropriate name changes have been made your output files matches the design database file Enter the following commands and compare the output write format verilog hierarchy output consistent v write format ddc hierarchy output consistent ddc 6 Write the files for third party tools If you need more specific naming control use the define_name_rules command See Using the define_name_rules map Command on page 5 58 Summary of Commands for Changing Names Table 5 10 summarizes commands for changing names Table 5 10 Summary of Commands for Changing Names To do this Use this Change the names of ports cells and nets ina design to be Verilog or VHDL compliant Show effects of change_names without making the changes Define a set of rules for naming design objects Name rules are used by change_names and report_names List available name rules The following special cases apply change_names report_names define name rules report name rules e Synopsys database format is the only output format that can have designs containing unmapped synthetic library cells e The EDIF LSI and Mentor formats require a mapped design Saving Designs 5 61 e The equation format requires a combinational design e Schematics are ignored by equation LSI PLA state table TDL
235. o endpt set pin get object name Sendpt group path name Spin to Spin Chapter 8 Optimizing the Design 8 50 Fixing Heavily Loaded Nets Heavily loaded nets often become critical paths To reduce the load on a net you can use either of two approaches e If the large load resides in a single module and the module contains no hierarchy fix the heavily loaded net by using the balance buffer command Table 8 5 shows dcsh and dctcl scripts that use the balance buffer command to fix heavily loaded nets Table 8 5 Using balance buffer to Fix Heavily Loaded Nets dcsh Script dcicl Script include constraints con source constraints con compile compile balance buffer N balance buffer N from find pin buf1 Z from get_pins buf1 Z Note The balance_buffer command provides the best results when your library uses linear delay models If your library uses nonlinear delay models the second approach provides better results e If the large loads reside across the hierarchy from several modules apply design rules to fix the problem Table 8 6 shows dcsh and dctcl scripts that use design rules to fix heavily loaded nets Table 8 6 Using Design Rules to Fix Heavily Loaded Nets dcsh Script dcicl Script include constraints con source constraints con compile compile set_max_capacitance 3 0 set_max_capacitance 3 0 compile only_design_rule compile only_design_rule Performing Design Implementation 8 51 I
236. obtain the desired results Flatten the design before structuring Enter dc_shell xg t gt set_flatten true dc_shell xg t gt set_structure true dc_shell xg t gt compile When you run this command sequence Design Compiler first flattens the logic then goes back and restructures the design by sharing logic off the critical path Performing Design Implementation 8 41 Increase the flattening effort Enter dc_shell xg t gt set_flatten true effort medium dc_shell xg t gt compile Fine tune the results with minimization or phase inversion Enter dc_shell xg t gt set flatten true minimize multiple output phase true dc_shell xg t gt compile The set_flatten minimize command causes Design Compiler to share product terms between output logic cones minimization Minimization causes higher fanout but does not change the two level sum of products representation If you select the minimize single_output option Design Compiler minimizes the equations for each output individually The minimize multiple_output option enables minimization of the entire design by allowing optimization to share terms among outputs Minimization increases compile time therefore Design Compiler does not perform minimization during default flattening The set_flatten phase true command inverts the polarity of the outputs compares the original implementation with the complement and keeps the best result Setting the phase option to true increa
237. ock gating logic Shows unconstrained input and output ports and port loading ng_requirements Shows all timing exceptions set on the design Chapter 9 Analyzing and Resolving Design Problems 9 8 Table 9 4 Timing Analysis Commands Continued Command Analysis task description report_clock Checks the clock definition and clock skew information derive_clocks Checks internal clock and unused registers report_path_group Shows all timing path groups in the design report_timing Checks the timing of the design report_constraint Checks the design constraints report_delay_calculation Reports the details of a delay arc calculation Resolving Specific Problems This section provides examples of design problems you might encounter and describes the workarounds for them Analyzing Cell Delays Some cell delays shown in the full path timing report might seem too large Use the report_delay_calculation command to determine how Design Compiler calculated a particular delay value Example 9 1 shows a full path timing report with a large cell delay value Resolving Specific Problems 9 9 Example 9 1 Full Path Timing Report KKEKKKKK KKK KEK KKK KKK KKK KK KK KKK KKK KKK KKKKEKEK Report timing path full delay max max_paths 1 Design Adder8 Version 1999 05 Date Mon Jan 4 10 56 49 1999 kkxkxkxkxkxkxkxkxkkxkxkkkxkkkkkkkkkkkxkkkkkkkxkkkkkxkx k Operating Conditions Wire Loading Model Mode top Startpoint ci
238. ock network in terms of its latency and skew See also clock latency and clock skew clock gating The control of a clock signal by logic other than inverters or buffers either to shut down the clock signal at selected times or to modify the clock pulse characteristics clock latency The amount of time that a clock signal takes to be propagated from the clock source to a specific point in the design Clock latency is the sum of source latency and network latency Source latency is the propagation time from the actual clock origin to the clock definition point in the design Network latency is the propagation time from the clock definition point in the design to the clock pin of the first register You use the set clock latency command to specify clock latency clock skew The maximum difference between the arrival of clock signals at registers in one clock domain or between clock domains Clock skew is also known as clock uncertainty You use the set_clock_uncertainty command to specify the skew characteristics of one or more clock networks clock source The pin or port where the clock waveform is applied to the design The clock signal reaches the registers in the transitive fanout of all its sources A clock can have multiple sources You use the create_clock command with the source_object option to specify clock sources clock tree The combinational logic between a clock source and registers in the transitive fanout of th
239. ock object and defines its waveform in the current design set_clock_latency set_clock_uncertainty set_propagated_clock set_clock_transition Sets clock attributes on clock objects or flip flop clock pins set input delay Sets input delay on pins or input ports relative to a clock signal set max area Specifies the maximum area for the current design Commands for Setting Design Constraints B 3 set output delay Sets output delay on pins or output ports relative to a clock signal The advanced commands that set design constraints are group path Groups a set of paths or endpoints for cost function calculation This command is used to create path groups to add paths to existing groups or to change the weight of existing groups set false path Marks paths between specified points as false This command eliminates the selected paths from timing analysis set max delay Specifies a maximum delay target for selected paths in the current design set min delay Specifies a minimum delay target for selected paths in the current design set multicycle path Allows you to specify the time of a timing path to exceed the time of one clock signal Appendix B Basic Commands B 4 Commands for Analyzing and Resolving Design Problems The commands for analyzing and resolving design problems are all_connected Lists all fanouts on a net all_registers Lists sequential elements or pins in a design check_design Ch
240. ode it is recommended that you save designs in the ddc format However Design Compiler does allow you to save a design in the db format To do so enter the following command dc_shell xg t gt write format db xg force db design file db Design Compiler then generates the db file but also displays a message that this capability will be removed in a future release If you do not use the xg_force_db option Design Compiler displays an error message Chapter 5 Working With Designs in Memory 5 56 In DB mode to save a design in the db format enter the following command dc_shell gt write format db design file db Converting From db Format to ddc Format To convert your design data from db format to ddc format read the db file into dc_shell in XG mode then save the design in ddc format write format ddc To realize the memory savings from using the ddc format you must exit the current shell then restart the shell in XG mode and read the ddc file Ensuring Name Consistency Between the Design Database and the Netlist Before writing a netlist from within dc_shell make sure that all net and port names conform to the naming conventions for your layout tool Also ensure that you are using a consistent bus naming style Some ASIC and EDA vendors have a program that creates a synopsys dc setup file that includes the appropriate commands to convert names to their conventions If you need to change any net or port na
241. odel Name 05x05 Location my_lib Resistance 0 Capacitance 1 Area 0 Slope 0 186 Fanout Length Points Average Cap Std Deviation 1 0 39 Name 10x10 Location my_lib Resistance 0 Capacitance 1 Area 0 Slope 0 311 Fanout Length Points Average Cap Std Deviation fl 0 53 Chapter 6 Defining the Design Environment 6 10 Example 6 2 Wire Load Models Report Continued Name 20x20 Location my_lib Resistance 0 Capacitance 3 1 Area 0 Slope 0 547 Fanout Length Points Average Cap Std Deviation T 0 86 Wire Loading Model Selection Group Name my_lib Selection Wire load name min area max area 0 00 1000 00 05x05 1000 00 2000 00 10x10 2000 00 3000 00 20x20 Specifying Wire Load Models and Modes The technology library can define a default wire load model that is used for all designs implemented in that technology The default wire loaa library attribute identifies the default wire load model for a technology library Some libraries Support automatic area based wire load selection Design Compiler uses the library function wire_load_selection to choose a wire load model based on the total cell area For large designs with many levels of hierarchy automatic wire load selection can increase runtime To manage runtime set the wire load manually Defining Wire Load Models 6 11 You can turn off automatic selection of the wire load model by setting the auto wire load selection var
242. om clock to clock command from clock command to clock For example in the following command sequence paths from A to B are treated as two cycle paths because specific commands override general commands dc_shell xg t gt set_multicycle path 2 from A to B dc_shell xg t gt set_multicycle path 3 from A The following rules summarize the interaction of the timing exception commands General set_false_path commands override specific set multicycle path commands General set max delay commands override specific set multicycle path commands Specific set false path commands override specific set max delay Or set min delay commands Setting Optimization Constraints 7 25 e Specific set max delay commands override specific set multicycle path commands Setting Area Constraints The set max area command specifies the maximum area for the current design by placing a max area attribute on the current design Specify the area in the same units used for area in the technology library For example to set the maximum area to 100 enter dc shell xg t5 set max area 100 Design area consists of the areas of each component and net The following components are ignored when Design Compiler calculates design area e Unknown components e Components with unknown areas e Technology independent generic cells Cell Component area is technology dependent Design Compiler obtains this information from the technology library When
243. ommended Top Level Partitioning r q Top O EE KG kooo o Pa SN 7 Cede eS SS SS 21 generation Core logic i Pads En Boundary i Eee WL Asynchronous l LE ge M o a Wt Fie Middle ee 00000000 The top level of the design contains the I O pad ring and a middle level of hierarchy that contains submodules for the boundary scan logic the clock generation circuitry the asynchronous logic and the core logic The middle level of hierarchy exists to allow the flexibility to instantiate I O pads Isolation of the clock generation circuitry enables instantiation and careful simulation of this module Isolation of the asynchronous logic helps confine testability problems and static timing analysis problems to a small area HDL Coding for Synthesis HDL coding is the foundation for synthesis because it implies the initial structure of the design When writing your HDL source code always consider the hardware implications of the code A good coding style can generate smaller and faster designs This section provides information to help you write efficient code so that you can achieve your design target in the shortest possible time HDL Coding for Synthesis 3 13 Topics include e Writing technology independent HDL e Using HDL constructs e Writing effective code Writing Technology Independent HDL The goal of high level design that uses a com
244. on 8 41 basic flow 2 18 techniques for 8 41 design objects accessing 5 24 adding 5 28 defined 5 4 listing clocks 5 25 instances 5 24 IN 7 nets 5 25 ports 5 24 references 5 24 registers 5 25 specifying absolute path 5 27 relative path 5 25 design problems commands analyzing B 5 resolving B 5 design reuse partitioning 3 5 design rule attributes 7 3 design rule constraints capacitance 7 8 defined 4 3 fanout load 7 5 setting 7 3 transition time 7 4 design rule cost function 8 31 design rules commands B 2 Design Vision defined 1 8 designs analyzing 9 7 checking consistency 9 2 copying 5 29 creating 5 28 current 5 4 defined 5 3 duplicate checking for 5 16 editing 5 47 buses 5 47 cells 5 47 nets 5 44 5 47 ports 5 45 5 47 flat 5 3 hierarchical 5 3 linking 4 7 5 19 IN 8 listing details 5 16 names 5 16 listing current 5 17 parent 5 3 preserving implementation 8 28 reading 2 21 5 10 5 14 db format 5 16 HDL analyze command 5 10 HDL elaborate command 5 11 netlists 2 21 RTL 2 21 reference changing 5 22 removing from memory 5 52 renaming 5 30 reporting attributes 8 30 saving 5 53 5 54 default behavior 5 54 multiple 5 56 supported formats 5 53 translating 5 50 DesignWare defined 1 7 DesignWare library defined 1 7 4 5 file extension 4 6 specifying 4 6 4 10 DFT Compiler defined 1 7 directory structure bottom up compile figure 3 4 top down compile figure 3 3 disabled timing arc compar
245. on and Timing Analysis e Thechange link command Chapter 5 Working With Designs in Memory 5 18 For more information see Changing Design References on page 5 22 Linking Designs For a design to be complete it must connect to all the library components and designs it references This process is called linking the design or resolving references Design Compiler uses the link command to resolve references The link command uses the link library and search path system variables and the local link library attribute to resolve design references Design Compiler resolves references by carrying out the following steps 1 It determines which library components and subdesigns are referenced in the current design and its hierarchy 2 It searches the link libraries to locate these references a Design Compiler first searches the libraries and design files defined in the current design s local link library attribute b If an asterisk is specified in the value of the link library variable Design Compiler searches in memory for the reference c Design Compiler then searches the libraries and design files defined in the link library variable 3 If it does not find the reference in the link libraries it searches in the directories specified by the search path variable See Locating Designs by Using a Search Path on page 5 21 Linking Designs 5 19 4 It links connects the located references to the design N
246. on might be lost Also dc_shell does not automatically save the designs loaded in memory If you want to save these designs before exiting use the write command For example dc_shell xg t gt write format ddc hierarchy output my_design ddc To exit dc_shell do one of the following e Enter quit Enter exit e Press Control d if you are running Design Compiler in interactive mode and the tool is busy When you exit dc shell text similar to the following appears the memory and the CPU numbers reflect your actual usage Memory usage for this session 1373 Kbytes CPU usage for this session 4 seconds Thank you Getting Command Help Design Compiler provides three levels of command help e A list of commands Running Design Compiler 2 13 e Command usage help e Topic help To get a list of all dc shell commands enter one of the following commands depending on your command language dc shell xg t5 help dc shell list commands In dctcl the help command without options displays the commands with their command summaries To get help about a particular dc shell command enter the command name with the help option The syntax is dc shell xg t5 command name help To get topic help in dc shell enter dc_shell xg t gt man topic where topic is the name of a shell command variable or variable group Using the man command or help command in dcsh you can display the man pages for the topic
247. on through a subdesign do not occur automatically To fine tune the area you can leave the hierarchy intact and enable boundary optimization For greater area reduction you might have to remove hierarchical boundaries Boundary Optimization Direct Design Compiler to perform optimization across hierarchical boundaries boundary optimization by using one of the following commands dc_shell xg t gt compile boundary_optimization or dc_shell xg t gt set boundary optimization subdesign Performing Design Implementation 8 59 If you enable boundary optimization Design Compiler propagates constants unconnected pins and complement information In designs that have many constants VCC and GND connected to the inputs of subdesigns propagation can reduce area Figure 8 11 shows this relationship Figure 8 11 Benefits of Boundary Optimization Subdesign Subdesign IN iba VCC Y Logic IN1 eure IN2 IN2 Hierarchy Removal Removing levels of hierarchy by ungrouping gives Design Compiler more freedom to share common terms across the entire design You can ungroup specific hierarchies before optimization by using the set_ungroup command or the compile command with the ungroup_al1 option to designate which cells you want ungrouped Also you can use the auto ungroup capability of Design Compiler to ungroup small hierarchies during op
248. onal Logic Together 3 5 Registering Block Outputs 3 7 Partitioning by Design Goal 3 8 Partitioning by Compile Technique 3 9 Keeping Sharable Resources Together 3 10 Keeping User Defined Resources With the Logic They Drive silice sens eee es Be 3 11 Isolating Special Functions 3 12 HDL Coding for SYAINCSISS vax ni than naar 3 13 Writing Technology Independent HDL 3 14 Inferring GComponents 0c ee eee eee 3 14 Using Synthetic Libraries 3 18 Designing State Machines 3 21 Using HDL Constructs sis de ceed NIT BARRENS ee LA 3 22 General HDL Constructs 3 22 Using Verilog Macro Definitions 3 27 Using VHDL Port Definitions 3 28 Writing Effective Code ss paaa aa NANANA enn en mien 3 28 Guidelines for Identifiers 3 28 Guidelines for Expressions 3 30 Guidelines for Functions 3 31 Guidelines for Modules 3 33 4 Working With Libraries Selecting a Semiconductor Vendor 4 2 Understanding the Library Requirements 4 3 Technology Libraries 4 3 Symbol Libraries aa Rien te e
249. onous Paths You can also use the set_max_delay and set_min_delay commands to constrain asynchronous paths across different frequency domains Table 7 3 shows dcsh and dctcl examples for constraining asynchronous paths Table 7 3 Examples for Constraining Asynchronous Paths dcsh Example dctcl Example dc_shell gt set_max delay 17 1 dc_shell xg t gt set_max_delay17 1 from find clock ciki from get clocks clki to find clock cik2 to get clocks clk2 dc shell set max delay 23 5 dc_shell xg t gt set max delay23 51 from find clock clk2 from get_clocks clk2 to find clock cik3 to get clocks c1k3 dc shell set max delay 31 6 dc_shell xg t gt set max delay 31 6 from find clock clk3 from get clocks clk3 to find clock clk1 to get_clocks clk1 Setting Multicycle Paths The multicycle path condition is appropriate when the path in question is longer than a single cycle or when data is not expected within a single cycle Use the set_multicycle_path command to specify the number of clock cycles Design Compiler should use to determine when data is required at a particular endpoint You can specify this cycle multiplier for setup or hold checks If you do not specify the setup or hold option with the set_multicycle_path command Design Compiler applies the multiplier value only to setup checks By default setup is checked at the next active edge of the clock at the endpoint after the da
250. onstraints Compile flow Effect on hierarchical pin timing constraints Ungrouping a hierarchy before Timing constraints placed on hierarchical pins optimization by using ungroup are preserved In previous releases timing attributes placed on the hierarchical pins of a cell were not preserved when that cell was ungrouped If you want your current optimization results to be compatible with previous results set the ungroup_preserve_constraints variable to false The default for this variable is true which specifies that timing constraints will be preserved Ungrouping a hierarchy during Timing constraints placed on hierarchical pins optimization by using compile are not preserved ungroup_all Or set_ungroup followed by To preserve timing constraints set the compile auto_ungroup_preserve_constraints variable to true Chapter 5 Working With Designs in Memory 5 44 Table 5 4 Preserving Hierarchical Pin Timing Constraints Continued Compile flow Effect on hierarchical pin timing constraints Automatically ungrouping a Design Compiler does not ungroup the hierarchy during optimization hierarchy that is by using compile auto_ungroup area delay To make Design Compiler ungroup the hierarchy and preserve timing constraints set the auto_ungroup_preserve_constraints variable to true When preserving timing constraints Design Compiler reassigns the timing constraints to appropriate adjacent persistent pins pins on t
251. or the cells with complex timing arcs such as memories and banked components Chapter 4 Working With Libraries 4 14 You do not normally need to set the preferred attribute as part of your regular compile methodology because a good starting cell is automatically determined during the library analysis step Because nonpreferred gates can be chosen to meet optimization constraints the effect of preferred attributes might not be noticeable after optimization For example to set a preference for the low drive inverter INV LD enter dc_shell xg t gt set prefer MY LIB INV LD 1 Use the remove_attribute command to remove cell preferences dc_shell xg t gt remove attribute MY LIB INV LD preferred MY_LIB INV_LD Use the min option if you want Design Compiler to prefer fewer but larger area buffers or inverters when it fixes hold time violations Normally Design Compiler gives preference to smaller cell area over the number of cells used in a chain of buffers or inverters You can change this preference by using the min option which tells Design Compiler to minimize the number of buffers or inverters by using larger area cells For example to set a hold preferred attribute for the inverter IV enter dc_shell xg t gt set prefer min class IV di Use the remove attribute command to remove the hold preferred cell attribute Directing Library Cell Usage 4 15 dc_shell xg t gt remove attribute class IV hold preferred cl
252. ormance caused by temperature fluctuations are most often handled as linear scaling effects but some submicron silicon processes require nonlinear calculations Supply voltage variation The design s supply voltage can vary from the established ideal value during day to day operation Often a complex calculation using a shift in threshold voltages is employed but a simple linear scaling factor is also used for logic level performance calculations Process variation This variation accounts for deviations in the semiconductor fabrication process Usually process variation is treated as a percentage variation in the performance calculation When performing timing analysis Design Compiler must consider the worst case and best case scenarios for the expected variations in the process temperature and voltage factors Defining the Operating Conditions 6 3 Determining Available Operating Condition Options Most technology libraries have predefined sets of operating conditions Use the report_1ib command to list the operating conditions defined in a technology library The library must be loaded in memory before you can run the report 11b command To see the list of libraries loaded in memory use the list libraries Or the list l1libs command For example to generate a report for the library my lib which is stored in my lib db enter the following commands dc_shell xg t gt read file my lib db dc_shell xg t gt report lib my
253. ormat EDIF Electronic Design Interchange Format see the EDIF 2 0 O Interface User Guide Saving Designs 5 53 Table 5 8 Supported Output Formats Continued Format Description eqn Synopsys equation format LSI LSI Logic Corporation netlist format MIF Mentor Intermediate netlist format PLA Berkeley Espresso programmable logic arry format St Synopsys State Table format TDL Tegas Design Language netlist format Verilog IEEE Standard Verilog see the HDL Compiler documentation VHDL IEEE Standard VHDL see the HDL Compiler documentation Commands to Save Design Files Design Compiler provides the following ways to save design files e The write command e The write_milkyway command Using the write Command You use the write command to convert designs in memory to a format you specify and save that representation to disk It is recommended that in XG mode you save designs in the ddc format rather than the db format Chapter 5 Working With Designs in Memory 5 54 Use options to the write command as shown To do this Use this Specify a list of designs to save The default is the current design Specify the format in which a design is saved Specify that all designs in the hierarchy are saved Specify a single file into which designs are wriiten Specify that only modified designs are saved Specify the name of the library in which the design is saved design_list format You can speci
254. ost successful method for reducing the worst negative slack to zero To reduce runtime you can place a dont_touch attribute on all blocks that already meet timing constraints dc_shell xg t gt dont_touch noncritical_blocks dc_shell xg t gt compile map_effort high incremental mapping This incremental approach works best for a technology library that has many variations of each logic cell Performing Design Implementation 8 55 Optimizing for Minimum Area If your design has timing constraints these constraints always take precedence over area requirements For area critical designs do not apply timing constraints before you compile If you want to view timing reports you can apply timing constraints to the design after you compile If your design does not meet the area constraints you can try the following methods to reduce the area e Disable total negative slack optimization e Enable Boolean optimization e Manage resource selection e Use flattening e Optimize across hierarchical boundaries Disabling Total Negative Slack Optimization By default Design Compiler prioritizes total negative slack over meeting area constraints This means Design Compiler performs area optimization only on those paths that have positive slack To change the default priorities prioritize area over total negative slack use the ignore_tns option when setting the area constraints dc_shell xg t gt set_max_area ignore tns max area
255. ote In a hierarchical design Design Compiler considers only the top level design s local link library It ignores local link libraries associated with the subdesigns Design Compiler uses the first reference it locates If it locates additional references with the same name it generates a warning message identifying the ignored duplicate references If Design Compiler does not find the reference a warning appears advising that the reference cannot be resolved By default the case sensitivity of the linking process depends on the source of the references To explicitly define the case sensitivity of the linking process set the 1ink_force_case variable The arrows in Figure 5 3 show the connections that the linking process added between the instances references and link libraries In this example Design Compiler finds library component NAND2 in the LIBRARY_2 technology library it finds subdesign MULTIPLIER in a design file Chapter 5 Working With Designs in Memory 5 20 Figure 5 3 Resolving References EXREF Link libraries k S _ References Technology libraries 4 TINA ANG Qt LIBRARY 1 Ut NAND2 LIBRARY 2 AND2 U2 MULTIPLIER U3 MULTIPLIER U4 ADDER LL ER j Locating Designs by Using a Search Path You can specify the design file location by using the complete path or only the file name If you specify only the file name Design Compiler uses the search path defined in the
256. ote that comparators are extracted as a part of a datapath Mixed signed and unsigned operators in a single datapath block Variable shift operators lt lt gt gt lt lt lt gt gt gt for Verilog and sll srl sla sra rol ror for VHDL To enable variable shift extraction set the hdlin_use_syn_shifters variable to true MUXs Operations with bit truncation Shift operators limited to shifts of constant amounts Chapter 8 Optimizing the Design 8 64 The datapath flow can extract these components only if they are e Directly connected to each other that is no nonarithmetic logic between components e Not connected to an input or output port The following components cannot be extracted by any Synopsys datapath methodology e Equality and non equality comparators e Shift operators of nonconstant amounts e Operations that have user specified implementations Using DC Ultra datapath optimization a datapath block can now include truncated bits This feature is illustrated in Example 8 7 Example 8 7 Design dp Truncates d After Addition of c module dp a b e e input 63 0 a b c output 63 0 e reg 63 0 e reg 127 0 d always a or b or c begin d a brt Cc e a d 127 64 end endmodule Using DC Ultra Datapath Optimization 8 65 In this example dis truncated after the addition of c With DC Ultra datapath optimization operators that follow bit truncation are extracted T
257. ou are confident about the structure you want you can use one of the following strategies to preserve your buffer network e Group the cells into a new hierarchy and set dont touch attributes on that hierarchy e Set the dont touch network attribute on the pin that begins the network e Set the dont touch attribute on all cells and nets within the network that you want to retain Resolving Specific Problems 9 27 Chapter 9 Analyzing and Resolving Design Problems 9 28 Design Example Optimizing a design can involve using different compile strategies for different levels and components in the design This appendix shows a design example that uses several compile strategies Earlier chapters provide detailed descriptions of how to implement each compile strategy Note that the design example used in this appendix does not represent a real life application This appendix includes the following sections e Design Description e Setup File e Default Constraints File e Compile Scripts You can access the files described in these sections at SYNOPSYS doc syn guidelines A 1 Design Description The design example shows how you can constrain designs by using a subset of the commonly used dc_shell commands and how you can use scripts to implement various compile strategies The design uses synchronous RTL and combinational logic with clocked D flip flops Figure A 1 shows the block diagram for the design example The des
258. ou define the environment by specifying operating conditions wire load models and system interface characteristics Operating conditions include temperature voltage and process variations Wire load models estimate the effect of wire length on design performance System interface characteristics include input drives input and output loads and fanout loads The environment model directly affects design synthesis results In Design Compiler the model is defined by a set of attributes and constraints that you assign to the design using specific dc shell commands Figure 6 1 illustrates the commands used to define the design environment 6 1 Figure 6 1 Commands Used to Define the Design Environment set_operating conditions set_drive AM set_load set_driving_cell set_load set_wire_load_model set_fanout_load This chapter contains the following sections e Defining the Operating Conditions e Defining Wire Load Models e Modeling the System Interface Chapter 6 Defining the Design Environment 6 2 Defining the Operating Conditions In most technologies variations in operating temperature supply voltage and manufacturing process can strongly affect circuit performance speed These factors called operating conditions have the following general characteristics Operating temperature variation Temperature variation is unavoidable in the everyday operation of a design Effects on perf
259. ove the net Setting dont_touch on a reference sets an implicit dont touch on all cells using that reference during subsequent optimizations of the design Setting dont_touch on a design has an effect only when the design is instantiated within another design as a level of hierarchy In this case the dont_touch attribute on the design implies that all cells under that level of hierarchy are subject to the dont_touch attribute Setting dont_touch on the top level design has no effect because the top level design is not instantiated within any other design Preserving Subdesigns 8 29 e You cannot manually or automatically ungroup objects marked as dont_touch That is the ungroup command and the compile ungroup_all and auto_ungroup options have no effect on dont_touch objects Note The dont_touch attribute is ignored on synthetic part cells for example many of the cells read in from an HDL description and on nets that have unmapped cells on them During compilation warnings appear for dont_touch nets connected to unmapped cells generic logic Use the report_design command to determine whether a design has the dont_touch attribute set dc_shell xg t gt set_dont_touch SUB_A Performing set dont touch on design SUB A 1 dc_shell xg t gt report design KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKEKKXEXEX XX Report design Design SUB_A Version 1999 05 Date Mon Jan 4 10 56 49 1999 KKKKKKKKKKKKKKKKKKKKKKKKKKKKKKKEKKKE
260. ow max_transition min_capacitance minus_uncertainty output_not_used pad_location XNF only part XNF only plus_uncertainty port_direction port is pad ref name rise drive structure ungroup wired logic disable xnf init xnf loc design or lib file name float float float float float float true false string string float fin inout out unknown true false reference name float true false true false true false string string Appendix C Predefined Attributes C 4 Table C 3 Library Attributes Attribute name Value default values float k process values float k temp values float k volt values float nom process float nom temperature float nom voltage float Table C 4 Library Cell Attributes Attribute name Value area float dont touch true false dont use true false preferred true false Table C 5 Net Attributes Attribute name Value ba net resistance dont touch load subtract pin load wired and float true false float true false true false C 5 Table C 5 Net Attributes Continued Attribute name Value wired_or true false Table C 6 Pin Attributes Attribute name Value disable timing true false max_time_borrow float pin_direction in inout out unknown Table C 7 Reference Attributes Attribute name Value dont_touch true false is black box true false is co
261. owing advantages e Compiles the reference design once e Requires less memory than the uniquify method e Takes less time to compile than the uniquify method Chapter 8 Optimizing the Design 8 26 The principal disadvantage of the compile once don t touch method is that the characterization might not apply well to all instances Another disadvantage is that you cannot ungroup objects that have the dont touch attribute Ungroup Method The ungroup method has the same effect as the uniquify method it makes unique copies of the design but in addition it removes levels of hierarchy This method uses the ungroup command to produce a flattened netlist For details about the ungroup command See Removing Levels of Hierarchy on page 5 35 After ungrouping the instances of a subdesign you can recompile the top level design For example the following command sequence uses the ungroup method to resolve the multiple instances of design C in design TOP dc_shell xg t gt current design B dc shell xg t5 ungroup U3 U4 dc_shell xg t gt current design top dc_shell xg t gt compile Figure 8 6 shows the result of running this command sequence Resolving Multiple Instances of a Design Reference 8 27 Figure 8 6 Ungroup Results TOP U1 U2 B A B U3 U10 U4 U10 D D B U3 U11 U4 U11 ty po S Design Compiler memory The ungroup method has the fol
262. p flop flip flop with asynchronous set or reset or flip flop with synchronous set or reset Be careful when mixing rising and falling edge triggered flip flops in your design If a module infers both rising and falling edge triggered flip flops and the target technology library does not contain a falling edge triggered flip flop Design Compiler generates an inverter in the clock tree for the falling edge clock Inferring Registers Without Control Signals For inferring registers without control signals make the data and clock pins controllable from the input ports or through combinational logic If a gate level simulator cannot control the data or clock pins from the input ports or through combinational logic the simulator cannot initialize the circuit and the simulation fails Inferring Registers With Control Signals You can initialize or control the state of a flip flop by using either an asynchronous or a synchronous control signal For inferring asynchronous control signals on latches use the async_set_reset compiler directive attribute in VHDL to identify the asynchronous control signals HDL Compiler automatically identifies asynchronous control signals when inferring flip flops Chapter 3 Preparing Design Files for Synthesis 3 16 For inferring synchronous resets use the sync_set_reset compiler directive attribute in VHDL to identify the synchronous controls Inferring Three State Drivers Assign the high impedan
263. pile options gt gt Silog path s rpt file report constraint all violators verbose gt gt Silog path s rpt file report timing path end gt gt Silog path S rpt file report timing max path Smaxpaths gt gt Silog path s rpt file report qor gt gt S log path s rpt file Compile Scripts A 27 Example A 27 run scr Initial compile with estimated constraints include script path initial compile scr current design ChipLevel write hierarchy out db path ChipLevel init db Characterize and write script for all modules include script path characterize scr Recompile all modules using write script constraints remove design all include script path recompile scr current design ChipLevel write hierarchy out db path ChipLevel_final db Example A 28 initial compile scr Initial compile with estimated constraints include script path read scr current design ChipLevel include script path defaults con include script path adder16 scr include script path cascademod scr include script path comp16 scr include script path mult8 scr include script path mult16 scr include script path muxmod scr include script path pathseg scr Appendix A Design Example A 28 Example A 29 adder16 scr Script file for constraining Adder16 rpt_file adder16 rpt design adder16 current design Adder16 include script path defaults con Defin
264. plementation By default high level optimization performs resource allocation and implementation based on timing constraints To change the default and force Design Compiler to base resource allocation and implementation on area constraints set the following variables before compile dc_shell xg t gt set_resource allocation area only dc_shell xg t gt set_resource implementation area only To specify area driven resource allocation and implementation for a specific design set the following variables before you compile dc_shell xg t gt current design subdesign dc_shell xg t gt set resource allocation area only dc_shell xg t gt set resource implementation area only Chapter 8 Optimizing the Design 8 58 Using Flattening In most cases flattening increases the area In highly random designs with unpredictable structures flattening might reduce the area However flattening is CPU intensive and the process might not finish for some designs Use the set_flatten command on specific modules that might benefit from this technique do not use the set_flatten command on the top level design The minimize and phase options discussed in Optimizing Random Logic on page 8 41 can also reduce area Optimizing Across Hierarchical Boundaries Design Compiler respects levels of hierarchy and port functionality except when automatic ungrouping of small hierarchies is enabled Boundary optimizations such as constant propagati
265. pletely automatic synthesis process is to have no instantiated gates or flip flops If you meet this goal you will have readable concise and portable high level HDL code that can be transferred to other vendors or to future processes In some cases the HDL Compiler tool requires compiler directives to provide implementation information while still maintaining technology independence In Verilog compiler directives begin with the characters or In VHDL compiler directives begin with the two hyphens followed by pragma or synopsys For more information see the HDL Compiler documentation The following sections discuss various methods for keeping your HDL code technology independent Inferring Components HDL Compiler provides the capability to infer the following components e Multiplexers e Registers e Three state drivers Chapter 3 Preparing Design Files for Synthesis 3 14 e Multibit components These inference capabilities are discussed in the following pages For additional information and examples see the HDL Compiler documentation Inferring Multiplexers HDL Compiler can infer a generic multiplexer cell MUX_OP from case statements in your HDL code If your target technology library contains at least a 2 to 1 multiplexer cell Design Compiler maps the inferred MUX_OPs to multiplexer cells in the target technology library Design Compiler determines the MUX_OP implementation during compile based on the
266. ptimization 8 61 e Explores better solutions that might involve a different resource sharing configuration e Allows the tool to make better tradeoffs between resource sharing and datapath optimization DC Ultra datapath optimization is enabled by default To disable DC Ultra datapath optimization set hlo_disable_datapath_optimization to true The default is false To use the improved datapath generators and better arithmetic components starting with Design Compiler version W 2004 12 ensure the following settings e set synthetic library dw_foundation sldb e set synlib enable dpgen true default is true These enhancements require a DesignWare license Note If you do not specify the no auto Awlib option in the set ultra optimization command and hlo disable datapath optimzationis false the default the dw foundation sldb library is automatically added to the synthetic library list if it is not already there DC Ultra datapath optimization requires a DC Ultra Features license and a DesignWare Foundation license This section contains the following e Datapath Extraction e Two Different Datapath Optimization Methods Chapter 8 Optimizing the Design 8 62 e Methodology Flow e Datapath Report e Commands Specific to DC Ultra Datapath Optimization Datapath Extraction Datapath design is commonly used in applications that contain extensive data manipulation such as 3 D multimedia and digital signal processing
267. r Accessing SolvNet SolvNet includes an electronic knowledge base of technical articles and answers to frequently asked questions about Synopsys tools SolvNet also gives you access to a wide range of Synopsys online services including software downloads documentation on the Web and Enter a Call to the Support Center To access SolvNet 1 Go to the SolvNet Web page at http solvnet synopsys com 2 If prompted enter your user name and password If you do not have a Synopsys user name and password follow the instructions to register with SolvNet If you need help using SolvNet click HELP in the top right menu bar or in the footer Customer Support XXXI Contacting the Synopsys Technical Support Center If you have problems questions or suggestions you can contact the Synopsys Technical Support Center in the following ways e Open a call to your local support center from the Web by going to http solvnet synopsys com Synopsys user name and password required then clicking Enter a Call to the Support Center e Send an e mail message to your local support center E mail support_center synopsys com from within North America Find other local support center e mail addresses at http www synopsys com support support_ctr e Telephone your local support center Call 800 245 8005 from within the continental United States Call 650 584 4200 from Canada Find other local support center
268. r MS Star MTB Star Power Star Rail Star RC Star RCXT Star Sim Star SimXT Star Time Star XP SWIFT Taurus TimeSlice TimeTracker Timing Annotator TopoPlace TopoRoute Trace On Demand True Hspice TSUPREM 4 TymeWare VCS Express VCSi Venus Verification Portal VFormal VHDL Compiler VHDL System Simulator VirSim and VMC are trademarks of Synopsys Inc Service Marks MAP in SVP Caf and TAP in are service marks of Synopsys Inc SystemC is a trademark of the Open SystemC Initiative and is used under license ARM and AMBA are registered trademarks of ARM Limited All other product or company names may be trademarks of their respective owners Printed in the U S A Document Order Number 36042 000 ZA Design Compiler User Guide version X 2005 09 Contents What s New in This Release XVI About This Manual 24 a riens es mate nat xxvi Customer Support pce dred we cede a GL series XXX 1 Introduction to Design Compiler Design Compiler and the Design Flow 1 2 Design Compiler Family sr durs DA Wan a KG AE le 1 4 DG EXpetl rraca nauen ean NG MALALANG KAKA DAA ARNAN WEN 1 5 DUA aaa mO Ka ANA ma O Aa 1 6 HDL Compiler 10015 mama co pow eee eae BARAHA 1 6 DesignWare Library 000 cee eee 1 7 DFT CGMbpiletac2 aerate Os eee oe eset eee ees 1 7 Module Compiler Essen ean Oe MR eee ies 1 7 Power Compilers snes KABA LA dis de saw ee aa rex 1 7 DESIGN VISION sa
269. r version you are using an error message appears The error message provides details about the version mismatch Listing Designs in Memory To list the names of the designs loaded in memory use the list designs command dc_shell xg t gt list designs A 7 B 1 The asterisk next to design A shows that A is the current design To list the memory file name corresponding to each design name use the show_file option dc_shell xg t gt list designs show file userl designs design_A A ddc Aa 83 home designer dc B ddc B E 1 The asterisk next to design A shows that A is the current design File B ddc contains both designs B and C To check for duplicate designs loaded in memory use the list_duplicate_designs command dcsh only dc_shell gt list_duplicate_designs Warning Multiple designs in memory with the same design name Chapter 5 Working With Designs in Memory 5 16 Design File Path seq2 A db home designer dc seq2 B db home designer dc Setting the Current Design You can set the current design the design you are working on in the following ways e With the read file command When the read file command successfully finishes processing it sets the current design to the design that was read in dc_shell xg t gt read file format ddc MY DESIGN ddc Reading ddc file designs ex MY DESIGN ddc Current design is MY DESIGN e With the elaborate command e With the current design
270. rary The syntax for dctcl is set target_library my_tech db The syntax for desh is target_library my_tech db Link Library Design Compiler uses the link library to resolve references For a design to be complete it must connect to all the library components and designs it references This process is called linking the design or resolving references During the linking process Design Compiler uses the link library system variable the local link library attribute and the search path system variable to resolve references These variables and attribute are described below e link library variable Thelink library variable specifies a list of libraries and design files that Design Compiler can use to resolve references When you load a design into memory Design Compiler also loads all libraries specified in the link library variable Specifying Libraries 4 7 Because the tool loads the libraries while loading the design rather than during the link process the memory usage and runtime required for loading the design might increase However the advantage is that you know immediately whether your design can be processed with the available memory Note In DB mode the libraries are read in during the link process An asterisk in the value of the link library variable specifies that Design Compiler should search memory for the reference local_link_library attribute The local_link_library attribute is a list of design
271. re set at this level and then a hierarchical compile approach is used set rpt_file cascademod rpt set design cascademod current_design CascadeMod source S script_path defaults con Define design environment set_load 2 5 all_outputs set_driving_cell lib_cell FD1 all_inputs set_drive 0 clk_name Define design constraints set input delay 1 35 clock Sclk_name datal data2 set input delay 3 5 clock Sclk name cin set input delay 4 5 clock Sclk name rst start set output delay 5 5 clock Sclk name comp out set max area 0 Use compile once dont touch approach for Comparator set dont touch u12 compile if shell is in xg mode 0 write hier o S db_path design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl Appendix A Design Example A 18 Example A 19 compi6 tcl Script file for constraining Comparator set rpt file comp16 rpt set design comp16 current_design Comparator source S script_path defaults con Define design environment set_load 2 5 cp_out set_driving_cell lib_cell FD1 all_inputs Override auto wire load selection set wire load model name 05x05 set wire load mode enclosed Define design constraints set input delay 1 35 clock Scilk name ain bin set output delay 5 1 clock Sclk name cp out set max area 0 compile if shell is in xg mode 0 write hier o S db path s design
272. read_ddc command 5 15 read file command 2 21 4 11 5 10 5 14 5 17 read_lib command 4 11 read_milkyway command 5 14 read_verilog command 2 21 read_vhdl command 2 21 reference attributes C 6 references changing design 5 22 reporting 5 24 resolving 4 7 5 19 references using 5 7 register inference D flip flop 3 16 D latch 3 15 defined 3 15 edge expressions 3 16 register types mixing 3 16 registers inferring IN 13 HDL Compiler 3 15 listing 5 25 remove attribute command 7 5 7 8 7 9 remove_bus command 5 47 remove_cell command 5 47 remove_clock command 7 13 remove_constraint command 7 27 remove_design command 4 16 5 52 remove_input_delay command 7 14 remove_license command 2 17 remove_multibit command 3 18 remove_net command 5 47 remove_output_delay command 7 14 remove_port command 5 47 remove_wire_load_model command 6 13 removing levels of hierarchy 5 35 rename_design command 5 30 report_attribute command 5 65 report_auto_ungroup 5 41 report_cell command 9 25 report_clock command 5 25 purpose 7 13 skew option 7 14 report_compile_options command 8 5 report_constraint command 9 16 9 19 all violators option report violations 9 19 verbose option 9 18 report delay calculation command 9 9 report design command 6 5 8 30 report hierarchy command 5 31 report lib command 4 12 6 4 6 9 6 17 report net command 5 25 report path group command 8 35 report port command 5 24 7 14 report reference command 5
273. real clock set infinite drive strength if find port clk clk set_drive 0 clk Apply default timing constraints for modules set_input_delay 1 2 all_inputs clock clk_name set_output_delay 1 5 all_outputs clock clk_name set_clock_uncertainty setup 0 45 clk_name Set operating conditions set_operating_conditions WCCOM Turn on auto wire load selection library must support this feature auto_wire_load_selection true Default Constraints File A 15 Compile Scripts Example A 15 through Example A 26 provide the dctcl scripts used to compile the ChipLevel design Example A 27 through Example A 38 provide the dcsh scripts used to compile the ChipLevel design The compile script for each module is named for that module to ease recognition The initial dctcl script files have the tcl suffix The initial dcsh script files have the scr suffix Scripts generated by the write_script command have the wscr or wtcl suffix depending on which command language generated them Example A 15 run tcl Initial compile with estimated constraints source S script path initial compile tcl current design ChipLevel if shell is in xg mode 0 write hier o S db path ChipLevel init db else write f ddc hier o S ddc_path ChipLevel_init ddc Characterize and write script for all modules source S script_path characterize tcl Recompile all modules using write script constra
274. rent wire load models are updated with the correct delays set the auto ungroup preserve constraints Variable to true in addition to setting the compile auto ungroup override wlim variable to true e Constraints or timing exceptions are set on pins of the hierarchy You can override this behavior by setting the auto ungroup preserve constraints Variable to true Design Compiler ungroups the hierarchy and moves timing constraints to adjacent persistent pins that is pins on the same net that remain after ungrouping For more information on preserving timing constraints see Preserving Hierarchical Pin Timing Constraints During Ungrouping on page 5 44 e The hierarchy has more child cells than that specified by compile auto ungroup area num cells Or compile auto ungroup delay num cells e Thehierarchy has a dont touch attribute or ungroup attribute For more information on these compile variables and options see the man pages Changing the Design Hierarchy 5 43 Preserving Hierarchical Pin Timing Constraints During Ungrouping Hierarchical pins are removed when a cell is ungrouped Depending on whether you are ungrouping a hierarchy before optimization or after optimization Design Compiler handles timing constraints placed on hierarchical pins in different ways The table below summarizes the effect that ungrouping has on timing constraints within different compile flows Table 5 4 Preserving Hierarchical Pin Timing C
275. ribute to limit the list to attributes that apply to one of the following classes design port cell clock pin net lib or reference Chapter 5 Working With Designs in Memory 5 64 For example the max_fanout attribute has a predefined type of float Suppose you enter the following command Design Compiler displays an error message set attribute lib icell ipin max fanout 1 type integer If an attribute applies to more than one object type Design Compiler searches the database for the named object For information about the search order see The Object Search Order on page 5 68 When you set an attribute on a reference subdesign or library cell the attribute applies to all cells in the design with that reference When you set an attribute on an instance cell net or pin the attribute overrides any attribute inherited from the instance s reference Viewing Attribute Values To see all attributes on an object use the report attribute command dc_shell xg t gt report attribute obj type object To see the value of a specific attribute on an object use the get attribute command For example to get the value of the maximum fanout on port OUT7 enter dc_shell xg t gt get attribute OUT7 max fanout Performing get attribute on port OUT7 3 000000 Working With Attributes 5 65 If an attribute applies to more than one object type Design Compiler searches the database for the named object For infor
276. ription Synopsys Common Licensing checks out a license for the appropriate HDL compiler If you know the tools and interfaces you need you can use the get_license command to check out those licenses This ensures that each license is available when you are ready to use it For example dc_shell xg t gt get_license HDL Compiler Once a license is checked out it remains checked out until you release it or exit dc_shell Releasing Licenses To release a license that is checked out to you use the remove_license command For example dc_shell xg t gt remove_license HDL Compiler Running Design Compiler 2 17 Following the Basic Synthesis Flow Figure 2 2 shows the basic synthesis flow You can use this synthesis flow in both the design exploration and design implementation stages of the high level design flow discussed previously Also listed in Figure 2 2 are the basic dc_shell commands that are commonly used in each step of the basic flow For example the commands analyze elaborate and read file are used inthe step that reads design files into memory All the commands shown in Figure 2 2 can take options but no options are shown in the figure Note Under Select Compile Strategy top down and bottom up are not commands They refer to two commonly used compile strategies that use different combinations of commands Following Figure 2 2 is a discussion of each step in the flow including a reference to the chapter i
277. rize u7 current_design PathSegment echo current_design PathSegment gt S script_path pathseg wtcl echo group design mult cell mult U100 gt gt S script_path pathseg wtcl write script format dctcl gt gt S script_path pathseg wtcl Appendix A Design Example A 24 Example A 25 recompile tcl source S script_path read tcl current design ChipLevel source S script_path defaults con source S script path adder16 wtcl compile if shell is in xg mode 0 write hier o S db path adder16 wtcl db else write f ddc hier o S dde path adder16 wtcl ddc set rpt file adder16_wtcl rpt source S script_path report tcl source S script path cascademod wtcl dont touch u12 compile if shell is in xg mode 0 write hier o S db path cascademod wtci db else write f ddc hier o S ddc_path cascademod_wtcl ddc set rpt file cascade wtcl rpt source S script_path report tcl Compile Scripts A 25 source S script_path comp16 wtcl compile if shell is in xg mode 0 write hier o S db path comp16 wtcl db else write f ddc hier o S ddc_path comp16_wtcl ddc set rpt file comp16 wtcl rpt source S script_path report tcl source S script_path mult8 wtcl compile if shell is in xg mode 0 write hier o S db path mult8 wtcl db else write f ddc hier o S ddc_path mult8_wtcl ddc set rpt file mult8 wtcl rpt source S scr
278. rized with a cell in the technology library You can use set_drive and the drive_of commands together to represent the drive resistance of a cell However these commands are not as accurate for nonlinear delay models as the set_driving_cell command is Figure 6 3 shows a hierarchical design The top level design has two subdesigns U1 and U2 Ports 11 and 12 of the top level design are driven by the external system and have a drive resistance of 1 5 Modeling the System Interface 6 15 Figure 6 3 Drive Characteristics top level design set driving cell set drive 1 5 External logic System PAD MAN k MAN l2 XI AND 14 1 5 sub design1 sub design2 To set the drive characteristics for this example follow these steps 1 Because ports 1 and 12 are not driven by library cells use the set_drive command to define the drive resistance Enter dc_shell xg t gt current design top level design dc_shell xg t gt set drive 1 5 I1 I2 To describe the drive capability for the ports on design sub design2 change the current design to sub design2 Enter dc_shell xg t gt current design sub design2 An IV cell drives port 13 Use the set driving cell command to define the drive resistance Because IV has only one output and one input define the drive capability as follows Enter dc_shell xg t gt set driving cell lib cell IV 13 Chapter 6 De
279. rompt e The DB mode dctcl command language is preceded by the dc_shell t gt prompt e The DB mode dcsh command language example is preceded by the dc_shell gt prompt About This Manual xxvii Preface xxviii Audience This manual is intended for logic designers and engineers who use the Synopsys synthesis tools with the VHDL or Verilog hardware description language HDL Before using this manual you should be familiar with the following topics High level design techniques ASIC design principles Timing analysis principles Functional partitioning techniques Related Publications For additional information about Design Compiler see Synopsys Online Documentation SOLD which is included with the software for CD users or is available to download through the Synopsys electronic software transfer EST system Documentation on the Web which is available through SolvNet at http solvnet synopsys com The Synopsys MediaDocs Shop from which you can order printed copies of Synopsys documents at http mediadocs synopsys com You might also want to refer to the documentation for the following related Synopsys products Automated Chip Synthesis Design Budgeting e Design Vision e DesignWare components e DFT Compiler e Design Compiler FPGA e Module Compiler e PrimeTime e Power Compiler e HDL Compiler Also see the following related documents XG Mode User Guide e Using Tcl With Synopsys Tools
280. roup design mult cell mult U100 gt gt script_path pathseg wscr write script gt gt script path pathseg wscr Appendix A Design Example A 36 Example A 37 recompile scr include script path read scr current design ChipLevel include script path defaults con include script path adder16 wscr compile write f db hier o db path adder16 wscr db rpt file adderl6_wscr rpt include script path report scr include script path cascademod wscr dont touch u12 compile write f db hier o db path cascademod_wscr db rpt file cascade wscr rpt include script path report scr include script path comp16 wscr compile write f db hier o db path comp16 wscr db rpt file comp16 wscr rpt include script path report scr include script path mult8 wscr compile write f db hier o db path mult8 wscr db rpt file mult8 wscr rpt include script path report scr include script path mult16 wscr compile ungroup all write f db hier o db path mult16 wscr db rpt file mult16 wscr rpt include script path report scr report timing requirements ignore gt gt log path rpt file include script path muxmod wscr compile write f db hier o db path muxmod wscr db rpt file muxmod wscr rpt include script path report scr Compile Scripts A 37 Example A 37 recompile scr Continued include script_path pathseg wscr compile write f db hier o db path pathseg_wscr
281. roup attribute use the remove attribute command or set the ungroup attribute to false dc_shell xg t gt set ungroup object false e Use the ungroup a11 compile option to remove all lower levels of the current design hierarchy including DesignWare parts For example enter dc_shell xg t gt compile ungroup all Ungrouping Hierarchies Automatically During Optimization Design Compiler provides two options to automatically ungroup hierarchies cell count based auto ungrouping and delay based auto ungrouping To use the auto ungrouping capability enter compile auto ungroup area delay Chapter 5 Working With Designs in Memory 5 40 You can use only one argument at a time either the area argument for cell count based auto ungrouping or the delay argument for delay based auto ungrouping Note The compile ultra command also does automatic ungrouping for more information see Automatic Ungrouping Using the compile_ultra command on page 8 45 You can use the auto ungrouping capability for all compile options except top and incremental mapping Before ungrouping begins the tool issues a message to indicate that the specified hierarchy is being ungrouped After auto ungrouping use the report auto ungroup command to get a report on the hierarchies that were ungrouped during cell count based auto ungrouping or delay based auto ungrouping This report gives instance names cell names and the number of instances for eac
282. s enabled by default XG mode uses optimized memory management techniques that increase the tool capacity and can reduce runtime XG mode supports only the dctcl command language If you attempt to use any of the previous switch combinations that used to start Design Compiler in dctcl command language that is dc_shell t or dc shell tcl mode the tool automatically starts in XG mode and displays the dc shell xg t5 prompt Table 1 summarizes the different switch combinations for starting Design Compiler in XG mode and DB mode Table 1 Starting Design Compiler Mode Command Prompt XG mode default dctcl command dc_shell xg t dc_shell xg t gt language only dc shell xg_ mode dc shell tcl mode xg mode DB mode dctcl command dc shell db mode tcl mode dc shell ts language dc shell t db mode dcsh command dc shell db mode dcsh_ mode dc shells language If you enter any of the following commands dc shell displays an error message dc shell dc shell dcsh mode dc shell db mode For more information see the Design Compiler Command Line Interface Guide Chapter 1 I O Methodology Changes Design Compiler version X 2005 09 includes the following I O changes e Enhanced database format ddc In XG mode you must store your design data in a new binary format called ddc This format stores design data in a more efficient manner than the db format enab
283. s language dc shell t db mode dcsh command dc shell db mode dcsh mode dc shells language Running Design Compiler 2 11 You can also include numerous options in these command lines such as checkout to access licensed features in addition to the default features checked out by the program wait to set a wait time limit for checking out any additional licenses f to execute a script file before displaying the initial dc shell prompt x to include a dc shell statement that is executed at startup For a detailed list of options see the Design Compiler Command Line Interface Guide and the man pages for dc_ shell At startup dc_shell does the following tasks 1 2 Creates a command log file Reads and executes the synopsys dc setup files Executes any script files or commands specified by the x and f options respectively on the command line Displays the program header and dc shell prompt in the window from which you invoked dc shell The program header lists all features for which your site is licensed Exiting Design Compiler You can exit Design Compiler at any time and return to the operating system Chapter 2 Design Compiler Basics 2 12 Note By default dc_shell saves the session information in the command log file However if you change the name ofthe sh_command_log_file dctcl command language or command_log_file variable dcsh command language after you start the tool session informati
284. s problem The high effort compile uses the map_effort high option of the compile command on the initial compile on the HDL description of the design dc_shell xg t gt elaborate my design dc_shell xg t gt compile map_effort high A high effort compile pushes Design Compiler to the extreme to achieve the design goal If you have a DC Expert license a high effort compile invokes the critical path resynthesis strategy to restructure and remap the logic on and around the critical path Chapter 8 Optimizing the Design 8 54 This compile strategy is CPU intensive especially when you do not use the incremental compile option with the result that the entire design is compiled using a high map effort Performing a High Effort Incremental Compile You can often improve compile performance of a high effort compile by using the incremental compile option Also if none of the previous strategies results in a design that meets your optimization goals a high effort incremental compile might produce the desired result An incremental compile incremental mapping compile option allows you to incrementally improve your design by experimenting with different approaches An incremental compile performs only gate level optimization and does not perform logic level optimization The resulting design s performance is the same or better than the original design s This technique can still require large amounts of CPU time but it is the m
285. s subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and to comply with them Disclaimer SYNOPSYS INC AND ITS LICENSORS MAKE NO WARRANTY OF ANY KIND EXPRESS OR IMPLIED WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Registered Trademarks Synopsys AMPS Arcadia C Level Design C2HDL C2V C2VHDL Cadabra Calaveras Algorithm CATS CRITIC CSim Design Compiler DesignPower DesignWare EPIC Formality HSIM HSPICE Hypermodel iN Phase in Sync Leda MAST Meta Meta Software ModelTools NanoSim OpenVera PathMill Photolynx Physical Compiler PowerMill PrimeTime RailMill RapidScript Saber SiVL SNUG SolvNet Superlog System Compiler Testify TetraMAX TimeMill TMA VCS Vera and Virtual Stepper are registered trademarks of Synopsys Inc Trademarks Active Parasitics AFGen Apollo Apollo Il Apollo DPII Apollo GA ApolloGAII Astro Astro Rail Astro Xtalk Aurora AvanTestchip AvanWaves BCView Behavioral Compiler BOA BRT Cedar ChipPlanner Circuit Analysis Columbia Columbia CE Comet 3D Cosmos CosmosEnterprise CosmosLE CosmosScope CosmosSE Cyclelink Davinci DC Expert DC Expert Plus DC Professional DC Ultra DC Ultra Plus De
286. ses compile time therefore the default value for the phase option is false Chapter 8 Optimizing the Design 8 42 Optimizing Structured Logic If the default compile does not give the desired result for your structured logic design try the following techniques If the first technique does not give the desired results try the second one e Map the design with no flattening or structuring Enter dc_shell xg t gt set_structure false dc_shell xg t gt compile e Flatten with structuring Enter dc_shell xg t gt set_flatten true dc_shell xg t gt set_structure true dc_shell xg t gt compile When you run this command sequence Design Compiler first flattens the logic then goes back and restructures the design by sharing logic off the critical path Optimizing High Performance Designs For high performance designs that have significantly tight timing constraints you can invoke a single DC Ultra command compile_ultra for better quality of results QoR This command allows you to apply the best possible set of timing centric variables or commands during compile for critical delay optimization as well as improvement in area QoR Because compile_ultra includes all compile options and starts the entire compile process no separate compile command is necessary Note Compile options such as map_effort incremental mapping and area effort are not compatible with the compile ultra command Performing Design Implementatio
287. sics 2 8 e By typing single commands interactively on the console command line in the Design Vision window You can use this approach to supplement the subset of Design Compiler commands available through the menu interface For more information on Design Vision see the Design Vision User Guide and Design Vision online Help Setup Files When you invoke Design Compiler it automatically executes commands in three setup files These files have the same file name synopsys dc setup but reside in different directories The files contain commands that initialize parameters and variables declare design libraries and so forth Design Compiler reads the three synopsys dc setup files from three directories in the following order 1 The Synopsys root directory 2 Your home directory Running Design Compiler 2 9 3 The current working directory the directory from which you invoke Design Compiler Table 2 1 Setup Files File Location Function System wide synopsys dc setup file User defined synopsys dc setup file Design specific synopsys dc setup file Synopsys root directory BSYNOPSYS admin setup User home directory Working directory from which you started Design Compiler This file contains system variables defined by Synopsys and general Design Compiler setup information for all users at your site Only the system administrator can modify this file This file contains variabl
288. sign Advisor Design Analyzer Design Vision DesignerHDL DesignTime DFM Workbench Direct RTL Direct Silicon Access Discovery DW8051 DWPCI Dynamic Model Switcher Dynamic Macromodeling ECL Compiler ECO Compiler EDAnavigator Encore Encore PQ Evaccess ExpressModel Floorplan Manager Formal Model Checker FoundryModel FPGA Compiler Il FPGA Express Frame Compiler Galaxy Gatran HANEX HDL Advisor HDL Compiler Hercules Hercules Explorer Hercules ll Hierarchical Optimization Technology High Performance Option HotPlace HsMP US HSPICE Link i Virtual Stepper iN Tandem Integrator Interactive Waveform Viewer Jupiter Jupiter DP JupiterXT JupiterXT ASIC JVXtreme Liberty Libra Passport Libra Visa Library Compiler Magellan Mars Mars Rail Mars Xtalk Medici Metacapture Metacircuit Metamanager Metamixsim Milkyway ModelSource Module Compiler MS 3200 MS 3400 Nova Product Family Nova ExploreRTL Nova Trans Nova VeriLint Nova VHDLlint Optimum Silicon Orion ec Parasitic View Passport Planet Planet PL Planet RTL Polaris Polaris CBS Polaris MT Power Compiler PowerCODE PowerGate ProFPGA ProGen Prospector Protocol Compiler PSMGen Raphael Raphael NES RoadRunner RTL Analyzer Saturn ScanBand Schematic Compiler Scirocco Scirocco i Shadow Debugger Silicon Blueprint Silicon Early Access SinglePass SoC Smart Extraction SmartLicense SmartModel Library Softwire Source Level Design Star Star DC Sta
289. sign Compiler FPGA User Guide Chapter 1 Introduction to Design Compiler 1 8 2 Design Compiler Basics This chapter provides basic information about Design Compiler functions The chapter presents both high level and basic synthesis design flows Standard user tasks from design preparation and library specification to compile strategies optimization and results analysis are introduced as part of the basic synthesis design flow presentation This chapter includes the following sections The High Level Design Flow Running Design Compiler Following the Basic Synthesis Flow A Design Compiler Session Example 2 1 Note Even though the following terms have slightly different meanings they are often used synonymously in Design Compiler documentation Synthesis is the process that generates a gate level netlist for an IC design that has been defined using a Hardware Description Language HDL Synthesis includes reading the HDL source code and optimizing the design from that description Optimization is the step in the synthesis process that attempts to implement a combination of library cells that best meet the functional timing and area requirements of the design Compile is the Design Compiler command and process that executes the optimization step After you read in the design and perform other necessary tasks you invoke the compile command to generate a gate level netlist for the design Chapter 2 Design Compil
290. sign rule costs and the delay costs by using the set_cost_priority command to specify the ordering You must run the set_cost_priority command before running the compile command You can disable evaluation of the design rule cost function by using the no_design_rule option when running the compile command You can disable evaluation of the optimization cost function by using the only_design_rule option when running the compile command Calculating Transition Time Cost Design Compiler determines driver transition times from the technology library If the transition time for a given driver is greater that the max_transition value Design Compiler reports a design rule violation and works to correct the violation Calculating Fanout Cost Design Compiler computes fanout load for a driver by using the following equation Chapter 8 Optimizing the Design 8 32 gt fanout_load i 1 m is the number of inputs driven by the driver fanout load is the fanout load of the ith input If the calculated fanout load is greater than the max fanout value Design Compiler reports a design rule violation and attempts to correct the violation Calculating Capacitance Cost Design Compiler computes the total capacitance for a driver by using the following equation m NG je mis the number of inputs driven by the driver C is the capacitance of the th input If the calculated capacitance is greater than the max_capacitance valu
291. sts faster and uses less memory than HDL Compiler Design Compiler provides the following ways to read design files e The analyze and elaborate commands e The read_file command e The read_vhdl and read_verilog commands These commands are derived from the read_file format VHDL and read_file format verilog commands See Chapter 5 Working With Designs in Memory For detailed information on the recommended reading methods see the HDL Compiler documentation 4 Define Design Environment Design Compiler requires that you model the environment of the design to be synthesized This model comprises the external operating conditions manufacturing process temperature and voltage loads drives fanouts and wire load models It directly Following the Basic Synthesis Flow 2 21 influences design synthesis and optimization results You define the design environment by using the set command s listed under this step of Figure 2 2 See Chapter 6 Defining the Design Environment 5 Set Design Constraints Design Compiler uses design rules and optimization constraints to control the synthesis of the design Design rules are provided in the vendor technology library to ensure that the product meets specifications and works as intended Typical design rules constrain transition times set_max_transition fanout loads set_max_fanout andcapacitances set_max_capacitance These rules specify technology requirements that you
292. t DC Ultra datapath optimization Critical path slack 30 0 11 report_timing Using DC Ultra Datapath Optimization 8 69 Table 8 10 Item Summary of DC Ultra Datapath Optimization Improvements DC Expert DC Ultra datapath optimization Design area 3236 2007 report_area Overall compile time 56 6 17 68 Datapath blocks are created during compile CPU processing time 143 48 CPU time Methodology Flow To use DC Ultra datapath optimization follow the guidelines in this section Important DC Ultra datapath optimization requires both the DC Ultra Features license and the DesignWare Foundation license It is the only feature in DC Ultra to require both licenses Set set_ultra_optimization to true This checks out the DC Ultra Features license When you compile the following information is displayed in the compile log Information Datapath optimization is enabled DP 1 To use the improved datapath generators and better arithmetic components provided with Design Compiler version W2004 12 ensure the following settings set synthetic_library dw_foundation sldb Chapter 8 Optimizing the Design 8 70 set synlib enable dpgen true default is true Note To disable DC Ultra datapath optimization set hlo disable datapath optimization to true The default is false If set to true the following message is displayed Warning The built in datapath optimization in the compile command will
293. t the optimization constraints create clock clk period 10 set input delay max 1 35 clock clk ain bin set input delay max 3 5 clock clk cin set output delay max 2 4 clock clk cout set max area 0 map and optimize the design compile analyze and debug the design report constraint all violators report area save the design database write format db hierarchy output Adder16 db Chapter 2 Design Compiler Basics 2 26 Example 2 3 Top Down Compile Script in dctcl specify the libraries set target_library my_lib db set symbol_library my_lib sdb set link_library list Starget_library read the design read_verilog Adder16 v define the design environment set_operating_conditions WCCOM set_wire_load_model 10x10 set_load 2 2 sout set_load 1 5 cout set_driving_cell lib_cell FD1 all_inputs set_drive 0 clk set the optimization constraints create_clock clk period 10 set_input_delay max 1 35 clock clk ain bin set_input_delay max 3 5 clock clk cin set_output_delay max 2 4 clock clk cout set_max_area 0 map and optimize the design compile analyze and debug the design report_constraint all_violators report_area save the design database write format ddc hierarchy output Adder16 dde You can execute these commands in any of the following ways e Enterdc shell and type each command in the order shown in the example
294. ta is launched from the startpoint default multiplier of 1 Hold data is launched one clock cycle after the setup data but checked at the edge used for setup default multiplier of zero Chapter 7 Defining Design Constraints 7 22 Figure 7 6 shows the timing relationship of setup and hold times Figure 7 6 Setup and Hold Timing en FF1 FF2 CLKA CLKB FF1 CLKA Setup Time Hold Time FF2 CLKB 0 10 20 30 40 The timing path starts at the clock pin of FF1 rising edge of CLKA and ends at the data pin of FF2 Assuming that the flip flops are rising edge triggered the setup data is launched at time 0 and checked 20 time units later at the next active edge of CLKB at FF2 Hold data is launched one CLKA clock cycle time 20 and checked at the same edge used for setup checking time 20 The setup option of the set_multicycle_path command moves the edge used for setup checking to before or after the default edge For the example shown in Figure 7 6 e A setup multiplier of zero means that Design Compiler uses the edge at time zero for checking e A setup multiplier of 2 means that Design Compiler uses the edge at time 40 for checking Setting Optimization Constraints 7 23 The hold option of the set multicycle path command launches the hold data at the edge before or after the default edge but Design Compiler still checks the hold data at the edge used for checking setup As shown in Fig
295. te Fri Dec 3 13 44 07 2004 KEK KK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKK KKKEEKK Resource Sharing Report for design add in file usr home dp_add v Contained Resource Module Parameters Resources Contained Operations r256 add 4 2 DP OP 245 8218 add 1 root sub 4 r258 add 4 2 DP OP 245 8218 sub O root sub 4 r260 add 4 2 DP OP 245 8218 add 4 2 Datapath Report for design add in file usr home dp_add v RTL datapath Connections for add 4 2 DP OP 245 8218 str Bus RTL Wire Datapath Port Direction Width a I1 input 8 b I2 input 8 e I3 input 8 a I4 input 8 z O1 output 16 Datapath Blocks in add_4_2_DP_OP_245_8218 str Out Contained Operation Port Width Datapath Block Operation_Line Type O1 16 I1 12 13 14 add_4_2 UNSIGNED sub_0_root_sub_4 UNSIGNED add_1_root_sub_4 UNSIGNED Implementation Report Chapter 8 Optimizing the Design 8 74 No multiplexors to report 1 In this example the report_resources command generates the following three reports e Resource Sharing Report e Datapath Report e Implementation Report From the Resource Sharing Report you see that there are three arithmetic operators identified as add_1_root_sub 4 sub O root sub 4
296. telephone numbers at http www synopsys com support support_ctr Preface XXXiI Introduction to Design Compiler The Design Compiler tool is the core of the Synopsys synthesis products Design Compiler optimizes designs to provide the smallest and fastest logical representation of a given function It comprises tools that synthesize your HDL designs into optimized technology dependent gate level designs It supports a wide range of flat and hierarchical design styles and can optimize both combinational and sequential designs for speed area and power This chapter includes the following sections e Design Compiler and the Design Flow e Design Compiler Family Design Compiler and the Design Flow Figure 1 1 shows a simplified overview of how Design Compiler fits into the design flow Figure 1 1 Design Compiler and the Design Flow C HDL Pa HDL Compiler Constraints SDC Design Compiler IP DesignWar Timing amp power Library NI analysis a Timing Datapath Power optimization optimization optimization Technology Library J ee Formal Area Test Timing verification Symbol optimization synthesis closure Library a Ka SDF Pai PDEF Ca Optimized netlist Y Back annotation Place amp route Chapter 1 Introduction to Design Compiler 1 2 You use Design Compiler for logic synthesis w
297. th 2 from all inputs to all registers data pins edge triggered Ungroup DesignWare parts designware cells N filter find cell is oper true if dc shell status set ungroup designware cells true compile write f db hierarchy o db path design db include script_path report scr report timing requirements ignore gt gt log path rpt file Compile Scripts A 33 Example A 34 muxmod scr Script file for constraining MuxMod rpt_file muxmod rpt design muxmod current_design MuxMod include script_path defaults con Define design environment set_load 2 2 Y_IN set driving cell lib_cell FD1 all inputs Define design constraints set input delay 1 35 clock clk name D R F UPC set input delay 2 35 clock clk name MUX CNT set output delay 5 1 clock cilk name Y IN set max area 0 compile write f db hierarchy o db path design db include script path report scr Appendix A Design Example A 34 Example A 35 pathseg scr Script file for constraining path segment rpt file pathseg rpt design pathseg current design PathSegment include script path defaults con Define design environment set load 2 5 all outputs set driving cell lib cell FD1 all inputs set drive 0 clk_ name Define design rules set max fanout 6 S1 S2 Define design constraints set input delay 2 2 clock clk name
298. th version of a cell which might produce a netlist with violations When you translate CMOS three state cells into FPGA functional equivalents between the technologies might not exist Translating Designs From One Technology to Another 5 51 e Buses driven by CMOS three state components must be fully decoded Design Compiler can assume that only one bus driver is ever active If this is the case bus drivers are translated into control logic To enable this feature set the compile assume fully decoded three state buses variable to true before translating e If a three state bus within a design is connected to one or more output ports translating the bus to a multiplexed signal changes the port functionality Because translate does not change port functionality this case is reported as a translation error Removing Designs From Memory The remove design command removes designs from dc shell memory For example after completing a compilation session and saving the optimized design you can use remove design to delete the design from memory before reading in another design By default the remove design command removes only the specified design To remove its subdesigns specify the hierarchy option To remove all designs and libraries from memory specify the a11 option If you defined variables that reference design objects Design Compiler removes these references when you remove the design from memory This prevents future
299. that must be met for a functional design for example the maximum transition time for nets These conditions are called design rule constraints In addition to cell information and design rule constraints technology libraries specify the operating conditions and wire load models specific to that technology Design Compiler requires the technology libraries to be in db format In most cases your semiconductor vendor provides you with db formatted libraries If you are provided with only library source code see the Library Compiler documentation for information about generating technology libraries Understanding the Library Requirements 4 3 Design Compiler uses technology libraries for these purposes Implementing the design function The technology libraries that Design Compiler maps to during optimization are called target libraries The target libraries contain the cells used to generate the netlist and definitions for the design s operating conditions The target libraries that are used to compile or translate a design become the local link libraries for the design Design Compiler saves this information in the design s local link library attribute For information about attributes see Working With Attributes on page 5 62 Resolving cell references The technology libraries that Design Compiler uses to resolve cell references are called link libraries In addition to technology libraries link libraries can also
300. the following sections Design Compiler Modes Design Compiler Interfaces Setup Files Starting Design Compiler Exiting Design Compiler Getting Command Help Using Command Log Files Using Script Files Working with Licenses Chapter 2 Design Compiler Basics 2 6 Design Compiler Modes Design Compiler provides two modes of operation e XG mode This is the default XG mode uses optimized memory management techniques that increase the tool capacity and can reduce runtime In XG mode you use the dctcl command language to interact with Design Compiler ex DB mode This mode uses the original Design Compiler memory management techniques In DB mode you use the dcsh or dctcl command language to interact with Design Compiler In general dc shell behaves the same in XG mode and DB mode but XG mode can provide you with reduced memory consumption and runtime Unless otherwise specified all features discussed in this manual are available in both XG mode and DB mode Features that are available only in a particular mode are marked as such Additionally all examples presented in this manual work in both the dctcl and dcsh command languages When the command syntax is the same in both XG mode and DB mode the manual provides a single example preceded by the dc shell xg t5 prompt When the command syntax differs the manual provides different examples as appropriate Adctcl XG mode example is preceded by the dc_shell xg t
301. the new instance cell_name name If you do not specify an instance name Design Compiler creates one for you The created instance name has the format Un where nis an unused cell number for example U107 Note You cannot use the design_name and cel1 name options with the hdl_all_blocks or hal bussed option Example 1 To group all cells in the HDL function bar in the process ftj into design new block enter dc_shell xg t gt group hdl block ftj bar design name new block Example 2 To group all bused gates beneath process ftj into separate levels of hierarchy enter dc_shell xg t gt group hdl block ftj hdl_bussed Removing Levels of Hierarchy Design Compiler does not optimize across hierarchical boundaries therefore you might want to remove the hierarchy within certain designs By doing so you might be able to improve timing results Changing the Design Hierarchy 5 35 Removing a level of hierarchy is called ungrouping Ungrouping merges subdesigns of a given level of the hierarchy into the parent cell or design Ungrouping can be done before optimization or during optimization either explicitly or automatically Note Designs subdesigns and cells that have the dont_touch attribute cannot be ungrouped including auto ungrouping before or during optimization Ungrouping Hierarchies Before Optimization You use the ungroup command to ungroup one or more designs before optimization Use as follows
302. tical range defined 8 36 critical path resynthesis 8 54 current design IN 5 defined 5 4 displaying 5 17 current instance 5 5 changing 5 25 default 5 25 defined 5 25 displaying 5 26 resetting 5 26 current_design command 5 17 variable 5 17 current_design runtime 5 18 current_instance command 5 25 variable 5 26 D dangling logic preserving 9 14 data management 3 2 data organization 3 3 datapath extraction DC Ultra 8 63 datapath optimization DC Ultra 8 61 three methods 8 67 db format 5 8 reading 5 15 saving 5 56 DB mode 2 7 starting Design Compiler 2 11 DC Expert defined 1 5 DC FPGA defined 1 8 DC Ultra defined 1 6 DC Ultra datapath optimization 8 61 bit truncation 8 65 commands and variables specific to 8 76 datapath extraction 8 63 IN 6 datapath report 8 73 licenses required 8 62 8 70 methodology flow 8 70 three optimization methods 8 67 dc_ shell exiting 2 12 session example 2 25 DC Expert license 8 54 dcsh command language 2 8 dctcl command language 2 8 ddc format 5 8 reading 5 15 saving 5 55 default compile 8 40 default wire load attribute 6 11 default wire load mode attribute 6 12 define name rules map command 5 58 definitions attribute 5 62 Boolean optimization 8 57 checkpointing 9 6 common base period 7 12 compiler 2 2 critical range 8 36 current design 5 4 current instance 5 5 5 25 design 5 3 flat design 5 3 hierarchical cell 5 5 hierarchical design 5 3 leaf cell 5 5 negativ
303. timization In this case you do not specify the hierarchies to be ungrouped For details about ungrouping hierarchies see Removing Levels of Hierarchy on page 5 35 Chapter 8 Optimizing the Design 8 60 Optimizing Data Paths Datapath design is commonly used in applications that contain extensive data manipulation such as 3 D multimedia and digital signal processing DSP Datapath extraction transforms arithmetic operators for example addition subtraction and multiplication into datapath blocks to be implemented by a datapath generator This transformation improves the QOR by utilizing the carry save arithmetic technique Beginning with version W 2004 12 Design Compiler provides improved datapath generators and better arithmetic components for both DC Expert and DC Ultra To take advantage of these enhancements make sure that the dw_foundation sldb library is listed in the synthetic library and the synlib_enable_dpgen variable is set to true the default If necessary use the following commands e set synthetic library dw_foundation sldb e set synlib enable dpgen true These enhancements require a DesignWare license Using DC Ultra Datapath Optimization DC Ultra enables datapath extraction and explores various datapath and resource sharing options during compile DC Ultra datapath optimization provides the following benefits e Shares datapath operators e Extracts the datapath Using DC Ultra Datapath O
304. ting information The estimated capacitance and resistance are used to calculate the delay of nets After placement and routing you should back annotate the design with detailed information on the net delay The wire load model is shipped with the technology library vendors develop the wire load model based on statistical information specific to the vendor s process You can also custom generate the model based on back annotation The model includes coefficients for area capacitance and resistance per unit length and a fanout to length table for estimating net lengths the number of fanouts determines a nominal length GL 13 GL 14 Index A accessing help 2 13 all_clocks command 5 25 all_ connected command 5 48 all fanin command 8 52 all_outputs command 5 24 all_registers command 5 25 analyze command 2 21 5 10 5 14 analyzing design 9 7 architectural optimization 8 2 area constraints command to set 7 26 async set reset compiler directive 3 16 attribute values saving 5 66 setting 5 63 viewing 5 65 attributes creating 5 66 defined 5 62 design rule 7 3 getting descriptions 5 63 listing 5 40 removing 5 40 5 66 7 5 search order 5 65 5 66 viewing 9 25 attributes list of auto wire load selection 6 12 cell degradation 7 3 clock C 1 connection class 7 3 default wire load 6 11 default wire load mode 6 12 design C 2 dont touch 8 28 9 14 9 24 9 26 fanout load 7 5 is black box 9 12 is hierarchi
305. tores design data in a more efficient manner than the db format enabling increased capacity In addition reading and writing files in ddc format is faster than reading and writing files in db format The ddc format stores only logical design information e Milkyway format Chapter 5 Working With Designs in Memory 5 8 The Milkyway format allows you to read and write a Milkyway database within Design Compiler to use with other Synopsys Galaxy tools such as Physical Compiler JupiterXT and Astro The Milkyway format stores both logical and physical design information but it requires a mapped design Reading Designs Design Compiler can read designs in the formats listed in Table 5 1 Table 5 1 Supported Input Formats Format Description ddc Synopsys internal database format XG mode only Milkyway Format for reading a Milkyway database from Design Compiler XG mode only db Synopsys internal database format EDIF Electronic Design Interchange Format see the EDIF 2 0 O Interface User Guide eqn Synopsys equation format LSI LSI Logic Corporation netlist format MIF Mentor Intermediate netlist format PLA Berkeley Espresso programmable logic array format St Synopsys state table format TDL Tegas Design Language netlist format Verilog IEEE standard Verilog see the HDL Compiler documentation VHDL IEEE standard VHDL see the HDL Compiler documentation Reading Designs 5 9 Commands for Reading Design Fil
306. tributes to longer runtimes because the tool automatically re uniquifies the designs when you run the compile command You cannot turn off the uniquify process Resolving Multiple Instances of a Design Reference 8 21 e The compile once don t touch method This method uses the set_dont_touch command to preserve the compiled subdesign while the remaining designs are compiled e The ungroup method This method uses the ungroup command to remove the hierarchy These methods are described in the following sections Uniquify Method The uniquify process copies and renames any multiply referenced design so that each instance references a unique design The process removes the original design from memory after it creates the new unique designs The original design and any collections that contain it or its objects are no longer accessible Note In DB mode the original design remains in memory after you run the uniquify command You can invoke this process manually by running the uniquify command or automatically when you run the compile command The uniquification process can resolve multiple references throughout the hierarchy the current design except those having a dont_touch attribute After this process finishes the tool can optimize each design copy based on the unique environment of its cell instance Chapter 8 Optimizing the Design 8 22 You can also create unique copies for specific references by using the r
307. types allowed by the command Specifying Design Objects 5 27 To specify an object type use either the find command in desh or the get_ command in dctcl For more information about these commands see the Design Compiler Command Line Interface Guide For example to place a dont_touch attribute on hierarchical cell U1 U15 in the Count_16 design enter dc_shell xg t gt set_dont_touch usr designs Count 16 ddc Count 16 U1 U5 1 Creating Designs Thecreate design command creates a new design The memory file name is my design db and the path is the current working directory dc_shell xg t gt create design my design 1 dc_shell xg t gt list designs show file work dir mapped test ddc test 4 test DW0O1 inc 16 O test DW02 mult 16 16 1 work dir my design db my design 1 Designs created with create design contain no design objects Use the appropriate create commands such as create clock create cel1 or create port to add design objects to the new design For information about these commands see Editing Designs on page 5 47 Chapter 5 Working With Designs in Memory 5 28 It is recommended that in XG mode you store design data in the ddc format rather than the db format After you have added design objects to your design save your design in the ddc format by using the write format ddc command See Saving Designs in ddc Format on page 5 55 Copying Designs The copy_design command cop
308. u specify the name of the filename log file with the filename log file variable in the synopsys dc setup file Using Script Files You can create a command script file by placing a sequence of dc shell commands in a text file Any dc shell command can be executed within a script file In desh comments are enclosed between and For example This is a comment In detcl a at the beginning of a line denotes a comment For example This is a comment To execute a script file use one of the following commands e include in desh e source in dctcl When a script finishes processing dc shell returns a value of 1 if the script ran successfully or a value of 0 if the script failed For more information about script files see the Design Compiler Command Line Interface Guide Working with Licenses In working with licenses you need to determine what licenses are in use and know how to obtain and release licenses Chapter 2 Design Compiler Basics 2 16 Listing the Licenses in Use Before you check out a license use the 1icense_users command to determine which licenses are already in use For example dc_shell xg t gt license users bill engl Design Compiler matt eng2 Design Compiler DC Ultra Opt 2 users listed Getting Licenses When you invoke Design Compiler the Synopsys Common Licensing software automatically checks out the appropriate license For example if you read in an HDL design desc
309. um cells variable 5 41 5 43 compile auto ungroup count leaf cells variable 5 41 5 42 8 46 compile auto ungroup delay num cells variable 5 42 5 43 8 46 compile auto ungroup override wlm 5 43 8 46 compile auto ungroup override wlm variable 5 43 8 46 compile fix cell degradation variable 8 34 compile new boolean structure variable 8 57 compile ultra command 8 43 automatic ungrouping 8 45 compiler directives async set reset 3 16 enum 3 21 full case 3 25 implementation 3 19 infer multibit 3 18 infer mux 3 15 label 3 19 map to module 3 19 3 32 ops 3 19 return port name 3 32 state vector 3 21 sync set reset 3 17 compiler log format variable 9 4 connect net command 5 47 connection class attribute 7 3 constants global defining 3 26 constraints area 7 26 defining 7 1 design rule setting 7 3 removing 7 27 simplifying 3 7 timing 7 10 constraints file design example A 13 copy design command 5 29 cost calculation capacitance 8 33 fanout 8 32 maximum delay 8 34 minimum delay 8 37 minimum porosity 8 39 transition time 8 32 cost function 8 31 constraints report constraint command 9 18 design rule 8 31 optimization 8 31 create bus command 5 47 create cell command 5 47 create clock command 7 10 7 13 and path groups 8 35 clock defining 7 11 default behavior 7 11 create design command 5 28 create multibit command 3 18 create net command 5 44 5 47 create port command 5 45 5 47 critical negative slack defined 8 36 cri
310. ure 7 6 assuming a default setup multiplier e Ahold multiplier of 1 means that the hold data is launched from CLKA at time 40 and checked at CLKB at time 20 e Ahold multiplier of 1 means that the hold data is launched from CLKA at time 0 and checked at CLKB at time 20 To undo a set multicycle path command use the reset path command with similar options Using Multiple Timing Exception Commands A specific timing exception command refers to a single timing path A general timing exception command refers to more than one timing path If you execute more than one instance of a given timing exception command the more specific commands override the more general ones The following rules define the order of precedence for a given timing exception command e The highest precedence occurs when you define a timing exception from one pin to another pin e Acommand using only the from option has a higher priority than a command using only the to option e For clocks used in timing exception commands if both from and to are defined they override commands that share the same path defined by either the from or the to option Chapter 7 Defining Design Constraints 7 24 This list details the order of precedence highest at the top defined by these precedence rules 1 o SOS SO LE ar MN command from pin to pin command from clock to pin command from pin to clock command from pin command to pin command fr
311. ving ports such as clock lines keep the drive strength setting at O so that Design Compiler does not buffer the net Each semiconductor vendor has a different way of distributing these signals within the silicon Both the set drive and the set driving cell commands affect the port transition delay The set driving cel1 command can place design rule requirements such as max fanout or max transition on input ports if the specified cell has input ports The most recently used command takes precedence For example setting a drive resistance on a port with the set drive command overrides previously run set driving cel1 commands The set driving cell Command Use the set driving cel1 command to specify drive characteristics on ports that are driven by cells in the technology library This command is compatible with all the delay models including the nonlinear delay model and piecewise linear delay Chapter 6 Defining the Design Environment 6 14 model The set driving cel1 command associates a library pin with an input port so that delay calculators can accurately model the drive capability of an external driver Use the remove driving cell command or reset design command to remove driving cell attributes on ports The set_drive and set_input_transition Commands Use the set_drive or set input transition command to set the drive resistance on the top level ports of the design when the input port drive capability cannot be characte
312. w which a hierarchy is not ungrouped The default is 500 This threshold value of a hierarchy refers to the number of child cells in that hierarchy that is the cells are not counted recursively To include leaf cells of the design hierarchy set the compile auto ungroup count leaf cells variable to true Note In DB mode the compile ultra command does only delay based auto ungrouping it does not perform early area based auto ungrouping Hierarchies are not automatically ungrouped in the following cases The wire load model for the hierarchy is different from the wire load model of the parent hierarchy You can override this behavior by setting the compile auto ungroup override wlm variable to true the default is false The ungrouped child cells of the hierarchy then inherit the wire load model of the parent hierarchy Consequently the child cells might have a more pessimistic wire load model To ensure that the cells that are ungrouped into different wire load models are updated with the correct delays set the auto ungroup preserve constraints Variable to true in addition to setting the compile auto ungroup override wlim variable to true Constraints or timing exceptions are set on pins of the hierarchy Chapter 8 Optimizing the Design 8 46 You can override this behavior by setting the auto_ungroup_preserve_constraints variable to true Design Compiler ungroups the hierarchy and moves timing constraints to adjace
313. while you are interactively running Design Compiler Chapter 2 Design Compiler Basics 2 14 Using Command Log Files The command log file records the dc_shell commands processed by Design Compiler including setup file commands and variable assignments By default Design Compiler writes the command log to a file called command log in the directory from which you invoked dc_shell You can change the name of the command log file by using the command_log_file variable dcsh command language or sh_command_log_file variable dctcl command language in the synopsys dc setup file You should make any changes to these variables before you start Design Compiler If your user defined or project specific synopsys dc setup file does not contain either variable Design Compiler automatically creates the command log file Each Design Compiler session overwrites the command log file To save a command log file move it or rename it You can use the command log file to e Produce a script for a particular synthesis strategy e Record the design exploration process e Document any problems you are having Using the Filename Log File By default Design Compiler writes the log of filenames that it has read to the filename log file in the directory from which you invoked dc shell You can use the filename log file to identify data files Running Design Compiler 2 15 needed to reproduce an error in case Design Compiler terminates abnormally Yo
314. ws the path group of an endpoint Time of day TIME OF DAY time Shows the current time Total negative TOTAL NEG SLACK tns Shows the total negative slack slack of the design Trials TRIALS trials Tracks the number of transformations that the optimizer tried before making the current selection Worst negative WORST NEG SLACK wns Shows the worst negative slack slack of the current path group Analyzing Your Design During Optimization 9 5 Saving Intermediate Design Databases Design Compiler provides the capability to output an intermediate design database during the trials phase of the optimization process This capability is called checkpointing Checkpointing saves the entire hierarchy of the intermediate design You can use this intermediate design to debug design problems as described in Analyzing Design Problems on page 9 7 You can automatically checkpoint the design based on CPU time intervals optimization phase or both To checkpoint based on elapsed CPU time set the compile checkpoint cpu interval variable to the required time interval in minutes Each checkpoint overwrites the previous checkpoint file To checkpoint based on optimization phase set the compile checkpoint phases variable to true This creates a checkpoint file at the following points before starting delay optimization pre delay before starting the first phase of design rule fixing pre DRC1 before starting the second phase of des
315. y If you specify both flattening and structuring Design Compiler first performs flattening then structuring The Optimization Process 8 5 Gate Level Optimization Gate level optimization works on the generic netlist created by logic synthesis to produce a technology specific netlist It includes the following processes e Mapping This process uses gates combinational and sequential from the target technology libraries to generate a gate level implementation of the design whose goal is to meet timing and area goals You can use the various compile command options to control the mapping algorithms used by Design Compiler e Delay optimization The process goal is to fix delay violations introduced in the mapping phase Delay optimization does not fix design rule violations or meet area constraints e Design rule fixing The process goal is to correct design rule violations by inserting buffers or resizing existing cells Design Compiler tries to fix these violations without affecting timing and area results but if necessary it does violate the optimization constraints e Area optimization The process goal is to meet area constraints after the mapping delay optimization and design rule fixing phases are completed However Design Compiler does not allow area recovery to introduce design rule or delay constraint violations as a means of meeting the area constraints Chapter 8 Optimizing the Design 8 6 You can chang
316. y 5 clock Sclk name S2 S1 OP set max area 0 Perform path segmentation for multiplier group design mult cell mult U100 set input delay 10 clock Scik name mult product set output delay 5 clock Scilk name mult product set multicycle path 2 to mult product compile if shell is in xg mode 0 write hier o S db path s design db else write f ddc hier o S ddc_path design ddc source S script_path report tcl report timing requirements ignore gt gt Silog path s rpt file Compile Scripts A 23 Example A 24 characterize tcl Characterize and write script for all modules current_design ChipLevel characterize ul current design Adder16 write script gt Siscript path adder16 wtc1 current design ChipLevel characterize u2 current design CascadeMod write script format dctcl gt S script_path cascademod wtcl current_design ChipLevel characterize u3 current_design Comparator write script format dctcl gt S script_path comp16 wtcl current_design ChipLevel characterize u4 current_design Multiply8x8 write script format dctcl gt S script_path mult8 wtcl current_design ChipLevel characterize u5 current_design Multiply16x16 write script format dctcl gt S script_path mult16 wtcl current_design ChipLevel characterize ub current_design MuxMod write script format dctcl gt S script_path muxmod wtcl current_design ChipLevel characte
317. y for medium size and large designs Note The bottom up compile strategy is also known as the compile characterize write_script recompile method The bottom up compile strategy provides these advantages e Compiles large designs by using the divide and conquer approach e Requires less memory than top down compile e Allows time budgeting The bottom up compile strategy requires e iterating until the interfaces are stable Chapter 8 Optimizing the Design 8 12 e Manual revision control The bottom up compile strategy compiles the subdesigns separately and then incorporates them in the top level design The top level constraints are applied and the design is checked for violations Although it is possible that no violations are present this outcome is unlikely because the interface settings between subdesigns usually are not sufficiently accurate at the start To improve the accuracy of the interblock constraints you read in the top level design and all compiled subdesigns and apply the characterize command to the individual cell instances of the subdesigns Based on the more realistic environment provided by the compiled subdesigns characterize captures environment and timing information for each cell instance and then replaces the existing attributes and constraints of each cell s referenced subdesign with the new values Using the improved interblock constraint you recompile the characterized subdesigns and again ch
318. you specify both timing and area constraints Design Compiler attempts to meet timing goals before area goals To prioritize area constraints over total negative slack but not over worst negative slack use the ignore tns option when you specify the area constraint dc_shell xg t gt set max area ignore tns 100 Chapter 7 Defining Design Constraints 7 26 To optimize a small area regardless of timing remove all constraints except for maximum area You can use the remove_constraint command to remove constraints from your design Be aware that this command removes all optimization constraints from your design Verifying the Precompiled Design Before compiling your design verify that e The design is consistent Use the check_design command to verify design consistency For information about the check_design command see Checking for Design Consistency on page 9 2 e The attributes and constraints are correct Design Compiler provides many commands for reporting the attributes and constraints For information about these commands see Analyzing Design Problems on page 9 7 and Analyzing Timing Problems on page 9 8 Verifying the Precompiled Design 7 27 Chapter 7 Defining Design Constraints 7 28 Optimizing the Design Optimization is the Design Compiler synthesis step that maps the design to an optimal combination of specific target library cells based on the design s functional speed and area requirem
319. ype exact default latch type design type dont touch dont touch network driven by logic one driven by logic zero driving cell dont scale driving cell fall driving cell from pin fall driving cell from pin rise driving cell library fall driving cell library rise driving cell multiplier Appendix C Predefined Attributes C 2 float float true false internally generated string library cell name library cell name equation fsm pla netlist true false true false true false true false string string string string string string float Table C 2 Design Attributes Continued Attribute name Value driving_cell_pin_fall string driving_cell_pin_rise string driving cell rise string fall drive float fanout load float flatten true false flatten effort flatten minimize flatten phase flip flop type flip flop type exact is black box is combinational is hierarchical is mapped is sequential is test circuitry is unmapped latch type latch type exact load true false true false true false internally generated string library cell name true false true false true false true false true false true false true false internally generated string library cell name float C 3 Table C 2 Design Attributes Continued Attribute name Value local_link_library max_capacitance max_fanout max_time_borr

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