Xilinx UG518 SP601 Hardware, User Guide
Contents
1. Memory U2 Ska Schematic Net Name mia Kane Ji DDR2 DQ7 F9 DO7 M3 DDR2 DO8 C8 DO8 M1 DDR2 DO9 C2 DQ9 N2 DDR2_DQ10 D7 DQ10 N1 DDR2_DQ11 D3 DQ11 T2 DDR2_DQ12 D1 DQ12 T1 DDR2_DQ13 D9 DQ13 U2 DDR2_DQ14 B1 DQ14 U1 DDR2_DQ15 B9 DQ15 F2 DDR2 BAO L2 BAO F1 DDR2_BA1 L3 BA1 E1 DDR2_BA2 L1 BA2 E3 DDR2_WE_B K3 WE L5 DDR2_RAS_B K7 RAS K5 DDR2_CAS_B L7 CAS K6 DDR2_ODT K9 ODT G3 DDR2_CLK_P J8 CK G1 DDR2_CLK_N K8 CK H7 DDR2_CKE K2 CKE L4 DDR2_LDQS_P F7 LDQS L3 DDR2_LDQS_N E8 LDQS P2 DDR2_UDQS_P B7 UDQS P1 DDR2_UDQS_N A8 UDQS K3 DDR2_LDM F3 LDM K4 DDR2_UDM B3 UDM References See the Elpida DDR2 SDRAM Specifications for more information Ref 11 Also see the Spartan 6 FPGA Memory Controller User Guide Ref 3 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX 3 SPI x4 Flash Detailed Description The Xilinx Spartan 6 FPGA hosts a SPI interface which is accessible to the Xilinx iMPACT configuration tool The SPI memory device operates at 3 0V the Spartan 6 FPGA I Os are 3 3V tolerant and provide electrically compatible logic levels to directly access the SPI flash through a 2 5V bank The XC6SLX16 2CSG324 is a master device when accessing an external SPI flash memory device The SP601 SPI interface has two parallel connected configuration options see Figure 1 4 an SPI X4 Winbond W25064VSFIG 64 Mb flash memory device and a flash programming header J12 J12 supports a user def2. FPGA U1 Pin Schematic Net Name Pin Number Pin Name H12 FLASH A17 7 A17 D18 FLASH A18 6 A18 D17 FLASH A19 5 A19 G14 FLASH_A20 4 A20 F14 FLASH A21 3 A21 C18 FLASH_A22 1 A22 C17 FLASH_A23 30 A23 F16 FLASH A24 56 A24 R13 FPGA DO DIN MISO MISO1 33 DQO T14 FPGA D1 MISO2 35 DQ1 v14 FPGA_D2_MISO3 38 DQ2 U5 FLASH_D3 40 DO3 V5 FLASH_D4 44 DO4 R3 FLASH D5 46 DO5 T3 FLASH D6 49 DQ6 R5 FLASH_D7 51 DQ7 M16 FLASH_WE_B 55 WE_B L18 FLASH_OE_B 54 OE_B L17 FLASH_CE_B 14 CEO B3 FMC_PWR_GOOD_FLASH_RST_B 16 RP_B Note Memory U10 pin 56 address A24 is not connected on the 16 MB device It is made available for larger density devices References See the Numonyx Embedded Flash Memory Data Sheet for more information Ref 13 In addition see the Spartan 6 FPGA Configuration User Guide for more information Ref 2 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description 5 10 100 1000 Tri Speed Ethernet PHY The SP601 uses the onboard Marvell Alaska PHY device 88E1111 for Ethernet communications at 10 100 or 1000 Mb s The board supports a GMII MII interface from the FPGA to the PHY The PHY connection to a user provided Ethernet cable is through a Halo HFJ11 1G01E RJ 45 connector with built in magnetics On power up or on reset the PHY is configured to operate in GMII mode with PHY address 0b00111 using the settings shown in Table 1 8 These settings can
3. UG518 06 091009 Figure 1 8 SP601 Oscillator Pin 1 Location Identifiers SMA Connectors Differential A high precision clock signal can be provided to the FPGA using differential clock signals through the onboard 500 SMA connectors J8 N and J7 P Table 1 13 SP601 Clock Source Connections Source FPGA U1 Pin Schematic Net Name Pin Number Pin Name K16 SYSCLK N 5 OUT B U5 200 MHz OSC K15 SVSCLK P 4 OUT X227 MHz OSC V10 USER CLOCK 5 OUT USER SMA CLOCK H18 SMACLK N J8 1 SMA Connectors H17 SMACLK_P 17 1 24 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description 9 VITA 57 1 FMC LPC Connector The VITA 57 1 FMC expansion connector J1 on the SP601 implements the VITA 57 1 1 LPC format of the VITA 57 1 FMC standard specification The VITA 57 1 FMC LPC connector provides 68 single ended 34 differential user defined signals The VITA 57 1 FMC standard calls for two connector densities a High Pin Count HPC and a Low Pin Count LPC implementation A common 10 x 40 position 400 pin locations connector form factor is used for both versions The HPC version has 400 pins present the LPC version 160 pins The Samtec connector system is rated for signaling speeds up to9 GHz 18 Gb s based on a 3dB insertion loss point within a two level signaling environment Refer to the Samtec website for data sheets and characterization informatio
4. Appendix D References Additional Documentation The following documents are available for download at http www xilinx com products spartan6 SP601 Hardware User Guide Spartan 6 Familv Overview This overview outlines the features and product selection of the Spartan 6 family Spartan 6 FPGA Data Sheet DC and Switching Characteristics This data sheet contains the DC and switching characteristic specifications for the Spartan 6 family Spartan 6 FPGA Packaging and Pinout Specifications This specification includes the tables for device package combinations and maximum I Os pin definitions pinout tables pinout diagrams mechanical drawings and thermal specifications Spartan 6 FPGA Configuration User Guide This all encompassing configuration guide includes chapters on configuration interfaces serial and parallel multi bitstream management bitstream encryption boundary scan and JTAG configuration and reconfiguration techniques Spartan 6 FPGA SelectIO Resources User Guide This guide describes the SelectIOTM resources available in all Spartan 6 devices Spartan 6 FPGA Clocking Resources User Guide www xilinx com 5 UG518 v1 4 September 24 2010 Preface About This Guide XILINX This guide describes the clocking resources available in all Spartan 6 devices including the DCMs and PLLs e Spartan 6 FPGA Block RAM Resources User Guide This guide describes the Spartan 6 device block RAM capabili
5. Status LEDS cia ARK KARIN KEN SIAN NEN KIIN da EA 27 11 FPGA Awake LED and Suspend Jumper eee 28 12 FPGA INIT and DONE LEDs Lena 29 19 User I O 24 te VN PAK eer N Ae a Pee ead reb PE Wet uni 30 14 FPGA PROG B Pushbutton Switch 0000 00 cee eee 34 15 Configuration Options ise e eser rh a sevan Kuussa saana 35 JTAG Configuration ss isaac sia asia tue ir greci dulces rie betonen Kema 35 16 Power Management 36 AC Adapter and 5V Input Power Jack Switch eee 36 Onboard Power Supplies 222 2 rep eT ER ERE b Eua sanaa 36 Power System Test Points ied ee b is seba Ee E ib ceeds KSERKSES ERE a maa 37 SP601 Hardware User Guide www xilinx com UG518 v1 4 September 24 2010 XILINX Appendix A Default Jumper and Switch Settings Appendix B VITA 57 1 FMC LPC Connector Pinout Appendix C SP601 Master UCF Appendix D References www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Preface About This Guide This manual accompanies the Spartan 6 FPGA SP601 Evaluation Board and contains information about the SP601 hardware and software tools Guide Contents This manual contains the following chapters Chapter 1 SP601 Evaluation Board provides an overview of the SP601 evaluation board and details the components and features of the SP601 board Appendix A Default Jumper and Switch Settings Appendix B VITA 57 1 FMC LPC Connector Pinout Appendix C SP601 Master UCF
6. 10 100 1000 Tri Speed Ethernet PHY IIC Bus e 8Kb NV memory e External access 2 pin header e VITA 57 1 FMC LPC connector e 8 Clock Generation e Oscillator Differential e Oscillator Socket Single Ended 2 5V or 3 3V e SMA Connectors Differential e 9 VITA 57 1 FMC LPC Connector e 10 Status LEDs e FPGA AWAKE e INIT e DONE e 13 User I O e User LEDs e User DIP switch e User pushbuttons e GPIO male pin header e 14 FPGA PROG B Pushbutton Switch e 15 Configuration Options e 3 SPI x4 Flash both onboard and off board e 4 Linear Flash BPI e JTAG Configuration 16 Power Management e AC Adapter and 5V Input Power Jack Switch e Onboard Power Supplies o N 00 A Q N www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Related Xilinx Documents Block Diagram Figure 1 1 shows a high level block diagram of the SP601 and its peripherals LEDs Part of DIP Switch FMC LPC 10 100 1000 Expansion Connector Ethernet GMII GPIO Header USB Spartan 6 Parallel Flash XC6SLX16 Differential Clock ui Clock Socket SMA Clock Pushbuttons a S IIC EEPROM MODE SPI x4 or USB UART Expansion Connector and Header DIP Switch External Config UG518 01 090909 Figure 1 1 SP601 Features and Banking Related Xilinx Documents Prior to using the SP601 Evaluation Board users should be familiar with Xilinx resources See the following locations for additional documentation on Xilinx tools and
7. 2010 Table of Contents REVISION PUSIERA add ard 2 Preface About This Guide Guide Contents olon cee ccc cece e es 5 Additional Documentation 5 Additional Support Resources 6 Chapter 1 SP601 Evaluation Board VOL VAC W nn ENERE EE ese gs cess altace eaa PG Hee daha tre Meena e 7 Additional Information 0 0 00 ccc cnc NNN 7 Feat Sece sen ate eer atte re Geers kaa Kar ta KIEL taa at iss sn van 8 Block Diagram iuter trennt nA ne C ee teen eder bee dee dot ae tee 9 Related Xilinx Documents nn LLA 9 Detailed Description eree Ei id 10 1 Spartan 6 XC6SLX16 2CSG324 FPGA ee 11 Configuration Fetes e beta KK dme ehe eee qued ue ie eee 11 I O Voltage Rails s t aree a e pl Dd A Ee o dare Pecan edes 12 2 128 MB DDR2 Component Memory LLee e 12 3 SPI x4 Flash di ia IRR ERR ERA ERE ERE AU EA Nr RN 15 4 Linear Flash BPI L cc ee gr mra a y ea 17 5 10 100 1000 Tri Speed Ethernet PHY LL 19 6 USB to UART Bridge ss vissa nae t i batir PaRi Pe REPRE ER EREC REG 21 7 UE BUS CT E 22 8 amp Kb NV Memory e park ea be hg le dee ele Ra me hr ERN ER redes 22 8 Clock Generation lt s s si lussa ise 9 X RV WR Y XR PE rx E REREPRENYCECPES 23 Oscillator Differential 25 221204 e ete boe tah md aid 23 Oscillator Socket Single Ended 2 5V or 3 3V liess eee 24 SMA Connectors Differential soseen 24 9 VITA 57 1 FMC LPC Connector L ena 25 10
8. AI PHY TXC GTPCLK 14 GTXCLK B9 PHY TXCLK 10 TXCLK A8 PHY_TXER 13 TXER B8 PHY_TXCTL_TXEN 16 TXEN F8 PHY TXD0 18 TXDO G8 PHY_TXD1 19 TXD1 A6 PHY_TXD2 20 TXD2 B6 PHY_TXD3 24 TXD3 E6 PHY_TXD4 25 TXD4 F7 PHY TXD5 26 TXD5 A5 PHY TXD6 28 TXD6 C5 PHY_TXD7 29 TXD7 References See the Marvell Alaska Gigabit Ethernet Transceivers product page for more information Ref 16 Also see the LogiCORE IP Tri Mode Ethernet MAC User Guide Ref 5 20 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description 6 USB to UART Bridge The SP601 contains a Silicon Labs CP2103GM USB to UART bridge device U4 which allows connection to a host computer with a USB cable The USB cable is supplied in this evaluation kit Type A end to host computer Type Mini B end to SP601 connector J9 Table 1 10 details the SP601 J9 pinout Xilinx UART IP is expected to be implemented in the FPGA fabric The FPGA supports the USB to UARI bridge using four signal pins transmit TX receive RX Reguest to Send RTS and Clear to Send CTS Silicon Labs provides royalty free Virtual COM Port VCP drivers which permit the CP2103GM USB to UART bridge to appear as a COM port to host computer communications application software for example HyperTerm or TeraTerm The VCP device driver must be installed on the host PC prior to establishing communications with the SP601 Refer to the SP601 Getting S
9. D11 C14 FMC_LA10_P D8 D9 FMC_LA01_CC_N C11 C15 FMC LA10 N C8 D11 FMC LA05 P B14 C18 FMC LA14 P B2 D12 FMC LA05 N A14 C19 FMC LA14 N A2 D14 FMC LA09 P G11 C22 FMC LA18 CC P R10 D15 FMC LA09 N F10 C23 FMC LA18 CC N T10 D17 FMC LA13 P B11 C26 FMC_LA27_P R11 D18 FMC LA13 N All C27 FMC_LA27_N T11 D20 FMC LA17 CC P R8 C30 IIC SCL MAIN P11 D21 FMC LA17 CC N T8 C31 IIC SDA MAIN N10 D23 FMC LA23 P N5 SP601 Hardware User Guide www xilinx com 25 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board Table 1 14 VITA 57 1 FMC LPC Connections Cont d XILINX a s Schematic Net Name e St e E Schematic Net Name SA D24 FMC LA23 N P6 D26 FMC LA26 P U7 D27 FMC_LA26_N V7 G2 FMC CLK1 M2C P T9 H2 FMC_PRSNT_M2C_L U13 G3 FMC_CLK1_M2C_N V9 H4 FMC CLKO M2C P C10 G6 FMC LA00 CC P D9 H5 FMC CLKO M2C N A10 G7 FMC LA00 CC N C9 H7 FMC LA02 P C15 G9 FMC LA03 P C13 H8 FMC_LA02_N A15 G10 FMC LA03 N A13 H10 FMC LA04 P B16 G12 FMC LA08 P F11 H11 FMC LA04 N Al6 G13 FMC_LA08_N E11 H13 FMC LAQ7 P E7 G15 FMC LA12 P D6 H14 FMC LAO7 N E8 G16 FMC LA12 N C6 H16 FMC LA11 P B12 G18 FMC LA16 P C7 H17 FMC LA11 N A12 G19 FMC_LA16_N A7 H19 FMC LA15 P G9 G21 FMC LA20 P N7 H20 FMC LA15 N F9 G22 FMC_LA20_N P8 H22 FMC LA19 P N6 G24 FMC LA22 P R7 H23 FMC_LA19_N P7 G25 FMC LA22 N T7 H25 FMC LAZI P T
10. GA1 0 J1 C30 C31 ST MICRO IIC SDA MAIN M24 C08 WDW6TP IIC SCL MAIN Address range 54 56 0b1010100 0b1010110 2 1 OO IIC EXTERNAL ACCESS CONNECTOR UG518 13 070809 Figure 1 6 IIC Bus Topology The IIC Bus on the SP601 provides access to a 2 pin header the onboard 8 Kb EEPROM and the VITA 57 1 FMC interface The user must ensure there are no IIC address conflicts with the onboard EEPROM address when attaching additional IIC devices via FMC or the IIC 2 pin header Note that FMC Mezzanine cards are designed with 2 Kb IIC EEPROMs and will not conflict with the Carrier Card SP601 8 Kb EEPROM address range This is because 2 Kb EEPROMs reside below the 8 Kb EEPROM space See the VITA 57 1 specification along with any IIC 2 Kbit EEPROM data sheet for more details 8 Kb NV Memory The SP601 hosts a 8 Kb ST Microelectronics M24C08 WDW6TP IIC parameter storage memory device U7 The IIC address of U7 is 001010100 and U7 is not write protected WP pin 7 is tied to GND Table 1 12 IIC Memory Connections SPI Memory U7 FPGA U1 Pin Schematic Net Name Pin Number Pin Name Not Applicable Tied to GND 1 AO Not Applicable Tied to GND 2 Al www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Table 1 12 IIC Memory Connections Cont d Detailed Description SPI Memory U7 FPGA U1 Pin Schematic Net Name Pin Number Pin Name Not Appl
11. Hardware User Guide www xilinx com 35 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX J4 1 FPGA TDO Bypass FMC LPC J1 Jumper 1 2 JTAG TDO Include FMC LPC J1 Jumper 2 3 3 FMC TDO H 1x3 UG518 32 040910 Figure 1 17 VITA 57 1 FMC JTAG Bypass Jumper The JTAG chain can be used to program the FPGA and access the FPGA for hardware and software debug The JTAG connector USB Mini B J10 allows a host computer to download bitstreams to the FPGA using the iMPACT software tool and also allows debug tools such as the ChipScope Pro Analyzer tool or a software debugger to access the FPGA The iMPACT software tool can also program the SPI x4 flash or the BPI flash via the USB J10 connection iMPACT can download a temporary design to the FPGA through the JTAG This provides a connection within the FPGA from the FPGA s JTAG port to the FPGA s SPI or BPI interface Through the connection made by the temporary design in the FPGA iMPACT can indirectly program the SPI flash or BPI flash from the JTAG USB J10 connector 16 Power Management AC Adapter and 5V Input Power Jack Switch The SP601 is powered from a 5V source that is connected through a 2 1 mm x 5 5 mm type plug center positive SP601 power can be turned on or off through a board mounted slide switch When the switch is in the on position a green LED DS15 is illuminated Onboard Power Supplies The diagram in Figure 1 18 shows the power s
12. MISO2 LOC T14 9 on U17 thru series R186 100 ohm 35 on U10 3 on J12 NET FPGA D2 MISO3 LOC V14 1 on U17 38 on U10 2 on J12 NET FPGA DONE LOC V17 2 on DS9 LED NET FPGA HSWAPEN LOC D4 1 on R81 100 ohm to GND NET FPGA_INIT_B LOC U3 1 on DS10 thru series R90 27 4 ohm NET FPGA M0 CMP MISO LOC T15 1 on J3 1 on SW2 DIP Sw NET FPGA M1 LOC N12 2 on SW2 DIP Sw NET FPGA MOSI CSI B MISOO0 LOC T13 15 on U17 5 on J12 SP601 Hardware User Guide www xilinx com 45 UG518 v1 4 September 24 2010 Appendix C SP601 Master UCF XILINX NET FPGA ONCHIP TERMI LOC L6 ZIO no connect R86 is DNP NET FPGA ONCHIP TERM2 LOC C2 RZQ 100 ohm to GND NET FPGA PROG B LOC V2 1 on SW3 pushbutton NET FPGA SUSPEND LOC R16 2 on J14 NET FPGA TCK BUF LOC Al7 14 on U21 D29 on J1 NET FPGA TDI BUF LOC D15 18 on U21 NE FPGA TDO LOC D16 1 on J4 D30 on J1 NE FPGA TMS BUF LOC B18 16 on U21 D31 on J1 NET FPGA VTEMP LOC P3 if 2 on R87 150 ohm p u to VCC1V8 d NET GPIO BUTTONO LOC P4 2 on SW6 pushbutton NE GPIO BUTTONI LOC F6 2 on SW4 pushbutton N GPIO BUTTON2 LOC E4 2 on SW5 pushbutton NI GPIO BUTTON3 LOC F5 2 on SW7 pus
13. NET FMC LA22 P LOC R7 G24 on J1 NET FMC LA23 N LOC P6 D24 on J1 NET FMC LA23 P LOC N5 D23 on J1 NET FMC LA24 N LOC V8 H29 on J1 NET FMC LA24 P LOC U8 H28 on J1 NET FMC LA25 N LOC N11 G28 on J1 NET FMC LA25 P LOC M11 G27 on J1 NET FMC_LA26_N LOC V7 D27 on J1 NET FMC LA26 P LOC U7 D26 on J1 NET FMC LA27 N LOC T11 C27 on J1 NET FMC LA27 P LOC R11 C26 on J1 NET FMC LA28 N LOC V11 H32 on J1 NET FMC LA28 P LOC U11 H31 on J1 NET FMC LA29 N LOC N8 G31 on J1 NET FMC LA29 p LOC M8 G30 on J1 NET FMC_LA30_N LOC V12 H35 on J1 NET FMC LA30 P LOC T12 H34 on J1 NET FMC LA31 N LOC V6 G34 on J1 NET FMC LA31 P LOC T6 G33 on J1 NET FMC_LA32_N LOC V15 H38 on J1 NET FMC LA32 P LOC U15 H37 on J1 NET FMC LA33 N LOC N9 G37 on J1 NET FMC_LA33_P LOC M10 G36 on J1 NET FMC_PRSNT_M2C_L LOC U13 H2 on J1 NET FMC_PWR_GOOD_FLASH_RST_B LOC B3 DI on JI 16 on U10 NET FPGA AWAKE LOC P15 2 on DS8 LED NET FPGA CCLK LOC R15 16 on U17 7 on J12 NET FPGA CMP CLK LOC U16 3 on J3 NET FPGA_CMP_CS_B LOC P13 4 on J3 NET FPGA_CMP_MOSI LOC V16 2 on J3 NET FPGA_DO_DIN_MISO_MISO1 LOC R13 8 on U17 thru series R187 100 ohm 33 on U10 6 on J12 NET FPGA D1
14. is applied DS16 LED_GRN LED_RED I STATUS USB to JTAG logic DS17 LIC PWR GOOD Green Illuminates to indicate that the board power is good SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 27 Chapter 1 SP601 Evaluation Board XILINX 11 FPGA Awake LED and Suspend Jumper The suspend mode jumper permits the FPGA to enter an inactive suspend mode The FPGA Awake LED DS8 will go out when the FPGA enters this mode FPGA AWAKE IINS NHO Q31 VCC2V5 FPGA SUSPEND J14 Suspend Jumper OFF AWAKE default ON SUSPEND UG518 19 070809 Figure 1 9 FPGA Awake LED and Suspend Jumper Table 1 16 FPGA Awake Suspend Mode Jumper Connections FPGA U1 Pin P15 FPGA_AWAKE Awake LED DS8 2 Schematic Net Name Suspend Mode I O R16 FPGA_SUSPEND Suspend J14 2 See the Spartan 6 FPGA Power Management User Guide for more information Ref 10 28 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description 12 FPGA INIT and DONE LEDs The typical Xilinx FPGA power up and configuration status LEDs are present on the SP601 The INIT LED DS10 comes on after the FPGA powers up and completes its internal power on process The DONE LED DS9 comes on after the FPGA programming bitstream has been downloaded and the FPGA successfully configured VCO2V5 VCC2V5 FPGA DONE VCC2V5 LINSs d34 0
15. solutions e ISE www xilinx com ise e Answer Browser www xilinx com support e Intellectual Property www xilinx com ipcenter SP601 Hardware User Guide www xilinx com 9 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX Detailed Description Figure 1 2 shows a board photo with numbered features corresponding to Table 1 1 and the section headings in this document R190 R191 z GPIO MOMENTART mor y G 1 Beeb oy Hm dd Sy v a XILINX f FMC JTAG W INpOWN NOLO WILI WANLT S6 SP601 e ajnpokni MILO WLI WIANLT pa S a En UG518 02 091009 Figure 1 2 SP601 Board Photo The numbered features in Figure 1 2 correlate to the features and notes listed in Table 1 1 Table 1 1 SP601 Features Number Feature Notes schemaile Page 1 Spartan 6 FPGA XC6SLX16 2CSG324 2 DDR2 Component Elpida EDE1116ACBG 1 Gb 5 DDR2 SDRAM 3 SPI x4 Flash and Headers SPI select and External Headers 8 4 Linear Flash BPI StrataFlash 8 bit J3 device 3 pins 8 shared w SPI x4 10 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description Table 1 1 SP601 Features Cont d Number Feature Notes n 5 10 100 1000 Ethernet PHY GMII Marvell Alaska PHY 7 6 RS232 UART USB Bridge Uses CP2103 Serial to USB connection 10 7 TIC Goes to Header and VITA 57 1 F
16. 13 on Jl NET FMC LA08 P LOC F11 44 G12 on J1 NET FMC LAQO N LOC F10 D15 on J1 NET FMC LAQ9 P LOC G11 D14 on J1 44 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX NET FMC LA10 N LOC C8 C15 on J1 NET FMC LA10 P LOC D8 C14 on J1 NET FMC LA11 N LOC A12 H17 on J1 NET FMC LA11 P LOC B12 H16 on J1 NET FMC_LA12_N LOC C6 G16 on J1 NET FMC LA12 P LOC D6 G15 on J1 NET FMC_LA13_N LOC All D18 on J1 NET FMC LA13 P LOC B11 D17 on J1 NET FMC LA14 N LOC A2 C19 on J1 NET FMC LA14 P LOC B2 C18 on J1 NET FMC_LA15_N LOC F9 H20 on J1 NET FMC LA15 P LOC G9 H19 on J1 NET FMC LA16 N LOC A7 G19 on J1 NET FMC LA16 P LOC C7 G18 on J1 NET FMC LA17 CC N LOC T8 D21 on J1 NET FMC LA17 CC P LOC R8 44 D20 on J1 NET FMC LA18 CC N LOC T10 C23 on J1 NET FMC LA18 CC P LOC R10 C22 on J1 NET FMC_LA19_N LOC P7 H23 on J1 NET FMC LA19 p LOC N6 44 H22 on J1 NET FMC LA20 N LOC P8 G22 on J1 NET FMC_LA20_P LOC N7 G21 on J1 NET FMC_LA21_N LOC V4 dH H26 on J1 NET FMC LA21 P LOC T4 dH H25 on J1 NET FMC LA22 N LOC T7 G25 on J1
17. 31 L elli Lsa INIT_B 0 LED ON 1 INIT_B 1 LED OFF LNS NH9 0437 R90 274 196 1 16W FPGA INIT B UG518 21 070809 Figure 1 10 FPGA INIT and DONE LEDs Table 1 17 FPGAINIT and DONE LED Connections FPGA U1 Pin Schematic Net Controlled LED Name U3 FPGA INIT B DS10 INIT V17 FPGA DONE DS9 DONE SP601 Hardware User Guide www xilinx com 29 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board 30 13 User I O XILINX The SP601 provides the following user and general purpose I O capabilities e User LEDs e User DIP switch e Pushbutton switches e CPU Reset pushbutton switch e GPIO male pin header A visa b 1 R94 27 4 1 1 16W UG518 23 070809 User LEDs The SP601 provides four active high green LEDs as described in Figure 1 11 and Table 1 18 GPIO LED 3 GPIO LED 2 GPIO LED 1 GPIO LED 0 N N N r r r IE Ww owe ow 5 o o N o N O 2 5 El Tullit x n n n 4 4 4 4 11 Rot mo 1 R93 27 4 27 4 27 4 2 1 1 2 1 1 16W 1 16W 1 16W Figure 1 11 User LEDs Table 1 18 User LEDs Figfaradce Signal Name Color Label FPGA Pin Designator DS11 GPIO LED 0 Green E13 DS12 GPIO LED 1 Green C14 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description Table 1 18 User LEDs Cont d Reference Designator Sign
18. 5 on U10 N FLASH A20 LOC G14 4 on U10 NET FLASH A21 LOC F14 3 on U10 NET FLASH A22 LOC C18 1 on U10 NE FLASH A23 LOC C17 30 on U10 NE FLASH A24 LOC F16 56 on U10 NET FLASH CE B LOC L17 14 on U10 NET FLASH D3 LOC U5 40 on U10 NET FLASH D4 LOC V5 44 on U10 NE FLASH D5 LOC R3 46 on U10 N FLASH D6 LOC T3 49 on U10 N FLASH D7 LOC R5 51 on U10 NET FLASH OE B LOC L18 54 on U10 NI FLASH WE B LOC M16 55 on U10 NI FMC CLKO M2C N LOC A10 H5 on Jl N FMC CLKO M2c P LOC C10 H4 on J1 NI FMC CLK1 M2C N LOC V9 G3 on J1 NI FMC CLK1 M2c P LOC T9 G2 on J1 NI FMC LA00 CC N LOC C9 G7 on J1 N FMC LAOO CC P LOC D9 G6 on J1 N FMC LAO1 CC N LOC C11 D9 on J1 NET FMC LA01 CC P LOC D11 D8 on J1 NE FMC LAO2 N LOC Al5 H8 on J1 NE FMC LAO2 P LOC C15 H7 on J1 N FMC LA03 N LOC Al3 G10 on Jl N FMC LA03 P LOC C13 G9 on J1 NET FMC LA04 N LOC Al6 H11 on J1 NET FMC LA04 P LOC B16 H10 on J1 NE FMC LAO5 N LOC Al4 D12 on J1 NET FMC LAO05 P LOC B14 D11 on J1 NET FMC LA06 N LOC C12 C11 on J1 NET FMC LA06 P LOC D12 C10 on J1 NET FMC LAO7 N LOC E8 H14 on J1 NE FMC LA07 P LOC ET s H13 on J1 NET FMC LA08 N LOC E11 G
19. A G27 FMC LA25 P M11 H26 FMC LA21 N V4 G28 FMC_LA25_N N11 H28 FMC LA24 P U8 G30 FMC LA29 P M8 H29 FMC LA24 N V8 G31 FMC_LA29_N N8 H31 FMC LA28 P U11 G33 FMC LA31 P T6 H32 FMC LA28 N V11 G34 FMC LA31 N V6 H34 FMC_LA30_P T12 G36 FMC_LA33_P M10 H35 FMC_LA30_N v12 G37 FMC_LA33_N N9 H37 FMC_LA32_P U15 H38 FMC LA32 N V15 26 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX 10 Status LEDs Table 1 15 defines the status LEDs Table 1 15 Status LEDs Detailed Description nererence Signal Name Color Label Description Designator PWR Indicates power available for VITA 57 1 DS1 FMC_PWR_GOOD_FLASH_RST_B Green GOOD FMC expansion connector DS2 PHY_LED_LINK10 Green 10 Indicates link speed 10 Mb s DS3 PHY_LED_LINK100 Green 100 Indicates link speed 100 Mb s DS4 PHY LED LINK1000 Green 1000 Indicates link speed 1 Gb s DS5 PHY LED DUPLEX Green DUP Indicates duplex data DS6 PHY LED RX Green RX Indicates RX data activity DS7 PHY LED TX Green TX Indicates TX data activity DS8 FPGA AWAKE Green AWAKE FPGA is not in low power suspend mode Illuminates to indicate the status of the DS9 FPGA_DONE Green DONE DONE pin when the FPGA is successfully configured Illuminates after power up to indicate that DS10 FPGA INIT Red INIT the FPGA has successfully powered up and completed its internal power on process DS15 VCC5 Green Illuminates when 5V supply
20. I obr DDR2 UDM DDR2 LDM ODT 12 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description Table 1 3 Termination Resistor Reguirements Cont d Signal Name DDR2_CK P N Board Termination 1008 differential at memory component On Die Termination Notes 1 Nominal value of Vyr for DDR2 interface is 0 9V Table 1 4 FPGA On Chip OCT Termination External Resistor Requirements FPGA U1 Pin FPGA Pin Number Board Connection for OCT ZIO L6 No Connect RZO C2 1000 to GROUND Table 1 5 shows the connections and pin numbers for the DDR2 Component Memory Table 1 5 DDR2 Component Memory Connections Memory U2 oo Schematic Net Name Pin Number Pin Name J7 DDR2 A0 v J6 DDR2 A1 H5 DDR2_A2 NU L7 DDR2 A3 F3 DDR2 A4 H4 DDR2 A5 H3 DDR2 A6 d H6 DDR2_A7 P D DDR2 A8 v D1 DDR2_A9 F4 DDR2 A10 Mi D3 DDR2 All I G6 DDR2_A12 van L2 DDR2 DO0 L1 DDR2_DQ1 K2 DDR2 DQ2 K1 DDR2 DO3 e H2 DDR2 DO4 H1 DDR2 DO5 id J3 DDR2 DO6 SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 13 Chapter 1 SP601 Evaluation Board 14 Table 1 5 DDR2 Component Memory Connections Cont d XILINX
21. L7 on U2 NET DDR2_CKE LOC H7 IOSTANDARD SSTL18 II K2 on U2 NET DDR2_CLK_N LOC G1 IOSTANDARD SSTL18 II K8 on U2 NET DDR2_CLK_P LOC G3 IOSTANDARD SSTL18 II J8 on U2 NET DDR2 DQO LOC L2 IOSTANDARD SSTL18 II G8 on U2 NET DDR2 D01 LOC L1 IOSTANDARD SSTL18 II G2 on U2 NET DDR2_DQ2 LOC K2 IOSTANDARD SSTL18 II H7 on U2 NET DDR2_DQ3 LOC K1 IOSTANDARD SSTL18 II H3 on U2 NET DDR2 D04 LOC H2 IOSTANDARD SSTL18 II H1 on U2 NET DDR2_DQ5 LOC H1 IOSTANDARD SSTL18 II H9 on U2 NET DDR2_DQ6 LOC J3 IOSTANDARD SSTL18 II Fl on U2 NET DDR2 DQ7 LOC J1 IOSTANDARD SSTL18 II F9 on U2 N DDR2 D08 LOC M3 IOSTANDARD SSTL18 II C8 on U2 NET DDR2_DQ9 LOC M1 IOSTANDARD SSTL18 II C2 on U2 NET DDR2_DQ10 LOC N2 IOSTANDARD SSTL18 II D7 on U2 NET DDR2_DQ11 LOC NL IOSTANDARD SSTL18 II D3 on U2 NET DDR2_DQ12 LOC T2 IOSTANDARD SSTL18 II D1 on U2 N DDR2 DQ13 LOC Ti IOSTANDARD SSTL18 II D9 on U2 NET DDR2 D014 LOC U2 IOSTANDARD SSTL18 II Bl on U2 NET DDR2_DQ15 LOC ul IOSTANDARD SSTL18 II B9 on U2 NET DDR2 LDM LOC K3 IOSTANDARD SSTL18 II F3 on U2 N DDR2 LDOS N LOC L3 IOSTANDARD SSTL18 II E8 on U2 NI DDR2 LDQS P LOC L4 IOSTANDARD SSTL18 II F7 on U2 SP601 Hardware User Guide ww
22. LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2009 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 07 15 09 1 0 Initial Xilinx release 08 19 09 1 1 Added Appendix B VITA 57 1 FMC LPC Connector Pinout Updated Figure 1 17 Updated Table 1 4 Table 1 18 and Table 1 21 Added introductory paragraph to Appendix C SP601 Master UCF Miscellaneous typographical edits and new user guide template 05 17 10 1 2 Updated Figure 1 1 Figure 1 2 Figure 1 14 Figure 1 18 Table 1 9 Table 1 1 Table 1 11 and Table 1 15 Added Figure 1 7 Figure 1 8 and Table 1 13 e Updated 9 VITA 57 1 FMC LPC Connector page 25 Appendix B VITA 57 1 FMC LPC Connector Pinout and Appendix C SP601 Master UCF 06 16 10 1 3 Reversed order of 15 Configuration Options and 16 Power Management Updated 1 Spartan 6 XC6SLX16 2CSG324 FPGA and 2 128 MB DDR2 Component Memory Added Table 1 25 Added UG394 Spartan 6 FPGA Power Management User Guide to Appendix D References 09 24 10 14 Added Power System Test Points including Table 1 24 SP601 Hardware User Guide www xilinx com UG518 v1 4 September 24
23. MC 10 8 Clock socket SMA Differential Single Ended Differential 9 9 VITA 57 1 FMC LPC LVDS signals clocks PRSNT 6 connector 10 LEDs Ethernet PHY Status 7 11 LED Header FPGA Awake LED Suspend Header 8 12 LEDs FPGA INIT DONE 9 LED User I O active High 9 DIP Switch User I O active High 9 13 Pushbutton User I O CPU_RESET active High 9 12 pin 8 I O Header 6 pins x 2 male header with 8 I Os 10 active High 14 Pushbutton FPGA_PROG_B 9 15 USB JTAG Cypress USB to JTAG download cable 14 15 logic 16 Onboard Power Power Management 11 12 13 1 Spartan 6 XC6SLX16 2CSG324 FPGA A Xilinx Spartan 6 XC6SLX16 2CSG324 FPGA is installed on the SP601 Evaluation Board References See the Spartan 6 FPGA Data Sheet Ref 1 Configuration The SP601 supports configuration in the following modes e Master SPI x4 e Master SPI x4 with off board device e BPI e JTAG using the included USB A to Mini B cable For details on configuring the FPGA see 15 Configuration Options The Mode DIP switch SW2 is set to M 1 0 01 Master SPI default References See the Spartan 6 FPGA Configuration User Guide for more information Ref 2 SP601 Hardware User Guide www xilinx com 11 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX I O Voltage Rails There are four available banks on the LX16 CSG324 device Banks 0 1 and 2 are connected for 2 5V I O Bank 3 is used for the 1 8V DDR2 component memo
24. SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEOUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR
25. al Name Color Label FPGA Pin DS13 GPIO LED 2 Green C4 DS14 GPIO LED 3 Green A4 User DIP switch The SP601 includes an active high four pole DIP switch as described in Figure 1 12 and Table 1 19 VCC2V5 GPIO SWITCH O GPIO SWITCH 1 GPIO SWITCH 2 GPIO SWITCH 3 UG518 24 070809 Figure 1 12 User DIP Switch Table 1 19 User DIP Switch Connections FPGA U1 Pin Schematic Net Name SW8 Pin Number D14 GPIO SWITCH 0 1 E12 GPIO SWITCH 1 2 F12 GPIO SWITCH 2 3 V13 GPIO SWITCH 3 4 SP601 Hardware User Guide www xilinx com 31 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX User Pushbutton Switches The SP601 provides five active high pushbutton switches SW6 SW4 SW5 SW7 and SW9 The five pushbuttons all have the same topology as the sample shown in Figure 1 13 Four pushbuttons are assigned as GPIO and the fifth is assigned as a CPU RESET Figure 1 13 and Table 1 20 describe the pushbutton switches VCC1V8 Pushbutton CPU RESET UG518 25 070809 Figure 1 13 User Pushbutton Switch Typical Table 1 20 Pushbutton Switch Connections FPGA U1 Pin Schematic Net Name Switch Pin P4 GPIO BUTTON 0 SW6 2 F6 GPIO BUTTON 1 SW4 2 F4 GPIO BUTTON 2 SW5 2 F5 GPIO BUTTON 3 SW7 2 N4 CPU RESET SW9 2 32 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Descri
26. appropriate pins the net names below should be replaced with net names in the user RIL See the Constraints Guide for more information The latest version of the UCF can be found on the SP601 board documentation website at http www xilinx com sp601 NET CPU RESET LOC N4 2 on SW9 pushbutton NET DDR2_A0 LOC J7 IOSTANDARD SSTL18_II M8 on U2 NET DDR2 A1 LOC J6 IOSTANDARD SSTL18 II M3 on U2 NET DDR2_A2 LOC H5 IOSTANDARD SSTL18 II M7 on U2 NET DDR2_A3 LOC L7 IOSTANDARD SSTL18 II N2 on U2 NET DDR2_A4 LOC F3 IOSTANDARD SSTL18_II N8 on U2 NET DDR2_A5 LOC H4 IOSTANDARD SSTL18 II N3 on U2 NET DDR2_A6 LOC H3 IOSTANDARD SSTL18 II N7 on U2 NET DDR2_A7 LOC H6 IOSTANDARD SSTL18 II P2 on U2 NET DDR2_A8 LOC D2 IOSTANDARD SSTL18 II P8 on U2 NET DDR2_A9 LOC D1 IOSTANDARD SSTL18 II P3 on U2 NET DDR2_A10 LOC F4 IOSTANDARD SSTL18 II M2 on U2 NET DDR2_A11 LOC D3 IOSTANDARD SSTL18 II P7 on U2 NET DDR2_A12 LOC G6 IOSTANDARD SSTL18_II R2 on U2 NET DDR2 BAO LOC F2 IOSTANDARD SSTL18 II L2 on U2 NET DDR2 BA1 LOC F1 IOSTANDARD SSTL18 II L3 on U2 NET DDR2 BA2 LOC El IOSTANDARD SSTL18 II L1 on U2 NET DDR2 CAS B LOC K5 IOSTANDARD SSTL18 II
27. be overwritten via software commands passed over the MDIO interface Table 1 8 PHY Configuration Pins Pin Connection on Bit 2 Bit 1 Bit 0 Board Definition and Value Definition and Value Definition and Value CFG0 Voc25V PHYADRD 1 PHYADR 1 1 PHYADRI 0J 1 CFG1 Ground ENA_PAUSE 0 PHYADR 4 0 PHYADR 3 0 CFG2 Vec 2 5V ANEG 3 1 ANEG 2 1 ANEG 1 1 CFG3 Vec 2 5V ANEG 0 1 ENA XC 1 DIS 125 1 CFG4 Vec 2 5V HWCFG MD 2 1 HWCEG MD 1 1 HWCFG MD 0 1 CFG5 Vec 2 5V DIS FC 1 DIS SLEEP 1 HWCFG_MDJ3 1 CFG6 PHY_LED_RX SEL BDT 0 INT POL 1 75 5002 0 Table 1 9 Ethernet PHY Connections U3 M88E111 FPGA U1 Pin Schematic Net Name Pin Number Pin Name P16 PHY_MDIO 33 MDIO N14 PHY_MDC 35 MDC J13 PHY INT 32 INT B L13 PHY RESET 36 RESET B M13 PHY CRS 115 CRS L14 PHY COL 114 COL L16 PHY RXCLK 7 RXCLK P17 PHY RXER 8 RXER N18 PHY_RXCTL_RXDV 4 RXDV M14 PHY RXD0 3 RXD0 U18 PHY RXD1 128 RXD1 U17 PHY_RXD2 126 RXD2 T18 PHY RXD3 125 RXD3 T17 PHY RXD4 124 RXD4 N16 PHY_RXD5 123 RXD5 SP601 Hardware User Guide www xilinx com 19 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX Table 1 9 Ethernet PHY Connections Cont d U3 M88E111 FPGA U1 Pin Schematic Net Name Pin Number Pin Name N15 PHY_RXD6 121 RXD6 P18 PHY_RXD7 120 RXD7
28. d Switch Settings REFDES Type Function Default SW1 SLIDE POWER ON OFF OFF SW2 DIP 2 POLE MODE 1 MO ON 1 2 M1 OFF 0 SW8 DIP 4 POLE GPIO 1 OFF 2 OFF 3 OFF 4 OFF J4 HDR 1X3 JTAG BYPASS JUMP 1 2 EXCLUDE FMC J14 HDR_1X2 SUSPEND OPEN 0 AWAKE J15 HDR_1X2 SPI SELECT ON U17 SPI MEM SELECTED SP601 Hardware User Guide www xilinx com 39 UG518 v1 4 September 24 2010 Appendix A Default Jumper and Switch Settings XILINX 40 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 Appendix B Figure B 1 shows the pinout of the FMC LPC connector Pins marked NC are not connected VITA 57 1 FMC LPC Connector Pinout XILINX ololese Hef b TITIO IOI jx os lt 100 O O am 7 Ww T T T is OJO AAA a i nn Nc NC tt de AA 41 FMC LPC Connector Pinout www xilinx com Figure B 1 For more information refer to the VITA 57 1 FMC LPC Connections table Table 1 14 SP601 Hardware User Guide UG518 v1 4 September 24 2010 Appendix B VITA 57 1 FMC LPC Connector Pinout XILINX 42 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Appendix C SP601 Master UCF The UCF template is provided for designs that target the SP601 Net names provided in the constraints below correlate with net names on the SP601 rev C schematic On identifying the
29. hbutton NI GPIO_HDRO LOC N17 1 on J13 thru series R100 200 ohm N GPIO HDR1 LOC M18 3 on J13 thru series R102 200 ohm N GPIO_HDR2 LOC A3 5 on J13 thru series R101 200 ohm NET GPIO_HDR3 LOC L15 7 on J13 thru series R103 200 ohm NET GPIO_HDR4 LOC F15 2 on J13 thru series R99 200 ohm NET GPIO_HDR5 LOC B4 dH 4 on J13 thru series R98 200 ohm N GPIO_HDR6 LOC F13 44 6 on J13 thru series R97 200 ohm NI GPIO_HDR7 LOC P12 8 on J13 thru series R96 200 ohm NI GPIO LED 0 LOC E13 2 on DS11 LED NI GPIO LED 1 LOC C14 2 on DS12 LED N GPIO LED 2 LOC C4 2 on DS13 LED NET GPIO LED 3 LOC A4 2 on DS14 LED d NET GPIO SWITCH O LOC D14 1 on SW8 DIP Sw NE GPIO SWITCH 1 LOC E12 2 on SW8 DIP Sw N GPIO_SWITCH_2 LOC F12 3 on SW8 DIP Sw NET GPIO_SWITCH_3 LOC V13 4 on SW8 DIP Sw d NET IIC SCL MAIN LOC P11 44 6 on U7 thru series R203 0 ohm C30 on J1 2 on J16 NET IIC SDA MAIN LOC N10 44 5 on U7 thru series R204 0 ohm C31 on J1 1 on J16 fitt NET PHY COL LOC L14 114 on U3 NET PHY_CRS LOC M13 115 on U3 NET PHY_INT LOC J13 32 on U3 NE PHY MDC LOC N14 35 on U3 NE PHY MDIO LOC P16 33 on U3 N PHY RESET LOC L13 36 on U3 NI PHY RXCLK LOC L16 7 on U3 NI PHY RXCTL RXDV LOC N18 4 on U3 NI PHY RXDO LOC M14 3
30. icable Pulled up 0Q to VCC3V3 3 A2 N10 IC SDA MAIN 5 SDA P11 IIC SCL MAIN 6 SCL Not Applicable Tied to GND 7 WP References See the ST Micro M24C08 Data Sheet for more information Ref 17 In addition see the Xilinx XPS IIC Bus Interface Data Sheet Ref 6 Also see 9 VITA 57 1 FMC LPC Connector page 25 8 Clock Generation There are three clock sources available on the SP601 Oscillator Differential The SP601 has one 2 5V LVDS differential 200 MHz oscillator U5 soldered onto the board and wired to an FPGA global clock input e Crystal oscillator Epson EG 2121CA 200 0000M LHPA e PPM frequency jitter 50 ppm References See the Epson EG 2121CA Data Sheet for more information Ref 14 SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 23 Chapter 1 SP601 Evaluation Board XILINX Oscillator Socket Single Ended 2 5V or 3 3V One populated single ended clock socket X2 is provided for user applications The option of 3 3V or 2 5V power may be selected via a 0 resistor selection The SP601 board is shipped with a27 MHz 2 5V oscillator installed Figure 1 7 shows the unpopulated user oscillator socket indicating the socket pin 1 location Figure 1 8 shows the oscillator installed indicating its pin 1 location n oe an 0 Socket has notch E in crossbar ER I fl MIA 6 e ida ln sve Silkscreened outline A has beveled corner i MAC 10
31. ilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX 4 Linear Flash BPI SP601 Hardware User Guide U1 FPGA ADDR DATA CTRL BPI FLASH INTERFACE Detailed Description U10 NUMONYX TYPE J3vD T28F128J3D 75 UG518 09 070809 Figure 1 5 Linear Flash BPI Interface Table 1 7 BPI Memory Connections An 8 bit 16 MB Numonyx linear flash memory TE28F128 3D 75 J3D type is used to provide non volatile bitstream code and data storage The J3D devices operate at 3 0V the Spartan 6 FPGA I Os are 3 3V tolerant and provide electrically compatible logic levels to directly access the linear flash BPI through a 2 5V bank For details on configuring the FPGA see 15 Configuration Options BPI Memory U10 FPGA U1 Pin Schematic Net Name Pin Number Pin Name K18 FLASH AO 32 AO K17 FLASH Al 28 Al jig FLASH_A2 27 A2 J16 FLASH A3 26 A3 G18 FLASH A4 25 A4 G16 FLASH_A5 24 A5 H16 FLASH_A6 23 A6 H15 FLASH_A7 22 A7 H14 FLASH_A8 20 A8 H13 FLASH_A9 19 A9 F18 FLASH_A10 18 A10 F17 FLASH_A11 17 A11 K13 FLASH_A12 13 A12 K12 FLASH_A13 12 A13 E18 FLASH_A14 11 A14 E16 FLASH_A15 10 A15 G13 FLASH_A16 8 A16 www xilinx com 17 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board 18 Table 1 7 BPI Memory Connections Cont d XILINX BPI Memory U10
32. ined SPI mezzanine board The SPI configuration source is selected via SPI select jumper J15 For details on configuring the FPGA see 15 Configuration Options SPI Prog J12 TMS TDI i TDO Silkscreen TCK GND 3V3 O O O O O O O O O HDR_1X9 FPGA_PROG_B FPGA_D2_MISO3 FPGA_D1_MISO2 FPGA_MOSI_CSI_B_MISOO FPGA_DO_DIN_MISO_MISO1 VCC3V3 UG518_04_040910 Figure 1 3 J12 SPI Flash Programming Header SP601 Hardware User Guide www xilinx com UG518 v1 4 September 24 2010 15 Chapter 1 SP601 Evaluation Board SPI X4 DIN DOUT CCLK FLASH FPGA SPI INTERFACE MEMORY XILINX J12 SPIX4_CS_B SPI_CS_B WINBOND W25Q64VSFIG 2 1 ON SPI X4 U17 SPI PROGRAM OFF SPI EXT J12 O Olyis HEADER SPI SELECT JUMPER UG518 07 070809 Figure 1 4 SPI Flash Interface Topology Table 1 6 SPI x4 Memory Connections SPI MEM U17 SPI HDR J12 iis s Schematic Net Name Pin i Pin Pin Name Pin Name Number V2 FPGA PROG B 1 V14 FPGA D2 MISO3 1 103 HOLD B 2 T14 FPGA_D1_MISO2_R 9 102 WP B 3 V3 SPI CS B 4 TMS T13 FPGA MOSI CSI B MISO0 15 DIN 5 TDI R13 FPGA_D0_DIN_MISO_MISO1 8 101 DOUT 6 TDO R15 FPGA_CCLK 16 CLK 7 TCK 8 GND 9 VCC3V3 J15 2 SPIX4_CS_B 7 CS_B References See the Winbond Serial Flash Memory Data Sheet for more information Ref 12 See the XPS Serial Peripheral Interface Data Sheet for more information Ref 4 16 www x
33. l Alaska Gigabit Ethernet Transceivers Product Page ST Micro M24C08 Data Sheet www xilinx com 49 UG518 v1 4 September 24 2010 Appendix D References XILINX 50 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010
34. llowing methods e 3 SPIx4 Flash page 15 e 4 Linear Flash BPI page 17 e JTAG Configuration page 35 For more information refer to the Spartan 6 FPGA Configuration User Guide Ref 2 Table 1 23 Mode Pin Settings M2 0 Mode Pins M1 MO Configuration Mode 00 Master Byte Peripheral Interface BPI 01 Master SPI x1 x2 or x4 10 Not implemented on SP601 11 Not implemented on SP601 JTAG Configuration JTAG configuration is provided through onboard USB to JTAG configuration logic where a computer host accesses the SP601 JTAG chain through a Type A computer host side to Type Mini B SP601 side USB cable The JTAG chain of the board is illustrated in Figure 1 16 JTAG configuration is allowable at any time under any mode pin setting JTAG initiated configuration takes priority over the mode pin settings FMC bypass jumper J4 must be connected between pins 1 2 for JTAG access to the FPGA on the basic SP601 board as shown in Figure 1 16 When the VITA 57 1 FMC expansion connector is populated with an expansion module that has a JTAG chain then jumper J4 must be set to connect pins 2 3 in order to include the FMC expansion module s JTAG chain in the main SP601 JTAG chain FPGA FMC LPC Expansion m5 TDI TDO gt TDI 56 0 mE Ji n e 50 J4 E TDO O Default jumper setting excludes FMC To include FMC jumper pins 2 3 UG518 31 070809 Figure 1 16 JTAG Chain SP601
35. n U4 25 on U4 5 on X2 USER OSC Socket SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 47 Appendix C SP601 Master UCF XILINX 48 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Appendix D References This section provides references to documentation supporting Spartan 6 FPGAs tools and IP For additional information see www xilinx com support documentation index htm Documents supporting the SP601 Evaluation Board IO SN JOS DE xe 19 Spa 2 10 DS162 Spartan 6 FPGA Data Sheet DC and Switching Characteristics UG380 Spartan 6 FPGA Configuration User Guide UG388 Spartan 6 FPGA Memory Controller User Guide DS570 XPS Serial Peripheral Interface SPI Data Sheet UG138 LogiCORE IP Tri Mode Ethernet MAC v4 2 User Guide D5606 XPS IIC Bus Interface 02 008 Data Sheet UG381 Spartan 6 FPGA SelectIO Resources User Guide DS614 Clock Generator v3 01a Data Sheet DS643 Multi Port Memory Controller MPMC v5 02a Data Sheet UG394 Spartan 6 FPGA Power Management User Guide Additional documentation 11 12 13 14 15 16 17 SP601 Hardware User Guide Elpida DDR2 SDRAM Specifications EDE1116ACBG Winbond Serial Flash Memory Data Sheet W25064VSFIG Numonyx Embedded Flash Memory Data Sheet TE28F128 3D 75 Epson Toyocom Oscillator Data Sheet EG2121CA 200 0000M LHPA PCI SIG PCI Express Specifications Marvel
36. n for the RoHS compliant VITA 57 1 FMC LPC connector ASP 134603 01 and its mate Note The SP601 board VADJ voltage for the FMC LPC connector J1 is fixed at 2 5V non adjustable The 2 5V rail cannot be turned off The FMC LPC J1 connector is a keyed connector oriented so that a plug on card faces away from the SP601 board The SP601 VITA 57 1 FMC interface is compatible with 2 5V mezzanine cards capable of supporting 2 5V VADJ Table 1 14 shows the VITA 57 1 FMC LPC connections The connector pinout is in Appendix B VITA 57 1 FMC LPC Connector Pinout Any signal named FMC_HPC_xxxx that is wired between a U1 FPGA pin and some other device does not appear in this table The SP601 supports all FMC LA Bus connections available on the FMC LPC connector LA 00 33 along with all available FMC M2C clock pairs CLKO_M2C_P N and CLK1 M2C P N The SP601 does not support the FMC DP Bus connections since the SP601 does not support any Gigabit Transceivers on the FMC DP Bus Therefore DPO C2M P N DPO M2C P N and GBTCLKO M2C P N are not supported by the SP601 FMC interface For more details about FMC see the VITA57 1 specification available at http www vita com fmc html Table 1 14 VITA 57 1 FMC LPC Connections ns UE Schematic Net Name i oh Bc v Schematic Net Name m Re C10 FMC LA06 P D12 D1 FMC_PWR_GOOD_FLASH_RST_B B3 C11 FMC_LA06_N C12 D8 FMC_LA01_CC_P
37. on U3 N PHY_RXD1 LOC U18 128 on U3 N PHY RXD2 LOC Ul7 126 on U3 NET PHY RXD3 LOC T18 125 on U3 NE PHY RXD4 LOC T17 124 on U3 NET PHY_RXD5 LOC N16 123 on U3 N PHY RXD6 LOC N15 121 on U3 N PHY RXD7 LOC P18 120 on U3 NET PHY_RXER LOC P17 8 on U3 NET PHY_TXCLK LOC B9 10 on U3 NE PHY TXCTL TXEN LOC B8 16 on U3 NET PHY TXC GTXCLK LOC A9 14 on U3 NET PHY TXDO LOC F8 18 on U3 NET PHY TXD1 LOC G8 19 on U3 NET PHY TXD2 LOC A6 20 on U3 NET PHY_TXD3 LOC B6 if 24 on U3 NET PHY TXD4 LOC E6 25 on U3 NET PHY_TXD5 LOC F7 26 on U3 NET PHY_TXD6 LOC A5 28 on U3 NET PHY_TXD7 LOC C5 29 on U3 46 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX NET PHY TXER d NET SMACLK N NET SMACLK P FH NET SPI CS B T NET SYSCLK N NET SYSCLK P H NET USB 1 CTS NET USB 1 RTS NET USB 1 RX NET USB 1 TX d NET USER CLOCK LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC A8 H18 H17 V3 K16 K15 U10 T5 L12 K14 V10 d d if d d d d 13 on U3 1 on J8 SMA 1 on J7 SMA 1 on J15 4 on J12 5 on U5 EG2121CA 5 of U20 SI500D DNP 6 on U5 EG2121CA 4 of U20 SI500D DNP 22 on U4 23 on U4 24 o
38. on connector Features page 8 provides a general listing of the board features with details provided in Detailed Description page 10 Additional Information Additional information and support material is located at http www xilinx com sp601 This information includes Current version of this user guide in PDF format Example design files for demonstration of Spartan 6 FPGA features and technology Demonstration hardware and software configuration files for the SP601 linear and SPI memory devices Reference Design Files Schematics in PDF format and DxDesigner schematic format Bill of materials BOM Printed circuit board PCB layout in Allegro PCB format Gerber files for the PCB Many free or shareware Gerber file viewers are available on the internet for viewing and printing these files Additional documentation errata freguently asked guestions and the latest news For information about the Spartan 6 family of FPGA devices including product highlights data sheets user guides and application notes see the Spartan 6 FPGA website at http www xilinx com support documentation spartan 6 htm SP601 Hardware User Guide www xilinx com 7 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX Features The SP601 board provides the following features see Figure 1 2 and Table 1 1 e 1 Spartan 6 XC6SLX16 2CSG324 FPGA 128 MB DDR2 Component Memory SPI x4 Flash Linear Flash BPI
39. ption GPIO Male Pin Header The SP601 provides a 2X6 GPIO male pin header supporting 3 3V power GND and eight I Os Figure 1 14 and Table 1 21 describe the J13 GPIO Male Pin Header TE F 2888 BRE GPIO HDRO D o o oo GPIOHDR4 ZSSR T fais GPIO HDR1 oe xx 9 APIO HDR a ATTI E gi E 2832 Mano ES GPIO HDR2 Q3 A SIE NOT og 9 GPIOHDR6 2 280 U Slo jo NEN b GPIO HDR3 o 7 ojo 8 o GPIO HDR7 N 9 ojo 10 11 12 o o J13 VCC3V3 UG518 24 091009 Figure 1 14 GPIO Male Pin Header Topology Table 1 21 GPIO Header Pins FPGA U1 Pin Signal Name J13 Pin N17 GPIO HDRO 1 M18 GPIO HDR1 3 A3 GPIO HDR2 5 L15 GPIO HDR3 7 F15 GPIO_HDR4 2 B4 GPIO_HDR5 4 F13 GPIO_HDR6 6 P12 GPIO_HDR7 8 SP601 Hardware User Guide www xilinx com 33 UG518 v1 4 September 24 2010 Chapter 1 SP601 Evaluation Board XILINX 14 FPGA PROG B Pushbutton Switch The SP601 provides one dedicated active low FPGA PROG B pushbutton switch as shown in Figure 1 15 VCC2V5 Pushbutton FPGA PROG B UG518_28_041210 Figure 1 15 FPGA_PROG_B Pushbutton Switch Topology Table 1 22 FPGA_PROG_B Pushbutton Switch Connections FPGA U1 Pin Schematic Net Name SW3 Pin V2 FPGA PROG B 1 34 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Detailed Description 15 Configuration Options The FPGA on the SP601 Evaluation Board can be configured by the fo
40. ry interface of Spartan 6 FPGA s hard memory controller The voltage applied to the FPGA I O banks used by the SP601 board is summarized in Table 1 2 Table 1 2 WO Voltage Rail of FPGA Banks FPGA Bank I O Voltage Rail 0 2 5V 1 2 5V 2 2 5V 3 1 8V References See the Spartan 6 FPGA documentation for more information at http www xilinx com support documentation spartan 6 htm 2 128 MB DDR2 Component Memory There are 128 MB of DDR2 memory available on the SP601 board A 1 Gb Elpida EDE1116ACBG 84 ball DDR2 memory component is accessible through Bank 3 of the LX16 device The Spartan 6 FPGA hard memory controller is used for data transfer across the DDR2 memory interface s 16 bit data path using SSTL18 signaling The SP601 board supports the standard VCCINT setting of 1 20V 5 This setting provides the standard memory controller block MCB performance of 625 Mb s for DDR2 memory in a 2 speed grade device Signal integrity is maintained through DDR2 resistor terminations and memory on die terminations ODT as shown in Table 1 3 and Table 1 4 Table 1 3 Termination Resistor Requirements Signal Name Board Termination On Die Termination DDR2 A 14 0 49 90 to Vary DDR2_BA 2 0 49 90 to Vary DDR2_RAS_N 49 90 to Vrr DDR2 CAS N 49 90 to Ver DDR2_WE_N 49 90 to Ver DDR2_CS_N 100Q to GND DDR2_CKE 4 7KQ to GND DDR2_ODT 4 7KO to GND DDR2_DO 15 0 ODT
41. tarted Guide for driver installation instructions Table 1 10 USB Type B Pin Assignments and Signal Definitions USE let Signal Name Description 1 VBUS 5V from host system not used 2 USB DATA N Bidirectional differential serial data N side 3 USB DATA P Bidirectional differential serial data P side 4 GROUND Signal ground Table 1 11 CP2103GM Connections FPGA U1 Pin UART Function Schematic U4 CP2103GM UART Function in FPGA Net Name Pin in CP2103GM U10 RIS output USB 1 CTS 22 CTS input T5 CTS input USB 1 RIS 23 RIS output L12 TX data out USB 1 RX 24 RXD data in K14 RX data in USB 1 TX 25 TXD data out References Refer to the Silicon Labs website for technical information on the CP2103GM and the VCP drivers In addition see some of the Xilinx UART IP specifications at e http www xilinx com support documentation ip documentation xps uartlite pdf e http www xilinx com support documentation ip documentation xps uart16550 pdf SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 21 Chapter 1 SP601 Evaluation Board 22 7 IIC Bus The SP601 TIC bus hosts four items e FPGA U1IIC interface e 2 pin IIC external access header e 8 KbNV Memory e VITA 57 1 FMC Connector J1 The SP601 HC bus topology is shown in Figure 1 6 FPGA IIC INTERFACE XILINX VITA 57 1 FMC LPC FMC LPC GA0 1
42. ties e Spartan 6 FPGA DSP48A1 Slice User Guide This guide describes the architecture of the DSP48A1 slice in Spartan 6 FPGAs and provides configuration examples e Spartan 6 FPGA Memory Controller User Guide This guide describes the Spartan 6 FPGA memory controller block a dedicated embedded multi port memory controller that greatly simplifies interfacing Spartan 6 FPGAs to the most popular memory standards e Spartan 6 FPGA PCB Designer s Guide This guide provides information on PCB design for Spartan 6 devices with a focus on strategies for making design decisions at the PCB and interface level Additional Support Resources To search the database of silicon and software guestions and answers or to create a technical support case in WebCase see the Xilinx website at http www xilinx com support 6 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Chapter 1 SP601 Evaluation Board Overview The SP601 board enables hardware and software developers to create or evaluate designs targeting the Spartan amp 6 XC6SLX16 2CSG324 FPGA The SP601 provides board features for evaluating the Spartan 6 family that are common to most entry level development environments Some commonly used features include a DDR2 memory controller a parallel linear flash a tri mode Ethernet PHY general purpose I O GPIO and a UART Additional functionality can be added through the VITA 57 1 1 expansi
43. upply architecture and maximum current handling on each supply The typical operating currents are significantly below the maximum capable The board is normally shipped with a 15W power supply which should be sufficient for most applications The SP601 uses power solutions from Linear Technology Corporation LTC 36 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Power System Test Points Detailed Description The SP601 has 17 Keystone 5002 miniature PC test points TP1 to TP17 These test points are identified in the SP601 board schematic and the function of each is listed in Table 1 24 Table 1 24 SP601 Power System Test Points REFDES Function TP1 5 0V Input Voltage TP2 GND TP3 2 5V VCCO and Logic TP4 3 3V FMC and Logic TP5 LTM4616 U15 ITH pin M8 for 2 5V regulator TP6 LTM4616 U15 ITH pin F8 for 3 3V regulator TP7 1 2V VCCINT TP8 1 8V DDR2 TP9 LTM4616 U19 ITH pin M8 for 1 2V regulator TP10 LTM4616 U19 ITH pin F8 for 1 8V regulator TP11 0 9V VIT DDR2 memory termination voltage TP12 12V FMC TP13 3 0V J3D U10 Flash TP14 GND TP15 GND TP16 GND TP17 GND SP601 Hardware User Guide UG518 v1 4 September 24 2010 www xilinx com 37 Chapter 1 SP601 Evaluation Board XILINX 5V DDR2 Memory Termination La Linear Regulator U18 ion LTC3413 0 9V 3A max J18 Dual Switcher LTM4616 U15 3 3V 98A max 2 5V 98A max Dual S
44. w xilinx com 43 UG518 v1 4 September 24 2010 Appendix C SP601 Master UCF XILINX NET DDR2 ODT LOC K6 IOSTANDARD SSTL18 II K9 on U2 NET DDR2 RAS B LOC L5 IOSTANDARD SSTL18 II K7 on U2 NE DDR2_UDM LOC K4 IOSTANDARD SSTL18 II B3 on U2 NET DDR2_UDQS_N LOC P1 IOSTANDARD SSTL18 II A8 on U2 NET DDR2_UDQS_P LOC p2 IOSTANDARD SSTL18 II B7 on U2 NET DDR2 WE B LOC E3 IOSTANDARD SSTL18 II K3 on U2 fitt NE FLASH AO LOC K18 32 on U10 NET FLASH Al LOC K17 28 on U10 NET FLASH A2 LOC J18 27 on U10 NET FLASH_A3 LOC J16 26 on U10 NE FLASH A4 LOC G18 25 on U10 NET FLASH A5 LOC G16 24 on U10 NET FLASH A6 LOC H16 23 on U10 NET FLASH_A7 LOC H15 22 on U10 NE FLASH A8 LOC H14 20 on U10 NET FLASH_A9 LOC H13 19 on U10 NET FLASH_A10 LOC F18 18 on U10 NET FLASH All LOC F17 17 on U10 NET FLASH A12 LOC K13 13 on U10 NE FLASH A13 LOC K12 12 on U10 NET FLASH A14 LOC E18 11 on U10 NET FLASH A15 LOC E16 10 on U10 NET FLASH A16 LOC G13 8 on U10 NET FLASH A17 LOC H12 7 on U10 NE FLASH A18 LOC D18 6 on U10 N FLASH A19 LOC D17
45. witcher LTM4616 U19 FPGA VCCINT 1 2V 8A max S SG DDR2 Memory VCC1V8 1 8V 98A max gt Linear Regulator LT1763 U11 SPI x4 Memory VCC3VO 3 0V 9 500mA max BPI Memory Buck Boost Regulator LT1731 FMC Connector VCC12VP 12V 91A max U8 VTT DDR2 System FMC Connector VCC3V3 FPGA VCCAUX VCCO VCC2V5 FMC VADJ System UG518_03_060210 Figure 1 18 Power Supply Table 1 25 Onboard Power System Devices Device Type Reference Description Power Rail Net Power Rail Schematic Designator Name Voltage V Page LIM4616IV PBF U19 1 2 Dual 8A Switching uModule VCCINT 1 20 12 LIM4616IV PBF U19 1 2 Dual 8A Switching uModule VCCIV8 1 80 12 LIM4616IV PBF U15 1 2 Dual 8A Switching uModule VCC2V5 2 50 11 LTM4616IV4PBF U15 1 2 Dual 8A Switching uModule VCC3V3 3 30 11 LTC3413EFE PBF U18 3A Memorv Term Switching VTT DDR2 0 9 13 Regulator LTC1763CS8 TRPBF U11 500 mA LDO Linear Regulator VCC3V0 3 0 13 LT1371CR TRPBF U8 3A Switching Regulator VCC12V_P 12 13 Notes 1 Vccinr tolerance meets or exceeds the Vccinr 5 specification in the Recommended Operating Conditions table in the Spartan 6 FPGA Data Sheet Ref 1 38 www xilinx com SP601 Hardware User Guide UG518 v1 4 September 24 2010 XILINX Appendix A Default Jumper and Switch Settings Table A 1 shows the default jumper and switch settings for the SP601 Table A 1 Default Jumper an
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