JL2005D 1.3M-Pixel Digital Camera Controller
Contents
1. 1 0 08 Y T UIZ DETAIL F SECTION G G Dimension 100 pin LQFP Symbol Min Nom Max Unit A 1 6 mm A1 0 05 0 15 mm A2 1 35 1 40 1 45 mm C 0 09 0 20 mm 0 17 0 2 0 27 mm D 16 mm D1 14 mm 0 5 mm E 16 mm E1 14 mm L1 1 mm JEILIN Technology Co Ltd 12 of 13 2005 11 08 c3 JL2005D 1 3M Pixel Digital Camera Controller V1 0 JEILIN Technology Co Ltd 8F No 179 Jian Yi Rd Chung Ho Taipei Hsien Taiwan Tel 886 2 8221 5466 Fax 886 2 8221 5456 Website www jeilin com tw Email jeilin jeilin com tw 2005 JEILIN Technology Corp Ltd All rights reserved The information in this document has been carefully checked and is believed to be reliable however no responsibility can be assumed for inaccuracies that may not have been caught All information in this document is subject to change without prior notice The information contained in this document is presented only as a guide for applications of our products No responsibility is assumed by JEILIN Technology for any infringements of intellectual property or other rights of the third parties which may result from its use No license is granted by implication or otherwise under any intellectual property or other rights of JEILIN Technology or others No part of this document may be reproduced in any form in an electronic retrieval system or otherwise without the prior written permission of JEILIN Technology JEILIN2. Technology Co Ltd 13 of 13 2005 11 08
3. data bit 0 52 D DQ1 B2 16 bit SDRAM data bit 1 or Key 1 16 bit SDRAM data bit 2 or Key 2 2 53 D_DQ2 B2 8 bit SDRAM data bit 1 54 D_DQ3 B2 16 bit SDRAM data bit 3 or Key 3 16 bit SDRAM data bit 4 or Key 4 id 55 D DQ4 B2 8 bit SDRAM data bit 2 56 D DQ5 B2 16 bit SDRAM data bit 5 or Key 5 16 bit SDRAM data bit 6 or Key_6 2 57 D DQ6 B2 8 bit SDRAM data bit 3 58 D DQ7 B2 116 bit SDRAM data bit 7 or Key 7 2 59 GPIO 26 B2 General purpose 26 or DDR high byte data strobe output 60 D_LDQM O2 DDR low byte data write mask or SDRAM low byte data input output mask 61 D_WE O2 SDRAM write enable active low 62 D_CAS O2 SDRAM column address strobe active low 63 D_RAS O2 SDRAM raw address strobe active low 64 D_BSO O2 SDRAM bank address 0 65 D_BS1 O2 SDRAM bank address 1 66 D_A10 B2 SDRAM address bus or M51 nEA 67 D AO B2 SDRAM address bus or Firmware CFGO 4 JEILIN Technology Co Ltd 7 of 13 2005 11 08 OF JL2005D 1 3M Pixel Digital Camera Controller V1 0 Pin No Pin Name Type Description 68 D A1 B2 SDRAM address bus or Firmware CFG1 69 _ 2 B2 SDRAM address bus or Firmware CFG2 a 70 VCC2 5V P 2 5 core power 71 GND Ground 72 VCC3 3V P 3 3 I O power 73 D A3 B2 SDRAM address bus or Firmware_CFG3 4 D pais 16 bit SDRAM data bit 15 or Firmware_CFG15 8 bit SDRAM data bit 7 75 D
4. integrates excellent image processing features such as AE bad pixel cancellation image compression engine In DSC mode it stores the compressed image data to an external SDRAM In PC Camera mode the compressed image data is downloaded to PC though USB interface 2 Features Dual mode operation Supports CMOS image sensor with CIF VGA and 1 3M resolution Auto bad pixel cancellation AE measurement Built in compressed engine Support 8 16 bit DDR SDR SDRAM up to 128Mb 16Mb 32Mb 64Mb 128Mb SDRAM chip test and downgrade SDRAM address remapping Status LCD controller Embedded turbo mode 8051 with ISP function Built in 24K bytes mask ROM Supports external ROM USB1 1 interface Provides multi function GPlOs PWM waveform generator for mechanical shutter and flash light control Low battery detect 100 pin LQFP package COB Chip On Board 3 Application Low Cost SDRAM DSC Web JEILIN Technology Co Ltd 4 of 13 2005 11 08 c JL2005D 1 3M Pixel Digital Camera Controller V1 0 4 Block Diagram JEILIN Technology Co Ltd 5 of 13 2005 11 08 JL2005D 1 3M Pixel Digital Camera Controller V1 0 OP 5 Pin Descriptions Pin No Pin Name Description 1 VDD33_XSC P 3 3 Crystal pad power 2 XSCI ICLK Crystal oscillator pad input connect to12 MHz crystal 3 XSCO OCLK Cry
5. JL2005D 1 3M Pixel Digital Camera Controller JEILIN Technology Co Ltd 8F No 179 Jian Yi Rd Chung Ho Taipei Hsien Taiwan TEL 886 2 82215466 FAX 886 2 82215456 c JL2005D 1 3M Pixel Digital Camera Controller V1 0 Table of Contents 0 REVISION HISTORY cii kai AD HERUROR E HA EVER EQ 3 T GENERAL DESCRIPTION 4 Ze FEATURES p 4 3 ee X 4 4 BLOCK DIAGRAM 5 5 PIN DESCRIPTIONS sun 6 6 ELECTRICAL CHARATERISTIGS 10 7 PACKAGE OUTLINE AND DIMENSION 2 0020e000000000000000000n0nennoneneonenennensnesnenennensnesnnee 11 JEILIN Technology Co Ltd 2 of 13 2005 11 08 c3 JL2005D 1 3M Pixel Digital Camera Controller V1 0 0 Revision History First Release 2005 11 08 JEILIN Technology Co Ltd 3 of 13 2005 11 08 c JL2005D 1 3M Pixel Digital Camera Controller V1 0 1 General Description JL2005D is a low cost and highly integrated DSC controller It consists of CMOS image sensor interface image processing image compression engine low battery detect status LCD interface DDR SDRAM interface UART port and USB1 1 interface JL2005D supports VGA and 1 3 mega pixels CMOS sensors It provides dual mode operation DSC mode and PC CAM mode It is designed to fulfill the requirements of digital camera applications The JL2005D
6. V 0 3 to 3 6 V Vec1 Power Supply 2 5V 0 3 to 2 75 V Vin Input Voltage 0 3 to Vcc 0 3 V Vour Output Voltage 0 3 to Vect0 3 V Tsrc Storage Temperature 55 to 150 C Recommended Operation Conditions SYMBOL PARAMETER MIN TYP MAX UNITS Vec Power Supply 3 3V 3 0 3 3 3 6 V Vcci Power Supply 2 5V 2 25 2 5 2 75 V Topr Operating Temperature 0 25 70 DC Electrical Characteristics for 3 3 volts operation Under Recommended Operating Conditions Vcc 3 0V 3 6V 0 to 70 C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Vit Input Low Voltage 0 3 0 8 V Input High Voltage 2 0 Vcc 0 3 V Vr Schmitt Input Low Voltage 0 3 0 8 V Vr Schmitt Input High Voltage 2 0 Vec 0 3 V VoL Output Low Voltage 0 4 V Vou Output High Voltage 2 4 V JEILIN Technology Co Ltd 10 of 13 2005 11 08 JL2005D 1 3M Pixel Digital Camera Controller V1 0 7 Package Outline and Dimension Package Outline 100 pin LQFP Gl 2 SEATING ZEN AN PLANE 96X 100X b JEILIN Technology Co Ltd 110f 13 2005 11 08 c JL2005D 1 3M Pixel Digital Camera Controller V1 0 Package Outline 100 pin LQFP continued 10 05 bi BASE METAL Le Ai c cl a 1 8 7 0 25 S GAGE PLANE
7. _DQ14 B2 16 bit SDRAM data bit 14 or Firmware_CFG14 zh D DQ13 16 bit SDRAM data bit 13 or Firmware_CFG13 8 bit SDRAM data bit 6 77 D DQ12 B2 16 bit SDRAM data bit 12 or Firmware CFG12 78 D pati B 16 bit SDRAM data bit 11 or Firmware CFG11 m 8 bit SDRAM data bit 5 79 D DQ10 B2 16 bit SDRAM data bit 10 or Firmware CFG10 ud D pag B 16 bit SDRAM data bit 9 or Firmware CFG9 E 8 bit SDRAM data bit 4 81 D DQ8 B2 16 bit SDRAM data bit 8 8 or Firmware CFG8 4 82 GPIO_27 B2 General purpose 26 or DDR low byte data strobe output ga D UDOM 65 DDR high byte data write mask or SDRAM high byte data input output mask 84 D CLK O2 IDDR inverted clock 85 D CLK O2 DDR SDRAM clock 86 D CKE O2 SDRAM clock enable 87 11 B2 SDRAM address bus 88 D A9 B2 SDRAM address bus 89 D A8 B2 SDRAM address bus 90 D A7 B2 SDRAM address bus or Firmware CFG7 T 91 D A6 B2 SDRAM address bus or Firmware CFG6 92 D A5 B2 SDRAM address bus or Firmware CFG5 93 D A4 B2 SDRAM address bus or Firmware CFG4 94 VDD33_USB P 3 3V USB1 1 transceiver power 95 DM USB USB D signal 96 DP USB USB D signal 97 VSS33 USB USB1 1 transceiver ground 98 VDD25 PLL P 2 5 PLL and battery detect ADC power JEILIN Technology Co Ltd 8 of 13 2005 11 08 JL2005D 1 3M Pixel Digital Camera Controller V1 0 Pin No Pin Type Description 99 VSS25 PLL Ground for PLL and batt
8. ery detect ADC 100 DET Al battery detect input NOTE 1 This pin can be function as GPIO when internal mask ROM was enabled 2 To prevent from disturbing normal SDRAM data access please connect this pin to weak pull up and weak pull down resistor for input Key function 9 Must pull down this pin for normal operation 4 Signals on this pin will be latched to internal register when power on reset was active After power on reset was removed this pin will return to normal function as well 5 Pull down this pin to select external ROM or pull up this pin to select internal mask ROM 6 Each GPIO pin has it s own function select register Alt firmware can program each GPIO pin to different function individually It is as GPIO pin after power on reset Buffer Type Descriptions All CMOS input pin can take 5V tolerance BUFFER DESCRIPTION 3 3V CMOS Input pin S Schmitt Trigger B2 3 3V CMOS Bi drectional pin with 2 mA drive 3 3V CMOS Output pin with 2 mA drive 3 3V CMOS Output pin with open drain XTAL clock input XTAL clock output Analog input USB Interface Power pin Ground pin JEILIN Technology Co Ltd 9 of 13 2005 11 08 c JL2005D 1 3M Pixel Digital Camera Controller V1 0 6 ELECTRICAL CHARATERISTICS Absolute Maximum Ratings SYMBOL PARAMETER RATING UNITS Vece Power Supply 3 3
9. stal oscillator pad output connect to12 MHz crystal 4 VSS33 XSC Crystal pad ground 5 RESET 1 S Power on reset active low 6 S_PWDN O2 CMOS image sensor power down signal 7 S_RESET O2 CMOS image sensor reset signal 8 S EXCLK O2 CMOS image sensor system clock 9 S PCLK CMOS image sensor pixel clock 10 S HSYNC CMOS image sensor horizontal synchronous 11 S_VSYNC CMOS image sensor vertical synchronous 12 00 CMOS image sensor video data bus 13 D1 CMOS image sensor video data bus 14 S D2 CMOS image sensor video data bus 15 S D3 ICMOS image sensor video data bus 16 S D4 CMOS image sensor video data bus 17 D5 CMOS image sensor video data bus 18 S 06 CMOS image sensor video data bus 19 D7 CMOS image sensor video data bus 20 SCL OD Serial clock output 21 SDA OD Serial data output 22 GPIO_O B2 General purpose I O 0 or Pattern generator output 23 GPIO 1 B2 General purpose 1 or Pattern generator 1 output 24 GPIO 2 B2 General purpose I O 2 or External interrupt input active low 6 25 GPIO 3 B2 General purpose I O 26 GPIO_4 B2 General purpose I O 4 or USB Plug in input 27 GPIO 5 B2 General purpose I O 5 or MPU data write enable output active low 28 GPIO 6 B2 General purpose I O 6 29 VCC2 5V P 2 5V core power 30 GND Ground 31 VCC3 3V P 3 3 I O power 32 GPIO 7 B2 General purpose I O 7 or MPU program read enable output active low 33 GPIO_8 B2 General purpose I O 8 or MPU program
10. write enable output active low 34 GPIO 9 B2 General purpose I O 9 or MPU Address latch enable output active high 35 GPIO 10 B2 General purpose 10 or MPU address data bit 0 JEILIN Technology Co Ltd 6 of 13 2005 11 08 JL2005D 1 3M Pixel Digital Camera Controller V1 0 Pin No Pin Description 36 GPIO 11 B2 General purpose 11 or MPU address data bit 1 37 GPIO 12 B2 General purpose 12 or MPU address data bit 2 38 GPIO 13 B2 General purpose 13 or MPU address data bit 3 39 GPIO 14 B2 General purpose 14 or MPU address data bit 4 40 GPIO 15 B2 General purpose 15 MPU address data bit 5 41 GPIO 16 B2 General purpose 16 or MPU address data bit 6 42 GPIO_17 B2 General purpose I O 17 or MPU address data bit 7 43 GPIO 18 B2 General purpose 18 or MPU address bit 8 44 GPIO 19 B2 General purpose 19 or MPU address bit 9 45 GPIO 20 B2 General purpose I O 20 or MPU address bit 10 46 GPIO 21 B2 General purpose I O 21 or MPU address bit 11 47 GPIO_22 B2 General purpose I O 22 or MPU address bit 12 48 GPIO_23 B2 General purpose I O 23 or MPU address bit 13 49 GPIO_24 B2 General purpose I O 24 or MPU address bit 14 50 GPIO_25 B2 General purpose 25 or MPU address bit 15 16 bit SDRAM data bit 0 or Key_0 51 D DQO B2 8 bit SDRAM
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