DE2 Development and Education Board User Manual
Contents
1. 14896 Fitter has disabled Advanced Physical Optimization because it is not supported A p Processing 61 26 00 00 28 Figure 4 1 Compilation Message for project When compilation is complete the Quartus II software displays a message Click OK to close the message box The Ouartus II Messages window displays many messages during compilation It should not display any critical warnings it may display a few warnings that indicate that the device timing information is preliminary or that some parameters on the I O pins used for the LEDs were not set The software provides the compilation results in the Compilation Report tab as shown in Figure 4 2 aa asic YAXIO Neck My First 38 sone tere ean www terasic com FPGA Manual July 8 2015 Flow Summary Flow Status Successful Thu Jun 25 13 58 08 2015 Quartus II 64 Bit Version 15 0 0 Build 145 04 22 2015 SJ Full Version Revision Name my_first_fpga Top level Entity Name my_first_fpga Family MAX 10 Device 10M50DAF484C6GES Timing Models Preliminary Total logic elements 32 49 760 lt 1 Total combinational functions 32 49 760 lt 1 Dedicated logic registers 27 49 760 lt 1 Total registers 27 Total pins 6 360 2 Total virtual pins 0 Total memory bits 0 1 677 312 0 Embedded Multiplier 9 bit elements 0 288 0 Total PLLs 1 4 25 UFM blocks 0 1 0 ADC blocks 0 2 0 Figure 4 2 Compilation Report Example2. MAX10 NEEK FPGA Development Kit tus Il 15 0 64 bit terktile www terasic com Copyright O 2003 2015 Terasic Inc All Rights Reserved CONTENTS AAA GhapterL ST OCU CUO Naiara tania t diva 1 Ms o AP couocsmaosesnetmenecessueuacanaactiees l L BOr YOU BN on oo taa elote toco 2 ke nat WO b an E e o EE a 6 Chapter2 Assign INe DEVICE sisi nia 7 21 AD ao aaa pssst cee e PS IE A 7 Chapters LOSON nn San inai aa Aa erna oa 12 cali ae eat PPP 12 AAA e e RU E 27 IA TNS Pn aa no 33 3 4 Create a Default TimeQuest SDC Hile ooooooooooWooooo Wan 35 Chapter 4 Compile and Verify Your DESIGN s oooooooooooooooooooooooooo ooooooooooooooooooooooooooooooooo 37 an Comapile VOU DES aman oa anna SNN oba 37 2 2 Program me POA DEVICES on aon aral 39 Sa os A Aa Na 41 Chapter 5 MAX70 NEEK Technical Support ooooooco oo 44 dl ECACC UAC OSG Brantas nnen nu uan an sa arti 44 Tasic MAX10 Neek My First ii www terasic com www terasic com FPGA Manual Jul y 8 2015 Chapter 1 Introduction This tutorial provides comprehensive information that will help you understand how to create a FPGA design and run it on you MAX10 NEEK development board The following sections provide a quick overview of the design flow explain what you need to get started and describe what you will learn 1 1 Design Flow Figure 1 1shows the FPGA design flow block diagram The standard FPGA design flow begins with design entry using schematic
3. File v vlg verilog www teraSic com Masic MAX10 Neek My First 13 ter ee ae ee FPGA Manual July 8 2015 www terasic com Save in k my_first_fpga v e ae E Name a ez y h db 2 Recent Places a Desktop Libraries ai A Computer Network 4 rr Fie name 7 Save as type Verilog HDL Files v vig verilog v Cancel Y Add file to current project Figure 3 3 Saving the Verilog HDL file The resulting empty file 1s ready for you to enter the Verilog HDL code 8 Type the following Verilog HDL code into the blank simple counter v file see Figure 3 4 The Verilog File of simple_counter v It has a single clock input and a 32 bit output port module simple_counter CLOCK 50 counter out input CLOCK_50 output 31 0 counter_out reg 31 0 counter_out Tasic MAX10 Neek My First 14 www terasic com www terasic com FPGA Manual July 8 2015 always posedge CLOCK 50 on positive clock edge begin counter_out lt 1 counter_out 1 increment counter end endmodule end of module counter File Edit View Project Assignments Processing Tools Window Help Search altera com Y D2 HUJ Xa M s amp my first fpga y Ed y GEO OD AO ob ea Project Navigator EELE 2 my_first_fpga bdf 4P simple_counter v E EE EA A IS UAB E E Entity 5 It has a single clock input and a 32 bit output po
4. device selected in Available devices list A e Other n a Device and Pin Options Available devices Name Core Voltage LEs Total I Os GPIOs Memory Bits Embe 10M50DAF484C6GES 1 2V 49760 360 360 1677312 288 E 10M50DAF484C7G 1 2V 49760 360 360 1677312 z lt Migration Devices 0 migration devices selected Figure 4 6 Device and Options Choose unused pins Reserve all unused pins Choose the As input tri stated option See Figure 4 7 PM asic WAX10 Neck My First 42 one terion ean www terasic com FPGA Manual July 8 2015 General ee Fil Specify device wide options for reserving all unused pins on the device To reserve individual dual des Le Hella purpose configuration pins go to the Dual Purpose Pins tab To reserve other pins individually use Unused Pins the Assignment Editor Dual Purpose Pins Capacitive Loading Reserve all unused pins As input tri stated y Board Trace Model I O Timing Voltage Pin Placement Error Detection CRC CvP Settings Partial Reconfiguration Description Reserves all unused pins on the target device in one of 5 states as inputs that are tri stated as outputs that drive ground as outputs that drive an unspecified signal as input tri stated with bus hold or as input tri stated with weak pull up Reset Figure 4 7 Setting unused pins Click twice OK 4 In the Processing menu choose Start Compilation After the compilation Choose Tools gt Programm
5. pll qi ibrary sai 4 Basic gt Ari pos gt Bri incIkO frequency 50 000 MHz OP 4 Cl a Operation Mode Normal EN Pr Cik Dc o an ol SSeS Tas TEA gt Co 4 P Compile Dee gt I C gt P Analysis gt Mis Figure 3 14 Place the PLL Symbol 12 Move the mouse so that the cursor also called the selection tool is over the pll symbol s cO output pin The orthogonal node tool cross hair icon appears 13 Click and drag a bus line from the cO output to the simple counter clock input This action ties the pll output to the simple_counter input see Figure 3 15 inclkO frequency 50 000 MHz Operation Mode Normal cik Ratio Ph dg DC Figure 3 15 Draw a Bus Line connect pll c0 port to simple counter CLOCK 50 port 14 Add an input pin and an output bus with the following steps a Double click my_first_fpga bdf blank area b Under Libraries libraries gt primitives gt pin gt input See Figure 3 16 asic 4X10 Neck My First 24 eee er www terasic com FPGA Manual July 8 2015 c Click OK If you need more space to place symbols you can use the vertical and horizontal scroll bars at the edges of the BDF window to view more drawing space Pal Symbol Libraries gt amp logic gt amp other d E pin E bidir 8 input amp output E storage Name input ms E Repeat insert mode Insert symbol as block Cancel Figure 3 16 Input pin symbol d Place
6. the new pin onto the BDF so that it is touching the input to the pll symbol e Use the mouse to click and drag the new input pin to the left notice that the ports remain connected as shown in Figure 3 17 inclkO frequency 50 000 MHz Operation Mode Normal Cik Ratio Ph dg DC Figure 3 17 Connecting the PLL symbol and Input port f Change the pin name by double clicking pin name and typing CLOCK_50 see Figure 3 18 This name correlates to the oscillator clock that 1s connected to the FPGA PM asic WAXI0 Neck My First 25 sone baina www terasic com FPGA Manual July 8 9015 ia Pin Properties General To create multiple pins enter a name in AHDL bus notation For example name 3 0 or enter a comma seperated list of names Pin name s CLOCK_50l Default value VCC ha Figure 3 18 Change the input port name g Using the Orthogonal Bus tool draw a bus line connected on one side to the simple_counter output port and leave the other end unconnected at about 4 to 8 grid spaces to the right of the simple_counter h Right click the new output bus line and choose Properties i Type counter 31 0 as the bus name see Figure 3 19 The notation X Y is the Quartus II method for specifying the bus width in BDF schematics where X is the most significant bit MSB and Y is the least significant bit LSB jJ Click OK Figure 3 20 shows the BDF asic NAXIO Neck My First 26 e tere ean www te
7. www terasic com MAX10 Neek My First FPGA Manual 20 www terasic com July 8 2015 1 ALTPLL Hlparameter 7 Bloutput MIEDA B Summary Settings Reconfi perry Clocks General Modes Inputs Lock gt Bandwidth SS gt Clock switchover gt Able to implement the reguested PLL inclkO frequency 50 000 MHz i Optional Inputs Operation Mode Normal __ Create an pllena input to selectively enable the PLL ox Rato Ph daN D C Create an areset input to asynchronously reset the PLL col 1 1 0 00 50 00 _ Create an pfdena input to selectively enable the phase frequency detector Lock Output Create locked output Enable self reset on loss lock Advanced Parameters Using these parameters is recommended for advanced users only Create output file s using the Advanced PLL parameters Configurations with output clock s that use cascade counters are not supported Figure 3 10 MegaWizard Plug In Manager page2 of 12 Selections 7 Click Next three times 8 At the top of the wizard click the tab 3 Output Clocks to jump to the Output Clocks gt clk cO page Clock Division Settings input 10 Figure 3 11 MAX10 Neek My First 21 oe as ean www terasic com FPGA Manual Jul y 8 2015 O Parameter Output I E 5 Summary Settings Clocks clk c4 G0 Gore External Output Clock lement the requeste Y Use this clock inclkO frequency 50 000 MHz Clock Tap Settings Requested Settings Actual Se
8. 0 00 20 Type Message p Messages Figure 3 31 Default SDC Naming the SDC with the same name as the top level file except for the sdc extension causes the Quartus II software to using this timing analysis file automatically by default If you used another name you would need to add the SDC to the assignments file list MAX10 Neek My First 36 FPGA Manual www terasic com July 8 2015 www terasic com Chapter 4 Compile and Verify Your Design After creating your design you must compile it Compilation converts the design into a bitstream that can be downloaded into the FPGA The most important output of compilation is an SRAM Object File sof which you use to program the device The software also generates other report files that provide information about your code as it compiles 4 1 Compile Your Design If you want to store SOF in memory device such as flash or EEPROMs you must first convert the SOF to a file type specifically for the targeted memory device Now that you have created a complete Quartus II project and entered all assignments you can compile the design In the Processing menu choose Start Compilation or click the Play button on the toolbar If you are asked to save changes to your BDF click Yes While compiling your design the Quartus II software provides useful information about the compilation see Figure 4 1 asic NAXIO Neck My First 37 sone tere ean w
9. 00 50 00 Figure 3 24 Place the Ipm mux symbol 13 Add input buses and output pins to the counter bus mux symbol as follows a Using the Orthogonal Bus tool draw bus lines from the datalx 3 0 and dataOx 3 0 Input ports to about 8 to 12 grid spaces to the left of counter_bus_mux PM asic MIO Neck My First 30 sane teenie een www terasic com FPGA Manual July 8 9015 b Draw a bus line from the result 3 0 output port to about 4 to 8 grid spaces to the right of counter_bus_mux c Right click the bus line connected to data1x 3 0 and choose Properties d Name the bus counter 26 23 which selects only those counter output bits to connect to the four bits of the datalx input Because the input busses to counter_bus_mux have the same names as the output bus from simple_counter counter x y the Quartus II software knows to connect these busses e Click OK f Right click the bus line connected to data0x 3 0 and choose Properties g Name the bus counter 24 21 which selects only those counter output bits to connect to the four bits of the datalx input h Click OK Figure 3 25 shows the renamed buses Figure 3 25 Renamed counter_bus_mux Bus Lines If you have not done so save your project file before continuing 14 Double click my_first_fpga bdf Blank area 15 Under Libraries double click quartus libraries gt primitives gt pin gt output see Figure 3 26 asic NAXIO Neck My First 31 e tere
10. 4 2 Program the FPGA Device After compiling and verifying your design you are ready to program the FPGA on the development board You download the SOF you just created into the FPGA using the USB Blaster II circuitry on the board Set up your hardware for programming using the following steps a Connect the power supply cable to your board and to a power outlet b For the MAX10 NEEK board connect the USB Blaster II included in your development kit to J9 and the USB cable to the USB Blaster II Connect the other end of the USB cable to the host computer Refer to the getting started user guide for detailed instructions on how to connect the cables c Turn the MAX10 NEEK board on using the on off switch Program the FPGA using the following steps 1 Choose Tools gt Programmer The Programmer window opens See Figure 4 3 asic NAXIO Neck My First 39 ee www terasic com FPGA Manual July 8 9015 File Edit View Processing Tools Window Help 4 Hardware Setup NEEK10 USB 1 Mode JTAG Enable real time ISP to allow background programming when available Device Checksum Usercode Program Verify Blank Examine Security Configure Check Bit Figure 4 3 Programmer Window 2 Click Hardware Setup 3 If it is not already turned on turn on the USB Blaster II USB 0 option under currently selected hardware See Figure 4 4 Hardware Settings JTAG Settings Select a programming ha
11. 484C6GES ramped i2 3 4 5 6 7 8 9 1011 12 13 14 15 16 17 18 OO Search altera com Direction Input Input Output Output Output Output Location PIN_N5 PIN_T22 PIN_C3 PIN A3 PIN B3 PIN C2 B2 NO B5 NO B8 NO B8 NO B8 NO 25 LEDR O B8 NO lt lt new node gt gt I O Bank VREF Group I O Standard 2 5 V default 2 5 V default 2 5 V default 2 5 V default 2 5 V default 2 5 V default Reserved Figure 3 30 Completed Pin Planning Example Now you are finished creating your Quartus II design 3 4 Create a Default TimeQuest SDC File irrent Streng Slew Rate 12mA 12mA 12mA 12mA 12mA 12mA ault ault ault 2 default ault 2 default ault 2 default ault 2 default Timing settings are critically important for a successful design For this tutorial you will create a basic Synopsys Design Constraints File sdc that the Quartus II TimeQuest Timing Analyzer uses during design compilation For more complex designs you will need to consider the timing requirements more carefully To create an SDC perform the following steps 1 Open the TimeQuest Timing Analyzer by choosing Tools gt TimeQuest Timing Analyzer 2 Choose File gt New SDC file The SDC editor opens 3 Type the following code into the editor MAX10 Neek My First 35 FPGA Manual www terasic com www terasic com July 8 2015 create_clock
12. Board on which you will test your project Using a development board helps you to verify whether your design is really working NW You have gone through the quick start guide and or the getting started user guide for your development kit These documents ensure that you have e Installed the required software e Determined that the development board functions properly and is connected to your computer Next step you should installed the USB Blaster II driver Plug in the 5 volt adapter to provide power to the board Use the mini USB cable to connect the mini USB connector J8 type B on the MAX10 NEEK board to a USB port on a computer that runs the Quartus II software Turn on the power switch on the MAX10 NEEK board The computer will recognize the new hardware connected to its USB port but it will be unable to proceed if it does not have the required driver already installed The MAX10 NEEK board is programmed by using Altera USB Blaster II mechanism If the USB Blaster II driver is not already installed the Driver Software Installation window in Figure 1 2 will appear asic NAXIO Neck My First 2 sone teres ean www terasic com FPGA Manual July 8 2015 Device driver software was not successfully installed Please consult with your device manufacturer for assistance getting this device installed Unidentified Device DE No driver found What can I do rf my device did not install properly Figure 1 2 Driver Installation wind
13. Dewa san o o miia RY OVO Orv ob ee Project Navigator 18x Q x Entity A MAX 10 10M50DAF484C6GES gt my_first_fpga E gt A Hierarchy Su Tasks Tax Flow Customize Y View Quartus II Information 4 gt Compile Design gt P Analysis amp Synthesis y E AA ID Message 253020 Default device 10M08DAF484C7G is automatically selected for the device fa Messages Figure 2 4 my_first_fpga project TadasiC MAX10 Neek My First 11 www terasic com www terasic com FPGA Manual July 8 2015 Chapter 3 Design Entry 3 1 Add a PLL Megafunction This section describes How to Add a PLL Megafunction In the design entry step you create a schematic or Block Design File bdf that is the top level design You will add library of parameterized modules LPM functions and use Verilog HDL code to add a logic block When creating your own designs you can choose any of these methods or a combination of them l Choose File gt New gt Block Diagram Schematic File see Figure 3 1 to create a new file Block1 bdf which you will save as the top level design New Quartus IT Project 4 Design Files AHDL File Block Diagram Schematic File EDIF File Qsys System File State Machine File SystemVerilog HDL File Td Script File Verilog HDL File VHDL File 4 Memory Files Hexadecimal Intel Format File Memory Initialization File 4 Verification Debugging Files In System Sourc
14. EG gt On Chip Memory gt Simulation Debug and Verification gt Bitec Figure 3 21 Selecting Ipm mux 7 Under How many data inputs do you want Select 2 inputs default 8 Under How wide should the data input and result output be Select 4 see Figure 3 22 asic NAXIO Neck My First 28 e tere ean www terasic com FPGA Manual July 8 9015 TA Alr F ariarniar inane Zara HIUG in Manage 30 LPM_MUX Parameter Settings Currently selected device family Max 10 Match project default How many data inputs d 2 hd NUW WIV SIIWUlU LITE E E data input and the 4 bits Testi Arak hueso ha Do you want to pipeline the multiplexer Yes I want an output latency of 1 Y dock cycles Create an asynchronous Clear input Create a Clock Enable input eee Figure 3 22 Ipm mux settings 9 Click Next 10 Click Finish twice The Symbol window appears see Figure 3 23 for an example asic 4X10 Neck My First 29 yee PE T can www terasic com FPGA Manual July 8 2015 pe Symbol Libraries 4 E Project EF counter bus mux E pill E simple counter gt amp d altera 15 0 145 quart Name counter_bus_mux les E Repeat insert mode _ Insert symbol as block Figure 3 23 Ipm mux Symbol 11 Click OK 12 Place the counter bus mux symbol below the existing symbols on the BDF See Figure 3 24 incIkO frequency 50 000 MHz Operation Mode Normal co 1 10 0
15. First FPGA Project 3 3 Assign the Pins In this section you will make pin assignments Before making pin assignments perform the following steps 1 Choose Processing gt Start gt Start Analysis amp Elaboration in preparation for assigning pin locations 2 Click OK in the message window that appears after analysis and elaboration completes To make pin assignments that correlate to the KEY 0 and CLOCK 50 input pins and LEDR 3 0 output pin perform the following steps 1 Choose Assignments gt Pins Planner which opens the Pin Planner a spreadsheet like table of specific pin assignments The Pin Planner shows the design s six pins See Figure 3 29 asic NAXIO Neck My First 33 A www terasic com FPGA Manual July 8 9015 PIN Planner k Mv design my Tirst Toga my Tirst Toga my Tirst Toda File Edit View Processing Tools Window Help Top View Wire Bond MAX 10 10M50DAF484C6GES 12 54 56 7 8 9 101112131415 1617 18192021 22 i aas O AS 0883Y 2990 COLI NVIIOIVODOVAS gt 0 00 x0y9000100000000000 E F HEME x 40 REY ao gt eee we SUDODA AOD De E T AT RoS 020001 4 5 Early Pin Planning C Early Pin Planning Pe Run I O Assignmer 7 Export Pin Assignme T Tur p Node Name Direction Location I O Bank VREF Group I O Standarc Reserved irre 3 CLOCK_50 Input 5 V fault 12 2 KEYIOI Input 5 V fault 121 2 LEDRI3I Output 5 V fault 1217 25 LEDR Output 3 fau
16. G x a 1 4 Installed IP 4 Project Directory No Selection Available 4 Library 4 Basic Functions gt Arithmetic gt Bridges and Adaptors 4 Clocks PLLs and Resets 4 ALTCLKCTRL AP eee ALTPLL_RECONFIG 3 Alter econ gt Configuration and Programming gt I O gt Miscellaneous gt On Chip Memory Simulation Debug and Verification gt Bitec gt DSP gt Interface Protocols gt Low Power gt Memory Interfaces and Controllers gt Processors and Peripherals gt University Program Search for Partner IP 4 Figure 3 7 IP Catalog 3 Double click on the ALTPLL 4 In Sve IP Variation specify the following selections see Figure 3 8 a Choose ALTPLL b Under Which type of output file do you want to create Choose Verilog Gs Under What name do you want for the output file Type pll at the end of the already created directory name asic NAXIO Neck My First 18 e tere ean www terasic com FPGA Manual July 8 9015 G Save IP Variation IP variation file name E My_design my_first_fpga pll w IP variation file type Cancel VHDL 9 Verilog Figure 3 8 Save IP Variation Selections d Click OK 5 In the MegaWizard Plug In Manager page 1 of 12 window make the following selections see Figure 3 9 a Confirm that the Current selected device family option shows the device family that corresponds to the development board you are using b The device speed grade is choosed 7 for MA
17. X10 NEEK c Set the frequency of the inclockO input 50 MHz d Click Next www terasic com FPGA Manual July 8 9015 1 ALTPLL 1 Parameter Settings lareset incIkO frequency 50 000 MHz Operation Mode Normal Cik RatiofPh dg DC co 1 4 0 00 50 00 2 PLL Bloutput MIEDA 5 Summary Reconfiguration Clocks General Modes gt Inputs Lock gt Bandwidth SS a Clock switchover gt Currently selected device family Match project default Able to implement the requested PLL General Which device speed grade will you be using _ Use military temperature range devices only What is the frequency of the inclkO input 50 000 _ Set up PLL in LVDS mode Data rate Not Available PLL Type Which PLL type will you be using Fast PLL gt Enhanced PLL 9 Select the PLL type automatically Operation Mode How will the PLL outputs be generated 9 Use the feedback path inside the PLL 4 In narmal made 3 In snurre sunrhranniis camnensatian Made CA In zera delav hitter made Conned the thmimic nort hidirectional C1 With na camnensatian Create an fbin input for an external feedback External Feedback Mode Which output clock will be compensated for Figure 3 9 MegaWizard Plug In Manager page 1 of 12 Selections 6 Turn off all options on MegaWizard page 4 As you turn them off pins disappear from the PLL block s graphical preview See Figure 3 10 for an example
18. a aa au aa aa O oo Ms td 4 dii p 4 PE p 3 All la AA A Lal 9 lt lt Filter gt gt 23 Find 3 Find Next Type ID Message Messages System Processin 300 164 0Yo 00 00 00 Figure 3 6 Placing the simple counter symbol 18 Press the Esc key or click an empty place on the schematic grid to cancel placing further instances of this symbol 19 Save your project regularly Using Quartus Add a PLL Megafunction Megafunctions such as the ones available in the LPM are pre designed modules that you can use in FPGA designs These Altera provided megafunctions are optimized for speed area and device family You can increase Efficiency by using a megafunction instead of writing the function yourself Altera also provides more complex functions called MegaCore functions which you can evaluate for free but require a license file for use in production designs This tutorial design uses a PLL clock source to drive a simple counter A PLL uses the on board oscillator MAX10 NEEK Board is 50 MHz to create a constant clock frequency as the input to the counter To create the clock source you will add a pre built LPM megafunction named ALTPLL 1 Tools gt IP Catalog gt Library gt Basic Functions gt clocks PLLsand Resets 2 Click PLL There will be a ALIPLL The IP Catalog appears see Figure 3 7 asic NAXIO Neck My First 17 ne www terasic com FPGA Manual July 8 9015 IP Catalog i
19. and specify additional project wide settings with the Settings command Assignments menu You can use the various pages of the Settings dialog box to add functionality to the project Don t show me this introduction again Back Finish Cancel Help Figure 2 1 New Project Wizard introduction 2 Click Next 3 Enter the following information about your project a What is the working directory for this project Enter a directory in which you will store your Quartus II project files for this design b For example E My_design my_first_fpga c File names project names and directories in the Quartus II software cannot contain spaces d What is the name of this project Type my_first_fpga e What is the name of the top level design entity for this project Type my_first_fpga See Figure 2 2 asic NAXIO Neck My First 8 A www terasic com FPGA Manual July 8 9015 Directory Name Top Level Entity What is the working directory for this project E My_design my_first_fpga What is the name of this project myffirstfpga OO What is the name of the top level design entity for this project This name is case sensitive and must exactly match the entity name in the design file my first fpga cca Use Existing Project Settings Figure 2 2 Project information f Click Next g You will assign a specific FPGA device to the design and make pin assignments See Figure 2 3 MAX10 Neek My F
20. e file VHDL component declaration file Quartus II symbol file pll inst v Instantiation template file pll bb v Verilog HDL black box file Figure 3 12 MegaWizard Plug In Manager page 12 of 12 Selections Double click my_first_fpga bdf blank area and open the Symbol window showing the newly created PLL megafunction See Figure 3 13 Libraries 4 E Project E pil E simple counter b E d faltera 15 0 145 quart incIkO frequency 50 000 MHz Operation Mode Normal cik Ratio Ph dg DC co 1 10 0 00 50 00 Name oh O Repeat insert mode Insert symbol as block Figure 3 13 PLL Symbol 11 Click OK and place the pll symbol onto the BDF to the left of the simple_counter symbol You can move the symbols around by holding down the left mouse button helping you ensure that they PM asic M0 Neck My First 23 sone terete een www terasic com FPGA Manual July 8 2015 line up properly See Figure 3 14 y Quartus II 64 Bit E l ly_d ASIC TY st f 3qa r f j gt id Ga m yf st tp Ic A File Edit View Project Assignments Processing Tools Window Help Search altera Sd 4 Da 9 amp my_first_fpga JE eee w gt A Ss amp pa p 3 Project Navigator 18x 23 my_first_fpga bdf E 4P simple_counter v IP Catalog a xa fMavaoer07171IANXNNNDONSO ae 2 amp Files 4 a Installec 2 my first fpga bdf desai 4 simple counter v F Pa a gt E
21. ean www terasic com FPGA Manual July 8 9015 al Symbol Libraries gt amp logic gt amp other 4 E pin Et bidir Et input E output gt storage Name output oma E Repeat insert mode Insert symbol as block Figure 3 26 choose an output pin 16 Click OK 17 Place this output pin so that it connects to the counter_bus_mux result 3 0 bus output line 18 Rename the output pin as LEDR 3 0 as described in steps 13 c and d see Figure 3 27 counter ee ee ee AN Oa Figure 3 27 Rename the output pin 19 Attach an input pin to the multiplexer select line using an input pin a Double click the my first fpga bdf Blank area b Under Libraries double click quartus libraries gt primitives gt pin gt input c Click OK 20 Place this input pin below counter_bus_mux 21 Connect the input pin to the counter_bus_mux sel pin 22 Rename the input pin as KEY 0 see Figure 3 28 asic WAXI0 Neck My First 32 cnc hernia www terasic com FPGA Manual July 8 9015 inclkO frequency 50 000 MHz Operation Mode Normal Cik Ratio Ph dg DC Figure 3 28 Adding the KEY 0 Input Pin You have finished adding symbols to your design You can add notes or information to the project as text using the Text tool on the toolbar indicated with the A symbol For example you can add the label OFF SLOW ON FAST to the KEY 0 input pin and add a project description such as My
22. er Select the my_first_fpga sof file from the project directory Click Start At this time you could find the other LEDs are unlighted asic 4X10 Neck My First 43 oe ein www terasic com FPGA Manual July 8 2015 Chapter 5 MAX10 NEEK Technical Support 5 1 Headquarter amp Branches e Tel 886 3 575 0880 e Add China 406 Jingfeng Bld B Intl Business Center Special No 1 Guang Gu Rd Wuhan China 430074 e Email sales terasic com cn support terasic com cn asic NAXIO Neck My First 44 ino www terasic com FPGA Manual July 8 2015
23. es and Probes File Logic Analyzer a ES Figure 3 1 New BDF 2 Click OK 3 Choose File gt Save As and enter the following information e File name my_first_fpga e Save as type Block Diagram Schematic File bdf PM asic NAXIO Neck My First 12 sone baina ean www terasic com FPGA Manual July 8 9015 4 Click Save The new design file appears in the Block Editor see Figure 3 2 AOS X Search altera com it QM M VUT O bb n ALI ul 46 ot a o lane File Edit View Project AEENJWTEES PORTE Window Help D 05494 424 a l myfirstafpga y BOR ra GP STOP Poo OG Project Navigator 19x 2 my_first_fpga bdf x A Xi ip MeagaverOnrrtIAIvNVNVNao GE Entity 4 MAX 10 10M50DAF484C6GES gt my_first_fpga Tasks Pax 4 Compile Design gt P Analysis amp Synthesis ha rra Mb NA Mo jm daa amp gt lt gt Type ID Message Y 253020 Default device 10M08DAF484C7G is automatically selected for the device f gt Messages 9 228 0 00 00 00 Figure 3 2 Bank BDF 5 Add HDL code to the blank block diagram by choosing File gt New gt Verilog HDL File 6 Click OK to create a new file Verilogl v which you will save as simple counter v 7 Select File gt Save As and enter the following information see Figure 3 3 e File name simple_counter v e Save as type Verilog HDL
24. irst 9 ee ee www terasic com FPGA Manual Ju y 8 2015 a izarc x Family amp Device Settings Select the family and device you want to target for compilation You can install additional device support with the Install Devices command on the Tools menu To determine the version of the Quartus II software in which your target device is supported refer to the Device Support List webpage Device family Show in Available devices list Family MAX 10 DA DF DC SA SF SC Y package Any Devices Pin count rv Target device Core Speed grade Auto device selected by the Fitter Name filter 9 Specific device selected in Available devices list Show advanced devices Other n a Available devices Name Core Voltage LES Total I Os GPIOs Memory Bits Embedded m 10M50DAF256C8GES 1 2V 49760 178 n 1677312 10M50DAF256I7G 1 2V 49760 178 1677312 1OMSODAFABACOGES 149760 1677312 a 10M50DAF484C7G 1 2V 49760 1677312 288 10M50DAF484C8G 1 2V 49760 360 360 1677312 288 ANMONNACAGACOCCC AN ANTEN aan aan 44773919 700 4 rr p Figure 2 3 Specify the Device Example h Click Finish 4 When prompted choose Yes to create the my first fpga project directory You just created your first Ouartus II FPGA project See Figure 2 4 www terasic com MAX10 Neek My First 10 www terasic com FPGA Manual July 8 2015 File Edit View Project Assignments Processing Tools Window Help Search altera com
25. led as indicated in Figure 1 7 Click Finish and you can start using the MAX10 NEEK board asic 4X10 Neck My First 5 oe een www terasic com FPGA Manual July 8 2015 Update Driver Software Altera USB Blaster II Unconfigured kw ue Windows has successfully updated your driver software Windows has finished installing the driver software for this device Altera USB Blaster I Unconfigured Figure 1 7 The driver is installed 1 3 What You Will Learn In this tutorial you will perform the following tasks Create a design that causes LEDs on the development board to blink at a speed that is controlled by an input key this design is easy to create and gives you a visual feedback that the design works Of course you can use your MAX10 NEEK board to run other designs as well For the LED design you will write Verilog HDL code for a simple 32 bit counter add a phase locked loop PLL megafunction as the clock source and add a 2 input multiplexer megafunction When the design is running on the board you can press an input switch to multiplex the counter bits that drive the output LEDs Becoming familiar with Quartus II design tools This tutorial will not make you an expert but at the end you will understand basic concepts about Quartus II projects such as entering a design using a schematic editor and HDL compiling your design and downloading it into the FPGA on your MAX10 NEEK development board Develop a foundati
26. lso double click in a blank area of the BDF to open the Symbol dialog box see Figure 3 5 W Symbol Libraries d Project EX simple counter gt d altera 15 0 145 quart Name simple_counter era Repeat insert mode _ Insert symbol as block Te ee Figure 3 5 Adding the Symbol to the BDF 16 Click OK 17 Move the cursor to the BDF grid the symbol image moves with the cursor Click to place the simple_counter symbol onto the BDF You can move the block after placing it by simply clicking and dragging it to where you want it and releasing the mouse button to place it See Figure 3 6 asic NAXIO Neck My First 16 e tere ean www terasic com FPGA Manual July 8 9015 G Quartus II 64 Bit E My design my first fpga my first fpga my_first_fpga oy Xx File Edit View Project Assignments Processing Tools Window Help Search altera com Y 2 SUAJ 32348 9 o mycfirstfpga y Ed 7 G Fh pjo er Project Navigator 20 ad r my_first_fpga bdf a y simple_counter v s A 3 Ma 9 A o0ev07171I13NNND0Ox gt 5 gt Files 2 my_first_fpga bdf 2d simple counter v Hierarchy m Files Tasks 4 B Compile Design b Analysis amp Synthesis Heber ee a e rd ed ad eee ey Core boo oa aa aa aa aa banana aa ana aa aa aan aa aa aa aa aa aa au aa aa aa au aa aan aa au aa aa uu a
27. lt 12r wm 5 LEDR 1 Output 5 V fault 12r 115 LEDRO Output fault 121 AA r 0 00 00 00 Figure 3 29 Pin Planner Example 2 In the Location column next to each of the six node names add the coordinates pin numbers as shown in Table 3 1 for the actual values to use with your MAX10 NEEK board Table 3 1 Pin Information Setting Double click in the Location column for any of the six pins to open a drop down list and type the location shown in the table alternatively you can select the pin from a drop down list For example if you type Fl and press the Enter key the Quartus II software fills in the full PIN FI location name for you The software also keeps track of corresponding FPGA data such as the I O bank and VREF Group Each bank has a distinct color which corresponds to the top view wire bond drawing in the upper right window See Figure 3 30 asic 4X10 Neck My First 34 oe ein www terasic com FPGA Manual July 8 2015 Direction Input Group Input Outp roup Output Output Output Output Node Name 4 gt KEY O 0 in KEYIOI 4 5 LEDRJ3 0 out LEDRI3 E 2 LEDR 2 ri LEDRI1I i 5 LEDR O lt lt new group gt gt LD X lt i gt 4 amp Early Pin Planning C Early Pin Planning Isi Pp Run I O Assignmer C Export Pin Assignme C Pin Finder 5 Highlight Pins 4 III Top View Wire Bond MAX 10 10M50DAF
28. n the development board and the design should be running 4 3 Verify The Hardware When you verify the design in hardware you observe the runtime behavior of the FPGA hardware design and ensure that it is functioning appropriately Verify the design by performing the following steps 1 Observe that the four development board LEDs appear to be advancing slowly in a binary count pattern which is driven by the simple counter bits 26 23 The LEDs are active low therefore when counting begins all LEDs are turned on the 0000 state www terasic com MAX10 Neek My First 4 FPGA Manual www terasic com July 8 2015 2 Press and hold KEY 0 on the development board and observe that the LEDs advance more quickly Pressing this KEY causes the design to multiplex using the faster advancing part of the counter bits 24 21 3 If other LEDs emit faintness light Choose Assignments gt Device Click Device and Options See Figure 4 6 Select the family and device you want to target for compilation You can install additional device support with the Install Devices command on the Tools menu To determine the version of the Quartus II software in which your target device is supported refer to the Device Support List webpage Device family Show in Available devices list Family MAX 10 DA DF DC SA SF SC e Package Any v Devices Pin count Any 7 Name filter Auto device selected by the Fitter 9 Specific
29. on to learn more about FPGAs For example you can create and download digital signal processing DSP functions onto a single chip or build a multi processor system or create anything else you can imagine all on the same chip You don t have to scour data books to find the perfect logic device or create your own ASIC All you need is your computer your imagination and an Altera MAX10 NEEK FPGA development board asic NAXIO Neck My First 6 ee www terasic com FPGA Manual July 8 9015 Chapter 2 Assign The Device You begin this tutorial by creating a new Quartus II project A project is a set of files that maintain information about your FPGA design The Quartus II Settings File gsf and Quartus II Project File qpf files are the primary files in a Quartus II project To compile a design or make pin assignments you must first create a project 2 1 Assign The Device 1 In the Quartus II software select File gt New Project Wizard The Introduction page opens See Figure 2 1 asic NAXIO Neck My First 7 seule hed aii nan www terasic com FPGA Manual July 8 2015 G New Project Wizard Introduction The New Project Wizard helps you create a new project and preliminary project settings including the following Project name and directory Name of the top level design entity Project files and libraries Target device family and device EDA tool settings You can change the settings for an existing project
30. ow Since the desired driver is not available on the Windows Update Web site open the Computer Management and select the Device Manager This leads to the window in Figure 1 3 File Action View Help e 20 06 l Computer Management Local a g terasic PC System Tools gt Mi Computer Task Scheduler gt a Disk drives gt Sl Event Viewer ME Display adapters More Actions gt El Shared Folders gt 8 DVD CD ROM drives b He Local Users and Groups gt 63 Human Interface Devices p 5 Performance D Cg IDE ATA ATAPI controllers Ey Device Manager b Jungo a Storage b 2 Keyboards f Disk Management p R Mice and other pointing devices b Es Services and Applications D A Monitors b amp F Network adapters gt Other devices Unknown device gt Ports COM amp LPT D p Processors p X Sound video and game controllers b 7 Storage controllers gt Ml System devices p Universal Serial Bus controllers gt dap WSD Print Provider Figure 1 3 The USB Blaster II in device manager Right click Other devices gt Unknown device and select Update Driver Software then selecte Browse my computer for drive software and Click Next to get to Figure 1 4 PM asic WAX10 Neck My First 3 ee tee ean www terasic com FPGA Manual July 8 2015 Browse for driver software on your computer Search for driver software in this location C altera 15 0 quartus drivers usb blaster V Include s
31. period 20 000 name CLOCK_50 derive_pll_clocks derive_clock_uncertainty 4 Save this file Uy u m vy zu s File Edit View Project do oda as my_first_fpga sdc see Figure 3 31 ne pi fl Assignments Processing Tools Window Help A ie Deo o Ao ie MX yu IPx Project Navigator a 5 Files 2 my_first_fpga bdf 4 simple counter v art my first fpga es my_first_fpga bdf Hp my first fpga sdc E 3 ml OTAK US YF 263 ab reate clock period 20 000 name CLOCK 50 derive pll clocks derive clock uncertainty 4 gt E Search altera com IP Catalog Q x 4 Installed IP 4 Project Directory No Selection Available gt El pll gip 4 Library gt E counter bus mux gif a Pas dada 29 my_first_fpga sdc gt Arithmetic Y pga gt Bridges and Adaptors 4 Tur p Clocks PLLs and Rese 3 Files 4 A oo and Pro Tasks A x 4 Miscellaneous 2 ALTECC K X FIFO FIFO 4 B Compile E X LPM CLSHIFT gt Pb Analysis S LPM_CLSHIFT gt P Fitter PI 3 Tn gt i R Add x lm daa a gt lt gt Find Ne ID 170495 registers lost all their fanouts during netlist optimizations b D 16010 Generating hard block partition hard block auto generated inst gt O 21057 Implemented 38 device resources after synthesis the final resource count mig AAA Asa System A N Processing 27 100 0
32. rasic com FPGA Manual July 8 9015 Bus Properties Genera Name counter 31 0 E Hide name in block design file Figure 3 19 Change the output BUS name inclkO frequency 50 000 MHz Operation Mode Normal Figure 3 20 BDF 3 2 Add a Multiplexer This design uses a multiplexer to route the simple_counter output to the LED pins on the MAX10 NEEK development board You will use the MegaWizard Plug In Manager to add the multiplexer Ipm mux The design multiplexes two variations of the counter bus to four LEDs on the MAX10 NEEK development board 1 Choose Library 2 Click Basic Functions PM asic WAXI0 Neck My First 27 e tere ean www terasic com FPGA Manual July 8 9015 3 Click Miscellaneous 4 Click LPM MUX 5 Choose the device family that corresponds to the device on the development board you are using choose Verilog as the output file type and name the output file counter_bus_mux v see Figure 3 21 IP Catalog m a ye 4 Installed IP 4 Project Directory No Selection Available 4 Library 4 Basic Functions gt Arithmetic i gt Bridges and Adaptors Q Save IP Variation gt Clocks PLLs and Resets gt Configuration and Programming IP variation file name gt I O my first fpga counter bus mux v dl Miscellaneous IP variation file type Cancel 4 ALTECC 4 ALTEC VHDL Verilog ika 4 LPM CLSHIFT a ne 4 LPM_CONSTANT LPM_DECODE PA LPM_MUX LPM SHIFTR
33. rdware setup to use when programming devices This programming hardware setup applies only to the current programmer window Currently selected hardware i USE NEEK10 USB 1 Hardware Server Port Add Hardware NEEK10 Local USB 1 Available hardware items Remove Hardware Figure 4 4 Hardware Setting TadasiC MAX10 Neek My First 40 www terasic com www terasic com FPGA Manual July 8 2015 A Click Close 5 H the file name in the Programmer does not show my_first_fpga sof click Add File 6 Select the my_first_fpga sof file from the project dir ectory see Figure 4 5 le Programmer E My design my first fpga my first fpga my first fpga Chain1 cdf ee inna File Edit View Processing Tools Window Help Hardware Setup NEEK10 USB 1 Mode JTAG Search altera com ge j Progress 2 Stop ha Auto Dete Delete 2 Add File Change File A Save File Add Device Tu Up Down _ Enable real time ISP to allow background programming when available File Device Checksum Usercode Program Verify Blank Examine Security rase ISP Configure output files my_ LOMSODAF4 00273104 00273104 Y Check Bit LAMI IS 10M50DAF484ES Figure 4 5 Downloading Complete Congratulations you have created compiled and programmed your first FPGA design The compiled SRAM Object File sof is loaded onto the FPGA o
34. rt a MAX 10 10M50DAF484C6GES 3 module simple counter gt my_first_fpga 4 o CLOCK 50 5 counter out 6 4 rr 5 4 Hierarchy 2 Files 4 gt 8 input CLOCK 50 7 9 output 31 0 counter out Tasks ax reg 31 0 counter out Flow Compilation Customize always posedge CLOCK_ 50 on positi Tak A begin E counter out lt 1 counter out 1 increment 4 P Compile Design i end _1 gt P Analysis amp Synthesis endmodule end of mc A ss O td na p Dae E gt lt Type ID Message Y 253020 Default device 10M08DAF484C7G is automatically selected for the device fa gt ah x 4 mr p AL System 1 Processin Messages 0 00 00 00 Figure 3 4 The Verilog File of simple_counter v 9 Save the file by choosing File gt Save pressing Ctrl s or by clicking the floppy disk icon 10 Choose File gt Create Update gt Create Symbol Files for Current File to convert the simple_counter v file to a Symbol File sym You use this Symbol File to add the HDL code to your BDF schematic 12 To add the simple_counter v symbol to the top level design click the my_first_fpga bdf tab 13 Double click my_first_fpga bdf Blank area 14 Double click the Project directory to expand it asic 4X10 Neck My First 15 O TE www terasic com FPGA Manual July 8 2015 15 Select the newly created simple_counter symbol by clicking its icon You can a
35. s or a hardware description language HDL such as Verilog HDL or VHDL In this step you can create a digital circuit that is implemented inside the FPGA The flow then proceeds through compilation simulation programming and verification in the FPGA hardware D KENA KE GE Figure 1 1 Design Flow This tutorial guides you through all of the steps except for simulation Although it is not covered in this document simulation is very important to learn and there are entire applications devoted to simulating hardware designs There are two types of simulation Functional and Timing Functional simulation allows you to verify that your code is manipulating the inputs and outputs appropriately Timing or post place and route simulation verifies that the design meets timing and functions appropriately in the device asic AX10 Neck My First 1 oe een www terasic com FPGA Manual July 8 2015 1 2 Before You Begin This tutorial assumes the following prerequisites NW You generally know what a FPGA is This tutorial does not explain the basic concepts of programmable logic M You are somewhat familiar with digital circuit design and electronic design automation EDA tools M You have installed the Altera Quartus II 15 0 win7 64bits software on your computer If you do not have the Quartus II software you can download it from the Altera web site at www altera com download M You have a MAX10 NEEK Development
36. ttinc Operation Mode Normal 9 Enter output clock frequency 5 000000 Cik Ratio Ph dg DC 9 Enter output clock parameters ae sie 1 ES co 1 10 0 00 50 00 Clock multiplication factor a 1 ja Clock division factor 10 JE Clock phase shift 0 00 E Clock duty cycle 50 00 Note The displayed internal Description Mal settings of br Aa is gt Primary clock VCO frequenc 6 Y recommen or use advanced users only a d Per Clock Feasibility Indicato c0 ci c2 c3 c4 Figure 3 11 MegaWizard Plug In Manager page 6 of 12 Selections 9 Click Finish 10 The wizard displays a summary of the files 1t creates see Figure 3 12 Click Finish again asic 4X10 Neck My First 22 e Pa ton www terasic com FPGA Manual July 8 2015 24 ALTPLL A HlParameter 2 PLL BlOutput MIEDA 5 Summary Settings Reconfiguration Clocks Turn on the files you wish to generate A gray checkmark indicates a file that is automatically generated and a green checkmark indicates an optional file Click Finish to generate the selected files The state of each checkbox is maintained in subsequent MegaWizard Plug In Manager sessions incIkO frequency 50 000 MHz i En ya Operation Mode Normal The MegaWizard Plug In Manager creates the selected files in the following directory Cik Ratio Ph dagf DC 26 E My_design my_first_fpga co 1 10 0 00 50 00 Description Variation file PinPlanner ports PPF file AHDL Includ
37. ubfolders gt Let me pick from a list of device drivers on my computer This list will show installed driver software compatible with the device and all driver software in the same category as the device Figure 1 4 Specify the location of the driver Now choose Search for the best driver in these locations and click Browse to get to the pop up box in Figure 1 5 Find the desired driver which is at location C altera 15 0 quartus drivers usb blaster 11 Click OK and then upon returning to Figure 1 4 click Next At this point the installation will commence but a dialog box in Figure 1 6 will appear indicating that the driver has not passed the Windows Logo testing Click Install Anyway TadasiC MAX10 Neek My First 4 www terasic com www terasic com FPGA Manual July 8 2015 gt bin64 p di common gt cusp al Je drivers 386 gt Je sentinel gt Je usb blaster usb blaster ii 7 gt de wdrer TI usb blaster i Figure 1 5 Browse to find the location Windows Security Would you like to install this device software Name Altera USB Blaster Device Driver Package Ed Publisher Delaware Altera Corporation Always trust software from Delaware Altera Don t Install Corporation Fa You should only install driver software from publishers you trust How can I decide which device software is safe to install Figure 1 6 There is no need to test the driver The driver will now be instal
38. ww terasic com FPGA Manual July 8 2015 File Edit View Project Assignments Processing Tools Window Help Search altera com Y 1 ae H g QA A fu my_first_fpga v Y i Vy ef STOP gt gt rae de pul 4 Ww uy ou Project Navigator 48X WS Compilation Report my_first_fpga EJ 12 my first fpga bdf 4 my first fpga sdc IP Cat 19x a Table of Contents ae A gt Be Files ES Flow Summary Flow Status In progress Thu Jun 25 13 5 4 Installe a B mv fist fogabat FS Flow Settings Quartus II 64 Bit Version 15 0 0 Build 145 04 22 2015 4 Projec 4 a ee Flow Non Default Global Settings Revision Name my_first_fpga No 5 ed simple counter v i gt E pilgip Flow Elapsed Time Top level Entity Name my_first_fpga 4 Library Den HB Flow OS Summary Family MAX 10 4 Basic AA 2 Flow Log Device 10M50DAF484C6GES gt Ai 29 my first fpga sdc y 1 gt G Analysis amp Synthesis Timing Models Preliminary gt Br gt G Fitter Total logic elements 31 gt cl WD Flow Messages Total combinational functions 31 DC D Flow Suppressed Messages Dedicated logic registers 27 Total registers Total pins TE Poe Total virtual pins Total memory bits Embedded Multiplier 9 bit elements E Total PLLs 6 4 P Compile D4 SI UFM blocks gt BP Analysis ADC blocks gt P Fitter PI gt P Assembl Y p Tur 4 9 m oa gt aaner ID Message N N O Or OSOS a
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