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FB-2300 AII-In-One 386SX CPU CARD Module User's Manual

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1. D i J4 Sen GEN ASTI oe CN4 LCD connector gadag SO be M1 LM1LM2LM3LM4 Le DB1 k DB2 M3 CN7 swt CN12 M cnio J JF os k at 3 CN8 8 Ce H Ap CNI J9 I Lou Figure 5 2 CN4 LCD Connector Signal DP15 DP16 DP18 DP20 DP22 Ground GPOO 1 GPO1 1 Ground Ground Ground 12V 12V VLCD 2 VLCD 2 ENABLK ENAVEE Table 5 1 CN4 LCD Connector Pin Assignments NOTE 1 GPO0 and GPO1 pins are TIL outputs They could be used as LCD back light controls 2 Different LCD panels use different BIOS and pin connections If any trouble occurson connecting the FB2300 to the LCD panels please contact us 41 FablATech Corporation 42 CHAPTER 6 INSTALLATION This chapter provides information for you to set up a working system based on the FB2300 C PU board Carefully read the details of the CPU board s hardware descriptions before insta lla tion especially the jumper settings switch settings and cable connections The following topics are covered gt Overview gt CDROM gt Watchdog Timer 6 1 INSTALLATION PROC EDURES Follow the steps listed below to install the FB2300 system Step 1 Read the CPU board s hardware description in this manual Step 2 Set the jumpers Step 3 Make sure that the power supply connected to your passive CP
2. n n R H elo ry J4 JF BAY ye CN dddald eb a ONS E e Mi iMi MSL 1 2 J aik Pa y X m DB1 DB2 s3 IOOL4 l CN7 Z JS swi E DN CN12 2 m 6 m CN10 Ilres JP6 Hr H Ja EEK H Ap ONS sti jeu Front View Figure 3 2 Front View of CN11 Mini Din Connector Keyboard Data Pn A Keyboard Clock 16 Mouse Clock Table 3 2 CN11 Pin Assignments 17 FablATech Corporation 2 6 Pin J STKeyboard Mouse Connector J 9 PS 2 Function Enable J umper J P6 The following demonstrates the pin assignments of the 6 pin J ST keyboard mouse connector To use the PS 2 mouse an optional adapter cable has to be connected to the J9 6 pin headertype connector The pin assignments for the J STconnector are as follows J P6 is used to enable orto disable the J 9 function J2 J3 JP1 CN CN1 J5 J6 CN2 Jr CN3 m n U A i H Ela E J4 B f g Lol dddald ER ONS js BAT E M1 LM1LM2LM3LM4 Ji D I DB2 6 Pin 1 Mouse Data Pin 2 Keyboard Data CN7 Swi Pin 3 Ground CN12 Pin 4 VCC N1 g NO Pin 5 Mouse Clock H CNS 1 J Pin 6 Keyboard Clock DS GAA lon y B z 1 1 Enable PS 2 Mouse Disable PS 2 Mouse Fac
3. Figure 3 1 System Components Overview 15 FablATech Corporation 3 2 INDEX TO J UMPERS amp CONNEC TORS The following lists the jumperand connector functions for reference Label Function BA Onboard Buzzer CN1 40 pin 2 54mm IDE hard disk connector CN2 34 pin 2 54mm floppy connector CN3 26 pin 2 54mm parallel port connector CN4 2 0mm 44 pin LCD connector CN5 10 pin 2 54mm IDC connectorforCOM2 CN7 RJ 45 LAN connector CN8 10 pin TILI O connector CN9 40 pin PC 104 bus C amp D connector CN10 64 pin PC 104 bus A amp B connector CN11 Standard P S2 type keyboard mouse connector CN12 10 pin to BNC FB4616 board connector DB1 15 pin CRTconnector DB3 9 pin DB9 RS 232C serial port forCOM1 J1 2 pin extemal battery connector for SRAM disk J2 2 pin hard disk LED header J3 2 pin reset header J4 3 pin 2 0mm extra RS 232C J STheader J5 9 pin auxiliary powerconnector J6 4 pin extemal speaker header J7 3 pin power LED header J8 4 pin auxiliary powerconnector J9 PS 2 keyboard amp mouse connector JP1 M DE Select signal for TFTLCD JP2 3 pin RS485 terminator JP3 3x3 jumperto select CN5 RS 485 function JP4 2x3 SSD and DOC select JP6 PS 2 mouse function select JP7 2x3 CPU base clock select jumper SW1 1 amp 1 2 J P4 SSD and DOC mapping address settings SW1 3 SSD drive select SW1 4 and JM1 SSD m
4. Figure 3 16 CN12 to BNC F amp 4616 board Connector 3 ve 4 GND 5 J 6 mm 7 GND 8 BNCEN 9 iPx P I Table 3 13 CN12 Pin Assignment 28 FablATech Corporation 3 3 11 CPU Base Clock Select J P7 The CPU base clock Input clock istwice of its operation clock J2 J JP1 CNA CNI J5 J6 CN2 J7 CN3 J4 D i y 1 Bea GEN 2 7 1 gt N a dada DLA 00 BAT1 E L M1 MIL MELVSLMA D I gt r DB2 A M2 m CN7 l m swi gt P M4 SS 25 0MHz 33 3MHz CN10 A BBs l CN8 Factory Preset JP6 Y g z E a J8 Lat Or CNS J9 Af Jon Figure 3 17 J P7 CPU Base Clock Select 3 3 12 HDD J2 and Power J 7 LED Indicators J3 JP1 CNA CN J5 J6 CN2 DP CN3 o D P A aa a A J7 3 pin Power LED BEE EH cs ER ll e dddald SAR en JP4 E M1 LM1LM2LM3LM4 J1 m D I DB2 9 M3 CN7 swi CN12 d ento f 083 JP6 de i aB cng 8 eg Ess Hi CN9 J9 Joni J 2 2 pin Hard Disk LED Figure 3 18 Onboard LED Indic ators gt On Board Power L
5. Figure 3 14 J 4 RS 232C Header 27 FablATech Corporation 3 3 9 R 45 Connector CN7 CN7 isan RJ 45 connector with 2 LED indicators The upper LED orange is lit when the system is accessing data The lower LED green is lit when power is supplied normally or it blinks when the watchdog isenabled The following table liststhe pin assignment of CN7 J2 J JP1 CN4 CN1 J5 J6 CNS J7 CNS D G J4 i Hen GEN AJ A n CN5 m miiia ENZ DATT E L M1 LMYLM2LM3LM4 8 fi J1 k M2 DB1 Ol DB2 x mu e M3 N sw1 CN12 5 M4 og J DB3 JP6 dm d CN8 H B ea H Ap CN9 JO CU CNi Figure 3 15 CN7 RJ 45 Connector 2 Px 6 PRX 4 Notusd 8 NotUsed Table 3 12 CN7 RJ 45 Pin Assignments 3 3 10 CN12 Connector BNC It is necessary to use the BNC adapter board FB4616 and cable forattaching to CN12 connector The following table lists the pin assignment of CN12 Pm Ji ON On P JONG JP OD D ele E ER zu CNS Et dada Ha LA E M1 LM1LM2LM3LM4 J1 oH M2 DB1 DB2 M3 CN7 Swi F M4 CN12 CN10 JV PB3 JP6 de GE T a CN8 B 4 JP7 ONS SO long
6. Send outone character Transmit Step 1 Enable TXC signal and the bit O of the address of offset 4 just sets 1 Step 2 Send out the data Write this character to the offset 0 of the curent COM port address Step 3 Wait forthe buffersdata empty Check transmitter holding register THRE bit 5 of the address of offset 5 and transmitter shift register TSRE bit 6 of the address of offset 5 are all sets must be 0 Step 4 Disabled TXC signal and the bit O of the address of offset 4 sets 0 gt Send out one block data Transmit the data more than two characters Step 1 Enable TXC signal and the bit O of the address of offset 4 just sets 1 Step 2 Send outthe data Write all data to the offset 0 of the current COM port address Step 3 Wait forthe buffersdata empty Check transmitter holding register THRE bit 5 of the address of offset 5 and transmitter shift register TSRE bit 6 of the address of offset 5 are all sets must be 0 Step 4 Disabled TXC signal and the bit O of the address of offset 4 sets 0 gt Receive data The RS 485 s operation of receiving data isin the same of the RS 232 s 49 FablATech Corporation gt Basic Language Example a Initial 86C 450 UART OPEN COM1 9600 m 8 1 AS 1 LEN 1 REM Reset DTR OUT amp H3FC INP H3FC AND amp HFA RETURN b Send out one characterto COM1 REM Enable transmitter by setting DIRON OUT amp H3FC INP amp H3FC OR amp H
7. al nop nop gt Lock Configuration Register Mov Al 013h Out 22h al Nop Nop Move Al 000h Out 23h al Nop Nop Read the Value at Configuration Register Forexample read INDEX 3C h Unlock configuration register Move Al 03ch Out 22h al Nop Nop In Al 23h Nop Nop Push Ax Lock configuration register Pop ax AL result Write Data to Configuration Register Forexample write OFFh to INDEX 3Bh Unlock configuration register mov al 03bh 47 FablATech Corporation out 22h al nop nop mov al Offh out 23h al nop nop Lock configuration register 48 6 4 PROGRAMMING RS 485 The majority communicative operation of the RS 485 is in the same of the RS 232 When the RS 485 precedes the transmission which needs control the TXC signal and the installing steps are asfollows Step 1 Enable TXC Step 2 Send out data Step 3 Waiting fordata empty Step 4 Disable TXC NOTE Please refer to the section of the Serial Ports in the Chapter System Controllers for the detail description of the COM port s register gt Initialize COM port Step 1 Initialize COM port in the receiver interupt mode and or transmitter interupt mode All of the communication protocol buses of the RS 485 are in the same Step 2 Disable TXC transmitter control the bit O of the address of offset 4 just sets 0 NOTE Control the FB2300 CPU card s DTR sgnalto the RS 485 sTXC communication
8. called fimware that interacts directly with the hardware components and facilitates interaction between the system hardware and the operating system The BIOS Default Values ensure that the system will function at its normal capability In the worst situation the user ma y have comupted the original settings set by the manufacturer After the computer tumed on the BIOS will perform a diagnostics of the system is being tested Press the Del key to enter the BIOS Setup program and then the main menu will show on the screen The BIOS Setup main menu includes some options Use the Up Down arrow key to highlight the option that you wish to modify and then press the Enter key to assure the option and configure the functions AMIBIOS HIFLEX SETUP UTILITY VERSION 1 20 C 1998 American Megatrends Inc All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup Auto Detect Hard Disks Change User Password Change Supervisor Password Auto Configuration with Fail Safe Settings Save Settings and Exit Exit Without Saving Load configuration settings giving highest performance ESC Exit 11 5el F2 F3 Color F10 5ave Exit Figure 7 1 BIOS Main Menu 51 FablATech Corporation CAUTION 1 The factory default setting in the FB2300 BIOS is used to the lt Auto Configuration with Optimal Settings gt we recommend using the BIOS default setting unless you are very familiar
9. Figure 3 9 CN3 Parallel Port Connectors 24 FablATech Corporation DB25 Signal CN3 DB25 Signal 2 Din 4 15 DARA E 6 4 Di 8 BENI 6 ET 8 7 17 o DANI 18 22 Ground 23 12 PAPER 24 25 Ground 25 13 PRINTERSELECT 26 NoUsed Table 3 9 CN3 Parallel Port Pin Assignments 3 3 6 Auxiliary Power Connectors J 8 amp J 5 for standalone application The FB2300 provides two typesof power connectors J8 isa 4 pin 5V powerconnector J5 isa 9 pin power connector Using either of the connectors you can connect the power supply to the on board powerconnectorfor stand alone applications directly DB 25 3 5 J2 J3_ JP1 CN4 CN1_ J5 J6 CNS Ji CNS E M1 J1 me DB1 DB2 9 1 RE NE Gd ONS 3 Ground 8 V Bu Su ov NS Ground SI 8 e C o ax J8 Figure 3 10 Power Connectors mmm 25 FablATech Corporation 3 3 7 TILI O Connector CN8 CN8 isa 2x5 TILI O connectorand supports 4 TIL outputs and inputs J2 mm JP CN4 ON JP J6 CN2 JP CN3 CNS o en E JE J4 ES 4 i CNS 10 9 E EEERE upg EM BATI E M1 LM1LM2LM
10. SSD ESC Exit F5 Save Exit lt Select 4 Modify Hit lt Ctr gt to setup Flash disk displayed Step 11 Step 12 Step 13 SSD isC Step 14 Press F5 to save the setting The message Write to FLASH disk y n Press Y key to write the setting to the Flash disk The booting from other device Like physical HDD or FDD Use the FORMATcommand to format the flash disk in DOS mode This time this Use FORMATC S C U The S SYSTEM BOOTING C Check U UNFORMAT If format parameterno S the SSD will be alwaysto device B that can t boot up the system Note If Flash Disk Simulates field select HDD the total size of the flash disk must be above to 512KB CAUTION It isnot recommended that the user format the disk and copy files to the FLASH disk very often Since the FLASH EPROM s writing cycle is about 10 000 or 100 000 times writing data to the FLASH too often will reduce the lifetime of the FLASH EPROM chips 37 FablATech Corporation 38 FablATech Corporation CHAPTER5 CRT LCD FLAT PANEL DISPLAY This section describes the configuration and installation procedure when using the LCD and CRTdisplays gt LCD Flat Panel Displays gt CRT amp LCD Displays 5 1 LCD FLATPANEL DISPLAYS Using the Flash Memory Writer utility to download the new BIOS file into the ROM chip to configure the BIOS default settings for different types of LCD panels And then set your system properly and co
11. Serial Porti IRQ 4 9 OnBoard Serial Portz 2F8h OnBoard Parallel Port 378 Parallel Port Mode Norma I EPP Version N A Parallel Fort IRQ 7 Parallel Port DMA Channel N A ESC Exit 14 5el PgUp PgDn Modify F2 F3 Color Figure 7 5 Peripheral Setup Hard Disk Delay If this field is set to Disabled and the system BIOS executes too fast the result isthe BIOS can t find the hard disk drive Available Options Disabled 3 Sec 5 Sec 10 Sec and 15 Sec Default setting 3 Sec OnBoard IDE This field specifies the onboard primary IDE controller channels that will be used Available Options Disabled Enabled Default setting Enabled OnBoard FDC This field enables the floppy drive controller on the FB2300 Available Options Disabled Enabled Default setting Enabled OnBoard Serial Port 1 amp 2 These two fields select the I O port address foreach Serial port Referto Table 2 2 Available Options Disabled 2F8H 3F8H 2E8H and 3E8H Default setting 3F8H 2F8H OnBoard Serial Port 1 2 IRQ These fields select the IRQ foreach serial port Available Options 3 4 5 9 Default setting IRO 4 for Port 1 IRQ3 for Port 2 OnBoard Parallel Port 1 This field selectsthe O port addressfor parallel port Referto Table 2 2 Available Options Auto Disabled 378 278 and 3BCH Default setting 378H for Port 1 278H for Port 2 61 FablATech Corporation Parallel Port Mode This field specifies the parallel port mode ECP and EP
12. capacity The FB2300 also comes with a programmable Watchdog timer and other typical interfaces It is excellent for embedded systems MMI s workstations medical applications or POS POI systems As well an RS 232C 485 port providesthe remote control Especially the FB2300 provides CRT and LCD interface with 512KB VRAM on board and uses the C T65545 Chipset to support a wide range of LCD panels 1 2 SERIES COMPARISON TABLE Model B2300 mamm mea VGACRTLCD Cam5545 caressa Yes Yes Yes Ethemet10Mbps ve J FablATech Corporation 1 3 FEATURES The system provides a number of special features that enhance its reliability ensure its availability and improve its expansion capabilities as well as its hardware structure 06000000000 06000000000 Up to 33 MHz 386SX single board computer ISA and PC 104 expansion bus 2 MB EDO RAM on board 6 MB space forexpansion 10Base T NE2000 compatible network Without on FB2300A ProvidesCRTand LCD interface with 512KB VRAM 1MB VRAM isoptional Parallel port floppy and IDE Interface 1 RS 232C and 1 RS 232C RS485 PS 2 compatible keyboard and mouse interface Provides 4 sockets for up to 4MB 2MB 2MB EPROM SRAM Flash disk or 3 sockets for up to 3MB 1 5MB 1 5MB SSD and 1 socket for DiskO nC hip 4 TILinputsand 4 TIL outputs E2KEY function forsafe CMOSdata keeping Option On board buzzer and LED indicator On board Lithium battery for SRAM
13. 01 REM Send out one character PRINT 1 OUTC HR REM Check transmitter holding register and shift register IF INP amp H3FD AND amp H60 gt 0 THEN 60 REM Disable transmitter by resetting DTR OUT amp H3FC INP amp H3FC AND amp HEF RETURN c Receive one character fom COM1 REM Check COM1 receiver buffer IF LOF 1 lt 256 THEN 70 REM Receiver buffer is empty INPSTR RETURN REM Read one character from COM1 buffer INPSTR ANPUT 1 41 RETURN NOTE The example of the above program is based on COM1 I O Address 3F8h The RS 485 of the FB2300 uses COM2 If you want to program it please referto the BIOS Setup for COM2 address setup 50 CHAPTER 7 BIOS SETUP This chapter describes the FB2300 BIO S menu displays and explains how to perform common tasks and presents detailed explanations of the elements found in each of the BIOS menus The following topics are covered BIOS Setup Overview Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup Auto Detect Hard Disks Password Setting Load Default Setting BIOS Exit 000000000 7 1 BIOS SETUP OVERVIEW BIOS Basic Input Output System isa program used to initia lize and set up the O devices of the computer which includesthe ISA busand connected devicessuch asthe video displa y diskette drive and the keyboard The BIOS provides a menu driven interface to the console subsystem The console subsystem contains special software
14. 10 DB1 a E es CN12 JP6 Hg Ho CN9 J9 a LEDI J4 CN5 DB2 CN7 DB3 EE Mel CN8 CN11 CN9 BUSC amp D 0000000000000000000 00000000000000000000 Figure 3 6 CN9 40 Pin PC 104 Connector Bus C D Pin Signal Fin Signal Pin Signal Pin Signal 3 SBHE 23 SD8 4 MEM16 24 DRQS 5 123 25 s9 6 016 26 DACK6 7 22 27 gou 8 RO10 23 DROG 9 121 29 so 10 IRQ11 30 DACKz 19 MEMRDI16 39 Key2 20 DRQO 40 Ground Table 3 6 CN9 40 Pin PC 104 Connector Bus C D 21 FablATech Corporation 3 PC 104 ISA Signal Description Name O Descgpton OOO BUSC LK Output The BUSC LK signal of the I O channel is asynchronous to the CPU clock RSTDRV Output is Si igh during power up low line voltage or hardware reset SAO SA19 Input Output The System Address lines run from bit O to 19 They are latched onto the falling edge of BALE LA17 LA23 Input Output The Unlatched Addressline run from bit17to 23 ALE Output The Buffered Address Latch Enable is used to latch SAO SA19 onto the falling edge This sig i ing DMA cycles enor exist on the I O board held low with a valid address IRO 3 7 9 12 14 15 Input The Interupt Request signal indicates I O service request attention They are pri
15. 2300 supports CRT color monitor STN Dua Scan TFT monochrome and color panels It can be connected to create a compact video solution for the industrial environment 1MB maximum of V RAM on boarded allows a maximum CRT resolution of 800X600 with 256 colors and a LCD resolution of 640X480 with 64K colors For different VGA display modes your monitor must possess certain characteristics to display the mode you want 5 2 1 CRTConnector DB1 D I isa 15 pin connector The pin assignments forthe D I connector are as follows J2 J3 JP1 CN4 CNI J5 J6 CN2 JX CN3 m U P i z J JM S da EENS PF CNS Pin 1 Red Ena ue ET EI eine G E M1 LM1LM2LM3LM4 e In 2 reen Pin 3 Blue vi Seel pBi HHI DB ba i Pin 13 Hsync 3 D E ma CN7 Pin 14 Vsync m sw E Pin 5 amp 10 Digital Ground l n CN12 1 Pin 6 7 8 Analog Ground CN10 os JP6 LE Ea ae ons Others Not Used E JP7 CN9 JO S pis DB1 Front View Figure 5 1 DB1 CRTConnector 40 FablATech Corporation 5 2 2 LCD Connectorand Jumper Settings CNA CN4 isa 2 0mm 44 pin connector that provides 24 bit LCD interface signals J2 J3 JP1 CN4 CN1 J35 _ J6 CN2_ J7 CN3
16. 3LM4 A h M2 DB1 DB2 r x ge ON swt CN12 i i S T D me Pin 1 INPO Pin 2 OUTI JPG ME s Pin 3 INP1 Pin A OUTL D As ge eml cna mn TI Lou Pin5 INP2 Pin6 OUT I Pin 7 INP3 Pint 8 OUT3 Pin 9 5V Pin 10 Ground Figure 3 11 CN8 TIL Connector 3 3 8 Serial Ports 1 RS 232C Pin Definitions DB3 and CN5 DB3 is standard DB9 serial port connectorforCOM1 and CN5 is 10 pin 2 54mm IDC connectorforCOM2 The included serial port adapter cablesare used to transfer CN5 connectorinto standard DB9 connector J2 J3 JP1 CNA CN J5 J6 CN2 J7 CN3 n n P z W Ze 5 Pe DB3 HA SEE ey El a d Mi LM1LM2LM3LM4 Pa Ji m DB1 DB2 9 x a CN swi CN12 SU p og B3 M JP6 de Se a CNB 1 L H JE CN9 J9 ei cn Figure 3 12 DB3 and CN5 RS232C Connectors The following left table shows DB3 s signal connections and the following right ta ble shows signal connections of the included cable E o ul H 8 Signal DCD2 DSR2 RXD2 RTS2 TXD2 CTS2 DTR2 RI2 Ground Case Ground Table 3 10 RS 232C Connector N 1 2 3 4 5 6 7 8 9 UTO BOUN NO re 1 UT KO BOUNN OF 1 E o 26 FablATech Corporation 2 RS 485 J umper Selec
17. AM DISK csssssssssssssscsesssssssssssssssssscssssssesseesssesesesesesesrsrsssceseneesesessesacaneseceeesnsnaes 35 4 3 1 Programming EPROM DIRK ENEE 35 4 3 2 Programming Flash and SRAM dek ENEE 35 CHAPTER ech te dd att NES CRT LCD FLAT PANEL DISPLAY 5 1 LGD FLATPANEL DISPLAY Si ee ee eege deeg ees 39 5 2 CRTSLCDODSPIAY a 40 5 21 CREECONMECHOF DBI tee sedat sad a iaa 40 CHAPTER G Ao kan a le INSTALLATION 6 1 INSTALLATON PROCEDURES eege geed EELER SEELEN ENEE eg EE B 6 2 CEDRO Misa O 44 6 2 1 VGA Dnvertor WIN Tirah ida aid ie ataca 44 6 225 CLAN KEEN eege a E Een EE Een ee die 44 6 3 INTERNAL WA TC HDO G TIMER cccssssssssssssescsesssssssssssessscssssscesesesesesesesesesescerscacaseneseaeeeeeacesasecececesesesesesesnsrereraness 45 6 3 1 Watchdog Timer SQtting sss nsina iiia aiaa iaiia 45 6 3 2 Watchdog Enabled Disa bled INDEX 27H ENEE erro 46 6 3 3 Select Watchdog Report Signal INDEX 20 ENEE 46 6 3 4 Timeout Satus amp Reset Watchdog INDEX BC Hh eesseessestessesssssstesseesseessesseestesneesseestesaeentesneesneeatenseens 46 6 3 5 Programming Watchdog Basic Operation 47 6 4 PROG RAMMING RS 4GD iia 49 CHAPTER iaa EA BIOS SETUP 7 1 BIO S SETUP OVERVIE a dt aaa 51 7 2 STANDARD CMOSSETUP irisa aa aa a a a E 53 7 3 ADVANCED CMOS SETUP aii 55 7 4 ADVANCED G HIPSET SETUP ainia cin riia 59 75 PERIPHERA SEI chat inicia id n dt zu ad al ak dv iret a mkv 61 7 6 AUTO DETEC T HARD DISKS cccssssssssssssssssssssssssssss
18. B2300 providesthree programmable timers each with a timing frequency of 1 19 MHz Seconds lt gt gt A4 Hous 06 Dayofwek 08 Month MEN Wea a E o B 0D 11 12 tatus register C Status register D Diagnostic status byte Status register B S 11 Fxeddiktypebyte driveC 12 fixeddisktype byte de D 7 l i 19 2D 2E 2F 14 15 16 17 18 30 31 32 33 nformation flags set during poweron 34 7F Reserved for system BIOS Table 2 4 Real Time Clock 8 Non Volatile RAM TimerO The output of this timer is tied to interrupt request 0 IRQ 0 Timer1 Thistimeris used to trigger memory refresh cycles Timer2 This timer provides the speaker tone Application programs can load different counts into this timerto generate various sound frequencies 8 FablATech Corporation 2 5 SERIAL PORTS The ACEs Asynchronous Communication Elements AC El to ACE4 are used to convert parallel data to a serial format on the transmit side and convert serial data to parallel on the receiver The serial format in order of transmission and reception is a start bit followed by five to eight data bits a parity bit if programmed and one one and half five bit format only ortwo stop bits The ACEsare capable of handling divisors of 1 to 65535 and produce a 16x clock for side driving the intemal transmitter logic Provisions are also included to use this 16x clock to drive the receiver logic Al
19. ED indicator LED1 LED1 is lit yellow when poweris connected to the system Rear Panel LED Indicators LM1 LM 1 is located on the rear panel with three LED indicators 29 FablATech Corporation 30 FablATech Corporation CHAPTER 4 SOLID STATE DISK The section describesthe varioustypes of solid state disk The following topics are covered Overview Switc h Setting Jumper Setting Programming Flash amp SRAM Disk SSD Type Supported 4 1 OVERVIEW The FB2300 provides four 32 pin J EDEC DIP sockets which may be populated with up to 4MB of EPROM or 2MB of FLASH or 2MB of SRAM disk It is ideal for diskless systems high reliability and orhigh speed accessapplications controller for industrial or line test instruments and etc FLASH disk function enables you to use the 5V FLASH EPROM instead of UV EPROM and allows you to directly program the ROM disk without having to purchase any additional programming equipment If small page less or equal 512 bytes per page 5V FLASHs were used you could format FLASH disk and copy files onto FLASH disk just like using a normal floppy disk Youcan use all of the related DOScommand such as COPY DEL etc to update files on the 5V FLASH disk The write protect function allows you to prevent your data on small page 5V FLASH or SRAM disk from accidental deletion or overwrite An on board Lithium battery oran extemal battery pack that could be connected ensures data retention of SRAM to
20. ET signal to the IDE drive 3 You can not run BIOS Setup at system boot since there is no delay for the Hit Del To run Setup message Available Options Disa bled Enabled Default setting Ena bled BootUp Num Lock This field is used to activate the Num Lock function upon system boot If the setting is on after a boot the Num Lock light is lit and usercan use the number key Available Options On Off Default setting On Hoppy Drive Swap The field reverses the drive letter assignments of your floppy disk drives in the Swap A B setting otherwise leave on the default setting of Disabled No Swap This works separately from the BIOS Features floppy disk swap feature It is functionally the same as physically interchanging the connectors of the floppy disk drives When the function s setting is lt Enabled gt the BIOS swapped floppy drive assignments so that Drive A becomes Drive B and Drive B becomes Drive A underDOS Available Options Disa bled Enabled Default setting Disa bled Hoppy Drive Seek This field is used to set if the BIOS will seek the floppy lt A gt drive upon boot Available Options Disabled Enabled Default setting Disa bled Hoppy Access Control This field specifies the read write access when booting from a floppy drive Available Options Nomal Read only Default setting Normal HDD Access Control This field specifiesthe read write accesswhen booting from a HDD drive Available Options Nomal Read only Defa
21. IPC Solution Website http www fabiatech com Email supportefa biatec h com FB 2300 A In One 386SX CPUCARD Module User s Manual Oct 2005 Version 2 3 Part Number FB2300 Copyright C opyright 2001by FablATech Corporation The content of this publication may not be reproduced in any part orasa whole transcribed stored in a retrieval system translated into any language or transcribed in any form orby any means electronic mechanical magnetic etc or otherwise without the prior written permission of FablATech Corporation Disclaimer FablATech makes no representation of wamanties with respect to the contents of this publication In an effort to continuously improve the product and add features FablATech reserves the right to revise the publication or change specifications contained in it from time to time without prior notice of any kind from time to time FablATech shall not be reliable fortechnical or editorial errors or omissions which may occur in this document FablATech shall not be reliable for any indirect special incidental or consequential damages resulting from the fumishing performance or use of this document Trademarks Trademarks brand names and products names mentioned in this publication are used for identific ation purpose only and are the properties of their respective owners Technical Support If you have problems or difficulties in using the system board or setting up the releva nt devices and software t
22. J1 H Aer D Ta M1 M4 P2 ca EN JP3 E LM1LM2LM3LM4 SW1 CN12 CN10 1 J4 CN5 DB2 CN7 Bs EE J8 Lat CN9 J9 DB3 S Bu CN8 CN11 CN10 BUSA amp B 00000000000000000000000000000000 A9000000000000000000000000000000 Figure 3 5 CN10 64 Pin PC 104 Connector Bus A amp B EL TL EE 1 JoCHK 33 au 2 Ground 34 DACKI 3 s7 35 SA13 4 RSIDRV 36 DRQ1 5 s6 37 a 6 5v 38 REFSH 40 BUSC LK R08 21 sa 41 e svC2 421 RO7 Bj a fa sas 1010 00 46 ROS IRQ4 15 SD1 Lol ai Del zws 48 17 spo 49 sae 18 2v 50 IRQ3 27 SA17 59 ai 28 OR 60 os 31 sam 63 Ground 32 DRO3 64 Ground Table 3 5 CN10 64 Pin PC 104 Connector Bus A B NOTE Power input V DN 12V or 12V for Pin 10 Pin14 is supplied from the system power connected to the powerconnector 20 FablATech Corporation 2 40 Pin PC 104 Connector Bus C D CN9 J2 J3 JP1 CN4 CN1 J5 J6 CNS J7 CNS 4 JE D D JPY pom Jad l M2 pa B Ti Go Bo JP3 LM1LM2LM3LM4 CN
23. M bits T TMS27C 010 128KX8 1M bits TOSHIBA TC S711000 128KX8 1M bits AMD Am27C 020 256KX8 2M bits FUJ ITSU MBM 27C 2001 256KX8 2M bits HITACHI HN27C 201 256KX8 2M bits INTEL D27C020 256KX8 2M bits MITSUBISHI M5M27C 201 256KX8 2M bits NEC D27C2001 256KX8 2M bits NS NM27C020 256KX8 2M bits SGS THOMSON M27C 2001 256KX8 2M bits T TMS27C 020 256KX8 2M bits TOSHIBA TC S712000 256KX8 2M bits AMD Am27C 040 512KX8 4M bits FUJ ITSU MBM 27C 4001 512KX8 4M bits HITACHI HN27C 401 512KX8 4M bits INTEL D27C 040 512KX8 4M bits 74 M5M27C401 D27C4001 NM27C040 M27C 4001 TMS27C 080 TMS27C 040 TC 5714000 512KX8 4M bits 512KX8 4M bits 512KX8 4M bits 512KX8 4M bits 1024X8 8M bits 512KX8 4M bits 512KX8 4M bits 75 FablATech Corporation E PROGRAMMING TILI O AND GPOO 1 BASIC OPERATION If we would like to use I O access control must be programming the M6117C configuration register we need to unlock register at first and lock it after finishing operation The Input data SDO BITO IPO SD1 BIT1 IP1 SD2 BIT2 1P2 SD3 BIT3 AP3 The output data SD8 BIT8 Out0 SD9 BIT 9 Outl SD10 BIT10 0 ut2 SD11 BIT 11 Out3 SD12 BIT12 GPO0 SD13 BIT13 GPO1 When write INDEX 73H BIT 7 0 will sent to SD 15 8 Unlock Configuration Register Mov al 013h Mov dx 22h Out dx al Nop Nop Mov al OC bh Mov dx 23h Out dx al Nop Nop Lock Conf
24. P are both bi directional data transfer schemes that adhere to the IEEE P1284 specific a tio ns Available Options Normal EPP ECP Default setting Normal EPP Version This field indicatesthe EPP forthe Parallel Port specific ation version used in the system Parallel Port IRO This field specifies the IRQ forthe parallel Available Options 5 7 Default setting IRQ 7 for Parallel Port Parallel Port DMA Channel This field is view only 62 7 6 AUTO DETECT HARD DISKS This field detects the parameters of an IDE hard disk drive and automatically enters them into the Standard CMOS Setup screen 7 7 PASSWO RD SETTING This BIOS Setup has an optional password feature The system can be configured so that all users must enter a password every time the system boots or when BIOS Setup isexecuted User can set either a Supervisor password ora User password 7 8 SETTING PASSWO RD Select the appropnate password icon Supervisor or User from the Security section of the BIOS Setup main menu Enter the password and press Enter The screen does not display the characters entered After the new password is entered retype the new password as prompted and press Enter If the password confirmation is incorrect an error message appears If the new password is entered without error press Esc to retum to the BIOS Main Menu The password is stored in CMOSRAM after BIOS completes The next time the system boots you are prompted for the pa
25. TB Bit 3 Parity Enable PEN Bit 4 Even Parity Select EPS Bit 5 Stick Parity Bit 6 Set Break Bit 7 Divisor Latch Access Bit DLAB MODEM Control Register MCR Bit 0 Data Terminal Ready DTR Bit 1 Reguest to Send RT5 Bit 2 Out 1 OUT1 Bit 3 Out 2 OUT2 Bit 4 Loop Bit 5 Must be O Bit 6 Must be O Bit 7 Must be O Line Status Register LSR Bit 0 Data Ready DR Bit 1 Overrun Error OR Bit 2 Parity Error PE Bit 3 Framing Error FE Bit 4 Break Interrupt Bl Bit 5 Transmitter Holding Register Empty THRE Bit 6 Transmitter Shift Register Empty TSRE Bit 7 Must be 0 MODEM Status Register MSR Bit 0 Delta Clearto Send DCTS Bit 1 Delta Data Set Ready DDSR Bit 2 Training Edge Ring Indicator TERI Bit 3 Delta Receive Line Signal Detect DSLSD Bit 4 Clearto Send CTS Bit 5 Data Set Ready DSR Bit 6 Ring Indicator RI Bit 7 Received Line Signal Detect RSLD 10 FablATech Corporation DivisorLatch LS MS AS MS Desired Baud Rate Divisor Used to Generate 16x Clock N owe Mn a Ll Pp BOO 6 MM 8 ee PM ee 28800 Table 2 6 Serial Port Divisor Latch 2 6 PARALLEL PORTS gt Register Address Port Address Read Write Input data Printer status buffer Printer control latch Table 2 7 Registers Address gt Printer Interface Logic The parallel portion of the SMC 37C 669 makes the attachment of various devices that acce
26. U board is tumed off Step 4 Connect all necessary cables Make sure that the FDC HDC serial and parallel cablesare connected to pin 1 of the related connector Step 5 Connect the hard disk floppy disk flat cables from the CPU board to the drives Connect a power source to each drive Step 6 Plug the keyboard into the keyboard connector Step 7 Tum on the power Step 8 Configure yoursystem with the BIOS Setup program then re boot your system Step 9 If the CPU board does not work tum off the power and read the hardware description carefully again Step 10 If the CPU board still does not perform property retum the board to your dealer for immediate service 43 FablATech Corporation 6 2CDROM FB2300 provides a CD ROM includes the manual files a complete manual file and a quick setting guide and the reguired utility files Follow the following description to install these utility files 6 2 1 VGA DriverforWIN3 1 Sep 1 Step 2 Step 3 Step 4 Step 5 Step 6 Sep 7 Step 8 Step 9 To install the VGA driver insert the CD ROM into the CD ROM device and enter DRIVER gt FB2300 gt VG A gt 65545 If your system is not equipped with a CD ROM device copythe VGA driverfrom the CD ROM to a 1 44 diskette Execute setup exe file The screen showsthe chip type Press any key to enterthe main menu There are some items for choice to setup Please choose the lt Windows Version 3 1 gt item noti
27. Wait Disable PCLK2 10 ISA I O High Speed Enabled PCLKZ 12 ISA Memory High Speed Enabled 1 0 Recovery Disable 1 0 Recovery Period 0 us 16Bit o Insert Wait Disable Watch Dog Timer Output Control Disabled WatchDog TimeOut Trigger Signal Reset ESC Exit T4 5el PgUp PgDn Modify F2 F3 Color Figure 7 4 Advanced Chipset Setup ATBus Clock This field sets the polling clock speed of ISA Bus PC 104 Available Options 14 318 2 PCLK 5 PCLK 6 PCLK 8 and PCLK 12 Default setting 14 318 2 NOTE 1 PCLK meansthe CPU inputs clock 2 User is recommended to use setting at the range of 8MHz to 10MHz Slow Refresh This field sets the DRAM refresh cycle time Available Options 15 us 60 us and 120 us Default setting 60 us RAS Precharge Time This field specifies the length of the RAS precharge part of the DRAM access cycle when EDO DRAM isinstalled Available Options 1 5 3 5 T Default setting 1 5T RAS Active Time Insert Wait This field specifies the RAS Active Time Insert Wait function Available Options Disabled Enabled Default setting Disabled CAS Precharge Time Insert Wait This field specifies the DRAM CAS precharge time Available Options Disabled Enabled Default setting Disa bled 59 FablATech Corporation Memory Write Insert Wait This field specifies the Memory Write Insert Wa it function Available Options Disa bled Enabled Default setting Disa bled ISA VO High Speed The field specifies th
28. aan anna tea nn 19 Table 3 5 CN3 64 Pin PC 104 Connector Bus A EB u eee eee eee eee eee nenene ten nn teen h ent 20 Table 3 6 CN9 40 Pin PC 104 Connector Bus C 8D eee eee eee craneo 21 Table 3 7 PC 104 ISA Pin Acgionmente eee eee eee eee eee nenene AK KKK AK KK AAR AKA R KARR KK A Rt n 22 Table 3 8 CN1 Hard Disk IDE Connechor A 23 Table 3 9 CN3 Parallel Port Pin ASSIQGNMENKS 2 2 2222 eee eee eee eee eee een nee ate h na e tn ah nantes 25 Table 3 10 RS 232C Connector iis ioc A tka uo nd dee adver eee 26 Table 3 LVGN5 Pin Assi Me NUS iii A ee oe 27 Table 3 12 CN7 RJ 45 Pin Asgionmente AAA 28 Table 4 1 SW1 4 SSD Memory Type Gelect eee eee ee eee nenene nen nK KKK ARK AA EE unnn R Rt n Es 34 Table 5 1 CN4 LCD Connector Pin Asgonments AA 41 Vill FablATech Corporation CHAPTER 1 OVERVIEW This chapter provides an overview of your system features and capabilities The following topics are covered gt Introduction gt Packing List gt Features 1 1 INTRODUCTION The FB2300 series are featured with a compact all In One mature and well developed half size 386SX CPU card It provides greater performance such as support foronboard 2MB DRAM with 6MB expansion capacity 10Base T NE2000 compatible network one RS 232C PS 2 compatible keyboard and mouse interface 1 parallel port It has four sockets of up to 4MB 2MB SSD or three socket for up to 3MB 1 5MB and one socket for the DiskO nC hip with up to 288 MB memory
29. age Up Page Down or keys to set the current date Follow the month day and year format Highlight the lt Time gt field and then press the Page Up Page Down or keys to set the current date Follow the hour minute and second format The user can bypass the date and time prompts by creating an AUTOEXEC BAT file For information on how to create this file please referto the MS DOS manual Hoppy Setup The lt Standard CMOS Setup gt option records the types of floppy disk drives installed in the system To enter the configuration value for a particular drive highlight its comesponding field and then select the drive type using the left or right arrow key Hard Disk Setup The BIOS supports various types for user settings The BIOS supports Pri Master Pri Slave gt lt Sec Master gt and lt Sec Slave gt so the user can install up to four hard disks Forthe master and slave jumpers please refer to the hard disk s installation descriptions and the hard disk jumper settings You can select lt AUTO gt under the lt TYPE gt and lt MODE gt fields This will enable auto detection of your IDE drives during bootup This will allow you to change your hard drives with the power off and then power on without having to reconfigure your hard drive type If you use older hard disk drives which do not support this feature then you must configure the hard disk drive in the standard method as described above by the lt USER gt optio
30. arallel Port 1 bi directional type parallel port Keyboard PC ATcompatible keyboard with 6 pin mini din connector Real Time Clock BIOS Watchdog Solid State Disk TIL Ethemet Mouse amp keyboard Buzzer LED Indicator Power Connector Battery Speaker Power Reg PC Board Dimensions Safety Other Optional features BQ3287MTorcompatible chips Legal AMI Flashed system fla sh BIOS with easy upgrade capability Programmable Watchdog timer 4 socketsof up to 4MB EPROM or2MB SRAM Fla sh disk or 3 sockets of up to 3MB EPROM or 1 5MB SRAM Flash disk and 1 socket for DiskO nChip 4 TILinputsand outputs NE2000 compatible RJ 45 edge connector or BNC PS 2 compatible mouse amp keyboard interface One buzzeron board Power LAN and HDD One 4 pin and one 8 pin 2 5mm optional powerconnector Onboard Lithium battery for SRAM disk Extemal speaker connector 5V 2 0A maximum 6 layers 185 mm X 122 mm EMI considered on every output signals E2KEY function forsafe CMOSdata storage 69 FablATech Corporation B1 PLACEMENT J2 J3 JP CNA CN1 J5 J6 CN2 J7 CN DB1 DB2 1 o M3 E CN7 SW1 CN12 p M4 CN10 AR DB3 JP6 i ae CN8 Dem e CNS J9 E sve E G5 E 4 E 5 M1 Kn BETET 70 B2 DIMENSIONS 1219 43 5 hole TYP CE EE EHT mmm Unit mm 71 FablATech Corporation C EXTERNAL WATCHDOG TIMER The I O ports of extemal Wa
31. ce the function key defined Press ENTER selected the lt All Resolutions gt when this line appears symbol which means this item is selected Pressing End starts to install The screen will show the dialog box demanding the user to type the WIN31 s path The defaultisCA WINDOWS Asthe setup iscompleted the system will generate the message asfollows Installation is done Change to your Windows directory and type SETUP to run the Windows Setup program Choose one of the new drivers marked by an Please refer to the User s Guide to complete the installation Press the Esc key to retum to the main menu and re press the Esc key to retum to the DOS mode In the WIN31 you can find the lt Chips CPL gt icon located in the CONTROL PANEL group Adjust the lt Refresh Rate gt lt Cursor Animation gt lt Font size gt lt Resolution gt and lt Big Cursor Note In the VGA directory a readme txt file isincluded to provide installation information 6 2 2 Sep 1 Step 2 LAN Utility To install the LAN utility insert the CD ROM into the CD ROM device and enter DRIVER gt FB2300 gt LAN gt UM9008 If your system is not equipped with a CD ROM device copy the LAN driverfrom the CD ROM to a 1 44 diskette Exec ute install exe file 44 6 3 INTERNAL WATC HDOG TIMER This section describes how to use the Watchdog Timer disabled enabled and trigger The FB2300 is equipped with a programmable time o
32. d Disk IDE Connector BL _DAma DATA 15 Pin ESAS E 7 Dms 8 DAAV Table 3 8 CN1 Hard Disk IDE Connector 23 FablATech Corporation 3 3 4 Reset Header J 3 J3 isused to connect to an extemal reset switch Shorting these two pins will reset the system J5 J6 CN2 _ J7 CN3 o CN5 yp2 Lal Di e Mi Lian J 3 J1 h M2 DB1 DB2 x s ll ony 2 Reset EA sw E 1 Reset CN12 ong Kf DB3 JP6 de ZE F 9 _ cNs B 7 CN9 rk Jeu Figure 3 8 J 3 Reset Header 3 35 Parallel Port Connector CN3 Use the included adapter cable to connect the 26 pin header type CN3 This adapter cable is mounted on a bracket and is included in your FB2300 package The connector for the parallel port is a 25 pin D type female connector The following table shows signal connections between 26 pin 8 DB25 connectors J24r J3 JP1 CN4 CN1 J5 J6 C CN3 E kaf 5 D e CN3 ESE n n L pla B o CNS 25 1 dddald 2 E E e Mi LM1LM2LM3LM4 J1 e DB1 DB2 26 2 Y M3 CN7 Swi CN12 M CN10 Tipps JP6 de SCC D CNS A H JP7 CNS JO or
33. disk Flash BIOS with easy upgrade utility Software programmable watchdog timer Low power consumption 5V only 2 0A maximum EMI Considered on every output signals Compact size 185 mm x 122 mm FablATech Corporation 1 4 PACKING LIST The following accessories are included in the package Before you begin installing your FB2300 board take a moment to make sure that they have been included inside the FB2300 package gt 00000 1 FB2300 all in one CPU board 1 40 pin hard disk drive interface cable 1 34 pin floppy drive interface cable 1 parallel port interface and seral port interface cable with bracket 1 BNC adapter with FB4616 Option item 1 PS 2 mouse adaptercable with bracket O ption item 1 CD ROM including necessary utility drivers quick setting guide file and this manual file NOTE If any of the listed accessoriesis missing or damaged please contact your dealer for immediate servicing FablATech Corporation FablATech Corporation CHAPTER 2 SYSTEM CONTROLLERS This chapter describes the major structure of the FB2300 CPU board The following topics are covered Microprocessor DMA Controller Keyboard Controller Interupt Controller Serial Ports Parallel Ports 000000 2 1 MIC ROPROCESSOR The FB2300 uses the AU M6117 CPU it is designed to perform systems like Intel s 386SX system with deep green features The 386SX core is the same as M1386SX of Acer Labs Inc and 100 object code com
34. e ISA I O High Speed function Available Options Disa bled Enabled Default setting Ena bled ISA Memory High Speed This field specifiesthe ISA Memory High Speed function Available Options Disa bled Enabled Default setting Ena bled VO Recovery If I O Recovery Feature field is enabled the BIOS insert a delay time between two I O commands The delay time is defined in I O Recovery Period field Available Options Disa ble Ena ble Default setting Disa ble VO Recovery Period This specifies the I O recovery delay time Available Options 0 3 5 us Default setting 1 5 us 16Bit ISA Insert Wait This field specifies the 16bit ISA Insert Wait function Available Options Disable Enable Default setting Disable Watch Dog Timer Output Control This function isto enable or disable the Watchdog timer function Available Options Disabled 30 45 60 75 90 105 and 120 sec Default setting Disabled Watch Dog Timeout Trigger Signal This field can be configured This function is to select IRQ or RESETforthe Watchdog different function Available Options IRO 3 IRQ4 IRO9 IR10 IRQ11 IRQ12 IRQ15 and RESET Default setting RESET 60 7 5 PERIPHERAL SETUP This section is used to configure penpheral features AMIBIOS SETUP PERIPHERAL SETUP C 1998 American Megatrends Inc All Rights Reserved Hard disk Delay 3 Sec Available Options Onboard IDE Enabled 3 OnBoard FDC Enabled 4 OnBoard Serial Port1 3F5h 5 OnBoard
35. emory type select JM4 LED1 Intemal Power LED Table 3 1 List of Connectors and J umpers 3 3 SYSTEM SETTING S Jumper pins allow you to set specific system parameters Set them by changing the pin location of jumperblocks A jumper block isa small plastic encased conductor shorting plug that slips over the pins To change a jumper setting remove the jumper from its current location with your fingers or small needle nosed pliers Place the jumper over the two pins designated for the desired setting Press the jumper evenly onto the pins Be careful not to bend the pins We will show the locations of the FB2300 jumper pins and the factory default settings CAUTION Do not touch any electronic component unless you are safely grounded Wear a grounded wrist strap ortouch an exposed metal part of the system unit chassis The static discharges from your fingers can pemmanently damage the electronic components 16 FablATech Corporation 3 3 1 Keyboard Mouse Connector CN11 amp J 9 1 6 Pin Mini DIN Keyboard Mouse Connector CN11 The keyboard mouse connector isa Mini DIN 6 pin connector labeled CN11 Itisa PS 2 type connector and is also used fora standard IBM compatible keyboard with a keyboard adapter cable The pin assignments forthe PY2 port connector are asfollows J J JP1 CNA CNI J5 J6 CN2 Ji CN3
36. ercan load the optimal default settings forthe BIOS The optimal default settings are best case values that should optimize system performance If CMOSRAM is comupted the optimal settingsare loaded automatically Load high performance settings Y N AMIBIOS HIFLEX SETUP UTILITY VERSION 1 16 C 1996 American Megatrends Inc All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup uto Detect Hard Disks Load high performance settings Y N 7 N Exit Without Saving Load configuration settings giving highest performance ESC Exit Tl Sel F2 F3 Color F1 Save 4 Exit Figure 7 7 Load High Performance Setting 64 7 11 1 Auto Configuration with Fail Safe Settings User can load the Fail Safe BIOS Setup option settings by selecting the Fail Safe item from the Default section of the BIOS Setup main menu The Fail Safe settings provide far from optimal system performance but are the most sta ble settings Use this option asa diagnostic aid if the system is behaving ematic ally Load failsafe settings Y N AMIBIOS HIFLEX SETUP UTILITY VERSION 1 16 C 1996 American Megatrends Inc All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup uto Detect Hard Disks KI Load failsafe settings CY N 7 N Exit Without Saving Load failsafe configuration settings ESC Exit Tl Sel F2 F3 Col
37. ervice routine to execute The following table contains the system information of hardware interupt pniorities System interupe IRO neon RN IRO O System timer Timer Channel O output 1 oon oa keyboard controle output burt niempt 2 Cascade from second programmable intenupt if see cee lings come ee TS Ch RO4 COML O 11 n IRQ6 Foppydiskette adapter In 70h IRQ8 RealTimeCock CTC E 3 72h RO10LANadapter CT n ROCO 5 J I RQ12 ReseredforPY2mouse 76h RO 14Harddiskette adapter Ab RO 15Reserved forWatchdog_____ 8 Table 2 2 Interrupt Controller FablATech Corporation 2 4 1 VO PortAddress Map HexRange ss Dewee 070 071 Real time clock RTC non mask able interrupt NMI 080 09F DMA page registers 208 20A EMS register 0 300 31F_ Prototype card streaming type adapter 320 33F LAN adapter Table 2 3 I O Port Address Map FablATech Corporation 2 4 2 Real Time Clock and Non Volatile RAM The FB2300 contains a realtime clock compartment that maintains the date and time in addition to storing configuration information about the computer system It contains 14 bytes of clock and control registers and 114 bytes of general purpose RAM Because of the use of CMOS technology it consumes very little power and can be maintained for long periods of time using an intemal Lithium battery The contents of each byte in the CMOS RAM are listed below 2 4 3 Timer The F
38. h FFh 512 sec NOTE 1 If you program the watchdog to generate IRO 15 signal when it times out you should initial IRO 15 intemupt vectorand enable the second intemupt controller 8259 PIC in orderto enable CPU to processthis interupt An intemupt service routine is required too 45 FablATech Corporation 2 Before you initialize the interupt vector of IRO 15 and enable the PIC please enable the watchdog timer previously otherwise the watchdog timer wil generate an interupt at the time watchdog timer is enabled 6 3 2 Watchdog Enabled Disabled INDEX 37H Bit 7 Reserved Please do not set this bit In old version M6117C data sheet this bit iscounter read mode Bt6 0 Disa ble watchdog timer 1 Enable watchdog timer Bit 5 0 Other function Please do not modify these bits 6 3 3 Select Watchdog Report Signal INDEX 38H Bit 7 4 Watchdog timertime out report signal select 0000 No output signal 0001 IRQ3 selected 0010 IRQ4 selected 0011 IRQ5 selected 0100 IRQ6 selected 0101 IRQ7 selected 0110 IRO9 selected 0111 IRO10 selected 1000 IRO 11 selected 1001 IRQ 12 selected 1010 IRQ 14 selected 1011 IRQ 15 selected 1100 NMI selected 1101 System reset selected 1110 No output signal 1111 No output signal Bit 3 0 Otherfunction Please do not modify these bits NOTE 1 If you program the watchdog to generate IRO 15 signal when it times out you should initialize IRO 15 interupt vector and enable the second intemupt controlle
39. hat are not explained in this manual please contact our service engineer for service or send email to support fabiatech com Retuming Your Board For Service amp Technical Support If your board requires servicing contact the dealer from whom you purchased the product for service information You can help assure efficient servicing of your product by following these guidelines o A list of your name address telephone facsimile number oremail address where you may be reached during the day Q Description of you peripheral attachments Q Description of you software operating system version application software etc and BIOS configuration o Description of the symptoms Extract wording any message Forupdated BIOS drivers manuals or product information please visit us at www fabiatech com Static Electricity Precautions Before removing the board from its anti static bag read this section about static electricity precautions Static electricity isa constant dangerto the computer systems The charge that can build up in your body may be more than sufficient to damage integrated circuitson any PC board It is therefore important to observe basic precautions whenever you use or handle computer components Although areas with humid climates are much less prone to static build up it is always the best to safeguard against accidents which may result in expensive repairs The following measures should generally be sufficient to protec
40. iguration Register mov al 013h mov dx 22h out 22h al nop nop mov al 000h Mov dx 23h out dx al nop nop o Read the INPUT Value at Configuration Register Forexample read INDEX 3eh Unlock configuration register mov al 03eh mov dx 22h out 22h al nop nop inc dx In al dx and al Ofh INPO INP3 BITO BIT3 data nop nop push Ax 76 Lock configuration register pop gt ax AL result Write OUTPUT Data to Configuration Register Forexample write OFFh to INDEX 3dh Unlock configuration register mov mov out nop nop mov inc out nop nop mov mov out Inc mov out al 03dh dx 22h dx al al Offh OUTO OUTS BIT8 BIT11 data dx dx al dx 22h al 73h dx al dx al 00h dx al Lock configuration register 7
41. lates field select HDD that the flash disk will act asa physical hard disk Then save the setting The system will be restart the screen like below 36 FablATech Corporation Step 8 Step 9 AMIBIOS SETUP ADVANCED CMOS SETUP 011998 American Megatrends Inc All Rights Reserved Floppy Drive 5eek Floppy Access Control HDD Access Control PS5 2 Mouse Support Tupematic Rate System Keyboard Primary Display Password Check Wait For FU If Error Hit DEL Message Display LE 32k Shadow C800 32k Shadow D000 32k Shadow D800 32k Shadow E000 32k Shadow BOG SRAM Disk Simulates Close all screen at POST state OLA E Mad Oly Bolid State DISK DOGOH LASH Disk Simulates HDD Disabled Normal Normal Disabled Fast Absent Absent Setup Enabled Enabled Enabled Disabled Disabled Disabled Disabled Disabled Available Options HDD FDD ESC Exit tl 3el PgUp PgDn Modify F2 F3 Color HDD Disabled The screen like below Step 10 Press hold down ctr_ keys ctrl underine to display the SSD Setup menu On the screen use the up ordown arrow keys to select a flash type and size FB2300 SSD BIOS version 1 20 c 2000 FablATech Corp EPROM Disk Setting Absent Flash Disk Setting Disk 80h C Unknow 2048 Maximum SRAM Disk Setting Absent Base Port Address 0078h Firmware Seg DOOOh Data Bank Seg 800h DOS Booting Driver As BIOS Setting M4 U5 Socket Setting
42. ltaneously 5 Setthe JM1to JM4 jumpersto EPROM position 6 Install the EPROM in Socket U21 U16 U10 and U5 7 Poweron the system 4 3 2 Programming Hash and SRAM disk Programming SSD FDD Step 1 Install the Flash SRAM chips in Socket U21 U16 U10 or U5 Step 2 Set the J M1 to J M4 jumpers and SW1 to FLASH SRAM Disk position Step 3 Connect power to the system Step 4 Power on Step 5 Press Delete key to display the BIOS Setup menu Step 6 Enter CMOS Setup menu Then choice to CMOS SET UP gt ADVANCE CMOS SETUP gt SSD FUNCTION set to DOOOH SEG MENT Step 7 In the Flash Disk Simulates field select FDD that the flash disk will act asa physical floppy Then save the setting The system will be restart the screen like below 35 FablATech Corporation Step 8 Step 9 Step 10 Step 11 Step 12 Step 13 Step 14 AMIBIOS SETUP ADVANCED CMIS SETUP C11998 American Megatrends Inc All Rights Reserved Floppy Drive Seek Disabled Available Options Floppy Access Control Normal HDD HDD ficcess Control Normal gt FDD P572 Mouse Support Disabled Typematic Rate Fast System Keyboard Absent Primary Display Absent Password Check Setup Wait For PU If Error Enabled Hit DEL Message Display Enabled CO 32k Shadow Enabled C800 32k Shadow Disabled D1000 32k Shadow Disabled D8500 32k Shadow Disabled E009 J32k Ec Disabled a isabled ESC Exit tl 5el PgUp PgDn Modify Close all sc
43. n Boot Sector Virus Protection This option protects the boot sector and partition table of your hard disk against accidental modifications Any attempt to write to them will cause the system to halt and display a waming message If this occurs you can either allow the operation to continue or use a bootable virusfree floppy disk to reboot and investigate your system The default setting is 53 FablATech Corporation lt Disabled gt This setting is recommended because it conflicts with new operating systems Installation of new operating system requiresthat you disable thisto prevent write errors 54 7 3 ADVANC ED CMOS SETUP The lt Advanced CMOS SETUP gt option consists of configuration entries that allow you to improve your system performance or let you set up some system features according to your preference Some entries here are required by the CPU board s design to remain in their default settings AMIBIOS SETUP ADVANCED CMOS SETUP C 1998 American Megatrends Inc All Rights Reserved et Boot Device IDE 0 Available Options nd Boot Device Floppy Disabled 3rd Boot Device CDROM k IDE O Quick Boot Enabled IDE 1 BootUp Num Lock n IDE 2 Floppy Drive Swap Disabled IDE 3 Floppy Drive Seek Disabled Floppy Floppy ccess Control Normal ARMD FDD HDD Access Control Normal ARMD HDD PS 2 Mouse Support Disabled CDROM Typematic Rate Fast SC3I System Keyboard Absent NETWORK Primary Display Absent Password Check Setu
44. nd E800 Default setting Disa bled 57 FablATech Corporation Hash Disk Simulates When HDD isselected the system will boot from the flash disk asif itisa hard disk drive C When FDD is selected the system will boot from the flash disk as if it isa floppy disk drive al Available Options HDD FDD Default setting HDD SRAM Simulates When HDD is selected the system will boot from the SRAM asif itisa hard disk drive C When FDD is selected the system will boot from the SRAM asif it isa floppy disk drive a Available Options HDD FDD Default setting HDD Close all screen at post Upon poweron the system will skip POST and enterthe OSin five seconds If this function is enabled also configure the following fieldsto these parameters Hit Del Message Display Disabled Wait For Fl If Error Disabled System Keyboard Absent Primary Display Absent Hard Disk Display Disabled Available Options Disabled Enabled Default setting Disabled 58 7 4 ADVANCED CHIPSET SETUP This option controls the configuration of the board s chipset Control keys for this screen are the same asforthe previous screen AMIBIOS SETUP ADVANCED CHIPSET SETUP C 1996 American Megatrends Inc All Rights Reserved Available Options Slow Refresh 60 us 14 31872 RAS Precharge time 1 5T PCLKZ 5 RAS Active Time Insert Wait Disable PCLKZ b CAS Precharge Time Insert Wait Disable PCLK2Z 8 Memory Write Insert
45. ndow always shows the gray statement Flash EPROM Programming is going to start System will not be usable until Programming of Flash EPROM is successfully complete In case of any enor existing Flash EPROM must be replaced by new program Flash EPROM Asthe gray statement pressthe lt Y gt key to updating the new BIOS And then the lt Message gt box will show the lt Programming Flash EPROM gt and the gray statement shows lt Please Wait gt The BIOS update is successful the message will show lt Flash Update Completed Pass gt NOTE 1 If the system doesn t detect the boot procedure after power on please pressthe F5 key immediately The system will passthe CONFIG SYS and AUTO EXEC BAT files 2 The BIOS flash disk is not a standard accessory Now the onboard BIOS are the newest BIOS If user needs to add some functions in the future please contact our technical supporting engineers they will provide the newest BIOS for updating 3 Use the file AMIFLASH EXE from the attached CD ROM sfile It not uses Version 6 31 68 APPENDIX A SPECIHCATIONS CPU Chipset AL M6117 up to 40 MHzunder5V powersupply Bus Interface ISA and PC 104 expansion bus DRAM 2MB EDO RAM on board and 8MB expansion capacity CRT LCD Display CRTand LCD interface with 512K VRAM standard 1 MBVRAM optional HDC Two IDEtype han disk drives FDC Two 5 25 or 3 5 floppy disk drives Serial Port 1 RS 232C port 1 RS 232C RS 485 P
46. nfigure the FB2300 VGA module for the right type of LCD panel you are using The samples of LCD models listed on the table are just some of the LCD panel models available in the market that the Chips amp Technologies used by FB2300 VGA module can support If you are using a different LCD panel other than those listed choose from the panel description column which type of LCD panel you are using The FB2300 still needs components to be used for LCD panel The inverter board provides the control for the brightness and the contrast of the LCD panels while the inverter is the one that supplies the high voltage to drive the LCD panel Each item will be explained further in the section The following showsthe block diagram of using FB2300 for LCD display The block diagram shows that FB2300 till needs componentsto be used with a LCD panel The transfer board FB4608 provides the control forthe brightness and the contrast of the LCD panel while inverter board FB46xx isthe one that supplies the high voltage to drive the LCD panel Both FB4608 and FB46xx are available from FablATech with all the necessary Cables NOTE Be careful with the pin orientation when installing the connectors and the cables A wrong connection can easily destroy your LCD panel The pin 1 of the cable connectors is indicated with a stickerand the pinl of the ribbon cable is usually with different color 39 FablATech Corporation 5 2 CRT amp LCD DISPLAY The FB
47. ntinue If this field is set to Disabled the AMIBIOS does not wait for you to press the lt F1 gt key after an error message Available Options Disa bled Enabled Default setting Disa bled Hit DEL Message Display Set this field to Disabled to prevent the message asfollows Hit DEL if you want to run setup It will prevent the message from appearing on the first BIOS screen when the computer boots Available Options Disabled Enabled Default setting Ena bled C000 32k Shadow E800 32k shadow These fields control the location of the contents of the 32KB of ROM beginning at the specified memory location If no adapter ROM is using the named ROM area this area is made available to the local bus The settings are 1 Disabled The video ROM isnot copied to RAM The contents of the video ROM cannot be read from or written to cache memory 2 Enabled The contents of C000h C 7FFFh are written to the same address in system memory RAM for faster execution 3 Cached The contents ofthe named ROM area are written to the same address in system memory RAM for faster execution if an adapter ROM will be using the named ROM area Also the contents of the RAM area can be read from and written to cache memory Available Options Disa bled Enabled Cached Default setting Disa bled Solid State Disk This field is used to enable or disa ble the Solid State Disk function Available Options Disa bled D000 D800 E000 a
48. ogramming Watchdog Basic Operation 47 6 4 PROGRAMMING SAOD aa a dais 49 7 1 BIOS SETUP OVERVIEW iia ds 51 7 2 Seiterter UE 53 73 ADVANCED CMOSSETUE iii a dai 55 7 4 ADVANCED CHIPSETSETUP a e a a ere i A a A a A 59 7 5 PERIPHERA SETUP oia E EE EE A 6l 7 6 AUTO DETECTHARD DISKS ui as 63 7 7 PASWORD SEMN Gaia ica 63 7 8 SETTING PASO RD a dida ide 63 7 9 PASSWORD CHECKING dee ee a Aer Ee ER AE 63 7 10 OAD DEFA ULT OU EEN 64 7 11 AUT CONFIGURATION WITH OPTIMAL SETTINGS csssssssssesssscsesssssssesssesscssssesscesesesesesesesesesrscssaseseseseeeeeececasececeeesnsnses 64 7 11 1 Auto Configuration with Fail Safe Settings ENEE ENEE 65 7125 BOSA EE 66 7 137 SAVE SETTING SAND EXT genge EES 66 T A EXIT WITHOUT SAVING das 67 FAD ABIOS BOA EE 68 A SPEC ele a le 69 BL PLA CGEM ENIF sitnine h a Ea dv vadn dava ia is 70 BENENNEN EE EE Ee 71 C EXTERNAL WATCHDOG TIMER isscscssssssssssssssssssssssnsnsssusssusnsnsosecesesesessvsueseseseseauauoveeueueueseuenscsecesesasasasaueseaeaeauauauoseueueueueuenensoseses 72 D1 SRAM MEMORY dE 73 DASS BR TYPE SUPPORTED aia 74 E PROGRAMMING TILI O AND G POO 1 BASIC OPERATION EEN NENNEN 76 List of Figures FB 2300 AIHN ONE 3865X CPU CARD MODULE USER S MANUAL CROPTER La ei e eae oo Root OVERMIEW ERAT A A M 1 1 INTR DUC TON iia dai A AAA ARA a O A 1 1 2 SERIES COMPARISON TAB E ico aaa EEN 1 1 3 FEATURES 000 a 2 1 4 PACKING DST dada dauchtassensadh daUestatsundalehsaudvstceuseadelia se
49. onnector BNC EE 28 3 311 CPU Ba se Clock lect P7 Seege ee eer erer EE Ee 29 3 3 12 HDD J 2 and Power J 7 LED Indicators ee 29 41 OVERVIE iii Seet 31 4 2 SWITCH ul e 32 ELL OVENI issue sss av de nize vedas devas a 3 4 2 2 SSD and DOC Mapping Address Setting Switch 1 1 1 2 amp J PA eee 3 4 2 3 SSD Memory Type Select Switch 1 4 and J M1 to J M4 eee eee nenene A 4 3 PROGRAMMING EPRO M FLASH SRAM DISK csssssssssssssssssssssssssssssssssscsssssseseessesesesesesesesrerssasaneneseseseesecacesesecesnsnseaes 35 4 3 1 Programming EPROM DISK EEN 35 4 3 2 Programming Flash and SRAM dek ENEE 35 CHAPTERS CRT LCDFLAT PANEL DISPLAY erer 3 5 1 LED FLAT PANEL DISPLAY SE idee seess deiere 39 5 2 ERTSACODISPLA Y Sit O 40 521 CRT Connector DBL iii a dia 40 5 2 2 LCD Connector and Jumper Settings CNA leese 41 6 1 INSTALLATION PROCEDURES uti li ees 43 6 2 C DRO Mo aara O P it A O OY 44 6 2 1 VGA Driver for WIN3 1 voc ccsssesssssssscssssessssssssssscsesssssssesssnsesssessscessnsessssssscassesesesesuessneeseseseseesenseseses 44 IV 6 2 2 LAN Ur a Ra boat 44 6 3 INTERNAL WA TC ADO G TIMER o d d scott om da vist a NENNEN ana 45 6 3 1 Watchdog Timer Setting EENEG 45 6 3 2 Watchdog Enabled Disabled INDEX 37H EEN NEEN 46 6 3 3 Select Watchdog Report Signal INDEX 38H ou ENEE ENEE 46 6 3 4 Timeout Satus amp Reset Watchdog INDEX 3C Hh eesseestessesssesstesseesneeseesseestesneesseestesseentesseeseeatenseens 46 6 3 5 Pr
50. or F1i Save amp Exit Figure 7 8 Load Failsafe Setting 65 FablATech Corporation 7 12 BIOS EXIT It is used to exit the BIOS main menu in two types situation After making your changes you can either save them or exit the BIOS menu and without saving the new values 7 13 SAVE SETTINGS AND EXIT It is used to save the modified values set in the lt Standard CMOS Setup gt Advanced CMOS Setup gt lt Advanced Chipset Setup gt and the new password if it has been changed will be stored in the CMOS The CMOS checksum is calculated and written into the CMOS As you select this function the following message will appear at the center of the screen to assist you to save data to CMOSand Exit the Setup Sa ve current settings and exit Y N C 1996 American Megatrends Inc All Rights Reserved AMIBIOS HIFLEX SETUP UTILITY VERSION 1 16 Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup uto Detect Hard Disks Save current settings and exit Y N 7 Y Exit Without Saving Write the current settings to CMOS and exit ESC Exit Tl Sel F2 F3 Color F1 Save 4 Exit Figure 7 9 Save Current Settings and Exit 66 7 14 EXITWITHOUTSAVING When you select this option the following message will appear at the center of the screen to help to abandon all Data and Exit Setup Quit without saving Y N AMIBIOS HIFLEX SETUP UTILITY VERSION 1 16 C 1996 Ame
51. or IBM SDLC Channel 5 Spare Channel 2 Diskette adapter Channel 6 Spare Channel 3 Spare Channel 7 Spare Table 2 1 DMA Channel Controller FablATech Corporation 2 3 KEYBOARD CONTROLLER The 8042 processor is programmed to support the keyboard serial interface The keyboard controller receives serial data from the keyboard checks its panty translates scan codes and presents it to the system as a byte data in its output buffer The controller can interupt the system when data is placed in its output buffer or wait for the system to poll its status register to determine when data isavailable Data can be written to the keyboard by writing data to the output buffer of the keyboard controller Each byte of data is sent to the keyboard controller in series with an odd party bit automatically inserted The keyboard controller is required to acknowledge all data tra nsmissions Therefore another byte of data will not be sent to keyboard controller until acknowledgment is received for the previous byte sent The output buffer full interuption may be used forboth send and receive routines 2 4 INTERRUPT CONTROLLER The equivalent of two 8259 Programmable Interupt Controllers PIC are included on the FB2300 board They accept requests from peripherals resolve prioritieson pending intemupts in service issue interupt requests to the CPU and provide vectors which are used as acceptance indices by the CPU to determine which interupt s
52. or different types of memory AO to A6 have different explanations These bits are used to select the bank number of specific memory located in CSO and CS1 ee isi AAA NOTE BSO to BS5 are the memory bank select bits For example 128KB memory has sixteen 8K byte banks so 4 bits BSO to BS3 are needed 73 FablATech Corporation Example Select the 10th bank of the M1 U21 on the FB2300 Using CXK581000P M 128K 8 and the base port is amp H78 100 base port 8H78 110 OUTbase_port amp H19 D2 SSD TYPE SUPPO RTED The following list contains 5V FLASHs supported by the FB2300 SST PH29EE010 128KX8 1M bits SST PH28SF040 512KX8 1M bits SST PH28SF040A 512KX8 1M bits WINBOND W29EE011 128KX8 1M bits ATMEL AT29C 020 ATMEL AT29C 040 256KX8 2M bits ATMEL AT29C 040A 512KX8 4M bits The following list contains SRAMs supported by the FB2300 AKM AKM 628128 128KX8 1M bits HITACHI HM 628128 128KX8 1M bits NEC UPD431000A 128KX8 1M bits SONY C XK581000P M 128KX8 1M bits HITACHI HM 628512 512KX8 4M bits NEC UPD434000 512KX8 4M bits SONY C XK584000P M 512KX8 4M bits The following list contains EPRO Ms supported by the FB2300 AMD Am27C 010 128KX8 1M bits FUJ ITSU MBM 27C 1001 128KX8 1M bits HITAC HI HN27C 101 128KX8 1M bits INTEL D27C010 128KX8 1M bits MITSUBISHI M5M27C 101 128KX8 1M bits NEC D27C1001 128KX8 1M bits NS NM27C010 128KX8 1M bits SGS THOMSON M27C 1001 128KX8 1
53. oritized in the following sequence Highest IRQ 9 10 11 12 13 15 3 4 5 6 7 Lowest drive its data onto the data bus read data from the data bus memory are being used MEMR 16 Input Output The Memory Read signal islow while any memory location is being read The System Memory Write is low while any of the low Imega bytes of memory is being written The Memory Write signal islow while any memory location is being written DRQ 0 3 5 7 Input DMA Request channels O to 3 are for 8 bit data transfers DMA Request channels 5 to 7 are for 16 bit data transfers DMA request should be held high until the corresponding DMA has been completed DMA request priority isin the following sequence Highest DRO 0 1 2 3 5 6 7 Lowest The DMA Acknowledges 0 to 3 5to 7 are the corresponding acknowledge signalsforDRQ Oto 3and 5to 7 The DMA Address Enable is high when the DMA controller is driving the address bus It is low when the CPU is driving the address bus the microprocessoron the O channel channel isreached SBHE Input Output The System Bus High Enable indicates the high byte SD8 SD15 on the data bus MASTER Input The MASTER is the signal from the O processor which gains control as the master and should be held low fora maximum of 15 mic roseconds or system may be lost due to the lack of refresh MEM16 Input O pen The Memory Chip Select 16 indicates that the present data transfer is a 1 collector wait state 16 bit da
54. p Wait For PU If Error Disabled Hit DEL Message Display Enabled CO00 32k Shadow Enabled C800 32k Shadow Disabled ESC Exit tl Sel D000 32k Shadow Disabled Pglip PgDn Mod ify D800 32k Shadow Disabled F2 F3 Color E000 32k Shadow Disabled E800 32k Shadow Disabled Solid State DISK Disabled FLASH Disk Simulates HDD ESC Exit T 3el SRAM Disk Simulates HDD Pglip PgDn Mod ify F2 F3 Color Figure 7 3 Advanced CMOS Setup 155 3 Boot Device These fields determine where the system attempts to look for the boot drive priority for an operating system The default procedure isto check the hard disk and then the floppy drive and lastthe CDROM Available Options Disabled IDEO 1 IDE 2 IDE 3 Floppy ARMD FDD ARMD HDD CDROM and SCS Network Default setting IDE O for 1 Boot device Floppy for And Boot Device CDROM for 3 Boot Device S M A R Tfor Hard Disks This field is used to activate the S M A R T System Management and Reporting Technologies function for S M A R T HDD drives This function requires an application that can give SM A R T message Available Options Disa bled Enabled Default Disa bled Ouick Boot This field isused to activate the quick boot function of the system When set to Enabled 1 BIOS will not wait for up to 40 secondsif a Ready signal is not received from the IDE drive and will not configure its drive 55 FablATech Corporation 2 BIOS will not wait for 0 5 seconds after sending a RES
55. patible with the Intel 3865X microprocessor System manufacturers can provide 386 CPU based systems optimized for both cost and size Instruction pipelining and high bus bandwidth ensure short average instruction execution time and high system throughput Furthermore it can keep the state intemally from charge leakage while extemal clock to the core is stopped without storing the data in registers The power consumption here is almost zero until the clock stops The intemal structure of this core is 32 bit data and address bus with very low supply cument Real mode aswell as Protected mode are available and can run MS DOS MS Windows 2 2 DMA CONTROLLER The equivalent of two 8237A DMA controllers are implemented in the FB2300 board Each controller isa fourchannel DMA device that will generate the memory addresses and control signals necessary to transfer information directly between a peripheral device and memory This allows high speeding information transfer with less CPU intervention The two DMA controllers are intemally cascaded to provide four DMA channels for transfers to 8 bit peripherals DMA1 and three channels for transfers to 16 bit peripherals DMA2 DMA2 channel 0 provides the cascade interconnection between the two DMA devices thereby maintaining IBM PC AT compatibility The following isthe system information of DMA channels DMA Contoller 1 DMA Controller 2 Channel 0 Spare Channel 4 Cascade forcontroller1 Channel 1 Reserved f
56. pt eight bits of parallel data at standard TTL level gt Data Swapper The system microprocessor can read the contents of the printers Data Latch through the Data Swapper by reading the Data Swapper address 11 FablATech Corporation gt Printer Status Buffer The system microprocessor can read the printer status by reading the address of the Printer Status Buffer The bit definitions are described below 7 6 5 4 3 2 1 0 X X X ERROR SLCT PE ACK BUSY Figure 2 1 Printer Status Buffer NOTE X represents not used Bit 7 This sgnal may become active during data entry when the printer is off line during printing or when the print head is changing position orin an error state When Bit 7 is active the printer is busy and can not accept data Bit 6 This bit represents the current state of the printers ACK signal A O means the printer has received the character and is ready to accept another Normally this signal will be active for approximately 5 microseconds before receiving a BUSY message stops Bit5 A 1 meansthe printer has detected the end of the paper Bit 4 A 1 meansthe printer is selected Bit 3 A O meansthe printer hasencountered an enorcondition O PrinterControl Latch amp Printer Control Swapper The system microprocessor can read the contents of the printer control latch by reading the address of printer control swappe
57. r 8259 PIC in order to enable CPU to process this interupt An intemupt service routine is required too Before you configure the IRO signals make sure they are not conflicted with other devices like Floppy printer serial ports LAN and PS 2 mouse etc Referto Table 2 2 Interupt Controller for IRQ reference 2 Before you initialize the intemupt vector of IRO 15 and enable the PIC please enable the watchdog timer previously otherwise the watchdog timer will generate an interupt at the time watchdog timer is enabled If you want to generate IRO 15 signalto wam your program when watchdog times out the following table listed the relation of timer factors between time out period And if you use the IRO 15 signalto wam your program when watchdog timer out please enterthe BIOS Setup the Peripheral Setup gt menu the lt OnBoard PCI IDE gt and 4DE Prefetch gt these two items must set to Primary 6 3 4 TimeoutSiatus amp Reset Watchdog INDEX 3CH Bt7 0 Timer timeout not happened 1 Timer timeout happened Read only 46 Bit5 Write this bit 1 to reset timer The value on this bit hasno meaning Bt6 Otherfunction Bit 4 0 Please do not modify these bits 6 35 Programming Watchdog Basic Operation If we would like to access M6117C configuration register we need to unlock register at first and lock it after finishing operation gt Unlock Configuration Register Mov al 013h out 22h al nop nop mov al Oc5h out 23h
58. r Bit definitions are as follows 7 6 5 4 3 2 1 0 X STROBE AUTO FD XT INIT SLDC IN IRQ ENABLE DIR write only Figure 2 2 Printer Control Bit Definitions NOTE X represents not used Bit 5 Direction control bit When logic 1 the output buffers in the parallel port are disabled allowing data driven from extemal sources to be read when logic 0 they work as a printer port This bit is writing only Bit 4 A 1 in this position allows an interupt to occur when ACK changes from low state to high state Bit 3 A 1 in this bit position selects the printer 12 FablATech Corporation Bit 2 A Ostartsthe printer 50 microseconds pulse minimum Bit 1 A 1 causesthe printer to line feed after a line is printed Bit 0 A 0 5 microsecond minimum highly active pulse clocks data into the printer Valid data must be present fora minimum of 0 5 microseconds before and afterthe strobe pulse 13 FablATech Corporation 14 FablATech Corporation CHAPTER 3 HARDWARE FEATURES This section describes the pin assignments for system s extemal connectors and the jumper settings Board Overview gt System Setting 3 1 BOARD OVERVIEW The FB2300 is an all in one half size 386SX CPU board This section provides hardware jumper settings the connectors locations and the pin assignment J2 J3 JP1 CN4 CN1 JS J6 CN2 J7 CNS
59. reen at POST state Disabled F2 F3 Color Press hold down ct keys ctrl amp undenine to display the SSD Setup menu On the screen use the up ordown arrow keysto select a flash type and size The screen like below FB2300 SSD BIOS version 1 20 c 2000 FablA Tech Corp EPROM Disk Setting Absent Fla sh Disk Setting Disk B Unknow 2048 Maximum SRAM Disk Setting Absent Base Port Address 0078h Firmware Seg DOOOh Data Bank Seg 800h DOS Booting Driver As BIOS Setting M4 U5 Socket Setting SSD Hit lt Ctr gt to setup Flash disk Press F5 to save the setting The message Write to FLASH disk y n displayed Press Y key to save the setting to the Flash disk The booting from other device Like physical HDD or FDD Use the FORMATcommand to format the flash disk in DOS mode This time this SSD is B Use FORMATB S C U The S SYSTEM BOOTING C Check U UNFORMAT If format parameterno S the SSD will be alwaysto device B that can t boot up the system Programming SSD HDD Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Install the Flash SRAM disk in Socket U21 U16 U10 or U5 Set the J M1 to J M4 jumpers and SW1 to FLASH SRAM Disk position Connect power to the system Power on Press Delete key to display the BIOS Setup menu Enter CMOS Setup menu Then choice to CMOS SET UP gt ADVANCE CMOS SETUP gt SSD FUNCTION set to DOOOH SEG MENT In the Flash Disk Simu
60. rican Megatrends Inc All Rights Reserved Standard CMOS Setup Advanced CMOS Setup Advanced Chipset Setup Peripheral Setup uto Detect Hard Disks Dutol Quit without saving Y N 7 N Duto Exit Without Saving Exit without saving the current settings ESC Exit Ttl Sel F2 F3 Color Fi6 Save amp Exit Figure 7 10 Quit Without Saving 67 FablATech Corporation 7 15 BIOS UPDATE The BIOS progra m instructions are contained within computer chips called FLASH ROMs that are located on your system board The chips can be electronically reprogrammed allowing you to upgrade your BIOS finmware without removing and installing chips The FB2300 provides FLASH BIOS update function for you to easily upgrade newer BIOS version Please follow the operating stepsforupdating new BIOS Step 1 Step 2 Step 3 Step 4 Step 5 Step 6 Step 7 Tum on your system and skip detecting the CONFIG SYS and AUTO EXEC BAT files Keep your system in the real mode Insert the FLASH BIOS diskette into the floppy disk drive In the MS DOS mode you can type the AMIFLASH program AA gt AMIFLASH The screen will show the message asfollows Enter the BIOS File name from which Flash EPROM will be programmed The File name must and with a lt ENTER gt or press lt ESC gt to exit Enter the file name to the box of lt Enter File Name gt And the box of Message gt will show the notice as follows The bottom of this wi
61. s Enable When M4isinstalled with DOC set the J P4 to Enable DOC position asfollows Also set SW1 4 to ON and JM1 JM4 to DOC position The settings of J M1 J M4 will be introduced in next page D800 0 8KBytes DA00 0 8KBytes Note Disable DOC M4 only Factory Preset Figure 4 2 SSD and DOC Mapping Address Settings M4 U5 is ready for serving DiskOnC hip 33 Enable DOC M4 only If DOC isenabled please set SW1 4 to ON position to enable flash function and FablATech Corporation 4 2 3 SSD Memory Type Select Switch 1 4 and J M1 to J M4 The Switch 1 2 is used to select the memory bank segment s You must select an appropriate address so that the FB2300 will not conflict with memory installed on other add on memory cards Additionally be sure not to use shadow RAM area or EMM drivers page frame in this area ON OFF SW1 4 Memory Type Remark Off EPROM Preset FLASH DOC Table 4 1 SW1 4 SSD Memory Type Select Socket Package U21 M1 DIP32 U16 M2 DIP32 U10 M3 DIP32 U5 M4 DIP32 JM1toJM4 5 EPROM Flash DOC M4 only Factory Preset Figure 4 3 J M1 to J M4 Settings If you are not going to use the Solid State Disk SSD you can use BIOS setup program to disable the SSD BIOS The FB2300 will not occupy any memory address if the SSD BIOS is disabled If you are going to install the EMM386 EXE driver plea
62. se use the X option to prevent EMM 386 EXE from using the particular range of segment address as an EMS page which is used by FB2300 For example write a statement in the CONFIG SYS file as follow If the memory configuration of FB2300 is C 800 0 DEVIC E C DOS EMM386 EXE X C 800 C 9FF 34 FablATech Corporation 4 3 PROGRAMMING EPRO M FLASH SRAM DISK FB2300 can boot from the EPROM FLASH orSRAM disk The following introduces how to use any of the devices for boot up purpose The drive number of flash disk always followsthe existing physcial hard disks and the drive number of SRAM disk always following the flash disk Please see the following table for details Number Of Physic al HDD Physical HDD 1 Physical HDD 2 0 None None 80H C None 80H C 81H D None None 80H C None 80H C 81H D 4 3 1 Programming EPROM DISK 1 Use the generate ROM utility to create a ROM file in EPROM 2 Use the EPROM writer machine to program the EPROM 3 Install the EPROM in Socket U21 U16 U10 or U5 4 Adjust SW1 3 Note 1 If there isno DOS booting system on this SSD the disk number will be 1 B If any DOS booting system is found by SSD BIOS the disk number will be 0 A But you can change the disk number from 0 to 1 by pressing the lt ESC gt key during system bootup Note 2 The EPROM disk and flash disk will not exist simu
63. sescssesesssesesesesrscsssceneseeesessesasasesesesesesesesesesesrersranaseneeseeeeesnes 63 7 7 PASSW O DiS a N E E EEEE E E e e 63 7 8 SETTING PASSWORD EE 63 7 9 PASSWORD CHECKIN Gitina nin ni ii 63 TO LOAD DEFAULT SETTINGS ast r n Ata a dan Ain E u dn 64 7 11 AUT CONFIGURATION WITH OPTIMAL SETTINGS cssssssssssesescsesssssssssssssessscssesesesesesesesesesrsusrscasaneneseseseesacaseceseeesnsnses 64 7 11 1 Auto Configuration with Fail Safe SettidQS ENEE ss 65 LIZ Ce KE RE 66 LIS SAVE SETTINGS CN DUNN ere 66 AS SS 67 FAS BIOS UPDATE aa 68 A SPEGIFNCATON E 69 EAR EWEN geed ee Ee 70 b2 DIMENSIONS za aa a a a vadn ii iia 71 C EXTERNAEWATEHDO GTIMER r n t a e aSa ae Eataa Vasi ase a 72 D1 SRAM MEMORY d CT 73 D2 SSD TYPE SUPPORTED rara ae 74 E PROGRAMMING TILI O AND GPOO0 1 BASIC OPERATION wisssssesssscssssssssesssssssessscsesssesssessseseseseseseassesesesesestessesesesenens 76 List of Tables Table 2 1 DMA Channel Conter 5 Table 2 2 Interrupt Conti llevada capi 6 Table 2 3 1 0 Port Address MaD EEN 7 Table 2 4 Real Time Clock Non Volatile RAM AA 8 Table 2 5 ACE Accessible Reader 9 Table 2 6 Serial Port Divisor LAtCH ee eee eee ee eee eee nene eee ena rn 11 Table 2 7 Registers Addrece ENEE 11 Table 3 1 List of Connectors and lumpem ee eee cnn 16 Table 3 2 CNIT Pin e Il CN 17 Table 3 3 NERT e ue ne 18 Table 3 4 Floppy Connector Pin Asionments 0000 eee nene nene
64. so included in the ACE a completed MODEM control capability and a processor interupt system that may be software tailored to the computing time required to handle the communications link The following table isa summary of each ACE accessible register Port Address ert Perser buffer read Transmitter holding register write O Base 1 Intemuptenable sid X Base 5 linestatus Base 0 Divisorlatch least significant byte Base 1 Divisorlatch most significant byte X Table 2 5 ACE Accessible Registers O Receiver Buffer Register RBR Bit 0 7 Received data byte Read Only gt Transmitter Holding Register THR Bit 0 7 Transmitter holding data byte Write Only O IntemuptEnable Register IER Bit O Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Enable Received Data Available Intemupt ERBFI Enable Transmitter Holding Empty Interupt ETBEI Ena ble Receiver Line Status Intemupt ELSI Ena ble MODEM Status Inte rupt EDSSI Must be 0 Must be 0 Must be 0 Must be 0 O Intenupt Identification Register IIR Bit O Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 0 if Interupt Pending Interrupt ID Bit O Interupt ID Bit 1 Must be 0 Must be 0 Must be 0 Must be 0 Must be 0 FablATech Corporation gt Line Control Register LCR Bit 0 Word Length Select Bit O WLSO Bit 1 Word Length Select Bit 1 WLS1 Bit 2 Number of Stop Bit S
65. ssword function ispresent and isenabled Enter new supervisor password AMIBIOS HIFLEX SETUP UTILITY VERSION 1 16 C 1996 American Megatrends Inc All Rights Reserved Advanced Chipset Setup Peripheral Setup Auto Detect Hard Disks Enter new supervisor password Al Exit Without Saving Change the supervisor password Standard CMOS Setup Advanced CMOS Setup ESC Exit Tl Sel F2 F3 Color F10 Save amp Exit Figure 7 6 Enter New Super User Password 7 9 PASSWORD C HEC KING The password check option is enabled in Advanced Setup by choosing either Always the password prompt appears every time the system is powered on or Setup the password prompt appears only when BIOS is run The password is stored in CMOS RAM Usercan enter a password by typing on the keyboard As user select Supervisor or User The BIOS prompts for a password user must set the Supervisor password before user can set the User password Enter 1 6 character as password The password does not appear on the screen when typed Make sure you write it down 63 FablATech Corporation 7 10 LOAD DEFAULT SETTINGS It permits user to select a group of setting for all BIOS Setup options Not only can you use these fields to guickly set system configuration parameters you can choose a group of settings that have a better chance of working when the system is having configuration related problems 7 11 AUTO CONAGURATION WITH OPTIMAL SETTINGS Us
66. t and Pin Definitions J P2 J P3 When RS 485 mode is selected the RS 485 signals use the same connector as RS 232C J P2 isthe terminator on off jumper only when using RS 485 mode J P3 isused to set up the RS 232C and RS 485 forthe CN5 The following figure and table guide you how to set up RS 485 serial port J2 J3 JP CN4 On J5 J6 CN2 JP CN3 CN5 Signal DB9 1 E 1 gt JP4 S f 2 LM1LM2LM3LM4 3 485 2 Ce BEES i a 5 485 3 Vous M3 a nc M4 cNIO del ES 3 9 A ee a M imir ELAN gt gt Table 3 11 C N5 Pin Assignments RS 232C RS 485 TerminatorOff Terminator On Factory Preset Figure 3 13 J P2 and J P3 RS 485 Select 3 Extra RS 232C Header J 4 3 pin 2 0mm J ST Header 4 provides basic RS 232C signals of serial port 2 It is used to interface with touch screen module or other intemal connection usage J2 J3_ JP1 CN4 CN1 J5 J6 CNS Ji CN u Lo n PL Ss dem EE Ga ddaa DA ke E M1 LM1LM2LM3LM4 J 4 MUI m BB ez Ep Pin 1 TXD2 Wow Pin 2 RXD2 sm E 3 1 Pin 3 Ground M4 CN12 CN10 pap DB3 JP6 H E 7 i P CN8 Ja Leit H JP7 CN9 J9 lema
67. t your equipment from static discharge O Touch a grounded metal object to discharge the static electricity in your body or ideally weara grounded wrist strap O When unpacking and handling the board or other system components place all materials on an antic static surface o Be careful not to touch the components on the board especially the golden finger connectorson the bottom of every board Table of contents 1 1 INTRODUCTION ooo dea A NOVA Eu zda N ROA DOS RENA 1 1 2 SERIES COMPARISON RT 1 1 3 FEATURES a a aaa 2 1 4 PACKING Sii lid 3 2 1 O OT 5 2 2 DMA CONIROUER oia adidas 5 2 3 KEYBOARD CONTROLLER maaa dit 6 2 4 INTERRUPTEONIROLLER iii lead de ao te od a dr ba ak ad dr ar 6 241 MO Pot Adde S MAD paa 7 2 4 2 Real Time Clock and Non Volatile BAM een 8 ZAZ let EE 8 2 5 SERIALZ PO RTS ee 9 2 6 TR ON e Agsartsntanen a E E E 11 3 1 BOARD OMERV IEW aida cumussubterwedeaceaastit deve EE Ps dt d dan 15 3 2 INDEX TO J UMPERS 6 CONNECTORS ronnan aana E a RA EA 16 33 SYSTEM SETTING ere A O id 16 3 3 1 Keyboard Mouse Connector CN11 EJO NEEN 17 3 3 2 PC 104 Connector CN10 GNOD een 20 3 3 3 Hard Disk IDE Connector CN 3 3 34 Rest Header 3 EE 24 335 ParallelPort Connector CNJ idad 24 3 3 6 Auxiliary Power Connectors J 8 amp J5 for standalone application u 25 334 MEVO Connector C NO Zeus EE eege 26 3 3 8 Se al EI EAE TEE A A EE EAE 26 339 RAS Connector CNT aia e 28 3 3 10 CN12 C
68. ta memory operation 1016 Input Open collector The I O Chip Select 16 indicates that the present data transfer is a 1 wait OSC Output The Oscillatorisa 14 31818 MHz signal ANS Input Open collector The Zero Wait State indicates to the microprocessor that the present bus cycle can be completed without inserting additional wait cycle Table 3 7 PC 104 ISA Pin Assignments state 16 bit data I O operation 22 FablATech Corporation 3 3 3 Hard Disk IDE Connector CN1 A 40 pin header type connector CN1 is provided to interface with up to two embedded hard disk drives IDE AT bus This interface through a 40 pin cable allows the userto connect up to two drives in a daisy chain fashion To enable or disable the hard disk controller please use BIOS Setup program to select The following table illustrates the pin assignments of the hard disk drive s 40 pin connector p N4 CN1 J5 J6 CN2 Ji CN3 s E J4 CN1 Hard disk connector dP Hl CNS D Bjoa B R ddd DEE e E d Mi LMILM2LM3LM4 mm p r J ppe 00000000000000000000 dt M2 00000000000000000000 x us CN7 40 2 swt F rr CN12 CN10 at DB3 JP6 a Se CNS 8 La ld 4P7 CN9 824 Jeun i Figure 3 7 CN1 Har
69. tchdog Timer are 76 77H The following introduces how to program the extemal Watchdog Timer DO D2 Watchdog Timer Setting D2 D1 DO Second 0 0 0 4 0 0 1 12 0 1 0 20 0 1 1 28 1 0 0 36 1 0 1 42 1 1 0 50 1 1 1 58 D3 D4 Watchdog Trigger Signals D3 D4 Signal 0 0 System Reset 0 1 1 0 IRO 15 1 1 IRO 11 D5 Watchdog Enabled Dis bled 0 Disa bled 1 Enabled D6 D7 Don t care 72 D1 SRAM MEMORY BANKS This provides the information about how to access the memory on the FB2300 The FB2300 hardware divides every 8K bytes of memory into a memory bank To access the data in the memory you have to assign a bank number The memory bank number starts from zero The last memory bank number depends on the size of the memory chip used on the FB2300 For example if you use the 128K bytes memory chip the bank number would be in the range of 0 to 15 If a SRAM isinstalled to the system of BIOS CMOS SETUP are determined by select 68h or 78h The I O port address of the bank select is base port 0 and the I O port address of the chip select is base port 2 The following isthe format of the chip select and bank enable Reamer vo Por D7 D6 D5 D4 03 02 01 007 a Pe O K M NN Where WPE Write protect enable bit A6 A0 Bank select bits AO is the LSB CS1 CS0 Chip select bitsof MEM1 to MEM3 Where CS1 CS0 Chip select F
70. the FB2300 31 FablATech Corporation 4 2 SWITCH SETTINGS The following shows the locations of the FB2300 switch and the factory default settings CAUTION The switch setting needsto adjust with the jumpers setting make sure the jumper settings and the switch setting are correct J2 JD JP CNA CN J5 J6 CN2 J7 CN 1 2 3 4 Figure 6 1 Switch amp SSD Type J umper Location 32 FablATech Corporation 4 2 1 Overview There isa DIP Switch on the FB2300 It performsthe following functions These functions ma y be required to perform with relevantjumpers Detailed settings will be specified latter Switch 1 1 1 2 JP4 Set the SSD and DOC mapping Switch 1 3 JM1toJM4 SSD type select Switc h 1 4 SSD drive select ON OFF 1 2 3 4 Figure 4 1 SWL Switch Select Note If EPROM generated utility is required please contact us 4 2 2 the solid sta te disk JP4 SSD Mapping SSD and DOC Mapping Address Setting Switch 1 1 1 2 J P4 Switch 1 1 1 2 and J P4 are provided to select the base port addresses forthe DiskOnChip and DOC Mapping Disa ble C 800 0 8KBytes Disa bled Disa ble CC 00 0 8KBytes Disa bled Disa ble D000 0 8KBytes Disa bled Disa ble D800 0 8KBytes Disa bled Enable C 800 0 8KBytes CA00 0 8KBytes Enable CC 00 0 8KBytes CE00 0 8KBytes Enable D000 0 8KBytes D200 0 8KByte
71. tory Preset Figure 3 3 J 9 6 Pin J ST Keyboard Connector An Signal 3 4 6 Keyboard Clock Table 3 3 J 9 Pin Assignments 18 FablATech Corporation CN2 34 pin 2 54mm IDC Hoppy Connector One 34 pin floppy drive interface cable is provided to connect to the floppy drive device 4 o A M2 DB1 JE 2 M swt CN12 CN10 f DB3 JP6 HE 4 cns JP7 m ONS JO on EL CN2 Hoppy connector 33 1 34 2 Figure 3 4 CN2 Hoppy Connector Signal Signal No Connection Drive Enable A Write Data Index Ground Ground Head MotorB Read Data Ground Track 0 Select A Write Enable Select B Ground MotorA Direction Write Protect Disk Change Step Ground Table 3 4 Hoppy Connector Pin Assignments Note the included floppy cable supports 720KB 1 44MB and 2 88MB floppy disk drives and these disk drives 360KB and 1 2MB disk drives are not supported 19 FablATech Corporation 3 3 2 PC 104 Connector CN10 CN9 1 64 Pin PC 104 Connector Bus A B CN10 J2 11 J3 J5 J7 CNS J6 CNS D JP1 CNA CN1 ol D D EST
72. ult setting Normal PS 2 Mouse Support The PS 2 mouse function is optional Before you configure this field make sure your FB2300 supports this feature The setting of Enabled allows the system to detect a PS 2 mouse on bootup If detected IRQ12 will be used for the PS 2 mouse IRO 12 will be reserved for expansion cards if a PS 2 mouse is not detected Disabled will reserve IRQ12 for expansion cardsand therefore the PSY 2 mouse will not function Available Options Disa bled Enabled Default setting Disa bled Typematic Rate This function specifiesthe keystroke repeat rate when a key is pressed and held down Available Options Fa st Slow Default setting Fa st System Keyboard This field specifies if an error message should be prompted when a keyboard is not attached Available Options Absent Present 56 Default setting Absent Primary Display The field specifiesthe type of monitor insta lled in the system Available Options Absent Normal Default setting Absent Password Check This field enables password checking every time the computeris powered on orevery time the BIOS Setup isexecuted If Always is chosen a user password prompt appears every time and the BIOS Setup Program executes and the computer is tumed on If Setup is chosen the password prompt appearsif the BIOS executed Available Options Setup Always Default setting Setup Wait for EU If Enor AMIBIOS POSTenor messagesare followed by Press lt F1 gt to co
73. ut period watchdog timer User can use the program to enable the watchdog timer Once you have enabled the watchdog timer the program should trigger it every time before it times out If your program fails to trigger or disa ble this timer before it times out because of system hang up it will generate a reset signal to reset the system or trigger an IRQ signal The time out period can be programmed to be 30 5 u secondsto 512 seconds Software Program i Time Base Enable and Trigger Watchdog Register Counter Write and Trigger and 7 Compartor RESET Figure 6 1 Watchdog Block Diagram 6 3 1 Watchdog Timer Setting The watchdog timer is a circuit that may be used from your program software to detect crashes or hang ups The watchdog timer is automatically disabled after reset Once you have enabled the watchdog timer your program must trigger the watchdog timer every time before it times out After you trigger the watchdog timer it will be set to zero and start to count again If your program fails to tigger the watchdog timer before time out it will generate a reset pulse to reset the system or trigger an IRQ signal to tell your program that the watchdog istimes out Watchdog timer INDEX 39H 3AH and 3BH 3Bh 3Ah 39h D7 DO D7 DO D7 DO Counter M S LSB For example INDEX 3Bh 3A 39h h 00h 00h O1h 30 5 sec 02h 61 usc 00h 0lh 00h 7 8 m sec 00h 02h 00h 15 6 m sec 01h 00h 00h 2 sec 02h 00h 00h 4 sec FFh FF
74. vta dva Deka ddd a da den 3 CHAPITER e da tt Gogha et podobe too ooo ok obyt othe SYSTEMCONTROLLERS 21 O AT 5 2 2 DMA CONTROLLER de 5 2 3 KEYBOARD CONTROLLER carita ii ti e dc Ee 6 2 4 INTERRUPTCO NIROLLER E 6 241 VO Pom AdGress Ma pz gesuegt 7 2 4 2 Real Time Clock and Non Volatile RAM ENEE 8 Z433 TME AA A a E ica 8 2 5 SERIAL PO Sica did A A Ee EE 9 2 6 PARALLEECPO TS EE 11 CHPIER Oo sc e oe ran re oe HARDWARE FEATURES 3 1 BOARD OVERVIEW kimin a aaa 15 3 2 INDEX TO J UMPERS 6 CONNECTORS Seud tuinra a a A A T ET a A A E AE 16 3 3 Kgl IER UE 16 3 3 1 Keyboard Mouse Connector CN11 8 1 9 ee eeeeeeeeeeeneee onen een nenene nenene neon 17 3 3 2 PC I04Connect or CNIS CNO viii iaa ida diia 20 3 3 3 Hard Disk IDE Connector CN 23 33 4 Reset Header lia ees eer eer EE 24 3 3 5 Parallel Port Connector CNB wee een 24 3 3 6 Auxiliary Power Connectors J 8 amp J 5 forstandalone application 25 3 3 7 TIO Connecton EN Dias dia 26 3 3 8 Sena en 26 SC MR TE elek rie Le RA 28 EKhlfleddhkifgelldTeredldi Oe EE 28 33 11 CPU B se C lock Select J P7 3 ssd dd 29 3 3 12 HDD J 2 and Power J 7 LED Indicators EEN 29 CAPER sins eet Nit Us Di SOLID STATE DISK 4 1 OVERVIEW aa ee 31 4 2 SWITCH SETTINGS Ai O O AE 32 421 EE 3 4 22 SSD and DOC Mapping Address Setting Switch 1 1 1 2 amp J PA 3 4 2 3 SSD Memory Type Select Switch 1 4 and J M1 to J MA ENEE A 4 3 PROGRAMMING EPRO M FLASH SR
75. with the setting function or you can contact the technical support engineer 2 If the BIOS losses setting the CMOS will detect the Auto Configuration with Fail Safe Settings gt to boot the operation system this option will reduce the performance of the system It is recommended to choose the lt Auto Configuration with Optimal Setting gt in the main menu The option is best case valuesthat should optimize system performance 3 The BIOS settings are described in detail in this section 52 7 2 STANDARD CMOS SETUP The lt Standard CMOS Setup gt option allows you to record some basic system hardware configuration set the system clock and error handling If the CPU board is already installed in a working system you will not need to select this option anymore AMIBIOS SETUP STANDARD CMOS SETUP C 1996 American Megatrends Inc All Rights Reserved Date mm dd yyyy Sun IE 63 2000 Base Memory KB Time hh mm ss 18 38 36 Extd Memory MB Floppy Drive A 1 44 MB 3 Floppy Drive B Not Installed LBA Blk PIO 32Bit Type Size Cyln Head WPcom Sec Mode Mode Mode Mode Pri Master Auto DEF Pri Slave uto off Sec Master Not Installed Sec Slave Not Installed Boot Sector Virus Protection Disabled Month Jan Dec ESC Exit Tl Sel Day 01 31 PqUp PgDn Modify Year 1901 2099 F F3 Color Figure 7 2 Standard CMOS Setup Date amp Time Setup Highlight the lt Date gt field and then pressthe P

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