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G9001A_G9002 User's Manual - Nippon Pulse Motor Taiwan

Contents

1. 1 25 Description 0001 0000 0000 0000 1000h System communication to all devices Polls all of the devices device Nos 0 to 63 one by one and refreshes the device information areas that correspond to each device number The device information contains the following Device in use 0 when no response and 1 when it responds Device type Reset to 1 when it is a data device I O setting information No response to a system communication is not treated an error However an error with a CRC mismatch may be possible 0001 0001 0000 0000 1100h System communication to all devices except those devices excluded from cyclic communication After checking the device information area the center device polls all the devices whose device in use bit is set to 0 one by one and refreshes the device information areas that correspond to each device number The details are refreshed the same as by writing a command 1000h No response to a system communication is not treated an error However an error with a CRC mismatch may be possible 0001 0010 OO 1200h to 123Fh System communication to specified devices The center device polls only the specified devices and refreshes the device information areas that correspond to each specified device number The details are refreshed the same as by writing a command 1000h No response to a system c
2. Conditions Results Transmission are of Cable Terminating Pulse I F chip Max rate devices used resistor transformer length 20 Mbps 32 CAT5 100 ohm 1000 uH RS485 100 m 20 Mbps 64 CAT5 100 ohm 1000 uH RS485 50 m 10 Mbps 64 CAT6 100 ohm 1000 uH RS485 100 m Note In the figures above the maximum length figures are results from ideal conditions in a laboratory In actual use the results may not be the same 2 1 Cable Commercially available LAN cables were used CAT5 Category 5 CAT6 Category 6 We used these LAN cables because they are high quality cheap and easy to obtain Lower quality cables such as cheap instrument cables may significantly reduce the effective total length of the line LAN cables normally consist of several pair of wires Make sure to use wires from the same pair for one set of communication lines Even when using cables with the same category and rating the performance of each cable manufacturer may be different Always use the highest quality cables in the same category 2 2 Terminating resistor Select resistors that match the impedance of the cable used Normally a 100 ohm resistor is recommended Therefore we used terminating resistors with this value Adjusting this resistor value may improve the transmission line quality 2 3 Pulse transformer We recommend using pulse transformers in order to isolate the GND of each local device By isolating the
3. toe acc I 11 4 4 6 RD WR AO and I 11 LE Rem TES I 11 Lcd EE l 11 4 4 A1 to ute E N E tee 1 11 E SHIP E l 11 4 4 11 D8 to DIS pannon niece Nee i ce 1 12 4 4 12 SPDO SPD ie dee odie de I 12 A213 SO Headed tds e erede e a e ee dd aes 1 12 4 4 14 50 50 pueda ed 1 12 4 4 15 51 e de o tide eoe t Avene e tes l 12 AANE AMOR Ean OEE EA AEE l 13 AAA eene E AEE AE EEE ENA EOE EEA AE EARS l 13 CE uii n 1 13 2419 M 1 13 4 5 Address map t tee 1 14 A S Device information AeA I 18 4 5 2 Cyclic communication area I 19 4 5 3 Change to Input Port Interrupt Setting 1 20 4 5 4 Change In Input Interrupt Flag 2 1 1 enne 1 21 4 5 5 POM Gala alea eoe poc inetd de aspe dun epe eu l 21 426 Em 1 22 427 Interrupt Status E EA eet eerte s ER ERO
4. Port 2 Port 1 This address also contains a change interrupt setting for parts of device Nos 5 and 6 In order to prevent problems with the settings for these parts it is better to read the address and then use a mask IV 7 example of how to use a mask to prevent corruption of the settings for device numbers 5 6 Read the current settings WORK Inpw 0x00C2h WORK WORK and Ox9FFEh WORK WORK or 0x6001h Outpw 0x00C2h WORK Specify the mask and port data to monitor In this case a logical AND process may not be needed Write 2 When using only the lower 8 bytes in the address map The center device details that can be seen from an external CPU are from the command area to the data transmission reception FIFOs Use commands to access other areas Specify the device data for device numbers 4 and 7 To set the data write the data to the I O buffer Then issue a write command to the target s device number area Outpw 0x0004h 0x6001h Outpw 0x0000h 0x5208h A write command is constructed as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 1 4 Specify the address here The lower 2 address bits are not used Leave them at 0 Positions marked with amp are not used Leave them at 0 IV 8 2 4 Check clear existing input change interrupts When the
5. Watchdog timer setting TMD ermine 20 Mbps 10Mbps 5Mbps 2 5 Mbps L 5 ms 10 ms 20 ms 40 ms H 20 ms 40 ms 80 ms 160 ms 11 9 4 4 10 4 4 11 4 4 12 4 4 13 4 4 14 4 4 15 4 4 16 4 4 17 TOUT Once the watchdog timer has timed out this terminal goes LOW SO Serial output signal for communication Positive logic tri state output SOEH SOEL Output enable signal for communication The difference between the SOEH and SOEL is that the logic is inverted When sending SOEH HIGH and ZSOEL LOW SOEI When using more than I O device connect the SOEH signal of the other I O device to this terminal By being wire OR ed with the output enable signal from this device the device outputs an enable signal to SOEH or SOEL SI Serial input signal for communication Positive logic MRER Monitor output used to check communication quality When the I O device receives an error frame such as a CRC error this terminal goes LOW for exactly 128 CLK cycles 3 2 us By timing this interval using a counter you can check the quality of the communication MSEL Communication status monitor output When the I O device receives a frame intended for this device and everything is normal when communication MFER is OFF this terminal goes LOW for exactly 128 CLK cycles 3 2 us This be used to check the cyclic communication time BRK By providing H
6. 6000h to 607Fh Read the device information area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 0001 O x xxxx 6100h to 617Fh 0110 0010 O 6200h to 627Fh Read the cyclic communication error flag area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device Read the input change interrupt setting area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used this device 0110 0 11 6300h to 637Fh Read the input change interrupt flag area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device 0110 0100 O 998 6400h to 647Fh Read the port data area The contents of the word in this area are copied to the I O buffer Use this function when you want to reduce the number of addresses used in this device Note For all bits marked with a the upper bits of the device address should be set in order starting from the left end of the bits For bits marked with an amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit
7. nnne 1 41 7 4 4 I F mode IF1 H 2 2 0 0600 000000 nnn nnnm 1 42 7 4 5 mode 2 IFA L IFO ED iiir reete rne e ta rene 1 43 7 4 6 I F mode 1 IF1 L 1 44 8 2 eee 1 45 ll 1699002 2 4 atender eta e ed ete dii DH a DR EARTH IHE AE DH IIo 11 1 jeje 11 3 2 hare ares 11 3 3 Basic specificatloris 5 ett tbe athleta tu i tia M Il 3 3 1 I O device specifications 59002 11 3 4 Hardware Description 11 4 4 15 List of terminals 80 uite ee dO ERR de Reed ede lee 11 4 4 2 Terminal assignment 11 6 4 3 Complete block diagratm 2 2 nine ene RE tenere e Eid e Re Echec eie 11 7 4 4 Functions Of termirials 3 eem re 1 8 iti hee te ean tih teneo E ite te ben od 1 8 4 4 2 HRS Migs ce test n imn estne mande 1 8 4 4 3 niunt een ete tie enr ae 1 8 424 4 HONO to PONG Tria e e rn ence inde eee Il 8 4 4 5 DNSM ient bt E NER ceo tein ae ay Il 9 424 6 HDNSQ itr a ee RE en eines Il 9 AAT SPDO0 SPDT onir A A EA eee ei ay Il 9 42423 LOD LEER
8. IV 16 2 9 Data communication 3 Start the PCL device G9x03 The data communication example below shows how to start pulse output by setting the registers in the PCL device G9x03 The local devices are the same as in the previous section Assume that the data to place in the PCL device G9x03 are as follows only the data needed to trigger the pulse output Register name Set value Remarks RFL 00000100h RFH 00000200h RMG 00C7h Multiplication rate 1 Outpw 0x0006h 0x0091h RFL setting Outpw 0x0006h 0x0100h Write a register write command and place the data in the Outpw 0x0006h 0x0000h FIFO Outpw 0x0000h 0x4028h Lastly issue a device communication command Dev Sts Inpw 0x0000h Check the EDTE bit to see if this data communication ended normally before starting the next data communication YES Error processing Outpw 0x0006h 0x0092h RFH setting Outpw 0x0006h 0x0200h Outpw 0x0006h 0x0000h Process the next set of data the same way Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Error processing IV 17 Outpw 0x0006h 0x0095h RMG setting Outpw 0x0006h 0x00C7h Outpw 0x0006h 0x0000h Outpw 0x0000h 0x4028h Dev_Sts Inpw 0x0000h Error processing Outpw 0x0006h 0x0051h Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Finally place a start command for the PCL device in the FIF
9. circuit System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A15 Connect these lines to the decoding circuit and use them to create the 5 signal to A2 Connect these lines to AO to A2 on the center device A3 to A8 on the center device should be pulled up 11 5 1 1 4 I F mode 1 IF1 L IFO L 68000 type CPU G9001A AS A9 to A23 GND System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows to A23 Connect these lines to the decoding circuit and use them to create the CS signal to A2 Connect these lines to AO to A2 on the center device A3 to A8 on the center device should be pulled up 6 1 1 5 Connecting to CPU without wait function The center device can be connected to a CPU that does not have a wait function Lets look at an example with the CPU interface using I F mode 4 while it is connected to an Intel 8031 8 bit CPU Since this CPU does not have a terminal for executing a wait function care is needed when programming CLK G9001A VDD 8031 intel A8 to A15 A9 to A15 P2 0 to 2 7 Decoding circuit ALE to A8 P0 0 to PO 7 lt gt DO to D7 RD WR System reset Points 1 Set IF1 H and IFO I F mode 4 2 Si
10. eau d be ees VII 3 24 4 RDJADD iro ec ete oe naw a seas edad a aa VII 3 2 4 5 RVER VII 3 I Center device G9001A User s Manual Outline This LSI is a center device of the Motionnet system It contains 256 byte RAM for controlling I O and 512 byte RAM for data communication and can control up to 64 local devices The local devices can be classified into devices G9002 that control input output signals such as G8014C on the T NET system and data device G9x03 G90044 that control by data such as G8015 It allocates device numbers from 0 to 63 for each local device One device G9002 has 4 ports 1 port 8 bits for input output select input output by terminals Therefore connecting all the local devices to the center device as I O device G9002 you can connect I Os of 2048 points 64 units x 4 ports x 8 bits 2048 by serial communication One data device G9x03 or G9004A can communicate max 256 bytes data maximum data length of the PCL device G9x03 will be 8 byte communication Suppose that all of the local devices connected to the center device as PCL devices G9x03 64 axes can be controlled by serial communication Features Maximum data transfer speed is 20 Mbps Transfer cycle time is less than 1 msec when 64 local devices are connected in case of cyclic communication only One center device can connect up to 256 ports 2048 bits for I O connection
11. Assume that the routine is started by an interrupt being issued INT LOW Sts Inpw 0x0000h Read the status data in the center device AL YES LOOP 0 WORK LOOP lt lt 3 Com 0x6300h or WORK Outpw 0x0000h Com Data Inpw 0x0004h Note 1 Shift the loop variable 3 bits left to create the read address Read the contents of the target address using the command that was just created NO The bit positions which are HIGH correspond to device Input change and port numbers whose input has changed YES Process specified by user In this step process all the flags that have become HIGH Process specified by the user the other flags do not need to be processed Write back the data you just read in order to clear the Com 0x5300h or WORK change interrupt flag Outpw 0x0004h Data Note that the command is different from the one used to read the data Outpw 0x0000h Com LOOP LOOP 1 N Note 2 2 LOOP lt 16 22 Although this example checks the interrupt flags on all the addresses by using loop processing you can check just Q YES the areas required End The read command is constructed as follows 15 14 13 1211110 9 8 7 6 5 4 3 2 1 0 011 1 0 0 0 1 1 8 When writing data used to Specify the address in these 8 bits clear the flags these bits The lower 2 bits of the address byte are not used Lea
12. IFO pull up or pull down with 5 to 10 K ohms resistor Use of one resistor for 8 lines is also available 4 4 12 SPDO SPD1 Specify communication speed with these terminals SPD1 SPDO Communication speed L L 2 5 Mbps L H 5 Mbps H L 10 Mbps H H 20 Mbps All of the devices on the communication line shall be set to the same speed Either 40 MHz or 80 MHz is connected to the clock signal as far as you do not mistake setting of the CKSL you can get communication speed of 20 Mbps 4 4 13 SO Serial output signal for communication Positive logic Connect this line to data input of a RS485 device 4 4 14 SOEH SOEL Output enable signal for communication Difference between SOEH and SOEL is that only logic is different When sending signals SOEH will become and SOEL will become L Connect either of needed signal to the data enabled input of a RS485 device 4 4 15 SIA SIB Serial input signals for communication Positive logic Basically these two are identical in functions Each of them can construct independent signal line as follows Line Transceiver Transformer Center Local Local Local device device device device Line Transformer Sip Transceiver Commonly using the serial output signal SO from the center device provide RS485 and pulse transformer individually for each line the signal line load can be decreased When connecting to m
13. Write Available 5 RD Negative Read Available 6 AO Positive Address bus bit 0 LSB Available 7 At Positive Address bus bit 1 Available 8 A2 Positive Address bus bit 2 Available 9 A3 Positive Address bus bit 3 Available 10 GND GND 11 4 Positive Address bus bit 4 Available 12 Positive Address bus bit 5 Available 13 A6 Positive Address bus bit 6 Available 14 A7 Positive Address bus bit 7 Available 15 A8 Positive Address bus bit 8 Available 16 VDD 3 3 V power input 17 DO B Positive Data bus bit 0 LSB Available 18 D1 B Positive Data bus bit 1 Available 19 D2 B Positive Data bus bit 2 Available 20 D3 B Positive Data bus bit 3 Available 21 GND GND 22 D4 B Positive Data bus bit 4 Available 23 D5 B Positive Data bus bit 5 Available 24 D6 B Positive Data bus bit 6 Available 25 D7 B Positive Data bus bit 7 Available 26 VDD 3 3 V power input 27 D8 B Positive Data bus bit 8 Available 28 09 B Positive Data bus bit 9 Available 29 D10 B Positive Data bus bit 10 Available 30 D11 B Positive Data bus bit 11 Available 31 GND GND 32 D12 B Positive Data bus bit 12 Available 33 D13 B Positive Data bus bit 13 Available 34 014 B Positive Data bus bit 14 Available 35 D15 B Positive Data bus bit 15 Available 36 VDD 3 3 V power input 37 INT O Negative Interrupt request Available 38 WRQ O Negative Wait
14. Data float delay time for RD 7 Troup CL 40pF 28 ns WR signal width Twr Note6 14 ns Data setup time for WR 7 22 5 Data hold time for WR 7 Tap 0 ns Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or HIGH the 2WRQ signal LOW level will be held for 24 x Note 3 When CKSL LOW CKSL HIGH the data output delay time will be 4 24 Note 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until 2WR goes HIGH 1 43 7 4 6 I F mode 1 IF1 L IFO L 16 bit 68000 etc Read cycle A 8 1 4 pum Tscs 15 0 ose Sow R W WR E Tous D 15 0 Tsup Write cycle A 8 1 4 N LS A0 Tsrw R W WR NEEBEPFENN 0 15 0 84 Item Symbol Condition Min Max Unit Address setup time for LS Ths 17 ns Address hold time for LS 7 Tea 0 5 CS setup time for LS 4 T s 10 ns CS hold time for LS 7 Tee 0 ns R W setup time for LS 4 Trws 2 5 R W hold time for LS Tsrw 14 ns C 40 Note 1 2 1476 1 5 ns ACK ON del for L CK ON delay time for LS 4
15. 2 4 10100000 140h Cyclic communication errorflags Cyclic communication error flags Device Device No 48 to 63 No 48 to 63 10011 111 13Eh Input change interrupt settings Device No Input change interrupt settings Device No TEE EE EROS DIOS noe e op d rut i E CE 10010000 120 Input change interrupt settings Device No Input change interrupt settings Device No 60 to 63 60 to 63 1 0001111 11Eh Input change interrupt flags Device 0 Input change interrupt flags Device No 0 foll lis ENTE MEER PETERE PRU 10000000 100h Input change interrupt flags Device 60 Input change interrupt flags Device No 60 to 63 to 63 01111111 OFEh Port data No 0 1 Device No 0 Port 0 1 Port data No 0 1 Device No 0 Port 0 1 _ 01111110 OFCh Port data No 2 Device No 0 Port 2 3 Port data 2 3 Device No 0 Port 2 3 _ 00000001 002h Port data 252 253 Device 63 Port data No 252 253 Device No 63 Port axes aca POLLO A a ak aaa toe ested Und LEE 0 0000 000 000h Port No 254 255 Device No 63 Port 2 3 Port data No 254 255 Device No 63 Port 2 3 Note The hexadecimal notation for the addresses above are written with the assumption that AO 0 17 Note The discussion of address maps below largely concerns I F mode 4 5 1
16. 5 V interface 46 P32 B Bit 2 on port 3 Available 47 P33 B Bit 3 on port 3 Available 48 P34 B Bit 4 on port 3 Available 49 P35 B Bit 5 on port 3 Available 50 P36 B Bit 6 on port 3 Available 51 P37 B Bit 7 on port 3 Available 52 GND GND 53 VDD Power source 3 3 V 54 PON ie Sets P20 to P27 to use negative Available 55 P3N a Sets P30 to P37 to use negative Available 56 SOEI Positive Enables serial output 57 BRK Positive Requests a break frame to be sent Available 58 RST Negative Reset Available 59 DNSM Mode to set the device number Available 60 5 Negative Serial output of next chip device number 61 GND GND from the power supply 62 CKSL Select clock rate L 40 MHz 80 MHz Available 63 VDD Power source 3 3 V 64 GND GND 65 PMDO Selects input output port mode 0 Available 66 PMD1 Selects input output port mode 1 Available 67 PMD2 Selects input output port mode 2 Available 68 SPDO Selects communication speed 0 Available 69 SPD1 Selects communication speed 1 Available 70 VDD Power source 3 3 V 71 GND GND 72 CLK Reference clock 73 VDD Power source 3 3 V 74 GND GND 75 DN5 Negative Device number bit 5 Available 76 Negative Device number bit 4 Available 77 DN3 Negative Device number bit 3 Available 78 DN2 Negative Device n
17. DN 5 0 000000 is 00h In the case that a continuous address by DNSO signal is set it is necessary at least approximately 50 us until the next step address is confirmed 4 4 7 SPDO SPD1 Set the communications speed All of the devices on the same communication line must be set to the same speed SPD1 SPDO Communication speed L L 2 5 Mbps L H 5 Mbps H L 10 Mbps H H 20 Mbps 4 4 8 TUD A watchdog timer is included on the chip to assist in administration of the communication status see the terminal section When the data transmission interval from a center device to this device exceeds the set time the watchdog timer times out This terminal is used to set output conditions when the watchdog timer times out When HIGH The LSI keeps its current status When the TUD LOW LSI is Reset 4 4 9 TMD Specify the time for the watchdog timer The watchdog timer is used to administer the communication status When the interval between data packets sent from a center device is longer than the specified interval the watchdog timer times out the timer restarts its count at the end of each data packet received from a center device The time out may occur because of a problem on the communication circuit such as disconnection or simply because the center device has stopped communicating The time used by the watchdog timer varies with communication speed selected
18. Device information area With system communication the center device polls all local devices from device 0 to 63 According to the response from local devices the center device can confirm the connection status device type settings for the I O port on each local device and refresh its own device information area When a CPU knows the device information the center device can write to it 8 bits of device information are required for each device 765 43210 0 0 0 Device information setting Set value Porto Porti Port2 PMD2 PMD1 PMDO 000 Output Output Output Output L L L 001 Input Output Output Output L L H 010 Input Input Output Output L H L 011 Input Input Input Output L H H Other than the Input Input Input Input Other than the above above When a local device is a data device G9x03 G90044 the port used to exchange data status or general purpose ports have a different meaning for each device Device type 0 VO device 1 Data device Use of device 0 Do not use 1 Used Ex To get device information for device Nos 0 and 1 access address 078h For a 16 bit CPU address 078h 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 P Device No 1 Device No 0 1 18 4 5 2 Cyclic communication area flags The
19. GNDs the system will have greater resistance to electrical noise If pulse transformers are not used the transmission distance may be less We used 1000 uH transformers in our experiments 2 4 I F chip We selected I C chips with specifications better than the RS485 standard In the experiment we used 5 V line transceivers When 5 V line transceivers are used level shifters are needed to make the connections 1 18 2 5 Parts used in our experiments Show below is a list of the parts used in the interface circuits of our experiments Use of other parts may change the system s response This list is only for your reference Parts Manufacturer Model name CAT5 Oki Wire Co Ltd F DTI C5 SLA CAT6 Oki Wire Co Ltd DTI C6X Pulse transformer Nippon Pulse Motor Co Ltd NPT102F Line transceiver TEXAS INSTRUMENTS SN75LBC180AP Level shifter TEXAS INSTRUMENTS SN74LVC244ADB 2 6 Other precautions Cables When you are planning long distance transmission cable quality will be the single most important factor Specialized cables designed for use as field buses such as those by CC Link and LONWORKS have guaranteed quality and may be easier to use Pulse transformers Needless to say the pulse transformers should handle 20 Mbps 10 MHz without becoming saturated The transformer s inductance is also important Since up to 64 pulse transformers may be connected the actual working specificat
20. Il 9 4 4 9 TMD a LEER Il 9 AO ALOUD iiic R E a in eae oe eae a 11 10 44 11 5 Qi iie meets mtt etim rete icti cate 1 10 4 4 12 OEH FSOEL ih e deir t e EE eee 11 10 424 13 S OBL x dide Soviets eave eet e ter ete ent 11 10 1 10 424 15 AMRER tb prenne te ER c ee c eit 11 10 4 4 10 S MSEBL iren e en a e 11 10 BoA ae BRK 11 10 4 4 18 5 2 11 11 4 4 19 2 P3N HERE RR DERE Ms 11 11 4 4 20 POO to 07 P10 to 17 P20 to 27 P30 to mee 11 11 4 5 Status after eset e eate baa 11 11 5 Electrical Characteristics 1 12 5 1 Er e P 11 12 5 2 Recommended operating 24000 0 ene 11 12 9 2 DG Characteristics mt HEN PR RU DH RE TERI Ind 11 12 5 4 AG CharaCtenStiGs 2 tette EUH aim 11 13 5 4 1 System dock iioii oed due duh Leeds 11 13 5 4 2 Reset tIMING P e ines ee 11 13 5 4 3 Fixed output data 0 ener nnns 11 14 5 4 4 Input data set tim
21. No 62 63 Cyclic communication error flags Device Cyclic communication error flags Device No 48 to 63 Input change interrupt settings Device No Input change interrupt settings Device No Input change interrupt settings Device No 60 to 63 Input change interrupt flags Device No 0 Input change interrupt flags Device No 0 Input change interrupt flags Device No 60 to 63 1 0000 000 Port data No 254 255 Device No 63 Port 2 3 Note The hexadecimal notation for the addresses above are written with the assumption that AO 0 l 16 Address 3 I F mode 1 2 1 to A8 Writing Reading 11111111 1FFh Command bits 0 to 15 Status bits 0 to 15 11111110 1FCh Invalid Interrupt status bits 0 to 15 1 1111 101 1FAh Input output buffer bits O to 15 Input output buffer bits O to 15 1 1111 100 1F8h Data transfer FIFO bits 0 to 15 Data receiving FIFO bits 8 to 15 1 1111 011 1F6h Not defined 56 words Not defined 56 words 1 1000 100 18gn Any data written here will be ignored Always read as 00h 11000011 186h Device information Device 0 1 Device information Device No 0 1 10100100 148h Device information Device 62 63 Device information Device No 62 63 __ 10100 011 146h Cyclic communication error flags Cyclic communication error flags Device REDUCE LNs Melly Device No 0 to 15 00 NO O t0 15
22. RO 1000 uH 2 Note 2 Serial line 2 B Note 1 When connecting the serial lines to line transceivers make the path as short and straight as possible Serial line 1 and serial line 2 are identical except for their serial signal input terminals on the center device SIA and SIB In order not to load the lines too heavily two identical line inputs are provided If there are only a few local devices and the serial line is relatively short a single one of the input lines named above will be enough to maintain a reliable signal If you will not be using one or the other of the two inputs SIA or SIB connect the unused terminal SIA or SIB to VDD or GND Note 1 When connecting the serial lines to line transceivers make the path as short and straight as possible Running these lines on a PC board could deteriorate the communication performance Note 2 Pull down resistors to GND should be 5 to 10 k ohms 13 1 4 Line transceivers and pulse transformers for local devices Use RS 485 line transceivers and pulse transformers 1000 uH or equivalent to make serial communication connections Connect the line transceivers as shown below Connect terminating resistors which match the cable impedance at both ends of the transmission line The terminating resistors can be either before or after the pulse transformer The same effect will be obtained at either position When using 5 V line driver receiver ICs such as a l
23. The center device will generate a no response error in this case and retry the communication An example of how to write the data 01234567h to the RMV the feed amount register in a PCL device G9x03 When using a 16 bit CPU 1 First write an RMV write command 0090h to the transmitting FIFO 006h 2 Next write the lower 16 bits data 4567h for the RMV register into the transmitting FIFO 006h 3 Finally write the upper 16 bits data 0123h to be sent to the RMV register into the transmitting FIFO 006h Details of the data transmitting FIFO 1st word 0090h 2nd word 4567h 3rd word 0123h When using an 8 bit CPU 1 First write the lower half of the RMV write command 90h to the transmitting FIFO 006h 2 Then write the upper half 00h of the RMV write command to the transmitting FIFO 007h 3 Next write bits O to 7 67h for the RMV register into the transmitting FIFO 006h 4 Next write bits 8 to 15 45h intended for the RMV register into the transmitting FIFO 007h 5 Next write bits 16 to 23 23h to be sent to the RMV register into the transmitting FIFO 006h 6 Finally write bits 24 to 31 01h for the RMV register into the transmitting FIFO 007h Details of the data transmitting FIFO 1st byte 90h 2nd byte 00h 3rd byte 67h 4th byte 45h bth byte 23h 6th byte 01h 1 33 5 1 3 Input change interrupt 5 1 4 5 1 5 When the status o
24. The center device provides input interrupt function to a CPU Local devices are classified into the following devices device dedicated to control I O port G9002 PCL device to generate pulse strings G9x03 CPU emulation device to control data communication between CPUs and other peripheral equipment G9004A Local devices are allocated device numbers 0 to 63 with hardware These device numbers can be assigned at random in a Motionnet system Further by system communication device numbers can automatically be allocated The center device is integrated with a memory for I O ports Thus the center device can operate I O status just like accessing normal memories The center device is integrated with four types of CPU I F circuits Z80 8086 H8 68000 etc As it applies for typical CPU interfaces it will offer wide possibility to interface with a variety of CPUs The center device normally uses 512 bytes area as address area However if resource is shorted it can use 8 byte areas Input 3 3 V single power as power supply However the major terminals can be connected to devices that run with 5 V 3 General specifications 3 1 Communication system specifications Item Description Reference clock Note 1 40 MHz or 80 MHz Communication speed Note 2 2 5M 5 M 10 M or 20 Mbps Communication sign NRZ sign Communication protocol NPM original method Communication method H
25. center device communicates with all the I O ports using cyclic communication In this type of cyclic communication if a communication error occurs for a specific device G9002 on three consecutive communication cycles the center device will treat this as cyclic communication error When this error occurs the bit in this area corresponding to the device number will become 1 By checking these bits you can identify the device G9002 in error Ex When reading address 0 8 For a 16 bit CPU address 0 8 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 N Error on device number 15 Error on device number As seen above the lowest bit shows the error status of the local device with the lowest address number By reading OB8h local device numbers from 0 to 15 can be checked In the same way by reading BAh you can check device numbers 16 to 31 To determine the address proceed as follows discard any remainder Address 0B8h Device No 8 For an 8 bit CPU Address 0 8 7 6 5 4 3 2 1 0 Error on device number 7 Error on device number The bits are read in groups of 8 by an 8 bit CPU but the meaning of each bit is the same The device number refers to the number allocated to each local device The numbers are specified on the external terminals on local devices Duplicate use of the same number is prohibited To
26. connecting more than one oscillator the duty will not be ideal In this case select 80 MHz The center device divides the frequency inside and creates 40 MHz frequency If you do not want 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI RST This is an input terminal for a reset signal By inputting an L level signal the center device is reset As the center device synchronizes with a clock arrange a circuit so that it does not disconnect the clock while resetting Reset signal length longer than 10 clock cycles is required CKSL Use to select clock rate L Connect 40 MHz clock frequency to the CLK terminal H Connect 80 MHz clock frequency to the CLK terminal Select this when the duty of the 40 MHz clock collapses too much 1 10 4 4 4 4 4 5 4 4 6 4 4 7 4 4 8 4 4 9 IFO Specify CPU I F mode Set status CPU signal to connect to terminals Example I F mode RD WR AO WRQ IFO i i of CPU terminal terminal terminal terminal L L I F mode 1 VDD R W LDS DTACK 68000 L H I F mode 2 RD HWR VDD WAIT H8 H L I F mode RD WR GND READY 8086 H H I F mode 4 RD WR AO WAIT Z80 This LSI has the following four interface modes The above four CPUs are typical ones among CPUs currently available on the market Even if a CPU you are examining is other than the above CPUs most of the CPUs can be connected using either
27. cyclic communication error occurs and the center device sets the cyclic communication error flag bit that corresponds to the device number to 1 Also when bit 3 in the RENVO register is 0 the center device outputs an interrupt request to the CPU 1 34 The CPU checks the existence of a cyclic communication error interrupt EIOE 1 in the status register when an interrupt occurs and then reads the cyclic communication error flags to see which I O device G9002 has an error By writing back the flag data just read the interrupt is reset If needed the device with an error can be excluded from further cyclic communication by software processing in the CPU 2 Data communication errors When data communications from the center device fail it automatically retries the communication three times If it fails all three times a data communication error occurs and the center device sets the status register data communication error bit EDTE to 1 It stores the device number which has the error EDNO to 5 in the interrupt status register And when bit 4 in the RENVO register is 0 it outputs an interrupt request to the CPU The CPU checks the data communication error interrupt status when an interrupt occurs and then reads the interrupt status bits EDNO to 5 to determine which device has an error and whether the local device received data or not LNRV Shown below is a detailed description of the LNRV bit and examples of how to h
28. deb yx CR 1 24 possnnt 1 25 4 8 1 ere Pre rn terae RR LEE ARR Eara se E a a abaa ae E ee Seen I 25 4 8 2 Memory access 1 28 4 8 3 Register access 1 29 CM Lem 30 4 9 1 RENVO TOgISIGE creen rrt I 30 4 9 2 I 31 4 9 3 iiem 1 31 9 4 RDJADD ceto tenter ee e b es Ee ERE l 31 4 4 09 55 A EAE 1 31 5 Descriptionofthie SOftWare ee det dca 1 32 5 1 Qutline of control 1 32 5 1 1 Communication I 32 9 1 2 Communication 2 2 inen visit e eate sog dde ee lt ng en d Ue l 32 5 1 3 Input change iriterr pt uite reden CERE a n RR ER eas kae nha Dre 1 34 b 1 4 Break f hctlonoca 2i dte Ed paca casa desk ortu 1 34 5 1 5 Control of communication 1 34 5 2 Operating 1 37 E E 1 37 5 2 2 Cyclic communication procedures l 37 5 2 3 Data communica
29. interval of 8 reference CLK cycles at 40 MHz before the data can be read by the CPU When reading data from the I O buffer there is no restriction on the timing It can be read in any order Read commands must be written low bit to high bit order When the WRQ terminal is connected to the wait terminal on the CPU the timing is controlled automatically by the CPU s wait control function Read data from the memory Next operation Address CS WR Ld DATA CGommand A wait of 8 clock cycles at 40 MHz 11 12 1 3 Line transceiver and pulse transformer for the center device To make connections for serial communication use RS 485 line transceivers driver receiver and pulse transformers 1000 pH or equivalent Connect the line transceivers as shown below On a transmission line connect terminating resistors suitable for the cable impedance 100 ohms or similar The position of the terminating resistor can be either before or after the pulse transformer The same effect will be obtained at either position When using a 5 V line driver receiver ICs such as a level shifter are needed to assert signals on lines such as SO SOEH and SI Line transceiver 3 3 V DI DE RO Pulse transformer Terminating resistor 1000 uH Y or Z pq equivalent a A Serial line 1 B Center device x Line transceiver 3 3 V DI DE Pulse transformer Terminating resistor
30. lower 8 bytes in the address map Outpw 0x0004h 0x1200h Put the data in the I O buffer and issue a write command Outpw 0x0000h 0x5404h Outpw 0x0004h 0x5634h Outpw 0x0000h 0x5405h In order to read port 0 on device number 2 and then Outpw 0x0000h 0x6404h read the I O buffer Data Inpw 0x0004h Discard the upper 8 bits Issue a read command to read port 0 on device number Outpw 0x0000h 0x640Ah 5 and then read the I O buffer Sts Inpw 0x1140h read command is constructed as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 1 10 111 10 1110 0 10 6 Specify the address here When accessing ports 0 and 1 0 When accessing ports 2 and 3 1 A write command is constructed as follows 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 11110 0 11 O 1 Specify the address here IV 14 2 7 Data communication 1 Put the value in the register of the PCL device G9x03 The data communication example below shows data being placed in a register that is integrated in the PCL device G9x03 Assume that the local devices to be used are as follows Assume that 00123456h will be placed in the RMV register of the PCL device G9x03 Device type Configuration item Device number PCL device Device address 40 28h Store the data in the receiving
31. of the interfaces above For details see the hardware specification sheets of the CPU you are planning to use and check with which mode you can connect Note The classification of the CPU interface modes above is applicable only for the center device The CPU emulation device G9004A also has unique CPU interface modes Mode classification of this is different than the above CS Input L level signal to this terminal when accessing this LSI RD WR 0 and WRQ Connect I F signals with a CPU Input signals vary with setting of the IFO to 1 For the details see items IFO and IF 1 INT Outputs an interrupt request signal When not using this terminal keep this terminal open IFB Use this terminal when connecting with a CPU having no wait control input terminal By reading a command from a CPU this signal becomes L level When the command process is complete this signal returns to H level After confirming that this terminal is H level access the center device A1 to A8 Enter address signal to these terminals When the is L address bus A1 to 8 are inverted inside When to control at 8 byte area process as follows terminal status A 8 3 process Remarks L Pull up set to H I F mode 1 2 H GND set to L I F mode 3 4 4 4 10 DO to D7 Connect lower 8 bits of the data bus 1 11 4 4 11 D8 to D15 Connect upper 8 bits of the data bus When used as I F mode 4 IF1
32. or superheated air reflow make sure to observe the following conditions and do not reflow more than two times Temperature profile The temperature profile of an infrared reflow furnace must be within the range shown in the figure below The temperatures shown are the temperature at the surface of the plastic package Maximum temperature The maximum allowable temperature at the surface of the plastic package is 260 C peak A profile The temperature must not exceed 250 C A profile for more than 10 seconds In order to decrease the heat stress load on the packages keep the temperature as low as possible and as short as possible while maintaining the proper conditions for soldering Package body temperature C Max peak temperature 260 C repie eap Aa E ESS Less than 10 seconds at 250 C Preliminary i heating Main heating 140 to 200 C 220 C or higher 60 120 sec Less than 35sec A profile applied to lead free soldering 4 Solder dipping causes rapid temperature changes in the packages and may damage the devices Therefore do not use this method VI 2 3 2 I O device G9002 1 In order to prevent damage caused by static electricity pay attention to the following Make sure to ground all equipment tools and jigs that are present at the work site Ground the work desk surface using a conductive mat or similar apparatu
33. see the CLK section of the Terminal Function in this manual 2 When setting CKSL H Item Symbol Min Max Unit Frequency 80 2 12 5 ns HIGH duration ns LOW duration ns 5 4 2 Reset timing RST amm m Internal RST Item Symbol Min Max Unit Reset length Twnsn 10 Clock cycles Delay time 10 Clock cycles Note 1 After the internal RST goes LOW the I O device G9002 will be ready Note 2 The reset signal must last at least 10 cycles of the system clock While resetting make sure the clock signal is continuously available to the device If the clock is stopped while resetting the device cannot be reset normally 1 13 5 4 3 5 4 4 Fixed output data timing 7 0 Refreshed output data The I O device refreshes the received data while the output signal MSEL is LOW indicates that the data was successfully received The refresh timing will be slightly advanced or delayed depending on the data receive timing of the center device G9001A However when MSEL changes from LOW to HIGH the I O device must have already read the received data Therefore if you want to use the received data by another external device take out the data during MSEL is HIGH so that you can get reliable data Input data set timing MSEL Internal register
34. sources that generate large voltage surges and take appropriate precautions against static electricity 4 Provide external circuit protection components so that overvoltages caused by noise voltage surges or static electricity are not fed to the LSI 2 Precautions for transporting and storing 515 1 Always handle LSls carefully and keep them in their packages Throwing or dropping LSIs may damage them 2 Do not store LSls in a location exposed to water droplets or direct sunlight 3 Do not store the LSI in a location where corrosive gases are present or in excessively dusty environments 4 Store the LSls in an anti static storage container and make sure that no physical load is placed on the LSls VI 1 3 Precautions for mounting 3 1 About the center device G9001A 1 Plastic packages absorb moisture easily Even if they are stored indoors they will absorb moisture as time passes Putting the packages in to a solder reflow furnace while they contain moisture may cause cracks in plastic case or deteriorate the bonding between the plastic case and the frame The storage warranty period is one year as long as the moisture barrier bags are not opened 2 If you are worried about moisture absorption dry the chip packages thoroughly before reflowing the solder Dry the packages for 20 to 36 hours at 125 5 C The packages should not be dried more than two times 3 To heat the entire package for soldering such as infrared
35. te VI 1 t Design precautioris etre indere educ eue ea eda a ee ec a eed tends VI 1 2 Precautions for transporting and storing 18515 nennen nnns VI 1 3 Precautions for mounting 4i titii reo i deett der e ba er adc nl eee bae dines baat ee VI 2 3 1 About the center device G90014 sssssssssssse eene nennen eene ener nenne VI 2 3 2 O device 59002 iint nt o unt uere E gunt cea aces eevee S dd ees VI 3 A Other precautions tado tute Lee ga tee th eere deti ede Ta Puede VI 4 VII Differences between the G9001 and 9001 VII 1 1 How to distinguish between the G9001 and G9001A using a Vil 1 2 Newly added functions the 6900 VII 1 2 1 Malri status 55 oe re meae etin nemine inu tameii aa oi VII 1 2 2 Operation comrmiands ui eto do Eee tee eode teu eti e iau aea VII 1 2 3 Register access command eee eee eo oe ree eee eue ne edid VII 2 MICE VII 2 2 4 1 RENVO register ed eec eed evs eed aee et aede d Boe ev mide hue e ke VII 2 2 4 2 RERON Tue iUe ttd et eu ed e bal a a o e iU a e es VII 3 2 4 3 RSY ONT tief eU uu de va edet eee edad o
36. the address map in the center device The lowest bit is fixed to 0 Data Data to write 16 bits Return value None 2 Read command from the center device Inpw Address Address Value corresponding to the address map in the center device The lowest bit is fixed to 0 Return value Read data 16 bits IV 3 2 Software Examples 2 1 Start of the simplest cyclic communication The simplest example is to issue a system communication command let the center device automatically collect data from the local devices and then start cyclic communication Send a system communication command to all local devices Outpw 0x0000h 0x1000h Sts Inpw 0x0000h Waits for completion of the system lt lt communication Without a completion signal the center YES Outpw 0x0000h 0x3000h Read status device cannot start the next operation Start cyclic communication Note Unless otherwise specified the flow charts shown in this manual omit the steps needed to process errors Be aware that when actually creating programs you will have to add steps for processing errors We recommend creating the steps used to check errors after reading the status register IV 4 2 2 center device specifies the data for the local devices that are connected This method assumes that the data for the local devices is already known and this data is manually specified in the address map
37. to ease the thermal stress on the 5 5 shed se reso gt Product flow direction Far infrared heater pre heater Mid infrared heater reflow heater Package and substrate surface temperatures must never exceed 260 C and 230 C for 30 to 50 seconds Temperature C DU ee Se 2 230 190 rere A 180 60 to 120 seconds 35 to 50 seconds i 4 Recommended temperature profile of a far infrared heater hot air reflow 7 When using hot air for solder reflow the restrictions are the same as for infrared reflow equipment 8 If you will use a soldering iron the temperature at the leads must not be 260 C or less for more than 10 seconds and must not be 350 C or less for more than 3 seconds VI 3 4 Other precautions 1 When the LSI will be used in poor environments high humidity corrosive gases or excessive amounts of dust we recommend applying a moisture prevention coating 2 The package resin is made of fire retardant material however it can burn When baked or burned it may generate gases or fire Do not use it near ignition sources or flammable objects 3 This LSI is designed for use in commercial apparatus office machines communication equipment measuring equipment and household appliances If you use it in any device that may require high quality and reliability or where fault
38. until the next time an error occurs Code Error conditions 0001 I O setting information in the device information area in the center device is not identical to the I O port combination specified using the PMD terminal on the local device 0010 An I O device G9002 received a data communication frame 0011 Adata device received frames larger than the receiving buffer capacity of the data device 15 8 to 11 ERAO to 3 If the CPU tries to access the G90014 illegally it will store one of the following codes in these bits The code is stored until the next time an error occurs Code Error conditions 0001 The CPU tried to write a cyclic communication start command but the number of devices used was set to zero 0010 Tried to write a start sending command without putting any data in the data sending FIFO 12t015 CAEO0t03 0011 While the DBSY 1 a device tried to do one of the following 1 Reading or writing to the transmitting or receiving FIFO 2 Wrote a system start command or a data communication start command 0100 Tried to communicate with a device which had device information area bit 7 set to 0 means the device is not used 1 24 4 8 ae EI COMB1 COMBO uem _ AL pm EU 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Note Write to the 8 bit CPU I F IFO H IF1 1 in the following ord
39. with available in the 5V interface column note the following These terminals can be input at 5 V level signal These are deleted diodes for overcurrent protection on 3 3 V lines If over voltage may be possible to charge due to reflection linking or inductive noise we recommend inserting a diode for overcurrent protection Without overcurrent protection diode Level shifter gt Outputs from 5 devices be connected to the center device as far as these TTL level Even if a signal is pulled up to 5V the output level will be less than 3 3 V However CMOS level signals cannot be connected On the CPU bus interface pull up of 5 V level is possible for stabilizing bus lines prevent floating Use 10 k ohm or larger capacity pull up resistors 4 2 Terminal allocation diagram SPDO SPD1 SIA GND VDD SIB GND CKSL GND CLK VDD GND GND GND RST VDD Note 0 SOEL MSYN MERF MCRY For each pin number see the marks on the actual LSI As shown above to the lower left of the NPM logo mark is the 1st pin D12 GND D11 D10 D9 D8 VDD D7 D6 D5 D4 GND D3 D2 D1 DO 4 3 Entire block diagram G9001A RST SPD 1 0 Clock control Internal clock 20 MHz CKSL circuit Internal clock 40 MHz CLK Memory area Device information area CS RD WR IF 1 0 A 8 0 CPU V F circul Command D 15 0 circuit control circu
40. CL 40 Note2 2 10 15 ns Tsuw n 40pF 7 ns ACK CK ON delay time for LS 7 CL 40pF 7 s Data float delay time for ACK 40pF Note 3 2Tax ns Data float delay time for LS 7 C 40pF 14 ns Data setup time for LS 7 Tost 22 ns Data hold time for ACK 0 5 Note 1 When CKSL LOW CKSL HIGH the ACK signal LOW level will be held for MIN 4 x MAX 28Tcik 15 Note 2 When CKSL LOW CKSL HIGH the ACK signal LOW level will be held for MIN 4 x MAX 20 15 Note 3 When CKSL LOW CKSL HIGH the data float delay time will be 4T xk 8 External dimensions Plastic QFP13 64pin Unit mm 1294 1 10 1 0 1 i 0 18 0 125 00 0 025 45 ll I O device G9002 User s Manual 11 2 1 Outline This LSI is an I O device for the Motionnet system The center device can control input and output signals for four ports each of which can be specified as an input or output port using terminal settings One port 8 bits 2 Features Four terminal ports be controlled Each port has 8 bits Input or output operation can be selected for each port Specify the I O selection using the LSI terminals The signal logic can be specified for each I O port Specify the logic using the LSI terminals A single 3 3 V power so
41. DNSM is LOW are the signals from other local devices through the DNSO terminal connected to the DNO terminal If this signal is held LOW normal address setting cannot be performed 9 Is one of the DNSO signals connected to the ZDNO terminals of multiple local devices Connect the DNSO signals in a daisy chain arrangement 10 Is an SOEL signal output by another local device connected to the SOEI terminal Only the SOEH signal can be connected to the SOEI terminal 11 When the device being checked is an I O device G9002 is the PMD 2 0 terminal setting wrong Is the combination of input and output ports set properly 12 When the device being checked is an I O device G9002 are the settings on PON P1N 2 and or P3N correct Using these terminals the signal logic can be changed for each port 13 Is there an open state input terminal 14 After releasing a reset does the TOUT terminal go LOW If so a local device is waiting for a signal from the center device The devices themselves must be appropriate 3 4 5 6 7 3 Checking the system 1 Is cable polarity correct Twisted pair cables must be used The polarity of these two lines must be correct The output from Y on the RS485 chip must be connected to input A on another RS485 chip and output Z must be connected to input B Are there termination resistors at both ends of the cable Is a terminal resistor connected in some other position not at the en
42. FIFO in the following order Outpw 0x0006h 0x0090h reds the command to the PCL device G9x03 Outpw 0x0006h 0x3456h 2 Write the data lower 16 bits Outpw 0x0006h 0x0012h 3 Write the data upper 16 bits The writing order to the FIFO is specified for the PCL device G9x03 in the user s manual for the G9x03 The register access command for the PCL device G9x03 is specified in the user s manual for the G9x03 Start data communication with the specified device number A PCL device G9x03 that receives this communication Outpw 0x0000h 0x4028h will write the data to the register specified in the data details Sts Inpw 0x0000h Read status Waits until the data communication is complete This process may be waiting for an interrupt YES YES Error processing Check the EDTE bit If the data communication failed take the defined steps Note that the EDTE bit will be cleared by reading the status The EDTE bit changes with the same timing as the CEND bit data communication command is constructed as follows 7 6 5 4 3 2 1 0 O O 15 14 13 12 11 10 9 8 0 1 0 0 0 0 0 0 Specify the address in these IV 15 2 8 Data communication 2 Read a register a PCL device G9x03 The example of data communication below shows how to read a register that is integrated in t
43. IGH pulses that are longer than the specified interval the I O device will be made to wait for a break frame When the device receives a break frame send request from a center device it immediately sends break frame A pulse at least 3200 usec long is needed in order to be seen as the BRK input pulse positive logic 1 10 4 4 18 PMDO to PMD2 Terminals used to determine the port direction of the four I O ports These terminals can set the ports as follows PMD2 PMD1 PMDO 7 0 P1 7 0 P2 7 0 P3 7 0 L L L Output Output Output Output L L H Input Output Output Output L H L Input Input Output Output L H H Input Input Input Output H L L Input Input Input Input When PMDO to 2 are set other than as shown above all the ports will be input ports However do not use any settings not shown 4 4 19 PON P1N 2 P3N Specify the input output logic for each port corresponds to port 0 P1N corresponds to port 1 P2N corresponds to port 2 and P3n corresponds to port 3 If a port is set HIGH by the corresponding PxN terminal then when this port is HIGH the center device will see a 1 If a port is set LOW by the corresponding PxN terminal then when this port is LOW the center device will see a 1 4 4 20 POO to 07 P10 to 17 P20 to 27 P30 to 37 Input output port terminals When used in output mode these terminal outputs are o
44. Input Input Input Other than the above above When a local device is a data device G9x03 G90044 the port used to exchange data status or general purpose ports have a different meaning for each device Device type 0 I O device Use of device 0 Do not use 1 Data device 1 Used When the device information is already known to a CPU you can write data from a CPU When a system communication is started during cyclic communication the center device halts the cyclic communication and executes the system communication which has a higher priority After the system communication is complete the center device will restart the cyclic communication Even if cyclic communications are halted the center device can still execute system communications 2 Cyclic communication In cyclic communication the center device communicates continuously to perform I O control of the I O devices G9002 This communication takes place in cycles Communication starts with the local device that has the lowest device number and proceeds through all the devices that are present When the I 32 communication with the device that has the highest number is complete the center device again starts to communicate with the local device that has the lowest device number If the communication target is a data device G9x03 G90044 it exchanges information such as device status By writing a cyclic communication start c
45. Motionnet Remote I O amp Remote Motion G9001A G9002 Center device device User s Manual NPM Nippon Pulse Motor Co Ltd Preface Thank you for considering our super high speed serial communicator LSI the G9000 To learn how to use the G9000 read this manual to become familiar with the product The handling precautions for installing this LSI are described at the end of this manual Make sure to What Motionnet is As a next generation communication system the Motionnet can construct faster and more volume large scale systems with wire saving than conventional T NET system conventional LSI product to construct serial communication system by NPM Further it has data communication function which the T NET does not have so that it can control data control devices such as PCL series pulse train generation LSI made by NPM The Motionnet system consists of one center device connected to a CPU bus a maximum of 64 local devices all connected using cables of two or three conductive cores Cautions 1 Copying all or any part of this manual without written approval is prohibited 2 The specifications of this LSI may be changed to improve performance or quality without prior notice 3 Although this manual was produced with the utmost care if you find any points that are unclear wrong or have inadequate descriptions please let us know Logic indicators 1 Terminal names and signal na
46. O and send it to the G9x03 using data communication When the G9x03 receives the data correctly the PCL device G9x03 should start Check the EDTE bit to see if the device communication was successful or not YES Error processing IV 18 2 10 Data communication 4 Start PCL6045B using a CPU emulation device The CPU emulation device G9004A can substitute for a CPU and it can be connected to normal CPU peripheral devices This section gives an example of how to start the PCL6045B LSI made by NPM that is used to generate pulse trains for 4 axes by the CPU emulation device G9004A Device type Configuration item Configuration data G9004A Device address 40 28h Registers to set in the PCL6045A B Register name Set value Remark PRFL 00000100h PRFH 00000200h PRMG 012Bh Multiplication rate 1 Send command data to the G9004A and it will process it one command at a time similar to a CPU to control the PCL6045A B Instruction to write data to the PCL6045B I O buffer Instruction to write the data in the I O buffer of the PCL6045B to the PRFL register Instruction to write data to the PCL6045B I O buffer Instruction to write the data in the buffer of the PCL6045B to the PRFH register Outpw 0x0006h 0x1184h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0081h Out
47. OR of all 256 input port change interrupt flag bits When all the bits return to O this bit returns to 0 EIOE Becomes 1 when a cyclic communication error occurs The center device then outputs an interrupt signal INT This signal is an OR of all 64 cyclic communication error flag bits For details about the conditions when the error occurred see 1 cyclic communication error in section 5 1 5 When all the bits return to O this bit returns to 0 EDTE Becomes 1 when a data communication error occurs The center device then outputs an interrupt signal INT For details about the conditions when the error occurred see 2 Data communication error in section 5 1 5 The method for clearing this bit will depend on status bit 9 in the RENVO register ERAE Becomes 1 when a local device reception processing error occurs The center device then outputs an interrupt signal INT For details about the conditions when the error occurred see the interrupt status CAE bit description on the next page Refer to this status bit to check which error occurred the device No and other error details The method for clearing this bit will depend on status bit 9 in the RENVO register CAER A CPU access error occurred When there is a problem accessing a CPU such as a data send command being written when there is no data to send this bit becomes 1 The center device then outputs an interrupt signal INT For details about
48. Peete eee e reer eter All 0000h except RVER 0001 h 1 37 6 How to calculate the communication cycle time The calculations of the communication cycle time can be classified as follows K Communication speed coefficient Communication speed Mbps K 20 1 10 2 5 4 2 5 8 N Number of local devices connected B Number of bytes of data to send when sending 2 bytes of data B 2 6 1 Time required for one cycle Basic item Required time us Communication time required per local device CT 7 7XK Cycle time CT 7 4 x N us Ex Calculating the cycle time with a communication speed of 20 Mbps and 30 local devices 7 7 x 1 7 4 x 30 453 us 6 2 Time required for one complete data communication There are two types of data communications as follows 1 When there is data in the response from a local device the data length is variable 2 When there is no data in the response from a local device Basic item Required time us Data sending time ST Bx0 6 3 25 x K Response time with data JT B x 0 6 5 65 x K Response time without data UT 5 05 x K One complete data communication cycle ST JT 7 4 us 6 3 Total cycle time including data communication The total time can be obtained by adding the data communication times to the ordinary communication cycle time Ex 1 Communication speed 20 Mbps 34 lo
49. Px 7 0 The I O device reads the data input on the ports using basically the same timing for the output data It sends the data it receives to the center device G9001A in the next cyclic communication The I O device reads the data on its input lines while MSEL is LOW To send it data from outside do so while MSEL is HIGH so that the I O device will be looking at stable data when the signal goes LOW again Also unless it is receiving cyclic communications from the center device G9001A normally the I O device G9002 will not read data that is sent to its input ports Il 14 6 External dimensions 80 pin LQFP Unit mm 0 1 45 0 055 0 045 e E 0to10 045 25 f 0 75 Il 15 lll Connection Examples and Recommended Environments G9000 Series 111 1 2 1 Connection examples 1 1 An example of a circuit to interface a CPU to a center device Four modes are available for connecting a CPU to the center device Shown below is an example for connecting a CPU to the IFO and terminals Please note that the CPU shown in the connection example below is only a representative example If the interface is similar CPUs other than the one shown below may be connected in this fashion For details see the hardware instructions for the CPU you are using 1 1 1 I F mode 4 IFO Z80 type CPU WAIT WRQ DO to D7 DO to D7 RST System reset Note 1
50. Q output CPU has a wait function 40 MHz or longer must be inserted by the CPU software 11 10 Address Next address CS A a WR TS SS WRQ DATA Command gt REEL DN CPU automatically waits for the required period of time 1 2 2 2 Write data to memory using write commands The write commands can be used to write data to certain memory areas Shown below is the write timing when I F mode 4 is selected Intervals of 4 clock cycles at 40 MHz are needed to write data into the I O buffer or to write write commands into the command area The following operations both read and write require intervals of at least 8 clock cycles at 40 MHz The data can be written in any order However the commands must be written in low bit high bit order When the WRQ terminal is connected to the wait terminal on a CPU the timing is controlled automatically by the CPU s wait control function Write data to the memory Next operation Ms PLATA Address 5 WR DATA A wait of 4 clock cycles at40 MHz A wait of 8 clock cycles at 40 MHz 111 11 1 2 2 3 Read data from memory using read commands Use read commands to read data from certain memory areas The read timing when I F mode 4 is selected is shown below After writing a read command the center device reads data from the I O buffer After a read command is sent the center device needs an
51. R signal width Twr Note6 14 ns Data setup time for WR 7 22 5 Data hold time for WR 7 Tap 0 ns Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or HIGH the 2WRQ signal LOW level will be held for 24 x Note 3 When CKSL LOW CKSL HIGH the data output delay time will be 4 24 Note 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until 2WR goes HIGH 1 42 7 4 5 I F mode 2 IF1 L IFO H 16 bit H8 etc Read cycle A 8 1 CS WRQ RD D 15 0 Write cycle A 8 1 CS WRQ WR D 15 0 Item Symbol Condition Min Max Unit Address setup time for RD WR 4 Tarw 18 ns Address hold time for RD WR 7 Trwa 0 ns CS setup time for RD 4WR 4 Tesrw 8 ns CS hold time for RD WR 7 Tawes 0 ns WRQ ON delay time for CS 4 40pF 11 ns WRQ ON delay time for RD 4 Trowt 4 Note 1 17 ns WRQ signal LOW time Twat Note 2 12 ns i C 40 Note 3 4 2Tcuc 24 ns D ata output delay time for RD 4 C 40pF Note 5 m C 40 Note 4 0 ns D ata output delay time for WRQ 7 C 40pF Note 5
52. V I F Vin 0 3 to 7 0 V Output resisting voltage open drain Vopp 0 3 to 7 0 V Input current lin 10 mA Storage temperature Tsto 40 to 125 SG 5 2 Recommended operating conditions Vss OV Item Symbol Rating Unit Power supply voltage Vop 3 0 to 3 6 V Input voltage ViN 2 Input voltage 5V I F Vin Up to 5 5 V Storage temperature Ta 40 to 85 V 5 3 DC characteristics Vss OV Item Symbol Condition Min Max Unit Current laa CLK 80 MHz 36 mA consumption Output leakage current loz 10 10 uA Input capacitance 5 6 pF LOW input current lit 10 10 uA HIGH input current lu 10 10 Terminals except CLK 0 8 V EPIRI eure Vt CLK terminal Vox0 2 V Terminals except CLK 2 0 V CLK terminal Vopx 0 8 V 0 4 mA 0 4 V LOW output voltage VoL Bi directional I F lo 8mA 0 4 V 1 pA Vss 0 05 V lou 4 mA 24 V HIGH output voltage Von PEER Va0 05 V Vo 0 4V 4 mA LOW output current lot Bi directional I F Vo 0 4V 8 mA HIGH output current lou 2 4 V 4 mA 1 12 5 4 AC characteristics 5 4 1 System clock 1 When setting CKSL L Item Symbol Min Max Unit Frequency fei 40 MHz Cycle 25 ns HIGH duration 10 15 ns LOW duration 10 15 ns Note In order to secure good communication quality use a clock offering the nearest figures to the standards above For details
53. When you use an interrupt controller the CPU will output IORQ as an interrupt acknowledge signal that is used to determine the interrupt vector At this time when this LSI s CS terminal goes LOW the LSI may output a ZWRQ signal and still not be able to capture the vector properly Therefore arrange the decoding circuit so that it only functions when the M1 signal is HIGH Note 2 Pull up terminals D8 to D15 to VDD externally 5 to 10 k ohms Note 3 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows to A15 Connect these lines to the decoding circuit and use them to create the 5 signal to A2 Connect these lines to AO to A2 on the center device Connect A3 to A8 on the center device to GND 3 1 1 2 I F mode3 IF1 H IFO L 8086 type CPU G9001A VDD Decoding CLK circuit A1 to A8 System reset System reset Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows Address signal as used in this example refers to signals output from the latching circuit A3 to A19 Connect these lines to the decoding circuit and use them to create the CS signal to A2 Connect these lines to AO to A2 on the center device Connect A3 to A8 on the center device to GND 111 4 1 1 3 I F mode L IFO H8 type CPU Decoding A9 to A15
54. a 0101 0011 5300h to 537Fh Writes to the input change interrupt flag area The contents of the input output buffer are written into one word of the above area 0101 0100 OFFF 998 5400h to 547Fh Writes to the port data area The contents of the input output buffer are written into one word of the above area 0110 0000 6000h to 607Fh Reads the device information area The contents of one word in the above area are copied to the input output buffer 0110 0001 O x xxxx 6100h to 617Fh Reads the cyclic communication error flag area The contents of one word in the above area are copied to the input output buffer 0110 0010 6200h to 627Fh Reads the input change interrupt setting area The contents of one word in the above area are copied to the input output buffer 0110 0 11 6300h to 637Fh Reads the input change interrupt flag area The contents of one word in the above area are copied to the input output buffer 0110 0100 998 6400h to 647Fh Reads the port data area The contents of one word in the above area are copied to the input output buffer Note Bit with 4 symbol Set upper bit of the device address from the upper side of the bit Bit with amp symbol Assign 0 for port 0 and 1 and assign 1 for port 2 and 3 Bit with x symbol Any value is available If all of the address map 512
55. a 2 ooftware Examlples 2 et aee pare Oder o epe IV 4 2 1 Start of the simplest cyclic IV 4 2 2 The center device specifies the data for the local devices that are connected IV 5 2 3 Set up input change IV 7 2 4 Check and clear any existing input change interrupts IV 9 2 5 Check and clear cyclic communication errors IV 11 2 6 Communication with port data port data and data device IV 13 2 7 Data communication 1 Put the value in the register of the PCL device 9 03 IV 15 2 8 Data communication 2 Read a register in a PCL device 9 03 IV 16 2 9 Data communication 3 Start the PCL device 9 03 IV 17 2 10 Data communication 4 Start a PCL6045B using a CPU emulation device 19 2 11 An example of measuring when break IV 23 V Troubleshooting V 1 1 Gheckirig the center device e Ee t tee eta teet lee ines V 1 2 Gheckirig the local devices epe tea RR tinte V 1 Ss Checking the system iin eem pda emp Eie V 1 MI dandling recalls
56. ach local device The lowest 4 bits will be the area for setting up interrupts for the local device with the lowest address number The lowest of the 4 bits corresponds to port 0 the next bit corresponds to port 1 and so forth When you want to monitor another local device determine the address using the following rule discard any remainder Address 0COh device number 2 The rule is the same for an 8 bit CPU except that the data will be transferred in units of 8 bits Since mainly status information corresponds to each port on data devices G9x03 G9004A you just enter 1 for the port which has the status you want to monitor For details see 5 1 3 Input change interrupt Be especially careful when monitoring the status of a device to make sure that port 0 is not monitoring all the bits For details about which status information corresponds to which port see the user s manual for each data device G9x03 G90044 For examples of use see point 2 in the Set up an input change interrupt section of Software Examples in Chapter IV 1 20 4 5 4 Change In Input Interrupt Flag area If a port has been specified in the area for setting Change In Input Interrupts when its port status changes the center device will issue an interrupt to a CPU and change the bit to a 1 The interrupt allows the CPU to determine the device number and port number or status which changed by reading this area Ex To monitor por
57. alf duplex communication Communication I F Note 3 RS 485 or pulse transfer Connection method Multi drop connection Number of local devices 64 devices max Cyclic communication cycle When using 8 local devices when 20 Mbps 128 points OUT 128 points 0 12 msec Note 4 When using 16 local devices IN 256 points OUT 256 points 0 24 msec When using 32 local devices IN 512 points OUT 512 points 0 49 msec When using 64 local devices IN 1024 points OUT 1024 points 0 97 msec Note 1 When transferring data with 20 Mbps speed and if the clock duty can be maintained to ideal 50 50 condition the center device can be operated by inputting 40 MHz clock signal The above ideal conditions mean that an oscillator and the center device are connected as 1 1 and close to each other Actually even these conditions cannot establish 50 50 However a duty approximate to the ideal one will be established Even if the ideal duty is broken a little when signal lines are shorter and or the number of local devices is smaller the center device can operate without any trouble For the details see the section for the CLK terminal When the signal lines are longer and or the number of connected local devices is greater and if it is difficult to warranty the clock duty you should take measures such as preparing an 80 MHz signal or preparing a 40 MHz clock proprietary to the center device To select clock rate specif
58. andle it LNRV status Conditions which cause this How to handle it After three retries if there is no If the target local device has a cyclic response from a local device the communication error check the wiring 1 LNRV bit is set to 1 and the local device status This means that the local device could If there is no cyclic communication not receive the data error retry the communication There was at least one response from You have to check whether the local the three retries However the center device received the data device could not receive a normal For example if the local device is a 0 response due to a CRC error or other PCL device G9x03 you can check problems by reading the sent data In this case the LNRV bit will be O and If the device could not receive the data itis unknown whether the local device normally try sending it again received the data or not When bit 9 in the RENVO register is 0 the interrupt signal can be reset by reading the status register However the interrupt status register itself is not cleared by reading 3 Other error processing 1 When local device detects an error in the receiving frame such as a CRC error it does not respond 2 When any of the following errors occurs in a local device it sends notice of the error to the center device in a response frame In cyclic communication a local device G9002 receives a frame that is different
59. any local devices on one line or when a signal line is long signal quality will be deteriorated remarkably In order to prevent this problem separate to two lines Even divided into two lines use easiness from a CPU is identical One line can connect to max 64 devices Even when two lines are used the max number of devices is 64 1 12 4 4 16 MCRY This is a monitor output to confirm communication When a signal is transferred on the signal line this terminal outputs L signal If there is no signal on the signal line this terminal outputs H signal 4 4 17 MERR This is a monitor output to check communication quality When the center device receives an error frame such as a CRC error or when it cannot receive a response frame within 20 us the signal becomes L only for 128 cycles 3 2 us of the CLK By measuring the condition using the counter you can check communication quality 4 4 18 MERF This is a monitor terminal to confirm communication control status When the center device receives an error response frame this terminal outputs L level signal only for 0 2 seconds The error response frame is as follows A local device normally receives signals from the center device if there is no CRC error on the local device However it may possible that the received data do not match with the local device status such as receiving output data on the input port In this case the local device sends back the data to t
60. bytes required by the center device are allocated so as the CPU can review the whole of them the commands described on this page are not needed If resources administrated by the CPU are shorted and only 8 bytes can be secured for the center device by using the commands described on this page the CPU can access all of the addresses the center device has 1 28 4 8 3 Register access command Description 0101 0101 0000 0000 5500h RENVO write command Store data in the input output buffer and issue this command the value in the input output buffer is copied to the RENVO register 0110 0101 0000 0000 6500h RENVO read command When this command is issued the value of the RENVO register is copied to the input output buffer By reading the input output buffer you can obtain the value of the RENVO 0110 0101 0000 0001 6501h Error counter read command When this command is issued the value of the error counter register is copied to the input output buffer By reading the value of the input output buffer you can obtain the value of the error counter 0110 0101 0000 0010 6502h Cyclic cycle register read command When this command is issued the value of the cyclic cycle register is copied to the input output buffer Reading the input output buffer you can obtain the value of the cyclic cycle register 0110 0101 0000 0011 6503h Receive address register read command W
61. cal devices are connected and on 4 occasions the data communication consisted of 2 bytes for sending and 6 bytes for receiving Cycle time Cyclic time Data communication time x Number of times of data communication 7 7 X 1 7 4 x 34 2 x 0 6 3 25 x1 6x0 6 5 65 x1 7 4 x4 513 4 21 1x4 597 8 us Note The formula above contains some margin for error In actual operation a shorter total time can be obtained However if a communication error occurs the total time will be longer than the calculated time 1 38 7 Electrical Characteristics 7 1 Absolute maximum ratings Item Symbol Rating Unit Power supply voltage Vss 0 3 4 0 V Input voltage Vin Vss 0 3 to 0 5 V Input voltage 5V I F Vin Vss 0 3 to 7 0 V Output current Terminal lour 30 Storage temperature Tsto 65 to 150 7 2 Recommended operating conditions Item Symbol Rating Unit Power supply voltage 3 0 to 3 6 V Input voltage Vin Vss to Vpp V Input voltage 5V I F Vin Vss to 5 5 V Storage temperature Ta 40 to 85 C 7 3 DC characteristics Item Symbol Condition Min TYP Max Unit Current consumption lad CLK 80 MHz 45 mA Output leakage current loz 1 1 Input capacitance 10 pF LOW input current lit 1 HIGH input current 1 LOW input current Vit 0 8 V HIGH in
62. ce No 0 00111 1001 079h Device information Device No 1 Device information Device No 1 01011 0110 0B6h Device information Device 62 _______ Device information Device No 62 0 1011 0111 0B7h Device information Device No 63 Device information Device No 63 01011 1000 OB8h Cyclic communication error flags Cyclic communication error flags Device eee Device No Oto 7 1 Ne01t07 Z L 24 0 1011 1001 OB9h Cyclic communication error flags Cyclic communication error flags Device Device No 8to15 805 4 4 010111110 OBEh Cyclic communication error flags Cyclic communication error flags Device lee ie cag ilar scs AEJBVICS No 48 to 55 Le __________ 481055 Cr iere eee eL 0 1011 1111 OBFh Cyclic communication error flags Cyclic communication error flags Device Device No 56 to 63 No 56 to 63 01100 0000 0 Input change interrupt settings Device Input change interrupt settings Device eta rotes c x xor rccte N NO Iu orte 011000001 OCth Input change interrupt settings Device Input change interrupt settings Device O a A SITS S S S S 0 1101 1110 ODER Input change interrupt settings Device Input change interrupt settings Device ____ 60 61 NNO OU 61 ee os Lee EC 011011111 ODFh Input change interrupt set
63. clear flags In order to return a bit to 0 that was changed to a 1 when an error occurred write a 1 to this bit The simplest way to clear a flag is to write the same data back to the same cyclic communication error flag position that it was read from For examples of how to use these flags see point 2 in the Check and Clear Errors in Software examples in Chapter IV 1 19 4 5 3 Change to Input Port Interrupt Setting area Port information for the I O devices G9002 that are connected can be obtained automatically using the cyclic communication system The center device also uses cyclic communication to periodically obtain status information for the data devices G9x03 G9004A that are connected These changes to input ports and status changes in data devices can be detected automatically and then the center device can generate an interrupt INT for a CPU This area can be addressed by writing bits that correspond to the local device number whose status you want to monitor When a bit is set to 1 its status will be monitored Ex When you want to monitor port 2 on device number 0 In order to specify device number 0 you have to access address OCOh Port 3 Port 2 Port 1 Port 0 For a 16 bit CPU address OCOh 15 14 13 12 11 10 9 8 7 6 5 AN 3 2 1 0 Device No 3 Device No 2 Device No 1 Device No 0 As shown above there are 4 bits which correspond to e
64. data for the general purpose port if any needs to be set To access this area see the device number and port number described in the address map To learn which status register corresponds to which port when the local device is a data device G9x03 or G90044 see the User s manual for each data device G9x03 G90044 For examples of use see point 2 in the Change In Input Interrupt Setting section of Software Examples in Chapter IV 1 21 4 6 Status STSW SS SSS oo STSB1 STSBO 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 BBSY DBSY RESY SESY o 688 REF o OAER ERAE EDTE EIGE TOPC BRKE CEND Bit Symbol Description CEND Becomes 1 when ready for data to be written to the transmitting FIFO buffer When the system communication or data communication is complete and the next chunk of data can be sent to the transmitting FIFO buffer this bit becomes 1 and the center device outputs an interrupt signal INT The method for clearing this bit will depend on status bit 9 in the RENVO register BRKF When the center device receives a break frame this bit becomes 1 and an interrupt signal INT is output The method for clearing this bit will depend on status bit 9 in the RENVO register IOPC Becomes 1 when any input port which had enabled the input change interrupt setting and that status changed The center device then outputs an interrupt signal INT This signal is an
65. ds When a 5V line transceiver is used is a level shifter connected Is the inductance of the pulse transformer too low Is the pulse transformer connected properly Are there any faulty contacts on connectors Is the same address used for two local devices Are pulse transformers connected to all branch points 0 If a pulse transformer is not used is the GND signal connected to all the branch points shared GND 1 2 3 4 5 6 7 8 9 1 11 Is the operating voltage on all the line transceivers at the same level Handling Precautions 1 Design precautions 1 Never exceed the absolute maximum ratings even for a very short time 2 Take precautions against the influence of heat in the environment and keep the temperature around the LSI as cool as possible 3 Please note that ignoring the following may result in latching up and may cause overheating and smoke Do not apply a voltage greater than 3 3V greater than 5V for 5V connectable terminals to the input output terminals and do not pull them below GND Please consider the voltage drop timing when turning the power ON OFF Consider power voltage drop timing when turning ON OFF the power Make sure you consider the input timing when power is applied Be careful not to introduce external noise into the LSI Hold the unused input terminals to 3 3 V or GND level Do not short circuit the outputs Protect the LSI from inductive pulses caused by electrical
66. e specify how to modify the addresses that will be output for each process OX Address is fixed 10 Increment the address When an 8 bit CPU 1 When a 16 bit CPU 2 11 Decrement the address When an 8 bit CPU 1 When a 16 bit CPU 2 Processing details Specify what the CPU should do 001 Write 010 Read The description of other combined processes is omitted Number of repetitions When 0 is specified the G9004 will execute the process details one time When 1 or more is specified the G9004 will execute the operation specified in the processing details the number of repetitions 1 Now interpret the values placed in the FIFO as follows Interpreted results To address 04h While incrementing the address number Write data Two times Write data two times to address 04h while adding one to the address each time Then what data should be written This corresponds to two words written to the FIFO sequentially Since the G9004 will execute the process two times two words need to be written IV 21 In all the following operations were commanded by the CPU emulation device 1st process Write 0100h to the specified address 004h 2nd process Write 0000h to the specified address 006h Actually these operations are equivalent to the procedures used to place data in the I O buffer of the PCL6045B After that instructions are needed about which data should be written to which register These are equivalent to the follow
67. e Details MCED By setting this bit to 1 the CEND interrupt is masked The status register is changed changed changed changed changed changed MCSE By setting this bit to 1 the interrupt is masked The status register is changed cS ox 3 Always set this bit to 0 8 BKOF By setting this bit to 1 the auto break function will be disabled MCLR Select the method for clearing the following status bits CEND BRKF EDTE ERAE CAER 0 Cleared by reading its status default setting 1 Not cleared by reading its status To clear the bit use INT group status clear command 04xxh 15 10 Always set this bit to 0 VII 2 2 4 2 RERCNT This is 16 bit register for counting errors This is a read only register It counts the total number of communication errors including no response and CRC errors When the number of errors exceeds 65535 the counter stops counting To clear the counter issue a counter clear command 0600h Note that the center device counts a failure to respond as a system communication error Originally a failure to respond to a system communication is not treated as error After the reset all the bits are zero 2 4 3 RSYONT 16 bit register for measuring the cyclic communication cycle The center device counts the time after MSYN changes in units of 1 This is a read only register The center device always count the cycles and you can read the amou
68. er COMBO then COMB1 4 8 1 Operation command Command Description 0000 0000 0000 0000 0000h 0000 0001 0000 0000 Resets the software 0100h Resets the center device This is the same function as the RST input 0000 0010 0000 0000 Resets the transmitting FIFO 0200h Resets only the data transmitting FIFO 0000 0011 0000 0000 Resets the receiving FIFO 00300h Resets only the data receiving FIFO 0001 0000 0 009 Clear command for the INT group status 04xxh Bits 0 1 4 5 and 6 of the command have the following meaning 0 CAER ERAE EDTE 0 0 BRKF CEND By changing each of these bits the corresponding status will be cleared However if RENVO 9 0 the clear command will be ignored 0000 0110 0000 0000 Error count clear command 0600h Clear the error counter register to zero 0000 0110 0001 0000 Break communication command 0610h Set RENVO 8 1 and disable the auto break function You can issue a break communication at any time using this command When REIVO 8 0 this command is ignored Note For all bits marked with the upper bits of the device address should be set in order starting from the left end of the bits For bits with marked with an amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit to 1 Either 0 or 1 may be used for bits marked with a For bits marked with an x either O or 1 may be used Invalid command
69. er device will read the response data from the data receiving FIFO Note 1 While cyclic communication is stopped data communication is disabled Note 2 Writing a send data command clears the data receiving FIFO Exclude a device with an error 1 The center device reads the interrupt status bits EDNO to 5 to identify the deice which has an error 2 Set the device in use bit in the device information area which corresponds to the device with an error to 0 Restoring excluded devices to cyclic communications Set the corresponding device in use bit in the device information area to 1 Or when RENVO 8 0 the following methods are available 1 Send a rising edge ON signal to the excluded local device s BRK terminal 2 When the center device receives the break frame it will output an interrupt request to the CPU 3 Write a command 1100h check all of the excluded devices and refresh the device information area 5 3 Status after reset Command L0 reer ete teeter ee 0000h Status eee ere ee 0000h Interrupt 0000h buffer 0000h Data transmitting FIFO m Undetermined Data receiving FIFO mmm Undetermined Device information LL All 00h Cyclic communication error flag All 00h Input change interrupt setting All 00h Input change interrupt flag All 00h Port data eee Peete etree eee eee ere eee reer All 00h Registers
70. er or the data transfer FIFO The timing for writing to the I O buffer address 4 and 5 when I F mode 4 or the data transfer FIFO address 6 and 7 when I F mode 4 is shown below Await time is necessary to perform continuous writing The wait must be 4 clock cycles or longer at 40 MHz 1 Does not use the ZWRQ output CPU does not have a wait function Address Next address CS T Aa SS RC N SSS DATA 25 wait of 4 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the ZWRQ output CPU has a wait function Address ws Ss WRQ gt CPU automatically waits for the required period of time 8 1 2 1 2 Writing to memory address The timing for writing to the memory area 078h to 1FFh with I F mode 4 is shown below Await time is necessary to perform continuous writing The wait must be 6 clock cycles or longer at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address Next address 5 WR TS 44 DATA lt gt a wait of 6 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the WRQ output CPU has a wait function Address Next address CS _ HWR N Bo 5 WRQ DATA Ea CPU automatically waits for the
71. ete flag in the FIFO Write a data communication command send the command data stored in the FIFO When CEND HIGH and EDTE 0 the local device flag has been reset IV 20 For detailed description of the G9004A CPU emulation device see the user s manual In this paragraph a simple explanation will be provided following the example above Assume that the G9004A is substituting for a 16 bit CPU Let the CPU emulation device substitute for a CPU The description of how to set the external terminals on the CPU emulation device is omitted The present subject is how to define the CPU operation to be done See the flow chart for writing command data to the FIFO Make sure the first data written sends 1184h to the FIFO This is the operation command for the CPU emulation device The CPU emulation device interprets the data received as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 mamm n acl Number of Processing Setting to Starting repetitions details refresh the address Communication wait setting description omitted Starting address Address to output on the address bus when the CPU emulation device is substituted for a CPU When it substitutes for a 16 bit CPU the lowest bit is ignored always 0 Address modification When the number of repetitions is set to 1 or more the CPU emulation device will repeat multiple processes continuously In this cas
72. evel shifter are needed to assert signals on lines such as 50 and SI 1 Circuit example for a single local device VDD Local device Line transceiver Terminating Pulse transformer resistor 1000 or equivalent Serial line ZDNO to ZDN5 IN DNSM Device number Note 1 Make the wiring as straight and short as possible circuit on a circuit board GND 11 14 Using the connections shown below the address of the local device above will be the address of the local device underneath it plus 1 2 Circuit example for multiple local devices Line transceiver 3 3 V Local device Pulse transformer Terminating resistor Serial line Note 1 Make the wiring as straight and short as possible circuit on a circuit board SO SOEH 51 SOEL DNSO Note 3 In the case that a continuous address by DNSO signal is set it is necessary at SOEI least approximately 50 ys until next Device number DNO to DN5 address is confirmed DNSM Local device GND Note 2 The pull down resistor to GND should be 5 to 10 k ohms 11 15 1 5 Aconnection example of a level shifter When using a 5 V line transceiver a level shifter is needed Shown below is an example of the connections for a level shifter SN74LVC244A and a line transceiver SN75LBC180A SN75LBC180A Pulse transformer SN74LVC244A G9000 series Communication l
73. f an input port changes the center device can output an interrupt request to CPU A bit corresponding to any input port number whose status changed can be set to 1 in the interrupt setting register And if the input port data changed while receiving cyclic communication data the center device will output an interrupt request to a CPU and it will change the bit in the input change interrupt flag register which corresponds to the input port number to 1 Then the CPU checks the input change interrupt status IOPC 1 when an interrupt occurs and reads the input change interrupt flag to identify which input port changed By writing back the flag data just read the interrupt can be reset In the case of an device G9002 If the input port data changed while receiving data an input change interrupt will occur In the case of data device G9x03 G9004A If bit 0 on input port 0 changes from 0 to 1 an input change interrupt will occur For ports other than input port 0 if the input port data changes an input change interrupt will occur the same way as it does for I O data The PCL device G9x03 handles the status register 16 bits as input ports O and 1 and the general purpose terminal status register as input port 2 data using cyclic communication The status register consists of bits to stop operation to indicate an error has happened and to indicate an event has occurred Using the input change interrupt functio
74. from the I O setting PMD terminal setting in case of an I O device G9002 An I O device receives a data communication frame A data device G9x03 G90044 receives a frame larger than the receiving buffer capacity 3 If the communication line does not change after 20 sec or longer when communicating at 20 Mbps after the center device has finished sending data it concludes that the local device could not receive the data In data communications and system communications the center device attempts sending the data three times During this time it also attempts to reestablish communications by inserting one cycle of cyclic communications If the result is still not good after the three attempts an error occurs and the status changes Also if the interrupt is not masked by the RENVO register the center device outputs an interrupt request to the CPU If the communication line does not change during the three attempts the center device concludes that the local device has not received the data and it will set LNRV bit 7 in the interrupt status register to 1 1 35 4 When frame received by the center device is faulty such as CRC error the center device sends a resend request to the local device a request to send the same data again It automatically sends the resend request up to three times During this time the center device also inserts one cycle of cyclic communications for a retry If the result is still no good after th
75. he PCL device G9x03 Assume that the local devices to be used are as follows Assume you want to read the register value in the PCL device G9x03 Device type Configuration item Configuration data PCL device Device address 40 28h Write a read command from the PCL device G9x03 register to the FIFO Register access command of the PCL device G9x03 is specified in the user s manual for the G9x03 Outpw 0x0006h 0x00DOh Have data communication with the specified device number A PCL device that received this communication returns the specified register data to the center device The returned data is stored in the receiving FIFO Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Read status Waits until the data communication will complete This process may be waiting for an interrupt YES Error processing Com Inpw 0x0006h Read the data in the receiving FIFO Data L Inpw 0x0006h The data details and order are specified in the user s Data H Inpw 0x0006h manual for the G9x03 Since 3 words of return data are specified the communication is completed by reading the FIFO three times If the number of words in the return data is not known read the status in the center device Keep reading the receiving FIFO until the RDBB bit goes LOW Data Inpw 0x0006h When reading data while checking the RDBB Dev_Sts Inpw 0x0000h RDBB 1
76. he center device in order to notify the center device that the received data is useless This is error response frame Other case is that a local device sends data longer than 8 bytes to a PCL device G9x03 8 bytes FIFO and the PCL device returns receipt process error format error 4 4 19 MSYN This is a monitor output of cyclic communication cycle Each time a cyclic communication cycle ends this signal level changes between L and H I 13 4 5 Address Address map 1 I F mode 4 Please be aware of Notes 1 and 2 while accessing AO to A8 Writing Reading 0 0000 0000 000h Command bits 0 to 7 Note 1 Status bits 0107 0 0000 0001 001h Command bits 8 to 15 Note 1 Status bits 8 to 15 0 0000 0010 002h Invalid Interrupt status bits O to 7 0 0000 0011 003 Invalid Interrupt status bits 8 to 15 0 0000 0100 004h Input output buffer bits 0 to 7 Input output buffer bits O to 7 0 0000 0101 005h Input output buffer bits 8 to 15 Input output buffer bits 8 to 15 0 0000 0110 006 Data transfer FIFO bits 0 to 7 Note 1 Data receiving FIFO bits Oto7 Note 2 0 00000111 007 Data transfer FIFO bit 8 to 15 Note 1 Data receiving FIFO bits 8to 15 Note 2 0 a 1000 Not defined 112 bytes Not defined 112 bytes 00111 0111 077h Any data written here will be ignored Always read as 00h 00111 1000 078h Device information Device 0 Device information Devi
77. he interrupt flags on all the addresses by using loop processing you can YES check just the areas required Note 1 In the address creation step above the program shifts the LOOP variable one bit left 2x This is because the address number to read increases by 2 each time the loop is executed Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 16 4 IV 11 2 When using only the upper 8 bytes in the address Assume that the routine is started by an interrupt being issued INT LOW Sts Inpw 0x0000h Read the status data in the center device Note 1 WORK LOOP lt lt 5 Shift the loop variable 5 bits left to create the read Com 0x6100h or WORK address Outpw 0x0000h Com Read the contents of the target address using the Data Inpw 0x0004h command that was just created Communication The bit positions which are 1 correspond to device and error port numbers whose input has changed In this step process all the flags that are 1 the other flags Process specified by the user do not need to be processed _ Write back the data you just read in order to clear the Com 0x5100h or WORK change interrupt flag Outpw 0x0004h Data Note that the command is different from the one used to Outpw 0x0000h Com read the data LOOP LOOP 1 Although this example checks the interrupt flags o
78. he output delay time see section 7 4 AC characteristics in the G9001A manual 1 2 2 Access by commands The center device has 9 address terminals used to access 512 bytes of memory The access timing for each of these addresses is shown below However for certain CPUs this amount of memory is not directly available In this case just use three address terminals to access 8 bytes in the center device When addressing in this fashion commands are used to access addresses beyond the basic 8 bytes The access timing used to access the memory area in the center device with commands is different from the method used for direct memory address However CPU s with a wait function don t need to be aware of these timing requirements since they use the 2WRQ terminal on the center device For CPUs that don t have a wait function monitor the IFB output or use software to observe the timing described below this is essential 1 2 2 1 Write operation command The operation commands shown below commands that don t need data such as Start and Stop use the write timing to write continuously to the command area address 1 when the I F mode 4 They must wait 8 clock cycles or longer to perform continuous writing at 40 MHz 1 Does not use the WRQ output CPU does not have a wait function Address Next address CS TES i 7 wR oo Np N DATA 4 waiting period of 8 clock cycles at 2 Uses the WR
79. hen this command is issued the value of the receive address register is copied to the input output buffer By reading the input output buffer you can obtain the value of the receive address register 0110 0101 0000 0100 6504h The register owned by the G90014 are not allocated on the address map Therefore in order to Version information register read command When this command is issued the version information register value is copied to the input output buffer By reading the input output buffer you can get the value of the version information register access these registers the commands described above shall be used 1 29 4 9 Register 4 9 1 RENVO register This is a 16 bit register used to establish the environment e Bits 0 to 6 Mask an interrupt a change on the INT terminal for the same bit position in the status register Unwanted interrupts can be ignored using this function Even if the interrupt is masked the status of the bits is not masked and can change as usual e Bit 8 In the original G9001 model the center device automatically issues a break signal at a certain interval in order to detect new devices that have been added In the G9001A this auto break signal can be suppressed When this bit is set to 1 the center device does not automatically issue a break signal e Bit 9 In the original G9001 depending on type of interrupt that occurred the status could be cleared by merely reading the statu
80. ice is read System communication commands are assigned to all local devices Outpw 0x0000h 0x1000h IV 23 V Troubleshooting During the initial design stage your system may not function normally due to simple misunderstandings or you may need to think about the problem differently If your system does not function normally after it is completely designed check the following 1 Checking the center device 1 Is power supplied properly 3 3 V only 2 Is the external clock signal stopped while a reset signal is input 3 Is the reset signal released 4 Is the clock signal supplied correctly 40 MHz or 80 MHz 5 Is the CKSL terminal set correctly LOW 40 MHz HIGH 80 MHz 6 Does the IF 1 0 terminal setting match the CPU that is connected 7 Is the data transfer speed identical throughout the system 8 Do the access times follow the specified timings 9 Is there open state input terminal 2 Checking the local devices 1 Is power supplied properly 3 3 V only 2 Is the external clock signal stopped while a reset signal is input Is the reset signal released Is the clock signal supplied correctly 40 MHz or 80 MHz Is the CKSL terminal set correctly LOW 40 MHz HIGH 80 MHz Does the data transfer speed match the setting on the center device When the DNSM is HIGH is the address set properly through the DN 5 0 terminal The address must be set using negative logic 8 When the
81. ine If the pulse transformer is at the end of the communication line insert a terminating resistor either GND before or after the pulse transformer Note 1 The pull down resistor to GND should be 5 to 10 k ohms 11 16 1 6 Complete configuration We recommend a configuration with the center device at one end of the line and the local devices at other end as shown below If you want to place the center device in the middle of the line use two communication lines so that the center device is effectively at the end of each line Center device SIB i 4 SO d 5 SOEH 2 3 E 2 Local device J9UJJOJSUEIJ If needed construct the same configuration on this side Local device 51 SO SOEH J9UJJ0JSUEIJ Terminating resistors needed at the ends of the line Insert them either Local device before or after the pulse transformer to get the same effect Terminating resistors are not needed anywhere except for the ends of the line J WJOJSUEJ OUI Local device J9UJJOJSUEJ 17 2 Recommended environment Shown below are the results of our experimental communication results and the environment used for the experiment These results can be used to design your own system However other system configurations are possible The example below is only for your reference
82. ing 1 licite dee ree de dudes 11 14 6 ana ee d obe e eh eto Oe a ene 11 15 IIl Connection Examples and Recommended 1 1 lt bte trente p tte edt tm te eignet reti 3 1 1 An example of a circuit to interface a CPU to a center device 111 3 1 1 1 VE mode 4 IE 1 HIFO m ET sain an rnt eee eae 3 15152 F mode3 IF1 Fy IFO S 0 in onere e te eel 111 4 1212320 mode S IE E EQ Ete de eee tpe 5 1 154 l E mode Es IE a E ioi er e Renee ee tn 111 6 1 1 5 Connecting to a CPU without a wait 7 T A ACCESS TIMING i cett fa vn ea E ip ena a Ee dO ER ete ld 1 8 1 2 1 et 1 8 1 2 1 1 Write to the I O buffer or the data transfer 11 8 1 2 1 2 Writing to a memory 111 9 tata Read ies eR 111 9 1 2 2 Access by commands te tutes cit it ei E Ee edes 111 10 1 2 2 1 Write operation 10 1 2 2 2 Write data to memory using
83. ing blocks written to the FIFO Let s look at them 0100h and 0081h were written to the FIFO The first data is sent to the CPU emulation device The interpreted meanings are as follows Interpreted results Write data 0081h to specified address 00h once This instruction is used to issue a command to the PCL6045B and has the meaning write the contents of the I O buffer into the PRFL register Now the data are sent to the PRFL In the same way commands can be stacked up in the FIFO so that the register setting is complete The last 0100h and 0051h mean write 0051h to address OOh This instruction corresponds to the FH speed start command on the PCL6045B After receiving this instruction the PCL6045B starts feeding pulses at FH speed Groups of commands can be stacked up for sending in the FIFO When a certain number of commands is stored in the FIFO send the command data to the CPU emulation device using data communication While interpreting the command data received the CPU emulation device will repeat its operation as a substitute for a CPU When all of the commands have been received the CPU emulation device turns on a bit in the status data which mean that the local side has completed the reception process This is passed along to the center device by cyclic communication Notes Be careful about the size of the command data group sent to the CPU emulation device The FIFO in the center device is 256 bytes long As l
84. ions of these devices must be very similar We used 1000 uH pulse transformers However in order to obtain better response characteristics you may want to try pulse transformers with a larger reactance Line transceivers We used TEXAS Instruments chips for the experiments Other possibilities are available from MAXIM and LINEAR TECHNOLOGY who offer very high performance transceivers Connectors If possible the connectors should match the cable characteristics Although we did not use them modular type connecters will be better for LAN cables Cable connections Do not connect one cable to another cable using connectors etc In a multi drop system the number of cables increases as the number of local devices increase However connecting a cable just to extend the line should be avoided Processing of excess cable Excess cable left over after making all the runs should be eliminated Unneeded cable length may restrict the line overall usable length and may introduce electrical noise Circuit board substrate Create circuits on a substrate with 4 or more layers to prevent the introduction of noise Estimating cable length in the system design phase In the first estimate use shorter line lengths In the actual system configuration lines may be lengthened Estimates made using the maximum length may lead to impossible communication distances Minimum cable length Each cable must be at least 60 cm 23 1 2 in l
85. it Data receiving Data transfer FIFO Receipt data Transfer processing processing circuit circuit SIA Serial signal Serial signa mE SIB receiving circuit transfer circuit m 4 4 Functions of terminals 4 4 1 4 4 2 4 4 3 This is an input terminal of the reference clock By setting of the CKSL terminal either of the following clock rate signals can be connected CKSL L 40 MHz CKSL H 80 MHz By selecting either of these clock rates the serial communication transfer rate does not change This clock rate selection affects communication precision For a small scale serial communication and transfer rate below 10 Mbps use of the center device with 40 MHz does not give any restriction With 20 Mbps transfer speed however longer communication lines or a large number of connected local devices may deteriorate communication precision due to collapse of signals on the circuit This deterioration of communication quality can be corrected inside the LSI if the deterioration level is not much In order to improve correction precision however evenness of the clock duty is required In other words if the duty is ideal 50 50 the capacity to correct collapse of the signals in the communication lines can be improved On the contrary if the duty is not ideal the center device cannot cope with collapses of the communication line As a result if the duty is close to ideal the center device can be used with 40 MHz When
86. le 11 VDD Power source 3 3 V 12 GND GND 13 POO B Bit 0 on port O Available 14 P01 B Bit 1 on port 0 Available 15 P02 B Bit 2 on port O Available 16 B Bit 3 on port 0 Available 17 P04 B Bit 4 on port 0 Available 18 P05 B Bit 5 on port O Available 19 P06 B Bit 6 on port O Available 20 P07 B Bit 7 on port 0 Available 21 VDD Power source 3 3 V 22 GND GND 23 P1N Negative 5 Sets P10 to P17 to use negative Available 24 P10 B Bit on port 1 Available 25 P11 B Bit 1 on port 1 Available 26 P12 B Bit 2 on port 1 Available 27 P13 B Bit 3 on port 1 Available 28 P14 B Bit 4 on port 1 Available 29 P15 B Bit 5 on port 1 Available 30 P16 B Bit 6 on port 1 Available 31 P17 B Bit 7 on port 1 Available 32 GND GND 33 VDD Power source 3 3 V 34 P20 B Bit 0 on port 2 Available 35 P21 B Bit 1 on port 2 Available 36 P22 B Bit 2 on port 2 Available 37 P23 B Bit 3 on port 2 Available 38 P24 B Bit 4 on port 2 Available 39 P25 B Bit 5 on port 2 Available 40 P26 B Bit 6 on port 2 Available 41 P27 B Bit 7 on port 2 Available 42 VDD Power source 3 3 V 43 GND GND 44 P30 B Bit 0 on port 3 Available 45 P31 B Bit 1 on port 3 Available 11 4 Signal name I O Logic Description
87. longer than 10 clock cycles is required CKSL Use to select clock rate L Connect 40 MHz clock frequency to the CLK terminal H Connect 80 MHz clock frequency to the CLK terminal Select this when the duty of the 40 MHz clock collapses too much DNO to DN5 Input terminals for setting device address Since these terminals use negative logic setting all the terminals to zero calls up device address 3Fh There are two methods for entering a device address Select the input method using the DNSM terminal 11 8 4 4 5 5 Select the input method for loading the device address 1 When the DNSM H Specify an address from 00 to 3Fh using the DNO to DN5 terminals 2 When the DNSM L Input a DNSO signal that is output by some other chip on the ZDNO terminal on this device When using this input method this chip has an address equal to the other chip s address plus one When using this method connect terminals DN1 to ZDN5 to GND When two sequential sets of serial data match the data is taken to be a device address 4 4 6 5 The numeric equivalent of the address on to DN5 1 will be output after being converted into serial bit stream Connect this output to another local device s DNO terminal make all the other DNSM terminals of that local device LOW so that other devices can get the address and pass it along to the next data sending device Please note that the next address after 3Fh
88. mes that start with a use negative logic Ex CS means that the CS terminal uses negative logic This has the same meaning as CS 2 The expression PCL device G9x03 and data device G9x03 means G9003 G9103 Motionnet Pulse Control LSI G9103 is our product under development as of April 2009 l Center device G9001 2 5222 1 1 Rei c E 1 3 VM EK DP 1 3 3 General specifications 1 4 3 1 Communication system 1 4 3 2 Center device specifications 69001 1 5 4 Hardware sese nist nn 1 6 4 1 Alist of terminals 64 ert ue lee EHE TER AUF IRSE 1 6 4 2 Terminal allocation 2 2 0 0000000 UnA 1 8 453 on b Pate e RUD IRE 1 9 4 4 Functions of terminals 5 Tate PR ends I 10 4 4 12 1 10 4 4 2 RST e pu ee ed ive edet edad eects 1 10 e Me cilm EE 1 10 LES MUN I 11 4 4 5 HOS edi eie
89. n the center device can output an interrupt request by changing the status of the PCL device G9x03 Break function when RENVO 8 1 Local devices have BRK terminals By applying a HIGH to the terminal for a certain length of time to create a break signal the local device will enter the break waiting status Also the center device periodically sends a break frame sending request to the local devices every 16384 cycles in cyclic communication or approximately every 250 msec at 20 Mbps offering another way to make a break The local devices in break waiting status send break frames when they receive a break frame send request More than one device may send a break at once The center device recognizes the break frame and outputs an interrupt request to a CPU It also sets the BRK bit bit 1 in the status register to 1 This function is used to restore the devices that were excluded from the system such as by device extension or due to an error The CPU detects an interrupt caused by a break and can then issue a system communication command This allows it to refresh all the devices in polling operation or to refresh the device information for devices that are currently stopped Control of communication errors 1 Cyclic communication errors When a cyclic communication error occurs the center device does not retry the communication However if it fails to communicate three times in a row three consecutive cycles a
90. n all the Note 2 addresses by using loop processing you can check just LOOP lt 4 the areas required YES The read command is constructed as follows 15 14 13 12 11 10 9 8 7 5 4 3 6 2 0 1 1 0 0 0 0 1 0 72 9 When writing data used to Specify the address in these 6 bits clear the flags these bits The lower 2 bits of the address byte are not used Leave them become 0101 at 0 1 X The lowest bit marked with amp is empty Leave it at 0 Note 1 In the address creation step above the program shifts the LOOP variable five bits left This is done to create the command above Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 16 4 IV 12 2 6 Communication with port data port data and data device status This section describes data exchange using the I O port on an I O device G9002 and how to obtain the status of a data device Assume that the local devices to be used are as follows Only an example of how to read the status is given for the PCL device G9x03 Device type Item to configure Configuration data Output data I O device Device address 2 Port 0 Input Port 1 Output 12h Port 2 Output 34h Port 3 Output 56h PCL device Device address 5 Note The por
91. nce the 8031 does not have a wait terminal the WRQ terminal cannot be used However some waiting time is needed to be able to access the center device since it takes some time to finish processing a command and a wait function is therefore essential for continuous access operations In the example above the IFB output terminal on the center device is connected to a port on the 8031 The IFB bit is monitored using a routine in the 8031 so that the 8031 does not try to access the center device while it is processing a command Note 1 When you only need to control 8 bytes without using the complete address map the address signals can be handled as follows A3 to A15 Connect these lines to the decoding circuit and use them to create the CS signal to A2 Connect these lines to AO to A2 on the center device to A8 on the center device should be connected to GND Note 2 Pull up D8 to D15 to VDD externally 5 to 10 K ohms 11 7 1 2 Access timing 1 2 1 Normal access The center device has 9 address terminals used to access 512 bytes of memory The access timing for each of these addresses is shown below CPUs that have a wait function can be connected to the WRQ terminal on the center device so that they can be used without special concern for signal timing However CPUs without a wait function must monitor the IFB output or use one of the following timing schemes this is essential 1 2 1 1 Write to the I O buff
92. nd to the target s device number Outpw 0x0004h Ox8B81h Outpw 0x0000h 0x5014h area Outpw 0x0004h 0x0083h Outpw 0x0000h 0x5028h Specify the device data for device number 20 Be careful not to corrupt the data for device number 21 Outpw 0x0000h 0x3000h Start cyclic communication Awrite command is constructed as follows 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 O 1 0 1 0 0 0 0 O0 8 Specify the address here The lower bit is not used in the address Leave it at 0 Positions marked with amp are not used Leave them at 0 IV 6 2 3 Set up an input change interrupt Assume that the center device wants to detect changes on the ports for the following two local devices Device No Port numbers to monitor for change 4 Port 0 7 Port 1 Port 2 1 When the whole address be used Specify the ports to monitor for device numbers 4 and 7 Be careful not to corrupt the data for device numbers 5 and 6 Outpw 0x00C2h 0x6001h End In I F mode 3 address 00C2h has the following meaning Monitor Port 1 and if there is a change on this port an input change interrupt will be issued Device No 7 Device No 6 Device No 5 Device No 4 15 14 13 12 11 109 8 7 6 5 4 3 2 1 0 0 1 1 0 0 0 j 0 0 0 0 0 0 0 0 0 1 Port 0
93. nt of time that has passed just before changing the MSYN The counter counts up to 65535 approx 65 5 ms The center device cannot measure the time if the MSYN signal length exceeds this value Read timing p L MSNY gt Can read this length as the time counted in microseconds 2 4 4 RDJADD This register latches the device address for the most recently received normal data communication This is a read only register After a reset all the bits are zero Device address for the most recently received normal data 2 4 5 RVER This register is used to read the version information in the G9001 or G9001A This is a read only register It always has the following value 0001h VII 3 Notes Oct 6 2009 No DA70109 1 5E VII 4
94. nts a failure to respond as a system communication error Originally a failure to respond to a system communication is not treated as error After the reset all the bits are zero 4 9 3 RSYONT 16 bit register for measuring the cyclic communication cycle The center device counts the time after MSYN changes in units of 1 This is a read only register The center device always count the cycles and you can read the amount of time that has passed just before changing the MSYN The counter counts up to 65535 approx 65 5 ms The center device cannot measure the time if the MSYN signal length exceeds this value Read timing 2 SS MSNY gt Can read this length as the time counted in microseconds 4 9 4 RDJADD This register latches the device address for the most recently received normal data communication This is a read only register After a reset all the bits are zero Device address for the most recently received normal data communication 4 9 5 RVER This register is used to read the version information in the G9001 or G9001A This is a read only register It always has the following value 0001h 15 13 10 8 4 0 This register is used to distinguish the 829001 from the G9001A Do the following to determine which chip is being used Write 0000h to the input output buffer Issue a read command 6504h to the RVER regis
95. o 63 Port 2 Port data No 254 Device No 63 Port 2 111111111 1FFh Port data No 255 Device No 63 Port 3 Port data No 255 Device No 63 Port 3 Note 1 Write in lower bit to upper bit order This order is especially important when accessing the FIFO used exclusively for sending data Note 2 Read in lower bit to upper bit order This order is especially important when accessing the FIFO used exclusively for receiving data I 15 Address map 2 I F mode 3 01011011 01011100 01011111 0 1100 000 01101111 01110000 01111 111 11111111 Cyclic communication error flags Cyclic communication error flags Device No 48 to 63 Input change interrupt settings Device No 60 to 63 Input change interrupt flags Device No 60 to 63 Port No 254 255 Device No 63 Port 2 3 1 to 8 Writing Reading 0 0000 000 000h Command bits 0 to 15 Status bits 0 to 15 0 0000 001 002h Invalid Interrupt status bits O to 15 0 0000 010 004h Input output buffer bits O to 15 Input output buffer bits O to 15 0 0000 011 006h Data transfer FIFO bits 0 to 15 Data receiving FIFO bits 8 to 15 0 Y 190 Bi Not defined 56 words Not defined 56 words 00111011 076h Any data written here will be ignored Always read as 00h 0 0111 100 078h Device information Device No 0 1 Device information Device No 0 1 Device information Device No 62 63 Device information Device
96. oes not change This clock rate selection affects communication precision For a small scale serial communication and transfer rate below 10 Mbps use of the center device with 40 MHz does not give any restriction With 20 Mbps transfer speed however a longer communication line or a large number of connected local devices may deteriorate communication precision due to collapse of signals on the circuit This deterioration of communication quality can be corrected inside the LSI if the deterioration level is not much In order to improve correction precision evenness of the clock duty is required In other words if the duty is ideal 50 50 the capacity to correct collapse of the signals in the communication lines can be improved On the contrary if the duty is not ideal the center device cannot cope with collapses of the communication line As a result if the duty is close to ideal the center device can be used with 40 MHz When connecting more than one oscillators the duty will not be ideal In this case select 80 MHz The center device divides the frequency inside and creates 40 MHz frequency If you do not want to 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI RST This is an input terminal for a reset signal By input L level signal the center device is reset As the center device synchronizes with a clock arrange a circuit so that it does not disconnect the clock while resetting Reset signal length
97. of the center device Then cyclic communication is started By doing this mis settings in local devices can be found rather easily an error occurs when there is a mis setting For example assume that the following three devices are connected The device numbers shown below are in decimal notation Local device type Device No Input port Output ports 1 I O device 10 Port 0 Port 1 to 3 2 PCL device 11 Port 0 to 2 Port 3 3 I O device 20 Port 0 to 2 Port 3 Note The port attributes of the PCL device G9x03 are fixed Input ports 0 and 1 contain status information 1 When the whole address map can be used all 512 bytes Outpw 0x0082h Ox8B81h Outpw 0x008ch 0x0083h Outpw 0x0000h 0x3000h Specify device data for device numbers 10 and 11 Specify device data for device number 20 Be careful not to corrupt the data for device number 21 Start cyclic communication For information about device data values see section 5 1 2 in Chapter With a PCL device G9x03 this value is always 8Bh IV 5 2 When using only the lower 8 bytes in the address map The details in the center device that can be seen by an external CPU are from the command area to the data transmission reception FIFOs Use commands to access other areas Specify the device data for device numbers 10 and 11 To set the data write the data to the I O buffer Then issue a write comma
98. ommand the center device communicates only with devices whose device information bit is set to 1 This communication continues until a cyclic communication stop command is written 2 Data communication In data communication the center device communicates with other data devices such as the PCL device G9x03 Normally the center device executes cyclic communications continuously A data communication command from a CPU allows you to perform data communications by interrupting the cyclic communications After writing data to the data transmitting FIFO write a send data command The center device will start the data communication on an interrupt when the current cyclic communication is complete When the data communication is complete the CEND bit 0 in the status register changes to 1 and an interrupt signal is output When data is received from a data device RDBB status register bit 10 becomes 1 so that the center device can read the data until receiving FIFO is emptied If data communication commands are written continuously further data communication will be postponed until another round of cyclic communications is executed once the current data communication is complete This ensures continuity in the cyclic communications After a local device has received data it will ignore any further data received until it has read out all of the data received and it will not send any response to the center device while reading the data
99. ommand Description 0001 0000 0 00 Clear command for the INT group status 04xxh Bits 0 1 4 5 and 6 of the command have the following meaning 0 CAER ERAE EDTE 0 0 BRKF CEND By changing each of these bits the corresponding status will be cleared However if RENVO 9 0 the clear command will be ignored 0000 0110 0000 0000 Error count clear command 0600h Clear the error counter register to zero 0000 0110 0001 0000 Break communication command 0610h Set RENVO 8 1 and disable the auto break function You can issue a break communication at any time using this command When REIVO 8 0 this command is ignored VII 1 2 3 Register access command Some registers have been added that were not in the G9001A These are not seen in the memory map so they can only be accessed using commands Register name Write Read Detail command command RENVO 5500h 6500h Environment setting register RERCNT 6501h Error counting register RSYCNT 6502h Elapsed cyclic time register RDJADD 6503h Device number latching register when data is received normally RVER 6504h Version information 2 4 Register 2 4 1 RENVO register A 16 bit register for establishing the environment bits are zero after a reset 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 519191919129 WOR BKOF o WOSE WERE WEDE METE WOP WARK WCE Bit nam
100. ommunication errorflag error flag 0CO to ODF Set input port change Set input port change interrupt interrupt OEO to OFF Reset input port change Input port change interrupt flag interrupt flag 100 to 1FF I O port data port data Communication 1 to 128 word frame 1 word 16 bits data length Data When communicating 3 words write 1 register of PCL 19 3 us communication When communicating 128 words 168 1 us time CPU I F Integrated 4 types of CPU I F circuit 280 8086 H8 68000 etc Transfer method Cyclic transfer for I O port transit transfer for data communication Package 64 pin model section 10 x 10 x 1 4 mm Power source 3 3 10 Storage 65 to 150 C temperature range Operating 40 to 85 C Note By issuing an operation command to the center device you can access the entire address area through a single I O buffer It will take more time than direct access Required address area is only 8 bytes 3 address signals For concrete use example see the software examples in chapter IV 4 Hardware description 4 1 A list of terminals QFP 64 Signal name I O Logic Description 5V interface 1 IFO CPU I F mode setting bit 0 Available 2 mode setting bit 1 Available 3 CS Negative Select chip Available 4 WR Negative
101. ommunication is not treated an error However an error with a CRC mismatch may be possible 0001 0011 1300h to 133Fh Obtain attribute information for the specified devices The polling response frame consists of device attribute information This command polls the specified devices and copies the attribute information into the data receiving FIFO The device information area does not change The details of the data receiving FIFO are as follows Bits 0 to 4 Number of bytes for the longest piece of data 8 1 Bits 5 to 7 Not used not defined Bits 8 to 15 Device type code I O device 01h Data device 81h Bits 16 to 18 Set the I O port PMD terminal information when an I O device is selected Bit 19 Always 0 Bits 20 to 31 Data device type G9003 000h G9004A 001h G9103 002h 0011 0000 0000 0000 3000h Start cyclic communication Start cyclic communication with devices that have 1 in the device in use bit in the device information 0011 0001 0000 0000 3100h Stop cyclic communication Stop the current cyclic communication 0100 0000 OO 4000h to 403Fh Data communication Sends data in the transmitting FIFO to the specified devices The data received in response will be stored in the receiving FIFO 0100 0001 0000 0000 4100h Cancel data communication Halt the data communication and reset the transmitting FIFO This command will be ignored after the da
102. ong Although this may seem contradictory to the excess cable precaution this minimum length is necessary 11 19 Using different cables system Do not mix cables from different manufacturers even when they are in the same category Different cable models from the same manufacturer should not be used either Using different cables together may deteriorate the communication quality 20 Software Examples flow chart G9001A IV 2 1 Assumption This Chapter outlines software for the center device using flow charts In the flow charts required variables are used for convenience 1 1 Environment and precautions used for the descriptions The descriptions below assume that I F mode 3 is selected Therefore a 16 bit data bus is used Address map details are found in item 2 I F mode 3 of the Address Map section in Chapter 1 The addresses described there will be used in the descriptions in this section Also these descriptions are based on the assumption that the wiring connections around the center device have been properly prepared and that the connected local devices are turned on And of course we presume that connections to the serial line and the termination resistances are all correct 1 2 Commands used We will use the following two commands to access the address map in the center device 1 Write command to the center device Outpw Address Data Address Value corresponding to
103. ong as the command group size does not exceed this value there should not be a problem However if the communication data increases the ratio of data that need to be caught as communication errors such as electrical noise will increase If the amount of data is small the data packet size used for sending is also small and it may be possible to for data packets to pass through between burst of noise If the packet size is too large a data collapse may occur due to a noise environment CRC error in which case proper communication cannot be established If the communication line is too long or the number of local devices connected is too great it is better to send command data after dividing it into smaller pieces IV 22 2 11 An example of measuring when break occurs If RENVO 8 1 the center device sends a break frame request periodically every 16 384 cycles of cyclic communication or every 250ms at 20 Mbps At this time if there is a device that has just been added to the communication line it places an H on the BRK terminal for a certain interval the local device will return a break frame If the center device receives this break frame it sets the BRKF bit in the status STSW register HIGH and changes the INT signal to LOW Now using the interrupt the CPU can see that a new device has been added The software is started when an interrupt is received INT LOW Sts Inpw 0x0000h The status in the center dev
104. pen drains Therefore they should be pulled up externally a few k ohms is all that is needed 1 5 V input and output are possible in the following conditions As an input Connect a 5 V signal As an output the pins can be pulled up to 5 V 2 Be careful not to provide too much voltage by reflection or linking 3 We recommend the use of diodes at each terminal to prevent the possibility of too much voltage 4 5 Status after reset to P07 When LOW HIGH when PON HIGH LOW when output is selected P10 to P17 When P1N LOW HIGH when P1N HIGH H LOW when output is selected P20 to P27 When P2N LOW HIGH when P2N HIGH LOW when output is selected P30 to P37 When P3N LOW HIGH when P3N HIGH LOW when output is selected Note A HIGH output H means that the terminal is externally pulled up to the voltage provided by the power supply Output circuits for the I O port terminals are open drains in order to handle a 5 V output Therefore an external pull up resistor is essential for correct operation A resister with a few K ohms is all that is needed to pull up the terminal 11 11 5 Electrical Characteristics 5 1 Absolute maximum ratings Vss OV Item Symbol Rating Unit Power supply voltage Vop 0 3 to 5 0 V Input voltage Vin 0 3 to Vpp 0 3 V Input voltage 5
105. plete This bit stays 0 for any other case Note 1 When errors occur on more than one device only the device number where the last error occurred would be shown 1 23 4 7 Interrupt status ISTW ISTB1 ISTBO AA Em 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 CAES 2 1 CAEO 2 1 LNRV 0 EDNS5 EDN3 EDN2 EDN2 EDNO Bit Symbol Description These bits show the number of the device which has an error when 0105 EDNOto5 EDTE 1 or ERAE 1 These details are stored until the next time an error occurs 6 Not defined Always 0 When a local device is not receiving data this bit is 1 When the data communication terminates with an error EDTE 1 and if a local device cannot receive data from the center device the local device does not respond this bit becomes 1 When the local 7 LNRV device has received the data communication data from a local device is interrupted by a communication error and the center device does not receive the data normally you have to check whether the local device received the data normally this bit returns to 0 This condition is stored until the next time an error occurs These errors occur even if a local device received data normally but the packet details of the data do not match at the local device When this error occurs the center device will store one of the following codes in these bits This condition is stored
106. port status set in the previous section changes an input change interrupt will occur This section describes how to check and clear this interrupt 1 When the whole address map is used Assume that the routine is started by an interrupt being issued INT LOW Read the status data in the center device Sts Inpw 0x0000h Note 1 WORK LOOP lt lt 1 Shift the loop variable 1 bit left to create the read Add 0x00e0h WORK address Data Inpw Add Read the contents of the address that was created Input change YES The bit positions which are HIGH correspond to device and port numbers whose input has changed In this step process all the flags that have become HIGH the other flags do not need to be processed Process specified by the user Outpw Add Data Loop Loop 1 Write back the data you just read in order to clear the change interrupt flag Although this example checks the interrupt flags on all the addresses by using loop processing you can check just the areas required Note 1 In the address creation step above the program shifts the LOOP variable one bit left 2x This is because the address number to read increases by 2 each time the loop is executed Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 4 16 9 2 When using only the upper 8 bytes the address
107. put current Vin 2 0 V LOW output voltage VoL lo 6 mA 0 4 V HIGH output voltage Vou lou 6 mA 0 4 V LOW output current lo VoL 0 4 V 6 mA HIGH output current loH Vpp 0 4 V 6 mA Internal pull up resistance 20 120 l 39 7 4 characteristics 7 4 1 System clock 1 When setting CKSL L Item Symbol Min Standard Max Unit Frequency 40 40 MHz Cycle 25 25 ns HIGH duration 10 12 5 15 ns LOW duration Tou 10 12 5 15 ns Note In order to secure good communication quality use a clock offering the nearest figures to the standards above For details see the CLK section of the terminal function in this manual 2 When setting CKSL Item Symbol Min Standard Max Unit Frequency 80 2 12 5 ns HIGH duration ns LOW duration ns 7 4 2 Reset timing RST Internal RST Item Symbol Min Standard Max Unit Reset length Twarsti 10 Clock cycles Delay time Torst 10 Clock cycles Note 1 The reset signal must last at least 10 cycles of the system clock While resetting Make sure the clock signal is continuously available to the device If the clock is stopped while resetting the device cannot be reset normally Note 2 After the internal RST goes LOW
108. pw 0x0006h 0x1184h Outpw 0x0006h 0x0200h Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0082h Outpw 0x0006h 0x1184h Outpw 0x0006h 0x012Bh Instruction to write data to the PCL6045B buffer Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Instruction to write the data in the buffer of the Outpw 0x0006h 0x0085h PCL6045B to the PRMG register Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0051h Instruction to the PC6045B to start feeding a pulse train at Data communication command send the command Outpw 0x0000h 0x4028h data stored in the FIFO This step checks the read status EDTE flag If a Dev Sts Inpw 0x0000h communication error occurs the next process should not be started If there is no error the PCL6045B will begin operation 1 gt In this step it is not clear if the PCL6045B is operating or not ejep puewwoy IV 19 Sts 28h Inpw 0x01A0h Outpw 0x0006h 0x0400h Outpw 0x0000h 0x4028h Dev Sts Inpw 0x0000h Error processing G9004A status bit 1 in this case equivalent to port 0 indicates whether reception by the local devices is complete When the G9004A completes all the processes specified this bit becomes 1 In other words this will mean that the PCL6045B has definitely started operation if there is no problem with the command data Put a reset instruction command for the local receive processing compl
109. ree resend requests the center device outputs an interrupt request to the CPU When sending this resend request since the local device already has the data LNRV bit 7 in the interrupt status register will be set to 0 1 36 5 2 Operating procedure 5 2 1 5 2 2 5 2 3 5 2 4 5 2 5 Reset After turning ON the power make sure to reset at least once before starting any operation 1 To perform a reset place a LOW on the RST terminal for at least 10 reference clock cycles 2 Wait until the status bit 13 RBSY becomes 0 Cyclic communication procedures 1 Write a command 1000h start system communications to all the devices and allow the device information area to be set automatically If the device information is already known you may write data information to the devices from the CPU 2 Place an initial value in the port data area Steps 1 and 2 can be performed in either order 3 Write a command 3000h to start cyclic communications After that write output information to the port data area when needed and read input information from the port data area Data communication procedure 1 Write data to be sent multiple words to the data transmitting FIFO 2 Write a send data command 4000h to 403Fh to send the data 3 Wait until the status bit O CEND becomes 1 4 If data has been received the status bit 10 RDBB will become 1 Until the status bit 10 RDBB returns to 0 the cent
110. request Available 39 IFB O Negative CPU I F is busy Available 40 MCRY Negative By detecting a communication line Available signal this signal becomes L for a rated interval 41 MERR O Negative When received an error frame and no Available response this signal becomes L level for a rated interval 42 GND GND 43 O Negative When receiving an error response frame Available this signal becomes L level for a rated interval 44 MSYN Negative The level reverses at each cyclic cycle Available 45 SOEL Negative Enable serial output Signal name I O Logic Description 5V interface 46 SOEH Positive Enable serial output 47 SO Positive Serial output 48 VDD 3 3 V power input 49 SPDO Communication speed setting bit 0 Available 50 SPD1 Communication speed setting bit 1 Available 51 SIA Positive Serial input A 52 GND GND 53 VDD 3 3 V power input 54 SIB Positive Serial input B 55 GND GND 56 CKSL Clock selection L 40 MHz 80 MHz Available 57 GND GND 58 CLK Reference clock 59 VDD 3 3 V power input 60 GND GND 61 GND GND 62 GND GND 63 RST Negative Reset 64 VDD 3 3 V power input Note 1 I in the I O column is for input is output and B is both directions Note 2 As for the terminals
111. required period of time 1 2 1 3 Read timing The data read timing for reading the status addresses 0 and 1 when the I F mode 4 the data receive FIFO addresses 6 and 7 when the I F mode 4 and the memory area 078h to 1FFh when the I F mode 4 is shown below When reading the I O buffer addresses 4 and 5 when the I F mode 4 no waiting time is needed Await of 4 clock cycles is needed for continuous reading at 40 MHz 1 Does not use the WRQ output CPU does not have wait function Address Next address CS T ie o gt N jg DATA wait of 4 clock cycles or longer at 40 MHz must be inserted by the CPU software 9 2 Uses the WRQ output CPU has a function Address Next address RD M S Eo m WRQ CPU automatically waits for the required period of time Note The memory area 078h to 1FFh when the I F mode 4 is shared with the internal serial reception circuit In order to prevent a conflict between reading by a CPU and the internal timing the center device transfers data from the memory area internal RAM to an indirect reading buffer and then reads the data from this buffer In order to secure the necessary data transfer time 2 clock cycles at 40 MHz the center device outputs WRQ L in response to RD L when reading the memory area Please note the output delay time for reading data For details about t
112. s In the new G90014 this auto clear function can be disabled By setting this bit to 1 the CEND BRKF EDTE ERAE and CAER status bits may not be cleared by reading them To clear these bits use the INT group status clear command 04xxh After a reset all the bits will be zero 1 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 519191919129 WOR BKOF o WOSE WERE WEDE VETE WTOP WARK WCE Bit name Details MCED By setting this bit to 1 the CEND interrupt is masked The status register is changed status register is changed status register is changed status register is changed status register is changed status register is changed status register is changed 27 i O 8 BKOF Bysettingthis bit to 1 the auto break function will be disabled MCLR Select the method for clearing the following status bits CEND BRKF EDTE ERAE CAER 0 Cleared by reading its status default setting 1 Not cleared by reading its status To clear the bit use INT group status clear command 04xxh 15 10 Do g Always set this bit to 0 1 30 4 9 2 RERCNT This is 16 bit register for counting errors This is a read only register It counts the total number of communication errors including no response and CRC errors When the number of errors exceeds 65535 the counter stops counting To clear the counter issue a counter clear command 0600h Note that the center device cou
113. s with an appropriate resistance factor However do not allow work on a metal surface which can cause a rapid change in the electrical charge on the LSI if the charged LSI touches the surface directly due to extremely low resistance When picking up an LSI using a vacuum device provide anti static protection using a conductive rubber pick up tip Anything which contacts the leads should have as high a resistance as possible When using a pincer that may make contact with the LSI terminals use an anti static model Do not use a metal pincer if possible Store unused LSls in a PC board storage box that is protected against static electricity and make sure there is adequate clearance between the LSls Never directly stack them on each other as it may cause friction that can develop an electrical charge 2 Operators must wear wrist straps which are grounded through approximately 1M ohm of resistance 3 Use low voltage soldering devices and make sure the tips are grounded 4 Do not store or use LSls or a container filled with LSIs near high voltage electrical fields such those produced by a CRT 5 To preheat LSIs for soldering we recommend keeping them at a high temperature in a completely dry environment i e 125 C for 24 hours The LSI must not be exposed to heat more than 2 times 6 When using an infrared reflow system to apply solder we recommend the use of a far infrared pre heater and mid infrared reflow devices in order
114. s or malfunctions may directly affect human survival or injure humans such as in nuclear power control devices aviation devices or spacecraft traffic signals fire control or various types of safety devices we will not be liable for any problem that occurs even if it was directly caused by the LSI Customers must provide their own safety measures to ensure appropriate performance in all circumstances VI 4 VII Differences between the 609001 G9001A The G9001A is a G9001 with upgrades to its functions This section describes the new functions added to the G9001A 1 How to distinguish between a G9001 and G9001A using a program Since a version information register is built in you can check the model number using this register D Write 0000h in the input output buffer Issue a read command 6504h to the RVER register 8 Read the input output buffer The meaning of the value read is as follows 0000h G9001 0001h G9001A 2 Newly added functions in the G9001A 2 1 Main status Bit 15 BBSY has been added 15 14 13 12111 10 9 8 7 6 5 4 3 2 1 0 BBSY DBSY RBSY SBSY 0 RDBB TDBB REF 0 CAER ERAE EDTE ETOE BRKF CEND Symbol When RENVO 8 1 and a break communication command 0610h is 15 BBSY issued this bit turns 1 until the break communication is complete This bit stays 0 for all other conditions 2 2 Operation commands The following operation commands have been added C
115. t 2 on device number 0 To read the status of device number 0 you must access address OEOh Port 3 Port 2 Port 1 Port 0 For a 16 bit CPU address OEOh 15 14 13 12 11 10 9 8 7 6 5 443 2 1 0 Device No 3 Device No 2 Device No 1 Device No 0 4 bits correspond to each local device The lower 4 bits are the Input Interrupt Setting area of the local device with the lowest address number The lowest bit among these 4 corresponds to port 0 the next bit corresponds to port 1 and so forth To check other local devices specify the address by using the following rule discard any remainder Address OEOh device number 2 The procedure is the same for an 8 bit CPU except that data will be handled in units of 8 bits To clear flags In order to return a bit to 0 that was changed to a 1 when a change occurred the input write a 1 to this bit The simplest way to clear a flag is to write the same data back to the same input change interrupt flag area that it was read from For examples of use see point 2 in the Change In Input Interrupt Setting section of Software Examples in Chapter IV 4 5 5 Port data area This area is used primarily to set the data for output ports on devices G9002 and to check the data from the input ports When the local device is a data device G9x03 G9004A this area is used to read status information and set
116. t area configuration of the PCL device G9x03 is always as follows fixed Port No Mode Description Port 0 Input Main status MSTSBO lower 16 bits Port 1 Input Main status MSTSB1 upper 16 bits Port 2 Input Input value from the general purpose 1 0 port IOPIB Port 3 Output Output value to the general purpose I O port IOPIB 1 When the whole address map can be used Outpw 0x0108h 0x1200h Outpw 0x010Ah 0x5634h Sts Inpw 0x0000h Write data to the I O device G9002 output port If the system is in the middle of cyclic communication just write the data here and it will be sent automatically to the target I O device G9002 Ports 2 and 3 can be specified at the same time 16 bit CPU Read status If you want to confirm whether the port data you wrote has been transferred use the following routine If you don t need to check it you don t need to use this routine Eie cim mamme ullae cac eue IEEE CAE cu Rm E Data Inpw 0x0108h Sts Inpw 0x0114h Get the data input from device G9002 port 0 This area will be filled with data automatically by cyclic communication Discard the upper 8 bits Read ports 0 and 1 at device address 5 This area might be automatically set as the status data for the PCL device G9x03 This area will be filled with data automatically by cyclic communication IV 13 2 When using only the
117. ta has been sent Note For all bits marked with the upper bits of the device address should be set in order starting from the left end of the bits For bits marked with amp when the port is 0 or 1 set the bit to 0 When the port is 2 or 3 set the bit to 1 For bits marked an x either O or 1 may be used G9002 I O device G9x03 PCL device G9004A CPU emulation device 1 26 Description 0101 0001 O x xxxx 5100h to 517Fh Write to the cyclic communication error flag area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0010 O 5200h to 527Fh Write to the input change interrupt setting area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0101 0011 xxx 5300h to 537Fh Write to the input change interrupt flag area The contents of the I O buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0100 O 998 5400h to 547Fh Write to the port data area The contents of the buffer are written into a word in this area Use this function when you want to reduce the number of addresses used in this device 0110 0000
118. ta hold time for WR 7 0 5 Note 1 Only when reading memory area address 078h to 1FFh WRQ LOW will be output by RD LOW Note 2 When CKSL LOW or HIGH the WRQ signal LOW level will be held for 24 x Note 3 When CKSL LOW CKSL HIGH the data output delay time will be 24 Note 4 When reading memory address addresses 078h to 1FFh Note 5 When reading non memory addresses addresses 078h to 1FFh Note 6 The time that the 4WRQ signal is output will be the interval after WRQ goes HIGH until 2WR goes HIGH l 41 7 4 4 I F mode 3 IF1 H IFO L 16 bit 8086 etc Read cycle A 8 1 CS WRQ RD D 15 0 Write cycle A 8 1 CS WRQ WR D 15 0 Item Symbol Condition Min Max Unit Address setup time for RD WR 4 Tarw 18 ns Address hold time for RD WR 7 Trwa 0 ns CS setup time for RD 4WR 4 Tesrw 8 ns CS hold time for RD WR 7 Tawes 0 ns WRQ ON delay time for CS 4 40pF 11 ns WRQ ON delay time for RD 4 Trowt 4 Note 1 17 ns WRQ signal LOW time Twat Note 2 12 ns C 40 Note 3 4 2Tcuc 24 ns D ata output delay time for RD 4 C 40pF Note 5 m C 40 Note 4 0 ns D ata output delay time for WRQ 7 C 40pF Note 5 Data float delay time for RD 7 Troup CL 40pF 28 ns W
119. ter Read the data in the input output buffer If the result is 0000h it is a G9001 If itis 0001h itis a 9001 1 31 5 Description of the software 5 1 Outline of control 5 1 1 Communication control The center device controls all the communications One communication cycle consists of a communication from the center device to the local devices and the communication from the local devices back to the center device The response from the local devices may include I O information and data 5 1 2 Communication type System communications cyclic communications and data communications are the three communication types available 1 System communications System communications automatically confirm the connection status device type and I O port settings of each local device By writing a system communication start command 1000h the center device polls all of the local devices device No 0 to 63 one by one and refreshes the device information area according to the response from the local devices 8 bits are used for the device information about each device 765 43210 0 0 0 Device information I O setting Set value Porto 2 Port3 PMD2 PMD1 PMDO 000 Output Output Output Output L L L 001 Input Output Output Output L L H 010 Input Input Output Output L H L 011 Input Input Input Output L H H Other than the Input
120. the center device automatically resets the internal memory area to all zeros address 078h to 1ffh After the reset is complete the center device is once again ready During the reset the status RBSY bit 13 remains 1 Therefore make sure that this bit has returned to 0 before accessing the center device at the end of a reset The following are the minimum times needed to reset the internal memory area CKSL L 270 6 75 usec at 40 MHz CKSL H 540 6 75 usec at 80 2 1 40 7 4 3 I F mode 4 IF1 H IFO H 8 bit 780 etc Read cycle A 8 0 CS WRQ RD D 7 0 Write cycle A 8 0 CS WRQ WR D 7 0 Item Symbol Condition Min Max Unit Address setup time for RD WR 4 Tarw 18 ns Address hold time for RD WR 7 Trwa 0 ns CS setup time for 4RD 4WR 4 T suw 8 ns CS hold time for RD WR 7 Tawes 0 ns WRQ ON delay time for 4CS 4 C 40pF 11 ns WRQ ON delay time for RD 4 Trowt 4 Note 1 17 ns WRQ signal LOW time Twat Note 2 12 5 C 40pF Note 3 4 24 ns D ata output delay time for RD 4 C 40pF Note 5 Be 40pF Note 4 0 ns Data output delay time for WRQ 7 L ata output delay time for Q 40pF Note 5 10 m Data float delay time for RD 7 Troup CL 40pF 28 ns WR signal width Twr Note6 14 ns Data setup time for WR 7 22 ns Da
121. the conditions when the error occurred see the interrupt status ERA bit description on the next page Refer to this status bit to check which error occurred the device No and other error details The method for clearing this bit will depend on status bit 9 in the RENVO register Not defined Always 0 REF When there is not yet sent output port data this bit becomes 1 When data is written to the output port this bit becomes 1 When the center device successfully completes two rounds of cyclic communication to all the ports without any errors this bit will return to O TDBB When there is data to send in the transmitting FIFO this bit becomes 1 After data is written to the transmitting FIFO this bit becomes 1 Once a data send command or a transmitting FIFO reset command is written this bit returns to 0 10 RDBB When data has been received in the receiving FIFO this bit becomes 1 When receiving data from a data device this bit becomes 1 After a CPU has read all of the data received this bit returns to O 11 Not defined Always 0 12 SBSY Becomes 1 when cyclic communication starts 1 22 Bit Symbol Description 13 RBSY Is 1 during a reset 14 DBSY Is 1 during system communication or data communication When RENVO 8 is 1 and the center device issues a break communication command 15 BBSY 0610h this bit stays 1 until the break communication is com
122. tings Device Input change interrupt settings Device No 62 63 No 62 63 011100000 OEOh Input change interrupt flags Device No Input change interrupt flags Device No ee SR EENE EEEN 011100001 1 Input change interrupt flags Device No Input change interrupt flags Device No 21 PORNO N 01111 1110 OFEh Input change interrupt flags Device Input change interrupt flags Device toot NOU 552622522 let 60 61 O 1111 1111 OFFh Input change interrupt flags Device No Input change interrupt flags Device No SERE CSS 1 0000 0000 100h Port data No 0 Device No 0 Port 0 Port data No 0 Device No 0 Port 0 l 14 AO to A8 Writing Reading 1 0000 0001 101h Port data No 1 Device No 0 Port 1 Port data No 1 Device No 0 Port 1 1 0000 0010 102h Port data No 2 Device No 0 Port2 Port data No 2 Device No 0 Port 2 100000011 103h Port data No 3 Device No 0 Port 3 Port data No 3 Device No 0 Port 3 11111 1100 1 Port data No 252 Device No 63 Port 0 Port data No 252 Device No 63 Port 0 11111 1101 1FDh Port data No 253 Device No 63 Port 1 Port data No 253 Device No 63 Port 1 11111 1110 TFEh Port data No 254 Device N
123. tion l 37 5 2 4 Exclude a device with an l 37 5 2 5 Restoring excluded devices to cyclic 2 1 37 5 9 otatlis after Tesel er ORDRE 37 6 How to calculate the communication cycle I 38 0 1 Time required Tor one cycle 22 c tete Ri ette Ca eb Rage Font RE Dent pata c io aie 1 38 6 2 Time required for one complete data communication 1 38 6 3 Total cycle time including data I 38 7 Electrical Characteristics I 39 7 1 Absolute maximum l 39 7 2 Recommended operating 2222 4 00 0 0 I 39 7 3 DC CHaracteristiCs i eR vib esate dece 1 39 7 4 oed de RU ee e ue dae a 1 40 7 4 1 Systern clock tede eene ied tpe ee pde e 1 40 7 4 2 Reset timing laeta eene ene eet ee e id e Ride e tide 1 40 7 4 3 mode4 IF 1 H 0 0 0 600000000000000001000000404000
124. to 1 For bits marked with an x either 0 or 1 may be used If all of the address map byte 512 bytes requested by the center device are allocated so that a CPU can see them the commands from 5000h and after as shown above are not needed If the resources controlled by a CPU are limited and only 8 bytes are available for addresses the commands from 5000h and up can be used to access to all of the addresses owned by the center device 1 27 4 8 2 Memory access command Description 0101 0000 5000h to 507Fh Writes data to the device information area The data in the input output buffer are written into one word of the device information area Relationship between The contents of the input output buffer and the area is shown in the table below Input output buffer bit 7 to 0 bit15 to 8 bit 7 to 0 bit15 to 8 bit 7 to 0 bit15 to 8 bit 7 to 0 07Eh bit15 to 8 07Fh Address 078h 079h 07Ah 07Bh 07Ch 07Dh Command Device No 5000h 5004h 5008h 500Ch 0101 0001 O x xxxx 5100h to 517Fh Writes to the cyclic communication error flag area The contents of the input output buffer are written into one word of the above area 0010 O 5200h to 527Fh Writes to the input change interrupt setting area The contents of the input output buffer are written into one word of the above are
125. umber bit 2 Available 79 DN1 Negative Device number bit 1 Available 80 DNO Negative Device number bit 0 common with the Available serial input line Il 5 4 2 Terminal assignment drawings 0 2 Q 5 5 5 amp 00 Q N Z y O n n OQ o amp ZAN gt 000 0n 0n nOn On 55 Fs 7 56 55 P26 P25 P24 P23 P22 P21 P20 VDD GND P17 P16 P15 P14 P13 P12 P11 P10 1 GND VDD Q a Zz O QA Q z A Q gt fL 0 0 a F amp gt Note Locate each number from the markings on the chip As shown in the figure above pin number 1 is at the lower left of the NPM logo mark 11 6 4 3 Complete block diagram G9002 5 DN 5 0 DNSM PMD 2 0 3 0 N SPD 1 0 CLK CKSL Communication control Manage device number Manage level output Watchdog timer Clock control 11 7 DNSO MSEL MRER TOUT PO 7 0 1 7 0 2 7 0 7 0 4 4 Functions of terminals 4 4 1 4 4 2 4 4 3 4 4 4 CLK This is an input terminal of the reference clock By setting of the CKSL terminal either of the following clock rate signals can be connected CKSL L 40 MHz CKSL H 80 MHz By selecting either of these clock rates the serial communication transfer rate d
126. urce is all that is needed Connections can be made to 5 V devices on the main terminals 3 Basic specifications 3 1 I O device specifications G9002 Item Description Number of input output ports 4 input output ports 1 port 8 bits Input or output operation can be selected using the terminals The I O signal logic can be set for each port using the terminals Transfer system Cyclic transfer Package 80 pin QFP Mold size 12 x 12 x 1 4 mm Power source 3 3 V 10 Storage temperature range 40 to 125 Operation temperature range 40 to 85 11 3 4 Hardware Description 4 1 List of terminals QFP 80 Signal name I O Logic Description 5 V interface 1 MRER Negative Goes LOW fora specified time when an abnormal communication is received 2 MSEL Negative Goes LOW fora specified time when this I O device is receiving data 3 TOUT O Negative Watchdog timer output 4 TMD Enable the watchdog timer Available 5 TUD Specify the operation when the watchdog Available timer signal is output 6 Sl Positive Serial input 7 SOEL O Negative Enables serial output 8 SOEH O Positive Enables serial output 9 50 Positive Serial output 10 4PON ae Sets to P07 to use negative Availab
127. ve become 0101 them at 0 The lowest bit marked with an amp is empty Leave it at 0 Note 1 In the address creation step above the program shifts the LOOP variable three bits left This is done to create the command above Note 2 The number of loop executions will always be less than 16 This is because one read loop can obtain the data for 4 local devices 64 4 16 IV 10 2 5 Check and clear cyclic communication errors If the same device number reports the same fault 3 times in a row in cyclic communication an error occurs This section describes how to check and clear this cyclic communication error 1 When the whole address map can be used Assume that the routine is started by an interrupt being issued INT LOW Sts Inpw 0x0000h Read the status data in the center device Oe 9 YES LOOP 0 Note 1 WORK LOOP lt lt 1 Shift the loop variable 1 bit left to create the read address Add 0x00B8h WORK Read the contents of the address that was just created Data Inpw Add NO Bit positions which are 1 correspond to device numbers where a cyclic communication error has occurred Communication error In this step process all the flags that are 1 the other flags Process specified by the user do not need to be processed Write back the data you just read in order to clear the Outpw Add Data change interrupt flag LOOP LOOP 1 Although this example checks t
128. write 111 11 1 2 2 3 Read data from memory using read 12 1 3 Line transceiver and pulse transformer for the center device 13 1 4 Line transceivers and pulse transformers for local devices 1 14 1 5 A connection example of a level shifter 2 1 111 16 1 6 Complete configuration aiara REI edison 11 17 2 Recommended environment 11 18 2 1 Cable titan bnt beca n eti ee teen adidas 111 18 2 2 TerminatingiTesistOF D e d bd D e Eu eras 111 18 2 3 Pulse transformer ere tn cta deep 111 18 v Mom E O dss 11 18 2 5 Parts used our 111 19 2 6 Other precautions me a rt etie Didi eed 19 IV Software Examples flow IV 1 T ASSUImbptlIOn albae E op eos fete e Eta MORI AUT dpt d IV 3 1 1 Environment and precautions used for the descriptions IV 3 122 Commands used 2 tre eo RUE o ate ee HIM De Fer tats E Eee d
129. y using the LSI terminal In either clock rate the maximum speed of 20 Mbps is the same Note 2 Select the communication speed using the LSI terminal Regardless of the selection of the communication speed the reference clock remains the same Note 3 NPM recommends using a system with a pulse transformer Note 4 The number of I O ports in the parenthesis is true when the all the connected local devices connected as device G9002 When data devices are connected such as PCL device G9x03 the number of available I O points will be decreased However basic cyclic cycle alt frequency does not change When the center device communicates data the frequency will be changed For this matter see the Calculation of communication time in this manual 3 2 Center device specifications G9001A Item Description Address area Normally it uses 512 bytes area 0 to 8 However 8 bytes area 0 to A2 can be used when using the buffer temperature range Note Adoressman Address h Writing Reading 000 to 001 Command Status 002 to 003 Invalid Interrupt status 004 to 005 I O buffer buffer 006 to 007 Data sending FIFO Data receiving FIFO 008 to 077 Not specified 112 bytes poe 112 078 to 0B7 Device information 8 bits Device information 8 device bits device 0 8 to OBF Reset cyclic Cyclic communication c

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