Home

bdiGDB User Manual

1. IO 0 OJO0 0 O O ilO 0 Olx nbr The bit i selects the instruction cache scan chain bit 32 the bit x extends access to register 6 scan chain bit 37 In the register definition file reg940t def you will find some examples Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 49 ARM926E The 16bit register number contains the fields of the appropriate MCR MRC instruction that would be used to access the CP15 register opc_1 opc_2 CRm nbr Normally opc_1 opc_2 and CRm are zero and therefore you can simply enter the CP15 register num ber In the register definition file reg926e def you will find some examples TI925T The CP15 registers are directly accessed via JTAG The following table shows the numbers used to access the CP15 registers and functions O or 0x30 ID 1 or 0x31 Control 2 or 0x32 Translation table base 3 or 0x33 Domain access control 5 or 0x35 Fault status 6 or 0x36 Fault address 8 or 0x38 Cache information 13 or Ox3d Process ID 0x10 TI925T Status 0x11 TI925T Configuration 0x12 TI925T I max 0x13 TI925T I min 0x14 TI925 hread ID 0x18 Flush I D TLB 0x19 Flush I TLB Oxla Flush I TLB entry Oxlb Flush D TLB Oxlc Flush D TLB entry 0x20 Flush I cache
2. NS elastic sealing back panel Mar front panel 5 3 Mount the screws do not overtighten it 5 4 Mount the two plastic caps that cover the screws 5 5 Plug the cables A ds Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse replacement Microfuse MSF 1 6 AF Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 57 C Trademarks All trademarks are property of their respective holders Copyright 1997 2006 by ABATRON AG Switzerland V 1 18
3. 2 1 1 Changing Target Processor Type Before you can use the BDI2000 with an other target processor type e g ARM lt gt PPC a new setup has to be done see chapter 2 5 During this process the target cable must be disconnected from the target system The BDI2000 needs to be supplied with 5 Volts via the BDI OPTION connec tor Rev A or via the POWER connector Rev B C For more information see chapter 2 2 1 External Power Supply To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 9 2 1 2 Adaptive Clocking Adaptive clocking is a feature which ensures that the BDI2000 never loses synchronization with the target device whatever the target clock speed is To achieve this BDI2000 uses two signals TCK and RTCK When adaptive clocking is selected BDI2000 issues a TCK signal and waits for the Returned TCK RTCK to come back BDI2000 does not progress to the next TCK until RTCK is received For more information about adaptive clocking see ARM documentation Note Adaptive clocking is only supported with BDI2000 Rev B C and a special target cable This special cable can be ordered separately from Abatron Rev B C 20 pin Multi ICE SDDDDDD DD A Connector Target System 1 7 19 1 Vcc Target SSeS 3 TRST 2 20
4. Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 78 4 Transmit the initial configuration parameters With bdisetup c the configuration parameters are written to the flash memory within the BDI The following parameters are used to configure the BDI BDI IP Address The IP address for the BDI2000 Ask your network administrator for as signing an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Subnet Mask The subnet mask of the network where the BDI is connected to A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask If the BDI and the host are in the same subnet it is not necessary to enter a subnet mask Default Gateway Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Config Host IP Address Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Configuration file Enter the full path and name of the configuration file This file is read via TFTP Keep in mind that TFTP has it s own root directory usual tftpboot You can simply copy the configuration file to this directory and the use the file name without any path For more
5. address Example the address of the RAM area WORKSPACE 0x00000020 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 ldi for GNU Debugger BDIZ000 ARM User Manual 30 SIO port baudrate When this line is present a TCP IP channel is routed to the BDI s RS232 connector The port parameter defines the TCP port used for this BDI to host communication You may choose any port except 0 and the default Telnet port 23 On the host open a Telnet session using this port Now you should see the UART output in this Telnet session You can use the normal Telnet connection to the BDI in parallel they work completely inde pendent Also input to the UART is implemented port The TCP IP port used for the host communication baudrate The BDI supports 2400 115200 baud Example SIO 7 9600 TCP port for virtual lO DCC port When this line is present a TCP IP channel is routed to the ARM debug communication channel DCC The port parameter defines the TCP port used for this BDI to host communication You may choose any port except 0 and the default Telnet port 23 On the host open a Telnet session using this port Now you should see the DCC output in this Telnet session You can use the normal Telnet connection to the BDI in parallel they work completely independent Also input to DCC is implemented port The TCP IP port used for the host communication Example DCC 7 TCP port for DCC VO Daisy chained JTAG devices For AR
6. ARM User Manual 33 3 2 4 Part FLASH The Telnet interface supports programming and erasing of flash memories The bdiGDB system has to know which type of flash is used how the chip s are connected to the CPU and which sectors to erase in case the ERASE command is entered without any parameter CHIPTYPE type fsys This parameter defines the type of flash used It is used to select the cor rect programming algorithm format AM29F AM29BX8 AM29BX16 I28BX8 I28BX16 AT49 AT49X8 AT49X16 STRATAX8 STRATAX16 MIRROR MIRRORX8 MIRRORX16 M58X32 AM29DX16 AM29DX32 CFM32 CFM16 LPC2000 STA2051 STR710F ST30F ADUC7000 AT91SAM7S fsys For the CMF32 CMF16 and LPC2000 the BDI needs to know the system frequency Enter the correct value for fsys in KHz Example CHIPTYPE AM29F CHIPTYPE CFM32 8000 fsys is 8 MHz CHIPSIZE size The size of one flash chip in bytes e g AM29F010 0x20000 This value is used to calculate the starting address of the current flash memory bank size the size of one flash chip in bytes Example CHIPSIZE 0x80000 BUSWIDTH width Enter the width of the memory bus that leads to the flash chips Do not en ter the width of the flash chip itself The parameter CHIPTYPE carries the information about the number of data lines connected to one flash chip For example enter 16 if you are using two AM29F010 to build a 16bit flash memory bank with the width of the flash memory bus in bits 8 16 32 Example BU
7. 0 cl cO n 2 r c static unsigned int poll dcc void unsigned int ret ___asm__ mre pl4 0 0 c0 cO n r ret return ret void write dcc char unsigned int c while poll_dcc amp DCC_OUTPUT_BUSY write dcc c unsigned int read dcc char void while poll_dec amp DCC INPUT READY return read dccl void write dcc string const char s while s write_dcc_char s Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 46 3 4 Telnet Interface A Telnet server is integrated within the BDI The Telnet channel is used by the BDI to output error messages and other information Also some basic debug tasks may be done by using this interface Enter help at the Telnet command prompt to get a list of the available commands Telnet Debug features e Display and modify memory locations e Display and modify registers e Single step a code sequence e Set hardware breakpoints for code and data accesses e Load a code file from any host e Start Stop program execution e Programming and Erasing Flash memory During debugging with GDB the Telnet is mainly used to reboot the target generate a hardware reset and reload the application code It may be also useful during the first installation of the bdiGDB sys tem or in case of special debug needs Notes The DUMP command uses TFTP to write a binary image to a
8. 0x22 Flush I cache entry 0x23 Flush D cache 0x24 Flush D cache entry address 0x25 Clean D cache entry address 0x26 Clean Flush D cache entry address 0x27 Flush D cache entry index 0x28 Clean D cache entry index 0x29 Clean Flush D cache entry index 0x2a Clean D cache 0x2b Drain Write buffer 0x37 I cache TLB Lock Down Ox3a D cache TLB Lock Down Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 50 3 5 Multi Core Support The bdiGDB system supports concurrent debugging of up to 4 ARM cores connected to the same JTAG scan chain For every core you can start its own GDB session The default port numbers used to attach the remote targets are 2001 2004 In the Telnet you switch between the cores with the command select lt 0 3 gt In the configuration file simply begin the line with the appropriate core number If there is no n in front of a line the BDI assumes core 0 The following example defines two cores on the scan chain TARGET CLOCK 1 JTAG clock 0 Adaptive 1 8MHz 2 4MHz 3 2MHz WAKEUP 1000 wakeup time after reset 0 CPUTYPE ARM7TDMI Q SCANPRED 00 JTAG devices connected before this core 0 SCANSUCC 14 JTAG devices connected after this core Q VECTOR CATCH catch unhandled exceptions 0 BREAKMODE SOFT Oxef180000 SOFT or HARD X To
9. configuration file also via BOOTP For this simple enter 0 0 0 0 as the BDI s IP address see following chapters If present the subnet mask and the default gateway router is taken from the BOOTP vendor specific field as defined in RFC 1533 With the Linux setup tool simply use the default parameters for the c option root LINUX_1 bdisetup bdisetup c p dev ttySO0 b57 The MAC address is derived from the serial number as follows MAC 00 0C 01 xx xx xx repace the xx xx xx with the 6 left digits of the serial number Example SN 93123457 gt gt 00 0C 01 93 12 34 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 17 2 5 1 Configuration with a Linux Unix host The firmware logic update and the initial configuration of the BDI2000 is done with a command line utility In the ZIP Archive bdisetup zip are all sources to build this utility More information about this utility can be found at the top in the bdisetup c source file There is also a make file included Starting the tool without any parameter displays information about the syntax and parameters A To avoid data line conflicts the BDI2000 must be disconnected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 Following the steps to bring up a new BDI2000 1 Build the setup tool The setup tool is delivered only as source files This allows to build the
10. ee ee ee ek ee ee ee 16 2 5 1 Configuration with a Linux Unix hos iss RE N GE DR EDE DEE ss ig es 17 2 5 2 Configuration with a Windows hOSt ee ee RA AR Re AA Re ee ee ee de ee ee ee ee ee ee 19 2 5 3 TAS COVE PROCS CUI SE Ee Ge Re EE ee N se ES 20 2 6 Testing the BD12000 to host connection ee ee RA AA ee Re ee ee ee 21 27 FIP Server tor Windows NT ies es ER GERS SR ENE WERP RES ER N ERWE Ee ee RE ERGER ENE RE GEE ee 21 3 Using bdiGDB NE EE N EE EE EE 22 3 1 Principle of speardd en ss esse en KS ER DER eg ER GN ee Ge ede ne GE DE Ee 22 3 2 Configuration del AE EE N EO EE 23 32 Pa INTE so oe ES END EO RD EE GE ER ED EG EE ED ee an 24 3 2 2 Part ERGE Tas EER ch ce ce GE EG OE EE EE EER Ge ae ee aat 27 EE diie SEE OE TE EE EE OE EE ETE EE 32 3 2 4 Part FLASH iiae e sd eects cece we eek dec De ee ee E EER DE n RE EE EE ee Ee 33 3 2 5 Pat REGS ES eT DE Ee EE Ne EE EE EE DE ee 40 3 3 Debugging with GODE Es EE ER ES EE ER Du RE RE EE IG EKEN Te Ra EE ee Ee 42 os ENE ie ES io N OE OR GO RE EE EE 42 3 3 2 Connecting to the TANGO se ek se Ek SE RR IG ESEG ER EER ER Ee DE Dee ke 42 3 3 9 Breakpoint HanoliNE se EER ES EER EN DE Ee DEER GN Ee ERG N Re EE Ree aed 43 GEE Blei el ese dd je die AE EE N N 43 3 3 5 largetserial I O via BDI ER OE EE EE N 44 3 3 6 Target DCC VO via BDI ies NEE EE Ee Ke ie ig Ge DE dee Ge EE GE DE ig 45 3 4 Telnet Interface RE EE EE N OE EE nennen 46 GE fae Command RE EE OR OE ME IR EE ET 47 3 4 2 CP15 COIS AE ME
11. format SREC BIN AOUT ELF COFF or ROM Example FORMAT ELF FORMAT ELF 0x10000 LOAD mode In Agent mode this parameters defines if the code is loaded automatically after every reset mode AUTO MANUAL Example LOAD MANUAL START address The address where to start the program file If this value is not defined and the core is not in ROM the address is taken from the code file If this value is not defined and the core is already in ROM the PC will not be set before starting the target This means the program starts at the normal reset ad dress Ox00000000 address the address where to start the program file Example START 0x10000 DEBUGPORT port The TCP port GDB uses to access the target port the TCP port number default 2001 Example DEBUGPORT 2001 PROMPT string This entry defines a new Telnet prompt The current prompt can also be changed via the Telnet interface Example PROMPT AT91 gt DUMP filename The default file name used for the Telnet DUMP command filename the filename including the full path Example DUMP dump bin TELNET mode By default the BDI sends echoes for the received characters and supports command history and line editing If it should not send echoes and let the Telnet client in line mode add this entry to the configuration file mode ECHO default NOECHO or LINE Example TELNET NOECHO use old line mode Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000
12. host file Writing via TFTP on a Linux Unix system is only possible if the file already exists and has public write access Use man tftpd to get more information about the TFTP server on your host Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 47 3 4 1 Command list y lt address gt lt count gt MDH lt address gt lt count gt MDB lt address gt lt count gt DUMP lt addr gt lt size gt lt file gt MM lt addr gt lt value gt lt cnt gt MMH lt addr gt lt value gt lt cnt gt MMB lt addr gt lt value gt lt cnt gt MT lt addr gt lt count gt MC lt address gt lt count gt MV RD lt name gt RDUMP lt file gt RDALL RDCP lt number gt RDIB lt number gt RI lt nbr gt 4 lt name gt lt value gt RMCP lt number gt lt value gt RMIB number lt value gt BOOT RESET HALT RUN time display target memory as word 32bit display target memory as half word 16bit display target memory as byte 8bit dump target memory to a file modify word s 32bit in target memory modify half word s 16bit in target memory modify byte s 8bit in target memory memory test calculates a checksum over a memory range verifies the last calculated checksum display general purpose or user defined regi
13. jumper is inserted correctly Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 13 2 3 Status LED MODE The built in LED indicates the following BDI states Rev B C MODE LED BDI STATES The BDI is ready for use the firmware is already loaded The power supply for the BDI2000 is lt 4 75VDC The BDI loader mode is active an invalid firmware is loaded or loading firmware is active Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 14 2 4 Connecting the BDI2000 to Host 2 4 1 Serial line communication Serial line communication is only used for the initial configuration of the bdiGDB system The host is connected to the BDI through the serial interface COM1 COM4 The communication cable included between BDI and Host is a serial cable There is the same connector pinout for the BDI and for the Host side Refer to Figure below Target RS232 Connector arget System for PC host ARM 7TDMI GND O on GND RD gt lt Po RD TD w w TD RTS N RTS gt lt x BDl2000 CTS CTs DSR Oo DSR DCD a _ DCD PC Host DTR n p PTR a RS232 Connector for PC host RS232 Target System ARM 7TDMI GND O1 ow GND RD id Po RD TD ay w T
14. only active if there is a newer firmware or logic version present in the execution directory of the bdiGDB setup software Press this button to write the new firmware and or logic into the BDI2000 flash mem ory programmable logic Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 20 BDI IP Address Subnet Mask Default Gateway Config Host IP Address Configuration file Transmit Enter the IP address for the BDI2000 Use the following format XXX XXX XXX XXX e g 151 120 25 101 Ask your network administrator for assigning an IP address to this BDI2000 Every BDI2000 in your network needs a different IP address Enter the subnet mask of the network where the BDI is connected to Use the following format xxx xxx xxX XxxX 9 255 255 255 0 A subnet mask of 255 255 255 255 disables the gateway feature Ask your network administrator for the correct subnet mask Enter the IP address of the default gateway Ask your network administra tor for the correct gateway IP address If the gateway feature is disabled you may enter 255 255 255 255 or any other value Enter the IP address of the host with the configuration file The configura tion file is automatically read by the BDI2000 after every start up Enter the full path and name of the configuration file e g D ada target config bdi evs332 cnf For information about the syntax of the configuration file see the bd
15. the target should also be possible Target System RS232 Connector 1 CD 2 RXD 3 TXD 4 DTR 5 GROUND 6 DSR 7 RTS 8 CTS 9 RI XXX BDI Output m The configuration parameter SIO is used to enable this serial VO routing The BDI asserts RTS and DTR when a TCP connection is established Ethernet 10 BASE T E TARGET SIO 7 9600 Enable SIO via TCP port 7 at 9600 baud Warning Once SIO is enabled connecting with the setup tool to update the firmware will fail In this case either disable SIO first or disconnect the BDI from the LAN while updating the firmware Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 45 3 3 6 Target DCC VO via BDI It is possible to route a TCP IP port to the ARM s debug communciation channel DCC This way the application running on the target can output messages via DCC that are displayed for example in a Telnet window The BDI routes every byte received via DCC to the connected TCP IP channel and vice versa Below some simple functions you can link to your application in order to implement IO via DCC define DCC_OUTPUT_BUSY 2 define DCC_INPUT_READY 1 static unsigned int read dcc void unsigned int c asm _ mre pl4 0 0 cl cO n r c return c static void write_dcc unsigned int c __asm__ mcr pl4 0
16. 06 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 42 3 3 Debugging with GDB Because the target agent runs within BDI no debug support has to be linked to your application There is also no need for any BDI specific changes in the application sources Your application must be fully linked because no dynamic loading is supported 3 3 1 Target setup Target initialization may be done at two places First with the BDI configuration file second within the application The setup in the configuration file must at least enable access to the target memory where the application will be loaded Disable the watchdog and setting the CPU clock rate should also be done with the BDI configuration file Application specific initializations like setting the timer rate are best located in the application startup sequence 3 3 2 Connecting to the target As soon as the target comes out of reset BDI initializes it and loads your application code If RUN is selected the application is immediately started otherwise only the target PC is set BDI now waits for GDB request from the debugger running on the host After starting the debugger it must be connected to the remote target This can be done with the fol lowing command at the GDB prompt gdb target remote bdi2000 2001 bdi2000 This stands for an IP address The HOST file must have an appropriate entry You may also use an IP address in the form xxx xxx XXX XXX
17. 2001 This is the TCP port used to communicate with the BDI If not already suspended this stops the execution of application code and the target CPU changes to background debug mode Remember every time the application is suspended the target CPU is freezed During this time no hardware interrupts will be processed Note For convenience the GDB detach command triggers a target reset sequence in the BDI gdb gdb detach Wait until BDI has resetet the target and reloaded the image gdb target remote bdi2000 2001 Note GDB sometimes fails to connect to the target after a reset because it tries to read an invalid stack frame With the following init list entries you can work around this GDB startup problem WGPR 11 0x00000020 set frame pointer to free RAM WM32 0x00000020 0x00000028 dummy stack frame Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 43 3 3 3 Breakpoint Handling If your GDB version does not support the Z packet protocol unit it inserts breakpoints by replacing code via simple memory read write commands When breakpoint mode HARD is selected the BDI checks the memory write commands for such hidden Set Breakpoint actions If such a write is de tected the write is not performed and the BDI sets an appropriate hardware breakpoint The BDI as sumes that this is a Set Breakpoint action when memory write length is 4 bytes and the patte
18. AO EA DEE EE eneen en 48 3 5 Multi Cors DOL ei EE ER DE etre n eee eee ere 50 A Specifications ee KEER Ee Ee SE ee Ee tcc aa ect ee es ER ER EE EER 51 5 Environmental NOUGE es se ER Ee Ee EEN RE ea ee Ne kie Ve ee eN AK n Re GEN ke eN eN ENE patineta 52 6 Declaration of Conformity EE RSA N KERR SEE ER RR ERKEN ARGK RAS GRA BES RENEE ERWE GEKEER RE RE REN enna 52 T EE OE EE EE EE EE raui 53 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bdi for GNU Debugger BDIZ000 ARM User Manual 3 7 Appendices A Troubleshooting EE EE EE 54 B MainienanCe ii ER EE SE ee diate Se Ee Ee ee N ia avs Ee RR GEE RA Re RE ee Ge een GE ee ee eek de Ee See 55 GIE Tel vy GR N EE EE OE OE 57 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 4 1 Introduction bdiGDB enhances the GNU debugger GDB with JTAG debugging for ARM7 ARM9 based targets With the builtin Ethernet interface you get a very fast download speed of up to 70Kbytes sec No tar get communication channel e g serial line is wasted for debugging purposes Even better you can use fast Ethernet debugging with target systems without network capability The host to BDI commu nication uses the standard GDB remote protocol An additional Telnet interface is available for special debug tasks e g force a hardware reset program flash memory The following figure shows how the BDI2000 interface is connected between t
19. Aa JTAG interface for GNU Debugger ARM ARM4 User Manual Manual Version 1 18 for BDI2000 AR N 1997 2006 by Abatron AG ldi for GNU Debugger BDIZ000 ARM User Manual 2 1 Introd cti n EE EE EE N EE N OE arana A n raaa nana Aas anaa nni Ra nara aaia 4 id BDI2000 oe e a a ES EE EE et ee ee eee errs 4 1 2 BDI Configuration eee see es cena sd eerie eee EE seeds Ie EE we aca ts GE Ge Ee AE EE De GEE ie 5 SD Eie EE EE N EE ae anes es dso dace N N OE 6 2 1 Connecting the BDI2000 to TEL ss ei EE aes etc EE EE eN ee EE EE eens 6 2 1 1 Changing Target Processor Type iss ee see AE RA AA Re ee de ee Ge ee ee AA ee 8 2 1 2 Adaptive COCR ING seca ER ES EE ER ER N EE DER GE Ee Es De AE BR ES GE RO Ee Ee 9 2 2 Connecting the BDI2000 to Power Supply sees ee Re AA Re AA Re ee ee Re ee ee ee ee nne 11 22 1 External Power SUPER ER RE EG ENS GEE SAK RED ERGER Re GER SE GR GE REG RENE ENE ERG 11 2 2 2 Power Supply from Target System eise see ese ee Re AA AR AA Re ee ee ee ee de ee 12 2 4 Status LED MOD E dsrscs Ge Ge N ie SE ERGE Se ee Ee EREA N be ee AGE ES ERGE GED de ie 13 24 Connecting the BDI200D to HOS iese si RENE EER AE DER Ee KEER EER REG EE RE EN GEEN e ee ekke ge 14 2 4 1 Serial line COMMUNICATION issie EER ARE ERSE S ERG RE RE KG GR GARAGE RE KAS AGE DEER dee AG EE Geek Ne 14 242 Ethernet c mm MEaAtION GE ss GEE SR ee ee ED aa 15 2 5 Installation of the Configuration Software esse ee Re RR ee Re ee ee ee
20. BDIMODE AGENT the BDI working mode LOADONLY AGENT BREAKMOD SOFT SOFT or HARD i HOST IP 1514120 25 100 FILE E cygnus root usr demo arm myapp FORMAT COFF LOAD ANUAL lt AGENT gt load application MANUAL or AUTO after reset FLASH WORKSPACE 0x00000000 workspace in target RAM for fast programming algorithm CHIPTYPE AM2 9F Flash type AM29F AM29BX8 AM29BX16 I28BxX8 I28BX16 CHIPSIZE 0x20000 The size of one flash chip in bytes e g AM29F010 0x20000 BUSWIDTH 8 The width of the flash memory bus in bits 8 16 32 FILE E cygnus root usr demo arm boot hex The file to program ERASE 0x04000000 erase sector 0 of flash in U12 AM29F010 ERASE 0x04004000 erase sector 1 of flash ERASE 0x04008000 erase sector 2 of flash ERASE 0x0400C000 erase sector 3 of flash ERASE 0x04010000 erase sector 4 of flash ERASE 0x04014000 erase sector 5 of flash ERASE 0x04018000 erase sector 6 of flash ERASE 0x0401C000 erase sector 7 of flash Based on the information in the configuration file the target is automatically initialized after every re set Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 6 2 Installation 2 1 Connecting the BDI2000 to Target The enclosed cables to the target system are designed for the ARM Development Boards In case where the target system has the same connector layout the cable 14 pin or 20 pi
21. M targets the BDI can also handle systems with multiple devices connected to the JTAG scan chain In order to put the other devices into BYPASS mode and to count for the additional bypass registers the BDI needs some information about the scan chain layout Enter the number count and total instruction register irlen length of the devices present before the ARM chip Predecessor En ter the appropriate information also for the devices following the ARM chip Successor SCANPRED countirlen This value gives the BDI information about JTAG devices present before the ARM chip in the JTAG scan chain count The number of preceding devices irlen The sum of the length of all preceding instruction regis ters IR Example SCANPRED 1 8 one device with an IR length of 8 SCANSUCC count irlen This value gives the BDI information about JTAG devices present after the ARM chip in the JTAG scan chain count The number of succeeding devices irlen The sum of the length of all succeeding instruction reg isters IR Example SCANSUCC 2 12 two device with an IR length of 8 4 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bd for GNU Debugger BDIZ000 ARM User Manual 31 Low level JTAG scan chain configuration Sometimes it is necessary to configure the test access port TAP of the target before the ARM debug interface is visible and accessible in the usual way The BDI supports this configuration in a very ge neric way via th
22. P BDl2000 RTS N y RTS CTS pe co CTS DSR O DSR PC Host DCD 4 x DCD DTR N p DTR ma E RS232 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 15 2 4 2 Ethernet communication The BDI2000 has a built in 10 BASE T Ethernet interface see figure below Connect an UTP Un shilded Twisted Pair cable to the BD2000 For thin Ethernet coaxial networks you can connect a commercially available media converter BNC gt 10 BASE T between your network and the BDI2000 Contact your network administrator if you have questions about the network 10 BASE T Connector 1 TD 2 TD 3 RD Target System 6 RD Rev B C 7TDMI PC Host mm The following explains the meanings of the built in LED lights TX RX 10 BASE T LI TX RX 10 BASE T BDl2000 Ethernet 10 BASE T C LED Name Description LI Link When this LED light is ON data link is successful between the UTP port of the BDI2000 and the hub to which it is connected TX Transmit When this LED light BLINKS data is being transmitted through the UTP port of the BDI2000 RX Receive When this LED light BLINKS data is being received through the UTP port of the BDI2000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Ma
23. RM710T ARM720T ARM740T ARM9TDMI ARM920T ARM940T TMS470 ARM9E ARM946E ARM966E ARM926E TI925T MAC7100 FA526 Example CPUTYPE ARM920T CLOCK main init With this value s you can select the JTAG clock rate the BDI2000 uses when communication with the target CPU The main entry is used after processing the initialization list The init value is used after target reset until the initialization list is processed If there is no init value defined the main value is used all the times Adaptive clocking is only supported with BDI2000 Rev B C and needs a special target connector cable main init 0 Adaptive 1 16 MHz 6 200 kHz 2 8 MHz 7 100 kHz 3 4 MHz 8 50 kHz 4 1 MHz 9 20 kHz 5 500 kHz 10 10 kHz Example CLOCK 1 JTAG clock is 16 MHz RESET type time Normally the BDI drives the reset line during startup If reset type is NONE the BDI does not assert a hardware reset during startup This entry can also be used to change the default reset time type NONE HARD default SGOLD enables S GOLD ARM9 TAP during reset time The time in milliseconds the BDI assert the reset signal Example RESET NONE no reset during startup RESET HARD 1000 assert RESET for 1 second TRST type Normally the BDI uses an open drain driver for the TRST signal This is in accordance with the ARM recommendation For boards where TRST is simply pulled low with a weak resistor TRST will always be asserted and JTAG debugging is
24. SWIDTH 16 FILE filename The default name of the file that is programmed into flash using the Telnet prog command This name is used to access the file via TFTP If the file name starts with a this is replace with the path of the configuration file name This name may be overridden interactively at the Telnet interface filename the filename including the full path or for relative path Example FILE F gnu arm bootrom hex FILE bootrom hex FORMAT format offset The format of the file and an optional address offset The optional param eter offset is added to any load address read from the program file format SREC BIN AOUT ELF or COFF Example FORMAT SREC FORMAT ELF 0x10000 WORKSPACE address _ If a workspace is defined the BDI uses a faster programming algorithm that runs out of RAM on the target system Otherwise the algorithm is pro cessed within the BDI The workspace is used for a 1kByte data buffer and to store the algorithm code There must be at least 2kBytes of RAM avail able for this purpose address the address of the RAM area Example WORKSPACE 0x00000000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 AR for GNU Debugger BDIZ000 ARM User Manual 34 ERASE addr increment count mode wait The flash memory may be individually erased or unlocked via the Telnet interface In order to make erasing of multiple flash sectors easier you can enter an erase list All entries in the era
25. Select This output of the BDI2000 connects to the target TMS line reserved reserved GROUND System Ground RESET System Reset This open drain output of the BDI2000 is used to reset the target system reseved reseved GROUND System Ground Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bdi for GNU Debugger BDIZ000 ARM User Manual 71 2 2 Connecting the BDI2000 to Power Supply 2 2 1 External Power Supply The BDI2000 needs to be supplied with 5 Volts max 1A via the BDI OPTION connector Rev A or via POWER connector Rev B C The available power supply from Abatron option or the en closed power cable can be directly connected In order to ensure reliable operation of the BDI2000 keep the power supply cable as short as possible A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics LT BDI OPTION Connector 2 GROUND BDI OPTION 1 4 GROUND TEER 6 GROUND 2 Vec GND 8 GROUND 10 GROUND The green LED BDI marked light up when 5V power is connected to the BDI2000 12 Vcc 5V 14 Vcc 5V Rev B C POWER Connector 1 Vcc 1 Vcc 5V 3 GROUND The green LED BDI marked light up when 5V power i
26. Supported standard Flash Memories There are currently 3 standard flash algorithm supported The AMD Intel and Atmel AT49 algorithm Almost all currently available flash memories can be programmed with one of this algorithm The flash type selects the appropriate algorithm and gives additional information about the used flash For 8bit only flash AM29F MIRROR l28BX8 AT49 For 8 16 bit flash in 8bit mode AM29BX8 MIRRORX8 I28BX8 STRATAX8 AT49X8 For 8 16 bit flash in 16bit mode AM29BX16 MIRRORX16 I28BX16 STRATAX16 AT49X16 For 16bit only flash AM29BX16 28BX16 AT49X16 For 16 32 bit flash in 16bit mode AM29DX16 For 16 32 bit flash in 32bit mode AM29DX32 For 32bit only flash M58X32 The AMD and AT49 algorithm are almost the same The only difference is that the AT49 algorithm does not check for the AMD status bit 5 Exceeded Timing Limits Only the AMD and AT49 algorithm support chip erase Block erase is only supported with the AT49 algorithm If the algorithm does not support the selected mode sector erase is performed If the chip does not support the selected mode erasing will fail The erase command sequence is different only in the 6th write cycle Depending on the selected mode the following data is written in this cycle see also flash data sheets 0x10 for chip erase 0x30 for sector erase 0x50 for block erase To speed up programming of Intel Strata Flash and AMD MirrorBit Flash an additional algorithm is imp
27. ace in internal SRAM CHIPTYPE STA2051 STA2051 internal flash CHIPSIZE 0x40000 256k internal program flash BUSWIDTH 32 select 32 for this flash FILE Ssta2051b0 bin The file to program FORMAT BIN 0x40000000 ERASE OXOOOOOOFF erase all sectors of bank 0 ST30F7xx Internal Flash The ST30F7xx flash is handled like the STA2051 flash The only difference is that there exists only flash bank 0 but with 12 sectors ERASE OXOOOOOFFF erase all sectors of bank 0 ADuC7000 Internal Flash The BDI2000 supports programming of the ADuC7000 internal flash As second parameter for the ERASE command PAGE default or MASS can be entered Following a configuration example FLASH WORKSPACE 0x00010020 workspace in internal SRAM CHIPTYPE ADUC7000 ADuUC7000 internal flash CHIPSIZE 0x10000 764k internal program flash BUSWIDTH 16 select 16 for this flash FILE E temp aduc8k bin FORMAT BIN 0x00080000 ERASE 0x88000 erase page ERASE 0x88200 erase page ERASE 0x88400 erase page ERASE 0x88600 erase page Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 37 AT91SAMZS Internal Flash The BDI2000 supports programming of the Atmel AT91SAM7S internal flash Before using any flash function it is important that the MC_FMR is programmed with the correct values for FMCN and FWS This can be done via the initialization list Followi
28. cement Microfuse MSF 1 6 AF 1 1 Unplug the cables Swiss Made M BDI2000 Alaton AG F 2 1 Remove the two plastic caps that cover the screws on target front side e g with a small knife 2 2 Remove the two screws that hold the front panel BDI OPTION BDI MAIN BDI TRGT MODE 3 1 While holding the casing remove the front panel and the red elastig sealing casing NS elastic sealing front panel Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 56 4 1 While holding the casing slide carefully the print in position as shown in figure below m Jumper settings o E o om DEFAULT INIT MODE Fuse Position Fuse Position Rev B C Rev A Pull out carefully the fuse and replace it 7 Type Microfuse MSF 1 6AF Manufacturer Schurter Reinstallation 5 1 Slide back carefully the print Check that the LEDs align with the holes in the back panel 5 2 Push carefully the front panel and the red elastig sealing on the casing Check that the LEDs align with the holes in the front panel and that the position of the sealing is as shown in the figure below casing
29. communication port Com 1 Com 4 is selected Problem No working with the target system loading firmware is ok Possible reasons e Wrong pin assignment BDM JTAG connector of the target system see chapter 2 e Target system initialization is not correctly gt enter an appropriate target initialization list e An incorrect IP address was entered BDI2000 configuration BDM JTAG signals from the target system are not correctly short circuit break e The target system is damaged Problem Network processes do not function loading the firmware was successful Possible reasons e The BDI2000 is not connected or not correctly connected to the network LAN cable or media converter e An incorrect IP address was entered BDI2000 configuration Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 55 B Maintenance The BDI needs no special maintenance Clean the housing with a mild detergent only Solvents such as gasoline may damage it If the BDI is connected correctly and it is still not responding then the built in fuse might be damaged in cases where the device was used with wrong supply voltage or wrong polarity To exchange the fuse or to perform special initialization please proceed according to the following steps A ks Observe precautions for handling Electrostatic sensitive device Unplug the cables before opening the cover Use exact fuse repla
30. d The BDI needs to know which opcode GDB uses to set a breakpoint By default a pattern of OxE7FFDEFFE is as sumed If a GDB build uses a different pattern the cor rect opcode patter has to be specified here If your GDB version supports Z packets then it is recommended to define the pattern OxDFFFDFFF This pattern allows to debug mixed ARM Thumb applications Note For ARM9E cores the BKPT instruction is always used for software breakpoints BREAKMODE HARD BREAKMODE SOFT Oxdfffdfff This parameter defines how single step instruction step is implemented The alternate step mode HWBP may be useful when stepping instruc tions should not enter exception handling JTAG HWBP Example This is the default mode For ARM9 targets the JTAG single step feature is used For ARM7 targets a range breakpoint that excludes the current instruction is used In this mode a hardware breakpoint on the next instruc tion s is used to implement single stepping STEPMODE HWBP If a workspace is defined the BDI uses a faster download mode via the ARM s Debugger Communications Channel DCC The workspace is used for a short code sequence that reads from the DDC and writes to memory There must be at least 32 bytes of RAM available for this code There is no handshake between the BDI and the code consuming the data transferred via DCC If the helper code on the target executes to slow this download mode may fail and you have to disable it
31. d address and data reg isters of indirect memory mapped registers The address of a IMMn regis ter is first written to addr and then the register value is access using data as address addr the address of the Address register data the address of the Data register Example DMM1 0x04700000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bd for GNU Debugger BDIZ000 ARM User Manual 47 Example for a register definition AT91M40400 Entry in the configuration file REGS DMM1 0x04700000 Internal Memory Map Base Address FILE E bdi reg40400 def The register definition file The register definition file name type addr size r r External Bus Interface EBI Registers csr0 OxFFE0000032 csrl OxFFE0000432 csr2 OxFFE0000832 csr3 OxFFE0O000c32 csr4 OxFFE0001032 csr5 OxFFE0001432 csr6 M OxFFE0001832 csr7 M OxFFEO001c32 rer M OxFFE0002032 mcr M OxFFE0002432 Now the defined registers can be accessed by name via the Telnet interface BDI gt rd csr0 BDlI rm csr0 0x01002535 Example for CP15 register definition ARM720T r id CP15 0x0000 32 control CP1S 0x0001 32 ttb CP15 0x0002 32 dac CP15 0x0003 32 fsr CP15 0x0005 32 far CP15 0x0006 32 iide CP15 0x0007 32 invalidate ID cache itlb CP15 0x0008 32 invalidate TLB itibs CP15 0x2008 32 jinvalidate TIB single entry pid CP15 0x000d 32 process identifier Copyright 1997 20
32. e SCANINIT and SCANPOST configuration commands Both accept a string that de fines the JTAG sequences to execute The following example shows how to use these commands Configure ICEPick module to make ARM926 TAP visible SCANINIT t1 w1000 t0 w1000 toggle TRST SCANINIT i6 07 qd8 89 i6 02 connect and select router SCANINIT d32 81000082 set IP control SCANINIT d32 a018206f configure TAPO SCANINIT Ad32 a018216f c15 enable TAPO clock 5 times in RTI SCANINIT 110 ffff scan bypass i Between SCANINIT and SCANPOST the ARM ICEBreaker is configured and the DBGRQ bit in the ARM debug control register is set r SCANPOST 110 002f IP router ARM bypass SCANPOST A33 0102000106 IP control SysReset SCANPOST i10 ffff scan bypass The following low level JTAG commands are supported in the string Use between commands I lt n gt lt b2b1b0 gt write IR bO is first scanned D lt n gt lt b2b1b0 gt write DR bO is first scanned n the number of bits 1 256 bx a data byte two hex digits W lt n gt wait for n decimal micro seconds TI assert TRST TO release TRST R1 assert RESE RO release RESET CH lt n gt clock TCK n decimal times with TMS high CL lt n gt clock TCK n decimal times with TMS low The following diagram shows the parts of the standard reset sequence that are replaced with the SCAN string Only the appropriate part of the reset seque
33. er defi nition file and information for different registers type has to be defined in the configuration file The register name type address offset number and size are defined in a separate register definition file This way you can create one register definition file for a specific target processor that can be used for all possible positions of the internal memory map You only have to change one entry in the configuration file An entry in the register definition file has the following syntax name type addr size name The name of the register max 12 characters type The register type GPR General purpose register CP15 Coprocessor 15 register MM Absolute direct memory mapped register DMM1 DMM4 Relative direct memory mapped register IMM1 1MM4 Indirect memory mapped register addr The address offset or number of the register size The size 8 16 32 of the register The following entries are supported in the REGS part of the configuration file FILE filename The name of the register definition file This name is used to access the file via TFTP The file is loaded once during BDI startup filename the filename including the full path Example FILE C bdi regs reg40400 def DMMnh base This defines the base address of direct memory mapped registers This base address is added to the individual offset of the register base the base address Example DMM1 0x01000 IMMn addr data This defines the addresses of the memory mappe
34. estored ERASE Oxfc101000 PAGE erase page 1 ERASE Oxfc102000 PAGE erase page 2 ERASE Oxfc103000 PAGE erase page 3 ERASE Oxfcl100000 MASS mass erase security byte will be restored LPC2000 Internal Flash The LPC2100 LPC2000 internal flash is programmed using the LPC2100 built in flash program ming driver via the so called IAP Commands Details about the IAP commands you find in the LPC2100 user s manual This driver needs the current System Clock Frequency CCLK in KHz This frequency has to be provided via the CHIPTYPE parameter CHIPTYPE LPC2000 lt fsys kHz gt CHIPTYPE LPC2000 14745 select LPC2100 flash fsys 14 745MHz The erase parameter has a different meaning It is not an address but a bit map of the sectors to erase bit erase sector 0 bit1 erase If you add BLANK after the sector map then a blank check is executed after the erase Following some examples ERASE OXOOOOOOFO BLANK erase sector 4 7 with blank check ERASE OXOOOO7FFF BLANK erase sector 0 14 with blank check ERASE 0x00000002 erase only sector 1 no blank check The BDI needs also a workspace of 2k bytes in the internal SRAM It is used to store the data to program and to create a context from which the flash drivers can be called FLASH CHIPTYPE PC2000 14745 select LPC2100 flash fsys 14 745MHz CHIPSIZE 0x20000 128k internal flash WORKSPACE 0x40001000
35. h For example clearing all lock bits of an Intel J3 Strata flash takes up to 0 7 seconds If unlock is used without any parameter all sectors in the erase list with the UNLOCK option are processed To clear all lock bits of an Intel J3 Strata flash use for example BDI gt unlock OxFF000000 1000 To erase or unlock multiple continuos flash sectors blocks of the same size the following Telnet commands can be used ERASE lt addr gt lt step gt lt count gt UNLOCK lt addr gt lt step gt lt count gt addr This is the address of the first sector to erase or unlock step This value is added to the last used address in order to get to the next sec tor In other words this is the size of one sector in bytes count The number of sectors to erase or unlock The following example unlocks all 256 sectors of an Intel Strata flash 28F256K3 that is mapped to 0x00000000 In case there are two flash chips to get a 32bit system double the step parameter BDI gt unlock 0x00000000 0x20000 256 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 40 3 2 5 Part REGS In order to make it easier to access target registers via the Telnet interface the BDI can read ina register definition file In this file the user defines a name for the register and how the BDI should access it e g as memory mapped memory mapped with offset The name of the regist
36. he host and the target Target System JTAG Interface UNIX PC Host BDl2000 GNU Debugger GDB Ethernet 10 BASE T 1 1 BDI2000 The BDI2000 is the main part of the bdiGDB system This small box implements the interface be tween the JTAG pins of the target CPU and a 10Base T ethernet connector The firmware and the programable logic of the BDI2000 can be updated by the user with a simple Windows Linux config uration program The BDI2000 supports 1 8 5 0 Volts target systems 3 0 5 0 Volts target systems with Rev A B Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual e 1 2 BDI Configuration As an initial setup the IP address of the BDI2000 the IP address of the host with the configuration file and the name of the configuration file is stored within the flash of the BDI2000 Every time the BDI2000 is powered on it reads the configuration file via TFTP Following an example of a typical configuration file bdiGDB configuration file for ARM PID7T board r r INIT WM32 0x0B000020 0x00000000 Clear Reset Map r TARGET CPUTYPE ARM7TDMI CLOCK 1 JTAG clock 0 Adaptive 1 8MHz 2 4MHz ENDIAI LITTLE memory model LITTLE BIG VECTOR CATCH catch unhandled exceptions
37. he two Telnet com mands that are used to access CP15 registers RDCP lt number gt display control processor 15 register RMCP lt number gt lt value gt modify control processor 15 register The parameter number selects the CP15 register This parameter has a special numbering scheme which depends of the ARM CPU type More information is also found in the ARM documentation ARM710T ARM720T ARM740T The 16bit register number is used to build the appropriate MCR MRC instruction to access the CP15 register opc_2 0 CRm 000 O nbr Normally opc 2 and CRm are zero and therefore you can simply enter the CP15 register number In the register definition file reg720t def you will find some examples ARM920T Via JTAG CP 15 registers are accessed either direct physical access mode or via interpreted MCR MRC instructions Read also ARM920T manual part Debug Support Scan Chain 15 Register number for physical access mode bit 12 0 O 0 OJO 0 O OJilO O O x nbr The bit i selects the instruction cache scan chain bit 33 the bit x extends access to register 15 scan chain bit 38 Register number for interpreted access mode bit 12 1 lopc 211 CRm opc_1 0 nbr The 16bit register number is used to build the appropriate MCR MRC instruction ARM940T ARM946E ARM966E The CP15 registers are directly accessed via JTAG
38. iGDB User manual This name is transmitted to the TFTP server when reading the configuration file Click on this button to store the configuration in the BDI2000 flash memory 2 5 3 Recover procedure In rare instances you may not be able to load the firmware in spite of a correctly connected BDI error of the previous firmware in the flash memory Before carrying out the following procedure check the possibilities in Appendix Troubleshooting In case you do not have any success with the tips there do the following e Switch OFF the power supply for the BDI and open the unit as described in Appendix Maintenance e Place the jumper in the INIT MODE position e Connect the power cable or target cable if the BDI is powered from target system ees areas i iem e Switch ON the power supply for the BDI again and wait untilthe q INIT MODE LED MODE blinks fast P Me e Turn the power supply OFF again N DEFAULT e Return the jumper to the DEFAULT position e Reassemble the unit as described in Appendix Maintenance Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bd for GNU Debugger BDIZ000 ARM User Manual 27 2 6 Testing the BDI2000 to host connection After the initial setup is done you can test the communication between the host and the BDI2000 There is no need for a target configuration file and no TFTP
39. impossible In that case the TRST driver type can be changed to push pull Then the BDI actively drives also high level type OPENDRAIN default PUSHPULL Example TRST PUSHPULL Drive TRST also high Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 28 STARTUP mode runtime This parameter selects the target startup mode The following modes are supported RESET This default mode forces the target to debug mode im mediately out of reset No code is executed after reset STOP In this mode the BDI lets the target execute code for runtime milliseconds after reset This mode is useful when monitor code should initialize the target system RUN After reset the target executes code until stopped by the Telnet halt command Example STARTUP STOP 3000 let the CPU run for 3 seconds WAKEUP time This entry in the init list allows to define a delay time in ms the BDI inserts between releasing the reset line and starting communicating with the tar get This delay is necessary when a target needs some wake up time after a reset e g Cirrus EP7209 time the delay time in milliseconds Example WAKEUP 3000 insert 3sec wake up time BDIMODE mode param This parameter selects the BDI debugging mode The following modes are supported LOADONLY Loads and starts the application code No debugging via JTAG interface AGENT The debug agent runs within the BDI There is no need f
40. information about TFTP use man tftpd root LINUX_1 bdisetup bdisetup c p dev ttySO b57 N gt lt 1151 120 25 101 N gt h151 120 25 118 N gt feval7t cnft Connecting to BDI loader Writing network configuration Writing init list and mode Configuration passed 5 Check configuration and exit loader mode The BDI is in loader mode when there is no valid firmware loaded or you connect to it with the setup tool While in loader mode the Mode LED is flashing The BDI will not respond to network requests while in loader mode To exit loader mode the bdisetup v s can be used You may also power off the BDI wait some time 1min and power on it again to exit loader mode root LINUX_1 bdisetup bdisetup v p dev ttyS0O b57 s BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware V1 03 bdiGDB for ARM Logic V1 02 ARM MAC 00 Oc 01 92 15 21 IP Addr 151 120 25 101 Subnet t 259 2052295 259 Gateway 255 255 255 255 Host IP 151 120 25 118 Config eval7t cnf The Mode LED should go off and you can try to connect to the BDI via Telnet root LINUX_1 bdisetup telnet 151 120 25 101 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 AR for GNU Debugger BDIZ000 ARM User Manual 19 2 5 2 Configuration with a Windows host First make sure that the BDI is properly connected see Chapter 2 1 to 2 4 A To avoid data line conflicts the BDI2000 must be discon
41. internal SRAM for buffer code and stack FILE E cygwin home bdidemo arm lpc2100 bin FORMAT BIN 0x00000000 ERASE OXOOOOT7FFF BLANK erase sector 0 14 with blank check For LPC213x LPC214x define always 0x80000 as CHIPSIZE independent of the actual implement ed flash memory size Based on this CHIPSSIZE the BDI selects the correct sector table FLASH CHIPTYPE PC2000 12000 select LPC2100 flash fsys 12 000 MHz CHIPSIZE 0x80000 select LPC213x 4x sector layout WORKSPACE 0x40001000 internal SRAM for buffer code and stack FILE E cygwin home bdidemo arm mcb2130 bin FORMAT BIN 0x00000000 ERASE OxOO7FFFFF BLANK erase sector 0 26 with blank check Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 36 STA2051 STR710F Internal Flash For the STA2051 STR710F internal flash the BDI assumes the following structure of the address 14 bit 2 bit 8 bit 8 bit reserved bank 1 reserved bank 0 Select the sectors to erase by setting the appropriate bit in the bankO or bank1 field You can only set bits in one bank at the same time It is not possible to erase both banks in one step Following some examples ERASE 0x00000080 erase sector BOF7 ERASE OXOOOOOOFF erase all sectors of bank 0 ERASE 0x00030000 erase all sectors of bank 1 FLASH WORKSPACE 0x20000000 worksp
42. is used to access the startup code via TFTP filename the filename including the full path Example FILE F gdb target config pid7t startup hex FORMAT format The format of the startup file Currently COFF S Record a out Binary and ELF file formats are supported If the startup code is already stored in ROM on the target select ROM as the format format COFF SREC AOUT BIN ELF or ROM Example FORMAT COFF START address The address where to start the startup code If this value is not defined and the core is not in ROM the address is taken from the code file If this value is not defined and the core is already in ROM the PC will not be set before starting the code address the address where to start the startup code Example START 0x10000 Note If an init list and a startup code file are present the init list is processed first and then the startup code is loaded and executed Therefore it is possible first to enable some RAM with the init list before the startup code is loaded and executed INIT WM32 OXOBOOOO20 Ox00000000 Clear Reset Map FILE d gdb bdi startup hex FORMAT SREC START 0x100 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 27 3 2 2 Part TARGET The part TARGET defines some target specific values CPUTYPE type This value gives the BDI information about the connected CPU type The CPU type from the following list ARM7TDMI ARM7DI A
43. lects SOFT as the breakpoint mode BREAKMODE SOFT SOFT or HARD HARD uses hardware breakpoints All the time the application is suspended i e caused by a breakpoint the target processor remains in debug mode 3 2 Configuration File The configuration file is automatically read by the BDI2000 after every power on The syntax of this file is as follows comment part name core identifier parameterl parameter2 parameterN comment core identifier parameterl parameter2 parameterN part name core identifier parameterl parameter2 parameterN core identifier parameterl parameter2 parameterN etc Numeric parameters can be entered as decimal e g 700 or as hexadecimal 0x80000 The core is optional If not present the BDI assume core 0 See also chapter Multi Core Support Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 bd for GNU Debugger BDIZ000 ARM User Manual 24 3 2 1 Part INIT The part INIT defines a list of commands which should be executed every time the target comes out of reset The commands are used to get the target ready for loading the program file WGPR register value Write value to the selected general purpose register register the register number 0 15 value the value to write into the register Example WGPR 0 5 WREG name value Write value to the selected CPU register by name name the register name CPSR value the value to write into
44. lemented that makes use of the write buffer This algorithm needs a workspace otherwise the standard Intel AMD algorithm is used The following table shows some examples Chipsize Am29F010 AM29F 0x020000 Am29F800B AM29BX8 AM29BX16 0x100000 Am29DL323C AM29BX8 AM29BX16 0x400000 Am29PDL128G AM29DX16 AM29DX32 0x01000000 Intel 28F032B3 I28BX8 0x400000 Intel 28F640J3A STRATAX8 STRATAX16 0x800000 Intel 28F320C3 I28BX16 0x400000 AT49BV040 AT49 0x080000 AT49BV1614 AT49X8 AT49X16 0x200000 M58BW016BT M58X32 0x200000 SST39VF160 AT49X16 0x200000 Am29LV320M MIRRORX8 MIRRORX16 0x400000 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 39 Note Some Intel flash chips e g 28F800C3 28F160C3 28F320C3 power up with all blocks in locked state In order to erase program those flash chips use the init list to unlock the appropriate blocks WM16 OXFFFOOOOO 0x0060 unlock block 0 WM16 OxFFF00000 0x00D0 WM16 OxFFF 10000 0x0060 unlock block 1 WM16 OxFFF10000 0x00D0 WM16 OXFFFOOOOO OxFFFF select read mod or use the Telnet Unlock command UNLOCK lt addr gt lt delay gt addr This is the address of the sector block to unlock delay A delay time in milliseconds the BDI waits after sending the unlock com mand to the flas
45. me use relative names For example bdi mpc750 cfg accesses C tftp bdi mpc750 cfg You may enter the TFTP server into the Startup group so the server is started every time you logon Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 22 3 Using bdiGDB 3 1 Principle of operation The firmware within the BDI handles the GDB request and accesses the target memory or registers via the JTAG interface There is no need for any debug software on the target system After loading the code via TFTP debugging can begin at the very first assembler statement Whenever the BDI system is powered up the following sequence starts initial configuration valid no activate BDI2000 loader Get configuration file via TFTP Power OFF Process target init list Load program code via TFTP and set the PC RUN selected Start loaded program code Process GDB reguest Power OFF Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 23 Breakpoints There are two breakpoint modes supported One of them SOFT is implemented by replacing appli cation code with a special pattern The other HARD uses the built in breakpoint logic If HARD is used only up to 2 breakpoints can be active at the same time The following example se
46. n can be directly connected In order to ensure reliable operation of the BDI EMC runtimes etc the target cable length must not exceed 20 cm 8 LT 44141411117 20 pin Multi ICE 1 19 4 4 Connector gt UENEN 1 Vcc Target Target System BEEBE 14141114 2 20 ay 1 13 14 pin Target 5 TDI gt HuEEEE lt Connector TENERE 1 Vcc Target 7 TMS 5 14 2 GROUND 8 GROUND 3 TRST 9 TCK 4 GROUND 10 GROUND 5 TDI 7 TMS 13 TDO BDI MAIN 9 TCK 15 RESET 11 TDO 12 RESET The green LED TRGT marked light up when target is powered up Rev B C GEREIS SELLE 20 pin Multi ICE 1 19 ig Connector LI 1 Vcc Target a Target System 444 3 TRST 1 13 20 gt rarer lt mapa EE 5 TDI EENEN onnector T J 1 Vcc Target 7 TMS K 2 GROUND 8 GROUND Po 3 TRST 9 TCK BDlzo00 4 GROUND 10 GROUND 5 TDI TARGET A 7 TMS 13 TDO 9 TCK 15 RESET 11 TDO 12 RESET The green LED TRGT marked light up when target is powered up For BDI MAIN TARGET A connector signals see table on next page Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 7 BDI MAIN TARGET A Connector Signals Describtion reserved This pin is currently not used JTAG Test Reset This open drain pu
47. nce is replaced If only a SCANINIT string is defined then the standard post sequence is still executed If reset mode hard Assert reset Toggle TRST Execute SCANINIT string If reset mode hard Delay for reset time Check if Bypass register s present Read and display ID code Check if CEBreaker is accessible If startup reset Set DBGRQ bit If reset mode hard Release reset Wait until reset is really release Execute SCANPOST string Delay for wake up time Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 32 3 2 3 Part HOST The part HOST defines some host specific values IP ipaddress The IP address of the host ipaddress the IP address in the form xxx xxx xxXX XXX Example IP 151 120 25 100 FILE filename The default name of the file that is loaded into RAM using the Telnet load command This name is used to access the file via TFTP If the filename starts with a this is replace with the path of the configuration file name filename the filename including the full path or for relative path Example FILE F gnu demo arm test elf FILE test elf FORMAT format offset The format of the image file and an optional load address offset If the im age is already stored in ROM on the target select ROM as the format The optional parameter offset is added to any load address read from the im age file
48. nected from the target system while programming the logic for an other target CPU see Chapter 2 1 1 BDI2000 Update Setup r Connect BDI2000 Loader Channel SN 95111242 C Port COM2 MAC 000C01951112 Speed 115200 r BDI2000 Firmware Logic Current Newest Current Loader 1 05 Erase Firmware 1 18 1 18 Em Logic 1 06 1 06 Update F Configuration BDI IP Address 151 120 25 101 Subnet Mask 255 255 255 255 Default Gateway 255 255 255 255 Config Host IP Address 151 120 25 119 Configuration file JEcygwin home bdidemo arm eval t cfg Cancel Ok Transmit Writing setup data passed dialog box BDI2000 Update Setup Before you can use the BDI2000 together with the GNU debugger you must store the initial config uration parameters in the BDI2000 flash memory The following options allow you to do this Channel Baudrate Connect Current Update Select the communication port where the BDI2000 is connected during this setup session Select the baudrate used to communicate with the BDI2000 loader during this setup session Click on this button to establish a connection with the BDI2000 loader Once connected the BDI2000 remains in loader mode until it is restarted or this dialog box is closed Press this button to read back the current loaded BDI2000 software and logic versions The current loader firmware and logic version will be displayed This button is
49. ng a configuration example INIT WM32 OxFFFFFD44 0x00008000 Disable watchdog WM32 OxFFFFFD08 OxA5000001 Enable user reset i Setup PLL WM32 OxFFFFFC20 0x00000601 CKGR MOR Enabling the Main Oscillator DELAY 20 WM32 OxFFFFFC2C 0x1l0480a0e CKGR_PLLR 96 1MHz DIV 14 MUL 72 1 DELAY 20 WM32 OxFFFFFC30 0x00000007 PMC_MCKR MCK PLL 2 48MHz DELAY 20 i Setup Internal Flash for 48MHz Master Clock WM32 OxFFFFFF60 0x00300100 MC_FMR Flash mode FWS 1 FMCN 48 r TARGET CPUTYPE ARM7TDMI CLOCK diy JTAG clock start with a slow clock RESET HARD 300 Assert reset line for 300 ms BREAKMODE HARD SOFT or HARD STEPMODE HWBP FLASH CHIPTYPE AT91SAM7S Don t forget to set MC_FMR FMCN and MC_FMR FWS CHIPSIZE 0x10000 The AT91SAM7S64 has 64kB internal flash BUSWIDTH 32 Use 32 bit for AT91SAM7S FILE at91 sam7s bin FORMAT BIN 0x00100000 An explicit erase is not necessary because a page is automatically erased during programming But the BDI2000 supports also erasing a page or the complete flash memory The ERASE command supports a second parameter PAGE default or CHIP can be used A page is erased by program ming it with all OxFF Following an example how to erase the complete flash via Telnet BDI gt erase 0x00100000 chip Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 ldi for GNU Debugger BDIZ000 ARM User Manual 38
50. nt and shall not encompass any other damages includ ing but not limited loss of profit special incidental consequential or other similar claims ABATRON Switzerland specifically disclaims all other warranties expressed or implied including but not limited to implied warranties of merchantability and fitness for particular purposes with respect to defects in the diskette cable BDI2000 and documentation and the program license granted here in including without limitation the operation of the program with respect to any particular application use or purposes In no event shall ABATRON be liable for any loss of profit or any other commercial damage including but not limited to special incidental consequential or other damages Failure in handling which leads to defects are not covered under this warranty The warranty is void under any self made repair operation except exchanging the fuse Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 54 Appendices A Troubleshooting Problem The firmware can not be loaded Possible reasons e The BDI is not correctly connected with the target system see chapter 2 e The power supply of the target system is switched off or not in operating range 4 75 VDC 5 25 VDC gt MODE LED is OFF or RED e The built in fuse is damaged gt MODE LED is OFF e The BDI is not correctly connected with the Host see chapter 2 e A wrong
51. nual 16 2 5 Installation of the Configuration Software On the enclosed diskette you will find the BDI configuration software and the firmware required for the BDI2000 For Windows NT users there is also a TFTP server included The following files are on the diskette b20armgd exe Windows configuration program b20armgd hlp Windows help file for the configuration program b20armgd xxx Firmware for the BDI2000 armjed20 xxx JEDEC file for the BDI2000 Rev A B logic device armjed21 xxx JEDEC file for the BDI2000 Rev C logic device tftpsrv exe TFTP server for WindowsNT Windows95 WIN32 console application cfg Configuration files def Register definition files bdisetup zip ZIP Archive with the Setup Tool sources for Linux UNIX hosts Overview of an installation configuration process e Create a new directory on your hard disk e Copy the entire contents of the enclosed diskette into this directory e Linux only extract the setup tool sources and build the setup tool e Use the setup tool to load update the BDI firmware logic Note A new BDI has no firmware logic loaded e Use the setup tool to transmit the initial configuration parameters IP address of the BDI IP address of the host with the configuration file Name of the configuration file This file is accessed via TFTP Optional network parameters subnet mask default gateway Activating BOOTP The BDI can get the network configuration and the name of the
52. ol 4 BDl2000 2SooN QO 13 TDO 15 RESET The green LED TRGT marked light up when target is powered up For TARGET B connector signals see table on next page Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 70 BDI TARGET B Connector Signals TDO Describtion JTAG Test Data Out This input to the BDI2000 connects to the target TDO line reserved TDI JTAG Test Data In This output of the BDI2000 connects to the target TDI line reserved RTCK Returned JTAG Test Clock This input to the BDI2000 connects to the target RTCK line Vcc Target 1 8 5 0V This is the target reference voltage It indicates that the target has power and it is also used to create the logic level reference for the input comparators It also controls the output logic levels to the target It is normally fed from Vdd I O on the target board 3 0 5 0V with Rev A B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less JTAG Test Clock This output of the BDI2000 connects to the target TCK line JTAG Test Reset This open drain push pull output of the BDI2000 resets the JTAG TAP controller on the target Default driver type is open drain JTAG Test Mode
53. ols V1 0 break code 0 DCC 8 DCC I O via TCP port 8 1 CPUTYPE ARM7TDMI 1 SCANPRED 14 JTAG devices connected before this core 1 SCANSUCC 00 JTAG devices connected after this core 1 VECTOR CATCH catch unhandled exceptions 1 BREAKMODE SOFT Oxef180000 SOFT or HARD X Tools V1 0 break code 1 DCC 7 DCC I O via TCP port 7 For a complete configuration example see eb63_eval7t cfg on the diskette This configuration was used to debug an AT91EB63 daisy chained with an Evaluator 7T board Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 51 4 Specifications Operating Voltage Limiting Power Supply Current RS232 Interface Baud Rates Data Bits Parity Bits Stop Bits Network Interface Serial Transfer Rate between BDI and Target Supported target voltage Operating Temperature Storage Temperature Relative Humidity noncondensing Size Weight without cables Host Cable length RS232 5 VDC 0 25 V typ 500 mA max 1000 mA 9 600 19 200 38 400 57 600 115 200 8 none 1 10 BASE T up to 16 Mbit s 1 8 5 0 V 3 0 5 0 V with Rev A B 5 60 C 20 C 65 C lt 90 rF 190 x 110 x 35 mm 420g 2 5m Specifications subject to change without notice Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 52 5 Environmental notice N es Disposal of
54. on as the appropriate Watchpoint Control register is written to This way the debugger or the user via Telnet has full access to all features of this watchpoint hardware When setting a watchpoint use the following register numbers The values will be written to the lceBreaker immediately before a target restart 100 Watchpoint 0 Address Value 110 Watchpoint 1 Address Value 101 Watchpoint 0 Address Mask 111 Watchpoint 1 Address Mask 102 Watchpoint 0 Data Value 112 Watchpoint 1 Data Value 103 Watchpoint 0 Data Mask 113 Watchpoint 1 Data Mask 104 Watchpoint 0 Control Value 114 Watchpoint 1 Control Value 105 Watchpoint 0 Control Mask 115 Watchpoint 1 Control Mask Example BDI gt rmib 100 0x00104560 3 3 4 GDB monitor command The BDI supports the GDB V5 x monitor command Telnet commands are executed and the Telnet output is returned to GDB gdb target remote bdi2000 2001 Remote debugging using bdi2000 2001 0x10b2 in start gdb monitor md 0 1 00000000 Oxe59f 018 442503144 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 44 3 3 5 Target serial I O via BDI A RS232 port of the target can be connected to the RS232 port of the BDI2000 This way it is possible to access the target s serial VO via a TCP IP channel For example you can connect a Telnet session to the appropriate BDI2000 port Connecting GDB to a GDB server stub running on
55. or any debug software on the target This mode accepts a second parameter If RUN is entered as a second pa rameter the loaded application will be started immedi ately otherwise only the PC is set and BDI waits for GDB requests Example BDIMODE AGENT RUN ENDIAN format This entry defines the endiannes of the memory system format The endiannes of the target memory LITTLE default BIG Example ENDIAN LITTLE VECTOR CATCH mask When this line is present the BDI catches exceptions For ARM7 targets or when there is no mask value present catching exceptions is only pos sible if the memory at address 0x00000000 to 0x0000001F is writable For ARM9 targets the mask is used to setup the EmbeddedlCE Vector catch register Do not define a mask for ARM7 targets mask ARM9 only selects the exceptions to catch Example VECTOR CATCH catch all unhandled exception VECTOR CATCH OX1F catch Abort SWI Undef Reset Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 29 BREAKMODE mode opc This parameter defines how breakpoints are implemented and optional the GDB breakpoint opcode See also 3 3 3 Breakpoint Handling mode SOFT This is the normal mode Breakpoints are implemented STEPMODE mode WORKSPACE address by replacing code with a special pattern mode HARDIn this mode the breakpoint hardware is used Only 2 opc Example breakpoints at a time are supporte
56. ord 16bit from the selected memory place address the memory address Example RM16 0x00000000 Read a word 32bit from the selected memory place address the memory address Example RM32 0x00000000 Because a memory access to an invalid memory space via JTAG leads to a deadlock this entry can be used to define up to 32 valid memory ranges If at least one memory range is defined the BDI checks against this range s and avoids accessing of not mapped memory ranges start the start address of a valid memory range end the end address of this memory range Example MMAP OxFFEQ0000 OxFFFFFFFF Boot ROM Delay for the selected time value the delay time in milliseconds 1 30000 Example DELAY 500 delay for 0 5 seconds Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 26 Using a startup program to initialize the target system For targets where initialization can not be done with a simple initialization list there is the possibility to download and execute a special startup code The startup code must be present in a file on the host The last instruction in this startup code should be a SWI After processing the initlist the BDI downloads this startup code to RAM starts it and waits until it completes If there is no SWI instruc tion in the startup code the BDI terminates it after a timeout of 5 seconds FILE filename The name of the file with the startup code This name
57. r the CFMCLKD register used during the JTAG lockout recovery Calculate this entry based on the reset system frequency PLL disabled RECOVER 19 CLKD for 8 MHz system clock Example for the ARM PID7T board AM29F010 in U12 FLASH WORKSPACE CHIPTYPE CHIPSIZE BUSWIDTH FILE ERASE ERASE ERASE ERASE ERASE ERASE 0x000 AM2 9F 0x200 8 00000 00 Workspace in target RAM for faster programming algorithm Flash type C gdb pid7t boot rom hex 0x04 0x04 0x04 0x04 0x04 0x04 00000 04000 08000 oc000 10000 14000 erase erase erase erase erase erase sector sector sector sector sector sector The size of one The width of the The file to program 0 OD LN O Q Q O 0 of flash chip in bytes e g AM29F010 0x20000 flash memory bus in bits 8 16 32 flash SIMM f flash SIMM f flash SIMM f flash SIMM f flash SIMM f flash SIMM Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 35 MAC7110 Internal Flash WORKSPACE 0x40000000 workspace in internal SRAM CHIPTYPE CFM32 8000 select Program flash fsys 8MHz CHIPSIZE 0x80000 7512k internal program flash BUSWIDTH 32 32 bit bus FILE mac7100 cfg The file to program FORMAT BIN O0xfc101000 ERASE Oxfc100000 PAGE erase page 0 security byte will be r
58. rn to write is the one defined with the BREAKMODE parameter default is OXE7FFDEFE If your GDB version make use of the Z Packet then GDB tells the BDI to set clear breakpoints with this special protocol unit The BDI will respond to this request by replacing code in memory or by set ting the appropriate hardware breakpoint The pattern used to replace memory is the one defined with the BREAKMODE parameter It is recommended to define a pattern of OXDFFFDFFF in this case because this pattern allows to debug mixed ARM Thumb applications The ARM IceBreaker supports two hardware breakpoints watchpoints For ARM7 and ARM9 one of them is used to support software breakpoints and vector catching for ARM7 targets The other can be used for a hardware breakpoint To make both available for hardware breakpoints you should se lect BREAKMODE HARD and disable vector catching For ARM9E the BKPT instruction is always used to implement software breakpoints In that case no hardware breakpoint watchpoint is used to implement software breakpoints User controlled hardware breakpoints The ARM IceBreaker has a special watchpoint hardware integrated Normally the BDI controls this hardware in response to Telnet commands BI BDx or when breakpoint mode HARD is selected Via the Telnet commands BI and BDx you cannot access all the features of the breakpoint hardware Therefore the BDI assumes that the user will control setup this watchpoint hardware as so
59. s connected to the BDI2000 Please switch on the system in the following sequence e 1 gt external power supply e 2 gt target system Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 WA for GNU Debugger BDIZ000 ARM User Manual 12 2 2 2 Power Supply from Target System The BDI2000 needs to be supplied with 5 Volts max 1A via BDI MAIN target connector Rev A or via TARGET A connector Rev B C This mode can only be used when the target system runs with 5V and the pin Vcc Target is able to deliver a current up to 1A 5V For pin description and layout see chapter 2 1 Connecting the BDI2000 to Target Insert the enclosed Jumper as shown in figure below Please ensure that the jumper is inserted correctly A For error free operation the power supply to the BDI2000 must be between 4 75V and 5 25V DC The maximal tolerable supply voltage is 5 25 VDC Any higher voltage or a wrong polarity might destroy the electronics BDI OPTION Connector BDI TRGT BDI MAIN BDI OPTION 13 14 2 C Jumper The green LEDs BDI and TRGT marked light up when target is powered up and the jumper is inserted correctly 13 Vcc Target 5V 14 Vcc BDI2000 5V POWER 3 i Connector 1 Vcc BDI2000 5V 2 Vcc Target 5V 4 Jumper POWER BDI TRGT The green LEDs BDI and TRGT marked light up when target is powered up and the
60. se list will be processed if you enter ERASE at the Telnet prompt without any parameter This list is also used if you enter UNLOCK at the Telnet without any parameters With the in crement and count option you can erase multiple equal sized sectors with one entry in the erase list address RECOVER clkd increment count mode wait Example Address of the flash sector block or chip to erase If present the address offset to the next flash sector If present the number of equal sized sectors to erase BLOCK CHIP UNLOCK Without this optional parameter the BDI executes a sec tor erase If supported by the chip you can also specify a block or chip erase If UNLOCK is defined this entry is also part of the unlock list This unlock list is processed if the Telnet UNLOCK command is entered without any parameters The wait time in ms is only used for the unlock mode Af ter starting the flash unlock the BDI waits until it pro cesses the next entry ERASE Oxff040000 erase sector 4 of flash ERASE Oxff060000 erase sector 6 of flash ERASE Oxff000000 CHIP erase whole chip s ERASE Oxff010000 UNLOCK 100 unlock wait 100ms ERASE Oxff000000 0x10000 7 erase 7 sectors If this entry is present the BDI automatically executes a JTAG lockout re covery during reset processing if the MAC7100 flash is secured Use this entry only if you really need to recover a secured a MAC7100 device clkd Example The value fo
61. server is needed on the host e If not already done connect the bdiGDB system to the network e Power up the BDI2000 e Start a Telnet client on the host and connect to the BDI2000 the IP address you entered dur ing initial configuration e If everything is okay a sign on message like BDI Debugger for ARM should be displayed in the Telnet window 2 7 TFTP server for Windows NT The bdiGDB system uses TFTP to access the configuration file and to load the application program Because there is no TFTP server bundled with Windows NT Abatron provides a TFTP server appli cation tftpsrv exe This WIN32 console application runs as normal user application not as a system service Command line syntax __ tftpsrv p w dRootDirectory Without any parameter the server starts in read only mode This means only read access request from the client are granted This is the normal working mode The bdiGDB system needs only read access to the configuration and program files The parameter p enables protocol output to the console window Try it The parameter w enables write accesses to the host file system The parameter d allows to define a root directory tftpsrv p Starts the TFTP server and enables protocol output tftpsrv p w Starts the TFTP server enables protocol output and write accesses are allowed tftpsrv dC tftp Starts the TFTP server and allows only access to files in C tftp and its subdirectories As file na
62. sh pull output of the BDI2000 resets the JTAG TAP controller on the target Default driver type is open drain System Ground JTAG Test Clock This output of the BDI2000 connects to the target TCK line JTAG Test Mode Select This output of the BDI2000 connects to the target TMS line This open collector output of the BDI2000 is used to reset the target system TDI JTAG Test Data In This output of the BDI2000 connects to the target TDI line Vcc Target 1 8 5 0V This is the target reference voltage It indicates that the target has power and it is also used to create the logic level reference for the input comparators It also controls the output logic levels to the target It is normally fed from Vdd I O on the target board 3 0 5 0V with Rev A B This input to the BDI2000 is used to detect if the target is powered up If there is a current limiting resistor between this pin and the target Vdd it should be 100 Ohm or less JTAG Test Data Out This input to the BDI2000 connects to the target TDO line The BDI2000 works also with targets which have no dedicated TRST pin For this kind of targets the BDI cannot force the target to debug mode immediately after reset The target always begins execu tion of application code until the BDI has finished programming the Debug Control Register Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 8
63. ster dump all user defined register to a file display all ARM registers display control processor 15 register display IceBreaker register modify general purpose or user defined register modify control processor 15 register modify IceBreaker register reset the BDI and reload the configuration res the target system change startup mode GO lt pc gt set PC and start current core GO lt n gt lt n gt lt n gt lt n gt start multiple cores in requested order WEL pe single step an instruction HALT lt n gt lt n gt lt n gt lt n gt force core s to debug mode n core number BI lt addr gt lt mask gt set instruction breakpoint CI lt id gt clear instruction breakpoint s BD R W lt addr gt lt data gt set data watchpoint 32bit access BDH R W lt addr gt lt data gt set data watchpoint 16bit access BDB R W lt addr gt lt data gt set data watchpoint 8bit access BDM R W lt addr gt lt mask gt set data watchpoint with address mask CD lt id gt clear data watchpoint s INFO display information about the current state LOAD lt offset gt lt file gt lt format gt load program file to target memory VERIFY lt offset gt lt file gt lt format gt verify a program file to target memory PROG lt offset gt lt file gt lt format gt program flash memory 7 lt format g
64. t SREC BIN AOUT ELF or COFF ERASE lt address gt lt mode gt erase a flash memory sector chip or block m lt mode gt CHIP BLOCK or SECTOR default is sector ERASE lt addr gt lt step gt lt count gt erase multiple flash sectors UNLOCK lt addr gt lt delay gt unlock a flash sector UNLOCK lt addr gt lt step gt lt count gt unlock multiple flash sectors FLASH lt type gt lt size gt lt bus gt FENA lt addr gt lt size gt FDIS DELAY lt ms gt SELECT lt core gt SCAN lt nbr gt lt len gt lt b2b1b0 gt HOST lt ip gt PROMPT lt string gt CONFIG change flash configuration enable autoamtic programming to flash memory disable autoamtic programming to flash memory delay for a number of milliseconds change the current core Access a JTAG scan chain DO is first scanned len the number of bits 1 256 bx a data byte two hex digits change IP address of program file host defines a new prompt string display or update BDI configuration CONFIG lt file gt lt hostIP gt lt bdiIP gt lt gateway gt lt mask gt HELP QUIT display command list terminate the Telnet session Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 48 3 4 2 CP15 Registers Via Telnet it is possible to access the Coprocessor 15 CP15 registers Following t
65. the equipment must be carried out at a designated disposal site 6 Declaration of Conformity CE CE DECLARATION OF CONFORMITY This declaration is valid for following product Type of device BDM JTAG Interface Product name BDI2000 The signing authorities state that the above mentioned equipment meets the requirements for emission and immunity according to EMC Directive 89 336 EEC The evaluation procedure of conformity was assured according to the following standards EN 50081 2 EN 50082 2 This declaration of conformity is based on the test report no QNL E853 05 8 a of QUINEL Zug accredited according to EN 45001 Manufacturer ABATRON AG St ckenstrasse 4 CH 6221 Rickenbach Authority VOL LY yew foe ne MMMM CE Max Vock Ruedi Dummermuth Marketing Director Technical Director Rickenbach May 30 1998 Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 ldi for GNU Debugger BDIZ000 ARM User Manual 53 7 Warranty ABATRON Switzerland warrants the physical diskette cable BDI2000 and physical documentation to be free of defects in materials and workmanship for a period of 24 months following the date of purchase when used under normal conditions In the event of notification within the warranty period of defects in material or workmanship ABATRON will replace defective diskette cable BDI2000 or documentation The remedy for breach of this warranty shall be limited to replaceme
66. the register Example WREG CPSR 0x600000D3 WCP15 register value Write value to the selected Coprocessor 15 register register the register number see chapter CP 15 registers value the value to write into the register Example WCP15 2 0x00004000 set Translation Base Address WMB8 address value Write a byte 8bit to the selected memory place address the memory address value the value to write to the target memory Example WM8 OxFFFFFA21 0x04 SYPCR watchdog disable WM 16 address value Write a half word 16bit to the selected memory place address the memory address value the value to write to the target memory Example WM16 0x02200200 0x0002 TBSCR WM32 address value Write a word 32bit to the selected memory place address the memory address value the value to write to the target memory Example WM32 0x02200000 0x01632440 SIUMCR WBIN address filename Write a binary image to the selected memory place The binary image is read via TFTP from the host Up to 4 such entries are supported address the memory address filename the filename including the full path Example WBIN 0x4000 pagetable bin Copyright 1997 2006 by ABATRON AG Switzerland V 1 18 VAR for GNU Debugger BDIZ000 ARM User Manual 25 RM8 address value RM16 address value RM32 address value MMAP start end DELAY value Read a byte 8bit from the selected memory place address the memory address Example RM8 0x00000000 Read a half w
67. tool on any Linux Unix host To build the tool simply start the make utility root LINUX_1 bdisetup make CC 02 c o bdisetup o bdisetup c cc 02 c o bdicnf o bdicnf c cc 02 c o bdidll o bdidll c cc s bdisetup o bdicnf o bdidll o o bdisetup 2 Check the serial connection to the BDI With bdisetup v you may check the serial connection to the BDI The BDI will respond with infor mation about the current loaded firmware and network configuration Note Login as root otherwise you probably have no access to the serial port root LINUX_1 bdisetup bdisetup v p dev ttyS0O b57 BDI Type BDI2000 Rev C SN 92152150 Loader V1 05 Firmware unknown Logic unknown MAC 00 Oc 01 92 15 21 IP Addr 255 255 255 255 Subnet 295 2590 ADA Gateway 255 255 255 255 Host IP 255 255 255 255 Config 22222222222222722 3 Load Update the BDI firmware logic With bdisetup u the firmware is loaded and the CPLD within the BDI2000 is programmed This con figures the BDI for the target you are using Based on the parameters a and t the tool selects the correct firmware logic files If the firmware logic files are in the same directory as the setup tool there is no need to enter a d parameter root LINUX_1 bdisetup bdisetup u p dev ttySO0 b57 aGDB tARM Connecting to BDI loader Erasing CPLD Programming firmware with b20armgd 103 Programming CPLD with armjed21 102

bdiGDB User Manual

Contents

Download Pdf Manuals

Related Search

Related Contents