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User Manual - ECA Services Ltd

1. mum PCIE1 TX1 P prer e PCIE1_TX3_N PCIE1_TX4_P PCIE1_TX4_N 7 EN ERE PCIE1 TX5 P PCIE1 TX5 N PCIE1 TX6 P PCIE1 TX6 N PCIE1 TX7 P PCIE1 7 PCIEO P PCIE1 P PCIE1 PCIEO RX4 P PCIE1 RX4 P PCIEO RX1 PCIE1 RX1 N PCIEO RX2 P PCIE1 RX2 P PCIEO RX2 PCIE1 RX2 N PCIEO RX3 P PCIE1 RX3 P PCIEO RX3 N PCIE1 RX3 N PCIEO RX4 P PCIE1 RX4 P PCIEO RX4 N PCIE1 RX4 N RX5 P PCIE1 RX5 P PCIEO RX5 PCIE1 RX5 N N N N E MN M PCIEO RX6 P PCIE1 RX6 P PCIEO RX6 PCIE1 RX6 N PCIEO RX7 P PCIE1 RX7 P PCIEO 7 PCIE1_RX7_N PCIEO_REF_CLK_ PCIE1 P PCIEO REF P PCIE1 P mus ew __ __ P FI3 0 FI3 TX1 P FI3 TX1 N PCIEO P PCIEO PCIEO 1 P PCIEO TX1 PCIEO TX2 PCIEO 2 PCIEO TX3 P PCIEO TX3 PCIEO TX4 P PCIEO TX4 PCIEO TX5 PCIEO TX5 PCIEO TX6 P PCIEO TX6 PCIEO TX7 P PCIEO 7 4 LED HS LED LS HPC only 2 pin out _ To T s EN PCIE1 TX1 P INN BEN s PCIE1 TX5 P _ lt M NUN ENWEN PCIE1 TX5 N PCIE1 TX6 P PCIE1 TX6 N
2. 66 37 To terminate an active IPMItool SOL session please use the key sequence tilde and dot E Note There can only be one Serial over LAN session active at once 4 9 Dynamic Power Budgeting Before the Shelf Manager can activate an ATCA blade M4 Hot Swap state it needs to check the power demand of that FRU PICMG Get Power Level IPMI command and perform power budgeting based on the power capabilities of the ATCA Shelf Instead of reporting a static and predefined value e g 300W to Shelf Manager the Advantech ATCA blade IPMC uses an intelligent mechanism to calculate its own power demand dynamically The IPMC detects the current CPU type the amount and size of populated memory DIMMs the RTM power draw if plugged and the needed FMM power if modules present Based on this data the IPMC calculate and report a power value which is representing the real power requirements of the current blade configuration Note The dynamic power budget mechanism can be enabled and disabled with the help of Advantech OEM IPMI commands default value is enabled ipmitool raw 2 0x40 0x39 0x28 0x00 0x06 0x00 0x00 4 10 MAC Address Mirroring All MAC addresses consumed by the MIC 5333 will also be stored in the FRU EEPROM making them available to be read even if the payload is not powered User can easily get all the MAC addresses via Advantech s IPMI OEM command See Appendix B OEM Comm
3. Ox40 0x39 0x28 0x00 OxOD 0 00 0 01 397228 90 Disable PROC interrupts ipmitool raw 0x40 0x39 0x28 0x00 OxOD 0 00 0x00 Ro 2 29 Ze YO B 2 6 Graceful Shutdown Timeout The IPMC provides the option to wait at system halt for the x86 part to finish the shutdown process If this procedure isn t finished within a default timeout of 60 seconds the blade payload power will be turned off immediately The value can be changed from 0 up to 255 seconds with following command Read graceful shutdown timeout value ipmitool raw 0 2 0x41 0x39 0x28 0x00 OxOE 0x01 39 28 00 lt timeout gt 5 2 Change graceful shutdown timeout ipmitool raw 0x40 0x39 0x28 0x00 OxOE 0x01 timeout og wo D 5 2 B 2 7 Temperature Failure Retry Mechanism In case of upper non recoverable temperature sensor events of payload dependent sensors e g CPU temperature the ATCA board would loop deactivation activation through the FRU states forever To prevent this a maximum number of 15 temperature failure activation retries is implemented in case such critical situations occur The retry number can be changed and disabled with following commands Read temperature failure activation retry number ipmitool raw 0x41 0x39 0x28 0x00 0x05 0x01 39 28 00 lt retries gt 5
4. A LX2F17 Intel 350 LPC1768 Bl LAN oL lo IPMC Block Zone 1 ShMC Figure 4 1 IPMC Interface Block Diagram 4 2 1 IPMB 0 Interface The IPMBO interface is the communication path between the SHMC and through Zone 1 Redundant IPMB 0 channels IPMBO A and IPMBO B provide failure safe message transfer over the backplane The IPMB address of IPMC is determined by Hardware Address pins HA 7 0 on the Zone 1 connector The manual of the chassis backplane contains information that allows relating the physical IPMB address to the slot location within the chassis The IPMC is accessible over the Shelf manager with following bridged command ipmitool lan H ShMM IP Address gt t Blade IPMB address Command Command Line Syntax lan Specifies Ethernet interface H lt ShMMIP Address gt IP address assigned to the Shelf Manager of the ATCA Chassis A none Authentication type default none t lt Blade IPMB address gt IPMC s remote PMB target address ATCA slot dependent 4 2 2 KCS The Keyboard Controller Style KCS protocol is used as IPMI system interface connection to the x86 part on the blade It s based on the Low Pin Count LPC bus and used as the local IPMC interface to BIOS and the Operating System OS on the x86 blade KCS is a fast IPMI interface compared to IPMB but is
5. Figure 3 17 Install the screws 3 4 3 RTM Optional For installation of the RTM please refer to the RTM user manual Please make sure that the RTM used in conjunction with the MIC 5333 is compliant Please contact your Advantech representative to obtain a list of compliant RTMs the current compliant RTM at the time of publication is the RTM 5106 3 4 4 Storage Optional Dual MO 297 Solid State Drive SSD modules are available to be installed on the MIC 5333 It is an option installed by customer request and the MIC 5333 will need to be installed with a specific daughter board and bracket from the factory This chapter assumes that the MIC 5333 is shipped with the storage module installed Mounting instructions are still provided here to support customer development as well as in house RMA or replacement For installation of the storage module please follow the below procedures 1 Loosen the screws as marked below and remove them on the storage module 26 2 gt Q9 63 34 1200 GOPOZY qao n W qi COSHOF YS L ys rA 2 Extract the 297 SSD gently If the user needs to remove the 2 297 as well repeat step 1 and 2 again 1000 09902 NS 3 install the 550 insert the MO 297 module until the golden fingers are firmly seated in the socket 4 Install the module on the MIC 5333 then fasten the screws To obtain a list of compliant SSDs
6. 0 Core voltage 29 CPUO 1 80 VOL Voltage CPU 0 voltage 1 80V 30 CPU1 0 85 VOL Voltage CPU 1 voltage 0 85V 31 CPU1 1 05 VOL Voltage CPU 1 voltage 1 05V CPU1 CORE VOL Voltage CPU 1 Core voltage 33 CPU1 1 80 VOL Voltage CPU 1 voltage 1 80V 34 DDR AB VOL Voltage DDR DIMM voltage 1 5V 35 DDR CD VOL Voltage DDR DIMM C D voltage 1 5V 36 DDR EF VOL Voltage DDR DIMM E F voltage 1 5V 3 DDR GH VOL Voltage DDR DIMM G H voltage 1 5V 38 V48 TMP Temperature 48V Power Input module 39 INTAKEO TMP Temperature LM75 Intake temperature s 40 POWER TMP Temperature LM7512V Power module 41 OUTLETO TMP Temperature LM75 Exhaust 0 temperature 42 OUTLET1 TMP Temperature LM75 Exhaust 1 temperature 43 CPU O TMP Temperature 0 temperature 44 CPU 1 TMP Temperature CPU 1 temperature PECI 45 CPUO DIMMO TMP Temperature DIMM temperature PECI 46 CPUO DIMM1 TMP Temperature DIMM temperature PECI 47 CPUO DIMM2 TMP Temperature DIMM temperature PECI 48 CPUO DIMM3 TMP Temperature DIMM temperature PECI 49 CPU1 DIMMO TMP Temperature DIMM temperature PECI 50 CPU1_DIMM1 TMP Temperature DIMM temperature PECI CPU1 DIMM2 TMP DIMM temperature PECI 52 CPU1_DIMM3 TMP Temperature DIMM temperature LAN IO BI TMP Temperature i350 LAN controller MEZMODULE 1 MEZMODULE2 2nd FMM FRU Device Locator only if FMM is plugged MEZMODULE3 3rd FMM FRU Device Locator
7. 0 50 event OxO9 By referring to Table 4 8 Integrity Sensor List this event can be interpreted as the RTC has been successfully synced time with the ShMM 4 5 System Event Log The IPMC supports a non volatile System Event Log SEL which stores events of onboard sensors as well as hosted FRUs such as RIM modules The SEL can hold up to 4095 SEL entries In case of a fully populated SEL System Management Software needs to clear the System Event Log Besides putting logs in local SPI Flash these events will also be delivered to the Shelf Manager with platform events via 0 interface Below is an example shows an IPMC System Event Log read using the Linux IPMItool root localhost ipmitoolselelist 09716 2012 0871672012 08 16 201 09716 201 2 2 08 16 2012 2002 08 16 201 8127 20 2 2 15 20 46 15 22 13 2211 2222 38 43 20 43 28 17 02 09 17 03 FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Hot Swap HOTSWAP FRU Transl Transl Transi Transi Transi Transi Transi Lion tion tion Lion tion tion tion to 1 to M2 to M3 to INTEGRITY OEM Specific Asserted to M6 to M1 to M2 to M3 A
8. PCIE1 TX7 P PCIE1 7 2 P PCIE1 P PCIEO RXO N PCIE1 RXO N PCIEO RX4 P PCIE1 RX4 P PCIEO RX1 PCIE1 RX1 N PCIEO RX2 P PCIE1 RX2 P PCIEO RX2 PCIE1 RX2 N PCIEO RX3 P PCIE1 RX3 P PCIEO RX3 N PCIE1 RX3 N PCIEO RX4 P PCIE1 RX4 P PCIEO 4 PCIE1 4 0 RX5 P PCIE1 RX5 P PCIEO RX5 U d d d M M CIE1 RX5 N z RX6 P PCIE1 RX6 P z PCIEO RX6 N PCIE1 RX6 N PCIE1 RX7 P PCIEO 7 PCIE1 7 PCIEO REF CLK P PCIE1 REF CLK P N N N PCIEO REF P amp FI1 LED HS PCIE1 REF CLK P LED LS RST w _ PCIEO TX5 PCIEO TX5 PCIEO TX6 P PCIEO TX6 PCIEO TX7 P PCIEO 7 4FI2 LED HS ZFI2 LED LS FMM3 pin out _ FM PRSNT PCIEO P PCIEO PCIEO RX4 P PCIEO RX1 PCIEO RX2 P PCIEO RX2 PCIEO RX3 P x PCIEO RX3 RX4 P PCIEO RX4 RX5 P RX5 PCIEO RX6 P PCIEO RX6 PCIEO RX7 P PCIEO RX7 PCIEO REF P PCIEO REF P N N N N RST m SB SCL 7 E E E E E 2 E E p m TX6 P PCIEO TX7 P PCIEO 7 E
9. PEx16 1 RTM PE16 1 10 RX PEx16 1 RTM PE16 1 3 RX PEx16 1 RTM PE16 1 11 RX Zone 3 J34 pin out PEx16 0 RTM PE16 1 O RX PEx16 0 RTM PE16 1 8 RX PEx16 0 RTM PE16 1 1 RX PEx16 0 16 1 9 RX PEx16 0 RTM PE16 1 2 RX PEx16 0 RTM PE16 1 10 RX PEx16 0 16 1 3 RX 16 0 _ 16 1 11 PEx16 1 RTM PE16 1 14 RX PEx16 1 RTM PE16 1 7 RX 16_1 _ 16 1 15 RX PEx16 0 RTM PE16 1 4 RX PEx16 0 16 1 12 RX PEx16 0 RTM PE16 1 5 RX 16 0 16 1 13 16 0 _ 16 1 6 16 0 RTM 16 1 14 16 0 _ 16 1 7 RX PEx16 0 16 1 15 RX PEx16 1 RTM PE16 1 10 TX PEx16 1 RTM PE16 1 3 TX PEx16 1 RTM PE16 1 11 TX PEx16 0 RTM PE16 1 O TX PEx16 0 PE16 1 8 TX PEx16 0 RTM PE16 1 1 TX PEx16 0 RTM PE16 1 9 TX PEx16 0 RTM PE16 1 2 TX PEx16 0 16 1 10 TX PEx16 0 RTM PE16 1 3 TX PEx16 0 16 1 11 TX PEx16 1 RTM PE16 1 14 TX PEx16 1 RTM PE16 1 7 TX PEx16 1 RTM PE16 1 15 TX PEx16 0 RTM PE16 1 4 TX PEx16 0 _ 16 1 12 TX PEx16 0 RTM PE16 1 5 TX PEx16 0 RTM PE16 1 13 TX PEx16 0 RTM PE16 1 6 TX 16 0 _ 16 1 14 16 0 _ 16 1 7 16 0 _ 16 1 15 Appendix F FMM Interface pin out FMM 1 pin out
10. The MIC 5333 ATCA blade supports following IPMI interfaces KCS local payload interface active payload and OS support needed IPMB 0 remote bridged via Shelf Manager independent of payload LAN interface remote payload independent The upgrade procedures in the following chapters are described with the help of KCS since this is the easiest method Using LAN or IPMB is similar only the IPMItool interface parameters which need to be used are different 5 2 IPMC Firmware Upgrade 5 2 1 Upload the new IPMC firmware image Type IPMItool HPM 1 upgrade command and select the new IPMC firmware image root localhost ipmitool hpm upgrade mic5333 standard hpm fw 00 38 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y Performing upgrade stage Versions Upload Progress Upload Image Active Backup File 100 Time Size nem ponens 53 33 TPMCO Ouse 0 34 00 51 40131 Firmware upgrade procedure successful 5 2 2 Activate IPMC FW image Although the new IPMC FW is successfully downloaded to the board called the deferred version it needs to be activated before it will be functional Use the following HPM 1 command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 Waiting
11. GND Default Connection Shelf GND short to logic 1 2 Closed Table 3 4 Jumper Settings 1 M ias te tr a Figure 3 12 Jumper Locations Chapter 4 Hardware Management This chapter describes the IPMC firmware features 4 1 Intelligent Plattorm Management Controller The term Intelligent Plattorm Management Controller IPMC describes an IPMI Baseboard Management Controller BMC located on a PICMG compliant ATCA board The IPMC is the essential part involved in management of the platform It s implemented on NXP s ARM Cortex M3 LPC1768 controller and acts as standard IPMI management controller with additional ATCA functionality extensions Main tasks are the module healthy monitoring voltage and temperature sensors hot swap state management participation ATCA information data storage and providing several IPMI communication interfaces A Lattice LFXP2F17 FPGA is used to provide additional connectivity for the IPMC and payload It provides extension interfaces with configurable routing options as well as some additional stand alone functionality 4 2 IPMI Interface The management controller provides four IPMI messaging interfaces These are the IPMB 0 bus for communication with the shelf manager the local IPMB bus IPMB L for basic communication with subsidiary FRUs like RTM s the LAN side band interface RMCP RMCP and the on board payload interface to x86 5 System LPC Lattice
12. LE B Figure 2 5 10GE Dual Star Solution 5333 5001 MIC 5333 FMM 5001B LE B FMM 5001B Figure 2 6 10GE Dual Dual Star Solution MIC 5333 2x FMM 5001B Below is the summary of the MIC 5333 Fabric Interface options Ethernet Interface per channel Topology FMM 2 Dual Star FMM 5001Q Dual Star o FMM 5004M KR4 Dual Dual Star FMM 5004M FMM 5004M 10G XAUI Dual Star BEEN 5001 106 Dual Dual Star FMM 5001B FMM 5001B Table 2 7 MIC 5333 Fabric Interface Options The MIC 5333 Fabric Interface supports PICMG 3 1 Option 1 or 9 2 4 3 Ethernet Interface There are two RJ 45 LAN ports on the MIC 5333 front panel which implemented using an Intel 1350 4 quad port GbE controller Intel 1350 4 Base Interface Backplane Copper 10 100 1000 Mb s Ports 0 1 Quad Intel 82599 Fabric Interface Backplane or Mellanox CX 3 KR or KR4 10 40 Gb s via FMM Intel 1350 4 Interface Front Panel Copper 10 100 1000 Mb s v Ports 2 3 Table 2 8 Ethernet Interface Link Speed Configuration For further information regarding the front panel LED description please see chapter 3 4 6 LED Definition 2 5 Zone 3 Interface RTM The MIC 5333 supports the following connectivity to an optional RTM through the zone 3 interface please refer to the Appendix E Zone 3 Interface RTM pin out 2x PCI Express x16 From
13. Gen1 4x PCle root ports 2x SATA 3Gb s USB 2 0 and supports four internal GbE MAC MIC 5333 uses 2 for SGMII interface to Zone3 as well Intel amp QuickAssist amp hardware acceleration and offload For more details please refer to section 2 3 2 2 3 DMI Gen1 Direct Media Interface is the chip to chip connection between the processor and PCH This high speed interface integrates advanced priority based servicing allowing for concurrent traffic and true isochronous transfer capabilities Base functionality is completely software transparent permitting current and legacy software to operate normally For the CaveCreek chipset the DMI interface operates at 2 5 GT s 2 2 4 PCI Express Port Configuration Intel Xeon E5 2600 series processors support 40 Express Gen3 ports On the MIC 5333 each processor is configured to one x16 port and three x8 ports The PCI Express interface is connected for FMM and RTM use om 0 a o Fables Crammer 12 _ 2 connected to FMM1 1 to Fabric Interface Channel 3 4 EO II 9 ForRTMuse connected to Zoned reserve __ wana s WETU T ________ x8 connected to connected to FMM1 2 Table 2 3 PCI Express Port Configuration on the MIC 5333 E Note PCle hot swap is not supported for graphic controllers e g 5002 installed on RTM 2 2 5 Redundant BIOS Flash T
14. INTEL Cave Creek 1066 1333 1600 OUR Rag ul 1066 1333 1600 ODRI Rag Dd 1066 1333 1600 RAJDI s omo 1066 1333 1600 1066 1333 1600 1066 1333 1600 a ul 1066 1333 1600 cons econ coo 1066 1333 1600 FUGA LATTICE LyFXP2 17E 5F 46864C St s TPM INFINEON SLES6SSTT1 2 FW3 16 ec NXP 17 1768 80100 Figure 1 2 MIC 5333 Block Diagram 1 3 Product Configurations Model Name Configurations MIC 5333 with dual Intel Xeon E5 2658 CPU with Cave Creek SKU4 MIC 5333S42 P1E no FMM no memory no MO 297 SSD MIC 5333 with dual Intel Xeon E5 2648L CPU with Cave Creek SKU4 MIC 5333842 P2E no FMM no memory no MO 297 SSD MIC 5333 with dual Intel Xeon E5 2658 CPU with Cave Creek SKU1 no MIC 5333812 P1E FMM no memory no MO 297 SSD MIC 5333 with dual Intel Xeon E5 2648L CPU with Cave Creek SKU1 5333512 2 no FMM memory 297 550 Table 1 1 MIC 5333 Configurations 1 4 Related Products Model Name Configurations RTM 5106 ATCA RTM for MIC 5333 with eight SFP interfaces Dual 10GE Module with 2x fabric ports for dual dual star support FMM 5001BE based on 182599 Table 1 2 MIC 5333 Related Products Note Contact Advantech for information on available and future RTMs and FMMs Chapter 2 Board Features This chapter describes the MIC 5333 hardware features 2 1 Technical Data Pr
15. abuse accident or improper installation Advantech assumes no liability under the terms of this warranty as a consequence of such events Because of Advantech s high quality control standards and rigorous testing most of our customers never need to use our repair service If an Advantech product is defective it will be repaired or replaced at no charge during the warranty period For out of warranty repairs you will be billed according to the cost of replacement materials service time and freight Please consult your dealer for more details If you think you have a defective product follow these steps 1 Collect all the information about the problem encountered for example Advantech products used other hardware and software used etc Note anything abnormal and list any onscreen messages you get when the problem occurs 2 Call your dealer and describe the problem Please have your manual product and any helpful information readily available 3 If your product is diagnosed as defective obtain an RMA return merchandise authorization number from your dealer This allows us to process your return more quickly 4 Carefully pack the defective product a fully completed Repair and Replacement Order Card and a photocopy proof of purchase date such as your sales receipt in a shippable container A product returned without proof of the purchase date is not eligible for warranty service 5 Write the RMA number visibly on the outside o
16. command The IPMC will do a specified number of tries to read out the Shelf Manager time If not successful it will generate an integrity sensor event 4 11 2 Payload Time Synchronization IPMC synchronization with payload is initiated by the payload itself payload has to use and issue the Get Set SEL Time IPMI commands This is done by BIOS can be performed by an OS driver the KCS interface 4 11 3 RTC Synchronization Relations RTC synchronization with Shelf Manager is only done during the early initialization of IPMC Synchronization with payload is always done later after the ATCA board transitioned to M4 Means synchronization from IPMC with Shelf Manager and payload is basically independent from each other Chapter 5 Firmware Upgrade This chapter describes how to update the IPMC FW FPGA and BIOS for the MIC 5333 5 1 HPM 1 Upgrade Functionality The term HPM 1 Update describes the update of following software firmware components Firmware FPGA Configuration BIOS Image NVRAM Image BIOS Settings 5 1 1 IPMItool Before upgrading users need to prepare a HPM 1 capable update utility Advantech recommends to use the open and verified IPMItool gt version 1 8 10 In general any tool compliant to the PICMG HPM 1 R1 0 specification can be used 5 1 2 Interfaces 1 provides a way to upgrade firmware via different interfaces verify chapter 4 2 IPMI Interfaces
17. 1 FMM type Il 1x PClex8 from CPU socket 1 2 x MO 297 SSD Built in 2 x 5 2658 or E5 2648L 95W 128GB memory FMM 5001Q FMM 5001F 2x 64GB MO 297 SSDs 283W for E5 2658 real measurement for 242 8 W for E5 2648L Real Measurement Test Programs TDISK sh LAN FN sh PTU Gen Memorytester OS Red Hat Enterprise Linux 6 2 64bit Advantech common RTM interface Type 2 Interface 2 x PClex16 1x PClex4 DMI 2 x USB 1x COM 2 x SGMII Physical PCB Dimensions GHP 280 00 x 322 25 mm 11 02 x 12 69 W x D Characteristics Weight 3 275kg Operating Non operating Temperature 0 55 32 131 40 70 40 158 F Humidity 5 to 93 40 non 95 40 C non condensing Environment condensing Shock 4 G each axis 20 G each axis Vibration 5 500 2 0 5 Grms 2 16 Grms 30 mins each axis ETSI EN300019 2 1 Class1 2 EN300019 2 2 Class 2 3 ETSI Environment EN300019 2 3 Class 3 1E Designed to meet GR63 CORE PICMG 3 0 R3 0 3 1 R1 0 HPM 1 Compliance Safety UL60950 1 CSAC22 2 e FCC47 CFR Part15 Class A CE Mark EN55022 EN55024 EN300386 Designed to meet GR1089 CORE Table 2 1 MIC 5333 Technical Data E Note 1 MIC 5333 supports 2 x 95W CPUs Special system airflow requirements apply MIC 5333 will be compliant to PICMG3 1 R2 0 when released 2 2 Product Features 2 2 1 Processors The MIC 5333 supports dual Intel Xeon E5 2600 series processors using latest 32nm silicon architecture with a bu
18. F 1st FMM FRU Device Locator only if FMM is plugged MMXXXX TMP Temperature FMM Temperature sensor FMMXXXX TMP Temperature FMM Temperature sensor FMMXXXX TMP Temperature FMM Temperature sensor only if FMM is plugged 4 4 2 Threshold Based Sensors According to the IPMI specification sensor event thresholds are classified as 53 54 55 56 57 58 9 5 Non critical Critical or Non recoverable When different thresholds are reached different actions may be executed by shelf manager e g fan speed adjustment for temperature sensor events Below table list the six sensor thresholds specified for threshold based sensors in the following subchapters LNC Lower Non critical Lower Critical LNR Lower Non recoverable Table 4 3 Sensor Threshold Description 4 4 2 1 Voltage Sensors All power rails produced from 12 are monitored by the NXP LPC1768 ADC and NCT7904D hardware monitor devices The ADC of LPC1768 and NCT7904D provide 8 bit resolution for voltage sensing All the voltage sensors are listed in Table 4 4 Sensor Name Nomina LNR LCR LNC UNC UCR UNR Value HU CAP VOL 65 80 0 85 0 90 0 V48 A VOL 48 0 36 0 38 0 40 0 70 0 75 0 80 0 V48 B VOL 48 0 36 0 38 0 40 0 70 0 75 0 80 0 BAT 3 0 VOL 3 00 2 30 2 80 2 90 3 45 3 60 3 80 MAN 3 3 VOL 3 30 2 80 3 00 3 15 3 45 3 60 3 80 MAN 5 0 VOL 5 00 4 30 4 50 4 65 5 35 5 50 5 70 PAY 3 3 VOL 3 30 2 80 3 00 3 15 3 45 3 60 3 80 PAY 5 0 VOL 5 00 4 30 4 50 4
19. Failure to comply with these precautions or with specific warnings elsewhere in this manual could result in personal injury or damage to the equipment Advantech intends to provide all necessary information to install and handle the product in this manual Because of the complexity of this product and its various uses we do not guarantee that the given information is complete If you need additional information ask your Advantech representative The product has been designed to meet the standard industrial safety requirements It must not be used except in its specific area of office telecommunication industry and industrial control Only personnel trained by Advantech or persons qualified in electronics or electrical engineering are authorized to install remove or maintain the product The information given in this manual is meant to complete the knowledge of a specialist and must not be used as replacement for qualified personnel Keep away from live circuits inside the equipment Operating personnel must not remove equipment covers Only factory authorized service personnel or other qualified service personnel may remove equipment covers for internal subassembly or component replacement or any internal adjustment Do not install substitute parts or perform any unauthorized modification of the equipment or the warranty may be voided Contact your local Advantech representative for service and repair to make sure that all safety features are maint
20. LAN setup IP Address 192 168 1 1 LAN Channel Number 5 Username administrator Password advantech 4 8 2 LAN Configuration with IPMItool The open source IPMItool utility is used in this chapter for the SOL and LAN parameter configuration Any other utility based on standard IPMI commands can be used as well To get an overview of all possible commands within an IPMItool command group 5 t please use the single keywords e g lan user or sol only 4 8 2 1 LAN Commands an print channel number Get the LAN configuration parameters for a given channel root localhost ipmitool lan print Set in Progress Set Complete Auth Type Support NONE MDS PASSWORD Auth Type Enable Callback NONE MDS PASSWORD User NONE MD5 PASSWORD Operator NONE MD5 PASSWORD Admin NONE MD5 PASSWORD OEM IP Address Source Static Address IP Address to DSZ l69 ll Subnet Mask 555225002200 Address 5067 Default Gateway IP RMCP Cipher Suites Oy Cipher Suite Priv Max gt X Cipher Suite Unused c CALLBACK u USER O OPERATOR a ADMIN O OEM lan set channel command option This command can be used to change several IPMC LAN parameters e g IP address netmask gateway IP address Below example demonstrates how to change the BMC IP address root localhost ipmitool lan set 5 ipad
21. OxA6 Command Command Line Syntax T Transit address gt IPMC s IPMB address ATCA slot dependent is the transit address for double bridging B lt Transitchannel gt Transit channel for double bridging is 0 It s the default value B 0 and can be skipped in command therefore t lt Target address gt RTM s MMC IPMB L address is the target address of the bridging OxA6 according to iRTM specification b Target channel Target channel number for IPMB L is 7 and needs to be specified in the command b 7 4 3 FRU Information The IPMC provides IPMI defined Field Replaceable Unit FRU information about the ATCA board and the connected extension modules The MIC 5333 FRU data include general board information s such as product name HW version or serial number A total of 2kB non volatile storage space is reserved for the FRU data The boards IPMI FRU information can be made accessible via all IPMC interfaces and the information can be retrieved at any time 4 3 1 PICMG FRU Records In addition to the standard IPMI FRU data areas the MIC 5333 FRU stores ATCA specification PICMG 3 0 R3 0 defined PICMG records These FRU records e g E Keying information are mandatory for the ATCA board functionality Please note that the PICMG FRU data records are essential for any ATCA blade Improper record data or wrong modifications can influence the correct activation through the shelf manager and behavior of the board
22. amp Ethernet Controller 1350 is a single compact low power component that supports quad port and dual port gigabit Ethernet designs The device offers four fully integrated gigabit Ethernet media access control MAC physical layer PHY ports and four SGMII SerDes ports that can be connected to an external PHY The 1350 supports PCI Express PCle v2 1 2 5GT s and 5GT s The device enables two port or four port 1000BASE T implementations using integrated PHY s The MIC 5333 also supports PXE boot and SoL Serial over LAN over the Base Interface channels PXE boot can be enabled with Launch PXE OpROM through the BIOS setup menu see Section 5 4 Advanced BIOS Features Setup Information about the PXE expansion ROM configuration is also provided in this section The Intel i350 controller supports side band functionality This side band interface NC SI is used by the IPMC to establish LAN sessions to enable RMCP RMCP based communication to the management part See Section 4 6 Serial over LAN for details on setting up connections to the BMC 2 4 2 Fabric Interface The fabric connectivity of MIC 5333 is implemented using a FMM Fabric Mezzanine Module concept This allows the MIC 5333 to scale from legacy 10GE to high speed 40GE network interfaces For a standard dual star topology the traffic from Fabric Interface channel 1 and 2 goes to the CPU through FMM 72 To implement a dual dual star topology additional fabric channels 3
23. and 4 can be supported by installing a FMM 5004M or FMM 5001B on the FMM 1 for 40GE or 10GE network interface respectively 2 4 2 1 40 FI For the 40 fabric interface two kinds of FMM solutions are offered one is the FMM 5001Q using quad Intel 82599ES controllers to provide four 10GBaseKR for each Fabric Interface channel 1 and 2 1 Niantic 1 Niantic 3 Niantic 2 Niantic 2 CPU 0 CPU 1 Figure 2 2 40GE Dual Star Solution 1 MIC 5333 FMM 5001Q FMM KR routing xi CPUD connects to Niantic 1 2 CPUT connects to Niantic 3 4 xiii Niantic1 port 0 N1 0 connects to channel 1 port 0 FI1 0 N1 1 connects to FI2 0 2 0 connects to FI1 1 N2 1 connects to FI2 1 xvii 3 0 connects to FI1 2 xviii M3 lconnects to FI2 2 xix N4 0 connects to FI1 3 N4 1 connects FI2 3 The other is the FMM 5004M using Mellanox ConnectX 3 EN controllers to provide dual 40GBaseKRA interface to the fabric interface MIC 5333 5004 ES PClex8 PClex8 m Figure 2 3 40GE Dual Star Solution 2 MIC 5333 FMM 5004M MIC 5333 FMM 5004M 5004 PClex8 Figure 2 4 40GE Dual Dual Star Solution MIC 5333 2x FMM 5004M 2 4 2 2 10GE FI For the 10GE fabric interface FMM 5001B is designed to implement thisfunctionality An onboard Intel 82599EB controller provides two additional XAUI ports to the backplane MIC 5333 FMM 5001B
24. data in network packets and exchange them via LAN With the help of SOL the user can connect to a virtual serial console e g payload x86 system from remote SOL can be used on the blade for serial based OS and pre OS communication over LAN e g OS command line interface and serial redirected BIOS menu 4 8 1 Preconditions for SOL 4 8 1 1 Supported LAN Interfaces Four Ethernet interfaces can be used for Serial over LAN Base interface channel 1 2 Front panel I O interfaces 1 2 Important note The LAN controller used for SOL is connected to the management power domain Thus it s also possible to gain a connection to IPMC even if payload power is off Base Interface 1 intel i350 Front Panel Interface 1 LAN Front Panel Interface 2 controller Base Interface 2 UART 1 2 Figure 4 3 SoL Functional Block Diagram 4 8 1 2 LAN Controller and UART MUX Configuration The LAN and UART configuration of the x86 blade is flexible and allows different configurations To avoid wrong setups users should always verify the actual LAN and UART configuration settings verify chapter 4 16 2 Configuration Setting OEM commands before working with SOL 1 Select the LAN interface to be used front panel or base interface 2 Make sure the LAN channel priority is appropriate 3 Select UART interface to be used COM1 or COM2 4 8 1 3 Default Parameter Following default parameters are used for the initial
25. number Read out the SOL configuration parameters for a given channel ipmitool I lanplus lt IP Address gt U User P Password sol info Set in progress set complete Enabled false Force Encryption true Force Authentication true Privilege Level ADMINISTRATOR Character Accumulate Level ms 250 Character Send Threshold 522 RELLY Count Retry Interval ms Volatile Bit Rate kbps Non Volatile Bit Rate kbps Payload Channel Payload Por sol set parameter value channel This command allows modifying special SOL configuration parameters ipmitool I lanplus lt IP Address gt U User P Password sol set SOL set parameters and values Set in progress set complete set in progress commit write enabled true false force encryption true false force authentication true false privilege level user operator admin oem character accumulate level in 5 ms increments character send threshold N Fetrvecounr N retry interval in 10 ms increments non volatile bit rate serial 9 6 19 2 38 4 57 6 115 2 volatile bit rate serial 9 6 L9 2 38 4 57 96 1154 2 4 8 3 2 SOL Session Activation Finally the IPMItool sol activate command need to be issued to establish the SOL session from remote ipmitool I lanplus IP Address U User P Password sol activate SOL Session operational Use for help terminated ipmitool
26. of warranty 3 2 Memory 3 2 1 Requirement As described in Section 2 3 DDR3 DIMMs the MIC 5333 supports 8 x DDR3 VLP very low profile 0 72 18 29mm un buffered registered ECC SDRAM DIMMs To allow proper MIC 5333 functionality please comply with population requirements when installing memory modules Mixing of Registered and Unbuffered DIMMs is not allowed To optimize the memory performance by balanced sharing the load on each channel of a socket Advantech requires the use of identical memory modules with the same density rank speed timing parameters and other factors Although unbalanced configurations might work they are not supported Advantech For supported memory characteristics please refer to Table 2 7 Supported DIMM Configurations 3 2 2 Memory Installation Please review the following procedures for memory installation ASW aere CPUO CH3 CPU1 CH1 CPUO CH1 CPUO CH2 CPU1 CHO CPU1 CH3 CPU1 CH2 Yi yr 4 gt lt a 4 3 T 4 t 1487 4 A gt i y Ls MEN y 21 f M Ii TI il M Figure 3 1 MIC 5333 DIMM Slots Overview Open the ejector on the empty DIMM socket where you want to inst
27. only accessible from a running OS IPMI driver support is needed to be able to use the IPMItool from OS level via the KCS IPMC interface See Appendix With working IPMI driver the IPMC can be easily accessed from OS via KCS No interface parameters are needed at all to use the local onboard IPMI connection lpmitool Command 4 2 3 LAN Interface The IPMI LAN Interface on the blade is accomplished by using a shared LAN Controller together with the x86 system In addition to systems PCI Express link a LAN controller side band interface Network Controller Sideband Interface short NC SI is connected to the IPMC This NC SI channel is used by the IPMC to receive and transmit IPMI management traffic from and to network with help of the LAN controller IPMI over LAN IOL uses the Remote Management Control Protocol RMCP specified in IPMI v1 5 in request response manner for IPMI communication IPMI v1 5 LAN messages are encapsulated in RMCP packets while IPMI v2 0 specification added an enhanced protocol for transferring IPMI messages and other types of payloads uses RMCP overall packet format but defines extensions such as encryption and the ability to carry additional traffic types e g serial data in addition to IPMI messages See Chapter 4 8 3 SoL Session with IPMItool Four Ethernet interfaces can be used for IPMI over LAN Two Front IO interfaces 1 2 Two backplane BI interfaces 1 2 Note T
28. please contact your Advantech representative 3 4 5 Front Panel The MIC 5333 is 10096 compatible to AdvancedTCA specifications All LED signals are shown on the front panel Users can refer to section 3 6 LED definition to understand the details of the board operating status Button and 2 are reserved for customization Button is set as a reset function by default while Button2 is not assigned Users can define the functions for each For details please contact your Advantech representative to obtain further information Retaining Thumbscrews Handle Top side FI Channel 1 2 3 4 Status LEDs BI Channel 1 2 Status LEDs OOS LED Dual Color User LEDs Button2 Reserved Health LED TOasIT Button1 Reserved 7 18 58 2 USB2 E USB1 05 2 miniUSB COM RJ45 LAN2 LAN1 Hot Swap LED FMM Bay Handle Bottom side Retaining Thumbscrews Figure 3 11 MIC 5333 Front Panel Configuration 3 4 6 LED Definition This section describes how to identify the system operating status via LED signals from the front panel Before starting please refer to table 3 2 to learn the LED signal identification in this manual In the following section we will use amber as an example 00 0 o Table 3 2 LED Signal Identification LEDName Name LEDName Function Display 4x KR interface all link OO QO 4x KR interface all Active Fl port Speed Link No
29. the Intel CrystalForest Server Platform It enables the highest performance available in the ATCA form factor with up to 16 cores and 32 threads of processing power scalable offload based on Intel amp QuickAssist amp technology and supports up to four 40G fabric ports Fast PCI Express gen 3 lanes running at up to 8Gbps and best in class virtualization support combined with superior thermal design make it an integrator s choice for ultra high performance applications and workload consolidation from special purpose processors to Intel amp architecture Two interfaces between the CPUs improve memory and access throughput and latencies when one processor needs to access resources hosted by the other socket With four DDR3 DIMMs per socket in a quad channel design running up to 1600 5 the MIC 5333 not only offers superior memory bandwidth over 3 channel designs but can also support memory densities up 256GB using latest LR DIMM technology It outperforms previous generation dual socket designs while keeping similar thermal characteristics with balanced airflow resistance Intel s CaveCreek PCH provides power and cost efficient integration standard peripheral interfaces e g Express SATA USB etc along with Intel QuickAssist hardware acceleration QuickAssist hardware acceleration and offload can be scaled by adding additional CaveCreek devices via Fabric Mezzanine Modules FMMs on the blade or an attach
30. to activate the new NVRAM image Component requires Payload Cold Reset The payload reset can be performed through different ways 55 If the user is working on the local OS KCS a linux reboot poweroff or halt If the user accesses the IPMC through the other interfaces LAN IPMB a deactivation and activation cycle is needed to load the new NVRAM image 5 6 Verify Successful Upgrades To verify successful updates the IPMItool hom check command can be used root localhost ipmitool hpm check PICMG HPM 1 Upgrade Agent 1 0 2 Device Device Revision Product Id e2d 0x81 0x5333 Manufacturer Id 0x2839 Unknown 0x2839 Versions Active Backup FPGAA 1 28 Bross 24 NVRAMM 0 04 Component requires Payload Cold Reset After a successful upgrade the new backup version should be the former active version if Backup versions are supported And the new Active version should be the version of the used upload file Appendix IPMI PICMG Command Subset Supported by IPMC IPM Device Global Commands IPMI Command Spec Ref IPMI PICMG3 0 AMC2 0 Requirement IPMI Spec Ref Get Channel Authentication Capabilities App App IPMI PICMG3 0 AMC2 0 Requirement 22h Mandatory 24h Mandatory 25h Mandatory IPMI PICMG3 0 AMC2 0 Requirement 38h Optional App Optional App 42h Optional Set User Access App 43h Ge
31. 0x00 MAC Number Response 39 28 00 MAC Address B 6 Load Default Configuration OEM command Several configurations settings are provided by the MMC verify chapter B 2 Configuration Setting OEM commands To reset all of them to their default values a single OEM command is available to perform this task with only one IPMI command ipmitool raw OxF2 0x39 0x28 0x00 Response 29 29 00 Appendix C Zone 1 P10 Pin out wem Pe e im hems Le hemn o _ 33 48 48V input feed 48 B 48V input feed B Appendix D Zone 2 Interface pin out Zone 2 J22 pin out Base Interface and Fabric Interface FI CH4 F CHA FI CH4 CHA CHA DESEE IEEE S F CH4 CHA FI FI CHA CHA ko dE ee s FI CH3 FI CH3 FI CH3 FI CH3 FI CH3 FI CH3 FI CH3 FI CH3 F CH3 CH3 FI CH3 FI CH3 FI CH3 FI CH3 FI CH3 CH3 B S j o U Zone 2 J23 pin out Base Interface and Fabric Interface J23 e FI CH2 FI CH2 FI CH2 FI CH2 FI FI CH2 FI CH2 CH2 FI CH2 FI CH2 FI CH2 FI CH2 FI 2 FI CH2 FI CH2 CH2 FI CH1 FI CH1 FI CH1 FI CH1 FI CH1 FI CH1 FI CH1 CH1 FI CH1 FI CH1 FI CH1 FI CH1 CH
32. 1 CH1 FI_CH1 CH1 BI CH1 BI CH1 BI CH1 BI CH1 BI CH1 BI CH1 BI 1 CH1 DA DA DB DB DC DC DD DD BI CH2 BI CH2 BI CH2 BI CH2 BI CH2 BI CH2 BI CH2 BI CH2 DA DA DB DB DC DC DD DD i i Appendix E Zone 3 Interface RTM pin out Zone 3 J31 pin out RTM 12 RTM 3 3V MP RTM IPMBL MMC ENABLE DYH H RTM MDIO1 MDIOO RTM 0581 _ USBO B SGMIIT1 RTM SGMIIO not connected UART1 RTM PCIE2 CLK RTM PCIE1 PCIEO CLK 4 2 PE4 2 3 4 2 4 2 2 m 4 2 RTM 4 2 1 4 2 PE4 2 0 3 32 ep otcnnectes notcomested notconnecied notcomected DENN DECEM O e om nmn not connected not connected Zone 3 J33 pin out PEx16 1 PEx16 1 PEx16 1 PEx16 1 16 1 0 16 1 4 RTM PE16 1 0 RTM 16 1 4 RX RX TX TX PEx16 1 PEx16 1 PEx16 1 PEx16 1 RTM PE16 1 8 RTM PE16 1 12 RTM PE16 1 8 RTM PE16 1 12 RX RX TX TX PEx16 1 PEx16 1 PEx16 1 PEx16 1 RTM PE16 1 1 16 1 5 RTM PE16 1 1 RTM PE16 1 5 RX RX TX TX PEx16 1 PEx16 1 PEx16 1 PEx16 1 RTM PE16 1 9 RTM PE16 1 13 RTM PE16 1 9 RTM PE16 1 13 RX RX TX TX PEx16 1 PEx16 1 PEx16 1 PEx16 1 PE16 1 2 PE16 1 6 RTM PE16 12 RTM PE16 1 6 RX RX TX TX
33. 2 Set retry value ipmitool raw 0x40 0x39 0x28 0x00 0x05 0x01 lt retries gt 39 20 90 5 2 Disable retry mechanism ipmitool raw 0 2 0x40 0x39 0x28 0x00 0 05 0 01 OxFF 5 2 227529200 2 8 Synchronization The IPMC firmware implements synchronization feature which allows users to sync system times between Shelf Manager IPMC and payload refer to chapter 4 13 RTC Synchronization The following setting values are available to configure the described synchronization mechanism Setting Synchronization mechanism 0 00 Shelf Manager Payload Time Sync default gets time from ShMM X86 payload gets time from during BIOS execution time is updated if time is changed in BIOS menu shelf Manager Time Sync only gets time from ShMM X86 payload gets time from during BIOS execution time is NOT updated if time is changed in BIOS menu 0 02 Payload Time Sync only X86 payload gets time from during BIOS execution time is updated if time is changed in BIOS menu 0x03 No Time Synchronization Time sync feature disabled 0x04 IPMC Time Sync from x86 payload time is overwritten with x86 payload time by BIOS Read RTC synchronization setting ipmitool raw 0x41 0x39 0x28 0x00 0x07 0x00 Response 39 28 00 se
34. 4 3 2 FRU Information Access Commands The FRU device IPMI commands are supported by the IPMC to read and write the board s FRU information Correct and board specific FRU data is programmed to each MIC 5333 during manufacturing Please be very careful using the regular IPMI FRU write command avoid if possible 4 3 3 MIC 5333 FRU Data Details 4 3 3 1 Board Information Area Field description Board information Format version Board area length Language code Manufacturer date time Board manufacturer type length Board manufacturer Board product name type length Board product name Board serial number type length Board serial number Board part number type length Board part number FRU file ID type length FRU file ID Additional custom Mfg Info fields C1h No more info fields unused space Board area checksum Ox19 English 10 characters written during manufacturing unused Table 4 1 Board Information Area 4 3 3 2 Product Information Area Ox19 English Product part model number Product version Hardware Version 10 characters written during Product area length Language code Product Manufacturer type length Product manufacturer Product name type length Product name Product part model number type length Product serial number type length Product serial number manufacturing Assert Tag type length Assert Tag FRU File ID type length FRU File ID Custom product info are
35. 6 1333 SR DR QR only for SR DR Ranks 1066 1333 Table 2 6 Supported DIMM Configurations 26 4G and 8GB DDR3 DRAM technologies are supported for these devices UDIMMs x8 x16 RDIMMs 4 LRDIMMs x4 Up to 4 ranks supported per memory channel 1 2 or 4 ranks per DIMM Supports a maximum of 256GB DDR3 1600 memory At time of manual publication Advantech has tested 16GB DDR3 1600 RDIMMs 2 3 2 RAS Mode Four DRAM RAS modes are supported by the memory controller which can be configured in BIOS setup menu Independent Channel Mode Default Channels can be populated in any order in Independent Channel Mode All four channels may be populated in any order and have no matching requirements All channels must run at the same interface frequency but individual channels may run at different DIMM timings RAS latency CAS latency etc Rank Sparing Mode In Rank Sparing Mode one rank is a spare of the other ranks on the same channel The spare rank is held in reserve and is not available as system memory The spare rank must have identical or larger memory capacity than all the other ranks sparing source ranks on the same channel After sparing the sparing source rank will be lost Mirrored Channel Mode In Mirrored Channel Mode the memory contents are mirrored between Channel and Channel 2 and also between Channel 1 and Channel 3 As a result of the mirroring the tota
36. 75 5 25 5 50 5 70 PAY 12 VOL 12 0 10 4 10 6 11 0 13 0 13 4 13 6 LAN 1 0 VOL 1 0 0 85 0 90 0 93 1 07 1 10 eS LAN_1_8 VOL 1 8 1 55 1 62 1 71 1 89 1 98 2 05 PCH 1 0 VOL 1 0 0 70 0 78 0 84 1 16 1 22 1 30 PCH 1 5 VOL 5 1 28 1535 1 42 1 57 1 65 1 72 PCH 1 8 VOL 1 8 1 53 1 62 1 71 1 89 1 98 2 07 CPUO 0 85 VOL 0 85 0 50 0 54 0 57 1 26 1 32 1 40 CPUO 1 05 VOL 1 05 0 75 0 90 0 95 1515 1 20 1 40 CPUO CORE VOL 1 10 0 50 0 54 0 57 1 42 1 46 1 50 CPUO 1 80 VOL 1 80 1 45 1 55 1 62 1 89 1 95 2 00 CPU1 0 85 VOL 0 85 0 50 0 54 0 57 1 26 1 32 1 40 CPU1 1 05 VOL 1 05 0 75 0 90 0 95 1515 1 20 1 40 CPU1 CORE VOL 1 10 0 50 0 54 0 57 1 42 1 46 1 50 CPU1 1 80 VOL 1 80 1 45 1 55 1 62 1 89 1 95 2 00 DDR AB VOL 1 50 1 20 1 35 1 425 1 575 1 65 1 975 DDR CD VOL 1 50 1 20 135 1 425 1 575 1 65 1 975 DDR EF VOL 1 50 1 20 1 35 1 425 1 575 1 65 1 975 DDR GH VOL 1 50 1 20 1 35 1 425 1 575 1 65 1 975 Table 4 4 MIC 5333 Voltage Sensors List 4 4 2 2 Current Sensor The 48V power module provides an output payload power only current draw reading This value is used for the 48V current sensor supported by IPMC Sensor Name Nominal LNR LCR LNC UNC Value V48 CUR 8 9 10 4 4 2 3 Board Power Sensor The actual ATCA board power managment power and payload power is calculated and readable over IPMI via one IPMC sensor Sensor Name Nominal LNR LCR LNC UNC UCR UNR Value BOARD POWER 400 400 400 Table 4 4 MIC 5333 Current Sensor List 4 4 2 4 Temperature
37. Although the new BIOS image is successfully loaded deferred version it needs to be activated before users can boot the new BIOS Following two actions are needed to finish the upgrade 5 4 2 1 HPM 1 activate command Schedule the BIOS load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 5 4 2 2 Payload cold reset A payload cold reset is required to activate the new BIOS image Component requires Payload Cold Reset The payload reset can be performed through different ways If the user is working on the local OS KCS a linux reboot poweroff or halt If the user accesses the IPMC through the other interfaces LAN IPMB a deactivation and activation cycle is needed to load the new BIOS image 5 5 NVRAM Upgrade In contrast to the BIOS image update the setting update image is not directly written to any of the BIOS SPI flashes The BIOS settings are stored in the external SPI flash of the IPMC to support a deferred activation For extended flexibility the external SPI flash supports different sections to store up to four BIOS setting images in the external flash at the same time Each of these settings can be set to active at any time and will be copied to the active BIOS flash at the next OS boot slot 5 5 1 Select Upgrade Section optional As described above the IPMC provides multiple upgrade sections for different
38. C in order to access the console screen your terminal PC runs on Microsoft Windows common application that can act as a client for the SSH Telnet rlogin and raw TCP protocols called can be installed and used PuTTY was originally written for Microsoft Windows however it has also been ported to various Unix like operating systems 15 available as open source software for download from the internet 3 3 3 PuTTY Configuration Assuming both the CP2102 driver and PuTTY have been installed successfully on the terminal PC with Microsoft Windows the user can check the COM port UART number under COM and LPT in the Device Manager which can be accessed by entering the Control Panel followed by opening up System and then Hardware Let us assume the CP210x USB to UART Bridge Controller has been assigned with COM12 You can open up PuTTY and begin the configuration as shown below If you use the RJ45 and a serial port on the terminal PC please use the COM port number of that serial port instead of COM12 Specify COM12 under serial line and 115200 for speed no parity no flow control Check Serial for connection type Click the Open button and a PuTTY terminal screen will appear PuTTY Configuration x gt lt Appearance i Behaviour delete a stored session il Colours E Connection H SSH Serial Close
39. CPUO CPU1 1x PCI Express x4 From CPU1 DMI 2x USB 2 0 From PCH 1x COM From FPGA RTM Link From FPGA 2 x SGMII From The rear transition module is used to provide additional I O expansion for the main CPU board It is managed with an on board MMC and is fully hot swappable Customers may use the standard Advantech RTM 5104 or request acustomized RTM for more information please contact your local Advantech representative For detailed specifications of the RTM 5104 please refer to table 2 9 For the detailed pin definition of the Zone 3 interface please see Appendix E Zone 3 Interface RTM pin out RTM 5106S00E 8x SFP Table 2 9 Advantech RTM 5104 Specifications Please contact your local Advantech representative for more information about the RTM 5104 2 6 Fabric Mezzanine Module FMM The FMM board is used to provide an option to expand the feature set of both the main CPU board and RTM board It is managed by the main board s IPMC or RTM board s MMC but does not support hot swap functionality PClexs PCle width 1 8 219 PClex8 1 PClex8 2 PClex8 PClex8 PCle source CPUO CPU1 CPUO CPU1 CPU1 Table 2 10 FMM PCle Source on the MIC 5333 The MIC 5333 supports 3 FMM sites to provide the most flexibility The 50010 a double sized FMM uses four Intel amp 182599 controllers andprovides two fabric in
40. DEM x 3 11 mmm ATTE ELIT er rrr mmm Figure 3 8 MIC 5333 w FMM module and Storage Module locations Nit nnm 44 a 2 n t La H Figure 3 9 Locate the appropriate FMM site on the blade F NEW Dodge Ja 5001 MOA a T 2 ec S anim T re CE gu a E chee a Figure 3 10 Install the screws Installation of EMI shielding Cover FMM 5001QE A Z a s zr Figure 3 11 Install the standoffs Figure 3 13 Align the screw holes with standoffs Figure 3 14 Install the screws Installation of EMI shielding Cover FMM 5001FE Nba us zt 3 5 lr gt at R 2 gt gt lt E 4 w 4 n 9 d oD 2 4 E 7 m We p iR a X m Figure 3 15 Install the standoffs Figure 3 16 Align the screw holes with standoffs ie S ERR 6 37 E rd 5 5 ofl 7 P 44 1 ti ae 294 i Z lt rn gt lt bee
41. Event data 2 is used to identify which component the event relates to This can either be a HPM 1 component a logical component feature on the board for example FRU or simply a board specific event Event data 3 7 3 identifies the action or a subcomponent For example If the component in byte 2 was a HPM 1 component it might report if this was an update a rollback or boot failure If the component in byte 2 was it might indicate the subcomponent within the FRU that the event relates to Event data 3 2 0 holds the result code For the HPM 1 example above it might report that an update or rollback either succeeded or failed For the FRU example it might indicate a checksum error 4 4 4 3 Event Data Table All event data combinations supported by the IPMC Integrity Sensor can be found in following list Activation Failed _ ____ mme _ oon o 2 fme om _ O ouso _ wm _ _ We _ om _ mar __ _ om _ O mime _ Troma ence Jooo ______ oue ar p rr aa o _ Wawa meneame a Wa us wawara Table 4 8 Integrity Sensor List For example below is a SEL entry generated by the integrity sensor Jan 6 08 52 29 2010 from 0x64 0 0 sensor
42. NVRAM sections OEM commands are used to select the upload and activation setting from the different BIOS setting sections in the external flash root localhost ipmitool raw 0 2 0x40 0x39 0x28 0x00 0x03 0x01 section Default section for a NVRAM update is section zero 0x00 if the OEM command is not used 5 5 2 Load New NVRAM Image Type IPMItool HPM 1 upgrade command and select the new NVRAM image root localhost ipmitool upgrade mic5333 standard hpm nvram 00 04 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y Performing upgrade stage Versions Upload Progress Upload Image Active Backup File 100 Time Size n ee N ponens 54 S333 502025 0 27 q 0006 Component requires Payload Cold Reset Firmware upgrade procedure successful 5 5 3 Activate HPM NVRAM image Following two actions are needed to boot BIOS with the new NVRAM image and BIOS settings 5 5 3 1 OEM NVRAM section activate command oince more than one possible NVRAM sections exist an OEM command is used to activate a selected NVRAM section The default section is 0 00 root localhost ipmitool raw 0 2 0x40 0x39 0x28 0x00 0x03 0x02 section 5 5 3 2 Payload cold reset A payload cold reset is required
43. OS load supervision is 60 seconds This setting can be changed through the BIOS setup menu Note assure a safe booting process the BMC watchdog timer cannot be set to less than 60 seconds 4 7 E Keying Electronic Keying E Keying is a mandatory mechanism of PICMG 3 0 system management infrastructure which is used to dynamically satisfy the needs that had traditionally been satisfied by various mechanical connector keying solutions Prevent damage to boards Prevent mis operation Verify fabric compatibility 4 7 1 Zone3 RTM The IPMC on the MIC 5333 and the MMC on the RTM handle the E keying control For the RTM the PCI Express ports need E keying to carry out the hot swap function Brief E keying information of Zone 3 is listed in Table 4 10 The user may also get a detailed E keying connectivity record via a CLI command through the shelf manager E keying Connected Source Controlled by Zone3 PCI Express port 0 Physical CPUO Intel Xeon E5 2600 PCle port 2 PMC MMC R Zone3 PCI Express port 1 Physical Intel Xeon E5 2600 PCle port 2 PMC MMC R Table 4 9 Zone 3 E keying Information 4 8 Serial over LAN SoL Serial over LAN SOL is an extension to IPMI over LAN IOL and allows to transmit serial data via LAN in addition to IPMI commands verify chapter 4 2 IPMI Interfaces Its defined in the IPMI v2 0 specification and based on the protocol to encapsulate serial
44. Sensors The MIC 5333 ATCA blade supports several temperature sensors either via board populated IC s e g TMP75 or Intel PECI readings from CPU Sensor Name Value LNR LCR LNC UNC UCR UNR 48 40 15 10 5 80 90 100 33 15 10 5 45 55 70 40 15 10 5 65 75 85 OUTLETO TMP 40 15 10 5 65 75 85 OUTLET1 TMP 40 15 10 5 65 75 85 CPU 0 40 15 10 5 85 105 115 CPU 1 TMP 40 15 10 5 85 105 115 CPUO DIMMO TMP 40 15 10 5 70 75 85 CPUO DIMM1 TMP 40 15 10 5 70 75 85 CPUO DIMM2 TMP 40 15 10 5 70 75 85 CPUO 40 15 10 5 70 75 85 CPU1 DIMMO TMP 40 15 10 5 70 19 85 CPU1_DIMM1 TMP 40 15 10 5 70 19 85 CPU1_DIMM2 TMP 40 15 10 5 70 75 85 CPU1 40 15 10 5 70 75 85 40 15 10 5 85 95 110 Table 4 5 MIC 5333 Current Sensor List Note Please refer to the FMM user manual for the FMM temperature sensors 4 4 3 Discrete sensors 4 4 3 1 IPMC Device Locator Each IPMC provides a PICMG compliant FRU device locator for the subsystem This record is used to hold location and type information of the IPMC 4 4 3 2 Mezzanine Module Device Locator The FRU device locator for each Add In card is also placed in the front board sensor data repository 4 4 3 3 FRU Hotswap Sensor Front blade Each IPMC contains a PICMG compliant Hot Swap sensor inside it s sensor data repository 4 4 3 4 FRU Hotswap Sensor RTM The front
45. User Manual MIC 5333 AdvancedTCA 40GbE Dual Socket CPU Blade with Intel Xeon E5 2600 series EP Processors Revision History 1 0 1 release August 30 2012 Copyright The documentation and the software included with this product are copyrighted 2012 by Advantech Co Ltd rights are reserved Advantech Co Ltd reserves the right to make improvements in the products described in this manual at any time without notice No part of this manual may be reproduced copied translated or transmitted in any form or by any means without the prior written permission of Advantech Co Ltd Information provided in this manual is intended to be accurate and reliable However Advantech Co Ltd assumes no responsibility for its use nor for any infringements of the rights of third parties which may result from its use Acknowledgements ATCA and AMC are trademarked by PCI Industrial Computer Manufacturers Group whilst Xeon and C600 B are trademarked by the Intel Corp All other product names or trademarks are properties of their respective owners Product Warranty 2 years Advantech warrants to you the original purchaser that each of its products will be free from defects in materials and workmanship for two years from the date of purchase This warranty does not apply to any products which have been repaired or altered by persons other than repair personnel authorized by Advantech or which have been subject to misuse
46. a sme um om LAN Device Commands IPMI IPMI PICMG3 0 AMC2 0 Command CMD Spec Ref Requirement Set LAN Configuration 23 1 Transport 01h Optional Mandatory Parameters Get LAN Configuration 23 2 Transport 02h Optional Mandatory Parameters Serial Modem Device Commands IPMI IPMI PICMG3 0 AMC2 0 Command Spec Ref Requirement Set Serial Modem Configuration Set Serial Modem Configuration Optional Mandatory Get Serial Modem Configuration Optional Mandatory Set SOL Configuration 26 2 Transport 21h None Parameters Get SOL Configuration 26 3 Transport 22h None Parameters AdvancedTCA Commands PICMG Command CMD 3 0 Table Requirement 00 Get PICMG Properties h Get Address Info 01h Get FRU LED Properties 05h Get LED Color Capabilities PICMG3 0 2 0 Set FRU LED State Get FRU LED State 08h Set IPMB State 09h Set FRU Activation Policy Get FRU Activation Policy OBh Set FRU Activation OCh h h h Get Device Locator Record ID OD Compute Power Properties 10h Get IPMB Link Info 18h FRU Control Capabilities 1Eh HPM 1 Upgrade Commands eem IPMI PICMG3 0 AMC2 0 Command CMD Table Requirement Get target upgrade capabilities 2Eh Get component properties 2Fh Abort Firmware Upgrade 30h Initiate upgrade action 31h Upload firmware block 32 Get upgrade status 34 Activate firmware 35 Query Self test Results 36h Quer
47. a fields C1h no more info fields unused Product area checksum calculated Table 4 2 Product Information Area 4 3 4 FRU Data Example Below example shows a default MIC 5333 FRU data cutout Board and Product Info areas using the Linux IPMItool root localhost ipmitool fru FRU Device Description Board Mfg Date Board Mfg Board Product Board Serial Board Part Number Product Manufacturer Product Name Product Part Number Version Product Product Serial 4 4 Sensors Builtin FRU Device TD Q 1 27 22 Advantech MIC 5233 1234567 ll 9 Advantech MIC 5353 MIC 5353 pl DT 1234567 One of the main IPMC tasks is the sensor part with monitoring board voltages and temperatures and providing a lot of other helpful board operation information s All important voltages and temperatures are connected to the IPMC Moreover the IPMC Management Subsystem also registers the below logical sensors e PICMG Hot Swap sensors PICMG IPMB sensor BMC Watchdog sensor FW Progress sensor e Version change sensor e Advantech OEM Sensor Integrity Sensor 4 4 1 Sensor List A complete MIC 5333 sensor list inclusive all FRU Device Locator records could be found in below table No Sensor ID Sensor Type Description Event Reading Type MIC 5333 1 FRU Device Locator HOTSWAP Hot Swap PICMG Front board Hot Swap HS RTM Hot Swap PICMG RTM Ho
48. ained Safety Precaution Static Electricity Follow these simple precautions to protect yourself from harm and the products from damage 1 To avoid electrical shock always disconnect the power from your system chassis before you work on it Don t touch any components on the CPU card or other cards while the system is on 2 Disconnect power before making any configuration changes The sudden rush of power as you connect a jumper or install a card may damage sensitive electronic components 3 When unpacking a static sensitive component from its shipping carton do not remove the component s antistatic packing material until you are ready to install the component in a computer Just before unwrapping the antistatic packaging be sure you are at an ESD workstation or grounded with an ESD strap This will discharge any static electricity that may have built up in your body 4 When transporting a sensitive component first place it in an antistatic container packaging We Appreciate Your Input Please let us know of any aspect of this product including the manual which could use improvement or correction We appreciate your valuable input in helping make our products better This page is left blank intentionally Glossary ACPI AHCI AMC APIC ATCA BMC CMC EHCI FI FMM FRU FW GbE HPM IOH IPMC IPMI MCH NVRAM OOS PCH PCle PECI PICMG PXE QPI RDIMM RMCP RTM RX SAS SATA SCSI SDR SerDes Ad
49. all the DIMM Insert the memory module into the empty slot Please align the notches on the module with the socket keys Push the module into socket until the ejectors firmly lock Repeat steps 1 3 for the remaining modules to be populated Install the MIC 5333 into the chassis and boot the board checking thatthe full memory quantity shown in the BIOS menu is correct See Section 3 3 Console Terminal Setup and Section 3 4 Installing the MIC 5333 To remove DIMM modules please follow the instructions listed below 1 Remove the MIC 5333 from the chassis See Section 3 4 Installing the MIC 5333 Select the DIMM to remove and push the DIMM ejector on each side of the DIMM socket outward simultaneously The module shall pop out by itself Close the ejectors of the empty DIMM socket Repeat steps 2 3 for the remaining modules to be removed 3 3 Console Terminal Setup The MIC 5333 contains five serial interfaces listed below More details about setup will described through an example to show how to configure the MIC 5333 console with the following example sections RJ45 on the front panel COM 2 miniUSB on the front panel Serial over LAN SoL I O or BI Ethernet interface UART1 routed to Zone 3 3 1 UART Multiplexer The UART multiplexer can be to route the console to any of the connections mentioned above By default the UART multiplexer is set to automatic mode This means that the mux
50. ands 4 11 RTC Synchronization Several different clock sources are available in any system To avoid system time differences a synchronization mechanism between this sources is needed e g to align System Event Log timestamps Advantech x86 ATCA blades support RTC synchronization between these clock sources This feature offers users the possibility to determine the desired master real time clock on the ATCA board Below drawing illustrates the given clock sources and provides an overview of possible clock synchronization directions Operating 5ystem iig aa cac Chipset Shelf IVlanager Figure 4 4 Real Time Clock Synchronization Overview From the IPMC s point of view are two more participants in an ATCA System which maintain their own time because they implement a separate Real Time Clock These are the Shelf Manager and the on board payload The IPMC firmware has implemented a RTC synchronization feature which allows configuring the RTC synchronization between Shelf Manager IPMC and payload according to the need of each user The IPMC will synchronize the time from Shelf Manager as soon as the ShMC is ready to communicate with the IPMC This is done with the help of the Get SEL Time IPMI command 4 11 1 Shelf Manager Time Synchronization The IPMC will synchronize to Shelf Manager time as soon as the ShMM is ready to communicate with the IPMC This is done with the help of the Get SEL Time IPMI
51. are available for all programmable components BIOS BIOS Settings IPMC firmware FPGA including rollback support Advantech s IPMI solution combined with an optimized UEFI BIOS continues to offer advanced features used on previous generation MIC 532x blades such as Dynamic Power Budgeting BIOS redundancy Real Time Clock Synchronization CMOS Backup CMOS Override and MAC Mirroring Advantech IPMI firmware has been tested for CP TA compliance using the Polaris Networks ATCA Test Suite and against a variety of AdvancedTCA shelf management solutions FMM Site for 40Gb 10Gb Fabric VLP DIMMs Double Size FMM FMM Site for extension Dual MO 297 550 Two USB ports 45 console port hen RUN EUR diio User Status LEDs Two 10 100 1000BASE T ports mini USB console Single Size FMMs FMM 5004M 2 Output FMM 5001 Figure 1 1 MIC 5333 Overview Top Side 1 2 Block Diagram The hardware implementation is shown in the following block diagram Refer to Table 1 1 next page for the detailed product technical specification MIC 5333 B101 System Block Diagram 33 UF J34 222 OPT 1 P10 t 7 70ne3 T 211111111117 O 111111111777 VSE MAN
52. asten the retaining thumbscrews Unlock the other handle and fully open both handles pushing both handles outwards to extract the board Pull the MIC 5333 out of the chassis eo Figure 3 6 Unlock the ejector handle N Caution 00 NOT attempt to extract the board when the blue LED is off or blinking This may cause non recoverable damage to the board 3 4 2 FMM The MIC 5333 supports three FMM sites for feature flexibility and expansion such as 40G 10G FI option VGA output and Intel QuickAssist support for details please refer to table 2 10 This chapter assumes that the MIC 5333 is shipped with the FMM installed Mounting instructions are provided here to support customer development as well as in house RMA and repair For installation of the FMM please follow the below procedures 1 Locate the appropriate FMM1 FMM2 or FMMS site on the blade depending on which FMM site you wish to populate refer to figure 3 9 and make sure the module and the carrier connectors are aligned Insert the FMM module until the connector is firmly seated in the socket 2 Install the screws refer to figure 3 10 and power on the MIC 5333 to make sure the installation is completed 3 the FMM follow the procedure in reverse O z Ad le HY Ee s r w Y fT f T a me zu E EI
53. board SDR also supports the FRU Hot Swap sensor for a possible connected Rear Transition Module 4 4 3 5 BMC Watchdog Sensor The BMC Watchdog sensor is supported according to the Watchdog 2 sensor type listed in the IPMI specification 4 4 3 6 FW Progress Sensor The IPMC SDR contains a FW Progress sensor in order to support logging of the OS boot process The IPMC supports adding and forwarding of SEL entries from the BIOS OS system firmware progress events by sending Add sel entry commands with the matching sensor type to the IPMC through the KCS interface 4 4 3 7 Version Change Sensor A Version Change sensor is supported according to the IPMI specification 4 4 3 8 Physical IPMB 0 Sensor The physical IPMB 0 sensor is implemented by IPMC according to the PICMG specification It s used to monitor the state of the local board IPMBs IPMB A and IPMB B from the IPMC to the backplane connector 4 4 3 9 VR HOT Sensor The IPMC contains a sensor to monitor the state of the voltage regulators on each subsystem The sensor is implemented as a discrete OEM sensor The single bits can be seen in following table Bit 7 6 5 4 3 2 1 0 Description VR VR CPU 1 CPU O HOT HOT Table 4 7 Voltage Regulator Sensor Bits 4 4 3 10 PROC HOT Sensor The IPMC contains a sensor to monitor the state of the CPU Processor Hot signals on each subsystem The sensor is implemented as a discrete OEM sensor and the underlying bit
54. d 5 and reserved for onboard MO 297 SSD storage modules 3Gbps board MO 29 storage module optional 3Gbps board MO 297 storage module optional Table 2 4 SATA Port Configuration on the MIC 5333 2 2 7 USB Controller In the Intel CaveCreek PCH there are 6x USB ports controlled through Enhanced Host Controller Interface EHCI for USB 2 0 high speed support The USB port connection in the MIC 5333 is listed in table 2 6 0 1 Front Panel Ports USB devices on an RTM connected to Zone 3 Table 2 5 USB Ports on the MIC 5333 2 2 8 Real time Clock RTC Because there is no battery installed on the MIC 5333 the integrated real time clock is fed by IPMC management power Due to the on board super cap the date and time can be kept for up to 2 hour periods of power loss 2 3 DDR3 DIMM Memory 2 3 1 Memory Characteristics The MIC 5333 uses DDR3 VLP SDRAM As shown in Figure 2 1 each CPU uses 4 channels on the MIC 5333 and each channel supports one un buffered registered ECC VLP DIMM for a total of 8 sockets Supported memory characteristics on the MIC 5333 are listed on table 2 7 Intel Xeon E5 2600 Series Rea Ch 1 Intel Xeon E5 2600 Series VLP R UDIMM chi2 ME R VLP R UDIMM 3 gt CPU1 Socket R Figure 2 1 DIMM slots on the MIC 5333 LRDIMMs 8GB 16GB and 32GB 1066 1333 1600 106
55. dr 172 21 35 104 Setting LAN IP Address to 172 21 39 1404 4 8 2 2 User Commands user list Get the list of all supported users root localhost ipmitool user list ID Name Callin Dink Awen IPMI Channel Priv LIMELE true true true NO ACCESS callback true true true NO ACCESS 2 user true true true NO ACCESS 4 Operator crue true NO ACCESS user set name lt user id gt username This command is used to change the user name root localhost ipmitool user set name 2 newuser user set password lt user id gt password This command is used change the user password root localhost ipmitool user set password 2 newpassword 4 8 3 SoL Session with IPMItool Advantech recommends using IPMItool to successful open a SOL session The lanplus interface of IPMItool must be used to be able to change SOL parameters and establish SOL sessions Following general IPMItool parameters are needed for RMCP and IPMItool sol commands ipmrtooL I lLenplus lt 1P Address gt U lt User gt P lt Password gt sol SOL Command Command Line Syntax lanplus Specifies as desired protocol H IP Address IP address assigned to the IPMC U User User account default administrator P Password Password used with specified user account default password for user administrator is advantech 4 8 3 1 SOL Parameter Commands sol info channel
56. e Read and Store Configuration OEM commands can be used to read and change several important board settings The following sub chapters describe the needed command details B 2 1 LAN controller interface selection The MMC firmware provides an OEM IPMI command to allow users to switch the MMC connected NC SI interface between one front panel LAN IO RJ 45 connector and the AMC connector Base interface AMC Ports 0 amp 1 These commands can be used to read out the actual selected IPMl over LAN Serial over LAN interface and to change the selection LAN controller interface selection settings OOh Front panel LAN IO 01h Base Interface LAN BI default Read LAN Interface selection ipmitool raw 0 2 0x41 0x39 0x28 0x00 0x04 0x00 39 28 00 setting 5 2 Change LAN Interface selection ipmitool raw Ox40 0x39 0x28 0x00 0 04 0 00 setting 29209 100 2 B 2 2 LAN controller channel selection and priority In addition to the selected LAN controller interface users may need to configure each single LAN controller channel port as a dedicated NC SI interface to the BMC Additional OEM commands for the configuration of the NC SI LAN controller channel selection and priority are provided to allow a flexible configuration LAN channel selection priority setting list 0 The first channel that links up gets the NC SI connection to the BMC 1 Channel 1 is t
57. ed Rear Transition Module RTM Fabric connectivity is implemented using up to two FMM type sites each site connecting to two backplane fabric channels This allows the MIC 5333 to scale from legacy 10GE to high speed 40 network interfaces as well as optional dual dual star support for the most demanding applications in high end data and enterprise networking utilizing 4 hub blades per system A variety of Advantech standard FMMs can be used to implement 10GBaseKR amp 40GBaseKR4 interfaces Beyond that Fabric Mezzanine Module type socket with PCle x8 connectivity provides extension possibilities for additional front port I O offload and acceleration controllers such as Intel QuickAssist accelerators IPSec offload engines or customer specific logic FMMs not only have higher PCI Express bandwidth than AMCs but also integrate well in terms of thermal design cost and board real estate when compared to Advanced Mezzanine Cards This unmatched flexibility combined with the highest performance Intel amp Xeons available make the MIC 5333 equally well suited for application and data plane workloads The onboard IPMI firmware based on Advantech s IPMI core just offers greater modularity and flexibility for the customization of system management features and also provides the framework for added value features enhancing Reliability Availability Serviceability Usability and Manageability RASUM of the product HPM 1 based updates
58. ettings Read COM port UART setting ipmitool raw 0x41 0x39 0x28 0x00 0x08 port 39 28 00 lt setting gt 2 Change COM port UART MUX setting ipmitool raw 0x40 0x39 0x28 0x00 0x08 port setting OW 5 B 2 4 Dynamic Power Budgeting The IPMC provides the option to calculate the power demand depending on the population on the blade e g CPU type RAM This option can be enabled and disabled with commands below default enabled A fixed value is reported by the Get Power Level command in case of disabled power budgeting Read dynamic power budgeting setting ipmitool raw 0x41 0x39 0x28 0x00 0x06 0x00 Response 39 28 00 setting Enable dynamic power budgeting ipmitool raw 0x40 0x39 0x28 0x00 0x06 0x00 0x01 Response Dg wo 300 Disable dynamic power budgeting ipmitool raw 0 2 0x40 0x39 0x28 0x00 0x06 0x00 0x00 39 28 00 y x 9 3 29 gt c eu The IPMC provides the option to enable and disable PROCHOT interrupts to the x86 part The interrupt generation is disabled by default The IPMC provides following commands to enable disable this feature Read PROC HOT interrupts setting ipmitool raw Ox41 0x39 0x28 0x00 OxOD 0 00 Response 39 28 00 setting Enable PROC HOT interrupts ipmitool
59. f the package and ship it prepaid to your dealer Declaration of Conformity CE This product has passed the CE test for environmental specifications when shielded cables are used for external wiring We recommend the use of shielded cables FCC Class A Note This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is operated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user will be required to correct the interference at his or her own expense Technical Support and Assistance 1 Visit Advantech web site at www advantech com support where you can find the latest information about the product N Contact your distributor sales representative or Advantech s customer service center for technical support if you need additional assistance Please have the following information ready before you call Product name and serial number Description of your peripheral attachments Description of your firmware version A complete description of the problem The exact wo
60. firmware activation OK NOTE The front panel FRU LED s 1 and 2 red OOS and green payload LED are flashing during the FW update activation This procedure needs around 20 seconds to finalize the update 5 3 FPGA Upgrade 5 3 1 Upload new FPGA image Type IPMItool HPM 1 upgrade command and select the new FPGA image root localhost ipmitool hpm upgrade mic5333 standard hpm fpga 01 28 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage Versions Upload Progress Upload Image Active Backup File 100 Time Size e ees oes unes 2 15383 LEZ i 01 24 6eea0 Component requires Payload Cold Reset Firmware upgrade procedure successful 5 3 2 Activate HPM FPGA image Although the new FPGA configuration is successfully stored on the board deferred version it needs to be activated before it s loaded into the FPGA chip Following two actions are needed to finish the upgrade 5 3 2 1 HPM 1 activate command Schedule the FPGA load with the HPM 1 Activate command root localhost ipmitool hpm activate PICMG HPM 1 Upgrade Agent 1 0 2 5 3 2 2 Payload cold reset In order to activate the new FPGA image a payload cold reset is required Component requires Payload Cold Reset The payload reset ca
61. gnment pin falls into the receptacle Retaining Thumbscrews Figure 3 5 Alignment pin slides into the receptacle 4 Hold both handle ejectors on either side of the board and then close them to make the board becomes fully seated Make ensure the handles latched securely Fasten the retaining thumbscrews on either side of the MIC 5333 blade The blue hot swap LED on the front panel will show a ON2Blink OFF transition to indicate a normal power on sequence of the MIC 5333 Once the finrmware and payload has been successfully activated the PICMG 3 0 LEDs will be shown as below ___2 __ l Dt Table 3 1 PICMG3 0 LEDs Definition All the LEDs status shown on the front panel is listed in Section 3 6 Jumper Setting amp LED Definition IE Note Regarding the slot information please refer to the backplane chassis manual The MIC 5333 also supports hot swap i e no need to turn off the chassis power before installing the board To extract the MIC 5333 from the chassis 1 2 Unlock the ejector handle at the bottom side next to the FMM bay The extraction request will be delivered to the IPMC The IPMC will perform a graceful shutdown of the ACPI aware operating system The blue hot swap LED will start blinking once the ejector handle is unlocked After the x86 subsystem on the blade has been powered down the blue hot swap LED will light up which indicates the board is ready to be removed Unf
62. he LAN controller used for IPMI communication is connected to the management power domain Thus the LAN interface is accessible even if payload power is off Following IPMItool parameters are needed to connect to the IPMC vial LAN ipmitool I lan H lt IP Address gt U User P lt Password gt lt Command gt Command Line Syntax lan Specifies Ethernet interface H lt P Address gt IP address assigned to the IPMC U lt User gt User account default administrator P lt Password gt Password used with specified user account default password for user administrator is advantech 4 2 4 IPMB L Interface IPMB L is the local interface between the Front Board IPMC and a Module Management Controller MMC on a compliant Rear Transition Module such as the RTM 5104 RTM is connected to the IPMB L bus through 2 bus isolators A RTM can only be reached bridged via one of the blades three main interfaces described in preceding chapters Simplest way to bridge from blade IPMC to RTM MMC is via the onboard KCS interface LIL LOG b 7 t OxAO Command Below example uses the IPMC LAN interface ipmitool I lan H IP Address U User P Password b 7 t Command Double bridged IPMItool commands are needed to use the 0 interface Shelf Manager LAN for RTM accesses I Lam H 9ShMM IP Address A none T Transrt address gt b 7 t
63. he MIC 5333 has two SPI flash devices for storing redundant x86 firmware BIOS BIOS configuration etc The integrated management controller IPMC controls which flash device is active Failover and rollback operations between the flash devices are compliant to HPM 1 By default the MIC 5333 starts to boot from the active BIOS chip and will switch to the backup BIOS chip if it detects a problem such as the BIOS is stuck in POST or fails to boot For more details please refer to Chapter 5 about AMI BIOS setup From an OS point of view there is only one active BIOS SPI flash visible at any time 2 2 6 Serial ATA Controller The MIC 5333 supports a total of 2 SATA lanes In the legacy interface there are two modes of operation to support different operating system conditions In the Native IDE enabled operating system the PCH utilizes two controllers to enable all six ports of the bus The first controller supports ports 0 3 and the second controller supports ports 4 and 5 In AHCI mode only one controller is utilized enabling all six ports and the second controller will be disabled Since the built in Serial ATA SATA controller in the Intel amp CaveCreek is used to support only 2 ports only one controller is utilized to support both ports 4 and 5 in each mode the first controller is enabled in AHCI mode while the second controller is enabled in Native IDE mode On the MIC 5333 SATA 3Gbps support is available on PCH Ports 4 an
64. he preferred port if it is up otherwise use channel 2 if it is up 2 Channel 2 is the preferred port if it is up otherwise use channel 1 if it is up 3 Channel 1 is the only allowed port always use it never change to channel 2 4 Channel 2 is the only allowed port always use it never change to channel 1 The NC SI LAN controller channel setting will be stored permanently in the non volatile EEPROM The default value is O Read LAN channel selection priority ipmitool raw 0x41 0x39 0x28 0x00 0x04 0x01 Response 39 28 00 setting Change LAN channel selection priority ipmitool raw 0x40 0x39 0x28 0x00 0 04 0 01 setting 2 20 WO 5 2 B 2 3 FPGA COM port UART MUX MIC 5333 implements several serial interfaces which can be configured in some ways This is done inside the FPGA with the help of an UART MUX refer to Section 3 3 1 UART Multiplexer The BMC provides OEM commands to configure these UARTS via IPMI The following COM1 COM2 port settings are available Caution Verify the note below about the UART dependency COM interfaces Port Interface Table B 1 COM interfaces COM1 MUX Setting Connection no interface connected open Serial over LAN SOL Table B 2 COM1 UART MUX settings COM2 MUX no interface connected open default Serial over LAN SOL Front Panel RJ45 Front panel mini USB RTM mini USB Table B 3 COM2 UART MUX s
65. ilt in memory controller It is a two chip platform CPU and PCH as opposed to a traditional three chip platform CPU MCH and The Intel Xeon E5 2600 series feature per socket two Intel QuickPath Interconnect point to point links capable of up to 8 0 GT s up to 40 lanes of Gen 3 PCI Express links capable of 8 0 GT s and 4 lanes of DMI2 PCI Express Gen 2 interface with a peak transfer rate of 5 0 GT s The processor supports up to 46 bits of physical address space and 48 bit of virtual address space It is also capable of supporting up to 4 channels DDR3 DIMM memory supporting both UDIMMs and RDIMMs for more details about DDR3 DIMM supported specification please refer to section 2 3 The currently supported processors on the MIC 5333 are listed on table 2 2 Xeon E5 2648L 8C 16T 1 80 GHz 20 MB DDR3 1600 70 Watt LGA2011 Xeon E5 2658 8C 16T 2 10 GHz 20MB DDR3 1600 95 Waitt LGA2011 Table 2 2 MIC 5333 Supported Processors List The 5 series Xeon processors support cache memory as listed below A 32 KB instruction and 32 KB data first level cache L1 for each core 256 KB shared instruction data mid level L2 cache for each core Up to 20 MB last level cache LLC up to 2 5 MB per core instruction data last level cache LLC shared among all cores 2 2 2 Platform Controller Hub PCH Intel s CaveCreek PCH provides power and cost efficient integrated standard peripheral interfaces e g
66. l physical memory available to the system is half of what is populated Mirrored Channel Mode requires that Channel 0 and Channel 2 and Channel 1 and Channel 3 must be populated identically with regards to size and organization DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 2 and across Channel 1 and Channel 3 must be populated the same Lockstep Channel Mode In Lockstep Channel Mode each memory access is a 128 bit data access that spans Channel O and Channel 1 and Channel 2 and Channel 3 Lockstep Channel mode is the only RAS mode that allows SDDC for x8 devices Lockstep Channel Mode requires that Channel O and Channel 1 and Channel 2 and Channel 3 must be populated identically with regards to size and organization DIMM slot populations within a channel do not have to be identical but the same DIMM slot location across Channel 0 and Channel 1 and across Channel 2 and Channel 3 must be populated identically E Note 5 The memory channel mode can configured in BIOS setup menu described in Chapter 5 AMI BIOS Setup 6 Regarding the correct installation of memory modules please refer to Section 3 2 Memory for further details 2 4 Ethernet Interface 2 4 1 Base Interface The MIC 5333 uses an Intel i350 AM4 LAN controller connected to the CaveCreek PCH through a PCle x4 interface to provide dual GbE ports for the Base Interface The Intel
67. mask of the sensor is provided in below table Bit 7 6 5 4 3 2 1 0 Description PROC PROC HOT HOT CPU1 CPUO Table 4 8 Processor Hot Sensor Bits 4 4 3 11 Therm Trip Sensor The IPMC contains a sensor to monitor the CPU Therm Trip state through the FPGA on each subsystem The sensor is implemented as a discrete OEM sensor The single bits can be seen in the following table Bit 7 6 5 4 3 2 1 0 Description Memory Memory Memory Memory Therm Therm Hot G H HotE F Hot C D Hot A B Trip Trip CPU1 CPUO Table 4 6 Therm Trip Sensor Bits 4 4 4 Integrity Sensor 4 4 4 1 Overview The Advantech Integrity Sensor is an OEM sensor according to the SDR Sensor Data Record definitions in the IPMI specification Its main purpose is to monitor internal firmware states and report events to the operator that would otherwise go unnoticed hence integrity sensor Examples for those events are checksum errors firmware update success failure firmware rollbacks 4 4 4 2 Sensor Characteristics The Integrity sensor does not support sensor reading but generates event messages only These events are stored in the local System Event Log SEL and sent to the default event receiver The event message contains three bytes of event data The first byte defines how the event is supposed to be treated the value of defines that event data 2 and 3 contain OEM data please verify the IPMI specification for details on OEM sensors
68. n be performed through different ways If the user is working on the local OS KCS a linux reboot poweroff or halt f user accesses the IPMC through another interface LAN IPMB deactivation and activation cycle is needed in order to update the FPGA NOTE The front panel FRU LED s 1 and 2 red OOS and green payload LED are flashing during the FW update activation This procedure needs around 60 seconds to finalize the update 5 4 BIOS Upgrade 5 4 1 Upload new BIOS image Type IPMItool HPM 1 upgrade command and select the new BIOS image root localhost ipmitool hpm upgrade mic5333 standard hpm bios 00 24 img PICMG HPM 1 Upgrade Agent 1 0 2 Validating firmware image integrity OK Performing preparation stage Services may be affected during upgrade Do you wish to continue y n y OK Performing upgrade stage ID Name Versions Upload Progress Upload Image Active Backup File 50 100 Time Size a ses unes ws Seas BBOSS JI 052272 ues qu vec Component requires Payload Cold Reset Firmware upgrade procedure successful NOTE During the BIOS update the front panel FRU LED s 1 and 2 red OOS and green payload LED will flash This procedure needs around 26 minutes viaa KCS with HPM 1 to complete the update Please do not power off or otherwise disrupt the board during the firmware update process 5 4 2 Activate HPM BIOS image
69. ocessor System Memory Zone 2 Front I O Interface Operating System IPMC Watchdog Timer FMM Miscellaneous Power Requirement Zone 3 CPU Max Speed Chipset BIOS Technology Max Capacity Socket Fabric interface Base interface serial COM Ethernet USB 2 0 Compalibility BMC Controller IPMI Supervision Interval Site Interface Storage Real Time Clock Configuration Consumption RTM Dual Intel Xeon E5 2648L E5 2658 8 core processors 2 1GHz Intel Cave Creek SKU1 and SKU4 Dual 64 Mbit BIOS firmware flashes with AMI UEFI based BIOS 8 0 GT s Four channel DDR3 1066 1333 1600MHz SDRAM 72 bit ECC Un Registered LR DIMM support Configurable up to 256 GB 8 VLP DIMMs 4 8 x 10GBaseKR with dual star backplane topology supported via FMM 5001Q 2 4 x 40GBaseKR4 with dual star backplane topology supported via 5004 1350 GbE MAC PHY supporting two 10 100 1000Base T ports 2 16C550 compatible Serial Ports 1 RJ 45 connector 1 mini USB connector 2 x 10 100 1000BASE T through PCle based i350 MAC PHY 2 Type A ports WindRiver PNE LE 4 2 RedHat Enterprise 5 7 amp 6 2 CentOS 6 1 Windows Server 2008 64bit NXP LPC1768 Cortex M Compliant with IPMI 2 0 using Advantech IPMI code base 1 for x86 BIOS POST OS Boot Application IPMI compliant 1 FMM type socket 2 FMM type sockets FMM type I 2 x PCle x8 from CPU socket 0 and
70. rding of any error messages Warnings Cautions and Notes Warning Warnings indicate conditions which if not observed can cause personal injury Caution Cautions are included to help you avoid damaging hardware or losing data for example there is a danger of a new battery exploding if it is incorrectly installed Do not attempt to recharge force open or heat the battery Replace the battery only with the same or equivalent type recommended by the manufacturer Discard used batteries according to the manufacturer s instructions Note Notes provide optional additional information Document Feedback To assist us in making improvements to this manual we would welcome comments and constructive criticism Please send all such in writing to support advantech com Packing List RJ45to DB9 Console Cable x1 p n 1700002270 Mini USB to USB Console Cable x1 p n 1700018550 Warranty certificate document x p n 2190000902 If any of these items are missing or damaged contact your distributor or sales representative immediately Safety Instructions This section provides warnings that precede potentially dangerous procedures throughout this manual Instructions contained in the warnings must be followed during all phases of operation service and repair of this equipment You should also employ all other safety precautions necessary for the operation of the equipment in your operating environment
71. rmats This chip includes a complete USB 2 0 full speed function controller bridge control logic and a UART interface with transmit receive buffers and modem handshake signals For a terminal PC to connect to the console function on the MIC 5333 with a mini USB to USB cable the CP2102 driver is available for download from Silicon Labs website hyperlink below and must be installed on the terminal PC The PC can for example run a Linux 2 4 or 2 6 kernel or Windows XP The miniUSB port is bus powered i e powered by the terminal PC and the COM port will not be lost when power cycling the blade or ATCA system Prerequisite Commercial mini USB to USB cable Advantech P N 1700018550 2102 driver needed to be installed on the terminal PC before using the console please download from https www silabs com products interface usbtouart Pages default aspx Serial over LAN SoL User may also establish the console via SoL function which is described in section 4 6 Serial over LAN SoL Prerequisite RJ45 Ethernet cable and IPMItool see section 4 6 2 1 IPMItool Note When SoL is used as the console terminal please skip Section 3 3 2 and 3 3 3 UART1 amp UART2 Zone3 The MIC 5333 connects two UART interfaces to the Zone 3 To establish the console link through the RTM please refer to the RTM user manual 3 3 2 Terminal Emulator A terminal emulator application must be available on the terminal P
72. sserted Asserted Asserted Asserted Asserted Asserted Asserted Asserted 08 17 2012 Hot Swap HOTSWAP Transition 08 17 2012 09 17 04 FRU Hot Swap HOTSWAP Transition to Asserted b 08 17 2012 09 34 57 OEM INTEGRITY Specific Asserted 4 6 Watchdog Timers Two kinds of watchdog timers are built into the IPMC One is used to supervise the IPMC firmware watchdog and the other is used to supervise the x86 payload BMC watchdog When the IPMC is firmware is stuck the IPMC watchdog bites and resets the IPMC The payload is not affected from this watchdog event The BMC Watchdog of the MIC 5333 IPMC is used for BIOS Power Self Test POST watchdog OS load watchdog Application level watchdog user application dependent After Payload power on the BMC Watchdog will monitor the BIOS POST process and will bite in case the BIOS fails When the watchdog bites the payload will be reset and the IPMC selects the other BIOS image to boot Once BIOS POST is finished successfully the BMC watchdog timer is disabled before the OS boot loader starts If the BMC watchdog is enabled again for OS load supervision the user needs to make sure the running OS will reset or disable the BMC watchdog afterwards If not the IPMC will reset the payload as the timeout action The default timeout period for the BMC watchdog used as the BIOS POST timer and
73. t Swap BMC WATCHDOG Watchdog 2 IPMI BMC Watchdog sensor ow FW PROGRESS System Firmware IPMI FW Progress sensor Progress Discrete VERSION CHANGE Version IPMI Version Change Change sensor Discrete IPMB 0 IPMB Link PICMG 0 status sensor Discrete VR HOT OEM Discrete Voltage regulator HOT Status PROC HOT OEM Discrete Processor HOT status THERM TRIP OEM Discrete CPU 0 1 Thermal Trip BOARD POWER Other Units based Total Board Power indication V48 CUR Current Threshold 48V Power Input module Dibia HU CAP VOL Voltage 48V Hold Up capacitor Threshold voltage 3 V48 A VOL Voltage 48V Power Input module N N 9 1 LM 8 EN 14 V48 B VOL Voltage 48V Power Input module 15 BAT 0 VOL Voltage Battery Gold cap voltage 16 MAN 3 3 VOL Voltage Management Power voltage 17 5 0 VOL Voltage Management Power voltage 18 PAY 3 3 VOL Voltage Payload Power voltage 3 3V 19 PAY 5 0 VOL Voltage Payload Power voltage 5V 20 PAY 12 VOL Voltage Payload Power voltage 12V 21 LAN 1 0 Voltage i350LAN controller voltage 22 LAN 1 8 VOL Voltage i350LAN controller voltage 23 PCH 1 0 Voltage PCH supply voltage 1 0V 24 1 5 VOL Voltage PCH supply voltage 1 5V 25 1 8 VOL Voltage PCH supply voltage 1 8V 26 CPUO O 85 VOL Voltage 0 voltage 0 85V 2 CPUO 1 05 VOL Voltage 0 voltage 1 05V 28 CPUO CORE VOL Voltage
74. t User Access App 44h Set User Name App 45h Get User Name App 46h Set User Password App Activate Payload App 48h Deactivate Payload App 49h Set User Payload Access App 4Ch Get User Payload Access App 4Dh Get Channel Payload Support App 4Eh Get Channel Payload Version App 4Fh Master Write Read App 52h Get Channel Cipher Suites App 54h Set Channel Security Keys App 56h Event Commands IPMI IPMI PICMG3 0 AMC2 0 Command Spec Ref Requirement Set Event Receiver S E 00h Mandatory Get Event Receiver S E Mandatory Platform Event a k a Event 23 3 S E 02h Mandatory Message Sensor Device Commands IPMI IPMI PICMG3 0 AMC2 0 Command Spec Ref Requirement Get Device SDR Info S E 20h Get Device SDR se zm Reserve Device SDR Repository S E 22h Get Sensor Reading Factors 23h Set Sensor Hysteresis 24 Get Sensor Hysteresis S E 25h Set Sensor Threshold S E 26h Get Sensor Threshold S E 27h Set Sensor Event Enable S E 28h Get Sensor Event Enable S E 29h Get Sensor Event Status S E 2Bh Get Sensor Reading 35 14 Mandatory Get Sensor Type 35 16 Optional FRU Device Commands IPMI IPMI PICMG3 0 AMC2 0 Command Spec Ref Get FRU Inventory Area Info FRU Get FRU Inventory Area Info Area Info 344 Storage 10h Mandatory Write FRU Dat Mandatory SEL Device Commands PICMG3 0 2 0 Spec Ref Requirement mes on
75. t all of 4x KR interface link FMM 5001Q Active Notall of 4x KR interface Active NoLink 40Gb s Link OO 40Gb s Active Fl port 1 2 Speed Link 10Gb s Link Clive 106 Active Link 10Gb s Link OO 10Gb s Active Fl port 1 2 Speed Link FMM 5001B Acti QO Q 1G Active NoLink Q 1Gb s Q 100Mb s Q 10Mb s Port 1 2 BI port 1 2 Active Link Active port 1 2 Speed No Link Q User defined USR Status Q User defined 1Gb s 100Mb s 10Mb s LAN Port 1 2 Q Link Link Active OO Active No Link Out of System out of service Q FW active payload enabled Health Status OO O Fw active payload disabled O FW is not active Q Board is not activated ready to be swapped Hot swap Q O Board is de activating unsafe to swap Board is active unsafe to swap Table 3 3 LED Definition Note Fl channel 3 and 4 support is optional and only active when populating the board with the FMM 5004ME 40G version or FMM 5001BE 10G version of the n FMM site 1 on the MIC 5333 3 4 7 Jumper Settings This section describes the jumper definition of the MIC 5333 f In normal operation users should not need to accessor modify jumpers 1 2 Closed rom MS Normal Mode Default Clean CMOS 2 3 Closed fe Clear CMOS 123 Shelf GND open to logic 2 3 Closed Fe e GND
76. terfaces with four 10GBaseKR ports each The other option to deploy the MIC 5333 with 40G technology is by using the FMM 5004M which uses Mellanox 3 EN controllers to provide dual 40GBaseKRA interfaces Model Name Jescription Chip FMM 5001Q Four 10GBaseKR FI Quad Intel 82599ES FMM 5004M 40GBaseKRA FI Mellanox CX 3 V FMM 5001B 10GBaseKX4 and XAUI FI Intel amp 82599EB v Table 2 11 Advantech FMM 5000 Series Configuration at Fabric Site For the front panel customers may choose from the following Advantech FMM 5000 options or request a customized FMM For detailed Advantech standard product FMM specifications please refer to table 2 12 Model Name Descriptior Chip FMM 5001F Dual 10GE Module with 2x SFP front IO Intel amp 82599 2x SFP FMM 5002 Server Graphic Support for Debug Bring Up SM750 1x VGA port Intel FMM 5006 QuickAssist Accelerator FMM N A CaveCreek Table 2 12 Advantech FMM 5000 Series Configuration on the front panel FMM 3 Site 3 Installation This chapter describes the procedure to install the MIC 5333 into a chassis Peripherals DIMMs SSD installation jumper settings and LED definitions are also described here 3 1 Processor The MIC 5333 is shipped with two CPUs and heat sinks installed from the factory Please do not attempt to remove the heat sinks or the cooling performance will be affected Tampering with the heat sinks will result in a loss
77. tting Store synchronization setting ipmitool raw 0x40 0x39 0x28 0x00 0x07 0x00 setting 5 gt 39 20 90 B 3 Read Port 80 BIOS POST Code OEM command To be able to read out the actual BIOS boot state via IPMI the IPMC provides an Advantech OEM command to reflect the actual BIOS POST Port 80 code ipmitool raw 0x2e 0x80 0x39 0x28 0x00 39 28 00 POST Code 5 2 In case of upper non recoverable temperature sensor events of payload dependent The IPMC provides the option to calculate the power demand depending on the B 4 Load NVRAM Defaults OEM command The IPMC implements an OEM command to be able to load the NVRAM default values from SW side without the need of extracting the blade and performing any jumper plug and re plug ipmitool raw Ox81 0x39 0x28 0 00 Response oJ 9 WO B 5 MAC Address Mirroring OEM command The blade LAN Controller MAC addresses will also be stored in the FRU EEPROM making the MAC s available even if the payload is not powered This helps to relate the MAC address and the physical logical ATCA blade location The board is equipped with 5 MAC addresses in total Please find below the used order in the FRU EEPROM Internal Use Area IO Interface 2 IPMC MAC w FMM MAC addresses if plugged Table B 4 MAC Address mapping table Read MAC Address OEM command ipmitool raw 0x2e Oxe2 0x39 0x28
78. vanced Configuration and Power Interface Advanced Host Controller Interface Advanced Mezzanine Card Advanced Programmable Interrupt Controller Advanced Telecommunications Computing Architecture Base Interface Baseboard Management Controller Carrier Management Controller Enhanced Host Controller Interface Fabric Interface Fabric Mezzanine Module Field Replaceable Unit Firmware Gigabit Ethernet Hardware Platform Management I O Controller Hub Intelligent Platform Management Controller Intelligent Platform Management Interface Memory Controller Hub Non volatile Random Access Memory Out Of Service Platform Controllers Hub PCI Express Platform Environment Control Interface PCI Industrial Computer Manufacturers Group Pre boot Execution Environment QuickPath Interconnection Registered DIMMs Remote Management Control Protocol Rear Transition Module Receive Serial Attached SCSI Serial Advanced Technology Attachment Small Computer System Interface Sensor Data Record Serializer Deserializer ShMC SOL TCLK TPM TX UDIMM UHCI VLP XAUI Shelf Manager Controller Serial Over LAN Telecom Clock Trusted Platform Module Transmit Unbuffered DIMMs Universal Host Controller Interface Very Low Profile X means ten Attachment Unit Interface Chapter 1 Product Overview This chapter briefly describes the MIC 5333 1 1 MIC 5333 Overview Advantech s MIC 5333 is 40G dual processor ATCA blade based on
79. will automatically switch to the connection except for SOL where an input character needs to be received The UART multiplexer switch can also be set via OEM command please refer to Appendix B Advantech OEM IPMI Command Set for details For example when RJ45 to 9 cable is plugged into the MIC 5333 by detecting a character entered through the cable the UART multiplexer will automatically bridge the console to the terminal PC through this interface Once another mini USB cable is connected and the user enters any character the multiplexer will then switch the output to this interface as this is the latest request The previous RJ45 link will consequently become disconnected Step1 The user establishes a console link through any available output e g RJ 45 Step2 When the user plugs another console cable into the MIC 5333 e g miniUSB the UART MUX will switch the output from RJ45 to this new interface last in first serve rule 222 Step3 The original link RJ 45 becomes disconnected Figure 3 2 UART Multiplexer Switching Mechanism RJ45 For a terminal PC to connect to the console function on the MIC 5333 with a RJ45 to DB9 cable no additional driver is needed Prerequisite RJ45 to DB9 cable Advantech P N 1700002270 mini USB COM2 The MIC 5333 uses a USB to UART bridge called CP2102 GM from Silicon Labs to convert data traffic between USB and UART fo
80. window on exit C Awas C Never clean exit Figure 3 3a PuTTY Configuration Pul TY Configuration Figure 3 3b PuTTY Configurations If the connection is successful and the user enters BIOS setup menu upon boot the MIC 5333 BIOS setup menu will be displayed on the PuTTY screen g COM12 Pal TY BIOS Information BIOS Vendor Core Version Compliancy Project Version Build Date and Time Memory Information Total Memory American Megatrends 4 6 4 1 0 12 x64 UEFI 2 1 MIC 5333 5333INH12 04 20 2012 11 19 19 8192 MB DDR3 Choose the system default language gt lt Select Screen v Select Item Sat 01 01 2005 Enter Select 05 01 43 Change Opt F1 General Help F2 Previous Values F3 Optimized Defaults F4 Save 5 Exit JESC Exit Lame Oe zu E um aun GE ER EE aun am uama GEN GER ZEN GEN uma am GENE am System Date System Time Access Level Administrator Figure 3 4 MIC 5333 BIOS setup menu shown on PuTTY screen 3 4 Installing the MIC 5333 3 4 1 MIC 5333 To install MIC 5333 into the chassis 1 Leave the ejector handles in the open position 2 Choose a node slot in chassis and align the PCB edge to the card guide rail 3 Carefully slide the MIC 5333 into the system until the connector contacts start to mate into the backplane Make sure the front panel ali
81. y Rollback status 37h Initiate Manual Rollback 38h h Finish firmware upload 33h h h Appendix B Advantech OEM IPMI Command Set Advantech management solutions support extended OEM IPMI command sets based on the IPMI defined OEM Group Network Function NetFn Codes 2Eh 2Fh The first three data bytes of IPMI requests and responses under the OEM Group Network Function explicitly identify the OEM vendor that specifies the command functionality To be more precise the vendor IANA Enterprise Number for the defining body occupies the first three data bytes in a request and the first three data bytes following the completion code position in a response Advantech s IANA Enterprise Number used for OEM commands is 002839h The BMC supports Advantech IPMI OEM commands listed in the below table otore Configuration Settings 2Eh 2Fh Read Configuration Settings O0h 2Eh 2Fh Read Port 80 BIOS POST Code 00h 2Eh 2Fh Clear CMOS 00h 2Eh 2Fh Read MAC Address 00h 2Eh 2Fh Load Default Configuration 2Eh 2Fh F2h B 1 IPMItool raw command To be able to use the Advantech OEM commands with the open source IPMItool users have to use the raw command of IPMItool Please find the below command structure details of the IPMItool raw commands General raw request ipmitool raw netfn cmd data Response if raw netfn is 2Eh OEM Group lt IANA Enterprise Number data B 2 Configuration Setting OEM commands Th

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