PCI S5920 Developer's Kit User Manual And Technical
Contents
1. CADCLK2 2 192 3 ren it PTBURST 423 39445 pree PTBURST 695 5C 6 Cio PTRDY 857 758 2 lt PTNUMI Q DQ23 DT 10 9 9 310 Ros PTNUMO S ETNUMO 12 Dem 44 PTADR 14 13 13 14 PTWR 5020 PTWR DXFER 16 15 15 16 DOIS C14 C15 16 7 18 9 20 DXFER gt 18 17 17 18 Be ee SYSRST S SYSRST 20 19 19 20 pois a ia di 1 CADDINT A 2 21 21 22 44 TROF 1921 24 23 23 24 D 4 25 25 26 ca SELECT SELECT 28 27 27 28 DU wre 30 29 29 30 DE 1 INT LOAD T ES Bar NT LOAD _ M 34 33 33 34 Des 4 MDMODE 36 35 35 36 Q R6 26 35 d DOI d EXTEVAL _EXTEVAL 4 39 39 40 200 lt 2 4 42 gt RPI 44 43 43 44 46 45 45 46 jm em em em em C28 C29 48 47 47 48 50 49 49 50 3 bd J4 J5 lt 42 9 192 10K 4 BE 3 J N 5 35 1 BE 2 Q 7 75 6 4 BEST 18 sm 3 EA 2 080 ADRS 14 13 13 4 2922. 1 2 3 4 20 AD3I AD31 146 5 1 20 AD30 147 AD30 AD30 DQ30 B21 AD29 AD29 148 25 DQ29 AD29 AD29 DQ29 A22 AD28 AD28 152 37 DQ28 AD28 AD28 DQ28 823 27 AD27 154 45 DQ27 AD27 2 4 AD27 DQ27 A23 AD26 AD26 155 53 DQ26 AD26 AD26 DQ26 B24 AD25 AD25 156 65 DQ25 AD25 AD25 0025 25 AD24 AD24 158 77 DQ24 AD24 8 0024 B27 AD23 AD23 2 8 85 5023 AD23 AD23 8 0023 A28 22 AD22 3 93 DQ22 AD22 AD2 8 829 AD2I 4 J 105 DQ I A29 20 AD20 6 21 8 117 DQ20 AD20 AD20 30 ADI9 ADI9 7 53 125 DQI9 ADI9 ADI9 502 A31 ADIS ADIS 8 d 133 2018 ADIS ADIS ADIT 832 ADIT ADIT D lap 09 nom DQI7 ADIS l4 Ape 715 pois 2157 DQI6 A44 5 ADIS 32 A 76 DQIS ADIS ADIS 2015 845 ADI4 Apia 78 DQI4 A46 ADI3 ADI3 35 79 DQI3 ADI3 ADI3 DQI3 847 ADI2 36 80 DQI2 ADI2 ADI2 012 ADII ADIT 38 ADI poit 8 848 ADIO 39 ADIO 83 DQIO A49 40 84 9 2 ADO ADI DQ9 S BS2 ADS ADS 42 86 DQS ADOS ADS Apo 833 AD ADT 44 AD7 88 DQ7 1 Apos 45 AD6 46 AD6 pos 52 DQG B55 ADS ADS 47 94 DQS 5 ADOS ADS 55 A
3. 5920 8 16 32 Bit Add On Bus lt 8 16 Bit Add On Bus Interface PCI Local Bus Figure 1 1 Developer Kit Block Diagram Chapter 1 Introduction Page 2 The Developer s Kit Goal The S5920DK1 was designed to help both hardware and software engineers go into production with a new design as quickly as possible Hence AMCC has provided the following A fully functional hardware design example of an SRAM interface and an ISA bus card interface Documentation text files to help come up to speed quickly on all parts of the 5920DK1 Hardware all source files to re create the 5920DK1 boards and use them as the basis for your design Also included are all source files for the EPLDs Software program examples and utility tool source code to help develop your new software and debug hardware Win95 and WinNT software device drivers for the 5920 and S5933 are currently available through our Development Partners Please visit our web site at www amcc com for up to date links Chapter 1 Introduction Page 3 Developer s Kit Features The S5920 PCI Card The Primary design aid to the Developer s Kit is the main PCI Developer Card This board contains the 5920 device interfaced to the PCI Bus giving the developer a functional example of device location trace lengths routing and decoupling The Add On Bus of the 55920 is interfaced to board signal headers SRAM and an EPLD device The EPLD supplied serv
4. LL PTBURST MEMW MEMW PTBEWS LIRDY amp SMEMW TORF SMEMW PTBE 0 3 2 15 1 05 IW IOR 12 22 NEG IS PTBEI MEMCHI6 02 OCS Te MEMCHI6 19 PTBEO IOCHI6 70 IOCHRDY 5 1OCS16 NUM 0 1 PTNUMI IOCHRDY IOCHRDY NUMO 21 71 SRDY PTADR 22 PTNUMO SRDR 75 PTADR 2 PTADR IOCHCHK PTWR 23 TI RESET PTWR PTWR RESET DXFER 25 78 ISA_INT DXFER DXFER ISA_INT SYSRST 27 81 SAI SA O SYSRST SYSRST SAL ADDINT 29 82 SAO ADDINT ADDINT SAO IRQR 31 83 DATA_LAI TROF IRQ DATA LAI SELECT 32 86 SELECT SELECT LAO WR 33 87 DATA_DIR WR WR DATA_DIR RDA 34 94 DATA RD BEHOZ PD DATA ENS 95 ADDR LA BE 0 3 BE3 ADDR LA 98 OPTIONS VO BEL VO 99 OPTIONS 100 OPTIONS 16 BEOR vO 2 6 ADR6 TDI 1 Ap T we RIL 2 ADR4 3 id 3 a 4 4 ADR2 5 00101 VO 6 CR 10K 6 DQ 47 I vos 2 ro 0 veca 8 AAA 8 4 DIO 9 B 9 4 gt UO 57 10 24 1040 5 gt 70 55 vor vac obro 7 37 0 OPO EPLD PROGRAMING yo o DIO NA on 70645 lt on 7096s 1 1 1 e 1 2p SEN gt OPTION2 03 4 AA x gt OPTIONS 9 5 6 12 A OPTIONS N aie Vai OPTIONS
5. 2DIR 2CBA spo 33 Bs Bs 33 pa Dot 6 1M 1Bl 7 SDI 1 1A2 1 2 DQ 313 m 2 502 9 e dpa 503 DO4 10 45 27 SD4 DOS 12 145 7 185 735 SD5 DOS 13 _ 146 186 44 SD6 187 507 14 23 SD7 DOS 15 8 e IBI 42 SDS DOI 16 71 SD9 DO 17 _ 2 2 5 282 40 5010 Dos 19 243 amp 283 38 SDI DUM 39 2A4 Q 284 37 5012 Don 21 243 285 36 SDI3 2A6 286 Dols 24 247 287 1 Q 2A8 _ 2B8 23 VCC 45V Title Size Number Revision A Date 5 Feb 1998 Sheet of File H CD ROM ISA_DRVR SCH Drawn By 1 2 3 4 5920 ISA Adaptor Card Sheet 3 Chapter 5 Developer Kit Design Aids Page 36 SBHE MEMR SMEMR MEMW SMEMW IOR 16 10 516 IOCHRDY SRDY IOCHCHK RESET SYSCLK Osc TC AEN MASTER REFRESH DRQ7 DRQ6 DRQS DRQ3 pra DRQI DRQO DACK7 DACK6 DACKS DACK3 DACK2 DACKO 18015 IRQI4 IRQI2 IRQII IRQIO 1809 1607 1606 IRQS IRQ4 IRQ3 ISA_CON LA23 LA22 LA20 LAI9 LA18 LA17 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SAI SAO 015 014 013 012 SDII 010 09 08 07 06 05 04 03 02 01 00 A12 A20 A29 PT lt SD 16 BAIE
6. 4 41206 yog 17 4 4159 0027 25 21104 yop 15 0010 MADII 25 Ant io DQ26 MADIO 23 night voi L 4 DQ9 23 sig voi 4 0025 _ 26 ng yoo DQS MAD9 26 t yog 5024 27 98 MAD8 27 A MAD 57 A MAD 5 45 c MAD6 6 MADS 7 MADS 7 s U3 8 5 US 0 2 lt 39 38 n 1 08 9 12 A 2E 32 10 1 37 A0 WE A0 WE 10 ii 2 40 10 2016 10 U6 82 MADIG MADI6 2 21 DQ7 MADI6 2 ke 1O07 0015 3 pois Apis l MADIS MADIS 31 Ais e yos 20 DQ6 MADIS 31 Ais ex 006 DQi4 4 28 3 4147 yos 9 DQS 3 442 yos DQI3 8 Q Apia 0 28 35 oq 18 DQ4 28 DQI2 10 mg 7 MADE 4 41206 yos 17 DQ3 4 41500 u pou MADII 25 413 yo 5 DQ MADII 25 Ant 192 010 12 2 56 MADIO 23 14 DQ 23 200 5 ADIO AI0C VOL AI0C VOL 9 14 65 MAD9 26 13 DQO 26 DOS 15 poe AD 67 MADS Maba 27 49 95 190 27 9 22 100 807 16 Do gt LL MAD MAD 5 ci B 1 8 Aps 69 MADS MAD6 61 6 6 DQS 19 pos 9 8 5 MADS 7 5 02 7 lhs UA DQ 21
7. 83 MAD4 8 8 22 E 6 MAD3 9 DQ lp 58 MAD __10 w 22 MAD 10 2 DQI 25 Ap 54 MADI 11 gt 0 MADI 1 gt 00 0010 31 DQO 21 Apo 9 MADO 12 o we 29 12 49 we 2 MEO ues MEI 1 28 5 ME2 NM PTBE 0 3 Te 85 PTBEO ME3 73 86 MRD 59 MWR PTBURST 2 87 PTBURST MWR lt PNM S PINUMI B PINUMI of 1 16 S ETNUMO 22 PINUMO 2 120 RI 08 2 Prage ADI 26 prADR 5 17 775 EPLD PROGRAMING PTWR PTWR 4 DXFER 35 L DXFER amp SV SRSTH 91 DXFER 92 10K 5 SYSRST 09 59 IN GCLRn INJOE2n 90 6 EXTEVAL 53 EXTEVAL IN OEIn 39 10K 7 gt GCLK2 IN GCLK 8 VCCI RTTY TO 9 gt K JP6 5 0 Title oG lt H ADCLK2 3 lt ADCLK2 TBD Size Number Revision NIN IY1 MEMCLK n Date 5 Feb 1998 Sheet of File 5920 2 Drawn 1 2 3 lt 010 31 ADCLKI J3 ee o C2 C3 ls C8
8. BALE SBHE SBHE MEMR MEMR gt SMEMRF SMEMR MEMW gt SMEMW ins IOR rows OWE s 6 IOCHIG IOCS16 TOCHRDY IOCHRDY a SRDY OCHCHK RESET RESET 2 SYSCLK 14 3181MHz 3 our vec CISA INT SAINT RP2 SA23 SA22 SA21 SA20 SA19 SA18 SA17 SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SAI SAO 015 014 013 012 5011 210 09 08 07 06 05 SD4 SD3 SD2 SD1 00 74AC20 U7B 74A C20 Title Size Number Revision A Date 5 Feb 1998 Sheet of File _ Drawn By 2 3 4 55920 ISA Adaptor Card Sheet 4 Chapter 5 Developer Kit Design Aids Page 37 55920 Pinout and Pin Assignment Bus s a E BRERBPRCdoOSSGONfORLSsSESSSUSOPBSOS SSSS 5595 685 998285582585885595625858588 GND 121 80 5 0012 PTNUMO 122 79 0013 PTNUM1 123 78 0014 IRQ 124 77 0924 0019 125 76 0015 SYSRST4 126 75 SELECT SDA 127 74 c SCL 128 73 129 72 c3 RD amp GND 130 751r vcc 1
9. s MEMCHIG HEADER 5X2 IOCHIG TOCHRDY TOCHCHKE VY 10K A Title Size Number Revision A Date 5 Feb 1998 Sheet File H A CD ROM ISA_CNTL SCH Drawn By 1 2 3 4 5920 ISA Adaptor Card Sheet 2 Chapter 5 Developer Kit Design Aids Page 35 1 2 4 1 c 24 20E 48 ICLK DO 3L 0 00131 0 p SA 3 2 102 1Q2 SD 16 0 Dos 103 103 DO4 D4 S 104 Des 15 P 105 Dos W 1 6 106 po 33 197 107 DOE 27 1 ips Ej 108 pos 26 201 5 202 202 DOIT 3 203 Q 203 DOI2 30 204 204 3 2D5 205 29 DOM 27 226 206 2 7 207 DOIS 26 28 208 c1 c2 c4 les les cs Ta Ta Ja Ja bd bd bd bd DOIS 19 11 12 DOI 444 4 DUE 0023 20 i Eee rey bd bd 2 16 17 T 19 _ C21 20 20 a 23 _ C22 34 26 31 1 a 560 10E 1 i 0 20E 224 IDIR ICBA 4 35 1 neo
10. Bus Controls Register Access Controls Pass Thru Data Controls Mail Box Bus NVRAM Bus Add On User Bus
11. byte object Hexadecimal notations are indicated with a trailing h or a leading Ox 9A4Fh 0110h Binary notations are indicated with a trailing b 1010b 0110b Developer Recommended Documentation AMCC Data Book 5920 PCI Interface supplied PCI Local Bus Specification Revision 2 1 PCI SIG PCI BIOS Specification Revision 2 1 PCI SIG Other related Applications Notes and Design Notes can be downloaded from the AMCC website at http www amcc com To obtain listed documentation from the PCI SIG contact PCI Special Interest Group P O Box 14070 Portland OR 97214 800 433 5177 503 797 4207 FAX 503 234 6762 Chapter 1 Introduction Page 5 2 DEVELOPER HARDWARE INSTALLATION Developer s Kit Contents The 5920 Developer Kit contains the following hardware software and documentation Primary Developer 5920 PCI Card This card is the main design aid of the 55920 Developer Kit We recommend designers follow this design as an example of correct device location trace lengths routing and decoupling Contains Serial nvRAM 32K DWORDs SRAM 128K optional Pre programmed EPLD Four Add On bus to logic analyzer connectors Four user design to Add On bus interface connectors e ISA Adapter Card This card is designed to help convert existent ISA based cards to PCI based designs When connected to the main PCI card virtually any ISA card may be inserted Hard
12. cedet eia age ne Jumper Descriptions Fest Point Descriptions onn obese iem ERR REOR Teen ve RR PCB Connector Descriptions ISA Adaptor EU eR ee e UD uie RP Ms Jumper Descriptions Point Descriptions oerte D RR PER FERRE PCB Connector Descriptions zero diete Chapter 5 Developer Kit Design Aids SCHEMALICS eiecti eee eee ie eee eed eee tenes mr IgM ETE Software Source Code 24 24 24 25 26 27 27 27 27 28 1 INTRODUCTION Introduction The AMCC PCI Developer s Kit contains everything needed for the PCI developer to immediately begin operating and experimenting with a 5920 based PCI design For software engineers the Developer s Kit 15 a fully functional PCI to Add On bus test card The programmer can immediately begin testing and operating numerous aspects of PCI Bus to Add On Bus data transfers timings control and overall operation The programmer can also test and become familiar with the various aspects of PCI BIOS functions and PCI Configuration Space operation A set of DOS based development programs allow the programmer to view and change device register contents from the PCI Bus as well as view and change PCI configurations Additional development software provides downloading editing configuring and programming capability to the optional serial boot
13. e 53920 PCL Card mam poete iier uti ISA Adapter Card Ee eoe nO feet i SOftW ate eg dbpO onl eR ei Ae eere Notional tace retro rer ette Developer Recommended Chapter 2 Developer Kit Hardware Installation Developers Kit Contents irte tt e prete be ive ete uites System Requirements eei ete etre tese I E e e setae Installing H rdware eter epe periere Dee epe ep Ede Installing the 5920 PCI entierement eene Installing the ISA Adapter esses e Connecting the HP Logic Analyzer Installing The Software System Checkout iet pr eol ehe ig ttg Chapter 3 Developer Kit Software Introduction ete e Win95 and WinNT Software Device Drivers Software Tools SERM PI PCI SIG ID Policy ete EE HR EHE AURA Utility Program ete i tee edes OPR EXE U tility Pro grain a eoe rt etie CFG EXE Utility Program ntt eee itte re Ete it eie i eei fe ie ete utn MEMRW EXE Utility Program SCAN EXE Utility Program nnt etin perte pr ree DKTEST EXE Utility onere eee Chapter 4 Developer Kit Hardware 553020 PCI Card eere uite cette ete
14. load nvRAM contained on the main Developer Kit PCI card For the hardware designer the Developer s Kit provides fully functional PCI to Add On bus design examples The main 5920 PCI card shows Add On bus connection to onboard SRAM The ISA Adapter card allows the designer to plug in an existent ISA card to the Add On bus to begin logic optimization and reduction The Developer s Kit comes complete with schematics PCB artwork EPLD equation source code for each application example and development software source code The designer is able to implement portions or all of an Add On bus design using a supplied bread board Extra headers and EPLD sockets are available in the Developer Kit to further assist in proto typing and general experimentation Dedicated Hewlett Packard PCI logic analyzer headers are provided for directly cable connection Chapter 1 Introduction Page 1 Developer s Kit Overview The PCI Developer s kit contains two printed circuit boards plus a software tools CD ROM The 55920 PCI card contains 55920 SRAM and a pre programmed EPLD containing Add On bus control functions This card was developed to demonstrate interconnection of the 55920 PCI interface chip to the PCI Bus and interconnection of the 5592075 Add On Bus to a basic SRAM design The onboard EPLD is specifically programmed to control the Add On bus for Active Mode data transfers for burst or single cycle data reads and writes to the SRAM The Add On bus sign
15. menu Typing opr followed by a will display the option list COMMAND SYNTAX R 33 A W lt register gt lt data gt Option Menu Display the 55920 Operation registers Displays the 5920 Base Address 0 space in a hex table format W lt register gt lt data gt Writes to the register named with the hex data Example w omb 103 33 Displays the 55933 Operation registers if installed Used for S5933DK1 A Displays the Add On Operation registers through the S5933DK1 ISA card Displays help menu Example of Operation register display 5920 Operation registers Out Mailbox OMB 00000020 In Mailbox IMB 00000 Mailbox Flags MBEF 0000F00C Interrupt Reg INTCSR 00000C0C Reset Control RCR 00000000 Pass Thru PTCR 80808080 NOTE Some of the utility programs perform a PCI Bus scan and list all found devices each time the program is run with a task The user is then required to select which PCI device in the list the program task is directed to before performing it The opr exe program is an example of this By using the DOS SET command to assign data to variables the PCI device selection menu can be skipped Example by typing SET AMCC_DID 5920 will assign 5920 to the device ID The next time opr exe is run it will use the 5920 selection from the PCI Bus scan and perform the task without asking Only one variable needs to be set to identify a PCI device The variables tha
16. schematic for further details Test Point Description There are no test point incorporated on the ISA Adaptor card PCB Connector Description None J2 tru J5 The Add On bus from the 55920 is wired to an on board EPLD and SRAM application design The Add On bus is also paralleled to these four connectors When the ISA Adaptor card is in place these connectors become the Add On bus interface by removing the on board EPLD from the design This is accomplished thru grounding pin 40 of J2 which is a disable signal to the EPLD This applies to the ISA Adaptor card as well as any user proto deign connected to the 5920 PCI card J6 This connector is supplied for programming the EPLD U1 on the ISA Adaptor card For programming use the Altera programming cable P N PL BYTEBLASTER available for approximately 150 from your local Altera distributor Chapter 4 Developer Kit Hardware Page 27 Chapter 5 Developer Kit Design Aids The AMCC PCI Developer s Kit was designed to provide everything needed for the developer to immediately begin operating and experimenting with a 55920 based PC design Additionally the kit includes many design development aids intended to help reduce the design time for both software and hardware designers Software source code schematic and PCB source files and EPLD equation files are all included as aids to new 5920 based PCI designs The following section details these design aids Sche
17. 31 151 ADO ADI AD2 AD3 ADA ADS AD6 07 ADB 09 010 ADI ADI2 13 014 015 016 ADIT 18 19 020 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 CLK RST INTA C BEO 1 2 FRAME DEVSEL IRDY TRDY IDSEL STOP LOCK PAR PERR SERRE DQMODE FL SNV TEST OUT TEST SNV IN TEST SE IN TEST SCAN IN Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vss Vdd Vdd Vdd Vdd Vdd Vdd Vdd Vdd 59200 DAI 092 093 DQ4 DQ5 Dae DQ7 0910 0912 0913 pala 0915 Dale 0917 0918 0919 0920 0921 0922 0923 0924 0925 0926 0927 0928 0929 BPCLK ADCLK ADDINT SYSRST DXFR ADR2 ADR3 ADR4 ADR5 ADRO BEO BE 2 SELECT WR RD PTNUMO PTNUMI PTBEO 2 PTATNE PTBURST PTADR PTWR PTRDY PTMODE MDO 2 MD5 MD7 LOAD MDMODE SDA SCL 100 99 98 96 95 94 92 88 86 84 83 82 80 79 78 76 157 145 133 125 117 105 93 85 77 65 53 45 37 25 13 140 134 124 102 126 144 68 67 66 64 132 87 63 62 60 75 74 72 122 123 n6 ne ne 120 114 112 107 108 115 104 57 61 69 73 81 89 97 101 109 148 127 128 Data Bus
18. 31 70 GND ADR6 132 69 MD2 DQ18 133 68 2 ADCLK 134 67 ADR3 RSVD3 135 66 55 ADR4 RSVD4 136 65 0025 GND 137 64 ADRS FLT 138 63 1 RST 139 5920 62 140 160 61 0 GND 141 60 5 CLK 142 59 DQMODE MDMODE 143 58 DXFR 144 57 MDO 2017 145 56 Kx ADO AD31 146 55 r3 1 AD30 147 54 AD29 148 53 0026 RSVD5 149 52 AD3 GND 150 51 VCC 151 50 GND AD28 152 49 GND GND 153 48 AD4 AD27 154 47 AD5 AD26 155 46 AD25 156 45 0027 0016 157 44 07 AD24 158 43 C BEOK 159 42 08 IDSEL 4160 GND 000000000000000000000000000 22989226652828260906905852226525222822 oc 7 o Chapter 5 Developer Kit Design Aids Page 38 PCI Bus 5920 Controls Power amp Ground 56 55 54 52 48 47 46 44 42 40 39 38 36 35 34 32 14 12 n gt e 158 156 155 154 152 148 147 146 142 139 58 43 28 15 159 16 20 18 19 160 A 28 27 24 26 59 138 135 136 113 149 29 10 17 21 30 33 4 49 50 70 90 103 106 110 121 129 130 137 141 150 153 31 51 n 91 111 1
19. 44332211 reads and reads Chapter 3 Developer Kit Software Page 21 SCAN EXE Utility Program The scan exe utility program allows the user to see a brief display of all PCI devices within the host system Bridges I O cards video cards and the 5920 developer s kit are displayed by vendor ID Device ID etc The following is a display example of the utility Typing scan Example of PCI bus scan 0 8086 DID 1250 SVID 0000 SID 0000 BUS 0 INDEX 0 1 VID 8086 DID 7000 SVID 0000 SID 0000 BUS 0 INDEX 0 Intel 2 VID 102B DID 0519 SVID 0000 SID 0000 BUS 0 INDEX 0 Unknown User 3 VID 10E8 DID 5920 SVID 10E8 SID 00EE BUS 0 INDEX 0 AMCC 4 VID 8086 DID 1229 SVID 8086 SID 0009 BUS 0 INDEX 0 Intel Intel Note Number 3 is the 55920 Developer s Kit Chapter 3 Developer Kit Software Page 22 DKTEST EXE Utility Program The dktest exe utility program provides the user with the ability to test and exercise various circuits of the 55920 Developer s Kit The program tests the read and write capabilities of the onboard nvRAM SRAM 55920 operation registers and the Pass Thru data channels The following is the option menu Typing dktest followed by a will display the option list COMMAND SYNTAX dktest NV NVSIZE NOSAVE MEM OP PT PTSIZE NOCHK Option Menu NV Saves the contents of the nvRAM Reads and writes 2048 byte test pattern to the nvRAM Restores the contents of the nvRAM when complete NVSIZE S
20. 5 5 6 ae 2 g 16 9 9 10 11 12 BE 0 3 DQ29 14 13 13 14 ADR DQ28 16 15 5 16 DQ 7 18 17 17 18 5026 20 19 19 20 ADRS 2 m 2 21 21 22 ADEL OL ADR 2 6 24 23 nL 26 25 25 26 DOIS 28 27 27 28 30 29 29 30 20 32 31 32 m 34 33 34 36 35 35 36 A 38 37 3 cL Q 40 39 39 40 VCC 42 41 41 42 gt 44 43 43 44 46 45 45 46 48 47 47 48 50 49 49 50 IDC2X25 IDC2X25 Title Size Number Revision A Date 5 Feb 1998 Sheet of File H CD ROM AD_IFACE SCH Drawn By 1 2 3 4 55920 ISA Adaptor Card Sheet 1 Chapter 5 Developer Kit Design Aids Page 34 1 2 3 4 D 33MHZ om Yi 33MHZ lt ADCLK APIK SYSCLK SYSCLK gt 9 8 IN GCLRn 2421 OPTION 92 90 OPTION2 2 GCLK2 WADE 16 2 BALE 3 2 SBHE 1 3 n SBHE PTATN To MHZ MEMR 60 5 1 PTATN SMEMR 2 aah PTBURST
21. 9 205 16 15 15 16 5028 18 17 17 18 5927 ADR 20 19 19 20 0026 2 CADR 2 6 ADRI 2 21 21 22 DQ25 5024 4 24 23 23 24 7 DOIS psi 26 25 25 26 MDG 28 27 27 28 5 30 29 29 30 vcc q E 340 32 31 31 32 34 33 33 3 LED 33 33 34 MD2 DOIO 36 35 35 36 7 aU 21 398 n lt 0 0 7 40 39 39 40 424 42 gt 44 43 43 44 46 45 45 46 48 47 47 48 50 49 49 50 Title Size Number Revision Date 5 Feb 1998 Sheet of File H CD ROM 5920SCH3 SCH Drawn By 1 2 3 4 S5920 PCI Card Sheet 3 Chapter 5 Developer Kit Design Aids Page 33 PTATN PTBURST NEA 2 10 C PINUMI NUMA LOD 2 12 PTADR 14 13 13 14 PTWR 16 15 15 16 DXFER 18 17 17 18 SYSRST 20 19 19 20 ADDINT amp SYSRST 22 21 21 22 TROF ADDINT 24 23 23 24 Q IRQR gt 26 25 25 26 28 27 27 28 SELECT lt SELECT 30 29 29 30 RDF WR 32 31 31 32 RD E 34 33 33 34 H E 36 35 35 36 38 37 37 38 40 39 39 42 41 41 42 44 43 43 44 46 45 45 46 Nut 48 47 47 48 50 49 49 50 gt IDC2X25 IDC2X25 P5 P4 2 4 1025 43 3 6
22. AMEG PCI 55920 Developer s Kit User Manual And Technical Reference Manual Revision 1 3 April 1998 cr For Marketing and Application Information Contact Applied Micro Circuits Corporation 6290 Sequence Drive San Diego CA 92121 4358 619 450 9333 http www amcc com The material in this document supersedes all previous documentation issued for any of the products included herein reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice and advises its customers to obtain the latest version of relevant information to verify before placing orders that the information being relied on is current AMCC does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patents rights nor the rights of others AMCC reserves the right to ship devices of higher grade in place of those of lower grade AMCC SEMICONDUCTOR PRODUCTS ARE NOT DESIGNED INTENDED AUTHORIZED OR WARRANTED TO BE SUITABLE FOR USE IN LIFE SUPPORT APPLICATIONS DEVICES OR SYSTEMS OR OTHER CRITICAL APPLICATIONS Copyright 1998 Applied Micro Circuits Corporation PRINTED IN the United States of America Contents Chapter 1 Introduction Developer s Kit Overview aee eae Developer s Kit Goal sce couette eet e RR REED REN Features ierit eet to oe tee tdi UP PI
23. D4 48 95 D AD04 2 DQ4 BS6 AD3 52 96 AD03 AD3 DQ3 A57 AD2 54 98 DQ2 ADO2 gt AD2 DQ2 858 ADI 55 Ami por 99 5 Apoo 58 00 31 ADO 56 190 DQO DUS CIBER PTBE3 2 2 PTBE2 C BEO C BEO PTBEO PTATN i PAR PAR PTBURST 12 PTBURST _ prBURST 8 PTRDY 15 PTRDY PTRDY 4 2 FRAME FRAMER 16 FRAME SPTNUMIS 2 PINUMIS A36 TRDY 19 E 123 PTNUMO TRDY TRDY SPTNUMO PTNUMO B35 IRDY 18 107 PTADR IRDY IRDY 8 PTADR PTADR A38 STOP 22 24 108 PTWR STOP 7837 DEVSEL 20 5 PTWR DXFER PIWR DEVSEL gt DEVSEL DXFER DXFER ipse A26 IDSEL 160 S Locks B3 mE 23 Locke 5 svsRsre _ 026 SYSRST SYSRSTF 134 ADCLKI 5 ADCLK ADCLKI B40 PERR 24 140 TPS PERR SERRE 26 PERR BPCLK 102 JPSADDINT SERR SERR S ADDINT ROF ADDINT mos 24 TROF E16 PCICLK 142 bCICLK 9 2 32 TBD RST 139 ADRG 132 ADR6 ADRS INTA INTA 58 INTAR ADR4 xL INTB 7 L 4 ADR Ul 8 ADR 2 6 INTD gt VBEM BE2 REQ E 55920 BEI m e BEO BE 0 3 2 s PRSNT2 9 VCCI REMEK 29 SELE 77 WEE SELECT PRSNTI p5 NVV SCAN TEST WR 5 RDF WR 7 149 SNV_TESTN RD RD
24. TDI U7 TEST SE TDO ide 7 TMS A 24C16 NAND OUT MD6 TRST 2 I 18 SDONE 0 SDA DAS pp A SDA B SBOR SLC 4 O E SCL REQ64 18 MD2 P E y ce 4 e 15 2 R2 FLT 138 2 m 10K DOMODE 59 DOMODE E INDLDE e UM R4 10 1 104 143 MDMODE 660 ON OFF woes NORMAL TEST PRBE FLOATPINS FUNCTIONAL Tide 32BITBUS 8 16 BIT BUS ACTIVE MODE PASSIVE MODE Size Number Revision A Date 5 Feb 1998 Sheet of File H ACD ROM 5920SCH1 SCH Drawn By 1 2 3 4 5920 PCI Card Sheet 1 Chapter 5 Developer Kit Design Aids Page 31 cc HIGH SPEED BURST MODE MEMORY INTERFACE 31 31 16 2 21 2915 MADI6 2 21 MADIS 31 107 20 DOM MADIS 31 16 20 030 _ 3 4147 yos 29 DQI3 3 i yos L1 0029 28 55 oq DQI2 28 id 5028
25. als are also routed to a set of four external application connectors These connectors provide the designer with additional Add On bus connection capability The designer can utilize these for attaching his her own application PCB to the PCI card s Add On bus Two of these connectors are designed to provide simultaneous connection of the user s PCB and a logic analyzer Although many logic analyzers may be connected the are designed specifically for connection directly with Hewlett Packards PCI logic analyzer pod cabling The second PCB is an ISA Adapter interface card designed specifically to mate with the 55920 PCI card The adapter card was developed to provide direct connect of many existent ISA cards to the 55920 Add On bus An adapter card EPLD 1 programmed to convert Add On bus signals to ISA card signals and vise versa The adapter card provides the designer with a basic functioning interface example to the PCI bus allowing the designer to start design optimization and logic reduction The programmer can immediately begin reading and writing data from the PCI bus to ISA card addresses It is important for the designer to remember the developer s kit was designed to demonstrate various aspects of S5920 user design The specific EPLDs Add On logic components and software was chosen to support multiple application illustrations Therefore the device costs and complexity is more than will be necessary for many applications 5920 PCI
26. ard e Remove the cover mounting screws on your computer and carefully remove the cover Store the cover in a safe place Ensure the Developer Kit s main 5920 PCI Card is jumpered as shown in one of the two figures below for either SRAM or ISA Adapter card operation See the jumper description section of this manual to configure for other required options Chapter 2 Hardware Installation Page 7 Hold the Developer PCI Card its top corners and insert into any available PCI slot Press down gently but firmly until the card is seated Follow all suggested safety guidelines in your computer manufacturer s manual J4 J5 Short z Active Mode Add On Bus Open Passive Mode Add On Bus us e JP4 JP8 P v T 40MH 2 Serial ge JP6 eu xu V Installed Short Factory Test zj ips FPGA P Open Normal Operation JPi u md i gt gt a AMCC Short 5920 Outputs Floated d 5920 Open 5920 Outputs Driven J6 gt gt Short 32 Add On Bus Open 8 16 Bit Add On Bus Figure 2 1 PCI Card Jumpers for Active Mode SRAM Operation J4 J5 Short Active Mode Add On Bus Open Pass
27. are updates Chapter 2 Hardware Installation Page 11 System Checkout After installing the hardware and software as described in the previous sections an operational test should be run to ensure proper system to Developer s Kit function This will ensure the motherboard system BIOS PCIBIOS utility programs DOS Win95 and the Developer s Kit hardware are all in sync The following steps will operate various aspects of the DK to verify correct operation STEP 1 Test the Presence of the S5920DK1 Run the SCAN EXE program Examine the display and verify a VID 10E8 DID 5920 entry is present This indicates a PCIBIOS is present and has located and recognized the 5920 Developer Kit main card If this line is not present verify the settings in the system BIOS menus and the correct installation of the main card STEP 2 Test the state the 55920 PCI Configuration space Run the CFG EXE program Select the DK by entering the number beginning the line containing the VID and DID of the DK as indicated in step 1 above Examine the Command register The two least significant bits should be a one This indicates the BIOS has enabled the 5920 on the PCI bus to respond as either a memory or device There should also be values other than FF or 00 in Base Address registers BO B1 B3 and B4 Write down the address for B1 for the next step Note the values place in the Base Address registers are assigned by the system BIOS during power
28. e resistor and jumper accordingly Refer to the 5920 PCI card schematic before altering the default configuration JP11 Termination JP11 is provided to allow an optional series resistor termination to be installed in the ADCLKI The designer can install any value resistor and jumper accordingly Refer to the 5920 PCI card schematic before altering the default configuration Test Point Description PCI CLK General purpose test point of the PCI clock To be temporarly used with a low impedeance oscilloscope probe for examine PCI clock signal integrity TP2 SDA General purpose test point of nvRAM s serial data line To be used to verify signal integrity and data transmission during reads and write to the serial nvRAM SCL General purpose test point of nvRAM s serial clock line To be used to verify signal integrity and clock transmission during reads and write to the serial nvRAM Chapter 4 Developer Kit Hardware Page 25 ADCLKI General purpose test point of the 5920 s Add On bus clock input To be temporarly used with a low impedeance oscilloscope probe for examine ADCLK clock s input signal integrity BPCLK General purpose test point of the 5920 s Add On bus BPCLK s synchronous clock output To be temporarly used with a low impedeance oscilloscope probe for examine BPCLK s output signal integrity TP6 IRQ General purpose test point of the Add On bus interrupt output from the PCI bu
29. es as an example of Add On Local Bus interface control to SRAM The ISA Adapter Card The ISA Adapter Card supplied with the Developers Kit may be interconnected to the signal headers on the main PCI Developer Card This interconnection provides the developer with a data and control signal path to many existent PC ISA Bus designs to begin transferring data and examining 5920 register data The Software For the software developer the 5920DK provides a fully functional PCI bus to Add On bus test environment Much software development can start immediately without waiting for your new hardware to be built The software developer can become familiar with the PCI BIOS and PCI Configuration Space Registers Additional supplied software supports downloading editing and programming data to an optional serial boot load nvRAM on the 5920DK Source code is included for all programs supplied with the 5920DK allowing easily customization of the programs to your application Chapter 1 Introduction Page 4 Notation Conventions Low Active Signals Signals which are asserted or active in the low voltage state are defined with a trailing number pound sign within the schematics or with a leading exclamation for EPLD equations The following designations are used throughout this book when referring to the size of data objects A BYTE is an 8 bit object A WORD is a 16 bit or 2 byte object A DWORD is a double word and is a 32 bit 4
30. field is a DWORD default if not otherwise specified C Read and display data repeat read and display only if data changes L Continually repeat the read or write Examples Note if you type it wrong the option menu will be displayed automatically Writing DWORDs to memory addresses type memrw afff80000 044332211 Response 44332211 gt fff80000 memrw afff80004 088776655 Response 88776655 gt fff80000 Reading DWORDs from memory addresses type memrw afff80000 Response fff80000 44332211 memrw afff80004 Response fff80004 88776655 memrw afff80001 Response fff80000 55443322 Writing DWORDS to I O addresses type memrw afff8 044332211 Response 44332211 gt fff8 The C and L options are designed to aid the hardware engineer capture scope or logic analyzer PCI or Add On bus signals The C option shown in the example below will read data from the address indicated and display it The program will then re display the address s data only if the value changes A C will terminate the sampling This option is used for testing for a register status bit change or changing data on an input port The L option will continue to loop and execute a read or write of data to the address specified memrw afff80000 c Response fff80000 44332211 and waits for a change memrw afff80000 010 85920 Response 1180000 44332211 writes and repeats writing memrw afff80000 Response fff80000
31. ies having device drivers for the AMCC 85933 and 85920 PCI devices AMCC works closely with vendors making sure their products enhance your development process However we leave all aspects of development marketing and support to these development partners See the above web sites for the latest information on these device drivers Software Tools for the AMCCPCI Program Microsoft Visual 5 0 For device drivers and 32 bit development Win32 VxDs WinNT Kernel Mode Device Drivers WDM Device Drivers etc CXL A menu support library included on the CD ROM Both source code and documentation are included Used extensively in AMCCPCI Software Tools for All Other Supplied Programs Borland 4 51 or higher Borland Turbo Assembler TASM 4 0 or higher 10 has been supplied in assembly language General Use Software Tools SoftICE 3 2 Although normally used for kernel mode work such as device drivers we have found this debugger to be useful for many other debugging tasks such as working in Win95 DOS boxes Chapter 3 Developer Kit Software 14 PCI SIG ID Policy The PCI Special Interest Group has developed a device and card identification system to ensure all PCI Bus devices are uniquely identified This identification system allows software operating systems to load appropriate software drivers based on the ID numbers Use the following table as a reference guide for temporary PCI identification numbers fo
32. iles were created and compiled with Microsoft s Visual C version 5 0 Borland s C version 4 51 and Borland s Turbo Assembler version 4 0 These files give the programmer a basic example of 5920 and PC BIOS calls in standard C for data transfer and status operation Chapter 5 Developer Kit Design Aids Page 29 59205 1 c w s9520 sch 5920SCH1 SCH 290 31 PTBE 0 3 PTATN PTBURST 5920SCH2 c w s9520 sch 5920SCH2 SCH K DQI 0 31 gt 3 PTATN PTBURST PTRDY PTNUMI1 PTNUMO DXFER SYSRST gt gt ADCLK2 EXTEVAL 5920SCH3 c w s9520 sch 5920SCH3 SCH gt DQI 0 31 EXTEVAL 3 PTATN PTBURST mm PTRDY PTRDY PTNUMI PTNUMO PTADR PTWR DXFER PTNUMI1 PTNUMO PTADR PTWR DXFER SYSRST SYSRST ADCLKI lt ADDINT C ADCLK2 ADDINT IRQ ADR 0 6 lt BE 0 3 lt _4 SELECT ADR O 6 BE 0 3 SELECT WR RD lt MD 0 7 MDMODE 4 INT LOAD 0 INTILOAD amp RD MD 0 7 MDMODE 5920 PCI Card Block Diagram Chapter 5 Developer Kit Design Aids Page 30
33. ion and configuration registers on the Developer s Kit PCI card or a newly developed PCI card The following table lists each utility program and describes their function Utility Programs Program AMCCPCI EXE Reads and writes to the 55920 nvRAM to change power up DOS Win95 configurations options SCAN EXE Performs a PCI Bus scan for devices and lists by VID DID SVID DOS Win95 Bus and Index MEMRW EXE Reads and writes to PCI memory or I O space to move data DOS through the 55920 Pass Thru data channels OPR EXE Reads and writes to the 55920 operation registers from the PCI DOS bus CFG EXE Reads and writes to the 55920 configuration registers from the DOS Win95 PCI bus Each program s source code is supplied in either machine Applied Micro Circuits Corporation provides the source to programmers for use in all or part for the development of All programs except have been built in a Borland C IDE environment To modify the programs search for the project file 5920 ide Open it in Windows Explorer to launch the Borland IDE NOTE References to DOS platforms indicates the system must boot in DOS Not a DOS window or DOS prompt under Win95 Win95 indicates will run in a DOS prompt in Win95 Chapter 3 Developer Kit Software Page 13 Win95 and WinNT Software Device Drivers Currently Applied Micro Circuits Corporation maintains links on its web site www amcc com to third party software compan
34. ion space display for the 5920 Vendor ID VID 10E8 RO Device ID 210 5920 RO Command PCICMD 0103 R W Status PCISTS 0280 RO Revision ID RID 00 RO Class Code CLCD 000004 RO SVID SVID 10E8 RO SID SID OOEE RO Cache Line CALN 00 RO Latency Timer LAT 00 RO Header HDR 00 RO BIST BIST 00 RO Base 0 BO 0000FC81 R W Base 1 B1 FFF80000 R W Base 2 2 00000000 R W Base 3 B3 FFCO00000 R W Base 4 B4 FF800000 R W Base 5 B5 Not Implemented Exp ROM Addr XROM 00000000 RO Interrupt Line INTLN 09 R W Interrupt Pin INTPIN 01 RO Min Grant MING 00 RO Latency MAXL 00 RO Chapter 3 Developer Kit Software Page 20 Utility Program The memrw exe utility program allows the user to read or write 8 16 or 32 bit data to a PCI bus address located in memory or I O space This tool can be used for reading and writing to SRAM through the ISA Adapter card to registers on an ISA card inserted or to the 5920 operation registers The following is the option menu Typing memrw followed by a will display the option list COMMAND SYNTAX memrw A lt address gt O data C L I B W D L Option Menu Indicates the O command below will be to I O space over memory O Cause a write data to memory address indicated A lt address gt The hex address to R W data B The data field is a BYTE The data field is a WORD D The data
35. ive Mode Add On Bu 3 35 JP4 JP8 yu e 40MH T e z Serial JPG d NVRAM JP11 UTE 4 Removed Short Factory Test are R Open Normal Operation rwy gt gt fo e P Short 5920 Outputs Floated 5920 Open 5920 Outputs Driven J6 5 zm m gt gt Short 32 Bit Add On Bus Open 8 16 Bit Add On Bus Figure 2 2 PCI Card Jumpers for Passive Mode ISA Adapter Operation Chapter 2 Hardware Installation Page 8 Installing the ISA Adapter Card No jumpering is necessary prior to installing the Developer Kit s ISA Adapter Card Hold the Developer ISA Adapter Card by its sides align with connectors J2 through J5 on the main S5920 PCI card Press down gently but firmly until the card is seated Carefully install the main 5920 PCI card into the PC ISA Connector FPGA Figure 2 2 ISA Adapter Card Chapter 2 Hardware Installation Page 9 Connecting The Hewlett Packard Logic Analyzer The 5920 PCI card was developed with a set of conveniently located logic analyzer connectors These connectors were specifically designed to allow the ISA Adapter card or a new proto type design to be connected simultaneously with a logic analyzer This allows the developer to operate and test Add On bus circuits while examining setup and hold times a
36. long with data transfers The ISA Adapter card and developer proto types connect to the 55920 Add On bus through connectors J2 to J5 on the component side of the 5920 PCI card The logic analyzer connects to the Add On bus through the same connectors from the solder side of the 55920 PCI card The four connectors contain all the signals of the Add On bus and ground references These connectors are pin designated for direct pod cable connection to the Hewlett Packard 16500B or logic analyzer Up to four cables may be connected to cover the entire Add On bus signal set Refer to the schematics for signal location before connecting the HP or any other logic analyzer Figure 2 3 Logic Analyzer Connection Chapter 2 Hardware Installation Page 10 Installing The Software Shown below are the basic directory folders for the CD ROM supplied with the developer kit The content description of each folder and sub folder is also listed For normal hardware development it is only necessary to copy the utility programs to the hard drive for easy access and execution S5933 Hardware Folder Misc Miscellaneous drawings and PCB assembly files PCBs The Gerber files for the Developer Kit PCBs PLDs The CUPL source files for the PLDs and description docs Sch The OrCAD schematics for building the S5933DK1 S5933 Software Folder Contains the assembly source code for the AMCCDIAG utility program Also contains example h librar
37. matics All schematics source files for the 55920 PCI card and the ISA Adapter card are shown in Appendix A The source files and library files are contained on the CD ROM The schematics were developed under Protel rev 3 1 for Windows 95 These files can be imported into other software development tools using EDIF or DXF file formats Some software packages are capable of directly importing The bill of materials are also located in the CD ROM PCB Artwork All PCB artwork source files for the 55920 PCI card and the ISA Adapter card are contained on the CD ROM The PCBs were developed under Protel PCB rev 3 1 for Windows 95 These files can be imported into other software development tools using direct or DXF file formats 5920 PCI Card and ISA Adapter Card EPLD Equations The PCI Card and ISA Adapter Card application example EPLD equation files are contained on the CD ROM The files give a basic implementation for interfacing the Add On bus to SRAM and also to adapt the Add On bus to an ISA controller These examples give the designer a basic start from which to begin logic optimization to reduce component cost thru a smaller and slower PLDs expects the final solution for many ISA designs to be less than 5 for final glue These files were created with Altera s MAX plus II version 8 0 6 Chapter 5 Developer Kit Design Aids Page 28 Software Source Code All software source code files are supplied on the CD ROM These f
38. mmends the technique of solder bridging between pads with no sharp points left after soldering be utilized Refer to the 5920 PCI card schematic before altering the default configuration Chapter 4 Developer Kit Hardware Page 24 JP6 EPLD JP6 is provided to allow the designer alternate clock input and output configurations to the onboard EPLD JP6 is pre jumpered through extra fine traces for normal operation of the SRAM and ISA adaptor applications Should the designer desire to change the example EPLD equations to function differently or implement other clock frequencies these traces may be cut and wire wrap soldered between pads as desired Refer to the 55920 PCI card schematic before altering the default configuration JP7 Termination An optional clock input or output R C termination is provided for the clock signal The designer may install components and jumper JP7 as needed Refere to the 5920 PCI card schematic for details ADCLK3 8 is provided to allow the designer alternate clock input and output configurations to his development card when attached to the 55920 external connectors JP8 is pre jumpered through extra fine traces for normal operation of the ISA Adaptor application Refer to the 5920 PCI card schematic before altering the default configuration JP9 Termination JP9 is provided to allow an optional series resistor termination to be installed when using crystal Y1 The designer can install any valu
39. pecifies the size of the nvRAM read write range Default is 2048 NOSAVE Do not save or restore the nvRAM contents MEM Reads and writes to SRAM on the PCI card OP Reads and writes to all the 55920 operation reisters and bits PT lt region gt Specifies the Pass Thru region to use in the memory test PTSIZE lt size gt Defines the size of the Pass Thru region for testing Default entire region NOCHK Do not check if the Pass Thru regions are enabled Example of nvRAM test dktest nv Testing 2048 bytes of nvRAM should take about 50 seconds saving current nvRAM contents running data test restoring contents All tests passed Example of SRAM test of 20000h DWORDS dktest mem testing memory address Oxfff80000 size 0x20000 All tests passed Example of operation register tests dktest testing operation registers All tests passed Chapter 3 Developer Kit Software Page 23 Chapter 4 Developer Kit Hardware 5920 PCI Card The following section describes various aspects of the hardware design for the 55920 PCI card Jumper Descriptions JP1 TEST The TEST signal is a reserved input to the 55920 and must always be left open or in the logic state For factory use only JP2 The FLT signal floats all 55920 output signals when asserted Leave JP2 open for normal operation JP3 DOMODE DQMODE defines the Add On bus DQ width JP3 shor
40. r use in the developer s kit The indicated numbers are the factory defaults pre programmed into the onboard nvRAM and are loaded into the 5920 PCI Configuration Registers during power up initialization Configuration Register Name Value Vendor Identification VID 10E8h Device Identification DID 5920h Revision Identification RID 00h Subsystem Vendor ID SVID 10E8h Subsystem Identification SID OOEEh The PCI SIG has divided identification numbers into two groups Group one is dedicated to the chip manufacturer to uniquely identify the silicon device on the PCI bus Group two is dedicated to the end user or board manufacturer to uniquely identify the end product on the PCI bus e VID The vendor identification number is assigned by the PCI SIG to the IC manufacturer In this case 1OE8h has been registered to the name Applied Micro Circuits Corporation for identifying AMCC as a PCI chip device manufacturer e DID The device identification number is assigned by AMCC under it s rights of VID assignment AMCC assigns a unique DID to each of it s PCI chip devices In this case AMCC has assigned 5920h to uniquely identify the 55920 PCI interface chip Revision The revision number is also assigned by AMCC This number is assigned and programmed to identify the revision level of the silicon die within the device package In this case the register is hardwired to the silicon s revision SVID The sub vendor identification number is as
41. ry Image Edit Base Addresses Lists Base Address Registers Edit Other Configuration Registers Lists Configuration Registers Edit Location 45h Configuration Bits Lists location 45 hex Bits Exit Menu Write to Device Which PCI Device Which nvRAM Display Memory Image Displays Memory Image in hex Exit Menu 2 5933 Non volatile memory builder Load Memory Image PCI Device Which PCI device Which Serial nvRAM File Which File Exit Menu Save Memory Image Save to File File name Merge with File Which File Exit Menu Edit Memory Image Edit Base Addresses Lists Base Address Registers Edit Other Configuration Registers Lists Configuration Registers Edit Location 45 Configuration Bits Lists location 45 hex Bits Exit Menu Write to Device Which PCI Device Which nvRAM Display Memory Image Displays Memory Image in hex Exit Menu 3 Exit Program Note The program modifies data from it s own memory space This space defaults to set variables upon start up modify what s in the nvRAM the contents must be loaded into the program space by choosing Load Memory Image from device and select the serial nvRAM type from your board The 5920 DK is shipped with a 24C16 serial nvRAM device Developer s Kit nvRAM Factory Settings Chapter 3 Developer Kit Software Page 17 The following are the factory programmed settings for the nvRAM to run the SRAM and ISA Adapter card design examples Ba
42. s To be used to examine by an oscilloscope or logic analyzer to see the presence of an inetrrupt from the PCI bus to the Add On bus PCB Connector Description Jl This is the primary PCI edge connector All PCI communications and handshaking take place through this connector Refer to the PCI SIG specification for signal names and definations J2 tru J5 The Add On bus from the 85920 is wired to an on board EPLD and SRAM application design The Add On bus is also paralleled to these four connectors When the ISA Adaptor card is in place these connectors become the Add On bus interface by removing the on board EPLD from the design This is accomplished thru grounding pin 40 of J2 which is a disable signal to the EPLD This applies to the ISA Adaptor card as well as any user proto design connected to the 5920 PCI card J6 This connector is supplied for programming the EPLD U6 on the 5920 PCI card For programming use the Altera programming cable P N PL BYTEBLASTER available for approximately 150 from your local Altera distributor Chapter 4 Developer Kit Hardware Page 26 ISA Adaptor Card The following section describes various aspects of the hardware design for the ISA Adaptor card Jumper Descriptions to JP5 Options These optional jumpers are available for future and user application implementation This jumper block allows for five undefined options to be defined and implemented into the onboard EPLD See the
43. se Address Registers Type Base Address 0 Base Address 1 Memory Base Address 2 Disabled Base Address 3 Memory Base Address 4 Memory Size 128 bytes 128 bytes 1 Mbytes 1 Mbytes Pass Thru Memory Width Location Prefetchable 32 Bits Anywhere No 16 Bits Anywhere No 8 Bits Anywhere No Other Configuration Registers Vendor ID Subsystem Vendor ID Revision ID Base Class Code Sub Class Code Programming Latency Timer Interrupt Line Maximum Grant Location 45 Hex Readretry RD Operation WRmode WR Operation Target Latency Timer Control Max Device ID Subsystem ID BIST Capable Interrupt Pin Latency 00 IMPORTANT NOTE The developer s Kit hardware and software has been designed to operate using the Base Address and Configuration Register values indicated above Altering these values may cause improper operation The ISA Adaptor Card was designed to function in memory mapped mode and not I O Designers may change settings with the appropiate software and hardware design changes Chapter 3 Developer Kit Software Page 18 OPR EXE Utility Program The opr exe utility program allows the user to display and read or write to the 55920 Operation registers addressed in either memory or I O space This tool can be used for reading and writing to outgoing mailbox incoming mailbox mailbox status Interrupt reset control and the Pass Thru configuration registers The following is the option
44. signed by the PCI SIG to the end board manufacturer to uniquely identify the manufacturer s name All developers need to acquire a unique SID number from the PCI SIG for their company name In this case AMCC has assigned 10E8h to identify AMCC as the manufacturer of the 55920 developer kit Chapter 3 Developer Kit Software Page 15 e SID The system identification number is assigned by the end product manufacturer under the rights of their SVID assignment This will uniquely identify the end product within the market for software operating systems In this case AMCC has assigned a unique SID of OOEEh as the 85920 developer kit Chapter 3 Developer Kit Software Page 16 AMCCPCI EXE Utility Program The utility program provides the user with a menu driven display to change the 5920 configuration space and device power up options The configuration space values and power up options are contained in an nvRAM connected to the 5920 This program contains the necessary software routines to read change and write the contents of this serial nvRAM The following is list of the program menu tree Typing in either DOS or a DOS window under Win95 will start the utility program 1 5920 Non volatile memory builder Load Memory Image PCI Device Which PCI device Which serial nvRAM File Which File Exit Menu Save Memory Image Save to File File name Merge with File Which File Exit Menu Edit Memo
45. t can be set for all the utility programs are AMCC VID AMCC DID AMCC_SVID 510 AMCC_INDEX Chapter 3 Developer Kit Software 19 CFG EXE Utility Program The cfg exe utility program allows the user to display and modify the 85920 Configuration registers At startup a brief display shows all PCI devices within the host system Bridges I O cards video cards and the 55920 developer s kit are displayed by vendor ID Device ID etc Once the 55920 developer s kit has been selected cfg exe is used to read and write to the 5592075 configuration registers The following is the option menu Typing cfg followed by 2 will display the option list COMMAND SYNTAX R SCAN W register name gt lt data gt Option Menu R Displays the PCI configuration space in a hex table format W lt register gt lt data gt Writes to the R W register named with the hex data Example w pcicmd 103 SCAN Scans and displays PCI bus devices located used if set Displays help menu Example of opening PCI bus scan 0 VID 8086 DID 1250 SVID 0000 SID 0000 BUS 0 INDEX 0 Intel 1 VID 8086 DID 7000 SVID 0000 SID 0000 BUS 0 INDEX 0 Intel 2 VID 102B DID 0519 SVID 0000 SID 0000 BUS 0 INDEX 0 Unknown User 3 VID 10E8 DID 5920 SVID 10E8 SID 00EE BUS 0 INDEX 0 AMCC 4 VID 8086 DID 1229 SVID 8086 SID 0009 BUS 0 INDEX 0 Intel Note Number 3 is the 55920 Developer s Kit Example of the configurat
46. ted configures the DQ bus for 32 bits and open configures a 16 bit DQ bus The default is open for developer kit SRAM operation For ISA adaptor operation set according to the ISA card installed JP4 Pass Thru mode configures how the Add On bus will function when using the Pass Thru data channel JP4 open will configure the Add On bus to function in passive mode This mode allows other devices to share the Add On bus and requires these devices to drive 55920 bus control signals JP4 shorted will configure the Add On bus for active mode In this mode data reads or writes to the Pass Thru channel will cause the 5920 to drive the DQ bus and bus control signals through an internal state machine The 5920 PCI card SRAM application uses an EPLD programmed to operate in active mode Short JP4 to use the onboard EPLD for the SRAM application The ISA Adaptor card application is provided with two example EPLDs One EPLD operates in active mode and the other in passive mode Jumper according to which EPLD is installed in the ISA Ada ptor card ADCLK BPCLK The developer kit is designed to offer the designer all possible input and output clock jumpering configurations The 5920 PCI card is pre jumpered through extra fine traces for normal operation of the SRAM and ISA adaptor applications These traces may be cut and solder bridged between pads to configure for user designs Due to the high frequency of the clock line AMCC highly reco
47. up They can be changed through the utility program but will result in the Blue Screen of Death if re located over other software STEP 3 Test the SRAM Read and Write Operation While in DOS run the MEMRW EXE program Enter the following memrw a B1 address 044332211 memrw a B1 address 4 gt 088776655 Next type the following and verify the response is the same as indicated memrw lt 1 address gt Response B1 address 44332211 memrw lt 1 address 4 gt Response B1 address 4 88776655 lt 1 address 1 gt Response B1 address 1 55443322 This correct responses indicates successful reads and writes to the onboard SRAM through the 5920 Pass Thru data channel and proper operation of the EPLD state machine STEP 4 Test the nvRAM Run the AMCCPCI program Select the 5920 non volatile memory builder Select to load a memory image from the 24C16 A successful load verifies proper reading operation through the 5920 Next select write to device A successful nvRAM write verifies complete nvRAM operation The operational tests are complete Chapter 2 Hardware Installation Page 12 Chapter 3 Developer Kit Software Introduction The software utility programs supplied with the Developer s Kit provides PCI card diagnostics and a developer interface based on the programming language and x86 style systems These programs are the interface through which the developer can access 55920 operat
48. ware and software engineers may the begin accessing the ISA design and start converting Developer Software Tool CD ROM e 55920 Data Book Developer Kit User Manual this manual Chapter 2 Hardware Installation Page 6 System Requirements The minimum system requirements are e 386 processor 512K system RAM memory 10 Meg Hard Disk Space CD ROM Drive DOS 5 0 or Higher with ANSI SYS e 256 color VGA Display PCI bus motherboard slots The recommended system requirements are e 486DX processor or better 1 MB system RAM memory 10 Meg Hard Disk e 3 5 Floppy Disk Drive CD ROM Drive e DOS 5 0 or Higher with ANSLSYS e 256 color VGA Display Keyboard Installing Hardware The following section details the installation procedure for hardware components contained in the Developer s Kit This developers kit is intended and designed for an electronics laboratory environment in which the PC containing the DK will remain open This allows access to special connectors for logic analyzers and physical space to insert the ISA adapter card and the ISA card under evaluation Be sure that all AC power has been removed from your computer before proceeding AMCC recommends all installation work be done at a static free workstation If one is not available ensure that you have removed the static charge from your cloths by touching an object made of metal on the computer before proceeding Installing the PCI C
49. y and include C files S5920 Hardware Folder PCI Card Altera The Altera EPLD code for the PCI card DXF The DXF format files for building the PCI card PCB Gerbers The Gerber plotter files for the PCI card PCB Sch The Protel schematic files for the PCI card OrCADlibrary The 5920 and 5933 OrCAD schematic library files PCB The Protel PCB files for the PCI card PCB NC The NC drill files for the PCI card PCB ISA Card Altera The Altera EPLD code for the PCI card DXF The DXF format files for building the PCI card PCB Gerbers The Gerber plotter files for the PCI card PCB Sch The Protel schematic files for the PCI card PCB The Protel PCB files for the PCI card PCB NC The NC drill files for the PCI card PCB S5920 Software Folder Contains the Utility programs for the S5920DK1 and the source code library and include folders for the programs Also contains example h library and include C files nvRAM Tool Folder Contains the nvRAM utility program AMCCPCI EXE used or both the 55920 and 5933 Dks Also includes the source code library and include folders for the program Books Folder The S5920 data book PDF file The 5933 data book PDF file The 5920 DK manual Applications Folder Contains various application and design notes for the 55933 and 55920 PCI devices Also are the device summary files for device history Licence doc The Developer s Kit user license agreement readme txt Latest manual and softw
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