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G9004A User's Manual

1. 14 7 Message communication mode MOD LOW Configuration block diagram Center Control bus Serial communication Control bus device G9001A gt G9004A CPU Local CPU 7 1 Terminals for use by a local CPU Terminal name LIFO Description Local bus interface mode 0 LIF1 Local bus interface mode 1 LRST Negative Resets the local bus LAO to1 Positive Address for local bus lines O to 1 LA2 to 5 Positive Pull down to GND 5 10Kohm resistors LCS Negative Chip select for the local bus LWR Negative Write signal for the local bus LRD Negative Read signal for the local bus LWRQ Negative Wait request for the local bus LIFB Negative Interface busy for the local bus LIRQ Negative Interrupt request for the local bus LDO to 7 Positive Low byte signal for the local bus LD8 to 15 wlwlololo 0o Positive 7 2 map for the local CPU 16 bit interface 1 and 2 8086 H8 and 68000 LIF1 L Writing Write command High byte signal for the local bus Reading Read status Write transmission data 8 bit I f 1 and 2 Z80 6809 etc LIF1 H LAO to LA1 Writing Write command Read reception data Reading Read status Invalid Invalid Write transmission data Read reception data Invalid
2. Note 1 When CKSL LOW CKSL HIGH the data output delay time will be 12 11 58 11 5 3 16 bit I F 1 IF1 L IFO Read cycle LA 1 LCS LWRQ LRD LD 15 0 Write cycle LA 1 LCS LWRQ LWR LD 15 0 Item Symbol Condition Min Max Unit Address setup time for LRD LWR 17 ns Address hold time for LRD LWR 7 Trwa 0 ns LCS setup time for LRD LWR 4 Tosaw 5 ns LCS hold time for LRD LWR f Tawcs 0 ns LWRQ ON delay time for 4L CS Ci 40pF 12 ns LWRQ signal LOW time Twat Note 1 6 11 ns Data output delay time for LRD 4 C 40pF 29 ns Data output delay time for LWRQ 7 Twrap Ci 40pF 16 ns Data float delay time for LRD 7 Troup 40pF 30 ns LWR signal width Note 2 12 ns Data setup time for LWR 7 Tpwn 22 ns Data hold time for LWR T Twro 0 ns Note1 When CKSL LOW CKSL HIGH the data output delay time will be 12 11 Note 2 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until WR goes HIGH 59 11 5 4 16 bit I F 2 IF1 L IFO L Read cycle D M O EL Tas Tsa LCS Tsrw R W LWR i ACK LWRQ TARWDAKL LD 15 0 Write cycle LA 1 4 LCS EN LS LRD Tean R W LWR ACK LWRQ LD 150
3. Invalid 15 7 3 Command and status information that can be used by a local CPU 7 3 1 G9004A s commands that can be used by a local CPU Command code 00h Invalid 01h Software reset 02h Reset transmission FIFO 03h Reset reception FIFO 04h Wait for a sending break frame 10h Data send request Description No meaning Does not affect the operation Software reset Has the same result as applying a LOW to the RST terminal See the Note Resets only the data transmission FIFO If written during the data sending process status register bit 6 1 it may cause a CPU access error status register bit 3 1 Resets only the data reception FIFO Writing this command while no data is being received status register bit 5 0 may cause a CPU access error status register bit 3 1 The device enters a break frame waiting status This has the same results as applying a HIGH pulse to the BRK terminal Data send request Make the status register 0 bit 3 in the CPU emulation device equal 1 set the sending request interrupt so that the center device will be notified that transmission data exists Note When turning ON the power a reset signal must be supplied RST LOW 7 3 2 G9004A status information that can be seen from a local CPU 7 6 5 4 3 21 0 Interrupt due to the data receipt Interrupt due to the data transmission process being complete Interrupt due to a communication link d
4. E Item Symbol Condition Min Max Unit Address setup time for LS J Tas 17 ns Address hold time for LS 7 Tus 0 ns LCS setup time for LS 4 Toss 8 ns LCS hold time for LS 7 LE 0 ns R W setup time for LS 4 Trws 3 ns R W hold time for LS T 4 ns ACK ON delay time for LS 4 5 C 40pF Note 1 6 9 ns CL 40pF Note 1 9 ns TsuakR 40pF 16 ns ACK ON delay time for LS T Tean Qi 40pF 16 a Data float delay time for ACK 4 Tour 4 Note2 2Tax ns Data float delay time for LS 7 C 40 30 ns Data setup time for LS 7 Tsst 22 ns Data hold time for ACK 0 ns Note 1 When CKSL LOW CKSL HIGH MIN and MAX 12 9 Note 2 When CKSL LOW CKSL HIGH MIN 60 11 6 Timing when CPU emulation is selected 11 6 1 LCLK timing The LCLK uses the following timing even when the device is not in the emulation mode LCLK A it TLCLK When L 40 MHz Tax 25 ns Item Symbol Condition Cycle Unit LCK1 2L LCK0 L 2MHz 20 Clock T LCK1 L LCK0 4 MHz 10 y L_10MHz 4 LCK1 H LCKO H 20 MHz 2Tak When 80 MHz 25 ns Item Symbol Condition Cycle Unit LCK1 2L L
5. 4 Hardware description 4 1 A list of terminals QFP 80 No Signal name I O Logic Description 5V Interface Select operation mode L Message Jo NoD on es Available TUD MER QA when outputting watchdog Available TMD Select watchdog timer Available 4 LCKo nac of local bus control clock Available 5 LCK1 iue oe of local bus control clock Available 6 LWTO Positive Interval time of local bus 0 Available 7 LWT1 Positive Interval time of local bus 1 Available 8 LIFO Local bus I F mode 0 Available 9 Local bus I F mode 1 Available 10 VDD 3 3 V power input 11 LCS Negative Chip selection for local bus Available 12 LWR Negative Write signal for local bus Available 13 LRD lO Negative Read signal for local bus Available 14 LAO Positive Address for local bus 0 Available 15 GND GND 16 LA1 Positive Address for local bus 1 Available 17 LA2 Positive Address for local bus 2 Available 18 LA3 Positive Address for local bus 3 Available 19 LA4 Positive Address for local bus 4 Available 20 LAS Positive Address for local bus 5 Available 21 VDD 3 3 V power input 22 LDO B Positive Data for local bus 0 Available
6. 68 Notes Oct 6 2009 No DA70120 1 1E 69
7. CPU support 151 PCL series etc Local device bus 8 1 Terminals on the G9004A Terminal name Description Local bus interface mode 0 Local bus interface mode 1 LWTO Positive Local bus interval time setting 0 LWT1 Positive Local bus interval time setting 1 LRST Negative Local bus reset LAO to LA5 Positive Local bus address LCS Negative Local bus chip select LWR Negative Local bus write signal LRD Negative Local bus read signal LWRQ Negative Local bus wait request LIRQ Negative Local bus interrupt request LDO to LD7 Positive Local bus data 0 to 7 LD8 to LD15 Positive Local bus data 8 to 15 Shown below are representative CPUs and the corresponding terminals on the G9004A Typical CPU G9004A CPU name Terminal name G9004A terminal name G9004A mode Z80 LRD 8 bit interface 1 LWR 8086 RD LRD 16 bit interface 1 WR LWR Upper enable None Lower enable None R W LWR Upper strobe LRD No distinction between upper lower Lower strobe LRD No distinction between upper lower 16 bit interface 2 RD LRD Upper WR LWR No distinction between upper lower Lower WR LWR No distinction between upper lower 16 bit interface 1 R W LWR E LRD
8. When using 16 local devices IN 256 points OUT 256 points 0 24 msec When using 32 local devices IN 512 points OUT 512 points 0 49 msec When using 64 local devices IN 1024 points OUT 1024 points 0 97 msec Note The communication cycle will be extended dependant upon data communication 3 2 Specifications of the CPU emulation device G9004A Item Description CPU emulation mode Communication sentence 1 to 128 words frame 1 word 16 bits length Data buffer size 128 words D TOU When communicating 5 words write to one register in the PCL ata communication time 217 us Data transfer method Status Cyclic transfer Data Transient transfer Control address space 64 bytes 8 bit I F Z80 6809 etc CPU interface 16 bit I F 8086 H8 68000 etc Message communication mode Communication sentence 1 to 128 words frame 1 word 16 bits length Data buffer size 18 WOES 1 word reserved for the system 127 words Message data Data communication time When communicating 128 words 169 3 us Status Cyclic transfer Data transfer system Data communication Transient transfer CPU interface 8 bit I F Z80 6809 etc 16 bit I F 8086 H8 68000 etc Others Package 80 pin QFP mold size 12 x 12 x 1 4 mm Power supply 3 3 10 Storage temperature range 65 to 150 C Operating temperature range 40 to 85 C
9. LRD LWR CLK GND System reset Note 1 When only one device is connected to the G9004A there is no need for a decoder circuit The LCS output terminal on the G9004A can be connected to the CS terminal on the PCD4541 Note 2 The LCLK clock output on the CPU emulation device G9004A cannot be connected to the CLK input clock input on the PCD4541 The LCLK output is 3 3 V but the PCD4541 is a 5V device and its CLK input uses CMOS levels Viu 4 V min Vi 1 V max It cannot be connected directly to 3 3V devices Also the PCD4541 needs a 4 9152 MHz clock If it is connected to some other clock speed such as a 5 MHz clock it may complicate setting the multiplication factor For details see the user s manual for the PCD4541 Note 3 LCK1 HIGH LCKO LOW LWT1 H LWTO L When these settings are used the device will have the status shown below LCLK 10 MHz Local bus access interval 5 x Ti ci 500 ns The local bus access interval is the minimum time from the 1st access to next access when the CPU emulation device is reading or writing to the PCD4541 Since the PCD4541 does not have an output terminal to tell a CPU to wait the CPU has to use its own resources to time the waiting period Another method for accessing the PCD4541 is to have the center device G9001A execute a number of NOP commands to allow the required time to pass However using the local bus access interval will reduce the burden on
10. Port 1 gt 7 6 5 4 3 21 0 Local reception FIFO status 1 Data present 0 No data Local transmission FIFO status 1 Data present 0 No data Local emulation status 1 Processing 0 Stopped Local LIRQ input status 1 LOW 0 HIGH Port 3 bit 0 halt emulation status L RST terminal status 1 LOW 0 HIGH Local message communication status 1 Processing data transmission 0 Processing complete LWRQ terminal status 1 LOW 0 HIGH Status 2 setting information Port 2 7 6 5 4 3 2 10 Set local operation mode 0 Message communication 1 CPU emulation Local CPU interface mode 00 16 bit interface 2 68000 etc 01 16 bit I F 1 8086 H8 etc 10 8 bit I F 2 6809 etc 11 8 bit I F 1 480 etc Local LCLK setting Local LWT setting Operation information Port 3 7 6 5 43 2 1 0 0 0 0 0 Halt emulation execute by changing from O to 1 Change the LRST terminal status 0 HIGH 1 LOW 13 Communication image Center device G9001 CPU emulation device G9004A Cyclic and data Port Port 0 data communication Port 0 Data Port 1 data Port 1 Status data Area Port 2 data Cyclic communicatio Port 2 Port 3 data S Port 3 Operation data Data transmission FIFO Data transmission FIFO Data reception FIFO Data communication Data reception FIFO 5 X
11. Place a command 0400h in the Data transmission FIFO d ta transmission Mess Upper 00h 04h 00h FIFO Reset the rseceive process complete interrupt Interrupt occurs 12 The center device reads the status V Data communication complete bit 021 2 End emulation communication 27 8 2 2 4 Example of combined processing 16 bit CPU interface After writing 1234h to address 0 read addresses 4 and 6 With a communication wait time Center device G9001A Local device G9004A Start 1 Place a Data transmission FIFO command Address Upper Lower 0100h in Oth O0h the data 01h 12h 34h transmission 02h 12h 84h FIFO 2 Place data 1234h in the data transmission FIFO 3 Place a command 1284h in the data transmission FIFO 4 Write a data communication command odode Data communication 1st time KR RRR EKER RRR ERK 1 Write 1234h to address 0 2 Place a Data transmission FIFO command Address Upper Lower 1284h inthe oon 12h 84h data 01h EEh FFh transmission 02h DDh CCh FIFO 3 Read from address 4 FFEEh and write it Wait time i the data transmission FIFO 4 Read from address 6 DDCCh and write it to the data transmission FIFO 5 Set the status for port 0 interrupt information V Receive process complete interrupt Bit 121 Y Write request Bit 021 6 Send the
12. 1 LCS LRD LWRQ NP X DIETE LD15 0 8 3 1 2 Read cycle 2 wait 2 cycles LCLK LA5 1 LCS LRD LWRQ LD15 0 8 3 1 3 Write cycle 1 without a wait cycle LCLK LA5 1 LCS LWR LWRQ LD15 0 8 3 1 4 Write cycle 2 wait 2 cycle LCLK LA5 1 LCS LRD 30 8 3 2 16 bit CPU I F 2 68000 etc 8 3 2 1 Read cycle 1 without a wait cycle LCLK LA5 1 LCS LWR LRD STB MEM LWRQ ACK _ EE LD15 0 8 3 2 2 Read cycle 2 wait 2 cycles LCLK LA5 1 LCS LWR LDR STB LWRQ ACK i EE 8 3 2 3 Write cycle 1 without a wait cycle LCLK LA5 1 LCS LWR LDR STB LWRQ ACK orm LD15 0 8 3 2 4 Write cycle 2 wait 2 cycles LCLK LA5 1 LCS LWR LDR STB LWRQ ACK y 31 8 3 3 8 bit CPU I F Z80 etc 8 3 3 1 Read cycle 1 without a wait 2 cycles LCLK LA5 0 LCS LRD LWRQ LD7 0 8 3 3 2 Read cycle 2 wait 2 cycles LCLK LA5 0 LCS LRD LWRQ LD7 0 8 3 3 3 Write cycle 1 without a wait cycle LCLK LA5 0 LCS LRD LWRQ LD7 0 8 3 3 4 Write cycle 2 wait 2 cycles LCLK LA5 0 LCS LRD LWRQ LD7 0 32 8 3 4 8 bit CPU I F 2 6809 etc 8 3 4 1 Read cycle 2 without a wait cycle LCLK RD E LA5 0 LCS LWR LWRQ LD7 0 8 3 4 2 Read cycle 2 without 2
13. 20 8 bit interface 2 8 2 Control method for using a center device G9001A When you want to perform CPU emulation using the G9004A write the commands and data using the formats specified for the data transmission FIFO in the center device G90014 The center device s data transmission FIFO can store up to 128 words including write commands write data and read commands When writing data there is no data to be sent from the G9004A But when reading data the G9004A will send a read command and then read data from the center device Therefore more than 128 words of data cannot be handled by the G9004A When writing data When reading data Combined case Center device data Center device data Center device data transmission FIFO transmission FIFO transmission FIFO Address Upper Lower Address Upper Lower Address Upper Lower 00h 00h Command reading 00h Command writing 01h Writing data 1 01h Command reading Oth Writing data 1 02h Writing data 2 02h Command reading 02h Writing data 2 O3h reading s 04h Command writing 05h Writing data If the G9004A is set up to use an 8 bit CPU interface the following precautions should be noted When the center device G9001A uses a 16 bit interface In the case that the number of writing for G9004 is odd number add one byte of dummy data T
14. I O device the device outputs an enable signal to SOEH or SOEL When not used connect to the GND SI Serial input signal for communication Positive logic MRER This is a monitor output to check communication quality When the center device receives an error frame such as a CRC error the signal becomes L only for 128 cycles 3 2 us of the CLK By measuring the condition using the counter you can check communication quality MSEL Communication status monitor output When this device receives a frame intended for this device and everything is normal when communication MRER is OFF this terminal goes LOW for exactly 128 CLK cycles 3 2 us This can be used to check the cyclic communication time BRK By providing HIGH pulses that are longer than the specified interval this device will be made to wait for a break frame When this device receives a break frame send request from a center device it immediately sends a break frame A pulse at least 3200 usec long is needed in order to be seen as the BRK input pulse positive logic MOD Selects the operating mode for this IC MOD L Message communication mode MOD CPU emulation mode LCKO to 1 Selects the clock frequency LCLK for controlling a local bus LCK1 LCK 0 The clock frequency LCLK L L 2 MHz L H 4 MHz H L 10 MHz H H 20 MHz When this IC is in CPU emulation mode the speed of the emulation depends on the above
15. M E 9 5 19 561 600 9 SAEC LKA 2 dot 9 5 20 E00 dx Lec an M Iesu t 10 EAE ep PETERE RC ER EA 10 b 22 uiae adea c cM caa C aie etd 10 b 29 LAO LA S ecce cett a ED ML Eee Lt mad 10 IHE T MERERI IU 10 020 ud com cere eo SALAM A ML LEE NIAE 10 DO AER esas obe Mcd Md n et tA Med 10 M ne 11 5 28 HEIBQ uii get tete Fete pet Ae Hg e OS He Pere oe 11 5 29 EDO to LD Visi ine nene E RE Ee I HH d ne E He Ro ce c EC OR e Lud 11 5 30 ED8 to LDI ruriini a eH ER Lid EE UR C TQUE re aa edo 11 5 91 EWT Cand LWT avian died dec Eee de er Het ea ee Hee uL abt ee At ee 11 5 92 CKS iio tite n aene o d e d d a a o Re qu EH P ee Ies 12 5 39 VDD GND isi tee Sh e tp die EUR des e et e 12 6 Setting the status and operation information for the G990044A 13 7 Message communication mode MOD LOW 0 15 7 1 Terminals for use by a local CPU iii 15 22 VO map for the local uiii te tee vade ag tu en ie e Ee E ol ees 15 7 3 Command and status informat
16. PRFL 000001 00h PRFH 00000200h PRMG 012Bh Multiplication rate 1 Send command data to the G9004A It will process one by one and controls the PCL6045B Instruction to write data to the PCL6045B buffer Instruction to write the data in the I O buffer of the PCL6045B to the PRFL register Outpw 0x0006h 0x1184h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0081h Outpw 0x0006h 0x1184h 5 F Outpw 0x0006h 0x0200h Instruction to write data to the PCL6045B buffer Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0082h Outpw 0x0006h 0x1184h Outpw 0x0006h 0x012Bh Instruction to write data to the PCL6045B buffer Outpw 0x0006h 0x0000h Outpw 0x0006h 0x0100h Outpw 0x0006h 0x0085h Instruction to write the data in the I O buffer of the PCL6045B to the PRFH register ejep puewwoy Instruction to write the data in the I O buffer of the PCL6045B to the PRMG register Outpw 0x0006h 0x0100h Instruction to the PCL6045B to start feeding a pulse train at Outpw 0x0006h 0x0051h FH speed Data communication command send the command data stored in the FIFO Outpw 0x0000h 0x4028h This step checks the read status EDTE flag If a communication error occurs the next process should not be started This action Dev Sts Inpw 0x0000h also can be performed using the interrupt procedure If there is no error the PCL6045B will b
17. Place a command Data transmission FIFO SADOh in the data Address Upper Lower transmission FIFO 00h 3Ah DOh Read from address 16 01h FFh FFEEh and write to 02h DDh the data transmission 03h BBh FIFO 04h 99h Read from address 14 DDCCh and write to the i data transmission FIFO Wait time i 4 Read from address 12 BBAAh and write to the E data transmission FIFO Read from address 10 9988h and write to the data transmission FIFO Set the status for port 0 interrupt information V Receive process complete interrupt Bit 121 V Interrupt request Bit 021 Send the FIFO contents to the center device Interrupt occurs 8 The center device reads the status Data communication complete bit 0 1 gt Input change interrupt bit 221 4 Reset the input change interrupt 5 Read from the reception FIFO 6 Place a command Data transmission FIFO 0400h in the data Address Upper Lower transmission FIFO 00h 04h 00h Reset the reception process complete interrupt Interrupt occurs 8 Read the center device status V Data communication complete bit 021 2 End emulation communication 26 Read in order from address 16 14 12 and 10 Without a communication wait time Center device G9001A Local device G9004A Start 1 Place a command Data transmission FIFO 32D0h in the data Access Hoper Lowa transm
18. Pulse ransfOrtmer catt ina lea eee at bo etat libn cedendo 48 ST Meo AA 48 9 7 5 Parts used in our experiments cette ce regie cue eo eds 49 97 6 Other precautions dieere Mere 49 10 Genter device G900 TA ie d pe eta it rre e e RE SE fe ERR 50 10 1 Program example of CPU emulation mode 51 10 1 1 Control example of the 60458 nennen nennen nnns nennen 51 10 1 2 Control example 4541 53 Electrical characteristics 6 Indre ee tetra erae eto eec ierat aaepe 55 11 1 Absolute maximum 55 11 2 Recommended operating 55 11 3 DG chataclerisliGS odiosa date eei a cire eiua 55 11 4 AG Characteristics ood iiia cie ri a net de siege ah Vaa ia E aas ee ed sta ne 56 BE dE THE 56 1124 2 Beset timing en inner trader 56 11 5 Timing of CPU message communication mode 57 11 5 1 8 bit I F 1 IF1 FO 57 14 5 2 8 DIBE 2 As IEO m t t a reo aah aee DOR RR C eee rds 58 115 3 16 bit VF 1 IF1 S L
19. bit I O mode 1 or the data transfer FIFO address 2 in the 8 bit I O mode 1 is shown below A wait time is necessary to perform continuous writing The wait must be 6 clock cycles or longer at 40 MHz 1 Does not use LWRQ output CPU does not have a wait function si Next address LCS I 55 4222 7 LWR Bo N SSS ER wait of 6 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the LWRQ output CPU has a wait function LA c wey xe s LWRQ RH e eM LD 5 4 CPU automatically waits for the required period of time 40 9 2 3 Read status Shown below is the timing when reading from address 0 in the 8 bit I O mode 1 A wait time is necessary to perform continuous writing The wait must be 4 clock cycles or longer at 40 MHz 1 Does not use the LWRQ output CPU does not have a wait function LA Next address LRD LD pa gt K L_ wait of 4 clock cycles or longer at 40 MHz must be inserted by the CPU software 2 Uses the LWRQ output CPU has a wait function LA LCS E d LRD RE Me 4 LWRQ LD M _ hs CPU automatically waits for the required period of time 41 9 3 Connection to peripheral LSIs when the CPU emulation mode is selected 9 3 1 Connections to a PCL6045B 8086 type CPU emulation The PCL6045B is a pulse
20. contents of the data transmission FIFO to the center device Interrupt occurs 5 The center device reads the status V Data communication complete Bit 021 V Input change interrupt Bit 2 1 gt 6 Reset the input change interrupt 7 Read the data from the data reception FIFO 8 Write b 0400h to the data transmission FIFO Reset the Data transmission FIFO receive Address Upper Lower process 00h 04h 00h complete interrupt 9 Write a data communication command 4008h Interrupt occurs 10 The center device reads the status V Data communication complete Bit 0 1 gt End of emulation communication 28 After writing 1234h to address 0 read addresses 4 and 6 Without a communication wait time Center device G9001A Local device G9004A Start 1 Place a command 0100h in the data transmission Data transmission FIFO FIFO Address Upper Lower 2 Place data 00h Oth 00h 1234h in the Oth 12h 34h data transmission 02h 12h 84h FIFO 3 Place a command 1284h in the data transmission FIFO 4 Write a data communication command Interrupt occurs 1 Write 1234h to address 0 5 The center device reads the status 2 Place a command ps 1284h in the data Data transmission FIFO V Data communication complete Bit 021 transmission FIFO Address Upper Lower 3 Read f
21. cycles LD7 0 8 3 4 3 Write cycle 1 without a wait cycle LCLK 33 8 3 5 Example of a burst cycle 8 bit CPU I F 2 280 etc 8 3 5 1 Burst read cycle 1 Fixed address LCLK LA5 0 LCS LRD LWRQ LD7 0 8 3 5 2 Bust read cycle 2 add an address LCLK LA5 0 LCS LRD LWRQ LD7 0 n 1 n 2 8 3 5 3 Burst read cycle 3 subtract an address LCLK LA5 0 LCS LRD LWRQ LD7 0 8 3 5 4 Burst write cycle add an address LCLK LA5 0 LCS LWR LWRQ LD7 0 34 n 2 n 2 9 Connection examples and recommended environment 9 1 Example of a connection to a CPU using the CPU message communication mode MOD L 9 1 1 8 bit I F 1 IF1 HIGH IFO HIGH Z80 type CPU G9004A ob Decoding A2 to A15 LEER LCS LIRQ wart fona DO to D7 LDO to LD7 RESET RST System reset Note 1 When you use an interrupt controller the CPU will output IORQ as an interrupt acknowledge signal that is used to determine the interrupt vector At this time when this LSI s LCS terminal goes LOW the LSI may output a LWRQ signal and still not be able to capture the vector properly Therefore arrange the decoding circuit so that it only functions when the M1 signal is HIGH Note 2 Pull up terminals LD8 to LD15 to the power supply externally 5 to 10 k ohms Note 3 Pull the LA2 to LAS input terminals down to GND using external resistors 5
22. is read this bit returns to 0 Try to write data to the transmission FIFO during transmission CPU access error processing status register bit 6 1 or writing a transmission FIFO reset command 02h Try to read the reception FIFO even though it has received no data status register bit 5 0 or writing a data reception FIFO reset command 03h Communica valid This bit is used to see if the communication line is connected When the tion link device detects a change on the communication line this bit becomes 1 If the communication line does not change within a specified time this bit becomes 0 exists Received data When there is message data in the data reception FIFO this bit becomes 1 in progress After writing the data transmission command 10h this bit becomes 1 Data transmission When data communication with the center device is complete when a receiving information command 0002h issued by the center device this bit becomes 0 Transmissio exists nesta If there is message data in the data transmission FIFO this bit becomes 1 7 4 Information command for the center device G9001A To send a message the first word in the transmission FIFO of the center device is used for the information command The remaining 127 words can be used freely as message data any format is allowed Center device transmission FIFO Address Upper 00h Information comm
23. no physical load is placed on the LSls 67 13 3 Precautions for mounting 1 Plastic packages absorb moisture easily Even if they are stored indoors they will absorb moisture as time passes Putting the packages in to a solder reflow furnace while they contain moisture may cause cracks in plastic case or deteriorate the bonding between the plastic case and the frame The storage warranty period is one year as long as the moisture barrier bags are not opened 2 If you are worried about moisture absorption dry the chip packages thoroughly before reflowing the solder Dry the packages for 20 to 36 hours at 125 5 C The packages should not be dried more than two times 3 To heat the entire package for soldering such as infrared or superheated air reflow make sure to observe the following conditions and do not reflow more than two times Temperature profile The temperature profile of an infrared reflow furnace must be within the range shown in the figure below The temperatures shown are the temperature at the surface of the plastic package Maximum temperature The maximum allowable temperature at the surface of the plastic package is 260 C peak A profile The temperature must not exceed 250 C A profile for more than 10 seconds In order to decrease the heat stress load on the packages keep the temperature as low as possible and as short as possible while maintaining the proper conditions for soldering Package body t
24. read process to the center device In addition if the reception process complete interrupt flag bit 1 on port 0 is 1 and this command is received the device will send the same data as it last sent the data resend process Data send process Note Reset the reception process complete interrupt flag Reset the reception process complete interrupt flag bit 1 on port 0 to 0 In the case that the bit number 1 of the state 1 is 1 the value returned to 0 after receiving this command Note LIRQ input interrupt reset Reset the LIRQ input interrupt bit 2 on port 0 to O Note Note Please use it with the beginning word of sending data without fail If itis used at except the beginning it is ignored 22 Communication wait setting Select whether to use the communication wait time during the reading and writing processes When set to 0 the G9004A will return the normal response without data soon after receiving a command from the center device G90014 When set to 1 the G9004 will wait a maximum of 10 usec at 20 Mbps to respond after receiving a command from the center device G9001A While waiting if the received processes are all complete and there is a read command the device will send read data If there is no read command or if the received processes do not complete within the waiting time it sends a normal response without data Commands other than writing reading processes are inv
25. significantly reduce the effective total length of the line LAN cables normally consist of several pair of wires Make sure to use wires from the same pair for one set of communication lines Even when using cables with the same category and rating the performance of each cable manufacturer may be different Always use the highest quality cables in the same category Terminating resistor Select resistors that match the impedance of the cable used Normally a 100 ohm resistor is recommended Therefore we used terminating resistors with this value Adjusting this resistor value may improve the transmission line quality Pulse transformer We recommend using pulse transformers in order to isolate the GND of each local device By isolating the GNDs the system will have greater resistance to electrical noise If pulse transformers are not used the transmission distance may be less We used 1000 uH transformers in our experiments chip We selected I C chips with specifications better than the RS485 standard In the experiment we used 5 V line transceivers When 5 V line transceivers are used level shifters are needed to make the connections 48 9 7 5 Parts used in our experiments Show below is a list of the parts used in the interface circuits of our experiments Use of other parts may change the system s response This list is only for your reference Parts Manufacturer Model name CAT5 O
26. the software The waiting time of 500 ns was determined from the values specified in the PCD4541 user s manual 43 9 4 Connections to a serial communication line Use RS 485 line transceivers and pulse transformers 1000 or equivalent to make serial communication connections Connect the line transceivers as shown below Connect terminating resistors which match the cable impedance at both ends of the transmission line The terminating resistors can be either before or after the pulse transformer The same effect will be obtained at either position When using a 5 V line transceiver ICs such as a level shifter are needed to assert signals on lines such as SO SOEH and SI 1 Circuit example for a single local device VDD Line transceiver Local device Terminating resistor Pulse transformer Serial line Device number DNO to DNS DNSM Note 1 Make the wiring as straight and short as possible circuit on a circuit board GND 44 2 Circuit example for multiple local devices Using the connections shown below the address of the local device above will be the address of the local device underneath it plus 1 Line transceiver 3 3 V Local device i ivot Terminating Pulse transformer resistor Serial line Note 1 Make the wiring as straight and short as possible circuit on a circuit board SO SOEH SI SOEL DNSO SOEI DNO t
27. to 10 K ohms 35 9 1 2 8 bit I F 2 IF1 HIGH IFO LOW VDD 6809 type CPU G9004A Decodin 2 15 i UE CLK LIF1 LCS LIFO MOD LAO to LA1 GND LIRQ LRD LWR LWRQ LDO to LD7 RST Note 1 Pull the LA2 to LA5 terminals down to the GND 5 to 10 K ohms Note 2 Pull the LD8 to LD15 terminals up to the power supply using external resistors 5 to 10 K ohms 36 9 1 3 16 bit I F 1 IF1 LOW IFO HIGH VDD 8086 type CPU G9004A Decoding A1 to A19 circuit ALE A16 to A19 ADO to AD15 DO to D15 GND LDO to LD15 Interrupt control circuit LIRQ LRD LWR LWRQ RST System reset System reset H8 type CPU G9004A VDD TU CLK CLK LIFI A2 to 15 3 qp t MOD A1 LA1 RD LRD HWR LWR Al WAIT LWRQ RESET RST System reset Note 1 Pull LAO and the LA2 to LA5 terminals down to GND 5 to 10 K ohms 37 9 1 4 16 bit I F 2 IF1 LOW IFO LOW 68000 type CPU G9004A AS CLK LIF1 2 A23 LCS LIFO MOD LA1 Interrupt control circuit System reset Note 1 Pull the LAO LA2 to LAS input terminals down to GND 5 to 10 K ohms 38 9 1 5 Connecting to a CPU without a wait function The center device can be connected to a CPU that does not have a wait function Let s look at an example with the CPU interface using 8 bit I F 1 while it is
28. to 43 6 V Input voltage ViN Vss to Vpp V Input voltage 5V I F Vin Vss to 5 5 V Storage temperature Ta 40 to 85 11 3 DC characteristics Item Symbol Condition Min Max Unit Current consumption laa CLK 80 MHz 34 mA Input leakage current lu 1 1 Output leakage current loz 1 1 Input capacitance 10 pF DNO to 5 DNSM SPDO to 1 TUD TMD LCKO to 1 LIFO O to 1 165 HA LOW input current li LWTO to 1 CKSL MOD Input terminals and input output 4 A terminals other than the above SOEI SI BRK 190 uA HIGH input current lu Input terminals and input output 4 1 A terminals other than the above LOW input current Vi 0 8 V HIGH input current Vin 2 0 V LOW output voltage Vo lou 6 mA 0 4 V HIGH output voltage Vou lou 6 mA Voo 0 4 V LOW output current lo VoL 0 4V 6 mA HIGH output current lou Vpp 0 4 V 6 mA Internal pull up pull down Rpua 20 120 K ohm resistance 55 11 4 AC characteristics 11 4 1 System clock 1 When setting CKSL L and data transfer rate 20 Mbps Item Symbol Min Max Unit Frequency foLk 40 MHz Cycle 25 ns HIGH duration 10 15 ns LOW duration 10 15 ns 2 When setting CKSL L and data transfer rate 10 Mbps Item Symbol Min Max Unit Frequency foLk 40 MHz Cycle 25 ns HIGH duration ns LOW duration n
29. 01A Local device G9004A Start 1 Place a command Data transmission FIFO 0102h in the data Address Upper Lower transmission FIFO 00h Oth 02h 2 Place the data 01h 12h 34h 1234h into the data transmission FIFO Interrupt occurs 4 The center device reads the status Data communication complete bit 021 1 Write 1234h to address 2 2 Set status port 0 interrupt information 1 Receive process complete interrupt bit 121 Interrupt occurs lt V Interrupt request Bit 021 5 The center device reads the status V Input change interrupt Bit 2 1 gt 6 Reset the input change interrupt 7 Write 0400M to the Data transmission FIFO data transmission Address Upper Lower FIFO 00h 04h 00h Reset reception process complete interrupt Interrupt occurs 9 The center device reads the status V Data communication complete Bit 021 End emulation communication 24 8 2 2 2 Example of writing continuous data 16 bit CPU interface Write 1234h to address 4 2345h to address 6 and 3456h to address 8 Without a communication wait time Center device G9001A Local device G9004A Start 1 Place a Data transmission FIFO command Address Upper Lower 2184h in the 00h 21h 84h data Oth 12h 34h transmission 02h 23h 45h 03h 34h 56h 2 Place data 1234h
30. 1 1 8 bit I F 1 HIGH IFO 35 9 1 2 8 bit I F 2 IF1 HIGH IFO LOW 36 9 1 3 16 bit I F 1 IF1 LOW IFO HIGH eee ee cece cece aeeeeaae enne en nennen nns nnn inneren 37 9 1 4 16 bit I F 2 IF 1 LOW IFO 4 22 2 1 0 0000 38 9 1 5 Connecting to a CPU without a wait function 39 9 2 Access timing when the CPU message communication mode is selected MOD L 40 9 2 1 Normal acess anne edd e ad Bled aloes vade dg age na doe eee Pg qae 40 9 2 2 Write to command or data transfer FIFO ie 40 9 2 8 R ad Status eei ode gu eue voe eee tuu 41 9 3 Connection to peripheral LSIs when the CPU emulation mode is 42 9 3 1 Connections to a PCL6045B 8086 type CPU emulation sene 9 3 2 Connections to the PCD4541 780 type CPU emulation see 9 4 Connections to a serial communication line 44 9 5 A connection example of a level shifter essssssssssssseeeeeenenneneen nennen 46 9 6 Complete configurato N s uoce etie nine de e 47 9 7 Recommended environment sise 48 9 751 Cable tte eem edo 48 9 2 Terminating resiStOr cioe dest 48 9 3
31. 23 101 B Positive Data for local bus 1 Available 24 102 B Positive Data for local bus 2 Available 25 LD3 B Positive Data for local bus 3 Available 26 GND GND 27 104 B Positive Data for local bus 4 Available 28 105 B Positive Data for local bus 5 Available 29 LD6 B Positive Data for local bus 6 Available 30 LD7 B Positive Data for local bus 7 Available 31 VDD 3 3 V power input 32 108 B Positive Data for local bus 8 Available 33 LD9 B Positive Data for local bus 9 Available 34 LD10 B Positive Data for local bus 10 Available 35 LD11 B Positive Data for local bus 11 Available 36 GND GND 37 1012 B Positive Data for local bus 12 Available 38 1013 B Positive Data for local bus 13 Available 39 LD14 B Positive Data for local bus 14 Available 40 1015 B Positive Data for local bus 15 Available 41 VDD 3 3 V power input 42 LWRQ Negative Wait request for local bus Available 43 LIRQ Negative Interrupt request for local bus Available 44 LIFB O Negative Busy interface for local bus Available 45 LRST O Negative Reset for local bus Available 46 GND GND 47 LCLK Local bus control block 48 When a communication error is received this Available signal becomes L level for a rated interval No Signal
32. 41 will begin operation In this step it is not clear if the PCD4541 is operating or not Dev_Sts Inp 0x0000h G9004A status bit 1 in this case equivalent to port 0 indicates whether reception by the local devices is complete This action also can be performed using the interrupt procedure triggered by the input change interrupt function When the G9004A completes all the processes specified this bit becomes 1 In other words this will mean that the PCD4541 has definitely started operation if there is no problem with the command data Sts 28h Inp 0x01A0h Outp 0x0006h 0x00h Outp 0x0007h 0x04h Put a reset instruction command for the local receive processing complete flag in the FIFO Outp 0x0000h 0x28h Write a data communication command send the Outp 0x0001h 0x40h command data stored in the FIFO Dev Sts Inp 0x0000h When CEND H the local device flag has been reset 54 11 Electrical Characteristics 11 1 Absolute maximum ratings Item Symbol Rating Unit Power supply voltage Vpp Vss 0 3 to 44 0 V Input voltage Vin Vss 0 3 to Vpp 0 5 V Input voltage 5V I F Vin Vss 0 3 to 7 0 V Output current Terminal lour 30 mA Storage temperature Tsto 65 to 150 11 2 Recommended operating conditions Item Symbol Rating Unit Power supply voltage Vpp 3 0
33. 6 bits Return value None 2 Write command to the center device 8 bits Outp Address Data Address Value corresponding to the address map in the center device 16 bits Data Data to write 8 bits Return value None 3 Read command from the center device 16 bits Inpw Address Address Value corresponding to the address map in the center device 16 bits The lowest bit is ignored Return value Read data 16 bits 4 Read command from the center device 8 bits Inpw Address Address Value corresponding to the address map in the center device 16 bits Return value Read data 8 bits Also see the individual items in the Message communication procedure and CPU emulation procedure sections 50 10 1 Program example of the CPU emulation mode Using the CPU interface mode of the G9004A the PCL6045B uses a 16 bit I F 1 and the PCD4541 uses an 8 bit I F 1 10 1 1 Control example of the PCL6045B Shown below is a program example that lets the center device G9001 A control a PCL6045B through a G9004A The PCL6045B is a pulse train generating LSI for NPM s motion control network Set the CPU I F to 8086 mode IFO L IF1 One PCL6045B can generate pulse trains for four axes In the example below use the device address of 28h for the G9004A Registers to set in the PCL6045B Register name Set value Remark
34. CK0 L 2MHz 40 Clock cycle T LCK1 L LCKO H 4 MHz 20 ag EPAR LCK1 LCKO L 10MHz 8 LCK1 H LCKO 20 MHz ATak 61 11 6 2 8 bit I F 1 IF1 IFO Read cycle LA 5 0 LCS LWRQ LRD LD 7 0 Write cycle LA 5 0 58 Ne 0 5 5 y I LWRQ LWR LD 7 0 Item Symbol Condition Min Max Unit Address setup time for LRD LWR Tarw 1 1 ns i LWT1 L Address hold time for LRD LWR 7 Tawa WTO L Note 1 Tick 1 ns CS setup time for LRD LWR 4 1 Ti 41 ns CS hold time for LRD LWR 7 Trwcs 0 1 ns LWRQ ON set up time for LRD 2 WR J P Trwwt 12 ns LRD LWR OFF signal LOW time for 4L WRQ 1 9 CL 40pF 2Ticik 2 3Ticik ns Data setup time for LRD 7 Toro 23 ns Data hold time for LRD T Troup 0 ns LRD signal width Tro 2Ticik ns LWR signal width Twr 2Ticik ns Data output delay time for LWR 4 Twnp CL 40pF 5 15 ns Data hold time for LWR T Twrup 2 1 ns Note The addresses do not change until the next cycle so the hold time varies with value used for LWT 62 11 6 3 8 bit I F 2 IF1 IFO L Read cycle T CYC LRD E Tae Tea o T LA 6 0 C e i H _ Tose LCS E E m _ LWRQ Trwe ed LWR Terro L
35. D 70 31 Tcvc Write cycle LRD E Eo Tae Tpwe Tea bo E LA 50 LCS A gt LWRQ Trwe Terw LWR LD 7 0 Item Symbol Condition Min Max Unit Address setup time for LRD E 7 Tae 1 1 ns Address hold time for LRD E i is mA 1 1 ns R W setup time for LRD E 7 Tawe 1 1 ns R W hold time for LRD E 4 1 1 ns LCS setup time for LRD E 1 Tese 1 1 ns 4L CS hold time for 4LRD E 4 Tecs 1 1 ns LWRQ ON set time for LRD E 7 Tewr CL 40pF 12 ns LWRQ signal LOW time for zZLWRQ Twre CL 40pF 2 2Ticik ns Data setup time for LRD E 4 23 5 Data hold time for LRD E 4 0 ns LRD E signal width TPWE 2Ticik ns LRD E cycle time Toye STLcuk ns Data setup time for LRD E 4 Toi Tick 3 Tia 1 ns Data hold time for LRD E 4 Tewwo 1 1 ns Note 1 When CKSL LOW or HIGH the data output delay time will be 12 11 63 11 6 4 16 bit I F 1 IF1 L IFO Read cycle LA 5 1 EOS fl LWRQ LRD LD 15 0 Write cycle LA 5 1 LCS LWRQ LWR LD 15 0 Item Symbol Condition Min Max Unit Address setup t
36. IEO El i e ie ease et ente hne RR YE 59 11 5 4 16 bit I F 2 0 2222 10 000 entente nnns 60 11 6 Timing when CPU emulation is selected 61 116 1 LCEK UMNO Ss scons EE 61 1126 2 8 bit VEC Hi EQ m ED ccs ot Irina e nenne Fee Hp Covel 62 11 6 3 8 bit I F 2 IF1 IFO 63 11 6 4 16 bit I F 1 L IFO H 64 11 6 0 16 bit VF 2 IF AS E IFO S b rero tee eet a cen n tee Re cea Ne 65 T2 External dimerisioris acp etel raid cm eid pua am es 66 T3 sFlandling precautigris ede ue eR e da 67 13 1 Design 67 13 2 Precautions for transporting and storing 5 5 67 13 3 Precautions for 1 sise 68 13 4 Other precautions 1 Outline This LSI is a CPU emulation device G9004A This LSI can be connected to our Motionnet and perform data communications with a center device G90014 Either of the following two operation modes can be selected from a terminal 1 CPU emulation mode In this mode the G9004A emulates CPU terminal signals using data communicated from the center device G9001A Although the communication format from the center device is limited this LSI outputs signals identical to those from CPU termina
37. Motionnet Remotel O amp RemoteMotion G9004A CPU emulation device User s Manual NPM Nippon Pulse Motor Co Ltd Preface Thank you for considering our super high speed serial communicator LSI the G9000 series To learn how to use the G9000 series device read this manual and G9001 A G9002 user s manual to become familiar with the product What the Motionnet is As a next generation communication system the Motionnet can construct faster more volume large scale wire saving systems than the conventional T NET systems conventional LSI product to construct serial communication system by NPM Further it has data communication function which the T NET does not have so that the Motionnet can control data control devices such as in the PCL series pulse train generation LSI made by NPM The Motionnet system consists of one center device connected to a CPU bus and maximum 64 local devices and they are connected by using cables of two or three conductive cores Cautions 1 Copying all or any part of this manual without written approval is prohibited 2 The specifications of this LSI may be changed to improve performance or quality without prior notice 3 Although this manual was produced with the utmost care if you find any points that are unclear wrong or have inadequate descriptions please let us know 4 We are not responsible for any results that occur from using this LSI regardless
38. NPM logo mark LIRQ LWRQ VDD LD15 LD14 LD13 LD12 GND LD11 LD10 LD9 LD8 VDD LD7 LD6 LD5 LD4 GND LD3 LD2 LD1 LDO VDD 4 3 Entire block diagram G9004A RST SPD 1 0 CKSL CLK LCS LRD LWR LIF 1 0 LA 5 0 LD 15 0 LCK 1 0 LWT 1 0 DN 5 0 DNSM TMD TUD SI SOEI Clock control Internal clock 20 MHz circuit Internal clock 40 MHz Command control circuit CPU emulation control circuit Manage device number Watchdog timer Data receiving Receipt data Transfer processing processing circuit circuit Serial signal Serial signal receiving circuit transfer circuit LIRQ LWRQ LIFB LCLK LRST DNSO 5 Functions of terminals 5 1 CLK 5 2 5 3 This is an input terminal of the reference clock By setting of the CKSL terminal either of the following clock rate signals can be connected CKSL L 40 MHz CKSL H 80 MHz By selecting either of these clock rates the serial communication transfer rate does not change This clock rate selection affects communication precision For a small scale serial communication and transfer rate below 10 Mbps use of the center device with 40 MHz does not give any restriction With 20 Mbps transfer speed however longer communication lines or a large number of connected local devices may deteriorate communication precision due to collapse of signals on the circuit This deterioration of communication qua
39. Outp 0x0006h 0 00 Outp 0x0007h 0 01 Outp 0x0006h 0x81h Outp 0x0007h 0x00h Outp 0x0006h Oxc3h Outp 0x0006h 0 00 Outp 0x0007h 0x10h Outp 0x0006h 0x00h Outp 0x0007h 0x0Oh Outp 0x0007h 0 21 Outp 0x0006h 0x00h Outp 0x0007h 0 01 Outp 0x0006h 0x82h Outp 0x0007h 0x00h Outp 0x0006h Oxc3h Outp 0x0007h 0 21 Outp 0x0006h 0x00h Outp 0x0007h 0x20h Outp 0x0006h Outp 0x0007h 0x00h Outp 0x0006h 0x00h Outp 0x0007h 0 01 Outp 0x0006h 0x84h Outp 0x0007h 0x00h Outp 0x0006h Oxc3h Outp 0x0007h 0 21 Outp 0x0006h 0x00h Outp 0x0007h 0x02h Outp 0x0006h 0x58h Outp 0x0007h 0x00h Outp 0x0006h 0x00h Outp 0x0007h 0x01h Outp 0x0006h 0x11h Send command data to the G9004A and it will process it one command at a time similar to a CPU to control the PCD4541 Write an R1 register FL select command to the command address Operation command to send to the G9004A 0100h Data 81h FL select command Note1 Write the data at the address specified in the R1 register FL upper byte first then the middle and finally the lower byte Operation command to send to the to G9004A 21C3h Note1 Write an R2 register FH select command to the command address Operation command to send to the G9004A 0100h Data 82h FH select comm
40. P SW etc for 4DNO to DN5 terminals 2 When the DNSM L Input a DNSO signal that is output by some other chip on the DNO terminal on this device When using this input method this chip has an address equal to the other chip s address plus one When using this method connect terminals DN1 to DN5 to GND When two sequential sets of serial data match the data is taken to be a device address 5 5 DNSO The numeric equivalent of the address on DNO to DN5 1 will be output after being converted into serial bit stream Connect this output to another local device s DNO terminal make all the other DNSM terminals of that local device LOW so that other devices can get the address and pass it along to the next data sending device In the case that continuous address by 0350 signal is set it is necessary to have at least about 50 us until the next step address is confirmed 5 6 SPDO SPD1 Specify communication speed with these terminals All of the devices on the communication line shall be set to the same speed SPD1 SPDO Communication speed L L 2 5 Mbps L H 5 Mbps H L 10 Mbps H H 20 Mbps 5 7 TUD A watchdog timer is included on the chip to assist in administration of the communication status When the data transmission interval from a center device to this device exceeds the set time the watchdog timer times out This terminal is used to set output conditions when the watchdog timer ti
41. a Interval time 11 5 32 CKSL Selects the clock specifications for the input on the CLK terminal When CKSL L supply a 40 MHz clock signal on the CLK terminal The duty cycle should be approximately 50 If the duty cycle is too far away from 5096 the number of communication faults will increase When CKSL H the device uses the CLK signal input after dividing by 2 internally Therefore the duty cycle will not have such a great influence In this case supply an 80 MHz clock signal 5 33 VDD GND Supply 3 3 VDC 10 for power on the VDD terminal Make sure to use all the terminals 12 6 Setting the status and operation information for the G9004A During the cyclic communication and during data communication the status register information registers 0 to 2 is written to the port data area ports 0 to 2 that corresponds to the device address in the center device When the operating information is written to the port data area port 3 that corresponds to the center device s device address it is passed along to the CPU emulation device G9004A using the cyclic communication Status 0 Interrupt information Port 0 7 6 5 4 3 21 0 1 Local interrupt request result of ORing bits1 to 3 1 Local receive process complete interrupt CPU emulation mode 1 Local LIRQ input interrupt CPU emulation mode 1 Local transmission request interrupt message communication model Status 1 Status information
42. alid The only valid setting is for the 1st word 01h address in the center device data transmission FIFO Setting it to any other address is not allowed Processing bytes setting Set the number of processing bytes when you want to read or write continuously Set a burst cycle Enter the number of processing bytes 1 as the setting When the device is used with a 16 bit CPU interface set the number in units of words Otherwise when the device is used with an 8 bit CPU interface set the number in units of bytes Commands other than write read processes are not allowed 23 8 2 2 Examples of CPU emulation control procedures The device model number is shown in parenthesis Numbers marked with mean that the operations are carried out by a center device G9001A emulating a CPU Assume that the local device address for the G9004A is 08h In addition the port status information of the cyclic communication or data communication is sent to the port data area of the center device G9001A In order to generate an interrupt position 1 in the center device G9001A when an interrupt request bit 0 1 on port 0 occurs in the local device G9004A you must enable the input change interrupt that corresponds to port 0 set it to 1 8 2 2 1 Examples of writing single units of data 16 bit CPU interface Write the data 1234h to address 2 without using communication wait time Center device G90
43. and Note1 Write the data at the address specified in the R2 register FH upper byte first then the middle and finally the lower byte Operation command to send to G9004A 21C3h Data 002000h Note1 Write an R4 register multiplication rate setting select command to the command address Operation command to the G9004A 0100h Data 84h multiplication rate select command Note1 Write the data at the address specified in the R4 register multiplication rate upper byte first then the middle and finally the lower byte Operation command to send to the G9004A 21C3h Note1 Instruction of an FH constant speed start sent to the PCD4541 Operation command to send to the G9004A 0100h Data 11h Note 1 Operation commands to the G9004A must be written to the data transmission FIFO in the center device G9001 A Write the upper and lower bits to the same address If only 8 bits are needed you will still have to write dummy data to upper 8 bits and sent an operation command to the G9004A using the same address 53 Data communication command send the command Outp 0x0000h 0x28h data stored in the FIFO Outp 0x0001h 0x40h Write in order of lower to upper bit This step checks the read status EDTE flag If a communication error occurs the next process should not be started This action also can be performed using the interrupt procedure If there is no error the PCD45
44. and 01h to 7Fh Message data any format Information command Command code Description 0001h Message transmission Use this command to send a message or data from the center device to a local CPU You can attach a message or data at the end of this command There is also an Information command without any message Transmits FIFO data of G9004A for sending to G9001A 0002h When the G9004A receives this command the data transmission process complete interrupt lt local status register bit 1 1 gt and the device resets the transmission processing flag local status register bit 6 gt You can attach a message or data at the end of this command 0003h Resend request command When the G9004A receives this command it sends the same data as it last sent Use this command when the center device cannot receive data from the local device due a data communication error or other reason Note Use this when sending request is failed because of some causes In the case that the 0001h command is used in place of resend request command the operation of 0003h command after that is not guaranteed 42 7 5 Message communication procedure The device model numbers are shown in parenthesis Numbers marked with mean that the operations are carried out by a CPU Assume that the local device address for the G9004A is 08h In addition the port status information for the Cycle communicatio
45. btract address Process detail setting 000 NOP 001 Write process 010 Read process 011 Data send process 100 Reset receive process complete interrupt 101 Reset LIRQ input interrupt Communicating wait setting Number of process times setting Start address setting Set the top address for the read or write process If the CPU emulation device G90044 is using a 16 bit CPU interface the lower bit setting is ignored and always treated as 0 Commands other than writing and reading processes are invalid Address refresh setting When the number of processing times does not equal zero select an address refresh method When the number of processing times is 0 commands other than writing and reading processes are invalid Process detail setting Select the processing detail for the CPU emulation device G9004A Item Processing detail Do nothing command The device does nothing Reception process NOP complete interrupt does not occur When sending FIFO for G9004A has data do not use this command The operation is not guaranteed The CPU emulation device G9004A reads the number of bytes specified in ud E the processing register starting from the start address The CPU emulation device G9004A writes the number of bytes specified in the processing register starting from the start address The device sends the data that was read by using the
46. connected to an Intel 8031 8 bit CPU Since this CPU does not have a terminal for executing a wait function care is needed when programming CLK 8031 intel G9004A 8 to A15 A2 to A15 P2 0 to 2 7 F Decoding CLK LIF1 circuit LCS LIFO ALE A0 to A1 LAO to LA1 P0 0 to P0 7 lt 3 GND LDO to LD7 LRD LWR System reset Points 1 Set IF1 H and IFO H 8 bit I F 1 2 Since the 8031 does not have a wait terminal the WRQ terminal cannot be used However the G9004A needs a certain internal processing time to access write read a CPU And a wait function is therefore essential for continuous access operations In the example above the LIFB output terminal on the G9004A is connected to a port on the 8031 The LIFB bit is monitored using a routine in the 8031 so that the 8031 does not try to access the G9004A while it is processing a command Note 1 Pull the LA2 to LA5 terminals down to GND 5 10Kohms 39 9 2 Access timing when the CPU message communication mode is selected MOD L 9 2 1 Normal access CPUs that have a wait function can be connected to the LWRQ terminal on the G9004A so that they can be used without special concern for signal timing However CPUs without a wait function must monitor the LIFB output or use one of the following timing schemes this is essential 9 2 2 Write to command or data transfer FIFO The timing for writing to command address 0 in the 8
47. each pin can be set for input or output using the operation mode MOD In the column I refers to input refers to output and B refers to bi directional Note 2 As for the terminals with available in the 5V interface column note the following These terminals can be input 5 V level signals These are the input that diode overcurrent protection is deleted on 3 3 V lines If over voltage may possibly be charged due to reflection linking or inductive noise we recommend inserting a diode for overcurrent protection L Without overcurrent protection diode Level shifter AM Outputs including bi directional from 5V devices can be connected to the center device as far as these are TTL level Even when a signal is pulled up to 5V the output level will be less than 3 3 V However CMOS level signals cannot be connected On the CPU bus interface pull up of a 5 V level is possible for stabilizing bus lines prevent floating Use 10 k ohm or larger capacity pull up resistors 4 2 Terminal assignment drawings DNSM DNO DN1 DN2 DN3 DN4 DN5 VDD S SOEI GND CLK VDD RST GND GND VDD GND GND GND a o o ER 05 X 60 e gt oS PP X a LCK1 LWTO TOUT LIFO LIF1 S 9 gt Note Locate each pin number from the markings the chip As shown in the figure above pin number 1 is at the lower left of the
48. egin operation In this step it is not clear if the PCL6045B is operating or not G9004A status bit 0 in this case equivalent to port 0 becomes OR Sts 28h Inpw 0x01A0h signal of bit 1 local side completes receipt process to bit 3 This action also can be performed using the interrupt procedure triggered by the input change interrupt function When the G9004A completes all the processes specified this bit becomes 1 In other words this will mean that the PCL6045B has definitely started operation if there is no problem with the command data 51 Put a reset instruction command for the local receive Outpw 0x0006h 0x0400h processing complete flag in the FIFO Outpw 0x0000h 0x4028h Sts Inpw 0x0000h GEND 1 gt YES End Write a data communication command send the command data written in the FIFO When CEND H the local device flag has been reset 52 10 1 2 Control example of PCD4541 Below shows a program example that lets a center device G9001A control a PCD4541 through a G9004A In this example the center device G9001A communicates in CPU I F model 4 Z80 type 8 bit CPU The PCD4541 is NPM s sequence LSI for stepper motors In the example below use a device address of 28h for the G9004A Registers to set in the PCD4541 Register name Set value Remark PRFL 001000h PRFH 002000h PRMG 000258h Multiplication rate 1
49. emperature C Max peak temperature 260 C Lane E Less than 10 seconds at 250 Preliminary heating Main heating 440 to 200 C 220 C or higher 1 60 to 120 sec Less than 40 sec gt e Time A profile applied to lead free soldering 4 Solder dipping causes rapid temperature changes in the packages and may damage the devices Therefore do not use this method 13 4 Other precautions 1 When the LSI will be used in poor environments high humidity corrosive gases or excessive amounts of dust we recommend applying a moisture prevention coating 2 The package resin is made of fire retardant material however it can burn When baked or burned it may generate gases or fire Do not use it near ignition sources or flammable objects 3 This LSI is designed for use in commercial apparatus office machines communication equipment measuring equipment and household appliances If you use it in any device that may require high quality and reliability or where faults or malfunctions may directly affect human survival or injure humans such as in nuclear power control devices aviation devices or spacecraft traffic signals fire control or various types of safety devices we will not be liable for any problem that occurs even if it was directly caused by the LSI Customers must provide their own safety measures to ensure appropriate performance in all circumstances
50. his dummy data is ignored on the G9004A side Writing operation is not executed the next operation command will be processed Additionally in the case that writing of odd number bytes is executed several time simultaneously the data is returned in the packed state so as to cross the word boarder On the G9004A side any dummy data are not added When the center device G9001A uses an 8 bit interface The operation command for the G9004A must be written to the same address in the center device G9001A data transmission FIFO by arranging the upper and lower bytes in order If the number of data bytes to write is odd write one dummy data byte to make the total even Then use the following operation commands for the G9004A at the same address Shown below is an example where 3 bytes of data are to be written Write a dummy data byte to the upper 8 bits of address 02h Center device G9001A data transmission FIFO data Address Upper 8 bytes Lower 8 bytes 00h Write command upper Write command lower 01h Write data 2 Write data 1 Write the 02h Write data 4 dummy data Write data 3 operation 03h Write command upper Write command lower 4 commands to the 04h Write data 5 Write data 4 same addresses 05h 06h 21 8 2 1 Command 1514 13 12 11 109 8 7 6 5 4 3 2 10 Start address setting Address refresh setting OX Fixed address 10 Add address 11 Su
51. ime for LRD LWR TARW Ticik 1 1 ns LWT1 L Address hold time for LRD LWR 7 Tawa LWTO L Note 1 Tick 1 ns CS setup time for LRD 4LWR 4 1 Tiax i ns CS hold time for LRD LWR 7 Trwes 0 1 ns LWRQ ON set time for LRD LWR a Trwwt 12 ns LRD 4L WR OFF delay time for LWRQ y CL 40pF 2 3Ticik ns Data setup time for LRD 7 Tob 23 ns Data hold time for LRD T Tnpup 0 ns LRD signal width Trp ns SL WR cycle time Twn 2Ticik ns Data setup time for LWR 4 CL 40pF 5 15 ns Data hold time for LWR T Twnup 2 1 ns Note The hold time varies with the LWT set value as the address does not change until next cycle 64 11 6 5 16 bit I F 2 IF1 L IFO L Read cycle LA 5 1 LCS 4ad a a LS LRD R W LWR Taks ACK LWRQ LD 15 0 qr I D TsHDR Write cycle LA 1 Le idi LS LRD E 1 p R W LWR p MES ACK LWRQ LD 15 0 Lp Tap 9 5 Tsuow Item Symbol Condition Min Max Unit Address setup time for LS J Tas Tiax 1 Tiax i ns Address hold time for ACK f T Mice Tak 1 1 1 ns AKA LWTO Note LCLK LCLK LCS setup time for LS i Toss 1 1 ns LCS hold time for 7 Takcs Tiak 1 2Tiak 1 ns R W setup t
52. ime for LS 4 Trws Tiak 1 Tia d ns R W hold time for ACK T Takaw Tiak 1 2Tiak 1 ns LS LRD OFF delay time for ACK Taks CL 40pF 2Ticik 41 ns Data setup time for LS 7 Taek 23 ns Data hold time for LS f Tous 0 ns Data output delay time for LS 4 Tap CL 40pF 2 17 ns Data hold time for LS f TsHpw 0 1 ns Note The hold time varies with the LWT set value as the address does not change until next cycle 65 12 External dimensions 80pin LQFP Unit mm G9004A XXXXXXXXX JAPAN Se 0 5BSC 0 22 1295 0 CD 010M 0 145 252 0 08 1506 0 to 10 2 1 2 T x Pd lt 0 45 min i 0 75 max 66 13 Handling precautions 13 1 Design precautions 1 Never exceed the absolute maximum ratings even for a very short time 2 Take precautio
53. in the data transmission 3 Pas data 2345h in the data transmission 4 Pas data 3456h in the data transmission 5b Wre a data communication command Interrupt occurs 1 Write 1234h to address 4 6 The center device reads the status 2 Write 2345h to address 6 3 Write 3456h to address 8 4 Set the status on port 0 interrupt information 1 Receive process complete interrupt Bit 1 1 Interrupt occurs lt Y Interrupt request Bit 021 V Data communication complete bit 0 1 gt 7 The center device reads the status V Input change interrupt bit 221 8 Reset the input change interrupt 9 Place a command Data transmission FIFO 0400h in Address Upper Lower the data 00h 04h 00h transmission FIFO Reset reception process complete interrupt 10 Write a data communication command 4008h Interrupt occurs 11 Center device reads the status V Data communication complete Bit 0 21 End emulation communication 25 8 2 2 3 Example of reading continuous data 16 bit CPU interface Read data addresses 16 14 12 and 10 in this order Using a communication wait time Center device G9001A Local device G9004A Start Data transmission FIFO Address Upper Lower 00h 3Ah DOh 1 Place a command SADOh in the data transmission FIFO Data communication 1st time FIR RR REE 1
54. ion that can be used by a local 16 7 3 1 G9004A s commands that can be used by a local CPU 16 7 3 2 G9004A status information that can be seen from a local 16 7 4 Information command for the center device G9001A 17 7 5 Message communication procedure si 18 8 CPU emulation mode MOD H iii 20 8 1 Terminals on the 09004 ener nnne sre nnns sinn nenne innen nnne 20 8 2 Control method for using a center device G9001A nes 21 8 2 1 Gomlimialid uoce es cada de ud e HIR cR CALI E cR Ep RUE eR Ra due SORT eoa E ETATS 22 8 2 2 Examples of CPU emulation control procedures ssssssssssseseeeeenenenenn 24 8 3 Emulatiornitiming 5 eite e er haec e Eben eoe ERE pea etg eode end 30 8 3 1 16 bit CPU I F 1 8086 H8 etc 2 2 1 0 0 000 00000 entretenir sinn innen 30 8 3 2 16 bit CPU I F 2 68000 etc iii 31 8 3 3 8 bit CPU I F 780 etc iii 32 8 3 4 8 bit CPU I F 2 6809 etc iii 33 8 3 5 Example of a burst cycle 8 bit CPU I F 2 280 etc useseessseesseesseesseesrsssensrserineresrrennne 34 9 Connection examples and recommended environment e 35 9 1 Example of a connection to a CPU using the CPU message communication mode MOD L 35 9
55. is used for a wait request signal for a local bus It will be either an input or output terminal depending on the mode selected In the CPU emulation mode you supply a wait request signal from an external circuit In the message communication mode this terminal outputs a wait request signal when the device cannot be accessed LIRQ This terminal is used for an interrupt request signal for a local bus It will be either an input or output terminal depending on the mode selected In the CPU emulation mode you supply an interrupt request signal from an external circuit In the message communication mode this terminal outputs an interrupt request signal from internal operations LDO to LD7 These terminals are used for the low byte signals of a local data bus These are bi directional terminals LD8 to LD15 These terminals are used for the high byte signals of a local data bus These are bi directional terminals When using an 8 bit CPU interface pull up these terminals to VDD 5 to 10 K ohm resistors 5 31 LWTO and LWT1 These terminals are used to set the time interval between writing and reading to a local bus Use these terminals only in the CPU emulation mode These are not used in the message communication mode Tick clock cycle Time interval An example of the reading procedure when using a 16 bit CPU interface 1 LA X Address X Next address LRD LD Data Dat
56. isconnection CPU access error While establishing a communication link Reception data exists Sending process active Transmission data exists l Bit Item Description When the G9004A receives message data from the center device this bit becomes 1 and an interrupt signal is output LIRQ L 0 E After this status register is read this bit returns to O When the device only receives an information command this bit stays 0 and the device does not output an interrupt LM After writing a data transmission command 10h when the G9004A receives an 1 faces information command reset transmission processing flag 0002h this bit becomes lete 1 and the device outputs an interrupt signal LIRQ L After this status register is read this bit returns 0 16 Item Description Communica disconnecte interrupt When the interval between sending one data sentence and the next from tion link the center device to the PCL exceeds a specified time time out this bit d becomes 1 and the device outputs an interrupt signal LIRQ L After reading this status register the interrupt signal is reset This is used to monitor the watchdog timer output 1 TOUT L When the PCL device does any of the following on a command from a CPU this bit becomes 1 and the device outputs an interrupt signal LIRQ L After this status register
57. ission FIFO 2 Write a data communication command 4008h Interrupt occurs 3 Read the status 1 Place a command Data transmission FIFO Y Data communication complete Bit 0 1 gt 32D0h in the data Address Upper Lower transmission FIFO 00h 3Ah DOh 2 Read address 16 01h FFh EEh FFEEh and write it 02h DDh CCh to the data 03h BBh AAh transmission FIFO L 04h 99h 88h 3 Read address14 DDCCh and write it to the data transmission FIFO 4 Read address12 BBAAh and write it to the data transmission FIFO 5 Read address10 9988h and write it to the data transmission FIFO 6 Set port 0 interrupt information 1 V Receive process complete interrupt Bit 1 1 gt Interrupt occurs lt V Interrupt request Bit 021 4 The center device reads the status V Input change interrupt bit 221 5 Reset the input change interrupt 6 Place a command Data transmission FIFO 0300h in the data Address Upper Lower transmission FIFO 00h 03h DOh Data sending process 7 Write a data communication command 4008h 1 Send the contents of the data transmission FIFO ito the center device ooo Data communication 2nd time FOO E k e k k Interrupt occurs 8 The center device reads the status V Data communication complete lt bit 0 1 gt 9 Read data from the data reception FIFO 10
58. ki Wire Co Ltd F DTI C5 SLA CAT6 Oki Wire Co Ltd DTI C6X Pulse transformer Nippon Pulse Motor Co Ltd NPT102F Line transceiver TEXAS INSTRUMENTS SN75LBC180AP Level shifter TEXAS INSTRUMENTS SN74LVC244ADB 9 7 6 Other precautions Cables When you are planning long distance transmission cable quality will be the single most important factor Specialized cables designed for use as field busses such as those by CC Link and LONWORKS have guaranteed quality and may be easier to use Pulse transformers Needless to say the pulse transformers should handle 20 Mbps 10 MHz without becoming saturated The transformer s inductance is also important Since up to 64 pulse transformers may be connected the actual working specifications of these devices must be very similar We used 1000 pulse transformers However in order to obtain better response characteristics you may want to try pulse transformers with a larger reactance Line transceivers We used TEXAS Instruments chips for the experiments Other possibilities are available from MAXIM and LINEAR TECHNOLOGY who offer very high performance transceivers Connectors If possible the connectors should match the cable characteristics Although we did not use them modular type connecters will be better for LAN cables Cable connections Do not connect one cable to another cable using connectors etc In a multi drop system the number of cables increases as the nu
59. lity can be corrected inside the LSI if the deterioration level is not much In order to improve correction precision however evenness of the clock duty is required In other words if the duty is ideal 50 50 the capacity to correct collapse of the signals in the communication lines can be improved On the contrary if the duty is not ideal the center device cannot cope with collapses of the communication line As a result if the duty is close to ideal the center device can be used with 40 MHz When connecting more than one oscillator the duty will not be ideal In this case select 80 MHz The center device divides the frequency inside and creates 40 MHz frequency If you do not want to 80 MHz frequency you may prepare a separate 40 MHz oscillator for this LSI RST This is an input terminal for a reset signal By inputting an L level signal the center device is reset The RST line must be held LOW for at least 12 reference clock cycles After turning ON the power a reset signal must be input before starting communication DNO to 5 Input terminals for setting device address Since these terminals use negative logic setting all the terminals to zero calls up device address 3FH There are two methods for entering a device address Select the input method using the DNSM terminal 5 4 DNSM Select the input method for loading the device address 1 When the DNSM H Input numeric values 0 to 3Fh with negative logic using DI
60. ls Therefore it can control various LSIs that are normally connected to a CPU 2 Message communication mode One word 16 bits is reserved by the system in this mode which is used for communication the data commands and formats are specified The user can use the remaining 127 words to communicate data The format for the message data is not specified which means that this LSI can communicate freely with almost any CPU that is connected to the center device and to this LSI 2 Features Compatible with our Motionnet Can control various CPU support LSIs using data communications Amaximum of 256 bytes of data can be communicated in one sentence Amaximum of 64 devices can be connected using one line It has a safety design using a communication failure detection circuit contains a watchdog timer Powered from just 3 3 VDC 3 General specifications 3 1 Communication system specifications Item Description Reference clock 40 MHz or 80 MHz Communication speed 2 5M 5 M 10 M or 20 Mbps Communication sign NRZ sign Communication protocol NPM original method Communication method Half duplex communication Communication I F RS 485 or pulse transfer Connection method Multi drop connection Number of local devices 64 devices max Cyclic communication cycle when 20 Mbps When using 8 local devices IN 128 points OUT 128 points 0 12 msec
61. mber of local devices increase However connecting a cable just to extend the line should be avoided Processing of excess cable Excess cable left over after making all the runs should be eliminated Unneeded cable length may restrict the line overall usable length and may introduce electrical noise Circuit board substrate Create circuits on a substrate with 4 or more layers to prevent the introduction of noise Estimating cable length in the system design phase In the first estimate use shorter line lengths In the actual system configuration lines may be lengthened Estimates made using the maximum length may lead to impossible communication distances Minimum cable length Each cable must be at least 60 cm long Although this may seem contradictory to the excess cable precaution this minimum length is necessary Using different cables in one system Do not mix cables from different manufacturers even when they are in the same category Different cable models from the same manufacturer should not be used either Using different cables together may deteriorate the communication quality 49 10 Center device G9001 A We will use the following four commands to access the address map in the center device 1 Write command to the center device 16 bits Outpw Address Data Address Value corresponding to the address map in the center device 16 bits The lowest bit is ignored Data Data to write 1
62. mes out When TUD HIGH The LSI keeps its current status When the TUD LOW The LSI is Reset 5 8 TMD Specify the time for the watchdog timer The watchdog timer is used to administer the communication status When the interval between data packets sent from a center device is longer than the specified interval the watchdog timer times out the timer restarts its count at the end of each data packet received from a center device The time out may occur because of a problem on the communication circuit such as disconnection or simply because the center device has stopped communicating The time used by the watchdog timer varies with communication speed selected Watchdog timer setting TMD terminal Po Mbps 10Mbps 5Mbps 2 5 Mbps L 5 ms 10 ms 20 ms 40 ms H 20 ms 40 ms 80 ms 160 ms 5 9 TOUT Once the watchdog timer has timed out this terminal goes LOW 5 10 SO Serial output signal for communication Positive logic tri state output 5 11 SOEH SOEL Output enable signal for communication Difference between SOEH and SOEL is that only the logic is different When sending signals SOEH will become H and SOEL will become L 5 12 5 13 5 14 5 15 5 16 5 17 5 18 5 19 SOEI When using more than one device G9004A connect the SOEH signal of the other device G90044 to this terminal By being wire OR ed with the output enable signal from this
63. n or data communication is sent to the port data area in the center device G90014 In order to generate an interrupt position 1 in the center device G9001A when an interrupt request bit 0 1 on port 0 occurs in the local device G9004A you must enable the input change interrupt that corresponds to port 0 set it to 1 1 When the center device G9001A is the first to send a message and the local device G9004A responds Center device G9001A Local device G9004A Start 1 Write an information command 0001h Message transmission to the data transmission FIFO 2 Place a message in the data transmission FIFO 3 Write a data communication command 4008h Interrupt occurs Interrupt occurs 4 The center device reads the status 1 Read the status V Data transmission complete bit 0 1 gt V Data reception interrupt bit 0 1 gt 2 Read the message in the data reception FIFO 3 Place the message in the data transmission FIFO 4 Write a data transmission command 10h Set the status for port 0 interrupt information Local device data transmission request interrupt Bit 1 1 gt Interruptoccurs lt Y Local device interrupt request Bit 0 1 5 The center device reads the status Input change interrupt bit 2 1 gt 6 Input change interrupt 7 Send an information command to the data transmission FIFO Write 0001h Message transmissi
64. name I O Logic Description 5V Interface When sending data to this chip this signal 9r Negative becomes L de for a rated 50 VDD 3 3 V power input 51 SOEH Positive Enable serial output 52 SOEL O Negative Enable serial output 53 SO Positive Serial output 54 4 TOUT O Negative Watchdog timer output Available 55 DNSO O Negative Serial output of device number for next chip Available 56 GND GND 57 BRK Positive Break frame send request Available 58 SPDO Communication speed 0 Available 59 SPD1 Communication speed 1 Available 60 CKSL Clock rate selection L 40 MHz 80 MHz Available 61 DNSM Device number selection mode Available 62 DNo Negative ud number bit 0 common with serial Available 63 DN1 Negative Device number bit 1 Available 64 DN2 Negative Device number bit 2 Available 65 DN3 Negative Device number bit 3 Available 66 DN4 Negative Device number bit 4 Available 67 DN5 Negative Device number bit 5 Available 68 VDD 3 3 V power input 69 Sl Positive Serial input 70 SOEI Positive Enable serial output 71 GND GND 72 CLK Reference clock 73 VDD 3 3 V power input 74 RST Negative Reset 75 GND GND 76 GND GND 77 VDD 3 3 V power input 78 GND GND 79 GND GND 80 GND GND Note 1 In the I O column
65. ns against the influence of heat in the environment and keep the temperature around the LSI as cool as possible 3 Please note that ignoring the following may result in latching up and may cause overheating and smoke Do not apply a voltage greater than 3 3V greater than 5V for 5V connectable terminals to the input output terminals and do not pull them below GND Please consider the voltage drop timing when turning the power ON OFF Consider power voltage drop timing when turning ON OFF the power Make sure you consider the input timing when power is applied Be careful not to introduce external noise into the LSI Hold the unused input terminals to 3 3 V or GND level Do not short circuit the outputs Protect the LSI from inductive pulses caused by electrical sources that generate large voltage surges and take appropriate precautions against static electricity 4 Provide external circuit protection components so that overvoltages caused by noise voltage surges or static electricity are not fed to the LSI 13 2 Precautions for transporting and storing LSIs 1 Always handle LSls carefully and keep them in their packages Throwing or dropping LSIs may damage them 2 Do not store LSls in a location exposed to water droplets or direct sunlight 3 Do not store the LSI in a location where corrosive gases are present or in excessively dusty environments 4 Store the LSls in an anti static storage container and make sure that
66. o DN5 LH ons Device number Note 3 In the case that continuous address by amp DNSO is set it is necessary to have at least about 50 5 until next address Local device is confirmed GND Note 1 When connecting the serial lines to line transceivers make the path as short and straight as possible Running these lines on a PC board could deteriorate the communication performance Note 2 Pull down resistors to GND should be 5 to 10 k ohms 45 9 5 Aconnection example of a level shifter When using a 5 V line transceiver a level shifter is needed Shown below is an example of the connections for a level shifter TI SN74LVC244A and line transceiver TI SN75LBC180A SN75LBC180A Pulse transformer G9000 series SN74LVC244A Communication line If the pulse transformer is at the end of the communication line insert a terminating resistor either GND before or after the pulse transformer 46 9 6 Complete configuration We recommend a configuration with the center device at one end of the line and the local devices at other end as shown below If you want to place the center device in the middle of the line use two communication lines so that the center device is effectively at the end of each line Center device SIB SIA 2 d SO 5 g 5 SOEH 2 5 S 2 T Local device 4 E 3 2 Sl 2 5 S0 S e 1SOEH If needed construct the same z configura
67. of item 3 above Logic indicators 1 Terminal names and signal names that start with a use negative logic Ex CS means that the CS terminal uses negative logic This has the same meaning as CS ENS 1 DAI h 1 3 General speciflCatlons d dade de dt d ag quoe gu T Ae a dau Re pea a ete 1 3 1 Communication system specifications enne nennen nnns nnns 1 3 1 Specifications of the CPU emulation device G9004A 1 4 a EE 3 4 1 A list or terminals QEP 80 terne ed te tte te et ea ea tei Ro Lue oe ie 3 4 2 Terminal assignment drawings iii 5 4 3 Entire block diagram iter rer ee bare deor baud hase e held 6 5 FUNCTIONS OF terminals de toc het Lec n e tib ebbe ia ot e Pa ee 7 Pe T eee 7 a 7 5 9 JEDNO O5 ud oe alte ett 7 sc usu EE 7 BD HON SO UH 8 5 6 SP DO SPD Tc mto Root ane ete sata vac en ue pe ede T 8 SAM 8 SEM pnr 8 sa Jeu PEL 8 Saco 8 SOB OM EE 8 soi THEE ER 9 mm EL T E EM 9 b T4 S MBEB ziii aat teda ia E ee d adt lu LR DONE aet 9 b 15 adi S Lodo E erepta utere Pam 9 uM sl MEET 9 MODES e no cL e t ME LI
68. on 8 Write a data communication command 4008h KKK KKK k k k k k k k k k k Data communication 2nd time Kk k k k k kk k K K K k k k k When the Local device receives a message from the center Liu device it sends the data in the FIFO to the center device Interrupt occurs 9 Read the status Data communication complete bit 0 1 gt 10 Read the message in the data reception FIFO 11 Send an information command 0002h reset the data transmission processing flag to the data transmission FIFO This is how the center device informs the local device that the data was received normally Interrupt occurs Reset the data transmission FIFO 13 Read the center device status Interrupt occurs Data communication complete bit 0 1 gt 5 Read the local device status Transmission process complete interrupt bit 1 18 2 When the local device G90044 is the first to send a message and the center device G9001A responds Center device G9001A Local device G9004A Start 1 Place a message in the data transmission FIFO 2 Write a data send command 10h Set the status for port 0 interrupt information 1 Y Local device data send request interrupt bit 1 1 gt Interrupt occurs Local device interrupt request bit 0 1 gt 1 Read the center device status Input change interrupt bit 221 2 Reset the input change interrup
69. ou can access the LSI This terminal cannot be used in the CPU emulation mode LAO to LA5 Address signals for the local bus These will be either input or output terminals depending on the mode selected In the CPU emulation mode the device outputs address signals from terminals LAO to LAS In the message communication mode input address signals on LAO and LA1 Pull LA2 to LA5 down to GND 5 10Kohm resistors LCS This is a chip select signal for the local bus It will be either an input or output terminal depending on the mode selected In the CPU emulation mode this device outputs a chip select signal for an external circuit In the message communication mode you supply a chip select signal that will be used to access this LSI LWR This terminal is used for a write signal for a local bus It will be either an input or output terminal depending on the mode selected In the CPU emulation mode this terminal outputs a write signal for external circuit In the message communication mode you supply a write signal in order to access this LSI LRD This terminal is used for a read signal for a local bus It will be either an input or output terminal depending on the mode selected In the CPU emulation mode this terminal outputs a read signal for an external circuit In the message communication mode you supply a read signal in order to access this LSI 10 5 27 5 28 5 29 5 30 LWRQ This terminal
70. rom address 001 4 FFEEh and write it to the data te ADDS CCR transmission FIFO 4 Read from address 6 DDCCh and write it to the data transmission FIFO 5 Set the status on port 0 interrupt information 4 Receive process complete interrupt Bit 1 2 1 Interrupt occurs Y Interrupt request lt Bit 0 1 gt 6 The center device reads the status V Input change interrupt lt Bit 2 1 gt 7 Reset the input Data transmission FIFO change interrupt Address Upper Lower Write 0300h 00h 03h 00h to the data transmission Data sending process Send the contents of the data transmission FIFO ito the center device ooo Data communication 2nd time FOO RR Interrupt occurs 10 The center device reads the status Complete data communication bit 021 11 Read the data from the data receipt FIFO 12 Place a Data transmission FIFO command Address Upper Lower 0400h 00h 04h 00h in the data transmission FIFO Reset the reception process complete interrupt 13 Write a data communication command Interrupt occurs 14 The center device reads the status Compete data communication Bit 0 1 gt End emulation communication 29 8 3 Emulation timing 8 3 1 16 bit CPU I F 1 8086 H8 etc 8 3 1 1 Read cycle 1 without a wait cycle LCLK LA5
71. s 3 When setting CKSL Item Symbol Min Max Unit Frequency 80 2 12 5 ns HIGH duration ns LOW duration ns 11 4 2 Reset timing RST Internal RST Item Symbol Min Max Unit Reset length Twrsri 10 Clock cycles Delay time Torst 10 Clock cycles Note 1 The reset signal must last at least 10 cycles of the system clock While resetting make sure the clock signal is continuously available to the device If the clock is stopped while resetting the device cannot be reset normally 56 11 5 Timing of CPU message communication mode 11 5 1 8 bit I F 1 IF1 IFO Read cycle LA 1 0 LCS LWRQ LRD LD 7 0 Write cycle LA 1 0 LCS LWRQ LWR LD 7 0 Item Symbol Condition Min Max Unit Address setup time for LRD LWR 17 ns Address hold time for LRD LWR 7 Tawa 0 ns 4 LCS setup time for LRD LWR 4 Tesni 5 ns LCS hold time for LRD LWR 7 Trwcs 0 ns LWRQ ON delay time for LCS Ci 40pF 12 ns LWRQ signal LOW time Twat Note 1 6 11 ns Data output delay time for LRD 4 CL 40 29 ns Data output delay time for LWRQ T Ci 40pF 16 ns Data float delay time for LRD 7 Troup 40pF 30 ns LWR signal width Twr Note 2 12 ns Data setup time for LWR 7 Tpwn 22 n
72. s Data hold time for LWR 7 0 ns Note1 When CKSL LOW HIGH the data output delay time will be 12 11 Note 2 The time that the WRQ signal is output will be the interval after WRQ goes HIGH until WR goes HIGH 57 11 5 2 8 bit I F 2 IF1 IFO L Read cycle LRD E Tpwe TEA LA 1 0 ED LCS Tose Tecs eeu pl mee n MM LWRQ ad hr ne LWR qu NEN Write cycle Terc LRD E SL LA 1 0 LCS Tose Twar Tecs 1 EE LWRQ Trwe Terw TEM p To Te ow 3 Item Symbol Condition Min Max Unit Enable cycle time 100 ns Enable pulse width Tpwe 40 ns Address setup time for LRD E 7 17 5 Address hold time for LRD E 4 0 ns R W setup time for LRD E 7 5 ns R W hold time for LRD E 4 5 ns LCS setup time for 4LRD E 7 Tose 5 ns LCS hold time for LRD E 4 Tecs 0 ns LWRQ ON delay time for LCS 4 40pF 12 ns LWRQ signal LOW time Twat Note 1 11 ns Data output delay time for E T Teno Ci 40pF 19 ns Data output delay time for LWRQ 7 40pF 6 ns Data float delay time for LRD E Tapa 40pF 19 ns Data setup time for LRD E 4 22 5 Data hold time for LRD E 4 0 ns
73. setting However when the message communication mode is selected only the LCLK output frequency will change and the operation speed remains constant LCLK Outputs a clock for controlling a local bus If needed it can be used for an external circuit 5 20 5 21 5 22 5 23 5 24 5 25 5 26 LIFO to 1 Using these terminals select the CPU interface specifications for the local bus LIF1 LIF 0 CPU I F interface L L I F 16 bit 2 68000 etc L H I F 16 bit 1 8086 H8 etc H L I F 8 bit 2 6809 etc H H I F 8 bit 1 Z80 etc LRST Output a reset signal for the local bus In any of the following cases this signal goes LOW 1 When a LOW is applied to the RST terminal 2 When TUD is LOW the watchdog timer has timed out only effective during approximate 32 cycles on LCLK The 4LRST terminal status can be changed by setting bit 1 of port 3 See section 6 Setting the status information and G9004A operation information When bit 1 0 LRST HIGH When bit 1 1 LRST LOW LIFB Outputs an interface busy signal for the local bus Use this signal in the message communication mode when connecting to a CPU that does not have a wait control input terminal This terminal goes LOW when a command or data is sent from a CPU or when the status is being read When this LSI completes its internal processing it goes HIGH Make sure that this terminal is HIGH and then y
74. t 8 Send an information command 0001h message transmission to the data transmission FIFO 4 Place a message in the data transmission FIFO b Write a data communication command 4008h xkkkkkkkkkkkkxkkxkx Data communication 1st time FIRE RRR After receiving a message from the center device the local device sends the data in the FIFO to the center RUNE 525 LE Interrupt occurs Interrupt occurs 6 The center device reads the status 3 The local device reads the status V Data communication compete bit 0 1 gt Data received interrupt Bit 021 7 Read the message in the data reception FIFO 4 Read the message in the data reception FIFO 8 Send an information command 0002h Reset the data send processing flag to the data transmission FIFO This is how the center device informs the local device that the data was received normally 9 Write a data communication command 4008h Interrupt occurs Reset data transmission FIFO 10 Read the status Interrupt occurs Data communication compete bit 0 1 gt 5 Read the status of the local device V Data transmission process complete interrupt bit 121 End of message communication 19 8 CPU emulation mode MOD H Configuration block diagram Control bus Center side G9001A CPU G9001A N G9004A Serial communication CPU support LSIs PCL series etc
75. tion on this side B Local device g E SI 2 a SO 2 3 2 SOEH Terminating resistors are 2 needed at the ends of the line Insert them either Local device before or after the pulse 5 transformer to get the 3 z SI same effect Terminating 2 5 SO resistors are not needed S 9 anywhere except for the i lt ends of the line 3 Local device S E SI 2 S SO o 3 5 47 Shown below are the results of our experimental communication results and the environment used for the experiment These results can be used to design your own system However other system configurations are possible 9 7 Recommended environment The example below is only for your reference Conditions Results Transmission ae of Cable Terminating Pulse VF chip Max rate devices used resistor transformer length 20 Mbps 32 CAT5 100 ohm 1000 uH RS485 100 m 20 Mbps 64 CAT5 100 ohm 1000 uH RS485 50m 10 Mbps 64 CAT6 100 ohm 1000 uH RS485 100 m Note In the figures above the maximum length figures are results from ideal conditions in a laboratory 9 7 1 9 7 2 9 7 3 9 7 4 In actual use the results may not be the same Cable Commercially available LAN cables were used Category 5 6 Category 6 We used these LAN cables because they are high quality inexpensive and easy to obtain Lower quality cables such as cheap instrument cables may
76. train generating LSI for NPM s motion control network One PCL6045B can generate pulse trains for four axes G9004A 8086 type emulation CPU PCL6045B 5V VDD LA5 Decoding CLK LIFT LCS circuit LIFO 9 Note 2 Note 1 MOD LA1 to LA4 GND LIRQ System reset GND Note 1 The G9004A can be connected to two PCL6045Bs In this case the LA5 signal is used to tell the two chips apart This line is the equivalent of a decoder circuit When only one device is connected to the G9004A there is need to provide a decoder circuit The LCS output terminal on the G9004A can be connected to the CS terminal on the PCL6045B Note 2 The LCLK clock output on the CPU emulation device G9004A cannot be connected to the CLK input clock input on the PCL6045B The LCLK output is 3 3 V but the PCL6045B are 5V devices and their CLK inputs use CMOS levels Viu 4 V min Vi 1 V max They cannot be connected directly to 3 3V devices Also the PCL6045B needs a 19 6608 MHz clock If it is connected to some other clock speed such as a 20 MHz clock it may complicate setting the multiplication factor For details see the user s manual for the PCL6045B 42 9 3 2 Connections to the PCD4541 Z80 type CPU emulation The PCD4541 is an NPM sequence LSI for use with stepper motors G9004A Z80 type emulation CPU PCD4541 LA4 to LA5 pecoding LIFT gt circuit MOD LAO to LA3 LIRQ

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