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GRLIB IP Core User's Manual

1. F0 77 KEY MAKE BREAK KEY MAKE BREAK KEY MAKE BREAK A 1C F0 1C 9 46 F0 46 54 FO 54 B 32 F0 32 OE F0 0E INSERT E0 70 E0 F0 70 C 21 F0 21 4E F0 4E HOME E0 6C E0 F0 6C D 23 F0 23 55 FO 55 PG UP E0 7D E0 F0 7D E 24 F0 24 5D F0 5D DELETE E0 71 E0 F0 71 F 2B F0 2B BKSP 66 F0 66 END E0 69 E0 F0 69 G 34 F0 34 SPACE 29 F0 29 PG DN E0 7A E0 F0 7A H 33 F0 33 TAB 0D F0 0D U E0 75 E0 F0 75 ARROW I 43 F0 43 CAPS 58 F0 58 L E0 6B E0 F0 6B ARROW J 3B F0 3B L SHFT 12 FO 12 D E0 72 E0 F0 72 ARROW K 42 F0 42 L CTRL 14 FO 14 R E0 74 E0 F0 74 ARROW L 4B F0 4B L GUI E0 1F EO FO 1F NUM 77 F0 77 M 3A F0 3A L ALT 11 FO 11 KP E0 4A E0 F0 4A N 31 FO0 31 R SHFT 59 F0 59 KP 7C F0 7C O 44 F0 44 RCTRL E0 14 E0 FO 14 KP 7B F0 7B P 4D F0 4D R GUI E0 27 E0 F0 27 KP 79 F0 79 Q 15 F0 15 R ALT E0 11 E0 FO 11 KP EN E0 5A E0 F0 5A R 2D F0 2D APPS E0 2F E0 F0 2F KP 71 FO0 71 S 1B FO0 1B ENTER SA FO SA KP 0 70 F0 70 T 2C F0 2C ESC 76 F0 76 KP 1 69 F0 69 U 3C F0 3C Fl 5 F0 05 KP 2 72 F0 72 V 2A F0 2A F2 F0 06 KP 3 7A F0 7A W 1D F0 1D F3 F0 04 KP 4 6B F0 6B X 22 F0 22 F4 0C F0 0C KP5 73 F0 73 Y 35 F0 35 F5 3 F0 03 KP 6 74 F0 74 Z 1A F0 1A F6 OB F0 0B KP7 6C F0 6C 0 45 F0 45 F7 83 F0 83 KP 8 75 F0 75 1 16 F0 16 FS DA F0 0A KP 9 7D F0 7D 2 1E F0 1E F9 1 F0 01 5B F0 5B 3 26 F0 26 F10 9 F0 09 3 4C F0 4C 4 25 F0 25 F11 78 F0 78 52 F
2. Table 407 DSU memory map Address offset Register 0x 000000 DSU control register 0x000008 Time tag counter 0x000020 Break and Single Step register 0x000024 Debug Mode Mask register 0x 000040 AHB trace buffer control register 0x000044 AHB trace buffer index register 0x000050 AHB breakpoint address 1 0x000054 AHB mask register 1 0x000058 AHB breakpoint address 2 0x00005c AHB mask register 2 0x 100000 0x110000 Instruction trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 C Trace bits 31 0 0x 110000 Intruction Trace buffer control register 0x200000 0x210000 AHB trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 C Trace bits 31 0 0x300000 0x300FFC TU register file 0x301000 0x30107C FPU register file 0x301800 0x30187C FPU register file check bits 0x400000 Ox4FFEFC IU special purpose registers 0x400000 Y register 0x400004 PSR register 0x400008 WIM register 0x40000C TBR register 0x400010 PC register 0x400014 NPC register 0x400018 FSR register 0x40001C CPSR register 0x400020 DSU trap register 0x400024 DSU ASI register 0x400040 0x40007C ASR16 ASR31 when implemented 0x700000 Ox 7FFFFC ASI diagnostic access ASI value in DSU ASI register address address 19 0 ASI 0x9 Local instruction RAM ASI OxB Local data RAM ASI OxC Instruction cache tags ASI
3. see GRLIB IP Library User s Manual Signal name Field Type Function Active SRI DATA 15 0 Input Memory data High 15 0 used for IO accesses 7 0 used for checkbits for SRAM accesses 15 8 use for data for SRAM accesses BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low WRNI 3 0 Input Not used BWIDTH 1 0 Input Not used SD 31 0 Input Not used 2 CB 7 0 Input Not used PROMDATA 31 0 Input Not used EDAC Input Not used SRO ADDRESS 27 0 Output Memory address High DATA 15 0 Output Memory data High 15 0 used for IO accesses 7 0 used for checkbits for SRAM accesses 15 8 use for data for SRAM accesses RAMSN 7 0 Output SRAM chip select Low RAMOENT 7 0 Output SRAM output enable Low IOSN Output IO area chip select Low ROMSN 7 0 Output Not used Low OEN Output Output enable Low WRITEN Output Write strobe Low WRN 1 0 Output SRAM write enable Low WRNI 0 corresponds to DATA 15 8 WRN 1 corresponds to DATA 7 0 BDRIVE 1 0 Output Drive byte lanes on external memory bus Con Low trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 15 8 BDRIVE 1 corresponds to DATA 7 0 VBDRIVE 15 0 Output Vectored I O pad drive signal Low READ Output Read strobe High RAMN Output Common SRAM Chip Select Always asserted Low when one of the 8 RAMSN signals is asserted ROMN Output Not used SA 14 0 Output Not
4. Signal name Field Type Function Active MEMO ADDRESS 27 0 Output Memory address High CBO 7 0 Output EDAC Checkbit DATA 31 0 Output Memory data SDDATA 63 0 Output Sdram memory data RAMSN 4 0 Output SRAM chip select Low RAMOEN 4 0 Output SRAM output enable Low IOSN Output Local I O select Low ROMSNI 3 0 Output PROM chip select Low OEN Output Output enable Low WRITEN Output Write strobe Low WRNI 3 0 Output SRAM write enable Low WRNI 0 corresponds to DATA 31 24 WRN 1 corresponds to DATA 23 16 WRN 2 corresponds to DATA 15 8 WRN 3 corresponds to DATA 7 0 Any WRN signal can be used for CB MBEN 3 0 Output Byte enable Low MBEN 0 corresponds to DATA 31 24 MBEN 1 corresponds to DATA 23 16 MBEN 2 corresponds to DATA 15 8 MBEN 3 corresponds to DATA 7 0 Any MBEN signal can be used for CB BDRIVE 3 0 Output Drive byte lanes on external memory bus Con Low High trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 31 24 BDRIVE 1 corresponds to DATA 23 16 BDRIVE 2 corresponds to DATA 15 8 BDRIVE 3 corresponds to DATA 7 0 Any BDRIVE signal can be used for CB VBDRIVE 31 0 Output Vectored I O pad drive signals Low High SVBDRIVE 63 0 Output Vectored I O pad drive signals for separate Low High sdram bus READ Output Read strobe High SA 14 0 Output SDRAM separate address bus High AHBSI i Input AHB slave input signals
5. 31 30 29 28 27 26 25 24 23 20 19 18 17 PBRDY ABRDY IOBUSW IBRDY BEXCN IO WAITSTATES IOEN ROMBANKSZ 14 13 12 11 10 9 8 7 4 3 0 RESERVED PWEN PROM WIDTH PROM WRITE WS PROM READ WS 31 RESERVED 30 PROM area bus ready enable PBRDY Enables bus ready BRDYN signalling for the PROM area Reset to 0 29 Asynchronous bus ready ABRDY Enables asynchronous bus ready 28 27 T O bus width IOBUSW Sets the data width of the I O area 00 8 01 16 10 32 26 T O bus ready enable IBRDY Enables bus ready BRDYN signalling for the I O area Reset to 0 25 Bus error enable BEXCN Enables bus error signalling Reset to 0 24 RESERVED 23 20 T O waitstates IO WAITSTATES Sets the number of waitstates during I O accesses 0000 0 0001 1 0010 2 1111 15 19 T O enable IOEN Enables accesses to the memory bus I O area 18 RESERVED 17 14 PROM bank size ROMBANKSZ Returns current PROM bank size when read 0000 is a spe cial case and corresponds to a bank size of 256 MB All other values give the bank size in binary steps 0001 16kB 0010 32kB 1111 256 MB For value 0000 or 1111 only two chip selects are available For other values two chip select signals are available for fixed bank sizes For other values four chip select signals are available for programmable bank sizes Programmable bank
6. LEON3 LEON3 DSU3 SDRAM mu SPRAM STRI Controller High speed bus TRE AHB AHB Serial JTAG Bridge Dbg Link Dbg Link PROM Async Mem AHB Controller Low speed bus CTRL SRAM AHB APB Ethernet Bridge MAC ie UARTS Timers IrqCtrl Figure 2 LEON3 system with AHB AHB bus Operation 3 2 1 General AHB AHB bridge is connected to each AHB bus through a pair consisting of AHB Master and AHB Slave interface Address space occupied by the AHB AHB bridge on each bus is determined by Bank Address Registers which are configured through VHDL generics Bridge is capable of handling sin gle and burst transfers in both direction Internal FIFOs are used for data buffering The bridge imple ments SPLIT response to improve AHB bus utilization For more information on AHB transfers supported by the bridge refer to uni directional AHB AHB bridge AHB2AHB documentation 3 2 2 Dead lock detection A dead lock situation can occur if the bus is simultaneously accessed from both buses Bridge con tains dead lock detection logic which will resolve dead lock condition by giving RETRY response on the low speed bus Registers The core does not implement any registers Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x020 For description of vendor and device identifiers see GRLIB IP Library User s Manual 3 5 Configuration
7. Figure 171 Cache control register 23 Data cache snoop enable DS if set will enable data cache snooping 22 Flush data cache FD If set will flush the instruction cache Always reads as zero 21 Flush Instruction cache FI If set will flush the instruction cache Always reads as zero 16 Instruction burst fetch IB This bit enables burst fill during instruction fetch 15 Instruction cache flush pending IP This bit is set when an instruction cache flush operation is in progress 14 Data cache flush pending DP This bit is set when an data cache flush operation is in progress 5 Data Cache Freeze on Interrupt DF If set the data cache will automatically be frozen when an asynchronous interrupt is taken 4 Instruction Cache Freeze on Interrupt IF If set the instruction cache will automatically be frozen when an asynchronous interrupt is taken 3 2 Data Cache state DCS Indicates the current data cache state according to the following X0 disabled 01 frozen 11 enabled 1 0 Instruction Cache state ICS Indicates the current data cache state according to the following X0 disabled 01 frozen 11 enabled If the DF or IF bit is set the corresponding cache will be frozen when an asynchronous interrupt is taken This can be beneficial in real time system to allow a more accurate calculation of worst case execution time for a code segment The e
8. see GRLIB IP Library User s Manual Library dependencies Table 68 shows libraries used when instantiating the core VHDL libraries Table 68 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals APB signal definitions GAISLER MISC Signals component PS 2 signal and component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib gencomp all 78 library gaisler use gaisler misc all entity apbps2_ex is port rstn in std_ulogic clk in std_ulogic PS 2 signals ps2clk inout std_ulogic ps2data inout std_ulogic i end architecture rtl of apbuart_ex is APB signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none PS 2 signals signal kbdi ps2_in_type signal kbdo ps2_out_type begin ps20 apbps2 generic map pindex gt 5 paddr gt 5 pirq gt 4 port map rstn clkm apbi apbo 5 kbdi kbdo kbdclk_pad iopad generic map tech gt padtech port map ps2clk kbdo ps2_clk_o kbdo ps2_clk_oe kbdi ps2_clk_i kbdata_pad iopad generic map tech gt padtech port map ps2data kbdo ps2_data_o kbdo ps2_data_oe end kbdi ps2_data_i 14 11 Keboard scan codes Table 69 Scan code set 2 104 key keyboard 79
9. Bit Name Description SR 7 Bus status 1 when the core is in bus off and not involved in bus activities SR 6 Error status At least one of the error counters have reached or exceeded the error warning limit SR 5 Transmit status 1 when transmitting a message SR 4 Receive status 1 when receiving a message SR 3 Transmission complete l indicates the last message was successfully transferred SR 2 Transmit buffer status 1 means CPU can write into the transmit buffer SR 1 Data overrun status 1 if a message was lost because no space in fifo SR 0 Receive buffer status 1 if messages available in the receive fifo Receive buffer status is cleared when there are no more messages in the fifo The data overrun status signals that a message which was accepted could not be placed in the fifo because not enough space left NOTE This bit differs from the SJA1000 behavior and is set first when the fifo has been read out When the transmit buffer status is high the transmit buffer is available to be written into by the CPU During an on going transmission the buffer is locked and this bit is 0 The transmission complete bit is set to 0 when a transmission request or self reception request has been issued and will not be set to 1 again until a message has successfully been transmitted 21 5 5 Interrupt register The interrupt register signals to CPU what caused the interrupt The interrupt bits are only set if the corres
10. Signal name Field Type Function Active CLK N A Input Clock All input signals are latched on the rising edge of the clock ADDRESS N A Input Address bus Used for both read and write access DATAIN N A Input Data inputs for write data DATAOUT N A Output Data outputs for read data ENABLE N A Input Chip select High WRITE N A Input Write enable High Library dependencies Table 471 shows libraries used when instantiating the core VHDL libraries Table 471 Library dependencies Library TECHMAP Package GENCOMP Constants Imported unit s Description Technology contants Component declaration The core has the following component declaration library techmap use techmap gencomp all component syncram generic tech integer 0 abits integer 6 dbits integer 8 port clk in std_ulogic address in std_logic_vector abits 1 downto 0 datain in std_logic_vector dbits 1 downto 0 dataout out std_logic_vector dbits 1 downto 0 enable in std_ulogic write in std_ulogic end component Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library techmap use techmap gencomp all clk std_ulogic address std_logic_vector abits 1 downto 0 datain std_logic_vector dbits 1 downto 0 dataout std_logic_vector dbits 1 downto 0 enable std_ulogic
11. The following is required for successful communication with the EDCL A correct destination MAC address as set by the generics an Ethernet type field containing 0x0806 ARP or 0x0800 IP The IP address is then compared with the value determined by the generics for a match The IP header checksum and identification fields are not checked There are a few restrictions on the IP header fields The version must be four and the header size must be 5 B no options The protocol field must always be 0x11 indicating a UDP packet The length and checksum are the only IP fields changed for the reply The EDCL only provides one service at the moment and it is therefore not required to check the UDP port number The reply will have the original source port number in both the source and destination fields UDP checksum are not used and the checksum field is set to zero in the replies 35 7 291 The UDP data field contains the EDCL application protocol fields Table 306 shows the application protocol fields data field excluded in packets received by the EDCL The 16 bit offset is used to align the rest of the application layer data to word boundaries in memory and can thus be set to any value The R W field determines whether a read 0 or a write 1 should be performed The length Table 306 The EDCL application layer fields in received frames 16 bit Offset 14 bit Sequence number 1 bit R W 10 bit Length 7 bit Unused
12. AMBA bus Buffer DMA Controller y PCI Bridge Cfg Stat lt AHB Slave AHB Master y y MTx FIFO MRx FIFO TIx FIFO TRx FIFO t oat PCI Master PCI Target a pa a PCI Off chip bus Figure 213 DMA Controller unit Operation The DMA controller is set up by defining the location of memory areas between which the DMA will take place in both PCI and AHB address space as well as direction length and type of the transfer Only 32 bit word transfer are supported The DMA transfer is automatically aborted when any kind of error is detected during a transfer The DMA controller does not detect deadlocks in its communication channels If the system concludes that a deadlock has occurred it can manually abort the DMA transfer It is allowed to perform burst over a 1 Kbyte boundary of the AHB bus When this happens an AHB idle cycle will be automati cally inserted to break up the burst over the boundary When the DMA is not active the AHB slave interface of PCI Master Target unit will be directly con nected to AMBA AHB bus 439 51 3 Registers The core is programmed through registers mapped into APB address space Table 434 DMA Controller registers Address offset Register 0x00 Command status register 0x04 AMBA Target Address 0x08 PCI Target Address 0x0C Burst length 31 8 7 4 3 2 1 0 RESERVED TTYPE ERR RDY TD ST Figure 214 Status Command register 31 8
13. 2 SINGLE Single shot mode 1 ONGOING Transmission ongoing 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that if the SINGLE bit is 1b the channel is disabled i e the ENABLE bit is cleared to Ob if the arbitration on the CAN bus is lost Note that in the case an AHB bus error occurs during an access while fetching transmit data and the CanCONF ABORT bit is 1b then the ENABLE bit will be reset automatically At the time the ENABLE is cleared to 0b any ongoing message transmission is not aborted unless the CAN arbitration is lost or communication has failed Note that the ONGOING bit being 1b indicates that message transmission is ongoing and that config uration of the channel is not safe 22 9 7 Transmit Channel Address Register CanTxADDR R W Table 157 Transmit Channel Address Register 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer All bits are cleared to 0 at reset 22 9 8 Transmit Channel Size Register CanTxSIZE R W Table 158 Transmit Channel Size Register 31 21 20 6 5 0 SIZE 20 6 SIZE The size of the circular buffer is SIZE 4 messages All bits are cleared to 0 at reset 152 Valid SIZE values are between 0 and 16384 Note that each message occupies four 32 bit words Note that the resulting behavior of invalid SIZE values is undefined Note that only SIZE 4 1 messages can be stored simultaneously in the buffer This is to simpli
14. I O ready enable BEXCN enable Prom write enable Prom width Figure 232 Memory configuration register 468 57 4 57 5 8 0 7 4 10 11 17 12 19 23 20 25 26 28 27 Prom read waitstates Defines the number of waitstates during prom read cycles 0000 0 0001 1 1111 15 Prom write waitstates Defines the number of waitstates during prom write cycles 0000 0 0001 1 1111 15 9 8 Prom width Defines the data with of the prom area 00 8 01 16 10 32 The width is hardwired to 10 32 bit Reserved Prom write enable If set enables write cycles to the prom area NOT USED Reserved T O enable If set the access to the memory bus I O area are enabled NOT USED T O waitstates Defines the number of waitstates during I O accesses 0000 0 0001 1 0010 2 1111 15 Bus error BEXCN enable NOT USED Bus ready BRDYN enable NOT USED T O bus width Defines the data with of the I O area 00 8 01 16 10 32 The width is hardwired to 10 32 bit During power up reset the PROM waitstates fields are set to 15 maximum All other fields are ini tialized to zero Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier OxOOA For description of vendor and device identifiers see GRLIB IP
15. 25 AMBA signals maser bus signal ahbmil ahb_mst_in type signal ahbmo_m ahb_mst_out_vector others gt ahbm_none signal ahbsi_m ahb_slv_in type signal ahbso_m ahb_slv_out_type others gt ahbs_none AMBA signals slave bus signal ahbmi_s ahb_mst_in_type signal ahbmo_s ahb_mst_out_vector others gt ahbm_none signal ahbsi_s ahb_slv_in type signal ahbso_s ahb_slv_out_type others gt ahbs_none begin AHB AHB uni directional bridge ahb2ahb0 ahb2ahb generic map hsindex gt 1 hmindex gt 3 pfen gt 1 iburst gt 8 mb0en gt 1 haddr0 gt 164008 hmask gt 16 F00 hcache0 gt 1 pfetch0 gt 1 port map hclkm hclks rst ahbsi_s ahbso_s 3 ahbmi_m ahbmo_m 3 ahbso_s gnd gnd open open end 26 3 1 3 2 3 3 3 4 AHBBRIDGE Bi directional AHB AHB bridge Overview A typical application where AHB AHB Bridge is used to partition system in high speed AHB bus hosting LEON3 CPUs and external memory controller with low speed AHB bus hosting slow com munication IP cores is shown in figure 2 The bridge is capable of connecting two AHB buses clocked by synchronous clocks with any frequency ratio Internally the bridge consists of two uni directional AHB to AHB bridges see AHB2AHB core
16. APB address offset Register 16 020 Key 0 Register 16 024 Key 1 Register 16 028 Key 2 Register 16 02C Key 3 Register 16 030 Key 4 Register 16 034 Key 5 Register 16 038 Key 6 Register 16 03C Key 7 Register 16 040 Point X Input 0 Register 16 044 Point X Input 1 Register 16 048 Point X Input 2 Register 16 04C Point X Input 3 Register 16 050 Point X Input 4 Register 16 054 Point X Input 5 Register 16 058 Point X Input 6 Register 16 05C Point X Input 7 Register 16 060 Point Y Input 0 Register 16 064 Point Y Input 1 Register 16 068 Point Y Input 2 Register 16 06C Point Y Input 3 Register 16 070 Point Y Input 4 Register 16 074 Point Y Input 5 Register 16 078 Point Y Input 6 Register 16 07C Point Y Input 7 Register 16 0A0 Point X Output O Register 16 0A4 Point X Output 1 Register 16 0A8 Point X Output 2 Register 16 0AC Point X Output 3 Register 16 0BO0 Point X Output 4 Register 16 0B4 Point X Output 5 Register 16 0B8 Point X Output 6 Register 16 0BC Point X Output 7 Register 16 0CO Point Y Output O Register 16 0C4 Point Y Output 1 Register 16 0C8 Point Y Output 2 Register 16 0CC Point Y Output 3 Register 16 0D0 Point Y Output 4 Register 16 0D4 Point Y Output 5 Register 16 0D8 Point Y Output 6 Register 16 0DC Point Y Output 7 Register 16 0FC Status Register 264 33 8 1 Key 0 to 7 Registers W Table 253 Key 0 Register least significant 31 KEY 31 downto 0
17. FT AHB RAM a0 ftahbram generic map hindex gt 1 haddr gt 1 tech gt inferred kbytes gt 64 pindex gt 4 paddr gt 4 edacen gt 1 autoscrub gt 0 errcnt gt 1 cntbits gt 4 port map rst clk ahbsi ahbso apbi apbo 4 aramo stati cerror 0 lt aramo ce SDRAM controller sde ftsdctrl generic map hindex gt 3 haddr gt 16 600 hmask gt 16 FOO ioaddr gt 1 fast gt 0 pwron gt 1 invclk gt 0 edacen gt 1 errcnt gt 1 cntbits gt 4 54 port map rstn clk ahbsi stati cerror 1 lt sdo ce Memory controller mctrlO ftsrctrl generic map ahbso 3 rmw gt 1 sdi sdo pindex gt 10 edacen gt 1 errcnt gt 1 cntbits gt 4 port map rstn clk ahbsi stati cerror 2 lt memo ce end ahbso 0 apbi apbo 10 paddr gt 10 memi memo sdo2 10 10 1 10 2 55 AHBTRACE AHB Trace buffer Overview The trace buffer consists of a circular buffer that stores AMBA AHB data transfers The address data and various control signals of the AHB bus are stored and can be read out for later analysis AHB Trace Buffer Trace control Trace buffer RAM y t AHB slave interface IRQ AMBA AHB Figure 9 Block diagram The trace buffer is 128 bits wide the information stored is indicated in the table below Table 45 AHB Trace buffer
18. Signal name Field Type Function Active RSTN N A Input Reset Low RSTOUTN N A Output Reset from BRM core Low CLK N A Input System clock AHB BRM_CLK1 N A Input BRM clock 1 BRM_CLK2 N A Input BRM clock 1 TCLK N A Input External time base B15531 Input 1553 bus input signals busainp Positive data input from the A receiver High busainn Negative data input from the A receiver Low busbinp Positive data to the B receiver High busbinn Negative data to the B receiver Low B15530 Output 1553 bus output signals busainen Enable for the A receiver High busaoutin Inhibit for the A transmitter High busaoutp Positive data to the A transmitter High busaoutn Negative data to the A transmitter Low busbinen Enable for the B receiver High busboutin Inhibit for the B transmitter High busboutp Positive output to the B transmitter High busboutn Negative output to the B transmitter Low BRMI Input BRM input signals cmdok Command word validation alright High BRMO Output BRM output signals msgstart Message process started High cmdsync Start of command word on bus High syncnow Synchronize received High busreset Reset command received High opmode Operating mode cmdval Active command cmdokout Command word validated High cmdstb Active command value changed High APBI Input APB slave input signals APBO Output APB slave output signals AHBI A Input AMB master input signals AHBO Output AHB master output signals see GRLI
19. 149 11b system clock SCALER 1 8 SILENT Listen only to the CAN bus send recessive bits 3 SELECTIONSelection receiver input and transmitter output Select receive input 0 as active when 0b Select receive input 1 as active when 1b Select transmit output 0 as active when Ob Select transmit output 1 as active when 1b 2 ENABLE Set value of output 1 enable T ENABLEO Set value of output 0 enable O ABORT Abort transfer on AHB ERROR All bits are cleared to 0 at reset Note that constraints on PS1 PS2 and RSJ are defined as e PS1 1 gt PS2 e PS1 gt PS2 e PS2 gt RSJ Note that CAN standard TSEG1 is defined by PS1 1 Note that CAN standard TSEG2 is defined by PS2 Note that the SCALER setting defines the CAN time quantum together with the BPR setting system clock SCALER 1 BPR where SCALER is in range 0 to 255 and the resulting division factor due to BPR is 1 2 4 or 8 Note that the resulting bit rate is system clock SCALER 1 BPR 1 PS1 1 PS2 where PS1 is in the range 1 to 15 and PS2 is in the range 2 to 8 Note that RSJ defines the number of allowed re synchronization jumps according to the CAN stan dard being in the range 1 to 4 Note that the transmit or receive channel active during the AMBA AHB error is disabled if the ABORT bit is set to 1b Note that all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs while the ABORT bit is set to 1b The accesses wi
20. Figure 106 16 bit I O non sequential write access with 0 wait states Figure 107 16 bit I O non sequential read access with 0 wait states VO write accesses is extended with one extra latency cycle if bus exception is enabled If waitstates are configured through the VHDL generics or registers one extra data cycle will be inserted for each waitstate in both read and write cycles 30 4 Registers 241 The core is programmed through registers mapped into APB address space Table 221 FT SRAM IO controller registers APB Address offset Register 0x0 Memory configuration register 1 0x4 Memory configuration register 2 0x8 Memory configuration register 3 Table 222 MCFG1 register 31 27 26 25 24 23 20 19 0 RESERVED BRDY BEXC IOWS RESERVED 31 27 RESERVED 26 BRDYEN Enables the BRDYN signal 25 BEXCEN Enables the BEXCN signal 24 RESERVED 23 20 IOWS Sets the number of waitstates for accesses to the IO area Only available if the wsreg VHDL generic is set to one 19 0 RESERVED Table 223 MCFG2 register 31 13 12 9 8 2 1 0 RESERVED RAMBSZ RESERVED RAMWS 31 12 RESERVED 12 9 RAMBSZ Sets the SRAM bank size Only available if the banksz VHDL generic is set to zero Oth erwise the banksz VHDL generic sets the bank size 0 8 kB 15 256 MB RESERVED RAMWS Sets the number of waitstates for accesses to the RAM ar
21. get Master unit see GRLIB IP Library User s Manual 51 7 Library dependencies Table 437 shows libraries used when instantiating the core VHDL libraries Table 437 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER PCI Component Component declaration 51 8 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler pci all use gaisler pads all signal pcii pci_in_type signal pcio pci_out_type dma pcidma generic map memtech gt memtech dmstndx gt 1 dapbndx gt 5 dapbaddr gt 5 blength gt blength mstndx gt 0 fifodepth gt log2 fifodepth device_id gt CFG_PCIDID vendor_id gt CFG_PCIVID slvndx gt 4 apbndx gt 4 apbaddr gt 4 haddr gt 16 E00 ioaddr gt 16 800 nsync gt 1 port map rstn clkm pciclk pcii pcio apbo 5 ahbmo 1 apbi apbo 4 ahbmi ahbmo 0 ahbsi ahbso 4 pcipadsO pcipads generic map padtech gt padtech port map pci_rst pci_gnt pci_idsel pci_lock pci_ad pci_cbe pci_frame pci_irdy pci_trdy pci_devsel pci_stop pci_perr pci_par pci_req pci_serr pci_host pci_66 pcii pcio 441 442 52 52 1 52 2 52 3 PCITARGET Simple 32 bit PCI target with AHB interface
22. Figure 222 SDRAM Memory controller conected to AMBA bus and SDRAM Operation 55 2 1 General Synchronous dynamic RAM SDRAM access is supported to two banks of PC100 PC133 compati ble devices The controller supports 64M 256M and 512M device with 8 12 column address bits up to 13 row address bits and 4 banks The size of each of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte The operation of the SDRAM controller is controlled through the configuration register SDCFG see section 55 3 SDRAM banks data bus width is configurable between 32 and 64 bits 55 2 2 Initialization When the SDRAM controller is enabled it automatically performs the SDRAM initialization sequence of PRECHARGE 8x AUTO REFRESH and LOAD MODE REG on both banks simulta neously The controller programs the SDRAM to use page burst on read and single location access on write If the pwron VHDL generic is 1 the initialization sequence is also sent automatically when reset is released Note that some SDRAM require a stable clock of 100 us before any commands might be sent When using on chip PLL this might not always be the case and the pwron VHDL generic should be set to 0 in such cases 55 2 3 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices and at different frequencies three SDRAM parameters can be programmed through memory configuration register 2 MCFG2 TCAS TRP and TRECD
23. The main functionality consists of the DMA channels which are used to transfer data between an AHB bus and an Ethernet network There is one transmitter DMA channel and one Receiver DMA channel The operation of the DMA channels is controlled through registers accessible through the APB interface The MDIO interface is used for accessing configuration and status registers in one or more PHYs con nected to the MAC The operation of this interface is also controlled through the APB interface The optional EDCL provides read and write access to an AHB bus through Ethernet It uses the UDP IP ARP protocols together with a custom application layer protocol to accomplish this The EDCL contains no user accessible registers and always runs in parallel with the DMA channels 272 34 3 The Media Independent Interface MID is used for communicating with the PHY There is an Ethernet transmitter which sends all data from the AHB domain on the Ethernet using the MII interface Corre spondingly there is an Ethernet receiver which stores all data from the Ethernet on the AHB bus Both of these interfaces use FIFOs when transferring the data streams The GRETH also supports the RMII which uses a subset of the MII signals The EDCL and the DMA channels share the Ethernet receiver and transmitter 34 2 2 Protocol support The GRETH is implemented according to IEEE standard 802 3 2002 There is no support for the optional control sublayer and no mul
24. 1 Link Start LS Start the link i e allow a transition from ready to started state Reset value PRS 2 Autostart AS Automatically start the link when a NULL has been received Not reset 3 Interrupt Enable IE If set an interrupt is generated when one of bit 8 to 10 is set and its corresponding event occurs Reset value 0 4 Tick In TI The host can generate a tick by writing a one to this field This will increment the timer counter and the new value is transmitted after the current character is transferred A tick can also be generated by asserting the tick_in signal Reset value 0 5 Promiscuous Mode PM Enable Promiscuous mode Reset value 0 6 Reset RS Make complete reset of the SpaceWire node Self clearing Reset value 0 8 Tick out IRQ TQ Generate interrupt when a valid time code is received Not reset 9 Link error IRQ LI Generate interrupt when a link error occurs Not reset 10 Time Tx Enable TT Enable time code transmissions Reset value 0 11 Time Rx Enable TR Enable time code receptions Reset value 0 16 RMAP Enable RE Enable RMAP command handler Only available if rmap VHDL generic is set to 1 Reset value 1 17 RMAP buffer disable RD If set only one RMAP buffer is used This ensures that all RMAP commands will be executed consecutively Reset value 0 29 RMAP CRC available Set to one if RMAP CRC is enabled i
25. 20 19 FT scheme 00 no FT 01 4 bit checking implemented 16 Instruction burst fetch IB This bit enables burst fill during instruction fetch 15 Instruction cache flush pending IP This bit is set when an instruction cache flush operation is in progress 14 Data cache flush pending DP This bit is set when an data cache flush operation is in progress 13 12 Instruction Tag Errors ITE Number of detected parity errors in the instruction tag cache 11 10 Instruction Data Errors IDE Number of detected parity errors in the instruction data cache 9 8 Data Tag Errors DTE Number of detected parity errors in the data tag cache 7 6 Data Data Errors IDE Number of detected parity errors in the data data cache 5 Data Cache Freeze on Interrupt DF If set the data cache will automatically be frozen when an asynchronous interrupt is taken 4 Instruction Cache Freeze on Interrupt IF If set the instruction cache will automatically be frozen when an asynchronous interrupt is taken 3 2 Data Cache state DCS Indicates the current data cache state according to the following X0 disabled 01 frozen 11 enabled 1 0 Instruction Cache state ICS Indicates the current data cache state according to the following X0 disabled 01 frozen 11 enabled 395 45 4 DSU memory map The FPU register file check bits can be accessed at address 0x301800 0x30187C
26. Bit 3 0 Always 0 133 RX identifier 2 EFF frame Table 140 RX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 20 ID 19 ID 18 1D 17 ID 16 ID 15 ID 14 1D 13 Bit 7 0 Bit 20 downto 13 of 29 bit EFF identifier RX identifier 3 EFF frame Table 141 RX identifier 3 address 19 Bit7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 12 ID 11 ID 10 ID 9 ID 8 ID 7 ID 6 ID 5 Bit 7 0 Bit 12 downto 5 of 29 bit EFF identifier RX identifier 4 EFF frame Table 142 RX identifier 4 address 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 4 ID 3 ID 2 ID 1 ID 0 RTR 0 0 Bit 7 3 Bit 4 downto 0 of 29 bit EFF identifier Bit 2 1 if RTR frame Bit 1 0 Don t care Data field For received SFF frames the data field is located at address 19 to 26 and for EFF frames at 21 to 28 21 5 14 Acceptance filter The acceptance filter can be used to filter out messages not meeting certain demands If a message is filtered out it will not be put into the receive fifo and the CPU will not have to deal with it There are two different filtering modes single and dual filter Which one is used is controlled by bit 3 in the mode register In single filter mode only one 4 byte filter is used In dual filter two smaller fil ters are used and if either of these signals a match the message is accepted Each fi
27. DPD 0 o RESERVED RESERVED 0 0 PER 0 MIE 0 BM MS 0 Figure 203 Status amp Command register 31 16 Status Register Writing one to a bit 31 16 clears the bit Writes can not set a bit 31 Detected parity Error DPE 30 Signalled System Error SSE Not implemented Always reads 0 29 Received Master Abort RMA Set by the PCI Master interface when its transaction is terminated with Master Abort 28 Received Target Abort RTA Set by the PCI Master interface when its transaction is terminated with Target Abort 27 Signalled Target Abort STA Set by the PCI Target Interface when the target terminates transaction with Target Abort 26 25 DEVSEL timing DST Always reads 10 medium DEVSEL timing 24 Data Parity Error Detected DPD 23 Fast Back to Back Capable The Target interface is not capable of fast back to back transactions Always reads 0 22 UDF Supported Not supported Always reads 0 21 66 Mhz Capable Not supported Always reads 0 20 16 Reserved Always reads 00 0 15 0 Command Register Writing one to a bit 15 0 sets the bit Writing zero clears the bit 15 10 Reserved Always reads as 00 0 9 Fast back to Back Enable Not implemented Always reads 0 8 SERR enable No
28. cacheability information interrupt bus configuration information diagnostic information e AMBA APB slave interface with sideband signals as per GRLIB including interrupt bus configuration information diagnostic information 22 1 3 Hierarchy The CAN controller core can be partition in the following hierarchical elements e CAN 2 0 Core e Redundancy Multiplexer De multiplexer e Direct Memory Access controller e AMBA APB slave e AMBA AHB master Interface The external interface towards the CAN bus features two redundant pairs of transmit output and receive input i e O and 1 The active pair i e O or 1 is bselectable by means of a configuration register bit Note that all recep tion and transmission is made over the active pair For each pair there is one enable output i e O and 1 each being individually programmable Note that the enable outputs can be used for enabling an external physical driver Note that both pairs can be enabled simultaneously Note that the polarity for the enable inhibit inputs on physical interface drivers differs thus the meaning of the enable output is undefined Redundancy is implemented by means of Selective Bus Access as specified in CANWG Note that the active pair selection above provides means to meet this requirement Protocol The CAN protocol is based on a CAN 2 0 controller VHDL core The CAN controller complies with CANSTD except for the overload fr
29. end generate 1 0 pads driving checkbit signals cbh_pad iopadv generic map width gt 8 port map pad gt cb o gt memi cb en gt memo bdrive 0 i gt memo cb connect memory controller outputs to entity output signals address lt memo address ramsn lt memo ramsn romsn lt memo romsn oen lt memo oen rwen lt memo wrn ramoen lt memo ramoen writen lt memo writen read lt memo read iosn lt memo iosn sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm end 235 236 30 30 1 30 2 FTSRCTRLS8 8 bit SRAM 16 bit IO Memory Controller with EDAC Overview The fault tolerant 8 bit SRAM 16 bit I O memory interface uses a common 16 bit data bus to inter face 8 bit SRAM and 16 bit I O devices It provides an Error Detection And Correction unit EDAC correcting up to two errors and detecting up to four errors in a data byte The EDAC eight checkbits are stored in parallel with the 8 bit data in SRAM memory Configuration of the memory controller functions is performed through the APB bus interface SRO RAMSN SRO OEN SRO WRITEN MEMORY CONTROLLER SRO IOSN SRI A 27 0 SRI D 15 0 SRO D 15 0 AHB APB gt P Bridge Figure 101 Block diagram Operation The controller is configured through VHDL generics to decode two address ranges SRAM and I O area By defaul
30. 479 58 7 Library dependencies Below is a table with the required libraries that should be used when instantiating the VGA controller hardware TABLE 466 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration 58 8 Component instantiation library grlib use grlib amba all library Gaisler 27 use gaiser misc all architecture rtl of test is signal apbi apb_slv_in_type signal apbo apb_slv_out signal vgao apbvga_out_type signal ahbi ahb_mst_in_type signal ahbo ahb_mst_out_type signal clk_sel std_logic_vector 1 downto 0 signal clkmvga std_logic begin VGA Controller vga0 svgactrl generic map memtech gt memtech pindex gt 6 paddr gt 6 hindex gt 6 clk0 gt 40000 clk1 gt 20000 c1k2 gt 15385 clk3 gt 0 port map rstn clkm clkmvga apbi apbo 6 vgao ahbmi ahbmo 6 cl1k_sel end 58 9 Linux 2 6 command line options A video driver for SVGACTRL is provided Snapgear Linux p27 and later The proper kernel com mand line options must be used for the driver to detect the SVGACTRL core The table below lists the boot options and the order they should appear in 480 TABLE 467 Linux 2 6 kernel options Order Value Custom All Description 0 video grvga N A Needed to selec
31. A frame larger than the maximum size was received The excessive part was truncated 16 CRC Error CE A CRC error was detected in this frame 17 Overrun Error OE The frame was incorrectly received due to a FIFO overrun 18 Length Error LE The length field does not correspond to the number of bytes received 19 IP Detected ID IP packet detected 20 IP Error IR IP checksum error detected 21 UDP Detected UD UDP packet detected 22 UDP Error UR UDP checksum error detected 23 TCP Detected TD TCP packet detected 24 TCP Error TR TCP checksum error detected 31 0 Address Pointer to the buffer area from where the packet data will be loaded Figure 124 Receive descriptor Memory offsets are shown in the left margin 35 5 289 35 4 2 Starting reception Enabling a descriptor is not enough to start reception A pointer to the memory area holding the descriptors must first be set in the GRETH_GBIT This is done in the receiver descriptor pointer reg ister The address must be aligned to a 1 kB boundary Bits 31 to 10 hold the base address of descrip tor area while bits 9 to 3 form a pointer to an individual descriptor The first descriptor should be located at the base address and when it has been used by the GRETH_GBIT the pointer field is incre mented by 8 to point at the next descriptor The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached the des
32. Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 haddr ADDR filed of the AHB BARO defining SDRAM area 0 16 FFF 16 000 Default is OxFO000000 OXFFFFFFFF hmask MASK filed of the AHB BARO defining SDRAM area 0 16 FFF 16 FOO ioaddr ADDR filed of the AHB BARI defining I O address 0 16 FFFH 16 000 space where SDCFG register is mapped iomask MASK filed of the AHB BAR defining I O address 0 16 FFFH 16 FFFH space wprot Write protection 0 1 0 invelk Inverted clock is used for the SDRAM 0 1 0 fast Enable fast SDRAM address decoding 0 1 0 pwron Enable SDRAM at power on 0 1 0 sdbits 32 or 64 bit data bus width 32 64 32 edacen EDAC enable If set to one EDAC logic will be included 0 1 0 in the synthesized design An EDAC configuration regis ter will also be available errcnt Include an single error counter which is accessible from 0 1 0 the EDAC configuration register entbits Number of bits used in the single error counter 1 8 1 216 28 6 28 7 28 8 Signal descriptions Table 212 shows the interface signals of the core VHDL ports Table 212 Signals declarations Signal name Field Type Function Active CLK N A Input Clock RST N A Input Reset Low AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals SDI WPROT Input Not used DATA 63 0 Input Data CB 7 0
33. Note this manual describes the full functionality of the LEON3 core Through the use of VHDL generics parts of the described functionality can be suppressed or modified to generate a smaller or faster implementation 44 1 1 Integer unit The LEON3 integer unit implements the full SPARC V8 standard including hardware multiply and divide instructions The number of register windows is configurable within the limit of the SPARC standard 2 32 with a default setting of 8 The pipeline consists of 7 stages with a separate instruc tion and data cache interface Harvard architecture 44 1 2 Cache sub system LEON3 has a highly configurable cache system consisting of a separate instruction and data cache Both caches can be configured with 1 4 sets 1 256 kbyte set 16 or 32 bytes per line Sub blocking is implemented with one valid bit per 32 bit word The instruction cache uses streaming during line refill to minimize refill latency The data cache uses write through policy and implements a double word write buffer The data cache can also perform bus snooping on the AHB bus A local scratch pad ram can be added to both the instruction and data cache controllers to allow 0 waitstates access memory without data write back 370 44 1 3 Floating point unit and co processor The LEON3 integer unit provides interfaces for a floating point unit FPU and a custom co proces sor Two FPU controllers are available one for the high performa
34. The DMA control register contains a bit called Abort TX which if set causes the current transmission to be aborted the packet is truncated and an EEP is inserted This is only useful if the packet needs to be aborted because of congestion on the SpaceWire network If the congestion is on the AHB bus this will not help This should not be a problem since AHB slaves should have a maximum of 16 wait states The aborted packet will have its LE bit set in the descriptor The transmit enable register bit is also cleared and no new transmissions will be done until the transmitter is enabled again When an AHB error is encountered during transmission the currently active DMA channel is dis abled the packet is truncated and an EEP is inserted if the transmission has started and the transmit ter goes to the idle mode A bit in the DMA channel s control status register is set to indicate this error condition The client using the channel has to correct the error and enable the channel again RMAP The Remote Memory Access Protocol RMAP is used to implement access to resources in the node via the Space Wire Link Some common operations are reading and writing to memory registers and FIFOs The GRSPW has an optional hardware RMAP command handler which is enabled with a VHDL generic This section describes the basics of the RMAP protocol and the command handler implementation 42 6 1 Fundamentals of the protocol RMAP is a protocol which is designed
35. The receiver detects connections from other nodes and receives characters as a bit stream on the data and strobe signals It is also located in a separate clock domain which runs on a clock generated from the received data and strobe signals More information on the clock generation can be found in sec tion 42 8 1 The receiver is activated as soon as the link interface leaves the error reset state Then after a NULL is received it can start receiving any characters It detects parity escape and credit errors which causes the link interface to enter the error reset state Disconnections are handled in the link interface part in the system clock domain because no receiver clock is available when disconnected Received Characters are flagged to the host domain and the data is presented in parallel form The interface to the host domain is shown in figure 140 L Chars are the handled automatically by the host domain link interface part while all N Chars are stored in the receiver FIFO for further handling If two or more consecutive EOPs EEPs are received all but the first are discarded There are no signals going directly from the transmitter clock domain to the receiver clock domain and vice versa All the synchronization is done to the system clock D P gt Got Time code gt gt Got FCT i Got EOP Receiver CEEP s gt Got Nehar o gt p gt Time code 7 0 gt NChar 7 0 Receiver Clock Domain Host Clo
36. architecture rtl of ssrctrl_ex is Clock generator component component clkgen_m1401 generic clk_mul integer 1 clk_div integer 1 freq integer 100000 clock frequency in KHz port clkin in std_logic clk out std_logic main clock ddrclk out std_logic DDR clock ddrclkfb in std_logic DDR clock feedback ddrcl1k90 out std_logic DDR 90 clock ddrc1k180 out std_logic 180 clock ddrc1k270 out std_logic DDR clock ssrclk out std_logic SSRAM clock ssrclkfb in std_logic SSRAM clock feedback cgi in clkgen_in_type cgo out clkgen_out_type end component signals used to connect memory controller and memory bus signal memi memory_in_type signal memo memory_out_type AMBA bus AHB and APB signal apbi signal apbo apb_slv_out_vector others gt apb_none apb_slv_in_type signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in type signal ahbmo ahb_mst_out_vector others gt ahbm_none Signals used by clock and reset generators signal clkm rstn rstraw srclkl std_ulogic signal cgi clkgen_in_type signal cgo clkgen_out_type signal ddrclkfb ssrclkfb ddr_clkl ddr_clknl std_ulogic begin clkgen0 clkgen_m1401 clock generator port map sys_clk clkm ddr_clkl ddrclkfb open ddr_clknl sram_clk_fb cgi cgo rst0 rstgen reset generator
37. field contains the number of bytes to be read or written If R W is one the data field shown in Table 305 contains the data to be written If R W is zero the data field is empty in the received packets Table 307 shows the application layer fields of the replies from the EDCL The length field is always zero for replies to write requests For read requests it contains the number of bytes of data contained in the data field Table 307 The EDCL application layer fields in transmitted frames 16 bit Offset 14 bit sequence number 1 bit ACK NAK 10 bit Length 7 bit Unused The EDCL implements a Go Back N algorithm providing reliable transfers The 14 bit sequence number in received packets are checked against an internal counter for a match If they do not match no operation is performed and the ACK NAK field is set to 1 in the reply frame The reply frame con tains the internal counter value in the sequence number field If the sequence number matches the operation is performed the internal counter is incremented the internal counter value is stored in the sequence number field and the ACK NAK field is set to 0 in the reply The length field is always set to 0 for ACK NAK 1 frames The unused field is not checked and is copied to the reply It can thus be set to hold for example some extra id bits if needed Media Independent Interfaces There are several interfaces defined between the MAC sublayer and the Physical layer Th
38. generate a burst of two 16 bits reads During writes only the necessary bytes will be writen Figure 194 shows an interface example with 8 bit PROM and 8 bit SRAM Figure 195 shows an example of a 16 bit memory interface 8 bit PROM MEMO ROMSN 0 cs MEMOOEN gk MEMO WRITEN Jw MEMORY CONTROLLER MEMO RAMSN 0 MEML A 27 0 MEMI D 31 24 MEMO D 31 24 Figure 194 8 bit memory interface example 16 bit PROM MEMO ROMSN 0 cs MEMO OEN Jork MEMO WRITEN dre MEMORY CONTROLLER MEMO RAMSN 0 MEML A 27 0 MEMI D 31 16 MEMO D 31 16 Figure 195 16 bit memory interface example 47 6 Burst cycles To improve the bandwidth of the memory bus accesses to consecutive addresses can be performed in burst mode Burst transfers will be generated when the memory controller is accessed using an AHB burst request These includes instruction cache line fills double loads and double stores The timing of a burst cycle is identical to the programmed basic cycle with the exception that during read cycles the lead out cycle will only occurs after the last transfer 410 47 7 47 8 47 9 8 and 16 bit I O access Similar to the PROM RAM areas the I O area can also be configured to 8 or 16 bit mode However the I O device will NOT be accessed by multiple 8 16 bit accesses as the memory areas but only with one single access just as in 32 bit mode To access an I O device on a 16 bit bus LDUH STH instr
39. sig begin nal ahbmo ahb_mst_out_vector others gt ahbm_none AMBA Components are instantiated here el g port rs cl ah ah ap ap et et i end GRETH greth_gbit eneric map hindex pindex paddr pirg memtech mdcscaler burstlength nsync edcl edclbufsz macaddrh macaddrl ipaddrh ipaddrl map E k bmi bmo bi bo hi ho gt 0 gt 12 gt 12 gt 12 gt inferred gt 50 gt 32 gt 1 gt 1 gt 8 gt 16 00005E gt 16 00005D gt 16 c0a8 gt 16400354 gt rstn gt clk gt ahbmi gt ahbmo 0 gt apbi gt apbo 12 gt ethi gt etho 297 298 36 36 1 36 2 ETH_ARB Ethernet PHY arbiter Overview The Ethernet PHY arbiter provides access to a single physical Ethernet medium for two Media Access Controllers MACs It handles both half and full duplex modes The MACs are connected to sepa rate MII interfaces which the ETH_ARB the arbitrates to a single MII interface A block diagram is shown in figure 133 A Ethernet Medium PHY Mi ETH_ARB TE MAC MAC Figure 133 Ethernet PHY arbiter block diagram Operation 36 2 1 Arbitration method The ETH_ARB provides two MII interfaces to which Ethernet MACs can be connected These inter faces are identical to the one provided directly from a PHY There are two different arbitration a
40. 31 30 29 27 26 17 16 15 14 13 11 10 TZ 1 0 FPFT FCNT RESERVED D1 TUFT ICNT TB 7 0 DP TE mi Figure 174 asr16 Register protection control register 31 30 FP FT ID Defines which SEU protection is implemented in the FPU table 405 29 27 FP RF error counter Number of detected parity errors in the FP register file 26 17 Reserved 16 FP RF protection disable FDI Disables FP RF parity protection when set 15 14 IU FT ID Defines which SEU protection is implemented in the IU table 405 13 11 TURF error counter Number of detected parity errors in the IU register file 10 3 RF Test bits FTB In test mode these bits are xored with correct parity bits before written to the register file 2 DP ram select DP Only applicable if the IU or FPU register files consists of two dual port rams See text below for details 1 IU RF Test Enable Enables register file test mode Parity bits are xored with TB before written to the resgiter file 0 IU RF protection disable IDI Disables IU RF parity protection when set 45 2 4 IU register file error injection The SEU protection feature can be tested by inserting errors into the checkbits When the RF Test Enable bit asr16 1 is 1 the checkbits will be XORed with the RF Test bits before written to the register file If the IU and or FPU register files are implemented with dual port RAM then the DP bit defines which of
41. 388 44 11 Configuration options Table 402 shows the configuration options of the core VHDL generics Table 402 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 fabtech Target technology 0 NTECH 0 inferred memtech Vendor library for regfile and cache RAMs 0 NTECH 0 inferred nwindows Number of SPARC register windows Choose 8 windows to be 2 32 8 compatible with Bare C and RTEMS cross compilers dsu Enable Debug Support Unit interface 0 1 fpu Floating point Unit 0 15 0 no FPU 1 7 GRFPU 1 inferred multiplier 2 DW multiplier 3 Mod ule Generator multiplier 8 14 GRFPU Lite 8 simple FPC 9 data forwarding FPC 10 non blocking FPC 15 Meiko v8 Generate SPARC V8 MUL and DIV instructions 0 2 0 cp Generate co processor interface 0 1 0 mac Generate SPARC V8e SMAC UMAC instruction 0 1 0 pclow Least significant bit of PC Program Counter that is actually 0 2 2 generated PC 1 0 are always zero and are normally not gener ated Generating PC 1 0 makes VHDL debugging easier notag Currently not used nwp Number of watchpoints 0 4 0 icen Enable instruction cache 0 1 1 irepl Instruction cache replacement policy 0 1 0 0 least recently used LRU 1 least recently replaced LRR 2 random isets Number of instruction cache sets 1 4 1 ilinesize Instruction c
42. 48 48 1 48 2 48 3 421 MUL32 Signed unsigned 32x32 multiplier module Overview The multiplier module is highly configurable module implementing 32x32 bit multiplier Multiplier takes two signed or unsigned numbers as input and produces 64 bit result Multiplication latency and hardware complexity depend on multiplier configuration Variety of configuration option makes it possible to configure the multiplier to meet wide range of requirements on complexity and perfor mance For DSP applications the module can be configured to perform multiply amp accumulate MAC opera tion In this configuration 16x16 multiplication is performed and the 32 bit result is added to 40 bit value accumulator Operation The multiplication is started when 1 is samples on MULI START on positive clock edge Operands are latched externally and provided on inputs MULI OP1 and MULLOP2 during the whole operation The result appears on the outputs during the clock cycle following the clock cycle when MULO READY is asserted if multiplier if 16x16 32x8 or 32x16 configuration is used For 32x32 configuration result appears on the output during the second clock cycle after the MULI START was asserted Signal MULI MAC shall be asserted to start multiply amp accumulate MAC operation This signal is latched on positive clock edge Multiplication is performed between two 16 bit values on inputs MULLOP1 15 0 and MULIOP2 15 0 The 32 bit result of the
43. AHBO Output AHB master output signals see GRLIB IP Library User s Manual Library dependencies Table 53 shows libraries used when instantiating the core VHDL libraries Table 53 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER UART Signals component Signals and component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all 62 library grlib use grlib amba all library gaisler use gaisler uart all entity ahbuart_ex is port clk in std _ultogic rstn in std_ulogic UART signals ahbrxd in std ulogic ahbtxd out std_ulogic i end architecture rtl of ahbuart_ex is AMBA signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none UART signals signal ahbuarti uart_in_type signal ahbuarto uart_out_type begin AMBA Components are instantiated here AHB UART ahbuart0 ahbuart generic map hindex gt 5 pindex gt 7 paddr gt 7 port map rstn clk ahbuarti ahbuarto apbi apbo 7 AHB UART input data ahbuarti rxd lt ahbrxd connect AHB UART output to entity output signal ahbtxd lt ahbuarto txd end ah
44. CMR 6 reserved CMR 5 reserved CMR 4 Self reception request Transmits and simultaneously receives a message CMR 3 Clear data overrun Clears the data overrun status bit CMR 2 Release receive buffer Free the current receive buffer for new reception CMR 1 Abort transmission Aborts a not yet started transmission CMR 0 Transmission request Starts the transfer of the message in the TX buffer A transmission is started by writing 1 to CMRO O It can only be aborted by writing 1 to CMR 1 and only if the transfer has not yet started Setting CMR 0 and CMR 1 simultaneously will result in a so called single shot transfer 1 e the core will not try to retransmit the message if not successful the first time Giving the Release receive buffer command should be done after reading the contents of the receive buffer in order to release this memory If there is another message waiting in the FIFO a new receive interrupt will be generated if enabled and the receive buffer status bit will be set again The Self reception request bit together with the self test mode makes it possible to do a self test of the core without any other cores on the bus A message will simultaneously be transmitted and received and both receive and transmit interrupt will be generated 127 21 5 4 Status register The status register is read only and reflects the current status of the core Table 122 Bit interpretation of command register SR address 2
45. D1 D2 D3 Dn 2 Dn 1 EOP Figure 138 The SpaceWire packet with protocol ID that is expected by the GRSPW Link interface The link interface handles the communication on the SpaceWire network and consists of a transmitter receiver a FSM and FIFO interfaces An overview of the architecture is found in figure 137 42 3 1 Link interface FSM The FSM controls the link interface a more detailed description is found in the SpaceWire standard The low level protocol handling the signal and character level of the SpaceWire standard is handled by the transmitter and receiver while the FSM in the host domain handles the exchange level The link interface FSM is controlled through the control register The link can be disabled through the link disable bit which depending on the current state either prevents the link interface from reaching the started state or forces it to the error reset state When the link is not disabled the link interface FSM is allowed to enter the started state when either the link start bit is set or when a NULL character has been received and the autostart bit is set The current state of the link interface determines which type of characters are allowed to be transmit ted which together with the requests made from the host interfaces determine what character will be sent Time codes are sent when the FSM is in the run state and a request is made through the time interface
46. OXFFF 0x000 space hmask MASK filed of the AHB BARO defining the address 0 OXFFF OxFFO space pirq Index of the interrupt line 0 NAHBIRQ 1 0 TWIDTH Timing counter width PIO_mode0_T1 Reset value for T1 6 PIO_mode0_T2 Reset value for T2 28 PIO_mode0_T4 Reset value for T4 2 PIO_mode0_Teoc Reset value for Teoc 23 The default values for PIO_mode0_ are calculated for a 100 MHz clock 98 17 6 17 7 17 8 Signal descriptions Table 95 shows the interface signals of the core VHDL ports Table 95 Signal descriptions Signal name Field Type Function Active rst Input Synchronous reset signal Low arst Input Asynchronous reset signal Low clk Input Clock signal AHBMI Input AHB master input signals AHBMO 7 Output AHB master output signals ata_resetn Output Reset signal to ATA device Low ddin 15 0 Input Data Input ddout 15 0 Output Data Output ddoe Output Data output enable High da 2 0 Output Device address csOn Output Chip Select 0 Low csin Output Chip Select 1 Low diorn Output Device IO read Low diown Output Device IO write Low iordy Input IO channel ready intrq Input Device interrupt dmack Output DMA ACK signal Always set to 1 cfo atasel Output Select True IDE mode for CompactFlash csel Output Device Master select signal da 10 3 Output Grounded address signals power Output Power switch
47. Only readable Rx Descriptors Available RD Set to one to indicate to the GRSPW that there are enabled descriptors in the descriptor table Cleared by the GRSPW when it encounters a disabled descriptor Reset value 0 No Spill NS If cleared packets will be discarded when a packet is arriving and there are no active descriptors If set the GRSPW will wait for a descriptor to be activated Figure 151 GRSPW DMA channel control status register 24 0 RX MAXIMUM LENGTH 31 24 0 Receiver packet maximum length in bytes Only bits 24 2 are writable Bits 1 0 are always 0 Not reset Figure 152 GRSPW DMA channel receiver max length register 10 9 43 0 TRANSMITTER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR SELECT RES 3 0 9 4 31 10 Reserved Descriptor selector Offset into the descriptor table Shows which descriptor is currently used by the GRSPW For each new descriptor read the selector will increase with 16 and eventually wrap to zero again Reset value 0 Descriptor table base address Sets the base address of the descriptor table Not reset Figure 153 GRSPW transmitter descriptor table address register 339 340 31 10 32 0 RECEIVER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR SELECT RES 31 10 Reserved Descriptor Selector Offset into the descriptor table Shows which descriptor is currently used by the GRSPW For each new
48. Overview This core implements PCI interface with a simple target only interface The interface is developed primarily to support DSU communication over the PCI bus Focus has been put on small area and robust operation rather than performance The interface has no FIFOs limiting the transfer rate to about 5 Mbyte s This is however fully sufficient to allow fast download and debugging using the DSU AMBA AHB PCI Bus AHB Master AHB PCI Interface gt Target Figure 218 Target only PCI interface Registers The core implements one PCI memory BAR 31 abits 1 abits 2 0 AHB address 31 abits 1 UNUSED Figure 219 AHB address register BARO 0x 100000 The interface consist of one PCI memory BAR occupying 2 abits bytes default 2 Mbyte of the PCI address space and an AHB address register Any access to the lower half of the address space def 0 OXFFFFF will be forwarded to the internal AHB bus The AHB address will be formed by concatenating the AHB address filed of AHB address register with the LSB bits of the PCI address An access to the upper half of the address space default 1 Mbyte on 0x100000 0x1 FFFFF of the BAR will read or write the AHB address register Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x012 For description of vendor and device identifies see GRLIB IP Library User s Manual 52 4 52 5 5
49. READ Output Read strobe High RAMN Output Common SRAM Chip Select Always asserted Low when one of the 8 RAMSN signals is asserted ROMN Output Common PROM Chip Select Always asserted Low when one of the 8 ROMSN signals is asserted SA 14 0 Output Not used CB 7 0 Output Checkbits PSEL Output Not used CE Output Single error detected High AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals SDO SDCASN Output Not used All signals are drive to inactive state Low see GRLIB IP Library User s Manual 232 29 8 29 9 29 10 Library dependencies Table 220 shows libraries used when instantiating the core VHDL libraries Table 220 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Component declaration The core has the following component declaration component ftsrctrl is generic hindex romaddr rommask ramaddr rammask ioaddr iomask ramws romws iows rmw srbanks banksz rombanks rombanksz rombankszdef pindex paddr pmask edacen errcnt entbits wsreg oepol prom8en port i end rst clk ahbsi ahbso apbi apbo srl sro sdo component Instantiation This example shows how the core can be instantiated integer integer integer integer integer integer i
50. Registers 10 3 1 Register address map The trace buffer occupies 128 kbyte address space in the AHB I O area The following register address are decoded Table 46 Trace buffer address space Address Register 0x000000 Trace buffer control register 0x000004 Trace buffer index register 0x000008 Time tag counter 0x000010 AHB break address 1 0x000014 AHB mask 1 0x000018 AHB break address 2 0x00001C AHB mask 2 0x010000 0x020000 Trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 wl Trace bits 31 0 10 3 2 Trace buffer control register The trace buffer is controlled by the trace buffer control register 31 16 1 0 DCNT RESERVED DMEN Figure 10 Trace buffer control register O Trace enable EN Enables the trace buffer 1 Delay counter mode DM Indicates that the trace buffer is in delay counter mode 31 16 Trace buffer delay counter DCNT Note that the number of bits actually implemented depends on the size of the trace buffer 10 3 3 Trace buffer index register The trace buffer index register indicates the address of the next 128 bit line to be written 31 4 3 0 INDEX 0000 Figure 11 Trace buffer index register 31 4 Trace buffer index counter INDEX Note that the number of bits actually implemented depends on the size of the trace buffer 10 4 10 5 57 10 3 4 Trace buffer time ta
51. There are three clock domains one for the AHB interface system clock one for the transmitter and one for the receiver The receiver clock can be twice as fast and the transmitter clock four times as fast as the system clock whose frequency should be at least 10 MHz The core only supports byte addressed 32 bit big endian host systems ee AHB clock domain D AA Send Transmitter s Transmitter 7 FSM i FIFO A f RMAP Ly Transmitter Transmitter DMA Engine Did AHB Master A gt RENG Interface Tx clock domain LinkInterface gt DMA Engine Did FSM A Rx clock domain 4 a APB Registers je Interface A RMAP Receiver Receiver AHB FIFO D 4 Recei N Char Data CCEIVET T gt FIFO gt Parallelization ji RxClock RxClock S Recovery a Figure 137 Block diagram 42 2 319 Operation 42 2 1 Overview The GRSPW can be split into three main parts the link interface the AMBA interface and the RMAP handler A block diagram of the internal structure can be found in figure 137 The link interface consists of the receiver transmitter and the link interface FSM They handle com munication on the SpaceWire network The AMBA interface consists of the DMA engines the AHB master interface and the APB interface The link interface provides FIFO interfaces to the DMA engines Th
52. counter width PIO mode 0 settings 100MHz clock PIO_mode0_T1 gt 6 TONS PIO_mode0_T2 gt 28 290ns PIO_mode0_T4 gt 2 30ns PIO_mode0_Teoc gt 23 240ns gt TO Tl T2 port map rst gt rstn arst gt l1 clk gt clkm ahbsi gt ahbsi ahbso gt ahbso 5 ATA signals ata_resetn gt ata rst ddin gt ata ddi ddout gt ata ddo ddoe gt ata oen da gt ata da csOn gt ata cs0 csin gt ata csl diorn gt ata dior diown gt ata diow iordy gt ata iordy 600 70 290 240 99 100 intrq dmack i ata_rst_pad port map ata_data_pad port map ata_da_pad port map ata_cs0_pad port map ata_csl_pad port map ata_dior_pad port map ata_diow_pad port map iordy_pad port map intrq_pad port map dmack_pad port map end rtl gt ata intra gt ata dmack outpad generic map ata_rst ata rst iopadv generic map ata_data ata ddo outpadv generic map ata_da ata da outpad generic map ata_cs0 ata cs0 outpad generic map ata_csl ata csl outpad generic map ata_dior ata dior outpad generic map ata_diow ata diow inpad generic map ata_iordy ata iordy inpad generic map ata_intra outpad generic map ata_dmack ata dmack ata intrq ata oen tech gt padtech tech gt padtech tech gt padtech width gt 16 gt 1 ata ddi oepol width g
53. described in section 42 3 4 When the link interface is in the connecting or run state it is allowed to send FCTs FCTs are sent automatically by the link interface when possible This is done based on the maximum value of 56 for the outstanding credit counter and the currently free space in the receiver N Char FIFO FCTs are sent as long as the outstanding counter is less than or equal to 48 and there are at least 8 more empty FIFO entries than the counter value N Chars are sent in the run state when they are available from the transmitter FIFO and there are credits available NULLs are sent when no other character transmission is requested or the FSM is in a state where no other transmissions are allowed The credit counter incoming credits is automatically increased when FCTs are received and decreased when N Chars are transmitted Received N Chars are stored to the receiver N Char FIFO for further handling by the DMA interface Received Time codes are handled by the time interface 42 3 2 Transmitter The state of the FSM credit counters requests from the time interface and requests from the DMA interface are used to decide the next character to be transmitted The type of character and the charac ter itself for N Chars and Time codes to be transmitted are presented to the low level transmitter which is located in a separate clock domain This is done because one usually wants to run the SpaceWire link on a different frequency tha
54. extmdata wrtcmd wrttsw rtaddrp rtaddr clkspd clrerr intack tflag ssflag rtbusy sreq Figure 46 Control register All these bits drive the corresponding input on the Core1553BRT core Bit 0 5 are reset to zero while bit 6 19 are reset according to the implementation corresponding VHDL generic Vector word register 31 16 15 0 RESERVED vword Figure 47 Vector word register 15 0 Drives the vector word input of the Core1553BRT Interrupt vector register 31 7 6 0 RESERVED intvect Figure 48 Interrupt vector register 6 0 Shows the value of the interrupt vector output of the Core1553BRT AHB page address register 31 12 0 ahbaddr RESERVED Figure 49 Address register 31 12 Holds the 20 top most bits of the AHB address of the allocated memory area Resets to the value specified with the ahbaddr VHDL generic 20 4 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x071 For a description of vendor and device identifiers see GRLIB IP Library User s Manual 116 20 5 Configuration options Table 110 shows the configuration options of the core VHDL generics Table 110 Configuration options Generic Function Allowed range Default endian Endiamness of the AHB bus Big 0 0 1 0 ahbaddr Reset value fo
55. ia romsn Boe A a A rwen i A E a O O A Figure 70 Prom write cycle 2 waitstates Memory mapped IO Accesses to IO have similar timing as PROM accesses The IO select IOSN and output enable OEN signals are delayed one clock to provide stable address before IOSN is asserted All accesses are performed as non consecutive accesses as shown in figure 71 The data2 phase is extended when waitstates are added 27 4 189 lead in datai data2 lead out DA iosn ror Ie wey Om e a a oen rT NELLY TO A TT TT TT T data cb Figure 71 I O read cycle 0 waitstates lead in data lead out address iosn i yk heh Ff rf fF FT writen CTT NALIN E TNT O data A a a a a a Figure 72 I O write cycle 0 waitstates SRAM access The SRAM area is divided on up to five RAM banks The size of banks 1 4 RAMSNT 3 0 is pro grammed in the RAM bank size field MCFG2 12 9 and can be set in binary steps from 8 Kbyte to 256 Mbyte The fifth bank RAMSN 4 decodes the upper 512 Mbyte and cannot be used simulta neously with SDRAM memory A read access to SRAM consists of two data cycles and between zero and three waitstates The read data and optional EDAC check bits are latched on the rising edge of the clock on the last data cycle Accesses to RAMSN 4 can further be stretched by de asserting BRDYN until the data is available On non consecuti
56. px Sample divisor 1 Qualifier val 000 Trig on equal yes arm Reset Dump GTKWave Download conf GRMON command Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x062 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 410 shows the configuration options of the core VHDL generics Table 410 Configuration options Generic Function Allowed range Default dbits Number of traced signals 1 255 32 depth Number of stored samples 256 16384 1024 trigl Number of trigger levels 1 63 1 usereg Use input register 0 1 1 usequal Use storage qualifier 0 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr The 12 bit MSB APB address 0 16 FFF 0 pmask The APB address mask 16 000 16 FOO F00 memtech Memory technology 0 NTECH 0 402 46 7 46 8 46 9 The usereg VHDL generic specifies whether to use an input register to synchronize the traced signals and to minimize their fan out If usereg 1 then all signals will be clocked into a register on the posi tive edge of the supplied clock signal otherwise they are sent directly to the RAM Signal descriptions Table 411 shows the interface signals of the core VHDL ports Table 411 Signal descriptions Signal name Field Type Function Active RST N A Input
57. 0x4 PACKET ADDRESS 24 0 Packet Length The number of bytes received to this buffer Only valid after EN has been set to O by the GRSPW 25 Enable EN Set to one to activate this descriptor This means that the descriptor contains valid control values and the memory area pointed to by the packet address field can be used to store a packet 26 Wrap WR If set the next descriptor used by the GRSPW will be the first one in the descriptor table at the base address Otherwise the descriptor pointer will be increased with 0x8 to use the descriptor at the next higher memory location The descriptor table is limited to 1 kbytes in size and the pointer will be automatically wrap back to the base address when it reaches the 1 kbytes boundary 27 Interrupt Enable IE If set an interrupt will be generated when a packet has been received if the receive interrupt enable bit in the DMA channel control register is set 28 EEP Termination EP This packet ended with an Error End of Packet character 29 Header CRC HC 1 if a CRC error was detected for the header and 0 otherwise 30 Data CRC DC 1 if a CRC error was detected for the data and O otherwise 31 Truncated TR Packet was truncated due to maximum length violation 31 0 Packet Address The address pointing at the buffer which will be used to store the received packet If the rxunaligned and rmap VHDL generics are both set to zero only bit 31 to 2 are used F
58. 16 GPIO bits std_ulogic std_ulogic apb_slv_in_type t apb_slv_out_type gpio_in_type t gpio_out_type This examples shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler misc all signal gpti begin gpio0 if CFG_GRGPIO_EN 0 generate grgpiod gptimer_in_type gr gpio generic map pindex gt 11 paddr gt 11 port map pio_pads pio_pad GR GPIO unit imask gt CFG_GRGPIO_IMASK rstn clkm apbi apbo 11 gpioi gpioo for i in 0 to 7 generate iopad generic map port map gpio i end generate end generate gpioo dout i tech gt padtech gpioo oen i gpioi din i nbits gt 8 317 318 42 GRSPW Space Wire codec with AHB host Interface and RMAP support 42 1 Overview The GRSPW Space Wire core provides an interface between the AHB bus and a SpaceWire network It implements the SpaceWire standard ECSS E 50 12A with the protocol identification extension ECSS E 50 11 The optional Remote Memory Access Protocol RMAP command handler imple ments the ECSS standard ECSS E 50 11 The GRSPW SpaceWire interface is configured through a set of registers accessed through an APB interface Data is transferred through DMA channels using an AHB master interface Currently there is one DMA channel but the core can easily be extended to use separate DMA chan nels for specific protocols
59. 440 51 4 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x016 For description of vendor and device identifiers see GRLIB IP Library User s Manual 51 5 Configuration options Table 435 shows the configuration options of the core VHDL generics Table 435 Configuration options Generic Function Allowed range Default mstndx DMA Controllers AHB Master interface index 0 NAHBMST 1 0 apbndx The AMBA APB index for the configuration status APB 0 NAPBMAX 1 0 interface apbaddr APB interface base address 0 16 FFFH 0 apbmask APB interface address mask 0 16 FFFH 16 FFF blength Number of bits in the Burst length register 16 51 6 Signal description Table 436 shows the interface signals of the core VHDL ports Table 436 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input AMBA system clock PCICLK N A Input PCI clock APBI Input APB slave input signals APBO F Output APB slave output signals AHBMI Input AHB master input signals AHBMO e Output AHB master output signals AHBSIO A Input AHB slave input signals main AHB bus AHBSOO ii Output AHB slave output signals main AHB bus AHBSI1 Input AHB slave input signals connected to PCI Tar get Master unit AHBSO1 7 Output AHB slave output signals connected to PCI Tar
60. ACR3 1 0 are unused The corresponding bits in the AMR registers selects if the results of the comparison doesn t matter A set bit in the mask register means don t care Dual filter mode standard frame When receiving a standard frame in dual filter mode the registers ACRO 3 are compared against the incoming message in the following way Filter 1 ACRO 7 0 amp ACR1 7 5 are compared to ID 28 18 ACR1 4 is compared to the RTR bit ACR1 3 0 are compared against upper nibble of data byte 1 ACR3 3 0 are compared against lower nibble of data byte 1 Filter 2 ACR2 7 0 amp ACR3 7 5 are compared to ID 28 18 ACR3 4 is compared to the RTR bit The corresponding bits in the AMR registers selects if the results of the comparison doesn t matter A set bit in the mask register means don t care Dual filter mode extended frame When receiving a standard frame in dual filter mode the registers ACRO 3 are compared against the incoming message in the following way 21 6 135 Filter 1 ACRO 7 0 amp ACR1 7 0 are compared to ID 28 13 Filter 2 ACR2 7 0 amp ACR3 7 0 are compared to ID 28 13 The corresponding bits in the AMR registers selects if the results of the comparison doesn t matter A set bit in the mask register means don t care 21 5 15 RX message counter The RX message counter register at address 29 holds the number of messages currently stored in the receive fifo The top three bits are always 0 Common regi
61. BARO register 31 abits PCI Base Address PCI Targets interface Base Address 0 The number of implemented bits depend on the VHDL generic abits Memory area of size 2abits bytes at Base Address is occupied through this Base Address register Register PAGEO is accessed through upper half of this area PCI memory accesses to the lower half of this area is translated to AHB accesses using PAGEO map register abits 1 4 These bits are read only and always read as 00 0 This field can be used to determine devices memory requirement by writing value of all ones to this register and reading the value back The device will return zeroes in unimplemented bits positions effectively defining memory area requested 3 Prefetchable Not supported Always reads 0 2 1 Base Address Type Mapping can be done anywhere in the 32 bit memory space Reads always as 00 0 Memory Space Indicator Register maps into Memory space Read always as 0 PAGEO register is mapped into upper half of the PCI address space defined by BARO register 31 dmaabits dmaabits 1 4321 0 BASE ADDRESS ae Soe one ala Figure 207 BAR register 31 dmaabits PCI Base Address PCI Targets interface Base Address 1 The number of implemented bits depends on the VHDL generic dmaabits Memory area of size 2 dmaabits bytes at Base Address is occupied through this Base Address register PCI memory accesses to this memory space are
62. BWIDTH 1 0 Input Sets the reset value of the PROM data bus width field in the MCFGI register SD 31 0 Input Not used CB 7 0 Input Checkbits PROMDATA 31 0 Input Not used EDAC Input The reset value for the PROM EDAC enable bit High Table 219 Signal descriptions 231 Signal name Field Type Function Active SRO ADDRESS 31 0 Output Memory address High DATA 31 0 Output Memory data High RAMSN 7 0 Output SRAM chip select Low RAMOENT 7 0 Output SRAM output enable Low IOSN Output IO area chip select Low ROMSN 7 0 Output PROM chip select Low OEN Output Output enable Low WRITEN Output Write strobe Low WRNI 3 0 Output SRAM write enable Low WRNI 0 corresponds to DATA 31 24 WRN 1 corresponds to DATA 23 16 WRN 2 corresponds to DATA 15 8 WRN 3 corresponds to DATA 7 0 Any WRN signal can be used for CB MBEN 3 0 Output Byte enable MBEN 0 corresponds to DATA 31 24 MBEN 1 corresponds to DATA 23 16 MBEN 2 corresponds to DATA 15 8 MBEN 3 corresponds to DATA 7 0 Any MBEN signal can be used for CB BDRIVE 3 0 Output Drive byte lanes on external memory bus Con Low trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 31 24 BDRIVE 1 corresponds to DATA 23 16 BDRIVE 2 corresponds to DATA 15 8 BDRIVE 3 corresponds to DATA 7 0 Any BDRIVE signal can be used for CB
63. COM GPL AHBCTRL_MB AMBA AHB bus controller for multiple buses with plug amp play COM APBCTRL AMBA APB Bridge with plug amp play 0x01 0x006 COM GPL AHBTRACE AMBA AHB Trace buffer 0x01 0x017 COM GPL Table 5 PCI interface Name Function Vendor Device License PCITARGET 32 bit target only PCI interface 0x01 0x012 COM GPL PCIMTF GRPCI 32 bit PCI master target interface with FIFO 0x01 0x014 COM GPL PCITRACE 32 bit PCI trace buffer 0x01 0x015 COM GPL PCIDMA DMA controller for PCIMTF 0x01 0x016 COM GPL PCIARB PCI Bus arbiter 0x04 0x010 LGPL Table 6 On chip memory functions Name Function Vendor Device License AHBRAM Single port RAM with AHB interface 0x01 Ox00E COM GPL AHBROM ROM generator with AHB interface 0x01 0x01B COM GPL SYNCRAM Parametrizable 1 port RAM COM GPL SYNCRAM_2P Parametrizable 2 port RAM COM GPL SYNCRAM_DP Parametrizable dual port RAM COM GPL REGFILE_3P Parametrizable 3 port register file COM GPL FTAHBRAM RAM with AHB interface and EDAC protection 0x01 0x050 FT Table 7 Serial communication Name Function Vendor Device License AHBUART Serial AHB debug interface 0x01 0x007 COM GPL AHBJTAG JTAG AHB debug interface 0x01 0x01C COM GPL APBPS2 PS2 Keyboard interface with APB interface 0x01 0x060 COM GPL APBUART Programmable UART with APB interface 0x01 0x00C COM GPL CAN_OC Opencores CAN 2 0 MAC with AHB interface 0x01 0x019 COM GPL GRETH Gaisler Research 10 100 Mbit Ethernet MAC with AHB I F 0x01
64. Output Identical to BDRIVE but has one signal for each L ow High data bit Every index is driven by its own regis ter This can be used to reduce the output delay ADDRESS 16 2 Output SDRAM address Low DATA 31 0 Output SDRAM data Low 1 see GRLIB IP Library User s Manual 2 Polarity selected with the oepol generic Library dependencies Table 454 shows libraries used when instantiating the core VHDL libraries Table 454 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Instantiation This examples shows how the core can be instantiated 456 The example design contains an AMBA bus with a number of AHB components connected to it including the SDRAM controller The external SDRAM bus is defined on the example designs port map and connected to the SDRAM controller System clock and reset are generated by GR Clock Generator and Reset Generator SDRAM controller decodes SDRAM area 0x60000000 OX6FFFFFFF SDRAM Configuration regis ter is mapped into AHB I O space on address AHB I O base address 0x100 library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all used for I O pads use gaisler misc all entity mctrl_ex is port
65. Table 419 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals Memory bus signals definitions Components SDMCTRL component ESA MEMORYCTRL Component Memory controller component declaration 47 18 Instantiation This examples shows how the core can be instantiated The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined on the example designs port map and connected to the memory controller System clock and reset are generated by GR Clock Gen erator and Reset Generator Memory controller decodes default memory areas PROM area is 0x0 Ox1FFFFFFF 1 O area is 0x20000000 0x3FFFFFFF and RAM area is 0x40000000 Ox7FFFFFFF SDRAM controller is enabled SDRAM clock is synchronized with system clock by clock generator library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all library esa use esa memoryctrl all entity mctrl_ex is used for I O pads 419 port clk in std_ulogic resetn in std_ulogic pllref in std_ulogic memory bus address out std_logic_vector 27 downto 0 memory bus data inout std_logic_vector 31 downto 0 ramsn out std_logic_vector 4 downto 0 r
66. The call will fail if the argument con tains an illegal value SET_TXBLOCK_ON_FULL This call sets the blocking mode for transmissions when all descriptors are in use The argument must be an integer in the range 0 to 1 0 selects non blocking mode while 1 selects blocking mode The call will fail if the argument contains an illegal value SET_DISABLE_ERR This call sets automatic link disabling due to link error interrupts Link error interrupts must be enabled for it to have any effect The argument must be an integer in the range 0 to 1 O disables auto matic link disabling while a 1 enables it The call will fail if the argument contains an illegal value SET_LINK_ERR_IRQ This call sets the link error interrupt bit in the control register The interrupt handler sends an event to the task specified with the event_id field when this interrupt occurs The argument must be an integer 349 in the range 0 to 1 The call will fail if the argument contains an illegal value or if the register write fails SET_EVENT_ID This call sets the task ID to which an event is sent when a link error interrupt occurs The argument can be any positive integer The call will fail if the argument contains an illegal value SET_PACKETSIZE This call changes the size of buffers and consequently the maximum packet sizes The this cannot be done while the link is running so first it is stopped and then the old buffers are deallocated Lastly the new buffe
67. The core has vendor identifier 0x01 Gaisler Research and device identifier 0x017 For a description of vendor and device identifiers see GRLIB IP Library User s Manual 178 25 8 25 9 Configuration options Table 188 shows the configuration options of the core VHDL generics Table 188 Configuration options Generic Function Allowed range Default hindex AHB slave index 0 AHBSLVMAX 1 0 haddr AHB slave address AHB 31 20 0 16 FFFH 16 900 hmask AHB slave address mask 0 16 FFFH 16 FOO ncpu Number of attached processors 1 16 1 tbits Number of bits in the time tag counter 2 30 30 tech Memory technology for trace buffer RAM 0 TECHMAX 1 0 inferred kbytes Size of trace buffer memory in Kbytes A value of 0 0 64 0 disabled will disable the trace buffer function Signal descriptions Table 189 shows the interface signals of the core VHDL ports Table 189 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBMI Input AHB master input signals AHBSI d Input AHB slave input signals AHBSO i Output AHB slave output signals DBGI Input Debug signals from LEON3 DBGO Output Debug signals to LEON3 DSUI ENABLE Input DSU enable High BREAK Input DSU break High DSUO ACTIVE Output Debug mode High PWDIn 1 0 Output Clock gating enable for processor n High se
68. The error mode can be reset and the pro cessor restarted at any address When a processor is in the debug mode an access to ASI diagnostic area is forwarded to the IU which performs access with ASI equal to value in the DSU ASI register and address consisting of 20 LSB bits of the original address AHB Trace Buffer The AHB trace buffer consists of a circular buffer that stores AHB data transfers The address data and various control signals of the AHB bus are stored and can be read out for later analysis The trace buffer is 128 bits wide the information stored is indicated in the table below Table 185 AHB Trace buffer data allocation Bits Name Definition 127 AHB breakpoint hit Set to 1 if a DSU AHB breakpoint hit occurred 126 Not used 125 96 Time tag DSU time tag counter 95 Not used 94 80 Hirq AHB HIRQ 15 1 79 Hwrite AHB HWRITE 78 77 Htrans AHB HTRANS 76 74 Hsize AHB HSIZE 73 71 Hburst AHB HBURST 70 67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65 64 Hresp AHB HRESP 63 32 Load Store data AHB HRDATA or HWDATA 31 0 Load Store address AHB HADDR In addition to the AHB signals the DSU time tag counter is also stored in the trace The trace buffer is enabled by setting the enable bit EN in the trace control register Each AHB transfer is then stored in the buffer in a circular manner The address to which the next transfer is writ ten is held
69. Video Video memory gt gt AQ COMP_SYNC Generator BLANK AQ REDI7 0 GREEN 7 0 BLUE 7 0 Figure 32 APBVGA block diagram Operation The video timing of APBVGA is fixed to generate a 640x480 display with 60 Hz refresh rate The text font is encoded using 8x13 pixels The display is created by scanning a segment of 2960 characters of the 4 Kbyte text buffer rasterizing the characters using the character ROM and sending the pixel data to an external video DAC using three 8 bit color channels The required pixel clock is 25 175 MHz which should be provided on the VGACLK input Writing to the video memory is made through the VGA data register Bits 7 0 contains the character to be written while bits 19 8 defines the text buffer address Foreground and background colours are set through the background and foreground registers These 24 bits corresponds to the three pixel col ors RED GREEN and BLUE The eight most significant bits defines the red intensity the next eight bits defines the green intensity and the eight least significant bits defines the blue intensity Maximum intensity for a color is received when all eight bits are set and minimum intensity when none of the bits are set Changing the foreground color results in that all characters change their color 1t is not possible to just change the color of one character In addition to the color channels the video control ler generates HS YNC VSYNC CSYNC and BLANK Togetherm the
70. end architecture rtl of ftram_ex is AMBA signals signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_type signal apbi apb_slv_in_type signal apbo apb_slv_out_vector other needed signals here signal stati ahbstat_in_type signal aramo ahbram_out_type begin other component instantiations here AHB Status Register astatO ahbstat generic map pindex gt 13 paddr gt 13 pirq gt 11 nftslv gt 3 port map rstn clkm ahbmi ahbso stati apbi apbo 13 stati cerror 1 to NAHBSLV 1 lt others gt 0 FT AHB RAM a0 ftahbram generic map hindex gt 1 haddr gt 1 tech gt inferred kbytes gt 64 pindex gt 4 paddr gt 4 edacen gt 1 autoscrub gt 0 errcnt gt 1 cntbits gt 4 port map rst clk ahbsi ahbso 1 apbi apbo 4 aramo stati cerror 0 lt aramo ce end architecture 185 186 27 27 1 27 2 FTMCTRL 8 16 32 bit Memory Controller with EDAC Overview The FTMCTRL combined 8 16 32 bit memory controller provides a bridge between external memory and the AHB bus The memory controller can handle four types of devices PROM asynchronous static ram SRAM synchronous dynamic ram SDRAM and memory mapped I O devices IO The PROM SRAM and SDRAM areas can be EDAC protected using a 39 7 BCH code The EDAC pro vides single error correction and double error detection for each 32 bit memory word The memory controller is co
71. gt 0 port map clk gnd clkm open open sdclk open cgi cgo cgi pllctrl lt 00 cgi pllrst lt resetn cgi pllref lt pllref Memory controller ftmctrl10 ftmctrl generic map srbanks gt 1 sden gt 1 edac gt 1 port map rstn clkm memi memo ahbsi ahbso 0 apbi apbo 0 wprot sdo memory controller inputs not used in this configuration memi brdyn lt 1 memi bexcn lt 1 memi wrn lt 1111 210 memi sd lt sd prom width at reset memi bwidth lt 10 I O pads driving data memory bus data signals datapads for i in 0 to 3 generate data_pad iopadv generic map width gt 8 port map pad gt memi data 31 i 8 downto 24 i 8 o gt memi data 31 i 8 downto 24 1 8 en gt memo bdrive i i gt memo data 31 i 8 downto 24 1 8 end generate connect memory controller outputs to entity output signals address lt memo address ramsn lt memo ramsn romsn lt memo romsn oen lt memo oen rwen lt memo wrn ramoen lt 1111 amp memo ramoen 0 sa lt memo sa writen lt memo writen read lt memo read iosn lt memo iosn sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm end 28 28 1 28 2 211 FTSDCTRL 32 64 bit PC133 SDRAM Controller with EDAC Overview The fault tolerant SDRAM memory interface handles PC133 SDRAM compatible
72. in ahb_mst_in_type ahbo out ahb_mst_out_type end component 19 10 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler b1553 all 112 signal bin signal bout signal brmi signal brmo b1553_in_type b1553_out_type brm1553_in_type brm1553_out_type bc1553_0 b1553brm generic map hindex gt 2 pindex gt 12 abits gt 17 mselin gt 0 port map rstn open clkm gnd 0 ahbmo 2 paddr gt 16104 pirg gt 2 brmi brmo bin bout apbi apbo 12 20 20 1 113 B1553RT AMBA plug amp play interface for Actel Core1553BRT Overview The interface provides a complete Mil Std 1553B Remote Terminal RT The interface connects to the MIL STD 1553B bus through external transceivers and transformers The interface is based on the Actel Core1553BRT core The interface provides a complete dual redundant MIL STD 1553B remote terminal RT apart from the transceivers required to interface to the bus At a high level the interface simply provides a set of memory mapped sub addresses that receive data written to or transmit data read from The inter face requires 2 048 words of memory which can be shared with a local processor The interface sup ports all 1553B mode codes and allows the user to designate as illegal any mode code or any particular sub
73. instructions Multi cycle instructions are entered two or three times in the trace buffer For store instructions bits 63 32 correspond to the store address on the first entry and to the stored data on the second entry and third in case of STD Bit 126 is set on the second and third entry to indicate this A double load LDD is entered twice in the trace buffer with bits 63 32 containing the loaded data Multiply and divide instructions are entered twice but only the last entry contains the result Bit 126 is set for the second entry For FPU operation producing a double precision result the first entry puts the MSB 32 bits of the results in bit 63 32 while the second entry puts the LSB 32 bits in this field When the processor enters debug mode tracing is suspended The trace buffer and the trace buffer control register can be read and written while the processor is in the debug mode During the instruc tion tracing processor in normal mode the trace buffer and the trace buffer control register can not be accessed 174 25 5 DSU memory map The DSU memory map can be seen in table 187 below In a multiprocessor systems the register map is duplicated and address bits 27 24 are used to index the processor Table 187 DSU memory map Address offset Register 0x000000 DSU control register 0x000008 Time tag counter 0x000020 Break and Single S
74. leaving at least one message position in the buffer empty This is to simplify wrap around condition checking E g CanRxSIZE SIZE 2 means that 7 CAN messages fit in the buffer at any given time 22 6 2 Write and read pointers The write pointer CanRxWR WRITE indicates the position 1 of the last CAN message written to the buffer The write pointer operates on number of CAN messages not on absolute or relative addresses The read pointer CanRxRD READ indicates the position 1 of the last CAN message read from the buffer The read pointer operates on number of CAN messages not on absolute or relative addresses The difference between the write and the read pointers is the number of CAN message positions avail able in the buffer for reception The difference is calculated using the buffer size specified by the CanRxSIZE SIZE field taking wrap around effects of the circular buffer into account Examples e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 Can RxWR WRITE 2 and CanRxRD READ 0 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 Can RxWR WRITE 0 and CanRxRD READ 6 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 Can RxWR WRITE 1 and CanRxRD READ 7 e There are 2 CAN messages available for read out when CanRxSIZE SIZE 2 Can RxWR WRITE 5 and CanRxRD READ 3 When a CAN message has been successfully received and stored the write pointer
75. normal interrupts are generated when transmitter interrupts are enabled TI the trans mitter is enabled and the transmitter FIFO goes from containing data to being empty FIFO interrupts are generated when the FIFO interrupts are enabled TF transmissions are enabled TE and the UART is less than half full that is whenever the TH status bit is set This is a level interrupt and the interrupt signal is continuously driven high as long as the condition prevails The receiver interrupts work in the same way Normal interrupts are generated in the same manner as for the holding register FIFO interrupts are generated when receiver FIFO interrupts are enabled the receiver is enabled and the FIFO is half full The interrupt signal is continuously driven high as long as the receiver FIFO is half full at least half of the entries contain data frames 86 15 4 Registers The core is controlled through registers mapped into APB address space Table 77 UART registers APB address offset Register 0x0 UART Data register 0x4 UART Status register 0x8 UART Control register OxC UART Scaler register 15 4 1 UART Data Register Table 78 UART data register 31 8 7 0 RESERVED DATA 0 Receiver holding register or FIFO read access Transmitter holding register or FIFO write access 15 4 2 UART Status Register Table 79 UART status register 31 26 25 20
76. signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect SDRAM controller and SDRAM memory bus signal sdi sdctrl_in type signal sdo sdctrl_out_type signal clkm rstn std_ulogic system clock and reset signal ce std_logic_vector 0 to 2 correctable error signal vector signals used by clock and reset generators signal cgi clkgen_in_type signal cgo clkgen_out_type signal gnd std_ulogic begin AMBA Components are defined here 218 Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 clk_div gt 2 sdramen gt 1 tech gt virtex2 sdinvclk gt 0 port map clk gnd clkm open open sdclk open cgi cgo cgi pllctrl lt 00 cgi pllrst lt resetn cgi pllref lt pllref rst0 rstgen port map resetn clkm cgo clklock rstn AHB Status Register astat0 ahbstat generic map pindex gt 13 paddr gt 13 pirq gt 11 nftslv gt 3 port map rstn clkm ahbmi ahbsi ce apbi apbo 13 SDRAM controller sde ftsdctrl generic map hindex gt 3 haddr gt 16 600 hmask gt 16 FOO ioaddr gt 1 fast gt 0 pwron gt 1 invclk gt 0 edacen gt 1 errcnt gt 1 cntbits gt 4 port map rstn cl
77. signal sdo sdctrl_out_type signal wprot wprot_out_type dummy signal not used signal clkm rstn std_ulogic system clock and reset signals used by clock and reset generators signal cgi clkgen_in_type signal cgo clkgen_out_type 234 signal gnd std_ulogic signal stati ahbstat_in_type correctable error vector begin AMBA Components are defined here Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 clk_div gt 2 sdramen gt 1 tech gt virtex2 sdinvclk gt 0 port map clk gnd clkm open open sdclk open cgi cgo cgi pllctrl lt 00 cgi pllrst lt resetn cgi pllref lt pllref rst0 rstgen port map resetn clkm cgo clklock rstn AHB Status Register astat0 ahbstat generic map pindex gt 13 paddr gt 13 pirq gt 11 nftslv gt 1 port map rstn clkm ahbmi ahbsi stati apbi apbo 13 stati cerror 0 lt memo ce Memory controller mctrl0 ftsrctrl generic map rmw gt 1 pindex gt 10 paddr gt 10 edacen gt 1 errcnt gt 1 cntbits gt 4 port map rstn clkm ahbsi ahbso 0 apbi apbo 10 memi memo sdo I O pads driving data memory bus data signals datapads for i in 0 to 3 generate data_pad iopadv generic map width gt 8 port map pad gt data 31 1 8 downto 24 i 8 o gt memi data 31 i 8 downto 24 1 8 en gt memo bdrive i i gt memo data 31 i 8 downto 24 1 8
78. tag bits The cache rams are sized automatically by the ram generators in the model Additional cache functionality 44 5 1 Cache flushing Both instruction and data cache are flushed by executing the FLUSH instruction The instruction cache is also flushed by setting the FI bit in the cache control register or by writing to any location with ASI 0x15 The data cache is also flushed by setting the FD bit in the cache control register or by writing to any location with ASI 0x16 Cache flushing takes one cycle per cache line during which the IU will not be halted but during which the caches are disabled When the flush operation is com pleted the cache will resume the state disabled enabled or frozen indicated in the cache control reg ister Diagnostic access to the cache is not possible during a FLUSH operation and will cause a data exception trap 0x09 if attempted 44 5 2 Diagnostic cache access Tags and data in the instruction and data cache can be accessed through ASI address space OxC OxD OxE and OxF by executing LDA and STA instructions Address bits making up the cache offset will be used to index the tag to be accessed while the least significant bits of the bits making up the address tag will be used to index the cache set Diagnostic read of tags is possible by executing an LDA instruction with ASI OxC for instruction cache tags and ASI 0xE for data cache tags A cache line and set are indexed by the address bits mak ing up
79. usbi0pad inpad generic usbilpad inpad generic usbi2pad inpad generic usbi3pad inpad generic usbi4pad inpad generic usb_linestate 0 usbi5pad inpad generic usb_linestate 1 usbi6 pad inpad generic usbo0pad outpad generic usbolpad outpad generic usbo2pad outpad generic usbo3pad outpad generic usbo4pad outpad generic usbo5pad outpad generic usbobpad outpad generic usb_clk_pad usb_ctrl u end generic hindex port map uclk sbdcl map gt 0 usbi u ut i u map tec map tec map tec map tec map tec usbi linestate 0 map tec usbi linestate 1 map tec map te map te map te map te map te map te map te clkpad generic map sbi rxactive h gt padtech h gt padtech h gt padtech h gt padtech h gt padtech h gt padtech h gt padtech ch gt padtech ch gt padtech ch gt padtech ch gt padtech ch gt padtech ch gt padtech ch gt padtech usbi port port port port port port port port port port port port port port din i ma ma ma ma O O O O O ma map map map map map map map map map usb_txready usbi txready usb_rxvalid usbi rxvalid usb_rxerror usbi rxerror usb_rxactive usbi rxactive usb_vbus usbi vbus usb_reset usbo reset usb_suspend usbo suspend usb_termsel usbo termselect E usb_xcvrsel usbo xcvrselect usb_opmod
80. write std_ulogic ram0 syncram generic map tech gt tech abits gt addrbits dbits gt dbits port map clk addr datain dataout enable write 60 60 1 60 2 483 SYNCRAM_2P Two port RAM generator Overview The two port RAM generator has a one read port and one write port Each port has a separate address and data bus All inputs are registered on the rising edge of clk The read data appears on dataout directly after the clk rising edge Address width data width and target technology is parametrizable through generics Write through is supported if the function syncram_2p_write_through tech returns 1 for the target technology Configuration options Table 472 shows the configuration options of the core VHDL generics Table 472 Configuration options Name Function Range Default tech Technology selection 0 NTECH 0 abits Address bits Depth of RAM is 2 its 1 see table below dbits Data width see table below sepclk If 1 separate clocks rclk wclk are used for the two ports If 0 0 1 0 rclk is used for both ports Table 473 shows the supported technologies for the core Table 473 Supported technologies Tech name Technology RAM cell abit range dbit range Inferred Behavioural description Tool dependent unlimited unlimited altera All Altera devices altsyncram umlimited unlimited virtex Xilinx Virtex Virtex E Spartan 2 RAM
81. y Advantages The main operation in ECC is the k P multiplication One k P multiplication requires about 1500 field multiplications in the base field which is the most expensive base operation The complexity of a field multiplication can be reduced by applying the Karatsuba method Normally the Karatsuba approach is applied recursively The GRECC core includes an iterative implementation of the Karat suba method which allows to realize area efficient hardware accelerators for the k P multiplication Hardware accelerators which are realized applying an iterative approach need up to 60 per cent less area and about 30 per cent less energy per multiplication than the recursive variants Background The Standards for Efficient Cryptography Group SECG was initiated by Certicom Corporation to address the difficulty vendors and users face when building and deploying interoperable security solu tions The SECG is a broad international coalition comprised of leading technology companies and key industry players in the information security industry One of the goals is to enable the effective incorporation of Elliptic Curve Cryptographic ECC technology into these various cryptographic solutions The Standards for Efficient Cryptography Group SECG has develop two sets of documents The first set under the name SEC specifies interoperable cryptographic technologies and solutions The second set Guidelines for Efficient Cryptography GEC provides
82. 0 Lp DMA Engine l RAM WH 4 RX_CLK Figure 122 Block diagram of the internal structure of the GRETH_GBIT Operation 35 2 1 System overview The GRETH_GBIT consists of 3 functional units The DMA channels MDIO interface and the optional Ethernet Debug Communication Link EDCL The main functionality consists of the DMA channels which are used for transferring data between an AHB bus and an Ethernet network There is one transmitter DMA channel and one Receiver DMA channel The operation of the DMA channels is controlled through registers accessible through the APB interface 35 3 285 The MDIO interface is used for accessing configuration and status registers in one or more PHYs con nected to the MAC The operation of this interface is also controlled through the APB interface The optional EDCL provides read and write access to an AHB bus through Ethernet It uses the UDP IP and ARP protocols together with a custom application layer protocol to accomplish this The EDCL contains no user accessible registers and always runs in parallel with the DMA channels The Media Independent Interface MII and Gigabit Media Independent Interface GMII are used for communicating with the PHY More information can be found in section 35 7 The EDCL and the DMA channels share the Ethernet receiver and transmitter More information on these functional units is provided in sections 35 3 35 6 35 2 2 Protocol support The GRETH_GBIT
83. 0 haddr integer 0 hmask integer 16 fff nslaves integer range 1 to NAPBSLV NAPBSLV debug integer range 0 to 2 2 print config to console icheck integer range 0 to 1 1 i port rst in std_ulogic clk in std_ulogic ahbi in ahb_slv_in type ahbo out ahb_slv_out_type apbi out apb_slv_in_type apbo in apb_slv_out_vector end component 13 9 Instantiation This examples shows how an APB bridge can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use work debug all AMBA signals signal ahbsi ahb_slv_in type signal ahbso ahb_slv_out_vector others gt ahbs_none signal apbi apb_slv_in type signal apbo apb_slv_out_vector others gt apb_none begin APB bridge apb0 apbctrl AHB APB bridge generic map hindex gt 1 haddr gt CFG_APBADDR port map rstn clk ahbsi ahbso 1 apbi apbo 72 13 10 APB slaves uartl apbuart generic map pindex gt 1 paddr gt 1 pirq gt 2 port map rstn clk apbi apbo 1 uli ulo irgctrl10 irqmp generic map pindex gt 2 paddr gt 2 port map rstn clk apbi apbo 2 irgo irqi Debug print out The APB bridge can print out the plug play information from the attached during simulation This is enabled by setting the debug VHDL generic to 2 Reporting starts by scanning the array from 0 to NAPBSLV 1 defined in the grli
84. 0x01D COM GPL GRETH_GIGA Gaisler Research 10 100 1000 Mbit Ethernet MAC with AHB 0x01 0x01D COM GRSPW SpaceWire link with RMAP and AHB interface 0x01 OxO1F FT USBDCL USB 2 0 AHB debug communication link 0x01 0x022 COM GRCAN CAN 2 0 Controller with DMA 0x01 0x03D COM 18 Table 8 Misc peripherals Name Function Vendor Device License ATACTRL IDE ATA controller with AHB interface 0x01 0x024 COM GPL GPTIMER Modular timer unit 0x01 0x011 COM GPL GPIO 32 bit General purpose I O port 0x01 0x01A COM GPL LOGAN On chip logic analyzer 0x01 0x062 COM GPL TAP Generic TAP controller COM GPL NUHOSP3 PROM amp I O interface for Nuhorizons Spartan3 board 0x01 0x02B COM GPL APBVGA Text only VGA controller 0x01 0x061 COM GPL CLKGEN Clock generator and frequency divider for Altera Xilinx COM GPL RSTGEN Generic reset generator COM GPL SVGACTRL SVGA video frame buffer 0x01 0x063 COM GPL Table 9 MIL STD 1553 Bus interface Name Function Device ID License B1553BC 1553 Bus controller with AHB interface 0x01 0x070 COM B1553RT 1553 Remote terminal with AHB interface 0x01 0x071 COM B1553BRM 1553 BC RT Monitor with AHB interface 0x01 0x072 COM Table 10 Encryption Name Function Vendor Device License GRAES 128 bit AES Encryption Decryption Core 0x01 0x073
85. 111 19 10 ETS e AET LECO a E A A A Ri 111 B1553RT AMBA plug amp play interface for Actel Corel 553BRT eecsceerereereerer 113 20 1 OVERVICW a e a E R E TEE EE TE a E 113 20 2 AUB interlace s aeis ie hte ee ees Reseda ies eee ah et oes a Re eR 114 20 3 REGISTERS NEES NEE O 114 20 4 Vendor and device identifiers 0 0 eee cess ceeceseeesceseeeeceeeeseecaecseecaacsaecsecsacsaecsacesecesesseeeeeeeseeseaeseeeees 115 20 5 A aie cxces dh seecs asses Ee Er sakcs sub KEE TEE EE EEEE dsvececescheugavess Aovscbeseess 116 20 6 Signal descriptions 44 4 since Aya e pa 117 20 7 Library dependencies sorone cierne operan sind EErEE rE EE ene EEES nS EE EE O ore SVE cias do espia em 118 20 8 Component declaration aerer e RE N EEN AE A EE 118 20 9 Instant E 118 21 22 23 24 25 CAN_OC GRLIB wrapper for OpenCores CAN Interface core ooooonocononcconcnnonncnoncnnccnnnos 120 21 1 COVEEVICW sss NN 120 21 2 Opencores CAN controller OVELVICW oooococnnocnconnonnonnnanonnnonnconccn non no cono no cnn nnno non nnnn ran non nr ano rn coran on ncnnecnnns 120 21 3 AB IMC Ri a 120 21 4 BasicCAN Mode a 121 21 5 Peli CAN Modera ds 125 21 6 Common registers enn un lies 135 21 7 Design Considerations miiirn vodor cus sh cvech vena gulch S EE KSEE Eees eE bE EE KOEKE TE or ESTS seas iS 136 21 8 Vendor and device 1Gentitiers 2 3 ova sscdesevagseetssiabeieas ssnyesucesssscenstesseesctsbes bcs taaan picar 136 21 9 Configuration Options sitiar eS ale tae ee
86. 12 11 0 RESERVED DISCONNECT TIMER64 11 0 21 12 Timer64 Used to generate the 6 4 and 12 8 us time periods Should be set to the smallest number of clock cycles that is greater than or equal to 6 4 us Reset value is set with VHDL generics or with input signals depending on the value of the usegen VHDL generic Disconnect Used to generate the 850 ns disconnect time period The disconnect period is the number is the number of clock cycles in the disconnect register 3 So to get a 850 ns period the smallest number of clock cycles that is greater than or equal to 850 ns should be calculated and this values 3 should be stored in the register Reset value is set with VHDL generics or with input signals depending on the value of the usegen VHDL generic Figure 150 GRSPW timer and disconnect register 31 1211 109 8 7 6 5 4 3 2 1 0 NS RDRX AT RA TA PR PS AI RI TI RE TE 31 10 11 12 Transmitter Enable TE Write a one to this bit each time new descriptors are activated in the table Writing a one will cause the SW node to read a new descriptor and try to transmit the packet it points to This bit is automatically cleared when the SW node encounters a descriptor which is disabled Reset value 0 Receiver Enable RE Set to one when packets are allowed to be received to this channel Reset value 0 Transmit Interrupt TI If set an inter
87. 16 FFF area and the start address together with haddr nslaves The maximum number of slaves 1 NAPBSLV NAPBSLV debug Print debug information during simulation 0 2 2 icheck Enable bus index checking PINDEX 0 1 1 enbusmon Enable APB bus monitor 0 1 0 asserterr Enable assertions for AMBA requirements Violations 0 1 0 are asserted with severity error assertwarn Enable assertions for AMBA recommendations Viola 0 1 0 tions are asserted with severity warning pslvdisable Disable APB slave rule check To disable a slave rule N A 0 check a value is assigned so that the binary representa tion contains a one at the position corresponding to the rule number e g 0x80 disables rule 7 Signal descriptions Table 63 shows the interface signals of the core VHDL ports Table 63 Signal descriptions Signal name Field Type Function Active RST N A Input AHB reset Low CLK N A Input AHB clock AHBI Output AHB slave input AHBO Input AHB slave output APBI Output APB slave inputs APBO Input APB slave outputs see GRLIB IP Library User s Manual 13 7 Library dependencies Table 64 shows libraries used when instantiating the core VHDL libraries Table 64 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions 13 8 Component declaration library grlib use grlib amba all component apbctrl generic hindex integer
88. 185 Prom non consecutive read cyclecs datai data2 datai data2 lead out oa romsn m Ps OF A O a oen Pie he I Ee te ef oe ES cb CB1 CB2 Figure 186 Prom consecutive read cyclecs datai data2 data2 data2 lead out ee romsn Pe ee WN eee ey om oen PN i Ms ie me ee data cb CB1 Figure 187 Prom read access with two waitstates 406 47 3 lead in data lead out address romsn Trott ir a O rwen iP AAAA TT oh oy oof ie i cb CB1 Figure 188 Prom write cycle 0 waitstates lead in data data data lead out a romsn ASI e AAA a rwen PAR AAA A e lt ane cb CB1 Figure 189 Prom write cycle 2 waitstates Two PROM chip select signals are provided MEMO ROMSN 1 0 MEMO ROMSN 0 is asserted when the lower half of the PROM area as addressed while MEMO ROMSN 1 is asserted for the upper half When the VHDL model is configured to boot from internal prom MEMO ROMSN 0 is never asserted and all accesses to the lower half of the PROM area are mapped on the internal prom Memory mapped I O Accesses to I O have similar timing to ROM RAM accesses the differences being that a additional waitstates can be inserted by de asserting the MEMI BRDYN signal The I O select signal MEMO IOSN is delayed one clock to provide stable address before MEMO IOSN is
89. 19 11 10 9 8 7 6 5 4 3 2 1 40 RCNT TCNT RESERVED RF TF RH TH FE PE OV BR TE TS DR 31 26 Receiver FIFO count RCNT shows the number of data frames in the receiver FIFO 25 20 Transmitter FIFO count TCNT shows the number of data frames in the transmitter FIFO 10 Receiver FIFO full RF indicates that the Receiver FIFO is full 9 Transmitter FIFO full TF indicates that the Transmitter FIFO is full 8 Receiver FIFO half full RH indicates that at least half of the FIFO is holding data 7 Transmitter FIFO half full TH indicates that the FIFO is less than half full 6 Framing error FE indicates that a framing error was detected 5 Parity error PE indicates that a parity error was detected 4 Overrun OV indicates that one or more character have been lost due to overrun 3 Break received BR indicates that a BREAK has been received 2 Transmitter FIFO empty TE indicates that the transmitter FIFO is empty 1 Transmitter shift register empty TS indicates that the transmitter shift register is empty 0 Data ready DR indicates that new data is available in the receiver holding register 15 5 15 6 87 15 4 3 UART Control Register Table 80 UART control register 31 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED RF TF EC LB FL PE PS TI RI TE RE 10 Receiver FIFO interrupt enable RF when set Receiver FIFO level interrupts are enabled Transmitter FIFO interrupt ena
90. 29 srbanks Number of SRAM banks 0 5 4 ram8 Enable 8 bit PROM SRAM and I O access 0 1 0 raml6 Enable 16 bit PROM SRAM and I O access 0 1 0 sden Enable SDRAM controller 0 1 0 sepbus SDRAM is located on separate bus 0 1 1 sdbits 32 or 64 bit SDRAM data bus 32 64 32 oepol Select polarity of drive signals for data pads 0 active low 1 0 1 0 active high edac Enable EDAC 0 1 sdlsb Select least significant bit of the address bus that is connected to SDRAM syncrst Choose between synchronous and asynchronous reset for chip 0 1 0 select oen and drive signals pageburst Line burst read of length 8 when 0 page burst read when 1 pro 0 2 0 grammable read burst type when 2 202 27 18 Signal descriptions Table 204 shows the interface signals of the core VHDL ports Table 204 Signal descriptions Signal name Field Type Function Active CLK N A Input Clock RST N A Input Reset Low MEMI DATA 31 0 Input Memory data High BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low CBI 7 0 Input EDAC checkbits High WRN 3 0 Input SRAM write enable feedback signal Low BWIDTH 1 0 Input Sets the reset value of the PROM data bus width High field in the MCFGI register EDAC Input The reset value for the PROM EDAC enable bit High SD 31 0 Input SDRAM separate data bus High Table 204 Signal descriptions 203
91. 5 5 6 Configuration options Table 25 shows the configuration options of the core VHDL generics Table 25 Configuration options 39 Generic Function Allowed range Default ioaddr The MSB address of the I O area Sets the 12 most sig O 16 FFF 16 FFF nificant bits in the 32 bit AHB address iomask The I O area address mask Sets the size of the I O area 0 16 FFF 16 FFFH and the start address together with ioaddr cfgaddr The MSB address of the configuration area 0 16 FFFH 16 FFO cfgmask The address mask of the configuration area Sets the size O 16 FFF 16 FFO of the configuration area and the start address together with cfgaddr If set to 0 the configuration will be dis abled rrobin Selects between round robin 1 or fixed priority 0 bus 0 1 0 arbitration algorithm split Enable support for AHB SPLIT response 0 1 0 defmast Default AHB master 0 NAHBMST 1 0 ioen AHB T O area enable Set ot O to disable the I O area 0 1 1 nahbm Number of AHB masters 1 NAHBMST NAHBMST nahbs Number of AHB slaves 1 NAHBSLV NAHBSLV timeout Perform bus timeout checks NOT IMPLEMENTED 0 1 0 fixbrst Enable support for fixed length bursts 0 1 0 debug Print configuration O none 1 short 2 all cores 0 2 2 fpnpen Enables full decoding of the PnP configuration records 0 1 0 When disabled the user defined registers in the PnP con figurat
92. 5 18h 3 7 Olh 26 7 09h 13 3 11h 6 7 19h 3 3 02h 24 OAh 12 12h 6 1Ah 3 03h 21 8 OBh 10 9 13h 5 5 1Bh 2 7 04h 20 7 OCh 10 14h 5 1Ch 2 5 05h 18 5 ODh 9 2 15h 4 6 1Dh 2 3 06h 17 1 OEh 8 6 16h 4 3 1Eh 2 1 07h 16 OFh 8 17h 4 1Fh 2 Table 76 Typematic delays Bits 5 6 Delay seconds 00b 0 25 01b 0 5 10b 0 75 11b 1 15 15 1 15 2 83 APBUART AMBA APB UART Serial Interface Overview The interface is provided for serial communications The UART supports data frames with 8 data bits one optional parity bit and one stop bit To generate the bit rate each UART has a programmable 12 bit clock divider Two FIFOs each 2 bytes deep are used for data transfer between the bus and UART when fifosize VHDL generic gt 1 Two holding registers are used data transfer between the bus and UART when fifosize VHDL generic 1 Hardware flow control is supported through the RTSN CTSN hand shake signals when flow VHDL generic is set Parity is supported when parity VHDL generic is set 4 0 CTSN Serial port Baud rate 8 bitelk Controller Le RTSN generator RXD gt Receiver shift register gt Transmitter shift register P TXD y Receiver FIFO or Transmitter FIFO or holding register holding register Figure 30 Block diagram Operation 15 2 1 Transmitter operation The trans
93. 6 255 The Advanced Encryption Standard AES standard specifies the Rijndael algorithm a symmetric block cipher that can process data blocks of 128 bits using cipher keys with lengths of 128 192 and 256 bits Rijndael was designed to handle additional block sizes and key lengths however they are not adopted in this standard AES 128 parameters The GRAES core implements AES 128 An AES algorithm is defined by the following parameters according to FIPS 197 e Nk number of 32 bit words comprising the cipher key e Nr number of rounds The AES 128 algorithm is specified as Nk 4 and Nr 10 The GRAES core has been verified against the complete set of Known Answer Test vectors included in the AES Algorithm Validation Suite AESAVS from National Institute of Standards and Technol ogy NIST Information Technology Laboratory Computer Security Division Throughput The data throughput for the GRAES core is around 128 90 bits per clock cycle i e approximately 1 4 Mbits per MHz The underlaying AES core has been implemented in a dual crypto chip on 250 nm technology as depicted in the figure below The throughput at 33 MHz operating frequency was 42 Mbit s the power consumption was 9 6 mW and the size was 14 5 kgates SSS SSH SST HTH AE ewer Feat 4 gt e o Figure 109 Dual Crypto Chip Characteristics The GRAES core has been synthesized for a Xilinx Virtex 2 XC2V6000 4 devices with
94. 64 32 n 4 mod NWINDOWS 64 e ln 0x300000 psr cwp 64 64 n 4 mod NWINDOWS 64 e Qin 0x300000 psr cwp 64 96 n 4 mod NWINDOWS 64 e gn_ 0x300000 NWINDOWS 64 e fn 0x301000 n 4 175 25 6 DSU registers 25 6 1 DSU control register The DSU is controlled by the DSU control register 31 11 109 8 7 65 4 3 2 1 0 PW HL PE EB EE DM BZ BX BS BWBE TE Figure 54 DSU control register 0 Trace enable TE Enables instruction tracing If set the instructions will be stored in the trace buffer Remains set when then processor enters debug or error mode 1 Break on error BE if set will force the processor to debug mode when the processor would have entered error condition trap in trap 2 Break on IU watchpoint BW if set debug mode will be forced on a IU watchpoint trap 0xb 3 Break on S W breakpoint BS if set debug mode will be forced when an breakpoint instruction ta 1 is executed 4 Break on trap BX if set will force the processor into debug mode when any trap occurs 5 Break on error traps BZ if set will force the processor into debug mode on all except the following traps priviledged_instruction fpu_disabled window_overflow window_underflow asynchronous_interrupt ticc_trap 6 Debug mode DM Indicates when the processor has entered debug mode read only 7 EE value of the external DSUEN sign
95. 9 Software drivers Drivers for the GRETH_GBIT MAC is provided for the following operating systems RTEMS eCos uClinux and Linux 2 6 The drivers are freely available in full source code under the GPL license from Gaisler Research s web site http www gaisler com 35 10 Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x01D For description of vendor and device identifiers see GRLIB IP Library User s Manual 295 35 11 Configuration options Table 310 shows the configuration options of the core VHDL generics Table 310 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr Addr field of the APB bar 0 16 FFFH 0 pmask Mask field of the APB bar 0 16 FFFH 16 FFFH pirq Interrupt line used by the GRETH 0 NAHBIRQ 1 0 memtech Memory technology used for the FIFOs 0 NTECH inferred ifg_gap Number of ethernet clock cycles used for one interframe gap 1 255 24 Default value as required by the standard Do not change unless you know what your doing attempt_limit Maximum number of transmission attempts for one packet 1 255 16 Default value as required by the standard backoff_limit Limit on the backoff size of the backoff time Default value as 1 10 10 required by the standard Sets the number of bits
96. AHB error was encountered in receiver DMA engine Cleared when written with a one Not Reset 5 Transmitter AHB Error TA An AHB error was encountered in transmitter DMA engine Cleared when written with a one Not Reset 6 Too Small TS A packet smaller than the minimum size was received Cleared when written with a one Reset value 0 7 1 nvalid Address IA A packet with an address not accepted by the MAC was received Cleared when written with a one Reset value 0 31 16 15 0 RESERVED Bit 47 downto 32 of the MAC Address Figure 127 MAC Address MSB 31 16 The two most significant bytes of the MAC Address Not Reset 31 0 Bit 31 downto 0 of the MAC Address Figure 128 MAC Address LSB 31 0 The 4 least significant bytes of the MAC Address Not Reset 31 16 15 11 10 6 4 3 2 1 0 DATA PHY ADDRESS REGISTER ADDRESS INV BU LF RD WR Figure 129 GRETH_GBIT MDIO ctrl status register 0 Write WR Start a write operation on the management interface Data is taken from the Data field Reset value q 1 Read RD Start a read operation on the management interface Data is stored in the data field Reset value 0 2 Linkfail LF When an operation completes BUSY 0 this bit is set if a functional management link was not detected Not Reset 3 Busy BU When an operation is performed this bit is set to one As soon as the operation is finished and the management link is idle this bit is cleared Reset value
97. AHBSO s Output AHB slave output signals APBI Input APB slave input signals APBO Output APB slave output signals WPROT WPROTHIT Input Unused 204 Table 204 Signal descriptions Signal name SDO Field SDCASN Type Output Function SDRAM column address strobe Active Low SDCKE 1 0 Output SDRAM clock enable High SDCSN 1 0 Output SDRAM chip select Low SDDQM 7 0 Output SDRAM data mask SDDQM 7 corresponds to SD 63 56 SDDQM 6 corresponds to SD 55 48 SDDQM 5 corresponds to SD 47 40 SDDQM 4 corresponds to SD 39 32 SDDQM 3 corresponds to SD 31 24 SDDQM corresponds to SD 23 16 SDDQM 1 corresponds to SD 15 8 SDDQM 0 corresponds to SD 7 0 Any SDDQM signal can be used for CB Low SDRASN Output SDRAM row address strobe Low SDWEN Output SDRAM write enable Low see GRLIB IP Library User s Manual 27 19 Signal definitions and reset values The signals and their reset values are described in table 205 Table 205 Signal definitions and reset values 205 Signal name Type Function Active Reset value address 27 0 Output Memory address High Undefined data 31 0 Input Output Memory data High Tri state cb 7 0 Input Output Check bits High Tri state ramsn 4 0 Output SRAM chip select Low Logical
98. All AHB operations are performed as incremental bursts of unspecified length Only word size accesses are done Registers The core does not contain any user accessible registers Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x022 For description of vendor and device identifiers see GRLIB IP Library User s Manual The USB vendor identifier is 0x1781 and product identifier is OxOAAO 495 63 5 Configuration options Table 483 shows the configuration options of the core VHDL generics Table 483 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 memtech Memory technology used for blockrams endpoint buff 0 NTECH 0 ers 63 6 Signal descriptions Table 484 shows the interface signals of the core VHDL ports Table 484 Signal descriptions Signal name Field Type Function Active UCLK N A Input USB UTMI Clock USBI Input USB UTMI Input signals USBO Output USB UTMI Output signals HCLK Input AMBA Clock HRST Input AMBA Reset Low AHBMI E Input AHB master input signals AHBMO ig Output AHB master output signals see GRLIB IP Library User s Manual 63 7 Library dependencies Table 485 shows libraries used when instantiating the core VHDL libraries Table 485 Library dependencies Library Package Impor
99. Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be polled void spw_reset struct spwvars spw Resets the GRSPW Table 380 Parameters for spw_reset Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be reset void spw_rmapen struct spwvars spw Enables hardware RMAP Has no effect if the RMAP command handler is not available in GRSPW Table 381 Parameters for spw_rmapen Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be set void spw_rmapdis struct spwvars spw Disables hardware RMAP Has no effect if the RMAP command handler is not available in GRSPW Table 382 Parameters for spw_rmapdis Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be set int spw_setdestkey struct spwvars spw Set the destination key of the GRSPW Has no effect if the RMAP command handler is not available The value from the spwvars struct is used Table 383 Return values for spw_setdestkey Value Description 0 The function completed successfully 1 The destination key parameter in the spwvars struct contains an illegal value 359 Table 384 Parameters for spw_setdestkey Parameter Description Allowed range spw Po
100. BARO defining SDRAM area 0 16 FFF 16 000 Default is OxFO000000 OXFFFFFFFF hmask MASK filed of the AHB BARO defining SDRAM area 0 16 FFF 16 FOO ioaddr ADDR filed of the AHB BARI defining I O address 0 16 FFFH 16 000 space where DDR control register is mapped iomask MASK filed of the AHB BAR1 defining I O address 0 16 FFFH 16 FFFH space ddrbits Data bus width of external DDR memory 16 32 64 16 MHz DDR clock input frequency in MHz 10 200 100 clkmul clkdiv The DDR input clock is multiplied with the clkmul 2 32 2 generic and divided with clkdiv to create the final DDR clock rstdel Clock reset delay in micro seconds 1 1023 200 col Default number of column address bits 9 12 9 Mbyte Default memory chip select bank size in Mbyte 8 1024 16 pwron Enable SDRAM at power on initialization 0 1 oepol Polarity of bdrive and vbdrive signals O active low 0 1 l active high ahbfreq Frequency in MHz of the AHB clock domain 1 1023 50 rskew Additional read data clock skew 255 255 0 166 23 5 23 6 Signal descriptions Table 181 shows the interface signals of the core VHDL ports Table 181 Signal descriptions Signal name Type Function Active RST_DDR Input Reset input for DDR clock domain Low RST_AHB Input Reset input for AHB clock domain Low CLK_DDR Input DDR input Clock CLK_AHB Input AHB clock LOCK Output DDR
101. COM GRECC Elliptic Curve Cryptography Core 0x01 0x074 COM Table 11 Simulation and debugging Name Function Vendor Device License SRAM SRAM simulation model with srecord pre load COM GPL MT48LC16M16 Micron SDRAM model with srecord pre load Free MT46V16M16 Micron DDR model Free CY7C1354B Cypress ZBT SSRAM model with srecord pre load Free AHBMSTEM AHB master simulation model with scripting 0x01 0x040 COM GPL AHBSLVEM AHB slave simulation model with scripting 0x01 0x041 COM GPL AMBAMON AHB and APB protocol monitor COM Table 12 CCSDS Telecommand and telemetry functions Name Function Vendor Device License GRTM CCSDS Telemetry encoder 0x01 0x030 FT GRTC CCSDS Telecommand decoder 0x01 0x031 COM GPL GRPW Packetwire receiver with AHB interface 0x01 0x032 COM GPL GRCTM CCSDS Time manager 0x01 0x033 COM GPL NOTE The CCSDS functions are described in separate manuals 1 3 Implementation characteristics The table below shows the approximate area for some of the GRLIP IP blocks mapped on Virtex2 Actel AX and typical ASIC technologies The area depends strongly on configuration options gener ics optimization constraints and used synthesis tools The data in the table should therefore be seen as an indication only The tools used to obtain the area was Synplify 8 1 for FPGA and Synopsys DC for ASIC The LUT area for Altera Stratix devices is roughly the same as for Virtex2 Using XST instead of Synp
102. Checkbits read from memory during a read operation are written to this field when the RB bit is set 7 EN EDAC enable Run time enable disable of the EDAC functions If EDAC is disabled no error detection will be done during reads and subword writes Checkbits will still be written to memory during write operations 8 RB Read bypass Store the checkbits read from memory during a read operation into the TCB field 9 WB Write bypass Write the TCB field as checkbits into memory for all write operations cntbits 9 10 SEC Single error counter This field is available when the errent VHDL generic is set to one during synthesis It increments each time a single error is detected It saturates when the maximum value is reached The maximum value is the largest number representable in the number of bits used which in turn is determined by the cntbits VHDL generic Each bit in the counter can be reset by writing a one to it 30 cntbits 10 Reserved 31 EAV EDAC available This bit is always one if the SDRAM controller contains EDAC 28 4 28 5 215 Vendor and device identifiers The module has vendor identifier 0x01 Gaisler Research and device identifier 0x055 For a descrip tion of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 211 shows the configuration options of the core VHDL generics Table 211 Configuration options
103. Curve Cryptography ECC is used as a public key mechanism The computational burden that is inhibited by ECC is less than the one of RSA ECC provides the same level of security as RSA but with a significantly shorter key length ECC is well suited for application in mobile communica tion The GRECC core implements encryption and decryption for an elliptic curve based on 233 bit key and point lengths The implemented curve is denoted as sect233r1 or B 233 The sect233r1 elliptic curve domain parameters are specified in the Standards for Efficient Cryptog raphy SEC SEC2 Recommended Elliptic Curve Domain Parameters document The document is established by the Standards for Efficient Cryptography Group SECG The B 233 elliptic curve domain parameters are specified in the Digital Signature Standard DSS document Federal Information Processing Standards FIPS Publication 186 2 The document is established by the National Institute of Standards and Technology NIST The GRECC can be used with algorithms such as e Elliptic Curve Digital Signature Algorithm DSA ECDSA which appears in FIPS 186 2 IEEE 1363 2000 and ISO IEC 15946 2 e Elliptic Curve El Gamal Method key exchange protocol e Elliptic Curve Diffie Hellman ECDH key agreement protocol The core provides the following internal AMBA APB slave interface with sideband signals as per GRLIB including e interrupt bus e configuration information e diagnost
104. DDR data width is set by the DDRBITS generic and will affect the width of DM DQS and DQ sig nals The DDR data width does not change the behaviour of the AHB interface except for data latency 23 2 2 Read cycles An AHB read access to the controller will cause a corresponding access to the external DDR RAM The read cycle is started by performing an ACTIVATE command to the desired bank and row fol lowed by a READ command CAS latency of 2 CL 2 is always used Byte half word 16 bit and word 32 bit AHB accesses are supported Incremental AHB burst access are supported for 32 bit words only The read cycle s are always terminated with a PRE CHARGE command no banks are left open between two accesses DDR read cyles are always performed in aligned 8 word bursts which are stored in a FIFO After an initial latency the data is then read out on the AHB bus with zero waitstates 162 23 2 3 Write cycles Write cycles are performed similarly to read cycles with the difference that WRITE commands are issued after activation An AHB write burst will store up to 8 words in a FIFO before writing the data to the DDR memory As in the read case only word bursts are supported 23 2 4 Initialization If the pwron generic is 1 then the DDR controller will automatically perform the DDR initialization sequence as described in the JEDEC DDR266 standard PRE CHARGE LOAD EXTMODE REG LOAD MODE REG PRE CHARGE 2xREFRESH and LOAD MODE REG The ge
105. Default hindex AHB slave index 1 NAHBSLV 1 0 ramaddr ADDR field of the AHB BAR defining RAM address space 0 16 FFFH 16 400 Default RAM area is 0x40000000 0x40FFFFFF rammask MASK field of the AHB BAR1 defining RAM address space 0 16 FFF 16 FFO ioaddr ADDR field of the AHB BAR2 defining IO address space 0 16 FFFH 16 200 Default RAM area is 0x20000000 0x20FFFFFF iomask MASK field of the AHB BAR2 defining IO address space 0 16 FFFH 16 FFO ramws Number of waitstates during access to SRAM area 0 15 0 iows Number of waitstates during access to IO area 0 15 2 srbanks Set the number of RAM banks 1 8 1 banksz Set the size of bank 1 4 1 16 kB 15 256 MB If setto 0 15 15 zero the bank size is set with the rambsz field in the MCFG2 register pindex APB slave index 1 NAPBSLV 1 0 paddr APB address 1 16 FFF 0 pmask APB address mask 1 16 FFF 16 FFFH edacen EDAC enable If set to one EDAC logic is synthesized 0 1 0 errcnt If one a single error counter is added 0 1 0 entbits Number of bits in the single error counter 1 8 1 wsreg Enable programmable waitstate generation 0 1 0 243 30 7 Signal descriptions 244 Table 226 shows the interface signals of the core VHDL ports Table 226 Signal descriptions Signal name Field Type Function Active CLK N A Input Clock RST N A Input Reset Low Table 226 Signal descriptions 245
106. EDCL oooooocioccconoconoccnonoconononnconnnoonnnnnncconononnncnn nono nnrnnncnnnconnos 275 34 7 Media Independent Interfaces i ccis rrer a rr a r viet coc diari EREEREER EER OR e EREE aE 277 34 8 Software din R haces asap E A AAE R AEN 277 34 9 RESISTORS ui ia 278 34 10 Vendor and device identifiers yenion i i E o E E E TEE ERE EE 280 34 11 Configuration OPtiONS ooonoonnonnonnonnnoncnnninnconncnnonnncononno cono evire Ckv okb be vi nro neon concen neon SE VEC EROS VE NES VSK EPEko N EET 281 34412 Signal description tintas E E E E E E RS 282 34 13 Library dependencies soirs inoseni cacaos ciendo ad ehea ber EEEE EE EESE ike orden oasis 282 3414 O NN 282 GRETH_GBIT Gigabit Ethernet Media Access Controller MAC w EDCL 284 35 1 NA A AN 284 35 2 Opera sli detritos 284 35 3 Tx DMA Itaca OS 285 35 4 RXDMA Interface aa is 288 35 5 MUDILO Intertace e a artesa 289 35 6 Ethernet Debug Communication Link EDCL 00 eee ceceeseceeeeceseeessecenceceeeeeneeeeeeesaeceaeeceseeenaeeeneenees 290 35 7 Media Independent Interfaces ici ratas 291 35 8 ROSISTERS ai cds Sie eee ch len eect A tea Se eee 292 35 9 SoftWare EVE cri 294 ES E AAA EAT RE R EE E A EET ee 294 35 11 Configtration Options esc ccsesececcsssevces actecaceshauecs cosa dus chsauesgesca cheb SE Ee Seb eSEE SEOSTE soeke S sas sheussbessebe 295 35 12 Signal descriptions ira pia as 296 35 13 AAA A 296 33 14 instanta ON aiii 296 ETH ARB Ethernet PHY arbitra dit
107. IP Library User s Manual Configuration options Table 47 shows the configuration options of the core VHDL generics Table 47 Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 NAHBSLV 1 0 ioaddr The MSB address of the I O area Sets the 12 most sig O 16 FFF 16 000 nificant bits in the 20 bit I O address iomask The I O area address mask Sets the size of the I O area 0 16 FFF 16 E00 and the start address together with ioaddr irq Interrupt number 0 NAHBIRQ 1 tech Technology to implement on chip RAM 0 NTECH kbytes Trace buffer size in kbytes 1 64 1 58 10 6 10 7 10 8 Signal descriptions Table 48 shows the interface signals of the core VHDL ports Table 48 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBMI Input AHB master input signals AHBSI Input AHB slave input signals AHBSO E Output AHB slave output signals see GRLIB IP Library User s Manual Library dependencies Table 49 shows libraries used when instantiating the core VHDL libraries Table 49 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions GAISLER MISC Component Component declaration Component declaration library grlib use grlib amba all li
108. Input AHB master input signals AHBMO 2 Output AHB master output signals AHBSI 2 Input AHB slave input signals AHBSO 2 Output AHB slave output signals 1 see PCI specification 2 see GRLIB IP Library User s Manual The PCIO record contains an additional output enable signal VADEN It is has the same value as aden at each index but they are all driven from separate registers A directive is placed on this vector so that the registers will not be removed during synthesis This output enable vector can be used instead of aden if output delay is an issue in the design For a system host the active low PCII host signal should to be connected to the PCI SYSEN signal For a device that is not a system host this signal should have a pull up connection 50 11 Library dependencies Table 433 shows libraries used when instantiating the core VHDL libraries Table 433 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER PCI Signals component PCI signals and component declaration GAISLER PADS Components PCI pads 50 12 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib stdlib all use grlib tech all library gaisler use gaisler pci all use gaisler pads all signal apbi apb_slv_in_type 437 sign
109. Library User s Manual Configuration options Table 459 shows the configuration options of the core VHDL generics Table 459 Configuration options Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 pindex APB slave index 0 NAPBSLV 1 0 romaddr ADDR filed of the AHB BARO defining PROM address space 0 16 FFF 16 000 Default PROM area is 0x0 OXFFFFFF rommask MASK filed of the AHB BARO defining PROM address space 0 16 FFF 16 FFO ramaddr ADDR filed of the AHB BAR defining RAM address space 0 16 FFFH 16 400 Default RAM area is 0x40000000 0x40FFFFFF rammask MASK filed of the AHB BAR1 defining RAM address space 0 16 FFF 16 FFO ioaddr ADDR filed of the AHB BAR2 defining IO address space 0 16 FFFH 16 200 Default IO area is 0x20000000 0x20FFFFFF iomask MASK filed of the AHB BAR2 defining IO address space 0 16 FFF 16 FFO paddr ADDR filed of the APB BAR configuration registers address 0 16 FFFH 0 space pmask MASK filed of the APB BAR configuration registers address 0 16 FFFH 16 FFFH space oepol Polarity of bdrive and vbdrive signals O active low 1 active 0 1 0 high 469 57 6 Signal descriptions Table 460 shows the interface signals of the core VHDL ports Table 460 Signal descriptions Signal name Field Type Function Polarity CLK N A Input Clock RST N A Input Reset Low SR
110. Mees 66 12 4 Signal descripta ties 66 12 5 Library dependencies is cc c ccsceees snp reisais devoc ins aces ee erreen sob KSEI KEETE EEn CACEN Gavscebsheedpessabcescassecsoes 66 12 6 Tnstamtiation ena ria arca lt Sets a pct ir 67 APBCTRL AMBA AHB APB bridge with plug amp play support ccooococnnncccnonccnnonccinnnacinnnnos 69 13 1 O VE EW eoeou ae eo Eere eneo TE r NEEE isis 69 13 2 Operation AER EEEE ESTES oi aiii 69 13 3 APB DUS MONIHOT o oeni dns ecos reten a iii 70 13 4 Vendor and device dente cial E e 70 13 5 Configuration Options monere ap oe e aE e E E eo i eee A ee ee estes Beds 70 13 6 Signal dEscript Ons iii 70 13 7 Library dependencia ios ate 71 13 8 Component declaration c cccccccs ses cccseeag esos hevscsunsshcscbosned cediendo nacida dieses 71 13 9 Tristan tat eat ti pr 71 13 10 Debus prnt Outitg sidecases dees ies 72 APBPS2 PS 2 keyboard with APB Ita A a e ene 73 14 1 INtrOdUCHON iia ii ais 73 14 2 Receiver Opera da 73 14 3 Transmitter Opera iia ibi bros bis 74 14 4 Clock Peneration iii esd oe ae ee ee 74 14 5 ROBISLOLS iii Adenda dies es 75 14 6 Vendor and device 1dentiflers sti ist 76 14 7 Configtiration OptiONs commonccncnticcincn ds ineenda cvecs eked eke ch echek ere orr EEEE TEESE CCa TES EEEE CVELE Sb bE O SEOSKO Eraio ey 77 14 8 Signal description ica 77 14 9 Library dependencies md o ies 77 TACO Instant ti E iia 77 14 11 Keboard scan codes caciones 79 14 12 AAA NN 81 APBUART AMBA APB UART Serial I
111. ONGOING bit being 1b indicates that message reception is ongoing and that configura tion of the channel is not safe 22 9 13 Receive Channel Address Register CanRxADDR R W Table 163 Receive Channel Address Register 31 10 9 0 ADDR 31 10 ADDR Base address for circular buffer All bits are cleared to 0 at reset 22 9 14 Receive Channel Size Register CanRxSIZE R W Table 164 Receive Channel Size Register 31 21 20 6 5 0 SIZE 20 6 SIZE The size of the circular buffer is SIZE 4 messages All bits are cleared to 0 at reset Valid SIZE values are between 0 and 16384 Note that each message occupies four 32 bit words 154 Note that the resulting behavior of invalid SIZE values is undefined Note that only SIZE 4 1 messages can be stored simultaneously in the buffer This is to simplify wrap around condition checking The width of the SIZE field may be made configurable by means of a VHDL generic In this case it should be set to 16 1 bits width 22 9 15 Receive Channel Write Register CanRxWR R W Table 165 Receive Channel Write Register 31 20 19 4 3 0 WRITE 19 4 WRITE Pointer to last written message 1 All bits are cleared to O at reset The field is implemented as relative to the buffer base address scaled with the SIZE field The WRITE field is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last mess
112. PAGE regis 16 28 26 ters Defines PCI address space size fifodepth Size of each FIFO is 2 fifodepth 32 bit words gt 3 5 device_id PCI device ID number 0 16 FFE 0 vendor_id PCI vendor ID number 0 16 FFF 0 master Disables enables PCI master interface 0 1 0 slvndx The AHB index of the master backend AHB slave interface 0 NAHBSLV 1 0 apbndx The AMBA APB index for the configuration status APB inter 0 NAPBMAX 0 face 1 paddr APB interface base address 0 16 FFFH 0 pmask APB interface address mask 0 16 FFFH 16 FFFH haddr AHB slave base address 0 16 FFFH 16 FOO hmask AHB address mask 0 16 FFFH 16 FOO ioaddr AHB I O area base address 0 16 FFFH 0 irq IRQ line driven by the PCI core 0 NAHBIRQ 1 0 irqmask Specifies which PCI interrupt lines that can cause an interrupt 0 F 0 nsync The number of clock registers used by each signal that crosses 1 2 1 the clock regions oepol Polarity of pad output enable signals O active low 1 active 0 1 0 high 436 50 10 Signal description Table 432 shows the interface signals of the core VHDL ports Table 432 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input AMBA system clock PCICLK N A Input PCI clock PCI Input PCI input signals PCIO Output PCI output signals APBI 2 Input APB slave input signals APBO 2 Output APB slave output signals AHBMI 2
113. PROM banks available 1 8 1 rombanksz Sets the size of one PROM bank 1 16 kB 2 32 kB 15 0 15 15 256 MB If set to zero the bank size is set with the rombsz field in the MCFG1 register rombankszdef Sets the reset value of the rombsz register field in MCFG1 if 0 15 15 available pindex APB slave index 1 NAPBSLV 1 0 paddr APB address 1 16 FFFH 0 pmask APB address mask 1 16 FFF 16 FFF edacen EDAC enable If set to one EDAC logic is synthesized 0 1 0 errcnt If one a single error counter is added 0 1 0 entbits Number of bits in the single error counter 1 8 1 wsreg Enable programmable waitstate generation 0 1 0 prom8en Enable 8 bit PROM mode 0 1 0 rmwold Select between normal 0 and old 1 rmw behavior With the 0 1 0 normal behavior the write strobe sro wrn decoding is skipped instead all write strobes are always active only for accesses to ram when rmw is enabled With the old behavior the decoding is skipped for accesses to all areas 29 7 Signal descriptions Table 219 shows the interface signals of the core VHDL ports Table 219 Signal descriptions Signal name Field Type Function Active CLK N A Input Clock 230 Table 219 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low SRI DATA 31 0 Input Memory data High BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low WRNI 3 0 Input Not used
114. Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals Memory bus signals definitions Components FTMCTRL component Instantiation This examples shows how the core can be instantiated The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined on the example designs port map and connected to the memory controller System clock and reset are generated by GR Clock Gen erator and Reset Generator Memory controller decodes default memory areas PROM area is 0x0 Ox1FFFFFFF 1 O area is 0x20000000 0x3FFFFFFF and RAM area is 0x40000000 Ox7FFFFFFF SDRAM controller is enabled SDRAM clock is synchronized with system clock by clock generator library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all used for I O pads entity mctrl_ex is 209 port clk in std_ulogic resetn in std_ulogic pllref in std_ulogic memory bus address out std_logic_vector 27 downto 0 memory bus data inout std_logic_vector 31 downto 0 ramsn out std_logic_vector 4 downto 0 ramoen out std_logic_vector 4 downto 0 rwen inout std_logic_vector 3 downto 0 romsn gt jout std_logic_vector 3 downto 0 iosn out std_logic oen out std_logic read out std_lo
115. RETRY responses on the PCI bus are not transparent and will automatically be retried by the master PCI interface until the transfer is either finished or aborted For burst accesses only linear incremental mode is supported and is directly translated from the AMBA commands The byte enables on the PCI bus are translated from the HSIZE control AHB signal and the AHB address according to the table below Note that only WORD HALF WORD and BYTE values of HSIZE are valid Table 429 Byte enable generation HSIZE Address 1 0 CBE 3 0 00 8 bit 00 1110 00 8 bit 01 1101 00 8 bit 10 1011 00 8 bit 11 0111 01 16 bit 00 1100 01 16 bit 10 0011 10 32 bit 00 0000 If the PCI host signal is asserted active low during reset the PCI Master function will be enabled after reset Registers The core is programmed through registers mapped into APB address space Table 430 AMBA registers Address offset Register Note 0x00 Configuration Status register 0x04 BARO register Read only access from AMBA write read access from PCI see section 50 4 0x08 PAGEO register Read only access from AMBA write read access from PCI see section 50 5 0x0C BARI register Read only access from AMBA write read access from PCI see section 50 4 0x10 PAGE register 0x14 IO Map register 0x18 Status amp Command register PCI Read only access from AMBA write read a
116. Reserved 7 4 Transfer Type TTYPE Perform either PCI Memory or I O cycles 1000 memory cycles 0100 I O cycles This value drives directly HMBSEL signals on PCI Master Targets units AHB Slave interface 3 Error ERR Last transfer was abnormally terminated If set by the DMA Controller this bit will remain zero until cleared by writing 1 to it 2 Ready RDY Current transfer is completed When set by the DMA Controller this bit will remain zero until cleared by writing 1 to it 1 Transfer Direction TD 1 write to PCI 0 read form PCI 0 Start ST Start DMA transfer Writing 1 will start the DMA transfer All other registers have to be set up before setting this bit Set by the PCI Master interface when its transaction is terminated with Target Abort Writing 1 31 0 ATA Figure 215 AMBA Target Address 31 0 AMAB Target Address ATA AHB start address for the data on AMBA bus In case of error it indicated failing address 31 0 PTA Figure 216 PCI Target Address 31 0 PCI Target Address PTA PCI start address on PCI bus This is a complete 32 bit PCI address and is not further mapped by the PCI Master Target unit In case of error it indicated failing address 31 blength blength 1 0 LEN Figure 217 Length register blentgh 1 0 DMA Transfer Length LEN Number of 32 bit words to be transferred
117. SP SP Absolute value FNEGS SP SP Negate FMOVS SP SP Move Copies operand to result output SP single precision float CC condition codes ing point number NV OF UF NX floating point exceptions see section 39 2 3 DP double precision floating point number INT 32 bit integer 311 Below is a table of worst case throughput of the floating point unit Table 321 Worst case instruction timing Instruction Throughput Latency FADDS FADDD FSUBS FSUBD FMULS FMULD FSMULD FITOS FITOD FSTOL FDTOI FSTOD FDTOS FCMPS FCMPD FCMPES 8 8 FCMPED FDIVS 31 31 FDIVD 57 57 FSQRTS 46 46 FSQRTD 65 65 39 2 3 Exceptions The floating point unit detects all exceptions defined by the IEEE 754 standard This includes detec tion of Invalid Operation NV Overflow OF Underflow UF Division by Zero DZ and Inexact NX exception conditions Generation of special results such as NaNs and infinity is also imple mented 39 2 4 Rounding All four rounding modes defined in the IEEE 754 standard are supported round to nearest round to inf round to inf and round to zero 312 40 40 1 40 2 40 3 40 4 GRLFPC GRFPU Lite Floating point unit Controller Overview The GRFPU Lite Floating Point Unit Controller GRLFPC is used to attach the GRFPU Lite float ing point unit FPU to the LEON integer unit IU It performs decoding and dispatchi
118. Sets the size of the transmitter header buffers The spw_ioctl_pkt_send struct is used for transmissions through the ioctl call Se the transmission section for more information The sent variable is set by the driver when returning from the ioctl call while the other are set by the caller typedef struct unsigned int hlen char hdr unsigned int dlen char data unsigned int sent spw_ioctl_pkt_send 344 Table 340 spw_ioctl_pkt_send member descriptions Member Description hlen Number of bytes that shall be transmitted from the header buffer hdr Pointer to the header buffer dlen Number of bytes that shall be transmitted from the data buffer data Pointer to the data buffer sent Number of bytes transmitted The spw_stats struct contains various statistics gathered from the GRSPW typedef struct unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned unsigned spw_stats int int int int int int int int int int int int int int tx_link_err rx_rmap_header_crc_err rx_rmap_data_crc_err rx_eep_err rx_truncated parity_err escape_err credit_err write_sync_err disconnect_err early_ep invalid_address packets_sent packets_received Table 341 spw_stats member descriptions Member Description tx_link_err Number of link errors detected during t
119. Spec Rev 2 0 3 9 ensured together with rule 1 HSIZE must never be larger than the bus width AMBA Spec Rev 2 0 3 43 6 HADDR must be aligned to the transfer size AMBA Spec Rev 2 0 3 12 3 25 http www arm com support faqip 582 html 7 Address and controls signals can only change when hready is low if http www arm com support faqip the previous HTRANS value was IDLE BUSY or if an ERROR 487 html SPLIT or RETRY response is given http www arm com support faqip 579 html 8 Address and control signals cannot change between consecutive AMBA Spec Rev 2 0 3 9 BUSY cycles 9 Address must be related to the previous access according to HBURST AMBA Spec Rev 2 0 3 9 and HSIZE and control signals must be identical for SEQUENTIAL accesses 10 Master must cancel the following transfer when receiving an RETRY AMBA Spec Rev 2 0 3 22 response 11 Master must cancel the following transfer when receiving an SPLIT AMBA Spec Rev 2 0 3 22 response 64 Table 55 AHB master rules Rule Number Description References 12 Master must reattempt the transfer which received a RETRY response AMBA Spec Rev 2 0 3 21 http www arm com support faqip 603 html 13 Master must reattempt the transfer which received a SPLIT response AMBA Spec Rev 2 0 3 21 http www arm com support faqip 603 html 14 Master can optionally cancel the following transfer when receiving an A
120. Table 254 Key 1 Register 31 KEY 63 downto32 Table 255 Key 2 Register 31 KEY 95 downto 64 Table 256 Key 3 Register 31 KEY 127 downto 96 Table 257 Key 4 Register 31 KEY 159 downto 128 Table 258 Key 5 Register 31 KEY 191 downto 160 Table 259 Key 6 Register 31 KEY 223 downto 192 Table 260 Key 7 Register most significant 31 8 KEY 232 downto 224 33 8 2 Point X Input 0 to 7 Registers W Table 261 Point X Input 0 Register least significant 31 X 31 downto 0 Table 262 Point X Input 1 Register 31 X 63 downto32 Table 263 Point X Input 2 Register 31 X 95 downto 64 Table 264 Point X Input 3 Register 31 X 127 downto 96 Table 265 Point X Input 4 Register 31 X 159 downto 128 Table 266 Point X Input 5 Register 31 X 191 downto 160 Table 267 Point X Input 6 Register 31 X 223 downto 192 Table 268 Point X Input 7 Register most significant 31 8 X 232 downto 224 265 266 33 8 3 Point Y Input 0 to 7 Registers W Table 269 Point Y Input O Register least significant 31 Y 31 downto 0 Table 270 Point Y Input 1 Register 31 Y 63 downto32 Table 271 Point Y Input 2 Register 31 Y 95 downto 64
121. a a a Figure 80 Read cycle with BEXCN lead in data2 lead out address ea A e A T l rwen fo A A a a data bexcn P ie ONS Ne ie i IP i aE ee Figure 81 Write cycle with BEXCN Chip select iosn is not asserted in lead in cycle for io accesses 27 13 Attaching an external DRAM controller To attach an external DRAM controller RAMSN 4 should be used since it allows the cycle time to vary through the use of BRDYN In this way delays can be inserted as required for opening of banks and refresh 27 14 Output enable timing A drive signal vector for the data I O pads is provided which has one drive signal for each data bit It can be used if the synthesis tool does not generate separate registers automatically for the current technology This can remove timing problems with output delay An additional vector is used for the separate SDRAM bus 198 27 15 Registers The core is programmed through registers mapped into APB address space Table 199 FTMCTRL memory controller registers APB Address offset Register 0x0 Memory configuration register 1 MCFG1 0x4 Memory configuration register 2 MCFG2 0x8 Memory configuration register 3 MCFG3 27 15 1 Memory configuration register 1 MCFG1 Memory configuration register 1 is used to program the timing of rom and IO accesses Table 200 Memory configuration register 1
122. aE E A A 312 40 2 Fl ating Pointiegister Ml circle E EEEE ashe 312 40 3 Floating Point State Register FSR rror nnn E eE ES 312 40 4 Floating Point Exceptions and Floating Point Deferred Queue c occcoconccnicnnonconnnoncnnninncnnconnornnonnconocnnons 312 GRGPIO General Purpose VO Portis 2g adi A ee 314 41 1 OVVIE W ae a caps 314 41 2 NN 314 41 3 REGISTERS ica iii pias 314 41 4 Vendor and device identifiers ooooonnnocnoncconconoconcnnnonnnnnnnan ono non non non no nn non nono con E nono non neon nene nana nn nin TS 315 41 5 Configuration Options iii air Maen zeae 316 41 6 Signal descripta A AEA A BAR OR ee 316 41 7 Library dependencies iovesccc cieccscescsateusces isopen sveket oE onee Ire eel deevseeveee souvepsusessbensesvasstecneavesene 316 41 8 Component declaratoria 316 41 9 Tnistamtiation ooieoe OS 317 GRSPW SpaceWire codec with AHB host Interface and RMAP support eeeeeee 318 42 1 OVERVIEWS sicsceeistes a e a inet sttiaoh cteectts eet Se Ae eA a eee eae eee 318 42 2 NS 319 42 3 Link AMTELLACE vrs 320 42 4 Receiver DMA en Sine ei rosas 322 42 5 Transmitter DMA 61 Sines iii ida 326 42 6 RMA Biss is sho sca E E T 328 42 7 AMBA interface cuna aparcado EOE EEE E CE iaa OTE E EOS Ere STE KOVEK SEN espia e 332 42 8 Synthesis add hardware ici iaa E las a E E E ie Da T ESTS 333 42 9 A ART 335 42 10 Vendor and device identifiers versatil CEEE N ETENEE ESE 340 42 11 Configuration options ii A AAA ea ee 340 42 12 Sigtial
123. abria 385 44 9 Implementation 385 AA NO Clock Satan Be cada iiid 386 AAA1 A NS 388 44 12 Signal descriptions siisii iseenese EEO couch schen oE seks ev EEE E EEEE EES CESCE E E 390 44 13 Library depe E ES miii ill 390 44 14 Component declaration siina E E RE E E T EREEREER 390 LEON3FT Fault Tolerant SPARC V8 Processor 0 0ssisesssnsssnestcesednnvessondsonnesseysudesneoses oxen 392 45 1 ON ATA ERTE T 392 45 2 Register file SEU protectionis ensena ie a a A ease 392 45 3 Cache Memoria aiii iba 393 45 4 DSU memory MAP AS EAA BPE RA I A 395 45 5 Vendor and device identifers ooooconnnocnoncconconocononnnonnnnn conc conc nn cnn non nono non nono c on non nono non nn conc nn nen nace rin nan crincnns 396 45 6 Contisuration OptlOOS Lts as 396 45 7 LIMON S vito ek iA Ais eA she asda Ris hie heise i de a E EESE 396 LOGAN On chip Logie Analyzer ya ccc netic ilar AA 397 46 1 Introduce otto aa 397 46 2 O GAs Adams heen ies 397 46 3 REGISTERS aco RN 398 46 4 Graphicaliantertace con in ira ice 401 46 5 Vendor anddevice 1dentiHers iria lid 401 46 6 Configuration Options vo iran ato ita teers eden ashes ety 401 46 7 Signal descriptions nissen enaa en te catalina ainia ty teen sone esta cabos 402 46 8 Elbrary dependencias rte 402 46 9 Instant a A E 402 MCTRL Combined PROM IO SRAM SDRAM Memory Controller oooonnnnccnnonccnnnncc 404 47 1 Over e Wise 404 47 2 PROM access waa 404 47 3 Memory mapped UV Olvido at 406 47 4 SRAMacCesS ii
124. accesses The AHB accesses are always word accesses HSIZE 0x010 of type incremental burst with unspec ified length HBURST 0x001 if rmap and rxunaligned are disabled Otherwise the accesses can be of size byte halfword and word HSIZE 0x000 0x001 0x010 Byte and halfword accesses are always NONSEQ The burst length will be half the AHB FIFO size except for the last transfer for a packet which might be smaller Shorter accesses are also done during descriptor reads and status writes The AHB master also supports non incrementing accesses where the address will be constant for sev eral consecutive accesses HTRANS will always be NONSEQ in this case while for incrementing accesses it is set to SEQ after the first access This feature is included to support non incrementing reads and writes for RMAP If the GRSPW does not need the bus after a burst has finished there will be one wasted cycle HTRANS IDLE BUSY transfer types are never requested and the core provides full support for ERROR RETRY and SPLIT responses Synthesis and hardware 42 8 1 Clock generation Figure 143 shows the clock recovery scheme for the receiver Data and strobe are coupled directly from their pads to an xor gate which generates the clock The output from the xor is then connected to a clock network The specific type of clock network depends on the technology used The xor gate is actually all that logically belongs to the Rx clock recovery module i
125. adoro aa 407 47 5 8 bit and 16 bit PROM and SRAM acces coococccconconconnconocnnonnnnnncnnnnnnnncrononn non nonnnon nc onn cn non nero nennnonnnnncrnss 408 47 6 Burst cycles ici it is 409 47 7 S and 16 bit O accessisse nsr cion one ireo eu scucus taa darian EVE EN OORSEE CTE aS OE EE ASE sp eeustasueesonsees 410 47 8 SDRAM ACCESS eai E E E E E E E A E E E A SE 410 47 9 A A a eee See a eek E A EE EE 410 47 10 Using busieady signalini snpra tpi eenaa e ie E E E E N OSEERE a TENE Ee 411 12 48 49 50 51 52 ATAT ACCESO uri eeetauteusen tideee seta A E E E 412 47 12 Attaching an external DRAM controller oo eee eeeeceneeeseceeecaecseesaeceecsecseceseseseaeeseseaeseeeeaaesaes 413 O O NAO 413 A IA AAA res gpeece er E E E E a T EEEa 415 AT AS Configuration Options rita ae 2 hs 416 A716 Signal dESCHPUONS caera ld its 416 ARIF Etbrary dependencies uc ks ee 418 47 18 A he diseven cs hota ous cates ona ch sence coca dete VEEE EEEE EESO CE EE S E 418 MUL32 Signed unsigned 32x32 multiplier module ooooococnnococnnocacinacccnnncnonnncconanacinnncnnnnos 421 48 1 OVGLVICWiii sete hie a SU ides oe aaclaied ten ty esl devas tae ete eh Sa eee ee eee aa 421 48 2 NO 421 48 3 O A NO 421 48 4 Configuration Options vmvinccnocncasnencnasotenecio no reneste vEt sker susebunnenessdpsnbeneosausntescebsseveeesopvay eoapsene nbesbassnecneaonsess 422 48 5 Sigtial de sCPUOUS isso 423 48 6 Library dependencies c 2o3 ain do A 423 48 7 Component de
126. ahb_slv_in type out ahb_slv_out_type in apb_slv_in_type out apb_slv_out_type in memory_in_type out memory_out_type This example shows how the core can be instantiated The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined in the example designs port map and connected to the memory controller System clock and reset are generated by the Clkgen_m1401 Clock Generator and GR Reset Generator The memory controller decodes default memory areas PROM area is 0x0 OXOOFFFFFF I O area is 0x20000000 0x20FFFFFF and RAM area is 0x40000000 Ox40FFFFFF library ieee use ieee std_logic_1164 all library grlib techmap use grlib amba all use grlib stdlib all use techmap gencomp all library gaisler use gaisler memctrl all use gaisler misc all entity ssrctrl_ex is port 472 sys stan an std ulogica sys_clk in std_ulogic 100 MHz main clock sram_flash_addr out std_logic_vector 22 downto 0 sram_flash_data inout std_logic_vector 31 downto 0 sram_cen out std_logic sram_bw out std_logic_vector 0 to 3 sram_flash_oe_n out std_ulogic sram_flash_we_n out std_ulogic flash_ce out std_logic sram_clk out std_ulogic sram_clk_fb in std_ulogic sram_mode out std_ulogic sram_adv_ld_n out std_ulogic sram_zz out std_ulogic iosn out std_ulogic i end
127. an illegal value SET_DESTKEY This call sets the destination key It can only be used if the RMAP command handler is available The argument must be an integer in the range 0 to 255 The call will fail if the argument contains an illegal value if the RMAP command handler is not available or if the register cannot be written SET_CLKDIV This call sets the clock division factor used in the run state The argument must be an integer in the range 0 to 255 The call will fail if the argument contains an illegal value or if the register cannot be written 348 SET_TIMER This call sets the counter used to generate the 6 4 and 12 8 us time outs in the link interface FSM The argument must be an integer in the range 0 to 4095 The call will fail if the argument contains an ille gal value or if the register cannot be written SET_DISCONNECT This call sets the counter used to generate the 850 ns disconnect interval in the link interface FSM The argument must be an integer in the range 0 to 1023 The call will fail if the argument contains an illegal value or if the register cannot be written SET_PROMISCUOUS This call sets the promiscuous mode bit The argument must be an integer in the range 0 to 1 The call will fail 1f the argument contains an illegal value or if the register cannot be written SET_RMAPEN This call sets the RMAP enable bit It can only be used if the RMAP command handler is available The argument must be an integer
128. are presented in the figures hereafter datal lead out datai lead out are romsn r NY Ny lo ramsn oen PA Ie pe ae A a gt j CBA ww Tar Xe Xs TT mee IT 00 hready i PX 1X 4 Figure 92 PROM SRAM non consecutive read cyclecs clk address romsn ramsn oen data cb haddr htrans hready hrdata datai datai datal datai lead out AR A gt O LO DO 0 TE E E CB1 XCB2 XCB3 XCB4 Ai r5 10 00 Figure 93 32 bit PROM SRAM sequential read access with 0 wait states and EDAC disabled clk address romsn ramsn oen data cb haddr htrans hready hrdata Figure 94 datai data2 lead out datai data2 lead out Papel Se A T AI O E Ti 1 gt w 2 o o XE jo IS TE 32 bit PROM SRAM non sequential read access with O wait states and EDAC enabled 223 224 clk address romsn ramsn oen data cb haddr htrans hready hrdata datai datai datal datai lead out CB1 XCB2 CB4 70 00 Figure 95 32 bit PROM SRAM sequential read access with O wait states and EDAC enabled clk address romsn ramsn writen data cb haddr htrans hready hwdata lead in datai data2 lead out lead in datal data2 lead out MPI QA Xx X ael Palio AN AAA MI a Nee T i Figure 9
129. asserted writen and rwen are clocked on the falling edge When a bus exception is detected an error response will be generated for the access data lead out address Seen NS O A a oy ie oen P NY FP Pp data bexcn Pra ei i FO Pe Figure 89 Read cycle with BEXCN lead in datai data2 data3 lead out ore A si WN hte is ele oe ele rwen rf re of ee Oh OCU a ice an bexcn Roh oh INS ep ie e Figure 90 Write cycle with BEXCN 29 2 3 Using bus ready signalling The Bus Ready BRDYN signal can be used to add waitstates to I O area accesses It is enabled by setting the Bus Ready Enable BRDYEN bit in the MCFGI register An access will have at least the amount of waitstates set with the VHDL generic or through the register but will be further stretched until BRDYN is asserted Additional waitstates can thus be inserted by de asserting the BRDYN sig nal BRDYN should be asserted in the cycle preceding the last one Read accesses will have the same 222 timing as when EDAC is enabled while write accesses will have the timing as for single accesses even 1f bursts are performed data data address iosn Ty Realty PF of O We oen NA eee Oo ie lee data brdyn PIA if oe O A Figure 91 READ cycle with one extra data cycle added with BRDYN 29 3 PROM SRAM IO waveforms The internal and external waveforms of the interface
130. background information on ellip tic curve cryptography and recommendations for ECC parameter and curve selection The Federal Information Processing Standards Publication Series of the National Institute of Stan dards and Technology NIST is the official series of publications relating to standards and guidelines adopted under the provisions of the Information Technology Management Reform Act This Digital Signature Standard DSS specifies a suite of algorithms which can be used to generate a digital signature Digital signatures are used to detect unauthorized modifications to data and to authenticate the identity of the signatory In addition the recipient of signed data can use a digital sig nature in proving to a third party that the signature was in fact generated by the signatory This is known as nonrepudiation since the signatory cannot at a later time repudiate the signature 233 bit elliptic curve domain parameters The core implements the 233 bit elliptic curve domain parameters sect233rl or the equivalent B 233 which are verifiably random parameters The following specification is established in Standards for Efficient Cryptography SEC SEC 2 Recommended Elliptic Curve Domain Parameters The veri fiably random elliptic curve domain parameters over Fm are specified by the septuple T m f x a b G n h where m 233 and the representation of F233 is defined by f x x3 4x74 41 The curve E y xy x a 00
131. be in another state than IDLE SETUP ENABLE AMBA Spec Rev 2 0 5 4 5 PADDR must be stable during transition from SETUP to ENABLE AMBA Spec Rev 2 0 5 5 6 PWRITE must be stable during transition from SETUP to ENABLE AMBA Spec Rev 2 0 5 5 7 PWDATA must be stable during transition from SETUP to ENABLE AMBA Spec Rev 2 0 5 5 8 Only one PSEL must be enabled at a time AMBA Spec Rev 2 0 5 4 9 PSEL must be stable during transition from SETUP to ENABLE AMBA Spec Rev 2 0 5 5 Table 58 Arbiter rules Rule Number Description References 1 HreadyIn to slaves and master must be driven by the currently selected http www arm com support faqip device 482 html 2 A master which received a SPLIT response must not be granted the AMBA Spec Rev 2 0 3 35 bus until the slave has set the corresponding HSPLIT line 66 12 3 12 4 12 5 Configuration options Table 59 shows the configuration options of the core VHDL generics Table 59 Configuration options Generic Function Allowed range Default asserterr Enable assertions for AMBA requirements Violations 0 1 1 are asserted with severity error assertwarn Enable assertions for AMBA recommendations Viola 0 1 1 tions are asserted with severity warning hmstdisable Disable AHB master rule check To disable a master rule 0 check a value is assigned so that the binary represe
132. bit mode 27 6 8 and 16 bit I O access Similar to the PROM SRAM areas the IO area can also be configured to 8 or 16 bits mode How ever the I O device will NOT be accessed by multiple 8 16 bits accesses as the memory areas but 192 27 7 27 8 only with one single access just as in 32 bit mode To access an IO device on an 8 bit bus only byte accesses should be used LDUB STB instructions for the CPU To accesses an IO device on a 16 bit bus only halfword accesses should be used LDUH STH instructions for the CPU To access the I O area in 8 or 16 bit mode ram8 or ram16 must be set respectively Burst cycles To improve the bandwidth of the memory bus accesses to consecutive addresses can be performed in burst mode Burst transfers will be generated when the memory controller is accessed using an AHB burst request These includes instruction cache line fills double loads and double stores The timing of a burst cycle is identical to the programmed basic cycle with the exception that during read cycles the lead out cycle will only occurs after the last transfer Burst cycles will not be generated to the IO area Only word HSIZE 010 bursts of incremental type HBURST INCR INCR4 INCR8 or INCR16 are supported SDRAM access 27 8 1 General Synchronous dynamic RAM SDRAM access is supported to two banks of PC100 PC133 compati ble devices This is implemented by a special version of the SDCTRL SDRAM controll
133. bit is set to 1b a reset of the core is performed The reset clears all the register fields to their default values Any ongoing CAN message transfer request will be aborted potentially violating the CAN protocol When the CanCTRL ENABLE bit is cleared to Ob the CAN core is reset and the configuration bits CanCONF SCALER CanCONF PS1 CanCONF PS2 CanCONF RSJ and CanCONFBPR may be modified When disabled the CAN controller will be in sleep mode not affecting the CAN bus by only sending recessive bits Note that the CAN core requires that 10 recessive bits are received before any reception or transmission can be initiated This can be caused either by no unit sending on the CAN bus or by random bits in message transfers Interrupt Three interrupts are implemented by the CAN interface Index Name Description 0 IRQ Common output from interrupt handler 1 TxSYNC Synchronization message transmitted 2 RxSYNC Synchronization message received The interrupts are configured by means of the pirg VHDL generic 148 22 9 Registers The core is programmed through registers mapped into APB address space Table 150 GRCAN registers APB address offset Register 16 000 Configuration Register 16 004 Status Register 16 008 Control Register 16 018 SYNC Mask Filter Register 16 01C SYNC Code Filter Register 16 100 Pending Interrupt Masked Status Registe
134. bits of the AMBA address byte address determine which half word that should be transferred to the I O device i e If the byte address is 0 and it is an 32 bit access bits 16 to 31 on the AHB bus is transferred on the 16 bit mem ory bus If the byte address is 2 and it is an 16 bit access bit 0 to 15 on the AHB bus is transferred on the 16 bit memory bus If the access is an 8 bit access the data is transferred on data lines 8 to 15 Data 15 8 on the memory bus In case of a write data lines 0 to 7 is also written to the I O device but these data lines does not transfer any valid data 30 2 3 Using Bus Exception The active low Bus Exception signal BEXCN can be used to signal access errors It is enabled by setting the BEXCEN bit in MCFG1 and is only active for the I O area The BEXCN signal is sampled on the same cycle as data is written to memory or read data is sampled When a bus exception is detected an error response will be generated for the access One additional latency cycle is added to the AMBA access when Bus Exception is enable 30 2 4 Using Bus Ready The Bus Ready BRDYN signal can be used to add waitstates to I O area accesses It is enabled by setting the Bus Ready Enable BRDYEN bit in the MCFG1 register An access will have at least the amount of waitstates set with the VHDL generic or through the register but will be further stretched until BRDYN is asserted Additional waitstates can thus be inserted by deasserting
135. checkbits of the loaded data will be stored in the TCB field dur ing memory read cycles NOTE when the EDAC is enabled the RMW bit in memory configuration register 2 must be set EDAC is not supported for 64 bit wide SDRAM data busses Bus Ready signalling The BRDYN signal can be used to stretch access cycles to the PROM I O area and the SRAM area decoded by RAMSN 4 The accesses will always have at least the pre programmed number of wait states as defined in memory configuration registers 1 amp 2 but will be further stretched until BRDYN is asserted BRDYN should be asserted in the cycle preceding the last one If bit 29 in MCFG1 is set BRDYN can be asserted asynchronously with the system clock In this case the read data must be kept stable until the de assertion of OEN RAMOEN and BRDYN must be asserted for at least 1 5 clock cycle The use of BRDYN can be enabled separately for the PROM I O and RAMSN 4 areas datai data2 data2 lead out clk We AA AA NSE NAS SNA SANI NS NON address A E A CO e oen AL e 1 1 O E data AS ie lt a Figure 77 READ cycle with one extra data2 cycle added with BRDYN synchronous sampling Lead out cycle is only applicable for I O accesses 196 Figure 78 shows the use of BRDYN with asynchronous sampling BRDYN is kept asserted for more than 1 5 clock cycle Two synchronization registers are used so it will take at least one additional cycle from when BRDYN is fi
136. clock divisor value is 8 bits wide so the maximum txclk frequency supported is 2 56 GHz note that there is also a restriction on the relation between the system and transmit clock frequencies 42 8 2 Timers There are two timers in the grpsw one for generating the 6 4 12 8 us periods and one for disconnect timing The system clock frequency must be at least 10 MHz to guarantee disconnect timing limits There are two user accessible registers which are used to the set the number of clock cycles used for the timeout periods These registers are described in section 42 9 The reset value for the timer registers can be set in two different ways selected by the usegen VHDL generic If usegen is set to 1 the sysfreq VHDL generic is used to generate reset values for the discon nect 6 4 us and 12 8 us timers Otherwise the input signals dcrstval and timerrstval will be used as reset values If the system clock frequency is 10 MHz or above the disconnect time will be within the limits specified in the SpaceWire standard 42 8 3 Synchronization The VHDL generic nsync selects how many synchronization registers are used between clock domains The default is one and should be used when maximum performance is needed It allows the transmitter to be clocked 4 times faster than the system clock and the receiver 2 times faster These are theoretical values without consideration for clock skew and jitter Note also that the receiver clocks data at both nega
137. core which will be associated with g 232 1 the struct passed to the function int spw_init struct spwvars spw Initializes the GRSPW core located at the address set in the struct spw Sets the following registers node address destination key clock divisor receiver maximum length transmitter descriptor table address receiver descriptor table address ctrl and dmactrl All bits are set to the values found in the spwvars struct If a register bit is not present in the struct it will be set to zero The descriptor tables are allocated to an aligned area using malloc The status register is cleared and lastly the link interface is enabled The run state frequency will be set according to the value in clkdiv Table 350 Return values for spw_init Value Description 0 The function completed successfully 1 One or more of the parameters could not be set correctly or the link failed to initialize Table 351 Parameters for spw_init Parameter Description Allowed range spw The spwvars struct associated with the GRSPW core that should be initialized int set_txdesc int pnt struct spwvars spw Sets a new address to the transmitter descriptor table address register Should only be used when no transmission is active Also resets the pointers for spw_tx and spw_checktx Explained in the section for those functions Table 352 Return values for spw_txdesc Value Description 0 Th
138. data allocation Bits Name Definition 127 96 Time tag The value of the time tag counter 95 AHB breakpoint hit Set to 1 if a DSU AHB breakpoint hit occurred 94 80 Hirq AHB HIRQ 15 1 79 Hwrite AHB HWRITE 78 77 Htrans AHB HTRANS 76 74 Hsize AHB HSIZE 73 71 Hburst AHB HBURST 70 67 Hmaster AHB HMASTER 66 Hmastlock AHB HMASTLOCK 65 64 Hresp AHB HRESP 63 32 Load Store data AHB HRDATA or HWDATA 31 0 Load Store address AHB HADDR In addition to the AHB signals a 32 bit counter is also stored in the trace as time tag Operation The trace buffer is enabled by setting the enable bit EN in the trace control register Each AMBA AHB transfer is then stored in the buffer in a circular manner The address to which the next transfer is written is held in the trace buffer index register and is automatically incremented after each transfer Tracing is stopped when the EN bit is reset or when a AHB breakpoint is hit An interrupt is gener ated when a breakpoint is hit Note the LEON3 Debug Support Unit DSU3 also includes an AHB trace buffer The trace buffer is intended to be used in system without the LEON3 processor or when the DSU3 is not present The size of the trace buffer is configured by means of the kbytes VHDL generic defining the size of the complete buffer in kbytes 56 10 3 The size of the trace buffer is TBD kbyte with the resulting line depth of TBD 16 kbyte
139. dcache context access 0x15 MMU diagnostic icache context access 0x19 MMU registers Ox1C MMU bypass 0x1D MMU diagnostic access 44 6 2 Cache operation When the MMU is disabled the caches operate as normal with physical address mapping When the MMU is enabled the caches tags store the virtual address and also include an 8 bit context field For snooping to work bit 2 of the dsnoop generic has to be set This will add extra RAM to save the phys ical tag along with the virtual tag On a SMP system with a virtual address space this is needed for snooping to work on the physical AHB bus if the MMU is enabled In addition for snooping to work if the MMU is enabled the cache size has to be less or equal 4k equivalent to 1 page size so that the tag offset is equal for the physical and virtual address of a translation Because the cache is virtually tagged no extra clockcycles are needed in case of a cache load hit In case of a cache miss or store hit write through cache at least 2 extra clock cycles are used if there is a TLB hit If there is a TLB miss the page table must be traversed resulting in up to 4 AMBA read 44 7 383 accesses and one possible writeback operation If a combined TLB is used by the instruction cache the translation is stalled until the TLB is free 44 6 3 MMU registers The following MMU registers are implemented Table 398 MMU registers ASI 0x19 Address Register 0x000
140. descriptions VHDL ports Signal name Field Type Function Active RST Input Reset Low HCLKM Input AHB master bus clock HCLKS Input AHB slave bus clock AHBSI T Input AHB slave input signals AHBSO 7 Output AHB slave output signals AHBMI Input AHB master input signals AHBMO Output AHB master output signals AHBSO2 Input AHB slave input signals SLOCKI Input Used in systems with multiple AHB AHB High bridges e g bi directional AHB AHB bridge to detect dead lock condition Tie to 0 in systems with only uni directional AHB AHB bus BLOCKI Input See SLOCKI High SLOCKO Output Indicates possible dead lock condition High BLOCKO Output Indicates possible dead lock condition High see GRLIB IP Library User s Manual Library dependencies Table 18 shows the libraries used when instantiating the core VHDL libraries Table 18 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler misc all entity ahb2ahb_ex is port clk in std_ulogic rstn in std_ulogic A other signals i end architecture rtl of ahb2ahb_ex is constant NCPU integer 4
141. descriptor read the selector will increase with 8 and eventually wrap to zero again Reset value 0 Descriptor table base address Sets the base address of the descriptor table Not reset Figure 154 GRSPW receiver descriptor table address register 42 10 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x1F For description of vendor and device identifiers see GRLIB IP Library User s Manual 42 11 Configuration options Table 335 shows the configuration options of the core VHDL generics Table 335 Configuration options Generic Function Allowed range Default tech Technology for fifo memories 0 NTECH inferred hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr Addr field of the APB bar 0 16 FFFH 0 pmask Mask field of the APB bar 0 16 FFFH 16 FFFH pirq Interrupt line used by GRSPW 0 NAHBIRQ 1 0 sysfreq Frequency of clock input clk in kHz 10000 usegen Use values calculated from sysfreq generic as reset values 0 1 1 for 6 4 us timer and disconnect timer nsync Number of synchronization registers 1 2 1 rmap Include hardware RMAP command handler RMAP CRC 0 1 0 logic will also be added rmapcrc Enable RMAP CRC logic 0 1 0 fifosizel Sets the number of entries in the 32 bit receiver and trans 4 32 32 mitter AHB fifos fifosize2 Sets the number
142. ee oia 438 51 2 Opera E Ea S RA KE EEE tasas 438 51 3 GA RR OS 439 51 4 Vendor and device Id titi 440 51 5 Confieuration options e dt dira dps 440 51 6 Signal desciiption ssc cei cceescvssvesdes ip heveeseschssaces dree se tious EE VEEE eub dentarias dei Seis 440 51 7 Elbrary dependencies seson vate iia din ciendo cede pias 440 51 8 Ipstantiation esee oreen reon er ena nE a EEEE ea rE ok VEEE NOPE eS EEDE S eE KETSE EE ESEESE EO Ere STE KESSENS EEANN iN 441 PCITARGET Simple 32 bit PCI target with AHB interface oooococnnocccnncccnoonncononacinnncnnnnos 442 52 1 NANA Aan EEAS RA FAAEA EAEAN EEE EAI AE ASEE ETNA EAA AEA CEAN AA 442 53 54 55 56 57 52 2 RESISTORS cocinaba 442 52 3 Vendor and device Identifier cocos tiros cestbscsdecatesdessvca ds era E na set ESIE dee s ke biel SEKE ER EEIE ii 442 52 4 CA E NN 443 52 5 Signal descripta Actions 443 52 6 Library dependencia A 443 PHY Ethernet PHY simulation model iia in eii ita 444 53 1 OVA VW isa R E TE E a TE E E NS 444 53 2 Operations s aa 444 53 3 COND ISULatiON Options er rar dai tt 445 53 4 SignalidescrptOOS EEEE EEA teca 446 53 5 Library dependencies msvoconeioicainordasneendserinnnsdn ios eiroet eneber KEETE Eeh CCSS deidades decide 446 53 6 Instantia RR 446 REGFILE_3P 3 port RAM generator 2 read 1 write oooooonnccnnnccnococonncnoncnannnonnncno nono ncnnos 448 54 1 OV EII Wisoic liada did cases aE O eE S 448 54 2 ContiSUFAION Opt cosido e aiii 448 54 3 Si
143. examples shows how the core can be instantiated The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined on the example designs port map and connected to the memory controller System clock and reset are generated by GR Clock Gen erator and Reset Generator 463 Memory controller decodes default memory areas PROM area is 0x0 OXFFFFFF and SRAM area is 0x40000000 Ox40FFFFF The 8 bit PROM mode is disabled Two SRAM banks of size 64 Mbyte are used and the fifth chip select is disabled library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all used for I O pads use gaisler misc all library esa use esa memoryctrl all entity srctrl_ex is port clk in std ulogi resetn in std_ulogic pllref in std_ulogic memory bus address out std_logic_vector 27 downto 0 memory bus data inout std_logic_vector 31 downto 0 ramsn out std_logic_vector 4 downto 0 ramoen out std_logic_vector 4 downto 0 rwen inout std_logic_vector 3 downto 0 romsn out std_logic_vector 1 downto 0 iosn out std_logic oen out std_logic read x out std_logic writen inout std_logic brdyn t Sin std_logic bexcn in std_logic modesel in std_logic PROM width select sdram 1 f sdck
144. field 0 65535 addr Sets the address of the operation to be performed The extended 0 232 4 address field is currently always set to 0 len The number of bytes to be writte read or read modify written 0 224 4 status Sets the status field 0 11 dstspalen Number of source path address bytes to insert before the destination 0 228 address dstspa Pointer to memory holding the destination path address bytes srespalen Number of source path address bytes to insert in a command Fora _ 0 12 reply these bytes are placed before the return address srcspa Pointer to memory holding the source path address bytes 361 362 43 43 1 43 2 IRQMP Multiprocessor Interrupt Controller Overview The AMBA system in GRLIB provides an interrupt scheme where interrupt lines are routed together with the remaining AHB APB bus signals forming an interrupt bus Interrupts from AHB and APB units are routed through the bus combined together and propagated back to all units The multipro cessor interrupt controller core is attached to AMBA bus as an APB slave and monitors the combined interrupt signals The interrupts generated on the interrupt bus are all forwarded to the interrupt controller The interrupt controller prioritizes masks and propagates the interrupt with the highest priority to the processor In multiprocessor systems the interrupts are propagated to all processors Interrupt level Interrupt
145. field is reset after command has been executed 17 PLL Reset This bit is used to set the PLL RESET bit during LOAD CONFIG REG commands 16 Initialize IN Set to 1 to perform power on DDR RAM initialisation Is automatically cleared when initialisation is completed 15 Clock enable CE This value is driven on the CKE inputs of the DDR RAM Should be set to 1 for correct operation 14 0 The period between each AUTO REFRESH command Calculated as follows tREFRESH reload value 1 SYSCLK Table 179 SDRAM configuration register SDCFG 31 14 12 11 0 reserved Data width DDR Clock frequency 14 12 DDR data width 001 16 bits 010 32 bits 011 64 bits read only 11 0 Frequency of the external DDR clock read only 23 3 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x025 For description of vendor and device identifiers see GRLIB IP Library User s Manual 23 4 Configuration options Table 180 shows the configuration options of the core VHDL generics Table 180 Configuration options Generic Function Allowed range Default fabtech PHY technology selection virtex2 virtex4 virtex2 spartan3e altera memtech Technology selection for DDR FIFOs infered virtex2 virtex4 infered spartan3e altera hindex AHB slave index 0 NAHBSLV 1 0 haddr ADDR filed of the AHB
146. for io accesses Attaching an external DRAM controller To attach an external DRAM controller MEMO RAMSN 4 should be used since it allows the cycle time to vary through the use of MEMI BRDYN In this way delays can be inserted as required for opening of banks and refresh Registers The memory controller is programmed through registers mapped into APB address space Table 414 Memory controller registers APB address offset Register 0x0 MCFG1 0x4 MCFG2 0x8 MCFG3 414 47 13 1 Memory configuration register 1 MCFG1 Memory configuration register 1 is used to program the timing of rom and local I O accesses Table 415 Memory configuration register 1 31 29 28 27 26 25 24 23 20 19 18 RESERVED IOBUSW IBRDY BEXCN IO WAITSTATES IOEN 12 11 10 9 8 T 4 3 0 RESERVED PWEN PROM WIDTH PROM WRITE WS PROM READ WS 31 29 RESERVED 28 27 T O bus width IOBUSW Sets the data width of the I O area 00 38 01 16 10 32 26 T O bus ready enable IBRDY Enables bus ready BRDYN signalling for the I O area Reset to 0 25 Bus error enable BEXCN Enables bus error signalling Reset to 0 24 RESERVED 23 20 T O waitstates IO WAITSTATES Sets the number of waitstates during I O accesses 0000 0 0001 1 0010 2 1111 15 19 T O enable IOEN Enables accesses to the memory
147. for registration An example application using the driver called rtems spwtest is provided in the Gaisler Research RTEMS distribution 343 42 15 1 Driver registration The function spacewire_register whose prototype is provided in spacewire h is used for registering the driver It returns 0 on success and 1 on failure 42 15 2 Opening the device After the driver is registered the device should be opened next It is done with the open call An exam ple of a open call is shown below fd open dev spacewire O_RDONLY A file descriptor is returned on success and 1 otherwise In the latter case errno is set Table 338 Open errno values ERRNO Description EINVAL Illegal device name or not available EIO Error when writing to grspw registers ETIMEDOUT Link did not startup 42 15 3 Closing the device The device is closed using the close call An example is shown below res close fd Close always returns 0 success for the Spacewire driver 42 15 4 Data structures The spw_ioctl_packetsize struct is used when changing the size of the drivers receive and transmit buffers typedef struct unsigned int rxsize unsigned int txdsize unsigned int txhsize spw_ioctl_packetsize Table 339 spw_ioctl_packetsize member descriptions Member Description rxsize Sets the size of the receiver descriptor buffers txdsize Sets the size of the transmitter data buffers txhsize
148. generics Table 235 Configuration options Generic Function Allowed range Default pindex Selects which APB select signal PSEL will be used to 0 to NAPBMAX 1 0 access the timer unit paddr The 12 bit MSB APB address 0 to 4095 0 pmask The APB address mask 0 to 4095 4095 nbits Defines the number of bits in the timers 1 to 32 32 ntimers Defines the number of timers in the unit 1to7 1 pirq Defines which APB interrupt the timers will generate 0 to MAXIRQ 1 sepirq If set to 1 each timer will drive an individual interrupt 0 to MAXIRQ 1 line starting with interrupt irq If set to 0 all timers will note ntimers irq must drive the same interrupt line irq be less than MAXIRQ sbits Defines the number of bits in the scaler 1 to 32 16 wdog Watchdog reset value When set to a non zero value the O y 2s _ 1 0 last timer will be enabled and pre loaded with this value at reset When the timer value reaches 0 the WDOG out put is driven active Signal descriptions Table 236 shows the interface signals of the core VHDL ports Table 236 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO i Output APB slave output signals GPTI DHALT Input Freeze timers High EXTCLK Input Use as alternative clock GPTO TICK 0 7 Output Timer ticks TICK O is high for one clock each High ti
149. gt 1 pwron gt 1 MHz gt 100 col gt 9 Mbyte gt 32 ahbfreq gt 50 ddrbits gt 64 port map rstneg rstn lclk clkm lock clkml clkml ahbsi ahbso 4 ddr crk ddr_clkb ddr_clk_fb_out ddr_clk_fb ddr_cke ddr_csb ddr_web ddr_rasb ddr_casb ddr_dm ddr dgs ddr_adl ddr ba ddr da 24 24 1 24 2 24 3 169 DIV32 Signed unsigned 64 32 divider module Overview The divider module performs signed unsigned 64 bit by 32 bit division It implements the radix 2 non restoring iterative division algorithm The division operation takes 36 clock cycles The divider leaves no remainder The result is rounded towards zero Negative result zero result and overflow according to the overflow detection method B of SPARC V8 Architecture manual are detected Operation The division is started when 1 is samples on DIVI START on positive clock edge Operands are latched externally and provided on inputs DIVI Y DIVI OP1 and DIVI OP2 during the whole opera tion The result appears on the outputs during the clock cycle following the clock cycle after the DIVO READY was asserted Asserting the HOLD input at any time will freeze the operation until HOLDN is de asserted Signal descriptions Table 183 shows the interface signals of the core VHDL ports Table 183 Signal declarations Signal name Field Type Function Active RST N A Inpu
150. if the wsreg VHDL generic is set to one Table 217 Memory configuration register 3 31 20 19 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SEC WB RB SE PE TCB 31 20 RESERVED 19 12 Single error counter SEC This field increments each time a single error is detected until the max imum value that can be stored in the field is reached Each bit can be reset by writing a one to it 11 Write bypass WB Enables EDAC write bypass When enabled the TCB field will be used as checkbits in all write operations 10 Read bypass RB Enables EDAC read bypass When enabled checkbits read from memory in all read operations will be stored in the TCB field SRAM EDAC enable SE Enables EDAC for the SRAM area PROM EDAC enable PE Enables EDAC for the PROM area Reset value is taken from the input signal sri edac 7 0 Test checkbits TCB Used as checkbits in write operations when WB is activated and checkbits from read operations are stored here when RB is activated All the fields in MCFG3 register are available if the edacen VHDL generic is set to one except SEC field which also requires that the errent VHDL generic is set to one The exact breakpoint between the SEC and RESERVED field depends on the cntbits generic The breakpoint is 11 cntbits The values shown in the table is for maximum cntbits value 8 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x051 For description of vendor
151. in the range 0 to 1 The call will fail if the argument contains an ille gal value if the RMAP command handler is not available or if the register cannot be written SET_RMAPBUFDIS This call sets the RMAP buffer disable bit It can only be used if the RMAP command handler is available The argument must be an integer in the range 0 to 1 The call will fail if the argument con tains an illegal value if the RMAP command handler is not available or if the register cannot be writ ten SET_CHECK_RMAP This call selects whether or not RMAP CRC should be checked for received packets If enabled the header CRC error and data CRC error bits are checked and if one or both are set the packet will be dis carded The argument must be an integer in the range 0 to 1 0 disables and 1 enables the RMAP CRC check The call will fail if the argument contains an illegal value SET_RM_PROT_ID This call selects whether or not the protocol ID should be removed from received packets It is assumed that all packets contain a protocol ID so when enabled the second byte the one after the node address in the packet will be removed The argument must be an integer in the range 0 to 1 0 disables and 1 enables the RMAP CRC check The call will fail if the argument contains an illegal value SET_TXBLOCK This call sets the blocking mode for transmissions The argument must be an integer in the range 0 to 1 O selects non blocking mode while 1 selects blocking mode
152. in the trace buffer index register and is automatically incremented after each transfer Trac ing is stopped when the EN bit is reset or when a AHB breakpoint is hit Tracing is temporarily suspended when the processor enters debug mode Note that neither the trace buffer memory nor the breakpoint registers see below can be read written by software when the trace buffer is enabled 25 4 173 Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores executed instructions The instruc tion trace buffer is located in the processor and read out via the DSU The trace buffer is 128 bits wide the information stored is indicated in the table below Table 186 Instruction trace buffer data allocation Bits Name Definition 127 Unused 126 Multi cycle instruction Set to 1 on the second and third instance of a multi cycle instruc tion LDD ST or FPOP 125 96 Time tag The value of the DSU time tag counter 95 64 Load Store parameters Instruction result Store address or Store data 63 34 Program counter Program counter 2 Isb bits removed since they are always zero 33 Instruction trap Set to 1 if traced instruction trapped 32 Processor error mode Set to 1 if the traced instruction caused processor error mode 31 0 Opcode Instruction opcode During tracing one instruction is stored per line in the trace buffer with the exception of multi cycle
153. information of all attached AHB units are printed to the console during the start of simulation Reporting starts by scanning the master interface array from 0 to NAHBMST 1 defined in the grlib amba package It checks each entry in the array for a valid vendor id all nonzero ids are considered valid and if one is found it also retrieves the device id The descriptions for these ids are obtained from the GRLIB DEVICES package and are then printed on standard out together with the master number If the index check is enabled done with a VHDL generic the report module also checks 1f the hindex number returned in the record matches the array number of the record currently checked the array index If they do not match the simulation is aborted and an error message is printed This procedure is repeated for slave interfaces found in the slave interface array It is scanned from 0 to NAHBSLV 1 and the same information is printed and the same checks are done as for the master interfaces In addition the address range and memory type is checked and printed The address infor mation includes type address mask cacheable and pre fetchable fields From this information the report module calculates the start address of the device and the size of the range The information finally printed is type start address size cacheability and pre fetchability The address ranges cur rently defined are AHB memory AHB I O and APB I O APB I O ranges are ignor
154. instructions Supervisor software should emulate FPops from the FQ in the same order as they were read from the FQ Note that instructions in the FQ may not appear in the same order as the program order since GRFPU executes floating point instructions out of order A floating point trap is never deferred past an instruction specifying source registers destination registers or condition codes that could be modified by the trap inducing instruction Execution or emulation of instructions in the FQ by the supervisor software gives therefore the same FPU state as if the instructions where executed in the program order 39 39 1 39 2 309 GRFPU Lite IEEE 754 Floating Point Unit Overview The GRFPU Lite floating point unit implements floating point operations as defined in IEEE Stan dard for Binary Floating Point Arithmetic IEEE 754 and SPARC V8 standard IEEE 1754 Supported formats are single and double precision floating point numbers The floating point unit is not pipelined and executes thus one floating point operation at a time GRFPU Lite Ik gt reset gt ctrl_out d Unpack Pack Iteration unit gt result el Add Sub Mul Div ar operand2 H round ctrl _in 4 Control 4 unit Functional Description 39 2 1 Floating point number formats The floating point unit handles floating point numbers in single or double precision f
155. interrupt bit in the control register is also set The interrupt will be generated regardless of whether the packet was received successfully or not The enable bit is set to indicate that the descriptor is valid which means it can be used by the to store a packet After it is set the descriptor should not be touched until the EN bit has been cleared by the GRETH_GBIT The rest of the fields in the descriptor are explained later in this section 31 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 0 0x0 RESERVED TR TD UR UD IR D LE 0E CE Fr AE IE WR EN LENGTH 31 0 0x4 ADDRESS 10 0 LENGTH The number of bytes received to this descriptor 11 Enable EN Set to one to enable the descriptor Should always be set last of all the descriptor fields 12 Wrap WR Set to one to make the descriptor pointer wrap to zero after this descriptor has been used If this bit is not set the pointer will increment by 8 The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached 13 Interrupt Enable IE Enable Interrupts An interrupt will be generated when a packet has been received to this descriptor provided that the receiver interrupt enable bit in the control register is set The interrupt is generated regardless if the packet was received successfully or if it terminated with an error 14 Alignment error AE An odd number of nibbles were received 15 Frame Too Long FT
156. is implemented according to IEEE standard 802 3 2002 There is no support for the optional control sublayer and no multicast addresses can be assigned to the MAC This means that packets with type 0x8808 the only currently defined ctrl packets are discarded 35 2 3 Hardware requirements The GRETH_GBIT is synthesisable with most Synthesis tools There are three or four clock domains depending on if the gigabit mode is used The three domains always present are the AHB clock Ethernet Receiver clock RX_CLK and the 10 100 Ethernet transmitter clock TX_CLK If the giga bit mode is also used the fourth clock domain is the gigabit transmitter clock GTX_CLK Both full duplex and half duplex operating modes are supported and both can be run in either 10 100 or 1000 Mbit The system frequency requirement AHB clock for 10 Mbit operation is 2 5 MHz 18 MHz for 100 Mbit and 40 MHz for 1000 Mbit mode The 18 MHz limit was tested on a Xilinx board with a DCM that did not support lower frequencies so it might be possible to run it on lower frequencies It might also be possible to run the 10 Mbit mode on lower frequencies RX_CLK and TX_CLK are sourced by the PHY while GIX_CLK is sourced by the MAC according to the 802 3 2002 standard The GRETH_GBIT does not contain an internal clock generator so GTX_CLK should either be generated in the FPGA with a PLL DLL or with an external oscillator Tx DMA interface The transmitter DMA interface is used for t
157. is sent on 8 bit basis as shown below Start DO D1 D2 D3 D4 D5 D6 D7 Stop Figure 15 Data frame Write Command Receive Resp byte optional Response byte encoding Read command bit 7 3 00000 bit 2 DMODE Send 10 Length 1 Adar 31 24 Adar 23 16 Addr 15 8 Addr 7 0 bit 1 0 AHB HRESP Receive Data 31 24 Data 23 16 Data 15 8 Data 7 0 Resp byte optional Figure 16 Commands Block transfers can be performed be setting the length field to n 1 where n denotes the number of transferred words For write accesses the control byte and address is sent once followed by the num ber of data words to be written The address is automatically incremented after each data word For 60 11 3 read accesses the control byte and address is sent once and the corresponding number of data words is returned 11 2 2 Baud rate generation The UART contains a 18 bit down counting scaler to generate the desired baud rate The scaler is clocked by the system clock and generates a UART tick each time it underflows The scaler is reloaded with the value of the UART scaler reload register after each underflow The resulting UART tick frequency should be 8 times the desired baud rate If not programmed by software the baud ra
158. is used 8 bytes will be transmitted TX identifier 1 this field is the same for both SFF and EFF frames Table 131 TX identifier 1 address 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 28 ID 27 ID 26 ID 25 ID 24 ID 23 ID 22 ID 21 Bit 7 0 The top eight bits of the identifier TX identifier 2 SFF frame Table 132 TX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 20 ID 19 ID 18 Bit 7 5 Bottom three bits of an SFF identifier Bit 4 0 Don t care TX identifier 2 EFF frame Table 133 TX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 20 ID 19 ID 18 1D 17 ID 16 ID 15 ID 14 ID 13 Bit 7 0 Bit 20 downto 13 of 29 bit EFF identifier TX identifier 3 EFF frame Table 134 TX identifier 3 address 19 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 12 ID 11 ID 10 ID 9 ID 8 ID 7 ID 6 ID 5 Bit 7 0 Bit 12 downto 5 of 29 bit EFF identifier TX identifier 4 EFF frame Table 135 TX identifier 4 address 20 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ID 4 ID 3 ID 2 ID 1 ID O Bit 7 3 Bit 4 downto 0 of 29 bit EFF identifier Bit 2 0 Don t care Data field For SFF frames the data field is located at address 19 to 26 and for EFF frames at 21 to 28 The data is transmitted s
159. memory devices attached to a 32 or 64 bit wide data bus The interface acts as a slave on the AHB bus where it occu pies configurable amount of address space for SDRAM access An optional Error Detection And Correction Unit EDAC logic only for the 32 bit bus corrects one bit error and detects two bit errors The SDRAM controller function is programmed by means of register s mapped into AHB I O address space Chip select decoding is done for two SDRAM banks FT SDRAM CONTROLLER SDO SDCLK SDO SDCSN 1 0 SDO SDRASN SDO SDCASN SDO SDWEN SDO SDDQM 7 0 SDO SDCLK SDO ADDRESS 16 2 SDLD 63 0 SDO D 31 0 CB 6 0 Figure 85 FT SDRAM memory controller connected to AMBA bus and SDRAM Operation 28 2 1 General Synchronous Dynamic RAM SDRAM access is supported to two banks of PC100 PC133 compati ble devices The controller supports 64 256 and 512 Mbyte devices with 8 12 column address bits up to 13 row address bits and 4 banks The size of each of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte The operation of the SDRAM controller is controlled through the configuration register SDCFG A second register ECFG is available for configuring the EDAC functions SDRAM banks data bus width is configurable between 32 and 64 bits 28 2 2 Initialisation When the SDRAM controller is enabled it automatically performs the SDRAM initialisation sequence of PRECHARGE 8x AUTO REFRESH and L
160. non incrementing reads have the same alignment restrictions as non verified writes Note that the Authorization failure error code will be sent in the reply if a violation was detected even if the length field was zero 42 6 5 RMW commands All read modify write sizes are supported except 6 which will lead to 3 B being read and written on the bus The RMW bus accesses have the same restrictions as the verified writes As in the verified write case the incrementing bit can be set to any value since only one AHB bus operation will be per formed for each RMW command 42 6 6 Control The RMAP command handler mostly runs in the background without any external intervention but there are a few control possibilities 330 There is an enable bit in the control register of the GRSPW which can be used to completely disable the RMAP command handler When it is set to 0 no RMAP packets will be handled in hardware instead they are all stored to the DMA channel There is a possibility that RMAP commands will not be performed in the order they arrive This can happen if a read arrives before one or more writes Since the command handler stores replies in a buffer with more than one entry several commands can be processed even if no replies are sent Data for read replies is read when the reply is sent and thus writes coming after the read might have been performed already if there was congestion in the transmitter To avoid this the RMAP buffer
161. of entries in the 9 bit receiver fifo N 16 64 64 Char fifo rxclkbuftype Select clock buffer type for receiver clock 0 does not 0 2 0 select a buffer instead i connects the input directly to the output synthesis tools may still infer a buffer 1 selects hardwired clock while 2 selects routed clock rxunaligned Receiver unaligned write support If set the receiver can 0 1 0 write any number of bytes to any start address without writing any excessive bytes rmapbufs Sets the number of buffers to hold RMAP replies 2 8 ft Enable fault tolerance against SEU errors 0 2 341 42 12 Signal descriptions Table 336 shows the interface signals of the core VHDL ports Table 336 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock TXCLK N A Input Transmitter default run state clock AHBMI Input AMB master input signals AHBMO ha Output AHB master output signals APBI Input APB slave input signals APBO Output APB slave output signals SWNI D Input Data input S Input Strobe input TICKIN Input Time counter tick input High CLKDIV10 Input Clock divisor value used during initialization and as reset value for the clock divisor register RMAPEN Input Reset value for the rmapen control register bit DCRSTVAL Input Reset value for disconnect timer Used if usegen VHDL generic is set to 0 TIMERRSTVAL Input Reset value for
162. of the core VHDL generics Table 480 Configuration options Generic Function Allowed range Default tech Target technology 0 NTECH 0 irlen Instruction register length generic tech only 2 8 2 idcode JTAG IDCODE instruction code generic tech only 0 255 9 id_msb JTAG Device indentification code MSB bits generic tech only 0 65535 0 id_Isb JTAG Device indentification code LSB bits generic tech only 0 65535 0 idcode JTAG IDCODE instruction generic tech only 0 255 9 62 7 Signal descriptions Table 481 shows the interface signals of the core VHDL ports Table 481 Signal declarations Signal name Field Type Function Active RST N A Input System reset Low CLK N A Input System clock AHB clock domain TCK N A Input JTAG clock TCKN N A Input Inverted JTAG clock TMS N A Input JTAG TMS signal High TDI N A Input JTAG TDI signal High TDO N A Output JTAG TDO signal High User defined data register interface TAPO_TCK N A Output TCK signal High TAPO_TDI N A Output TDI signal High TAPO_INST 7 0 N A Output Instruction in the TAP Ctrl instruction register High TAPO_RST N A Output TAP Controller in Test Logic_Reset state High TAPO_CAPT N A Output TAP Controller in Capture DR state High TAPO_SHFT N A Output TAP Controller in Shift DR state High TAPO_UPD N A Output TAP Controller in Update DR state High TAPO_XSEL1 N
163. options Table 19 shows the configuration options of the core VHDL generics Table 19 Configuration options bridge s slave interface user defined register 1 on the high speed bus Generic Function Allowed range Default tech Target technology 0 ffact Frequency ratio 0 hsb_hsindex AHB slave index on the high speed bus 0 to NAHBMAX 1 0 hsb_hmindex AHB master index on the high speed bus 0 to NAHBMAX 1 0 ncpu Number of CPUs on the high speed bus 0 15 0 hsb_iclize Cache line size in number of words for CPUs on the 4 8 8 high speed bus Determines the number of the words that are prefetched by the bridge when CPU performs instruction bursts hsb_bank0 Address area 0 mapped on the high speed bus and 0 1073741823 0 decoded by the bridge s slave interface on the low speed bus Appears as memory address register BARO on the bridge s low speed bus slave interface The generic has the same bit layout as bank address registers with bits 19 18 suppressed use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler misc package to generate this generic hsb_bank1 Address area 1 mapped on the high speed bus 0 1073741823 0 hsb_bank2 Address area 2 mapped on the high speed bus 0 1073741823 0 hsb_bank3 Address area 3 mapped on the high speed bus 0 1073741823 0 hsb_ioarea High speed bus configuration area will appear in the 0 16 FFFH 0 bridge s sla
164. or pseudo random replacement policy or as 2 way associative cache implementing LRR algorithm The set size is configurable to 1 64 kbyte and divided into cache lines of 16 32 bytes Each line has a cache tag associated with it consisting of a tag field valid field with one valid bit for each 4 byte sub block and optional lock and LRR bits On a data cache read miss to a cachable location 4 bytes of data are loaded into the cache from main memory The write policy for stores is write through with no allocate on write miss In a multi set configuration a line to be replaced on read miss is chosen according to the replacement policy Locked AHB transfers are generated for LDD STD LDST and SWAP instructions If a memory access error occurs during a data load the corresponding valid bit in the cache tag will not be set and a data access error trap tt 0x9 will be generated 44 4 2 Write buffer The write buffer WRB consists of three 32 bit registers used to temporarily hold store data until it is sent to the destination device For half word or byte stores the stored data replicated into proper byte alignment for writing to a word addressed device before being loaded into one of the WRB registers The WRB is emptied prior to a load miss cache fill sequence to avoid any stale data from being read in to the data cache Since the processor executes in parallel with the write buffer a write error will not cause an exception to the store instruc
165. or ed with the old values before they are stored into the status register Thus they are not cleared until written to with zeros from the AMBA APB bus If both 15 3 85 the receiver FIFO and shift registers are full when a new start bit is detected then the character held in the receiver shift register will be lost and the overrun bit will be set in the UART status register If flow control is enabled then the RTSN will be negated high when a valid start bit is detected and the receiver FIFO is full When the holding register is read the RTSN will automatically be reasserted again When the VHDL generic fifosize gt 1 which means that holding registers are not considered here some additional status and control bits are available The RF status bit not to be confused with the RF control bit is set when the receiver FIFO is full The RH status bit is set when the receiver FIFO is half full at least half of the entries in the FIFO contain data frames The RF control bit enables receiver FIFO interrupts when set A RCNT field is also available showing the current number of data frames in the FIFO Baud rate generation Each UART contains a 12 bit down counting scaler to generate the desired baud rate The scaler is clocked by the system clock and generates a UART tick each time it underflows It is reloaded with the value of the UART scaler reload register after each underflow The resulting UART tick frequency should be 8 times the de
166. play support oooooconoccoconccccconccononaninanacinnnoss 29 4 1 OVVIE W ee e E T e iii date 29 4 2 Operation snn a ia tas 29 4 3 NO 30 4 4 AHB DUS Monitor cia pil Sas oad pili 30 4 5 A A SR E oes Se ee EE 30 4 6 Configuration OPS os 31 4 7 Signal descriptions nr RS SRS SI a 32 4 8 Library dependencies msisite iones oest essnecsesvnscvees PORN rob ENE EE a einen dere pise ains es 32 4 9 Component declaran dieses 32 4 10 O 32 4 11 EDU GS pint out stent lived 33 AHBCTRL_MB AMBA AHB bus controller bus with support for multiple AHB DUSES ir A RR 36 5 1 OVA Wien di iii eet 36 5 2 Operation O ONO 37 5 3 AHB Split SuppOrt lt i ited iach ta heeee ibn Saeed te Sei eee ee a E 38 5 4 RESISTORS imita ld pilar pilotes biocidas N EEE AET citen 38 55 Configuration OPLIONS seiersen estrone irose orenetes se Eke EVEKEN Ok Ers ISEE Ers EE KEET rer KeS RE sae upessadste ne n cisne e 39 5 6 Signal descripto cia i 39 5 7 Library dependencia eee ae ee BA in Bi RS eh 40 5 8 Component declara psi ies 40 5 9 O as Sea ae es Rae a cg Bd eo 40 5 10 Debug printout NO 41 AHBJTAG JTAG Debug Link with AHB Master Interface ooooonnoconocccoccnnncnconncnoncnannnnnnnnos 43 10 11 6 1 OVENI E Wisteria R R E E s 43 6 2 OPCLAUON A O 43 6 3 A NN 44 6 4 Vendor and device 1dent fiers tias 44 6 5 Confis ration Options senei e hehe aot eee a ine Bi eS eee oe etd 44 6 6 Signal descriptions tomada iii 45 6 7 Fibra dependencies cum es 45 6 8 TnStamtiation s
167. port map sys_rst_in clkm cgo clklock rstn rstraw AMBA Components are defined here open sram_clk 473 Memory controller mctrl10 ssrctrl generic map hindex gt 0 pindex gt 0 port map rstn clkm ahbsi ahbso 0 apbi apbo 0 memi memo connect memory controller outputs to entity output signals sram_adv_ld_n lt 0 sram_mode lt 0 sram_zz lt 0 sram_flash_addr lt memo address 24 downto 2 sram_cen lt memo ramsn 0 flash_ce lt memo romsn 0 sram_flash_oe_n lt memo oen iosn lt memo iosn sram_bw lt memo wrn sram_flash_we_n lt memo writen I O pad instantiation with vectored enable instead bdr for iin 0 to 31 generate data_pad iopad generic map tech gt padtech port map sram_flash_data i memo data i memo vbdrive i memi data i end generate end 474 58 58 1 58 2 475 SVGACTRL Vga Controller Core Introduction The SVGACTRL core is a pixel based video controller frame buffer capable of displaying standard and custum resolutions with variable bit depth and refresh rates The controller consists of a synchro nization unit main controll unit FIFO unit and an AHB master as shown in the figure below Clk mux Video clocks AHB bus Clk self v __ys Hsync Vsync Csync Blank AHB ga Master gt Controller lp Red 7 0 Green 7 0 Blue 7 0 APB bus Operation SVGACTRL uses external frame buffer me
168. ratio The bridge is connected through a pair consisting of an AHB slave and an AHB master interface AHB transfer forwarding is performed in one direction AHB transfers to the slave interface are forwarded to the master interface Application of the uni directional bridge include system partitioning clock domain partitioning and system expansion Features offered by the uni directional AHB to AHB bridge are e single and burst AHB transfers e data buffering in internal FIFOs e efficient bus utilization through use of SPLIT response and data prefetching e posted writes e dead lock detection logic enables use of two uni directional bridges to build bi directional bridge see AHB AHB bridge core MASTER 1 MASTER 2 MASTER N AHB Bus 0 BUS CONTROL SLAVE 1 SLAVE 2 SLAVE I F AHB AHB BRIDGE MASTER I F MASTER 1 MASTER N AHB Bus 1 BUS CONTROL SLAVE 1 SLAVE 2 Figure 1 Two AHB buses connected with uni directional AHB AHB bridge Operation 2 2 1 General Address space occupied by the AHB AHB bridge on the slave bus is configurable and determined by Bank Address Registers in the slave interface AHB Plug amp Play configuration record The bridge is capable of handling single and burst transfers of incremental type HBURST HBURST4 HBURST8 HBURST16 Supported transfer sizes HSIZE are byte halfw
169. received The error response on AHB bus will result in target abort response for the PCI memory read cycle In case of PCI memory write cycle AHB access will not be finished with error response since write data is posted to the destination unit Instead the WE bit will be set in the units AMBA Configuration Status register If the PCI host signal is asserted active low the PCI target response to configuration cycles when no IDSEL signals is asserted none of AD 31 11 is asserted This is done for the master to be able to configure its own target If the core is not to be configured as the system host the PCI host signal should have a pull up connection to disable this feature PCI Target Configuration Space Header Registers Following registers are implemented in PCI Configuration Space Header Table 427 Configuration Space Header registers Address offset Register 0x00 Device ID amp Vendor ID 0x04 Status amp Command 0x08 Class Code amp Revision ID 0x0C BIST amp Header Type amp Latency Timer amp Cache Line Size 0x10 BARO 0x14 BARI 31 16 15 0 DEVICE_ID VENDOR_ID Figure 202 Device ID amp Vendor ID register 31 16 Device ID read only Returns value of device_id VHDL generic 430 15 0 Vendor ID read only Returns value of vendor_id VHDL generic 31 30 29 28 27 2625 24 23 2221 20 16 15 10 9 8 7 6 5 4 3 2 1 0 DPE RMA RTA STA 10
170. refresh function is enabled by setting bit 31 in SDCFG register 55 2 5 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in SDCFG PRE CHARGE AUTO REFRESH and LOAD MODE REG LMR If the LMR command is issued the CAS delay as programmed in SDCFG will be used remaining fields are fixed page read burst single location write sequential burst The command field will be cleared after a command has been executed Note that when changing the value of the CAS delay a LOAD MODE REGISTER command should be generated at the same time 55 2 6 Read cycles A read cycle is started by performing an ACTIVATE command to the desired bank and row followed by a READ command after the programmed CAS delay A read burst is performed if a burst access has been requested on the AHB bus The read cycle is terminated with a PRE CHARGE command no banks are left open between two accesses Note that only word bursts are supported by the SDRAM controller The AHB bus supports bursts of different sizes such as bytes and half words but they cannot be used 452 55 3 55 2 7 Write cycles Write cycles are performed similarly to read cycles with the difference that WRITE commands are issued after activation A write burst on the AHB bus will generate a burst of write commands without idle cycles in between As in the read case only word bursts are supported 55 2 8 Address bus connection The SDRAM address bus s
171. register Table 117 Bit interpretation of interrupt register IR address 3 Bit Name Description IR 7 reserved IR 6 reserved IR S reserved IR 4 not used wake up interrupt of SJA1000 IR 3 Data overrun interrupt Set when SR 1 goes from 0 to 1 IR 2 Error interrupt Set when the error status or bus status are changed IR 1 Transmit interrupt Set when the transmit buffer is released status bit 0 gt 1 IR O Receive interrupt This bit is set while there are more messages in the fifo This register is reset on read with the exception of IR O Note that this differs from the SJA1000 behavior where all bits are reset on read in BasicCAN mode This core resets the receive interrupt bit when the release receive buffer command is given like in PeliCAN mode Also note that bit IR 5 through IR 7 reads as 1 but IR 4 is 0 124 21 4 6 Transmit buffer The table below shows the layout of the transmit buffer In BasicCAN only standard frame messages can be transmitted and received EFF messages on the bus are ignored Table 118 Transmit buffer layout Addr Name Bits 7 6 5 4 3 2 1 0 10 ID byte 1 ID 10 ID 9 ID 8 ID 7 ID 6 ID S ID 4 ID 3 11 ID byte 2 ID 2 ID 1 ID 0 RTR DLC 3 DLC 2 DLC 1 DLC 0 12 TX data 1 TX byte 1 13 TX data 2 TX byte 2 14 TX data 3 TX byte 3 15 TX data 4 TX byte 4 16 TX data 5 TX byte 5 17 TX data 6 TX byt
172. set if the transmitter RAM was not able to provide data at a suf ficient rate This indicates a synchronization problem most probably caused by a low clock rate on the AHB clock The whole packet is buffered in the transmitter RAM before transmission so underruns cannot be caused by bus congestion The Alignment Error bit is set if more collisions occurred than allowed When running in 1000 Mbit mode the Late Collision bit indicates that a collision occurred after the slottime boundary was passed The packet was successfully transmitted only if these three bits are zero The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched The enable bit should be used as the indicator when a descriptor can be used again which is when it has been cleared by the GRETH_GBIT There are three bits in the GRETH_GBIT status register that hold transmission status The Transmit Error TE bit is set each time an transmission ended with an error when at least one of the three status bits in the transmit descriptor has been set The Transmit Successful TI is set each time a transmission ended successfully The Transmit AHB Error TA bit is set when an AHB error was encountered either when reading a descriptor reading packet data or writing status to the descriptor Any active transmissions are aborted and the transmitter is disabled The transmitter can be activated again by setting the transmit enable reg
173. signals are suitable to drive an external video DAC such as ADV7125 or similar APBVGA implements hardware scrolling to minimize processor overhead The controller monitors maintains a reference pointer containing the buffer address of the first character on the top most line When the text buffer is written with an address larger than the reference pointer 2960 the pointer is incremented with 80 The 4 Kbyte text buffer is sufficient to buffer 51 lines of 80 characters To sim plify hardware design the last 16 bytes 4080 4095 should not be written When address 4079 has been written the software driver should wrap to address 0 Sofware scrolling can be implemented by only using the first 2960 address in the text buffer thereby never activating the hardware scolling mechanism 16 3 16 4 91 Registers The APB VGA is controlled through three registers mapped into APB address space Table 85 APB VGA registers APB address offset Register 0x0 VGA Data register 0x4 VGA Background color 0x8 VGA Foreground color 16 3 1 VGA Data Register 31 19 8 7 0 RESERVED ADDRESS DATA Figure 33 VGA data register 19 8 Video memory address write access 7 0 Video memory data write access 16 3 2 VGA Background Color 31 24 23 16 15 8 7 0 RESERVED RED GREEN BLUE Figure 34 PS 2 status register 23 16 Video background color red 15 8 Video background
174. sizes can be changed by writing to this register field The written values corre spond to the bank sizes and number of chip selects as above Reset to 0000 when programmable Programmable ROMBANKSZ is only available when romasel VHDL generic is 0 For other values this is a read only register field containing the fixed bank size value 13 12 RESERVED 11 PROM write enable PWEN Enables write cycles to the PROM area 10 RESERVED 9 8 PROM width PROM WIDTH Sets the data width of the PROM area 00 8 01 16 10 32 7 4 PROM write waitstates PROM WRITE WS Sets the number of wait states for PROM write cycles 0000 0 0001 2 0010 4 1111 30 3 0 PROM read waitstates PROM READ WS Sets the number of wait states for PROM read cycles 0000 0 0001 2 0010 4 1111 30 Reset to 1111 199 During reset the prom width bits 9 8 are set with value on BWIDTH inputs The prom waitstates fields are set to 15 maximum External bus error and bus ready are disabled All other fields are undefine d 27 15 2 Memory configuration register 2 MCFG2 Memory configuration register 2 is used to control the timing of the SRAM and SDRAM 31 30 29 Table 201 Memory configuration register 2 28 27 26 25 24 23 22 21 20 19 18 17 16 SDRF TRP SDRAM TRFC TCAS SDRAM BANKSZ SDRAM COLSZ SDRAM CMD D64 SDPB 15 14 13 12 9
175. skip the received message not storing it to memory The write pointer will be incremented If the CanCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled CanRx CTRL ENABLE is cleared automatically to 0b The write pointer can be used to determine which message caused the AHB error Note that it could be any of the four word accesses required to writ a message that caused the AHB error If the CanCONF ABORT bit is set to 1b all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs as indicated by the CanSTAT AHBErr bit being 1b The accesses will be disabled until the CanSTAT register is read and automatically clearing bit CanSTAT AHBErr 22 6 7 Enable and disable When an enabled receive channel is disabled CanRxCTRL ENABLE 0b any ongoing CAN mes sage storage on the AHB bus will not be aborted and no new message storage will be started Note that only complete messages can be received from the CAN core If the message is stored success fully the write pointer CanRxWR WRITE is automatically incremented Any associated interrupts will be generated The progress of the any ongoing access can be observed via the CanRxCTRL ONGOING bit The CanRxCTRL ONGOING must be Ob before the channel can be re configured safely i e changing address size or read write pointers It is also possible to wait for the Rx and RxMiss interrupts described hereafter The channel can be re enabled again wi
176. state can be accessed by the DSU Entering the debug mode can occur on the following events e executing a breakpoint instruction ta 1 e integer unit hardware breakpoint watchpoint hit trap Oxb e rising edge of the external break signal DSUBRE e setting the break now BN bit in the DSU control register e atrap that would cause the processor to enter error mode e occurrence of any or a selection of traps as defined in the DSU control register e after a single step operation e one of the processors in a multiprocessor system has entered the debug mode e DSU AHB breakpoint hit 172 25 3 The debug mode can only be entered when the debug support unit is enabled through an external sig nal DSUEN When the debug mode is entered the following actions are taken e PC and nPC are saved in temporary registers accessible by the debug unit e an output signal DSUACT is asserted to indicate the debug state e the timer unit is optionally stopped to freeze the LEON timers and watchdog The instruction that caused the processor to enter debug mode is not executed and the processor state is kept unmodified Execution is resumed by clearing the BN bit in the DSU control register or by de asserting DSUEN The timer unit will be re enabled and execution will continue from the saved PC and nPC Debug mode can also be entered after the processor has entered error mode for instance when an application has terminated and halted the processor
177. the Address Tag field to the address tag of the line to be locked setting the lock bit and clearing the valid bits The locked cache line will be updated on a read miss and will remain in the cache until the line is unlocked The first cache line on certain cache offset is locked in the set 0 If several lines on the same cache offset are to be locked the locking is performed on the same cache offset and in sets in ascending order starting with set O The last set can not be locked and is always replaceable Unlocking is performed in descending set order NOTE Setting the lock bit in a cache tag and reading the same tag will show if the cache line locking was enabled during the LEON3 configuration the lock bit will be set if the cache line locking was enabled otherwise it will be 0 44 5 4 Local instruction ram A local instruction ram can optionally be attached to the instruction cache controller The size of the local instruction is configurable from 1 64 kB The local instruction ram can be mapped to any 16 Mbyte block of the address space When executing in the local instruction ram all instruction fetches are performed from the local instruction ram and will never cause IU pipeline stall or generate an instruction fetch on the AHB bus Local instruction ram can be accessed through load store integer word instructions LD ST Only word accesses are allowed byte halfword or double word access to the local instruction ram will generate data excep
178. the Data Input 3 Register is written to with data 32 7 4 Data Output Registers R Table 245 Data Output 0 Register 31 Data 127 downto 96 Table 246 Data Output 1 Register 31 Data 95 downto 64 Table 247 Data Output 2 Register 31 Data 63 downto 32 Table 248 Data Output 3 Register 31 Data 31 downto 0 Note that these registers can only be read after encryption or decryption has been completed An AMBA AHB response is given to read accesses that occur while the encryption or decryption is in progress If a read access is attempted before an encryption or decryption has even been initiated then 258 32 8 32 9 32 10 32 11 32 12 an AMBA AHB erro response is given Write accesses to these registers result in an AMBA AHB error response Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x073 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 249 shows the configuration options of the core VHDL generics Table 249 Configuration options Generic Function Allowed range Default hindex AHB slave index 0 NAHBSLV 1 0 ioaddr Addr field of the AHB I O BAR 0 16 FFFH 0 iomask Mask field of the AHB I O BAR 0 16 FFFH 16 FFC hirq Interrupt line used by the GRAES 0 NAHBIRQ 1 0 Signal descript
179. the cache offset and the least significant bits of the address bits making up the address tag Sim ilarly the data sub blocks may be read by executing an LDA instruction with ASI 0xD for instruction cache data and ASI OxF for data cache data The sub block to be read in the indexed cache line and set is selected by A 4 2 The tags can be directly written by executing a STA instruction with ASI 0xC for the instruction cache tags and ASI 0xE for the data cache tags The cache line and set are indexed by the address bits making up the cache offset and the least significant bits of the address bits making up the address tag D 31 10 is written into the ATAG filed see above and the valid bits are written with the D 7 0 of 380 the write data Bit D 9 is written into the LRR bit if enabled and D 8 is written into the lock bit if enabled The data sub blocks can be directly written by executing a STA instruction with ASI 0xD for the instruction cache data and ASI OxF for the data cache data The sub block to be read in the indexed cache line and set is selected by A 4 2 44 5 3 Cache line locking In a multi set configuration the instruction and data cache controllers can be configured with optional lock bit in the cache tag Setting the lock bit prevents the cache line to be replaced by the replacement algorithm A cache line is locked by performing a diagnostic write to the instruction tag on the cache offset of the line to be locked setting
180. the following results LUTs 5040 7 256x1 ROMs ROM256X1 128 256 e Frequency 125 MHz 32 7 Registers The core is programmed through registers mapped into AHB I O address space Table 238 GRAES registers AHB I O address offset Register 16 000 Control Register 16 010 Data Input 0 Register 16 014 Data Input 1 Register 16 018 Data Input 2 Register 16 01C Data Input 3 Register 16 020 Data Output 0 Register 16 024 Data Output 1 Register 16 028 Data Output 2 Register 16 02C Data Output 3 Register 16 03C Debug Register 32 7 1 Control Register W Table 239 Control Register 31 2 1 0 DE KE C Y 31 2 Unused 1 DEC 0 encrypt 1 decrypt only relevant when KEY 1 0 KEY 0 data will be input 1 key will be input Note that the Data Input Registers cannot be written before a command is given to the Control Regis ter Note that the Data Input Registers must then be written in sequence and all four registers must be written else the core ends up in an undefined state The KEY bit determines whether a key will be input KEY 1 or data will be input KEY 0 When a key will be input command is written the DEC bit determines whether decryption DEC 1 or encryption DEC 0 should be applied to the subsequent data input Note that the register cannot be written after a command has been given until the specif
181. this area must be specificed with the abits VHDL generic The address bus of the Core1553BRM is 16 bits wide but the amount of bits actually used depends on the setup of the data structures The AHB page address register should be programmed with the 32 abits top bits of the 32 bit AHB address abit being a VHDL generic The address provided by the Core1553BRM core is shifted left one bit and forms the AHB address together with the AHB page address register Note that all pointers given to the Core1553BRM core needs to be right shifted one bit because of this When the Core1553BRM core has been granted access to the bus it expects to be able to do a series of uninterrupted accesses To handle this requirement the AHB master locks the bus during these trans fers In the worst case the Core1553BRM can do up to 7 writes in one such access and each write takes 2 plus the number of waitstate cycles with 4 idle cycles between each write strobe This means care has to be taken if using two simultaneous active Corel553BRM cores on the same AHB bus All AHB accesses are done as half word single transfers The endianness of the interface depends on the endian VHDL generic The AMBA AHB protection control signal HPROT is driven permanently with 0011 i e a not cacheable not bufferable privileged data access During all AHB accesses the AMBA AHB lock sig nal HLOCK is driven with 1 and 0 otherwise Operation The mode of operation can be selected w
182. to poll It is incremented each time the function returns nonzero Table 373 Return values for spw_checktx Value Description 0 No packet has been transmitted 1 A packet has been correctly transmitted 2 A packet has been incorrectly transmitted Table 374 Parameters for spw_checktx Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be polled void send_time struct spwvars spw Sends a new time code Increments the time counter in the GRSPW and transmits the value Table 375 Parameters for send time Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be polled int check_time struct spwvars spw Check if a new time code has been received Table 376 Return values for check_time Value Description 0 No time code has been received 1 A new time code has been received Table 377 Parameters for check_time Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be polled 358 int get_time struct spwvars spw Get the current time counter value Table 378 Return values for get_time Value Description 0 63 Returns the current time counter value Table 379 Parameters for get_time Parameter Description
183. transmitted successfully or not The Wrap WR bit is also a control bit that should be set before transmission and it will be explained later in this section 273 31 15 14 13 12 11 10 0 0x0 RESERVED AL UE TE WR EN LENGTH 31 21 0 0x4 ADDRESS RESERVED 10 0 LENGTH The number of bytes to be transmitted 11 Enable EN Set to one to enable the descriptor Should always be set last of all the descriptor fields 12 Wrap WR Set to one to make the descriptor pointer wrap to zero after this descriptor has been used If this bit is not set the pointer will increment by 8 The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached 13 Interrupt Enable IE Enable Interrupts An interrupt will be generated when the packet from this descriptor has been sent provided that the transmitter interrupt enable bit in the control register is set The interrupt is generated regardless if the packet was transmitted successfully or if it terminated with an error 14 Underrun Error UE The packet was incorrectly transmitted due to a FIFO underrun error 15 Attempt Limit Error AL The packet was not transmitted because the maximum number of attempts was reached 31 2 Address Pointer to the buffer area from where the packet data will be loaded Figure 112 Transmitter descriptor Memory offsets are shown in the left margin To enable a descriptor the enable EN bit sho
184. use 0x00 returns the current set OxF2 Read ID the keyboard responds by sending a two byte device ID of OxAB 0x83 OxF3 Set typematic repeat rate keyboard will reply with ACK OxFA and wait for another byte which determines the typematic rate OxF4 Keyboard enable clears the keyboards output buffer enables keyboard scanning and returns an acknowledgement OxF5 Keyboard disable resets the keyboard disables keyboard scanning and returns an acknowledge ment OxF6 Set default load default typematic rate delay 10 9cps 500ms and scan code set 2 OxFE Resend upon receipt of the resend command the keyboard will retransmit the last byte OxFF Reset resets the keyboard bit O controls the scroll lock bit 1 the num lock bit 2 the caps lock bit 3 7 are ignored Table 73 Receive commands Command Description OxFA Acknowledge OxAA Power on self test passed BAT completed OxEE Echo respond OxFE Resend upon receipt of the resend command the host should retransmit the last byte 0x00 Error or buffer overflow OxFF Error of buffer overflow Table 74 The typematic rate delay argument byte MSB LSB DELAY DELAY RATE RATE RATE RATE RATE 82 Table 75 Typematic repeat rates Bits 0 Rate Bits 0 Rate Bits 0 Rate Bits 0 Rate 4 cps 4 cps 4 cps 4 cps 00h 30 08h 15 10h 7
185. used Table 446 shows the supported technologies for the core Table 446 Supported technologies Tech name Technology RAM cell abit range dbit range axcel Actel AX RTAX RAM64K36 2 12 unlimited altera All Altera devices altsyncram unlimited unlimited ihp25 THP 0 25 flip flops unlimited unlimited inferred Behavioural description synthesis tool dependent rhumc Rad hard UMC 0 18 flip flops unlimited unlimited virtex Xilinx Virtex Virtex E Spartan 2 RAMB4_Sn 2 10 unlimited virtex2 Xilinx Virtex2 Spartan3 Virtex4 RAMB16_Sn 2 14 unlimited proasic3 Actel Proasic3 ram4k9 2 12 unlimited lattice Lattice XP EC ECP dp8ka 2 13 unlimited memvirage Virage ASIC RAM hdss2_64x32cm4sw0 6 9 32 hdss2_128x32cm4sw0 hdss2_256x32cm4sw0 hdss2_512x32cm4sw0 54 3 54 4 54 5 Signal descriptions Table 447 shows the interface signals of the core VHDL ports Table 447 Signal descriptions 449 Signal name Field Type Function Active WCLK N A Input Write port clock WADDR N A Input Write address WDATA N A Input Write data WE N A Input Write enable High RCLK N A Input Read ports clock RADDRI N A Input Read portl address RE1 N A Input Read portl enable High RDATA1 N A Output Read portl data RADDR2 N A Input Read port2 address RE2 N A Input Read port2 enable High RDATA2 N A Output Read port2 data Library dependencies Table 448 shows libraries used when instantiatin
186. 0 4 Not valid NV When an operation is finished BUSY 0 this bit indicates whether valid data has been received that is the data field contains correct data Not Reset 10 6 Register Address This field contains the address of the register that should be accessed during a write or read operation Not Reset 15 11 PHY Address This field contains the address of the PHY that should be accessed during a write or read operation Not Reset 294 31 16 Data Contains data read during a read operation and data that is transmitted is taken from this field Not Reset 31 10 9 3 2 0 TRANSMITTER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR POINTER RESERVED Figure 130 GRETH_GBIT transmitter descriptor table base address register 31 10 Base address to the transmitter descriptor table Not Reset 9 3 Pointer to individual descriptors Automatically incremented by the Ethernet MAC 2 0 Reserved Reads as zeroes 31 10 9 3 2 0 RECEIVER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR POINTER RESERVED Figure 131 GRETH_GBIT receiver descriptor table base address register 31 10 Base address to the receiver descriptor table Not Reset 9 3 Pointer to individual descriptors Automatically incremented by the Ethernet MAC 2 0 Reserved Reads as zeroes 31 0 EDCL IP ADDRESS Figure 132 GRETH_GBIT EDCL IP register 31 0 EDCL IP address Reset value is set with the ipaddrh and ipaddrl generics 35
187. 0 0x00 10 reserved 0x00 reserved 0x00 11 Arbitration lost capture Arbitration lost capture 12 Error code capture Error code capture 13 Error warning limit Error warning limit Error warning limit 14 RX error counter RX error counter RX error counter 15 TX error counter TX error counter TX error counter 16 RX FI SFF RX Fl EFF TX FI SFF TX FI EFF Acceptance code 0 Acceptance code 0 17 RXID 1 RX ID 1 TX ID 1 TX ID 1 Acceptance code 1 Acceptance code 1 18 RXID2 RX ID 2 TX ID 2 TX ID 2 Acceptance code 2 Acceptance code 2 19 RX data 1 RX ID 3 TX data 1 TX ID 3 Acceptance code 3 Acceptance code 3 20 RX data 2 RX ID 4 TX data 2 TX ID 4 Acceptance mask 0 Acceptance mask 0 21 RX data 3 RX data 1 TX data 3 TX data 1 Acceptance mask 1 Acceptance mask 1 22 RX data 4 RX data 2 TX data 4 TX data 2 Acceptance mask 2 Acceptance mask 2 23 RX data 5 RX data 3 TX data 5 TX data 3 Acceptance mask 3 Acceptance mask 3 24 RX data 6 RX data 4 TX data 6 TX data 4 reserved 0x00 25 RX data 7 RX data 5 TX data 7 TX data 5 reserved 0x00 26 RX data 8 RX data 6 TX data 8 TX data 6 reserved 0x00 27 FIFO RX data 7 TX data 7 reserved 0x00 28 FIFO RX data 8 TX data 8 reserved 0x00 29 RX message counter RX msg counter 30 0x00 0x00 31 Clock divider Clock divider Clock divider Clock divider The transmit and receive buffers have different layout depending on if standard frame forma
188. 0 52 5 2E F0 2E F12 T F0 07 41 F0 41 6 36 F0 36 PRNT E0 12 E0 FO 49 F0 49 SCRN E0 7C 7C EO F0 12 3D F0 3D SCROLL 7E F0 7E 4A F0 4A 8 3E F0 3E PAUSE E1 14 77 NONE E1 FO0 14 80 Table 70 Windows multimedia scan codes KEY MAKE BREAK Next Track EO 4D EO FO 4D Previous Track EO 15 EO FO 15 Stop EO 3B EO FO 3B Play Pause EO 34 EO FO 34 Mute EO 23 EO FO 23 Volume Up EO 32 EO FO 32 Volume Down EO 21 EO FO 21 Media Select EO 50 EO FO 50 E Mail EO 48 EO FO 48 Calculator EO 2B EO FO 2B My Computer EO 40 EO FO 40 WWW Search EO 10 EO FO 10 WWW Home E0 3A EO FO 3A WWW Back EO 38 EO FO 38 WWW Forward EO 30 EO FO 30 WWW Stop EO 28 EO FO 28 WWW Refresh EO 20 EO FO 20 WWW Favor EO 18 EO FO 18 ites Table 71 ACPI scan codes Advanced Configuration and Power Interface KEY MAKE BREAK Power EO 37 EO FO 37 Sleep EO 3F EO FO 3F Wake E0 5E EO FO SE 14 12 Keyboard commands Table 72 Transmit commands 81 Command Description OxED Set status LED s keyboard will reply with ACK OxFA The host follows this command with an argument byte OxEE Echo command expects an echo response OxFO Set scan code set keyboard will reply with ACK OxFA and wait for another byte 0x01 0x03 which determines the scan code set to
189. 0 occupy OXxFFFFFO0O OxFFFFF200 masters on bus 1 occupy Ox FFFFF200 OxFFFFF400 Each unit occupies 32 bytes which means that the area has place for 16 masters and 16 slaves per bus 64 master and 64 slaves totally The address of the plug amp play information for a certain unit is defined by the AHB bus and its master slave index The address for masters is thus OXFFFFFO00 bus 512 n 32 and OxXFFFFF800 bus 512 n 32 for slaves where bus is bus number and n is master slave index In a multiple AHB bus system one AHB controller should decode plug amp play information e g AHBCTRL_MB on bus 0 while configuration area should be disabled for the AHB controllers on other buses 38 31 24 23 1211 10 9 54 0 Identification Register 00 VENDOR ID DEVICE ID 00 VERSION IRQ 04 USER DEFINED 08 USER DEFINED 0c USER DEFINED BARO 10 ADDR 00 P C MASK TYPE BAR1 14 ADDR 00 P C MASK TYPE Bank Address Registers BAR2 18 ADDR 00 P C MASK TYPE BAR3 1C ADDR 00 P C MASK TYPE 31 20 19 18 17 16 15 4 3 0 TYPE 5 3 5 4 P Prefetchable C Cacheable Figure 7 AHB plug amp play information record AHB split support 0001 APB I O space 0010 AHB Memory space 0011 AHB I O space AHB SPLIT functionality is supported if the split VHDL generic is set to 1 In this case all slaves must driver the AHB SPLIT signal Registers The core does not implement any registers 5
190. 00 00000000 00000000 00000000 00000000 00000000 00000000 00000001 b 0066 647EDE6C 332C7F8C 0923BB58 213B333B 20E9CE42 81FE115F 7D8F9DAD The base point G in compressed form is G 0300FA CODFCBAC 8313BB21 39F1BB75 SFEF65BC 391F8B36 F8F8EB73 71FD558B 3 ax b over Fm is defined by and in uncompressed form is 262 33 6 33 7 G 04 00FAC9DF CBAC8313 BB2139F1 BB755FEF 65BC391F 8B36F8F8 EB7371FD 558B0100 6A08A419 03350678 E58528BE BFSAOBEF F867A7CA 36716F7E 01F81052 Finally the order n of G and the cofactor are n 0100 00000000 00000000 00000000 0013E974 E72F8A69 22031D26 03CFE0D7 h 02 Throughput The data throughput for the GRECC core is around 233 16700 bits per clock cycle i e approximately 13 9 kbits per MHz The underlaying EEC core has been implemented in a dual crypto chip on 250 nm technology as depicted in the figure below The throughput at 33 MHz operating frequency was 850 kbit s the power consumption was 56 8 mW and the size was 27 6 kgates MAA PTET He eee Figure 110 Dual Crypto Chip Characteristics The GRECC core has been synthesized for a Xilinx Virtex 2 XC2V6000 4 devices with the following results e LUTs 12850 19 e Frequency 93 MHz 263 33 8 Registers The core is programmed through registers mapped into APB address space Table 252 GRECC registers
191. 00 800 PCI_MTF master target PCI with FIFO 1 100 2 000 6 000 PCIDMA master target PCI with FIFO DMA 1 800 3 000 9 000 PCITRACE 300 600 1 400 SRCTRL 100 200 500 SDCTRL 300 600 1 200 SVGACTRL 1 200 2 1 600 2 8 000 USBDCL 2 000 12 000 20 Table 14 Approximate area consumption for some FT GRLIB IP cores Block RTAX2000 Cells ASIC gates GRFPU Lite FT including LEON3 controller 7 100 4 RAM64K36 36 000 GRFPCFT for LEON3 30 000 RAM LEON3FT 8 8 Kbyte cache 7 500 48 RAM64K36 22 000 RAM LEON3FT 8 8 Kbyte cache DSU3 8 500 48 RAM64K36 27 000 RAM LEON3FT 8 4 Kbyte cache DSU3 8 500 38 RAM64K36 27 000 RAM FTSRCTRL 700 2 500 FTSRCTRL8 750 FTSDCTRL 1 000 3 500 FTAHBRAM 2 Kbyte with EDAC 300 5 RAM64K36 2 000 RAM The table below show the area resources for some common FPGA devices It can be used to quickly estimate if a certain GRLIB design will fit the target device Table 15 Area resources for some common FPGA devices FPGA Logic Memory Actel AX1000 18 144 Cells 32 RAM64K36 Actel AX2000 32 248 Cells 64 RAM64K36 Xilinx Spartan3 1500 33 248 LUT 64 RAMB16 Xilinx Virtex2 3000 28 672 LUT 96 RAMB16 Xilinx Virtex2 6000 67 584 LUT 144 RAMB16 2 1 2 2 21 AHB2AHB Uni directional AHB to AHB bridge Overview Uni directional AHB to AHB bridge is used to connect two AHB buses clocked by synchronous clocks with any frequency
192. 1 SYSCLK 15 64 bit data bus D64 Reads 1 if memory controller is configured for 64 bit data bus otherwise 0 Read only 20 19 SDRAM command Writing a non zero value will generate an SDRAM command 01 PRECHARGE 10 AUTO REFRESH 11 LOAD COMMAND REGISTER The field is reset after command has been executed 22 21 SDRAM column size 00 256 01 512 10 1024 11 4096 when bit 25 23 111 2048 otherwise 25 23 SDRAM banks size Defines the banks size for SDRAM chip selects 000 4 Mbyte 001 8 Mbyte 010 16 Mbyte 111 512 Mbyte 26 SDRAM CAS delay Selects 2 or 3 cycle CAS delay 0 1 When changed a LOAD COMMAND REGISTER command must be issued at the same time Also sets RAS CAS delay tRCD 29 27 SDRAM tpgc timing tare will be equal to 3 field value system clocks 30 SDRAM tpp timing tgp will be equal to 2 or 3 system clocks 0 1 31 SDRAM refresh If set the SDRAM refresh will be enabled 28 3 2 EDAC Configuration register ECFG The EDAC configuration register controls the EDAC functions of the SDRAM controller during run time 31 30 cntbits 10 cnbits 9 10 9 8 7 6 0 EAV RESERVED SEC WB RB EN TCB Figure 87 EDAC configuration register 6 0 TCB Test checkbits These bits are written as checkbits into memory during a write operation when the WB bit in the ECFG register is set
193. 1 ramoen 4 0 Output SRAM output enable Low Logical 1 rwen 3 0 Output SRAM write enable Low Logical 1 rwen 0 corresponds to data 31 24 rwen 1 corresponds to data 23 16 rwen 2 corresponds to data 15 8 rwen 3 corresponds to data 7 0 Any rwen signal can be used for cbf ramben 3 0 Output SRAM byte enable Low Logical 1 ramben 0 corresponds to data 31 24 ramben 1 corresponds to data 23 16 ramben 2 corresponds to data 15 8 ramben 3 corresponds to data 7 0 Any ramben signal can be used for cb oen Output Output enable Low Logical 1 writen Output Write strobe Low Logical 1 read Output Read strobe High Logical 1 iosn Output IO area chip select Low Logical 1 romsn 3 0 Output PROM chip select Low Logical 1 brdyn Input Bus ready Extends accesses to the IO area Low bexcn Input Bus exception Low sa 15 0 Output SDRAM address High Undefined sd 31 0 Input Output SDRAM data High Tri state scb 15 0 Input Output SDRAM check bits High Tri state sdesn 1 0 Output SDRAM chip select Low Logical 1 sdwen Output SDRAM write enable Low Logical 1 sdrasn Output SDRAM row address strobe Low Logical 1 sdcasn Output SDRAM column address strobe Low Logical 1 sddqm 3 0 Output SDRAM data mask Low Logical 1 sddqm 3 corresponds to sd 31 24 sddqm 2 corresponds to sd 23 16 sddqm 1 corresponds to sd 15 8 sddqm 0 corresponds to sd 7 0 Any sddqml signal can be used for scb 206 27 20
194. 12 6 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler sim all entity ambamon_ex is port clk in std_ulogic rst in std_ulogic end architecture rtl of ambamon_ex is APB signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others APB signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others begin AMBA Components are instantiated here library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler sim all entity ambamon_ex is port clk lt in std ulogica rst in std_ulogic err out std_ulogic end architecture rtl of ambamon_ex is AHB signals signal ahbmi ahb_mst_in type gt apb_none gt apb_none signal ahbmo ahb_mst_out_vector others gt apb_none AHB signals signal ahbsi ahb_slv_in type signal ahbso ahb_slv_out_vector others gt apb_none APB signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others begin mon0 ambamon generic map assert_err gt 1 assert_war gt 0 nahbm gt 2 nahbs gt 2 napb gt 1 gt apb_none 67 68 port map end rst clk ahbmi ahbmo ahbsi ahbso apbi apbo err str clk ahbmi ahbmo ahbsi ahbso
195. 133 MHz CL 3 TRP 1 TCAS 1 TRFC 6 22 82 22 67 52 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO REFRESH command to both SDRAM banks The period between the commands in clock periods is pro grammed in the refresh counter reload field in the MCFG3 register Depending on SDRAM type the required period is typically 7 8 or 15 6 us corresponding to 780 or 1560 clocks at 100 MHz The generated refresh period is calculated as reload value 1 sysclk The refresh function is enabled by setting bit 31 in MCFG2 27 9 1 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in MCFG2 PRE CHARGE AUTO REFRESH and LOAD MODE REG LMR If the LMR command is issued the CAS delay as programmed in MCFG will be used Line burst of length 8 will be set for read when pageburst VHDL generic is 0 Page burst will be set for read when pageburst VHDL generic is 1 Page burst or line burst of length 8 selectable via the MCFG2 register will be set when pageburst VHDL generic is 2 Remaining fields are fixed single location write sequential burst The command field will be cleared after a command has been executed When changing the value of the CAS delay a LOAD MODE REGISTER command should be generated at the same time NOTE when issuing SDRAM commands the SDRAM refresh must be disabled 27 9 2 Read cycles A read cycle is started by performing an ACTIVATE command to the
196. 16 The two most significant bytes of the MAC Address Not Reset 31 0 Bit 31 downto 0 of the MAC Address Figure 117 MAC Address LSB 31 0 The 4 least significant bytes of the MAC Address Not Reset 31 16 15 11 10 6 4 3 2 1 0 DATA PHY ADDRESS REGISTER ADDRESS INV BU LF RD WR Figure 118 GRETH MDIO ctrl status register 0 Write WR Start a write operation on the management interface Data is taken from the Data field Reset value 0 i Read RD Start a read operation on the management interface Data is stored in the data field Reset value 0 2 Linkfail LF When an operation completes BUSY 0 this bit is set if a functional management link was not detected Not Reset 3 Busy BU When an operation is performed this bit is set to one As soon as the operation is finished and the management link is idle this bit is cleared Reset value 0 4 Not valid NV When an operation is finished BUSY 0 this bit indicates whether valid data has been received that is the data field contains correct data Not Reset 10 6 Register Address This field contains the address of the register that should be accessed during a write or read operation Not Reset 15 11 PHY Address This field contains the address of the PHY that should be accessed during a write or read operation Not Reset 31 16 Data Contains data read during a read operation and data that is transmitted is taken from this field Not Reset 31 10 9 3 2 0 TR
197. 16 FFF 16 E00 ioaddr ADDR field of the AHB BARI defining I O address space 0 16 FFFH 16 200 Default I O area is 0x20000000 0x2FFFFFFE iomask MASK field of the AHB BAR1 defining I O address space 0 16 FFFH 16 E00 ramaddr ADDR field of the AHB BAR2 defining RAM address space 0 16 FFFH 16 400 Default RAM area is 0x40000000 0x7FFFFFFF rammask MASK field of the AHB BAR2 defining RAM address space 0 16 FFF 16 COO paddr ADDR field of the APB BAR configuration registers address 0 16 FFFH 0 space pmask MASK field of the APB BAR configuration registers address 0 16 FFFH 16 FFFH space wprot RAM write protection 0 1 invelk unused N A fast Enable fast SDRAM address decoding 0 1 romasel Sets the PROM bank size O selects a programmable mode where 0 28 28 the rombanksz field in the MCFG1 register sets the bank size See the description of the MCFG1 register for more details Values 1 14 sets the size in binary steps 1 16 kB 2 32 kB 14 128 MB Four chip selects are available for these val ues 15 sets the bank size to 256 MB with two chip selects Values 16 28 sets the bank size in binary steps 16 64 kB 17 128 kB 28 256 MB Two chip selects are available for this range The selected bank size is readable from the rombanksz field in the MCFG1 register for the non programmable modes sdrasel log2 RAM address space size 1 E g if size of the RAM 0 31 29 address space is 0x40000000 sdrasel is log2 2 30 1
198. 16 FFFF 16 COA8 value ipaddrl Sets the lower 16 bits of the EDCL IP address reset 0 16 FFFF 16 0035 value phyrstadr Sets the reset value of the PHY address field in the 0 31 0 MDIO register rmii Selects the desired PHY interface 0 MII 1 RMI 0 1 oepol Selects polarity on output enable ETHO MDIO_OE 0 1 0 active low 1 active high Not all addresses are allowed and most NICs and protocol implementations will discard frames with illegal addresses silently Consult network literature if unsure about the addresses 282 34 12 Signal descriptions Table 303 shows the interface signals of the core VHDL ports Table 303 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBMI Input AMB master input signals AHBMO t Output AHB master output signals APBI Input APB slave input signals APBO s Output APB slave output signals ETHI 7 Input Ethernet MII input signals ETHO Output Ethernet MII output signals see GRLIB IP Library User s Manual 34 13 Library dependencies Table 304 shows libraries used when instantiating the core VHDL libraries Table 304 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER ETHERNET_MAC Signals component GRETH component declarations GRETH sig nals GAISLER NET Si
199. 16 FFFH console Prints output from the UART on console during VHDL 0 1 0 simulation and speeds up simulation by always returning 1 for Data Ready bit of UART Status register Does not effect synthesis pirq Index of the interrupt line 0 NAHBIRQ 1 0 parity Enables parity 0 1 1 flow Enables flow control 0 1 1 fifosize Selects the size of the Receiver and Transmitter FIFOs 1 2 4 8 16 32 1 88 15 7 15 8 15 9 Signal descriptions Table 83 shows the interface signals of the core VHDL ports Table 83 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals UARTI RXD Input UART receiver data CTSN Input UART clear to send Low EXTCLK Input Use as alternative UART clock UARTO RTSN Output UART request to send Low TXD Output UART transmit data see GRLIB IP Library User s Manual Library dependencies Table 84 shows libraries that should be used when instantiating the core Table 84 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals APB signal definitions GAISLER UART Signals component Signal and component declaration Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all lib
200. 2 xy O See Be Sd Sees eS a ed Exception oe ty tae OS wae A Woinst o A See wipe j Sg ast AGAR wres l Y AN e AIN RA Write back 29 tbr wim psr Figure 166 LEON3 integer unit datapath diagram 372 44 2 2 Instruction pipeline The LEON integer unit uses a single instruction issue pipeline with 7 stages 1 FE Instruction Fetch If the instruction cache is enabled the instruction is fetched from the instruction cache Otherwise the fetch is forwarded to the memory controller The instruction is valid at the end of this stage and is latched inside the IU 2 DE Decode The instruction is decoded and the CALL and Branch target addresses are gener ated 3 RA Register access Operands are read from the register file or from internal data bypasses 4 EX Execute ALU logical and shift operations are performed For memory operations e g LD and for JMPL RETT the address is generated 5 ME Memory Data cache is accessed Store data read out in the execution stage is written to the data cache at this time 6 XC Exception Traps and interrupts are resolved For cache reads the data is aligned as appro priate 7 WR Write The result of any ALU logical shift or cache operations are written back to the register file Table 392 lists the cycles per instruction assuming cache hit and no icc or load interlock Table 392 Instruction timing Instruction Cycle
201. 2 6 Configuration options Table 438 shows the configuration options of the core VHDL generics Table 438 Configuration options 443 Generic Function Allowed range Default hindex Selects which AHB select signal HSEL will be used to access 0 to NAHBMAX 1 0 the PCI target core abits Number of bits implemented for PCI memory BAR 0 to 31 21 device_id PCI device id 0 to 65535 0 vendor_id PCI vendor id 0 to 65535 0 nsync One or two synchronization registers between clock regions 1 2 1 oepol Polarity of output enable signals O active low 1 active high 0 1 0 Signal descriptions Table 439 shows the interface signals of the core VHDL ports Table 439 Signals descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input AHB system clock PCICLK N A Input PCI clock PCI Input PCI input signals PCIO Output PCI output signals APBI 2 Input APB slave input signals APBO EZ Output APB slave output signals 1 see PCI specification 2 see GRLIB IP Library User s Manual The PCIO record contains an additional output enable signal vaden It is has the same value as aden at each index but they are all driven from separate registers A directive is placed on this vector so that the registers will not be removed during synthesis This output enable vector can be used instead of aden if output delay is an issue in
202. 29 4 clk address romsn ramsn oen data haddr htrans hready hrdata Registers 227 lead in data lead out Al A2 rake ve WP O dl Figure 100 I O read access with O wait states The core is programmed through registers mapped into APB address space Table 214 FT PROM SRAM IO controller registers APB Address offset Register 0x0 Memory configuration register 1 0x4 Memory configuration register 2 0x8 Memory configuration register 3 Table 215 Memory configuration register 1 31 27 26 25 24 23 20 19 18 17 14 13 12 11 10 9 8 7 4 3 0 RESERVED BR BE IOWS ROMBSZ EBSZ RW RBW RESERVED ROMWS 31 27 RESERVED 26 Bus ready enable BR Enables the bus ready signal BRDYN 25 Bus exception enable BE Enables the bus exception signal BEXCEN 24 RESERVED 23 20 T O wait states OWS Sets the number of waitstates for accesses to the I O area Only available if the wsreg VHDL generic is set to one 19 18 RESERVED 17 14 ROM bank size ROMBSZ Sets the PROM bank size Only available if the rombanksz VHDL generic is set to zero Otherwise the rombanksz VHDL generic sets the bank size and the value can be read from this field 0 8 kB 1 16 kB 15 256 MB 13 12 EDAC bank size EBSZ Sets the EDAC bank size for 8 bit PROM support Only available if the rombanksz VHDL generic is zero and edacen and prom8en VHDL
203. 298 36 1 OVerV A O 298 36 2 Opera A Meee ceas basen ecadseetakdee E can E E E S 298 36 3 ROESISTERS ic teu eescttiesit ret i oe la Rasa Rak is a 299 36 4 Confietitation Options iia Adi 299 36 5 Signal descriptor aaa riales 299 36 6 AAA dh cuccs ses ch ces eer ebeno erh seen KENS Eh CEE ses VEEE VE K SE ne VEESI rori 300 36 7 TnStantiation ts A PEA NAE EEA dee las AEA ds 300 10 37 38 39 40 41 42 43 GRFPU High performance IEEE 754 Floating point UNlt ooooconocononcnonononanononcnoncnannnonanons 301 37 1 OVA Wosicni ii odia supe tai 301 37 2 Functional description oooocnncnncconononconcnnnnonnnononn ereke sveket okki rehires roes neon aeS enn nan nE SKE EEO Er ESVE ancora con ncnnecnnons 301 37 3 Saako en 10 i St E E E E E ener 305 37 4 Minea ON AT 305 GREPC GREPU Control Units ari o 307 38 1 Floatins Pomtreglster le inet biie E A E ES 307 38 2 Floating Point State Register ESR ooonconicnnocnccnnocconncancnnncnnonanonnconoco non nocnnnnnnnnn cnn cnn non nrnn crono rn con non necnnons 307 38 3 Floating Point Exceptions and Floating Point Deferred Queue ooooonoccnocconnoccconcnnncnnnononancnnnnnnnnncnnonns 307 GRFPU Lite IEEE 754 Floating Point UnNit cooooocnnocccooncccnoncnononcnononncnnnnanonnnccnnnncconnnccnnnos 309 39 1 OVCIVI W e AE E a 309 39 2 Functional Description eeror rea india 309 GRLFPC GRFPU Lite Floating point unit Controller ooonccnncconccnoncconnnonancnoncnonccannnonnnon 312 40 1 O aa Ta
204. 2x core CPUCLK ahbi CPUCLK 2 CPUCLK CPUCLK ahbsi CPUCLK 2 CPUCLK CPUCLK ahbso CPUCLK 2 CPUCLK HCLK irqi CPUCLK 1 CPUCLK CPUCLK irqo HCLK 1 CPUCLK CPUCLK u0_0 p0 c0 syncO r 1 CPUCLK register Start point Through End point Propagation time dsu3_2x core CPUCLK ahbmi CPUCLK 2 CPUCLK CPUCLK ahbsi CPUCLK 2 CPUCLK dsui CPUCLK 1 CPUCLK r register rh register 1 CPUCLK irqmp2x core r2 register r register 1 CPUCLK 44 10 Clock gating To further reduce the power consumption of the processor the clock can be gated off when the pro cessor has entered power down state Since the cache controllers and MMU operate in parallel with the processor the clock cannot be gated immediately when the processor has entered the power down state Instead a power down signal DBGO idle is generated when all outstanding AHB accesses have been completed and it is safe to gate the clock This signal should be clocked though a positive 387 edge flip flop followed by a negative edge flip flop to guarantee that the clock is gated off during the clock low phase To insure proper start up state the clock should not be gated during reset LEON3CG RESETN E A DBGO IDLE y jo A a H GCLK AHB CLK gt CLK LEON3CG RESETN TEA DSUO PWD n GCLK AHB CLK gt CLK Figu
205. 3 0x13 29 Asynchronous interrupt 3 interrupt_level_4 0x14 28 Asynchronous interrupt 4 interrupt_level_5 0x15 27 Asynchronous interrupt 5 interrupt_level_6 0x16 26 Asynchronous interrupt 6 interrupt_level_7 0x17 25 Asynchronous interrupt 7 interrupt_level_8 0x18 24 Asynchronous interrupt 8 interrupt_level_9 0x19 23 Asynchronous interrupt 9 interrupt_level_10 Ox1A 22 Asynchronous interrupt 10 interrupt_level_11 0x1B 21 Asynchronous interrupt 11 interrupt_level_12 Ox1C 20 Asynchronous interrupt 12 interrupt_level_13 0x1D 19 Asynchronous interrupt 13 interrupt_level_14 Ox1E 18 Asynchronous interrupt 14 interrupt_level_15 Ox1F 17 Asynchronous interrupt 15 trap_instruction 0x80 OxFF 16 Software trap instruction TA 44 2 11 Single vector trapping SVT Single vector trapping SVT is an SPARC V8e option to reduce code size for embedded applications When enabled any taken trap will always jump to the reset trap handler tbr tba 0 The trap type will be indicated in tbr tt and must be decoded by the shared trap handler SVT is enabled by setting bit 13 in asr17 The model must also be configured with the SVT generic 1 376 44 2 12 Address space identifiers ASI In addition to the address a SPARC processor also generates an 8 bit address space identifier ASD providing up to 256 separate 32 bit address spaces During normal operation the LEON3 processor accesses instructions and data using ASI 0x8 OxB as defined in t
206. 31 0 Y 95 downto 64 Table 288 Point Y Output 3 Register 31 0 Y 127 downto 96 Table 289 Point Y Output 4 Register 31 0 Y 159 downto 128 Table 290 Point Y Output 5 Register 31 0 Y 191 downto 160 Table 291 Point Y Output 6 Register 31 0 Y 223 downto 192 Table 292 Point Y Output 7 Register most significant 31 9 8 0 Y 232 downto 224 33 8 6 Status Register R Table 293 Status Register 31 1 0 FS M 31 1 Unused 0 FSM 0 when ongoing when idle or ready 33 9 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x074 For description of vendor and device identifiers see GRLIB IP Library User s Manual 33 10 Configuration options 33 11 33 12 33 13 Table 294 shows the configuration options of the core VHDL generics Table 294 Configuration options 269 Generic Function Allowed range Default pindex APB slave index 0 NAPBSLV 1 0 paddr Addr field of the APB BAR 0 16 FFFH 0 pmask Mask field of the APB BAR 0 16 FFFH 16 FFC pirq Interrupt line used by the GRECC 0 NAHBIRQ 1 0 Signal descriptions Table 295 shows the interface signals of the core VHDL ports Table 295 Signal descriptions Signal name Field Type Function Active RSTN N A Input Reset Low CLK N A Input Clock APBI Input A
207. 40000000 0x40FFFFFF rammask MASK filed of the AHB BAR1 defining SRAM address space 0 16 FFF 16 FFO ioaddr ADDR filed of the AHB BAR2 defining IO address space 0 16 FFFH 16 200 Default IO area is 0x20000000 0x20FFFFFF iomask MASK filed of the AHB BAR2 defining IO address space 0 16 FFF 16 FFO ramws Number of waitstates during access to SRAM area 0 15 0 romws Number of waitstates during access to PROM area 0 15 2 iows Number of waitstates during access to IO area 0 15 2 rmw Enable read modify write cycles 0 1 0 prom8en Enable 8 bit PROM accesses 0 1 0 oepol Polarity of bdrive and vbdrive signals 0 active low 1 active 0 1 0 high srbanks Set the number of SRAM banks 1 5 1 banksz Set the size of bank 1 4 0 8 Kbyte 1 16 Kbyte 13 0 13 13 64Mbyte romasel address bit used for PROM chip select 0 27 19 56 8 Signal description Table 455 shows the interface signals of the core VHDL ports Table 456 Signal descriptions 461 Signal name Field Type Function Polarity CLK N A Input Clock RST N A Input Reset Low SRI DATA 31 0 Input Memory data High BRDYN Input Not used BEXCN Input Not used WRNI 3 0 Input Not used BWIDTH 1 0 Input BWIDTH 00 gt 8 bit PROM mode BWIDTH 10 gt 32 bit PROM mode SD 31 0 Input Not used 5 SRO ADDRESS 27 0 Output Memory address High DATA 31 0 Outpu
208. 5 1 0 000 0 IM 15 1 0 Figure 163 Processor interrupt mask register 31 16 Reserved 15 1 Broadcast Mask n BM n If BMn 1 the interrupt n is broadcasted written to the Force Register of all CPUs otherwise standard semantic applies Pending Register 0 Reserved 43 3 8 Processor interrupt force register NCPU gt 0 31 17 16 15 1 0 IFC 15 1 0 TF 15 1 0 Figure 164 Processor interrupt force register 31 17 Interrupt force clear n IFC n 15 1 Interrupt Force n 1F n Force interrupt nr n 0 Reserved Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier OxOOD For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 389 shows the configuration options of the core VHDL generics Table 389 Configuration options Generic Function Allowed range Default pindex Selects which APB select signal PSEL will be used to 0 to NAPBMAX 1 0 access the timer unit paddr The 12 bit MSB APB address 0 to 4095 0 pmask The APB address mask 0 to 4095 4095 ncpu Number of processors in multiprocessor system 1 to 16 1 367 43 6 Signal descriptions Table 390 shows the interface signals of the core VHDL ports Table 390 Signal descriptions Signal name Field Type Functi
209. 6 32 bit PROM SRAM non sequential write access with 0 wait states and EDAC disabled 225 lead in datai data2 datai data2 datai data2 lead out sy O E GE TD romsn Pl AL a dl Pe ramsn writen MS A A el A ct CEND ELAD E cb S a M ee E 00 hready jeer Cot X P2 Xx P Figure 97 32 bit PROM SRAM sequential write access with O wait states and EDAC disabled If waitstates are configured through the VHDL generics or registers one extra data cycle will be inserted for each waitstate in both read and write cycles The timing for write accesses is not affected when EDAC is enabled while one extra latency cycle is introduced for single access reads and at the beginning of read bursts 226 aia romsn i a O O ramsn writen oen AA E a EA O data Daiji e CBI CMI haddr A1 A2 htrans 10 00 hready wees Figure 98 32 bit PROM SRAM rmw access with 0 wait states and EDAC disabled Read Modify Write RMW accesses will have an additional waitstate inserted to accommodate decoding when EDAC is enabled VO accesses are similar to PROM and SRAM accesses but a lead in and lead out cycle is always present lead in datai data2 data3 lead out ae romsn amen a oe co E O E ramsn writen P J LSJT TO PF Pp ee haddr A1 A2 htrans 10 00 hready pee Figure 99 I O write access with 0 wait states
210. 6 4 us timer Used if usegen VHDL generic is set to 0 SWNO D Output Data output S Output Strobe output TICKOUT Output Time counter tick output High see GRLIB IP Library User s Manual 42 13 Library dependencies Table 337 shows libraries used when instantiating the core VHDL libraries Table 337 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER SPACEWIRE Signals component Component and record declarations 42 14 Instantiation This example shows how the core can be instantiated Normally di si do and so should be connected to input and output pads configured with LVDS driv ers How this is done is technology dependent The GRSPW in the example is configured with non ft memories of size 4 64 and 8 entries for AHB FIFOs N Char FIFO and RMAP buffers respectively The system frequency clk is 40 MHz and the transmitter frequency txclk is 20 MHz The memory technology is inferred which means that the synthesis tool will select the appropriate components The rx clk buffer uses a hardwired clock 342 42 15 The hardware RMAP command handler is enabled which also automatically enables rxunaligned and rmapcrc The Finally the DMA channel interrupt line is 2 and the number of synchronization registers is 1 library ieee use ieee std_logic_1164 all library grlib use grlib amb
211. 8 7 6 5 4 3 2 1 0 SE SI RAM BANK SIZE RBRDY RMW RAM WIDTH RAM WRITE WS RAM READ WS 31 30 29 26 257 223 20 18 17 16 14 13 12 27 23 21 19 15 SDRAM refresh SDRF Enables SDRAM refresh SRAM TRP parameter TRP tgp will be equal to 2 or 3 system clocks 0 1 SDRAM TRFC parameter SDRAM TRFC tree will be equal to 3 field value system clocks SDRAM TCAS parameter TCAS Selects 2 or 3 cycle CAS delay 0 1 When changed a LOAD COMMAND REGISTER command must be issued at the same time Also sets RAS CAS delay trep SDRAM bank size SDRAM BANKSZ Sets the bank size for SDRAM chip selects 000 4 Mbyte 001 8 Mbyte 010 16 Mbyte 111 512 Mbyte SDRAM column size SDRAM COLSZ 00 256 01 512 10 1024 11 4096 when bit 25 23 111 2048 otherwise SDRAM command SDRAM CMD Writing a non zero value will generate a SDRAM command 01 PRECHARGE 10 AUTO REFRESH 11 LOAD COMMAND REGISTER The field is reset after the command has been executed 64 bit SDRAM data bus D64 Reads 1 if the memory controller is configured for 64 bit SDRAM data bus width 0 otherwise Read only SDRAM Page Burst SDPB SDRAM programmed for page bursts on read when set else pro grammed for line burst lengths of 8 on read Programmable when pageburst VHDL generic is 2 else
212. A Output Xilinx User defined Data Register 1 selected High Xilinx tech only TAPO_XSEL2 N A Output Xilinx User defined Data Register 2 selected High Xilinx tech only TAPI_EN1 N A Input Enable shift out data port 1 TAPI_TDO1 when High disabled data on port 2 is used TAPI_TDO1 N A Input Shift out data from user defined register port 1 High TAPI_TDO2 N A Input Shift out data from user defined register port 2 High If the target technology is Xilinx or Altera the cores JTAG signals TCK TCKN TMS TDI and TDO are not used Instead the dedicated FPGA JTAG pins are used These pins are implicitly made visible to the core through technology specific TAP macro instantiation 491 62 8 Library dependencies Table 482 shows libraries used when instantiating the core VHDL libraries Table 482 Library dependencies Library Package Imported unit s Description GAISLER JTAG Component TAP Controller component declaration 62 9 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library gaisler use gaisler jtag all entity tap_ex is port elk dn std logic rst in std_ulogic JTAG signals tck in std_ulogic tms in std_ulogic tdi in std_ulogic tdo out std_ulogic i end architecture rtl of tap_ex is signal gnd std_ulogic signal tapo_tck tapo_tdi tapo_rst tapo_capt std_ulogic signal tapo_sh
213. AHB BAR defining I O address space 0 16 FFFH 16 000 where SDCFG register is mapped iomask MASK filed of the AHB BAR1 defining I O address space 0 16 FFFH 16 FFF wprot Write protection 0 1 0 invclk Inverted clock is used for the SDRAM 0 1 0 pwron Enable SDRAM at power on initialization 0 1 0 sdbits 32 or 64 bit data bus width 32 64 32 oepol Polarity of bdrive and vbdrive signals 0 active low 1 active 0 1 0 55 6 55 7 55 8 Signal descriptions Table 453 shows the interface signals of the core VHDL ports Table 453 Signal descriptions 455 Signal name Field Type Function Active CLK N A Input Clock RST N A Input Reset Low AHBSI 1 Input AHB slave input signals AHBSO 1 Output AHB slave output signals SDI WPROT Input Not used DATA 63 0 Input Data High SDO SDCKE 1 0 Output SDRAM clock enable High SDCSN 1 0 Output SDRAM chip select Low SDWEN Output SDRAM write enable Low RASN Output SDRAM row address strobe Low CASN Output SDRAM column address strobe Low DQM 7 0 Output SDRAM data mask Low DQM 7 corresponds to DATA 63 56 DQM 6 corresponds to DATA 55 48 DQM 5 corresponds to DATA 47 40 DQM 4 corresponds to DATA 39 32 DQM 3 corresponds to DATA 31 24 DQM 2 corresponds to DATA 23 16 DQM 1 corresponds to DATA 15 8 DQM 0 corresponds to DATA 7 0 BDRIVE Output Drive SDRAM data bus Low High VBDRIVE 31 0
214. ANSMITTER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR POINTER RESERVED Figure 119 GRETH transmitter descriptor table base address register 31 10 Base address to the transmitter descriptor table Not Reset 9 3 Pointer to individual descriptors Automatically incremented by the Ethernet MAC 2 0 Reserved Reads as zeroes 280 31 10 9 3 2 0 RECEIVER DESCRIPTOR TABLE BASE ADDRESS DESCRIPTOR POINTER RESERVED Figure 120 GRETH receiver descriptor table base address register 31 10 Base address to the receiver descriptor table Not Reset 9 3 Pointer to individual descriptors Automatically incremented by the Ethernet MAC 2 0 Reserved Reads as zeroes 31 0 EDCL IP ADDRESS Figure 121 GRETH EDCL IP register 31 0 EDCL IP address Reset value is set with the ipaddrh and ipaddrl generics 34 10 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x1D For description of vendor and device identifiers see GRLIB IP Library User s Manual 34 11 Configuration options Table 302 shows the configuration options of the core VHDL generics Table 302 Configuration options 281 Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr Addr field of the APB bar 0 16 FFFH 0 pmask Mask field of the APB b
215. B IP Library User s Manual 19 8 Library dependencies Table 107 shows libraries used when instantiating the core VHDL libraries Table 107 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals Signal definitions GAISLER B1553 Signals component Signal and component declaration The B1553BRM depends on VHDL libraries GRLIB GAISLER GR1553 and Core1553BRM 19 9 Component declaration The core has the following component declaration component b1553brm is generic hindex integer 0 pindex integer 0 paddr integer 0 pmask integer 16 ff0 pirg integer 0 ahbaddr integer range 0 to 16 FFFFF 0 abits integer range 12 to 17 16 rtaddr integer range 0 to 31 0 rtaddrp integer range 0 to 1 lockn integer range 0 to 1 mselin integer range 0 to 3 1 abstdin integer range 0 to 0 bcenable integer range 0 to 1 rtenable integer range 0 to 1 mtenable integer range 0 to 1 legregs integer range 0 to 4 1 enhanced integer range 0 to 1 initfreg integer range 12 to 24 20 betiming integer range 0 to i port rstn in std_ulogic rstoutn out std_ulogic clk A std_ulogic telk in std_ulogic brmi 2 ZA brm1553_in_type brmo out brm1553_out_type b1553i s aan b1553_in_type b15530 out b1553_out_type apbi in apb_slv_in_type apbo out apb_slv_out_type ahbi
216. B Map Address AHB MAP Maps PCI accesses to PCI BAR1 address space to AHB address space AHB address is formed by concatenating AHB MAP with LSB of the PCI address dmaabits 1 0 Reserved Reads always as 00 0 PCI Master Interface PCI Master interface occupies 256 MB of AHB memory address space and 128 kB of AHB I O address space PCI Master interface handles AHB accesses to its back end AHB Slave interface and translates them to PCI configuration memory or I O cycles Mapping of PCI masters AHB address space is configurable through VHDL generics PCI cycles per formed on the PCI bus are directly dependable on AHB access and value in Configuration Status reg ister The PCI Master interface is capable of performing following PCI cycles PCI Configuration Cycles Single PCI Configuration cycles are performed by accessing upper 64 kB of AHB I O address space allocated by the PCI Masters AHB Slave Type 0 Configuration cycles are supported Figure below shows mapping of LSB of AHB I O address 31 16 15 11 10 8 7 21 4 AHB ADDRESS MSB IDSEL FUNC REGISTER 00 Figure 210 Mapping of AHB I O addresses to PCI address for PCI Configuration cycles 31 16 AHB Address MSB Not used for Configuration cycle address mapping 15 11 IDSEL This field is decoded to drive PCI AD IDSEL 10 AD 31 11 signal lines are supposed to drive IDSEL lines during Configuration Cycles 10 8 Function Number FUNC Selects fu
217. B receiver High busboutin Inhibit for the B transmitter High busboutp Positive output to the B transmitter High busboutn Negative output to the B transmitter Low APBI Input APB slave input signals APBO i Output APB slave output signals AHBI 6 Input AMB master input signals AHBO Output AHB master output signals see GRLIB IP Library User s Manual Library dependencies Table 103 shows libraries used when instantiating the core VHDL libraries Table 103 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals Signal definitions GAISLER B1553 Signals component Signal and component declaration The B1553BC depends on GRLIB GAISLER GR1553 and Core1553BBC Component declaration The core has the following component declaration component b1553bc is generic hindex integer 0 pindex integer 0 paddr integer 0 pmask integer l6 fff pirg integer 0 i port rstn in std_ulogic clk in std_ulogic b1553i in b1553_in type b15530 out b1553_out_type apbi in apb_slv_in type apbo out apb_slv_out_type ahbi in ahb_mst_in type ahbo out ahb_mst_out_type end component 18 10 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler b1553 all signal bin b1553_in_type s
218. B4 Sn 2 10 unlimited virtex2 Xilinx Virtex2 Spartan3 Virtex4 RAMB16_Sn 2 14 unlimited Spartan3e axcel Actel AX RTAX RAM64K36 2 12 unlimited proasic Actel Proasic RAM256x9SST 2 14 unlimited proasic3 Actel Proasic3 ram4k9 ram512x18 2 12 unlimited lattice Lattice XP EC ECP dp8ka 2 13 unlimited memvirage Virage ASIC RAM hdss2_64x32cm4sw0 6 9 32 hdss2_128x32cm4sw0 hdss2_256x32cm4swO hdss2_512x32cm4sw0 memartisan Artisan ASIC RAM rf2_256x32m4 8 9 32 rf2_512x32m4 484 60 3 60 4 60 5 60 6 Signal descriptions Table 474 shows the interface signals of the core VHDL ports Table 474 Signal descriptions Signal name Field Type Function Active RCLK N A Input Read port clock RENABLE N A Input Read enable High RADDRESS N A Input Read address bus DATAOUT N A Output Data outputs for read data WCLK N A Input Write port clock WRITE N A Input Write enable High WADDRESS N A Input Write address DATAIN N A Input Write data Library dependencies Table 475 shows libraries used when instantiating the core VHDL libraries Table 475 Library dependencies Library Package Imported unit s Description TECHMAP GENCOMP Constants Technology contants Component declaration The core has the following component declaration library techmap use techmap gencomp all component syncram_2p generic tech integer 0 abits integer 6 dbits i
219. CEPT and CC outputs Table 135 shows signal timing during four arithmetic operations on GRFPU OPERAND4 OPERAND2 Ss DEE 006 OPID READY RESID RESULT ALLOW 2 ALLOW 1 ALLOW 0 S0p L Bl 004 ion a E Figure 135 Signal timing 38 38 1 38 2 38 3 307 GRFPC GRFPU Control Unit GRFPU Control Unit GRFPC is used to attach the GRFPU to the LEON integer unit 1U GRFPC performs scheduling decoding and dispatching of the FP operations to the GRFPU as well as manag ing the floating point register file the floating point state register FSR and the floating point deferred trap queue FQ Floating point operations are executed in parallel with other integer instruc tions the LEON integer pipeline is only stalled in case of operand or resource conflicts In the FT version all registers are protected with TMR and the floating point register file is protected using 39 7 BCH coding Correctable errors in the register file are detected and corrected using the instruction restart function in the IU Floating Point register file GRFPU floating point register file contains 32 32 bit floating point registers f0 f31 The regis ter file is acces
220. Can RxWR WRITE is automatically incremented taking wrap around effects of the circular buffer into account Whenever the read pointer CanRxRD READ equals CanRxWR WRITE 1 modulo Can RxSIZE SIZE 4 there is no space available for receiving another CAN message The error behavior of the CAN core is according to the CAN standard which applies to the error counter buss off condition and error passive condition 22 6 3 Location The location of the circular buffer is defined by a base address CanRxADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary 22 6 4 Reception procedure When the channel is enabled CanRxCTRL ENABLE 1 and there is space available for a message in the circular buffer as defined by the write and read pointer as soon as a message is received by the CAN core an AMBA AHB store access will be started The received message will be temporarily stored in a local store buffer in the CAN controller Note that the channel should not be enabled until the write and read pointers are configured to avoid the message reception to start prematurely After a message has been successfully stored the CAN controller is ready to receive a new message The write pointer CanRxWR WRITE is automatically incremented taking wrap around effects of the circular buffer into account Interrupts are provided to aid the user during reception as described in detail later in this se
221. DAC is present 26 12 SDRAM refresh counter reload value SDRAM REFRESH COUNTER 11 EDAC diagnostic write bypass WB Enables EDAC write bypass 10 EDAC diagnostic read bypass RB Enables EDAC read bypass 9 RAM EDAC enable RE Enable EDAC checking of the RAM area including SDRAM 8 PROM EDAC enable PE Enable EDAC checking of the PROM area Ar reset this bit is initial ized with the value of MEMI EDAC 7 0 Test checkbits TCB This field replaces the normal checkbits during write cycles when WB is set It is also loaded with the memory checkbits during read cycles when RB is set The period between each AUTO REFRESH command is calculated as follows tREFRESH reload value 1 SYSCLK 27 16 Vendor and device identifiers The core has vendor identifier 0x01 GAISLER and device identifier OxO5F For description of ven dor and device identifiers see GRLIB IP Library User s Manual 27 17 Configuration options Table 203 shows the configuration options of the core VHDL generics Table 203 Configuration options Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 pindex APB slave index 0 NAPBSLV 1 0 romaddr ADDR field of the AHB BARO defining PROM address space 0 16 FFF 16 000 Default PROM area is 0x0 Ox 1FFFFFFF rommask MASK field of the AHB BARO defining PROM address space 0
222. DER A Y Y SLAVE SLAVE Figure 3 AHB controller block diagram Operation 4 2 1 Arbitration The AHB controller supports two arbitration algorithms fixed priority and round robin The selection is done by the VHDL generic rrobin In fixed priority mode rrobin 0 the bus request priority is equal to the master s bus index with index O being the lowest priority If no master requests the bus the master with bus index 0 set by the VHDL generic defmast will be granted In round robin mode priority is rotated one step after each AHB transfer If no master requests the bus the last owner will be granted bus parking During incremental bursts the AHB master should keep the bus request asserted until the last access as recommended in the AMBA 2 0 specification or 1t might loose bus ownership For fixed length burst the AHB master will be granted the bus during the full burst and can release the bus request immediately after the first access has started For this to work however the VHDL generic fixbrst should be set to 1 4 2 2 Decoding Decoding generation of HSEL of AHB slaves is done using the plug amp play method explained in the GRLIB User s Manual A slave can occupy any binary aligned address space with a size of 1 4096 Mbyte A specific I O area is also decoded where slaves can occupy 256 byte 1 Mbyte The default address of the I O area is OxFFF00000 but can be changed with the cfgaddr and cfgmask
223. DL ports Table 31 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input System clock AHB clock domain TCK N A Input JTAG clock TCKN N A Input Inverted JTAG clock TMS N A Input JTAG TMS signal High TDI N A Input JTAG TDI signal High TDO N A Output JTAG TDO signal High AHBI aA Input AHB Master interface input AHBO Fkk Output AHB Master interface output TAPO_TCK N A Output TAP Controller User interface TCK signal High TAPO_TDI N A Output TAP Controller User interface TDI signal High TAPO_INST 7 0 N A Output TAP Controller User interface INSTsignal High TAPO_RST N A Output TAP Controller User interface RST signal High TAPO_CAPT N A Output TAP Controller User interface CAPT signal High TAPO_SHFT N A Output TAP Controller User interface SHFT signal High TAPO_UPD N A Output TAP Controller User interface UPD signal High TAPI_TDO N A Input TAP Controller User interface TDO signal High If the target technology is Xilinx or Altera the cores JTAG signals TCK TCKN TMS TDI and TDO are not used Instead the dedicated FPGA JTAG pins are used These pins are implicitly made visible to the core through TAP controller instantiation User interface signals from the JTAG TAP controller These signals are used to interface additional user defined JTAG data registers such as boundary scan registe
224. EEE SS 208 27 22 InstantlatlON o iaa ibas elias 208 FTSDCTRL 32 64 bit PC133 SDRAM Controller with EDAC oo eee eeteeeseeeeeee 211 28 1 OVEIVl Wisin a aiii 211 28 2 Operator i 211 28 3 ROSIStERS ii sd 213 28 4 Vendor and device 1Gent Hers suitte edi 215 28 5 Configuration Options ias RT E a E EE E E T E E aS 215 28 6 Signal descriptions 0 cccccvssteseck ced ipevsckcistaces heoo ias each iniciaran cus EEE EESE SASN esa 216 28 7 Library dependencies a ol raar a r Er el aE rE aE iii pida 216 29 30 31 32 33 28 8 TStA O eee E A E E E E R E A Nemeeetestoeensts 216 FTSRCTRL Fault Tolerant 32 bit PROM SRAM IO Controller oooonccnoccnnocnnocnnonncconcnnnno 219 29 1 DA E aes 219 29 2 OPA E E E E ERE ab 219 29 3 PROM SRA M O PAVE OT S a E aa aa e castes Seassssesbiecesstesbepbbevsestaeaieess 222 29 4 A NN 227 29 5 Vendorand device identifiers iss sisiisci teens eg nnn nein ate ee Sees 228 29 6 Configuration Options min 229 29 7 Signal description S midi 229 29 8 Library dep ndencies cti rra dat ra dea 232 29 9 Component declaration sssrinin irinse crisissen evei les erekere eroe EErEE Ek ECEN dssraceschesdeveus dei 232 29 10 O RR 232 FTSRCTRLS 8 bit SRAM 16 bit IO Memory Controller with EDAC eee 236 30 1 COVERVISW es assess onoke eioen Een tee ed dessa ch ied cncus EOE Gavccensechsvtes heb eiii dd dad his reinado 236 30 2 Operation ita 236 30 3 SRAM IO A A 237 30 4 REGISTERS di ias 241 30 5 Vendor and device ide
225. Eiras EEn ENESTE eE aTe RE GAE KOOP ses stecbabeascbeessbeveess 482 59 5 Component declarations 2 ois cent e e EEE di E 482 59 6 Instant OM a E E E es O eS ee ee 482 SYNCRAM_2P Two port RAM generator oococcnccccnoncncnoncnononcnnnnncncnnnnnnnnnn cnn nc cnn na cnnnnccnnnss 483 60 1 OV ELVIS Wisin orar 483 60 2 Configuration Options ns 483 60 3 Signal descriptions stat dit 484 60 4 Elbrary dependencies asias 484 60 5 A NN 484 60 6 A NN 484 SYNCRAM_DP Dual port RAM generatOT coccoococconcccnnnccnnonnnononcnonnnannnnnncnonnnconnnccnnnncnnnnss 486 61 1 VEL VIC W E E EE E EE cessed Dag RS UE sock bss SEA aida ane oes es 486 61 2 Configuration Options vocacion pitiriasis 486 61 3 Signal descriptions 3 siecle Ro eo aa 487 61 4 Library dependencia 487 61 5 Component declaration 4 4 23s Aes ei A 487 61 6 E A 487 TAP JTAG TAP Eolo ds 489 62 1 Overview iiss eos E A 489 62 2 ON 489 62 3 Technology specific TAP controllers iiime nE n TE non ran con ncan E c conca necnnons 489 62 4 ROBISTERS conociste dad ies tasa edi 489 62 5 Vendor and deviceGent Hers citar its 489 62 6 Configuration Options cur pira pda 490 62 7 Signal descriptions ieren E E E ae endosteal A ei 490 62 8 AA ea Eie E Enia oee ES p Se EE Pa EEE SERA SESE ne PESEE E OSE R aios 491 62 9 A TS 491 USBDCL USB Debug Communication Lidk oonccnnncninncnoncnoncnnnancnoncnoncnnno conan cnn cnn ncnnnnos 492 63 1 COVEEVICW sss ican sick NN 492 63 2 O A 492 63 3 RESISLERS ainia rs
226. FF 16 FFFH edacen Enable 1 Disable 0 on chip EDAC Otol 0 autoscrub Automatically store back corrected data with new check 0 to 1 0 bits during a read when a single error is detected Is ignored when edacen is deasserted errcnten Enables a single error counter Otol 0 entbits number of bits in the single error counter 1to8 1 ahbpipe Enable pipeline register on AHB input signals Otol 0 Signal descriptions Table 195 shows the interface signals of the core VHDL ports Table 195 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals APBI me Input APB slave input signals APBO Output APB slave output signals ARAMO CE Output Single error detected High see GRLIB IP Library User s Manual Library dependencies Tabel 196 shows libraries used when instantiating the core VHDL libraries Table 196 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Signals and component declaration 26 8 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib library gaisler use grlib amba all use gaisler misc all entity ftram_ex is port rst std_ulogic clk std_ulogic others signals i
227. GRE GAISLER RESEARCH GRLIB IP Core User s Manual Version 1 0 15 April 2007 Jiri Gaisler Edvin Catovic Marko Isom ki Kristoffer Glembo Sandi Habinc Copyright Gaisler Research 2007 Table of contents is Y 16 1 1 O A E 16 1 2 IP COLE NS A TAE A EEE E aii 16 1 3 Implementation Characteristics 0 0 0 eececeececeeseeeceseeeeeeseecsecsaesaecsacsecseceseeeceeeeeseseseaecaeseaecsaesaecseenaes 19 AHB2AHB Uni directional AHB to AHB bridge eee ceeseceeececeeeeeceeeeeeeeeeeneeeeaees 21 2 1 OI RATA E it pt 21 2 2 Operation td bi nee rei ae 21 2 3 A NO 22 2 4 Vendor and device identifiers ooooonccnocnonnconconncononononnnononan cnn ncnn E A E non n nan near r E 22 2 5 CONTISULAtION Options its tiva 23 2 6 Signal description iia ea eta Asean a eae ee eee 24 2 7 Library dependencia ni ananiona n unc lead a a a ceeuaussdsteses deseada des desd 24 2 8 Insta ii Bos sasduosvensastiabarteent apiesseness 24 AHBBRIDGE Bi directional AHB AHB bridge ooooocononcccnocccononcnononcnononcnononcnonanccnnnnccnnnnoss 26 3 1 OVELVICW aE E E es staces E dace th ocheh cokes sobs Sebaacebees ans iebions hovecesnshoesioseea d dais sos 26 3 2 OPCratiOn NN 26 3 3 Registers ain i Bastien i hinds ans ii ib Erse 26 3 4 Vendor and device Identifiers cociendo ib inicie 26 3 5 Configuration Opuons menis ar a E r E Ba aie a A GR EE NY 27 3 6 Signal descriptions ctra tits 28 3 7 Elbrary dependencies parao 28 AHBCTRL AMBA AHB controller with plug amp
228. HB clock HSB_AHBSI Input High speed bus AHB slave input signals HSB_AHBSO Output High speed bus AHB slave output signals HSB_AHBSOV Input High speed bus AHB slave input signals HSB_AHBMI Input High speed bus AHB master input signals HSB_AHBMO Output High speed bus AHB master output signals LSB_AHBSI Input Low speed bus AHB slave input signals LSB_AHBSO Output Low speed bus AHB slave output signals LSB_AHBSOV Input Low speed bus AHB slave input signals LSB_AHBMI Input Low speed bus AHB master input signals LSB_AHBMO Output Low speed bus AHB master output signals Library dependencies Table 21 shows the libraries used when instantiating the core VHDL libraries Table 21 Library dependencies Library Package Imported unit s Description GRLIB AMBA AMBA signal definitions GAISLER MISC Component declaration 4 1 4 2 29 AHBCTRL AMBA AHB controller with plug amp play support Overview The AMBA AHB controller is a combined AHB arbiter bus multiplexer and slave decoder according to the AMBA 2 0 standard The controller supports up to 16 AHB masters and 16 AHB slaves The maximum number of masters and slaves are defined in the GRLIB AMBA package in the VHDL constants NAHBSLV and NAH BMST It can also be set with the nahbm and nahbs VHDL generics MASTER MASTER A A AHBCTRL EN ARBITER DECO
229. I DATA 31 0 Input Memory data High BRDYN Input Not used BEXCN Input Not used WRNI 3 0 Input Not used BWIDTH 1 0 Input Not used SD 63 0 Input Not used E CB 7 0 Input Not used SCB 7 0 Input Not used EDAC Input Not used 470 Table 460 Signal descriptions Signal name Field Type Function Polarity SRO ADDRESS 27 0 Output Memory address High DATA 31 0 Output Memory data High SDDATA 63 0 Output Not used RAMSN 7 0 Output SSRAM chip select only bit 0 is used Low RAMOEN 7 0 Output Same as OEN Low IOSN Output T O chip select Low ROMSN 7 0 Output PROM chip select only bit 0 is used Low OEN Output Output enable Low WRITEN Output Write strobe Low WRNI 3 0 Output SSRAM byte write enable Low WRNI 0 corresponds to DATA 31 24 WRN 1 corresponds to DATA 23 16 WRN 2 corresponds to DATA 15 8 WRN 3 corresponds to DATA 7 0 MBEN 3 0 Output Not used Low BDRIVE 3 0 Output Drive byte lanes on external memory bus Con Low High trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 31 24 BDRIVE 1 corresponds to DATA 23 16 BDRIVE 2 corresponds to DATA 15 8 BDRIVE 3 corresponds to DATA 7 0 Any BDRIVE signal can be used for CB VBDRIVE 31 0 Output Identical to BDRIVE but has one signal for each L ow High data bit Every index is driven by its own regis t
230. IDEO_OUT_G 7 0 Video out color red VIDEO_OUT_B 7 0 Video out color green Video out color blue see GRLIB IP Library User s Manual Library dependencies Table 88 shows libraries used when instantiating the core VHDL libraries Table 88 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals APB signal definitions GAISLER MISC Signals component VGA signal and component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler misc all architecture rtl of apbuart_ex is signal apbi apb_slv_in type signal apbo apb_slv_out_vector others gt apb_none signal vgao apbvga_out_type begin AMBA Components are instantiated here APB VGA vga0 apbvga generic map memtech gt 2 pindex gt 6 paddr gt 6 port map rstn clk vgaclk apbi apbo 6 vgao end 93 94 17 17 1 17 2 ATACTRL ATA Controller Overview The AT Attachment controller ATACTRL is an ATA ATAPI 5 host interface based on the OCIDEC 2 IP core from OpenCores This IP core provides an interface to IDE Integrated Drive Electronics devices compatible to the ATA ATAPI 5 standard Only PIO transfer support is implemented i e DMA transfer is not supported Figure 36 s
231. IDTH Sets the data width of the RAM area 00 8 01 16 1X 32 RAM write waitstates RAM WRITE WS Sets the number of wait states for RAM write cycles 00 0 01 1 10 2 11 3 RAM read waitstates RAM READ WS Sets the number of wait states for RAM read cycles 00 0 01 1 10 2 11 3 47 13 3 Memory configuration register 3 MCFG3 MCFG3 is contains the reload value for the SDRAM refresh counter 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RESERVED SDRAM REFRESH RELOAD VALUE RESERVED 31 27 RESERVED 26 12 SDRAM refresh counter reload value SDRAM REFRESH RELOAD VALUE 11 0 RESERVED The period between each AUTO REFRESH command is calculated as follows REFRESH reload value 1 SYSCLK 47 14 Vendor and device identifiers The core has vendor identifier 0x04 ESA and device identifier OxOOF For description of vendor and device identifier see GRLIB IP Library User s Manual 416 47 15 Configuration options Table 417 shows the configuration options of the core VHDL generics Table 417 Configuration options Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 pindex APB slave index 0 NAPBSLV 1 0 romaddr ADDR filed of the AHB BARO defining PROM ad
232. IP Library User s Manual 21 9 21 10 21 11 21 12 Configuration options Table 147 shows the configuration options of the core VHDL generics Table 147 Configuration options 137 Generic Function Allowed range Default slvndx AHB slave bus index 0 NAHBSLV 1 0 ioaddr The AHB T O area base address Compared with bit 19 8 O 16 FFF 16 FFF of the 32 bit AHB address iomask The I O area address mask Sets the size of the I O area 0 16 FFF 16 FFO and the start address together with ioaddr irq Interrupt number 0 NAHBIRQ 1 0 memtech Technology to implement on chip RAM 0 0 NTECH Signal descriptions Table 148 shows the interface signals of the core VHDL ports Table 148 Signal descriptions Signal name Field Type Function Active CLK Input AHB clock RESETN Input Reset Low AHBSI E Input AMBA AHB slave inputs AHBSO Input AMBA AHB slave outputs CAN_RXI Input CAN receiver input High CAN_TXO Output CAN transmitter output High 1 see AMBA specification Library dependencies Table 149 shows libraries that should be used when instantiating the core Table 149 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions GAISLER CAN Component Component declaration Component declaration library grlib use grlib amba all use gaisler can all component can_
233. IRQ 1 0 txchannels Number of transmit channels 1 1 1 rxchannels Number of receive channels 1 1 1 ptrwidth Width of message pointers 4 16 16 Signal descriptions Table 173 shows the interface signals of the core VHDL ports Table 173 Signal descriptions Signal name Field Type Function Active RSTN N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals AHBI Input AMB master input signals AHBO Output AHB master output signals CANI Rx 1 0 Input Receive lines CANO Tx 1 0 Output Transmit lines En 1 0 Transmit enables see GRLIB IP Library User s Manual 159 22 14 Library dependencies Table 174 shows the libraries used when instantiating the core VHDL libraries Table 174 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER CAN Signals component GRCAN component and signal declarations 22 15 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library gaisler use gaisler can all entity example is generic padtech in integer 0 port CAN interface cantx out std_logic_vector 1 downto 0 canrx in std_logic_vector 1 downto 0 canen out std_logic_vector 1 downto 0 Signal declarations signal rstn std_ulogic signal clive std_ulogic
234. IRQ 3 1553 signals gt CPU IF MEM IF 4 Y A Yy APB slave IF ee I AHB master IF AMBA APB AMBA AHB Figure 39 Block diagram 102 18 2 18 3 18 4 AHB interface The Core1553BBC operates on a 65536 x 16 bit memory buffer and therefore a 128 kilobyte aligned memory area should be allocated The memory is accessed via the AMBA AHB bus The Core1553BBC uses only 16 address bits and the top 15 address bits of the 32 bit AHB address can be programmed in the AHB page address register The 16 bit address provided by the Core1553BBC is left shifted one bit and forms the AHB address together with the AHB page address register Note that all pointers given to the Corel553BBC core need to be right shifted one bit because of this All AHB accesses are done as half word single transfers The endianness of the interface depends on the endian VHDL generic The AMBA AHB protection control signal HPROT is driven permanently with 0011 i e a not cacheable not bufferable privileged data access The AMBA AHB lock signal HLOCK is driven with 0 Operation To transmit data on the 1553 bus an instruction list and 1553 messages should be set up in the mem ory by the processor After the bus interface has been activated it will start to process the instruction list and read write data words from to the specified memory locations Interrupts are generated when interrupt instructions are execute
235. Input Checkbits SDO SDCKE 1 0 Output SDRAM clock enable High SDCSN 1 0 Output SDRAM chip select Low SDWEN Output SDRAM write enable Low RASN Output SDRAM row address strobe Low CASN Output SDRAM column address strobe Low DQM 7 0 Output SDRAM data mask Low DQM 7 corresponds to DATA 63 56 DQM 6 corresponds to DATA 55 48 DQM 5 corresponds to DATA 47 40 DQM 4 corresponds to DATA 39 32 DQM 3 corresponds to DATA 31 24 DQM 2 corresponds to DATA 23 16 DQM 1 corresponds to DATA 15 8 DQM 0 corresponds to DATA 7 0 Any DQM signal can be used for CB BDRIVE Output Drive SDRAM data bus Low ADDRESS 16 2 Output SDRAM address DATA 31 0 Output SDRAM data CB 7 0 Output Checkbits CE N A Output Correctable Error High see GRLIB IP Library User s Manual Library dependencies Table 5 shows libraries used when instantiating the core VHDL libraries Table 213 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Instantiation This example shows how the core can be instantiated 217 The example design contains an AMBA bus with a number of AHB components connected to it including the FT SDRAM controller The external SDRAM bus is defined in the example designs port map and connected to the SDRAM controller System clock
236. K Output Transmitter clock RX_CLK Output Receiver clock RXD Output Receiver data RX_DV Output Receiver data valid High RX_ER Output Receiver error High RX_COL Output Collision High RX_CRS Output Carrier sense High TXD Input Transmitter data TX_EN Input Transmitter enable High TX_ER Input Transmitter error High MDC Input Management interface clock Currently not used see the IEEE 802 3 standard for a description of how the signals are used Library dependencies Table 444 shows the libraries used when instantiating the model VHDL libraries Table 444 Library dependencies Library Package Imported unit s Description GAISLER SIM Component Component declaration Instantiation This examples shows how the model can be instantiated library ieee use ieee std_logic_1164 all library gaisler use gaisler sim all entity phy_ex is port rst std_ulogic Clk 2 std logic i end architecture rtl of phy_ex is Signals signal eled_cfg std_logic_vector 2 downto 0 signal signal signal signal signal signal signal signal signal signal signal begin etx_clk erx_clk erxd erx_dv erx_er erx_col erx_crs etxd etx_en etx_er emdc std logic std_logic std_logic_vector 3 downto 0 std_logic std_logic std_logic std_logic std_logic_vector 3 downto 0 std_logic std_logic std_logic Other components are instantia
237. LRU least recently replaced LRR or pseudo random If the LRR algorithm can only be used when the cache is 2 way associative A cache line can be locked in the instruction or data cache preventing it from being replaced by the replacement algorithm NOTE The LRR algorithm uses one extra bit in tag rams to store replacement history The LRU algo rithm needs extra flip flops per cache line to store access history The random replacement algorithm is implemented through modulo N counter that selects which line to evict on cache miss Cachability for both caches is controlled through the AHB plug amp play address information The mem ory mapping for each AHB slave indicates whether the area is cachable and this information is used to statically determine which access will be treated as cacheable This approach means that the cach ability mapping is always coherent with the current AHB configuration The detailed operation of the instruction and data caches is described in the following sections Instruction cache 44 3 1 Operation The instruction cache can be configured as a direct mapped cache or as a multi set cache with asso ciativity of 2 4 implementing either LRU or random replacement policy or as 2 way associative cache implementing LRR algorithm The set size is configurable to 1 64 kbyte and divided into cache lines of 16 32 bytes Each line has a cache tag associated with it consisting of a tag field valid field with one vali
238. M TCAS parameter TCAS Selects 2 or 3 cycle CAS delay 0 1 When changed a LOAD COMMAND REGISTER command must be issued at the same time Also sets RAS CAS delay trep 25 23 SDRAM bank size SDRAM BANKSZ Sets the bank size for SDRAM chip selects 000 4 Mbyte 001 8 Mbyte 010 16 Mbyte 111 512 Mbyte 22 21 SDRAM column size SDRAM COLSZ 00 256 01 512 10 1024 11 4096 when bit 25 23 111 2048 otherwise 20 19 18 17 15 14 13 12 9 415 Table 416 Memory configuration register 2 SDRAM command SDRAM CMD Writing a non zero value will generate a SDRAM command 01 PRECHARGE 10 AUTO REFRESH 11 LOAD COMMAND REGISTER The field is reset after the command has been executed 64 bit SDRAM data bus D64 Reads 1 if the memory controller is configured for 64 bit SDRAM data bus width 0 otherwise Read only RESERVED SDRAM enable SE Enables the SDRAM controller SRAM disable SI Disables accesses RAM if bit 14 SE is set to 1 RAM bank size RAM BANK SIZE Sets the size of each RAM bank 0000 8 kbyte 0001 16 kbyte 1111 256 Mbyte RESERVED RAM bus ready enable RBRDY Enables bus ready signalling for the RAM area Read modify write enable RMW Enables read modify write cycles for sub word writes to 16 bit 32 bit areas with common write strobe no byte write strobe RAM width RAM W
239. M can be connected to the memory controller through the common or separate data bus If the separate bus is used the width is configurable to 32 or 64 bits 64 bit data bus allows the 64 bit SDRAM devices to be connected using the full data capacity of the devices 64 bit SDRAM devices can be connected to 32 bit data bus if 64 bit data bus is not available but in this case only half the full data capacity will be used There is a drive signal vector and separate data vector available for SDRAM The drive vector has one drive signal for each data bit These signals can be used to remove timing problems with the output delay when a separate SDRAM bus is used SDRAM bus signals are described in section 47 13 for configuration options refer to section 47 15 47 9 6 Clocking The SDRAM clock typically requires special synchronisation at layout level For Xilinx and Altera device the GR Clock Generator can be configured to produce a properly synchronised SDRAM clock For other FPGA targets the GR Clock Generator can produce an inverted clock Using bus ready signalling The MEMI BRDYN signal can be used to stretch access cycles to the I O area and the ram area decoded by MEMO RAMSN 4 The accesses will always have at least the pre programmed number of waitstates as defined in memory configuration registers 1 amp 2 but will be further stretched until 412 MEMI BRDYN is asserted MEMI BRDYN should be asserted in the cycle preceding the last one The
240. MA engine The receiver DMA engine handles reception of data from the SpaceWire network to different DMA channels Currently there is only one receive DMA channel available but the GRSPW has been writ ten so that additional channels can be easily added if needed 42 4 1 Basic functionality The receiver DMA engine reads N Chars from the N Char FIFO and stores them to a DMA channel Reception is based on descriptors located in a consecutive area in memory that hold pointers to buff ers where packets should be stored When a packet arrives at the GRSPW it reads a descriptor from memory and stores the packet to the memory area pointed to by the descriptor Then it stores status to the same descriptor and increments the descriptor pointer to the next one 42 4 2 Setting up the GRSPW for reception A few registers need to be initialized before reception can take place First the link interface need to be put in the run state before any data can be sent The DMA channel has a maximum length register which sets the maximum size of packet that can be received to this channel Larger packets are trun cated and the excessive part is spilled If this happens an indication will be given in the status field of the descriptor The minimum value for the receiver maximum length field is 4 and the value can only 323 be incremented in steps of four bytes If the maximum length is set to zero the receiver will not func tion correctly The node address registe
241. MBA Spec Rev 2 0 3 23 ERROR response Only a warning is given if assertions are enabled if it does not cancel the following transfer 15 Master must hold HWDATA stable for the whole data phase when wait AMBA Spec Rev 2 0 3 7 AMBA states are inserted Only the appropriate byte lanes need to be driven Spec Rev 2 0 3 25 for subword transfers 16 Bursts must not cross a 1 kB address boundary This means that htrans AMBA Spec Rev 2 0 3 11 can only be IDLE or NONSEQ when HADDR 9 0 0 17 HMASTLOCK indicates that the current transfer is part of a locked AMBA Spec Rev 2 0 3 28 sequence It must have the same timing as address control 18 HLOCK must be asserted at least one clock cycle before the address AMBA Spec Rev 2 0 3 28 phase to which it refers 19 HLOCK must be asserted for the duration of a burst and can only be http www arm com support faqip deasserted so that HMASTLOCK is deasserted after the final address 597 html phase 20 HLOCK must be deasserted in the last address phase of a burst http www arm com support faqip 588 html 21 HTRANS must be driven to IDLE during reset http www arm com support faqip 495 html 22 HTRANS can only change from IDLE to NONSEQ or stay IDLE http www arm com support faqip when HREADY is deasserted 579 html Table 56 AHB slave rules 65 Rule Number Description References 1 AHB slave must respond with a zero wait state OKAY resp
242. MMU control register 0x100 Context pointer register 0x200 Context register 0x300 Fault status register 0x400 Fault address register The definition of the registers can be found in the SPARC V8 manual 44 6 4 Translation look aside buffer TLB The MMU can be configured to use a shared TLB or separate TLB for instructions and data The number of TLB entries can be set to 2 32 in the configuration record The organisation of the TLB and number of entries is not visible to the software and does thus not require any modification to the operating system Floating point unit and custom co processor interface The SPARC V8 architecture defines two optional co processors one floating point unit FPU and one user defined co processor The LEON3 pipeline provides an interface port for both of these units Two different FPU s can be interfaced Gaisler Research s GRFPU and the Meiko FPU from Sun Selection of which FPU to use is done through the VHDL model s generic map The characteristics of the FPU s are described in the next sections 44 7 1 Gaisler Research s floating point unit GRFPU The high performance GRFPU operates on single and double precision operands and implements all SPARC V8 FPU instructions The FPU is interfaced to the LEON3 pipeline using a LEON3 specific FPU controller GRFPC that allows FPU instructions to be executed simultaneously with integer instructions Only in case of a data or resource depen
243. N E E E E 165 23 5 Signal descriptions 353 napa ia 166 23 6 Libraty dependenciES reinan eii 166 23 7 Component declaro ici at iii 167 23 8 NN 168 DIV32 Signed unsigned 64 32 divider module ooocononccinccnoccnonaninanononcnononano conc cnonacnoncnnnnos 169 24 1 OVA rate ene 169 24 2 NN 169 24 3 Signal descripta pira 169 24 4 Library dependencia ine Be et ee 170 24 5 Component declaration oenen e sale et eta ea ee eee eae 170 24 6 Instantiation soe xi ee ASE ew ee ees oe ee REL RIA 170 DSU3 LEON3 Hardware Debug Support Unit oooooonncccnoncccnoncccnoncnononanononcnononcnnnnccinnnccnnnos 171 25 1 OVEIVIE NW sii 171 25 2 Opera 171 25 3 AHB Trace Bd 172 26 27 28 25 4 Instruction trace Duo msi 173 25 5 DSU Mmemoty MAP ss esses citas da pilar ii titi 174 25 6 DSU registers mms iras r na TE o RE lineas elias 175 25 7 Vendor and device identifiers icp aae eaaa S eE oniAca cinco 177 25 8 Configuration Options sita 178 25 9 Signal descriptions citada its 178 25 107 Elbrary dependencies cm 178 25 11 Component declaration sisii tocino A cess scsck suck ae roetes Se EE veessbecnevcuestsstesgchsedebscschsuscgeutaevsesy 178 A IS A NN 179 FTAHBRAM On chip SRAM with EDAC and AHB interface ossee 181 26 1 IO NO 181 26 2 A sis EEEE ESEE es eee AG sorte ninth tees 181 26 3 RESISTORS O TA 183 26 4 Vendor and device Identidades 183 26 5 Confis ration options si 184 26 6 Signal dESCHPUOS curtir 184 26 7 ibrary dependencies d
244. N3 SPARC V8 processor enhanced with fault tolerance against SEU errors The fault tolerance is focused on the protection of on chip RAM blocks which are used to implement IU FPU register files and the cache memory The LEON3FT processor is functionally identical to the standard LEON3 processor and this chapter only outlines the FT features Register file SEU protection 45 2 1 IU SEU protection The SEU protection for the integer unit register file can be implemented in four different ways depending on target technology and available RAM blocks The SEU protection scheme is selected during synthesis using the uft VHDL generic Table 405 below shows the implementation character istics of the four possible SEU protection schemes Table 405 Integer unit SEU protection schemes ID Implementation Description 0 Hardened flip flops or TMR Register file implemented with SEU hardened flip flops No error checking 1 4 bit parity with restart 4 bit checksum per 32 bit word Detects and corrects 1 bit per byte 4 bits per word Pipeline restart on correction 2 8 bit parity without restart 8 bit checksum per 32 bit word Detects and corrects 1 bit per byte 4 bits per word Correction on the fly without pipeline restart 3 7 bit BCH with restart 7 bit BCH checksum per 32 bit word Detects 2 bits and corrects 1 bit per word Pipeline restart on correction The SEU error detection has no impact on behaviour or timi
245. OAD MODE REG on both banks simulta neously The controller programs the SDRAM to use page burst on read and single location access on write 212 28 2 3 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices and at different frequencies some SDRAM parameters can be programmed through SDRAM configuration register SDCFG The pro grammable SDRAM parameters can be seen in table below Table 209 SDRAM programmable timing parameters Function Parameter range unit CAS latency RAS CAS delay tcas RCD 2 3 clocks Precharge to activate trp 2 3 clocks Auto refresh command period tRFC 3 11 clocks Auto refresh interval 10 32768 clocks Remaining SDRAM timing parameters are according the PC100 PC133 specification 28 2 4 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO REFRESH command to both SDRAM banks The period between the commands in clock periods is pro grammed in the refresh counter reload field in the SDCFG register Depending on SDRAM type the required period is typically 7 8 or 15 6 us corresponding to 780 or 1560 clocks at 100 MHz The generated refresh period is calculated as reload value 1 sysclk The refresh function is enabled by setting bit 31 in SDCFG register 28 2 5 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in SDCFG PRE CHARGE AUTO REFRESH an
246. OxD Instruction cache data ASI OxE Data cache tags ASI OxF Instruction cache data 45 4 1 Data scrubbing There is generally no need to perform data scrubbing on either IU FPU register files or the cache memory During normal operation the active part of the IU FPU register files will be flushed to mem 396 45 5 45 6 45 7 ory on each task switch This will cause all registers to be checked and corrected if necessary Since most real time operating systems performs several task switches per second the data in the register files will be frequently refreshed The similar situation arises for the cache memory In most applications the cache memory is signifi cantly smaller than the full application image and the cache contents is gradually replaced as part of normal operation For very small programs the only risk of error build up is if a part of the applica tion is resident in the cache but not executed for a long period of time In such cases executing a cache flush instruction periodically e g once per minute is sufficient to refresh the cache contents 45 4 2 Initialisation After power on the check bits in the IU and FPU register files are not initialized This means that access to an uninitialized un written register could cause a register access trap tt 0x20 Such behaviour is considered as a software error as the software should not read a register before it has been written It is recommende
247. P receiver processes commands If they are correct and accepted the operation is performed on the AHB bus and a reply is formatted If an acknowledge is requested the RMAP transmitter auto matically send the reply RMAP transmissions have priority over DMA channel transmissions Packets with a mismatching destination logical address are never passed to the RMAP handler There is a user accessible destination key register which is compared to destination key field in incoming packets If there is a mismatch and a reply has been requested the error code in the reply is set to 3 Replies are sent if and only if the ack field is set to 1 329 Detection of all error codes is supported When a failure occurs during a bus access the error code is set to 1 General Error There is predetermined order in which error codes are set in the case of mul tiple errors in the GRSPW It is shown in table 332 Table 332 The order of error detection in case of multiple errors in the GRSPW The error detected first has number 1 Detection Order Error Code Error 1 2 RMAP command not supported by node 2 3 Invalid destination key 3 11 RMW data length error 4 9 Verify buffer overrun 5 10 Authorization failure 6 5 6 Early EOP EEP 7 4 Invalid data CRC 8 7 8 Late EOP EEP Read accesses are performed on the fly that is they are not stored in a temporary buffer before trans mitting This means that the error cod
248. PB slave input signals APBO i Output APB slave output signals DEBUG 10 0 N A Output Debug information see GRLIB IP Library User s Manual Note that the ECC core can also be used without the GRLIB plug amp play information The AMBA APB signals are then provided as IEEE Std_Logic_1164 compatible scalars and vectors Library dependencies Table 296 shows libraries used when instantiating the core VHDL libraries Table 296 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER CRYPTO Component GRECC component declarations Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler crypto all signal debug std_logic_vector 10 downto 0 270 greccO grecc generic map pindex gt paddr gt pmask gt pirg gt port map rstn gt clk gt apbi gt apbo gt debug gt pindex paddr pmask pirq rstn clk apbi apbo pindex debug 34 34 1 34 2 271 GRETH Ethernet Media Access Controller MAC with EDCL support Overview Gaisler Research s Ethernet Media Access Controller GRETH provides an interface between an AMBA AHB bus and an Ethernet network It supports 10 100 Mbit speed in both full and half duplex The AMBA interface consis
249. PED 001010110 DP DP exception is generated if either oper and is a NaN quiet or signaling Negate Absolute value and Move FABSS 000001001 SP SP Absolute value FNEGS 000000101 SP SP Negate FMOVS 000000001 SP SP Move Copies operand to result out put CC condition codes see table 319 UNF NV OF UF NX floating point exceptions see section 37 2 3 SP single precision floating point number DP double precision floating point number INT 32 bit integer Arithmetic operations include addition subtraction multiplication division and square root Each arithmetic operation can be performed in single or double precision formats Arithmetic operations have one clock cycle throughput and latency of three clock cycles except for divide and square root operations which have a throughput of 14 23 clock cycles and latency of 15 25 clock cycles see 303 table 317 Add sub and multiply can be started on every clock cycle providing very high throughput for these common operations Divide and square root operations have lower throughput and higher latency due to complexity of the algorithms but are executed parallelly with all other FP operations in a non blocking iteration unit Out of order execution of operations with different latencies is easily handled through the GRFPU interface by assigning an id to every operation which appears with the result on the output once the operation is completed s
250. RAM PROM Controller Overview The memory controller SSRCTRL is an 32 bit SSRAM PROM IO controller that interfaces external Synchronous pipelined SRAM PROM and I O to the AMBA AHB bus The controller acts as a slave on the AHB bus and has a configuration register accessible through an APB slave interface Figure 227 illustrates the connection between the different devices SRO ROMSN SRO OEN SRO WRITEN MEMORY CONTROLLER SRO RAMSN SRO RWN 3 0 SRI A 27 0 SRLD 31 0 SRO D 31 0 AHB APB Bridge Figure 227 32 bit SSRAM PROM IO controller The controller is configured by VHDL generics to decode three address ranges PROM SSRAM and T O area By default PROM area is mapped into address range 0x0 OXOOFFFFFF the SSRAM area is mapped into address range 0x40000000 Ox4OFFFFFF and the I O area is mapped to 0x20000000 Ox20FFFFFF One chip select is generated for each of the address areas The controller generates both a common write enable signal WRITEN as well as four byte write enable signals WRN The byte write enable signal enables byte and half word write access to the SSRAM A signal BDRIVE is provided for enabling the bidirectional pads to which the data signals are con nected The oepol generic is used to select the polarity of these enable signals If output delay is an issue a vectored output enable signal VBDRIVE can be used instead In this case each pad has its own enable signal driv
251. RITE1 N A Input Port 1 write enable High CLK2 N A Input Port2 clock ADDRESS2 N A Input Port2 address DATAIN2 N A Input Port2 write data DATAOUT2 N A Output Port2 read data ENABLE2 N A Input Port2 chip select High WRITE2 N A Input Port 2 write enable High 61 4 Library dependencies Table 479 shows libraries used when instantiating the core VHDL libraries Table 479 Library dependencies Library Package Imported unit s Description TECHMAP GENCOMP Constants Technology contants 61 5 Component declaration The core has the following component declaration library techmap use techmap gencomp all component syncram_dp generic tech integer 0 abits integer 6 dbits integer 8 port clkl Jn std lt ubogie addressl in std_logic_vector abits 1 downto 0 datainl in std_logic_vector dbits 1 downto 0 dataoutl out std_logic_vector dbits 1 downto 0 enablel in std_ulogic writel x dn stduulogie c1k2 2 in std ulogic address2 in std_logic_vector abits 1 downto 0 datain2 in std_logic_vector dbits 1 downto 0 dataout2 out std_logic_vector dbits 1 downto 0 enable2 in std_ulogic write2 in std_ulogic end component 61 6 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library techmap 488 use techmap gencomp all clkl in std_ulogic addressl in std_l
252. RL ENABLE 0b any ongoing CAN mes sage transfer request will not be aborted until a CAN bus arbitration is lost or the message has been sent successfully If the message is sent successfully the read pointer CanTxRD READ is automati cally incremented Any associated interrupts will be generated The progress of the any ongoing access can be observed via the CanTxCTRL ONGOING bit The CanTxCTRL ONGOING must be Ob before the channel can be re configured safely i e changing 144 22 6 address size or read write pointers It is also possible to wait for the Tx and TxLoss interrupts described hereafter The channel can be re enabled again without the need to re configure the address size and pointers Priority inversion is handled by disabling the transmitting channel i e setting CanTxC TRL ENABLE 0b as described above and observing the progress i e reading via the CanTxC TRL ONGOING bit as described above When the transmit channel is disabled it can be re configured and a higher priority message can be transmitted Note that the single shot mode does not require the channel to be disabled but the progress should still be observed as above No message transmission is started while the channel is not enabled 22 5 8 Interrupts During transmission several interrupts can be generated e TxLoss Message arbitration lost for transmit could be caused by communcations error as indicated by other interrupts as well e TxEr
253. RS ti ana si italia 467 57 4 Vendor and device identiliE tinta 468 57 5 Confieuration Options its date E EE eee ake 468 57 6 Sipmalsdescriptrons dd Sa 469 57 7 Library dependencies siii iseitis seiri cvecs sus suede snuck costh chen ocio oa Eeo en VEKU ra KOKE e ike ro Irk seas i 471 57 8 Component declara mica Seca EAA EEA ATS aii 471 14 58 59 60 61 62 63 57 9 Insta OM baaa iii 471 gt Y GACTRL Yea Controller Lor ii 475 58 1 Introductions ESE EA E A E NN 475 58 2 Operation ia 475 58 3 Ea EEE ON 476 58 4 Vendor and device identifiers oooooocononnoonconcoononnnnnnnononnnonnnonnonnn on non no cono nn conc nn nan nnnn ran conc ran cnn nora con ncnnecnnns 477 58 5 Configuration Opinion isis rat 478 58 6 Signal descriptions a 478 58 7 Library dependencies srs iri Sar ern aie ee eE EE EE EEEE E E E O a aee 479 58 8 Component instantiation eee ee ceeceeeeeeceseeeeeeseeceecseesaecsaesaecseceseseresseseeseseseaecaessaecsaesaecsesaeeaseegeees 479 58 9 Linux 2 6 command line Options cece eeceeceeeeseeseecseescecsecaeseceaeesecesceeeeeeeeeseaeeseecaecaaecaesaeeaseneees 479 SYNCRAM Single port RAM generator ccooocccconcccnoncnononcncnnnnnonnnncnnnnnnnnnnnnnn nc cono nccnnn caninos 481 59 1 OVA 481 59 2 Configuration Options vc lic eeter heee teste svccesneca sence tones cidade dad inten jasa bancas 481 59 3 Signal ASscriptlons iii 482 59 4 Library dependencies csc sisccesccsetenscaccsstseecescscscuscbensspeescd e
254. Reset Low CLK N A Input System clock TCLK N A Input Sample clock APBI Input APB slave input signals APBO Output APB slave output signals SIGNALS N A Input Vector of traced signals See GRLIB IP Library users manual Library dependencies Table 412 shows libraries used when instantiating the core VHDL libraries Table 412 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Component Component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grliby use grlib amba all library gaisler use gaisler misc all entity logan_ex is port erk s lt in std ulogic rstn in std_ulogic other signals i end architecture rtl of logan_ex is AMBA signals signal apbi apb_slv_in_type signal apbo signal signals std_logic_vector 63 downto 0 begin Logic analyzer core apb_slv_out_vector others gt apb_none 403 logan0 logan generic map dbits gt 64 depth gt 4096 trigl gt 2 usereg gt 1 usequal gt 0 pindex gt 3 paddr gt 3 pmask gt 16 F00 memtech gt memtech port map rstn clk clk apbi apbo 3 signals end 404 47 MCTRL Combined PROM IO SRAM SDRAM Memory Controller 47 1 Overview The memory controller handles a memory bus hosting PROM memory mapped I O
255. SH and LOAD MODE REG LMR If the LMR command is issued the CAS delay as programmed in MCFG2 will be used remaining fields are fixed page read burst single location write sequential burst The command field will be cleared after a command has been executed Note that when changing the value of the CAS delay a LOAD MODE REGIS TER command should be generated at the same time 47 9 2 Read cycles A read cycle is started by performing an ACTIVATE command to the desired bank and row followed by a READ command after the programmed CAS delay A read burst is performed if a burst access has been requested on the AHB bus The read cycle is terminated with a PRE CHARGE command no banks are left open between two accesses 47 9 3 Write cycles Write cycles are performed similarly to read cycles with the difference that WRITE commands are issued after activation A write burst on the AHB bus will generate a burst of write commands without idle cycles in between 47 9 4 Address bus connection The memory controller can be configured to either share the address and data buses with the SRAM or to use separate address and data buses When the buses are shared the address bus of the SDRAMs should be connected to A 14 2 the bank address to A 16 15 The MSB part of A 14 2 can be left unconnected if not used When separate buses are used the SDRAM address bus should be connected to SA 12 0 and the bank address to SA 14 13 47 9 5 Data bus SDRA
256. SH and LOAD MODE REG on both banks simulta neously The controller programs the SDRAM to use page burst on read and single location access on write 47 8 4 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices and at different frequencies some SDRAM parameters can be programmed through memory configuration register 2 MCFG2 The pro grammable SDRAM parameters can be seen in tabel 413 Table 413 SDRAM programmable timing parameters Function Parameter Range Unit CAS latency RAS CAS delay tcas RCD 2 3 clocks Precharge to activate trp 2 3 clocks Auto refresh command period tRFC 3 11 clocks Auto refresh interval 10 32768 clocks Remaining SDRAM timing parameters are according the PC100 PC133 specification Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO REFRESH command to both SDRAM banks The period between the commands in clock periods is pro 47 10 411 grammed in the refresh counter reload field in the MCFG3 register Depending on SDRAM type the required period is typically 7 8 or 15 6 us corresponding to 780 or 1560 clocks at 100 MHz The generated refresh period is calculated as reload value 1 sysclk The refresh function is enabled by setting bit 31 in MCFG2 47 9 1 SDRAM commands The controller can issue three SDRAM commands by writing to the SDRAM command field in MCFG2 PRE CHARGE AUTO REFRE
257. TS 341 42 13 Library dependencias isi ciccs esse sectest ie scgsc sb EEEE EAP EATE EEE ET 341 42 14 A covcesckeeieeecsetecs hohe caseschenecscouabenscsinued cvbspechebevsen scte scubvasvaedvneyscuacesbebectacuepeusepdne Seest 341 42157 REEMS Driver td ee as ees tae A eee neds 342 42 16 APLI en eee ee ee eee 350 IRQMP Multiprocessor Interrupt Controller cece eesecesneeeeeececeeeeeceeececseeeeeseeeeneeeenas 362 43 1 OVA We eo i tases eee et Rabi 362 43 2 Oporto 362 43 3 Rescata atte 364 44 45 46 47 43 4 Vendor and device Ident Hers Sucina ita aid 366 43 5 Conti stration Options etica pilar ice iii ari cdi 366 43 6 Signal Aescriptrons sssi erreen ene seth as Eeer reke rse ooetsesesebuntceccuseesbobestacsuteascuscesbsu sobs dele esca 367 43 7 Tabrarysdependencies ais 367 43 8 Instantiation 5 0023 A A A A A E 367 LEON3 High performance SPARC V8 32 bit ProcesSOT ooonoconocccocccononcnoncconcnnnnconn cono ncnnos 369 44 1 Olivares 369 44 2 LEONS ante Ser Ut ei 371 44 3 Instruction CACHE ita daa it 377 44 4 Data ca da A 378 44 5 Additional cache functionality ooonononnoccnocnnonccnnnoncononnnonnnonncnnconncn nono nono cocoa nnnn nana rnn conc r ano rn conan on non necnnns 379 44 6 Memory management nit 23 lacoste tr once dali tri cds 382 44 7 Floating point unit and custom CO processor interface oooocccccnonnnoccnonnonnnnnnoncnnncnnonononnconn cono cnn co nonnncnnono 383 44 8 Vendor and idevice 1AeOnt Hers cucuta ciao
258. Table 272 Point Y Input 3 Register 31 Y 127 downto 96 Table 273 Point Y Input 4 Register 31 Y 159 downto 128 Table 274 Point Y Input 5 Register 31 Y 191 downto 160 Table 275 Point Y Input 6 Register 31 Y 223 downto 192 Table 276 Point Y Input 7 Register most significant 31 8 0 Y 232 downto 224 The encryption or decryption operation is started when the Point Y Input 7 Register is written 33 8 4 Point X Output 0 to 7 Registers R Table 277 Point X Output 0 Register least significant 31 X 31 downto 0 Table 278 Point X Output 1 Register 31 X 63 downto32 Table 279 Point X Output 2 Register 31 X 95 downto 64 Table 280 Point X Output 3 Register 31 X 127 downto 96 Table 281 Point X Output 4 Register 31 X 159 downto 128 Table 282 Point X Output 5 Register 31 X 191 downto 160 Table 283 Point X Output 6 Register 31 X 223 downto 192 Table 284 Point X Output 7 Register most significant 31 8 X 232 downto 224 267 268 33 8 5 Point Y Output 0 to 7 Registers R Table 285 Point Y Output O Register least significant 31 0 Y 31 downto 0 Table 286 Point Y Output 1 Register 31 0 Y 63 downto32 Table 287 Point Y Output 2 Register
259. The TxSync interrupt is issued when a message matching the SYNC Code Filter Register S YNC and SYNC Mask Filter Reg 143 ister MASK registers is successfully transmitted Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus 22 5 5 Straight buffer It is possible to use the circular buffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address Can TxADDR ADDR field While the channel is disabled the read pointer CanTxRD READ can be changed to an arbitrary value pointing to the first message to be transmitted and the write pointer Can TxWR WRITE can be changed to an arbitrary value When the channel is enabled the transmission will start from the read pointer and continue to the write pointer 22 5 6 AMBA AHB error Definition e a message fetch occurs when no other messages is being transmitted e a message prefetch occurs when a previously fetched message is being transmitted e the local fetch buffer holds the message being fetched e the local prefetch buffer holds the message being prefetched e the local fetch buffer holds the message being transmitted by the CAN core e a successfully prefetched message is copied from the local prefetch buffer to the local fetch buffer when that buffer is freed after a successful transmission An AHB error response occurring on the AMBA AHB bus while a CAN message is being fetched will result in a T
260. The value of these field affects the SDRAM timing as described in table 449 451 Table 449 SDRAM programmable minimum timing parameters SDRAM timing paramteter Minumum timing clocks CAS latency RAS CAS delay tcas gt trop TCAS 2 Precharge to activate trp TRP 2 Auto refresh command period trc TRFC 3 Activate to precharge tr As TREC 1 Activate to Activate tac TRP TRFC 4 If the TCAS TRP and TRFC are programmed such that the PC100 133 specifications are fullfilled the remaining SDRAM timing parameters will also be met The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing in ns Table 450 SDRAM example programming SDRAM settings tcas trc trp trrc tras 100 MHz CL 2 TRP 0 TCAS 0 TRFC 4 20 80 20 70 50 100 MHz CL 3 TRP 0 TCAS 1 TRFC 4 30 80 20 70 50 133 MHz CL 2 TRP 1 TCAS 0 TRFC 6 15 82 22 67 52 133 MHz CL 3 TRP 1 TCAS 1 TRFC 6 22 82 22 67 52 55 2 4 Refresh The SDRAM controller contains a refresh function that periodically issues an AUTO REFRESH command to both SDRAM banks The period between the commands in clock periods is pro grammed in the refresh counter reload field in the SDCFG register Depending on SDRAM type the required period is typically 7 8 or 15 6 us corresponding to 780 or 1560 clocks at 100 MHz The generated refresh period is calculated as reload value 1 sysclk The
261. Tick in can be generated either by writing a one to the register field or by asserting the tick in signal A Tick in should not be generated too often since if the time code after the previous Tick in has not been sent the register will not be incremented and no new value will be sent The tick in field is automatically cleared when the value has been sent and thus no new ticks should be generated until this field is zero If the tick in signal is used there should be at least 4 system clock and 25 transmit clock cycles between each assertion A tick out is generated each time a valid time code is received and the timerxen bit is set When the tick out is generated the tick out signal will be asserted one clock cycle and the tick out register field is asserted until it is cleared by writing a one to it The current time counter value can be read from the time register It is updated each time a Time code is received and the timerxen bit is set The same register is used for transmissions and can also be written directly from the APB interface The control bits of the Time code are always stored to the time ctrl register when a Time code is received whose time count is one more than the nodes current time counter register The time ctrl reg ister can be read through the APB interface The same register is used during time code transmissions It is possible to have both the time transmission and reception functions enabled at the same time Receiver D
262. Timing The timing waveforms and timing parameters are shown in figure 82 and are defined in table 206 clk address ramsn romsn rwen writen data cb output clk address ramoen ramben oen read E e gt ane data cb input REDERTAS ACA he IGE NZ teTMCTRLO le ME gt gt teTMCTRLI teTMCTR teTMCTRL3 gt lETMCTRLS gt teTMCTRL1 teTMCTRL2 ramsn romsn ee A O teTMCTRL6 gt tETMCTRL6 teTMCTRL9 gt gt FTMCTRL10 brdyn bexcn Figure 82 Timing waveforms SRAM PROM accesses clk address iosn rwen writen Neal ENING NANA NI NNT Ne ST teTMCTRLO gt teTMCTRLI teTMCTRL2 teETMCTRL3 gt teTMCTRL1 tETMCTRL2 207 data output cs YX O iosn TN poo OO teTMCTRL6 _ teTMCTRL6 oen read tETMCTRL7 gt gt FTMCTRL8 data input tETMCTRL9 y e FTMCTRL10 brdyn bexcn Figure 83 Timing waveforms I O accesses Table 206 Timing parameters SRAM PROM and I O accesses Name Parameter Reference edge Min Max Unit tETMCTRLO address clock to output delay rising clk edge 0 10 ns teTMCTRL1 clock to output delay rising clk edge 0 10 ns tETMCTRL2 clock to data output delay rising clk edge 0 10 ns tETMCTRL3 clock to output delay falling clk edge 0 10 ns tFTMCTRLA clo
263. VHDL generics Access to unused addresses will cause an AHB error response 4 2 3 Plug amp play information GRLIB devices contain a number of plug amp play information words which are included in the AHB records they drive on the bus see the GRLIB user s manual for more information These records are combined into an array which is connected to the AHB controller unit 30 The plug amp play information is mapped on a read only address area defined by the cfgaddr and cfg mask VHDL generics By default the area is mapped on address OXFFFFFOOO OXFFFFFFFF The master information is placed on the first 2 kbyte of the block OxFFFFF000 OxFFFFF800 while the slave information id placed on the second 2 kbyte block Each unit occupies 32 bytes which means that the area has place for 64 masters and 64 slaves The address of the plug amp play information for a certain unit is defined by its bus index The address for masters is thus OxFFFFFOOO n 32 and OxFFFFF800 n 32 for slaves 31 24 23 1211109 5 4 0 Identification Register 00 VENDOR ID DEVICE ID 00 VERSION IRQ 04 USER DEFINED 08 USER DEFINED 0c USER DEFINED BARO 10 ADDR 00 P C MASK TYPE BAR1 14 ADDR 00 P C MASK TYPE Bank Address Registers BAR2 18 ADDR 00 P C MASK TYPE BAR3 1C ADDR 00 P C MASK TYPE 31 20 19 18 17 16 15 4 3 0 4 3 4 4 4 5 P Prefetchable TYPE C Cacheable 0001 APB I O space 0010 AHB Me
264. Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x070 For a description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 101 shows the configuration options of the core VHDL generics Table 101 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr ADDR field of the APB BAR 0 16 FFFH 0 pmask MASK field of the APB BAR 0 16 FFFH 16 FFFH pirq Interrupt number 0 NAHBIRQ 1 0 104 18 7 18 8 18 9 Signal descriptions Table 102 shows the interface signals of the core VHDL ports Table 102 Signal descriptions Signal name Field Type Function Active RSTN N A Input Reset Low CLK N A Input Clock B15531 Input 1553 bus input signals busainp Positive data input from the A receiver High busainn Negative data input from the A receiver Low busbinp Positive data to the B receiver High busbinn Negative data to the B receiver Low B15530 Output 1553 bus output signals busainen Enable for the A receiver High busaoutin Inhibit for the A transmitter High busaoutp Positive data to the A transmitter High busaoutn Negative data to the A transmitter Low busbinen Enable for the
265. XAHBErr interrupt If the CanCONF ABORT bit is set to Ob the channel causing the AHB error will skip the message being fetched from memory and will increment the read pointer No message will be transmitted If the CanCONF ABORT bit is set to 1b the channel causing the AHB error will be disabled CanTx CTRL ENABLE is cleared automatically to 0 b The read pointer can be used to determine which message caused the AHB error Note that it could be any of the four word accesses required to read a message that caused the AHB error If the CanCONF ABORT bit is set to 1b all accesses to the AMBA AHB bus will be disabled after an AMBA AHB error occurs as indicated by the CanSTAT AHBErr bit being 1b The accesses will be disabled until the CanSTAT register is read and automatically clearing bit CanSTAT AHBErr An AHB error response occurring on the AMBA AHB bus while a CAN message is being prefetched will not cause an interrupt but will stop the ongoing prefetch and further prefetch will be prevented temporarily The ongoing transmission of a CAN message from the fetch buffer will not be affected When the fetch buffer is freed after a successful transmission a new fetch will be initiated and if this fetch results in an AHB error response occurring on the AMBA AHB bus this will be handled as for the case above If no AHB error occurs prefetch will be allowed again 22 5 7 Enable and disable When an enabled transmit channel is disabled CanTxCT
266. a all use grlib tech all library gaisler use gaisler spacewire all entity spacewire_ex is port clk in std_ulogic rstn in std_ulogic spacewire signals di in std_ulogic si in std_ulogic do out std_ulogic so out std_ulogic i end architecture rtl of spacewire_ex is AMBA signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none Spacewire signals signal swni grspw_in_type signal swno grspw_out_type begin AMBA Components are instantiated here GRSPW swO grspw generic map tech gt inferred hindex gt 5 pindex gt 7 paddr gt 7 nsync gt 1 rmap gt 1 rxunaligned gt 0 rmapcrc gt 0 rxclkbuftype gt 0 sysfreq gt 40000 pirgq gt 2 fifosizel gt 4 fifosize2 gt 64 rmapbufs gt 8 ft gt 0 port map rstn clk apbi apbo 7 ahbmi ahbmo 5 swni swno swni rmapen lt l swni clkdiv10 lt 00000001 swni tickin lt 0 swni d lt di swni s lt si do lt swno d so lt swno s end RTEMS Driver The RTEMS GRSPW driver supports the standard accesses to file descriptors such as read write and ioctl User applications should include the file spacewire h which contains definitions of all necessary data structures used when accessing the driver and a function
267. a cycle will be inserted for each waitstate in both read and write cycles Burst cycles To improve the bandwidth of the memory bus accesses to consecutive addresses can be performed in burst mode Burst transfers will be generated when the memory controller is accessed using an AHB burst request These includes instruction cache line fills and burst from DMA masters The timing of a burst cycle is identical to the programmed basic cycle with the exception that during read cycles the lead out cycle will only occurs after the last transfer Registers The core does not implement any use programmable registers All configuration is done through the VHDL generics Vendor and device identifier The core has vendor identifier 0x01 Gaisler Research and device identifier 0x008 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 456 shows the configuration options of the core VHDL generics Table 455 Configuration options Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 romaddr ADDR filed of the AHB BARO defining PROM address space 0 16 FFF 16 000 Default PROM area is 0x0 OXFFFFFF rommask MASK filed of the AHB BARO defining PROM address space 0 16 FFF 16 FFO ramaddr ADDR filed of the AHB BARI defining SRAM address space 0 16 FFF 16 400 Default SRAM area is 0x
268. a from the AHB bus is stored in the buffer of IN endpoint 1 and transmitted in the same manner as for endpoint 0 Write commands also arrive to OUT endpoint 1 and are executed on the bus immediately No reply is sent for writes Each endpoint has two buffers that can hold one max payload packet each The USBDCL automati cally alternates between them when a packet has been received transmitted When it operates in high speed mode OUT transactions are replied with a ACK handshake if the other buffer the one to which the packet is not stored is empty and with a NYET if is full A NAK is sent if both are full since the packet cannot be received 63 2 2 Protocol The protocol used for the AHB commands is very simple and consists of two 32 bit control words The first word consists of the 32 bit AHB address and the second consists of a read write bit at bit 31 and the number of words to be written at bits 16 downto 2 All other bits in the second word are reserved for future use and must be set to 0 The read write bit must be set to 1 for writes Figure 236 shows the layout of a write command The command should be sent as the data cargo of an OUT transaction to endpoint 1 The data for a command must be included in the same packet The maximum payload is 512 B when running in high speed mode and 64 B in full speed mode Since the control information takes 8 B the maximum number of bytes per command is 504 B and 56 B respec tively Subword writes
269. a packet is received with an address not accepted by the MAC the IA status register bit will be set Packets larger than maximum size cause the FT bit in the receive descriptor to be set The length field is not guaranteed to hold the correct value of received bytes The counting stops after the word con taining the last byte up to the maximum size limit has been written to memory The address word of the descriptor is never touched by the GRETH 35 4 4 Reception with AHB errors If an AHB error occurs during a descriptor read or data store the Receiver AHB Error RA bit in the status register will be set and the receiver is disabled The current reception is aborted The receiver can be enabled again by setting the Receive Enable bit in the control register 35 4 5 Checksum offload Support is provided for checksum calculations in hardware for TCP UDP over IPv4 The checksum logic is always active and detects IPv4 packets with TCP or UDP payloads If IPv4 is detected the ID bit is set UD is set if an UDP payload is detected in the IP packet and TD is set if a TCP payload is detected in the IP packet TD and UD are never set if an IPv4 packet is not detected When one or more of these packet types is detected its corresponding checksum is calculated and if an error is detected the checksum error bit for that packet type is set The error bits are never set if the corre sponding packet type is not detected MDIO Interface The MDIO interfa
270. a pipeline stage This option improves timing but increases latency with one clock cycle Configuration options Table 424 shows the configuration options of the core VHDL generics Table 424 Configuration options Generic Function Allowed range Default mulpipe Include a pipeline stage 0 1 0 0 pipelining disabled 1 pipelining enabled Signal descriptions Table 425 shows the interface signals of the core VHDL ports Table 425 Signal descriptions Signal name Type Function Active CLK Input Clock 16x16 multiplier only HOLDN Input Hold When active the pipeline register is not Low updates 16x16 multiplier only 16 0 16x16 mult Input Operand 1 MBS bit is sign bit High 32 0 32x8 mult 32 0 32x16 mult 32 0 32x32 mult 16 0 16x16 mult Input Operand 2 MSB bit is sign bit High 8 0 32x8 mult 16 0 32x16 mult 32 0 32x32 mult P 33 0 16x16 mult Result Two MSB bits are sign bits High P 41 0 32x8 mult KKK KIX x K x P 49 0 32x16 mult P 65 0 32x32 mult Library dependencies Table 426 shows libraries used when instantiating the core VHDL libraries Table 426 Library dependencies Library Package Imported unit Description GRLIB MULTLIB Component Multiplier component declarations 426 49 5 Component declaration The core has the following component declaration compon
271. a ready DR indicates that new data has been received by the AMBA AHB master interface 1 Transmitter shift register empty TS indicates that the transmitter shift register is empty 31 14 13 0 RESERVED SCALER RELOAD VALUE Figure 19 AHB UART scaler reload register 11 4 11 5 11 6 11 7 11 8 61 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x007 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 51 shows the configuration options of the core VHDL generics Table 51 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr ADDR filed of the APB BAR 0 16 FFFH 0 pmask MASK filed of the APB BAR 0 16 FFFH 16 FFFH Signal descriptions Table 52 shows the interface signals of the core VHDL ports Table 52 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock UARTI RXD Input UART receiver data High CTSN Input UART clear to send High EXTCLK Input Use as alternative UART clock UARTO RTSN Output UART request to send High TXD Output UART transmit data High APBI Input APB slave input signals APBO t Output APB slave output signals AHBI 7 Input AMB master input signals
272. a vector available for SDRAM The drive vector has one drive signal for each data bit These signals can be used to remove timing problems with the output delay when a separate SDRAM bus is used 27 9 6 Clocking The SDRAM controller is designed for an external SDRAM clock that is in phase or slightly earlier than the internal AHB clock This provides the maximum margin for setup and hold on the external signals and allows highest possible frequency For Xilinx and Altera device the GRLIB Clock Gen erator CLKGEN can be configured to produce a properly synchronized SDRAM clock For other FPGA targets the custom clock synchronization must be designed For ASIC targets the SDRAM clock can be derived from the AHB clock with proper delay adjustments during place amp route 27 9 7 Initialisation Each time the SDRAM is enabled bit 14 in MCFG2 an SDRAM initialisation sequence will be sent to both SDRAM banks The sequence consists of one PRECHARGE eight AUTO REFRESH and one LOAD COMMAND REGISTER command Memory EDAC The FTMCTRL is provided with an EDAC that can correct one error and detect two errors in a 32 bit word For each word a 7 bit checksum is generated according to the equations below A correctable error will be handled transparently by the memory controller but adding one waitstate to the access If an un correctable error double error is detected the current AHB cycle will end with an error response The EDAC can be used durin
273. able 316 GRFPU operations Operation OpCode 8 0 Op1 Op2 Result Exceptions Description Arithmetic operations FADDS 001000001 SP SP SP UNE NV Addition FADDD 001000010 DP DP DP OF UF NX FSUBS 001000101 SP SP SP UNE NV Subtraction FSUBD 001000110 DP DP DP OF UF NX FMULS 001001001 SP SP SP UNF NV Multiplication FSMULD gives FMULD 001001010 DP DP DP OF UF NX exact double precision product of FSMULD ici SP SP DP UNF NY two single precision operands OF UF NX UNE NV OF UF FDIVS 001001101 SP SP SP UNE NV Division FDIVD 001001110 DP DP DP OF UF NX FSQRTS 000101001 SP SP UNE NV Square root FSQRTD 000101010 DP DP NX Conversion operations FITOS 011000100 INT SP NX Integer to floating point conversion FLOD 011001000 DE E FSTOI 011010001 SP INT UNE NV Floating point to integer conversion FDTOI 011010010 DP NX The result is rounded in round to zero mode FSTOIRND 111010001 SP INT UNE NV Floating point to integer conversion FDTOI_RND 111010010 DP NX Rounding according to RND input FSTOD 011001001 SP DP UNF NV Conversion between floating point FDTOS 011000110 DP SP UNF NV formats OF UF NX Comparison operations FCMPS 001010001 SP SP CC NV Floating point compare Invalid FCMPD 001010010 DP DP exception is generated if either oper and is a signaling NaN FCMPES 001010101 SP SP CC NV Floating point compare Invalid FCM
274. able in the non blocking mode the call will return with an error There is also a feature called Tx_block_on_ full which means that the write call blocks when all descriptors are in use The ioctl call used for transmissions is SPACEWIRE_IOCTRL_SEND A spw_ioctl_send struct is used as argument and contains length and pointer fields The structure is shown in the data structures section This ioctl call should be used when a header is taken from one buffer and data from another The header part is always transmitted first The hlen field sets the number of header bytes to be trans mitted from the hdr pointer The dlen field sets the number of data bytes to be transmitted from the data pointer Afterwards the sent field contains the total number header data of bytes transmitted The blocking behavior is the same as for write calls The call fails if hlen dlen is 0 one of the buffer pointer is zero and its corresponding length variable is nonzero Table 345 ERRNO values for write and ioctl send ERRNO Description EINVAL An invalid argument was passed The buffers could be null pointers or the length parameters could be 0 or larger than the maximum allowed size EBUSY The packet could not be transmitted because all descriptors are in use only in non blocking mode 42 15 7 Reception Reception is done using the read call An example is shown below len read fd rx_pkt tmp The requested number of bytes to b
275. able signals to select which buses the interface should be transmitting on Two decoders take the serial Manchester received data from each bus and extract the received data words The decoder contains a digital phased lock loop PLL that generates a recovery clock used to sample the incoming serial data The data is then de serialized and the 16 bit word decoded The decoder detects whether a command status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word The protocol controller block handles all the message sequencing and error recovery for all three operating modes Bus Controller Remote Terminal and Bus Monitor This is complex state machine that processes messages based on the message tables setup in memory or reacts to incoming com mand words The protocol controller implementation varies depending on which functions are imple mented The AMBA interface allows a system processor to access the control registers It also allows the processor to directly access the memory connected to the backend interface this simplifies the system design The interface comprises 33 16 bit registers Of the 33 registers 17 are used for control function and 16 for RT command legalization The B1553BRM core provides an AMBA interface for the Actel Corel553BRM core MIL STD 1553B Bus Controller Remote Terminal Bus Monitor The B1553BRM core implements two AMBA interfaces one AHB master interfa
276. ache line size in number of words 4 8 4 isetsize Size of each instruction cache set in kByte 1 256 1 isetlock Enable instruction cache line locking 0 1 0 dcen Data cache enable 0 1 1 drepl Data cache replacement policy 0 1 0 0 least recently used LRU 1 least recently replaced LRR 2 random dsets Number of data cache sets 1 4 1 dlinesize Data cache line size in number of words 4 8 4 dsetsize Size of each data cache set in kByte 1 256 1 Table 402 Configuration options 389 Generic Function Allowed range Default dsetlock Enable instruction cache line locking 0 1 0 dsnoop Enable data cache snooping 0 6 0 Bit 0 1 0 disable 1 slow 2 fast see text Bit 2 0 simple snooping 1 save extra physical tags MMU snooping ilram Enable local instruction RAM 0 1 0 ilramsize Local instruction RAM size in kB 1 512 1 ilramstart 8 MSB bits used to decode local instruction RAM area 0 255 16 8E dlram Enable local data RAM scratch pad RAM 0 1 0 dlramsize Local data RAM size in kB 1 512 1 dlramstart 8 MSB bits used to decode local data RAM area 0 255 16 8F mmuen Enable memory management unit MMU 0 1 0 itlbnum Number of instruction TLB entries 2 64 8 dtlbnum Number of data TLB entries 2 64 8 tlb_type Separate 0 or shared TLB 1 0 1 1 tlb_rep Random 0 or LRU 1 TLB replacement 0 1 0 lddel Load delay One cycle gives best performance but m
277. acknowledge MP IRQ Processor 0 Processor 1 Processor n CTRL BUS AHB BUS CONTROL l SLAVE 1 SLAVE 2 Figure 155 LEON3 multiprocessor system with Multiprocessor Interrupt controller Operation 43 2 1 Interrupt prioritization The interrupt controller monitors interrupt 1 15 of the interrupt bus APBI PIRQ 15 1 When any of these lines are asserted high the corresponding bit in the interrupt pending register is set The pend ing bits will stay set even if the PIRQ line is de asserted until cleared by software or by an interrupt acknowledge from the processor Each interrupt can be assigned to one of two levels 0 or 1 as programmed in the interrupt level regis ter Level 1 has higher priority than level 0 The interrupts are prioritised within each level with inter rupt 15 having the highest priority and interrupt 1 the lowest The highest interrupt from level 1 will be forwarded to the processor If no unmasked pending interrupt exists on level 1 then the highest unmasked interrupt from level 0 will be forwarded PIRQ 31 16 are not used by the IRQMP core Interrupts are prioritised at system level while masking and forwarding of interrupts in done for each processor separately Each processor in an multiprocessor system has separate interrupt mask and force registers When an interrupt is signalled on the interrupt bus the interrupt controller will
278. address for both transmit and receive operations The command legalization can be done internally or via a command legalization interface The interface consists of six main blocks 1553B encoders 1553B decoders backend interface com mand decoder RT controller blocks and a command legalization block A single 1553B encoder is used for the interface This takes each word to be transmitted and serializes it after which the signal is Manchester encoded The encoder also includes both logic to prevent the RT from transmitting for greater than the allowed period and loopback fail logic The loopback logic monitors the received data and verifies that the interface has correctly received every word that it transmits The output of the encoder is gated with the bus enable signals to select which buses the RT should use to transmit The interface includes two 1553B decoders The decoder takes the serial Manchester data received from the bus and extracts the received data words The decoder contains a digital phased lock loop PLL that generates a recovery clock used to sample the incoming serial data The data is then deseri alized and the 16 bit word decoded The decoder detects whether a command or data word is received and also performs Manchester encoding and parity error checking The command decoder and RT controller blocks decode the incoming command words verifying the legality Then the protocol state machine responds to the command transmit
279. ae 494 63 4 Vendor and device identifleT oooonicnnncnccnncononnonnnonnnononnconnonnccnnonnocnncnnnnn S E n rn cnn nena E A E nens 494 63 5 Configtitation Options mart tdt 495 63 6 63 7 63 8 Sigial descriptions isa eae ten tendo taah E tence ease been a ont eee Library dependencies sass isis cscs sista ce ves conde a Ann a EE aaa EEA Eea ET E an RATAR ea Instantiation 16 1 1 1 2 Introduction Scope This document describes specific IP cores provided with the GRLIB IP library When applicable the cores use the GRLIP plug amp play configuration method as described in the GRLIB User s Manual IP core overview The tables below lists the provided IP cores and their AMBA plug amp play device ID The license col umn indicates if a core is available under GNU GPL and or under a commercial license Cores marked with FT are only available in the FT version of GRLIB Note the open source version of GRLIB includes only cores marked with GPL or LGPL Table 1 Processors and support functions Name Function Vendor Device License LEON3 SPARC V8 32 bit processor 0x01 0x003 COM GPL DSU3 Multi processor Debug support unit 0x01 0x004 COM GPL IRQMP Multi processor Interrupt controller 0x01 0x00D COM GPL GRFPU High performance IEEE 754 Floating point unit COM GRFPU Lite Low area IEEE 754 Floating point unit COM LEON3FT Fault tolerant SPARC V8 32 bit Processor 0x01 0x053 FT Ta
280. age received Note that the WRITE field can be use to read out the progress of a transfer Note that the WRITE field can be written to in order to set up the starting point of a transfer This should only be done while the receive channel is not enabled 22 9 16 Receive Channel Read Register CanRxRD R W Table 166 Receive Channel Read Register 31 20 19 4 3 0 READ 19 4 READ Pointer to last read message 1 All bits are cleared to 0 at reset The field is implemented as relative to the buffer base address scaled with the SIZE field The READ field is written to in order to release the receive buffer indicating the position 1 of the last message that has been read out Note that it is not possible to fill the buffer There is always one message position in buffer unused Software is responsible for not over reading the buffer on wrap around i e setting WRITE READ 22 9 17 Receive Channel Interrupt Register CanRxIRQ R W Table 167 Receive Channel Interrupt Register 31 20 19 4 3 0 IRQ 19 4 IRQ Interrupt is generated when CanRxWR WRITE IRQ as a consequence of a message reception All bits are cleared to 0 at reset Note that this indicates that a programmed number of messages have been received The field is implemented as relative to the buffer base address scaled with the SIZE field 155 22 9 18 Receive Channel Mask Register CanRxMASK R W Table 168 Receive Channel Mask Regis
281. al read only 8 EB value of the external DSUBRE signal read only 9 Processor error mode PE returns 1 on read when processor is in error mode else 0 If written with 1 it will clear the error and halt mode 10 Processor halt HL Returns 1 on read when processor is halted If the processor is in debug mode setting this bit will put the processor in halt mode 11 Power down PW Returns 1 when processor in in power down mode 25 6 2 DSU Break and Single Step register This register is used to break or single step the processor s This register controls all processors in a multi processor system and is only accessible in the DSU memory map of processor 0 31 18 17 16 15 2 1 0 SS15 ne SS2 SS1 SSO BN15 aed BN2 BN1 BNO Figure 55 DSU Break and Single Step register 15 0 Break now BNx Force processor x into debug mode if the Break on watchpoint BW bit in the processors DSU control register is set If cleared the processor x will resume execution 31 16 Single step SSx if set the processor x will execute one instruction and return to debug mode The bit remains set after the processor goes into the debug mode 25 6 3 DSU Debug Mode Mask Register When one of the processors in a multiprocessor LEON3 system enters the debug mode the value of the DSU Debug Mode Mask register determines if the other processors are forced in the debu
282. al apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signal pcii pci_in_type signal pcio pci_out_type begin pci0 pci_mtf generic map memtech gt memtech hmstndx gt 1 fifodepth gt log2 CFG_PCIDEPTH device_id gt CFG_PCIDID vendor_id gt CFG_PCIVID hslvndx gt 4 pindex gt 4 paddr gt 4 haddr gt 16 E00 ioaddr gt 16 400 nsync gt 2 port map rstn clkm pciclk pcii pcio apbi apbo 4 ahbmi ahbmo 1 ahbsi ahbso 4 pcipadsO pcipads generic map padtech gt padtech PCI pads port map pci_rst pci_gnt pci_idsel pci_lock pci_ad pci_cbe pci_frame pci_irdy pci_trdy pci_devsel pci_stop pci_perr pci_par pci_req pci_serr pci_host pci_66 pcii pcio 438 51 51 1 51 2 PCIDMA DMA Controller for the GRPCI interface Introduction The DMA controller is an add on interface to the GRPCI interface This controller perform bursts to or from PCI bus using the master interface of GR PCI Master target unit Figure 1 below illustrates how the DMA controller is attached between the AHB bus and the PCI master interface
283. ame generation Note that there are three different CAN types generally defined e 20A which considers 29 bit ID messages as an error 22 4 22 5 141 e 2 0B Passive which ignores 29 bit ID messages e 2 0B Active which handles 11 and 29 bit ID messages Only 2 0B Active is implemented Status and monitoring The CAN interface incorporates the status and monitoring functionalities This includes e Transmitter active indicator Bus Off condition indicator e Error Passive condition indicator e Over run indicator e 8 bit Transmission error counter e 8 bit Reception error counter The status is available via a register and is also stored in a circular buffer for each received message Transmission The transmit channel is defined by the following parameters e base address e buffer size e write pointer e read pointer The transmit channel can be enabled or disabled 22 5 1 Circular buffer The transmit channel operates on a circular buffer located in memory external to the CAN controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA AHB master interface Each CAN message occupies 4 consecutive 32 bit words in memory Each CAN message is aligned to 4 words address boundaries 1 e the 4 least significant byte address bits are zero for the first word in a CAN message The size of the buffer is defined by the CanTxSIZE SIZE field specifying the numb
284. amoen out std_logic_vector 4 downto 0 rwen inout std_logic_vector 3 downto 0 romsn gt jout std_logic_vector 1 downto 0 iosn out std_logic oen out std_logic read out std_logic writen inout std_logic brdyn Hiin std_logic bexcn in std_logic sdram 1 f sdcke out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect memory controller and memory bus signal memi memory_in_ type signal memo memory_out_type signal sdo sdram_out_type signal wprot wprot_out_type dummy signal not used signal clkm rstn std_ulogic system clock and reset signals used by clock and reset generators signal cgi clkgen_in_type signal cgo clkgen_
285. and bus timing are described in a separate chapter The register map also differs depending on whether the core is in operating mode or in reset mode When reset the core starts in reset mode awaiting configuration Operating mode is entered by clearing the reset request bit in the command register To re enter reset mode set this bit high again AHB interface All registers are one byte wide and the addresses specified in this document are byte addresses Byte reads and writes should be used when interfacing with this core The read byte is duplicated on all byte lanes of the AHB bus The wrapper is big endian so the core expects the MSB at the lowest address The bit numbering in this document uses bit 7 as MSB and bit O as LSB 121 21 4 BasicCAN mode 21 4 1 BasicCAN register map Table 113 BasicCAN address allocation Address Operating mode Reset mode Read Write Read Write 0 Control Control Control Control 1 OxFF Command OxFF Command 2 Status Status 3 Interrupt Interrupt 4 OxFF Acceptance code Acceptance code 5 OxFF Acceptance mask Acceptance mask 6 OxFF Bus timing 0 Bus timing 0 7 OxFF Bus timing 1 Bus timing 1 8 0x00 0x00 9 0x00 al 0x00 10 TX idl TX idl OxFF 11 TX id2 rtr dlc TX id2 rtr dle OxFF 12 TX data byte 1 TX data byte 1 OxFF 13 TX data byte 2 TX da
286. and device identifiers see GRLIB IP Library User s Manual 29 6 Configuration options Table 214 shows the configuration options of the core VHDL generics Table 218 Controller configuration options 229 Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 romaddr ADDR field of the AHB BARO defining PROM address space 0 16 FFF 16 000 Default PROM area is 0x0 OXFFFFFF rommask MASK field of the AHB BARO defining PROM address space 0 16 FFF 16 FFO ramaddr ADDR field of the AHB BAR1 defining RAM address space 0 16 FFFH 16 400 Default RAM area is 0x40000000 0x40FFFFFF rammask MASK field of the AHB BAR1 defining RAM address space 0 16 FFF 16 FFO ioaddr ADDR field of the AHB BAR2 defining IO address space 0 16 FFFH 16 200 Default RAM area is 0x20000000 0x20FFFFFF iomask MASK field of the AHB BAR2 defining IO address space 0 16 FFFH 16 FFO ramws Number of waitstates during access to SRAM area 0 15 0 romws Number of waitstates during access to PROM area 0 15 2 iows Number of waitstates during access to IO area 0 15 2 rmw Enable read modify write cycles 0 1 0 srbanks Set the number of RAM banks 1 8 1 banksz Set the size of bank 1 4 1 16 kB 15 256 MB If setto 0 15 15 zero the bank size is set with the rambsz field in the MCFG2 register rombanks Sets the number of
287. and reset are generated by GR Clock Generator and Reset Generator It is also shown how the correctable error CE signal is connected to the ahb status register It is not mandatory to connect this signal In this example 3 units can be con nected to the status register The SDRAM controller decodes SDRAM area 0x60000000 OX6FFFFFFF SDRAM Configuration and EDAC configuration registers are mapped into AHB I O space on address AHB I O base address 0x 100 library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all used for I O pads use gaisler misc all entity mctrl_ex is port clk in std_ulogic resetn in std_ulogic pllref in std_ulogic other signals sdram memory bus sdcke out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data cb inout std_logic_vector 7 downto 0 EDAC checkbits i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type
288. apbi apbo err 13 13 1 13 2 APB Plug amp play record 69 APBCTRL AMBA AHB APB bridge with plug amp play support Overview The AMBA AHB APB bridge is a APB bus master according the AMBA 2 0 standard The controller supports up to 16 slaves The actual maximum number of slaves is defined in the GRLIB AMBA package in the VHDL constant NAPBSLV The number of slaves can also be set using the nslaves VHDL generic AHB BUS AHB APB Bridge APBO O 4 10 APB SLAVE AHB Slave APBO n Interface 4 lt APB SLAVE APBI Figure 20 AHB APB bridge block diagram Operation 13 2 1 Decoding Decoding generation of PSEL of APB slaves is done using the plug amp play method explained in the GRLIB IP Library User s Manual A slave can occupy any binary aligned address space with a size of 256 bytes 1 Mbyte Write to unassingned areas will be ignored while reads from unassigned areas will return an arbitrary value AHB error response will never be generated 13 2 2 Plug amp play information GRLIB APB slaves contain two plug amp play information words which are included in the APB records they drive on the bus see the GRLIB IP Library User s Manual for more information These records are combined into an array which is connected to the APB bridge The plug amp play information is mapped on a read only address area at the top 4 kbytes of the bridge add
289. apped into address range 0x0 OXOOFFFFFE the SRAM area is mapped into address range 0x40000000 0x40FFFFFE and the I O area is mapped to 0x20000000 Ox 20FFFFFE One chip select is decoded for the I O area while SRAM and PROM can have up to four and two select signals respectively The controller generates both a common write enable signal WRITEN as well as four byte write enable signals WREN If the SRAM uses a common write enable signal the controller can be configured to perform read modify write cycles for byte and half word write accesses Number of waitstates is separately configurable for the three address ranges A single write enable signal is generated for the PROM area WRITEN while four byte write enable signals RWEN 3 0 are provided for the SRAM area If the external SRAM uses common write enable signal the controller can be configured to perform read modify write cycles for byte and half word write accesses Number of waitstates is configurable through VHDL generics for both PROM and SRAM areas A signal BDRIVE is provided for enabling the bidirectional pads to which the data signals are con nected The oepol generic is used for selecting the polarity of these enable signals If output delay is an issue a vectored output enable signal VBDRIVE can be used instead In this case each pad has 56 2 56 3 459 1ts own enable signal driven by a separate register A directive is placed on these registers so that t
290. ar 0 16 FFFH 16 FFFH pirq Interrupt line used by the GRETH 0 NAHBIRQ 1 0 memtech Memory technology used for the FIFOs 0 NTECH inferred ifg_gap Number of ethernet clock cycles used for one interframe 1 255 24 gap Default value as required by the standard Do not change unless you know what your doing attempt_limit Maximum number of transmission attempts for one 1 255 16 packet Default value as required by the standard backoff_limit Limit on the backoff size of the backoff time Default 1 10 10 value as required by the standard Sets the number of bits used for the random value Do not change unless you know what your doing slot_time Number of ethernet clock cycles used for one slot time 1 255 128 Default value as required by the ethernet standard Do not change unless you know what you are doing mdcscaler Sets the divisor value use to generate the mdio clock 0 255 25 mdc The mdc frequency will be clk 2 mdcs caler 1 enable_mdio Enable the Management interface 0 1 0 fifosize Sets the size in 32 bit words of the receiver and transmit 4 32 ter FIFOs nsync Number of synchronization registers used 1 2 2 edcl Enable EDCL 0 1 0 edclbufsz Select the size of the EDCL buffer in kB 1 64 1 macaddrh Sets the upper 24 bits of the EDCL MAC address 0 16 FFFFFF 16 00005E macaddrl Sets the lower 24 bits of the EDCL MAC address 0 16 FFFFFF 16 000000 ipaddrh Sets the upper 16 bits of the EDCL IP address reset 0
291. are not supported so the number of bytes must be a multiple of four between 0 and 504 The words should be sent with the one to be written at the start address first Individual bytes should be transmitted msb first i e the one at bits 31 24 494 63 3 63 4 There is no reply sent for writes since the USB handshake mechanism for bulk writes guarantees that the packet has been correctly received by the target 31 0 Word 1 address 31 16 2 Word 2 r w length 31 0 Word 3 data 128 Figure 236 Layout of USBDCL write commands Figure 88 shows the layout of read commands and replies In this case the command only consists of two words containing the same control information as the two first words for write commands How ever for reads the r w bit must be set to 0 When the read is performed data is read to the buffer belonging to IN endpoint 1 The reply packet is sent when the next IN token arrives after all data has been stored to the buffer The reply packets only contains the read data no control information is needed with the word read from the start address transmitted first Individual bytes are sent with most significant byte first i e the byte at bit 31 downto 24 Read Command 31 0 Word 1 address 31 16 2 Word 2 r w length Read Reply 31 0 Word 0 data 126 Figure 237 Layout of USBDCL read commands and replies 63 2 3 AHB operations
292. as been set up via the AMBA APB interface messages are received by the CAN core To store messages to memory the DMA controller initiates a burst of write accesses on the AMBA AHB bus which are performed by the AHB master When a programmable number of mes sages have been received the DMA controller issues an interrupt The CAN controller can detect a SYNC message and generate an interrupt which is also available as an output signal from the core The SYNC message identifier is programmable via the AMBA APB interface Separate synchronisation message interrupts are provided The CAN controller can transmit and receive messages on either of two CAN busses but only on one at a time The selection is programmable via the AMBA APB interface Note that it is not possible to receive a CAN message while transmitting one AMBA Redundant AHB bus CAN bus On Chip AHB CAN 2 0 Core Memory slave DMA Controller eri AMBA APB bus Figure 51 Block diagram of the internal structure of the GRCAN 22 1 1 Function The core implements the following functions e CAN protocol e Message transmission e Message filtering and reception 140 22 2 22 3 e SYNC message reception e Status and monitoring e Interrupt generation e Redundancy selection 22 1 2 Interfaces The core provides the following external and internal interfaces e CAN interface e AMBA AHB master interface with sideband signals as per GRLIB including
293. asserted 407 lead in datai data2 lead out DA iosn IA A es oen AOS DO II TNT T T T data cb Figure 190 1O read cycle 0 waitstates lead in data lead out address iosn A A Ge oen ee eet A e a ES E ES dl cb CB1 Figure 191 VO write cycle 0 waitstates 47 4 SRAM access The SRAM area can be up to 1 Gbyte divided on up to five RAM banks The size of banks 1 4 MEMO RAMSN 3 0 is programmed in the RAM bank size field MCFG2 12 9 and can be set in binary steps from 8 Kbyte to 256 Mbyte The fifth bank MEMO RAMSNJ 4 decodes the upper 512 Mbyte A read access to SRAM consists of two data cycles and between zero and three waitstates Accesses to MEMO RAMSN 4 can further be stretched by de asserting MEMI BRDYN until the data is available On non consecutive accesses a lead out cycle is added after a read cycle to prevent bus contention due to slow turn off time of memories or I O devices Figure 192 shows the basic read cycle waveform zero waitstate 408 47 5 datai data2 lead out datai data2 lead out ree C a IX IX 42 ramsn NA Y Neb I Pie ramoen ts T cb CB1 CBA Y Figure 192 SRAM non consecutive read cyclecs For read accesses to MEMO RAMSN 4 0 a separate output enable signal MEMO RAMOENT n is provided for each RAM bank and only asserted when that bank is selected A write access is simila
294. ation When the Speed negotiation and reset procedure is finished the selected speed mode is noti fied to the Serial Interface Engine SIE The SIE is enabled when the SNE notifies that the reset procedure has finished It then waits for pack ets to arrive and processes them according to the USB 2 0 specification There are four endpoints one in out pair of control type with number 0 default pipe and one in out pair of bulk type with number 1 Data received to an endpoint is stored in the endpoint s buffer located in block ram The AIE reads the packets from the endpoint buffers and if the packet was received to endpoint O the device request is processed directly and a response is stored in the buffer for IN endpoint 0 This is also notified to the SIE which transmits the data to the host when the next IN token arrives Device requests never access the AHB bus 493 AHB UTMI USBDCL TXVALID TERM_SELECT SUSPENDM OPMODE 1 0 XCVR_SELECT RESET DATAIN 7 0 CLK LINESTATE 1 0 TXREADY RXVALID RXACTIVE 4 DATAOUT 7 0 lt RXERROR SIE d gt AHB Master AIE I gt Bienes ENDPOINT BUFFERS MI SNE Figure 235 Block diagram of the internal structure of the USBDCL If the packet was received to endpoint 1 it is an AHB command and the AIE performs the operation on the AHB bus Read commands arrive to OUT endpoint 1 and the read dat
295. ault the PROM area is mapped into address range 0x0 OXOOFFFFFE the SRAM area is mapped into address range 0x40000000 Ox40FFFFFF and the I O area is mapped to 0x20000000 Ox20FFFFFF One chip select is decoded for the I O area while SRAM and PROM can have up to 8 chip select sig nals The controller generates both a common write enable signal WRITEN as well as four byte write enable signals WREN If the SRAM uses a common write enable signal the controller can be configured to perform read modify write cycles for byte and half word write accesses Number of waitstates is separately configurable for the three address ranges The EDAC function is optional and can be enabled with the edacen VHDL generic The configura tion of the EDAC is done through a configuration register accessed from the APB bus During nomi nal operation the EDAC checksum is generated and checked automatically Single errors are corrected without generating any indication of this condition in the bus response If a multiple error is detected a two cycle error response is given on the AHB bus 220 Single errors can be monitored in two ways e by monitoring the CE signal which is asserted for one cycle each time a single error is detected e by checking the single error counter which is accessed from the MCFG3 configuration register The CE signal can be connected to the AHB status register which stores information of the AHB instruction causing the error and als
296. ause the PHY inserts a delay between packets and packet boundaries are located by letting the TEXTIO read function set an invalid value parameter to true when an invalid row is found The delays between packets are currently hard coded in the design When a certain number of packets have been sent set by the win_size generic a different delay value is used once and then the normal values are used again This is repeated indefinitely The output from the MAC is stored in a file called outdata in the current working directory Data is formatted in the same way as the input file An example of this formatting is shown in figure 221 start 1101 1001 new 1001 0000 new 1001 Figure 221 An example of an indata file layout Configuration options Table 442 shows the configuration options of the model VHDL generics Table 442 Configuration options Generic Function Allowed range Default win_size Sets the number of packets between each special delay all positive integers 3 446 53 4 53 5 53 6 Signal descriptions Table 443 shows the interface signals of the model VHDL ports Table 443 Signal descriptions Signal name Field Type Function Active RESETN Input Reset Low LED_CFG Input Configuration signals used to select the operat ing mode MDIO Input Data signal for the management interface Cur Output rently not used TX_CL
297. b amba package It checks each entry in the array for a valid ven dor id all nonzero ids are considered valid and if one is found it also retrieves the device id The description for these ids are obtained from the GRLIB DEVICES package and is printed on standard out together with the slave number If the index check is enabled done with a VHDL generic the report module also checks if the pindex number returned in the record matches the array number of the record currently checked the array index If they do not match the simulation is aborted and an error message is printed The address range and memory type is also checked and printed The address information includes type address and mask The address ranges currently defined are AHB memory AHB I O and APB I O All APB devices are in the APB I O range so the type does not have to be checked From this infor mation the report module calculates the start address of the device and the size of the range The information finally printed is start address and size 14 14 1 14 2 73 APBPS2 PS 2 keyboard with APB interface Introduction The PS 2 interface is a bidirectional synchronous serial bus primarily used for keyboard and mouse communications The APBPS2 core implements the PS2 protocol with a APB back end Figure 22 shows a model of APBPS2 and the electrical interface V FPGA ASIC PEN S2Data_out g e A Data Bea
298. be set again 42 4 4 Enabling descriptors As mentioned earlier one or more descriptors must be enabled before reception can take place Each descriptor is 8 byte in size and the layout is shown in figure 141 The descriptors should be written to the memory area pointed to by the receiver descriptor table address register When new descriptors are added they must always be placed after the previous one written to the area Otherwise they will not be noticed A descriptor is enabled by setting the address pointer to point at a location where data can be stored and then setting the enable bit The WR bit can be set to cause the selector to be set to zero when reception has finished to this descriptor IE should be set if an interrupt is wanted when the reception has finished The DMA control register interrupt enable bit must also be set for this to happen The descriptor packet address should be word aligned All accesses on the bus are word accesses so complete words will always be overwritten regardless of whether all 32 bit contain received data Also if the packet does not end on a word boundary the complete word containing the last data byte will be overwritten If the rxunaligned or rnap VHDL generic is set to 1 this restriction is removed and a number of bytes can be received to any packet address without excessive bytes being overwrit ten 324 31 30 29 28 27 26 25 24 0 0x0 TR DC HO EP TE WR EN PACKET LENGTH 31 0
299. ber of masters nahbs integer range 1 to NAHBSLV NAHBSLV number of slaves ioen integer range 0 to 15 1 enable I O area disirg integer range 0 to 1 0 disable interrupt routing fixbrst integer range 0 to 1 0 support fix length bursts debug integer range 0 to 2 2 print configuration to consolee fpnpen integer range 0 to 1 0 full PnP configuration decoding busndx integer range 0 to 3 0 icheck integer range 0 to 1 1 i port rst in std_ulogic clk in std_ulogic msti out ahb_mst_in_type msto in ahb_mst_out_bus_vector slvi out ahb_slv_in type slvo in ahb_slv_out_bus_vector end component Instantiation This examples shows how the core can be instantiated Note that master and slave outputs from all AHB buses in the systems are combined into vectors msto and slvo where each element holds master or slave outputs on one AHB bus library ieee use ieee std_logic_1164 all library grlib use grlib amba all AMBA signals signal signal signal signal ahbsi ahbso ahbmi ahbmo ahb_slv_in_type ahb_slv_out_bus_vector ahb_mst_in_type ahb_mst_out_bus_vector others gt others gt ahbs_none others gt others gt ahbm_none 5 10 41 begin ARBITER ahb0 ahbctrl AHB arbiter multiplexer generic map defmast gt CFG_DEFMST split gt CFG_SPLIT rrobin gt CFG_RROBIN ioaddr gt CFG_AHBIO nahbm gt 8 nahbs gt 8 bus
300. bit should be written with a one after the new descriptors have been enabled Reset value 0 Receive Enable RE Should be written with a one each time new descriptors are enabled As long as this bit is one the GRETH will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again This bit should be written with a one after the new descriptors have been enabled Reset value 0 Transmitter Interrupt TI Enable Transmitter Interrupts An interrupt will be generated each time a packet is transmitted when this bit is set The interrupt is generated regardless if the packet was transmitted successfully or if it terminated with an error Not Reset Receiver Interrupt RI Enable Receiver Interrupts An interrupt will be generated each time a packet is received when this bit is set The interrupt is generated regardless if the packet was received successfully or if it terminated with an error Not Reset Full Duplex FD If set the GRETH operates in full duplex mode otherwise it operates in half duplex Not Reset Promiscuous Mode PM If set the GRETH operates in promiscuous mode which means it will receive all packets regardless of the destination address Not Reset Reset RS A one written to this bit resets the GRETH core Self clearing Speed SP Sets the current speed mode 0 10 Mbit 1 100 Mbit Only used in RMII mode rmii 1 A default value is automatically read from
301. bits Defines the number of bits in the I O port 1 to 32 8 imask Defines which I O lines are provided with interrupt gen 0 16 FFFF 0 eration and shaping oepol Select polarity of output enable signals 0 active low 1 0 1 0 active high Signal descriptions Table 330 shows the interface signals of the core VHDL ports Table 330 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI A Input APB slave input signals APBO Output APB slave output signals GPIOO OEN 31 0 Output T O port output enable see oepol DOUT 31 0 Output T O port outputs VAL 31 0 Output The current synchronized value of the GPIO signals GPIOI DIN 31 0 Input T O port inputs see GRLIB IP Library User s Manual Library dependencies Table 331 shows libraries used when instantiating the core VHDL libraries Table 331 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Signals component Component declaration Component declaration The core has the following component declaration ibrary gaisler use gaisler misc all entity grgpio is 41 9 generic pindex paddr pmask imask nbits i port rst in clk in apbi in apbo ou gpioi in gpioo ou i end Instantiation integer 0 integer 0 integer l6 fff integer 16 0000 integer
302. ble TF when set Transmitter FIFO level interrupts are enabled External Clock EC if set the UART scaler will be clocked by UARTILEXTCLK Loop back LB if set loop back mode will be enabled Flow control FL if set enables flow control using CTS RTS when implemented Parity enable PE if set enables parity generation and checking when implemented Parity select PS selects parity polarity 0 even parity 1 odd parity when implemented Transmitter interrupt enable TI if set interrupts are generated when a frame is transmitted Receiver interrupt enable RI if set interrupts are generated when a frame is received Transmitter enable TE if set enables the transmitter O NU pu DAN ODO Receiver enable RE if set enables the receiver 15 4 4 UART Scaler Register Table 81 UART scaler reload register Al 12 11 0 RESERVED SCALER RELOAD VALUE 11 0 Scaler reload value Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier OxOOC For a description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 82 shows the configuration options of the core VHDL generics Table 82 Configuration options Generic Function Allowed range Default pindex APB slave index 0 NAPBSLV 1 0 paddr ADDR field of the APB BAR 0 16 FFFH 0 pmask MASK field of the APB BAR 0 16 FFFH
303. ble 2 Floating point units Name Function Vendor Device License GRFPU High performance IEEE 754 Floating point unit COM GRFPU Lite Low area IEEE 754 Floating point unit COM Table 3 Memory controllers Name Function Vendor Device License SRCTRL 8 32 bit PROM SRAM controller 0x01 0x008 COM GPL SDCTRL PC133 SDRAM controller 0x01 0x009 COM GPL FTSDCTRL 32 64 bit PC133 SDRAM Controller with EDAC 0x01 0x055 FT FTSRCTRL Fault Tolerant 32 bit PROM SRAM IO Controller 0x01 0x051 FT MCTRL 8 16 32 bit PROM SRAM SDRAM controller 0x04 0x00F LGPL FTMCTRL 8 32 bit PROM SRAM SDRAM controller with EDAC 0x01 0x054 FT AHBSTAT AHB failing address register 0x01 0x052 COM GPL DDRCTRL 8 16 32 64 bit DDR controller with two AHB ports Xilinx only 0x01 0x023 COM GPL DDRSPA Single port 16 32 64 bit DDR266 controller Xilinx and Altera 0x01 0x025 COM GPL SSRCTRL 32 bit synchronous SRAM SSRAM controller 0x01 0x00A COM FTSRCTRL8 8 bit SRAM 16 bit IO Memory Controller with EDAC 0x01 0x056 FT Table 4 AMBA Bus control 17 Name Function Vendor Device License AHB2AHB Uni directional AHB AHB Bridge 0x01 0x020 COM AHBBRIDGE Bi directional AHB AHB Bridge 0x01 0x020 COM AHBCTRL AMBA ABB bus controller with plug amp play
304. bled through the PAGEO register Because of the byte twisting byte sized PIO accesses work correctly but 16 and 32 bit PIO accesses need to be twisted before being sent to the PCI core NOTE Only accesses that go from AHB to PCI and vice versa are twisted i e not accesses to config uration space or the PAGEO register If any of the PCI interrupts lines specified through the irgmask generic is asserted the PCI core will drive irq number irq E g if irqmaskis 1 only PCI int A will be used but if it is 3 PCI int A and B will be used PCI Target Interface PCI target interface occupies two memory areas in the PCI address space Memory mapping is deter mined by BARO and BARI registers of the units Configuration Space Header The size of the PCI memory areas is determined by number of bits actually implemented by BAR registers configurable through abits and dmaabits VHDL generics PCI Target interface handles following PCI commands Configuration Read Write Single access to Configuration Space Header No AHB access is per formed Memory Read If prefetching is enabled the units AHB master interface fetches a cache line otherwise a single AHB access is performed Memory Read Line The unit prefetches data according to the value of the cache line size regis ter Memory Read Multiple The unit performs maximum prefetching This can cause long response time depending of the user defined FIFO depth Memory Write Memory Write an
305. bmi ahbmo 5 12 12 1 12 2 AMBAMON AMBA Bus Monitor Overview 63 The AMBA bus monitor checks the AHB and APB buses for violations against a set of rules When an error is detected a signal is asserted and error message is optionally printed Rules This section lists all rules checked by the AMBA monitor The rules are divided into four different tables depending on which type of device they apply to Some requirements of the AMBA specification are not adopted by the GRLIB implementation on a system level These requirements are listed in the table below Table 54 Requirements not checked in GRLIB Rule Number 1 Description A slave which issues RETRY must only be accessed by one master at a time References AMBA Spec Rev 2 0 3 38 Table 55 AHB master rules Rule Number Description References 1 Busy can only occur in the middle of bursts That is only after a NON AMBA Spec Rev 2 0 3 9 SEQ SEQ or BUSY http www arm com support faqip 492 html 2 Busy can only occur in the middle of bursts It can be the last access of AMBA Spec Rev 2 0 3 9 a burst but only for INCR bursts http www arm com support faqip 492 html 3 The address and control signals must reflect the next transfer in the AMBA Spec Rev 2 0 3 9 burst during busy cycles 4 The first transfer of a single access or a burst must be NONSEQ this is AMBA
306. brary gaisler use gaisler misc all component ahbtrace is generic hindex integer 0 ioaddr integer 16 000 iomask integer 16 E00 tech integer 0 irg integer 0 kbytes integer 1 port rst in std_ulogic clk in std_ulogic ahbmi in ahb_mst_in_type ahbsi in ahb_slv_in_type ahbso out ahb_slv_out_type end component 11 11 1 11 2 Send 11 Length 1 Addr 31 24 Addr 23 16 Addr 15 8 Addr 7 0 Data 31 24 Data 23 16 Data 15 8 Data 7 0 59 AHBUART AMBA ABB Serial Debug Interface Overview The interface consists of a UART connected to the AMBA AHB bus as a master A simple communi cation protocol is supported to transmit access parameters and data Through the communication link a read or write transfer can be generated to any address on the AMBA AHB bus Baud rate hi Serial port generator BDO y Controller gt AMBA APB RX K Receiver shift register gt Transmitter shift register gt K TX y 1 AHB master interface AHB data response AMBA AHB Figure 14 Block diagram Operation 11 2 1 Transmission protocol The interface supports a simple protocol where commands consist of a control byte followed by a 32 bit address followed by optional write data Write access does not return any response while a read access only returns the read data Data
307. bridge implements posted writes During the AHB write transfer on the slave side the data is buffered in the internal write FIFO and the transfer is completed on the slave side by always giving OKAY response The master interface requests the bus and performs the write transfer when the mas ter bus is granted If the burst transfer is longer than the size of the write FIFO the SPLIT response is given when the FIFO gets full When the FIFO becomes empty the splitted master is allowed to re attempt the remaining accesses of the write burst transfer 2 2 4 Locked transfers The AHB AHB bridge supports locked transfers The master bus will be locked when the bus is granted and remain locked until the transfer completes on the slave side Registers The core does not implement any registers Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x020 For description of vendor and device identifiers see GRLIB IP Library User s Manual 2 5 Configuration options Table 16 shows the configuration options of the core VHDL generics Table 16 Configuration options VHDI generics Generic Function Allowed range Default hsindex Slave I F AHB index 0 to NAHBMAX 1 0 hmindex Master I F AHB index 0 to NAHBMAX 1 0 dir Clock frequency ratio 0 1 0 0 clock frequency on master bus is higer than frequency on the slave bus 1 otherw
308. bus I O area 18 12 RESERVED 11 PROM write enable PWEN Enables write cycles to the PROM area 10 RESERVED 9 8 PROM width PROM WIDTH Sets the data width of the PROM area 00 8 01 16 10 32 7 4 PROM write waitstates PROM WRITE WS Sets the number of wait states for PROM write cycles 0000 0 0001 1 0010 2 1111 15 3 0 PROM read waitstates PROM READ WS Sets the number of wait states for PROM read cycles 0000 0 0001 1 0010 2 1111 15 Reset to 1111 During power up the prom width bits 9 8 are set with value on MEMI BWIDTH inputs The prom waitstates fields are set to 15 maximum External bus error and bus ready are disabled All other fields are undefined 47 13 2 Memory configuration register 2 MCFG2 Memory configuration register 2 is used to control the timing of the SRAM and SDRAM Table 416 Memory configuration register 2 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 SDRF TRP SDRAM TRFC TCAS SDRAM BANKSZ SDRAM COLSZ SDRAM CMD D64 RESERVED 15 14 13 12 9 8 7 6 5 4 3 2 1 0 SE Sl RAM BANK SIZE RBRDY RMW RAM WIDTH RAM WRITE WS RAM READ WS 31 SDRAM refresh SDRF Enables SDRAM refresh 30 SRAM TRP parameter TRP tgp will be equal to 2 or 3 system clocks 0 1 29 27 SDRAM TRFC parameter SDRAM TRFC tree will be equal to 3 field value system clocks 26 SDRA
309. c ccc cseccccveee eben sces apes sesstensesvnsca cep cpunbepesedeseasvecusseveeu sets sevtsessnecsebsndsts Eo EREE EESE irena 97 17 6 S1gtalAS SCH PONS turco ida alboriid 98 17 7 Library dependencies sso cin geek ee ee ee eS hs ap RE A ee 98 17 8 Install tati 98 B1553BC AMBA plug amp play interface for Actel Corel553BBC coooconnccnnocinicnnonnccononannss 101 18 1 OVVIE Wisin a 101 18 2 AB tear id 102 18 3 Operation dietas 102 18 4 NN 102 18 5 Vendor and device 1deMtifierS 3 02 esac sede secs cessed ssiaeities ssayesuces a EE Eor ra ES EED rien canti 103 18 6 Configuration options a a in 103 18 7 Sigal dE SCHPUOUS usa abi 104 18 8 Library dependencies eri in 104 18 9 Component declaratiON ooooncinnnnoninnnioncnnnnnnconecnnonnnnnnonn non non nnnnonn non no nn non nono non ESEVE kE non nn conc ENE TOOP IEPES nan ISERE SSS 104 18 10 Instant it aires 105 B1553BRM AMBA plug amp play interface for Actel Corel 553BRM sesers 106 19 1 II O NN 106 19 2 AUB Interface ona iets atid AEN A a sree aire nea eciees 107 19 3 OPCratiOn NN 107 19 4 REGISTERS 2c sve A S ENOAR S ets 108 19 5 Vendor and device identifiers inneni ceceseeeeceseeeeceseeeeeeaeeseecseesaecaecsaesaecacssecseeseeeeeeseseeseaeseeeeas 109 19 6 ConfiguratiOn Options mail 109 19 7 Signal descriptions iia a ari 110 19 8 Library dependencies siii ileso beth hi spsesedvnsce EEE SAKro rE EE oboe eones SVE ENTES VENEREE ES 111 19 9 Component declaran ices neok E hie E E E R E E
310. c prom S o prom exe bash make ahbrom vhd Creating ahbrom vhd file size 272 bytes address bits 9 The default binary file for creating a PROM is prom exe To use a different file run make with the FILE parameter set to the input file bash make ahbrom vhd FILE myfile exe The created PROM is realized in synthesizable VHDL code using a CASE statement For FPGA tar gets most synthesis tools will map the CASE statement on a block RAM ROM if available For ASIC implementations the ROM will be synthesized as gates It is then recommended to use the pipe option to improve the timing Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x01B For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 36 shows the configuration options of the core VHDL generics Table 36 Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 NAHBSLV 1 0 haddr The MSB address of the AHB area Sets the 12 most sig O 16 FFF 16 FFFH nificant bits in the 32 bit AHB address hmask The AHB area address mask Sets the size of the AHB 0 16 FFFH 16 FFO area and the start address together with haddr tech Not used pipe Add a pipeline stage on read data 0 0 kbytes Not used 50 8 5 8 6 8 7 8 8 Signal descriptions Table 37 shows the interface
311. ccess from PCI Configuration Space Header see section 50 4 434 50 8 31 28 27 23 22 15 14 13 12 11 109 8 7 0 MMAP RESERVED LTIMER WE SH BM MS WE RB CTO CLS Figure 211 Configuration Status register 31 28 Memory Space Map register Defines mapping between PCI Masters AHB memory address space and PCI address space when performing PCI memory cycles Value of this filed is used as 4 MSB of the PCI address LSB bits are taken from the AHB address 27 23 Reserved 22 15 Latency Timer LTIMER Value of Latency Timer Register in Configuration Space Header Read only 14 Write Error WE Target Write Error Write access to units target interface resulted in error Read only 13 System Host SH Set if the unit is system host Read only 12 Bus Master BM Value of BM field in Command register in Configuration Space Header Read only 11 Memory Space MS Value of MS field in Command register in Configuration Space Header Read only 10 Write Burst Command WB Defines PCI command used for PCI write bursts 0 Memory Write 1 Memory Write and Invalidate 9 Read Burst Command RB Defines PCI command used for PCI read bursts 0 Memory Read Multiple 1 Memory Read Line 8 Configuration Timeout CTO Received timeout when performing Configuration cycle Read only 7 0 Cache Line Size CLS Value of Cache Li
312. ce for the memory interface and one APB slave interface for the CPU interface and control registers The Actel Core1553BRM core entity named BRM is configured to use the shared memory interface and only internal register access is allowed through the APB slave interface Data is read and stored via DMA using the AHB master interface 19 2 19 3 107 BIS9SBRM A ce ce eee eee A es 1553 signals Actel Core1553BRM lg i Core1553BRM signals CPU IF MEMIF A y A 4 Control APB slave laa registers gt AHB master IF AMBA APB AMBA AHB Figure 40 Block diagram AHB interface The amount of memory that the Mil Std 1553B interface can address is 128 2 abit VHDL generic i e abit gt 128 kbytes The base address of this memory area must be aligned to a boundary of its own size and written into the AHB page address register The 16 bit address provided by the Corel1553BRM core is shifted left one bit and forms the AHB address together with the AHB page address register Note that all pointers given to the Core1553BRM core needs to be right shifted one bit because of this The amount of memory needed for the Core1553BRM core is operation and implementation specific Any configuration between 1 to 128 kilobytes is possible although a typical system needs at least 4 kbyte of memory The allocated memory area needs to be aligned to a boundary of its own size and the number of bits needed to address
313. ce provides access to PHY configuration and status registers through a two wire interface which is included in the MII interface The GRETH_GBIT provides full support for the MDIO interface 290 35 6 The MDIO interface can be used to access from 1 to 32 PHY containing 1 to 32 16 bit registers A read transfer 1 set up by writing the PHY and register addresses to the MDIO Control register and set ting the read bit This caused the Busy bit to be set and the operation is finished when the Busy bit is cleared If the operation was successful the Linkfail bit is zero and the data field contains the read data An unsuccessful operation is indicated by the Linkfail bit being set The data field is undefined in this case A write operation is started by writing the 16 bit data PHY address and register address to the MDIO Control register and setting the write bit The operation is finished when the busy bit is cleared and it was successful if the Linkfail bit is zero Ethernet Debug Communication Link EDCL The EDCL provides access to an on chip AHB bus through Ethernet It uses the UDP IP and ARP protocols together with a custom application layer protocol The application layer protocol uses an ARQ algorithm to provide reliable AHB instruction transfers Through this link a read or write trans fer can be generated to any address on the AHB bus The EDCL is optional and must be enabled with a generic 35 6 1 Operation The EDCL receives pack
314. chpoints 0 4 4 0 Number of implemented registers windows corresponds to NWIN 1 44 2 10 Exceptions 375 LEON adheres to the general SPARC trap model The table below shows the implemented traps and their individual priority Table 393 Trap allocation and priority Trap TT Pri Description reset 0x00 1 Power on reset write error 0x2b 2 write buffer error instruction_access_error 0x01 3 Error during instruction fetch illegal_instruction 0x02 5 UNIMP or other un implemented instruction privileged_instruction 0x03 4 Execution of privileged instruction in user mode fp_disabled 0x04 6 FP instruction while FPU disabled cp_disabled 0x24 6 CP instruction while Co processor disabled watchpoint_detected 0x0B 7 Hardware breakpoint match window_overflow 0x05 8 SAVE into invalid window window_underflow 0x06 8 RESTORE into invalid window register_hadrware_error 0x20 9 register file EDAC error LEON FT only mem_address_not_aligned 0x07 10 Memory access to un aligned address fp_exception 0x08 11 FPU exception cp_exception 0x28 11 Co processor exception data_access_exception 0x09 13 Access error during load or store instruction tag_overflow Ox0A 14 Tagged arithmetic overflow divide_exception 0x2A 15 Divide by zero interrupt_level_1 0x11 31 Asynchronous interrupt 1 interrupt_level_2 0x12 30 Asynchronous interrupt 2 interrupt_level_
315. cia 52 9 6 Signal descriptlons o iia 52 9 7 Library dependencias lis 52 9 8 Tsta OM 2 i sce Ga saete sesh seesvedses vag con sui aa r ae sess aa E a i Eea EREKE Ee EEEE ea cid 53 AHBTRACE AHB Trace DU ebandeud sues sdesu R e A aa 55 10 1 OV ELVIS W aore eraa e ees eee E E dd ida 55 10 2 Operation A EA 55 10 3 ROSISLORS soi cg cus ick tacky o ins ise dls pes 56 10 4 Vendor and device Identifiers usais iso 57 10 5 Configuration Options amaia 57 10 6 Signal descripta EEEE 58 10 7 Library dependencies nnn nan aen e pls ea as eg se AEE E RR T AR EREE STER E 58 10 8 Component declarations c c iccsecssesecevess oeseta css va seses ses sacusth sotea Soeek och cs Sou keri Eee eC edad dad revesii isise 58 AHBUART AMBA AHB Serial Debug Interface ooooonnncccnnoccconnccnonnccnnnnncnnoncnononacnnnnccnnn noo 59 11 1 COVERVIS Wisi OS 59 11 2 A NN 59 11 3 O E aidan sadanii iia Alesis 60 11 4 Vendor and device demtifi ers ii 61 11 5 Contisiitation Options iss claras lod pi svt near ae Ea EEE esas tides sats Seon cette EKES EEE VE EEEE nE A S 61 11 6 Signal desciipti ns ssnin pr eneen eo cas creaban OEE ENES ISEE EVE Ero aan ESE aSr KPA SAE SSe dead s OTEK ESE Ss 61 11 7 Labrary dependencies dica ais 61 11 8 Instantiations 152 52 Ae ARR AR A A A O E 61 AMBAMON AMBA Bus Monitor si ost erade eee a BQ ene 63 12 1 PD RN 63 12 2 RUNES 2 A Se er 63 12 3 Configuration Options eie e a a eea cos chuneshee sine genecbucsseee tetera atest dete ese
316. ck Domain Figure 140 Schematic of the link interface receiver 42 3 4 Time interface The time interface is used for sending Time codes over the Space Wire network and consists of a time counter register time ctrl register tick in signal tick out signal tick in register field and a tick out 322 42 4 register field There are also two control register bits which enable the time receiver and transmitter respectively Each Time code sent from the grspw is a concatenation of the time ctrl and the time counter register There is a timetxen bit which is used to enable Time code transmissions It is not possible to send time codes if this bit is zero Received Time codes are stored to the same time ctrl and time counter registers which are used for transmission The timerxen bit in the control register is used for enabling time code reception No time codes will be received if this bit is zero The two enable bits are used for insuring that a node will not accidentally both transmit and receive time codes which violates the SpaceWire standard It also insures that a the master sending time codes on a network will not have its time counter overwritten if another faulty node starts sending time codes The time counter register is set to 0 after reset and is incremented each time the tick in signal is asserted for one clock period and the timetxen bit is set This also causes the link interface to send the new value on the network
317. ck diagram Operation 6 2 1 Transmission protocol The JTAG Debug link decodes two JTAG instructions and implements two JTAG data registers the command address register and data register A read access is initiated by shifting in a command con sisting of read write bit AHB access size and AHB address into the command address register The AHB read access is performed and data is ready to be shifted out of the data register Write access is performed by shifting in command AHB size and AHB address into the command data register fol lowed by shifting in write data into the data register Sequential transfers can be performed by shifting in command and address for the transfer start address and shifting in SEQ bit in data register for fol lowing accesses The SEQ bit will increment the AHB address for the subsequent access Sequential transfers should not cross a 1 kB boundary Sequential transfers are always word based Table 28 JTAG debug link Command Address register 34 33 32 31 0 W SIZE AHB ADDRESS 34 Write W 0 read transfer 1 write transfer 33 32 AHB transfer size 00 byte 01 half word 10 word 11 reserved 31 30 AHB address Table 29 JTAG debug link Data register 32 31 0 SEQ AHB DATA 32 Sequential transfer SEQ If 1 is shifted in this bit position when read data is shifted out or write data shifted in the subsequent transfer w
318. ck to data non tri state delay rising clk edge 0 15 ns tETMCTRLS clock to data tri state delay rising clk edge 0 15 ns tETMCTRL6 clock to output delay rising clk edge 0 15 ns tETMCTRL7 data input to clock setup rising clk edge 7 ns tETMCTRL8 data input from clock hold rising clk edge 1 ns tFTMCTRLO input to clock setup rising clk edge 7 ns tETMCTRL10 input from clock hold rising clk edge 1 ns The timing waveforms and timing parameters are shown in figure 82 and are defined in table 206 208 27 21 27 22 sdcasn sdrasn gt E FTMCTRL11 sdwen sdesn write X_nop X read X nop X noe X term X nop X nop X nop sddqnm tFIMCTRLA1 oi SX XD a a tETMCTRLI2 A A e termCTRLI3 teTMCTRL14 data cb sa scb FTMCTRL15 Figure 84 Timing waveforms SDRAM accesses Table 207 Timing parameters SDRAM accesses Name Parameter Reference edge Min Max Unit tFTMCTRL11 clock to output delay rising clk edge 0 10 ns tFTMCTRL12 clock to data output delay rising clk edge 0 10 ns tFTMCTRL13 data clock to data tri state delay rising clk edge 0 15 ns tETMCTRL14 data input to clock setup rising clk edge 7 ns tETMCTRLI5 data input from clock hold rising clk edge 1 ns Library dependencies Table 208 shows libraries used when instantiating the core VHDL libraries Table 208 Library dependencies Library
319. claratoria direis 423 48 8 A NS 424 MULTLIB High performance multipliers oooonncccnnnoccnoncccnonaccnnncnonnnnnonnncnononcnnnnnccnnnncnnnnos 425 49 1 OVNI Wear il tada 425 49 2 Configuration opto Sica is ia 425 49 3 Signal descriptions ossessivo Kirssi ch iodo irene cubes soba candente oasis 425 49 4 Library dependencies meritos nit inca EEES EE e KEEP eS EERSTE REESE 425 49 5 Component declara nnna eis eds 426 49 6 Instantiation s ra 426 GRPCI PCL Tareet Master UE aia 427 50 1 OWORVICW sings 200 Site eas ade ee es iad tes lat esata atte ah Bae 427 50 2 OOPSLA ON abc ai 427 50 3 PCI Target Interface eset ie ek hae ti aaa 428 50 4 PCI Target Configuration Space Header Registers ooooonccncnconconoconcnnnonnnononanonancnn con ncnnc rn nora con ncnnccnnons 429 50 5 PCI T rget Map Registers csi rt ne itera atrapa 431 50 6 PCI Master Interface sisisihin ocio bandadas dalla dotes E did dido hinata 432 50 7 A O 433 50 8 Vendor and device identifiers ninan a E ran non no nn non nono O neon non neon nen A ANETES EEY 434 50 9 Configuration Opuons ici 435 50 10 Signal description saser ienee rerien r aoa e ates ois teces pE Esa a SEEE ass EEEE Eaa U EEEE A SESS 436 50 11 Library dependencies sinesi eens ineen tats onnee roire EErEE EE Se EI ESE aV e EOE KE EA E I SRE ETENEE S EEES 436 50 12 Tostadas 436 PCIDMA DMA Controller for the GRPCI interface conconocnnoninonionanancnnnnononancnnnnanananinnas 438 51 1 IntrOdU CHO iris en ii da
320. clk in std_ulogic resetn in std_ulogic pllref in std_ulogic sdcke out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt signal sdi sdctrl_in_type signal sdo sdctrl_out_type signal clkm rstn std_ulogic signal cgi clkgen_in_type signal cgo clkgen_out_type signal gnd std_ulogic begin Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 tech gt virtex2 s port map clk gnd clkm open open sdclk ope cgi pllctrl lt 00 cgi pllrst lt resetn rsto0 rstgen port map resetn clkm cgo clklock rstn SDRAM controller sde sdctrl generic map ioaddr gt 1 hindex gt 3 haddr gt pwron gt 0 invclk gt 0 clk_div gt 2 apb_none ahbs_none ahb
321. clock generator locked High CLKDDRO Internal DDR clock output after clock multiplication CLKDDRI Clock input for the internal DDR clock domain Must be connected to CLKDDRO AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals DDR_CLK 2 0 Output DDR memory clocks positive High DDR_CLKB 2 0 Output DDR memory clocks negative Low DDR_CLK_FB_OUT Output Same a DDR_CLK but used to drive an external clock feedback DDR_CLK_FB Input Clock input for the DDR clock feed back DDR_CKE 1 0 Output DDR memory clock enable High DDR_CSB 1 0 Output DDR memory chip select Low DDR_WEB Output DDR memory write enable Low DDR_RASB Output DDR memory row address strobe Low DDR_CASB Output DDR memory column address strobe Low DDR_DM DDRBITS 8 1 0 Output DDR memory data mask Low DDR_DQS DDRBITS 8 1 0 Bidir DDR memory data strobe Low DDR_AD 13 0 Output DDR memory address bus Low DDR_BA 1 0 Output DDR memory bank address Low DDR_DQ DDRBITS 1 0 BiDir DDR memory data bus 1 see GRLIB IP Library User s Manual 2 Polarity selected with the oepol generic Library dependencies Table 182 shows libraries used when instantiating the core VHDL libraries Table 182 Library dependencies laration Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec 23 7 Component declaration co
322. color green 7 0 Video background color blue 16 3 3 VGA Foreground Color 31 24 23 16 15 8 7 0 RESERVED RED GREEN BLUE Figure 35 PS 2 status register 23 16 Video foreground color red 15 8 Video foreground color green 7 0 Video foreground color blue Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x060 For a description of vendor and device identifiers see GRLIB IP Library User s Manual 92 16 5 16 6 16 7 16 8 Configuration options Table 86 shows the configuration options of the core VHDL generics Table 86 Configuration options Generic Function Allowed range Default memtech Technology to implement on chip RAM 0 NTECH 2 pindex APB slave index 0 NAPBSLV 1 0 paddr ADDR field of the APB BAR 0 16 FFFH 0 pmask MASK field of the APB BAR 0 16 FFFH 16 FFF Signal descriptions Table 87 shows the interface signals of the core VHDL ports Table 87 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock VGACLK N A Input VGA Clock APBI X Input APB slave input signals APBO Output APB slave output signals VGAO HSYNC Output Horizontal synchronization High VSYNC Vertical synchronization High COMP_SYNC Composite synchronization Low BLANK Blanking Low VIDEO_OUT_R 7 0 V
323. command 01 PRECHARGE 10 AUTO REFRESH 11 LOAD COMMAND REGISTER The field is reset after command has been executed SDRAM column size 00 256 01 512 10 1024 11 4096 when bit 25 23 111 2048 otherwise SDRAM banks size Defines the banks size for SDRAM chip selects 000 4 Mbyte 001 8 Mbyte 010 16 Mbyte 111 512 Mbyte SDRAM CAS delay Selects 2 or 3 cycle CAS delay 0 1 When changed a LOAD COMMAND REGISTER command must be issued at the same time Also sets RAS CAS delay tRCD SDRAM tpgc timing tare will be equal to 3 field value system clocks SDRAM tpp timing tgp will be equal to 2 or 3 system clocks 0 1 SDRAM refresh If set the SDRAM refresh will be enabled Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x009 For description of vendor and device identifiers see GRLIB IP Library User s Manual 454 55 5 Configuration options Table 452 shows the configuration options of the core VHDL generics Table 452 Configuration options high Generic Function Allowed range Default hindex AHB slave index 1 NAHBSLV 1 0 haddr ADDR filed of the AHB BARO defining SDRAM area Default 0 16 FFF 16 000 is 0xF0000000 OxXFFFFFFFF hmask MASK filed of the AHB BARO defining SDRAM area 0 16 FFFH 16 FOO ioaddr ADDR filed of the
324. compliant mode Following floating point trap types never occur and are therefore never set in the ftt field unimplemented_FPop all FPop operations are implemented unfinished_FPop all FPop operation complete with valid result invalid_fp_register no check that double precision register is O mod 2 is performed The controller implements the qne bit of the FSR register which reads 0 if the floating point deferred queue FQ is empty and 1 otherwise The FSR is accessed using LDFSR and STFSR instructions Floating Point Exceptions and Floating Point Deferred Queue Floating point unit implements SPARC deferred trap model for floating point exceptions fp_exception A floating point exception is caused by a floating point instruction performing an operation resulting in one of following conditions e an operation raises IEEE floating point exception ftt IEEE_754_exception e g executing invalid operation such as 0 0 while the NVM bit of the TEM field id set invalid exception enabled e sequence error abnormal error condition in the FPU due to the erroneous use of the floating point instructions in the supervisor software e hardware_error uncorrectable parity error is detected in the FP register file The trap is deferred to the next floating point instruction FPop FP load store FP branch following the trap inducing instruction When the trap is taken the floating point deferred queue FQ contains the trap inducing instr
325. connected to the AHB status register which stores information of the AHB instruction causing the error and also generates interrupts See the AHB status register documentation for more information The EDAC function can only be enabled for SRAM area accesses If an 16 bit or 32 bit bus access is performed the memory controller calculates the EDAC checksum for each byte read from the mem ory but the indication of single error is only signaled when the access is done 1 e if more then one byte in an 32 bit access has an single error only one error is indicated for the hole 32 bit access 30 2 1 Memory access The memory controller supports 32 16 8 bit single accesses and 32 bit burst accesses to SRAM An 32 bit or a 16 bit access is performed as multiple 8 bit accesses on the 16 bit memory bus where data is transferred on data lines 8 to 15 Data 15 8 The eight checkbits generated used by the EDAC is transferred on the eight first data lines Data 7 0 For 32 bit and 16 bit accesses the bytes read from the memory is arranged according to the big endian order i e for an 32 bit read access the bytes read from memory address A A 1 A 2 and A 3 corresponds to the bit 31 24 bit 23 16 bit 15 8 and bit 7 0 in the 32 bit word transferred to the AMBA bus 30 2 2 I O access The memory controller accepts 32 16 8 bit single accesses to the I O area but the access generated towards the I O device is always 16 bit The two least significant
326. contains an AMBA bus with a number of AHB components connected to it including the status register There are three Fault Tolerant units with EDAC connected to the status register cerror vector The connection of the different memory controllers to external memory is not shown library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler misc all entity mctrl_ex is port clk in std_ulogic rstn in std_ulogic other signals i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect memory controller and memory bus signal memi memory_in_type signal memo memory_out_type signal sdo sdo2 sdctrl_out_type signal sdi sdctrl_in_type correctable error vector signal stati ahbstat_in_type signal aramo ahbram_out_type begin AMBA Components are defined here AHB Status Register astat0 ahbstat generic map pindex gt 13 paddr gt 13 pirq gt 11 nftslv gt 3 port map rstn clkm ahbmi ahbsi stati apbi apbo 13 stati cerror 3 to NAHBSLV 1 lt others gt 0
327. criptor at address offset 0x3F8 has been used The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register It should never be touched when reception is active The final step to activate reception is to set the receiver enable bit in the control register This will make the GRETH_GBIT read the first descriptor and wait for an incoming packet 35 4 3 Descriptor handling after reception The GRETH indicates a completed reception by clearing the descriptor enable bit The other control bits WR IE are also cleared The number of received bytes is shown in the length field The parts of the Ethernet frame stored are the destination address source address type and data fields Bits 24 14 in the first descriptor word are status bits indicating different receive errors Bits 18 14 are zero after a reception without link layer errors The status bits are described in figure 124 except the checksum offload bits which are also described in section 35 4 5 Packets arriving that are smaller than the minimum Ethernet size of 64 B are not considered as a reception and are discarded The current receive descriptor will be left untouched an used for the first packet arriving with an accepted size The TS bit in the status register is set each time this event occurs If
328. cted devices Registers The core has 32 bit wide registers mapped into the AHB address space with an offset shown in table 89 The registers in the ATA device are also mapped into the AHB address space starting with an off set of 0x40 see table 93 Data bits 7 0 are used for accessing the 8 bit registers in the ATA device and bits 15 0 are used for accessing the 16 bit data register in the ATA device Table 89 Core Registers Name Offset CTRL 0x00 Control register STAT 0x04 Status register PCTR 0x08 PIO compatible timing register PFTRO 0x0c PIO fast timing register device 0 PFTR1 0x10 PIO fast timing register device 1 DTRO 0x14 Reserved for DMA timing register device 0 DTR1 0x18 Reserved for DMA timing register device 1 All the core registers can be read from and written to by any master on the AHB bus The Control register has the following bit layout see table 90 Table 90 Control Register Bit Description 31 CompactFlash power on switch 30 16 Reserved 15 Reserved DMA enable 14 Reserved 13 Reserved DMA direction 12 10 Reserved 9 Reserved Big Endian Little Endian conversion device 1 8 Reserved Big Endian Little Endian conversion device 0 7 IDE enable 6 Fast timing device 1 enable 5 Fast timing device 0 enable 4 Reserved PIO write ping pong enable 3 Fast timing device 1 IORDY enable 2 Fast tim
329. ction The main interrupts are the Rx RxFull and RxIrq which are issued on the successful reception of a mes sage when the message buffer has been successfully filled and when a predefined number of mes sages have been received successfully The RxMiss interrupt is issued whenever a message has been received but does not match a message filtering setting i e neither for the receive channel nor for the SYNC message described hereafter 146 The RxSync interrupt is issued when a message matching the SYNC Code Filter Register SYNC and SYNC Mask Filter Register MASK registers has been successfully received Additional interrupts are provided to signal error conditions on the CAN bus and AMBA bus 22 6 5 Straight buffer It is possible to use the circular buffer as a straight buffer with a higher granularity than the 1kbyte address boundary limited by the base address CanRxADDR ADDR field While the channel is disabled the write pointer CanRxWR WRITE can be changed to an arbitrary value pointing to the first message to be received and the read pointer CanRxRD READ can be changed to an arbitrary value When the channel is enabled the reception will start from the write pointer and continue to the read pointer 22 6 6 AMBA AHB error An AHB error response occurring on the AMBA AHB bus while a CAN message is being stored will result in an RxAHBErr interrupt If the CanCONF ABORT bit is set to Ob the channel causing the AHB error will
330. ctive transmissions including the character cur rently being shifted out from the transmitter shift register The transmitter holding register may not be loaded when the transmitter is disabled or when the FIFO or holding register is full If this is done data might be overwritten and one or more frames are lost The discussion above applies to any FIFO configurations including the special case with a holding register VHDL generic fifosize 1 If FIFOs are used VHDL generic fifosize gt 1 some additional status and control bits are available The TF status bit not to be confused with the TF control bit is set if the transmitter FIFO is currently full and the TH bit is set as long as the FIFO is less than half full less than half of entries in the FIFO contain data The TF control bit enables FIFO interrupts when set The status register also contains a counter TCNT showing the current number of data entries in the FIFO When flow control is enabled the CTSN input must be low in order for the character to be transmit ted If it is deasserted in the middle of a transmission the character in the shift register is transmitted and the transmitter serial output then remains inactive until CTSN is asserted again If the CTSN is connected to a receivers RTSN overrun can effectively be prevented 15 2 2 Receiver operation The receiver is enabled for data reception through the receiver enable RE bit in the UART control register The recei
331. d Figure 142 SpaceWire Transmitter descriptor Address offsets are shown in the left margin 42 5 5 The transmissions process When the txen bit is set the GRSPW starts reading descriptors immediately The number of bytes indi cated are read and transmitted When a transmission has finished status will be written to the first field of the descriptor and a packet sent bit is set in the DMA control register If an interrupt was requested it will also be generated Then a new descriptor is read and if enabled a new transmission starts otherwise the transmit enable bit is cleared and nothing will happen until it is enabled again 42 5 6 The descriptor table address register The internal pointer which is used to keep the current position in the descriptor table can be read and written through the APB interface This pointer is set to zero during reset and is incremented each time a descriptor is used It wraps automatically when the 1 kbytes limit for the descriptor table is reached or it can be set to wrap earlier by setting a bit in the current descriptor 328 42 6 The descriptor table register can be updated with a new table anytime when no transmission is active No transmission is active if the transmit enable bit is zero and the complete table has been sent or if the table is aborted explained below If the table is aborted one has to wait until the transmit enable bit is zero before updating the table pointer 42 5 7 Error handling
332. d on errors or when the interface has completed the list Registers The core is programmed through registers mapped into APB address space The internal registers of Core1553BBC are mapped on the eight lowest APB addresses These addresses are 32 bit word aligned although only the lowest 16 bits are used Refer to the Actel Corel 553BBC MIL STD 1553B Bus Controller data sheet for detailed information Table 97 B1553BC registers APB address offset Register 0x00 Control Status 0x04 Setup 0x08 List pointer 0x0C Message pointer 0x10 Clock value 0x14 Asynchronous list pointer 0x18 Stack pointer Ox1C Interrupt register 0x20 GR1553 status control 0x24 AHB page address register Table 98 GR1553 status register read 31 3 2 1 0 RESERVED extflag memfail busy 31 3 RESERVED 2 External flag bit Drives the extflag input of the Core1553BBC Resets to zero Memory failure Shows the value of the memfail output from Core1553BBC 0 Busy Shows the value of the busy output from Core1553BBC 18 5 18 6 Table 99 GR1553 status register write 103 31 1 0 RESERVED extflag 31 2 RESERVED 0 External flag bit Drives the extflag input of the Core1553BBC Resets to zero Table 100 GR1553 status register write 31 17 16 0 ahbaddr RESERVED 31 17 Holds the 15 top most bits of the AHB address of the allocated memory area 16 0 RESERVED
333. d Invalidate Handled similarly 50 4 429 The target interface supports incremental bursts for PCI memory cycles The target interface can finish a PCI transaction with one of the following abnormal responses Retry This response indicates that the master should perform the same request later while the target is temporarily busy This response is always given at least one time for read accesses but can also occur for write accesses Disconnect with data Indicates that the target will accept one more data transaction but no more This occurs if the master tries to read more data than the target has prefetched Disconnect without data Indicates that the target is unable to accept more data This occurs if the master tries to write more data than the target can buffer Target Abort Indicates that the current access caused an internal error and the target never will be able to finish it Targets AHB master interface is capable of burst transactions Burst transactions are performed on the AHB when supported by the destination unit AHB slave otherwise multiple single access are per formed A PCI burst crossing 1 kB address boundary will be performed as multiple AHB bursts by the AHB master interface The AHB master interface will insert an idle cycle before requesting a new AHB burst to allow re arbitration on the AHB AHB transactions with retry response are repeated by the AHB master until okey or error response is
334. d LOAD MODE REG LMR If the LMR command is issued the CAS delay as programmed in SDCFG will be used remaining fields are fixed page read burst single location write sequential burst The command field will be cleared after a command has been executed Note that when changing the value of the CAS delay a LOAD MODE REGISTER command should be generated at the same time 28 2 6 Read cycles A read cycle is started by performing an ACTIVATE command to the desired bank and row followed by a READ command after the programmed CAS delay A read burst is performed if a burst access has been requested on the AHB bus The read cycle is terminated with a PRE CHARGE command no banks are left open between two accesses Note that only word bursts are supported by the SDRAM controller The AHB bus supports bursts of different sizes such as bytes and halfwords but they cannot be used 28 2 7 Write cycles Write cycles are performed similarly to read cycles with the difference that WRITE commands are issued after activation A write burst on the AHB bus will generate a burst of write commands without idle cycles in between As in the read case only word bursts are supported 28 2 8 Address bus connection The SDRAM address bus should be connected to SA 12 0 the bank address to SA 14 13 and the data bus to SD 31 0 or SD 63 0 if 64 bit data bus is used 28 3 213 28 2 9 Data bus Data bus width is configurable to 32 or 64 bits 64 bit data bu
335. d accesses as well as all types of AHB burst accesses Internally the AHBRAM instantiates four 8 bit wide SYNCRAM blocks Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier OxOOE For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 33 shows the configuration options of the core VHDL generics Table 33 Configuration options Generic Function Allowed range Default hindex AHB slave bus index 0 NAHBSLV 1 0 haddr The MSB address of the AHB area Sets the 12 most sig 0 16 FFF 16 FFFH nificant bits in the 32 bit AHB address hmask The AHB area address mask Sets the size of the AHB 0 16 FFFH 16 FFO area and the start address together with haddr tech Technology to implement on chip RAM 0 NTECH 0 kbytes RAM size in Kbytes target dependent 1 Signal descriptions Table 34 shows the interface signals of the core VHDL ports Table 34 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBSI i Input AMB slave input signals AHBSO Output AHB slave output signals see GRLIB IP Library User s Manual Library dependencies Table 35 shows libraries used when instantiating the core VHDL libraries Table 35 Library dependencies Library Package Imported unit s Descripti
336. d bit for each 4 byte sub block and optional LRR and lock bits On an instruction cache miss to a cachable location the instruction is fetched and the corresponding tag and data line updated In a multi set configuration a line to be replaced is chosen according to the replacement pol icy If instruction burst fetch is enabled in the cache control register CCR the cache line is filled from main memory starting at the missed address and until the end of the line At the same time the instructions are forwarded to the IU streaming If the IU cannot accept the streamed instructions due to internal dependencies or multi cycle instruction the IU is halted until the line fill is completed If the IU executes a control transfer instruction branch CALL JMPL RETT TRAP during the line fill the line fill will be terminated on the next fetch If instruction burst fetch is enabled instruction streaming is enabled even when the cache is disabled In this case the fetched instructions are only forwarded to the IU and the cache is not updated During cache line refill incremental burst are gener ated on the AHB bus If a memory access error occurs during a line fill with the IU halted the corresponding valid bit in the cache tag will not be set If the IU later fetches an instruction from the failed address a cache miss will occur triggering a new access to the failed address If the error remains an instruction access error trap tt 0x1 will be generat
337. d for this core 0 1 txd Pointer to the transmitter descriptor table rxd Pointer to the receiver descriptor table The following functions are available in the basic API int spw_setparam int nodeaddr int clkdiv int destkey int nospill int timetxen int timerxen int rxmaxlen int spwadr struct spwvars spw Used for setting the different parameters in the spwvars struct Should always be run first after creat ing a spwvars struct This function only initializes the struct Does not write anything to the SpaceWire core Table 348 Return values for spw_setparam Value Description 0 The function completed successfully 1 One or more of the parameters had an illegal value 352 Table 349 Parameters for spw_setparam Parameter Description Allowed range nodeaddr Sets the node address value of the struct spw passed to the function 0 255 clkdiv Sets the clock divisor value of the struct spw passed to the function 0 255 destkey Sets the destination key of the struct spw passed to the function 0 255 nospill Sets the nospill value of the struct spw passed to the function 0 1 timetxen Sets the timetxen value of the struct spw passed to the function 0 1 timerxen Sets the timerxen value of the struct spw passed to the function 0 1 rxmaxlen Sets the receiver maximum length field of the struct spw passed to 0 225 1 the function spwadr Sets the address to the GRSPW
338. d from the header pointer and the data CRC is generated from data fetched from the data pointer The CRCs are appended after the corresponding fields The NON CRC bytes field is set to the number of bytes in the beginning of the header field that should not be included in the CRC calculation The CRC is skipped if the corresponding field is zero If both fields are zero nothing will be sent not even an EOP 42 5 4 Starting transmissions When the descriptors have been initialized the transmit enable bit in the DMA control register has to be set to tell the GRSPW to start transmitting New descriptors can be activated in the table on the fly while transmission is active Each time a set of descriptors is added the transmit enable register bit 327 should be set This has to be done because each time the GRSPW encounters a disabled descriptor this register bit is set to 0 31 16 15 14 13 12 11 8 7 0 0x0 cc LE IE WR EN NON CRC BYTES HEADER LENGTH 31 0 0x4 HEADER ADDRESS 31 24 23 0 0x8 DATA LENGTH 31 0 0xC DATA ADDRESS 7 0 Header Length Header Length in bytes If set to zero the header is skipped 11 8 Non CRC bytes Sets the number of bytes in the beginning of the header which should not be included in the CRC calculation This is necessary when using path addressing since one or more bytes in the beginning of the packet might be discarded before the packet reaches its dest
339. d that the boot code for the processor writes all registers in the IU and FPU register files before launching the main application The check bits in the cache memories do not need to be initialized as this is done automatically during cache line filling Vendor and device identifers The core has vendor identifers 0x01 Gaisler Research and device identifers 0x053 For description of vendor and device identiferss see GRLIB IP Library User s Manual Configuration options In addition to the configuration of the standard LEON3 processor the LEON3FT processor has the following configuartion options Table 408 shows the configuration options of the core VHDL generics Table 408 Configuration options Generic Function Range Default iuft fpft Register file SEU protection 0 no protection 1 4 bit parity 2 0 3 0 8 bit parity 3 7 bit BCH cft Enable cache memory SEU protection 0 1 ceinj Error injection Used for simulation only 0 3 Limitations The LEON3FT core does not support the following functions present in the LEON3 model Local scratch pad RAM Data cache snooping with MMU enabled 46 46 1 46 2 397 LOGAN On chip Logic Analyzer Introduction The LOGAN core implements an on chip logic analyzer for tracing and displaying of on chip signals LOGAN consists of a circular trace buffer and a triggering module When armed the logic analyzers stores the traced signals in the c
340. default the execution will start from address 0 This can be overridden by setting the RSTADDR generic in the model to a non zero value The reset address is always aligned on a 4 kbyte boundary 44 2 15 Multi processor support The LEON3 processor support synchronous multi processing SMP configurations with up to 16 processors attached to the same AHB bus In multi processor systems only the first processor will start All other processors will remain halted in power down mode After the system has been initial ized the remaining processors can be started by writing to the MP status register located in the multi processor interrupt controller The halted processors start executing from the reset address 0 or RSTADDR generic Enabling SMP is done by setting the smp generic to 1 or higher Cache snooping should always be enabled in SMP systems to maintain data cache coherency between the processors 44 3 377 44 2 16 Cache sub system The LEON3 processor implements a Harvard architecture with separate instruction and data buses connected to two independent cache controllers Both instruction and data cache controllers can be separately configured to implement a direct mapped cache or a multi set cache with set associativity of 2 4 The set size is configurable to 1 256 kbyte divided into cache lines with 16 or 32 bytes of data In multi set configurations one of three replacement policies can be selected least recently used
341. dency is the integer pipeline held The GRFPU is fully pipelined and allows the start of one instruction each clock cycle with the exception is FDIV and FSQRT which can only be executed one at a time The FDIV and FSQRT are however executed in a separate divide unit and do not block the FPU from performing all other operations in parallel All instructions except FDIV and FSQRT has a latency of three cycles but to improve timing the LEON3 FPU controller inserts an extra pipeline stage in the result forwarding path This results in a 384 latency of four clock cycles at instruction level The table below shows the GRFPU instruction timing when used together with GRFPC Table 399 GRFPU instruction timing with GRFPC Instruction Throughput Latency FADDS FADDD FSUBS FSUBD FMULS FMULD FSMULD FITOS FITOD FSTOI FDTOL FSTOD FDTOS FCMPS FCMPD FCMPES FCMPED 1 4 FDIVS 14 16 FDIVD 15 17 FSQRTS 22 24 FSQRTD 23 25 The GRFPC controller implements the SPARC deferred trap model and the FPU trap queue FQ can contain up to three queued instructions when an FPU exception is taken When the GRFPU is enabled in the model the version field in fsr has the value of 2 44 7 2 GRFPU Lite GRFPU Lite is a smaller version of GRFPU suitable for FPGA implementations with limited logic resources The GRFPU Lite is not pipelined and executes thus only one instruction at a time To improve performance the FPU cont
342. dered as a reception and are discarded The current receive descriptor will be left untouched an used for the first packet arriving with an accepted size The TS bit in the status register is set each time this event occurs If a packet is received with an address not accepted by the MAC the IA status register bit will be set Packets larger than maximum size cause the FT bit in the receive descriptor to be set The length field is not guaranteed to hold the correct value of received bytes The counting stops after the word con taining the last byte up to the maximum size limit has been written to memory The address word of the descriptor is never touched by the GRETH 34 4 4 Reception with AHB errors If an AHB error occurs during a descriptor read or data store the Receiver AHB Error RA bit in the status register will be set and the receiver is disabled The current reception is aborted The receiver can be enabled again by setting the Receive Enable bit in the control register MDIO Interface The MDIO interface provides access to PHY configuration and status registers through a two wire interface which is included in the MII interface The GRETH provided full support for the MDIO interface If it is not needed in a design it can be removed with a VHDL generic The MDIO interface can be used to access from 1 to 32 PHY containing 1 to 32 16 bit registers A read transfer i set up by writing the PHY and register addresses to the MDIO Con
343. derflows the result is flushed to zero GRFPU does not support denormalized numbers or gradual underflow A special Unfinished exception UNF is signaled when one of the operands is a denormalized number which are not handled by the arithmetic and conversion operations 37 2 4 Rounding All four rounding modes defined in the IEEE 754 standard are supported round to nearest round to inf round to inf and round to zero 37 2 5 Denormalized numbers Denormalized numbers are not handled by the GRFPU arithmetic and conversion operations A sys tem microprocessor with the GRFPU could emulate rare cases of operations on denormals in soft ware using non FPU operations A special Unfinished exception UNF is used to signal an arithmetic or conversion operation on the denormalized numbers Compare move negate and absolute value operations can handle denormalized numbers and don t raise unfinished exception GRFPU does not generate any denormalized numbers during arithmetic and conversion operations on normalized num bers If infinitely precise result of an operation is a tiny number smaller than minimum value repre sentable in normal format the result is flushed to zero with underflow and inexact flags set 304 37 2 6 Non standard Mode GRFPU can operate in a non standard mode where all denormalized operands to arithmetic and con version operations are treated as correctly signed zeroes Calculations are performed on zero oper an
344. desired bank and row followed by a READ command after the programmed CAS delay A read burst is performed if a burst access has been requested on the AHB bus The read cycle is terminated with a PRE CHARGE command no banks are left open between two accesses 194 27 10 27 9 3 Write cycles Write cycles are performed similarly to read cycles with the difference that WRITE commands are issued after activation A write burst on the AHB bus will generate a burst of write commands without idle cycles in between 27 9 4 Address bus The memory controller can be configured to either share the address and data buses with the SRAM or to use separate address and data buses When the buses are shared the address bus of the SDRAMs should be connected to A 14 2 the bank address to A 16 15 The MSB part of A 14 2 can be left unconnected if not used When separate buses are used the SDRAM address bus should be connected to SA 12 0 and the bank address to SA 14 13 27 9 5 Data bus SDRAM can be connected to the memory controller through the common or separate data bus If the separate bus is used the width is configurable to 32 or 64 bits 64 bit data bus allows the 64 bit SDRAM devices to be connected using the full data capacity of the devices 64 bit SDRAM devices can be connected to 32 bit data bus if 64 bit data bus is not available but in this case only half the full data capacity will be used There is a drive signal vector and separate dat
345. devices asyn chronous static ram SRAM and synchronous dynamic ram SDRAM The controller acts as a slave on the AHB bus The function of the memory controller is programmed through memory configura tion registers 1 2 amp 3 MCFG1 MCFG2 amp MCFG3 through the APB bus The memory bus supports four types of devices prom sram sdram and local I O The memory bus can also be configured in 8 or 16 bit mode for applications with low memory and performance demands Chip select decoding is done for two PROM banks one I O bank five SRAM banks and two SDRAM banks The controller decodes three address spaces PROM I O and RAM whose mapping is determined through VHDL generics Figure 184 shows how the connection to the different device types is made MEMO ROMSN 1 0 MEMO OEN MEMO WRITEN MEMO IOSN MEMORY CONTROLLER MEMO RAMSNI4 0 gt cs MEMO RAMOEN 4 0 OE w MEMO RWENI3 0 MEMO MBEN 3 0 MEMO SDCLK gt CLK MEMO SDCSN 1 0 E CSN MEMO SDRASN Y RAS MEMO SDCASN Y CAS WE MEMO SDWEN MEMO SDDQMI3 0 MEMLA 27 0 MEMI D 31 0 MEMO D 31 0 Figure 184 Memory controller conected to AMBA bus and different types of memory devices 47 2 PROM access Accesses to prom have the same timing as RAM accesses the differences being that PROM cycles can have up to 15 waitstates 405 datai data2 lead out datai data2 lead out ore Cor IX X a ee it Ne ae O A A y ie data pa cb CB1 CB2 Y Figure
346. diately and not first when entering operating mode The bus off recovery sequence starts when entering operating mode after writing 255 to this register in reset mode 130 21 5 12 Transmit buffer The transmit buffer is write only and mapped on address 16 to 28 Reading of this area is mapped to the receive buffer described in the next section The layout of the transmit buffer depends on whether a standard frame SFF or an extended frame EFF is to be sent as seen below Table 129 Write SFF Write EFF 16 TX frame information TX frame information 17 TXID1 TXID1 18 TXID2 TX ID 2 19 TX data 1 TX ID 3 20 TX data 2 TX ID 4 21 TX data 3 TX data 1 22 TX data 4 TX data 2 23 TX data 5 TX data 3 24 TX data 6 TX data 4 25 TX data 7 TX data 5 26 TX data 8 TX data 6 27 TX data 7 28 TX data 8 TX frame information this field has the same layout for both SFF and EFF frames Table 130 TX frame information address 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FF RTR DLC 3 DLC 2 DLC 1 DLC 0 Bit7 FF selects the frame format i e whether this is to be interpreted as an extended or standard frame 1 EFF 0 SFF Bit6 RTR should be set to 1 for an remote transmission request frame Bit 5 4 are don t care Bit 3 0 DLC specifies the Data Length Code and should be a value between 0 and 8 If a value greater than 8
347. disable bit can be set to force the command handler to only use one buffer which prevents this situation The last control option for the command handler is the possibility to set the destination key which is found in a separate register 331 Table 333 GRSPW hardware RMAP handling of different packet type and command fields gle address do not verify before writ ing send acknowledge Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Command Action Verify data Command Write before Acknow Increment Reserved Response Read write ledge Address 0 0 Response Stored to DMA channel 0 1 0 0 0 0 Not used Does nothing No reply is sent 0 1 0 0 0 1 Not used Does nothing No reply is sent 0 1 0 0 1 0 Read single Executed normally Address has address to be word aligned and data size a multiple of four Reply is sent If alignment restrictions are vio lated error code is set to 10 0 1 0 0 1 1 Read incre Executed normally No restric menting tions Reply is sent address 1 1 0 Not used Does nothing No reply is sent 1 1 1 Not used Does nothing No reply is sent 1 1 1 0 Not used Does nothing Reply is sent with error code 2 0 1 0 1 1 1 Read Mod Executed normally If length is ify Write not one of the allowed rmw val increment ues nothing is done and error ing address code is set to 11 If the length was correct alignment restric ti
348. dress space 0 16 FFF 16 000 Default PROM area is 0x0 Ox 1FFFFFFF rommask MASK filed of the AHB BARO defining PROM address space 0 16 FFF 16 E00 ioaddr ADDR filed of the AHB BARI defining I O address space 0 16 FFFH 16 200 Default I O area is 0x20000000 0x2FFFFFFE iomask MASK filed of the AHB BAR1 defining I O address space 0 16 FFFH 16 E00 ramaddr ADDR filed of the AHB BAR2 defining RAM address space 0 16 FFF 16 400 Default RAM area is 0x40000000 0x7FFFFFFF rammask MASK filed of the AHB BAR2 defining RAM address space 0 16 FFF 16 C00 paddr ADDR filed of the APB BAR configuration registers address 0 16 FFF 0 space pmask MASK filed of the APB BAR configuration registers address 0 16 FFFH 16 FFFH space wprot RAM write protection 0 1 invelk Inverted clock is used for the SDRAM 0 1 fast Enable fast SDRAM address decoding 0 1 romasel log2 PROM address space size 1 E g if size of the PROM 0 31 28 area is 0x20000000 romasel is log2 2 29 1 28 sdrasel log2 RAM address space size 1 E g if size of the RAM 0 31 29 address space is 0x40000000 sdrasel is log2 2 30 1 29 srbanks Number of SRAM banks 0 5 4 ram8 Enable 8 bit PROM and SRAM access 0 1 0 raml6 Enable 16 bit PROM and SRAM access 0 1 0 sden Enable SDRAM controller 0 1 0 sepbus SDRAM is located on separate bus 0 1 1 sdbits 32 or 64 bit SDRAM data bus 32 64 32 oepol Select polarity of drive signals for data pads 0 ac
349. ds instead of the denormalized numbers obeying all rules of the floating point arithmetics including rounding of the results and detecting exceptions 37 2 7 NaNs GRFPU supports handling of Not a Numbers NaNs as defined in the IEEE 754 standard Opera tions on signaling NaNs SNaNs and invalid operations e g inf inf generate Invalid exception and deliver QNaN_GEN as result Operations on Quiet NaNs QNaNs except for FCMPES and FCMPED do not raise any exceptions and propagate QNaNs through the FP operations by delivering NaN results according to table 318 QNaN_GEN is 0x7fffe00000000000 for double precision results and Ox7fff0000 for single precision results Table 318 Operations on NaNs Operand 2 FP QNaN2 SNaN2 none FP QNaN2 QNaN_GEN Operand 1 FP FP QNaN2 QNaN_GEN QNaN1 QNaN1 QNaN2 QNaN_GEN SNaNl QNaN_GEN QNaN_GEN QNaN_GEN 37 3 37 4 305 Signal descriptions Table 319 shows the interface signals of the core VHDL ports All signals are active high except for RST which is active low Table 319 Signal descriptions Signal VO Description CLK I Clock RST I Reset START I Start an FP operation on the next rising clock edge NONSTD I Nonstandard mode Denormalized operands are converted to zero OPCODE 8 0 I FP operation For codes see table 316 OPID 5 0 I FP operation id Every operation is associated with an id which will appear on the RESID output
350. e out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data i end architecture rtl of srctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect memory controller and memory bus signal memi memory_in_ type signal memo memory_out_type signal sdo sdctrl_out_type signal wprot wprot_out_type dummy signal not used signal clkm rstn std_ulogic system clock and reset signals used by clock and reset generators 464 signal cgi clkgen_in_type signal cgo clkgen_out_type signal gnd std_ulogic begin AMBA Components are defined here Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 clk_div gt 2 sdramen gt 1 tech gt virtex2 sdinvclk gt 0 port map clk gnd clkm open op
351. e 0 usbo opmode 0 usb_opmode 1 usbo opmode 1 usb_txvalid usbo txvalid r tech gt padtech port map usb_clkout uclk memtech gt memtech sbo clk m rstn ahbmi ahbmo 0 Information furnished by Gaisler Research is believed to be accurate and reliable However no responsibility is assumed by Gaisler Research for its use nor for any infringements of patents or other rights of third parties which may result from its use No license is granted by implication or otherwise under any patent or patent rights of Gaisler Research Gaisler Research AB tel 46 31 7758650 Forsta Langgatan 19 fax 46 31 421407 y L 413 27 Goteborg sales gaisler com IAH Sweden www gaisler com GAISLER RESEARCH Copyright 2006 Gaisler Research AB All information is provided as is There is no warranty that it is correct or suitable for any purpose neither implicit nor explicit
352. e GPIOO VAL signals The output enable is controlled by the I O port direction register A 1 in a bit position will enable the output buffer for the corresponding I O line The output value driven is taken from the I O port output register Each I O port can drive a separate interrupt line on the APB interrupt bus The interrupt number is equal to the T O line index PIO 1 interrupt 1 etc The interrupt generation is controlled by three registers interrupt mask polarity and edge registers To enable an interrupt the corresponding bit in the interrupt mask register must be set If the edge register is 0 the interrupt is treated as level sensi tive If the polarity register is 0 the interrupt is active low If the polarity register is 1 the interrupt is active high If the edge register is 1 the interrupt is edge triggered The polarity register then selects between rising edge 1 or falling edge 0 Registers The core is programmed through registers mapped into APB address space 315 Table 322 General Purpose 1 O Port registers APB address offset Register 0x00 T O port data register 0x04 T O port output register 0x08 T O port direction register 0x0C Interrupt mask register 0x10 Interrupt polarity register 0x14 Interrupt edge register Table 323 I O port data register 31 16 16 1 0 000 0 I O port input value 16 1 0 T O port inp
353. e GRETH_GBIT supports the Media Independent Interface MII and the Gigabit Media Independent Interface GMII The GMII is used in 1000 Mbit mode and the MII in 10 and 100 Mbit These interfaces are defined separately in the 802 3 2002 standard but in practice they share most of the signals The GMII has 9 additional signals compared to the MII Four data signals are added to the receiver and transmitter data interfaces respectively and a new transmit clock for the gigabit mode is also introduced Table 308 Signals in GMII and MII MII and GMII GMII Only txd 3 0 txd 7 4 tx_en rxd 7 4 tx_er gtx_clk rx_col rx_crs rxd 3 0 rx_clk rx_er rx_dv 292 35 8 Registers The core is programmed through registers mapped into APB address space Table 309 GRETH_GBIT registers 0x0 APB address offset Register Control register 0x4 Status Interrupt source register 0x8 MAC Address MSB OxC MAC Address LSB 0x10 MDIO Control Status 0x14 Transmit descriptor pointer 0x18 Receiver descriptor pointer 0x1C EDCL IP 31 30 28 27 9 8 7 6 5 4 3 2 10 ED BS GA RESERVED BM GBI SP RS PR FD RI TI RE TE DTi 30 28 31 Figure 125 GRETH_GBIT control register Transmit Enable TE Should be written with a one each time new descriptors are enabled As long as this bit is one th
354. e 0 to 1 0 support fix length bursts 2 debug integer range 0 to 2 fpnpen integer range 0 to 1 0 icheck integer range 0 to 1 1 i port rst in std_ulogic clk in std_ulogic msti out ahb_mst_in_type msto in ahb_mst_out_vector slvi out ahb_slv_in_type slvo in ahb_slv_out_vector i end component Instantiation print configuration to consolee full PnP configuration decoding This examples shows the core can be instantiated 4 11 33 library ieee use ieee std_logic_1164 all library grlib use grlib amba all AMBA signal signal ahbsi ahb_slv_in type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in type signal ahbmo ahb_mst_out_vector others gt ahbm_none begin ARBITER ahb0 ahbctrl AHB arbiter multiplexer generic map defmast gt CFG_DEFMST split gt CFG_SPLIT rrobin gt CFG_RROBIN ioaddr gt CFG_AHBIO nahbm gt 8 nahbs gt 8 port map rstn clkm ahbmi ahbmo ahbsi ahbso AHB slave sr0 srctrl generic map hindex gt 3 port map rstn clkm ahbsi ahbso 3 memi memo sdo3 AHB master el eth_oc generic map mstndx gt 2 slvndx gt 5 ioaddr gt CFG_ETHIO irq gt 12 memtech gt memtech port map rstn clkm ahbsi ahbso 5 ahbmi gt ahbmi ahbmo gt ahbmo 2 ethil ethol end Debug print out If the debug generic is set to 2 the plug amp play
355. e 1 will never be seen in a read reply since the header has already been sent when the data is read If the AHB error occurs the packet will be truncated and ended with an EFP The details of the support for the different commands are now presented All defined commands which are received but have an option set which is not supported in this specific implementation will not be executed and a possible reply is sent with error code 10 42 6 3 Write commands The write commands are divided into two subcategories when examining their capabilities verified writes and non verified writes Verified writes have a length restriction of 4 B and the address must be aligned to the size That is 1 B writes can be done to any address 2 B must be halfword aligned 3 B are not allowed and 4 B writes must be word aligned Since there will always be only on AHB opera tion performed for each RMAP verified write command the incrementing address bit can be set to any value Non verified writes have no restrictions when the incrementing bit is set to 1 If it is set to O the num ber of bytes must be a multiple of 4 and the address word aligned There is no guarantee how many words will be written when early EOP EEP is detected for non verified writes 42 6 4 Read commands Read commands are performed on the fly when the reply is sent Thus if an AHB error occurs the packet will be truncated and ended with an EEP There are no restrictions for incrementing reads but
356. e 6 18 TX data 7 TX byte 7 19 TX data 8 TX byte 8 If the RTR bit is set no data bytes will be sent but DLC is still part of the frame and must be specified according to the requested frame Note that it is possible to specify a DLC larger than 8 bytes but should not be done for compatibility reasons If DLC gt 8 still only 8 bytes can be sent 21 4 7 Receive buffer The receive buffer on address 20 through 29 is the visible part of the 64 byte RX FIFO Its layout is identical to that of the transmit buffer 21 4 8 Acceptance filter Messages can be filtered based on their identifiers using the acceptance code and acceptance mask registers The top 8 bits of the 11 bit identifier are compared with the acceptance code register only comparing the bits set to zero in the acceptance mask register If a match is detected the message is stored to the fifo 125 21 5 PeliCAN mode 21 5 1 PeliCAN register map Table 119 PeliCAN address allocation Operating mode Reset mode Read Write Read Write 0 Mode Mode Mode Mode 1 0x00 Command 0x00 Command 2 Status Status 3 Interrupt Interrupt 4 Interrupt enable Interrupt enable Interrupt enable Interrupt enable 5 reserved 0x00 reserved 0x00 6 Bus timing 0 Bus timing 0 Bus timing 0 7 Bus timing 1 Bus timing 1 Bus timing 1 8 0x00 0x00 9 0x0
357. e GRETH_GBIT will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again This bit should be written with a one after the new descriptors have been enabled Reset value 0 Receive Enable RE Should be written with a one each time new descriptors are enabled As long as this bit is one the GRETH_GBIT will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again This bit should be written with a one after the new descriptors have been enabled Reset value 0 Transmitter Interrupt TI Enable Transmitter Interrupts An interrupt will be generated each time a packet is transmitted when this bit is set The interrupt is generated regardless if the packet was transmitted successfully or if it terminated with an error Not Reset Receiver Interrupt RI Enable Receiver Interrupts An interrupt will be generated each time a packet is received when this bit is set The interrupt is generated regardless if the packet was received successfully or if it terminated with an error Not Reset Full Duplex FD If set the GRETH_GBIT operates in full duplex mode otherwise it operates in half duplex Not Reset Promiscuous Mode PM If set the GRETH_GBIT operates in promiscuous mode which means it will receive all packets regardless of the destination address Not Reset Reset RS A one written to this bit resets the GRETH_GBIT core Self cleari
358. e GRLIB IP Library User s Manual 25 10 Library dependencies 25 11 Table 190 shows libraries used when instantiating the core VHDL libraries Table 190 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER LEON3 Component signals Component declaration signals declaration Component declaration The core has the following component declaration 179 component dsu3 generic hindex integer 0 haddr integer 169004 hmask integer 16 f00 ncpu integer 1 tbits integer 30 tech integer 0 irg integer 0 kbytes integer 0 i port rst in std_ulogic clk in std_ulogic ahbmi in ahb_mst_in type ahbsi in ahb_slv_in type ahbso out ahb_slv_out_type dbgi in 13_debug_out_vector 0 to NCPU 1 dbgo out 13_debug_in_vector 0 to NCPU 1 dsui in dsu_in_type dsuo out dsu_out_type end component 25 12 Instantiation This examples shows how the core can be instantiated The DSU is always instantiated with at least one LEON3 processor It is suitable to use a generate loop for the instantiation of the processors and DSU and showed below library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler leon3 all constant NCPU integer 1 select number of processors signal leon3i 13_in_vector 0 to NCPU 1 signa
359. e address is technology dependent and generally not allowed Configuration options Table 476 shows the configuration options of the core VHDL generics Table 476 Configuration options Name Function Range Default tech Technology selection 0 NTECH 0 abits Address bits Depth of RAM is 2 lts 1 see table below 5 dbits Data width see table below Table 477 shows the supported technologies for the core Table 477 Supported technologies Tech name Technology RAM cell abit range dbit range altera All altera devices altsyncram unlimited unlimited virtex Xilinx Virtex Virtex E Spartan 2 RAMB4_Sn 2 10 unlimited virtex2 Xilinx Virtex2 Spartan3 Virtex4 RAMB16_Sn 2 14 unlimited Spartan3e proasic3 Actel Proasic3 ram4k9 2 12 unlimited lattice Lattice XP EC ECP dp8ka 2 13 unlimited memvirage Virage ASIC RAM hdss2_64x32cm4sw0 6 9 32 hdss2_128x32cm4sw0 hdss2_256x32cm4sw0 hdss2_512x32cm4sw0 memartisan Artisan ASIC RAM dp_256x32m4 8 10 32 dp_512x32m4 dp_1kx32m4 487 61 3 Signal descriptions Table 478 shows the interface signals of the core VHDL ports Table 478 Signal descriptions Signal name Field Type Function Active CLK1 N A Input Portl clock ADDRESS1 N A Input Portl address DATAIN1 N A Input Portl write data DATAOUTI N A Output Portl read data ENABLE1 N A Input Portl chip select High W
360. e ae eee 137 21 10 lt SiptialGESCerpt OM se sec ses ves ess ee a hess snee la il 137 21 11 Library dependencies senti 137 21 12 is A snssnenscbssscacossisuacscovsbevacoucsscuvseaveescubsa sete Ep ERS ENESOVE EKOS SEES 137 GRCAN CAN 2 0 Controller with DMA idad die dos 139 22 1 OVGEVICW id ta 139 22 2 o A 140 22 3 Protocol cnc is A tias 140 22 4 Stat s and MONIOTIOS scssi esre iye iksiri ca suse cus cease EErEE eS eE Era V E EEVEE EE Ea cus euteacuscheadeseus db eveck eases 141 22 5 TADOS ai A Ee 141 22 6 Recepcion dae doses 144 22 7 Global reset a dienabler coi 147 22 8 NN 147 22 9 Register conil Saves eth oases Seth ck scene east li es crias leas ii becas 148 2210 Memory Mapping iio 157 22 11 Vendor and device identifiers scenon e conc nono non nnnnnonn nena rnnn ran EE r ES 158 22 12 Configuration OPS italia 158 22 13 Sienal descriptions iu eased Bathe eva iss Raa ae ee ees Hee dv ee eae 158 2214 Libr ry dependencies sosesc Sscusied cs ails case NO 159 QQANS O A ON 159 DDRSPA 16 32 and 64 bit DDR266 Controller cccccnnnnnnnccnnnncnononeninacinncnnononinaniniccss 161 23 1 OVELVICW vihesse otirish kae eehu E Ee E e TE EEE accede sob rE SEIT EEEE SOEKE E EO NERE SNES S SES s 161 23 2 Operation it is 161 23 3 Vendor and device identifiers oooonconocnnnnconcnononnnonnnononnnonnnonncnnnon non nono non neon cnn nan nan rnn conc este retrivera ro s ovS 164 23 4 ContigUratiOn OPS isee E senesdbvarecnsl Mees tavts tes N E
361. e complete MII interface as defined by the IEEE 802 3 standard with the exception of the management interface Signals are provided for the management part also but they are currently not used and should be connected to dummy signals or left unconnected were appropri ate Although it was designed to be used with the Opencores MAC in the EDCL the MII interface should make it possible to connect it to any MAC The model can be used in any of the following modes 10 Mbit half or full duplex 100 Mbit half or full duplex The mode is selected with the LEDCFG signals and table 441 shows the different set tings The rx clk and tx clk signals are driven with the correct frequency depending on the selected mode The other signals are driven in such a way that the follow the 802 3 specification as closely as possible Table 441 The led_cfg values used for the different operating modes LED_CFG Mode 000 10 Mbit half duplex 001 10 Mbit full duplex 010 100 Mbit half duplex 011 100 Mbit full duplex The PHY model reads its in data from a file called indata from the current working directory The data should be stored as ASCII with one nibble in binary format per row It is read using the VHDL 53 3 445 TEXTIO functions The file should begin with a row containing an invalid bit vector anything that cannot be converted to a valid bit vector by TEXTIO and all packets should have such a row in between This is needed bec
362. e example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined in the example design s port map and connected to the memory controller System clock and reset are generated by GR Clock Gen erator and Reset Generator The CE signal of the memory controller is also connected to the AHB sta tus register Memory controller decodes default memory areas I O area is 0x20000000 0x20FFFFFF and RAM area is 0x40000000 0x40FFFFE library ieee use ieee std_logic_1164 all library grlib use grlib amba all library techmap use techmap gencomp all library gaisler use gaisler memctrl all use gaisler misc all entity ftsrctrl8_ex is port resetn in std_ulogic elk in std_ulogic address out std_logic_vector 27 downto 0 data inout std_logic_vector 31 downto 0 ramsn out std_logic_vector 3 downto 0 ramoen out std_logic_vector 3 downto 0 rwen out std_logic_vector 3 downto 0 oen out std_ulogic writen out std_ulogic read out std_ulogic iosn out std_ulogic brdyn in std_ulogic Bus ready bexcn in std_ulogic Bus exception i end architecture rtl of ftsrctrl8_ex is signal memi memory_in type signal memo memory_out_type signal apbi apb_slv_in type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in type signal ahbso ahb_slv_out_vec
363. e function completed successfully 1 The new address could not be written correctly Table 353 Parameters for spw_txdesc Parameter Description Allowed range pnt The new address to the descriptor table area 0 232 1 spw Pointer to the spwvars struct associated with GRSPW core that should be configured int set_rxdesc int pnt struct spwvars spw Sets a new address to the Receiver descriptor table address register Should only be used when no transmission is active Also resets the pointers for spw_rx and spw_checkrx Explained in the section for those functions Table 354 Return values for spw_rxdesc Value Description 0 The function completed successfully 1 The new address could not be written correctly Table 355 Parameters for spw_rxdesc Parameter Description Allowed range pnt The new address to the descriptor table area 0 232 1 spw Pointer to the spwvars struct associated with GRSPW core that should be configured void spw_disable struct spwvars spw Disables the GRSPW core the link disable bit is set to 1 Table 356 Parameters for spw_disable Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured void spw_enable struct spwvars spw Enables the GRSPW core the link disable bit is set to 0 354 Table 357 Parameters
364. e read is given in tmp The packet will be stored in rx_pkt The actual number of received bytes is returned by the function on success and 1 on failure In the latter case errno is also set The call will fail if a null pointer is passed The blocking behavior can be set using ioctl calls In blocking mode the call will block until a packet has been received In non blocking mode the call will return immediately and if no packet was available 1 is returned and errno set appropriately The table below shows the different errno values that can be returned Table 346 ERRNO values for read calls ERRNO Description EINVAL A NULL pointer was passed as the data pointer or the length was illegal EBUSY No data could be received no packets available in non blocking mode API A simple Application Programming Interface API is provided together with the GRSPW The API is located in GRLIB software spw The files are rmapapi c spwapi c rmapapi h spwapi h The spwapi h file contains the declarations of the functions used for configuring the GRSPW and transfer ring data The corresponding definitions are located in spwapi c The rmapapi is structured in the same manner and contains a function for building RMAP packets 351 These functions could be used as a simple starting point for developing drivers for the GRSPW The different functions are described in this section 42 16 1 GRSPW Basic API The basic GRSPW API i
365. e to which DMA channel a packet is destined Currently only one channel is available to which all packets except RMAP commands are stored but the GRSPW is prepared to be easily expandable with more DMA channels Figure 138 shows the packet type expected by the GRSPW RMAP Protocol ID 0x01 commands are handled separately from other packets if the hardware RMAP handler is enabled When enabled all RMAP commands are processed executed and replied in hardware All RMAP replies received are still stored to the DMA channel If the RMAP handler is disabled all packets are stored to the DMA channel More information on the RMAP protocol support is found in section 42 6 All packets arriving with the extended protocol ID 0x00 are dumped to the DMA channel This means that the hardware RMAP command handler will not work if the incoming RMAP packets use the extended protocol ID Note also that the reserved extended protocol identifier 1D 0x000000 are not ignored by the GRSPW It is up to the client receiving the packets to ignore them When transmitting packets the address and protocol ID fields must be included in the buffers from where data is fetched They are not automatically added by the GRSPW 320 42 3 Figure 138 shows a packet with a normal protocol identifier The GRSPW also allows reception and transmission with extended protocol identifiers but then the hardware RMAP and RMAP CRC calcu lations will not work Addr ProtiD DO
366. ea Only available if the wsreg VHDL generic is set to one Table 224 MCFG3 register 31 cnt 13 cnt 12 12 11 10 9 8 7 0 RESERVED SEC WB RB SEN TCB 31 RESERVED ent 13 ent 12 SEC Single error counter This field increments each time a single error is detected It saturates at 12 the maximum value that can be stored in this field Each bit can be reset by writing a one to it cnt number of counter bits 11 WB Write bypass If set the TCB field will be used as checkbits in all write operations 10 RB Read bypass If set checkbits read from memory in all read operations will be stored in the TCB field 9 SEN SRAM EDAC enable If set EDAC will be active for the SRAM area 8 RESERVED 7 0 TCB Used as checkbits in write operations when WB is one and checkbits from read operations are stored here when RB is one 242 30 5 30 6 All the fields in MCFG3 register are available if the edacen VHDL generic is set to one except SEC field which also requires that the errent VHDL generic is set to one Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x056 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 221 shows the configuration options of the core VHDL generics Table 225 Controller configuration options Generic Function Allowed range
367. ed 378 44 4 44 3 2 Instruction cache tag A instruction cache tag entry consists of several fields as shown in figure 169 Tag for 1 Kbyte set 32 bytes line 31 10 9 8g 7 0 ATAG LRR LOCK VALID Tag for 4 Kbyte set 16bytes line 31 12 9 8 3 0 ATAG 00 LRR LOCK 0000 VALID Figure 169 Instruction cache tag layout examples Field Definitions 31 10 Address Tag ATAG Contains the tag address of the cache line 9 LRR Used by LRR algorithm to store replacement history otherwise 0 8 LOCK Locks a cache line when set 0 if cache locking not implemented 7 0 Valid V When set the corresponding sub block of the cache line contains valid data These bits is set when a sub block is filled due to a successful cache miss a cache fill which results in a memory error will leave the valid bit unset A FLUSH instruction will clear all valid bits V O corresponds to address O in the cache line V 1 to address 1 V 2 to address 2 and so on NOTE only the necessary bits will be implemented in the cache tag depending on the cache configu ration As an example a 4 kbyte cache with 16 bytes per line would only have four valid bits and 20 tag bits The cache rams are sized automatically by the ram generators in the model Data cache 44 4 1 Operation The data cache can be configured as a direct mapped cache or as a multi set cache with associativity of 2 4 implementing either LRU
368. ed and or trigged 27 20 Number of traced signals 19 6 Last index of trace buffer Depth 1 5 0 Number of trig levels 46 3 2 Trace buffer index 31 abits abits 1 0 000 0 the index of the oldest sample Figure 178 Trace buffer index register B1 abits Reserved abits 1 0 The index of the oldest sample in the buffer abits is the number of bits needed to represent the configured depth Note that this register is written by the trigger engine clock domain and thus needs to be known stable when read out Only when the armed bit in the status register is zero is the content of this register reliable 46 3 3 Page register 31 000 0 current page Figure 179 Page register 31 4 Reserved 3 0 This register selects what page that will be used when reading from the trace buffer The trace buffer is organized into pages of 1024 samples Each sample can be between 1 and 256 bits If the depth of the buffer is more than 1024 the page register has to be used to access the other pages To access the i th page the register should be set i where i 0 15 46 3 4 Trig counter 31 abits abits 1 0 000 0 trig counter value Figure 180 Trig counter register 31 abits Reserved nbits 1 0 Trig counter value A counter is incremented by one for each stored sample after the final triggering event and when it reaches the value stored in
369. ed by the descriptor address field The GRETH does not add the Ethernet address and type fields so they must also be stored in the data buffer The 4 B Ethernet CRC is automatically appended at the end of each packet Each descrip tor will be sent as a single Ethernet packet If the size field in a descriptor is greater than 1514 B the packet will not be sent Rx DMA interface The receiver DMA interface is used for receiving data from an Ethernet network The reception is done using descriptors located in memory 34 4 1 Setting up descriptors A single descriptor is shown in figure 113 The address field should point to a word aligned buffer where the received data should be stored The GRETH will never store more than 1514 B to the buffer If the interrupt enable IE bit is set an interrupt will be generated when a packet has been received to this buffer this requires that the receiver interrupt bit in the control register is also set The interrupt will be generated regardless of whether the packet was received successfully or not The Wrap WR bit is also a control bit that should be set before the descriptor is enabled and it will be explained later in this section 31 17 16 15 14 13 12 11 10 0 0x0 RESERVED OE CE FT AE IE WR EN LENGTH 31 21 0 Ox4 ADDRESS RESERVED 10 0 LENGTH The number of bytes received to this descriptor 11 Enable EN Set to one to enable the descriptor Should always be set
370. ed by this module vsim c quiet leon3mp VSIM 1 gt run LEON3 MP Demonstration design 34 oogogoooenogoovooeHa grgpio leon3_0 leon3_0 VSIM 2 gt Se SR OSE HEHE SHE SHR SR H H HE SHE SHE H H H SHE SHE SHE SHE SESE H H H HE SHE SR E H HEHEHE hbctrl hbctrl hbctrl hbetril hbctrl hbctrl hbctrl hbctrl hbctrl hbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl apbctrl Te gptimer3 apbuart1 ahbuart7 RLIB Version 1 0 7 arget technology hbctrl inferred AHB arbiter multiplexer rev 1 Common I O area disabled Configuration area at Oxfffff000 mst0 mstl slv0 slvl slv0 slvl slv2 slv3 slv7 slv11 Gaisler Research Gaisler Research European Space Agency memory at 0x00000000 memory at 0x20000000 memory at 0x40000000 Gaisler Research memory at 0x80000000 European Space Agency O ports at 0x80000000 Gaisler Research O ports at 0x80000100 Gaisler Research O ports at 0x80000200 Gaisler Research O ports at 0x80000300 Gaisler Research O ports at 0x80000700 Gaisler Research O ports at 0x80000b00 8 bit GPIO Unit rev 0 GR Timer Unit rev 0 irgmp Multi processor Interrupt Controller rev 3 Generic UART rev 1 TEG 2 fifo 4 AHB Debug UART rev 0 LEON3 SPARC V8 processor rev 0 icache 1 8 kbyte memory library 8 bit scaler inferred 4
371. ed here Ethernet MAC e0 eth_oc generic map mstndx gt 1 slvndx gt 1 ioaddr gt 16 BOO irq gt 12 memtech gt inferred port map rstn clk ahbsi ahbso 1 ahbmi ahbmo 1 ethil ethol EDCL el edcl generic map mstndx gt 2 macaddrh gt 16 00005E macaddrl gt 000000 ipaddrh gt 16 COA8 ipaddrl gt 16 0033 udpport gt 8000 memtech gt inferred speed gt 0 port map rstn clk edcli ahbmi ahbmo 2 ethi2 etho2 edcli lsbip lt 0000 ETH_ARB ea0 eth_arb generic map fullduplex gt 0 mdiomaster gt 1 port map rstn ethi etho ethol ethil etho2 ethi2 end 37 37 1 37 2 301 GRFPU High performance IEEE 754 Floating point unit Overview GRFPU is a high performance FPU implementing floating point operations as defined in IEEE Stan dard for Binary Floating Point Arithmetic IEEE 754 and SPARC V8 standard IEEE 1754 Sup ported formats are single and double precision floating point numbers The advanced design combines two execution units a fully pipelined unit for execution of the most common FP operations and a non blocking unit for execution of divide and square root operations The logical view of the GRFPU is shown in figure 134 Sat f GRFPU clk gt Pipelined execution reset gt start gt d d 9 2 rea opcode y gt opid 6 allow 3 operand 64 resid 6 gt r
372. ed to the DMA channel The rxmaxlength register is still checked and packets exceeding this size will be truncated 326 42 5 If the RMAP handler is present RMAP commands will still be handled by it when promiscuous mode is enabled if the rmapen bit is set If it is cleared RMAP commands will also be stored to the DMA channel Transmitter DMA engine The transmitter DMA engine handles transmission of data from the DMA channel to the Space Wire network Currently there is only one DMA channel available but the GRSPW has been written so that additional DMA channels can be easily added if needed 42 5 1 Basic functionality The transmit DMA engine reads data from the AHB bus and stores them in the transmitter FIFO for transmission on the SpaceWire network Transmission is based on the same type of descriptors as for the receiver and the descriptor table has the same alignment and size restrictions When there are new descriptors enabled the GRSPW reads them and transfer the amount data indicated 42 5 2 Setting up the GRSPW for transmission Four steps need to be performed before transmissions can be done with the GRSPW First the link interface must be enabled and started by writing the appropriate value to the ctrl register Then the address to the descriptor table needs to be written to the transmitter descriptor table address register and one or more descriptors must also be enabled in the table Finally the txen bit in the DMA control r
373. ee section 3 2 Table 317 Throughput and latency Operation Throughput Latency FADDS FADDD FSUBS FSUBD FMULS FMULD FSMULD 1 3 FITOS FITOD FSTOI FSTOL RND FDTOI FDTOI_RND FSTOD 1 3 FDTOS FCMPS FCMPD FCMPES FCMPED 1 3 FDIVS 15 15 FDIVD 16 5 15 18 16 5 15 18 FSQRTS 23 23 FSQRTD 24 5 23 26 24 5 23 26 Throughput and latency are data dependant with two possible cases with equal statistical possibility Conversion operations execute in a pipelined execution unit and have throughput of one clock cycle and latency of three clock cycles Conversion operations provide conversion between different float ing point numbers and between floating point numbers and integers Comparison functions offering two different types of quiet Not a numbers QNaNs handling are pro vided Move negate and absolute value are also provided These operations do not ever generate unfinished exception unfinished exception is never signaled since compare negate absolute value and move handle denormalized numbers 37 2 3 Exceptions GRFPU detects all exceptions defined by the IEEE 754 standard This includes detection of Invalid Operation NV Overflow OF Underflow UF Division by Zero DZ and Inexact NX excep tion conditions Generation of special results such as NaNs and infinity is also implemented Over flow OF and underflow UF are detected before rounding If an operation un
374. egardless if the packet was transmitted successfully or if it terminated with an error 14 Underrun Error UE The packet was incorrectly transmitted due to a FIFO underrun error 15 Attempt Limit Error AL The packet was not transmitted because the maximum number of attempts was reached 16 Late Collision LC A late collision occurred during the transmission 1000 Mbit mode only 17 More MO More descriptors should be fetched for this packet Scatter Gather 1 0 18 IP Checksum IC Calculate and insert the IP header checksum for this packet The checksum is only inserted if an IP packet is detected 19 TCP Checksum TC Calculate and insert the TCP checksum for this packet The checksum is only inserted if an TCP packet is detected 20 UDP Checksum UC Calculate and insert the UDP checksum for this packet The checksum is only inserted if an UDP packet is detected 31 2 Address Pointer to the buffer area from where the packet data will be loaded Figure 123 Transmitter descriptor Memory offsets are shown in the left margin To enable a descriptor the enable EN bit should be set and after this is done the descriptor should not be touched until the enable bit has been cleared by the GRETH_GBIT The rest of the fields in the descriptor are explained later in this section 35 3 2 Starting transmissions Enabling a descriptor is not enough to start a transmission A pointer to the memory area holding the desc
375. egister is written with a one which triggers the transmission These steps will be covered in more detail in the next sections 42 5 3 Enabling descriptors The descriptor table address register works in the same way as the receiver s corresponding register which was covered in section 42 4 To transmit packets one or more descriptors have to be initialized in memory which is done in the fol lowing way The number of bytes to be transmitted and a pointer to the data has to be set There are two different length and address fields in the transmit descriptors because there are separate pointers for header and data If a length field is zero the corresponding part of a packet is skipped and if both are zero no packet is sent The maximum header length is 255 bytes and the maximum data length is 16 Mbyte 1 When the pointer and length fields have been set the enable should be set to enable the descriptor This must always be done last The other control bits must also be set before enabling the descriptor The transmit descriptors are 16 bytes in size so the maximum number in a single table is 64 The dif ferent fields of the descriptor is shown in figure 142 together with the memory offsets The CC field should be set if RMAP CRC should be calculated and inserted for the current packet This field is only used by the GRSPW when the CRC logic is available rmap or rmapcrc VHDL generic set to 1 The first CRC will be calculated from the data fetche
376. en sdclk open cgi cgo egi pllctrl lt 00 cgi pllrst lt resetn cgi pllref lt pllref rst0 rstgen port map resetn clkm cgo clklock rstn Memory controller srctrl10 srctrl generic map rmw gt 1 prom8en gt 0 srbanks gt 2 banksz gt 13 ramsel5 gt 0 port map rstn clkm ahbsi ahbso 0 memi memo sdo I O pads driving data memory bus data signals datapads for iin 0 to 3 generate data_pad iopadv generic map width gt 8 port map pad gt data 31 i 8 downto 24 i 8 o gt memi data 31 i 8 downto 24 1 8 en gt memo bdrive i i gt memo data 31 i 8 downto 24 1 8 end generate Alternative I O pad instantiation with vectored enable instead datapads for iin 0 to 3 generate data_pad iopadvv generic map width gt 8 port map pad gt data 31 i 8 downto 24 i 8 o gt memi data 31 i 8 downto 24 1 8 en gt memo bdrive 31 i 8 downto 24 i 8 i gt memo data 31 i 8 downto 24 1 8 end generate connect memory controller outputs to entity output signals address lt memo address ramsn lt memo ramsn romsn lt memo romsn oen lt memo oen rwen lt memo wrn ramoen lt memo ramoen writen lt memo writen read lt memo read iosn lt memo iosn sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm end 57 57 1 57 2 465 SSRCTRL 32 bit SS
377. en by a separate register A directive is placed on these registers so that they will not be removed during synthesis in case the output they drive is used in the design SSRAM PROM waveform Because the SSRAM Synchronous pipelined SRAM has a pipelined structure the data output has a latency of three clock cycles The pipelined structure enables a new memory operation to be issued each clock cycle Figure 228 and figure 229 show timing diagrams for the SSRAM read and write accesses 466 readO read0 1 read0 2 read0 3 A ao y aon ARYA _ RAMSN A Po oan ti lt i SN A y f carter y Figure 228 32 bit SSRAM read cycle As shown in the figure above the controller always perform a burst read access to the memory This eliminates all data output latency except for the first word when a burst read operation is executed write read A Al AO RAMSN NR i ap WRITEN e Lo EN D TECHED Figure 229 32 bit SSRAM write cycle A write operation takes three clock cycles On the rising edge of the first clock cycle the address and control signals are latched into the memory On the next rising edge the memory puts the data bus in high impedance mode On the third rising edge the data on the bus is latched into the memory and the write is complete The controller can start a new memory read or write operation in the second clock cycle In figure 229 this is illustrated by a read ope
378. enabled before the transmit enable bit is set 34 3 3 Descriptor handling after transmission When a transmission of a packet has finished status is written to the first word in the corresponding descriptor The Underrun Error bit is set if the FIFO became empty before the packet was completely transmitted while the Alignment Error bit is set if more collisions occurred than allowed The packet was successfully transmitted only if both of these bits are zero The other bits in the first descriptor word are set to zero after transmission while the second word is left untouched The enable bit should be used as the indicator when a descriptor can be used again which is when it has been cleared by the GRETH There are three bits in the GRETH status register that hold transmis sion status The Transmitter Error TE bit is set each time an transmission ended with an error when at least one of the two status bits in the transmit descriptor has been set The Transmitter Interrupt TD is set each time a transmission ended successfully 274 34 4 The transmitter AHB error TA bit is set when an AHB error was encountered either when reading a descriptor or when reading packet data Any active transmissions were aborted and the transmitter was disabled The transmitter can be activated again by setting the transmit enable register 34 3 4 Setting up the data for transmission The data to be transmitted should be placed beginning at the address point
379. enei cones dinner ds e EEO Eo ei do iio NEE SE de decido eines ds 45 6 9 SU ia 46 AHBRAM Single port RAM with AHB interface ooonoconoccononcnoncncnoncconcnnnnnnnn nono nonncnnnncnancon 47 7 1 OVELVICW seis c ccs E che cacuscasusves sia see cians devs E ad deis des 47 7 2 Vendor and device identifiers saiisine eh steesszetpsheserscee tetas sia sdveed spe Since serian acacia decret 47 7 3 Configuration Options sssini escris ir vestene STE rsr KEE cep cpunnepeseceseacvecusseveeu sets ena csebsndsts rai n alii es 47 7 4 SigtialASS CHP ONS turca 47 7 5 Library dependencias es ae RA a eee 47 7 6 Component declara sidra ion 48 17 Instantia oien NO 48 AHBROM Single port ROM with AHB interface oooooononcccnoncccnoncnononcnononcnononanonnncnnnnncnnnn nos 49 8 1 OVA Wisin tries 49 8 2 PROM sBemerationis iaa 49 8 3 Vendor and device identifiers 2 0 0 eee ce ceececeeceeeceseeeeeeseecsecsaesaecsacsaeceecseeseceseseeseseseaecaeseaecaaesaecseenaes 49 8 4 Configufation Options sc coimas aiii Seige sett deans ese ttes SS 49 8 5 Sipnal descriptrOns 3 sesso sea eaves a Sa A eee se eee 50 8 6 Library dependencia bis 50 8 7 Component declaration ia sii 50 8 8 Installation a o o e eta 50 AHBSTAT AHB Status Repite iii 51 9 1 Ove E e e E E E E E ise be et es eee 51 9 2 O 51 9 3 NO 51 9 4 Vendor and device identifiers eee ec eeceeeeeeeeceseeeseeseecaecsaesaecsacsaeceeceseeseceseseeseseseaecaeseaecsassaecneenaes 52 9 5 COD ISULAtION Optlons viden
380. ent mul_33_33 port x in std_logic_vector 32 downto 0 y in std_logic_vector 32 downto 0 p out std_logic_vector 65 downto 0 end component 49 6 Instantiation This examples shows how the core can be instantiated The core is configured to implement 16x16 pipelined multiplier with support for MAC operations library ieee use ieee std_logic_1164 all library grlib use grlib multlib all signal opl op2 std_logic_vector 32 downto 0 signal prod std_logic_vector 65 downto 0 begin m0 mul_33_33 port map opl op2 prod end 50 50 1 50 2 427 GRPCI PCI Target Master Unit Overview The PCI Target Master Unit is a bridge between PCI bus and AMBA AHB bus The unit is connected to the PCI bus through two interfaces PCI Target and PCI Master PCI Master interface is optional and can be disabled in the VHDL model Two interfaces connect the core to the AHB bus AHB Slave and AHB Master Interface PCI Configuration Status register is attached to AMBA APB bus The PCI and AMBA interfaces belong to two different clock domains Synchronization is performed inside the core through FIFOs with configurable depth AMBA bus PCI Bridge Cfe Stat y y AHB Slave AHB Master a Wee MTx FIFO MRx FIFO TTx FIFO TRx FIFO 1 no PCI Master PCI Target PCI Off chip bus Figure 200 PCI Mas
381. er This can be used to reduce the output delay SVBDRIVE Output Not used READ Output Not used SA 14 0 Output Not used CB 7 0 Output Not used SCB 7 0 Output Not used VCDRIVE 7 0 Output Not used SVCDRIVE 7 0 Output Not used CE Output Not used AHBSI 1 Input AHB slave input signals AHBSO 1 Output AHB slave output signals APBI 1 Input APB slave input signals APBO 1 Output APB slave output signals 1 See GRLIB IP Library User s Manual 2 Polarity is selected with the oepol generic 57 7 57 8 57 9 Library dependencies 471 Table 461 shows libraries used when instantiating the core VHDL libraries Table 461 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Component declaration The core has the following component declaration component ssrctrl generic hindex pindex romaddr rommask ramaddr rammask ioaddr iomask paddr pmask oepol i port rst clk ahbsi ahbso apbi apbo sri sro end component Instantiation integer 0 integer 0 integer 0 integer 16 ff0 integer 16 400 integer 16 ff0 integer 16 200 integer 16 ff0 integer 0 integer 16 fff integer 0 in std_ulogic in std_ulogic in
382. er core from Gaisler Research which is optionally instantiated as a sub block The SDRAM controller supports 64M 256M and 512M devices with 8 12 column address bits and up to 13 row address bits The size of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte The oper ation of the SDRAM controller is controlled through MCFG2 and MCFG3 see below Both 32 and 64 bit data bus width is supported allowing the interface of 64 bit DIMM modules The memory con troller can be configured to use either a shared or separate bus connecting the controller and SDRAM devices 27 8 2 Address mapping The two SDRAM chip select signals are decoded SDRAM area is mapped into the upper half of the RAM area defined by BAR2 register and cannot be used simultaneously with fifth SRAM bank RAMSN 4 When the SDRAM enable bit is set in MCFG2 the controller is enabled and mapped into upper half of the RAM area as long as the SRAM disable bit is not set If the SRAM disable bit is set all access to SRAM is disabled and the SDRAM banks are mapped into the lower half of the RAM area 27 8 3 Initialisation When the SDRAM controller is enabled it automatically performs the SDRAM initialisation sequence of PRECHARGE 8x AUTO REFRESH and LOAD MODE REG on both banks simulta neously The controller programs the SDRAM to use single location access on write The controller programs the SDRAM to use line burst of length 8 when pageburst VHDL gen
383. er of CAN mes sages 4 that fit in the buffer E g CanTxSIZE SIZE 2 means 8 CAN messages fit in the buffer Note however that 1t is not possible to fill the buffer completely leaving at least one message position in the buffer empty This is to simplify wrap around condition checking E g CanTxSIZE SIZE 2 means that 7 CAN messages fit in the buffer at any given time 22 5 2 Write and read pointers The write pointer CanTxWR WRITE indicates the position 1 of the last CAN message written to the buffer The write pointer operates on number of CAN messages not on absolute or relative addresses The read pointer CanTxRD READ indicates the position 1 of the last CAN message read from the buffer The read pointer operates on number of CAN messages not on absolute or relative addresses 142 The difference between the write and the read pointers is the number of CAN messages available in the buffer for transmission The difference is calculated using the buffer size specified by the CanTx SIZE SIZE field taking wrap around effects of the circular buffer into account Examples e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 2 and CanTxRD READ 0 e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 0 and CanTxRD READ 6 e There are 2 CAN messages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 1 and CanTxRD READ 7 e There are 2 CAN me
384. erflow EXC 1 Division by zero EXC 0 Inexact CC 1 0 O Result condition code of an FP compare operation 00 equal 01 operand lt operand2 10 operand gt operand2 11 unordered Timing An FP operation is started by providing the operands opcode rounding mode and id before rising edge The operands need to be provided a small set up time before a rising edge while all other signals are latched on rising edge The FPU is fully pipelined and a new operation can be started every clock cycle The only exceptions are divide and square root operations which require 15 to 26 clock cycles to complete and which are not pipelined Division and square root are implemented through iterative series expansion algorithm 306 CLK START OPCODE Since the algorithms basic step is multiplication the floating point multiplier is shared between multi plication division and square root Division and square root do not occupy multiplier during the whole operation and allow multiplication to be interleaved and executed parallelly with division or square root One clock cycle before an operation is completed the output signal RDY is asserted to indicate that the result of an FPU operation will appear on the output signals at the end of the next cycle The id of the operation to be completed and allowed operations are reported on signals RESID and ALLOW During the next clock cycle the result appears on RES EX
385. eric is 0 The controller programs the SDRAM to use page burst when pageburst VHDL generic is 1 The controller programs the SDRAM to use page burst or line burst of length 8 selectable via the MCFG register when page burst VHDL generic is 2 27 8 4 Configurable SDRAM timing parameters To provide optimum access cycles for different SDRAM devices and at different frequencies three SDRAM parameters can be programmed through memory configuration register 2 MCFG2 TCAS TRP and TRECD The value of these field affects the SDRAM timing as described in table 197 27 9 193 Table 197 SDRAM programmable minimum timing parameters SDRAM timing parameter Minimum timing clocks CAS latency RAS CAS delay tcas gt trop TCAS 2 Precharge to activate trp TRP 2 Auto refresh command period trc TRFC 3 Activate to precharge tr As TRFC 1 Activate to Activate trc TRP TRFC 4 If the TCAS TRP and TRFC are programmed such that the PC100 133 specifications are fulfilled the remaining SDRAM timing parameters will also be met The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing in ns Table 198 SDRAM example programming SDRAM settings tcas tRC trP tRFC TRAS 100 MHz CL 2 TRP 0 TCAS 0 TRFC 4 20 80 20 70 50 100 MHz CL 3 TRP 0 TCAS 1 TRFC 4 30 80 20 70 50 133 MHz CL 2 TRP 1 TCAS 0 TRFC 6 15 82 22 67 52
386. es 0 single sample point BTR1 6 4 TSEG2 Time segment 2 BTR1 3 0 TSEG1 Time segment 1 The CAN bus bit period is determined by the CAN system clock and time segment 1 and 2 as shown in the equations below ttseg1 tsc TSEGI 1 tiseg2 tsc TSEG2 1 tbit ttseg1 ttseg2 tscl The additional t term comes from the initial sync segment Sampling is done between TSEG1 and TSEG2 in the bit period Design considerations This section lists known differences between this CAN controller and SJA1000 on which is it based e All bits related to sleep mode areunavailable e Output control and test registers do not exist reads 0x00 e Clock divisor register bit 6 CBP and 5 RXINTEN are not implemented e Overrun irq and status not set until fifo is read out BasicCAN specific differences e The receive irq bit is not reset on read works like in PeliCAN mode e Bit CR 6 always reads 0 and is not a flip flop with no effect as in SJA1000 PeliCAN specific differences e Writing 256 to tx error counter gives immediate bus off when still in reset mode e Read Buffer Start Address register does not exist e Addresses above 31 are not implemented i e the internal RAM FIFO access e The core transmits active error frames in Listen only mode Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x019 For description of vendor and device identifiers see GRLIB
387. es See the transmission section for more information LINKDISABLE This call disables the link sets the linkdisable bit to 1 and the linkstart bit to 0 No argument is taken The call fails if the register write fails LINKSTART This call starts the link sets the linkdisable bit to O and the linkstart bit to 1 No argument is taken The call fails if the register write fails 42 15 6 Transmission Transmissions are done with either the write call or a special ioctl call Write calls are used when data only needs to be taken from a single contiguous buffer An example of a write call is shown below result write fd tx_pkt 10 On success the number of transmitted bytes is returned and 1 on failure Errno is also set in the latter case Tx_pkt points to the beginning of the packet which includes the destination node address The last parameter sets the number of bytes that the user wants to transmit 350 42 16 The call will fail if the user tries to send more bytes than is allocated for a single packet this can be changed with the SET_PACKETSIZE ioctl call or if a NULL pointer is passed The write call can be configured to block in different ways If normal blocking is enabled the call will only return when the packet has been transmitted I non blocking mode the transmission is only set up in the hardware and then the function returns immediately that is before the packet is actually sent If there are no resources avail
388. es The read data and optional EDAC check bits are latched on the rising edge of the clock on the last data cycle On non consecutive accesses a lead out cycle is added after a read cycle to prevent bus contention due to slow turn off time of PROM devices Figure 66 shows the basic read cycle waveform zero waitstate for non consecutive PROM reads Note that the address is undefined in the lead out cycle Figure 67 shows the timing for consecutive cycles zero waitstate Waitstates are added by extending the data2 phase This is shown in figure 68 and applies to both consecutive and non consecutive cycles Only an even number of waitstates can be assigned to the PROM area clk address romsn oen data cb clk address romsn oen data cb clk address romsn oen data cb datai data2 lead out datai data2 lead out Cp Xx XA 2 a os 2 Figure 66 Prom non consecutive read cyclecs datai data2 datai data2 lead out CB1 CB2 Figure 67 Prom consecutive read cyclecs datai data2 data2 data2 lead out CB1 Figure 68 Prom read access with two waitstates 187 188 27 3 lead in data lead out address romsn AL VTT TT T n SC rwen CT AAAA i PA EOS oof ES data Di cb CBI Figure 69 Prom write cycle 0 waitstates lead in data data data lead out
389. ese FIFOs are used to transfer N Chars between the AMBA and Space Wire domains dur ing reception and transmission The RMAP handler is an optional part of the GRSPW which can be enabled with a VHDL generic The RMAP handler handles incoming packets which are determined to be RMAP commands instead of the receiver DMA engine The RMAP command is decoded and if it is valid the operation is per formed on the AHB bus If a reply was requested it is automatically transmitted back to the source by the RMAP transmitter The GRSPW is controlled by writing to a set of user registers through the APB interface and three sig nals tick in rmapen and clkdiv10 The controlled parts are clock generation DMA engines RMAP handler and the link interface The link interface DMA engines RMAP handler and AMBA interface are described in section 42 3 42 4 42 6 and 42 7 respectively 42 2 2 Protocol support The GRSPW only accepts packets with a destination address corresponding to the one set in the node address register Packets with address mismatch will be silently discarded except in promiscuous mode which is covered in section 42 4 10 The node address register is initialized to the default address 234 during reset It can then be changed to some other value by writing to the register The GRSPW also requires that the byte following the destination address is a protocol identifier as specified in part 2 of the Space Wire standard It is used to determin
390. estrictions on the IP header fields The version must be four and the header size must be 5 B no options The protocol field must always be 0x11 indicating a UDP packet The length and checksum are the only IP fields changed for the reply The EDCL only provides one service at the moment and it is therefore not required to check the UDP port number The reply will have the original source port number in both the source and destination fields UDP checksum are not used and the checksum field is set to zero in the replies The UDP data field contains the EDCL application protocol fields Table 298 shows the application protocol fields data field excluded in packets received by the EDCL The 16 bit offset is used to align the rest of the application layer data to word boundaries in memory and can thus be set to any value The R W field determines whether a read 0 or a write 1 should be performed The length Table 298 The EDCL application layer fields in received frames 16 bit Offset 14 bit Sequence number 1 bit R W 10 bit Length 7 bit Unused field contains the number of bytes to be read or written If R W is one the data field shown in table 297 contains the data to be written If R W is zero the data field is empty in the received packets Table 299 shows the application layer fields of the replies from the EDCL The length field is always zero for replies to write requests For read requests it contains the number of by
391. esult 64 a y E Iteration unit round 2 4 a ly cc flush TE gt gt flushid 6 A nonstd gt Figure 134 1 GRFPU Logical View This document describes GRFPU from functional point of view Chapter Functional description gives details about GRFPU implementation of the IEEE 754 standard including FP formats opera tions opcodes operation timing rounding and exceptions Signals and timing describes the GRFPU interface and its signals GRFPU Control Unit describes the software aspects of the GRFPU integration into a LEON processor through the GRFPU Control Unit GRFPC For imple mentation details refer to the white paper GRFPU High Performance IEEE 754 Floating Point Unit available at www gaisler com Functional description 37 2 1 Floating point number formats GRFPU handles floating point numbers in single or double precision format as defined in IEEE 754 standard with exception for denormalized numbers See section 37 2 5 for more information on denor malized numbers 37 2 2 FP operations GRFPU supports four types of floating point operations arithmetic compare convert and move The operations implement all FP instructions specified by SPARC V8 instruction set and most of the operations defined in IEEE 754 All operations are summarized in table 316 with their opcodes oper ands results and exception codes Throughputs and latencies and are shown in table 316 302 T
392. eted as below Table 128 Bit interpretation of ECC 4 0 ECC 4 0 Description 0x03 Start of frame 0x02 1D 28 ID 21 0x06 1D 20 ID 18 0x04 Bit SRTR 0x05 Bit IDE 0x07 ID 17 ID 13 0x0F ID 12 ID 5 Ox0E 1D 4 ID O Ox0C Bit RTR 0x0D Reserved bit 1 0x09 Reserved bit 0 0x0B Data length code Ox0A Data field 0x08 CRC sequence 0x18 CRC delimiter 0x19 Acknowledge slot 0x1B Acknowledge delimiter Ox1A End of frame 0x12 Intermission 0x11 Active error flag 0x16 Passive error flag 0x13 Tolerate dominant bits 0x17 Error delimiter Ox1C Overload flag 21 5 9 Error warning limit register This registers allows for setting the CPU error warning limit It defaults to 96 Note that this register is only writable in reset mode 21 5 10 RX error counter register address 14 This register shows the value of the rx error counter It is writable in reset mode A bus off event resets this counter to 0 21 5 11 TX error counter register address 15 This register shows the value of the tx error counter It is writable in reset mode If a bus off event occurs this register is initialized as to count down the protocol defined 128 occurrences of the bus free signal and the status of the bus off recovery can be read out from this register The CPU can force a bus off by writing 255 to this register Note that unlike the SJA1000 this core will signal bus off imme
393. ets in parallel with the MAC receive DMA channel It uses a separate MAC address which is used for distinguishing EDCL packets from packets destined to the MAC DMA channel The EDCL also has an IP address which is set through generics Since ARP packets use the Ethernet broadcast address the IP address must be used in this case to distinguish between EDCL ARP packets and those that should go to the DMA channel Packets that are determined to be EDCL packets are not processed by the receive DMA channel When the packets are checked to be correct the AHB operation is performed The operation is per formed with the same AHB master interface that the DMA engines use The replies are automatically sent by the EDCL transmitter when the operation is finished It shares the Ethernet transmitter with the transmitter DMA engine but has higher priority 35 6 2 EDCL protocols The EDCL accepts Ethernet frames containing IP or ARP data ARP is handled according to the pro tocol specification with no exceptions IP packets carry the actual AHB commands The EDCL expects an Ethernet frame containing IP UDP and the EDCL specific application layer parts Table 305 shows the IP packet required by the EDCL The contents of the different protocol headers can be found in TCP IP literature Table 305 The IP packet expected by the EDCL Ethernet IP UDP 2B 4B 4B Data 0 242 Ethernet Header Header Header Offset Control word Address 4B Words CRC
394. external memory bus Con Low High trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 31 24 BDRIVE 1 corresponds to DATA 23 16 BDRIVE 2 corresponds to DATA 15 8 BDRIVE 3 corresponds to DATA 7 0 VBDRIVE 31 0 Output Vectored I O pad drive signals Low High SVBDRIVE 63 0 Output Vectored I O pad drive signals for separate Low High sdram bus READ Output Read strobe High SA 14 0 Output SDRAM separate address bus High AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals APBI Input APB slave input signals APBO ig Output APB slave output signals WPROT WPROTHIT Input Unused 418 Table 418 Signal descriptions Signal name Field Type Function Active SDO SDCASN Output SDRAM column address strobe Low SDCKE 1 0 Output SDRAM clock enable High SDCSN 1 0 Output SDRAM chip select Low SDDQM 7 0 Output SDRAM data mask Low DQM 7 corresponds to DATA 63 56 DQM 6 corresponds to DATA 55 48 DQM 5 corresponds to DATA 47 40 DQM 4 corresponds to DATA 39 32 DQM 3 corresponds to DATA 31 24 DQM 2 corresponds to DATA 23 16 DQM 1 corresponds to DATA 15 8 DQM 0 corresponds to DATA 7 0 SDRASN Output SDRAM row address strobe Low SDWEN Output SDRAM write enable Low see GRLIB IP Library User s Manual 47 17 Library dependencies Table 419 shows libraries used when instantiating the core VHDL libraries
395. fer breakpoint registers The DSU contains two breakpoint registers for matching AHB addresses A breakpoint hit is used to freeze the trace buffer by automatically clearing the enable bit Freezing can be delayed by program ming the DCNT field in the trace buffer control register to a non zero value In this case the DCNT value will be decremented for each additional trace until it reaches zero after which the trace buffer is frozen A mask register is associated with each breakpoint allowing breaking on a block of addresses Only address bits with the corresponding mask bit set to 1 are compared during breakpoint detec tion To break on AHB load or store accesses the LD and or ST bits should be set 31 2 1 Break address reg BADDR 31 2 0 31 210 Break mask feg BMASK 31 2 LD ST Figure 62 Trace buffer breakpoint registers 31 2 Breakpoint address bits 31 2 31 2 Breakpoint mask see text 1 LD break on data load address 0 ST beak on data store address 25 6 10 Instruction trace control register The instruction trace control register contains a pointer that indicates the next line of the instruction trace buffer to be written 31 16 0 RESERVED IT POINTER Figure 63 Instruction trace control register 15 0 Instruction trace pointer Note that the number of bits actually implemented depends on the size of the trace buffer Vendor and device identifiers
396. fered in the internal FIFO and the burst transfer is completed on the master side If the read FIFO is disabled or the burst is to non prefetchable area the first access in the burst is performed and the master bus is kept by performing BUSY transfers On the slave side the splitted master that initiated the transfer is allowed in bus arbitration by asserting HSPLIT signal to the AHB controller When the splitted master re attempts the transfer the slave interface completes the burst transfer if the read data was prefetched to the read FIFO In case of burst to non prefetchable location or if the read FIFO is disabled the first access in the transfer is completed by returning read data and the transfer on the slave side is extended by asserting HREADY low while the next access in the burst transfer is started on the master side This sequence is repeated until the transfer ends on the slave side Special case is the read burst marked as instruction fetch indicated on HPROT signal in which case the prefetching on the master side is completed at the end of cache line cache line size for instruction fetch transfers is also configurable In case of error response on the master side the error response will be given for the same access on the slave side SPLIT and RETRY responses are re attempted until OKAY or ERROR response is received The slave interface gives thus only OKAY or ERROR response on the slave interface 2 2 3 AHB write transfers AHB AHB
397. figuration options via VHDL generics TABLE 464 SVGACTRL Generics Generic Function Allowed Range Default length Size of the pixel FIFO 3 1008 384 part Pixel FIFO part length 1 336 128 memtech Memory technology 0 NTECH 0 pindex APB slave index 0 NAPBSLV 1 0 paddr 12 bit MSB APB address 0 16 FFF 0 pmask APB address mask 0 16 FFF 16 FFFH hindex AHB master index 0 NAHBMST 1 0 hirq Interrupt number 0 NAHBIRQ 1 0 clkO Period of dynamic clock 0 in ns 0 16 FFFFFFFF 40000 clk1 Period of dynamic clock 1 in ns 0 16 FFFFFFFF 20000 clk2 Period of dynamic clock 2 in ns 0 16 FFFFFFFF 15385 clk3 Period of dynamic clock 3 in ns 0 16 FFFFFFFF 0 burstlen AHB burst length 2 8 8 58 6 Signal descriptions Below is a table with the VGA controller input output signals TABLE 465 Signals Sinal name Field Type Description Active Rst N A Input Global reset low Clk N A Input System clock Vegaclk N A Input Pixel clock Apbi Input APB slave input Apbo id Output APB slave output Vgao Hsyne Output Horizontal sync Vsync Output Vertical sync Csync Output Composite sync Blank Output Blanking Video_out_R 7 0 Output Video out Red Video_out_G 7 0 Output Video out Green Video_out_B 7 0 Output Video out Blue Ahbi Input AHB master input Ahbo Output AHB master output Clk_sel N A Output 2 bit clock selector
398. for each timer The interrupt pending bit in the control register of the underflown timer will be set and remain set until cleared by writing 0 To minimize complexity timers share the same decrementer This means that the minimum allowed prescaler division factor is ntimers 1 reload register ntimers where ntimers is the number of implemented timers i e 3 By setting the chain bit in the control register timer n can be chained with preceding timer n 1 Decre menting timer n will start when timer n 1 underflows Each timer can be reloaded with the value in its reload register at any time by writing a one to the load bit in the control register The last timer acts as a watchdog driving a watchdog output signal when expired when the wdog VHDL generic is set to a time out value larger than 0 250 31 3 Registers The core is programmed through registers mapped into APB address space The number of imple mented registers depend on number of implemented timers Table 228 General Purpose Timer Unit registers APB address offset Register 0x00 Scaler value 0x04 Scaler reload value 0x08 Configuration register 0x0C Unused 0x10 Timer 1 counter value register 0x14 Timer 1 reload value register 0x18 Timer 1 control register Ox1C Unused 0xn0 Timer n counter value register Oxn4 Timer n reload value register Oxn8 Timer n contro
399. for spw_enable Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured void spw_start struct spwvars spw Starts the GRSPW core the link start bit is set to 1 Table 358 Parameters for spw_start Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured void spw_stop struct spwvars spw Stops the GRSPW core the link start bit is set to 0 Table 359 Parameters for spw_start Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured int spw_setclockdiv struct spwvars spw Sets the clock divisor register with the clock divisor value stored in the spwvars struct Table 360 Return values for spw_setclockdiv Value Description 0 The function completed successfully 1 The new clock divisor value is illegal Table 361 Parameters for spw_setclockdiv Parameter Description should be configured spw Pointer to the spwvars struct associated with GRSPW core that Allowed range int spw_set_nodeadr struct spwvars spw 355 Sets the node address register with the node address value stored in the spwvars struct Table 362 Return values for spw_set_nodeadr Value Description 0 The fu
400. ft tapo_upd std_ulogic signal tapi_enl tapi_tdo std_ulogic signal tapo_inst std_logic_vector 7 downto 0 begin gnd lt 0 tckn lt not tck TAP Controller tap0 tap tech gt 0 port map rst tck tckn tms tdi tdo tapo_tck tapo_tdi tapo_inst tapo_rst tapo_capt tapo_shft tapo_upd open open tapi_enl tapi_tdo gnd User defined JTAG data registers end 492 63 63 1 63 2 USBDCL USB Debug Communication Link Overview The Universal Serial Bus Debug Communication Link USBDCL provides an interface between an USB 2 0 bus and an AMBA AHB bus An external High Full Speed Universal Transceiver Macro cell Interface UTMI with an 8 bit interface is needed to connect to the USB The USBDCL is an AHB master and provides read and write access to the whole AHB address space using a simple pro tocol over two USB bulk endpoints Figure 234 shows how the USBDCL should be connected to the UTMI AHB FPGA USB gt USBDCL lt gt UMI Figure 234 USBDCL connected to an external UTMI device Operation 63 2 1 System overview Figure 235 shows the internal structure of the USBDCL This section describes the function of the dif ferent blocks briefly The Speed Negotiation Engine SNE detects connection by monitoring VBUS on the USB connector When a steady 5 V voltage is detected the SNE waits for a reset and then starts the High speed nego ti
401. ft register IK oy ps2_data_sync Vv 0 shift_reg 1111 1111 Frame_error 1 rx_irq 1 Y y Parity 0 1 update parity flag 0 y W update FIFO i Idle Figure 24 Flow chart for the receiver state machine Transmitter operations The transmitter part of APBPS2 is enabled for through the transmitter enable TE bit in the PS 2 con trol register The PS 2 interface has a 16 byte transmission FIFO that stores commands sent by the CPU Commands are used to set the LEDs on the keyboard and the typematic rate and delay Type matic rate is the repeat rate of a key that is held down while the delay controls for how long a key has to be held down before it begins automatically repeating Typematic repeat rates delays and possible other commands are listed in table 72 If the TE bit is set and the transmission FIFO is not empty a transmission of the command will start The host will pull the clock line low for at least 100 us and then transmit a start bit the eight bit com mand an odd parity bit a stop bit and wait for an acknowledgement bit by the device When this hap pens an interrupt is generated Figure 25 shows the flow chart for the transmission state machine Clock generation A PS 2 interface should generate a clock of 10 0 16 7 KHz To generate the PS 2 clock APBPS2 divides the APB clock with either a fixed or
402. fy wrap around condition checking The width of the SIZE field may be made configurable by means of a VHDL generic In this case it should be set to 16 1 bits width 22 9 9 Transmit Channel Write Register CanTxWR R W Table 159 Transmit Channel Write Register 31 20 19 4 3 0 WRITE 19 4 WRITE Pointer to last written message 1 All bits are cleared to 0 at reset The WRITE field is written to in order to initiate a transfer indicating the position 1 of the last mes sage to transmit Note that it is not possible to fill the buffer There is always one message position in buffer unused Software is responsible for not over writing the buffer on wrap around i e setting WRITE READ The field is implemented as relative to the buffer base address scaled with the SIZE field 22 9 10 Transmit Channel Read Register CanTxRD R W Table 160 Transmit Channel Read Register 31 20 19 4 3 0 READ 19 4 READ Pointer to last read message 1 All bits are cleared to 0 at reset The READ field is written to automatically when a transfer has been completed successfully indicat ing the position 1 of the last message transmitted Note that the READ field can be use to read out the progress of a transfer Note that the READ field can be written to in order to set up the starting point of a transfer This should only be done while the transmit channel is not enabled Note that the READ field can be aut
403. g access to PROM SRAM and SDRAM areas by setting the corresponding EDAC enable bits in the MCFG3 register The equations below show how the EDAC checkbits are generated CBO DO D4 D D7 D8 DI Dll D14 D17 D18 D19 D21 D26 D28 D29 D31 CB1 DO D1 D2 D4 D D8 DRO D12 DTE DITA D18 D20 D22 D24 D26 D28 CB2 DO D3 D4 D7 DI D1O D13 D15 D16 D19 D20 D23 D25 D26 D29 D31 CB3 DO D1 D5 D D7 Dll D12 D13 D16 D17 D21 D22 D23 D27 D28 D29 CRA D2 D3 D4 DS D6 2 DF D114 D15 Dis D119 D20 D271 D22 D23 D30 D31 CBS D8 D9 DLO AADIL S D2 S DLIA DIA PP D15 A D24 Y D25 A D26 5 D27 A D28 D29 D30 D31 CB6 DO Dl D2 D3 D4 D5 D6 D7 D24 D25 D26 D27 D28 D29 D30 D31 27 11 195 If the SRAM is configured in 8 bit mode the EDAC checkbit bus CB 7 0 is not used but it is still possible to use EDAC protection Data is always accessed as words 4 bytes at a time and the corre sponding checkbits are located at the address acquired by inverting the word address bits 2 to 27 and using it as a byte address The same chip select is kept active A word written as four bytes to addresses 0 1 2 3 will have its checkbits at address OxFFFFFFF addresses 4 5 6 7 at OXFFFFFFE and so on All the bits up to the maximum bank size will be inverted while the same chip select is alway
404. g mode This register controls all processors in a multi processor system and is only accessible in the DSU memory map of processor 0 31 18 17 16 15 2 1 0 DM15 DM2 DMIDM ED15 T ED2 EDI EDO Figure 56 DSU Debug Mode Mask register 176 15 0 Enter debug mode EDx Force processor x into debug mode if any of processors in a multiprocessor system enters the debug mode If 0 the processor x will not enter the debug mode 31 16 Debug mode mask If set the corresponding processor will not be able to force running processors into debug mode even if it enters debug mode 25 6 4 DSU trap register The DSU trap register is a read only register that indicates which SPARC trap type that caused the processor to enter debug mode When debug mode is force by setting the BN bit in the DSU control register the trap type will be Oxb hardware watchpoint trap 31 13 12 11 4 3 0 RESERVED EM TRAP TYPE 0000 Figure 57 DSU trap register 11 4 8 bit SPARC trap type 12 Error mode EM Set if the trap would have cause the processor to enter error mode 25 6 5 Trace buffer time tag counter The trace buffer time tag counter is incremented each clock as long as the processor is running The counter is stopped when the processor enters debug mode and restarted when execution is resumed 31 29 0 00 DSU TIME TAG VALUE Figure 58 Trace buffer time tag counter The va
405. g register The time tag register contains a 32 bit counter that increments each clock when the trace buffer is enabled The value of the counter is stored in the trace to provide a time tag 31 0 TIME TAG VALUE Figure 12 Trace buffer time tag counter 10 3 5 Trace buffer breakpoint registers The DSU contains two breakpoint registers for matching AHB addresses A breakpoint hit is used to freeze the trace buffer by clearing the enable bit Freezing can be delayed by programming the DCNT field in the trace buffer control register to a non zero value In this case the DCNT value will be dec remented for each additional trace until it reaches zero after which the trace buffer is frozen A mask register is associated with each breakpoint allowing breaking on a block of addresses Only address bits with the corresponding mask bit set to 1 are compared during breakpoint detection To break on AHB load or store accesses the LD and or ST bits should be set Ai 2 1 0 Break address reg BADDR 31 2 0 0 ji 2 1 0 Break mask reg BMASK 31 2 LD ST Figure 13 Trace buffer breakpoint registers BADDR breakpoint address bits 31 2 BMASK Breakpoint mask see text LD break on data load address ST beak on data store address Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x017 For description of vendor and device identifiers see GRLIB
406. g the core VHDL libraries Table 448 Library dependencies Library TECHMAP Package GENCOMP Constants Imported unit s Description Technology contants Component declaration The core has the following component declaration library techmap use techmap gencomp all component regfile_3p generic tech integer wrfst integer port wclk 2 in std ul gic waddr in std wdata in std we in std_ulogic rclk in std_ulogic raddrl in std rel y cin std logic rdatal out std raddrZ 40 std re2 in std_ulogic rdata2 out std end component 0 numregs 0 abits _logic_vector abits _logic_vector dbits _logic_vector abits _logic_vector dbits _logic_vector abits _logic_vector dbits integer integer ownto ownto ownto ownto ownto ownto dbits integer 8 64 450 55 55 1 55 2 SDCTRL 32 64 bit PC133 SDRAM Controller Overview The SDRAM controller handles PC133 SDRAM compatible memory devices attached to 32 or 64 bit wide data bus The controller acts as a slave on the AHB bus where it occupies configurable amount of address space for SDRAM access The SDRAM controller function is programmed by writing to a configuration register mapped into AHB I O address space Chip select decoding is provided for two SDRAM banks SDRAM CONTROLLER ADDRESS 16 2 D 63 0
407. generics are one Otherwise the value is fixed to 0 The resulting EDAC bank size is 22EBSZ 22ROMBSZ 8kB Note that only the three lower quarters of the bank can be used for user data The EDAC checksums are placed in the upper quarter of the bank 228 29 5 Table 215 Memory configuration register 1 11 ROM write enable RW Enables writes to the PROM memory area When disabled writes to the PROM area will generate an ERROR response on the AHB bus 10 RESERVED 9 8 ROM data bus width RBW Sets the PROM data bus width 00 8 bit 10 32 bit others reserved RESERVED ROM waitstates ROMWS Sets the number of waitstates for accesses to the PROM area Only available if the wsreg generic is set to one Table 216 Memory configuration register 2 31 13 12 9 8 7 6 5 4 3 2 1 0 RESERVED RAMBSZ RW RESERVED RAMW 31 13 RESERVED 12 9 RAM bank size RAMBSZ Sets the number of waitstates for accesses to the RAM area Only available if the banksz VHDL generic is set to zero Otherwise the banksz VHDL generic sets the bank size and the value can be read from this field 0 8 kB 1 16 kB 15 256 MB 8 7 RESERVED Read modify write enable RW Enables read modify write cycles for write accesses Only availa ble if the rmw VHDL generic is set to one 5 RESERVED 1 RAM waitstates RAMW Sets the number of waitstates for accesses to the RAM area Only avail able
408. gh TX_ER Output Transmit error High MDC Output MDIO clock MDIO_O Output MDIO output data MDIO_OE Output MDIO output enable High METHI N A Input MII output signals from master MAC METHO N A Output MII input signals to master MAC DETHI N A Input MII output signals from slave MAC DETHO N A Output MII input signals to slave MAC See ETHI and ETHO definitions 300 36 6 Library dependencies Table 315 shows libraries used when instantiating the core VHDL libraries Table 315 Library dependencies Library Package Imported unit s Description GAISLER NET Signals component Ethernet signals and component declaration 36 7 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler net all entity eth_arb_ex is port clk in std_ulogic rstn in std_ulogic Ethernet signals ethi in std_ulogic etho out std_ulogic i end architecture rtl of eth_arb_ex is signal edcli edcl_in_type MII signals signal ethil ethi2 eth_in_type signal ethol etho2 eth_out_type AMBA signals signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none begin AMBA Components are instantiat
409. gic writen inout std_logic brdyn Hiin std_logic bexcn in std_logic sdram 1 f sdcke out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect memory controller and memory bus signal memi memory_in_ type signal memo memory_out_type signal sdo sdram_out_type signal wprot wprot_out_type dummy signal not used signal clkm rstn std_ulogic system clock and reset signals used by clock and reset generators signal cgi clkgen_in_type signal cgo clkgen_out_type signal gnd std_ulogic begin Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 clk_div gt 2 sdramen gt 1 tech gt virtex2 sdinvclk
410. gle Executed normally Length must address ver be 4 or less Otherwise nothing is ify before done Same alignment restric writing no tions apply as for rmw No reply acknowledge is sent 0 1 1 1 0 1 Write incre Executed normally Length must menting be 4 or less Otherwise nothing is address ver done Same alignment restric ify before tions apply as for rmw If they writing no are violated nothing is done No acknowledge reply is sent 0 1 1 1 1 0 Write single Executed normally Length must address ver be 4 or less Otherwise nothing is ify before done and error code is set to 9 writing send Same alignment restrictions acknowledge apply as for rmw If they are vio lated nothing is done and error code is set to 10 If an AHB error occurs error code is set to 1 Reply is sent 0 1 1 1 1 1 Write incre Executed normally Length must menting be 4 or less Otherwise nothing is address ver done and error code is set to 9 ify before Same alignment restrictions writing send apply as for rmw If they are vio acknowledge lated nothing is done and error code is set to 10 If an AHB error occurs error code is set to 1 Reply is sent 1 0 Unused Stored to DMA channel 1 1 Unused Stored to DMA channel AMBA interface The AMBA interface consists of an APB interface an AHB master interface and DMA FIFOs The APB interface provides access to the user registers which are described in sect
411. gnal descriptlons sisene in oor neresen rens riveste bores Tek EDETS Ea EEES ENERE oE Eor RESAVA EEEE SEES OEE SE 449 54 4 Library dependencia ii 449 54 5 Component declaratoria 449 SDCTRL 32 64 bit PC133 SDRAM Controller ncicionionccinscomciaicic canaria 450 55 1 OV ELVIS Wisconsin ibis 450 55 2 Opera A eee kes es 450 55 3 REGISTERS rta tit 452 55 4 Vendor and device identifiers cinco lion eE E EE TR E E S EEEn 453 55 5 NN 454 55 6 St ON 455 55 7 Elbraty dependencies ai De ee ates 455 55 8 Instant aa ete t stage aia EN E 455 SRCTRL 8 32 bit PROM SRAM Controller oonnconicniconiconononinnananincnannnnoranoninonnanacanaccnness 458 56 1 OVEIVICW iis Sey iie aes eee TR 458 56 2 S DIt PROM ACCESS isa a 459 56 3 PROM SRAM Wave Mii A 459 56 4 A TS 460 56 5 RESISTORS cd ti o 460 56 6 Vendor and device identifleT oooconicnnncnnonncnnonnnoncnnnonncnnnon nono cono necnnonnn nn none rn enano nn cnn non neon non neon n cn nennncnnnnns 460 56 7 Configuration Options ieee et ta EEE E 460 56 8 Satake TRENN A E E E E 5 add Na 461 56 9 Library dependencies acia li 462 56 10 Component d clarations e asia eds ata aisha ti 462 56 11 NN 462 SSRCTRL 32 bit SSRAM PROM Controller oooconcociconononinonincnnanincnaccnnacanonnonnanananac nnoss 465 57 1 O cece HATA RHA Ms ES EE TE oe eas ae sith T 465 57 2 SSRAM PROM waveform cceececesecsecseeesecesesecseceseceeceseeeceseeeeseseseeecaessaecaeesaecaecsaeeseesseeeseeeeaeeegs 465 57 3 RESISTE
412. gnaled from a fault tol erant core The status register and the failing address register are accessed from the AMBA APB bus Operation The registers monitor AMBA AHB bus transactions and store the current HADDR HWRITE HMASTER and HSIZE internally The monitoring are always active after startup and reset until an error response HRESP 01 is detected When the error is detected the status and address register contents are frozen and the New Error NE bit is set to one At the same time an interrupt is gener ated The interrupt is generated on the line selected by the pirg VHDL generic The interrupt is usually connected to the interrupt controller to inform the processor of the error con dition The normal procedure is that an interrupt routine handles the error with the aid of the informa tion in the status registers When it is finished it resets the NE bit and the monitoring becomes active again Not only error responses on the AHB bus can be detected Many of the fault tolerant units containing EDAC have a correctable error signal which is asserted each time a single error is detected When such an error is detected the effect will be the same as for an AHB error response The only difference is that the Correctable Error CE bit in the status register is set to one when a single error is detected When the CE bit is set the interrupt routine can acquire the address containing the single error from the failing address reg
413. gnals Ethernet signals 34 14 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler ethernet_mac all entity greth_ex is port clk in std_ulogic rstn in std_ulogic ethernet signals ethi in eth_in_type etho in eth_out_type i end architecture rtl of greth_ex is AMBA signals signal apbi signal apbo signal ahbmi apb_slv_in_type apb_slv_out_vector others gt apb_none ahb_mst_in_type signal ahbmo begin a hb_mst_out_vector others gt ahbm_none AMBA Components are instantiated here GRETH el greth generic map hindex pindex paddr pirg memtech mdcscaler enable_mdio fifosize nsync edcl edclbufsz macaddrh macaddrl ipaddrh ipaddrl port map rst EJ ahbmi ahbmo apbi apbo ethi etho i end gt inferred gt 50 gt j gt 32 gt gt J gt 8 gt 16 00005E gt 16 00005D gt 16 c0a8 gt 16 0035 rstn Clik ahbmi ahbmo 0 apbi apbo 12 ethi etho 283 284 35 35 1 35 2 GRETH_GBIT Gigabit Ethernet Media Access Controller MAC w EDCL Overview Gaisler Research s Gigabit Ethernet Media Access Controller GRETH_GBIT provides an interface between an AMBA AHB bus and an Ethernet network It supports 10 100 1000 Mbit
414. h and device identifier 0x052 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 42 shows the configuration options of the core VHDL generics Table 42 Configuration options Generic Function Allowed range Default pindex APB slave index 0 NAHBSLV 1 0 paddr APB address 0 16 FFFH 0 pmask APB address mask 0 16 FFFH 16 FFFH pirq Interrupt line driven by the core 0 16 FFFH 0 nftslv Number of FT slaves connected to the cerror vector 1 NAHBSLV 1 3 Signal descriptions Table 43 shows the interface signals of the core VHDL ports Table 43 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBMI Input AHB slave input signals AHBSI i Input AHB slave output signals STATI CERROR Input Correctable Error Signals High APBI Input APB slave input signals APBO e Output APB slave output signals see GRLIB IP Library User s Manual Library dependencies Table 44 shows libraries used when instantiating the core VHDL libraries Table 44 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MISC Component Component declaration 9 8 53 Instantiation This examples shows how the core can be instantiated The example design
415. h a total of 15 asynchronous interrupts The inter rupt interface provides functionality to both generate and acknowledge interrupts 44 1 7 AMBA interface The cache system implements an AMBA AHB master to load and store data to from the caches The interface is compliant with the AMBA 2 0 standard During line refill incremental burst are gener ated to optimise the data transfer 44 1 8 Power down mode The LEON3 processor core implements a power down mode which halts the pipeline and caches until the next interrupt This is an efficient way to minimize power consumption when the application is idle and does not require tool specific support in form of clock gating To implement clock gating a suitable clock enable signal is produced by the processor 44 1 9 Multi processor support LEONJ3 is designed to be use in multi processor systems Each processor has a unique index to allow processor enumeration The write through caches and snooping mechanism guarantees memory coherency in shared memory systems 44 1 10 Performance Using 8K 8K caches and a 16x16 multiplier the dhrystone 2 1 benchmark reports 1 500 iteration s MHz using the gcc 3 4 4 compiler 02 This translates to 0 85 dhrystone MIPS MHz using the VAX 11 780 value a reference for one MIPS 371 44 2 LEONS3 integer unit 44 2 1 Overview The LEON3 integer unit implements the integer part of the SPARC V8 instruction set The implemen tation is focused on high perf
416. hat it can generate an extra waitstate This happens if the read is followed by an odd numbered read in a burst sequence of reads or if a subword write follows These situations are very rare during normal operation so the total timing impact is negligible The aramo ce signal is normally used to generate interrupts which starts an interrupt routine that corrects errors 183 Since this is not necessary when autoscrubbing is enabled aramo ce should not be connected to an AHB status register or the interrupt should be disabled in the interrupt controller 26 3 Registers The core is programmed through registers mapped into APB address space Table 192 FTAHBRAM registers APB Address offset Register 0x0 Configuration Register Table 193 Configuration Register 31 13 8 12 8 13 12 10 9 8 7 6 0 SEC MEMSIZE WB RB EN TCB 12 8 13 Single error counter SEC Incremented each time a single error is corrected includes errors on 12 10 checkbits Each bit can be set to zero by writing a one to it This feature is only available if the errc nten VHDL generic is set Log2 of the current memory size Write Bypass WB When set the TCB field is stored as check bits when a write is performed to the memory Read Bypass RB When set during a read or subword write the check bits loaded from memory are stored in the TCB field EDAC Enable EB When set the EDAC is used otherwise it is bypassed dur
417. he SPARC standard Using the LDA STA instructions alternative address spaces can be accessed The table shows the ASI usage for LEON Only ASI 5 0 are used for the mapping ASI 7 6 have no influence on operation Table 394 ASI usage ASI Usage 0x01 Forced cache miss 0x02 System control registers cache control register 0x08 0x09 OxOA 0x0B Normal cached access replace if cacheable 0x0C Instruction cache tags 0x0D Instruction cache data Ox0E Data cache tags OxOF Data cache data 0x10 Flush instruction cache 0x11 Flush data cache 44 2 13 Power down The processor can be configured to include a power down feature to minimize power consumption during idle periods The power down mode is entered by performing a WRASR instruction to asr19 wr g0 Sasrl9 During power down the pipeline is halted until the next interrupt occurs Signals inside the processor pipeline and caches are then static reducing power consumption from dynamic switching 44 2 14 Processor reset operation The processor is reset by asserting the RESET input for at least 4 clock cycles The following table indicates the reset values of the registers which are affected by the reset All other registers maintain their value or are undefined Table 395 Processor reset values Register Reset value PC program counter 0x0 nPC next program counter 0x4 PSR processor status register ET 0 S 1 By
418. he mask This allows for triggering on any specific value or range Furthermore each level has a match counter and a boolean equality flag The equality flag specifies whether a match means that the pattern should equal the traced signals or that it should not be equal It is possible to configure the trig ger engine to stay at a certain level while the traced signals have a certain value using this flag The match counter is a 6 bit counter which can be used to specify how many times a level should match before proceeding to the next This is all run time configurable through registers described in the reg ister section To specify post center or pre triggering mode the user can set a counter register that controls when the sampling stops relative to the triggering event It can be set to any value in the range 0 to depth 1 thus giving total control of the trace buffer content To support the tracing of slowly changing siganls the logic analyzer has a 16 bit sample frequency divider register that controls how often the siganls are sampled The default divider value of 1 will sample the siganls every clock cycle The usequal configuration option has a similar purpose as the sample frequency divider The user can define one of the traced signals as a qualifier bit that has to have a specified value for the current sig nals to be stored in the trace buffer This makes sampling of larger time periods possible if only some easily distinguished sample
419. he used memory area has the following address map Note that all 1553 data is 16 bit wide and will occupy two byte addresses Every sub address needs memory to hold up to 32 16 bit words Table 108 Memory map for 1553 data Address Content 0x000 0x03F RX transfer status words 0x040 0x07F Receive sub address 1 0x780 0x7BF Receive sub address 30 0x7C0 0x7FF TX transfer status words 0x800 0x83F Not used 0x840 0x87F Transfer sub address 1 OxF80 0xFBF Transfer sub address 30 OxFCO OxFFF Not used The AMBA AHB protection control signal HPROT is driven permanently with 0011 i e a not cacheable not bufferable privileged data access The AMBA AHB lock signal HLOCK is driven with 0 Registers The core is programmed through registers mapped into APB address space Table 109 B1553RT registers APB Address offset Register 0x00 Status 0x04 Control 0x08 Vector word 0x0C Interrupt vector 0x10 AHB page address register Status register read only 31 2 1 0 RESERVED rtaderr memfail busy Figure 45 Status register 2 RT address error Connected to the rtaderr output pin on Core1553BRT Memory failure Shows the value of the memfail output from Core1553BRT 0 Busy Shows the value of the busy output from Core1553BRT em 115 Control register 31 19 18 17 16 15 14 13 12 87 6 5 4 3 2 1 0 RESERVED sa30loop beasten intenbbr
420. he user into the correct byte address location The fifth byte corresponds to the EDAC checksum and is located in the upper part of the effective memory area as explained in detail in the definition of the MCFG1 memory configuration register The EDAC checksums are located in the upper quarter of what is defined as available EDAC area by means of the EBSZ field and the ROMBSZ field or rombanksz VHDL generic When set to 0 the size of the available EDAC area is defined as the PROM bank size When set to 1 as twice the PROM bank size When set to 2 as four times the PROM bank size And when set to 3 as eight times the PROM bank size For any other value than 0 the use of multiple PROM banks is required Example if ROMBSZ 10 and EBSZ 1 the EDAC area is 8kB 2 ROMBSZ 24EBSZ 16MB 0x01000000 The checksum byte for the first word located at address 0x00000000 to 0x00000003 is located at OxOO0CO0000 The checksum byte for the second word located at address 221 0x00000004 to 0x00000007 is located at O0x00C00001 and so on Since EBSZ 1 two PROM banks are required for implementing the EDAC area each bank with size 8MB 0x00800000 29 2 2 Access errors The active low Bus Exception signal BEXCN can be used to signal access errors It is enabled by setting the BEXCEN bit in MCFG1 and is active for all areas The BEXCN signal is sampled on the same cycle as read data is sampled For writes it is sampled on the last rising edge before writen rwen is
421. hey will not be removed during synthesis if the output they drive is used in the design S bit PROM access The SRCTRL controller can be configured to access a 8 bit wide PROM The data bus of external PROM should be connected to the upper byte of the 32 bit data bus i e D 31 24 The 8 bit mode is enabled with the prom8en VHDL generic When enabled read accesses to the PROM area will be done in four byte bursts The whole 32 bit word is then presented on the AHB data bus Writes should be done one byte at a time and the byte should always be driven on bit 31 24 on the AHB data bus independent of the byte address It is possible to dynamically switch between 8 and 32 bit PROM mode using the BWIDTH 1 0 input signal When BWIDTH is 00 then 8 bit mode is selected If BWIDTH is 10 then 32 bit mode is selected Other BWIDTH values are reserved for future use SRAM access is not affected by the 8 bit PROM mode PROM SRAM waveform Read accesses to 32 bit PROM and SRAM has the same timing see figure below datal data2 lead out A ROMSN RAMSN OEN D Figure 225 32 bit PROM SRAM IO read cycle The write access for 32 bit PROM and SRAM can be seen below lead in data lead out A RAMSN R e N O ESE RWEN ass sc CSI TNT E D Figure 226 32 bit PROM SRAM IO write cycle 460 56 4 56 5 56 6 56 7 If waitstates are configured through the VHDL generics one extra dat
422. hose that should go to the DMA channel Packets that are determined to be EDCL packets are not processed by the receive DMA channel When the packets are checked to be correct the AHB operation is performed The operation is per formed with the same AHB master interface that the DMA engines use The replies are automatically sent by the EDCL transmitter when the operation is finished It shares the Ethernet transmitter with the transmitter DMA engine but has higher priority 34 6 2 EDCL protocols The EDCL accepts Ethernet frames containing IP or ARP data ARP is handled according to the pro tocol specification with no exceptions IP packets carry the actual AHB commands The EDCL expects an Ethernet frame containing IP UDP and the EDCL specific application layer parts Table 297 shows the IP packet required by the EDCL The contents of the different protocol headers can be found in TCP IP literature Table 297 The IP packet expected by the EDCL Ethernet IP UDP 2B 4B 4B Data 0 242 Ethernet Header Header Header Offset Control word Address 4B Words CRC The following is required for successful communication with the EDCL A correct destination MAC address as set by the generics an Ethernet type field containing 0x0806 ARP or 0x0800 IP The IP address is then compared with the value determined by the generics for a match The IP header checksum and identification fields are not checked There are a few r
423. hould be connected to SA 12 0 the bank address to SA 14 13 and the data bus to SD 31 0 or SD 63 0 if 64 bit data bus is used 55 2 9 Data bus The external SDRAM data bus is configurable to either 32 or 64 bits width using the sdbits generic 64 bit data bus allows 64 bit SO DIMS to be connected using the full data capacity of the devices The polarity of the output enable signal to the data pads can be selected with the oepol generic Some times it is difficult to fulfil the output delay requirements of the output enable signal In this case the vbdrive signal can be used instead of bdrive Each index in this vector is driven by a separate register and a directive is placed on them so that they will not be removed by the synthesis tool 55 2 10 Clocking The SDRAM controller is designed for an external SDRAM clock that is in phase or slighly earlier than the internal AHB clock This provides the maximum margin for setup and hold on the external signals and allows highest possible frequency For Xilinx and Altera device the GRLIB Clock Gen erator CLKGEN can be configured to produce a properly synchronised SDRAM clock For other FPGA targets the custom clock synchronization must be designed or the inverted clock option can be used see below For ASIC targets the SDRAM clock can be derived from the AHB clock with proper delay adjustments during place amp route If the VHDL generic INVCLK is set then all outputs from the SDRAM cont
424. hows how the ATA controller should be connected AHB FPGA IDE lt gt ATA Signals ATACTRL DEVICE Figure 36 ATACTRL connected to an IDE device Operation 17 2 1 System overview Figure 37 shows a block diagram of the ATACTRL core The AHB Slave block contains control reg isters for the ATA controller and handles the AHB communication The ATA controller block handles the timing control and data transfer to and from the IDE device A write access to the register in the core is done with no wait states while a read access has one wait state When the ATA device is accessed the controller blocks the AHB bus until the transfer is completed AHB ATACTRL ATA signals gt AHB Slave ATA Controller lt Interface lt gt Figure 37 Block diagram of the internal structure of the ATACTRL 17 2 2 Device hardware reset Bit 0 in the core control register controls the reset signal to the ATA device When this bit is set to 1 the reset signal is asserted After system reset this bit is set to 1 The hardware reset procedure should follow this protocol 1 Set the ATA reset bit to 1 and wait for at least 25 us 17 3 95 2 Set the ATA reset bit to 0 and wait for at least 2 ms 3 Read the ATA status register until the busy bit is cleared 4 Execute an Identify device or an Identify packet device command for all conne
425. hrough the RDASR instruction and has the following layout 31 28 17 1615 14 13 1211109 8 7 54 0 asr17 INDEX RESERVED CS CF DWI SV LD FPU M V8 NWP NWIN Figure 168 LEON3 configuration register asr17 Field Definitions 31 28 Processor index In multi processor systems each LEON core gets a unique index to support enumeration The value in this field is identical to the hindex generic parameter in the VHDL model value in this field is identical to the hindex generic parameter in the VHDL model 17 Clock switching enabled CS If set switching between AHB and CPU frequency is available 16 15 CPU clock frequency CF CPU core runs at CF 1 times AHB frequency 14 Disable write error trap DWT When set a write error trap tt 0x2b will be ignored Set to zero after reset 13 Single vector trapping SVT enable If set will enable single vector trapping Fixed to zero if SVT is not implemented Set to zero after reset 12 Load delay If set the pipeline uses a 2 cycle load delay Otherwise a 1 cycle load delay i s used Generated from the ddel generic parameter in the VHDL model 11 10 FPU option 00 no FPU 01 GRFPU 10 Meiko FPU 11 GRFPU Lite 9 If set the optional multiply accumulate MAC instruction is available 8 If set the SPARC V8 multiply and divide instructions are available 7 5 Number of implemented wat
426. hus easier to find them and place constraints on them The fact there are three clock domains in the GRSPW of which all are possibly high frequency clocks makes it necessary to declare all paths between the clock domains as false paths In Synplify this is most easily done by declaring all the clocks to be in different clockgroups in the sde file Gf Synplify does not automatically put them in different groups This will disable any timing considerations between the clock domains and these constraints will also propagate to the place and route tool The type of clock buffer is selectable with a VHDL generic and the value zero provides a normal feed through which lets the synthesis tool infer the type of net used Registers The core is programmed through registers mapped into APB address space Table 334 GRSPW registers APB address offset Register 0x0 Control 0x4 Status Interrupt source 0x8 Node address OxC Clock divisor 0x10 Destination key 0x14 Time 0x18 Timer and Disconnect 0x20 DMA channel 1 control status 0x24 DMA channel 1 rx maximum length 0x28 DMA channel 1 transmit descriptor table address 0x2C DMA channel 1 receive descriptor table address 336 31 30 29 28 18 17 16 15 11 10 9 8 7 6 5 4 32 10 RARX RC RESERVED RD RE TR TT LI TQ RS PM TI IE ASLS LD O Link Disable LD Disable the Space Wire codec Reset value 0
427. ia Keyboard APBPS2 a y Clock 0 S2Clk Figure 22 APBPS2 electrical interface PS 2 data is sent in 11 bits frames The first bit is a start bit followed by eight data bits one odd parity bit and finally one stop bit Figure 23 shows a typical PS 2 data frame Data frame with parity Start DO D1 D2 D3 D4 D5 D6 D7 Parity Stop Figure 23 PS 2 data frame Receiver operation The receiver of APBPS2 receives the data from the keyboard or mouse and converts it to 8 bit data frames to be read out via the APB bus It is enabled through the receiver enable RE bit in the PS 2 control register If a parity error or framing error occurs the data frame will be discarded Correctly received data will be transferred to a 16 byte FIFO The data ready DR bit in the PS 2 status register will be set and retained as long as the FIFO contains at least one data frame When the FIFO is full the receiver buffer full RF bit in the status register is set The keyboard will be inhibited and buffer data until the FIFO gets read again Interrupt is sent when a correct stop bit is received then it s up to the software to handle any resend operations if the parity bit is wrong Figure 24 shows a flow chart for the operations of the receiver state machine 74 14 3 14 4 Data f Stop ps2_clk_fall update shi
428. iates an action supported by the core Table 115 Bit interpretation of command register CMR address 1 Bit Name Description CMR 7 reserved CMR 6 reserved CMR 5 reserved CMR 4 not used go to sleep in SJA1000 core CMR 3 Clear data overrun Clear the data overrun status bit CMR 2 Release receive buffer Free the current receive buffer for new reception CMR 1 Abort transmission Aborts a not yet started transmission CMR 0 Transmission request Starts the transfer of the message in the TX buffer A transmission is started by writing 1 to CMRO O It can only be aborted by writing 1 to CMR 1 and only if the transfer has not yet started If the transmission has started it will not be aborted when set ting CMR 1 but it will not be retransmitted if an error occurs Giving the Release receive buffer command should be done after reading the contents of the receive buffer in order to release this memory If there is another message waiting in the FIFO a new receive interrupt will be generated if enabled and the receive buffer status bit will be set again To clear the Data overrun status bit CMR 3 must be written with 1 123 21 4 4 Status register The status register is read only and reflects the current status of the core Table 116 Bit interpretation of status register SR address 2 Bit Name Description SR 7 Bus status 1 when the core is in bus off and
429. ic information The core can be partition in the following hierarchical elements e Elliptic Curve Cryptography ECC core e AMBA APB slave e GRLIB plug amp play wrapper Note that the core can also be used without the GRLIB plug amp play information Operation Elliptic Curve Cryptography ECC is an asymmetric cryptographic approach also known as public key cryptography that applies different keys for encryption and decryption The most expensive operation during both encryption and decryption is the elliptic curve point multiplication Hereby a point on the elliptic curve is multiplied with a long integer k P multiplication The bit sizes of the coordinates of the point P x y and the factor k have a length of hundreds of bits In this implementation the key and the point lengths are 233 bit so that for every key there are 8 write cycles necessary and for every point consisting of x and y there are 16 write cycles necessary After at least 16700 clock cycles the result can be read out 33 3 33 4 33 5 261 The key is input via eight registers The input point P x y is written via eight registers for x and eight registers for y After the last y input register is written the encryption or decryption is started The progress can be observed via the status register When the operation is completed an interrupt is generated The output point P x y is then read out via eight registers for x and eight registers for
430. ic operation completes A write access will be terminated with an AMBA AHB error response till the Data Input Register 3 has been written and the with an AMBA AHB retry response till the operation completes Any read access to this register results in an AMBA AHB error response 32 7 2 Debug Register R Table 240 Debug Register 31 0 FSM 31 0 FSM Finite State Machine Any write access to this register results in an AMBA AHB error response 32 7 3 Data Input Registers W Table 241 Data Input O Register 31 Data Key 127 downto 96 Table 242 Data Input 1 Register 31 Data Key 95 downto 64 Table 243 Data Input 2 Register 31 Data Key 63 downto 32 Table 244 Data Input 3 Register 31 Data Key 31 downto 0 257 Note that these registers can only be written with a key after a key will be input command has been written to the control register Note that the registers must then be written in sequence and all four registers must be written else the core ends up in an undefined state Note that these registers can only be written with data after a data will be input command has been written to the control register else an AMBA AHB error response is given Note that the registers must then be written in sequence and all four registers must be written else the core ends up in an undefined state The encryption or decryption operation is started when
431. ight create a 1 2 2 critical path on targets with slow data cache memories A 2 cycle delay can improve timing but will reduce performance with about 5 disas Print instruction disassembly in VHDL simulator console 0 1 tbuf Size of instruction trace buffer in kB 0 instruction trace dis 0 64 abled pwd Power down 0 disabled 1 area efficient 2 timing efficient 0 2 1 svt Enable single vector trapping 0 1 0 rstaddr Default reset start address 0 2 20_1 0 smp Enable multi processor support 0 15 0 390 44 12 Signal descriptions Table 403 shows the interface signals of the core VHDL ports Table 403 Signal descriptions Signal name Field Type Function Active CLK N A Input AMBA and processor clock leon3s leon3cg CLK2 Input Processor clock in 2x mode leon3sx2 GCLK2 Input Gated processor clock in 2x mode leon3sx2 RSTN N A Input Reset Low AHBI X Input AHB master input signals AHBO Output AHB master output signals AHBSI Input AHB slave input signals IRQI IRL 3 0 Input Interrupt level High RST Input Reset power down and error mode High RUN Input Start after reset SMP system only IRQO INTACK Output Interrupt acknowledge High IRL 3 0 Output Processor interrupt level High DBGI Input Debug inputs from DSU DBGO Output Debug outputs to DSU GCLK Input Gated processor clock for leon3cg see GRLIB IP Library User s Ma
432. ignal bout b1553_out_type bols53_0 4 Bi553bs generic map hindex gt 2 pindex gt 12 paddr gt port map rstn clkm bin bout apbi apbo 12 12 pirg gt 2 ahbmi ahbmo 2 105 106 19 19 1 B1553BRM AMBA plug amp play interface for Actel Core1553BRM Overview The interface provides a complete Mil Std 1553B Bus Controller BC Remote Terminal RT or Monitor Terminal MT The interface connects to the MIL STD 1553B bus through external trans ceivers and transformers The interface is based on the Actel Core1553BRM core The interface consists of six main blocks 1553 encoder 1553B decoders a protocol controller block AMBA bus interface command word legality interface and a backend interface The interface can be configured to provide all three functions BC RT and MT or any combination of the three All variations use all six blocks except for the command legalization interface which is only required on RT functions that implement RT legalization function externally A single 1553 encoder takes each word to be transmitted and serializes it using Manchester encoding The encoder also includes independent logic to prevent the interface from transmitting for greater than the allowed period as well as loopback fail logic The loopback logic monitors the received data and verifies that the interface has correctly received every word that it transmits The output of the encoder is gated with the bus en
433. igure 141 SpaceWire Receive descriptor Address offsets are shown in the left margin 42 4 5 Setting up the DMA control register To final step to receive packets is to set the control register in the following steps The receiver must be enabled by setting the rxen bit in the DMA control register see section 42 9 This can be done anytime and before this bit is set nothing will happen The rxdescav bit in the DMA control register is then set to indicate that there are new active descriptors This must always be done after the descrip tors have been enabled or the GRSPW might not notice the new descriptors More descriptors can be activated when reception has already started by enabling the descriptors and writing the rxdescav bit When these bits are set reception will start immediately when data is arriving 42 4 6 The effect to the control bits during reception When the receiver is disabled all packets going to the DMA channel are discarded If the receiver is enabled the next state is entered where the rxdescav bit is checked This bit indicates whether there are active descriptors or not and should be set by the external application using the DMA channel each time descriptors are enabled as mentioned above If the rxdescav bit is 0 and the nospill bit is 0 the packets will be discarded If nospill is one the grspw waits until rxdescav is set When rxdescav is set the next descriptor is read and if enabled the packet is received to
434. ill be to next word address 31 30 AHB Data AHB write read data For byte and half word transfers data is aligned according to big endian order where data with address offset 0 data is placed in MSB bits 44 6 3 6 4 6 5 Registers The core does not implement any registers mapped in the AMBA AHB or APB address space Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x01C For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 30 shows the configuration options of the core VHDL generics Table 30 Configuration options Generic Function Allowed range Default tech Target technology 0 NTECH 0 hindex AHB master index 0 NAHBMST 1 0 nsync Number of synchronization registers between clock 1 2 1 regions idcode JTAG IDCODE instruction code generic tech only 0 255 id_msb JTAG Device indentification code MSB bits generic 0 65535 tech only id_Isb JTAG Device indentification code LSB bits generic tech 0 65535 0 only idcode JTAG IDCODE instruction generic tech only 0 255 ainst Code of the JTAG instruction used to access JTAG 0 255 Debug link command address register dinst Code of the JTAG instruction used to access JTAG 0 255 3 Debug link data register 6 6 6 7 6 8 Signal descriptions Table 31 shows the interface signals of the core VH
435. imer counter value register when 1 is written to load bit in the timers control register or when the RS bit is set in the control register and the timer underflows Any unused most significant bits are reserved Always reads as 000 0 Table 234 General Purpose Timer Unit Configuration Register 31 7 6 5 4 3 2 1 0 000 0 DH CH IP IlE LD RS EN 31 7 Reserved Always reads as 000 0 6 Debug Halt DH Value of GPTI DHALT signal which is used to freeze counters e g when a sys tem is in debug mode Read only 5 Chain CH Chain with preceding timer If set for timer n decrementing timer n begins when timer n 1 underflows 4 Interrupt Pending IP Sets when an interrupt is signalled Remains 1 until cleared by writing 0 to this bit Interrupt Enable IE If set the timer signals interrupt when it underflows Load LD Load value from the timer reload register to the timer counter value register Restart RS If set the timer counter value register is reloaded with the value of the reload register when the timer underflows 0 Enable EN Enable the timer 31 4 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x011 For description of vendor and device identifiers see GRLIB IP Library User s Manual 252 31 5 31 6 Configuration options Table 235 shows the configuration options of the core VHDL
436. ination 12 Enable EN Enable transmitter descriptor When all control fields address length wrap and crc are set this bit should be set While the bit is set the descriptor should not be touched since this might corrupt the transmission The GRSPW clears this bit when the transmission has finished 13 Wrap WR If set the descriptor pointer will wrap and the next descriptor read will be the first one in the table at the base address Otherwise the pointer is increased with 0x10 to use the descriptor at the next higher memory location 14 Interrupt Enable IE If set an interrupt will be generated when the packet has been transmitted and the transmitter interrupt enable bit in the DMA control register is set 15 Link Error LE A Link error occurred during the transmission of this packet 16 Calculate CRC CC If set two CRC values according to the RMAP specification will be generated and appended to the packet The first CRC will be appended after the data pointed to by the header address field and the second is appended after the data pointed to by the data address field 31 0 Header Address Address from where the packet header is fetched Does not need to be word aligned 23 0 Data Length Length of data part of packet If set to zero no data will be sent If both data and header lengths are set to zero no packet will be sent 31 0 Data Address Address from where data is read Does not need to be word aligne
437. ing an operation resulting in one of following conditions e an operation raises IEEE floating point exception ftt IEEE_754_exception e g executing invalid operation such as 0 0 while the NVM bit of the TEM field id set invalid exception enabled e an operation on denormalized floating point numbers in standard IEEE mode raises unfinished_FPop floating point exception e sequence error abnormal error condition in the FPU due to the erroneous use of the floating point instructions in the supervisor software The trap is deferred to one of the floating point instruction FPop FP load store FP branch following the trap inducing instruction note that this may not be next floating point instruction in the program order due to exception detecting mechanism and out of order instruction execution in the GRFPC When the trap is taken the floating point deferred queue FQ contains trap inducing instruction and up to two FPop instructions that where dispatched in the GRFPC but did not complete 308 After the trap is taken the qne bit of the FSR is set and remains set until the FQ is emptied STDFQ instruction reads a double word from the floating point deferred queue the first word is the address of the instruction and the second word is the instruction code All instructions in the FQ are FPop type instructions First access to the FQ gives double word with trap inducing instruction following dou ble words contain pending floating point
438. ing device 0 IORDY enable 1 Compatible timing IORDY enable 0 ATA reset All bits except bit 0 are set to zero after reset Bit 0 is set to 1 The timing registers should be loaded with an appropriate value before any of bit 1 2 3 5 6 7 in the control register is set to 1 Bit 31 controls the power signal for CompactFlash cards When set to 1 the power signal is connected to Vcc This signal is used when the power to the CompactFlash card is controlled via a transistor in the design 96 The Status register has the following bit layout see table 91 Table 91 Status Register Bit Description 31 28 Device ID 0x02 27 24 Revision Number 0 23 16 Reserved 15 Reserved DMA transfer in progress 14 11 Reserved 10 Reserved DMA receive buffer empty 9 Reserved DMA transmit buffer full 8 Reserved DMARQ line status 7 PIO transfer in progress 6 Reserved PIO write ping pong full 5 1 Reserved 0 IDE interrupt status when set to 1 indicates that a device asserted its interrupt line The PIO timing registers have the following bit layout see table 92 Table 92 PIO Timing Register PCTR PFTRO PFTR1 Bit Description 31 24 End of Cycle Time Teoc 23 16 DIOW data hold T4 15 8 DIOR DIOW pulse width T2 7 0 Address valid to DIOR DIOW T1 All timing values are in ns per clock cycle minus 2 rounded up to the
439. ing edge Configuration options Table 468 shows the configuration options of the core VHDL generics Table 468 Configuration options Name Function Range Default tech Technology selection 0 NTECH 0 abits Address bits Depth of RAM is 24bits 1 see table below dbits Data width see table below Table 469 shows the supported technologies for the core Table 469 Supported technologies Tech name Technology RAM cell abit range dbit range altera All Altera devices altsyncram unlimited unlimited ihp15 THP 0 25 sram2k 512x32 2 9 unlimited inferred Behavioral description Tool dependent unlimited unlimited virtex Xilinx Virtex VirtexE Spartan2 RAMB4 Sn 2 12 unlimited virtex2 Xilinx Virtex2 Spartan3 Virtex4 RAMB16_Sn 2 14 unlimited Spartan3e axcel Actel AX RTAX RAM64K36 2 12 unlimited proasic Actel Proasic RAM256x9SST 2 14 unlimited proasic3 Actel Proasic3 ram4k9 ram512x18 2 12 unlimited lattice Lattice XP EC ECP sp8ka 2 13 unlimited memvirage Virage ASIC RAM hdss1_128x32cm4sw0 7 11 32 hdss1_256x32cm4sw0 hdss1_512x32cm4sw0 hdss1_1024x32cm8sw0 memartisan Artisan ASIC RAM sp_256x32m32 8 14 32 sp_512x32m32 sp_1kx32m32 sp_2kx32m32 sp_4kx32m32 sp_8kx32m32 sp_16kx32m32 482 59 3 59 4 59 5 59 6 Signal descriptions Table 470 shows the interface signals of the core VHDL ports Table 470 Signal descriptions
440. ing read and write Operations Test Check Bits TCB Used as checkbits when the WB bit is set during writes and loaded with the check bits during a read operation when the RB bit is set Any unused most significant bits are reserved Always read as 000 0 All fields except TCB are initialised at reset The EDAC is initally disabled EN 0 which also applies to diagnos tics fiels RB and WB are zero When available the single error counter SEC field is cleared to zero 26 4 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x050 For description of vendor and device identifiers see GRLIB IP Library User s Manual 184 26 5 Configuration options 26 6 26 7 Table 194 shows the configuration options of the core VHDL generics Table 194 Configuration options Generic Function Allowed range Default hindex Selects which AHB select signal HSEL will be used to 0 to NAHBMAX 1 0 access the memory haddr ADDR field of the AHB BAR 0 to 16 FFF 0 hmask MASK field of the AHB BAR 0 to 16 FFF 16 FFFH tech Memory technology 0 to NTECH 0 kbytes SRAM size in kbytes 1 to targetdep 1 pindex Selects which APB select signal PSEL will be used to 0 to NAPBMAX 1 0 access the memory configuration registers paddr The 12 bit MSB APB address 0 to 16 FFF 0 pmask The APB address mask 0 to 16 F
441. integer 0 ahbaddr integer range 0 to 16 FFFFF 0 clkspd integer range 0 to 3 1 rtaddr integer range 0 to 31 0 rtaddrp integer range 0 to 1 wrtcmd integer range 0 to E OL wrttsw integer range 0 to ge dy extmdata integer range 0 to 0 intenbbr integer range 0 to 0 bcasten integer range 0 to 1 sa30loop integer range 0 to 0 port rstn in std_ulogic clk in std_ulogic b1553i in b1553_in_type b15530 out b1553_out_type rti in rt1553_in_type rto out rt1553_out_type apbi in apb_slv_in_type apbo out apb_slv_out_type ahbi in ahb_mst_in_type ahbo out ahb_mst_out_type end component Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler b1553 all signal bin b1553_in_type signal bout b1553_out_type signal rti rt1553_in_type signal rto rt1553_out_type rt b1553rt generic map hindex gt 3 pindex gt 13 paddr gt 13 pmask gt 16 fff pirg gt 3 rtaddr gt 1 rtaddrp gt 0 sa30loop gt 1 port map rstn clkm bin bout rti rto apbi apbo 13 ahbmi ahbmo 3 119 rti useextok lt 0 120 21 21 1 21 2 21 3 CAN_OC GRLIB wrapper for OpenCores CAN Interface core Overview CAN_OC is GRLIB wrapper for the CAN core from Opencores It provides a bridge between AMBA AHB and the CAN Core registers The AHB slave interface is mapped i
442. inter to the spwvars struct associated with GRSPW core that should be set 42 16 2 GRSPW RMAP API The RMAP API contains only one function which is used for building RMAP headers int build_rmap_hdr struct rmap_pkt pkt char hdr int size Builds a RMAP header to the buffer pointed to by hdr The header data is taken from the rmap_pkt struct Table 385 Return values for build_rmap_hdr Value Description 0 The function completed successfully 1 One or more of the parameters contained illegal values Table 386 Parameters for build_rmap_hdr Parameter Description Allowed range pkt Pointer to a rmap_pkt struct which contains the data from which the header should be built hdr Pointer to the buffer where the header will be built spw Pointer to the spwvars struct associated with GRSPW core that should be set 360 Table 387 rmap_pkt struct fields Field Description Allowed Range type Selects the type of packet to build writecmd reademd rmwemd writerep readrep rmwrep verify Selects whether the data should be verified before writing yes no ack Selects whether an acknowledge should be sent yes no incr Selects whether the address should be incremented or not yes no destaddr Sets the destination address 0 255 destkey Sets the destination key 0 255 srcaddr Sets the source address 0 255 tid Sets the transaction identifier
443. interrupt taking into account all causes of the interrupt e Clear the handled interrupt using Pending Interrupt Clear Register Masking interrupts After reset all interrupt bits are masked since the Interrupt Mask Register is zero To enable generation of a module interrupt for an interrupt bit set the corresponding bit in the Inter rupt Mask Register Clearing interrupts All bits of the Pending Interrupt Register are cleared when it is read or when the Pending Interrupt Masked Register is read Reading the Pending Interrupt Masked Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register Selected bits can be cleared by writing ones to the bits that shall be cleared to the Pending Interrupt Clear Register 156 Forcing interrupts When the Pending Interrupt Register is written the resulting value is the original contents of the register logically OR ed with the write data This means that writing the register can force set an interrupt bit but never clear it Reading interrupt status Reading the Pending Interrupt Status Register yields the same data as a read of the Pending Interrupt Register but without clearing the contents Reading interrupt status of unmasked bits Reading the Pending Interrupt Masked Status Register yields the contents of the Pending Interrupt Register masked with the contents of the Interrupt Mask Register but without clearing the contents The i
444. ion 42 9 The DMA engines have 32 bit wide FIFOs to the AHB master interface which are used when reading and writ ing to the bus The transmitter DMA engine reads data from the bus in bursts which are half the FIFO size in length A burst is always started when the FIFO is half empty or if it can hold the last data for the packet The burst containing the last data might have shorter length if the packet is not an even number of bursts in size 42 8 333 The receiver DMA works in the same way except that it checks if the FIFO is half full and then per forms a burst write to the bus which is half the fifo size in length The last burst might be shorter There might be 1 to 3 single byte writes when writing the beginning and end of the received packets if the rmap or rxunaligned VHDL generics are set to 1 42 7 1 APB slave interface As mentioned above the APB interface provides access to the user registers which are 32 bits in width The accesses to this interface are required to be aligned word accesses The result is undefined if this restriction is violated 42 7 2 AHB master interface The GRSPW contains a single master interface which is used by both the transmitter and receiver DMA engines The arbitration algorithm between the channels is done so that if the current owner requests the interface again it will always acquire it This will not lead to starvation problems since the DMA engines always deassert their requests between
445. ion records are not mapped in the configuration area icheck Check bus index 0 1 1 busndx AHB bus number 0 Signal descriptions Table 26 shows the interface signals of the core VHDL ports Table 26 Signal descriptions Signal name Field Type Function Active RST N A Input AHB reset Low CLK N A Input AHB clock MSTI pe Output AMBA AHB master interface record array MSTO t Input AMBA AHB master interface record array vector SLVI Output AMBA AHB slave interface record array SLVO Input AMBA AHB slave interface record array vector see GRLIB IP Library User s Manual 40 5 7 5 8 5 9 Library dependencies Table 27 shows libraries used when instantiating the core VHDL libraries Table 27 Library dependencies Library GRLIB Package AMBA Imported unit s Description Types AMBA signal type definitions Component declaration library grlib use grlib amba all component ahbctrl generic defmast integer 0 default master split integer 0 split support rrobin integer 0 round robin arbitration timeout integer range 0 to 255 0 HREADY timeout ioaddr ahb_addr_type 16 fff I O area MSB address iomask ahb_addr_type lo fff I O area address mask cfgaddr ahb_addr_type l6 ff0 config area MSB address cfgmask ahb_addr_type 16 ff0 config area address maskk nahbm integer range 1 to NAHBMST NAHBMST num
446. ions Table 250 shows the interface signals of the core VHDL ports Table 250 Signal descriptions Signal name Field Type Function Active RSTN N A Input Reset Low CLK N A Input Clock AHBI Input AHB slave input signals AHBO i Output AHB slave output signals DEBUG 0 4 N A Output Debug information see GRLIB IP Library User s Manual Note that the AES core can also be used without the GRLIB plug amp play information The AMBA AHB signals are then provided as IEEE Std_Logic_1164 compatible scalars and vectors Library dependencies Table 251 shows libraries used when instantiating the core VHDL libraries Table 251 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER CRYPTO Component GRAES component declarations Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library use library use signal debug grlib grlib amba all gaisler gaisler crypto all GRAESO graes generic map hindex gt ioaddr gt iomask gt hirg gt port map rstn gt clk gt ahbi gt ahbo gt debug gt std_logic_vector 0 to 4 hindex ioaddr iomask hirq rstn clk ahbsi ahbso hindex debug 259 260 33 33 1 33 2 GRECC Elliptic Curve Cryptography Overview Elliptic
447. ions are made If incoming packet is an RMAP packet ID 0x01 and the command type field is 01b the packet is processed by the RMAP command handler which is described in section 42 6 Otherwise the packet is processed by the DMA engine as when RMAP is disabled At least 2 non EOP EEP N Chars needs to be received for a packet to be stored to the DMA channel If it is an RMAP packet with hardware RMAP enabled 3 N Chars are needed since the command byte determines where the packet is processed Packets smaller than these sizes are discarded 42 4 8 Status bits When the reception of a packet is finished the enable bit in the current descriptor is set to zero When enable is zero the status bits are also valid and the number of received bytes is indicated in the length field The DMA control register contains a status bit which is set each time a packet has been received The GRSPW can also be made to generate an interrupt for this event as mentioned in sec tion RMAP CRC is always checked for all packets when CRC logic is included in the implementation rmapcrc or rmap VHDL generic set to 1 If the received packet is not of RMAP type the CRC error indication bits in the descriptor should be ignored If the received packet is of RMAP type the bits are valid and the HC bit is set if a header CRC error was detected In this case the data CRC will not be calculated at all and the DC bit is undefined If the header CRC was correct the DC bit will also co
448. ircular buffer until a trigger condition occurs A trigger condition will freeze the buffer and the traced data can then be read out via an APB interface The depth and width of the trace buffer is configurable through VHDL generics as well as the number of trigger levels On chip Logic Analyzer core TE e Trace buffer nigger engine Bee PENERE On chip RAM i Write port Control unit with APB slave interface Read port AMBA APB Figure 176 On chip Logic Analyzer block diagram Operation 46 2 1 Trace buffer When the logic analyzer is armed the traced signals are sampled and stored to the trace buffer on the rising edge of the sample clock TCLK The trace buffer consists of a circular buffer with an index register pointing to the next address in the buffer to be written The index register is automatically incremented after each store operation to the buffer 46 2 2 Clocking LOGAN uses two clocks TCLK and the APB clock The trace signals are sampled on the rising edge of the sample clock TCLK while the control unit and the APB interface suse the APB clock TCLK and the APB clock does not need to be synchronized or have the same freqency 398 46 3 46 2 3 Triggering The logic analyzer contains a configurable number of trig levels Each trig level is associated with a pattern and a mask The traced signals are compared with the pattern only comparing the bits set in t
449. isc nnna a a E S E T E E a E E a 184 26 8 NN 185 FTMCTRL 8 16 32 bit Memory Controller with EDAC oooccnncccnnonnnonoconnnannnonnnconncconennnnos 186 27 1 OVV EW ane a e E E E a a teas E EEES 186 27 2 PROM ACCESS NO 186 27 3 Memory mapped LO iiss ieri ar aea aeaa aa aa EE aa aa tate a EEEa platos 188 27 4 SRAMacCesS cui ai Dio Ree 189 27 5 8 bit and 16 bit PROM and SRAM acces ccococccconconccnnconocnnonnnnnnonn nono nnnconnc rn non nooo non nc onn coronan cre nan nnncrnninns 190 27 6 S and 16 bit VO access ER 191 27 7 Bursticycle inicio lares e nd eee biie 192 27 8 SA O 192 27 9 Refresh NS 193 27 10 Memory EDAC aii inert e 194 27 11 _Bus Ready sinaloa had 195 ZT AD ACCESS COMO iii br it ti A iia 196 27 13 Attaching an external DRAM controller oooooncnicnnncnocononconnnnnconconoconononononono ran onnn cnn crn nono c conc rn con ncnnecnnns 197 27 14 Output enable timing oo ee eee cece cseeseecncesaecoecssessecsseseceseesessaeesesenevseecaecnassaecnasenesseseseeeeeesees 197 2715 SREBISUELS Scio seo SN 198 27 16 Vendor and device dentici n 200 2ZTAT CONTISUEAON OPIO Sister titi 201 27 18 Sigal descriptions iia o eii 202 27 19 Signal definitions and reset Values 0 ee eee eee cecesseceseesecoecseeseceseeeeceseeeeseneeceecaeesaecsecsaecseseseeeesens 205 27 20 SAMS sigs etn wee os ee Sacer eA A hs estes ies abies NN 206 27 21 O AAA ests cna ctenscbssecs eusar oes reer EEEE e EE vevvsbovhe vevbsi scans up chan ste COSTED EEK S
450. ise tech Memory technology pfen Prefetch enable Enables read FIFO 0 1 irqsync Interrupt synchronization Forward interrupts from each 0 1 0 bus to another iburst Instruction fetch burst length 4 8 8 rburst Read burst length 4 32 8 wburst Write burst length 2 32 2 bar0 Address area 0 decoded by the bridge s slave interface 0 1073741823 0 Appears as memory address register BARO on the slave interface The generic has the same bit layout as bank address registers with bits 19 18 suppressed use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler misc package to generate this generic barl Address area 1 BAR1 0 1073741823 0 bar2 Address area 2 BAR2 0 1073741823 0 bar3 Address area 3 BAR2 0 1073741823 0 sbus The number of the AHB bus to which the slave interface 0 3 0 is connected The value appears in bits 1 0 of the user defined register O in the slave interface configuration record and master configuration record mbus The number of the AHB bus to which the master inter 0 3 0 face is connected The value appears in bits 3 2 of the user defined register O in the slave interface configura tion record and master configuration record ioarea Configuration area for the master interface AHB bus 0 16 FFFH 0 Appear in the bridge s slave interface user defined regis ter 1 24 2 6 2 7 2 8 Signal descriptions Table 17 shows the interface signals of the core VHDL ports Table 17 Signal
451. ister 35 3 4 Setting up the data for transmission The data to be transmitted should be placed beginning at the address pointed by the descriptor address field The GRETH_GBIT does not add the Ethernet address and type fields so they must also be stored in the data buffer The 4 B Ethernet CRC is automatically appended at the end of each packet Each descriptor will be sent as a single Ethernet packet If the size field in a descriptor is greater than 1514 B the packet will not be sent 35 3 5 Scatter Gather I O A packet can be generated from data fetched from several descriptors This is called Scatter Gather I O The More MO bit should be set to 1 to indicate that more descriptors should be used to generate the current packet When data from the current descriptor has been read to the RAM the next descrip tor is fetched and the new data is appended to the previous data This continues until a descriptor with the MO bit set to 0 is encountered The packet will then be transmitted Status is written immediately when data has been read to RAM for descriptors with MO set to 1 The status bits are always set to O since no transmission has occurred The status bits will be written will be written to the last descriptor for the packet which had MO set to 0 when the transmission has fin ished No interrupts are generated for descriptors with MO set to 1 so the IE bit is don t care in this case The checksum offload control bits explained i
452. ister and correct it When it is finished it resets the CE bit and the monitoring becomes active again The correctable error signals from the fault tolerant units should be connected to the stati cerror input signal vector of the AHB status register core which is or ed internally and if the resulting signal is asserted it will have the same effect as an AHB error response Registers The core is programmed through registers mapped into APB address space Table 39 AHB Status registers APB address offset Registers 0x0 AHB Status register 0x4 AHB Failing address register Table 40 AHB Status register 31 10 9 8 7 6 3 2 0 RESERVED CE NE HWRITE HMASTER HSIZE 31 10 RESERVED 9 CE Correctable Error Set if the detected error was caused by a single error and zero otherwise 8 NE New Error Deasserted at start up and after reset Asserted when an error is detected Reset by writing a zero to it 52 9 4 9 5 9 6 9 7 NUCA 31 Table 40 AHB Status register The HWRITE signal of the AHB transaction that caused the error The HMASTER signal of the AHB transaction that caused the error The HSIZE signal of the AHB transaction that caused the error Table 41 AHB Failing address register AHB FAILING ADDRESS 31 0 The HADDR signal of the AHB transaction that caused the error Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Researc
453. isters Since reads to memory are always done on 32 bit word basis read access to 8 bit memory will be transformed in a burst of four read cycles while access to 16 bit memory will generate a burst of two 16 bit reads During writes only the necessary bytes will be written Figure 75 shows an interface example with 8 bit PROM and 8 bit SRAM Fig ure 76 shows an example of a 16 bit memory interface EDAC is not supported for 16 bit wide memories and therefore the EDAC enable bit corresponding to a 16 bit wide area must not be set 191 It is not allowed to set the ROM or RAM width fields to 8 bit width if ram8 is not set and also not to 16 bit width if ram16 is not set The RMW bit must not be set if RAM EDAC is not enabled when RAM width is set to 8 bit 8 bit PROM ROMSN 0 cs oeN Jog WRITEN ps MEMORY CONTROLLER RAMSN 0 RAMOEN 0 RWEN 0 A 27 0 D 31 24 D 31 24 Figure 75 8 bit memory interface example 16 bit PROM ROMSN 0 cs on lo WRITEN rp MEMORY CONTROLLER 16 bit RAM RAMSN 0 cs RAMOENIO kwao oe RWE 1 0 WE RWEN 0 1 A 27 0 D 31 16 D 31 16 Figure 76 16 bit memory interface example In 8 bit mode the PROM SRAM devices should be connected to the MSB byte of the data bus D 31 24 The LSB address bus should be used for addressing A 25 0 In 16 bit mode D 31 16 should be used as data bus and A 26 1 as address bus EDAC protection is not available in 16
454. ith the mselin VHDL generic or later changed by writing to the operation and status register of the Corel553BRM core For information about how the core functions during the different modes of operation see the Actel Corel 553BRM MIL STD 1553 BC RT and MT data sheet 108 19 4 Registers The core is programmed through registers mapped into APB address space The internal registers of Core1553BRM are mapped on the 33 lowest APB addresses These addresses are 32 bit word aligned although only the lowest 16 bits are used Refer to the Actel Corel 553BRM MIL STD 1553 BC RT and MT data sheet for detailed information Table 104 B1553BRM registers APB address offset Register 0x00 0x84 Core1553BRM registers 0x100 B1553BRM status control 0x104 B1553BRM interrupt settings 0x108 AHB page address register B1553BRM status control register 31 2 1 98 5 4 3 2 1 0 RESERVED reset clksel clkdiv rtaderr memfail busy active ssysfn Figure 41 B1553BRM status control register 12 5 Bit 12 5 are only available in the b1553brm_async toplevel which allows separate AHB and BRM frequencies 12 Reset For asynchronous toplevel only Software reset Self clearing 11 9 Clock select For asynchronous toplevel only 0 AHB clock 1 divided AHB clock 2 brm_clk1 3 brm_clk2 8 5 Clock divisor For asynchronous toplevel only BRM core clocked by AHB clock divided by 2 clkdiv 1 4 Add
455. ity AHBSI 1 Input AHB slave input signals AHBSO 1 Output AHB slave output signals SDO SDCASN Output Not used All signals are driven to inactive state Low 1 See GRLIB IP Library User s Manual 2 Polarity is selected with the oepol generic Library dependencies Table 457 shows libraries used when instantiating the core VHDL libraries Table 457 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Component declaration The core has the following component declaration component srctrl generic hindex romaddr rommask ramaddr rammask ioaddr iomask ramws romws iows rmw prom8en oepol srbanks banksz romasel i port rst clk ahbsi ahbso sri sro sdo i end component Instantiation integer range 0 to 13 integer range 0 to 27 19 in memory_ out memory_ out sdctrl_ integer 0 integer 0 integer 16 ff0 integer 1644004 integer 16 ff0 integer 16 200 integer 16 ff0 integer 0 integer 2 integer 2 integer 0 read modify write enable integer 0 integer 0 integer range 1 to 5 1 135 in std_ulogic in std_ulogic in ahb_slv_in type out ahb_slv_out_type in_type out_type out_type This
456. iv0 div32 port map rst clk holdn divi end divo 25 25 1 25 2 171 DSU3 LEON3 Hardware Debug Support Unit Overview To simplify debugging on target hardware the LEON3 processor implements a debug mode during which the pipeline is idle and the processor is controlled through a special debug interface The LEON3 Debug Support Unit DSU is used to control the processor during debug mode The DSU acts as an AHB slave and can be accessed by any AHB master An external debug host can therefore access the DSU through several different interfaces Such an interface can be a serial UART RS232 JTAG PCI USB or ethernet The DSU supports multi processor systems and can handle up to 16 pro Cessors LEON3 Debug I F Processor s j lt gt e gt Debug Support gt Unit z Le gt A AHB Slave I F AHB Master I F y y AMBA AHB BUS RS232 PCI Ethernet JTAG USB Z DEBUG HOST Figure 53 LEON3 DSU Connection Operation Through the DSU AHB slave interface any AHB master can access the processor registers and the contents of the instruction trace buffer The DSU control registers can be accessed at any time while the processor registers caches and trace buffer can only be accessed when the processor has entered debug mode In debug mode the processor pipeline is held and the processor
457. iver FIFO is not empty read accesses retrieve the next byte from the FIFO Bytes written to this field are stored in the transmitter holding FIFO if it is not full 76 14 6 14 5 2 PS 2 Status Register 31 27 26 22 5 43 2 1 0 RCNT TCNT RESERVED TRF RF KI FE PE DR Figure 27 PS 2 status register 0 Data ready DR indicates that new data is available in the receiver holding register read only 1 Parity error PE indicates that a parity error was detected 2 Framing error FE indicates that a framing error was detected 3 Keyboard inhibit KD indicates that the keyboard is inhibited 4 Receiver buffer full RF indicates that the output buffer FIFO is full read only 5 Transmitter buffer full TF indicates that the input buffer FIFO is full read only 26 22 Transmit FIFO count TCNT shows the number of data frames in the transmit FIFO read only 31 27 Receiver FIFO count RCNT shows the number of data frames in the receiver FIFO read only 14 5 3 PS 2 Control Register 31 3 2 10 RESERVED TI RI TERE Figure 28 PS 2 control register O Receiver enable RE if set enables the receiver 1 Transmitter enable TE if set enables the transmitter 2 Keyboard interrupt enable RI if set interrupts are generated when a frame is received 3 Host interrupt enable TI if set interrupts are generated when a frame is trans
458. ize words of each cache line Line size 2L5Z 15 12 Local ram size LRSZ Indicates the size Kbytes of the implemented local scratch pad ram Local ram size 2 11 4 Local ram start address Indicates the 8 most significant bits of the local ram start address 3 MMU present This bit is set to 1 if an MMU is present 382 44 6 All cache registers are accessed through load store operations to the alternate address space LDA STA using ASI 2 The table below shows the register addresses Table 396 ASI 2 system registers address map Address Register 0x00 Cache control register 0x04 Reserved 0x08 Instruction cache configuration register 0x0C Data cache configuration register 44 5 8 Software consideration After reset the caches are disabled and the cache control register CCR is 0 Before the caches may be enabled a flush operation must be performed to initialized clear the tags and valid bits A suitable assembly sequence could be flush set 0x81000f g1 sta gl g0 2 Memory management unit A memory management unit MMU compatible with the SPARC V8 reference MMU can optionally be configured For details on operation see the SPARC V8 manual 44 6 1 ASI mappings When the MMU is used the following ASI mappings are added Table 397 MMU ASI usage ASI Usage 0x10 Flush page 0x10 MMU flush page 0x13 MMU flush context 0x14 MMU diagnostic
459. k frequency all CPU core parts including integer unit and caches will operate at double AHB clock frequency while the AHB bus access is performed at the slower AHB clock fre quency The two clocks have to be synchronous and a multicycle paths between the two clock domains have to be defined at synthesis tool level A separate component leon3s2x is provided for the double clocked core Double clocked versions of DSU dsu3_2x and MP interrupt controller irqmp2x are used in a double clocked LEON3 system An AHB clock qualifier signal clken input is used to identify end of AHB cycle The AHB qualifier signal is generated in CPU clock domain and is high during the last CPU clock cycle under AHB clock low phase Sample leon3 clk2x design pro vides a module that generates an AHB clock qualifier signal Double clocked design has two clock domains AMBA clock domains HCLK and CPU clock domain CPUCLK LEON3 leon3s2x component and DSU3 dsu3_2x belong to CPU clock domain clocked by CPUCLK while the rest of the system is in AMBA clock domain clocked by HCLK Paths between the two clock domains paths starting in CPUCLK domain and ending in 386 HCLK and paths starting in HCLK domain and ending in CPUCLK domain are multicycle paths with propagation time of two CPUCLK periods or one HCLK period with following exceptions Start point Through End point Propagation time leon3s
460. kbyte Leon3 SPARC V8 Processor AHB Debug UART Leon2 Memory Controller size 512 Mbyte cacheable prefetch size 512 Mbyte size 1024 Mbyte cacheable prefetch AHB APB Bridge size 1 Mbyte APB Bridge at 0x80000000 rev 1 Leon2 Memory Controller size 256 byte Generic UART size 256 byte Multi processor Interrupt Ctrl size 256 byte Modular Timer Unit size 256 byte AHB Debug UART size 256 byte General Purpose I O port size 256 byte 2 32 bit timers cpu 1 irg 8 dcache 1 8 kbyte 35 36 5 1 AHBCTRL_MB AMBA AHB bus controller bus with support for multiple AHB buses Overview AMBA AHB bus controller with support for multiple AHB buses performs arbitration and bus control on one AHB bus identically to single bus AHB controller AHBCTRL In addition AHBCTRL_MB can decode plug amp play information for multiple AHB buses making it suitable for use in multiple AHB bus systems The AMBA AHB bus controller supports systems with up to 4 AHB buses LEON3 LEON3 DSU3 SDRAM SDRAM Controller SERV AHBCTRL_MB AHB AHB JTAG Bridge Dbg Link Async Mem PROM Controller AHB Bus 1 AHBCTRL_MB SRAM AHB APB Ethernet Bridge MAC 2 r UARTS Timers IrqCtrl Figure 5 System with multiple AHB buses The AMBA AHB controller with support for mu
461. km ahbsi ahbso 3 sdi sdo ce 0 input signals sdi data 31 downto 0 lt sd 31 downto 0 connect SDRAM controller outputs to entity output signals sa lt sdo address sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm I O pads driving data bus signals sd_pad iopadv generic map width gt 32 port map sd 31 downto 0 sdo data sdo bdrive sdi data 31 downto 0 I O pads driving checkbit signals cb_pad iopadv generic map width gt 8 port map cb sdo cb sdo bdrive sdi cb end 29 29 1 29 2 219 FTSRCTRL Fault Tolerant 32 bit PROM SRAMI IO Controller Overview The fault tolerant 32 bit PROM SRAM memory interface uses a common 32 bit memory bus to inter face PROM SRAM and I O devices Support for 8 bit PROM banks can also be separately enabled In addition it also provides an Error Detection And Correction Unit EDAC correcting one and detecting two errors Configuration of the memory controller functions is performed through the APB bus interface SRO ROMSN SRO OEN SRO WRITEN MEMORY CONTROLLER SRO RAMSN SRO RAMOEN SRO RWEN 3 0 SRI A 27 0 SRLD 31 0 SRO D 31 0 CB 7 0 AHB APB Bridge Figure 88 32 bit FT PROM SRAM IO controller Operation The controller is configured through VHDL generics to decode three address ranges PROM SRAM and I O area By def
462. l leon30 13_out_vector 0 to NCPU 1 signal irqi irq_in _ vector 0 to NCPU 1 signal irgo irq_out_vector 0 to NCPU 1 signal dbgi 13_debug_in_vector 0 to NCPU 1 signal dbgo 13_debug_out_vector 0 to NCPU 1 signal dsui dsu_in type signal dsuo dsu_out_type begin cpu for i in 0 to NCPU 1 generate u0 leon3s LEON3 processor generic map ahbndx gt i fabtech gt FABTECH memtech gt MEMTECH port map clkm rstn ahbmi ahbmo i ahbsi ahbsi ahbso irgi i irqo i dbgi i dbgo i irqi i lt leon30 i irqg leon3i i irq lt irqo i end generate dsu0 dsu3 LEON3 Debug Support Unit generic map ahbndx gt 2 ncpu gt NCPU tech gt memtech kbytes gt 2 port map rstn clkm ahbmi ahbsi ahbso 2 dbgo dbgi dsui dsuo 180 dsui enable lt dsuen dsui break lt dsubre dsuact lt dsuo active 26 26 1 26 2 181 FTAHBRAM On chip SRAM with EDAC and AHB interface Overview The FTAHBRAM core is a version of the AHBRAM core with added Error Detection And Correction EDAC The on chip memory is accessed via an AMBA AHB slave interface The memory imple ments 2 kbytes of data configured via the kbytes VHDL generics Registers are accessed via an AMB APB interface The on chip memory implements volatile memory that is protected by means of Error Detection And Correction EDAC One error can be corrected and two errors can be detected which is performed b
463. l processors except processor 0 are halted When the system is properly initialized processor 0 can start the remaining processors by writing to their STATUS bits 43 2 3 Irq broadcasting The Broadcast Register is activated when the generic ncpu is gt 1 A incoming irq that has its bit set in the Broadcast Register is propagated to the force register of all CPUs rather than only to the Pending Register This can be used to implement a timer that fires to all cpus with that same irq 364 43 3 Registers The core is controlled through registers mapped into APB address space The number of implemented registers depend on number of processor in the multiprocessor system Table 388 Interrupt Controller registers APB address offset Register 0x00 Interrupt level register 0x04 Interrupt pending register 0x08 Interrupt force register NCPU 0 0x0C Interrupt clear register 0x10 Multiprocessor status register 0x14 Broadcast register 0x40 Processor interrupt mask register 0x44 Processor 1 interrupt mask register 0x40 4 n Processor n interrupt mask register 0x80 Processor interrupt force register 0x84 Processor interrupt force register 0x80 4 n Processor n interrupt force register 43 3 1 Interrupt level register 31 17 16 1 0 000 0 IL 15 1 0 Figure 157 Interrupt level register 31 16 Reserved 15 1 Interrupt Level n IL n Interrupt level for i
464. l register Table 229 Scaler value 31 16 16 1 0 000 0 SCALER VALUE 16 1 0 Scaler value Any unused most significant bits are reserved Always reads as 000 0 Table 230 Scaler reload value 31 16 16 1 0 000 0 SCALER RELOAD VALUE 16 1 0 Scaler reload value Any unused most significant bits are reserved Always reada as 000 0 Table 231 General Purpose Timer Unit Configuration Register 31 10 9 8 7 3 2 0 000 0 DF SI IRQ TIMERS 31 10 Reserved Always reads as 000 0 9 Disable timer freeze DF If set the timer unit can not be freezed otherwise signal GPTILDHALT freezes the timer unit 8 Separate interrupts SI Reads 1 if the timer unit generates separate interrupts for each timer oth erwise 0 Read only T 3 APB Interrupt If configured to use common interrupt all timers will drive APB interrupt nr IRQ otherwise timer nwill drive APB Interrupt IRQ n has to be less the MAXIRQ Read only 2 0 Number of implemented timers Read only Table 232 Timer counter value register 32 1 0 TIMER COUNTER VALUE 251 Table 232 Timer counter value register 32 1 0 Timer Counter value Decremented by 1 for each n prescaler tick where n is number of implemented timers Any unused most significant bits are reserved Always reads as 000 0 Table 233 Timer reload value register 32 1 0 TIMER RELOAD VALUE 32 1 0 Timer Reload value This value is loaded into the t
465. laced between the CLK_AHB and CLKDDRI to avoid optimization of false paths during synthesis and place amp route The Xilinx version of the PHY generates the internal DDR read clock usnig an external clock feed back The feed back should have the same delay as DDR signals to and from the DDR memories The feed back should be driven by DDR_CLK_FB_OUT and returned on DDR_CLK_FB Most Xilinx FPGA boards with DDR provides clock feed backs of this sort The supported frequencies for the Xil inx PHY depends on the clock to output delay of the DDR output registers and the internal delay from the DDR input registers to the read data FIFO Virtex2 and Virtex4 can typically run at 120 MHz while Spartan3e can run at 100 MHz The read data clock in the Xilinx version of the PHY is generated using a DCM to offset internal delay of the DDR clock feed back If the automatic DCM phase adjustment does not work due to unsuitable pin selection extra delay can be added through the RSKEW generic The generic can be between 255 and 255 and is passed directly to the PHASE_SHIFT generic of the DCM The Altera version of the PHY use the DQS signals and an internal PLL to generate the DDR read clock No external clock feed back is needed and the DDR_CLK_FB_OUT DDR_CLK_FB signals are not used The supported frequencies for the Altera PHY are 100 110 120 and 130 MHz 23 2 9 Pads The DDRSPA core has technology specific pads inside the core The external DDR signals sho
466. last of all the descriptor fields 12 Wrap WR Set to one to make the descriptor pointer wrap to zero after this descriptor has been used If this bit is not set the pointer will increment by 8 The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached 13 Interrupt Enable IE Enable Interrupts An interrupt will be generated when a packet has been received to this descriptor provided that the receiver interrupt enable bit in the control register is set The interrupt is generated regardless if the packet was received successfully or if it terminated with an error 14 Alignment error AE An odd number of nibbles were received 15 Frame Too Long FT A frame larger than the maximum size was received The excessive part was truncated 16 CRC Error CE A CRC error was detected in this frame 17 Overrum Error OE The frame was incorrectly received due to a FIFO overrun 31 2 Address Pointer to the buffer area from where the packet data will be loaded Figure 113 Receive descriptor Memory offsets are shown in the left margin 34 4 2 Starting reception Enabling a descriptor is not enough to start reception A pointer to the memory area holding the descriptors must first be set in the GRETH This is done in the receiver descriptor pointer register The address must be aligned to a 1 kB boundary Bits 31 to 10 hold the base address of descriptor area while bits 9 to 3 form a pointer
467. late operation Use only with 16x16 0 to 1 0 multiplier option with no pipelining pipe 0 48 5 48 6 48 7 Signal descriptions Table 422 shows the interface signals of the core VHDL ports Table 422 Signal declarations Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock HOLDN N A Input Hold Low MULI OP1 32 0 Input Operand 1 High OP1 32 Sign bit OP1 31 0 Operand 1 in 2 s complement for mat OP2 32 0 Operand 2 High OP2 32 Sign bit OP2 31 0 Operand 2in 2 s complement format FLUSH Flush current operation High SIGNED Signed multiplication High START Start multiplication High MAC Multiply amp accumulate High ACC 39 0 Accumulator Accumulator value is held exter High nally MULO READY Output Result is ready during the next clock cycle for High 16x16 32x8 and 32x16 configurations Not used for 32x32 configuration or MAC operation NREADY Not used ICC 3 0 Condition codes High ICC 3 Negative result not used in 32x32 conf ICC 1 Zero result not used in 32x32 conf ICC 1 0 Not used RESULT 63 0 Result Available at the end of the clock cycle if High MULO READY was asserted in previous clock cycle For 32x32 configuration the result is avail able during second clock cycle after the MULL START was asserted Library dependencies Table 423 shows the
468. lgo rithms one for full duplex mode and one for half duplex The mode is selected with a VHDL generic and must correspond to the operating mode on the physical medium In half duplex mode both MACs have equal priority and the arbiter uses the normal CSMA CD protocol for selecting which MAC gains access to the medium In full duplex mode one MAC has priority master over the other slave When the master unit wants to transmit the arbiter stops any ongoing transmissions from the slave MAC and inserts an interframe gap Since the last 4 B of the interrupted frame will be interpreted as the CRC value it will be incorrect with a high probability and therefore discarded at the receiving end The master is allowed to transmit after the interframe gap and cannot be interrupted by the slave The reason for this solution is that there should be no contention of the medium on a full duplex network link and there fore Ethernet does not provide any signals for delaying a MAC transmission in this mode Since the arbiter will cause lost frames due to higher contention of the medium in half duplex and due to the arbitration protocol in full duplex the higher level protocols must provide reliable transmis sions for example ARQ with long enough time outs Normally this will not be a problem and the standard protocols such as TCP can be used Half duplex normally works fine without any special care but full duplex can cause problems for the slave since its
469. libraries used when instantiating the core VHDL libraries Table 423 Library dependencies Library GAISLER Package ARITH Imported unit s Signals component Description Signals component declaration Component declaration The core has the following component declaration component mul32 generic infer multype integer integer 1 I o 424 pipe integer 0 mac integer 0 i port rst in std_ulogic clk sm std l gica holdn in std_ulogic muli in mul32_in type mulo out mul32_out_type end component 48 8 Instantiation This examples shows how the core can be instantiated The module is configured to implement 16x16 pipelined multiplier with support for MAC operations library ieee use ieee std_logic_1164 all library grlib use gaisler arith all signal muli mul32_in_type signal mulo mul32_out_type begin mul0 mul32 generic map infer gt 1 multype gt 0 pipe gt 1 mac gt 1 port map rst clk holdn muli mulo end 49 49 1 49 2 49 3 49 4 425 MULTLIB High performance multipliers Overview The GRLIB MULTLIB VHDL library contains a collection of high performance multipliers from the Arithmetic Module Generator at Norwegian University of Science and Technology 32x32 32x8 32x16 16x16 unsigned signed multipliers are included 16x16 bit multiplier can be configured to include
470. lify for Xilinx FPGAs gives typically 15 larger area Table 13 Approximate area consumption for some standard GRLIB IP cores Virtex2 AX RTAX ASIC Block LUT RAM16 Cells RAM64 Gates AHBCTRL 200 500 1 000 AHBJTAG 120 350 1 000 AHBUART DSU UART 450 800 2 000 APBCTRL 150 200 800 APBPS2 450 800 2 000 APBUART 200 300 1 000 APBVGA 250 4 1 400 ATACTRL 400 600 2 000 CAN_OC CAN 2 0 core with AHB I F 1 600 2 2 800 2 5 000 GRCAN CAN 2 0 Controller with DMA 2 300 3 600 15 000 DDRCTRL 1 600 2 10 000 DDRSPA 32 bit 900 DIV32 64 32 bit iterative divider 400 500 2 000 GPTIMER 16 bit scaler 2x32 bit timers 250 400 1 300 GRETH 10 100 Mbit Ethernet MAC 1 500 2 500 8 000 GRETH 10 100 Mbit Ethernet MAC with EDCL 2 600 1 4 000 15 000 GRFPU Lite including LEON3 controller 4 000 6 7 000 4 35 000 GRFPU IEEE 754 floating point unit 9 000 100 000 GRFPC for LEON3 5 000 4 25 000 GRGPIO 16 bit configuration 100 150 800 GRSWP Spacewire link 1 900 3 2 800 3 15 000 IRQMP 1 processor 300 350 1 500 LEON3 8 8 Kbyte cache 4 300 12 6 500 40 20 000 LEON3 8 8 Kbyte cache DSU3 5 000 12 7 500 40 25 000 LOGAN 32 channels 1024 traces 1 trigger 300 2 MCTRL 350 1 000 1 500 MCTRL including SDRAM support 600 1 400 2 000 MUL32 32x32 multiplier 4 cycle iterative 200 1 400 5 500 PCI_TARGET simple PCI target 150 5
471. ligned address range can be watched the range is defined by the WADDR field masked by the WMASK field WMASKT x 1 enables comparison On a breakpoint hit trap OxOB is gener ated By setting the IF DL and DS bits a hit can be generated on instruction fetch data load or data store Clearing these three bits will effectively disable the breakpoint function 374 44 2 8 Instruction trace buffer The instruction trace buffer consists of a circular buffer that stores executed instructions The trace buffer operation is controlled through the debug support interface and does not affect processor oper ation see the DSU description The size of the trace buffer is configurable from 1 to 64 kB through a VHDL generic The trace buffer is 128 bits wide and stores the following information e Instruction address and opcode e Instruction result e Load store data and address e Trap information e 30 bit time tag The operation and control of the trace buffer is further described in section 25 4 Note that in multi processor systems each processor has its own trace buffer allowing simultaneous tracing of all instruction streams 44 2 9 Processor configuration register The application specific register 17 asr17 provides information on how various configuration options were set during synthesis This can be used to enhance the performance of software or to sup port enumeration in multi processor systems The register can be accessed t
472. ll be disabled until the CanSTAT register is read 22 9 2 Status Register CanSTAT R Table 152 Status register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 TxErrCntr 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RxErrCntr Acti AH OR Off Pass ve B Err 23 16 TxErrCntr Transmission error counter 8 bit 15 8 RxErrCntr Reception error counter 8 bit 4 ACTIVE Transmission ongoing 5h AHBErr AMBA AHB master interface blocked due to previous AHB error 2 OR Overrun during reception 1 OFF Bus off condition 0 PASS Error passive condition 150 All bits are cleared to O at reset The OR bit is set if a message with a matching ID is received and cannot be stored via the AMBA AHB bus this can be caused by bandwidth limitations or when the circular buffer for reception is already full The OR and AHBErr status bits are cleared when the register has been read Note that TxErrCntr and RxErrCntr are defined according to CAN protocol Note that the AHBErr bit is only set to 1b if an AMBA AHB error occurs while the Can CONF ABORT bit is set to 1b 22 9 3 Control Register CanCTRL R W Table 153 Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rese Ena t ble 1 RESET Reset complete core when 1 O ENABLE Enable CAN controller when 1 Reset CAN c
473. ll the supported calls SPACEWIRE_IOCTRL_ should be concatenated with the call number in the table to get the 346 actual constant used in the code Return values for all calls are O for success and 1 for failure Errno 1s set after a failure An example of a ioctl is shown below result ioctl fd SPACEWIRE_IOCTRL_SET_NODEADDR OxFE Table 343 ERRNO values for ioctl calls ERRNO Description EINVAL Null pointer or an out of range value was given as the argument EBUSY Only used for SEND Returned when no descriptors are available in non blocking mode ENOSYS Returned for SET_DESTKEY if RMAP command handler is not available or if an non implemented call is used ETIMEDOUT Returned for SET_PACKETSIZE if the link did not start after the size change ENOMEM Returned for SET_PACKETSIZE if it was unable to allocate the new buff ers EIO Error when writing to grspw registers Table 344 1octl calls supported by the GRSPW driver 347 Call Number SET_NODEADDR Description Change node address SET_RXBLOCK Change blocking mode of receptions SET_DESTKEY Change destination key SET_CLKDIV Change clock division factor SET_TIMER Change timer setting SET_DISCONNECT Change disconnection timeout SET_PROMISCUOUS Enable Disable promiscuous mode SET_RMAPEN Enable Disable RMAP command handler SET_RMAPBUFDIS Enable Disable
474. ls of the core VHDL ports Table 23 Signal descriptions Signal name Field Type Function Active RST N A Input AHB reset Low CLK N A Input AHB clock MSTI Output AMBA AHB master interface record array MSTO Input AMBA AHB master interface record array SLVI e Output AMBA AHB slave interface record array SLVO t Input AMBA AHB slave interface record array see GRLIB IP Library User s Manual Library dependencies Table 24 shows libraries used when instantiating the core VHDL libraries Table 24 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions Component declaration library grlib use grlib amba all component ahbctrl generic defmast integer 0 default master split integer 0 split support rrobin integer 0 round robin arbitration timeout integer range 0 to 255 0 HREADY timeout ioaddr ahb_addr_type l16 fff I O area MSB address iomask ahb_addr_type lo fff I O area address mask cfgaddr ahb_addr_type 16 ff0 config area MSB address cfgmask ahb_addr_type l6 ff0 config area address maskk nahbm integer range 1 to NAHBMST NAHBMST number of masters nahbs integer range 1 to NAHBSLV NAHBSLV number of slaves ioen integer range 0 to 15 1 enable I O area disirg integer range 0 to 1 0 disable interrupt routing fixbrst integer rang
475. lter consists of two parts the acceptance code and the acceptance mask The code registers are used for specifying the pat tern to match and the mask registers specify don t care bits In total eight registers are used for the acceptance filter as shown in the table below Note that they are only read writable in reset mode 134 Table 143 Acceptance filter registers Address Description 16 Acceptance code 0 ACRO 17 Acceptance code 1 ACR1 18 Acceptance code 2 ACR2 19 Acceptance code 3 ACR3 20 Acceptance mask 0 AMRO 21 Acceptance mask 1 AMR1 22 Acceptance mask 2 AMR2 23 Acceptance mask 3 AMR3 Single filter mode standard frame When receiving a standard frame in single filter mode the registers ACRO 3 are compared against the incoming message in the following way ACRO 7 0 amp ACR1 7 5 are compared to ID 28 18 ACR1 4 is compared to the RTR bit ACR1 3 0 are unused ACR2 amp ACR3 are compared to data byte 1 amp 2 The corresponding bits in the AMR registers selects if the results of the comparison doesn t matter A set bit in the mask register means don t care Single filter mode extended frame When receiving an extended frame in single filter mode the registers ACRO 3 are compared against the incoming message in the following way ACRO 7 0 amp ACR1 7 0 are compared to ID 28 13 ACR2 7 0 amp ACR3 7 3 are compared to ID 12 0 ACR3 2 are compared to the RTR bit
476. ltiple AHB buses is a combined AHB arbiter bus multiplexer and slave decoder according to the AMBA 2 0 standard The controller supports up to 16 AHB masters and 16 AHB slaves per AHB bus The maximum num ber of masters and slaves per bus are defined in the GRLIB AMBA package in the VHDL constants NAHBSLV and NAHBMST It can also be set with the nahbm and nahbs VHDL generics MASTER MASTER A A AHBCTRL Y y ARBITER SN DECODER v y SLAVE SLAVE Figure 6 AHB controller block diagram 3 2 37 Operation 5 2 1 Arbitration The AHB controller supports two arbitration algorithms fixed priority and round robin The selection is done by the VHDL generic rrobin In fixed priority mode rrobin 0 the bus request priority is equal to the master s bus index with index O being the lowest priority If no master requests the bus the master with bus index O set by the VHDL generic defmast will be granted In round robin mode priority is rotated one step after each AHB transfer If no master requests the bus the last owner will be granted bus parking During incremental bursts the AHB master should keep the bus request asserted until the last access as recommended in the AMBA 2 0 specification or 1t might loose bus ownership For fixed length burst the AHB master will be granted the bus during the full burst and can relea
477. lue is used as time tag in the instruction and AHB trace buffer The width of the timer up to 30 bits is configurable through the DSU generic port 25 6 6 DSU ASI register The DSU can perform diagnostic accesses to different ASI areas The value in the ASI diagnostic access register is used as ASI while the address is supplied from the DSU 31 7 0 ASI Figure 59 ASI diagnostic access register 7 0 ASI to be used on diagnostic ASI access 25 6 7 AHB Trace buffer control register The AHB trace buffer is controlled by the AHB trace buffer control register 31 16 2 1 0 DCNT RESERVED BR DMEN Figure 60 AHB trace buffer control register 0 Trace enable EN Enables the trace buffer 1 Delay counter mode DM Indicates that the trace buffer is in delay counter mode 2 Break BR If set the processor will be put in debug mode when AHB trace buffer stops due to AHB breakpoint hit 31 16 Trace buffer delay counter DCNT Note that the number of bits actually implemented depends on the size of the trace buffer 25 7 177 25 6 8 AHB trace buffer index register The AHB trace buffer index register contains the address of the next trace line to be written 31 4 3 0 INDEX 0000 Figure 61 AHB trace buffer index register 31 4 Trace buffer index counter INDEX Note that the number of bits actually implemented depends on the size of the trace buffer 25 6 9 AHB trace buf
478. m tdo tck tms tdi 100 20 16 40000000 true wait end process end Simulation DSU communication over the JTAG debug link can be simulated using jtagcom procedure The jtag com procedure sends JTAG commands to the AHBJTAG on JTAG signals TCK TMS TDI and TDO The commands read out and report the device identification code optionally put the CPU s in debug mode perform three write operations to the memory and read out the data from the memory The JTAG test works if the generic JTAG tap controller is used and will not work with built in TAP mac ros such as Altera and Xilinx JTAG macros since these macros don t have visible JTAG pins The jtagcom procedure is part of jtagtst package in gaisler library and has following declaration procedure jtagcom signal tdo in std_ulogic signal tck tms tdi out std_ulogic Cp start addr in integer cp TCK clock period in ns start time in us when JTAG test is started addr read write operation destination address haltcpu in boolean 7 1 7 2 7 3 7 4 7 5 47 AHBRAM Single port RAM with AHB interface Overview AHBRAM implements a 32 bit wide on chip RAM with an AHB slave interface Memory size is con figurable in binary steps through a VHDL generic Minimum size is 1kB and maximum size is depen dent on target technology and physical resources Read accesses are zero waitstate write access have one waitstate The RAM supports byte and half wor
479. m_none sdramen gt 1 dinvclk gt 0 n cgi cgo cgi pllref lt pllref 16 600 hmask gt 16 FOO 457 port map rstn clkm ahbsi ahbso 3 sdi sdo input signals sdi data 31 downto 0 lt sd 31 downto 0 connect SDRAM controller outputs to entity output signals sa lt sdo address sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm Data pad instantiation with scalar bdrive sd_pad iopadv generic map width gt 32 port map sd 31 downto 0 sdo data sdo bdrive sdi data 31 downto 0 end Alternative data pad instantiation with vectored bdrive sd_pad iopadvv generic map width gt 32 port map sd 31 downto 0 sdo data sdo vbdrive sdi data 31 downto 0 end 458 56 56 1 SRCTRL 8 32 bit PROM SRAM Controller Overview SRCTRL is an 8 32 bit PROM SRAM IO controller that interfaces external asynchronous SRAM PROM and I O to the AMBA AHB bus The controller can handle 32 bit wide SRAM and I O and either 8 or 32 bit PROM SRO ROMSN SRO OEN SRO WRITEN MEMORY CONTROLLER SRO RAMSN SRO RAMOEN SRO RWEN 3 0 SRI A 27 0 SRI D 31 0 SRO D 31 0 CB 7 0 AHB APB Bridge Figure 224 8 32 bit PROM SRAMIO controller The controller is configured through VHDL generics to decode three address ranges PROM SRAM and I O area By default PROM area is m
480. me the scaler underflows TICK 1 n are high for one clock each time the corrspondning timer underflows WDOG Output Watchdog output Equivalent to interrupt pend High ing bit of last timer WDOGN Output Watchdog output Equivalent to interrupt pending Low bit of last timer see GRLIB IP Library User s Manual 253 31 7 Library dependencies Table 237 shows libraries used when instantiating the core VHDL libraries Table 237 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER MISC Signals component Component declaration 31 8 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler misc all entity gptimer_ex is port clk in std_ulogic rstn in std_ulogic f other signals i end architecture rtl of gptimer_ex is AMBA signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none GP Timer Unit input signals signal gpti gptimer_in_type begin AMBA Components are instantiated here General Purpose Timer Unit timer0 gptimer generic map pindex gt 3 paddr gt 3 pirq gt 8 sepirg gt 1 port map rstn clk apbi apbo 3 gpti open gpti dhalt lt 0 gpti extclk lt 0 unused inp
481. mitted 14 5 4 PS 2 Timer Reload Register 31 12 11 0 RESERVED TIMER RELOAD REG Figure 29 PS 2 timer register 11 0 PS 2 timer reload register Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x061 For a description of vendor and device identifiers see GRLIB IP Library User s Manual 14 7 14 8 14 9 14 10 Configuration options Table 66 shows the configuration options of the core VHDL generics Table 66 Configuration options 77 Generic Function Allowed range Default pindex APB slave index 0 NAPBSLV 1 0 paddr ADDR field of the APB BAR 0 16 FFFH 0 pmask MASK field of the APB BAR 0 16 FFFH 16 FFFH pirq Index of the interrupt line 0 NAHBIRQ 1 0 fKHz Frequency of APB clock in KHz 1 163830 50000 fixed Used fixed clock divider to generate PS 2 clock 0 1 1 Signal descriptions Table 67 shows the interface signals of the core VHDL ports Table 67 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals PS2I PS2_CLK_I Input PS 2 clock input PS2_DATA_I Input PS 2 data input PS20 PS2_CLK_O Output PS 2 clock output PS2_CLK_OE Output PS 2 clock output enable Low PS2_DATA_O Output PS 2 data output PS2_DATA_OE Output PS 2 data output enable Low
482. mitter is enabled through the TE bit in the UART control register Data that is to be trans ferred is stored in the FIFO holding register by writing to the data register This FIFO is configurable to different sizes via the fifosize VHDL generic When the size is 1 only a single holding register is used but in the following discussion both will be referred to as FIFOs When ready to transmit data is transferred from the transmitter FIFO holding register to the transmitter shift register and converted to a serial stream on the transmitter serial output pin TXD It automatically sends a start bit followed by eight data bits an optional parity bit and one stop bit figure 31 The least significant bit of the data is sent first 84 Data frame no parity Start DO D1 D2 D3 D4 D5 D6 D7 Stop Data frame with parity Start DO D1 D2 D3 D4 D5 D D7 Parity Stop Figure 31 UART data frames Following the transmission of the stop bit if a new character is not available in the transmitter FIFO the transmitter serial data output remains high and the transmitter shift register empty bit TS will be set in the UART status register Transmission resumes and the TS is cleared when a new character is loaded into the transmitter FIFO When the FIFO is empty the TE bit is set in the status register If the transmitter is disabled it will immediately stop any a
483. mory located in the AHB address space A frame on the display is created by fetching the pixel data from memory and sending it to the screen through an external DAC using three 8 bit color vectors To hide the AHB bus latency the pixel data is buffered in a FIFO inside the core The start address of the frame buffer is specified in the Frame buffer Mem ory Position register and can be anywhere in the AHB address space In addition to the color vectors the video controller also generates HSYNC VSYNC CSYNC and BLANK signals control signals The SVGACTRL video timing is programmable through the Video Length Front Porch Sync Length and Line Length registers The bit depth selection and enabling of the controller is done through the status register These values makes it possible to display a wide range of resolutions and refresh rates The pixelclock can be either static or a dynamic multiplexed The frequency of the pixel clock is cal cultaed as Horizontal Line Length Vertical Line Length refresh rate When using a dynamically multiplexed clock bits 5 4 in the status register are used to controll the clock selector The dynamic pixel clocks should be defined in the SVGACTRL generics to allow the overlying software can read out the availabke pixel clock frequencies The SVGACTRL can use bit depths of 8 16 and 32 bits When using 32 bits bits 23 0 are used when 16 bits a 5 6 5 color scheme is used and when using 8 bits a color lo
484. mory space 0011 AHB I O space Figure 4 AHB plug amp play information record AMB split support AHB SPLIT functionality is supported if the split VHDL generic is set to 1 In this case all slaves must driver the AHB SPLIT signal AHB bus monitor An AHB bus monitor is integrated into the core It is enabled with the enbusmon generic It has the same functionality as the AHB and arbiter parts in the AMBA monitor core AMBAMON For more information on which rules are checked se the AMBAMON documentation Registers The core does not implement any registers 4 6 Configuration options Table 22 shows the configuration options of the core VHDL generics Table 22 Configuration options 31 Generic Function Allowed range Default ioaddr The MSB address of the I O area Sets the 12 most sig 0 16 FFF 16 FFFH nificant bits in the 32 bit AHB address iomask The I O area address mask Sets the size of the I O area 0 16 FFF 16 FFFH and the start address together with ioaddr cfgaddr The MSB address of the configuration area 0 16 FFFH 16 FFO cfgmask The address mask of the configuration area Sets the size O 16 FFF 16 FFO of the configuration area and the start address together with cfgaddr If set to 0 the configuration will be dis abled rrobin Selects between round robin 1 or fixed priority 0 bus 0 1 0 arbitration algorithm s
485. mponent ddrspa generic fabtech integer 0 memtech integer 0 hindex integer 0 haddr integer 0 hmask integer 16 f00 ioaddr integer 16 000 iomask integer l16 fff MHz integer 100 clkmul integer 2 clkdiv integer 2 col integer 9 Mbyte integer 16 rstdel integer 200 pwron integer 0 oepol integer 0 ddrbits integer 16 ahbfreq integer 50 i port rst_ddr in std_ulogic rst_ahb in std_ulogic clk_ddr in std_ulogic clk_ahb in std_ulogic lock out std_ulogic DCM locked clkddro out std_ulogic DCM locked clkddri in std_ulogic ahbsi in ahb_slv_in type ahbso out ahb_slv_out_type ddr_clk out std_logic_vector 2 downto 0 ddr_clkb out std_logic_vector 2 downto 0 ddr_clk_fb_out out std_logic ddr_clk_fb in std_logic ddr_cke out std_logic_vector 1 downto 0 ddr_csb out std_logic_vector 1 downto 0 ddr_web out std_ulogic ddr_rasb out std_ulogic ddr ras ddr_casb out std_ulogic ddr cas ddr_dm out std_logic_vector ddrbits 8 1 downto 0 ddr_dqs inout std_logic_vector ddrbits 8 1 downto 0 ddr_ad out std_logic_vector 13 downto 0 ddr_ba out std_logic_vector 1 downto 0 ddr_dq inout std_logic_vector ddrbits 1 downto 0 i end component ddr write enable ddr dm ddr dqs ddr address ddr bank address ddr data 167 168 23 8 Instantiati
486. ms_id event_id unsigned int is_rmap unsigned int is_rxunaligned unsigned int is_rmapcrc spw_config Table 342 spw_config member descriptions Member Description nodeaddr Node address destkey Destination key clkdiv Clock division factor rxmaxlen Receiver maximum packet length timer Link interface 6 4 us timer value disconnect Link interface disconnection timeout value promiscuous Promiscuous mode timetxen Time code transmission enable timerxen Time code reception enable rmapen RMAP command handler enable rmapbufdis RMAP multiple buffer enable linkdisabled Linkdisabled linkstart Linkstart check_rmap_error Check for RMAP CRC errors in received packets rm_prot_id Remove protocol ID from received packets tx_blocking Select between blocking and non blocking transmissions tx_block_on_full Block when all transmit descriptors are occupied rx_blocking Select between blocking and non blocking receptions disable_err Disable Link automatically when link error interrupt occurs link_err_irq Enable link error interrupts event_id Task ID to which event is sent when link error interrupt occurs is_rmap RMAP command handler available is_rxunaligned RX unaligned support available is_rmapcrc RMAP CRC support available 42 15 5 Configuration The GRSPW core and driver are configured using ioctl calls The table below lists a
487. multiple RMAP buffer utilization SET_CHECK_RMAP Enable Disable RMAP CRC error check for reception SET_RM_PROT_ID Enable Disable protocol ID removal for reception SET_TXBLOCK Change blocking mode of transmissions SET_TXBLOCK_ON_FULL Change the blocking mode when all descriptors are in use SET_DISABLE_ERR Enable Disable automatic link disabling when link error occurs SET_LINK_ERR_IRQ Enable Disable link error interrupts SET_EVENT_ID SET_PACKETSIZE GET_LINK_STATUS SET_CONFIG GET_CONFIG GET_STATISTICS CLR_STATISTICS Change the task ID to which link error events are sent Change buffer sizes Read the current link status Set all configuration parameters with one call Read the current configuration parameters Read statistics Clear all statistics SEND Send a packet with both header and data buffers LINKDISABLE Disable the link LINKSTART Start the link SET_NODEADDR This call sets the node address It is only used to check the destination of incoming packets The argu ment must be an integer in the range O to 255 The call will fail if the argument contains an illegal value or if the register can not be written SET_RXBLOCK This call sets the blocking mode for receptions The argument must be an integer in the range 0 to 1 0 selects non blocking mode while 1 selects blocking mode The call will fail if the argument contains
488. multiplication is added to the 40 bit accumulator value on signal MULI ACC to form a 40 bit value on output MULO RESULT 39 0 The result of MAC operation appears during the second clock cycle after the MULIMAC was asserted Synthesis Table 420 shows hardware complexity in ASIC gates and latency for different multiplier configura tions Table 420 Multiplier latencies and hardware complexity Multiplier size multype Pipelined pipe Latency clocks Approximate area gates 16x16 1 5 6 500 16x16 0 4 6 000 32x8 4 5 000 32x16 2 9 000 32x32 1 15 000 422 48 4 Configuration options Table 421 shows the configuration options of the core VHDL generics Table 421 Configuration options Generic Function Allowed range Default infer If set the multipliers will be inferred by the synthesis tool Use Otol 1 this option if your synthesis tool i capable of inferring efficient multiplier implementation multype Size of the multiplier that is actually implemented All configu 0 to 3 0 ration produce 64 bit result with different latencies O 16x16 bit multiplier 1 32x8 bit multiplier 2 32x16 bit multiplier 3 32x32 bit multiplier pipe Used in 16x16 bit multiplier configuration with inferred option 0 to 1 0 enabled Adds a pipeline register stage to the multiplier This option gives better timing but adds one clock cycle to latency mac Enable multiply amp accumu
489. n tain a valid value and is set to one if a data CRC error was detected 42 4 9 Error handling If a packet reception needs to be aborted because of congestion on the network the suggested solution is to set link disable to 1 Unfortunately this will also cause the packet currently being transmitted to be truncated but this is the only safe solution since packet reception is a passive operation depending on the transmitter at the other end A channel reset bit could be provided but is not a satisfactory solu tion since the untransmitted characters would still be in the transmitter node The next character somewhere in the middle of the packet would be interpreted as the node address which would prob ably cause the packet to be discarded but not with 100 certainty Usually this action is performed when a reception has stuck because of the transmitter not providing more data The channel reset would not resolve this congestion If an AHB error occurs during reception the current packet is spilled up to and including the next EEP EOP and then the currently active channel is disabled and the receiver enters the idle state A bit in the channels control status register is set to indicate this condition 42 4 10 Promiscuous mode The GRSPW supports a promiscuous mode where all the data received is stored to the DMA channel regardless of the node address and possible early EOPs EEPs This means that all non eop eep N Chars received will be stor
490. n figure 143 The clock output drives all flip flops in the receiver module found in figure 137 The data signal which is used for generating the clock is also coupled to the data inputs of several flip flops clocked 334 by the Rx clock as seen in figure 143 Care must be taken so that the delay from the data and strobe signals through the clock network are longer than the delay to the data input setup time D Q D X 4 D Q Lo S gt gt Figure 143 The clocking scheme for the receiver The clock is The transmitter clock is generated from the txclk input A separate clock input is used to allow the transmitter to be run at much higher frequencies than the system clock The SpaceWire node contains a clock divider which divides the txclk signal to the wanted frequency The transmitter clock should be 10 MHz during initialization and any frequency above 2 MHz in the run state There is an input signal called clkdiv10 which sets the clock divisor value during initialization and the reset value for the user accessible clock divisor register The user register value will be used in run state The resulting tx clock frequency will be txclk clock divisor value 1 So if no clock division is wanted the clock divisor should be set to 0 Since only integer values are allowed for the clock division and the required init frequency is 10 Mhz the frequency of the txclk input must be a multiple of 10 MHz The
491. n section 35 3 6 must be set to the same values for all descriptors used for a single packet 35 3 6 Checksum offloading Support is provided for checksum calculations in hardware for TCP and UDP over IPv4 The check sum calculations are enabled in each descriptor and applies only to that packet when the MO bit is set all descriptors used for a single packet must have the checksum control bits set in the same way The IP Checksum bit IC enables IP header checksum calculations If an IPv4 packet is detected when transmitting the packet associated with the descriptor the header checksum is calculated and inserted If TCP Checksum TC is set the TCP checksum is calculated and inserted if an TCP IPv4 288 35 4 packet is detected Finally if the UDP Checksum bit is set the UDP checksum is calculated and inserted if a UDP IPv4 packet is detected Rx DMA interface The receiver DMA interface is used for receiving data from an Ethernet network The reception is done using descriptors located in memory 35 4 1 Setting up descriptors A single descriptor is shown in figure 124 The address field points at the location where the received data should be stored There are no restrictions on alignment The GRETH_GBIT will never store more than 1518 B to the buffer the tagged maximum frame size If the interrupt enable IE bit is set an interrupt will be generated when a packet has been received to this buffer this requires that the receiver
492. n the host system clock The GRSPW has a separate clock input which is used to generate the transmitter clock More information on transmitter clock generation is found in section 42 8 1 Since the transmit ter often runs on high frequency clocks gt 100 MHz as much logic as possible has been placed in the system clock domain to minimize power consumption and timing issues 321 The transmitter logic in the host clock domain decides what character to send next and sets the proper control signal and presents any needed character to the low level transmitter as shown in figure 139 The transmitter handles sends the requested characters and generates parity and control bits as needed If no requests are made from the host domain NULLs are sent as long as the transmitter is enabled Most of the signal and character levels of the Space Wire standard is handled in the transmitter Exter nal LVDS drivers are needed for the data and strobe signals D Send Time code lt I i Send FCT S Transmitter Send NChar eH Time code 7 0 NChar 8 0 Transmitter Clock Domain Host Clock Domain Figure 139 Schematic of the link interface transmitter A transmission FSM reads N Chars for transmission from the transmitter FIFO It is given packet lengths from the DMA interface and appends EOPs EEPs and RMAP CRC values if requested When it is finished with a packet the DMA interface is notified and a new packet length value is given 42 3 3 Receiver
493. n the AHB I O space using the GRLIB plug amp play functionality The CAN core interrupt is routed to the AHB interrupt bus and the interrupt number is selected through the rg generic The FIFO RAM in the CAN core is implemented using the GRLIB parametrizable SYNCRAM_2P memories assuring portability to all supported technologies This CAN interface implements the CAN 20 A and 2 0B protocolos It is based on the Philips SJA1000 and has a compatible register map with a few exceptions CAN_OC Wrapper CAN_TXO 4 CAN Core tp Syncram_2p y 1 AHB slave interface IRQ CANRXI L op AMBA AHB Figure 50 Block diagram Opencores CAN controller overview This CAN controller is based on the Philips SJA1000 and has a compatible register map with a few exceptions It also supports both BasicCAN PCA82C200 like and PeliCAN mode In PeliCAN mode the extended features of CAN 2 0B is supported The mode of operation is chosen through the Clock Divider register This document will list the registers and their functionality The Philips SJA1000 data sheet can be used as a reference if something needs clarification See also the Design considerations chapter for differences between this core and the SJA1000 The register map and functionality is different between the two modes of operation First the Basic CAN mode will be described followed by PeliCAN Common registers clock divisor
494. n the AHB data bus For non aligned 16 bit half word write accesses the byte should be driven on the bits of the AHB data bus that correspond to the byte address big endian For 8 bit word write accesses the byte should always be driven on the AHB data bus bits that corresponds to the byte address big endian To summarize all legal AMBA AHB write accesses are supported according to the AMBA standard additional illegal accesses are supported as described above and it is always the addressed byte that is output It is possible to dynamically switch between 8 and 32 bit PROM mode by writing to the RBW field of the MCFG1 register The BWIDTH 1 0 input signal determines the reset value of this RBW regis ter field When RBW is 00 then 8 bit mode is selected If RBW is 10 then 32 bit mode is selected Other RBW values are reserved for future use SRAM access is not affected by the 8 bit PROM mode It is also possible to use the EDAC in the 8 bit PROM mode configured by the edacen VHDL generic and enabled via the MCFG3 register Read accesses to the 8 bit PROM area will be done in five byte bursts for all 32 16 and 8 bit AMBA AHB accesses After a potential correction the whole 32 bit word is output on the AHB data bus allowing the master to chose the bytes needed big endian EDAC support is not provided for write accesses they are instead performed in the same way as without the EDAC enabled The checksum byte must be written by t
495. n the core Only readable 30 Rx Unaligned access Set to one if unaligned writes are available for the receiver Only readable 31 RMAP available Set to one if the RMAP command handler is available Only readable Figure 144 GRSPW control register 31 337 24 23 21 8 7 6 54 3 2 1 0 LS EE 14 wE PE DE ER CE TO Tick Out TO A new time count value was received and is stored in the time counter field Cleared when written with a one Reset value 0 Credit Error CE A credit has occurred Cleared when written with a one Reset value 0 Escape Error ER An escape error has occurred Cleared when written with a one Reset value 0 Disconnect Error DE A disconnection error has occurred Cleared when written with a one Reset value 0 Parity Error PE A parity error has occurred Cleared when written with a one Reset value 0 Write synchronization Error WE A synchronization problem has occurred when receiving N Chars Cleared when written with a one Reset value 0 Invalid Address IA Set to one when a packet is received with an invalid destination address field i e it does not match the nodeaddr register Cleared when written with a one Reset value 0 Early EOP EEP EE Set to one when a packet is received with an EOP after the first byte for a non rmap packet and after the second byte for a RMAP packet Cleared when writte
496. n with a one Reset value 0 23 21 Link State LS The current state of the start up sequence 0 Error reset 1 Error wait 2 Ready 3 Started 4 Connecting 5 Run Reset value 0 Figure 145 GRSPW status register 31 8 7 0 RESERVED NODE ADDRESS 7 0 8 bit node address used for node identification on the SpaceWire network Reset value 254 Figure 146 GRSPW node address register 31 8 7 0 RESERVED CLOCK DIVISOR 7 0 8 bit Clock divisor value used for the clock divider when the link interface is in the run state The actual divisor value is Clock Divisor register 1 Reset value clkdiv10 input signal Figure 147 GRSPW clock divisor register 31 8 7 0 RESERVED DESTINATION KEY 7 0 RMAP destination key Reset value 0 Figure 148 GRSPW destination key register 338 31 8 7 6 5 0 RESERVED TIME CTRL TIME COUNTER 5 0 31 Time Counter The current value of the system time counter It is incremented for each tick in and the incremented value is transmitted The register can also be written directly but the written value will not be transmitted Received time counter values are also stored in this register Reset value 0 Time Control Flags The current value of the time control flags Sent with time code resulting from a tick in Received control flags are also stored in this register Reset value 0 Figure 149 GRSPW time register 22 21
497. nality can be enabled disabled during run time from the ECFG register and the logic can also be completely removed during synthesis with VHDL generics The ECFG register also contains control bits and checkbit fields for diagnostic reads These diagnostic functions are used for testing the EDAC functions on chip and allows one to store arbitrary checkbits with each written word Checkbits read from memory can also be controlled 64 bit bus support is not provided when EDAC is enabled Thus the sd64 and edacen VHDL generics should never be set to one at the same time Registers The memory controller is programmed through register s mapped into the AHB I O space defined by the controllers AHB BARI If EDAC is enabled through the use of the edacen VHDL generic an EDAC configuration register will be available Table 210 FT SDRAM controller registers AHB address offset Register 0x0 SDRAM Configuration register 0x4 EDAC Configuration register 214 28 3 1 SDRAM configuration register SDCFG SDRAM configuration register is used to control the timing of the SDRAM 3130 29 27 26 25 23 22 21 20 19 15 14 0 D64 SDRAM refresh reload value E SDRAM command SDRAM Col size SDRAM Bank size CAS delay tRCD tRFC tRP Refresh enable Figure 86 SDRAM configuration register 14 0 The period between each AUTO REFRESH command Calculated as follows tpppresy reload value
498. nce GRFPU available from Gaisler Research and one for the Meiko FPU core available from Sun Microsystems The floating point processors and co processor execute in parallel with the integer unit and does not block the operation unless a data or resource dependency exists 44 1 4 Memory management unit A SPARC V8 Reference Memory Management Unit SRMMU can optionally be enabled The SRMMU implements the full SPARC V8 MMU specification and provides mapping between multi ple 32 bit virtual address spaces and 36 bit physical memory A three level hardware table walk is implemented and the MMU can be configured to up to 64 fully associative TLB entries 44 1 5 On chip debug support The LEON3 pipeline includes functionality to allow non intrusive debugging on target hardware To aid software debugging up to four watchpoint registers can be enabled Each register can cause a breakpoint trap on an arbitrary instruction or data address range When the optional debug support unit is attached the watchpoints can be used to enter debug mode Through a debug support interface full access to all processor registers and caches is provided The debug interfaces also allows single stepping instruction tracing and hardware breakpoint watchpoint control An internal trace buffer can monitor and store executed instructions which can later be read out over the debug interface 44 1 6 Interrupt interface LEONS3 supports the SPARC V8 interrupt model wit
499. nction completed successfully 1 The new node address value is illegal Table 363 Parameters for spw_set_nodeadr Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured int spw_set_rxmaxlength struct spwvars spw Sets the Receiver maximum length register with the rxmaxlen value stored in the spwvars struct Table 364 Return values for spw_set_rxmaxlength Value Description 0 The function completed successfully 1 The new node address value is illegal Table 365 Parameters for spw_set_rxmaxlength Parameter Description Allowed range spw Pointer to the spwvars struct associated with GRSPW core that should be configured int spw_tx int crc int skipcrcsize int hsize char hbuf int dsize char dbuf struct spwvars spw Transmits a packet Separate header and data buffers can be used If CRC logic is available the GSPW inserts RMAP CRC values after the header and data fields if crc is set to one This function only sets a descriptor and initiates the transmission Spw_checktx must be used to check if the packet has been transmitted A pointer into the descriptor table is stored in the spwvars struct to keep track of the next location to use It is incremented each time the function returns 0 Table 366 Return values for spw_tx Value Description 0 The function completed successfully 1 The
500. nction on multi function device 7 2 Register Number REGISTER Used to index a PCI DWORD in Configuration Space 1 0 Should always be driven to 00 to generate Type 0 Configuration cycle I O cycles Single PCI I O cycles are supported Lower 64 kB of the AHB I O address space occupied by masters AHB slave interface are translated into PCI I O cycles Mapping is deter mined by value of I O Map register PCI memory cycles are performed by accessing 256 MB AHB address space occupied by masters AHB slave Mapping and PCI command generation are determined by value of AMBA Configu ration Status register Burst operation is supported for PCI memory cycles The PCI commands generated by the master are directly dependant of the AMBA transfer type and the value of Configuration Status register The Configuration Status register can be programmed to issue Memory Read Memory Read Line Memory Read Multiple Memory Write or Memory Write and Invalidate If a burst AHB access is made to PCI Masters AHB memory space it is translated to burst PCI mem 50 7 433 ory cycle When the PCI Master interface is busy performing the transaction on the PCI bus its AHB slave interface will not be able to accept new requests Retry response will be given to all accesses to its AHB slave interface Requesting AHB Master should repeat its request until OK or Error response is given by the PCI Masters AHB slave interface Note that
501. nd accumulate instructions To accelerate DSP algorithms two multiply amp accumulate instructions are implemented UMAC and SMAC The UMAC performs an unsigned 16 bit multiply producing a 32 bit result and adds the result to a 40 bit accumulator made up by the 8 Isb bits from the y register and the asr18 register The least significant 32 bits are also written to the destination register SMAC works similarly but per forms signed multiply and accumulate The MAC instructions execute in one clock but have two clocks latency meaning that one pipeline stall cycle will be inserted if the following instruction uses the destination register of the MAC as a source operand Assembler syntax umacrsl reg_imm rd smacrsl reg_imm rd Operation prod 31 0 rs1 15 0 reg_imm 15 0 result 39 0 Y 7 0 asr18 31 0 prod 31 0 Y 7 0 Sasr18 31 0 result 39 0 rd result 31 0 asr18 can be read and written using the RDASR and WRASR instructions 44 2 7 Hardware breakpoints The integer unit can be configured to include up to four hardware breakpoints Each breakpoint con sists of a pair of application specific registers asr24 25 asr26 27 Yoasr28 30 and asr30 31 registers one with the break address and one with a mask 31 2 1 0 asr24 Yoasr26 Yoasr28 Yoasr30 WADDR 3 1 2 IF 31 2 0 asr25 Yoasr27 oasr29 asr3 1 WMASK 31 2 DL DS Figure 167 Watch point registers Any binary a
502. ndex APB slave index 0 NAPBSLV 1 0 paddr ADDR field of the APB BAR 0 16 FFF 0 pmask MASK field of the APB BAR 0 16 FFO 16 FFO pirq Index of the interrupt line 0 NAHBIRQ 1 0 endian Data endianness of the AHB bus Big 0 Little 1 0 1 0 ahbaddr Reset value for address register 16 00000 16 FFFFF 16 00000 abits Number of bits needed to address the memory area 12 17 17 rtaddr RT address 0 31 0 rtaddrp RT address parity bit Set to achieve odd parity 0 1 1 lockn Lock rtaddrin rtaddrp mselin and abstdin 0 1 0 mselin Mode select 0 3 0 abstdin Bus standard A B 0 1 0 bcenable Enable bus controller 0 1 1 rtenable Enable remote terminal 0 1 1 mtenable Enable bus monitor 0 1 1 legregs Enable legalization registers 0 1 1 enhanced Enable enhanced register 0 1 1 initfreq Initial operation frequency 12 16 20 24 20 betiming Backend timing 0 1 1 Except for endian ahbaddr and abits these generics drive the corresponding signal or generic of the Core1553BRM core Bcenable rtenable mtenable legregs enhanced initfreq and betiming connects to generics on the Core1553BRM core and therefore are ignored unless the RTL version is used 110 19 7 Signal descriptions Table 106 shows the interface signals of the core VHDL ports Table 106 Signal descriptions
503. ndor and device identifiers o oooonnnocnonconnconccononnnonnnononanonnnonnrnn non no nn non nono con E non neon EESE enr 258 32 9 Configtitation O IODS a E tt 258 32 10 Sig al descriptions init e rod 258 32 11 AAA tress orike reus eere shan enre SE o ton EEEE E S Soeke VESON E ES ihi 258 32 12 Instantia oN tout iia 258 GRECC Elliptic Curve Cryptography a tit 260 33 1 RN 260 33 2 A O RN 260 34 35 36 33 3 Advantages iia bailaora 261 33 4 Back Sround oir pc rin cali rt cdas 261 33 5 233 bit elliptic curve domain parameters eeeesseeesseseerssrsteresetrrsteetsrsterrsstetssererseertrtertsteneerrnereteseet 261 33 6 Troup U a tt ES 262 33 7 Characteristics 262 33 8 REGISTERS rat abit 263 33 9 Vendor and device identifiers ce eescencecsseeensceereesecececeseecsueeeaeeceeeceaeceseecsaceeseeceneecseeeeeeeeeeesaeseates 268 33 10 Configtiration options iesise o risisco iuo rees riekin cobscauacbecnscevgeuscbsagchcodsbevschsassagescsoescbs 269 33411 Signal descriptions 3 45 E EE EEE TE AT EAT 269 33 12 A TO 269 O E ON 269 GRETH Ethernet Media Access Controller MAC with EDCL suppott ee 271 34 1 IIA A NON 271 34 2 Opera isa seriada ari 271 34 3 TEDMA terface es ais sees Ges vec see ci ca Sete cent es an ea bag oa sata vac r da ash dab ocd aaa E cave dase bet a dip eecnweagant 272 34 4 RA DMA interface creci rica invasi n 274 34 5 MDIO Intertace int eiii 275 34 6 Ethernet Debug Communication Link
504. ndx gt 0 port map rstn clkm ahbmi ahbmo 0 ahbsi ahbso 0 AHB slave sr0 srctrl generic map hindex gt 3 port map rstn clkm ahbsi ahbso 3 memi memo sdo3 AHB master el eth_oc generic map mstndx gt 2 slvndx gt 5 ioaddr gt CFG_ETHIO irq gt 12 memtech gt memtech port map rstn clkm ahbsi ahbso 5 ahbmi gt ahbmi ahbmo gt ahbmo 0 2 ethil ethol end Debug print out If the debug generic is set to 2 the plug amp play information of all attached AHB units on the current AHB bus are printed to the console during the start of simulation Reporting starts by scanning the master interface array from 0 to NAHBMST 1 defined in the grlib amba package It checks each entry in the array for a valid vendor id all nonzero ids are considered valid and if one is found it also retrieves the device id The descriptions for these ids are obtained from the GRLIB DEVICES pack age and are then printed on standard out together with the master number If the index check is enabled done with a VHDL generic the report module also checks 1f the hindex number returned in the record matches the array number of the record currently checked the array index If they do not match the simulation is aborted and an error message is printed This procedure is repeated for slave interfaces found in the slave interface array It is scanned from 0 to NAHBSLV 1 and the same information is pri
505. ne Size register in Configuration Space Header Read only 31 16 15 i IOMAP RESERVED Figure 212 I O Map register 31 16 I O Map IOMAP Most significant bits of PCI address when performing PCI I O cycle Concatenated with low bits of AHB address to from PCI address 15 0 Reserved Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x014 For description of vendor and device identifiers see GRLIB IP Library User s Manual 50 9 Configuration options Table 431 shows the configuration options of the core VHDL generics Table 431 Configuration options 435 Generic Function Allowed range Default memtech The memory technology used for the FIFO instantiation 0 mstndx The AMBA master index for the target backend AHB master 0 NAHBMST 1 0 interface dmamst The AMBA master index for the DMA controller if present 0 NAHBMS NAHBMST This value is used by the PCI core to detect when the DMA con disabled troller accesses the AHB slave interface readpref Prefetch data for the memory read command If set the target 0 1 0 prefetches a cache line otherwise the target will give a single word response abits Least significant implemented bit of BARO and PAGEO regis 16 28 21 ters Defines PCI address space size dmaabits Least significant implemented bit of BAR1 and
506. nearest interger value Teoc TO T1 T2 or T9 or T2i whichever is greater For more timing information read the ATA ATAPI 5 standard document and see figure 38 The PCTR timing register determines the timing for all PIO access except for access to the data reg ister For data register access the timing is determined by the PFTRO or the PFTR1 register TO 4 CS DA X KX DIOR DIOW Data Read x x l Data Write X T4 TI T2 Teoc t gt af lt i B Figure 38 PIO timing diagram 17 4 17 5 Table 93 ATA Device Registers 97 Name Offset Width Data Register 0x40 16 Features Error Register 0x44 8 Sector Number Register 0x48 8 Sector Count Register Ox4c 8 Cylinder Low Register 0x50 8 Cylinder High Register 0x54 8 Device Head Register 0x58 8 Command Status Register Ox5c 8 Alternate Status Device Control Register 0x78 8 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x024 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 94 shows the configuration options of the core VHDL generics Table 94 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 haddr ADDR filed of the AHB BARO defining the address 0
507. nerics col and Mbyte can be used to also set the correct address decoding after reset In this case no further software initialization is needed The DDR initialization can be performed at a later stage by setting bit 15 in the DDR control register 23 2 5 Configurable DDR SDRAM timing parameters To provide optimum access cycles for different DDR devices and at different frequencies three tim ing parameters can be programmed through the memory configuration register SDCFG TRCD TRP and TRECD The value of these field affects the SDRAM timing as described in table 175 Table 175 DDR SDRAM programmable minimum timing parameters SDRAM timing paramteter Minumum timing clocks Precharge to activate tgp TRP 2 Auto refresh command period trc TREC 3 Activate to read write tcp TRCD 1 Activate to Activate tac TRP TRFC 4 If the TCD TRP and TRFC are programmed such that the DDR200 266 specifications are fullfilled the remaining SDRAM timing parameters will also be met The table below shows typical settings for 100 and 133 MHz operation and the resulting SDRAM timing in ns Table 176 DDR SDRAM example programming DDR SDRAM settings trop trc tre trrc tras 100 MHz TRP 0 TRFC 4 TRCD 0 20 80 20 70 50 133 MHz TRP 1 TRFC 6 TRCD 1 20 82 22 67 52 The DDRSPA controller always uses CAS latency CL of two cycles This means the a DDR SDRAM speed grade of 75Z or bette
508. nfigured through three configuration registers accessible via an APB bus interface The external data bus can be configured in 8 16 or 32 bit mode depending on application requirements The controller decodes three address spaces on the AHB bus PROM IO and SRAM SDRAM The addresses are determined through VHDL generics External chip selects are provided for up to four PROM banks one IO bank five SRAM banks and two SDRAM banks Figure 65 below shows how the connection to the different device types is made APB AHB A D CB ROMSNI3 0 cs A tt OEN o PROM p k gt WRITEN WE CB gt APB IOSN cs A tk OE VO DK gt WE FTMCTRL RAMSN 4 0 cs A t RAMOEN 4 0 OE SRAM p k gt RWEN 3 0 WE MBEN 3 0 MBEN e3 ur AHB SDCSN 1 0 CSN A fF SDRASN RAS SDRAM P H gt SDCASN CAS CB k a SDWEN WE SDDQM 3 0 DQM A 27 0 gt D 31 0 ke gt CB 7 0 le gt Figure 65 FTMCTRL connected to different types of memory devices PROM access Up to four PROM chip select signals are provided for the PROM area ROMSN 3 0 There are two modes one with two chip select signals and one with four The size of the banks can be set in binary steps from 16 kB to 256 MB A read access to PROM consists of two data cycles and between 0 and 30 waitstat
509. ng Speed SP Sets the current speed mode 0 10 Mbit 1 100 Mbit Must not be set to 1 at the same time as bit 8 GB Gigabit GB 1 sets the current speed mode to 1000 Mbit and when set to 0 the speed mode is selected with bit 7 SP Burstmode BM When set to 1 transmissions use burstmode in 1000 Mbit Half duplex mode GB 1 FD 0 When 0 in this speed mode normal transmissions are always used with extension inserted Operation is undefined when set to 1 in other speed modes Gigabit Mac Available GA This bit always reads as a 1 and indicates that the MAC has 1000 Mbit capability EDCL Buffer Size BS Shows the amount of memory used for EDCL buffers 0 1 kB 1 2 kB 6 64 kB EDCL Available ED Set to one if the EDCL is available 293 76 54 32510 IA TS TA RA TI RI TE RE Figure 126 GRETH_GBIT status register O Receiver Error RE A packet has been received which terminated with an error Cleared when written with a one Not Reset 1 Transmitter Error TE A packet was transmitted which terminated with an error Cleared when written with a one Not Reset 2 Receive Successful RI A packet was received without errors Cleared when written with a one Not Reset 3 Transmit Successful TI A packet was transmitted without errors Cleared when written with a one Not Reset 4 Receiver AHB Error RA An
510. ng but a correction cycle scheme 1 and 3 will delay the the current instruction with 6 clock cycles An uncorrectable error in the IU register file will cause trap 0x20 register_access_error An uncorrectable error in the FPU register file will cause an deferred FPU exception with fsr ftt set to 5 hardware_error 45 3 393 45 2 2 FPU SEU protection The FPU register file has similar SEU protection as the IU register file but with less configuration options When the GRFPU is enabled the protection scheme is always 7 bit BCH with pipeline restart When GRFPU Lite is enable the rotection scheme is always 4 bit parity with pipeline restart Table 406 DP ram select usage TE DP Function 1 0 Write to IU register i l o g will only write location of rs1 Write to FPU register f will only write location of rs2 1 1 Write to IU register i l o g will only write location of rs2 Write to IU register f will only write location of rs1 0 X IU and FPU registers written nominally 45 2 3 ASR16 register ASR register 16 asr16 is used to control the IU FPU register file SEU protection It is possible to disable the SEU protection by setting the IDI FDI bits and to inject errors using the ITE FTE bits Corrected errors in the register file are counted and available in ICNT and FCNT fields The counters saturate at their maximum value 7 and should be reset by software after read out
511. ng Ethernet controllers with smaller pin counts It uses 6 7 signals which are a subset of the MII signals Table 300 shows the mapping betweem the RMII signals and the GRLIB MII interface Table 300 Signal mappings between RMII and the GRLIB MII interface RMI MII txd 1 0 txd 1 0 tx_en tx_en crs_dv rx_crs rxd 1 0 rxd 1 0 ref_clk rmii_clk rx_er not used Software drivers Drivers for the GRETH MAC is provided for the following operating systems RTEMS eCos uClinux and Linux 2 6 The drivers are freely available in full source code under the GPL license from Gaisler Research s web site http gaisler com 278 34 9 Registers The core is programmed through registers mapped into APB address space Table 301 GRETH registers APB address offset Register 0x0 Control register 0x4 Status Interrupt source register 0x8 MAC Address MSB OxC MAC Address LSB 0x10 MDIO Control Status 0x14 Transmit descriptor pointer 0x18 Receiver descriptor pointer Ox1C EDCL IP 31 30 28 7 65432 10 ED BS RESERVED sP RS PR FD RI TI RE TE 30 28 31 31 Figure 114 GRETH control register Transmit Enable TE Should be written with a one each time new descriptors are enabled As long as this bit is one the GRETH will read new descriptors and as soon as it encounters a disabled descriptor it will stop until TE is set again This
512. ng of the float ing point FP operations to the floating point units as well as managing the floating point register file the floating point state register FSR and the floating point deferred trap queue FQ The GRFPU Lite floating point unit is not pipelined and executes thus only one instruction at a time To improve performance the controller GRLFPC allows the GRFPU Lite floating point unit to exe cute in parallel with the processor pipeline as long as no new floating point instructions are pending Floating Point register file The floating point register file contains 32 32 bit floating point registers f0 f31 The register file is accessed by floating point load and store instructions LDF LDDF STD STDF and floating point operate instructions FPop In the FT version the floating point register file is protected using 4 bit parity per 32 bit word The controller is capable of detecting and correcting one bit error per byte Errors are corrected using the instruction restart function in the IU Floating Point State Register FSR The controller manages the floating point state register FSR containing FPU mode and status infor mation All fields of the FSR register as defined in SPARC V8 specification are implemented and managed by the controller conform to the SPARC V8 specification and IEEE 754 standard The non standard bit of the FSR register is not used all floating point operation are performed in standard IEEE
513. nhibit for the B transmitter High busboutp Positive output to the B transmitter High busboutn Negative output to the B transmitter Low RTI Input RT input signals cmdok Command word validation alright High useextok Enable external command word validation High RTO Output RT output signals msgstart Message process started High cmdsync Start of command word on bus High syncnow Synchronize received High busreset Reset command received High cmdval Active command cmdokout Command word validated High cmdstb Active command value changed High addrlat Address latch enable High intlat Interrupt latch enable High APBI Input APB slave input signals APBO Output APB slave output signals AHBI Input AMB master input signals AHBO Output AHB master output signals see GRLIB IP Library User s Manual 118 20 7 20 8 20 9 Library dependencies Table 112 shows libraries that should be used when instantiating the core VHDL libraries Table 112 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals Signal definitions GAISLER B1553 Signals component Signal and component declaration The B1553RT depends on GRLIB GAISLER GR1553 and Core1553BRT Component declaration The core has the following component declaration component b1553rt is generic hindex integer 0 pindex integer 0 paddr integer 0 pmask integer l6 fff pirg
514. not involved in bus activities SR 6 Error status At least one of the error counters have reached or exceeded the CPU warning limit 96 SR 5 Transmit status 1 when transmitting a message SR 4 Receive status 1 when receiving a message SR 3 Transmission complete l indicates the last message was successfully transferred SR 2 Transmit buffer status 1 means CPU can write into the transmit buffer SR 1 Data overrun status 1 if a message was lost because no space in fifo SR O Receive buffer status 1 if messages available in the receive fifo Receive buffer status is cleared when the Release receive buffer command is given and set high if there are more messages available in the fifo The data overrun status signals that a message which was accepted could not be placed in the fifo because not enough space left NOTE This bit differs from the SJA1000 behavior and is set first when the fifo has been read out When the transmit buffer status is high the transmit buffer is available to be written into by the CPU During an on going transmission the buffer is locked and this bit is 0 The transmission complete bit is set to 0 when a transmission request has been issued and will not be set to 1 again until a message has successfully been transmitted 21 4 5 Interrupt register The interrupt register signals to CPU what caused the interrupt The interrupt bits are only set if the corresponding interrupt enable bit is set in the control
515. nstruction can be started each cycle as long as there are no data dependencies When finished the result is writ ten back to the co processor register file 44 8 44 9 385 Vendor and device identifiers The core has vendor identifiers 0x01 Gaisler Research and device identifiers 0x003 For description of vendor and device identifiers see GRLIB IP Library User s Manual Implementation 44 9 1 Area and timing Both area and timing of the LEON3 core depends strongly on the selected configuration target tech nology and the used synthesis tool The table below indicates the typical figures for two baseline con figurations Table 401 Area and timing Actel AX2000 ASIC 0 13 um Configuration Cells RAM64 MHz Gates MHz LEON3 8 8 Kbyte cache 6 500 40 30 20 000 400 LEON3 8 8 Kbyte cache DSU3 7 500 40 25 25 000 400 44 9 2 Technology mapping LEONS3 has two technology mapping generics fabtech and memtech The fabtech generic controls the implementation of some pipeline features while memtech selects which memory blocks will be used to implement cache memories and the IU FPU register file Fabtech can be set to any of the provided technologies 0 NTECH as defined in the GRPIB TECH package See the GRLIB Users s Manual for available settings for memtech 44 9 3 Double clocking The LEON3 CPU core be clocked at twice the clock speed of the AMBA AHB bus When clocked at double AHB cloc
516. nta tion contains a one at the position corresponding to the rule number e g 0x80 disables rule 7 hslvdisable Disable AHB slave tests Values are assigned as for 0 hmstdisable pslvdisable Disable APB slave tests Values are assigned as for hmst 0 disable arbdisable Disable Arbiter tests Values are assigned as for hmstdis 0 able nahbm Number of AHB masters in the system 0 NAHBMST NAHBMST nahbs Number of AHB slaves in the system 0 NAHBSLV NAHBSLV napb Number of APB slaves in the system 0 NAPBSLV NAPBSLV Signal descriptions Table 60 shows the interface signals of the core VHDL ports Table 60 Signal descriptions Signal name Field Type Function Active RST N A Input AHB reset Low CLK N A Input AHB clock AHBMI pe Input AHB master interface input record AHBMO t Input AHB master interface output record array AHBSI Input AHB slave interface input record AHBSO Input AHB slave interface output record array APBI Input APB slave interface input record APBO Input APB slave interface output record array ERR N A Output Error signal error detected High see GRLIB IP Library User s Manual Library dependencies Table 61 shows libraries used when instantiating the core VHDL libraries Table 61 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions GAISLER SIM Component Component declaration
517. nted and the same checks are done as for the master interfaces In addition the address range and memory type is checked and printed The address infor mation includes type address mask cacheable and pre fetchable fields From this information the report module calculates the start address of the device and the size of the range The information finally printed is type start address size cacheability and pre fetchability The address ranges cur rently defined are AHB memory AHB I O and APB I O APB I O ranges are ignored by this module vsim c quiet leon3mp VSIM 1 gt run LEON3 MP Demonstration design GRLIB Version 1 0 7 Target technology inferred memory library inferred ahbctrl AHB arbiter multiplexer rev 1 ahbctrl Common I O area disabled ahbctrl Configuration area at Oxfffff000 4 kbyte ahbctrl mst0 Gaisler Research Leon3 SPARC V8 Processor ahbctrl mst1 Gaisler Research AHB Debug UART ahbctrl slv0 European Space Agency Leon2 Memory Controller ahbctrl memory at 0x00000000 size 512 Mbyte cacheable prefetch ahbctrl memory at 0x20000000 size 512 Mbyte ahbctrl memory at 0x40000000 size 1024 Mbyte cacheable prefetch ahbctrl slvl Gaisler Research AHB APB Bridge ahbctrl memory at 0x80000000 size 1 Mbyte apbctrl APB Bridge at 0x80000000 rev 1 apbctrl slv0 European Space Agency Leon2 Memory Controller apbctrl I O ports at 0x80000000 size 256 byte apbctrl
518. nteger 8 sepclk integer 0 port rclk in std_ulogic renable in std_ulogic raddress in std_logic_vector abits 1 downto 0 dataout out std_logic_vector dbits 1 downto 0 wclk in std_ulogic write in std_ulogic waddress in std_logic_vector abits 1 downto 0 datain in std_logic_vector dbits 1 downto 0 end component Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library techmap use techmap gencomp all rclk in std_ulogic renable in std_ulogic raddress in std_logic_vector abits 1 downto 0 dataout out std_logic_vector dbits 1 downto 0 wclk in std_ulogic 485 write in std_ulogic waddress in std_logic_vector abits 1 downto 0 datain in std_logic_vector dbits 1 downto 0 ram0 syncram_2p generic map tech gt tech abits gt addrbits dbits gt dbits port map rclk renable raddress dataout wclk write waddress datain enable write 486 61 61 1 61 2 SYNCRAM_DP Dual port RAM generator Overview The dual port RAM generator has two independent read write ports Each port has a separate address and data bus All inputs are latched on the on the rising edge of clk The read data appears on dataout directly after the clk rising edge Address width data width and target technology is parametrizable through generics Simultaneous write to the sam
519. nteger integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer in std in sta in ahb_ ahb_ in apb_ apb_ out out 0 0 16 f04 1644004 16 f04 162004 16 f04 to 8 to 15 to 8 to 15 to 15 K w Q 10 OE Go E 16 fff 0 to 1 0 to 1 1 to range range range 0 0 0 ulogic ulogic slv_in_type slv_out_type slv_in_type slv_out_type in memory_in_type out out memory_out_type sdctrl_out_type 1 Lo 1 15 15 The example design contains an AMBA bus with a number of AHB components connected to it including the memory controller The external memory bus is defined in the example design s port map and connected to the memory controller System clock and reset are generated by GR Clock Gen erator and Reset Generator The CE signal of the memory controller is also connected to the AHB sta tus register 233 Memory controller decodes default memory areas PROM area is 0x0 OXFFFFFF and RAM area is 0x40000000 0x40FFFFF library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all use gaisler pads all used for I O pads use gaisler misc all entity mctrl_ex is port clk in std_ulogic resetn in std_ulogic pllref in std_
520. nterface ooononionnncinonesnonicconcconnennornnccannccconnanos 83 15 1 IO O veg sestau be iiaet asdquannue cos tubeeah cose E AS AT 83 15 2 O seiors ae aer ee ck ca sste tees gua ES eR ences ADEE EE SEES KEE aE EEE EEAS SE uoetcusctesbebensepeescbuaecseed 83 15 3 Baud rate generator aii 85 15 4 RESISTERS 2 oes oor Los aa 86 15 5 Vendora d device iden values 87 15 6 Configuration OPtiOns min a a 87 15 7 Signal deSCrIPplONS cionado cto irsiy ieo cesses cob ebuetvseven svace ekb Oeo kN KEKE E estad e dea 88 15 8 Library dependencies renien nicole dolia dit ii lcd 88 15 9 Ipstantiation es nd CoE ee EE kE VEEE EA EEEE EED rS EE conan lisas ee 88 APBVGA VGA controller with APB interface oooonnocnnoncnoncnnncnnonncnnnnnnnnnonacono nono nccnncnonnnoo 90 16 1 ofi osa A RA 90 17 18 19 20 16 2 Op ra ein iia iia 90 16 3 RESISTORS miooo piro iia e ett 91 16 4 Vendor and device identifiers oooooncononnonnconcoanonnnonnnannnnncnnnon nono c on non nc cn ncn neon non nennn cnn rca cnn nen cnn nrnn cnn ncnncanccnnos 91 16 5 Configuration Opos aaa 92 16 6 Signal descriptions nia RE RA heey 92 16 7 Library dependenci S eiii iii 92 16 8 A A O 92 ATACTRI ATA Controller tinta il 94 17 1 OVNI Wei 94 17 2 A A ROO 94 17 3 ROBISLERS cova ccccsscuci E E paches svbea aio aaa E 95 17 4 Vendor and device 1G enters so ssedeesvaccsstssieh tees szetpshpsessseeusbassssaseveed sss dean serian EREE eE VEIRE o sia 97 17 5 Configuration Options v
521. nterface signals of the core VHDL ports Table 311 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBMI Input AMB master input signals AHBMO t Output AHB master output signals APBI Input APB slave input signals APBO T Output APB slave output signals ETHI s Input Ethernet MII input signals ETHO Output Ethernet MII output signals see GRLIB IP Library User s Manual 35 13 Library dependencies Table 312 shows libraries used when instantiating the core VHDL libraries Table 312 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER ETHERNET_MAC Signals component GRETH_GBIT component declarations GRETH_GBIT signals GAISLER NET Signals Ethernet signals 35 14 Instantiation This example shows how the core an be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler ethernet_mac all entity greth_ex is port clk in std_ulogic rstn in std_ulogic ethernet signals ethi in eth_in_type etho in eth_out_type i end architecture rtl of greth_ex is AMBA signals signal apbi signal apbo signal ahbmi apb_slv_in_type apb_slv_out_vector others gt apb_none ahb_mst_in_type
522. nterrupt n 0 Reserved 43 3 2 Interrupt pending register 31 16 15 1 0 000 0 IP 15 1 0 Figure 158 Interrupt pending register 31 17 Reserved 16 1 Interrupt Pending n IP n Interrupt pending for interrupt n 0 Reserved 365 43 3 3 Interrupt force register NCPU 0 31 16 15 1 0 000 0 TF 15 1 0 Figure 159 Interrupt force register 31 16 Reserved 15 1 Interrupt Force n IF n Force interrupt nr n 0 Reserved 43 3 4 Interrupt clear register 31 16 15 1 0 000 0 IC 15 1 0 Figure 160 Interrupt clear register 31 16 Reserved 15 1 Interrupt Clear n IC n Writing 1 to ICn will clear interrupt n 0 Reserved 43 3 5 Multiprocessor status register 31 28 16 15 0 NCPU 000 0 STATUS 15 0 Figure 161 PMultiprocessor status register 31 28 NCPU Number of CPU s in the system 1 27 16 Reserved 15 1 Power down status of CPU n 1 power down 0 running Write with 1 to force processor n out of power down 43 3 6 Processor interrupt mask register 31 16 15 1 0 000 0 IM 15 1 0 Figure 162 Processor interrupt mask register 31 16 Reserved 15 1 Interrupt Mask n IM n If IMn 0 the interrupt n is masked otherwise it is enabled 0 Reserved 366 43 4 43 5 43 3 7 Broadcast register NCPU gt 1 31 16 1
523. nterrupt registers comprise the following e Pending Interrupt Masked Status Register CanPIMSR R e Pending Interrupt Masked Register CanPIMR R e Pending Interrupt Status Register CanPISR R e Pending Interrupt Register CanPIR R W e Interrupt Mask Register CanIMR R W e Pending Interrupt Clear Register CanPICR W Table 170 Interrupt registers 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Tx Loss 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx Tx Rx OR Off Pass Miss Err Err Syn Syn Emp Full IRQ IRQ AH AH Cntr Cntr e c ty B B Err Err 16 TxLoss Message arbitration lost during transmission could be caused by communcations error as indicated by other interrupts as well 15 RxMiss Message filtered away during reception 14 TxErrCntr Transmission error counter incremented 13 RxErrCntr Reception error counter incremented 12 TxSync Synchronization message transmitted 11 RxSync Synchronization message received 10 Tx Successful transmission of message 9 Rx Successful reception of message 8 TxEmpty Successful transmission of all messages in buffer 7 RxFull Successful reception of all messages possible to store in buffer 6 TxIRQ Successful transmission of a predefined number of messages 5 RxIRQ Successful reception of a predefined number of messages 4 TxAHBErr AHB error during transmission 3 RxAHBErr AHB er
524. ntifiers oooooncnonnoncconconocononnnonnnnnonanonn conc non crono nn non nc nn E E nono non recono E nan narran craneo 242 30 6 Configtitation Options tetera 242 30 7 Signal descriptas ptes tas 243 30 8 Library dependencies sssrini hse risers ekod sects snack cedida EE CESES SEE VEK Sbe be eE dirias 246 30 9 Component declarations sieer ereere eene arene rE sys EErEE sea ates inca EEES EER NERSE eSEE ERSEK EARS 246 30 10 Instant O id 246 GPTIMER General Purpose Timer Unit ii A A a AA 249 31 1 OVA VW iii lidia 249 31 2 Operation es 249 31 3 RESISTORS ui a id bas 250 31 4 Vendor and device identifiers ooooooncnonnoncnonconocononnnonnnononanonnnonnnnn rE nn non ES E E nono non neon S eerie ns 251 31 5 Configuration Options c cc cscs ctoussee te eheuscesvs evens Rinden an eee baena 252 31 6 Signal description Se i iii llas iii 252 31 7 AA dh ccscs esc cost sce ck sock sob cs sed ieceveutsbovsen cas SEEE VE Lo Sbe be VEKSTEN zoa Sht 253 31 8 ISO ad ti tt 253 GRAES Advanced Encryption Standard cccsssccsssscssssscsssssessssncessacesenaceesscesenneesnaes 254 32 1 COVERVISW h sesh ss ante iodo seg ones BR ahd a E Succes bask e a aeaiee Sa e ESNE Vea oean aaao hs aoia s 254 32 2 NA 254 32 3 Bak A eee SEI ae ao MS Sd oe ad Me 254 32 4 AES 128 parameters ita lid bio 255 32 5 Throughput i it ii 255 32 6 Characteristics cocoa eset ner aon iaa tened Aer KEES ni unos desctectevens dd sheets 255 32 7 Roster is is drid 256 32 8 Ve
525. nual 44 13 Library dependencies Table 404 shows the libraries used when instantiating the core VHDL libraries Table 404 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER LEON3 Component signals LEON3 component declaration interrupt and debug signals declaration 44 14 Component declaration The core has the following component declaration entity leon3s is generic hindex integer 0 fabtech integer range 0 to NTECH 0 memtech integer range 0 to NTECH 0 nwindows integer range 2 to 32 8 dsu integer range 0 to 0 fpu integer range 0 to 3 0 v8 integer range 0 to 2 0 cp integer range 0 to 0 mac integer range 0 to 0 pclow integer range 0 to 2 2 notag integer range 0 to 0 nwp integer range 0 to 4 0 icen integer range 0 to 0 irepl integer range 0 to 2 isets integer range 1 to 4 1 ilinesize isetsize isetlock dcen drepl dsets dlinesize dsetsize dsetlock dsnoop ilram ilramsize ilramstart dlram dlramsize dlramstart mmuen itlbnum dtlbnum tlb_type tlb_rep lddel disas tbuf pwd svt rstaddr smp intege port clk Hin rstn in ahbi in ahbo gt t ahbsi in ahbso in irgi in irgo out dbgi in dbgo out i end integer integer integer integer integer integer integer integer integer integer integer integer in
526. o generates interrupts See the AHB status register documentation for more information When EDAC is enabled one extra latency cycle is generated during reads and subword writes The EDAC function can be enabled for SRAM and PROM area accesses but not for I O area accesses For the SRAM area the EDAC functionality is only supported for accessing 32 bit wide SRAM banks For the PROM area the EDAC functionality is supported for accessing 32 bit wide PROM banks as well as for read accesses to 8 bit wide PROM banks 29 2 1 8 bit PROM access The FTSRCTRL controller can be configured to access an 8 bit wide PROM The data bus of the external PROM should be connected to the upper byte of the 32 bit data bus 1 e D 31 24 The 8 bit mode is enabled with the prom8en VHDL generic When enabled read accesses to the PROM area will be done in four byte bursts for all 32 16 and 8 bit AMBA AHB accesses The whole 32 bit word is then output on the AHB data bus allowing the master to chose the bytes needed big endian Writes should be done one byte at a time For correct word aligned 32 bit word write accesses the byte should always be driven on bits 31 to 24 on the AHB data bus For non aligned 32 bit word write accesses the byte should be driven on the bits of the AHB data bus that correspond to the byte address big endian For correct half word aligned 16 bit half word write accesses the byte should always be driven on bits 31 to 24 or 15 to 8 o
527. oad timer n reload prescaler value timer 1 value gt pirq 4 timer 2 value gt pirq 1 ick E 1 tie gt timer n value gt pirq 2 Y 1 Figure 108 General Purpose Timer Unit block diagram Operation The prescaler is clocked by the system clock and decremented on each clock cycle When the pres caler underflows it is reloaded from the prescaler reload register and a timer tick is generated Timers share the decrementer to save area On the next timer tick next timer is decremented giving effective division rate equal to prescaler reload register value 1 The operation of each timers is controlled through its control register A timer is enabled by setting the enable bit in the control register The timer value is then decremented on each prescaler tick When a timer underflows it will automatically be reloaded with the value of the corresponding timer reload register if the restart bit in the control register is set otherwise it will stop at 1 and reset the enable bit The timer unit can be configured to generate common interrupt through a VHDL generic The shared interrupt will be signalled when any of the timers with interrupt enable bit underflows The timer unit will signal an interrupt on appropriate line when a timer underflows if the interrupt enable bit for the current timer is set when configured to signal interrupt
528. oc generic slvndx integer 0 ioaddr integer 16 000 iomask integer 16 FF0 irq integer 0 memtech integer 0 port resetn in std_logic clk v in std logic 138 ahbsi in ahb_slv_in type ahbso out ahb_slv_out_type can_rxi in std_logic can_txo out std_logic end component 22 22 1 139 GRCAN CAN 2 0 Controller with DMA Overview The CAN controller is assumed to operate in an AMBA bus system where both the AMBA AHB bus and the APB bus are present The AMBA APB bus is used for configuration control and status han dling The AMBA AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller This memory can be located on chip as shown in the block diagram or external to the chip The CAN controller supports transmission and reception of sets of messages by use of circular buffers located in memory external to the core Separate transmit and receive buffers are assumed Reception and transmission of sets of messages can be ongoing simultaneously After a set of message transfers has been set up via the AMBA APB interface the DMA controller ini tiates a burst of read accesses on the AMBA AHB bus to fetch messages from memory which are per formed by the AHB master The messages are then transmitted by the CAN core When a programmable number of messages have been transmitted the DMA controller issues an interrupt After the reception h
529. ogic_vector abits 1 datainl in std_logic_vector dbits 1 dataoutl out std_logic_vector dbits 1 enablel in std_ulogic writel in std_ulogic clk2 in std ulogic address2 in std_logic_vector abits 1 datain2 in std_logic_vector dbits 1 dataout2 out std_logic_vector dbits 1 enable2 in std_ulogic write2 in std_ulogic ram0 syncram_dp generic map tech gt tech port map clkl addressl datainl dataout2 enable2 write2 downto 0 downto 0 downto 0 downto 0 downto 0 downto 0 abits gt addrbits dataoutl enablel dbits gt dbits writel clk2 address2 datain2 62 62 1 62 2 62 3 62 4 62 5 489 TAP JTAG TAP Controller Overview JTAG TAP Controller provides an Test Access Port according to IEEE 1149 JTAG Standard The core implements the Test Access Port signals the synchronous TAP state machine a number of JTAG data registers depending on the target technology and an interface to user defined JTAG data regis ters y TOK JTAG TAP gt Ts gt Controller Interface to user defined data registers TDO Figure 233 TAP controller block diagram Operation 62 2 1 Generic TAP Controller The generic TAP Controller implements JTAG Test Access Point interface with signals TCK TMS TDI and TDO a synchronous state machine compliant to the IEEE 1149 standard JTAG instruction register and two JTAG data regi
530. okup table CLUT is used The CLUT has 256 adresses each 24 bits wide and the 8 bit values read from memory are used to index the CLUT to obtain the actual colour 476 58 3 Registers The SVGACTRL core is controlled by 11 registers mapped into APB adress space TABLE 462 APB Register map Register APB offset Status register 0x0 Video Length 0x4 Front Porch 0x8 Sync Length OxC Line Length 0x10 Framebuffer Memory Position 0x14 Dynamic Clock 0 0x18 Dynamic Clock 1 0x1C Dynamic Clock 2 0x20 Dynamic Clock 3 0x24 CLUT access register 0x28 58 3 1 Status register Table 463 Status register Reserved 9 8 76 54 3 2 1 0 0 Enable Starts the hardware 1 Reset Resets the hardware 2 Vertical Refresh displays current refresh state active high 3 Running displays the current mode active high 5 4 Clock Select clock selector when using dynamic pixelclock 7 6 Bit depth selector 01 8 bit mode 10 16 bit mode 10 or 01 32 bit mode 8 Hpolarity sets the polarity for the horizontal sync pulse 9 Vpolarity sets the polarity for the vertical sync pulse 58 3 2 Video length register Vertical video length Horizontal video length 15 0 Horizontal screen resolution in pixels 1 31 16 Vertical screen resolution in pixels 1 58 3 3 Front porch register Vertical front porch H
531. omatically incremented even if the transmit channel has been dis abled since the last requested transfer is not aborted until CAN bus arbitration is lost When the Transmit Channel Read Pointer catches up with the Transmit Channel Write Register an interrupt is generated TxEmpty Note that this indicates that all messages in the buffer have been transmitted The field is implemented as relative to the buffer base address scaled with the SIZE field 153 22 9 11 Transmit Channel Interrupt Register CanTxIRQ R W Table 161 Transmit Channel Interrupt Register 31 20 19 4 3 0 IRQ 19 4 IRQ Interrupt is generated when CanTxRD READ IRQ as a consequence of a message transmission All bits are cleared to 0 at reset Note that this indicates that a programmed number of messages have been transmitted The field is implemented as relative to the buffer base address scaled with the SIZE field 22 9 12 Receive Channel Control Register CanRxCTRL R W Table 162 Receive Channel Control Register 31 2 1 0 OnG Ena oing ble 1 ONGOINGReception ongoing read only 0 ENABLE Enable channel All bits are cleared to 0 at reset Note that in the case an AHB bus error occurs during an access while fetching transmit data and the CanCONF ABORT bit is 1b then the ENALBE bit will be reset automatically At the time the ENABLE is cleared to Ob any ongoing message reception is not aborted Note that the
532. on This examples shows how the core can be instantiated The DDR SDRAM controller decodes SDRAM area at 0x40000000 Ox7FFFFFFF The SDRAM registers aremapped into AHB I O space on address AHB I O base address 0x100 library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler memctrl all entity ddr_Interface is port ddr_clk out std_logic_vector 2 downto 0 ddr_clkb out std_logic_vector 2 downto 0 r_clk_fb in std logig r_clk_fb_out out std_logic r_cke out std_logic_vector 1 downto 0 r_csb out std_logic_vector 1 downto 0 r_web out std_ulogic ddr write enable r_rasb out std_ulogic ddr ras r_casb out std_ulogic ddr cas r_dm out std_logic_vector 7 downto 0 ddr dm r_dqs inout std_logic_vector 7 downto 0 ddr dgs r_ad out std_logic_vector 13 downto 0 ddr address r_ba out std_logic_vector 1 downto 0 ddr bank address r_dq inout std_logic_vector 63 downto 0 ddr data aa ad ad ad ad ad ad ad ad ad ad ad i end architecture rtl of mctrl_ex is AMBA bus signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal clkml lock std_ulogic begin DDR controller ddre ddrspa generic map fabtech gt virtex4 ddrbits gt 64 memtech gt memtech hindex gt 4 haddr gt 164004 hmask gt 16 F00 ioaddr
533. on GRLIB AMBA Types AMBA signal type definitions GAISLER MISC Component Component declaration 48 7 6 7 7 Component declaration library grlib use grlib amba all library gaisler use gaisler misc all component ahbram generic hindex integer 0 haddr integer 0 hmask integer tech integer 0 kbytes integer 1 port rst in std_ulogic clk in std_ulogic ahbsi in ahb_slv_in type ahbso out ahb_slv_out_type i end component Instantiation This examples shows how the core can be instantiated library grlib use grlib amba all library gaisler use gaisler misc all ahbram0 ahbram generic map hindex gt 7 haddr gt CFG_AHBRADDR tech gt CFG_MEMTECH kbytes gt 8 port map rstn clkm ahbsi ahbso 7 16 ff f4 8 1 8 2 8 3 8 4 49 AHBROM Single port ROM with AHB interface Overview The AHBROM core implements a 32 bit wide on chip ROM with an AHB slave interface Read accesses take zero waitstates or one waitstate if the pipeline option is enabled The ROM supports byte and half word accesses as well as all types of AHB burst accesses PROM generation The AHBPROM is automatically generated by the make utility in GRLIB The input format is a sparc elf binary file produced by the BCC cross compiler sparc elf gcc To create a PROM first compile a suitable binary and the run the make utility bash sparc elf gc
534. on Active RST N A Input Reset Low CLK N A Input Clock APBI Input APB slave input signals APBO Output APB slave output signals IRQI n INTACK Input Processor n Interrupt acknowledge High IRL 3 0 Processor n interrupt level High IRQO n IRL 3 0 Output Processor n Input interrupt level High RST Reset power down and error mode of processor n High RUN Start processor n after reset SMP systems only High see GRLIB IP Library User s Manual 43 7 Library dependencies Table 391 shows libraries that should be used when instantiating the core Table 391 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER LEON3 Signals component Signals and component declaration 43 8 Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler leon3 all entity irgmp_ex is port clk in std_ulogic rstn in std_ulogic Sa other signals i end architecture rtl of irqmp_ex is constant NCPU integer 4 AMBA signals signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signal ahbsi ahb_slv_in_type 368 GP Timer Unit input signals signal irqi irq_in _ vec
535. on register is used In the same manner if read diag nostics are enabled the stored checksum from memory is stored in the TCB field during a read and also during a subword write This way the EDAC functionality can be tested during run time Note that checkbits are stored in TCB during reads and subword writes even if a multiple error is detected An additional feature is the single error counter which can be enabled with the errcnten VHDL generic A single error counter SEC field is present in the configuration register and is incremented each time a single databit error is encountered reads or subword writes The number of bits of this counter is 8 set with the cntbits VHDL generic It is accessed through the configuration register Each counter bit can be reset to zero by writing a one to it The counter saturates at the value OF Ore 1 Each time a single error is detected the aramo ce signal will be driven high for one cycle This signal should be connected to an AHB status register which stores information and generates inter rupts see the AHB Status register documentation for more information Autoscrubbing is an error handling feature which is enabled with the autoscrub VHDL generic and cannot be controlled through the configuration register If enabled every single error encountered dur ing a read results in the word being written back with the error corrected and new checkbits generated It is not visible externally except for t
536. ons are checked next 1 byte can be rmw to any address 2 bytes must be halfword aligned 3 bytes are not allowed 4 bytes must be word aligned If these restrictions are violated nothing is done and error code is set to 10 If an AHB error occurs error code is set to 1 Reply is sent 0 1 1 0 0 0 Write sin Executed normally Address has gle address to be word aligned and data size do not verify a multiple of four If alignment is before writ violated nothing is done No ing no reply is sent acknowledge 0 1 1 0 0 1 Write incre Executed normally No restric menting tions No reply is sent address do not verify before writ ing no acknowledge 0 1 1 0 1 0 Write sin Executed normally Address has to be word aligned and data size a multiple of four If alignment is violated nothing is done and error code is set to 10 If an AHB error occurs error code is set to 1 Reply is sent 332 42 7 Table 333 GRSPW hardware RMAP handling of different packet type and command fields Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Command Action Verify data Command Write before Acknow Increment Reserved Response Read write ledge Address 0 1 1 0 1 1 Write incre Executed normally No restric menting tions If AHB error occurs error address do code is set to 1 Reply is sent not verify before writ ing send acknowledge 0 1 1 1 0 0 Write sin
537. onse to AMBA Spec Rev 2 0 3 9 BUSY cycles in the same way as for IDLE 2 AHB slave must respond with a zero wait state OKAY response to AMBA Spec Rev 2 0 3 9 IDLE 3 HRESP should be set to ERROR SPLIT or RETRY only one cycle AMBA Spec Rev 2 0 3 22 before HREADY is driven high 4 Two cycle ERROR response must be given AMBA Spec Rev 2 0 3 22 5 Two cycle SPLIT response must be given AMBA Spec Rev 2 0 3 22 6 Two cycle RETRY response must be given AMBA Spec Rev 2 0 3 22 7 SPLIT complete signalled to master which did not have pending AMBA Spec Rev 2 0 3 36 access 8 Split complete must not be signalled during same cycle as SPLIT http www arm com support faqip 616 html 9 It is recommended that slaves drive HREADY high and HRESP to http www arm com support faqip OKAY when not selected A warning will be given if this is not fol 476 html lowed 10 It is recommended that slaves do not insert more than 16 wait states If AMBA Spec Rev 2 0 3 20 this is violated a warning will be given if assertions are enabled Table 57 APB slave rules Rule Number Description References 1 The bus must move to the SETUP state or remain in the IDLE state AMBA Spec Rev 2 0 5 4 when in the IDLE state 2 The bus must move from SETUP to ENABLE in one cycle AMBA Spec Rev 2 0 5 4 3 The bus must move from ENABLE to SETUP or IDLE in one cycle AMBA Spec Rev 2 0 5 5 4 The bus must never
538. ontroller when 0 All bits are cleared to O at reset Note that RESET is read back as Ob Note that ENABLE should be cleared to Ob to while other settings are modified ensuring that the CAN core is properly synchronized Note that when ENABLE is cleared to Ob the CAN interface is in sleep mode only outputting reces sive bits Note that the CAN core requires that 10 recessive bits be received before receive and transmit opera tions can begin 22 9 4 SYNC Code Filter Register CanCODE R W Table 154 SYNC Code Filter Register 31 30 29 28 0 SYNC 28 0 SYNC Message Identifier All bits are cleared to 0 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 22 9 5 SYNC Mask Filter Register CanMASK R W Table 155 SYNC Mask Filter Register 31 30 29 28 0 MASK 28 0 MASK Message Identifier 151 All bits are set to 1 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 A RxSYNC message ID is matched when Received ID XOR CanCODE SYNC AND CanMASK MASK 0 A TxSYNC message ID is matched when Transmitted ID XOR CanCODE SYNC AND CanMASK MASK 0 22 9 6 Transmit Channel Control Register CanTxCTRL R W Table 156 Transmit Channel Control Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Sin Ong Ena gle oing ble
539. ord and word For AHB write transfers write data is always buffered in internal FIFO implementing posted writes For AHB read transfers the bridge uses GRLIB s AMBA Plug amp Play information to determine weather the read data will be prefetch and buffered in internal FIFO If the target address for an AHB read transfer is a prefetchable location the read data will be prefetched and buffered AHB master ini 22 2 3 2 4 tiating a read transfer to the bridge is always splitted on the first transfer attempt to allow other mas ters to use the slave bus while the bridge performs read transfer on the master bus If the interrupt synchronization is enabled the interrupts on the slave bus interrupt lines will be for warded to the master bus and vice versa 2 2 2 AHB read transfers When a read transfer is registered on the slave interface the bridge gives SPLIT response The master that initiated the transfer will be de granted allowing other bus master to use the slave bus while the bridge performs read transfer on the master side The master interface requests the bus and starts the read transfer on the master side Single transfer on the slave side is translated to single access on the master side If the read FIFO is enabled and the transfer is a burst transfer to a prefetchable location the master interface will perform transfer of either fixed length in case of fixed length burst or burst of the same length as the read FIFO Read data is buf
540. orizontal front porch 15 0 Horizontal front porch in pixels 31 16 Vertical front porch in pixels 58 4 477 58 3 4 Sync pulse register Vertical sync pulse length Horizontal sync pulse length 15 0 Horizontal sync pulse length in pixels 31 16 Vertical sync pulse length in pixels 58 3 5 Line length register Vertical video length Horizontal video length 15 0 Horizontal line length The length of the total line with front and back porch sync pulse length and horizontal screen resolution 31 16 Vertical line length The length of the total line with front and back porch sync pulse length and vertical screen resolution 58 3 6 Framebuffer memory position register Vertical sync pulse length 31 0 Holds the memory position of the framebuffer must be aligned on a 1 Kbyte boundary 58 3 7 Dynamic clocks 0 3 registers Dynamic clock 31 0 Dynamic pixel clock defined in ns 58 3 8 CLUT access register Color register Color data 31 24 Color lookup table register to set 23 16 Red color data to set in the specified register 15 8 Green color data to set in the specified register 7 0 Blue color data to set in the specified register Vendor and device identifiers The SVGACTRL hardware has device id 0x063 and the vendor id 1 Gaisler Research 478 58 5 Configuration options The SVGACTRL hardware has these con
541. ormance and low complexity The LEON3 integer unit has the following main features e 7 stage instruction pipeline e Separate instruction and data cache interface e Support for 2 32 register windows e Hardware multiplier with optional 16x16 bit MAC and 40 bit accumulator Radix 2 divider non restoring e Single vector trapping for reduced code size Figure 166 shows a block diagram of the integer unit call branch address I cache Y Al data address E jmpa i ej al A a SA NE A UA Docs An tr E a E a a E ere Fetch Ssh li ETE AE 25 Rt 2 5 Ope Pen A ai ER Po Se SSeS Sete Sa SSeS Cake SS SS o cS Se Se Stes Decode dhs Seb patie ts ee ae ate PU e He e spent A oe cn hie ss de ah RY dee is ds as eee et m register file imm rs1 rs2 Register Access y tor wim psr I O ont inst oe se pepe et Fo de e eo rst TA Dope e A Sia eee eS lt ol Execute ay mul div epc y y gt S 30 jmpl address RA a AI A A SS ll EA RS ALO O D cache Memory E address dataout Panor gt Sods o Inst 22202055 x pe See Se 2 et De Kes
542. ormat as defined in IEEE 754 standard 310 39 2 2 FP operations The floating point unit supports four types of floating point operations arithmetic compare convert and move The operations implement all FP instructions specified by SPARC V8 instruction set All operations are summarized in the table below Table 320 Floating point operations Operation Op1 Op2 Result Exceptions Description Arithmetic operations FADDS SP SP SP NV OF UF NX Addition FADDD DP DP DP FSUBS SP SP SP NV OF UF NX Subtraction FSUBD DP DP DP FMULS SP SP SP NV OF UF NX Multiplication FMULD DP DP DP NV OF UF NX FSMULD SP SP DP NV OF UF FDIVS SP SP SP NV OF UF NX Division FDIVD DP DP DP FSQRTS SP SP NV NX Square root FSQRTD DP DP Conversion operations FITOS INT SP NX Integer to floating point conversion FITOD DP FSTOI SP INT NV NX Floating point to integer conversion The result is FDTOI DP rounded in round to zero mode FSTOD SP DP NV Conversion between floating point formats FDTOS DP SP NV OF UF NX Comparison operations FCMPS SP SP CC NV Floating point compare Invalid exception is gener FCMPD DP DP ated if either operand is a signaling NaN FCMPES SP SP CC NV Floating point compare Invalid exception is gener FCMPED DP DP ated if either operand is a NaN quiet or signaling Negate Absolute value and Move FABSS
543. osn_pad outpad port map iosn memo iosn data_pad iopadvv generic map width gt 8 SRAM and I O Data port map data 15 downto 8 memo data 15 downto 8 memo vbdrive 15 downto 8 memi data 15 downto 8 cbdata_pad iopadvv generic map width gt 8 SRAM checkbits and I O Data port map data 7 downto 0 memo data 7 downto 0 memo vbdrive 7 downto 0 memi data 7 downto 0 APB bridge and AHB stat apb0 apbctrl AHB APB bridge generic map hindex gt 1 haddr gt 16 800 port map rstn clkm ahbsi ahbso 1 apbi apbo stati cerror 0 lt memo ce ahbstat0 ahbstat generic map pindex gt 15 paddr gt 15 pirq gt 1 port map rstn clkm ahbmi ahbsi stati apbi apbo 15 end 31 31 1 31 2 249 GPTIMER General Purpose Timer Unit Overview The General Purpose Timer Unit provides a common prescaler and decrementing timer s Number of timers is configurable through the ntimers VHDL generic in the range 1 to 7 Prescaler width is con figured through the sbits VHDL generic Timer width is configured through the tbits VHDL generic The timer unit acts a slave on AMBA APB bus The unit implements one 16 bit prescaler and 3 decre menting 32 bit timer s The unit is capable of asserting interrupt on timer s underflow Interrupt is configurable to be common for the whole unit or separate for each timer timer 1 reload timer 2 reload prescaler rel
544. out_type signal gnd std_ulogic begin Clock and reset generators clkgen0 clkgen generic map clk_mul gt 2 clk_div gt 2 sdramen gt 1 tech gt virtex2 sdinvclk gt 0 port map clk gnd clkm open open sdclk open cgi cgo cgi pllctrl lt 00 cgi pllrst lt resetn cgi pllref lt pllref Memory controller mctrlO mctrl generic map srbanks gt 1 sden gt 1 port map rstn clkm memi memo ahbsi ahbso 0 apbi apbo 0 wprot sdo memory controller inputs not used in this configuration memi brdyn lt 1 memi bexcn lt 1 memi wrn lt 1111 420 memi sd lt sd prom width at reset memi bwidth lt 10 I O pads driving data memory bus data signals datapads for i in 0 to 3 generate data_pad iopadv generic map width gt 8 port map pad gt data 31 1 8 downto 24 i 8 o gt memi data 31 i 8 downto 24 1 8 en gt memo bdrive i i gt memo data 31 i 8 downto 24 1 8 end generate connect memory controller outputs to entity output signals address lt memo address ramsn lt memo ramsn romsn lt memo romsn oen lt memo oen rwen lt memo wrn ramoen lt 1111 amp memo ramoen 0 sa lt memo sa writen lt memo writen read lt memo read iosn lt memo iosn sdcke lt sdo sdcke sdwen lt sdo sdwen sdcsn lt sdo sdcsn sdrasn lt sdo rasn sdcasn lt sdo casn sddqm lt sdo dqm end
545. plit Enable support for AHB SPLIT response 0 1 0 defmast Default AHB master 0 NAHBMST 1 0 ioen AHB I O area enable Set to0 to disable the I O area 0 1 1 nahbm Number of AHB masters 1 NAHBMST NAHBMST nahbs Number of AHB slaves 1 NAHBSLV NAHBSLV timeout Perform bus timeout checks NOT IMPLEMENTED 0 1 0 fixbrst Enable support for fixed length bursts 0 1 0 debug Print configuration O none 1 short 2 all cores 0 2 2 fpnpen Enables full decoding of the PnP configuration records 0 1 0 When disabled the user defined registers in the PnP con figuration records are not mapped in the configuration area icheck Check bus index 0 1 1 devid Assign unique device identifier readable from plug and N A 0 play area enbusmon Enable AHB bus monitor 0 1 assertwarn Enable assertions for AMBA recommendations Viola 0 1 tions are asserted with severity warning asserterr Enable assertions for AMBA requirements Violations 0 1 0 are asserted with severity error hmstdisable Disable AHB master rule check To disable a master rule N A 0 check a value is assigned so that the binary representa tion contains a one at the position corresponding to the rule number e g 0x80 disables rule 7 hslvdisable Disable AHB slave tests Values are assigned as for N A 0 hmstdisable arbdisable Disable Arbiter tests Values are assigned as for hmstdis N A 0 able 32 4 7 4 8 4 9 4 10 Signal descriptions Table 23 shows the interface signa
546. ponding interrupt enable bit is set in the interrupt enable register Table 123 Bit interpretation of interrupt register IR address 3 Bit Name Description IR 7 Bus error interrupt Set if an error on the bus has been detected IR 6 Arbitration lost interrupt Set when the core has lost arbitration IR S Error passive interrupt Set when the core goes between error active and error passive IR 4 not used wake up interrupt of SJA1000 IR 3 Data overrun interrupt Set when data overrun status bit is set IR 2 Error warning interrupt Set on every change of the error status or bus status IR 1 Transmit interrupt Set when the transmit buffer is released IR O Receive interrupt Set while the fifo is not empty This register is reset on read with the exception of IR O which is reset when the fifo has been emptied 128 21 5 6 Interrupt enable register In the interrupt enable register the separate interrupt sources can be enabled disabled If enabled the corresponding bit in the interrupt register can be set and an interrupt generated Table 124 Bit interpretation of interrupt enable register IER address 4 Bit Name Description IR 7 Bus error interrupt 1 enabled 0 disabled IR 6 Arbitration lost interrupt 1 enabled 0 disabled IR S Error passive interrupt 1 enabled 0 disabled IR 4 not used wake up interrupt of SJA 1000 IR 3 Data overrun inte
547. priori tize interrupts perform interrupt masking for each processor according to the mask in the correspond ing mask register and forward the interrupts to the processors 363 Priority select IRQ Pending Priority encoder 15 4 APBI PIRQ 15 1 gt D IRQO 0 IRL 3 0 AS IRQ IRQ Force 0 mask 0 Priority encoder 4 D ye aa IRQO n IRL 3 0 IRQ IRQ Force n mask n Figure 156 Interrupt controller block diagram When a processor acknowledges the interrupt the corresponding pending bit will automatically be cleared Interrupt can also be forced by setting a bit in the interrupt force register In this case the pro cessor acknowledgement will clear the force bit rather than the pending bit After reset the interrupt mask register is set to all zeros while the remaining control registers are undefined Note that interrupt 15 cannot be maskable by the LEON3 processor and should be used with care most operating sys tems do not safely handle this interrupt 43 2 2 Processor status monitoring The processor status can be monitored through the Multiprocessor Status Register The STATUS field in this register indicates if a processor is halted 1 or running 0 A halted processor can be reset and restarted by writing a 1 to its status field After reset al
548. programmable division factor The divider consist of a 14 bit down counter and can divide the APB clock with a factor of 1 16383 If the fixed generic is set to 1 the division rate is set to the fKHz generic divided by 10 in order to generate a 10 KHz clock If fixed is O the division rate can be programmed through the timer reload register 75 Y Y Start Stop d ps2clkoe 1 read FIFO Y 1 Data t ps2data 1 k_fall y ps2clk 0 Ack ps2clkoe 0 1 ps2data shift_reg 0 ps2data 1 update shift_reg ps2dataoe 0 y f 0 Waitrequest shift reg Simply 1 y timer timer 1 Parity 4 1 0 timer lt 5000 tx_irq 1 ps2data 1 ps2dataoe 1 0 1 ps2clk 1 ps2data 0 al timer 0 ps2data parity bit Figure 25 Flow chart for the transmitter state machine 14 5 Registers The core is controlled through registers mapped into APB address space Table 65 APB PS 2 registers APB address offset Register 0x00 PS 2 Data register 0x04 PS 2 Status register 0x08 PS 2 Control register 0x0C PS 2 Timer reload register 14 5 1 PS 2 Data Register 31 8 7 0 RESERVED DATA Figure 26 PS 2 data register 7 0 Receiver holding FIFO read access and Transmitter holding FIFO write access If the rece
549. r 16 104 Pending Interrupt Masked Register 16 108 Pending Interrupt Status Register 16 10C Pending Interrupt Register 16 110 Interrupt Mask Register 16 114 Pending Interrupt Clear Register 16 200 Transmit Channel Control Register 16 204 Transmit Channel Address Register 16 208 Transmit Channel Size Register 16 20C Transmit Channel Write Register 16 210 Transmit Channel Read Register 16 214 Transmit Channel Interrupt Register 16 300 Receive Channel Control Register 16 304 Receive Channel Address Register 16 308 Receive Channel Size Register 16 30C Receive Channel Write Register 16 3 10 Receive Channel Read Register 16 3 14 Receive Channel Interrupt Register 16 318 Receive Channel Mask Register 16 31C Receive Channel Code Register 22 9 1 Configuration Register CanCONF R W Table 151 Configuration Register 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 SCALER PS1 PS2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 RSJ BPR Sile Sele Ena Ena Abo nt ctio ble ble rt H 1 0 31 24 SCALER 23 20 PS1 19 16 PS2 14 12 RSJ 9 8 BPR Prescaler setting 8 bit system clock SCALER 1 Phase Segment 1 4 bit valid range 1 to 15 Phase Segment 2 4 bit valid range 2 to 8 ReSynchronization Jumps 3 bit valid range 1 to 4 Baud rate 2 bit 00b system clock SCALER 1 1 01b system clock SCALER 1 2 10b system clock SCALER 1 4
550. r For more information on the JTAG TAP controller user interface see JTAG TAP Controller IP core documentation If not used tie TAPI_TDO to ground and leave TAPO_ outputs unconnected see GRLIB IP Library User s Manual Library dependencies Table 32 shows libraries used when instantiating the core VHDL libraries Table 32 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER JTAG Signals component Signals and component declaration Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all library gaisler use gaisler jtag all 46 6 9 entity ahbjtag_ex is port clk in std_ulogic rstn in std_ulogic JTAG signals tek in std_ulogic tms in std_ulogic tdi in std_ulogic tdo out std_ulogic i end architecture rtl of ahbjtag_ex is AMBA signals signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signal gnd std_ulogic constant clkperiod integer 100 begin gnd lt 0 AMBA Components are instantiated here AHB JTAG ahbjtag0 ahbjtag generic map tech gt 0 hindex gt 1 port map rstn clkm tck tckn tms tdi tdo ahbmi ahbmo 1 open open open open open open open gnd jtagproc process begin wait jtagco
551. r address register 16 00000 16 FFFFF 16 00000 clkspd Clock speed 0 3 1 rtaddr RT address 0 31 0 rtaddrp RT address parity bit Set to achieve odd parity 0 1 1 wrtemd Write command word to memory 0 1 1 wrttsw Write status word to memory 0 1 1 extmdata Read write mode code data from to memory 0 1 0 intenbbr Generate interrupts for bad messages 0 1 0 bcasten Broadcast enable 0 1 1 sa30loop Use sub address 30 as loopback 0 1 0 All VHDL generics except endian are reset values for the corresponding bits in the wrapper control register 20 6 Signal descriptions Table 111 shows the interface signals of the core VHDL ports Table 111 Signal descriptions Signal name Field Type Function Active RSTN N A Input Reset Low CLK N A Input Clock B15531 Input 1553 bus input signals busainp Positive data input from the A receiver High busainn Negative data input from the A receiver Low busbinp Positive data to the B receiver High busbinn Negative data to the B receiver Low B15530 Output 1553 bus output signals busainen Enable for the A receiver High busaoutin Inhibit for the A transmitter High busaoutp Positive data to the A transmitter High busaoutn Negative data to the A transmitter Low busbinen Enable for the B receiver High busboutin I
552. r is needed to meet 133 MHz timing 23 2 6 Refresh The DDRSPA controller contains a refresh function that periodically issues an AUTO REFRESH command to both SDRAM banks The period between the commands in clock periods is pro grammed in the refresh counter reload field in the SDCFG register Depending on SDRAM type the required period is typically 7 8 us corresponding to 780 at 100 MHz The generated refresh period is calculated as reload value 1 sysclk The refresh function is enabled by bit 31 in SDCTRL register 23 2 7 SDRAM commands The controller can issue four SDRAM commands by writing to the SDRAM command field in SDCFG PRE CHARGE LOAD EXTMODE REG LOAD MODE REG and REFRESH If the LEMR command is issued the PLL Reset bit as programmed in SDCFG will be used remaining 163 fields are fixed 8 word sequential burst CL 2 The command field will be cleared after a command has been executed 23 2 8 Clocking The DDR controller is designed to operate with two clock domains one for the DDR memory clock and one for the AHB clock The two clock domains do not have to be the same or be phase aligned The DDR input clock CLK_DDR can be multiplied and divided by the DDR PHY to form the final DDR clock frequency The final DDR clock is driven on one output CLKDDRO which should always be connected to the CLKDDRI input If the AHB clock and DDR clock area generated from the same clock source a timing ignore constraint should be p
553. r needs to be set to hold the address of this Space Wire node Packets received with the incorrect address are discarded Finally the descriptor table and control register must be ini tialized This will be described in the two following sections 42 4 3 Setting up the descriptor table address The GRSPW reads descriptors from a area in memory pointed to by the receiver descriptor table address register The register consists of a base address and a descriptor selector The base address points to the beginning of the area and must start on a 1 kbytes aligned address It is also limited to be 1 kbytes in size which means the maximum number of descriptors is 128 The descriptor selector points to individual descriptors and is increased by 1 when a descriptor has been used When the selector reaches the upper limit of the area it wraps to the beginning automati cally It can also be set to wrap automatically by setting a bit in the descriptors The idea is that the selector should be initialized to O start of the descriptor area but it can also be written with another 8 bytes aligned value to start somewhere in the middle of the area It will still wrap to the beginning of the area If one wants to use a new descriptor table the receiver enable bit has to be cleared first When the rxactive bit for the channel is cleared it is safe to update the descriptor table register When this is fin ished and descriptors are enabled the receiver enable bit can
554. r to the read access but takes a minimum of three cycles Through an optional feed back loop from the write strobes the data bus is guaranteed to be driven until the write strobes are de asserted Each byte lane has an individual write strobe to allow efficient byte and half word writes If the memory uses a common write strobe for the full 16 or 32 bit data the read modify write bit in the MCFG2 register should be set to enable read modify write cycles for sub word writes lead in data lead out address ramsn gt esd eos ain O i A a rwen re NY SS ES TE E E a cb CB1 Figure 193 Sram write cycle 0 waitstates A drive signal vector for the data I O pads is provided which has one drive signal for each data bit It can be used if the synthesis tool does not generate separate registers automatically for the current technology This can remove timing problems with output delay S bit and 16 bit PROM and SRAM access To support applications with low memory and performance requirements efficiently it is not neces sary to always have full 32 bit memory banks The SRAM and PROM areas can be individually con figured for 8 or 16 bit operation by programming the ROM and RAM size fields in the memory configuration registers Since read access to memory is always done on 32 bit word basis read access to 8 bit memory will be transformed in a burst of four read cycles while access to 16 bit memory will 409
555. rCntr Error counter incremented for transmit e TxSync Synchronization message transmitted e Tx Successful transmission of one message e TxEmpty Successful transmission of all messages in buffer e TxIrq Successful transmission of a predefined number of messages e TxAHBErr AHB access error during transmission e Off Bus off condition e Pass Error passive condition The Tx TxEmpty and TxIrq interrupts are only generated as the result of a successful message trans mission after the CanTxRD READ pointer has been incremented Reception The receive channel is defined by the following parameters e base address e buffer size e write pointer e read pointer The receive channel can be enabled or disabled 22 6 1 Circular buffer The receive channel operates on a circular buffer located in memory external to the CAN controller The circular buffer can also be used as a straight buffer The buffer memory is accessed via the AMBA AHB master interface Each CAN message occupies 4 consecutive 32 bit words in memory Each CAN message is aligned to 4 words address boundaries i e the 4 least significant byte address bits are zero for the first word in a CAN message The size of the buffer is defined by the CanRxSIZE SIZE field specifying the number of CAN mes sages 4 that fit in the buffer E g CanRxSIZE SIZE 2 means 8 CAN messages fit in the buffer 145 Note however that it is not possible to fill the buffer completely
556. ransmission rx_rmap_header_crc_err Number of RMAP header CRC errors detected in received packets rx_rmap_data_crc_err Number of RMAP data CRC errors detected in received packets rx_eep_err Number of EEPs detected in received packets rx_truncated Number of truncated packets received parity_err Number of parity errors detected escape_err Number of escape errors detected credit_err Number of credit errors detected write_sync_err Number of write synchronization errors detected disconnect_err Number of disconnect errors detected early_ep Number of packets received with an early EOP EEP invalid_address Number of packets received with an invalid destination address packets_sent Number of packets transmitted packets_received Number of packets received The spw_config struct holds the current configuration of the GRSPW typedef struct unsigned unsigned unsigned unsigned unsigned unsigned int int int int int int nodeaddr destkey clkdiv rxmaxlen timer disconnect 345 unsigned int promiscuous unsigned int timetxen unsigned int timerxen unsigned int rmapen unsigned int rmapbufdis unsigned int linkdisabled unsigned int linkstart unsigned int check_rmap_err unsigned int rm_prot_id unsigned int tx_blocking unsigned int tx_block_on_full unsigned int rx_blocking unsigned int disable_err unsigned int link_err_irg rte
557. ransmitting data on an Ethernet network The transmission is done using descriptors located in memory 35 3 1 Setting up a descriptor A single descriptor is shown in figure 123 The number of bytes to be sent should be set in the length field and the address field should point to the data There are no alignment restrictions on the address field If the interrupt enable IE bit is set an interrupt will be generated when the packet has been sent this requires that the transmitter interrupt bit in the control register is also set The interrupt will be generated regardless of whether the packet was transmitted successfully or not 286 31 20 19 18 17 16 15 14 13 12 11 10 0 0x0 RESERVED uc Tc lic Mo LC AL UE TE WR EN LENGTH 31 0 0x4 ADDRESS 10 0 LENGTH The number of bytes to be transmitted 11 Enable EN Set to one to enable the descriptor Should always be set last of all the descriptor fields 12 Wrap WR Set to one to make the descriptor pointer wrap to zero after this descriptor has been used If this bit is not set the pointer will increment by 8 The pointer automatically wraps to zero when the 1 kB boundary of the descriptor table is reached 13 Interrupt Enable IE Enable Interrupts An interrupt will be generated when the packet from this descriptor has been sent provided that the transmitter interrupt enable bit in the control register is set The interrupt is generated r
558. rary grlib use grlib amba all library gaisler use gaisler uart all entity apbuart_ex is port elk ain std uloguie rstn in std_ulogic UART signals rxd in std_ulogic txd out std_ulogic i end architecture rtl of apbuart_ex is APB signals apb_slv_in_type apb_slv_out_vector signal apbi signal apbo UART signals signal uarti uart_in_type signal uarto uart_out_type others gt apb_none begin AMBA Components are instantiated here APB UART uart0 apbuart generic map pindex gt 1 paddr gt 1 pirq gt 2 console gt 1 fifosize gt 1 port map rstn clk apbi apbo 1 uarti uarto UART input data uarti rxd lt rxd APB UART inputs not used in this configuration uarti ctsn lt 0 uarti extclk lt 0 connect APB UART output to entity output signal txd lt uarto txd end 89 90 16 16 1 16 2 APBVGA VGA controller with APB interface Introduction The APBVGA core is a text only video controller with a resolution of 640x480 pixels creating a dis play of 80x37 characters The controller consists of a video signal generator a 4 Kbyte text buffer and a ROM for character pixel information The video controller is controlled through an APB interface A block diagram for the data path is shown in figure 32 Character ROM i gt Q HSYNC Q VSYNC
559. ration following the write operation Due to the memory automatically putting the data bus in high impedance mode when a write opera tion is performed the output enable signal OEN is held active low during all SSRAM accesses including write operations For the PROM and I O operations a number of waitstates can be inserted to increase the read and write cycle The number of waitstates can be configured separately for the I O and PROM address ranges through a programmable register mapped into the APB address space After a reset the wait states for PROM area is set to its maximum 15 Figure 230 and figure 231 show timing diagrams for the PROM read and write accesses 467 Read accesses to 32 bit PROM and I O has the same timing see figure 230 data lead out A ROMSN IOSN OEN D Figure 230 32 bit PROM IO read cycle The write access for 32 bit PROM and T O can be seen in figure 231 lead in data lead out A ROMSN E FN O E E O E EE IOSN WRITEN Figure 231 32 bit PROM IO write cycle 57 3 Registers The core is programmed through registers mapped into APB address space Table 458 SSRAM controller registers APB address offset Register 0x00 Memory configuration register 31 29 28 27 26 25 24 23 20 19 18 17 12 11 10 9 8 7 4 3 0 Reserved T O waitstates Reserved Prom write ws Prom read ws 1 0 width VO enable __
560. re 173 Examples of LEON3 clock gating The processor should exit the power down state when an interrupt become pending The signal DBGO ipend will then go high when this happen and should be used to re enable the clock When the debug support unit DSU3 is used the DSUO pwd signal should be used instead of DBGO idle This will insure that the clock also is re enabled when the processor is switched from power down to debug state by the DSU The DSUO pwd is a vector with one power down signal per CPU for SMP systems DSUO pwd takes DBGO ipend into account and no further gating or latch ing needs to be done of this signal If cache snooping has been enabled the continuous clock will insure that the snooping logic is activated when necessary and will keep the data cache synchronized even when the processor clock is gated off In a multi processor system all processor except node 0 will enter power down after reset and will allow immediate clock gating without additional software support Clock tree routing must insure that the continuous clock CLK and the gated clock GCLK are phase aligned The template design leon3 clock gating shows an example of a clock gated system The leon3cg entity should be used when clock gating is implemented This entity has one input more GCLK which should be driven by the gated clock Using the double clocked version of leon3 leon3s2x the GCLK2 is the gated double clock while CLK and CLK2 should be continuous
561. re are no free transmit descriptors currently available 2 There was illegal parameters passed to the function 356 Table 367 Parameters for spw_tx Parameter Description Allowed range cre Set to one to append RMAP CRC after the header and data fields 0 1 Only available if hardware CRC is available in the core skipcresize The number of bytes in the beginning of a packet that should not be 0 15 included in the CRC calculation hsize The size of the header in bytes 0 255 hbuf Pointer to the header data dsize The size of the data field in bytes 0 224 1 dbuf Pointer to the data area spw Pointer to the spwvars struct associated with GRSPW core that should transmit the packet int spw_rx char buf struct spwvars spw Enables a descriptor for reception The packet will be stored to buf Spw_checkrx must be used to check if a packet has been received A pointer in the spwvars struct is used to keep track of the next location to use in the descriptor table It is incremented each time the function returns 0 Table 368 Return values for spw_rx Value Description 0 The function completed successfully 1 There are no free receive descriptors currently available Table 369 Parameters for spw_rx Parameter Description Allowed range buf Pointer to the data area spw Pointer to the spwvars struct associated with GRSPW core that should receive the packe
562. read only RESERVED SDRAM enable SE Enables the SDRAM controller and disables fifth SRAM bank RAMSN 4 SRAM disable SI Disables accesses to SRAM bank if bit 14 SE is set to 1 RAM bank size RAM BANK SIZE Sets the size of each RAM bank 0000 8 kbyte 0001 16 kbyte 1111 256 Mbyte RESERVED RAM bus ready enable RBRDY Enables bus ready signalling for the RAM area Read modify write enable RMW Enables read modify write cycles for sub word writes to 16 bit 32 bit areas with common write strobe no byte write strobe RAM width RAM WIDTH Sets the data width of the RAM area 00 8 01 16 1X 32 RAM write waitstates RAM WRITE WS Sets the number of wait states for RAM write cycles 00 0 01 1 10 2 11 3 RAM read waitstates RAM READ WS Sets the number of wait states for RAM read cycles 00 0 01 1 10 2 11 3 27 15 3 Memory configuration register 3 MCFG3 MCFG3 contains the reload value for the SDRAM refresh counter and to control and monitor the memory EDAC It also contains the configuration of the register file EDAC 31 Table 202 Memory configuration register 3 28 27 26 RESERVED ME SDRAM REFRESH COUNTER 200 Table 202 Memory configuration register 3 12 11 10 9 8 7 0 WB RB RE PE TCB 31 28 RESERVED 27 Memory EDAC ME Indicates if memory E
563. recessive Ob is dominant Legend Naming and number in according to CAN standard IDE Identifier Extension 1b for Extended Format Ob for Standard Format RTR Remote Transmission Request 1b for Remote Frame Ob for Data Frame bID Base Identifier eID Extended Identifier DLC Data Length Code according to CAN standard 0000b 0 bytes 0001b 1 byte 0010b 2 bytes 0011b 3 bytes 0100b 4 bytes 0101b 5 bytes 0110b 6 bytes 0111b 7 bytes 158 22 11 22 12 22 13 1000b 8 bytes OTHERS illegal TxErrCntr Transmission Error Counter RxErrCntr Reception Error Counter AHBErr AHB interface blocked due to AHB Error when 1b OR Reception Over run when 1b OFF Bus Off mode when 1b PASS Error Passive mode when 1b Byte 00 to07 Transmit Receive data Byte 00 first Byte 07 last Vendor and device identifiers The module has vendor identfier 0x01 Gaisler Research and device identfier 0x03D For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 172 shows the configuration options of the core VHDL generics Table 172 Configuration options Generic name Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pindex APB slave index 0 NAPBSLV 1 0 paddr Addr field of the APB bar 0 16 FFFH 0 pmask Mask field of the APB bar 0 16 FFFH 16 FFC pirq Interrupt line used by the GRCAN 0 NAHB
564. required The decoder takes the serial Manchester received data from the bus and extracts the received data words The decoder contains a digital phased lock loop PLL that generates a recovery clock used to sample the incoming serial data The data is then deserialized and the 16 bit word decoded The decoder detects whether a command status or data word has been received and checks that no Manchester encoding or parity errors occurred in the word The protocol controller block handles all the message sequencing and error recovery This is a com plex state machine that reads the 1553B message frames from memory and transmits them on the 1553B bus The AMBA interface allows a system processor to access the control registers It also allows the processor to directly access the memory connected to the backend interface this simplifies the system design The B1553BC core provides an AMBA interface with GRLIB plug amp play for the Actel Core1553BBC core MIL STD 1553B Bus Controller B1553BC implements two AMBA inter faces one AHB master interface for the memory interface and one APB slave interface for the CPU interface and control registers The Actel Core1553BBC core entity named BC1553B is configured to use the shared memory inter face and only internal register access is allowed through the APB slave interface Data is read and stored via DMA using the AHB master interface B1553BC Oa GR1553BC 4 Actel Core1553BBC H
565. ress error Shows the value of the rtaderr output from Core1553BRM 3 Memory failure Shows the value of the memfail output from Core1553BRM Ze Busy Shows the value of the busy output from Core1553BRM 1 Active Show the value of the active output from Core1553BRM 0 Ssyfn Connects directly to the ssyfn input of the Core1553BRM core Resets to 1 B1553BRM interrupt register 31 2 1 0 RESERVED intackm intackh intlevel Figure 42 B1553RM interrupt register 2 Message interrupt acknowledge Controls the intackm input signal of the Core1553BRM core Rh Hardware interrupt acknowledge Controls the intackh input signal of the Core1553BRM core O Interrupt level Controls the intlevel input signal of the Core1553BRM core AHB page address register 31 abits 0 ahbaddr RESERVED Figure 43 AHB page address register 31 17 Holds the top most bits of the AHB address of the allocated memory area 19 5 19 6 Vendor and device identifiers 109 The core has vendor identifier 0x01 Gaisler Research and device identifier 0x072 For a description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 105 shows the configuration options of the core VHDL generics Table 105 Configuration options Generic Function Allowed range Default hindex AHB master index 0 NAHBMST 1 0 pi
566. ress space Each plug amp play block occupies 8 bytes The address of the plug amp play information for a certain unit is defined by its bus index If the bridge is mapped on AHB address 0x80000000 the address for the plug amp play records is thus 0x800FF000 n 8 31 24 23 1211 10 9 5 4 0 0x00 VENDOR ID DEVICE ID 00 VERSION IRQ Configuration word 0x04 ADDR C P MASK TYPE BAR 31 20 19 16 15 4 3 0 Figure 21 APB plug amp play information 70 13 3 13 4 13 5 13 6 APB bus monitor An APB bus monitor is integrated into the core It is enabled with the enbusmon generic It has the same functionality as the APB parts in the AMBA monitor core AMBAMON For more information on which rules are checked se the AMBAMON documentation Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0x006 For description of vendor and device identifiers see GRLIB IP Library User s Manual Configuration options Table 62 shows the configuration options of the core VHDL generics Table 62 Configuration options Generic Function Allowed range Default hindex AHB slave index 0 NAHBSLV 1 0 haddr The MSB address of the AHB area Sets the 12 most sig O 16 FFF 16 FFFH nificant bits in the 32 bit AHB address hmask The AHB area address mask Sets the size of the AHB 0 16 FFFH
567. rface two 16 32 or 64 bit DDR266 memory banks to a 32 bit AHB bus The controller acts as a slave on the AHB bus where it occupies a configurable amount of address space for DDR SDRAM access The DDR controller is programmed by writing to a configuration register mapped located in AHB I O address space Internally DDRSPA consists of a ABH DDR controller and a technology specific DDR PHY Currently supported technologeis for the PHY is Xilinx Virtex2 Virtex4 and Altera Startix II The modular design of DDRSPA allows to add support for other target technologies in a simple manner The DDRSPA is used in the following GRLIB template designs leon3 avnet ml401 leon3 avnet eval xc4v leon3 digilent xup leon3 digilent xc3s1600e and leon3 altera ep2s60 ddr AHB DDRSPA DDR CLOCK DDR266 CONTROLLER 16 32 64 bit DDR Memory CLK CLKN gt SKa CSN AHB SLAVE DDR RAS CAS PHY we DQM CKE CKE ADDR 13 0 ADDR 13 0 ADDRESS 16 2 a 3al A 1 0 D 127 0 DQ 63 0 Da 63 0 Figure 52 DDRSPA Memory controller conected to AMBA bus and DDR SDRAM Operation 23 2 1 General Double data rate SDRAM DDR RAM access is supported to two banks of 16 32 or 64 bit DDR266 compatible memory devices The controller supports 64M 128M 256M 512M and 1G devices with 9 12 column address bits up to 14 row address bits and 4 internal banks The size of each of each chip select can be programmed in binary steps between 8 Mbyte and 1024 Mbyte The
568. ring synthesis The APB interface is also removed since it is redundant without EDAC The following can be configured during run time EDAC can be enabled and disabled When it is dis abled reads and writes will behave as the standard memory Read and write diagnostics can be con trolled through separate bits The single error counter can be reset 182 If EDAC is disabled EN bit in configuration register set to 0 write data is passed directly to the memory area and read data will appear on the AHB bus immediately after 1t arrives from memory If EDAC is enabled write data is passed to an encoder which outputs a 7 bit checksum The checksum is stored together with the data in memory and the whole operation is performed without any added waitstates This applies to word stores 32 bit If a byte or halfword store is performed the whole word to which the byte or halfword belongs must first be read from memory read modify write A new checksum is calculated when the new data is placed in the word and both data and checksum are stored in memory This is done with 1 2 additional waitstates compared to the non EDAC case Reads with EDAC disabled are performed with 0 or 1 waitstates while there could also be 2 waitstates when EDAC is enabled There is no difference between word and subword reads Table 191 shows a summary of the number of waitstates for the different operations with and without EDAC Table 191 Summary of the number of waitsta
569. riptors must first be set in the GRETH_GBIT This is done in the transmitter descriptor pointer register The address must be aligned to a 1 kB boundary Bits 31 to 10 hold the base address of descriptor area while bits 9 to 3 form a pointer to an individual descriptor The first descriptor should be located at the base address and when it has been used by the GRETH_GBIT the pointer field is incremented by 8 to point at the next descriptor The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached the descriptor at address offset Ox3F8 has been used The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB bound ary The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register It should never be touched when a transmission is active The final step to activate the transmission is to set the transmit enable bit in the control register This tells the GRETH_GBIT that there are more active descriptors in the descriptor table This bit should always be set when new descriptors are enabled even if transmissions are already active The descrip tors must always be enabled before the transmit enable bit is set 287 35 3 3 Descriptor handling after transmission When a transmission of a packet has finished status is written to the first word in the corresponding descriptor The Underrun Error bit is
570. roller GRLFPC allows GRFPU Lite to execute in parallel with the processor pipeline as long as no new FPU instructions are pending Below is a table of worst case throughput of the GRFPU Lite Table 400 GRFPU Lite worst case instruction timing with GRLFPC Instruction Throughput Latency FADDS FADDD FSUBS FSUBD FMULS FMULD FSMULD FITOS FITOD FSTOI FDTOL FSTOD FDTOS FCMPS FCMPD FCMPES FCMPED 8 8 FDIVS 31 31 FDIVD 57 57 FSQRTS 46 46 FSQRTD 65 65 When the GRFPU Lite is enabled in the model the version field in fsr has the value of 3 44 7 3 The Meiko FPU The Meiko floating point core operates on both single and double precision operands and imple ments all SPARC V8 FPU instructions The Meiko FPU is interfaced through the Meiko FPU control ler MFC which allows one FPU instruction to execute in parallel with IU operation The MFC implements the SPARC deferred trap model and the FPU trap queue FQ can contain up to one queued instruction when an FPU exception is taken When the Meiko FPU is enabled in the model the version field in fsr has the value of 1 The Meiko FPU is not distributed with the open source LEON3 model and must be obtained sepa rately from Sun 44 7 4 Generic co processor LEON can be configured to provide a generic interface to a user defined co processor The interface allows an execution unit to operate in parallel to increase performance One co processor i
571. roller are delayed for 1 2 clock This is done by clocking all output registers on the falling clock edge This option can be used on FPGA targets where proper SDRAM clock synchronization cannot be achieved The SDRAM clock can be the internal AHB clock without further phase adjustements Since the SDRAM signals will only have 1 2 clock period to propagate this option typically limits the maximum SDRAM fre quency to 40 50 MHz Registers The memory controller is programmed through register s mapped into the AHB I O space defined by the controllers AHB BARI Table 451 SDRAM controller registers AHB address offset Register 0x0 SDRAM Configuration register 55 4 453 55 3 1 SDRAM configuration register SDCFG SDRAM configuration register is used to control the timing of the SDRAM 31 30 29 27 26 25 23 22 21 20 19 14 0 15 D64 SDRAM refresh reload value 14 0 15 20 19 22 21 25 23 26 29 27 30 31 B SDRAM command SDRAM Col size SDRAM Bank size CAS delay tRCD tRFC tRP Refresh enable Figure 223 SDRAM configuration register The period between each AUTO REFRESH command Calculated as follows tpppresy reload value 1 SYSCLK 64 bit data bus D64 Reads 1 if memory controller is configured for 64 bit data bus otherwise 0 Read only SDRAM command Writing a non zero value will generate an SDRAM
572. ror during reception Ze OR Over run during reception 1 OFF Bus off condition 0 PASS Error passive condition All bits in all interrupt registers are reset to Ob after reset 157 Note that the TxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis The interrupt generation is independent of the Can CONF ABORT field setting Note that the RxAHBErr interrupt is generated in such way that the corresponding read and write pointers are valid for failure analysis The interrupt generation is independent of the Can CONF ABORT field setting 22 10 Memory mapping The CAN message is represented in memory as shown in table 171 Table 171 CAN message representation in memory AHB addr 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 IDE RT bID eID R 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 eID 0x4 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 DLC TxErrCntr 15 14 13 12 11 10 9 8 T 6 5 4 3 2 1 0 RxErrCntr Ahb OR Off Pass Err 0x8 31 30 29 28 2T 26 29 24 23 22 21 20 19 18 17 16 Byte 0 first transmitted Byte 1 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 2 Byte 3 0xC 31 30 29 28 27 26 25 24 2B 22 21 20 19 18 17 16 Byte 4 Byte 5 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Byte 6 Byte 7 last transmitted Values Levels according to CAN standard 1b is
573. rrupt 1 enabled 0 disabled IR 2 Error warning interrupt 1 enabled 0 disabled IR 1 Transmit interrupt 1 enabled 0 disabled IR O Receive interrupt 1 enabled 0 disabled 21 5 7 Arbitration lost capture register Table 125 Bit interpretation of arbitration lost capture register ALC address 11 Bit Name Description ALC 7 5 reserved ALC 4 0 Bit number Bit where arbitration is lost When the core loses arbitration the bit position of the bit stream processor is captured into arbitration lost capture register The register will not change content again until read out 21 5 8 Error code capture register Table 126 Bit interpretation of error code capture register ECC address 12 Bit Name Description ECC 7 6 Error code Error code number ECC 5 Direction 1 Reception 0 transmission error ECC 4 0 Segment Where in the frame the error occurred When a bus error occurs the error code capture register is set according to what kind of error occurred if it was while transmitting or receiving and where in the frame it happened As with the ALC register the ECC register will not change value until it has been read out The table below shows how to inter pret bit 7 6 of ECC Table 127 Error code interpretation ECC 7 6 Description 0 Bit error Form error 1 2 Stuff error 3 Other 129 Bit 4 downto 0 of the ECC register is interpr
574. rs are allocated and the link is started again The configuration before the call will be pre served except for the packet sizes The argument must be a pointer to a spw_ioctl_packetsize struct The call will fail if the argument contains an illegal pointer the requested buffer sizes cannot be allo cated or the link cannot be re started GET_LINK_STATUS This call returns the current link status The argument must be a pointer to an integer The return value in the argument can be one of the following O Error reset 1 Error wait 2 Ready 3 Started 4 Connecting 5 Run The call will fail if the argument contains an illegal pointer GET_CONFIG This call returns all configuration parameters in a spw_config struct which is defined in spacewire h The argument must be a pointer to a spw_config struct The call will fail if the argument contains an illegal pointer GET_STATISTICS This call returns all statistics in a spw_stats struct The argument must be a pointer to a spw_stats struct The call will fail if the argument contains an illegal pointer CLR_STATISTICS This call clears all statistics No argument is taken and the call always succeeds SEND This call sends a packet The difference to the normal write call is that separate data and header buff ers can be used The argument must be a pointer to a spw_ioctl_send struct The call will fail if the argument contains an illegal pointer or the struct contains illegal valu
575. rst asserted until it is visible internally In figure 78 one cycle is added to the data2 phase datai data2 data2 lead out RO ae CUE ae ee ee ao free Me address romsn iosn a TN MA OP AA oen ee Ct A a S data brdyn le eT A e bexcn MAA Figure 78 BRDYN asynchronous sampling and BEXCN timing Lead out cycle is only applicable for I O accesses datal data2 data2 data2 lead out ws brdyn clk he Se Art NAS NANS NANAI AS NIAS address dii ss mo S S E le ih AS EE O SS oen PP WN tae Let ale Us A A te data brdyn Pt OA 0 1 a ite a ap Figure 79 Read cycle with one waitstate configured and one BRDYN generated waitstate synchronous sampling 27 12 Access errors An access error can be signalled by asserting the BEXCN signal which is sampled together with the data If the usage of BEXCN is enabled in memory configuration register 1 an error response will be generated on the internal AHB bus BEXCN can be enabled or disabled through memory configura tion register 1 and is active for all areas PROM IO and RAM BEXCN is only sampled in the last access for 8 and 16 bit mode for RAM and PROM That is when four bytes are written for a word access to 8 bit wide memory BEXCN is only sampled in the last access with the same timing as a sin gle access in 32 bit mode 197 datal data2 lead out address a O TI O oen O O A T T T e data bexcn fe i oN I e e
576. rupt will be generated each time a packet is transmitted The interrupt is generated regardless of whether the transmission was successful or not Not reset Receive Interrupt RI If set an interrupt will be generated each time a packet has been received This happens both if the packet is terminated by an EEP or EOP Not reset AHB Error Interrupt AJ If set an interrupt will be generated each time an AHB error occurs when this DMA channel is accessing the bus Not reset Packet Sent PS This bit is set each time a packet has been sent Never cleared by the SW node Cleared when written with a one Reset value 0 Packet Received PR This bit is set each time a packet has been received never cleared by the SW node Cleared when written with a one Reset value 0 TX AHB Error TA An error response was detected on the AHB bus while this transmit DMA channel was accessing the bus Cleared when written with a one Reset value 0 RX AHB Error RA An error response was detected on the AHB bus while this receive DMA channel was accessing the bus Cleared when written with a one Reset value 0 Abort TX AT Set to one to abort the currently transmitting packet and disable transmissions If no transmission is active the only effect is to disable transmissions Self clearing Reset value 0 RX Active RX Is set to 1 if a reception to the DMA channel is currently active otherwise it is 0
577. s MMU disabled Cycles MMU enabled IMPL REIT 43 3 Double load 2 2 Single store 2 4 Double store 3 5 SMUL UMUL 4 4 SDIV UDIV 35 35 Taken Trap 5 5 Atomic load store 3 5 All other instructions 1 1 Multiplication cycle count is 5 clocks when the multiplier is configured to be pipelined 44 2 3 SPARC Implementor s ID Gaisler Research is assigned number 15 OxF as SPARC implementor s identification This value is hard coded into bits 31 28 in the psr register The version number for LEON3 is 3 which is hard coded in to bits 27 24 of the psr 44 2 4 Divide instructions Full support for SPARC V8 divide instructions is provided SDIV UDIV SDIVCC amp UDIVCC The divide instructions perform a 64 by 32 bit divide and produce a 32 bit result Rounding and overflow detection is performed as defined in the SPARC V8 standard 373 44 2 5 Multiply instructions The LEON processor supports the SPARC integer multiply instructions UMUL SMUL UMULCC and SMULCC These instructions perform a 32x32 bit integer multiply producing a 64 bit result SMUL and SMULCC performs signed multiply while UMUL and UMULCC performs unsigned multiply UMULCC and SMULCC also set the condition codes to reflect the result The multiply instructions are performed using a 16x16 signed hardware multiplier which is iterated four times To improve the timing the 16x16 multiplier can optionally be provided with a pipeline stage 44 2 6 Multiply a
578. s allows the 64 bit SDRAM devices to be connected using the full data capacity of the devices 64 bit SDRAM devices can be connected to 32 bit data bus if 64 bit data bus is not available but in this case only half the full data capacity will be used 28 2 10 Clocking The SDRAM clock typically requires special synchronisation at layout level For Virtex targets GR Clock Generator can be configured to produce a properly synchronised SDRAM clock For other FPGA targets the GR Clock Generator can produce an inverted clock 28 2 11 EDAC The controller optionally contains Error Detection And Correction EDAC logic using a BCH 32 7 code It is capable of correcting one bit error and detecting two bit errors The EDAC logic does not add any additional waitstates during normal operation Detected errors will cause additional waitstates for correction single errors or error reporting multiple errors Single errors are automatically cor rected and generally not visible externally unless explicitly checked This checking is done by monitoring the ce signal and single error counter This counter holds the number of detected single errors The ce signal is asserted one clock cycle when a single error is detected and should be connected to the AHB status register This module stores the AHB status of the instruction causing the single error and generates interrupts see the AHB status register documenta tion for more information The EDAC functio
579. s are interesting This option has to be enabled with the usequal generic and the qualifier bit and value are written to a register 46 2 4 Arming To start operation the logic analyzer needs to be armed This is done by writing to the status register with bit O set to 1 A reset can be performed anytime by writing zero to the status register After the final triggering event the trigged flag will be raised and can be read out from the status register The logic analyzer remains armed and trigged until the trigger counter reaches zero When this happens the index of the oldest sample can be read from the trace buffer index register Registers Both trace data and all registers are accessed through an APB interface The LOGAN core will allo cate a 64 kbyte block in the APB address space Table 409 APB address mapping APB address offset Registers 0x0000 Status register 0x0004 Trace buffer index 0x0008 Page register 0x000C Trig counter 0x0010 Sample freq divider 0x0014 Storage qualifier setting 0x2000 Ox20FF Trig control settings 0x6000 Ox6FFF Pattern mask configuration 0x8000 OxXFFFF Trace data 399 46 3 1 Status register 31 30 29 28 27 20 19 6 5 0 usereg qualifier armed trigged dbits depth trig levels Figure 177 Status register 31 28 These bits indicate whether an input register and or storage qualifier is used and if the Logic Analyzer is arm
580. s asserted This way all the bank sizes can be supported and no memory will be unused except for a maximum of 4 byte in the gap between the data and checkbit area A read access will automati cally read the four data bytes individually from the nominal addresses and the EDAC checkbit byte from the top part of the bank A write cycle is performed the same way Byte or half word write accesses will result in an automatic read modify write access where 4 data bytes and the checkbit byte are firstly read and then 4 data bytes and the newly calculated checkbit byte are writen back to the memory This 8 bit mode applies to SRAM while SDRAM always uses 32 bit accesses The size of the memory bank is determined from the settings in MCFG2 The EDAC cannot be used on memory areas configured in 16 bit mode If the ROM is configured in 8 bit mode EDAC protection is provided in a similar way as for the SRAM memory described above The difference is that write accesses are not being handled automat ically Instead write accesses must only be performed as individual byte accesses by the software writing one byte at a time and the corresponding checkbit byte must be calculated and be written to the correct location by the software The operation of the EDAC can be tested trough the MCFG3 register If the WB write bypass bit is set the value in the TCB field will replace the normal checkbits during memory write cycles If the RB read bypass is set the memory
581. s based on a struct spwvars which stores all the information for a single GRSPW core The information includes its address on the AMBA bus as well as SpaceWire parame ters such as node address and clock divisor A pointer to this struct is used as a input parameter to all the functions If several cores are used a separate struct for each core is created and used when the specific core is accessed Table 347 The spwvars struct Field Description Allowed range regs Pointer to the GRSPW nospill The nospill value used for the core 0 1 rmap Indicates whether the core is configured with RMAP Set by 0 1 spw_init rxunaligned Indicates whether the core is configured with rxunaligned support 0 1 Set by spw_init rmapcrc Indicates whether the core is configured with RMAPCRC support 0 1 Set by spw_init clkdiv The clock divisor value used for the core 0 255 nodeaddr The node address value used for the core 0 255 destkey The destination key value used for the core 0 255 rxmaxlen The Receiver maximum length value used for the core 0 33554431 rxpnt Pointer to the next receiver descriptor 0 127 rxchkpnt Pointer to the next receiver descriptor that will be polled 0 127 txpnt Pointer to the next transmitter descriptor 0 63 txchkpnt Pointer to the next transmitter descriptor that will be polled 0 63 timetxen The timetxen value used for this core 0 1 timerxen The timerxen value use
582. sages for transmission one in the fetch buffer which is fed to the CAN core and one in the prefetch buffer After a message has been successfully transmitted the prefetch buffer contents are moved to the fetch buffer provided that there is message ready The read pointer CanTxRD READ is automatically incremented after a successful transmission i e after the fetch buffer contents have been transmitted taking wrap around effects of the circular buffer into account If there is at least an additional CAN message available in the circular buffer a new prefetch will be performed If the write and read pointers are equal no more prefetches and fetches will be performed and trans mission will stop If the single shot mode is enabled for the transmit channel CanTxCTRL SINGLE 1 any message for which the arbitration is lost or failed for some other reason will lead to the disabling of the chan nel CanTxCTRL ENABLE 0 and the message will not be put up for re arbitration Interrupts are provided to aid the user during transmission as described in detail later in this section The main interrupts are the Tx TxEmpty and TxIrq which are issued on the successful transmission of a message when all messages have been transmitted successfully and when a predefined number of messages have been transmitted successfully The TxLoss interrupt is issued whenever transmission arbitration has been lost could also be caused by a communications error
583. se the bus request immediately after the first access has started For this to work however the VHDL generic fixbrst should be set to 1 5 2 2 Decoding Decoding generation of HSEL of AHB slaves is done using the plug amp play method explained in the GRLIB User s Manual A slave can occupy any binary aligned address space with a size of 1 4096 Mbyte A specific I O area is also decoded where slaves can occupy 256 byte 1 Mbyte The default address of the I O area is OxFFFO0000 but can be changed with the cfgaddr and cfgmask VHDL generics Access to unused addresses will cause an AHB error response 5 2 3 Plug amp play information GRLIB devices contain a number of plug amp play information words which are included in the AHB records they drive on the bus see the GRLIB user s manual for more information These records are combined into an array which is connected to the AHB controller unit The plug amp play information is mapped on a read only address area defined by the cfgaddr and cfg mask VHDL generics By default the area is mapped on address OxFFFFFOOO OxFFFFFFFF and contains information for all buses in the system The master information is placed on the first 2 kbyte of the block OxFFFFFO00 OxFFFFF800 while the slave information is placed on the second 2 kbyte block The master and slave information area contains plug amp play information for all AHB busus in the system where each bus occupies 512 bytes masters on bus
584. sed by floating point load and store instructions LDF LDDF STD STDF and float ing point operate instructions FPop Floating Point State Register FSR GRFPC manages the floating point state register FSR containing FPU mode and status information All fields of the FSR register as defined in SPARC V8 specification are implemented and managed by the GRFPU conforming to SPARC V8 specification and IEEE 754 standard Implementation specific parts of the FSR managing are the NS non standard bit and ftt field If the NS non standard bit of the FSR register is set all floating point operation will be performed in non standard mode as described in section 37 2 6 When NS bit is cleared all operations are per formed in standard IEEE compliant mode Following floating point trap types never occur and are therefore never set in the ftt field unimplemented_FPop all FPop operations are implemented hardware_error non resumable hardware error invalid_fp_register no check that double precision register is 0 mod 2 is performed GRFPU implements the qne bit of the FSR register which reads 0 if the floating point deferred queue FQ is empty and 1 otherwise The FSR is accessed using LDFSR and STFSR instructions Floating Point Exceptions and Floating Point Deferred Queue GRFPU implements SPARC deferred trap model for floating point exceptions fp_exception A floating point exception is caused by a floating point instruction perform
585. signal ahbmo ahb_mst_out_vector others gt ahbm_none signal ahbmi ahb_mst_in_type signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal cani0 can_in_type signal canoo can_out_type Component instantiation grcan0 grcan generic map hindex gt 1 pindex gt 1 paddr gt 16 00C pmask gt LO FFC pirg gt 1 txchannels gt 1 rxchannels Bo Ly ptrwidth gt 16 port map rstn gt rstn clk gt clk apbi gt apbi apbo gt apbo 1 ahbi gt ahbmi ahbo gt ahbmo 1 cani gt canio cano gt cano0 160 cantx0_pad generic canrx0_pad generic Canen0_pad generic cantxl_pad generic canrxl_pad generic canenl_pad generic outpad map tec inpad map tec outpad map tec outpad map tec inpad map tec outpad map tec pad pad pad pad pad pad tec tec tee tec tec tec h h h h h h port port port port port port map map map map map map cantx 0 canrx 0 canen 0 cantx 1 canrx 1 canen 1 cani0 cani0 cani0 cani0 cani0 cani0 tx 0 rx 0 en 0 tx 1 Lx 109 en 1 23 23 1 23 2 161 DDRSPA 16 32 and 64 bit DDR266 Controller Overview DDRSPA is a DDR266 SDRAM controller with AMBA AHB back end The controller can inte
586. signals of the core VHDL ports Table 37 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low CLK N A Input Clock AHBSI Input AMB slave input signals AHBSO Output AHB slave output signals see GRLIB IP Library User s Manual Library dependencies Table 38 shows libraries used when instantiating the core VHDL libraries Table 38 Library dependencies Library Package Imported unit s Description GRLIB AMBA Types AMBA signal type definitions Component declaration component ahbrom generic hindex integer haddr integer 0 hmask integer 16 fff pipe integer 0 tech integer 0 port rst in std_ulogic clk in std_ulogic ahbsi ahbso i end component Instantiation in ahb_slv_in_type out ahb_slv_out_type This examples shows how the core can be instantiated library grlib use grlib amba all brom entity work ahbrom hindex gt 8 rstn clkm generic map port map haddr gt CFG_AHBRODDR pipe gt CFG_AHBROPIP ahbso 8 9 1 9 2 9 3 51 AHBSTAT AHB Status Registers Overview The status registers store information about AMBA AHB accesses triggering an error response There is a status register and a failing address register capturing the control and address signal values of a failing AMBA bus transaction or the occurence of a correctable error being si
587. sired baud rate If the EC bit is set the scaler will be clocked by the external clock input rather than the system clock In this case the frequency of external clock must be less than half the frequency of the system clock 15 3 1 Loop back mode If the LB bit in the UART control register is set the UART will be in loop back mode In this mode the transmitter output is internally connected to the receiver input and the RTSN is connected to the CTSN It is then possible to perform loop back tests to verify operation of receiver transmitter and associated software routines In this mode the outputs remain in the inactive state in order to avoid sending out data 15 3 2 Interrupt generation Interrupts are generated differently when a holding register is used VHDL generic fifosize 1 and when FIFOs are used VHDL generic fifosize gt 1 When holding registers are used the UART will generate an interrupt under the following conditions when the transmitter is enabled the transmitter interrupt is enabled and the transmitter holding register moves from full to empty when the receiver is enabled the receiver interrupt is enabled and the receiver holding register moves from empty to full when the receiver is enabled the receiver interrupt is enabled and a character with either parity framing or overrun error is received For FIFOs two different kinds of interrupts are available normal interrupts and FIFO interrupts For the transmitter
588. slvl Gaisler Research Generic UART 42 Se SR de dp de dp Ade de de dh de de Se e e apbctrl O ports at 0x80000100 size 256 byte apbctrl slv2 Gaisler Research Multi processor Interrupt Ctrl apbctrl O ports at 0x80000200 size 256 byte apbctrl slv3 Gaisler Research Modular Timer Unit apbctrl O ports at 0x80000300 size 256 byte apbctrl slv7 Gaisler Research AHB Debug UART apbctrl O ports at 0x80000700 size 256 byte apbctrl slv11 Gaisler Research General Purpose 1 0 port apbctrl O ports at 0x80000b00 size 256 byte grgpioll 8 bit GPIO Unit rev 0 gptimer3 GR Timer Unit rev 0 8 bit scaler 2 32 bit timers irq 8 irgmp Multi processor Interrupt Controller rev 3 cpu 1 apbuartl Generic UART rev 1 fifo 4 irq 2 ahbuart7 AHB Debug UART rev 0 leon3_0 LEON3 SPARC V8 processor rev 0 leon3_0 icache 1 8 kbyte dcache 1 8 kbyte VSIM 2 gt 6 1 6 2 43 AHBJTAG JTAG Debug Link with AHB Master Interface Overview The JTAG debug interface provides access to on chip AMBA AHB bus through JTAG The JTAG debug interface implements a simple protocol which translates JTAG instructions to AHB transfers Through this link a read or write transfer can be generated to any address on the AHB bus TDI TCK MJTAGTAP _ y Ts Controller JTAG Communication d Interface t TDO AHB master interface AMBA AHB Figure 8 JTAG Debug link blo
589. speed in both full and half duplex The AMBA interface consists of an APB interface for configuration and control and an AHB master interface which handles the dataflow The dataflow is handled through DMA channels There is one DMA engine for the transmitter and one for the receiver Both share the same AHB master interface The ethernet interface supports the MII and GMII interfaces which should be connected to an external PHY The GRETH also provides access to the MII Management interface which is used to configure the PHY Optional hardware support for the Ethernet Debug Communication Link EDCL protocol is also provided This is an UDP IP based protocol used for remote debugging Some of the supported features for the DMA channels are Scatter Gather I O and TCP UDP over IPv4 checksum offloading for both receiver and transmitter Software Drivers are provided for RTEMS eCos uClinux and Linux 2 6 APB AHB Ethernet MAC t MDIO_OE gt MDIO_O lt Registers 4 Po mDiO MDO gt MDC i a gt TX EN Transmitter gt gt TX_ER DMA Engine RAM gt TXD 7 0 lt gt Transmitter Hg mer la TX_CLK ol EDCL E RX_CRS Transmitter gt gt Pp RX_COL t gt AHB Master a Interface GTX_CLK EDCL gt pp Receiver ca ha RX_DV e ld RX_ER lt Recaiver Receiver k RXD 7
590. ssages available for transmit when CanTxSIZE SIZE 2 CanTxWR WRITE 5 and CanTxRD READ 3 When a CAN message has been successfully transmitted the read pointer CanTxRD READ is auto matically incremented taking wrap around effects of the circular buffer into account Whenever the write pointer CanTxWR WRITE and read pointer CanTxRD READ are equal there are no CAN mes sages available for transmission 22 5 3 Location The location of the circular buffer is defined by a base address CanTxADDR ADDR which is an absolute address The location of a circular buffer is aligned on a 1kbyte address boundary 22 5 4 Transmission procedure When the channel is enabled Can TxCTRL ENABLE 1 as soon as there is a difference between the write and read pointer a message transmission will be started Note that the channel should not be enabled if a potential difference between the write and read pointers could be created to avoid the message transmission to start prematurely A message transmission will begin with a fetch of the complete CAN message from the circular buffer to a local fetch buffer in the CAN controller After a successful data fetch a transmission request will be forwarded to the CAN core If there is at least an additional CAN message available in the circular buffer a prefetch of this CAN message from the circular buffer to a local prefetch buffer in the CAN controller will be performed The CAN controller can thus hold two CAN mes
591. sters There are three common registers with the same addresses and the same functionality in both Basi CAN and PeliCAN mode These are the clock divider register and bus timing register O and 1 21 6 1 Clock divider register The only real function of this register in the GRLIB version of the Opencores CAN is to choose between PeliCAN and BasiCAN The clkout output of the Opencore CAN core is not connected and it is its frequency that can be controlled with this register Table 144 Bit interpretation of clock divider register CDR address 31 Bit Name Description CDR 7 CAN mode 1 PeliCAN 0 BasiCAN CDR 6 unused cbp bit of SJA1000 CDR 5 unused rxinten bit of SJA1000 CDR 4 reserved CDR 3 Clock off Disable the clkout output CDR 2 0 Clock divisor Frequency selector 21 6 2 Bus timing 0 Table 145 Bit interpretation of bus timing 0 register BTRO address 6 Bit Name Description BTRO 7 6 SJW Synchronization jump width BTRO 5 0 BRP Baud rate prescaler The CAN core system clock is calculated as ty 2 ty BRP 1 where tei is the system clock The sync jump width defines how many clock cycles t a bit period may be adjusted with by one re synchronization 136 21 7 21 8 21 6 3 Bus timing 1 Table 146 Bit interpretation of bus timing 1 register BTR1 address 7 Bit Name Description BTR1 7 SAM 1 The bus is sampled three tim
592. sters bypass and device identification code register The core is capa ble of shifting and updating the JTAG instruction register putting the device into bypass mode BYPASS instruction and shifting out the devices identification number IDCODE instruction User defined JTAG test registers are accessed through user defined data register interface The access to the user define test data registers is provided through the user defined data register interface The instruction in the TAP controller instruction register appears on the interface as well as shift in data and signals indicating that the TAP controller is in Capture Data Register Shift Data Register or Update Data Register state Logic controlling user defined data registers should observe value in the instruction register and TAP controller state signals in order to capture data shift data or update data registers JTAG test registers such as boundary scan register can be interfaced to the TAP controller through the user data register interface Technology specific TAP controllers The core instantiates technology specific TAP controller for Altera and Xilinx devices Registers The core implements three JTAG registers instruction bypass and device identification code register Vendor and device identifiers The core does not have vendor and device identifiers since it does not have AMBA interfaces 490 62 6 Configuration options Table 480 shows the configuration options
593. t int spw_checkrx int size struct rxstatus rxs struct spwvars spw Checks if a packet has been received When a packet has been received the size in bytes will be stored in the size parameter and status is found in the rxs struct A pointer in the spwvars struct is used to keep track of the location in the descriptor table to poll It is incremented each time the function returns nonzero Table 370 Return values for spw_checkrx Value Description 0 No packet has been received 1 A packet has been received Table 371 Parameters for spw_checkrx Parameter Description Allowed range size When the function returns 1 this variable holds the number of bytes received TXS When the function returns 1 this variable holds status information spw Pointer to the spwvars struct associated with GRSPW core that should be polled 357 Table 372 The rxstatus struct Field Description Allowed range truncated Packet was truncated 0 1 dercerr Data CRC error bit was set Only indicates an error if the packet 0 1 received was an RMAP packet hercerr Header CRC error bit was se t Only indicates an error if the packet 0 1 received was an RMAP packet eep Packet was terminated with EEP 0 1 int spw_checktx struct spwvars spw Checks if a packet has been transmitted A pointer is used to keep track of the location in the descrip tor table
594. t 3 tech gt padtech tech gt padtech tech gt padtech tech gt padtech tech gt padtech tech gt padtech tech gt padtech 18 18 1 101 B1553BC AMBA plug amp play interface for Actel Core1553BBC Overview The interface provides a complete Mil Std 1553B Bus Controller BC The interface connects to the MIL STD 1553B bus through external transceivers and transformers The interface is based on the Actel Core1553BBC core The interface provides a complete MIL STD 1553B Bus Controller BC The interface reads mes sage descriptor blocks from the memory and generates messages that are transmitted on and transmit ted on the 1553B bus Data received is written to the memory The interface consists of five main blocks the 1553B encoder the 1553B decoder a protocol control ler block a CPU interface and a backend interface A single 1553B encoder takes each word to be transmitted and serializes it using Manchester encod ing The encoder includes independent logic to prevent the BC from transmitting for greater than the allowed period and to provide loopback fail logic The loopback logic monitors the received data and verifies that the interface has correctly received every word that is transmitted The encoder output is gated with the bus enable signals to select which buses the encoder should be transmitting Since the BC knows which bus is in use at any time only a single decoder is
595. t SFF or extended frame format EFF is to be transmitted received See the specific section below 126 21 5 2 Mode register Table 120 Bit interpretation of mode register MOD address 0 Bit Name Description MOD 7 reserved MOD 6 reserved MOD 5 reserved MOD 4 not used sleep mode in SJA1000 MOD 3 Acceptance filter mode 1 single filter mode 0 dual filter mode MOD 2 Self test mode If set the controller is in self test mode MOD 1 Listen only mode If set the controller is in listen only mode MOD Reset mode Writing 1 to this bit aborts any ongoing transfer and enters reset mode Writ ing 0 returns to operating mode Writing to MOD 1 3 can only be done when reset mode has been entered previously In Listen only mode the core will not send any acknowledgements Note that unlike the SJA1000 the Opencores core does not become error passive and active error frames are still sent When in Self test mode the core can complete a successful transmission without getting an acknowl edgement if given the Self reception request command Note that the core must still be connected to a real bus it does not do an internal loopback 21 5 3 Command register Writing a one to the corresponding bit in this register initiates an action supported by the core Table 121 Bit interpretation of command register CMR address 1 Bit Name Description CMR 7 reserved
596. t Memory data High RAMSN 4 0 Output SRAM chip select Low RAMOEN 4 0 Output SRAM output enable Low IOSN Output Not used Driven to 1 inactive Low ROMSN 1 0 Output PROM chip select Low RAMN Output Common SRAM chip select Asserted when one Low of the RAMSNJ 4 0 signals is asserted ROMN Output Common PROM chip select Asserted when one Low of the ROMSN 1 0 signals is asserted OEN Output Output enable Low WRITEN Output Write strobe Low WRNI 3 0 Output SRAM write enable Low WRNI 0 corresponds to DATA 31 24 WRN 1 corresponds to DATA 23 16 WRN 2 corresponds to DATA 15 8 WRN 3 corresponds to DATA 7 0 MBEN 3 0 Output Byte enable Low MBEN 0 corresponds to DATA 31 24 MBENT 1 corresponds to DATA 23 16 MBEN 2 corresponds to DATA 15 8 MBEN 3 corresponds to DATA 7 0 BDRIVE 3 0 Output Drive byte lanes on external memory bus Con Low High trols I O pads connected to external memory bus BDRIVE 0 corresponds to DATA 31 24 BDRIVE 1 corresponds to DATA 23 16 BDRIVE 2 corresponds to DATA 15 8 BDRIVE 3 corresponds to DATA 7 0 VBDRIVE 31 0 Output Identical to BDRIVE but has one signal for each L ow High data bit Every index is driven by its own regis ter This can be used to reduce the output delay READ Output Read strobe High SA 14 0 Output Not used High 462 56 9 56 10 56 11 Table 456 Signal descriptions Signal name Field Type Function Polar
597. t Reset Low CLK N A Input Clock HOLDN N A Input Hold Low DIVI Y 32 0 Input Dividend MSB part High Y 32 Sign bit Y 31 0 Dividend MSB part in 2 s complement format OP1 32 0 Dividend LSB part High OP1 32 Sign bit OP1 31 0 Dividend LSB part in 2 s comple ment format FLUSH Flush current operation High SIGNED Signed division High START Start division High DIVO READY Output The result is available one clock after the ready High signal is asserted NREADY Not used ICC 3 0 Condition codes High ICC 3 Negative result ICC 2 Zero result ICC 1 Overflow ICC 0 Not used Always 0 RESULT 31 0 Result High 170 24 4 24 5 24 6 Library dependencies Table 184 shows libraries used when instantiating the core VHDL libraries Table 184 Library dependencies Library GAISLER Package ARITH Imported unit s Signals component Description Divider module signals component declaration Component declaration The core has the following component declaration component div32 port rst in std_ulogic clk in std_ulogic holdn in std_ulogic divi in div32_in type divo out div32_out_type i end component Instantiation This examples shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use gaisler arith all signal divi div32_in_type signal divo div32_out_type begin d
598. t driver 1 custom N A One of these values is needed Custom is 1024x768 060 used when the user wants to specify all the timings like resolution and refresh rate 800x600 72 The other valuse is for predefined resolu 800x600 60 tions and refresh rates 640x480 60 2 Pixelclock Custom Pixelclock in ns 3 xres Custom Horizontal resolution in pixels 4 rmargin Custom Horizontal front porch in pixels 5 hsync_len Custom Horizontal Sync length in pixels 6 Imargin Custom Horizontal Back porch in pixels 7 yres Custom Vertical resolution in pixels 8 Ilmargin Custom Vertical front porch in pixels 9 vsync_len Custom Vertical Sync length in pixels 10 umargin Custom Vertical Back porch in pixels 11 bits_per_pixel All Bits per pixel Valid 8 16 32 12 Mem_size All Framebuffer memory size in bytes All of these valuse must be defined at the boot options in some form Exceptions are for the values 2 10 if a predefined mode is set Example using the predefined mode at 1024x768 60 with 2 MB memory size video grvga 1024x768 60 16 2000000 The same as above but using a custom mode video grvga custom 15385 1024 24 136 160 768 3 6 29 16 2000000 59 59 1 59 2 481 SYNCRAM Single port RAM generator Overview The single port RAM has a common address bus and separate data in and data out buses All inputs are latched on the on the rising edge of clk The read data appears on dataout directly after the clk ris
599. t implemented Always reads 0 7 Wait cycle control Not implemented Always reads 0 6 Parity Error Response PER Controls units response on parity error 5 VGA Palette Snoop Not implemented Always reads 0 4 Memory Write and Invalidate Enable MIE Enables the PCI Master interface to generate Memory Write and Invalidate Command 3 Special Cycles Not implemented Always reads 0 2 Bus Master BM Enbales the Master Interface to generate PCI cycles 1 Memory Space MS Allows the unit to respond to Memory space accesses 0 T O Space IOS The unit never responds to I O cycles Always reads as 0 31 8 7 0 CLASS CODE REVISION ID Figure 204 Class Code amp revision ID 31 8 Class Code Processor device class code 0x0B4000 Read only 7 0 Revision ID 0x00 Read only 31 24 23 16 15 8 7 0 BIST HEADER LTM CLS Figure 205 BIST Header Type Latency Timer and Cache Line Size register 31 24 BIST Not supported Reads always as 00 0 23 16 Header Type HEADER Header Type 0 Reads always as 00 0 15 8 Latency Timer LTIM Maximum number of PCI clock cycles that Master can own the bus 50 5 431 7 0 Cache Line Size CLS System cache line size Defines the prefetch length for Memory Read and Memory Read Line commands 31 abits 1 abits 2 4321 0 BASE ADDRESS 00 0 al ge o Figure 206
600. t the SRAM area is mapped into address range 0x40000000 Ox40FFFFFF and the I O area is mapped to 0x20000000 0x20FFFFFE One chip select is decoded for the I O area while SRAM can have up to 8 chip select signals The controller generates a common write enable signal WRITEN for both SRAM and I O Number of waitstates is separately configurable for the two address ranges The EDAC function is optional and can be enabled with the edacen VHDL generic The configura tion of the EDAC is done through a configuration register accessed from the APB bus During nomi nal operation the EDAC checksum is generated and checked automatically The 8 bit input to the EDAC function is split into two 4 bit nibbles A modified hamming 8 4 4 coding featuring a single error correction and double error detection is applied to each 4 bit nibble This makes the EDAC capable of correcting up to two errors and detecting up to four errors per 8 bit data Single errors cor rectable errors are corrected without generating any indication of this condition in the bus response If a multiple error uncorrectable errors is detected a two cycle error response is given on the AHB bus Single errors can be monitored in two ways e by monitoring the CE signal which is asserted for one cycle each time a corectable error is detected e by checking the single error counter which is accessed from the MCFG3 configuration register 30 3 237 The CE signal can be
601. ta byte 2 OxFF 14 TX data byte 3 TX data byte 3 OxFF 15 TX data byte 4 TX data byte 4 OxFF 16 TX data byte 5 TX data byte 5 OxFF 17 TX data byte 6 TX data byte 6 OxFF 18 TX data byte 7 TX data byte 7 OxFF 19 TX data byte 8 TX data byte 8 OxFF 20 RX idl RX idl 21 RX id2 rtr dle RX id2 rtr dlc 22 RX data byte 1 RX data byte 1 23 RX data byte 2 RX data byte 2 24 RX data byte 3 RX data byte 3 25 RX data byte 4 RX data byte 4 26 RX data byte 5 RX data byte 5 27 RX data byte 6 RX data byte 6 28 RX data byte 7 RX data byte 7 29 RX data byte 8 RX data byte 8 30 0x00 0x00 31 Clock divider Clock divider Clock divider Clock divider 122 21 4 2 Control register The control register contains interrupt enable bits as well as the reset request bit Table 114 Bit interpretation of control register CR address 0 Bit Name Description CR 7 reserved CR 6 reserved CR 5 reserved CR 4 Overrun Interrupt Enable 1 enabled 0 disabled CR 3 Error Interrupt Enable 1 enabled 0 disabled CR 2 Transmit Interrupt Enable 1 enabled 0 disabled CR 1 Receive Interrupt Enable 1 enabled 0 disabled CR 0 Reset request Writing 1 to this bit aborts any ongoing transfer and enters reset mode Writ ing O returns to operating mode 21 4 3 Command register Writing a one to the corresponding bit in this register init
602. tarting from the MSB at the lowest address 132 21 5 13 Receive buffer Table 136 Read SFF Read EFF 16 RX frame information RX frame information 17 RXID1 RX ID 1 18 RXID2 RX ID2 19 RX data 1 RX ID3 20 RX data2 RX ID4 21 RX data 3 RX data 1 22 RX data 4 RX data 2 23 RX data 5 RX data 3 24 RX data 6 RX data 4 25 RX data 7 RX data 5 26 RX data 8 RX data 6 27 RX FI of next message in fifo RX data 7 28 RX ID1 of next message in fifo RX data 8 RX frame information this field has the same layout for both SFF and EFF frames Table 137 RX frame information address 16 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FF RTR 0 0 DLC 3 DLC 2 DLC 1 DLC 0 Bit7 Frame format of received message 1 EFF 0 SFF Bit6 1if RTR frame Bit 5 4 Always 0 Bit 3 0 DLC specifies the Data Length Code RX identifier 1 this field is the same for both SFF and EFF frames Table 138 RX identifier 1 address 17 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1D 28 1D 27 1D 26 1D 25 1D 24 1D 23 1D 22 ID 21 Bit 7 0 The top eight bits of the identifier RX identifier 2 SFF frame Table 139 RX identifier 2 address 18 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1D 20 1D 19 1D 18 RTR 0 0 0 0 Bit 7 5 Bottom three bits of an SFF identifier Bit 4 1 if RTR frame
603. te will be automatically discovered This is done by searching for the shortest period between two falling edges of the received data corresponding to two bit periods When three identical two bit periods has been found the corresponding scaler reload value is latched into the reload register and the BL bit is set in the UART control register If the BL bit is reset by software the baud rate discovery process is restarted The baud rate discovery is also restarted when a break or framing error is detected by the receiver allowing to change to baudrate from the external transmitter For proper baudrate detection the value 0x55 should be transmitted to the receiver after reset or after sending break The best scaler value for manually programming the baudrate can be calculated as follows scaler system_clk 10 baudrate 8 5 10 Registers The core is programmed through registers mapped into APB address space Table 50 AHB UART registers APB address offset Register 0x4 AHB UART status register 0x8 AHB UART control register OxC AHB UART scaler register 31 2 1 0 RESERVED BLEN Figure 17 AHB UART control register 0 Receiver enable RE if set enables both the transmitter and receiver 1 Baud rate locked BL is automatically set when the baud rate is locked 31 765432 10 RESERVED FE OV TH TS DR Figure 18 AHB UART status register O Dat
604. ted here PHY model phy0 generic map phy win_size gt 8 port map resetn gt rst led_cfg gt eled_cfg mdio gt open tx_clk gt etx_clk rxd gt erxd rx_dv gt erx_dv rx_er gt erx_er erx_clk rx_col gt erx_col rx_crs gt erx_crs txd gt etxd tx_en gt etx_en tx_er gt etx_er end mdc gt emdc 447 rx_clk gt 448 54 54 1 54 2 REGFILE_3P 3 port RAM generator 2 read 1 write Overview The 3 port register file has two read ports and one write port Each port has a separate address and data bus All inputs are latched on the rising edge of clk The read data appears on dataout directly after the clk rising edge Note on most technologies the register file is implemented with two 2 port RAMs with combined write ports Address width data width and target technology is parametrizable through generics Write through is supported if the function syncram_2p_write_through tech returns 1 for the target technology Configuration options Table 445 shows the configuration options of the core VHDL generics Table 445 Configuration options Name Function Range Default tech Technology selection 0 NTECH 0 abits Address bits Depth of RAM is 22bits 1 see table 446 a dbits Data width see table 4461 wrfst Write first write through Only applicable to inferred technol 0 1 0 ogy numregs Not
605. ted unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER USB Signals component USBDCL component declarations USB signals 63 8 Instantiation This example shows how the core can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib tech all library gaisler use gaisler usb all entity usbdcl_ex is port clk in std_ulogic AHB Clock rstn in std_ulogic gt usb signals usb_clkout in std_ulogic usb_d inout std_logic_vector 7 downto 0 usb_linestate in std_logic_vector 1 downto 0 496 end usb_opmo usb_rese usb_rxac usb_rxer usb_rxva usb_susp de t tive ror lid end usb_termsel usb_txre usb_txva usb_xcvr usb_vbus ady lid sel out std out std_ulogic in std in std in std out st out st in std out std d d ulogic ulogic ulogic ulogic ulogic ulogic ulogic out std_ulogic in std ulogic architecture rtl of usbdcl_ex is constant padtech constant memtech AMBA signals signal ahbmi signal ahbmo begin intege intege r inferred r inferred ahb_mst_in_type ahb_mst_out_vector logic_vector 1 downto 0 others gt ahbm_none AMBA Components are instantiated here for iin 0 to 7 generate ad iopad generic map tech gt padtech USBDCL usb_d_pads usb_d_p port map usb_d i usbo do end generate
606. teger integer integer integer integer integer integer integer integer integer integer integer integer integer integer r range std_ulo std_ulo range range range range range range range range range O O Pibe A O O OG H qq range range range range range range range range range range range range range range range range range So 2 Ost oO N E 0 to 15 gic gic CP AES AA O to to to to to to to to to to to to to to to to to to 6 to 6 to to to 2 to to 6 to 2 to MOrFNO ABNF FD OC Hove ll 0 ahb_mst_in_type ahb_mst_out_type ahb_slv_in_type ahb_slv_out_vector 13_irq_in_type 13_irq_out_type 13_debug_in_type 13_debug_out_type a mn Il a mn Il Il o 5T2 255 Diz 255 43S 4 A 0 r 00 Cr BD Y A t i 7 1 16 8e 1 16484 power down single vector trapping 391 392 45 45 1 45 2 LEON3FT Fault Tolerant SPARC V8 Processor Overview LEON3 is a 32 bit processor core conforming to the IEEE 1754 SPARC V8 architecture It is designed for embedded applications combining high performance with low complexity and low power consumption The LEON3 core has the following main features 7 stage pipeline with Harvard architecture sepa rate instruction and data caches on chip debug support and multi processor extensions The LEON3FT processor is a derivate of the standard LEO
607. tep register 0x000024 Debug Mode Mask register 0x000040 AHB trace buffer control register 0x000044 AHB trace buffer index register 0x000050 AHB breakpoint address 1 0x000054 AHB mask register 1 0x000058 AHB breakpoint address 2 0x00005c AHB mask register 2 0x 100000 0x 110000 Instruction trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 C Trace bits 31 0 0x 110000 Intruction Trace buffer control register 0x200000 0x210000 AHB trace buffer 0 Trace bits 127 96 4 Trace bits 95 64 8 Trace bits 63 32 C Trace bits 31 0 0x300000 0x300FFC TU register file 0x301000 0x30107C FPU register file 0x400000 Ox4FFFFC TU special purpose registers 0x 400000 Y register 0x400004 PSR register 0x400008 WIM register 0x40000C TBR register 0x400010 PC register 0x400014 NPC register 0x400018 FSR register 0x40001C CPSR register 0x400020 DSU trap register 0x400024 DSU ASI register 0x400040 0x40007C ASR16 ASR31 when implemented 0x700000 Ox 7FFFFC ASI diagnostic access ASI value in DSU ASI register address address 19 0 ASI 0x9 Local instruction RAM ASI OxB Local data RAM ASI 0xC Instruction cache tags ASI OxD Instruction cache data ASI OxE Data cache tags ASI OxF Instruction cache data The addresses of the IU registers depends on how many register windows has been implemented e on 0x300000 psr cwp
608. ter 31 30 29 28 0 AM 28 0 AM Acceptance Mask bits set to 1b are taken into account in the comparison between the received message ID and the CanRxCODE AC field All bits are set to 1 at reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 22 9 19 Receive Channel Code Register CanRxCODE R W Table 169 Receive Channel Code Register 31 30 29 28 0 AC 28 0 AC Acceptance Code used in comparison with the received message All bits are cleared to Oat reset Note that Base ID is bits 28 to 18 and Extended ID is bits 17 to 0 A message ID is matched when Received ID XOR CanRxCODE AC AND CanRxMASS AM 0 22 9 20 Interrupt registers The interrupt registers give complete freedom to the software by providing means to mask interrupts clear interrupts force interrupts and read interrupt status When an interrupt occurs the corresponding bit in the Pending Interrupt Register is set The normal sequence to initialize and handle a module interrupt is e Set up the software interrupt handler to accept an interrupt from the module e Read the Pending Interrupt Register to clear any spurious interrupts e Initialise the Interrupt Mask Register unmasking each bit that should generate the module inter rupt e When an interrupt occurs read the Pending Interrupt Status Register in the software interrupt handler to determine the causes of the interrupt e Handle the
609. ter Target Unit Operation A connection between the PCI bus and the AMBA bus is provided by the units PCI target interface and AHB master The PCI target is capable of handling configuration and single or burst memory cycles on the PCI bus Configuration cycles are used to access Targets Configuration Space Header while the memory cycles are translated to AHB accesses The PCI target interface can be programmed to occupy two areas in the PCI address space Mapping to AHB address space is defined by a pair of map registers accessible from PCI and AHB address space The PCI master interface occupies one 256 MB AHB memory bank and one 128 KB AHB IO bank Accesses to the memory area are translated to PCI memory cycles and accesses to the IO area gener ate IO or configuration cycles Generation of PCI cycles and mapping to the PCI address spaces is controlled through registers Both target and master interface are capable of burst transactions Data is buffered internally in FIFOs with configurable size Since PCI is little endian and the controller s AHB is big endian it performs byte twisting on all accesses to preserve the byte ordering See figure 201 below 428 50 3 AMBA bus 31 24 23 16 15 8 7 0 Address O Address 3 GRPCI Address 3 Address O PCI Off chip bus 31 24 23 16 15 8 7 0 Figure 201 GRPCI byte twisting The byte twisting can be disa
610. tes for the different operations for the memory Operation Waitstates with EDAC Disabled Waitstates with EDAC Enabled Read 0 1 0 2 Word write 0 0 Subword write 0 1 2 If the ahbpipe VHDL generic is set to 1 pipeline registers are enabled for the AHB input signals If the pipeline registers are enabled one extra waitstate should be added to the read and subword write cases in Table 191 When EDAC is used the data is decoded the first cycle after it arrives from the memory and appears on the bus the next cycle if no uncorrectable error is detected The decoding is done by comparing the stored checksum with a new one which is calculated from the stored data This decoding is also done during the read phase for a subword write A so called syndrome is generated from the comparison between the checksum and it determines the number of errors that occured One error is automatically corrected and this situation is not visible on the bus Two or more detected errors cannot be corrected so the operation is aborted and the required two cycle error response is given on the AHB bus see the AMBA manual for more details If no errors are detected data is passed through the decoder unal tered As mentioned earlier the memory provides read and write diagnostics when EDAC is enabled When write diagnostics are enabled the calculated checksum is not stored in memory during the write phase Instead the TCB field from the configurati
611. tes of data contained in the data field 34 7 34 8 277 Table 299 The EDCL application layer fields in transmitted frames 16 bit Offset 14 bit sequence number 1 bit ACK NAK 10 bit Length 7 bit Unused The EDCL implements a Go Back N algorithm providing reliable transfers The 14 bit sequence number in received packets are checked against an internal counter for a match If they do not match no operation is performed and the ACK NAK field is set to 1 in the reply frame The reply frame con tains the internal counter value in the sequence number field If the sequence number matches the operation is performed the internal counter is incremented the internal counter value is stored in the sequence number field and the ACK NAK field is set to 0 in the reply The length field is always set to 0 for ACK NAK 1 frames The unused field is not checked and is copied to the reply It can thus be set to hold for example some extra identifier bits if needed Media Independent Interfaces There are several interfaces defined between the MAC sublayer and the Physical layer The GRETH supports two of them The Media Independent Interface MII and the Reduced Media Independent Interface RMI The MII was defined in the 802 3 standard and is most commonly supported The ethernet interface have been implemented according to this specification It uses 16 signals The RMII was developed to meet the need for an interface allowi
612. the BRDYN sig nal BRDYN should be asserted in the cycle preceding the last one SRAM IO waveforms The internal and external waveforms of the interface are presented in the figures hereafter 238 CLK RAMSN OEN D HADDR HTRANS HREADY HRDATA CLK A RAMSN WRITEN D HADDR HTRANS HREADY HWDATA HAINE ENEE RIE EE Ca Xan Kar Nars Kara Nas ave rr A AA a a a GT es Xe Xer 0 Xer ae AW A 8 ao a Ff 00 ON A any se wait states and EDAC enabled as ea Para Figure 102 32 bit SRAM sequential read accesses with 0 FAN ee ee mn a se en a ee A A A Gb a ae NM A A O AW NR uo Xm X e C D 31 0 Y D 31 0 Figure 103 32 bit SRAM sequential writeaccess with 0 wait states and EDAC enabled 239 HADDR re HREADY Figure 104 8 bit SRAM non sequential write access with 0 wait states and EDAC enabled RAMSN OEN PA bp F HREADY 1 iA a O pata _ _ Figure 105 8 bit SRAM non sequential read access with 0 wait states and EDAC enabled On a read access data is sampled one clock cycle before HREADY is asserted 240 CLK RAMSN WRITEN D HADDR HTRANS HREADY HWDATA CLK ROMSN RAMSN OEN D HADDR HTRANS HREADY HWDATA TS AE AE UR O E ES a S TE SES Dn SS AGE ME es Ccoyo INN INN E ANO lil ma
613. the PHY after reset EDCL Buffer Size BS Shows the amount of memory used for EDCL buffers 0 1 kB 1 2 kB 6 64 kB EDCL Available ED Set to one if the EDCL is available 16 3 4 322 1 0 IA TS TA RA TI RI TE RE Figure 115 GRETH status register Receiver Error RE A packet has been received which terminated with an error Cleared when written with a one Not Reset Transmitter Error TE A packet was transmitted which terminated with an error Cleared when written with a one Not Reset Receiver Interrupt RI A packet was received without errors Cleared when written with a one Not Reset Transmitter Interrupt TI A packet was transmitted without errors Cleared when written with a one Not Reset 279 4 Receiver AHB Error RA An AHB error was encountered in receiver DMA engine Cleared when written with a one Not Reset 5 Transmitter AHB Error TA An AHB error was encountered in transmitter DMA engine Cleared when written with a one Not Reset 6 Too Small TS A packet smaller than the minimum size was received Cleared when written with a one Reset value 0 7 Invalid Address IA A packet with an address not accepted by the MAC was received Cleared when written with a one Reset value 0 31 16 15 0 RESERVED Bit 47 downto 32 of the MAC Address Figure 116 MAC Address MSB 31
614. the buffer If the read descriptor is not enabled rxdescav is set to 0 and the packet is spilled depending on the value of nospill The receiver can be disabled at any time and will cause all packets received afterwards to be dis carded If a packet is currently received when the receiver is disabled the reception will still be fin ished The rxdescav bit can also be cleared at any time It will not affect any ongoing receptions but no more descriptors will be read until it is set again Rxdescav is also cleared by the GRSPW when it reads a disabled descriptor 325 42 4 7 Address recognition and packet handling When the receiver N Char FIFO is not empty N Chars are read by the receiver DMA engine The first character is interpreted as the logical address which is compared to the node address register If it does not match the complete packet is discarded up to and including the next EOP EEP Otherwise the next action taken depends on whether the node is configured with RMAP or not If RMAP is dis abled all packets are stored to the DMA channel and depending on the conditions mentioned in the previous section the packet will be received or not If the packet is received complete packet includ ing address and protocol ID but excluding EOP EEP is stored to the address indicated in the descrip tor otherwise the complete packet is discarded If RMAP is enabled the protocol ID and 3rd byte in the packet is first checked before any decis
615. the design Library dependencies Table 440 shows the libraries used when instantiating the core VHDL libraries Table 440 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER PCI Signals component PCI signals and component declaration 444 53 53 1 53 2 PHY Ethernet PHY simulation model Overview The Ethernet PHY simulation model is a model of an Ethernet PHY chip which is connected between the physical line and the MAC in Ethernet connections It receives a bitstream from the MAC and converts it into an analog signal which is driven on the line This model is loosely based on the Intel LXT971A chip It does not nearly implement all functionality provided by the real device but merely provides enough functions to make it possible to conduct simple simulations Operation The PHY simulation model was designed to make it possible to perform simple simulations on the EDCL unit also included in GRLIB The EDCL uses the Opencores Ethernet MAC for the Ethernet communication and the PHY model provides stimuli for the MAC receiver from a file and also stores output from the MAC in another file Figure 1 shows a block diagram of a typical connection Input from file f Output to file PHY MII Interface MAC Figure 220 Block diagram of the PHY simulation model connected to a MAC The PHY model provides th
616. the two register file DPRAMs the checkbits will be written to according to the fol lowing table Cache memory Each word in the cache tag or data memories is protected by four check bits An error during cache access will cause a cache line flush and a re excution of the failing instruction This will insure that the complete cache line tags and data is refilled from external memory For every detected error a counter in the cache control register is incremented The counters saturate at their maximum value 3 and should be reset by software after read out The cache memory check bits can be diagnostically 394 read by setting the PS bit in the cache control register and then perform a normal tag or data diagnos tic read 45 3 1 Cache Control Register 31 29 28 27 24 23 22 21 20 19 16 15 14 13121110987 6 543 2 1 0 ps TB Ds FD Fl FT 15 lp P ITE IDE DTE DDE DF IF DCS Ics Figure 175 Cache control register 28 Parity Select PS if set diagnostic read will return 4 check bits in the Isb bits otherwise tag or data word is returned 27 24 Test Bits TB if set check bits will be xored with test bits TB during diagnostic write 23 Data cache snoop enable DS if set will enable data cache snooping 22 Flush data cache FD If set will flush the instruction cache Always reads as zero 21 Flush Instruction cache FI If set will flush the instruction cache Always reads as zero
617. this register the sampling stops 0 means posttrig and depth 1 is pretrig Any value in between can be used 400 46 3 5 Sample frequency divider 31 16 15 0 000 0 divider value Figure 181 Sample freq divider register 31 16 Reserved 15 0 A sample is stored on every i th clock cycle where i is specified through this register This resets to 1 thus sampling occurs every cycle if not changed 46 3 6 Storage qualifier 31 ok i A 000 0 qualifier bit val Figure 182 Storage qualifier register 31 9 Reserved 8 1 Which bit to use as qualifier 0 Qualify storage if bit is 1 0 46 3 7 Trig control registers This memory area contains the registers that control when the trigger engine shall proceed to the next level 1 e the match counter and a one bit field that specifies 1f it should trig on equality or inequality There are trigl words where each word is used like in the figure below 31 7 6 0 000 0 match counter eq Figure 183 Trigger control register 31 7 Reserved 6 1 Match counter A counter is increased with one on each match on the current level and when it reaches the value stored in this register the trigger engine proceeds to the next level or if it is the last level it raises the trigged flag and starts the count of the trigger counter 0 Specifies if a match is that the pattern mask combination is equal or ineq
618. thout the need to re configure the address size and pointers No message reception is performed while the channel is not enabled 22 6 8 Interrupts During reception several interrupts can be generated e RxMiss Message filtered away for receive RxErrCntr Error counter incremented for receive RxSync Synchronization message received e R Successful reception of one message e RxFull Successful reception of all messages possible to store in buffer 22 7 22 8 147 RxIrq Successful reception of a predefined number of messages RxAHBErr AHB access error during reception OR Over run during reception OFF Bus off condition e PASS Error passive condition The Rx RxFull and RxIrq interrupts are only generated as the result of a successful message recep tion after the CanRxWR WRITE pointer has been incremented The OR interrupt is generated when a message is received while a previously received message is still being stored A full circular buffer will lead to OR interrupts for any subsequently received messages Note that the last message stored which fills the circular buffer will not generate an OR interrupt The overrun is also reported with the CanSTAT OR bit which is cleared when reading the register The error behavior of the CAN core is according to the CAN standard which applies to the error counter buss off condition and error passive condition Global reset and enable When the CanCTRL RESET
619. ticast addresses can be assigned to the MAC This means that packets with type 0x8808 the only currently defined ctrl packets are discarded 34 2 3 Clocking GRETH has three clock domains The AHB clock Ethernet receiver clock and the Ethernet transmit ter clock The ethernet transmitter and receiver clocks are generated by the external ethernet PHY and are inputs to the core through the MII interface The three clock domains are unrelated to each other and all signals crossing the clock regions are fully synchronozed inside the core Both full duplex and half duplex operating modes are supported and both can be run in either 10 or 100 Mbit The minimum AHB clock for 10 Mbit operation is 2 5 MHz while 18 MHz is needed for 100 Mbit Using a lower AHB clock than specified will lead to excessive packet loss Tx DMA interface The transmitter DMA interface is used for transmitting data on an Ethernet network The transmission is done using descriptors located in memory 34 3 1 Setting up a descriptor A single descriptor is shown in figure 112 The number of bytes to be sent should be set in the length field and the address field should point to the data The address must be word aligned If the interrupt enable IE bit is set an interrupt will be generated when the packet has been sent this requires that the transmitter interrupt bit in the control register is also set The interrupt will be generated regard less of whether the packet was
620. ting or receiving data or processing a mode code The B1553RT core provides an AMBA interface with GRLIB plug amp play for the Actel Core1553BRT MIL STD 1553B Remote Terminal B1553RT implements two AMBA interfaces one AHB master interface for the memory interface and one APB slave interface for the control registers The Actel Core1553BRT core entity named RT1553B is configured to use the shared memory inter face Data is read and stored via DMA using the AHB master interface B1553R1 ias GR1553RT 1553 signals Actel Core1553BRT gt RT signals p MEM IF A y APB slave IF ERA I AHB master IH A A AMBA APB AMBA AHB Figure 44 B1553RT block diagram 114 20 2 20 3 AHB interface The Core1553BRT core operates on a 2048 16 bit memory buffer and therefore a 4 kilobyte memory area should be allocated The memory is accessed via the AMBA AHB bus The Core1553BRT uses only 11 address bits and the top 20 address bits of the 32 bit AHB address can be programmed in the AHB page address register The 11 bit address provided by the Core1553BRT core is left shifted one bit and forms the AHB address together with the AHB page address register Note that all pointers given to the Core1553BRT core need to be right shifted one bit because of this All AHB accesses are done as half word single transfers The endianness of the interface depends on the endian VHDL generic T
621. tion 44 5 5 Local scratch pad ram Local scratch pad ram can optionally be attached to both instruction and data cache controllers The scratch pad ram provides fast 0 waitstates ram memories for both instructions and data The ram can be between 1 512 kbyte and mapped on any 16 Mbyte block in the address space Accessed per formed to the scratch pad ram are not cached and will not appear on the AHB bus The scratch pads rams do not appear on the AHB bus and can only be read or written by the processor The instruction ram must be initialized by software through store instructions before it can be used The default address for the instruction ram is 0x8e000000 and for the data ram 0x8f 000000 See section 44 11 for additional configuration details Note local scratch pad ram can only be enabled when the MMU is disabled 44 5 6 Cache Control Register The operation of the instruction and data caches is controlled through a common Cache Control Reg ister CCR figure 171 Each cache can be in one of three modes disabled enabled and frozen If disabled no cache operation is performed and load and store requests are passed directly to the mem ory controller If enabled the cache operates as described above In the frozen state the cache is 381 accessed and kept in sync with the main memory as if it was enabled but no new lines are allocated on read misses 31 23 22 21 16 15 14 6 5 432 1 0 ps FD FI IB IP DP DF IF pcs ICS
622. tion Depending on memory and cache activity the write cycle may not occur until several clock cycles after the store instructions has completed If a write error occurs the currently executing instruction will take trap 0x2b 44 5 379 Note the 0x2b trap handler should flush the data cache since a write hit would update the cache while the memory would keep the old value due the write error 44 4 3 Data cache tag A data cache tag entry consists of several fields as shown in figure 170 31 10 9 8 7 0 ATAG LRR LOCK VALID Figure 170 Data cache tag layout Field Definitions 31 10 Address Tag ATAG Contains the address of the data held in the cache line 9 LRR Used by LRR algorithm to store replacement history 0 if LRR is not used 8 LOCK Locks a cache line when set 0 if instruction cache locking was not enabled in the configuration 3 0 Valid V When set the corresponding sub block of the cache line contains valid data These bits is set when a sub block is filled due to a successful cache miss a cache fill which results in a memory error will leave the valid bit unset V O corresponds to address 0 in the cache line V 1 to address 1 V 2 to address 2 and V 3 to address 3 NOTE only the necessary bits will be implemented in the cache tag depending on the cache configu ration As an example a 2 kbyte cache with 32 bytes per line would only have eight valid bits and 21
623. tive and positive edges Thus the bitrate is twice as high as the clock rate The synchronization limits the Tx and Rx clocks to be at most 4 and 2 times faster than the system clock But it might not be possible to achieve such high clock rates for the Tx and Rx clocks for all technologies The asynchronous reset to the receiver clock domain has to have a maximum delay of one receiver clock cycle to ensure correct operation This is needed because the receiver uses has a completely 42 9 335 asynchronous reset To make sure that nothing bad happens the is a synchronous reset guard which prevents any signals from being assigned before all registers have their reset signals released 42 8 4 Fault tolerance The GRSPW core can optionally be implemented with fault tolerance against SEU errors in the FIFO memories The fault tolerance is enabled through the ft VHDL generic Possible options are byte par ity protection ft 1 or TMR registers ft 2 Note the GPL version of GRLIB does not include fault tolerance and the GRSPW core will not work unless the ff VHDL generic is 0 42 8 5 Synthesis Since the receiver and transmitter may run on very high frequency clocks their clock signals have been coupled through a clock buffer with a technology wrapper This clock buffer will utilize a low skew net available in the selected technology for the clock The clock buffer will also enable most synthesis tools to recognize the clocks and it is t
624. tive low 1 0 1 0 active high 47 16 Signal descriptions Table 418 shows the interface signals of the core VHDL ports Table 418 Signal descriptions Signal name Field Type Function Active CLK N A Input Clock RST N A Input Reset Low Table 418 Signal descriptions 417 Signal name Field Type Function Active MEMI DATA 31 0 Input Memory data High BRDYN Input Bus ready strobe Low BEXCN Input Bus exception Low WRNI 3 0 Input SRAM write enable feedback signal Low BWIDTH 1 0 Input Sets the reset value of the PROM data bus width High field in the MCFG1 register SD 31 0 Input SDRAM separate data bus High MEMO ADDRESS 27 0 Output Memory address High DATA 31 0 Output Memory data SDDATA 63 0 Output Sdram memory data RAMSN 4 0 Output SRAM chip select Low RAMOEN 4 0 Output SRAM output enable Low IOSN Output Local I O select Low ROMSN 1 0 Output PROM chip select Low OEN Output Output enable Low WRITEN Output Write strobe Low WRNI 3 0 Output SRAM write enable Low WRNI 0 corresponds to DATA 31 24 WRN 1 corresponds to DATA 23 16 WRN 2 corresponds to DATA 15 8 WRNI 3 corresponds to DATA 7 0 MBEN 3 0 Output Byte enable Low MBEN 0 corresponds to DATA 31 24 MBEN 1 corresponds to DATA 23 16 MBEN 2 corresponds to DATA 15 8 MBEN 3 corresponds to DATA 7 0 BDRIVE 3 0 Output Drive byte lanes on
625. to an individual descriptor The first descriptor should be located at the 34 5 34 6 275 base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at the next descriptor The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached the descriptor at address offset Ox3F8 has been used The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register It should never be touched when reception is active The final step to activate reception is to set the receiver enable bit in the control register This will make the GRETH read the first descriptor and wait for an incoming packet 34 4 3 Descriptor handling after reception The GRETH indicates a completed reception by clearing the descriptor enable bit The other control bits WR IE are also cleared The number of received bytes is shown in the length field The parts of the Ethernet frame stored are the destination address source address type and data fields Bits 17 14 in the first descriptor word are status bits indicating different receive errors All four bits are zero after a reception without errors The status bits are described in figure 113 Packets arriving that are smaller than the minimum Ethernet size of 64 B are not consi
626. to provide remote access via a SpaceWire network to memory mapped resources on a Space Wire node It has been assigned protocol ID 0x01 It provides three oper ations write read and read modify write These operations are posted operations which means that a source does not wait for an acknowledge or reply It also implies that any number of operations can be outstanding at any time and that no timeout mechanism is implemented in the protocol Time outs must be implemented in the user application which sends the commands Data payloads of up to 16 Mb 1 is supported in the protocol A destination can be requested to send replies and to verify data before executing an operation A complete description of the protocol is found in the RMAP standard 42 6 2 Implementation The GRSPW includes an handler for RMAP commands which processes all incoming packets with protocol ID 0x01 and type field bit 7 and 6 of the 3rd byte in the packet equal to 01b When such a packet is detected it is not stored to the DMA channel instead it is passed to the RMAP receiver The GRSPW implements all three commands defined in the standard with some restrictions The implementation is based on draft C of the RMAP standard Support is only provided for 32 bit big endian systems This means that the first byte received is the msb in a word The command handler will not receive RMAP packets using the extended protocol ID which are always dumped to the DMA channel The RMA
627. tor others gt ahbs_none signal ahbmi ahb_mst_in type signal ahbmo ahb_mst_out_vector others gt ahbm_none signal clkm rstn rstraw std_ulogic signal cgi clkgen_in_type signal cgo clkgen_out_type signal stati ahbstat_in_type begin clock and reset cgi pllctrl lt 00 cgi pllrst lt rstraw cgi pllref clk_pad clkpad port map clk clkm rst0 rstgen gt reset generator port map resetn clkm 1 rstn rstraw AHB controller ahb0 ahbctrl AHB arbiter multiplexer lt 0 generic map rrobin gt 1 ioaddr gt 16 fff devid gt 1642014 port map rstn clkm ahbmi ahbmo ahbsi ahbso Memory controller sr0 ftsrctrl18 generic map hindex gt 0 pindex gt 0 port map rstn clkm ahbsi ahbso 0 apbi apbo 0 brdyn_pad inpad port map brdyn memi brdyn bexcn_pad inpad port map bexcn memi bexcn addr_pad outpadv generic map width gt 28 port map address memo address 27 downto 0 rams_pad outpadv generic map width gt 4 port map ramsn memo ramsn 3 downto 0 oen_pad outpad port map oen memo oen rwen_pad outpadv generic map width gt 4 port map rwen memo wrn roen_pad outpadv generic map width gt 4 port map ramoen memo ramoen 3 downto 0 wri_pad outpad edacen gt 1 memi memo 247 248 port map writen memo writen read_pad outpad port map read memo read i
628. tor 0 to NCPU 1 signal irgo irq_out_vector 0 to NCPU 1 LEON3 signals signal leon3i 13_in_vector 0 to NCPU 1 signal leon30 13_out_vector 0 to NCPU 1 begin 4 LEON3 processors are instantiated here cpu for i in 0 to NCPU 1 generate u0 leon3s generic map hindex gt i port map clk rstn ahbmi ahbmo i ahbsi irgi i irgo i dbgi i dbgo i end generate MP IRQ controller irgctrl10 irqmp generic map pindex gt 2 paddr gt 2 ncpu gt NCPU port map rstn clk apbi apbo 2 irqi irgo end 44 44 1 369 LEON High performance SPARC V8 32 bit Processor Overview LEON3 is a 32 bit processor core conforming to the IEEE 1754 SPARC V8 architecture It is designed for embedded applications combining high performance with low complexity and low power consumption The LEON3 core has the following main features 7 stage pipeline with Harvard architecture sepa rate instruction and data caches hardware multiplier and divider on chip debug support and multi processor extensions 3 Port Register File IEEE 754 FPU Trace Buffer 7 Stage Integer pipeline Co Processor Debug port Debug support unit HW MUL DIV Interrupt port gt gt Interrupt controller Local IRAM l Cache D Cache Local DRAM ITLB SRMMU DTLB AHB I F i AMBA AHB Master 32 bit Figure 165 LEON3 processor core block diagram
629. translated to AHB accesses using PAGE map register dmaabits 1 4 These bits are read only and always read as 00 0 This field can be used to determine devices memory requirement by writing value of all ones to this register and reading the value back The device will return zeroes in unimplemented bits positions effectively defining memory area requested 3 Prefetchable Not supported Always reads as 0 2 1 Base Address Type Mapping can be done anywhere in the 32 bit memory space Reads always as 00 0 Memory Space Indicator Register maps in Memory space Read always as 0 PCI Target Map Registers PAGEO and PAGE registers map PCI access to AHB address space Table 428 PCI Target Map Registers Address Space Address Register PCI Upper half of PCI address space defined by BARO register PAGEO AMBA APB APB base address 0x10 PAGE 31 abits 1 abits 2 1 0 AHB MAP 00 0 BTEN Figure 208 PAGEO register 432 50 6 31 abits 1 AHB Map Address Maps PCI accesses to PCI BARO address space to AHB address space AHB address is formed by concatenating AHB MAP with LSB of the PCI address abits 2 1 Reserved Reads always as 00 0 0 BTEN Byte twisting enabled if 1 Reset value 1 May only be altered when bus mastering is disabled 31 dmaabits dmaabits 1 0 AHB MAP 00 0 Figure 209 PAGE register 31 dmaabits AH
630. transmissions can always be inter rupted If the master transmits for a long period without pauses the slave can timeout This has not yet been seen in normal operation but must be considered The MDIO interface is not arbitrated and one MAC has constant access to it The mdiomaster generic selects which of the MACs has access 36 3 36 4 36 5 Registers The core does not implement any user programmable registers Configuration options Table 313 shows the configuration options of the core VHDL generics Table 313 Configuration options Generic Function Allowed range Default fullduplex Select full duplex mode arbitration 0 1 0 mdiomaster Select which of the MACs that has access to the MDIO interface 0 1 0 0 selects the MAC connected to dethi detho and 1 selects the MAC connected to methi metho Signal description Table 314 shows the interface signals of the core VHDL ports Table 314 Signal descriptions Signal name Field Type Function Active RST N A Input Reset Low ETHI TX_CLK Input Transmit clock RX_CLK Input Receive clock RXD 3 0 Input Receive data RX_DV Input Receive data valid High RX_ER Input Receive data error High RX_COL Input Collision detect High RX_CRS Input Carrier sense High MDIO_I Input MDIO input data ETHO RESET Output Ethernet Reset High TXD 3 0 Output Transmit data TX_EN Output Transmit enable Hi
631. trol register and set ting the read bit This caused the Busy bit to be set and the operation is finished when the Busy bit is cleared If the operation was successful the Linkfail bit is zero and the data field contains the read data An unsuccessful operation is indicated by the Linkfail bit being set The data field is undefined in this case A write operation is started by writing the 16 bit data PHY address and register address to the MDIO Control register and setting the write bit The operation is finished when the busy bit is cleared and it was successful if the Linkfail bit is zero Ethernet Debug Communication Link EDCL The EDCL provides access to an on chip AHB bus through Ethernet It uses the UDP IP and ARP protocols together with a custom application layer protocol The application layer protocol uses an ARQ algorithm to provide reliable AHB instruction transfers Through this link a read or write trans 276 fer can be generated to any address on the AHB bus The EDCL is optional and must be enabled with a generic 34 6 1 Operation The EDCL receives packets in parallel with the MAC receive DMA channel It uses a separate MAC address which is used for distinguishing EDCL packets from packets destined to the MAC DMA channel The EDCL also has an IP address which is set through generics Since ARP packets use the Ethernet broadcast address the IP address must be used in this case to distinguish between EDCL ARP packets and t
632. ts of an APB interface for configuration and control and an AHB master interface which handles the dataflow The dataflow is handled through DMA channels There is one DMA engine for the transmitter and one for the receiver Both share the same AHB master interface The ethernet interface supports both the MII and RMII interfaces which should be con nected to an external PHY The GRETH also provides access to the MII Management interface which is used to configure the PHY Optional hardware support for the Ethernet Debug Communication Link EDCL protocol is also pro vided This is an UDP IP based protocol used for remote debugging APB AHB Ethernet MAC gt MDIO_OE gt MDIO_O l ___ Registers A MDIO e MDIO I A gt MDC gt TX EN Transmitter l p gt TX_ER DD lp DMA Engine FIFO Tranemittar gt TXD 3 0 HE 4 TX_CLK al EDOL RX CRS i AD EE lt gt AHB Master Transmitter lt RX_COL Interface EDCL t gt Receiver 4 RX_DV a lt RX_ER 5 gt Receiver Receiver 4 RXD 3 0 Lp DMA Engine le FIFO RX_CLK Figure 111 Block diagram of the internal structure of the GRETH Operation 34 2 1 System overview The GRETH consists 3 functional units The DMA channels MDIO interface and the optional Ether net Debug Communication Link EDCL
633. ual compared to the traced signals 46 3 8 Pattern mask configuration In these registers the pattern and mask for each trig level is configured The pattern and mask can con tain up to 8 words 256 bits each so a number of writes can be necessary to specify just one pattern They are stored with the LSB at the lowest address The pattern of the first trig level is at 0x6000 and the mask is located 8 words later at 0x6020 Then the next trig levels starts at address 0x6040 and so on 46 3 9 Trace data It is placed in the upper half of the allocated APB address range If the configuration needs more than the allocated 32 kB of the APB range the page register is used to page into the trace buffer Each stored word is dbits wide but 8 words of the memory range is always allocated so the entries in the trace buffer are found at multiples of 0x20 i e 0x8000 0x8020 and so on 401 46 4 Graphical interface 46 5 46 6 The logic analyzer is normally controlled by the LOGAN debug driver in GRMON It is also possible to control the LOGAN operation using a graphical user interface GUI written in Tcl Tk The GUI is provided with GRMON refer to the GRMON manual for more details Config for trig level Biel Update status Width 64 iprdata 32 bits XX Pattem Depth 4096 mes ts ox100 Trig 2 8 bits Mask Usereg yes Oxf Qualifier yes Armed no Trigged no 7 Trig count z048 1
634. uc tions should be used while LDUB STB should be used with an 8 bit bus SDRAM access 47 8 1 General Synchronous dynamic RAM SDRAM access is supported to two banks of PC100 PC133 compati ble devices This is implemented by a special version of the SDCTRL SDRAM controller core from Gaisler Research which is optionally instantiated as a sub block The SDRAM controller supports 64M 256M and 512M devices with 8 12 column address bits and up to 13 row address bits The size of the two banks can be programmed in binary steps between 4 Mbyte and 512 Mbyte The oper ation of the SDRAM controller is controlled through MCFG2 and MCFG3 see below Both 32 and 64 bit data bus width is supported allowing the interface of 64 bit DIMM modules The memory con troller can be configured to use either a shared or separate bus connecting the controller and SDRAM devices 47 8 2 Address mapping The two SDRAM chip select signals are decoded SDRAM area is mapped into the upper half of the RAM area defined by BAR2 register When the SDRAM enable bit is set in MCFG2 the controller is enabled and mapped into upper half of the RAM area as long as the SRAM disable bit is not set If the SRAM disable bit is set all access to SRAM is disabled and the SDRAM banks are mapped into the lower half of the RAM area 47 8 3 Initialisation When the SDRAM controller is enabled it automatically performs the SDRAM initialisation sequence of PRECHARGE 2x AUTO REFRE
635. uction 313 After the trap is taken the qne bit of the FSR is set and remains set until the FQ is emptied STDFQ instruction reads a double word from the floating point deferred queue the first word is the address of the instruction and the second word is the instruction code 314 41 41 1 41 2 41 3 GRGPIO General Purpose I O Port Overview The general purpose input output port core is a scalable and provides optional interrupt support The port width can be set to 2 32 bits through the nbits VHDL generic 1 e nbits 16 Interrupt genera tion and shaping is only available for those I O lines where the corresponding bit in the mask VHDL generic has been set to 1 Each bit in the general purpose input output port can be individually set to input or output and can optionally generate an interrupt For interrupt generation the input can be filtered for polarity and level edge detection The figure 136 shows a diagram for one I O line Direction D Q Output Value p Q O RAD Input Value Q D Q D GPIOO VAL Figure 136 General Purpose I O Port diagram Operation The I O ports are implemented as bi directional buffers with programmable output enable The input from each buffer is synchronized by two flip flops in series to remove potential meta stability The synchronized values can be read out from the I O port data register They are also available on th
636. uld therefore be connected directly the top level ports without any logic in between 23 2 10 Registers The DDRSPA core implements two control registers The registers are mapped into AHB I O address space defined by the AHB BAR of the core Table 177 DDR controller registers Address offset AHB I O BAR1 Register 0x00 SDRAM control register 0x04 SDRAM configuration register read only Table 178 SDRAM control register SDCTRL 31 30 29 27 26 25 23 22 21 20 18 17 16 15 14 0 Refresh tRP tRFC tCD SDRAM SRAM SDRAM _ PR IN CE SDRAM refresh load value bank size col size commnad 31 SDRAM refresh If set the SDRAM refresh will be enabled 30 SDRAM tRP timing tRP will be equal to 2 or 3 system clocks 0 1 29 27 SDRAM tRFC timing tRFC will be equal to 3 field value system clocks 26 SDRAM tRCD delay Sets tRCD to 2 field value clocks 25 23 SDRAM banks size Defines the decoded memory size for each SDRAM chip select 000 8 Mbyte 001 16 Mbyte 010 32 Mbyte 111 1024 Mbyte 164 Table 1758 SDRAM control register SDCTRL 22 21 SDRAM column size 00 512 01 1024 10 2048 11 4096 20 18 SDRAM command Writing a non zero value will generate an SDRAM command 010 PRE CHARGE 100 AUTO REFRESH 110 LOAD COMMAND REGISTER 111 LOAD EXTENDED COMMAND REGISTER The
637. uld be set and after this is done the descriptor should not be touched until the enable bit has been cleared by the GRETH 34 3 2 Starting transmissions Enabling a descriptor is not enough to start a transmission A pointer to the memory area holding the descriptors must first be set in the GRETH This is done in the transmitter descriptor pointer register The address must be aligned to a 1 kB boundary Bits 31 to 10 hold the base address of descriptor area while bits 9 to 3 form a pointer to an individual descriptor The first descriptor should be located at the base address and when it has been used by the GRETH the pointer field is incremented by 8 to point at the next descriptor The pointer will automatically wrap back to zero when the next 1 kB boundary has been reached the descriptor at address offset Ox3F8 has been used The WR bit in the descriptors can be set to make the pointer wrap back to zero before the 1 kB boundary The pointer field has also been made writable for maximum flexibility but care should be taken when writing to the descriptor pointer register It should never be touched when a transmission is active The final step to activate the transmission is to set the transmit enable bit in the control register This tells the GRETH that there are more active descriptors in the descriptor table This bit should always be set when new descriptors are enabled even if transmissions are already active The descriptors must always be
638. ulogic memory bus address out std_logic_vector 27 downto 0 memory bus data inout std_logic_vector 31 downto 0 ramsn Out std_logic_vector 4 downto 0 ramoen out std_logic_vector 4 downto 0 rwen inout std_logic_vector 3 downto 0 romsn out std_logic_vector 1 downto 0 iosn out std_logic oen out std_logic read out std_logic writen inout std_logic brdyn in std_logic bexcn in std_logic sdram 1 f sdcke out std_logic_vector 1 downto 0 clk en sdcsn out std_logic_vector 1 downto 0 chip sel sdwen out std_logic write en sdrasn out std_logic row addr stb sdcasn out std_logic col addr stb sddqm out std_logic_vector 7 downto 0 data i o mask sdclk out std_logic sdram clk output sa out std_logic_vector 14 downto 0 optional sdram address sd inout std_logic_vector 63 downto 0 optional sdram data cb inout std_logic_vector 7 downto 0 checkbits i end architecture rtl of mctrl_ex is AMBA bus AHB and APB signal apbi apb_slv_in_type signal apbo apb_slv_out_vector others gt apb_none signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ahbmi ahb_mst_in_type signal ahbmo ahb_mst_out_vector others gt ahbm_none signals used to connect memory controller and memory bus signal memi memory_in_type signal memo memory_out_type
639. use of MEMI BRDYN can be enabled separately for the I O and RAM areas datai data2 data2 lead out clk AANS AF NA AA ATST AS VIO IORI OT address a N a A A a oen Ee Me al a E e e A data woe vie a 5 Figure 196 READ cycle with one extra data2 cycle added with BRDYN synchronous sampling Lead out cycle is only applicable for I O accesses datai data2 data2 data2 lead out ws brdyn clk AANI NANA AA NI NE ENT NAIA N address A NA le O A a a oen eae O dr a CA data brdyn Po le whee ee irs ie ei Figure 197 Read cycle with one waitstate configured and one BRDYN generated waitstate synchronous sampling 47 11 Access errors An access error can be signalled by asserting the MEMI BEXCN signal which is sampled together with the data If the usage of MEMI BEXCN is enabled in memory configuration register 1 an error response will be generated on the internal AMBA bus MEMI BEXCN can be enabled or disabled through memory configuration register 1 and is active for all areas PROM I O an RAM 47 12 47 13 413 datal data2 lead out address a NS O e ee oen O O A T T T eo data bexcn AAA Iai e a a a Figure 198 Read cycle with BEXCN lead in data2 lead out address dde ie N LA yeh oo A S rwen PH ci A 7 0 E ee gl a a bexcn O I ie ie Figure 199 Write cycle with BEXCN Chip select iosn is not asserted in lead in cycle
640. used CB 7 0 Output Not used PSEL Output Not used CE Output Single error detected High AHBSI Input AHB slave input signals AHBSO Output AHB slave output signals 246 30 8 30 9 30 10 Library dependencies Table 227 shows libraries used when instantiating the core VHDL libraries Table 227 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AHB signal definitions GAISLER MEMCTRL Signals component Memory bus signals definitions component dec laration Component declaration The core has the following component declaration component ftsrctrl8 is generic hindex ramaddr rammask ioaddr iomask ramws iows srbanks banksz pindex paddr pmask edacen errcnt entbits wsreg oepol i port rst clk ahbsi ahbso apbi apbo Ser sro i end component Instantiation This example shows how the core can be instantiated integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer integer tn Stas in std_ in ahb_ out ahb_ in apb_ out apb_ 0 1644004 16 ff0 1642004 16 ff0 0 2 range 1 to 8 range 0 to 15 z 0 0 Lo fft range 0 to 1 range 0 to 1 range 1 to 8 0 pS O ulogic ulogic slv_in_type slv_out_type slv_in_type slv_out_type in memory_in_type out memory_out_type Th
641. used for the random value Do not change unless you know what your doing slot_time Number of ethernet clock cycles used for one slot time Default 1 255 128 value as required by the ethernet standard Do not change unless you know what you are doing mdcscaler Sets the divisor value use to generate the mdio clock mdc The 0 255 25 mdc frequency will be clk 2 mdcscaler 1 nsync Number of synchronization registers used 1 2 2 edcl Enable EDCL 0 1 edclbufsz Select the size of the EDCL buffer in kB 1 64 1 burstlength Sets the maximum burstlength used during DMA 4 128 32 macaddrh Sets the upper 24 bits of the EDCL MAC address 0 16 FFFFFF 16 00005E macaddrl Sets the lower 24 bits of the EDCL MAC address 0 16 FFFFFF 16 000000 ipaddrh Sets the upper 16 bits of the EDCL IP address reset value 0 16 FFFFH 16 COA8 ipaddrl Sets the lower 16 bits of the EDCL IP address reset value 0 16 FFFF 16 0035 phyrstadr Sets the reset value of the PHY address field in the MDIO regis 0 32 0 ter When set to 32 the address is taken from the ethi phyrstaddr signal sim Set to 1 for simulations and 0 for synthesis 1 selects a faster mdc 0 1 0 clock to speed up simulations Not all addresses are allowed and most NICs and protocol implementations will discard frames with illegal addresses silently Consult network literature if unsure about the addresses 296 35 12 Signal descriptions Table 311 shows the i
642. ut value Table 324 I O port output register 31 16 16 1 0 000 0 I O port output value 16 1 0 T O port output value Table 325 I O port direction register 31 16 16 1 0 000 0 1 0 port direction value 16 1 0 T O port direction value O output disabled 1 output enabled Table 326 Interrupt mask register 31 16 16 1 0 000 0 Interrupt mask 16 1 0 Interrupt mask O interrupt masked 1 intrrupt enabled Table 327 Interrupt polarity register 31 16 16 1 0 000 0 Interrupt polarity 16 1 0 Interrupt polarity O low falling 1 high rising Table 328 Interrupt edge register 31 16 16 1 0 000 0 Interrupt edge 16 1 0 Interrupt edge O level 1 edge 41 4 Vendor and device identifiers The core has vendor identifier 0x01 Gaisler Research and device identifier 0xO1A For description of vendor and device identifiers see GRLIB IP Library User s Manual 316 41 5 41 6 41 7 41 8 Configuration options Table 329 shows the configuration options of the core VHDL generics Table 329 Configuration options Generic Function Allowed range Default pindex Selects which APB select signal PSEL will be used to 0 to NAPBMAX 1 0 access the GPIO unit paddr The 12 bit MSB APB address 0 to 16 FFFH 0 pmask The APB address mask 0 to 16 FFF 16 FFFH n
643. uts end 254 32 32 1 32 2 32 3 GRAES Advanced Encryption Standard Overview The Advanced Encryption Standard AES is a symmetric encryption algorithm for high throughput application like audio or video streams The GRAES core implements the AES 128 algorithm sup porting the Electronic Codebook ECB method The AES 128 algorithm is specified in the Advanced Encryption Standard AES document Federal Information Processing Standards FIPS Publication 197 The document is established by the National Institute of Standards and Technology NIST The core provides the following internal AMBA AHB slave interface with sideband signals as per GRLIB including e interrupt bus e configuration information e diagnostic information The core can be partition in the following hierarchical elements e Advanced Encryption Standard AES core e AMBA AHB slave e GRLIB plug amp play wrapper Note that the core can also be used without the GRLIB plug amp play information Operation The input and output for the AES algorithm each consist of sequences of 128 bits digits with values of 0 or 1 These sequences will sometimes be referred to as blocks and the number of bits they con tain will be referred to as their length The cipher key for the AES 128 algorithm is a sequence of 128 bits can also be 192 or 256 bits for other algorithms To transfer a 128 bit key or data block four write operations are necessar
644. ve accesses a lead out cycle is added after a 190 27 5 read cycle to prevent bus contention due to slow turn off time of memories Figure 73 shows the basic read cycle waveform zero waitstate Waitstates are added in the same way as for PROM in figure 68 datal data2 lead out datai data2 lead out PRES C a A A 42 ramsn ALVAL S TT T ramoen cat T cb CB1 CB2 Y Figure 73 Sram non consecutive read cyclecs For read accesses to RAMSN 4 0 a separate output enable signal RAMOEN n is provided for each RAM bank and only asserted when that bank is selected A write access is similar to the read access but takes a minimum of three cycles Waitstates are added in the same way as for PROM Each byte lane has an individual write strobe to allow efficient byte and half word writes If the mem ory uses a common write strobe for the full 16 or 32 bit data the read modify write bit MCFG2 should be set to enable read modify write cycles for sub word writes lead in data lead out address ramsn ME A O A O rwen A hea oi he data cb CBI Figure 74 Sram write cycle 0 waitstates 8 bit and 16 bit PROM and SRAM access To support applications with low memory and performance requirements efficiently the SRAM and PROM areas can be individually configured for 8 or 16 bit operation by programming the ROM and RAM width fields in the memory configuration reg
645. ve interface user defined register 1 on the low speed bus Isb_hsindex AHB slave index on the low speed bus 0 to NAHBMAX 1 1sb_hmindex AHB master index on the low speed bus 0 to NAHBMAX 1 1sb_rburst Size of the prefetch buffer for read transfers initiated on 16 32 16 the low speed bus and crossing the bridge lsb_wburst Size of the write buffer for write transfers initiated on the 16 32 16 low speed bus and crossing the bridge Isb_bankO Address area 0 mapped on the low speed bus and 0 1073741823 0 decoded by the bridge s slave interface on the high speed bus Appears as memory address register BARO on the bridge s high speed bus slave interface The generic has the same bit layout as bank address registers with bits 19 18 suppressed use functions ahb2ahb_membar and ahb2ahb_iobar in gaisler misc package to generate this generic Isb_bank1 Address area 1 mapped on the low speed bus 0 1073741823 0 Isb_bank2 Address area 2 mapped on the low speed bus 0 1073741823 0 Isb_bank3 Address area 3 mapped on the low speed bus 0 1073741823 0 lsb_ioarea Low speed bus configuration area will appear in the 0 16 FFFH 0 28 3 6 3 7 Signal descriptions Table 20 shows the interface signals of the core VHDL ports Table 20 Signal descriptions Signal name Type Function Active RST Input Reset Low HSB_HCLK Input High speed AHB clock LSB_HCLK Input Low speed A
646. ver looks for a high to low transition of a start bit on the receiver serial data input pin If a transition is detected the state of the serial input is sampled a half bit clocks later If the serial input is sampled high the start bit is invalid and the search for a valid start bit continues If the serial input is still low a valid start bit is assumed and the receiver continues to sample the serial input at one bit time intervals at the theoretical centre of the bit until the proper number of data bits and the parity bit have been assembled and one stop bit has been detected The serial input is shifted through an 8 bit shift register where all bits have to have the same value before the new value is taken into account effectively forming a low pass filter with a cut off frequency of 1 8 system clock The receiver also has a configurable FIFO which is identical to the one in the transmitter As men tioned in the transmitter part both the holding register and FIFO will be referred to as FIFO During reception the least significant bit is received first The data is then transferred to the receiver FIFO and the data ready DR bit is set in the UART status register as soon as the FIFO contains at least one data frame The parity framing and overrun error bits are set at the received byte boundary at the same time as the receiver ready bit is set The data frame is not stored in the FIFO if an error is detected Also the new error status bits are
647. we Output Connected to Vcc for True IDE mode see GRLIB IP Library User s Manual Library dependencies Table 96 shows libraries used when instantiating the core VHDL libraries Table 96 Library dependencies Library Package Imported unit s Description GRLIB AMBA Signals AMBA signal definitions GAISLER ATA Signals component ATACTRL component declarations ATA signals Instantiation This example shows how the can be instantiated library ieee use ieee std_logic_1164 all library grlib use grlib amba all use grlib stdlib all use grlib devices all library techmap use techmap gencomp all library gaisler use gaisler ata all use work config all entity atactrl_ex is port rstn in std_ulogic clkm in std_ulogic ata_rst 2 out std logic ata_data inout std_logic_vector 15 downto 0 ata_da out std_logic_vector 2 downto 0 ata_cs0 out std_logic ata_csl out std_logic ata_dior out std_logic ata_diow out std_logic ata_iordy in std_logic ata_intrq in std_logic ata_dmack out std_logic i end architecture rtl of atactrl_ex is signal ahbsi ahb_slv_in_type signal ahbso ahb_slv_out_vector others gt ahbs_none signal ata ata_type begin AMBA Components are instantiated here atacO atactrl generic map hindex gt 5 haddr gt 16 A00 hmask gt 16 fff pirg gt 10 TWIDTH gt 8
648. when the FP operation is completed This value shall be incremented by 1 with wrap around for every started FP operation OPERAND1 63 0 FP operation operands are provided on these one or both of these inputs All 64 bits are used OPERAND2 63 0 for IEEE 754 double precision floating point numbers bits 63 32 are used for IEEE 754 single precision floating point numbers and 32 bit integers ROUND 1 0 I Rounding mode 00 rounding to nearest 01 round to zero 10 round to inf 11 round to inf FLUSH I Flush FP operation with FLUSHID FLUSHID 5 0 I Id of the FP operation to be flushed READY O The result of a FP operation will be available at the end of the next clock cycle ALLOW 2 0 O Indicates allowed FP operations during the next clock cycle ALLOW 0 FDIVS FDIVD FSQRTS and FSQRTD allowed ALLOWT 1 FMULS FMULD FSMULD allowed ALLOW 2 all other FP operations allowed RESID 5 0 O Id of the FP operation whose result appears at the end of the next clock cycle RESULT 63 0 O Result of an FP operation If the result is double precision floating point number all 64 bits are used otherwise single precision or integer result appears on RESULT 63 32 EXCEPT 5 0 O Floating point exceptions generated by an FP operation EXC 5 Unfinished FP operation Generated by an arithmetic or conversion operation with denormalized input s EXC 4 Invalid exception EXC 3 Overflow EXC 2 Und
649. xecution of the interrupt handler will not evict any cache lines and when control is returned to the interrupted task the cache state is identical to what it was before the interrupt If a cache has been frozen by an interrupt it can only be enabled again by enabling it in the CCR This is typically done at the end of the interrupt handler before control is returned to the interrupted task 44 5 7 Cache configuration registers The configuration of the two caches if defined in two registers the instruction and data configuration registers These registers are read only and indicate the size and configuration of the caches 31 3029 2827 26 25 24 23 20 19 18 16 15 12 11 4 3 0 CL REPL SN SETS SSIZE LR LSIZE LRSIZE LRSTART M Figure 172 Cache configuration register 31 Cache locking CL Set if cache locking is implemented 29 28 Cache replacement policy REPL 00 no replacement policy direct mapped cache 01 least recently used LRU 10 least recently replaced LRR 11 random 27 Cache snooping SN Set if snooping is implemented 26 24 Cache associativity SETS Number of sets in the cache 000 direct mapped 001 2 way associative 010 3 way associative 011 4 way associative 23 20 Set size SSIZE Indicates the size Kbytes of each cache set Size 2SIZE 19 Local ram LR Set if local scratch pad ram is implemented 18 16 Line size LSIZE Indicated the s
650. y since the bus interface is 32 bit wide After supplying a key will be input command to the control register the key is input via four registers After supplying a data will be input command to the control register the input data is written via four registers After the last input data register is written the encryption or decryption is started The progress can be observed via the debug register When the operation is completed an interrupt is generated The output data is then read out via four registers Note that the above sequence must be respected It is not required to write a new key between each data input There is no command needed for reading out the result The implementation requires around 89 clock cycles for a 128 bit data block in encryption direction and around 90 clock cycles for decryption direction For decryption an initial key calculation is required This takes around 10 additional clock cycles per every new key Typically large amounts of data are decrypted and also encrypted with the same key The key initialization for the decryption round does not influence the throughput Background The Federal Information Processing Standards FIPS Publication Series of the National Institute of Standards and Technology NIST is the official series of publications relating to standards and guide lines adopted and promulgated under the provisions of the Information Technology Management Reform Act 32 4 32 5 32
651. y using a 32 7 BCH code Some of the optional features available are single error counter diag nostic reads and writes and autoscrubbing automatic correction of single errors during reads Con figuration is pereformed via a configuration register Figure 64 shows a block diagram of the internals of the memory AHB Bus AHB Slave Interface ds A A AHB APB Bridge data Mux 4 error Configuration Register I Encoding Mux Config bits TCB A A A l r E APB Bus l l l l Decoding l A A Mux 4 4 y y data cb Syncram Figure 64 Block diagram Operation The on chip fault tolerant memory is accessed through an AMBA AHB slave interface The memory address range is configurable with VHDL generics As for the standard AHB RAM the memory technology and size is configurable through the tech and kbytes VHDL generics The mini mum size is 1 kb and the maximum is technology dependent but the values can only be increased in binary steps Run time configuration is done by writing to a configuration register accessed through an AMBA APB interface The address of the interface and the available options are configured with VHDL generics The EDAC functionality can be completely removed by setting the edacen VHDL generic to zero du

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