Cyclone V GX FPGA Development Kit User Guide
Contents
1. A 2 Programming Flash Memory Using the Nios 2 A 3 Restoring the Flash Device to the Factory Settings 4 Restoring the MAX V CPLD to the Factory Settings eee A 5 Additional Information Document Revision History HR ER Ye Y eR e Rd ode on Info 1 How to Contact Altera ii bee eee er RE RE ER ER e e e cR e Info 1 Typographic Conventions duce eee RE e CRAT EUR SHEER e as ewe ee Cer need Info 1 Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide N DTE SYN 1 About This Kit Kit Features The Altera Cyclone V GX FPGA Development Kit is a complete design environment that includes both the hardware and software you need to develop Cyclone V GX FPGA designs This section briefly describes the Cyclone V GX FPGA Development Kit contents For a complete list of this kit s contents and capabilities refer to the Cyclone V GX FPGA Development Kit page Hardware Software October 2012 Altera Corpo The Cyclone V GX FPGA Development Kit includes the following hardware m Cyclone V GX FPGA development board A development platform that allows you to develop and prototype hardware designs running on the Cyclone V GX FPGA Te For detailed information about the board components and interfaces refer to the Cyclone V GX FPGA Development Board Reference Manual m De2. 1 1 Quartus Web Edition Software 0 1 1 Cyclone V GX FPGA Development Kit Installer 2 1 1 2 Chapter 2 Getting Started VOU Begin iss Pen ete me i pan ae hee ker 2 1 Inspect the Boards Ce eee e e I dabei liess 2 1 Reterences ere gae sab ite bow adage E ied 2 2 Chapter 3 Software Installation Installing the Quartus II Web Edition Software eh 3 1 Licensing Considerations ee eee ree XEM E IR n Goth ie 3 1 Installing the Development Kit ene ene 3 1 Installing the USB Blaster Driver I 3 2 Chapter 4 Development Board Setup Up the Board cocos dee er use PUN LIN LM 4 1 Factory Default Switch Settings ee eee i ih 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page ssssss e 5 1 Using the Board Update Portal to Update User Designs 5 2 Chapter 6 Board Test System Preparing the Boardi Ded UL 6 2 Running the Board Test System eee ee 6 2 Using the Board Test System enhn 6 3 Th System Info Tab ER Ve ER VERE RR REPRE E ae RI be
3. October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 6 p id Chapter 6 Board Test System Using the Board Test System The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display If you exceed the 16 character display limit on either line a warning message appears User DIP Switches The read only User DIP switches control displays the current positions of the switches in the user DIP switch bank Change the switches on the board to see the graphical display change accordingly User LEDs The User LEDs control displays the current state of the user LEDs Click the graphical representation of the LEDs to turn the board LEDs on and off You can click ALL to turn on and off all of the user LEDs at once Push Button Switches The read only Push Button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 7 Using the Board Test System The Flash Tab The Flash tab allows you to read and write flash memory on your board Figure 6 3 shows the Flash tab Figure 6 3 The Flash Tab A Board Test Hel
4. 101 Innovation Drive San Jose CA 95134 www altera com UG 01123 1 1 Cyclone V GX FPGA Development Kit User Guide NA Feedback Subscribe 2012 Altera Corporation rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide N DTE RYN Contents Chapter 1 About This Kit Kit Features EL 1 1 Hardw be xu da 1 1
5. 1 PAN FORGE ON m On 0 Fan is turned on On m Off 1 Fan is turned off Set the DIP switch bank SW5 to match Table 4 3 and Figure 4 1 Table 4 3 SW5 JTAG DIP Switch Settings Part 1 of 2 Default Position Board Label Function Switch Switch 1 has the following options m On 0 Do not Include MAX V system 1 5M2210 JTAG EN controller in the JTAG chain Off m Off 1 Include MAX V system controller in the JTAG chain Switch 2 has the following options m On 0 Do not Include the HSMC Port A in the 2 HSMA JTAG EN JTAG chain On m Off 1 Include the HSMC Port A in the JTAG chain October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide Chapter 4 Development Board Setup Table 4 3 SW5 JTAG DIP Switch Settings Part 2 of 2 Factory Default Switch Settings 5 Board r Default Switch Label Function Position Switch 3 has the following options m On 0 Do not include the PCI Express Edge 3 PCIE JTAG EN connector in the JTAG chain On m Off 1 2 Include the PCI Express Edge connector in the JTAG chain 4 For more information about the FPGA board settings refer to the Cyclone V GX FPGA Development Board Reference Manual Cyclone V GX FPGA Development Kit User Guide October 2012 Altera Corporation RYN 5 Board Update Portal The Cyclone V GX FPGA Developme
6. SRAM Flash Project 0000 0110 C94193DB 022377CC EZDAEFAA 738183F3 0000 0120 78607616 1C4B4E7D OBSD1DSD 2A74SEE1 0000 0130 A8CD42D4 BASAAOOO 4F63785C EA36511D 0000 0140 A69750A5 FBABSDF7 7B 5EEF1 CA3C1898 0000 0150 43646162 A784471 4E80058E 513D2583 The following sections describe the controls on the SSRAM tab The Read control reads the SRAM on your board To see the SRAM contents type a starting address in the text box and click Read Values starting at the specified address appear in the table Write The Write control writes the SRAM on your board To update the SRAM contents change values in the table and click Write The application writes the new values to SRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 10 Chapter 6 Board Test System The Power Monitor Random Test Starts a random data pattern test to SSRAM memory Increment Test Starts an incrementing data pattern test to SSRAM memory The Power Monitor The Power Monitor measures and reports current power information To start the application click Power Monitor in the Board Test System application You can also run the Power Monitor as a stand alone application Po
7. flash format gt Design files available from the Cyclone V GX FPGA Development Kit page include flash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page A 2 for information about preparing your own design for upload To upload a design over the network into the user portion of flash memory on your board perform these steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page 2 In the Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank 3 Click Upload The progress bar indicates the percent complete 4 Toconfigure the FPGA with the new design after the flash memory upload process is complete set the DIP switch SW3 3 to the user on 0 position and power cycle the board gt As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write new designs to the user hardware 1 portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 Cyclone V GX FPGA Developm
8. m On Board USB Blaster II driver Installing the Quartus Il Web Edition Software The Quartus II Web Edition Software provides the necessary tools used for developing hardware and software for Altera devices Included in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the OpenCore Plus evaluation IP library The Quartus II software including Osys and the Nios II EDS are the primary development tools used to create the reference designs in this kit To install the Altera development tools perform these steps 1 Run the Quartus II Web Edition Software installer you acquired in Software on page 1 1 2 Follow the on screen instructions to complete the installation process choosing an installation directory that is relative to the Quartus II software installation directory T If you have difficulty installing the Quartus II software refer to Altera Software Installation and Licensing Manual Licensing Considerations The Quartus II Web Edition Software is license free and supports Cyclone V GX devices without any additional licensing requirement This kit also works in conjunction with the Quartus II Subscription Edition Software once you obtain the proper license file To purchase a subscription contact your Altera sales representative Installing the Development Kit To install the development kit perform these steps 1 Download the Cyclone V GX FPGA Development Kit installer fr
9. GX FPGA Development Kit User Guide Appendix A Programming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings October 2012 Altera Corporation S BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes October 2012 1 1 Maintenance release October 2012 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact 7 Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Inita Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project name
10. SRAM and flash memory on your board Figure 6 4 shows the SSRAM tab Figure 6 4 The SSRAM Tab System info GPIO Flash SSRAM SRAM 0000 0000 Power Monitor Address 0000 0000 Start address Range 0 0000 0000 Ox001F FFFF 0 3 FAS6C3E8 4 7 7SB8ABFD 8 B 608ES36SF 3ESEF3A3 0000 0010 4F7D2F37 F57DB62F 1525D7C5 559 1 1 0000 0020 ZBOFE6GCF D6391DBA A8 0ED3B 17496B4A 0000 0030 DSS3SFOB 308257DE 7C4798A3 3F 0B0269 0000 0040 A06A6212 10837898 OSAOBS B 0000 0050 44A0DDCE amp C643367 1 8 3SOFFO1C 0000 0060 S863BEF8 8730074C 141FFSE2 DASZE6CS8 0000 0070 87 7 99 F2AA852F A1DS8523 1C778BC8 0000 0080 DES1FE75 ABA2BC7B Sl1AOCFSD CE75F113 0000 0090 8571D4F4 39186372 45C3DOBC DB4815A1 0000 00A0 4C622A52 1B848808 2E3CA3FF 7C4D1DS3 0000 le760048B 4D57CF8C SAFFO116 31CB1B32 ASEAE444 FD046C7 4SCFED32 0B816734 0000 00D0 32801157 C188C443 30D86130 32FD88SA 0000 00 0 A882F6ED 3Bescpss S774AF19 Messages 0000 0020 67248891 1AB4470E ZASSEFBBE 1123B8A7 0000 0100 FOIBE3C1 C5C5285B SFEC84S6 5077 2 Detected the GPIO
11. flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Cyclone V GX FPGA development board and the Nios II EDS tools involved with reprogramming the user portions of the flash memory device The Cyclone V GX FPGA development board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default user configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios II EDS just as the hardware design was created using the Quartus II software For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map CAUTION Table A 1 shows the default memory contents of the 512 Mb CFI flash device For the Board Update Portal to run correctly and update designs in the user memory this memory map must not be altered Table A 1 Byte Address Flash Memory Map Block Description KB Size Address Range Unused 128 Ox03FE 0000 O3FF FFFF User software 28 800 0x023C 0000 03FD FFFF Factory software 8192 0x01BC 0000 023B FFFF zipfs html web content 4096 0x017C 0000 01BB FFFF User hardware 2 8064 OxOOFE 0000 017B FF
12. it is calculated refer to the 51570 51571 data sheet available on the Silicon Labs website ww w silabs com Target Frequency The Target frequency control allows you to specify the frequency of the clock Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possible within 100 parts per million ppm The Target frequency control works in conjunction with the Set New Frequency control October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 14 Chapter 6 Board Test System Configuring the FPGA Using the Quartus Programmer This control reads the current frequency setting for the oscillator associated with the active tab Clear This control sets the frequency for the oscillator associated with the active tab back to its default value This can also be accomplished by power cycling the board Set New Frequency The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the 51571 and the Frequency controls for the 515338 U25 Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with a specifi
13. suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch Settings on page 4 2 to return the board to its factory settings before proceeding 2 The FPGA development board ships with design examples stored in the flash memory device Verify the DIP switch SW3 3 is set to the factory off 1 position to load the design stored in the factory portion of flash memory 7 The FPGA development board can be powered by the PCIe host adapter or the laptop power adapter If you want to power the board by the PCIe host system plug the FPGA development card into a standard PCIe connector Alternatively to power the FPGA development board using the laptop power adaptor perform the following two steps 3 Connect the 65 W 15 VDC 4 3 A power supply to the DC Power Jack J9 on the FPGA board and plug the cord into a power outlet A Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage and a lower rated power supply may not be able to provide enough power for the board 4 Set the POWER switch SW1 to the on position When power is supplied to the board blue LED D23 illuminates indicating that the board has power The MAX V device on the board contains among other things a parallel flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and conf
14. the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 8 Chapter 6 Board Test System Using the Board Test System Random Test Starts a random data pattern test to flash memory which is limited to a scratch page in the upper 128K block CFI Query The CFI Query control updates the memory table displaying the CFI ROM table contents from the flash device Increment Test Starts an incrementing data pattern test to flash memory which is limited to a scratch page in the upper 128K block Reset The Reset control executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory which is limited to a scratch page in the upper 128K block Data Display Entry Boxes There are 8 rows and 4 columns Each column contain 8 hexadecimal numbers After entering the numbers in each cell press Enter on your keyboard Then click Write and Read button Flash Memory Map Displays the flash memory map for the Cyclone V GX FPGA Development Kit Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System Using the Board Test System The SSRAM Tab 6 9 The SSRAM tab allows you to read and write
15. to a working Ethernet port on a DHCP enabled network A separate working Ethernet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 With the board powered down set the DIP switch SW3 3 to the factory off 1 position 2 Attach the Ethernet cable from the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays the IP address 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs 7 You can click Cyclone V GX FPGA Development Kit on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs Te You can also navigate directly to the Cyclone V GX FPGA Development Kit page of the Altera website to determine if you have the latest kit software Using the Board Update Portal to Update User Designs The Board Update Portal allows you to write new designs to the user hardware 1 portion of flash memory Designs must be in the Nios II Flash Programmer File
16. FF User hardware 1 8064 0x0080 0000 OOFD FFFF Factory hardware 8064 0x0002 0000 007F FFFF PFL option bits 32 0x0001 8000 0001 FFFF Board information 32 0x0001 0000 0001 7FFF Ethernet option bits 32 0x0000 8000 000 FFFF User design reset vector 32 0x0000 0000 000 7FFF Altera recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page 4 October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide A 2 Appendix A Programming the Flash Memory Device Preparing Design Files for Flash Programming Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Cyclone V GX FPGA Development Kit page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board Update Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user h
17. M221082 Qsys Memory Map Messages Block description Address Detected the GPIO SRAM Flash Project maxi 0x0060 0000 0060 0IFF 0x0010 0000 0017 FFFF October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 2 Chapter 6 Board Test System Preparing the Board Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears and allows you to exercise the related board features Highlights appear in the board picture around the corresponding components The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the JTAG bus to the MAX II device you can measure the power of any design in the FPGA including your own designs 7 The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board With the p
18. System La On Windows click Start gt All Programs gt Altera gt Cyclone GX FPGA Development Kit version gt Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design running in the FPGA The Cyclone V GX FPGA development board s flash memory ships preconfigured with the design that corresponds to the GPIO Flash and SSRAM tabs If you power up your board with the DIP switch SW3 3 in a position other than the user on 0 position or if you load your own design into the FPGA with the Quartus II Programmer you receive a message prompting you to configure your board with a valid Board Test System design Using the Board Test System This section describes each control in the Board Test System application The System Info Tab The System Info tab shows board s current configuration Figure 6 1 on page 6 1 shows the System Info tab The tab displays the contents of the MAX V registers the chain the board s MAC address the flash memory map and other details stored on the board The following sections describe the controls on the System Info tab Board Information The Board information controls display static information about your board m Board Name Indicates the official name of the board m Part number Indicates the part number of the board B Serial number Indicates the serial number of the board Factory test version Indicates t
19. U25 tab Figure 6 6 The Clock Control U25 Tab F_vco 2457 6000 Registers Frequency MHz Disable al C 125 0000 CLKO 100 00 Disable CLKO F eua 409 6000 100 00 Disable CLK1 7 cue 156 2500 CLK2 100 00 Disable CLK2 7 100 0000 100 00 Disable CLK3 7 Default Set New Frequency Messages USB BlasterII on localhost 058 1 5 12702 324 22102 EPM221082 Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 13 The Clock Control Figure 6 7 shows the Clock Control 025 tab Figure 6 7 The Clock Control X2 Tab ANB RA 025 Serial port registers HS DIV Target frequency MHz 100 00 MHz 1 6 RFREQ O2F3ffcb4d Valid frequency range values are PXTAL 114 2858 Mie 10 00000000 to 810 00000000 MHz Messages USB BlasterII on localhost USB 1 5M 1270ZF324 22102 EPM221082 The following sections describe the Clock Control controls Serial Port Registers The Serial port registers control X2 tab shows the current values from the 51570 registers For more information about the Si570 registers refer to the Si570 Si571 data sheet available on the Silicon Labs website ww w silabs com fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values For more information about the fyrar value and how
20. and shell navigate to the lt install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaMfactory recovery directory and type the following command to run the restore script restore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes if powered by the laptop power adapter cycle the POWER switch SW1 off then on If the FPGA development board is powered by PCIe host cycle the host power Using the Quartus II Programmer click Add File and select lt install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaMfactory recovery Nc5gxfc7 fpga sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D15 and the 4 User LEDs D4 D7 illuminate indicating the flash memory device is now restored with the factory contents The flash device is ready for programming After all flash programming completes if powered by the laptop power adapter cycle the POWER switch SW1 off then on If the FPGA development board is powered by PCIe host cycle the host power The restore script cannot restore the board s MAC address automatically In the Nios II command shell type the following Nios II EDS command Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Appendi
21. ardware 1 and user software locations of the flash memory For more information about Nios EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios Il EDS If you have an FPGA design developed using the Quartus II software and software developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click Programs gt Altera gt Nios II EDS gt Nios II Command Shell 2 In the Nios command shell navigate to the directory where your design files reside and type the following Nios II EDS commands m For Quartus II sof files sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x800000 pfl optionbit 0x00018000 programmingmode FPP m For Nios II elf files elf2flash base 0x00000000 end 0x03FFFFFF reset 0x23C0000 input lt yourfile gt sw elf output lt yourfile gt sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader sources boot loader cfi sre ce The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them The Board Update Portal standard flash format conventionally uses either filename hw fla
22. available on the Cyclone V GX FPGA Development Kit page of the Altera website m Powerrail Indicates the currently selected power rail After selecting the desired rail click Reset to refresh the screen with new board readings UST A table with the power rail information is available in the Cyclone V GX FPGA Development Board Reference Manual Power Information The Power information control displays current maximum and minimum power readings for the following units mAmp Power Graph The power graph displays the mA power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset The yellow line indicates the minimum value read since the last reset Graph Settings The following Graph settings controls allow you to define the look and feel of the power graph m Scale select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the entire range of recorded values m Update speed Specifies how often to refresh the graph Reset This Reset control clears the graph resets the minimum and maximum values and restarts the Power Monitor October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 12 Chapter 6 Board Test System The Clock Control The Clock Control The Clock Control application sets the 51571
23. board design demos Contains demonstration applications documents Contains the kit documentation examples Contains the sample design files for the Cyclone V GX FPGA Development Kit Contains the original data programmed onto the board before shipment Use this data to restore factory recovery the board with its original factory contents Installing the USB Blaster Driver The Cyclone V GX FPGA development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the On Board USB Blaster II driver on the host computer T Installation instructions for the On Board USB Blaster II driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions For USB Blaster II configuration details refer to the On Board USB Blaster II page Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide N DTE 4 Development Board Setup The instructions in this chapter explain how to set up the Cyclone V GX FPGA development board Setting Up the Board To prepare and apply power to the board perform these steps 1 The FPGA development board ships with its board switches preconfigured to support the design examples in the kit If you
24. bug Header Breakout Board HSMC m Loopback Daughtercard HSMC m Power supply and cables The kit includes the following items m Power supply and AC adapters for North America Japan Europe and the United Kingdom m USB cable m Ethernet cable m Mini SMB cable The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to have Altera mail the software to you on DVDs Quartus Il Web Edition Software The Quartus II Web Edition Software is a licensed set of Altera tools with full functionality ration Cyclone V GX FPGA Development Kit User Guide Chapter 1 About This Kit Kit Features Download the Quartus II Web Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website St Tocompare the Quartus II subscription and web editions refer to Altera Quartus II Software Subscription Edition vs Web Edition The kit also works in conjunction with the subscription edition Cyclone V GX FPGA Development Kit Installer The license free Cyclone V GX FPGA Development Kit installer includes all the documentation and design examples for the kit For information on installing the Development Kit Installer refer to Installing the Development Kit on page 3 1 Cyclone V GX FPGA Development Kit Oct
25. c sof Before configuring the FPGA ensure that the Quartus II Programmer and the USB Blaster II driver are installed on the host computer the USB cable is connected to the FPGA development board power to the board is on and no other applications that use the JTAG chain are running To configure the Cyclone V GX FPGA perform these steps 1 Start the Quartus II Programmer Click Auto Detect to display the devices in the JTAG chain Click Add File and select the path to the desired sof Turn on the Program Configure option for the added file w N Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 Using the Quartus II programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete If the Quartus II programming window is already open and then you power cycle the board you may be required to click Hardware Setup in the Quartus II Programmer window and reselect USB Blaster II in order to properly detect the JTAG chain Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide A Programming the Flash Memory JN S RAN As you develop your own project using the Altera tools you can program the flash memory device so that your own design loads from
26. ees bee Saw ee EAS dhs ba ee 6 9 Read 1 eer E ERG 6 9 jou 6 9 Random Test E E E REG GR CERE RR A CK RECON 6 10 Increment Test xp Giu BA S xd bp X A er EN 6 10 The Power Monitor lees Rh ee hh et 6 10 General Information e hu e ar e 6 11 Power Information sa ag s E EE HO ERES EE E 6 11 Power Graph ep ee baute te beta dt 6 11 Graph Settings d RE Dee Eae DOE A Roper RE ERR E FERES CDU PEE ER 6 11 INIT Uc 6 11 The Clock Control 6 12 Serial Port Registers ee e ee id re pre ee RI I here Rr E bee EX ae 6 13 EXTAL 6 13 Target Frequency coenae erbe rte reine pd ioo e ede ao doe e Ie HA o tp len 6 13 Read ei bey sessed 6 14 acl PUTET 6 14 Set New Frequency ERO DUO P HO Ed a d iet 6 14 Configuring the FPGA Using the Quartus 6 14 Appendix A Programming the Flash Memory Device CPI Flash Map eite edad teria e de e en edat ad IRR pb hag A 1 Preparing Design Files for Flash Programming 0 A 2 Creating Flash Files Using the Nios 5 2 A 2 Programming Flash Memory Using the Board Update Portal
27. ent Kit October 2012 Altera Corporation User Guide 6 Board Test System The kit includes a design example and an application called the Board Test System BTS to test the functionality of the Cyclone V GX FPGA development board The BTS provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters Observe performance and measure power usage While using the BTS you reconfigure the FPGA several times with test designs specific to the functionality you are testing The BTS is also useful as a reference for designing systems To install the BTS follow the steps in Installing the Development Kit on page 3 1 The Board Test System GUI communicates over the JTAG bus to a test design running in the Cyclone V GX device Figure 6 1 shows the initial GUI for a board that is in the factory configuration Figure 6 1 Board Test System Graphical User Interface System info Flash SSRAM 45M Board information Board Name Cyclone V GX FPGA Development Kit Board Board P N 6XX 44121R Serial number 5SCGXDK00000029 Factory test version 12 0 2 0 92 00 92 00 92 00 V ver 1 MAX V registers ATERA AT Cyclone y Y 5 Use PSR ser Use PSS JTAG chain USB BlasterII on localhost USB 2 1 5CGXFC7 C7ES D6ES D7ES 81 2 5M 1270ZF324 22102Z EP
28. he first device in the chain The JTAG chain is normally mastered by the On board USB Blaster II Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 5 Using the Board Test System If you plug in an external USB Blaster cable to the JTAG header J13 the On Board USB Blaster II is disabled gt JTAG DIP switch bank SW5 selects which interfaces are in the chain Refer to Table 4 3 on page 4 3 for detailed settings Ta For details on the JTAG chain refer to the Cyclone V GX FPGA Development Board Reference Manual For USB Blaster II configuration details refer to the On Board USB Blaster II page Qsys Memory Map The Osys memory map control shows the memory map of the Osys system on your board The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off run a server program on the Ethernet port and detect push button presses Figure 6 2 shows the GPIO tab Figure 6 2 The GPIO Tab System info GPIO RYAN Character LCD Enter text Cyclone V GX Fpga Dev Kit SES 0 hd Cyclone 11 User DIP switch 1 OFF 0 ON User LEDs A Push button switches 2 Messages Detected the GPIO SRAM Flash Project
29. he illuminated PGM LED D12 D14 based on the following encoding m 0 PGM LED 012 and corresponds to the flash Page Select Switch memory page for the factory hardware design Read only PSS m 1 PGM LED D13 and corresponds to the flash memory page for the user hardware 1 design m 2 PGM LED D14 and corresponds to the flash memory page for the user hardware 2 design m PSO Sets the MAX II PSO register The following options are available m Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration m Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration m PSR Sets the MAX V PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information m PSS Displays the MAX V PSS register value Refer to Table 6 1 for the list of available options m SRST Resets the system and reloads the FPGA with a design from flash memory based on the other MAX V register values Refer to Table 6 1 for more information Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Cyclone V GX device is always t
30. he version of the Board Test System currently running on the board m MAX ver Indicates the version of MAX V code currently running on the board The MAX V code resides in the lt install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaNexamples directory Newer revisions of this code might be available on the Cyclone V GX FPGA Development Kit page of the Altera website m MAC Indicates the MAC address of the board October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 6 4 Chapter 6 Board Test System Using the Board Test System MAX V Registers The MAX V registers control allows you to view and change the current MAX V register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately For example writing a 0 to SRST resets the board Tahle 6 1 MAX V Registers Read Write Capability Register Name Description System Reset SRST Write only Set to 0 to initiate an FPGA reconfiguration Determines which of the up to three 0 2 pages of flash Read Write memory to use for FPGA reconfiguration The flash memory PSR ships with pages 0 and 1 preconfigured When set to 0 the value in PSR determines the page of Page Select Override flash memory to use for FPGA reconfiguration When set to PS0 Read Write 1 the value in PSS determines the page of flash memory to use for FPGA reconfiguration Holds the current value of t
31. igures the FPGA The DIP switch SW3 3 controls which design to load When the switch is in the factory off 1 position the PFL loads the design from the factory portion of flash memory The kit includes a MAX V design which contains the MAX V PFL megafunction The design resides in the install dir gt kits cyclone VGX_5cgxfc7df31_fpga examples max5 directory When configuration is complete the Config Done LED 015 illuminates signaling that the Cyclone V GX device configured successfully October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 4 2 Chapter 4 Development Board Setup Factory Default Switch Settings Te For more information about the PFL megafunction refer to Parallel Flash Loader Megafunction User Guide Factory Default Switch Settings This section shows the factory switch settings Figure 4 1 for the Cyclone V GX FPGA development board Figure 4 1 Switch Locations and Default Settings PCIE PRSNT2n 1 PCIE PRSNT2n x4 FAN FORCE ON SW4 SW5 EE 5M2210 JTAG EN CLKEN JTAG SW3 1 FACT LOAD L W HSMA JTAG EN E EC MODE PCIE JTAG EN On Of On Of On To restore the switches to their factory default settings perform these steps 1 Set the DIP switch bank SW3 to match Table 4 1 and Figure 4 1 Table 4 1 SW3 DIP Switch Settings Part 1 of 2 Board Default Switch Lahel Function Position Switch 1 ha
32. ios2 flash programmer utility refer to the Nios II Flash Programmer User Guide October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 4 Appendix A Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the FPGA development board Make sure you have the Nios II EDS installed and perform these steps 1 10 11 12 13 Set the board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 14 for more information Click Add File and select install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaMfactory recovery Nc5gxfc7 fpga sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D15 and the 4 User LEDs D4 D7 illuminate indicating that the flash device is ready for programming The flash device is ready for programming On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell In the Nios II comm
33. n 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 14 for more information 5 Click Add File and select install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaMfactory recovery Nc5gxfc7 fpga sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D15 and the 4 User LEDs D4 D7 illuminate indicating that the flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios Command Shell 9 In the Nios II command shell navigate to the install dir NkitsNcycloneVGX 5cgxfc7df31 fpga factory recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios II EDS on page 2 and type the following Nios II EDS command nios2 flash programmer base 0x00000000 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type the following Nios II EDS command nios2 flash programmer base 0x00000000 lt yourfile gt sw flash 11 Set the DIP switch SW3 3 to the user on 0 position and power cycle the board Programming the board is now complete St For more information about the n
34. nt Kit ships with the Board Update Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios II embedded processor an Ethernet MAC and an HTML web server When you power up the board with the DIP switch SW3 3 in the factory off 1 position the Cyclone V GX FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to the user hardware 1 portion of flash memory and provides useful kit specific links and design resources I gt After successfully updating the user hardware 1 flash memory you can load the user design from flash memory into the FPGA To do so set the DIP switch SW3 3 to the user on 0 position and power cycle the board The source code for the Board Update Portal design resides in the install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaNexamples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page A 4 to restore the board with its original factory contents Connecting to the Board Update Portal Web Page This section provides instructions to connect to the Board Update Portal web page 7 Before you proceed ensure that you have the following m APC with a connection
35. o press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b c and so on such as the steps listed in a procedure Bullets indicate list of items when the sequence of the items is not important 57 The hand points to information that requires special attention The question mark directs you to a software help system with related information The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document Cyclone V GX FPGA Development Kit User Guide October 2012 Altera Corporation
36. ober 2012 Altera Corporation User Guide N DTE BAN 2 Getting Started The remaining chapters in this user guide lead you through the following Cyclone V GX FPGA development board setup steps m Inspecting the contents of the kit m Installing the design and kit software m Setting up powering up and verifying correct operation of the FPGA development board m Configuring the Cyclone V GX FPGA m Running the Board Test System designs For complete information about the FPGA development board refer to the Cyclone V GX FPGA Development Board Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the boards to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Boards To inspect each board perform these steps 1 Placethe board on an anti static surface and inspect it to ensure that it has not been damaged during shipment Without proper anti static handling you can damage the board CAUTION 2 Verify that all components on the boards appear in place and intact In typical applications with the Cyclone V GX FPGA development board a heat sink is not necessary However under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines The board has two holes near
37. om the Cyclone V GX FPGA Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website 2 Run the Cyclone V GX FPGA Development Kit installer you acquired in Software on page 1 1 3 Choosing an installation directory that is relative to the Quartus II software installation directory follow the on screen instructions to complete the installation process October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 3 2 Chapter 3 Software Installation Installing the USB Blaster II Driver The installation program creates the Cyclone V GX FPGA Development Kit directory structure shown in Figure 3 1 Figure 3 1 Cyclone V GX FPGA Development Kit Installed Directory Structure 7 lt install dir gt The default Windows installation directory is C altera lt version gt kits cycloneVGX 5cgxfc7df31 fpga eg board design files demos f documents C examples __ factory recovery Note to Figure 3 1 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Table 3 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a hoard design fles starting point for a new prototype
38. ower to the board off follow these steps 1 Connect the USB cable to the board 2 Ensure that the Ethernet patch cord is plugged into the RJ45 connector 3 Ensure that the development board switches and jumpers are set to the default positions as shown in the Factory Default Switch Settings section starting on page 4 2 4 Set the DIP switch SW3 3 to the user on 0 position For more information about the board s DIP switch and jumper settings refer to the Cyclone V GX FPGA Development Board Reference Manual 5 Turn on the power to the board The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO SRAM and flash memory tests To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System To run the application navigate to the install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaNexamplesVboard test system directory and run the BoardTestSystem exe application Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 3 Using the Board Test
39. p About Configure System info 1 Flash ssram 2052 Flash Start address Range 0 0000 0000 OxO3FF FFFF O3FE 0000 R i CFI Query Reset Erase Address 0 3 4 7 8 B C F O3FE 0000 04324911 4880 00 31A21024A 8085800 STRA a e 0010 0001880D 36002402 406203C6 0140D880 gt CT O3FE 0020 20004010 E05400A1 06A05802 01041244 O3FE 0030 18AFE amp E7 00434482 E21400A0 5300 065 O3FE 0040 00000542 52720178 D0620926 D440BCOO 0050 10444806 03000301 0416141B 01098442 O3FE 0060 24020050 2323C082 08024C82 00541800 03FE 0070 90806208 8A420D82 0S6B1081 6444724 Block description Size Address 0000 03FF FFFF 3 409808 0x017C 0000 OIBRFFFF Messages Detected the GPIO SRAM Flash Project 0x0002 0000 007F FFFF 0x0001 8000 0001 FFFF 0x0001 0000 The following sections describe the controls on the Flash tab The Read control reads the flash memory on your board To see the flash memory contents type a starting address in the text box and click Read Values starting at the specified address appear in the table If you enter an address outside of the flash memory address space a warning message identifies the valid flash memory address range Write The Write control writes the flash memory on your board To update
40. programmable oscillator to any frequency between 10 MHz and 810 MHz with eight digits of precision to the right of the decimal point The 515338 device has four independently programmable outputs four outputs are programmable between 16 KHz and 350 MHz four outputs can support the higher frequencies but they cannot be programmed for multiple frequencies above 350 MHz If you want multiple outputs above 350 MHz all outputs above 350 MHz must be the same frequency and must be frequencies from 367 MHz to 473 33 MHz or from 550 MHz to 710 MHz Channel 0 of 15338 drives a 2 to 4 buffer that drives a copy of the clock to all four edges of the FPGA The Clock Control application runs as a stand alone application ClockControl exe resides in the install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaNexamplesVboard test system directory On Windows click Start gt Programs gt Altera gt Cyclone V GX FPGA Development Kit version Clock Control to start the application For more information about the 51571 515388 and the Cyclone V GX FPGA development board s clocking circuitry and clock input pins refer to the Cyclone V GX FPGA Development Board Reference Manual The Clock Control communicates with the MAX V device on the board through the bus The 51571 programmable oscillator is connected to the MAX V device through a 2 wire serial bus Figure 6 6 shows the Clock Control
41. s disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets For example file name and lt project name pof file October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI angled arrow instructs you t
42. s the following options 1 CLK SEL m On 0 SMA input clock is selected Off m Off 1 Programmable oscillator clock is selected Switch 2 has the following options 2 CLK EN m On 0 On board oscillator is disabled Off m Off 1 On board oscillator is enabled Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 4 Development Board Setup 4 3 Factory Default Switch Settings Table 4 1 SW3 DIP Switch Settings Part 2 of 2 Board Default Switch Lahel Function Position Switch 3 has the following options m On 0 Load the user design from flash at 3 FACT LOAD power up Off m Off 1 Load the user factory from flash at power up Switch 4 has the following options m On 0 On Board USB Blaster II sends 4 SEC MODE FACTORY command at power up Off m Off 1 On Board USB Blaster does not send FACTORY command at power up 2 Set DIP switch bank SW4 to match Table 4 2 and Figure 4 1 Table 4 2 SW4 DIP Switch Settings Default Position Board Label Function Switch Switch 1 has the following options 1 PCIE PRSNT2n x1 On 0 x1 presence detect is enabled Off m Off 1 x1 presence detect is disabled Switch 2 has the following options 2 PCIE PRSNT2n 4 m On 0 x4 presence detect is enabled Off m Off 1 2 x4 presence detect is disabled 3 Switch 4 has the following options Fan is not included
43. sh for hardware design files or filename sw flash for software design files Programming Flash Memory Using the Board Update Portal Once you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Appendix A Programming the Flash Memory Device A 3 Programming Flash Memory Using the Nios EDS x If you have generated a sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios Il EDS The Nios IT EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform these steps 1 Set the DIP switch SW3 3 to the factory off 1 to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board 3 Ifthe board has powered up and the LCD displays either Connecting or a valid IP address such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the Config Done LED D15 does not illuminate continue to step 4 to load the FPGA with a flash writing desig
44. ta ele 6 3 Board Information hh e re 6 3 Registers em c T RR ICI e 6 4 JTAG Chain b NER d CEA ER 6 4 Qsys Memory Map sie tess setas ch Hber Ea ee a euet west er e ate eg 6 5 The GPIO Tab ise et be E dee bee nce eh ante deena EC e a 6 5 Character LCD eth rare Ea rA et ere tois na ques e ra re and 6 6 User DIP Switches oii xh oberg P RE E RAD d EY eaae 6 6 User LEDS oc ete eve a we ack dd vx RP PE EG RESO AES 6 6 Push Button Switches een n 6 6 The Flash Tab abe phar ERAS seat ed e I d bee iren 6 7 Read i2 d bk ecw a ee ER RE A EXERCERE e ERA 6 7 WEE na eE oe oves P EPA dvd EUR duplo 6 7 nee e Gn pacti dac ose pa awed ai hacia Maes 6 8 Query A 6 8 Increment Test RR ea ba ee eI uA 6 8 vues We ek ee VERA UG e UEM ERU Pau 6 8 ee 6 8 October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide iv Contents Data Display Entry Boxes iicet t erre eer oe see E UE Ra heo e E 6 8 Flash Memory Map e hee be e rh bead 6 8 The SSRAM Tab REPERI
45. the FPGA that accommodate many different heat sinks including the Dynatron V31G You can perform power consumption and thermal modeling to determine whether your application requires additional cooling For information about measuring board and FPGA power in real time refer to The Power Monitor on page 6 10 St For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide 2 2 References Chapter 2 Getting Started References Use the following links to check the Altera website for other related information For the latest board design files and reference designs refer to the Cyclone V GX FPGA Development Kit page For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Cyclone V GX device documentation refer to the Documentation Cyclone V Devices page To purchase devices from the eStore refer to the Devices page For Cyclone V GX OrCAD symbols refer to the Capture CIS Symbols page For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide N SYAN 3 Software Installation This chapter explains how to install the following software m Quartus II Web Edition Software m Cyclone V GX FPGA Development Kit software
46. werMonitor exe resides in the install dir gt kits cycloneVGX_5cgxfc7df31_fpga examples board_test_system directory On Windows click Start gt All Programs gt Altera gt Cyclone V GX FPGA Development Kit lt version gt gt Power Monitor to start the application The Power Monitor communicates with the MAX V device on the board through the JTAG bus A power monitor circuit attached to the MAX V device allows you to measure the power that the Cyclone V GX FPGA is consuming Figure 6 5 shows the Power Monitor Figure 6 5 The Power Monitor General Information Power Information MAX V Version 1 Power Rail 1 1y_VCC_Core RMS Maximum Minimum 101 98 M enn Graph Settings connections USB BlasterII on localho Scale Select Update Speed Ist USB 1 5M 1270ZF324 22102Z EPM221 log2 200mA Fast Cyclone V GX FPGA Development Kit October 2012 Altera Corporation User Guide Chapter 6 Board Test System 6 11 The Power Monitor The following sections describe the Power Monitor controls General Information The General information controls display the following information about the MAX V device m MAX V version Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir NkitsNcycloneVGX 5cgxfc7df31 fpgaMfactory recovery and install dir gt kits cycloneVGX_5cgxfc7df31_fpga examples max5 directories Newer revisions of this code might be
47. x A Programming the Flash Memory Device A 5 Restoring the MAX V CPLD to the Factory Settings nios2 terminal and follow the instructions in the terminal window to generate a unique MAC address Ta Toensurethat you have the most up to date factory restore files and information about this product refer to the Cyclone V GX FPGA Development Kit page of the Altera website Restoring the MAX V CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX V CPLD on the FPGA development board Make sure you have the Nios II EDS installed and perform these steps 1 Setthe board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 57 DIP switch SW5 1 includes the MAX V device in the JTAG chain 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click Add File and select install dir NkitsNcycloneVGX 5cgxfc7df31 recovery 5 5 Turn on the Program Configure option for the added file 6 Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 St Toensurethat you have the most up to date factory restore files and information about this product refer to the Cyclone V GX FPGA Development Kit page of the Altera website October 2012 Altera Corporation Cyclone V GX FPGA Development Kit User Guide Cyclone V
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