FPSLIC STK594 User Guide - Digi-Key
Contents
1. FPGA I O FPGA AVR I O Select Ports Tab LOAD IOSELAO AVRloSelects RCO INTAO FPGAInterrupts D 7 0 ADINA 7 0 DataFromAVR aWE FIOWEA AVRControls Clock GCLK5 FPGAClocks 7 Uncheck Generate Template Test Bench File on the bottom left hand side of the Select Ports dialog Since we are not performing co verification it is not neces sary to generate the pre layout test bench file 8 Press OK AMEL FPSLIC STK594 User Guide Using System Designer 4 8 FPGA Place and The Figaro Integrated Development System IDS is used as the FPGA Place amp Route Route tool Figaro takes the gate level technology specific file generated by the synthesis tool and partitions places and routes the FPGA design 1 Press the Figaro IDS button to open the FPGA Place amp Route Tools Settings dia log see Figure 4 15 Figure 4 15 FPGA Place 8 Route Tools Settings Dialog FPGA Place amp Route Tool Settings Lx Open EDIF Netlist Browse Help C Open Saved FPGA design file fgd Cancel Run FPGA place amp route tool in stand alone mode Select this mode if you want to launch the FPGA place amp route tool to run macro generators Files Settings Huser Library Settings 2 Select Open EDIF Netlist and Browse to select COUNTER edf then press OK Figaro should open and complete the Open Map and Parts steps automatically once completed the Figaro Batch Options dialog appears see Fig2. qab SALA Place the Programming switch in the PROG position Using a 10 wire ribbon cable from the STK500 connect PORTD to the LEDS Using a 2 wire cable from the STK500 connect SWO and SW 1 to FPSLIC pins 177 and 178 respectively Connect the Power Supply from an AC outlet to the power connector on the STK500 development board Turn on the STK500 Note Prior to providing power to the STK500 development board it is necessary to FPSLIC STK594 User Guide adjust the VTARGET supplied by the STK500 to the STK594 for more informa tion on this adjustment please refer to Section 2 1 1 AMEL a 2819D FPSLI 11 04 Using System Designer 4 10 2 Software Setup 4 16 2819D FPSLI 11 04 The CPS utility allows for the programming reading and verification of data CPS sup ports Atmel s AT17F ATFS and AT17LV series of configuration memories 1 Launch CPS from Start gt All Programs gt Atmel gt CPS8 xx where xx represents the version Figure 4 20 CPS ATMEL AT17 CONFIGURATOR PROGRAMMING SYSTEM File Calibrate Help Procedure r Partition program and verify from an Atmel file y r Files Info R n One or more Atmel bst files may be generated for Input File Bg stemDesigner Designs STK zi El subsequent download sessions The optional checksum can be obtained from the log output of Output File c SystemDesigner Designs STK y El Checksum eac
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4. COUNTER ATT FPGA I O Attribute File FPSLIC STK594 User Guide 4 1 Rev 2819D FPSLI 1 1 04 Using System Designer 4 2 Description 4 3 Design Flow 4 2 2819D FPSLI 11 04 The design in this tutorial is composed of a simple AVR microcontroller program and a loadable counter implemented in the FPGA When the counter reaches the terminal value an interrupt to the microcontroller will be generated using the counter s carry out RCO signal The interrupt is active Low and must be held for three clock cycles prior to its acknowledgement by the microcontroller During the Interrupt Service Routine ISR the microcontroller increments the count of interrupt occurrences and places the incre mented data on PORTD and the AVR FPGA Data Bus triggering the counter s LOAD signal Once the counter has been loaded counting will commence and the process will be repeated Figure 4 1 shows a simplified block diagram of the tutorial design Figure 4 1 Tutorial Design Block Diagram PORTD AVR FPGA Microcontroller 8 bit Counter LOAD lt IOSELAO FPGA I O SELECT 0 aWE lt FIOWEA AVR Write Enable D 7 0 AVR Data Bus 8 bit ENABLE RESET RCO 17 gt FPGA Interrupt O 1 CLOCK be 7 Global Clock 5 a The design presented in this tutorial only performs the required steps for designing and programming an AT94K series device For more information on the optional steps i e Simulation and C
5. HDL Synthesis Software Compiler AWR FPGA Interface 2 Pre lavout Coverification Y SYSTEM DESIGNER 4 4 AIMEL FPSLIC STK594 User Guide 2819D FPSLI 11 04 Using System Designer 6 Select either Mentor VHDL or Mentor Verilog as the Tool Flow and press Next The add parts window opens see Figure 4 7 For this tutorial the instructions will assume Mentor Verilog has been selected Figure 4 7 New Project Wizard Window Step 5 of 6 Selected parts and toolflow The list below shows the part you have selected for your project When you are ready click Next to continue Project Parts U1 4T94K40 25DGC Mentor Yerilog SYSTEM DESIGNER Congratulations You have successfully completed the creation of your new System Designer project The project tree shows the tools and design files included in your project Using the vertical toolbar on the side of the tree you can add or delete parts modify toolflows or include new design files To begin click on a part in the project tree This will display the design flow in the part window Then click on any button in the design flow to run the associated design tool To close the New Project wizard and begin working with your project click the Finish button Cr TI E O 0 TI O SYSTEM Cancel Back E Finish 7 Press Finish to exit the New Project Wizard The project window now contains the TUTORIA
6. toser 29 17 0 1 TOSC2 ie SW DPDT R1 200K R2 10M LD LL 32 768 kHz 12 1 rT gt C2 33 pF 27 pF sw2 Y2 XT1 XT1 XHALI tees F o OUT l XT2 Cams m XTAL2 lt lt OSC8 SW DPDT Title ATSTKS594 Clock Circuitry Size Al Document Number CHW5472 Date Friday April 26 2002 Sheet 1026 4 3 2 so euwoyos ajojduio Complete Schematics r z lal E E 2 A A e 4 2152 8 amp amp S 57 ia 8 zz ig 2 152 iz 5 z 33 El 212 BS E zo I TEGER SEE BEER 8 B RIA A RR A N H NA AES 88 SBPEPESB Bez B eh AR alo cle RRS A els Bla sss Elkielelelaleleieiel 14 gzel Sella el AAAAA22R TT Saeger desee Epeasienada ERE BERBER S a bat Beer ATT B o o bi l 88 OTTER po j e 6
7. 4 System Designer Licensing 3 4 1 Requesting a System Designer License 3 2 2819D FPSLI 11 04 This installation assumes that you have no previous version of System Designer installed in your machine If you have a previous version of the software installed or you need step by step installation instructions please refer to the System Designer Installa tion Licensing and Troubleshooting tutorial available on the Atmel web site 1 Insertthe supplied System Designer CD ROM into the computer Ifthe CD does not automatically start execute SETUP EXE from the CD 2 From the CD Browser select Install Products and select System Designer The System Designer installation will perform a full installation as there are no optional components Note Do not install System Designer to a directory name that contains spaces other wise improper opperation will occur Note When you reach the portion of the System Designer installation prompting about licensing you should select one of two options either Custom or Skip Select Custom if you already have a valid license and follow the instructions outlined in Section 3 4 2 Configuring the System Designer License Choose Skip if you do not have a license and follow the instructions in Section 3 4 1 Requesting a System Designer License Note AVR Studio version 3 2 or higher is required for STK500 STK594 support From the CD Browser select Install Products and select CPS f
8. Guide Using System Designer 4 11 Running the Once programming has completed it is necessary to move the Programming Design Switch to the RUN position for configuration of the FPSLIC device to occur If the LEDs on the STK500 begin to count the configuration has occurred If the configu ration does not occur press the RESET button found on the STK594 board to initiate a configuration download Alternatively power cycling the STK500 will also initiate a configuration download AMEL 2819D FPSLI 11 04 FPSLIC STK594 User Guide Using System Designer 4 18 AlINEL FPSLIC STK594 User Guide 2819D FPSLI 1 1 04 AMEL FPSLIC STK594 User Guide Section 5 Technical Specifications System Unit Physical Dimensions 0000 een een 5 125 x 2 75 Wed isc 7 7 6 oz Operating Conditions Voltage Supply Voc 3 3V Voo 1 8 3 3V Connections 1 2222 9 pin D SUB Female Serial Communications Speed 250 kbps 5 1 Rev 2819D FPSLI 11 04 Technical Specifications 2819D FPSLI 1 1 04 AMEL Section 6 Complete Schematics See the following pages the complete schematics and assembly drawings of the STK594 FPSLIC STK594 User Guide 6 1 Rev 2819D FPSLI 1 1 04 Yy0 L1 T18d G6 1 82 BELT 3PINY s sn VESMLS 11544 4 3 2 SVV1 A 10801
9. Reset Switches 2 6 2819D FPSLI 1 1 04 The AT94K FPSLIC devices exist in two different variations the AL and AX The AL variation is a 3 3V device manufactured on a 0 35u process while the AX variation has a 1 8V core manufactured on a 0 18y process The primary difference between the two variations is that the AX device requires a split power supply as the I Os are still pow ered from a 3 3V supply while the core operates at 1 8V The STK594 supports both AT94K variations If an AX variant is being used it is neces sary to supply the proper core to the AT94K device Figure 2 11 shows how to set the jumper to select the core voltage Figure 2 11 AT94K Core Voltage Selector AT94KAL AT94KAX m AL mi AL VDD l VDD f o X X An oscillator is included on the STK594 for supplying an additional clock to the AT94K FPSLIC device The XTAL switch selects if the oscillator is connected to the XTAL1 pin or whether the clock is provided by the STK500 Figure 2 12 shows a simplified block schematic on how this is implemented Figure 2 12 XTAL Block Schematic FPSLIC The reset switch found on the STK594 is connected to the AT94K s RESET pin When pressed the AT94K device will reset and initiate a configuration download from the con figuration memory The reset switch found on the STK500 is connected to the AVRRESET When pressed the embedded AVR microcontroller resets and be
10. more information on adjusting VTARGET from within AVR Studio consult section 5 3 5 1 of the STK500 User Guide available on the Atmel web site www atmel com Note t may be necessary to adjust the Vpp voltage see Split Power Supply Support on page 6 of this section for more information The STK594 should be connected to the STK500 expansion header 0 and 1 It is impor tant that the top module is connected in the correct orientation as shown in Figure 2 1 on page 2 The EXPANDO written on the STK594 top module should match the EXPANDO written beside the expansion header on the STK500 board 2 1 Rev 2819D FPSLI 1 1 04 Using the STK594 Top Module Figure 2 1 Connecting the STK594 to the STK500 Board Note Connecting the STK594 with the wrong orientation may damage the boards Note Do not mount the STK594 at the same time an AVR is mounted on the STK500 board 2 2 PORT Since the AT94K devices have additional ports not available on the STK500 these ports Connectors are located on the STK594 board The STK594 ports have the same pinout and func tionality as the ports on the STK500 board Since Port A to Port D are already present on the STK500 board they are not duplicated on the STK594 2 2 1 PORTE Figure 2 2 shows the pinout for the I O port headers Port E Figure 2 2 General I O Ports i 2 PEO PE PE2 PES PE4 PE5 PE6 PE7 GND vTG PORT E Note Port E is also present on the STK500 but only PEO to PE2 3
11. shows the steps available for designing with Atmel FPSLIC devices The red and blue arrows show the dependencies between the various stages of development This tutorial will only show the minimum steps in order to complete a design The remainder of the steps involves simulation and co verification For further information on simulation and co verification please consult the Quick Start Tutorial available on the Atmel web site FPSLIC STK594 User Guide AMEL 4 7 2819D FPSLI 11 04 Using System Designer 4 5 Assembling the The Atmel AVR Assembler translates assembly source code into object code The gen Microcontroller erated object code can then be used as an input to a simulator emulator such as the Source Code Atmel AVR JTAG In Circuit Emulator ICE or used to program the target device The Assembler generates fixed code allocations therefore no linking is necessary 1 Press the SW Compiler button to open the Atmel AVR Studio 2 Click on NO when prompted to create a new file The window to open an existing file opens up 3 Browse to the C SystemDesigner Designs STK594 directory and select STK594 ASM Figure 4 11 Open File stk594 asm Look in a stk534 al ex stk94 asm Tutorial asm File name stk534 asm Files of type Asm Files asm Cancel 4 Press Build and close the Atmel AVR Studio if assembly was successful Note If assembly was not successful make sure th
12. 441 0311 74025 Heilbronn Germany Fax 1 408 436 4314 Tel 49 71 31 67 0 49 71 31 67 2340 Regional Headquarters Microcontrollers Europe 2325 Orchard Parkway 1150 East Cheyenne Mtn Blvd Atmel Sarl San Jose CA 95131 USA Colorado Springs CO 80906 USA Route des Arsenaux 41 Tel 1 408 441 0311 Tel 1 719 576 3300 Case Postale 80 Fax 1 408 436 4314 Fax 1 719 540 1759 17777 La Chantrerie Biometrics Imaging Hi Rel MPU Tel 41 26 426 5555 BP 70602 High Speed Converters RF Datacom Fax 41 26 426 5500 44306 Nantes Cedex 3 France Avenue de Rochepleine Tel 33 2 40 18 18 18 BP 123 Asia Fax 33 2 40 18 19 60 38521 Saint Egreve Cedex France Room 1219 Tel 33 4 76 58 30 00 Chinachem Golden Plaza ASICIASSP Smart Cards Fax 33 4 76 58 34 80 77 Mody Road Tsimshatsui Zone Industrielle East Kowloon 12100 Rousset Cedex France Hong Kong Tel 33 4 42 53 60 00 Tel 852 2721 9778 Fax 33 4 42 53 60 01 Fax 852 2722 1369 1150 East Cheyenne Mtn Blvd Japan Colorado Springs CO 80906 USA 9F Tonetsu Shinkawa Bldg Tel 1 719 576 3300 1 24 8 Shinkawa Fax 1 719 540 1759 Chuo ku Tokyo 104 0033 Japan Scottish Enterprise Technology Park Tel 81 3 3523 3551 Maxwell Building Fax 81 3 3523 7581 East Kilbride G75 OQR Scotland Tel 44 1355 803 000 Fax 44 1355 242 743 Atmel Programmable SLI Hotline Literature Requests 408 436 4119 www atmel com literature Atmel Programmable SLI e mail fpslic 9 atmel co
13. L design see Figure 4 9 2819D FPSLI 1 1 04 Using System Designer Figure 4 9 Project Window F System Designer Tutorial api c SystemD esigner designs stk594 r ga on the parts below to view a specific flow chart that guides you through the more info gt gt 8 From the System Designer desktop click on the Part Graphic see Figure 4 9 to switch to the Design Flow Manager see Figure 4 10 4 6 AIMEL IMEL FPSLIC STK594 User Guide 2819D FPSLI 1 1 04 Figure 4 10 Design Flow Manager ASS Designer Tutorial apj c ASystemD esigner designs stk594 Project Edit Tools Options Help Using System Designer Project Tutorial api Y Tutorial apj 5 ATS4K40 25D0C HDL Synthesis c SystemDesigne A Software Compiler c SystemDes R Pre layout Coverification c Syste 2 FPGA Place and Router c Systen R Post layout Coverification c 1Syst TONO Part U1 AT94K40 25DQC Quick Flow Advanced Flow Device View Figaro IDS Log Part U1 AT94K40 25DOC toolflow set to Mentor Verilog Log Project Tutorial was saved in c SystemDesigner designs stk594 Tutorial apj ut 94 40 2500 Device Options AT94K Device Option Interface Connections AVR FPGA Interface Prelayout Coverification Pre layout Coverify Postlayout Coverification Post layout Coverify Compiler In Circuit Emulation JTAG ICE The Design Flow Manager
14. Quality sets the trade off between Figaro s speed and the efficiency of the Place amp Route result see the online help for further information b Use the default setting for Timing Driven Design Checking the Timing Driven Design box allows Figaro to take account of critical paths when per forming the Place 8 Route see the online help for further information c Press Compile once completed the Figaro IDS Compile button will turn green d Select Exitfrom the File menu when prompted to save your design select Yes 4 12 AIMEL FPSLIC STK594 User Guide 2819D FPSLI 11 04 Using System Designer 4 9 Bitstream The Device Programming Utility takes the outputs from both the FPGA and AVR compil Generation ers and generates a single programming file for use in configuring the AT94K device 1 Press Device Programming Utility to open the programming utility The FPSLIC Control Register Settings dialog opens see Figure 4 17 Figure 4 17 FPSLIC Control Register Settings Dialog FPSLIC Control Register Settings Lx FPGA Bitstream lite File Settings M Include FPGA Bitstream FPSLIC CR Settings c 5ystemDesigner designs stk594 counter Browse FPGA CR Settings AVR Hex V Include AVR Hex File OK c WEystemDesignertdesignststks94tstks94 r Browse Help r Data RAM Load Data RAM during configuration ACE Data Ram File Format Bitstream Download c Text Fi 7 sil mo
15. RT1 assigned to PortE 3 2 gt UART1 pads AVR ports I O drive B54 B55 AVR port D I O amp mA C 2 mA AVR port E I O EmA C 20mA 6 Press OK to generate the combined bitstream file FPSLIC CR Settings FPGA CR Settings Cancel Bitstream Download Program Configurator Density 1m Note lt is possible to generate a bitstream for only the FPGA or AVR as you may only want to program that portion of the FPSLIC device To include only the AVR HEX file simply uncheck the Include FPGA Bitstream box Programming only the FPGA portion can be done in a similar fashion AMEL FPSLIC STK594 User Guide Using System Designer 4 10 Programming The programming file generated by the Bitstream Generator is used to program the con and Design figuration memory When the FPSLIC requests configuration data after a Reset or Execution Power On Reset the data is clocked out serially 4 10 1 Hardware Setup Before programming the configurator and verifying the tutorial design a few prepara tions need to be performed prior to its execution on hardware 1 2 Figure 4 19 In System Programming 7 Connect the PC s parallel port to the 25 pin connector of the ATDH2225 Pro gramming Dongle Connect the 10 pin ISP header on the STK594 to the 10 pin ribbon cable of the ATDH2225 The ATDH2225 is keyed to assure proper orientation see Figure 4 19 39094s1 557 reuszdiv B
16. Start gt Programs gt Atmel gt ModelTech gt ModelSim If ModelSim launches without any licensing errors the ModelSim license has been successfully installed Launch LeonardoSpectrum from Start Programs Atmel Leonardo Spec trum Leonardo Spectrum If LeonardoSpectrum launches without any licensing errors then the LeonardoSpectrum license has been successfully installed You can access the trouble shooting guide from Start Programs Atmel Trouble Shooting Guide AMEL 2819D FPSLI 1 1 04 Installing System Designer 2819D FPSLI 1 1 04 AMEL 4 1 Preparing the Example Files Section 4 Using System Designer This tutorial will guide you through the required steps for designing and programming AT94K series devices using System Designer Before starting the tutorial a few preparations need to be performed 1 Download STK594 ZIP from the FPSLIC software page of the Atmel web site and copy STK594 ZIPtoC SystemDesigner Designs 2 Extract the contents of the STK594 ZTP file to C SystemDesigner Designs The contents of the zip file are shown in Table 4 1 Table 4 1 STK594 ZIP File Description AT94KDEF INC Atmel AVR Assembler AT94K FPSLIC Include File COUNTER PIN FPGA Pin Lock File COUNTER V Top Level FPGA Verilog Counter Source File COUNTER VHD Top Level FPGA VHDL Counter Source File STK594 ASM Atmel AVR Assembler Source File
17. System Designer 4 7 AVR FPGA Interface 4 10 2819D FPSLI 1 1 04 The AVR FPGA Interface dialog provides a means for making the connections between the embedded FPGA and AVR microcontroller 1 Press the AVR FPGA Interface button 2 Select counter and press OK when prompted for Top Level Entity The Select Ports dialog appears see Figure 4 14 Figure 4 14 Select Ports Dialog Select Ports x Input design ports 110 Select lines from AVR Ut Connect AWRloSelects FPGAlnterrupts Disconnect DataFromAVR DataToAVR Load ict File m AWRControls SRAMAddress Help DataFromSRAM DataToSRAM SRAMControls y FPGAClocks uru V Generate Template Test Bench file Uncheck this box if you have an existing test bench file Make sure to modify the existing test bench file to reflect any changes made to the current FPGA AVR Interface Sixteen select signals 8 select signals for AT94K05 devices are sent to the FPGA for addressing the peripherals implemented in the FPGA These signals are decoded from 4 WO registry addresses 3 Select the AVRloSelects tab on the right hand side of the dialog box 4 Select the LOAD signal from the Input Design Ports and then select IOSELAO from the AVRloSelects 5 Press Connect to connect the counter s LOAD signal to FPGA AVR I O Select 0 6 Connect the remaining inputs and outputs as shown in Table 4 2 Table 4 2 FPGA AVR Interface Connections
18. advanced users In addition to adding support for new devices it also adds new support for peripherals previously not supported by the STK500 An additional RS 232 port and a Two Wire Serial Interface are among the new features Figure 1 1 STK594 Top Module for STK500 m 1 1 Rev 2819D FPSLI 1 1 04 Introduction 1 1 Features M STK500 Compatible M AVR Studio and System Designer Compatible m Supports AT94KAL and AT94KAX Devices B Supports all Added Features in FPSLIC Devices B JTAG Connector for On chip Debugging Using JTAG ICE m Additional RS 232C Port with Available RTS CTS Handshake Lines m On board 32 kHz Crystal for Easy RTC Implementations 2819D FPSLI 1 1 04 AMEL 2 1 Preparing the STK500 for Use with the STK594 2 1 1 Adjusting VTARGET for the AT94K Devices 2 1 2 Connecting the STK594 to the STK500 Starter Kit FPSLIC STK594 User Guide Section 2 Using the STK594 Top Module Prior to using the STK594 with the STK500 it is necessary to make a few adjustments to the STK500 Starter Kit to allow for proper operation of Atmel s AT94K FPSLIC devices According to the AT94K Series datasheet the Voc operating voltage is specified where Vcc 3 0 Voc 3 6 Volts with respect to ground The STK594 board requires that the STK500 board supplies a Vec within the operating range for the AT94K devices Prior to using the STK594 board it is necessary to adjust the VTARGET to a value between 3 0 and 3 6V For
19. ctory path for your new project using the controls below When you are ready click Next to continue E YSystemDesignerWdesignsYstk5941Tutorial apj Browse DESIGNER SYSTEM FPSLIC STK594 User Guide AIMEL 4 3 2819D FPSLI 11 04 Using System Designer 4 Set the Project Directory to C SystemDesigner Designs STK594 name the project TUTORIAL and press Next The part selection window appears see Figure 4 5 Figure 4 5 New Project Wizard Window Step 3 of 6 What part do you want to use Choose a part for your project from the Part Number list below Architecture Part Number Any AT94K05 25DQC A 94 05 2500 Product Family 94505 2506 Any 4T94505 25DG1 94 10 25 Package 94 10 25 Any y 4T9410 2540C 94 10 25401 94 10 2580 94 10 258 1 94 10 2500 94 40 25 Any 7 y emen a 5 Select AT94K10AL 25DQC from the parts list as this is the part found on the STK594 development board and press Next The software tool flow window opens see Figure 4 6 Note 1 Some boards use AT94K40AL 25DQC devices SYSTEM DESIGNER Figure 4 6 New Project Wizard Window Step 4 of 6 What is the software toolflow for this part Please select a software toolset for part U1 amp T94K40 25DQC from the list below Toolflowy Mentor vHDL Mentor Werilog Mertor verilog Tools AT94K Device Options
20. e include file AT94KDEF INC is in the design directory Only AT94K devices with a J label support JTAG ICE debugging For design entry using assembly language consult the AT94K datasheet for a summary of instructions supported by the FPSLIC devices The complete AVR Instruction Set Nomenclature describes each instruction in detail and has been installed as part of the System Designer Tool The AVR Instruction Set Nomenclature and FPSLIC datasheet can be accessed from the Help menu from the System Designer window and choosing Online Resources 4 6 Synthesizing the 1 Synthesis translates the VHDL or Verilog source code into gate level technology FPGA Source specific file for use with the target FPGA Place and Route tool File 2 Press the Synthesis Tool button A dialog box to add VHDL files appears see Figure 4 12 Figure 4 12 Add VHDL Files Dialog Box VHDL files are not added to the HDL Synthesis Tool in the project tree view pane on the left hand side The VHDL files should be added in the bottom up order i e file with the top level entity should be selected last in the file selection browser Do you want to Add VHDL files now 2819D FPSLI 1 1 04 FPSLIC STK594 User Guide Using System Designer 3 Press yes A file selection window appears 4 Select COUNTER V and press Open LeonardoSpectrum opens 5 Leonardo automatically selects Atmel AT94K as the Technology and lists COUNTER V under Input Le
21. e you have installed System Designer proceed to the FPSLIC section of the Atmel web site and click on the Request License button alternatively the direct link for the license request page is http www atmel com atmel products prod39r htm Note The Serial Number is located on the white sticker on the underside of the STK594 board or on the System Designer case A MEL FPSLIC STK594 User Guide 3 4 2 Configuring the System Designer License 3 4 3 Testing the System Designer License 3 4 4 Troubleshooting FPSLIC STK594 User Guide 1 Installing System Designer Once you have received your System Designer license from Atmel place the file in the C SystemDesigner directory Launch the Mentor Graphics License Configuration Utility from Start gt Programs gt Atmel gt Mentor Graphics Licensing gt Configure Licensing Follow the on screen instructions When it prompts you to select Configuration Option choose 3 Define the Product License Location and press Next Use the full path and file name when defining the license location for example C SystemDesigner fpslic dat If you used a different path and or file name make the necessary changes Note f you are using Windows 95 98 Me it is necessary to reboot the machine prior to running the System Designer software Once you have configured your license you can test it by invoking the Mentor Graphics programs that require a license 1 Launch ModelSim from
22. em Programming Circuitry Size A Document Number CHVV5472 RevA Date Friday April 26 2002 Sheet 4 of 6 5 4 3 2 1 sojeuieuos ojojduio 2 0 11 1944 0618 3PINY s sn 69 5 11544 TP1 b 1 GND T POINT F VCC VDD TP2 p 1 VCC T POINT F TP3 B 1 VDD TPOINTF VIN VOUT ADJ GND LT1117 1 8 SOT Title STK594 Split Power Rail Circuitry Size A Document Number CHW5472 SIIJBWIBYIS ajojduio 0 11 194 06182 3PINY 19SN Y6SMLS 11544 BELT vcc C22 0 1 uF vec A C18 0 1 uF U4 CTS 9 8 CTS R2OUT R N gt RD 12 RXD amp RD R1OUT RAN PA _m 44 TXD TUN Tour 4 Ot uF RTS RIS 10 T2IN T20UT 1 C1 1er 5 C2 C2 2 V C20 amp T 0 1 uF V MAX3232 2 C21 0 1 uF CONNECTOR DB9 Title STK594 RS 232 Spare 2 Circuitry Size A Document Number CHW5472 Rev A Date Friday April 26 2002 Sheet 6 of 6 2 1 sojeuieuos ojojduio Complete Schematics 2819D FPSLI 1 1 04 ATMEL CONFIDENTIAL AlINEL KRANIN Atmel Corporation Atmel Operations 2325 Orchard Parkvvay Memory RF Automotive San Jose CA 95131 USA 2325 Orchard Parkway Theresienstrasse 2 Tel 1 408 441 0311 San Jose CA 95131 USA Postfach 3535 Fax 1 408 487 2600 Tel 1 408
23. es the option of having separate I O pins for the UARTs rather than sharing with the general purpose I O pins Figure 2 6 shows the pinout of a header for the dedicated UART pins Figure 2 6 UART Header 1 2 RXO TXO RX1 ee TX1 UART The AT94K device has an additional UART The RS 232 port on the STK594 board has in addition to the RXD and TXD lines support for RTS and CTS flow control Figure 2 7 shows a simplified block schematic on how this is implemented Note The UART in AT94K devices does not support hardware RTS or CTS control If such functionality is needed it must be implemented in software Figure 2 7 UART Block Schematic RS 232 Logic Level Converter lt RxD TxD b CTS RTS De RS232 SPARE2 ajo o a This UART can also be used from devices placed in the STK500 board Simply connect the appropriate port pins to RXD and TXD on the STK594 board Note If no software RTS CTS flow control is implemented a jumper shorting RTS and CTS will ensure correct communication with an external application that uses such flow control A MEL FPSLIC STK594 User Guide 2 7 Two Wire Serial Interface TWSI 2 7 1 Description of Configuration Memory Pins 2 8 External Interrupts FPSLIC STK594 User Guide Using the STK594 Top Module The AT94K device includes dedicated I O pins for the TWSI rather than sharing with the general purpose I O pins Fig
24. gg soz ON on 2 sania s 8 8 8 g a He EE 2 2 2 85 83 3 g a L H 8 8 Y E YAZ 5 85 83 E S 2 R 3 2 E 8 i 1 83 s 24 8 t 3 88 gt EE 53 p E 5 2 395 83 53 ii iis 2 HM 8 z z FPSLIC STK594 User Guide 6 3 2819D FPSLI 1 1 04 Complete Schematics T 930 1996 2002 92 HHdv Kepu aed ZLVSMHO J8quINN jusuinsoq g zis SjepeeH PESHLS ML Na 4389 3 WES vas gt VOYNOO gt gt Hsol 2410 Od LNI lo 10d lo zli3d o zl19d lo l1vd VOYNOO FPSLIC STK594 User Guide 6 4 2819D FPSLI 11 04 0 11 194 06182 3PINY 19SN VESMLS 11544 BELT 5 4 3 2 1 VCC VCC A gt DO cSCL K gt gt cSDA INIT RESET OE CEO cSER_EN SER EN CON lt lt CE VCC A AT17LV010 LAP R7 4K7 A 1 2 rx 3 4 rx GND z vcc x19 10 CON10A D1 RESET lt RESET 1 2 1 1N4001 C14 0 003 uF VCC SW 4PDT sw4 gt C15 0 1 uF o Title STK594 In Syst
25. gins execution at location 0000 A MEL FPSLIC STK594 User Guide AMEL 3 1 System Requirements FPSLIC STK594 User Guide Section 3 Installing System Designer System Designer is the ideal software platform for all AT94K FPSLIC development It includes an Editor an Assembler and a Debugger as its development tools for the embedded AVR development and also includes a Simulator Synthesizer and a Place and Route tool for FPGA development System Designer also includes a Co Verification suite powered by Mentor Graphics allowing for step by step simulation of the FPGA and AVR design concurrently For a single user system System Designer requires a personal computer equipped as follows B CD ROM Drive B 250 Mbyte Minimum Hard Drive B 128 Mbyte RAM m Parallel Interface Port m Windows 95 98 2000 Me or WindowsNT 4 0 m Network Interface Card or Security Dongle The software security dongle is used to generate a unique HOSTID for systems without a network interface card The security dongle is connected to the PC through the parallel port interface It is possible to configure a floating network license through the security dongle The security dongle allows users to use the software dongle on different machines by removing and placing the dongle on other machines 3 1 Rev 2819D FPSLI 1 1 04 Installing System Designer 3 2 System Designer Installation 3 3 Configuration Programming System CPS Installation 3
26. h programming session In this version of CPS Options HEX values are only appended to the BST output Device ATT7LVO10 A em y files which have been partitioned The output file Low must be of the form lt file gt bst ar R x COMM Pot LPT Fast m vw Reset Polarity Data Rate FPGA Family A2 Bit Level Low r Console Start Procedure Restore Defaults View Log File 2 Select P Partition program and verify from an Atmel file under Procedure 3 Select FPSLIC COUNTER BST under nput File by browsing to C SystemDesigner Designs stk594 4 Select OUT BST under Output File 5 Select AT17LVO10 A 1M under Device 6 Select Low under Reset Polarity 7 Select AT40K Cypress under FPGA Family 8 Select LPT1 under COMM Port assuming LPT1 is the parallel port connected to the ATDH2225 programming adapter 9 Select Slow under Data Rate 10 Select Low under A2 Bit Level 11 Press Start Procedure When finished a statistics report will be provided in the CPS log window Note If the CPS utility is being launched for the first time the clock calibration dialog will be displayed Press Yes to proceed with calibration and select High for accurate calibration The Checksum is the number of data bits found in the BST file and it can be used to check if the data is corrupted during programming AMEL FPSLIC STK594 User
27. least significant bits are accessible To access all Port E bits the connector on the STK594 must be used 2819D FPSLI 11 04 FPSLIC STK594 User Guide 2 3 2 4 AT94K Devices JTAG Connector FPSLIC STK594 User Guide Using the STK594 Top Module Programmingthe The FPSLIC configuration process involves configuring the FPGA the AVR program code and the FPSLIC data memory This configuration requires a single bitstream that configures the FPGA the embedded AVR Program SRAM and the FPSLIC Data SRAM The combined bitstream is automatically generated by the Bitstream Generator a System Designer software utility After a reset and the internal clearing of the configuration data the FPSLIC device self initiates configuration The Master mode uses an internal oscillator to provide the Con figuration Clock CCLK for clocking the external EEPROM configurator which contains the configuration data After auto configuration is complete re configuration can be initiated manually by the user if needed Note The AT94K devices also support Self Programming For more information on this topic refer to the Code Self Modify application note available on the Atmel web site Note The AT94K devices also support Cache Logic Configuration For more infor mation on this topic refer to the Cache Logic Configuration application note available on the Atmel web site For more details on programming procedures refer to Secti
28. m FAQ Available on web site Disclaimer The information in this document is provided in connection with Atmel products No license express or implied by estoppel or otherwise to any intellectual property right is granted by this document or in connection with the sale of Atmel products EXCEPT AS SET FORTH IN ATMELS TERMS AND CONDI TIONS OF SALE LOCATED ON ATMELS WEB SITE ATMEL ASSUMES NO LIABILITY WHATSOEVER AND DISCLAIMS ANY EXPRESS IMPLIED OR STATUTORY WARRANTY RELATING TO ITS PRODUCTS INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTY OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NON INFRINGEMENT IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT INDIRECT CONSEQUENTIAL PUNITIVE SPECIAL OR INCIDEN TAL DAMAGES INCLUDING WITHOUT LIMITATION DAMAGES FOR LOSS OF PROFITS BUSINESS INTERRUPTION OR LOSS OF INFORMATION ARISING OUT OF THE USE OR INABILITY TO USE THIS DOCUMENT EVEN IF ATMEL HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES Atmel makes no representations or warranties with respect to the accuracy or completeness of the contents of this document and reserves the right to make changes to specifications and product descriptions at any time without notice Atmel does not make any commitment to update the information contained herein Atmel s products are not intended authorized or warranted for use as components in applications intended to support or sustain life O Atmel Corporation 2004 All rights reserved Atmel am
29. mie FPSLIC STK594 User Guide AMEL T AMEL FPSLIC STK594 User Guide Table of Contents Section 1 os AAA II agades 1 1 Section 2 Using the STK594 Top Module seen 2 1 2 1 Preparing the STK500 for Use with the 5 594 222222222 2 1 2 1 4 Adjusting VTARGET for the AT94K 1 65 222 2 1 2 1 2 Connecting the STK594 to the STK500 Starter Kit 2 1 2 2 PORT Conn cGlOtS iiuiis aee teris Diese ala 2 2 E e H 2 2 2 3 Programming the AT94K 1 5 2 3 24 TAG Connector ee Hrn 2 3 225 TOSC kj 2 4 2 6 Universal Asynchronous Receiver Transmitter UART 2 4 2 6 1 Second RS 2326 POIt aaa di 2 4 2 7 Two Wire Serial Interface 9 2 5 2 7 1 Description of Configuration Memory Pins 2 5 2 8 External Interrupts dara 2 5 2 9 Split Power Supply 2 6 2 10 XTAL Switch E 2 6 2411 Reset SWITCHES iia ie 2 6 Section 3 Installing System Designer a 3 1 3 1 System 15 3 1 3 3 Configuration Programming System CPS Installation 3 2 3 4 System Desig
30. ner 51 3 2 3 4 4 Requesting a System Designer 5 3 2 3 4 2 Configuring the System Designer License 3 3 3 4 8 Testing the System Designer 4 5 3 3 3 4 4 Troubleshooting sseeseeeeenenennn ene 3 3 Section 4 Using System Designer a aaa ee 4 1 4 1 Preparing the Example 5 4 1 43 Design FIOW seen 4 2 4 6 Synthesizing the FPGA Source 4 8 4 8 FPGA Place and 4 11 1 2819D FPSLI 11 04 Table of Contents 4 10 1 Hardware 4 15 4 10 2 Software Setup 4 16 Section 5 Technical Specifications una 5 1 Section 6 Complete Schematics sintio Ra esum 6 1 2819D FPSLI 11 04 FPSLIC STK594 User Guide ATMEL FPSLIC STK594 User Guide Section 1 Introduction The STK594 board is a top module designed to add AT94K FPSLIC support to the STK500 development board With this board the STK500 is extended to support all cur rent AT94K FPSLIC devices in a single development environment The STK594 includes connectors jumpers and hardware allowing full utilization of the new features of the FPSLIC family see Figure 1 1 This user guide acts as a general getting started guide as well as a complete technical reference for
31. o verification please consult the FPSLIC application notes available on the Atmel web site Figure 4 2 outlines the design flow followed in this tutorial For more information on a specific step consult the appropriate section within this tutorial Figure 4 2 Design Flow Microcontroller Assembly HDL Synthesis AVR lt gt FPGA FPGA Bitstream Interface Place amp Route Generation AMEL FPSLIC STK594 User Guide Using System Designer 4 4 Creating a The New Project Wizard allows you to choose your Project Directory Target Device Project and desired Tool Flow 1 Launch System Designer from the desktop icon or by pointing to Start gt Pro grams gt Atmel gt SystemDesigner 2 Create a new project by selecting New from the Project menu and then pressing the New Project Wizard button see Figure 4 3 Figure 4 3 New Project Wizard Window Step 1 of 6 Welcome to the New Project wizard The New Project wizard will guide you in the creation of your new System Designer project The steps that follow will include 1 Creating a project file 2 Selecting the parts for use with your project 3 Selecting the software tool sets for use with each part SYSTEM DESIGNER 3 Press Next The window to create a project file opens see Figure 4 4 Figure 4 4 New Project Wizard Window Step 2 of 6 New Project Wizard Step 2 of 6 Create Project File Select a name and dire
32. on 4 10 The JTAG connector is intended for the AT94K devices that have a built in JTAG inter face The pinout of the JTAG connector is shown in Figure 2 3 and is compliant with the pinout of the JTAG ICE available from Atmel Connecting a JTAG ICE to this connector allows On chip Debugging of the AT94K devices More information about the JTAG ICE and On chip Debugging can be found in the AVR JTAG ICE user guide available on the Atmel web site Figure 2 3 JTAG Connector 1 2 TCK GND TDO VTG TMS RST VTG N C TDI GND JTAG Note To determine if your AT94K device supports JTAG Debug examine the date code Any parts with a J after their date code support JTAG Example 4201J Figure 2 4 shows how to connect the JTAG ICE probe on the STK594 board Figure 2 4 Connecting JTAG ICE to the STK594 AMEL 2819D FPSLI 1 1 04 Using the STK594 Top Module 2 5 TOSC Switch 2 6 Universal Asynchronous Receiver Transmitter UART 2 6 1 Second RS 232C Port 2 4 2819D FPSLI 1 1 04 The AT94K device provides dedicated I O pins for TOSC1 and TOSC2 rather than sharing with the general purpose I O pins The TOSC switch selects whether or not the 32 kHz crystal is connected to the pins of the device Figure 2 5 shows a simplified block schematic on how this is implemented Figure 2 5 TOSC Block Schematic FPSLIC 32 kHz 40 o o TOSC Switch Unlike traditional AVR microcontrollers the AT94K device provid
33. onardo also lists COUNTER edf under Output 6 Press Run Flow Figure 4 13 shows a successful synthesis Figure 4 13 Leonardo Spectrum Successful Synthesis Mentor Graphics LeonardoSpectrum for Atmel Information Read Only File Edit View Tools Window Help lax ALTRA xl reg_g 7 D data arrival tine Technology inpu Constraints Optimize Output Click ASIC or FPGA to extend device tree and select a library Click c selected technology logo to open the vendor website Use all default advanced technology options under Advanced Settings Press Ar data required tine 5 ijjyYYYbi EO data required time data arrival time AIMEL amp Atmel AT40K 6 2 ATBKD4 ATIAK Design summary in file c SystemDesigner d Saving the design database in c SystemDesi Writing file c SystenDesigner designs stk5 Writing XDB version 1999 1 Calling set atmel eqn to set up writing Equ write c SystemDesigner designs stk594 coun Writing file c SystenDesigner designs stk5 CPU time taken for this run was 0 95 sec Run Successfully Ended On Wed Oct 27 12 42 0 Info Finished Synthesis run v DI Technology Settings A Advanced Settings 3 Ready Working Directory designs stk594 Ln 11 Col3 2 7 Close Leonardo Spectrum when prompted to save your project press No 2819D FPSLI 11 04 Using
34. or AT17 Devices This will install the CPS utility which is used to program the AT17 and ATFS series configu ration memories found on the STK594 Note When installing the CPS utility it is necessary to install the software in an account with Administrator privileges if the operating system is WindowsNT or Windows 2000 XP The licensing of System Designer is for the Mentor Graphics tools You can use System Designer without a valid license however you will not be able to use ModelSim LeonardoSpectrum or Co Verification The typical license is based on the hostID of your Network Interface Card NIC If you prefer to use a dongle based license it is necessary that you purchase a Security Don gle from Atmel Atmel Part Number ATDH94DNG The instructions below describe the configuration of a NIC based license If you request a dongle based license you will receive instructions on how to configure the license with the dongle If you wish to use a single license for multiple machines it is necessary to purchase a Security Dongle Prior to obtaining a license for System Designer it is necessary to first install the System Designer software suite During installation System Designer creates the file LMUTIL TXT which is found in the C SystemDesigner ETC directory assuming a default installation The LMUTIL TXT file contains the hostID of your NIC and is com posed of a combination of twelve alphanumeric characters Onc
35. p logo and combinations thereof and others are registered trademarks and Everywhere You Are and others are the trademarks of Atmel Corporation or its subsidiaries Mentor Graphics Leonardo LeonardoSpectrum and ModelSim are either registered trademarks or trademarks of Mentor Graphics Corporation or its subsidiaries Windows Windows NT are registered trademarks of Microsoft Corporation Other terms and product names may be trademarks of oth ers Printed on recycled paper 2819D FPSLI 1 1 04 xM
36. rnar m Program Configurato Output Bitstream File Density c SystemDesigneridesignsistk594fpslic_c Browse 2 Check the nclude FPGA Bitstream box and select COUNTER BST by pressing Browse 3 Check the Include AVR Hex File box and select STK594 HEX by pressing Browse 4 Select the FPSLIC Control Register Settings tab and use the default settings see Figure 4 18 5 Be sure to uncheck the Program Configurator option under the Bitstream Down load section of the FPSLIC Control Register Settings tab FPSLIC STK594 User Guide AIMEL 4 13 2819D FPSLI 1 1 04 Using System Designer 4 14 2819D FPSLI 1 1 04 Figure 4 18 Control Register Settings Dialog FPSLIC Control Register Settings ontrol Registers mi B26 On Chip Debug Enable B27 JTAG Enable 635 AVR Reset Pin Enabled T B36 Allow writes to AYR Program SRAM mi B37 Allow over write AYR Program SRAM Bootblock V 856 XTAL Pad Bias Resistor Enabled m B57 TOSC Pad Bias Resistor Enabled m B62 Enable Cache Writes to FPGA by AVR Vv B63 Enable FPGA to ReadiWrite to Data SRAM External Interrupts 548 B51 Ext INTO driven by Port 4 INTPO pad Ext INT1 driven by PortE lt 5 gt INTP1 pad Ext INT2 driven by PortE lt 6 gt INTP2 pad Ext INT3 driven by PortE lt 7 gt INTP3 pad rUART Pins B52 B53 UARTO assigned to C PortE lt 1 0 UARTO pads UA
37. ure 2 8 shows the pinout of a header for the dedicated TWSI pins Figure 2 8 TWSI Header 12 SDA m SCL TWSI An AT17LV010 10CC 1 Mbit Configuration Memory is included on the STK594 for sup plying the AT94K FPSLIC device with its configuration data as well as for non volatile data storage The configurator is a high density EEPROM with a TWSI interface A detailed datasheet of the Configuration Memory can be obtained from the Atmel web site The configurator can be connected to the I O pins of the embedded AVR microcontrol ler The 4 pin header marked CONFIG can be used for connecting the TWSI interface of the configurator to the I O pins of the target AVR microcontroller Two wire cables are included with the STK500 for connecting the configurator to the I O pins Figure 2 9 shows the pinout of a header for the Configuration Memory pins Figure 2 9 Configuration Memory Header t 2 cSDA me cSCL CSER_EN lee N C CONFIG Unlike traditional AVR microcontrollers the AT94K device provides the option of having separate I O pins for the External Interrupts rather than sharing with the general purpose I O pins Figure 2 10 shows the pinout of a header for the dedicated External Interrupt pins Figure 2 10 External Interrupt Header i2 INTPO M e INTP1 INTP2 l INTP3 EXT 2819D FPSLI 1 1 04 Using the STK594 Top Module 2 9 Split Power Supply Support 2 10 XTAL Switch 2 11
38. ure 4 16 Figure 4 16 Figaro Batch Options Dialog Figaro Batch Options Iof x Design Constraints Click here to edit assign pin locks gt Assign Pin Locks Click here to import constraints from file gt Import Constraints r Place and Route Quality 1 C2 C3 C4 05 C Auto Timing Driven Design Click on Compile button to run through the entire FPGA design flow To run individual steps in the design flow or to do manual place and route click on OK and select Window New Compile window on Figaro desktop Compile Help The Figaro Batch Options allows for the setting of various Figaro FPGA compiler constraints This includes I O Pin Locking I O Pad Attributes and Place amp Route quality effort levels 2819D FPSLI 1 1 04 Using System Designer Design Constraints a Press Import Constraints this opens the Import Constraints window Select Part pinout pin from the List files of the Type drop down list Alternatively we could have used the Assign Pin Locks GUI to perform the pin locking but it is not required for this design b Select COUNTER10 PIN and press OK Note f the board is soldered with the AT94K40AL 25DQC device select COUNTER40 PIN and press OK c Press Import Constraints again select IO Pad Attr att from the List files of the Type drop down list and then select the COUNTER ATT and press OK Place and Route a Use the default setting for Quality
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