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Xilinx UG334 Spartan-3A/3AN Starter Kit Board User Guide

1. 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 6 SLEW SLOW Figure 11 3 UCF Location Constraints for Flash Data I O Pins Figure 11 4 provides the UCF constraints for the Flash control pins including the I O pin assignment and the I O standard used NET NF_BYTE LOC NET NF_CE OC NET NF OE LOC NET NF RP LOC NET NF STS LOC NET NF WE LOC NET NF WP LOC Figure 11 4 Y21 W20 W19 R22 p22 AA22 E14 IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 DRIVE DRIVE DRIVE DRIVE PULLUP DRIVE DRIVE 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW 4 SLEW SLOW i D 4 SLEW SLOW 4 SLEW SLOW UCF Location Constraints for Flash Control Pins Setting the FPGA Mode Select Pins To configure the FPGA from NOR Flash set the FPGA configuration mode pins for BPI Up mode as shown in Table 11 3 The Spartan 3A 3AN FPGA families do not support the BPI Down mode that is available in the Spartan 3E FPGA family Table 11 3 Selecting BPI Up Configuration Mode J26 Also be sur
2. After Configuration Jumper J1 SPI Mode Atmel AT45DB161D STMicro M25P16 Setting Configuration Source Slave Select Signal Slave Select Signal Atmel SPI_SS_B AT45DB161D Y4 N A STMicro SPI_SS_B M25P16 DS YA Atmel SPI SS B ALT SS B AT45DB161D Y4 Y5 STMicro ALT_SS_B SPI_SS_B M25P16 Y5 Y4 None None None Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 93 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX 94 Shared SPI Flash and Platform Flash Data Line The SPI_MISO signal from the two SPI Flash PROMs is shared with data output signals from the parallel NOR Flash PROM and the serial output from the Platform Flash PROM as shown in Table 12 3 To avoid contention the FPGA application must ensure that only one data source is active at any time Table 12 3 Possible Potential Competing Devices on SPI_MISO NF_D lt 0 gt Data Signal or Disabled Device Disable Value Jumper Jumper J46 Platform Flash PROM Set to Disabled or Enable FPGA_INIT_B during Configuration as shown in Table 4 2 page 40 FPGA_INIT_B has no effect If setto Always Enabled then FPGA_INIT_B must be 1 SPI_SS_B SPI Flash PROM selected by 1 Jumper J1 as shown in Table 12 2 page 93 ALT_SS_B SPI Flash PROM selected by 1 Jumper J1 as shown in Table 12 2 page 93 NF_CE Parallel Flash PROM NF_CE 1orNF_OE 1 NF_OE Jumper Settings to Configure FPGA from Sel
3. Power control switch Power on status LED ay renee HERO ect xtemal 120 c Supply to FPGA o REG2_ SDA AS O Ba y 2 Supply to FPGA DDR2 SDRAM h A core VCCAUX EN REGI_SCL 1C19 Supply to FPGA REG1 SDA VO Banks 0 1 2 Y Em Supply to FPGA core VCCINT UG330 cx 01 021507 Figure 17 1 Spartan 3A 3AN Starter Kit Board Voltage Supplies The Spartan 3A 3AN Starter Kit board requires a 5 0V DC voltage input typically supplied by the AC wall adapter included with the kit However there is also a provision to connect the board directly to a 5 0V DC supply using through hole mounting solder pads The AC wall adapter must be a regulated 5 0V DC supply as supplied with the kit Some components and interfaces on the board such as the LCD character display and the PS 2 port are powered directly from the 5 0V supply rail Caution Connect either the AC wall adapter OR use the through hole mounting pads but not both The 5 0V input voltage is then converted to the other supply voltages required by the board components as summarized in Table 17 1 All non 5V voltages are supplied by two space efficient and cost effective National Semiconductor LP3906 Quad Output voltage Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 137 UG334 v1 0 May 28 2007 Chapter 17 Voltage Supplies 138 XILINX regulators Each regulator incorporates two high current switching buck regulators and two
4. IOSTANDARD IOSTANDARD SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II SSTL18 II Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 www xilinx com 113 Chapter 13 DDR2 SDRAM XILINX Reserve FPGA Veer Pins Five pins in I O Bank 3 are dedicated as voltage reference inputs Vpgg These pins cannot be used for general purpose I Os in a design Prohibit the software from using these pins with the constraints provided in Figure 13 5 Prohibit VREF pins on FPGA I O Bank 3 CONFIG PROHIBIT H7 CONFIG PROHIBIT J1 CONFIG PROHIBIT J8 CONFIG PROHIBIT L8 CONFIG PROHIBIT N1 CONFIG PROHIBIT R6 CONFIG PROHIBIT T1 CONFIG PROHIBIT T6 Figure 13 5 UCF Location Constraints for FPGA Vpgf Pins Special Layout Recommendations The Xilinx Memory Interface Generator MIG tool version 1 7 and later generates DDR2 SDRAM interfaces for Spartan 3A and Spartan 3AN FPGAs The MIG implementation leverages the FPGA s local clocking resources to capture the DDR2 SDRAM read data Consequen
5. The voltage on a specific output is generally described in Equation 10 1 The reference voltage VREFERENCE is different between the four DAC outputs Channels A and B use a 3 3V reference voltage Channels C and D have a separate reference voltage nominally also 3 3V supplied by the LP3906 regulator designated as IC18 The reference voltage for Channels C and D can be modified as described in I2C Voltage Adjustment Interface page 140 The reference voltages themselves have a 15 tolerance so there are slight corresponding variances in the output voltage D 11 0 ouT 4096 VREFERENCE Equation 10 1 UCF Location Constraints Figure 10 5 provides the UCF constraints for the DAC interface including the I O pin assignment and the I O standard used NET SPI MOSI LOC AB14 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET SPI SCK LOC AA20 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET DAC CS LOC w7 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET DAC CLR LOC AB13 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET DAC OUT LOC V7 IOSTANDARD LVTTL Figure 10 5 UCF Location Constraints for the DAC Interface Related Resources 82 Refer to the following links for additional information e LTC2624 Quad DAC Data Sheet http www linear com pc downloadDocument do navId H0 C1 C1155 C1005 C1156 P2048 D2170 e Xilinx PicoBlaze Soft Processor h
6. Double click Program Note Step 18 occurs later 14 Click the Programming Properties option under Category as shown in Figure 12 18 Programming Properties Ea 15 16 17 18 UG332_c4_29 032907 Figure 12 18 SPI PROM Programming Options Check Verify Unchecking Verify reduces programming time but the iMPACT software can only guarantee correct programming for a verified PROM Check Erase Before Programming Unchecking the Erase option reduces programming time However Xilinx recommends erasing the PROM when downloading a new FPGA bitstream Click OK The iMPACT software indicates successful programming as shown in Figure 12 18 The FPGA is configured with the new programming file Related Resources Refer to the following links for additional information 106 Xilinx Parallel Cable IV with Flying Leads www xilinx com onlinestore program_solutions htm pc Digilent JTAG3 Programming Cable www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Cables amp Cat Cable Atmel AT45DB161D DataFlash Data Sheet www atmel com dyn resources prod_documents doc3500 pdf STMicroelectronics M25P16 SPI Serial Flash Data Sheet www st com stonline books pdf docs 10027 pdf AN1579 Compatibility between the SO8 Package and the MLP Package for the M25Pxx in Your Application www st com stonline products literature an 9540 pdf Atmel SPI Serial Flash Programmer via RS 232 Reference Design
7. Auxiliary Clock Oscillator Socket A 133 MHz clock oscillator is installed in the auxiliary clock oscillator socket The provided eight pin socket accepts clock oscillators that fit the eight pin DIP 8DIP footprint Substitute the oscillator in this socket if the FPGA application requires a frequency other than 50 MHz or 133 MHz Alternatively use the FPGA s Digital Clock Manager DCM to generate or synthesize other frequencies from the on board 50 MHz or 133 MHz oscillator Caution Be aware of the pin 1 orientation on the crystal oscillator when installing it in the associated socket SMA Clock Input or Output Connector To provide a clock from an external source connect the input clock signal to the SMA connector The FPGA can also generate a single ended clock output or other high speed signal on the SMA clock connector for an external device UCF Constraints The clock input sources require two different types of constraints The location constraints define the I O pin assignments and I O standards The period constraints define the clock period and consequently the clock frequency and the duty cycle of the incoming clock signal Location Figure 3 2 provides the UCF constraints for the three clock input sources including the I O pin assignment and the I O standard used 34 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Related Resources NET CLK_50MHZ LOC E12
8. LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 35 gt LOC L19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 36 gt LOC L18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 37 gt LOC M20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 38 gt LOC M18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 39 gt LOC L20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 40 gt LOC P20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 Figure 15 3 UCF Location Constraints for 100 Pin Hirose FX2 Connector Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 125 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors XILINX Differential I O Connectors The Spartan 3A 3AN Starter Kit board includes stake pin headers with excellent signal integrity and matched impedance traces to demonstrate high performance differential I O Each differential pair supports approximately 600 Mbits per second Mbps data rates All I O pairs support differential input termination DIFF TERM as described in the Spartan 3A and Spartan 3AN data sheets The board is primarily designed to support loopback operations using a standard 34 pin socket to socket cable The two differential I O headers shown in Figure 15 1 page 121 consist of a 2x17 array of stake pins arrange on 0 1 inch centers The headers are not keyed Groun
9. The SPI bus transaction starts when the FPGA asserts AMP CS Low see Figure 9 4 The amplifier captures serial data on SPI MOSI on the rising edge of the SPI SCK clock signal The amplifier presents serial data on AMP_DOUT on the falling edge of SPI SCK AMP CS 130 50 SPI_SCK 30 1 1 1 1 l spi mosi 7 WU s EI E EN from FPGA i 85 max j m_i AMP DoUT __ Previous AA 6 AMOR 5 AM 4 AMAA 3 OA 2 MA All timing is minimum in nanoseconds unless otherwise noted TOR Figure 9 4 SPI Timing When Communicating with Amplifier The amplifier interface is relatively slow supporting only about a 10 MHz clock frequency 74 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Analog to Digital Converter ADC UCF Location Constraints Figure 9 5 provides the User Constraint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET SPI MOSI LOC AB14 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET AMP CS LOC W6 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET SPI_SCK LOC AA20 IOSTANDARD LVTTL SLEW SLOW DRIVE 12 NET AMP SHDN LOC W15 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET AMP_DOUT LOC T7 IOSTANDARD LVTTL Figure 9 5 UCF Location Constraints for the Pre amplifier Interface AMP Analog to Digital Converter ADC The LTC140
10. 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three eight bit data fields contain movement data as shown in Figure 8 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 kHz Mouse status byte Roy X direction byte m Y direction byte NNI T TI Rester N N Start bit Idle state 68 aaa pape pepe eee ebay T y di Stop bit Stop bit Stop bit Start bit Start bit Idle state UG330 c8 04 032007 Figure 8 4 PS 2 Mouse Transaction A PS 2 style mouse employs a relative coordinate system see Figure 8 5 wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y field and moving it down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG230_c8_05_021806 Figure 8 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represents the rate of mouse movement The larger the value the faster the mouse is moving The XV
11. A SD_DQ7 H2 SD_DQ6 K4 SD_DQ5 L1 SD DO4 L5 SD DOQ3 L3 SD DQ2 K1 SD DO1 K5 SD DQO H1 SD BA2 P5 Bank address inputs SD_BA1 R3 SD_BAO P3 SD_RAS M3 Command inputs SD_CAS M4 SD_WE N4 SD_CK_N M2 Differential clock input E SD_CK_P M1 8 SD_CKE N3 Active High clock enable input SD_CS M5 Active Low chip select input SD_UDM E3 Data Mask Upper and Lower data masks SD_LDM J3 SD_UDQS_N J5 Upper differential data strobe SD_UDQS_P K6 SD_LDOS_N K2 Lower differential data strobe SD_LDOS_P K3 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 111 UG334 v1 0 May 28 2007 Chapter 13 DDR2 SDRAM XILINX Table 13 1 FPGA to DDR2 SDRAM Connections Continued Category Miscellaneous DDR2SDRAM FPGA Pin Signal Name Number Function SD_LOOP_IN H4 I O self calibration loop Direction can be SD LOOP OUT H reversed if more convenient in the FPGA 0U application SD ODT P1 DDR2 SDRAM on device termination control UCF Location Constraints Address Figure 13 2 provides the User Constraint File UCF constraints for the DDR2 SDRAM address pins including the I O pin assignment and the I O standard used NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S NET S D_A lt 15 gt LOC D A 14 LOC D_A lt 13 gt LOC D A 12 LOC D_A lt 11 gt LOC D_A lt 10 gt LOC D_A lt 9 gt LOC D_A
12. FGG484 e Spartan 3AN Starter Kit Board Xilinx 700K gate XC3S700AN Spartan 3AN nonvolatile FPGA in the Pb free 484 ball BGA package FGG484 Internal 8 Mbit In System Flash memory Store FPGA configuration bitstream or nonvolatile data e 4 Mbit Xilinx Platform Flash configuration PROM e 64 MByte 512 Mbit of DDR2 SDRAM 32Mx16 data interface e 4 MByte 32 Mbit of parallel NOR Flash Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 19 UG334 v1 0 May 28 2007 20 Chapter 1 Introduction and Overview XILINX FPGA configuration storage MicroBlaze code storage shadowing x8 or x16 data interface after configuration Two 16 Mbit SPI serial Flash STMicroelectronics and Atmel DataFlash serial architectures FPGA configuration storage Supports single configuration bitstream or multiple MultiBoot configuration bitstreams Nonvolatile data storage e MicroBlaze code shadowing Two line 16 character LCD screen PS 2 port Supports PS 2 compatible mouse or keyboard Supports both mouse and keyboard using a Y splitter cable not included VGA display port 12 bit color 10 100 Ethernet PHY requires Ethernet MAC in FPGA Two nine pin RS 232 ports DTE and DCE style On board USB based programming solution FPGA download debug SPI serial Flash in system direct programming 50 MHz clock oscillator 8 pin DIP socket for second oscillator SMA connector for clock inputs or
13. Figure 2 4 UCF Constraints to Enable Suspend Mode For more information on Suspend mode see the following application note e XAPP480 Using Suspend Mode in Spartan 3 Generation FPGAs www xilinx com bvdocs appnotes xapp480 pdf 26 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Push Button Switches Push Button Switches Locations and Labels The Spartan 3A 3AN Starter Kit board has four momentary contact push button switches shown in Figure 2 5 The push buttons are located in the lower right corner of the board and are labeled BIN_NORTH BTN EAST BTN SOUTH and BTN WEST The FPGA pins that connect to the push buttons appear in parentheses in Figure 2 5 and the associated UCF is listed in Figure 2 7 Rotary Push Button Switch ROT A T13 Requires an internal pull up BTN NORTH ROT B R14 Requires an internal pull up T14 ROT CENTER R13 Requires an internal pull down BTN WEST BTN EAST U15 T16 Press Button for OvLegie I BTN SOUTH T1 5 UG334 c2 05 052407 Notes 1 All BTN push button inputs require an internal pull down resistor Figure 2 5 Four Push Button Switches Surround the Rotary Push Button Switch Operation Pressing a push button connects the associated FPGA pin to 3 3V as shown in Figure 2 6 Use an internal pull down resistor within the FPGA pin to generate a logic Low when the button is not pressed Figure 2 7 shows how to specify a pull d
14. G10 Receive Data from the PHY E RXD 3 H9 E_RXD lt 2 gt G9 E_RXD lt 1 gt G8 E_RXD lt 0 gt G7 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX MicroBlaze Ethernet IP Cores Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY Continued Signal Name no Function E_RX_DV H10 Receive Data Valid E_RX_CLK C12 Receive Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E_CRS H12 Carrier Sense E_COL G12 MII Collision Detect E_MDC D10 Management Clock Serial management clock E_MDIO E10 Management Data Input Output E_NRST D15 Active Low Reset MicroBlaze Ethernet IP Cores The Ethernet PHY is primarily intended for use with MicroBlaze applications As such an Ethernet MAC is part of the EDK Platform Studio s Base System Builder Both the full Ethernet MAC and the Lite version are available for evaluation The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications that do not require support for interrupts back to back data transfers and statistics counters The Ethernet MAC core requires design constraints to meet the required performance Refer to the OPB Ethernet MAC data sheet v1 02 for details The OPB clock frequency must be 65 MHz or higher for 100 Mbps Ethernet operations and 6 5 MHz or faster for 10 Mbps Ethernet operations The hardware evaluation versions of the Ethernet MAC cores
15. IOSTANDARD LVCMOS33 NET CLK_AUX LOC V12 IOSTANDARD LVCMOS33 NET CLK SMA LOC U12 IOSTANDARD LVCMOS33 Figure 3 2 UCF Location Constraints for Clock Sources Clock Period Constraints The Xilinx ISE development software uses timing driven logic placement and routing Set the clock PERIOD constraint as appropriate An example constraint appears in Figure 3 3 for the on board 50 MHz clock oscillator The CLK_50MHZ frequency is 50 MHz which equates to a 20 ns period The output duty cycle from the oscillator ranges between 40 to 60 Define clock period for 50 MHz oscillator NET CLK_50MHZ PERIOD 20 0ns HIGH 40 Figure 3 3 UCF Clock PERIOD Constraint Related Resources Refer to the following links for additional information e Epson SG 8002JF Series Oscillator Data Sheet 50 MHz Oscillator www eea epson com go Prod_Admin Categories EEA QD Crystal_Oscillators prog_oscillators go Resources TestC2 SG8002JF Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 35 UG334 v1 0 May 28 2007 Chapter 3 Clock Sources 36 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 lt XILINX Chapter 4 FPGA Configuration Options The Spartan 3A 3AN Starter Kit board supports a variety of FPGA configuration options Program the Spartan 3AN internal SPI Flash memory then configure the FPGA at power up This option is not
16. Press Knob Scroll Rotate Graphic Press Knob 3x 0 o For Boot Menu o c x 9 3 Press Knob o Scroll Scale Graphic 5 Scale a Press Knob 2x q for Press Knob 3 AutoPilot Volume AutoPilot Vo lume eus o os odos Go 2 0 gt Press Knob 1x 3 oo For Boot Menu 5 o lt AutoPilot UG334_c1_05_052707 Figure 1 5 LCD Screen Output using Menu System Power Saving Suspend Mode All of the preloaded FPGA configuration bitstreams have the power saving Suspend mode enabled Suspend mode reduces FPGA power consumption while preserving the present state of the FPGA application and the FPGA s configuration data Set the SUSPEND switch to RUN or SUSPEND as described in SUSPEND Switch page 26 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Key Components and Features Using one or two external multimeters measure the corresponding difference in current consumption as described in Measuring Power Across Voltage Supply Jumpers page 139 Caution Do not setthe SUSPEND switch to SUSPEND while programming the parallel NOR Flash PROM using configuration bitstream 4 as described in Table 1 2 RS 232 Serial Port Control Option Optionally control the demonstration design using a serial port connection to a PC or workstation On a PC use the HyperTerminal program to communicate to the FPGA application as shown in Figure 1 6 Using a
17. These four connections go to through hole pads not to a connector NET J19_IO lt 1 gt LOC Y18 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J19_IO lt 2 gt LOC W18 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J19_IO lt 3 gt LOC V17 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J19_TO lt 4 gt LOC W17 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 6 pin header J20 These four connections are shared with the FX2 connector NET J20_IO lt 1 gt LOC V14 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J20_IO lt 2 gt LOC V15 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J20_IO lt 3 gt LOC W16 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J20_IO lt 4 gt LOC V16 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 Figure 15 11 UCF Location Constraints for Six Pin Accessory Headers Connectorless Debugging Port Landing Pads J34 Landing pads for a connectorless debugging port are provided as the J34 header There is no physical connector on the board Instead a connectorless probe such as those available from Agilent provides an interface to a logic analyzer This debugging port is intended primarily for the Xilinx ChipScope Pro software with the Agilent FPGA Dynamic Probe It can however be used with either the Agilent or Tektronix probes without the ChipScope software using FPGA Editor s probe command e Xilinx ChipScope Pro Tool www xilinx com ise o
18. UCF Location ConstraldtS ER Rer e ee eed ane RR Re aan Related Resources Chapter 17 Voltage Supplies Measuring Power Across Voltage Supply Jumpers 222222200 PC Voltage Adjustment Interface 22 22222essseeeseesenenseeeeeen Possible Applications rn nee ee Restoring Default Voltages 2eeeeeeeeeeeeeeseeeeeennnnnenn UCF Location Constraints osete riken E EE REE E E A A Related Resources iii nissen a tke be trid antie iri Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 XILINX www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Preface About This Guide This user guide provides basic information on the Spartan 3A 3AN Starter Kit board capabilities functions and design It includes general information on how to use the various peripheral functions included on the board For detailed reference designs including VHDL or Verilog source code please visit the following web link e Spartan 3A 3AN Starter Kit Board Web Page http www xilinx com s3astarter and http www xilinx com s3anstarter There are multiple versions of the Spartan 3A 3AN Starter Kit This document describes the three kits that include the Revision D Spartan 3A 3AN Starter Kit Board which is an updated version of the Revision C Spartan 3A Starter Kit Board The following table describes the differe
19. beyond the 16th character on a line The cursor automatically moves to the second line when it shifts beyond the 40th character location of the first line The first and second line displays shift at the same time When the displayed data is shifted repeatedly both lines move horizontally The second display line does not shift into the first display line Execution Time 40 us www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX LCD Controller Table 5 3 Shift Patterns According to S C and R L Bits DB3 DB2 S C R L Operation 0 0 Shift the cursor position to the left The address counter is decremented by one 0 1 Shiftthe cursor position to the right The address counter is incremented by one Shift the entire display to the left The cursor follows the display shift The address counter is unchanged Shift the entire display to the right The cursor follows the display shift The address counter is unchanged Function Set Sets the interface data length the number of display lines and the character font The Starter Kit board supports a single function set with value 0x28 Execution Time 40 us Set CG RAM Address Sets the initial CG RAM address After this command all subsequent read or write operations to the display are to or from CG RAM Execution Time 40 us Set DD RAM Address Sets the initial DD RAM address After this co
20. but it defines the input value when the switch is in the middle of a transition Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 25 UG334 v1 0 May 28 2007 Chapter 2 Switches Buttons and Rotary Knob XILINX NET SW lt 0 gt LOC V8 IOSTANDARD LVTTL PULLUP NET SW lt 1 gt LOC U10 IOSTANDARD LVTTL PULLUP NET SW lt 2 gt LOC U8 IOSTANDARD LVTTL PULLUP NET SW lt 3 gt LOC T9 IOSTANDARD LVTTL PULLUP Figure 2 2 UCF Constraints for Slide Switches SUSPEND Switch The SUSPEND slide switch shown in Figure 2 3 connects directly to the FPGA s SUSPEND input pin If Suspend mode is enabled in the FPGA application then the FPGA enters Suspend mode whenever the switch is set to SUSPEND If the switch is then changed back to RUN then the FPGA resumes operation from the state before it entered Suspend mode Likewise if Suspend mode is enabled then the AWAKE pin is reserved to indicate when the FPGA is in Suspend mode See AWAKE LED page 32 RUN SUSPEND UG334_c2_03_052407 Figure 2 3 Suspend Switch To enable Suspend mode add the configuration string shown in Figure 2 4 to the user constraints file UCF If Suspend mode is not enabled in the application then the SUSPEND switch has no affect on the design and the AWAKE pin is available as a general purpose I O CONFIG ENABLE_SUSPEND FILTERED
21. command and read CG RAM using the Read Data from CG RAM or DD RAM command Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 47 UG334 v1 0 May 28 2007 Chapter 5 Character LCD Screen XILINX The CG RAM address counter either remains constant after read or write operations or auto increments or auto decrements by one location as defined by the I D set by the Entry Mode Set command Figure 5 5 provides an example that creates a special checkerboard character The custom character is stored in the fourth CG RAM character location which is displayed when a DD RAM location is 0x03 To write the custom character the CG RAM address is first initialized using the Set CG RAM Address command The upper three address bits point to the custom character location The lower three address bits point to the row address for the character bitmap The Write Data to CG RAM or DD RAM command is used to write each character bitmap row A 1 lights a bit on the display A 0 leaves the bit unlit Only the lower five data bits are used the upper three data bits are don t care positions The eighth row of bitmap data is usually left as all zeros to accommodate the cursor Upper Nibble Lower Nibble Write Data to CG RAM or DD RAM A5 A4 A3 A2 AI AO D7 D6 D5 D4 D3 D2 D1 DO Character Address Row Address Don t Care Character Bitmap Figure 5 5 Exa
22. s s ng S ng s ng S S s s s s s S UUUUUDUUDUUUDUUDUUDU DD DD DD D_UI D_UI D_UI D Lj D Lj D Lj DO 15 DO lt 14 gt DO 13 DO lt 12 gt DO 11 DO 10 DO 9 _DO lt 8 gt _DO lt 7 gt _DO lt 6 gt DQ 5 DO 4 DQ 3 _DO lt 2 gt DO 1 DQ 0 D BA 2 D BA 1 D BA 0 D RAS D CAS D WE D CK N D CK P D CKE D CS DM DOS N DOS P DM DOS N DOS P D ODT SD LOOP IN SD LOOP OUT LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC F3 G3 mL H5 H6 G1 G4 F2 H2 KA L5 L3 K1 K5 H1 P5 R3 P3 M3 MA N4 n M2 M1 N3 M5 E3 ug 5 n K6 33 K2 K3 PL n H4 H3 IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR o e Ml P Rl M INSCR ONU EE Ae Rab e EE d IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD IOSTANDARD
23. www xilinx com products boards s3astarter reference_designs htm atmel spi flash programmer www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Related Resources e Universal Scan SPI Flash Programming via JTAG Training Video www ricreations com JTAG Software Downloads htm Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 107 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX 108 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 13 DDR2 SDRAM The Spartan 3A 3AN Starter Kit board includes a 512 Mbit 32M x 16 Micron Technology DDR2 SDRAM MT47H32M16 with a 16 bit data interface as shown in Figure 13 1 5 0V 0 9 SSTL_18 Termination Voltage 18V DDR2 SDRAM Supply Voltage National SSTL_18 Reference Voltage Semiconductor LP3906 R lat iii See Table See Table o Ar c x Iz T9 e H4 H3 SD_LOOP Y UG334_c13_01_052407 Figure 13 1 FPGA Interface to Micron 512 Mbit DDR2 SDRAM Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 109 Chapter 13 DDR2 SDRAM XILINX All DDR2 SDRAM interface pins connect to the FPGA s I O Bank 3 on the FPGA I O Bank 3 and the DDR2 SDRAM are both powered by 1 8V supplied by a second National Semiconductor LP3906 regulator from the board s 5V supply input The
24. A converter www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Additional Resources Chapter 9 Analog Capture Circuit describes the functionality of the A D converter with a programmable gain pre amplifier Chapter 11 Parallel NOR Flash PROM describes the functionality of the STMicroelectronics parallel NOR PROM Chapter 12 SPI Serial Flash describes the functionality of the SPI Serial Flash memory interface Chapter 13 DDR2 SDRAM describes the functionality of the DDR2 SDRAM memory interface Chapter 14 10 100 Ethernet Physical Layer Interface describes the functionality of the 10 100Base T Ethernet physical layer interface Chapter 15 Expansion Connectors describes the various connectors available on the Spartan 3A 3AN Starter Kit board Chapter 16 Miniature Stereo Audio Jack describes the audio interface Chapter 17 Voltage Supplies describes the board s power distribution system Additional Resources To find additional documentation see the Xilinx website at http www xilinx com literature To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 11 UG334 v1 0 May 28 2007 Preface About This Guide 1
25. BPI configuration 0 Enabled 1 Disabled NF_OE W19 Active Low Flash Chip Enable Connects to FPGA pin LDC1 to support the BPI configuration 0 Enable data outputs to read Flash data 1 Disabled NF_RP Control Active Low Flash Reset Connects to FPGA user I O pin 0 Reset 1 Flash active NF_STS P22 Flash Status signal Optional input to FPGA open drain output from Flash NF_WE AA22 Active Low Flash Write Enable Connects to FPGA pin HDC to support the BPI configuration 0 Enable Flash data write operations 1 Disabled NF_WP E14 Active Low Hardware Write Protect Connects to FPGA user I O pin 0 Protect two outermost Flash boot blocks against all program and erase operations 1 Hardware protection disabled Shared SPI Flash and Platform Flash Data Line The least significant Flash data line NF_D lt 0 gt is shared with data output signals from the serial SPI serial Flash PROMs and the serial output from the Platform Flash PROM as shown in Table 11 2 page 87 To avoid contention the FPGA application must ensure that only one data source is active at any time 86 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX UCF Location Constraints Table 11 2 Possible Potential Competing Devices on SPI_MISO NF_D lt 0 gt Data Signal or Disabled Device Disable Value Jumper Jum
26. D c Ds Ds Ds Do Ds Da Da D4 Ds De D De Ds Popp Channel 1 Channel 0 Converted data is presented with a latency of one sample The sampled analog value is converted to digital data 32 SPI_SCK cycles after asserting AD_CONV FPGA Master Sample The converted values is then presented after the next AD_CONV pulse Sample J point J point AD_CONV nm SPI SCK es Channel 0 Channel 1 MIN Channel 0 ADC OUT UG334 c9 06 052407 Figure 9 6 Analog to Digital Conversion Interface Figure 9 7 shows detailed transaction timing The AD CONV signal is not a traditional SPI slave select enable Be sure to provide enough SPI SCK clock cycles so that the ADC leaves the ADC OUT signal in the high impedance state As shown in Figure 9 6 use a 34 cycle communications sequence The ADC 3 states its data output for two clock cycles before and after each 14 bit data transfer 4ns min AD_CONV 19 6ns min 3ns 1 T i 1 1 1 SPI_SCK f f fa 5 fo 8ns I 1 Channel 0 ADC_OUT High Z QU o AM oo M oU M AD CONV 1 45ns min 1 ra 1 1 30 31 32 33 34 gt amuser on Qe oe em E A y PT Channel 1 i High Z ADCOUT_3 M 2 M W o Jj 2 The A D converter sets its SDO output line to high impedance after 33 SPI SCK clock cycles UG330 c10 06 032007 Figure 9 7 Detailed SPI Timing to ADC UCF Location Constraints Figure 9 8 provides the User Constr
27. E_TX_EN LOC D8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 NET E_TXD lt 0 gt LOC F8 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 NET E_TXD lt 1 gt LOC E7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 NET E_TXD lt 2 gt LOC E6 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 NET E_TXD lt 3 gt LOC F7 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 NET E_TXD lt 4 gt LOC B2 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 4 PULLUP Figure 14 3 UCF Location Constraints for 10 100 Ethernet PHY Inputs Related Resources Refer to the following links for additional information e Standard Microsystems SMSC LAN8700 10 100 Ethernet PHY http www smsc com main catalog lan8700 html e Xilinx OPB Ethernet Media Access Controller EMAC v1 02a http www xilinx com bvdocs ipcenter data_sheet opb_ethernet pdf e Xilinx OPB Ethernet Lite Media Access Controller v1 01a The Ethernet Lite MAC controller core uses fewer FPGA resources and is ideal for applications the do not require support for interrupts back to back data transfers and statistics counters http www xilinx com bvdocs ipcenter data sheet opb ethernetlite pdf e EDK Documentation http www xilinx com ise embedded edk docs htm 120 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 15 Expansion Connectors The Spartan 3A 3AN Starter Kit board
28. FX2 IO17 D18 A13 B13 GND GND FX2_IO18 E17 A14 B14 A15 B15 Al6 B16 A17 B17 A18 B18 A19 B19 A20 B20 A21 B21 A22 B22 A23 B23 A24 B24 A25 B25 A26 B26 A27 B27 Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 16 Miniature Stereo Audio Jack The Spartan 3A 3AN Starter Kit board includes a miniature stereo audio jack plug as highlighted in Figure 16 1 The jack plug is located in the upper right corner of the board immediately above the SUSPEND slide switch Stereo audio miniature jack 1 8 3 5 mm Connect headphones or amplified speakers 3 3V digital outputs UG334_c16_01_052407 Figure 16 1 Stereo Miniature Jack Supported Audio Devices The port provides simple audio tones to an attached set of headphones or to amplified speakers The audio device must use a 1 8th inch or 3 5 mm audio jack as shown in Figure 16 2 A stereo connector is highly recommended The FPGA signal definition appears in Table 16 1 A monophonic connector will function but with the following limitations Only drive signals on the AUD_L signal Drive the AUD_R output to high impedance Hi Z three state so that it does not compete with the AUD_L channel Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 135 UG334 v1 0 May 28 2007 Chapter 16 Miniature Stereo Audio Jack XILINX 1 8 1 4 3 5 mm 6 3 mm Aldo Stereophonic one insula
29. Hirose FX2 100P 1 27DS header with 1 27 mm pitch Throughout the documentation this connector is called the FX2 connector As shown in Figure 15 2 43 FPGA I O pins interface to the FX2 connector Hirose 100 pin Expansion FPGA Connector J17 FX2_10 lt 40 1 gt See Table See Table FX2_CLKIN FX2_CLKOUT FX2_CLKIO UG334_c15_02_052407 Figure 15 2 FPGA Connections to the Hirose 100 Pin Edge Connector Three signals are reserved primarily as clock signals between the board and FX2 connector although all three connect to full I O pins Expansion Connector Compatibility For the majority of applications the FX2 connector on the Spartan 3A 3AN Starter Kit board is compatible with the other Xilinx development boards The Spartan 3E Starter Kit board and XC3S1600E Starter Kit board optionally provide limited differential I O capability on the FX2 connector The Spartan 3A 3AN Starter Kit board provides enhanced differential I O support using the Differential I O Connectors page 126 e Spartan 3E Starter Kit board www xilinx com s3estarter e XC3S1600E MicroBlaze Embedded Development Board www xilinx com sp3e1600e Furthermore the Spartan 3A 3AN Starter Kit board supports the other FX2 Connector Compatible Boards page 124 Voltage Supplies to the Connector The Spartan 3A 3AN Starter Kit board provides power to the Hirose 100 pin FX connector and any attached board via two supplies see F
30. IO L08N 2 I O J1 14 TX_ lt 2 gt TXP_ lt 2 gt AA6 IO L08P 2 I O J1 13 TXN_ lt 3 gt AB7 IO L10N 2 I O J1 22 TX_ lt 3 gt TXP_ lt 3 gt Y7 IO L10P 2 I O J1 21 TXN_ lt 4 gt AB8 IO L12N 2 I O J1 26 TX_ lt 4 gt TXP_ lt 4 gt AA8 IO_L12P 2 I O J1 25 TX CLK N AB10 IO L15N 2 I O J1 30 TX CLK TX CLK P AA10 IO_L15P 2 I O J1 29 Using Differential Inputs LVDS and RSDS differential inputs require input termination Two options are generally available The first option is to use external termination resistors as shown in Figure 15 4a External input termination resistors are not provided on the differential I O pins The second option called on chip differential termination is highlighted on the Spartan 3A 3AN Starter Kit board see Figure 15 4b This feature uses the DIFF TERM attribute available on differential I O signals Each differential I O pin includes a circuit that Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 127 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors XILINX behaves like an internal termination resistor of approximately 1000 On chip differential termination is only available on full I O pairs not on Input only pairs Differential inputs are powered by the Vccayx supply which is 3 3V by default Differential inputs are available in any I O bank Pads for 100 Differential termination surface mount resistor 100Q or PAD E dd penas EAD IBUFDS or xx
31. Kit board highlights the unique features of the Spartan 3A and Spartan 3AN FPGA families and provides a convenient development board for embedded processing applications The board highlights these features e Spartan 3AN specific features Nonvolatile configuration from internal SPI Flash e Spartan 3A 3AN specific features Parallel NOR Flash configuration SPI serial Flash configuration using either the STMicroelectronics or Atmel DataFlash architectures MultiBoot FPGA configuration from both Parallel NOR and SPI serial Flash PROMs e Embedded development MicroBlaze 32 bit embedded RISC processor www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Spartan 3A and Spartan 3AN FPGAs PicoBlaze eight bit embedded controller e Power management using the Suspend mode feature DDR2SDRAM memory interfaces Other Spartan 3 Generation Development Boards The Spartan 3A 3AN Starter Kit board demonstrates the full capabilities of the Spartan 3A and Spartan 3AN FPGA families and the Xilinx ISE development software For a development board specific to the Spartan 3E FPGA family consider the Spartan 3E Starter Kit board There are multiple ordering codes depending on the included power supply e Spartan 3E Starter Kit Board HW SPAR3E SK_xx www xilinx com s3estarter For MicroBlaze development consider the XC351600E Embedded Development board e XC3S1600E Embedded Devel
32. LOC C15 IOSTANDARD LVTTL SLEW un LOW DRIVE LOW DRIVE mon un mon Hs write protect control for ST M25P16 PROM NET ST_SPI_WP LOC C13 IOSTANDARD LVTTL SLEW SLOW DRIVE l S Figure 12 3 UCF Location Constraints for SPI Flash Connections Creating and Programming Configuration Images for SPI Serial Flash Refer to the Master SPI Mode chapter in the Spartan 3 Generation Configuration User Guide for information on how to create and format FPGA configuration images for SPI serial Flash and how to program SPI Flash using the Xilinx IMPACT software e UG332 Spartan 3 Generation Configuration User Guide www xilinx com bvdocs userguides ug332 pdf SPI Flash PROM Programming Options Starting with ISE 9 1i Service Pack 2 and later the IMPACT programming software supports two different methods to program an attached SPI Flash PROM as summarized in Table 12 5 Using the Direct Programming Method the programming cable communicates directly to the SPI Flash PROM The FPGA is not involved in the programming process and the FPGA I O pins that connect to the PROM must be in their high impedance state Hi Z during programming Hold the FPGA s PROG B input Low using jumper J16 to place the I Os in Hi Z the FPGA s DONE pin remains Low Using the Indirect Programming Method the programming cable connects to the FPGA s JTAG port The iMPACT software first programs th
33. Overview XILINX Spartan 3A FPGAs Web page www xilinx com spartan3a Data sheet www xilinx com bvdocs publications ds529 pdf Errata www xilinx com xInx xweb xil_publications_display jsp category 1212251 Additional documentation www xilinx com xInx xweb xil_publications_display jsp category 1212246 Spartan 3AN FPGAs Web page www xilinx com spartan3an Data sheet www xilinx com bvdocs publications ds557 pdf Errata www xilinx com xInx xweb xil_publications_display jsp category 1212871 Additional documentation www xilinx com xInx xweb xil_publications_display jsp category 1212828 Related Resources Refer to the following links for additional information 24 Spartan 3A 3AN Starter Kit www xilinx com s3astarter and www xilinx com s3anstarter Spartan 3A 3AN Rev D Starter Kit user guide www xilinx com bvdocs userguides ug334 pdf Spartan 3A Rev C Starter Kit user guide www xilinx com bvdocs userguides ug330 pdf Example User Constraints File UCF www xilinx com products boards s3astarter files s3astarter ucf Board schematics annotated www xilinx com products boards s3astarter s3astarter schematic pdf Bill of materials BOM list www xilinx com products boards s3astarter s3astarter_bom xls Link to design examples www xilinx com products boards s3astarter reference_designs htm Xilinx MicroBlaze Soft Processor www xilinx
34. PS 2 splitter cable un PS2_CLK2 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 65 UG334 v1 0 May 28 2007 Chapter 8 PS 2 Mouse Keyboard Port XILINX Keyboard 66 Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start a stop and an odd parity bit However the data packets are organized differently for a mouse and keyboard Both the keyboard and mouse interfaces allows bidirectional data transfers For example the FPGA host design can illuminate the state LEDs on the keyboard or change the communicate rate with the mouse The PS 2 bus timing appears in Table 8 2 and Figure 8 2 The clock and data signals are only driven when data transfers occur otherwise they are held in the idle state at a logic High The timing defines signal requirements for mouse to host communications and bidirectional keyboard communications As shown in Figure 8 2 the attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low Table 8 2 PS 2 Bus Timing Symbol Parameter Min Max Tek Clock High or Low Time 30 us 50 us Tsy Data to clock Setup Time 5 us 25 us Tup Clock to data Hold Time 5 us 25 us Tok
35. SLOW NET NF_A lt 14 gt LOC H22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 13 gt LOC J20 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 12 gt LOC J21 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 11 gt LOC J22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 10 gt LOC K22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 9 gt LOC N17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 8 gt LOC N18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 7 gt LOC N19 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 6 gt LOC N20 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 5 gt LOC N21 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 4 gt LOC N22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 3 gt LOC P18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 2 gt LOC R19 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 1 gt LOC T18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 0 gt LOC T17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW Upper four address lines NF_A lt 25 22 gt are unconnected using a 32Mbit Flash They are available as user I Os but do not connect to anything on the board CONFIG PROHIBIT B22 CONFIG PROHIBIT B21 CONFIG PROHIBIT G18 CONFIG PROHIBIT G17 Figure 11 2 UCF Location Constra
36. Table 12 4 The location of the J26 jumper appears in Figure 12 1 7 Disable the Platform Flash PROM by removing jumper J46 shown in Figure 12 1 and Table 12 4 8 For direct programming the FPGA s PROG_B pin must be held Low Insert a jumper in jumper J16 as shown in Figure 12 4 This holds all the FPGA s I O in three state to allow the JTAG programmer full access to the SPI PROM pins 9 Re apply power to the board Using a Separate JTAG Parallel Programming Cable Optional Using Embedded USB JTAG Programmer is the preferred programming method With the jumpers installed between the J23 and J25 headers the embedded USB programmer communicates directly to the SPI Flash PROM However it is possible to communicate directly to the SPI Flash PROM using another a programming cable such as e Xilinx Parallel Cable IV with flying leads e Digilent JTAG3 or JTAG USB programming cable Connect the cable directly to the J23 header block as illustrated in Figure 12 5 These cables are not provided with the Spartan 3A 3AN Starter Kit board but can be purchased separately mmm a JTAG3 Parallel Connector b Parallel Cable Ill or Parallel Cable IV with Flying Leads UG334 c12 05 052407 Figure 12 5 Attaching a JTAG Parallel Programming Cable to the Board Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 97 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX First turn off the power on the Starte
37. Tek Edge 0 Edge 10 ge AS Babe y 9 CLK PS2C FT IT afi HED Tsu DATA PS2D X Ho Oe BM UG230 c8 02 021806 Figure 8 2 PS 2 Bus Timing Waveforms The keyboard uses open collector drivers so that either the device or the host can drive the two wire bus If the host never sends data then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 8 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends an F0 key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they might send more than one scan code When an extended key is released an E0 F0 key up code is sent followed by the scan code www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX ESC 76 Shift e 12 Ctrl 14 Keyboard FA F3 F4 F5 Fe F7 F8 F9 F11 F12 1 05 04 oc 03 0B 83 OA 01 78 07 075 E
38. available in the Spartan 3A Starter Kit Download FPGA designs directly to the Spartan 3A 3AN FPGA via JTAG using the on board USB interface The on board USB JTAG logic also provides in system programming for the on board Platform Flash PROM SPI serial Flash and StrataFlash programming are performed separately Program the on board 4 Mbit Xilinx XCF04S serial Platform Flash PROM then configure the FPGA from the image stored in the Platform Flash PROM using Master Serial mode Program the on board 16 Mbit STMicroelectronics SPI serial Flash PROM or the 16 Mbit Atmel SPI based DataFlash PROM then configure the FPGA from the image stored in the SPI serial Flash PROM using SPI mode Further an FPGA application can dynamically load different FPGA configurations using the FPGA s MultiBoot mode See UG332 Spartan 3 Generation Configuration User Guide for additional details on the MultiBoot feature See Chapter 12 SPI Serial Flash for more information on using SPI serial Flash memory Program the on board 32 Mbit STMicroelectronics parallel NOR Flash PROM then configure the FPGA from the image stored in the Flash PROM using BPI Up configuration mode Further an FPGA application can dynamically load different FPGA configurations using the FPGA s MultiBoot mode See UG332 Spartan 3 Generation Configuration User Guide for additional details on the MultiBoot feature See Chapter 11 Parallel NOR Flash PROM for more information on
39. bitstream If the Suspend mode is not used then the FPGA s AWAKE pin is available as a full user I O pin If the FPGA is not yet configured the FPGA s AWAKE pin is dimly lit because pull up resistors are enabled during configuration The FPGA s PUDC_B pin is connected to GND on the board To light the AWAKE LED in an application drive the AWAKE pin High INIT_B LED The red colored INIT_B LED serves multiple purposes e At power up or when the PROG_B button is pressed the LED flashes momentarily while the FPGA clears its configuration memory e Ifconfiguration fails for any reason then the FPGA s DONE LED will be unlit and the INIT_B LED will light This indicates that the FPGA could not successfully configure e After the FPGA successfully completes the INIT_B pin is available as a general purpose user I O pin If no signal drives INIT_B then it is defined as an input pin with a pull down resistor It might appear that the LED dimly glows Drive the INIT_B pin High to turn off the LED or Low to light the LED e Ifusing the Readback CRC feature the INIT B pin is reserved and signals a CRC error after configuration If such an error occurs the FPGA drives INIT_B Low lighting the LED If using the INIT_B pin as a user I O pin after configuration drive the pin Low to light the LED and High to shut it off Jumper J46 shown in Table 4 2 page 40 must be in either the Disabled or Enabled during Configuration se
40. by a 32 bit shift register Each 32 bit command word consists of a command and an address followed by a data value As a new command enters the DAC the previous 32 bit command word is echoed back to the master The response from the DAC can be ignored although it is a useful to confirm correct communication DAC_OUT Bai Ret Slave LTC2624 DAC 31 arado Tes EESTI Master Don t Care Don t Care 12 bit Unsigned DATA COMMAND UG334 c10 04 052407 Figure 10 4 SPI Communications Protocol to LTC2624 DAC Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 81 UG334 v1 0 May 28 2007 Chapter 10 Digital to Analog Converter DAC XILINX The FPGA first sends eight dummy or don t care bits followed by a four bit command The most commonly used command with the board is COMMANDJ3 0 0011 binary which immediately updates the selected DAC output with the specified data value Following the command the FPGA selects one or all the DAC output channels via a four bit address field Following the address field the FPGA sends a 12 bit unsigned data value that the DAC converts to an analog value on the selected output s Finally four additional dummy or don t care bits pad the 32 bit command word Specifying the DAC Output Voltage As shown in Figure 10 2 each DAC output level is the analog equivalent of a 12 bit unsigned digital value D 11 0 written by the FPGA to the DAC via the SPl interface
41. com microblaze Xilinx PicoBlaze Soft Processor www xilinx com picoblaze Xilinx Embedded Development Kit www xilinx com ise embedded_design_prod platform_studio htm Xilinx Software Tutorials www xilinx com support techsup tutorials Xilinx Technical Support www xilinx com support www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 2 Switches Buttons and Rotary Knob Slide Switches Locations and Labels The Spartan 3A 3AN Starter Kit board has four slide switches as shown in Figure 2 1 The slide switches are located in the lower right corner of the board and are labeled SW3 through SWO Switch SW3 is the left most switch and SWO is the right most switch HIGH 1 LOW 0 SW3 sw2 SW1 SWO T9 U8 U 1 0 V8 UG330 c2 01 021507 Figure 2 1 Four Slide Switches Operation When in the UP or ON position a switch connects the FPGA pin to 3 3V a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce There is no active debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board UCF Location Constraints Figure 2 2 provides the UCF constraints for the four slide switches including the I O pin assignment and the I O standard used The PULLUP resistor is not required
42. down resistor for each FPGA input NET ROT A LOC T13 IOSTANDARD LVTTL PULLUP NET ROT B LOC R14 IOSTANDARD LVTTL PULLUP H NET ROT CENTER LOC R13 IOSTANDARD LVTTL PULLDOWN Figure 2 11 UCF Constraints for Rotary Push Button Switch Discrete LEDs Locations and Labels The Spartan 3A 3AN Starter Kit board has eight individual surface mount LEDs located immediately above the slide switches as shown in Figure 2 12 The LEDs are labeled LED7 through LEDO LED7 is the left most LED LEDO the right most LED 20 LED3 U19 ae LED7 W21 LED6 Y22 E 2 LEDA T19 901 UGS334 c2 12 052407 Figure 2 12 Eight Discrete LEDs 30 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 Optional Discrete LEDs Operation Each LED has one side connected to ground and the other side connected to a pin on the device via a 390 current limiting resistor To light an individual LED drive the associated FPGA control signal High If the FPGA is not yet configured the LEDs may be dimly lit because pull up resistors are enabled during configuration The FPGA s PUDC B pin is connected to GND on the board UCF Location Constraints Figure 2 13 provides the UCF constraints for the four push button switches including the I O pin assignment the I O standard used the output slew rate and the output drive current NET LED lt 7 gt
43. dy ca 73 SPI Control Interface 2 0 ce een een a ae 74 UCF Location Constraints 2 0 0 0 cn ene tenn eanan 75 Analog to Digital Converter ADC 2 222cseceeeeneeene eee 75 l terface s der a Le A ERA ERG aT Rl 75 SPI Control Intertac u 228 Hrn al bee ys de BAGS 75 UCF Location Constraints 2 0 0 0 ec en enn tent e nee 76 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 XILINX Connecting Analog Inputs ooo ooococccoccccccnncncc eh 77 Related Resouces nu ee A id a 77 Chapter 10 Digital to Analog Converter DAC SPI Communication 79 Interface Signals rcstis ee ee ER eee epis 80 SPI Communication Details oooooooooooononoornrrnrrnrara o 80 Communication Protocol o ooooooooorrr eee e 81 Specifying the DAC Output Voltage sese 82 UCF Location Constraints luus e 82 Related Resources 82 Chapter 11 Parallel NOR Flash PROM Flash Connections 84 Shared SPI Flash and Platform Flash Data Line eese 86 UCF Location Constraints 00 0 ccc e 87 A REOR 87 ID REP MILD II eae ata T 88 Control dci RE teehee ones ELA E LEE 88 Setting the FPGA Mode Select Pins 0 cece eee 88 Creating and Programming Configuration Images for Parallel Flash 89 Related Resources 89 Chapter 12 SPI Serial Flash SPI Flash PROM Select Jumpers J1 0 0 cece cece cee eee e
44. half second intervals tests the practical limit for clarity Compared with the 50 MHz clock available on the board the display is slow A PicoBlaze processor efficiently controls display timing plus the actual content of the display Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 43 UG334 v1 0 May 28 2007 Chapter 5 Character LCD Screen XILINX Character LCD Interface Signals Table 5 1 shows the interface character LCD interface signals Table 5 1 Character LCD Interface Signal Name FPGA Pin Function LCD_DB lt 7 gt Y15 Data bit DB7 LCD_DB lt 6 gt AB16 Data bit DB6 LCD_DB lt 5 gt Y16 Data bit DB5 LCD_DB lt 4 gt AA12 Data bit DB4 LCD_DB lt 3 gt AB12 Data bit DB3 When using the four bit LCD DB lt 2 gt AB17 Data bit DB2 interface drive these signals High LCD DB 1 AB18 Data bit DB1 18 LCD_DB lt 0 gt Y13 Data bit DBO LCD_E AB4 Read Write Enable Pulse 0 Disabled 1 Read Write operation enabled LCD_RS Y14 Register Select 0 Instruction register during write operations Busy Flash during read operations 1 Data for read or write operations LCD_RW W13 Read Write Control 0 Write LCD accepts data 1 Read LCD presents data Voltage Compatibility The character LCD is power by 5V The FPGA I O signals are powered by 3 3V However the FPGA s output levels are recognized as valid Low or High logic levels by the LCD The LCD controller accepts 5V TIL si
45. low drop out LDO linear regulators Table 17 1 Voltage Regulators and Supply Rails Xonage Heguiator Voltage Level e Components Supplied Regulator Output g p p PP Control Sw1 12V Jo FPGA internal core voltage VccINT National FPGA I O Banks 0 1 and 2 ationa VCCO 0 VCCO 1 and Semiconductor SW2 3 3V J10 VCCO 2 All 3 3V LP3906 components em FPGA i auxili LDO1 3 3V yu internal auxillary voltage VecAux LDO2 1 8V J12 Embedded USB programmer swi 0 9V 140 DDR2 SDRAM termination network DDR2 SDRAM component National RM ney J13 FPGA I O Bank 3 VCCO_3 Semiconductor LP3906 LDO1 3 3V ja Voltage reference to D A IC18 converter channels C and D 1 8V DDR2 SDRAM voltage LDO2 voltage divided J42 reference FPGA I O Bank 3 to 0 9V VREF inputs VREF_3 The board exploits all four regulator outputs for testing and evaluation purposes However a typical Spartan 3A 3AN FPGA application uses far fewer rails e The board uses a separate supply for Vccaux and sets it to 3 3V by default In a typical application the FPGA s Vccaux supply could connect directly to the 3 3V supply used for FPGA I O Banks 0 1 and 2 By default the VccAux supply is set to 3 3V Using the PC interface on regulator IC19 Vecayx can be reduced to 2 5V to reduce overall power consumption or to verify operation with Vocaux 2 5V e The DDR2 SDRAM interface uses multiple regulator outputs to test v
46. lt 8 gt LOC D_A lt 7 gt LOC D_A lt 6 gt LOC D_A lt 5 gt LOC D_A lt 4 gt LOC D_A lt 3 gt LOC D_A lt 2 gt LOC D_A lt 1 gt LOC D_A lt 0 gt LOC W3 V4 V3 y2 Vj p3 W2 W1 y UL UA U2 U3 R1 p4 R2 IOs TOST IOS TOSI IOS IOS IOS IOS IOS IOS TOSI TOSI IOS IOS IOS IOS PANI PANI PANI Fan RAN PANI RAN PAN PANI AN PANI PANI PANI PANI PANI PAN DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD DARD SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS SS Figure 13 2 UCF Location Constraints for DDR2 SDRAM Address Inputs 112 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX UCF Location Constraints Data Figure 13 3 provides the User Constraint File UCF constraints for the DDR2 SDRAM data pins including the I O pin assignment and I O standard used Control Figure 13 4 provides the User Constraint File UCF constraints for the DDR2 SDRAM control pins including the I O pin assignment and the I O standard used NET NET NET NET NET NET NET Figure 13 4 UCF Location Constraints for DDR2 SDRAM Control Pins sy i i i e e e e ng ng gi e ei i el i Figure 13 3 UCF Location Constraints for DDR2 SDRAM Data I O Pins S s
47. of the box demo design shipped with the board Includes how to set up and operate the demonstration evaluate MultiBoot and Suspend and provides demo technical details e Restoring the Out of the Box Flash Programming www xilinx com products boards s3astarter reference_designs htm out Provides a short overview of what the starter kit board does out of the box and includes instructions on how to restore the board to the original out of the box state The ZIP file includes the golden MCS files that are pre programmed into Flash memory before the board is shipped The PDF file contains instructions for restoring the board to its original settings using these MCS files in case any of the configuration memories were overwritten during normal use Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 21 UG334 v1 0 May 28 2007 Chapter 1 Introduction and Overview XILINX e Spartan 3A 3AN Starter Kit Board Verification Design www xilinx com products boards s3astarter reference_designs htm test This example includes the board test specification and the board test design This design was used during initial board verification and some functions are used during production test It is provided to test out a board if something is not working as expected The design files may also be of general interest The ZIP file has the design source a script to run them and the resulting compiled files e Programmer for the
48. operate for approximately eight hours in silicon before timing out To order the full version of the core visit the Xilinx website at www xilinx com ipcenter processor central processor ip 10 100emac 10 100emac order register htm Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 119 UG334 v1 0 May 28 2007 Chapter 14 10 100 Ethernet Physical Layer Interface XILINX UCF Location Constraints Figure 14 3 provides the UCF constraints for the 10 100 Ethernet PHY interface including the I O pin assignment and the I O standard used NET E_COL LOC G12 IOSTANDARD LVCMOS33 PULLDOWN NET E_CRS LOC H12 IOSTANDARD LVCMOS33 NET E_MDC LOC D10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET E_MDIO LOC E10 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET E_NRST LOC D15 IOSTANDARD LVCMOS33 SLEW SLOW DRIVE 4 NET E_RX_CLK LOC C12 IOSTANDARD LVCMOS33 NET E_RX_DV LOC H10 IOSTANDARD LVCMOS33 NET E_RXD lt 0 gt LOC G7 IOSTANDARD LVCMOS33 PULLUP NET E_RXD lt 1 gt LOC G8 IOSTANDARD LVCMOS33 PULLUP NET E_RXD lt 2 gt LOC G9 IOSTANDARD LVCMOS33 PULLUP NET E_RXD lt 3 gt LOC H9 IOSTANDARD LVCMOS33 PULLUP NET E_RXD lt 4 gt LOC G10 IOSTANDARD LVCMOS33 NET E_TX_CLK LOC E11 IOSTANDARD LVCMOS33 NET
49. resistor gt A 0 Rotary Shaft Encoder UG230_c2_06_030606 GND Figure 2 9 Basic Example of Rotary Shaft Encoder Circuitry Closing a switch connects it to ground generating a logic Low When the switch is open a pull up resistor within the FPGA pin pulls the signal to a logic High The UCF constraints in Figure 2 11 describe how to define the pull up resistor The FPGA circuitry to decode the A and B inputs is simple but must consider the mechanical switching noise on the inputs also called chatter As shown in Figure 2 10 the chatter can falsely indicate extra rotation events or even indicate rotations in the opposite direction Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 29 UG334 v1 0 May 28 2007 XILINX Chapter 2 Switches Buttons and Rotary Knob Rising edge on A when B is Low indicates RIGHT clockwise rotation Switch opening chatter on A Rotating RIGHT i eg e false clicks to the RIGHT 1L T NM Nc closing chatter on B injects false clicks to the LEFT B rising edge when A is Low Uu Detent Detent UG230 c2 07 030606 Figure 2 10 Outputs from Rotary Shaft Encoder Might Include Mechanical Chatter UCF Location Constraints Figure 2 11 provides the UCF constraints for the rotary encoder push button switch including the I O pin assignment and the I O standard used and defines a pull up or pull
50. rotary push button switch integrates two different functions The switch shaft rotates and outputs values whenever the shaft turns The shaft can also be pressed acting as a push button switch Push Button Switch Pressing the knob on the rotary push button switch connects the associated FPGA pin to 3 3V as shown in Figure 2 8 Use an internal pull down resistor within the FPGA pin to generate a logic Low Figure 2 11 shows how to specify a pull down resistor within the UCE There is no active debouncing circuitry on the push button 28 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Rotary Push Button Switch Rotary Push Button X FPGA I O Pin 3 3V je ROT_CENTER Signal UG230_c2_05_021206 Figure 2 8 Push Button Switches Require an Internal Pull up Resistor in the FPGA Input Pin Rotary Shaft Encoder In principal the rotary shaft encoder behaves much like a cam connected to the central shaft Rotating the shaft then operates two push button switches as shown in Figure 2 9 Depending on which way the shaft is rotated one of the switches opens before the other Likewise as the rotation continues one switch closes before the other However when the shaft is stationary also called the detent position both switches are closed A pull up resistor in each input pin generates a 1 for an open switch FPGA See the UCF file for details on specifying the pull up
51. the four bit data interface to the LCD as follows 1 Wait 15 ms or longer although the display is generally ready when the FPGA finishes configuration The 15 ms interval is 750 000 clock cycles at 50 MHz Write LCD_DB lt 7 4 gt 0x3 and pulse LCD_E High for 12 clock cycles Wait 4 1 ms or longer which is 205 000 clock cycles at 50 MHz Write LCD_DB lt 7 4 gt 0x3 and pulse LCD_E High for 12 clock cycles Wait 100 us or longer which is 5 000 clock cycles at50 MHz Write LCD_DB lt 7 4 gt 0x3 and pulse LCD_E High for 12 clock cycles Wait 40 us or longer which is 2 000 clock cycles at 50 MHz Write LCD_DB lt 7 4 gt 0x2 and pulse LCD_E High for 12 clock cycles Wait 40 us or longer which is 2 000 clock cycles at 50 MHz vsonanpmn Display Configuration After the power on initialization is completed the four bit interface is established The next part of the sequence configures the display 1 Issue a Function Set command 0x28 to configure the display for operation on the Spartan 3A 3AN Starter Kit board 2 Issue an Entry Mode Set command 0x06 to set the display to automatically increment the address pointer 3 Issue a Display On Off command 0x0C to turn the display on and disable the cursor and blinking 4 Finally issue a Clear Display command Allow at least 1 64 ms 82 000 clock cycles after issuing this command Writing Data to the Display To write data to the display specify the start address fol
52. the audio jack Set the SUSPEND switch to the RUN position Connect the included AC adapter to wall power and also to the board The AC adapter also includes attachments to support worldwide locals Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 13 UG334 v1 0 May 28 2007 Chapter 1 Introduction and Overview XILINX 6 Turn on the power switch The character LCD and VGA display if connected display various informational messages and instructions If an audio device is connected the board offers words of welcome in a variety of languages Use the rotary push button switch to control various board functions Optionally connect a PS 2 style keyboard to support one of the included demonstrating designs 10 Optionally connect a PC directly to the board using a standard 9 pin serial cable SPI Flash Select Jumpers both jumpers installed vertically Platform Flash Jumper jumper removed Power Supply Jumpers all jumpers installed Hart fass ee DIGILENT gt Ep IP Fy xuxx SPARTAN 3 FPGA Mode Select Jumpers bottom two jumpers installed SPI Mode UG334 c1 02 052707 Figure 1 2 Default Jumper Settings for Starter Kit Board For more information on the demonstration design visit the Design Examples web page e Spartan 3A 3AN Starter Kit Demo Design Overview www xilinx com products boards s3astarter reference designs htmitdemo e Restoring the Out of the Box Fl
53. to between 1 0V and 3 3V by controlling the LDO1 output on IC18 The corresponding IC control signals are REG2_SCL and REG2_SDA See Chapter 10 Digital to Analog Converter DAC for additional information Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 www xilinx com 7 XILINX Related Resources Restoring Default Voltages Any voltage adjustments are temporary and apply only as long as the 5 0V supply is connected To restore the original regulator output voltages remove and then reconnect the 5 0V supply input Caution Simply toggling the power switch will not restore the original regulator output voltage Remove and reconnect the external 5 0V supply input UCF Location Constraints Figure 17 3 provides the UCF constraints for the C control signals to the regulators Controls VCCAUX supply rail 1C19 NET REG1_SCL LOC E13 IOSTANDARD LVTTL DRIVE NET REG1_SDA LOC D13 IOSTANDARD LVTTL DRIVE LEW QUIETIO LEW QUIETIO 8 Si 8 Si Control D A Converter reference voltage for Channels C and D 1C18 NET REG2_SCL LOC D11 IOSTANDARD LVTTL DRIVE 8 SLEW QUIETIO NET REG2_SDA LOC F13 IOSTANDARD LVTTL DRIVE 8 SLEW QUIETIO Figure 17 3 UCF Constraints for Regulator I2C Control Signals Related Resources Refer to the following link for additional information e National Semiconductor LP3906 Dual High Current S
54. using parallel Flash memory Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 37 UG334 v1 0 May 28 2007 38 Chapter 4 FPGA Configuration Options XILINX Figure 4 1 indicates the position of the USB download programming interface and the on board non volatile memories that potentially store FPGA configuration images 16 Mbit Atmel DataFlash SPI Serial Flash 16 Mbit ST Micro SPI Serial Flash 4 Mbit Platform Flash PROGRAM Button PROM DONE LED USB based Download Debugging Port Uses standard USB cable In System SPI Flash Spartan 3AN Starter Kit board only 32 Mbit STMicro Flash Parallel NOR Flash memory Byte Peripheral Interface BPI mode FPGA Mode Select Jumpers UG334 c4 01 052407 Figure 4 1 Starter Kit FPGA Configuration Options The configuration mode jumpers determine which configuration mode the FPGA uses when power is first applied or whenever the PROG button is pressed The DONE pin LED lights when the FPGA successfully finishes configuration Pressing the PROG button forces the FPGA to restart its configuration process The Xilinx Platform Flash PROM provides easy JTAG programmable configuration storage for the FPGA The FPGA configures from the Platform Flash using Master Serial mode www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Configuration Mode Jumpers As shown in Table 4 1 the J26 jumper block settings
55. 0 9V reference voltage common to the FPGA and DDR2 SDRAM is also supplied by the National Semiconductor regulator See Voltage Regulators in the Starter Kit Schematic All DDR2 SDRAM interface signals are terminated See DDR2 SDRAM Termination Network in the Starter Kit Schematic for information on the SSTL18 termination scheme used on the board DDR2 SDRAM Connections Table 13 1 shows the connections between the FPGA and the DDR2 SDRAM Also see 32Mx16 DDR2 SDRAM in the Starter Kit Schematic 110 Table 13 1 FPGA to DDR2 SDRAM Connections DDR2SDRAM FPGA Pin Category Signal Name Number Function SD_A15 W3 Unused on 512 Mbit DDR2 SDRAM device SD_A14 ya but provided for potential future upgrades SD_A13 V3 SD_A12 Y2 Address inputs SD_A11 V1 SD A10 T3 SD A9 w2 SD_A8 w1 3 SD A7 Y1 SD_A6 U1 SD A5 U4 SD_A4 U2 SD_A3 U3 SD_A2 R1 SD_A1 T4 SD A0 R2 www xilinx com Spartan 3A 8AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX DDR2 SDRAM Connections Table 13 1 FPGA to DDR2 SDRAM Connections Continued DDR2 SDRAM FPGA Pin Category Signal Name Number Function SD_DO15 F3 Data input output Outputs defined for Em 048 0d SD DO13 Fl SD_DQ12 H5 SD_DO11 H6 SD_DQ10 Gl SD_DQ9 G4 S SD DOS F2
56. 02d pdf Sitronix ST7066U Character LCD Controller www sitronix com tw sitronix product nsf Doc ST7066U OpenDocument Samsung S6A0069X Character LCD Controller www samsung com Products Semiconductor DisplayDriverIC MobileDDI BWSTN S6A0069X S6A0069X htm Design Example Device DNA Reader and LCD Display Controller www xilinx com products boards s3astarter reference_designs htm dna_reader Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 55 UG334 v1 0 May 28 2007 Chapter 5 Character LCD Screen 56 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 6 VGA Display Port The Spartan 3A 3AN Starter Kit board includes a VGA display port via a standard high density HD DB15 female connector Connect this port directly to most PC monitors or flat panel LCDs using a standard monitor cable As shown in Figure 6 1 the VGA connector is the left most connector along the top of the board VGA_R lt 3 gt 510 Q Red VGA_B lt 3 gt VGA_B lt 2 gt VGA_B lt 1 gt VGA_B lt 0 gt HD DB15 VGA Connector front view not VGA cable 82 5 Q Vertical VGA VSYNC VGA HSYNC 82 5 Q Horizontal UG334 c6 01 052407 Figure 6 1 WGA Connections from the Starter Kit Board The FPGA directly drives the five VGA signals via resistors Each red green and blue signal has four outputs from the FPGA tha
57. 1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX Indirect SPI Flash Programming Using IMPACT To program the attached and selected SPI PROM using the iMPACT software and the Indirect programming method follow the steps outlined below 1 Invoke iMPACT and select Configure devices using Boundary Scan JTAG as shown in Figure 12 11 BL iMPACT Welcome to iMPACT Please select an action from the list below here Automatically connect to a cable and identify Boundary Scan chain y C Prepare a PROM File C Prepare a System ACE File C Prepare a Boundary S can File SWF C Configure devices using Slave Serial mode Cancel UG332_c4_22 032807 Figure 12 11 Indirect Programming Method Uses JTAG 2 Select Finish 102 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Creating and Programming Configuration Images for SPI Serial Flash 3 Select the FPGA bitstream file bit to be programmed into the FPGA as shown in Figure 12 12 This step is superfluous but required for iMPACT 9 1i This step will be eliminated starting in IMPACT 9 2i This file is not the special FPGA based SPI programming application E Assign New Configuration File File name m level bit File type All Design Files bit rbt nky isc bsd y Fora Cancel All Bypass Enable Programming of BPI Flash Device Attached to this FP
58. 2 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 1 Introduction and Overview Thank you for purchasing the Xilinx Spartan 3A 3AN Starter Kit The board is invaluable to develop a Spartan 3A or Spartan 3AN FPGA application Getting Started The Spartan 3A 3AN Starter Kit board is ready for use right out of the box The design stored in external Flash exercises the various I O devices such as the VGA display and serial ports In addition it demonstrates new FPGA features such as selectable MultiBoot and the power saving Suspend mode To start using the board follow the simple steps outlined in Figure 1 1 CHECK JUMPER SETTINGS Optional Connect VGA display Optional Connect headphones connect AC wall adapter PS 2 RS 232 or amplified speakers Set SUSPEND switch to RUN position 6 Tum on power switch Control operation using See messages and 1 O 9 rotary push button switch instructions on LCD character display UG334_c1_01_052407 Figure 1 1 Powering Up the Starter Kit Board 1 Double check the position of the board jumpers as shown in Figure 1 2 page 14 These settings are required for the demonstration design to configure correctly 2 Optionally connect a VGA display device The display device can be a CRT a flat panel or even a projector Optionally connect headphones or amplified speakers to
59. 2 34 TXN_3 cND IAN cuc GND GND AB7 AB8 an TxP_3 Guo 74 cuc GND GND Y7 AA8 AA10 27 31 33 1 3 5 7 9 11 13 15 17 19 21 23 25 29 126 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Differential I O Connectors Table 15 4 provides further detail on the pin assignment including the differential pair association the FPGA ball assignment and the connecting header pin Table 15 4 Differential l O Connections and Header Connections Differential Pair Signal Name FPGA Ball FPGA Pin Name Signal Direction Header Pin Receive Header J2 Top Header RXN_ lt 0 gt B4 IO L31N 0 I O J2 6 RX_ lt 0 gt RXP_ lt 0 gt A4 IO_L31P_0 I O J2 5 RXN_ lt 1 gt A5 IO L28N 0 I O J2 10 RX 1 RXP 1 B6 IO L28P 0 I O J2 9 RXN 2 A6 IO L26N 0 I O J2 14 RX 2 RXP 2 A7 IO L26P 0 I O J2 13 RXN 3 A8 IO L22N 0 I O J2 22 RX_ lt 3 gt RXP_ lt 3 gt A9 IO L22P 0 I O J2 21 RXN_ lt 4 gt c10 IO L21N 0 I O J2 26 RX_ lt 4 gt RXP_ lt 4 gt A10 IO L21P 0 I O J2 25 IO_L18N_0 RX_CLK_N All GLK7 I O J2 30 nn IO L18P 0 RX CLK P A12 GCLK8 I O J2 29 Transmit Header J15 Bottom Header TXN_ lt 0 gt AA3 IO L03N 2 I O J1 6 TX 0 TXP 0 AB2 IO L03P 2 I O J1 5 TXN_ lt 1 gt AA4 IO_LO4N_2 I O J1 10 TX_ lt 1 gt TXP_ lt 1 gt AB3 IO L04P 2 I O J1 9 TXN_ lt 2 gt AB6
60. 7A 1 provides two ADCs Both analog inputs are sampled simultaneously when the AD_CONV signal is applied Interface Table 9 3 lists the interface signals between the FPGA and the ADC The SPI_SCK signal is shared with other devices on the SPI bus The active High AD CONV signal is the active Low slave select input to the DAC The DAC CLR signal is the active Low asynchronous reset input to the DAC Table 9 3 ADC Interface Signals Signal FPGA Pin Direction Description SPI SCK AA20 FPGA gt ADC Clock AD_CONV Y6 FPGA gt ADC Active High initiates conversion process ADC_OUT D16 FPGA lt ADC Serial data Presents the digital representation of the sample analog values as two 14 bit two s complement binary values SPI Control Interface Figure 9 6 provides an example SPI bus transaction to the ADC When the AD_CONV signal goes High the ADC simultaneously samples both analog channels The results of this conversion are not presented until the next time AD_CONV is asserted a latency of one sample The maximum sample rate is approximately 1 5 MHz The ADC presents the digital representation of the sampled analog values as a 14 bit two s complement binary value Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 75 UG334 v1 0 May 28 2007 Chapter 9 Analog Capture Circuit XILINX ADC_OUT Slave LTC1407A 1 A D Converter ap conv MA Po P 2a Ds Ds Ds De D De Do
61. Control Option 0 6 6 cc rr 18 Power Saving Suspend Mode serranas ri nenna ne eee nee eee 18 RS 232 Serial Port Control Option 0 6 66 19 Key Components and Features 0 0 0 e cece cece eens 19 Design Irade Offs unse de decida 21 Configuration Methods Galore u un nuanses nnn 21 Voltages for all Applications 22eeeeeeeeeeeneeeeeeenenene nenn 21 Spartan 3A 3AN Starter Kit Design Examples 0 000005 21 Choose a Spartan 3 Generation Starter Kit Board for your Needs 22 Spartan 3A 3AN FPGA Features and Embedded Processing Functions 22 Other Spartan 3 Generation Development Boards oooooocccoccoocrococnn o 23 Spartan 3A and Spartan 3AN FPGAs sess eee 23 Related Resources nee ea 24 Chapter 2 Switches Buttons and Rotary Knob Slide Switches 25 Locations and Labels 0 0 0 0 c ccc cece RR es 25 Operation esser soar acabe mre ideae Ci acceder dece qut esu AAA A 25 UCF Location Constraints see hs 25 SUSPEND Switch usse res 26 Push Button Switches Tissus re 27 Locations and Labels o oooooooooo RR RR 3h 27 Operation eoe conc A e o Ie C ee Qu b Pa eee doni 27 PROG BPush Button Switch ccc cc cee he 28 UCF Location Constraints esee Rh hr re 28 Rotary Push Button Switch 2222cceeseeeeseesneneeneneennn 28 Locations and Labels us 8a ER UR
62. DARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 18 gt LOC E17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 19 gt LOC D20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 20 gt LOC D21 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 21 gt LOC D22 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 22 gt LOC E22 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 23 gt LOC F18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 24 gt LOC F19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 25 gt LOC F20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 26 gt LOC E20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 27 gt LOC G20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 28 gt LOC G19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 29 gt LOC H19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 30 gt LOC J18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 31 gt LOC K18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 32 gt LOC K17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 33 gt LOC K19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 34 gt LOC K20 IOSTANDARD
63. DRAM Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 91 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX FPGA SPI_MISO SPILSCK p 16Mbit AT45DB161D AB20 AB14 AA20 16Mbit DATAFLASH_WP DATAFLASH_RST C14 C15 ST_SPI_WP ALT_SS_B C13 Y5 SPI Flash Select Jumpers J1 UG334_c12 02 052407 Figure 12 2 SPI Serial Flash Interface Table 12 1 SPI Flash PROM Interface Signals Signal 5 Direction Description SPI MISO AB20 FPGA PROM Serial data Master Input Slave Output SPI MOSI AB14 FPGA gt PROM Serial data Master Output Slave Input SPI SCK AA20 FPGA gt PROM Clock Actively toggles during configuration User I O pin after configuration SPI SS B Y4 FPGA gt PROM Asynchronous active Low slave select signal Actively drives Low during SPI Flash configuration mode User I O pin after configuration Drive High if unused Steered to selected SPI Flash PROM Select Jumpers J1 page 93 ALT_SS_B Y5 FPGA gt PROM Second asynchronous active Low slave select signal Pulled High during configuration User I O pin after configuration Drive High if unused Steered to selected SPI Flash PROM Select Jumpers J1 page 93 DATAFLASH_WP C14 FPGA gt PROM Write protect input to Atmel AT45DB161D PROM Must be High to program the PROM Has external 4 7kQ pull up resistor DATAFLASH RS
64. Ethernet PHY Connections 00sec ccc cece et eee arara MicroBlaze Ethernet IP Cores 0 0 ccc cc ccc cc ccna UCF Location Constraints 0 0000 00 ccc rs Related Resources Chapter 15 Expansion Connectors Hirose 100 Pin FX2 Edge Connector J17 ooooooocccccccccccccccnco Expansion Connector Compatibility ooooocccoccorrcccoonrrrocarcnr ee Voltage Supplies to the Connector 0 6 6 ee Connector Pinout and FPGA Connections 0 0 06 6 666s FX2 Connector Compatible Boards 0 66 Mating Receptacle Connectors aeri a ninia ei eee eens UCF Location Constraints ossis esaia esses nnn Differential I O Connectors sse Using Differential Inputs lssssslsssssls Ie Using Differential Outputs sssss n Differential Trace Layout Considerations oooccoooccorococnnrroroaa 34 Conductor Cable Assemblies 2X17 1 0 0 cece eee eee rennen UCF Location Constraints 0 ccc cece cece e ene ee te hn Six Pin Accessory Headers 2564 daichii ida eae ee ee LAA dd teva dead Me ben bean c ons J19 Header a ds J20 Header eese erbe en ae E d oe taco s Digilent Peripheral Modules ssssssseeeee eee UCF Location Constraints ae een ee ee Pac ben Connectorless Debugging Port Landing Pads J34 Chapter 16 Miniature Stereo Audio Jack Supported Audio Devices u ek IRR AGER UR n FPGA Comnections ccc eee e es
65. GA UG332_c4_23_032807 Figure 12 12 Select the FPGA Bitstream File and Enable SPI Programming Select Enable Programming of SPI Flash Device Attached to this FPGA Click Open The iMPACT software warns that it changed the Startup clock source over to the JTAG clock pin TCK The SPI Flash image is not affected This warning is safely ignored E Warning xi A WARNING iMPACT 2257 Startup Clock has been changed to JtagClk in the bitstream stored in memory but the original bitstream File remains unchanged UG332_c4_24 032807 Figure 12 13 iMPACT Uses the JTAG Clock Input TCK for Startup Clock when Programming via JTAG Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 103 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX 7 As shown in Figure 12 14 select the programming file for the attached SPI Flash PROM Add PROM File 21x Look in E switches_leds ex E3 Desktop File name Files of type UG332 c4 26 032907 Figure 12 14 Select the SPIPROM Programming Flle 8 Click Open 9 Select the part number for the attached SPI Flash PROM as shown in Figure 12 15 Select Device Part Name Select PROM Part Name Cancel Help UG332_c4_27_032907 Figure 12 15 Select SPI Flash PROM Type 10 Click OK 104 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Creating and Programming Configuration Image
66. LCD are ignored Clear Display Clears the display and returns the cursor to the home position the top left corner This command writes a blank space ASCII ANSI character code 0x20 into all DD RAM addresses The address counter is reset to 0 location 0x00 in DD RAM Clears all option settings The I D control bit is set to 1 increment address counter mode in the Entry Mode Set command Execution Time 82 us 1 64 ms Return Cursor Home Returns the cursor to the home position the top left corner DD RAM contents are unaffected Also returns the display being shifted to the original position shown in Figure 5 3 The address counter is reset to 0 location 0x00 in DD RAM The display is returned to its original status if it was shifted The cursor or blink move to the top left character location Execution Time 40 us 1 6 ms Entry Mode Set Sets the cursor move direction and specifies whether or not to shift the display These operations are performed during data reads and writes Execution Time 40 us Bit DB1 1 D Increment Decrement 0 Auto decrement address counter Cursor blink moves to left 1 Auto increment address counter Cursor blink moves to right This bit either auto increments or auto decrements the DD RAM and CG RAM address counter by one location after each Write Data to CG RAM or DD RAM command or Read Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 49 UG334
67. LOC L22 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 1 gt LOC A13 IOSTANDARD LVCMOS33 SLE FAST DRIVE 8 NET FX2_10 lt 2 gt LOC B13 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 3 gt LOC A14 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 4 gt LOC B15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 5 gt LOC A15 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 6 gt LOC A16 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 7 gt LOC A17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 8 gt LOC B17 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2 IO 9 LOC A18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 10 gt LOC C18 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_IO lt 11 gt LOC A19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 12 gt LOC B19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 13 gt LOC A20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 14 gt LOC B20 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 15 gt LOC C19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 16 gt LOC D19 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_10 lt 17 gt LOC D18 IOSTAN
68. LOC W21 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 6 gt LOC Y22 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 5 gt LOC V20 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 4 gt LOC V19 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 3 gt LOC U19 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 2 gt LOC U20 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED lt 1 gt LOC T19 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 NET LED 0 LOC R20 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 Figure 2 13 UCF Constraints for Eight Discrete LEDs Optional Discrete LEDs The Spartan 3A 3AN Starter Kit board provides two optional LEDs shown in Figure 2 14 Depending on which features are used by an application these LED connections may be also used as user I O pins FPGA PROG_B Pin Press to reset reprogram FPGA gt PROC E I Ec Fg ds FPGA_INIT_B FPGA_AWAKE W21 AB15 RED YELLOW FPGA DONE Pin Lit when FPGA is configured GREEN UG334 c2 14 052407 Figure 2 14 AWAKE and INIT B LEDs Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 31 UG334 v1 0 May 28 2007 32 Chapter 2 Switches Buttons and Rotary Knob XILINX AWAKE LED The yellow colored AWAKE LED connects to the FPGA s AWAKE pin and is used if the FPGA Suspend mode is enabled in the
69. M or DD RAM 0 cen hr 52 OPEN au ka eat 52 Fo r Bit Data Interface 2 2er eee ete eet ce a te I aan 52 Transferring Eight Bit Data over the Four Bit Interface 222222220 53 Initializing the Display east ee la a Rate ua 53 Power On Initialization ooooooooorrr ehh rrr 54 Display Configuration ers ee ends epe iun cu een 54 Writing Data to the Display ssssssseeeeeeeeee Ie 54 Disabling the Unused LED pereen estener e 55 Related Resources 0 00 e teen nnn eens 55 Chapter 6 VGA Display Port Signal Timing for a 60 Hz 640x480 VGA Display 58 VGA Signal Timing nen AAA ee 60 UCF Location Constraints oooooccccoooooo ee 61 Related Resources 61 Chapter 7 RS 232 Serial Ports A A ce Den et see res d cec ee 63 UCF Location Constraints uu sese ees 64 Chapter 8 PS 2 Mouse Keyboard Port E ub b LE siu A eade ria qe edita eden RM ee 66 MOUSE per 68 Voltage Supply nn ae ee arena goa 69 Adding a Second PS 2 Port Using a Y Splitter Cable 69 UCF Location Constraints 0 0000 00 cence ee eens 70 Related Resources o o ooooooooooo cece nee teen e 70 Chapter 9 Analog Capture Circuit Digital Outputs from Analog Inputs 00 00 0 72 Programmable Pre Amplifier sss cece eens 73 Ititetface ila Eu ed bale le es attire is Re OS a a ad 73 Programmable Gain Su A a re en
70. OC D7 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA B 0 LOC C7 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_HSYNC LOC C11 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_VSYNC LOC B11 IOSTANDARD LVTTL DRIVE 8 SLEW FAST Figure 6 4 UCF Constraints for VGA Display Port Related Resources Refer to the following links for additional information e VESA Wwww vesa org e VGA timing information www epanorama net documents pc vga_timing html Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 61 UG334 v1 0 May 28 2007 Chapter 6 VGA Display Port 62 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Chapter 7 RS 232 Serial Ports Overview As shown in Figure 7 1 the Spartan 3A 3AN Starter Kit board has two RS 232 serial ports a female DB9 DCE connector and a male DB9 DTE connector The DCE style port connects directly to the serial port connector available on most personal computers and workstations via a standard straight through serial cable For typical applications the board does not require null modem cables gender changers or crossover cables Use the DTE style connector to control other RS 232 peripherals such as modems or printers or perform simple loopback testing with the DCE connector Computer RS 232 Peripheral Standard Standard 9 pin serial cable 9 pi
71. OSI 121310111273 pour SSD AGAIN BGAN SCK SPI Control Interface i W rsi LJ 850 AMP CS CHANNEL 1 CHANNEL O AD_CONV AMP_DOUT AD_DOUT UG334_c9_02_052407 Figure 9 2 Detailed View of Analog Capture Circuit Digital Outputs from Analog Inputs 72 The analog capture circuit converts the analog voltage on VINA or VINB and converts it to a 14 bit digital representation D 13 0 as expressed by Equation 9 1 Viy 1 65V D 13 0 GAIN x AV 7 x 8192 Equation 9 1 The GAIN is the current setting loaded into the programmable pre amplifier The various allowable settings for GAIN and allowable voltages applied to the VINA and VINB inputs appear in Table 9 2 The reference voltage for the amplifier and the ADC is 1 65V generated via a voltage divider shown in Figure 9 2 Consequently 1 65V is subtracted from the input voltage on VINA or VINB The maximum range of the ADC is 4 25V centered around the reference voltage 1 65V Hence 1 25V appears in the denominator to scale the analog input accordingly www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Programmable Pre Amplifier Finally the ADC presents a 14 bit two s complement digital output A 14 bit two s complement number represents values between 213 and 213 1 Therefore the quantity is scaled by 8192 or 213 See Programmable Pre Amplifier to control t
72. P p xxP X XI BUFGDS LAN 0 Signal TOT Signal XX xxN H a External 1000 termination resistor b On chip differential input termination not provided on the Starter Kit UG334 c15 04 052407 Figure 15 4 Differential Input Termination Options Using Differential Outputs Differential inputs are supported within any I O bank However with Spartan 3A and Spartan 3AN FPGAs differential outputs are only supported on I O Bank 0 or 2 Differential outputs are powered by the respective I O bank output voltage Vcco On the Spartan 3A 3AN Starter Kit board I O Banks 0 1 and 2 are all powered by a 3 3V supply OBUFDS PAD T E LxxN 2 UG330_c12_06_072706 Signal Figure 15 5 Differential Outputs Differential Trace Layout Considerations Figure 15 6 shows board layout extracted from the Starter Kit board that highlights the differential I O signal traces These traces were routed for optimal signal integrity e All differential pairs are routed with matched 100 impedance on the top board layer for maximum performance e The traces were routed to avoid via where possible e The trace lengths for differential pairs routed to a specific header either the Receive or Transmit header were matched to within 0 25 inches e The differential signals connections on the FPGA use the outer two ball rings to avoid breakout congestion e The Receive differential clock pair highlighted i
73. PGA Pin J34 A top bottom Pin Signal Name Supply to FPGA 1 1 SHIELD I O Banks 0 1 2 2 2 GND TMS_B 3 3 TDO_XC2C JISEL 4 4 TCK B TDO_FX2 5 5 FX2_IO1 A13 6 6 FX2_IO2 B13 4 7 y FX2 IO3 A14 8 8 FX2 IO4 B15 9 9 FX2 IO5 A15 10 10 FX2 IO6 A16 11 11 FX2_IO7 A17 4 12 12 FX2_IO8 B17 4 13 15 FX2 IO9 A18 14 14 FX2 IO10 C18 15 15 FX2 IO11 A19 16 16 FX2 IO12 B19 ie 17 FX2_1013 A20 18 18 FX2 IO14 B20 19 19 FX2 IO15 C19 20 20 FX2 IO16 D19 21 21 FX2 IO17 D18 22 27 FX2 IO18 E17 29 23 FX2_IO19 D20 24 24 FX2 IO20 D21 25 25 FX2 IO21 D22 26 26 FX2 IO22 E22 27 27 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 123 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors 124 Table 15 1 XILINX Hirose 100 Pin FX2 Connector Pinout and FPGA Connections J17 FX2_1023 Signal Name FPGA Pin Shared FX2 Connector J34 A top bottom FX2 IO24 FX2 IO25 FX2 IO26 FX2 IO27 FX2_1028 FX2_IO29 FX2_IO30 FX2 IO31 FX2_1032 FX2_1033 FX2 IO34 FX2 IO35 FX2 IO36 FX2 IO37 FX2_1038 FX2_1039 FX2 IO40 GND FX2_CLKOUT FX2_CLKIN IND FX2_CLKIO GND 46 46 L22 47 47 48 48 49 49 50 50 SHIELD FX2 Connector Compatible Boards The following boards are compa
74. Raw dee E Ere br Ea E 28 Opera cus oss segun Seius epa doeet Mk ae eee Me s Ced ge st a ea te A 28 Push Button Switch cceli s 28 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 XILINX Rotary Shaft Encoder 2 sss shes eee hen e Bene as 29 UCF Location ConstraidtS o o o ooo eere 30 Discrete LEDS 000 DRE a PCIE e Pei ACER IA Ed 30 Locations and Labels ees more e re pd ceo e ted b E Wes dC ebd Ros 30 Operati n ene route A A e C ee Qu b P E dedere dea 31 UCF Location Constraints eee nen 31 Optional Discrete LEDs sssssssssssssssse ee 31 AWAREIED Per 32 INIT BLED a ted re Wee os Letra HE PA edd EE eee 32 UCF Location Constraints eee eb re rer exe Me dais 32 Chapter 3 Clock Sources OS roin A E UP EL UE RUE Tre TIS 33 Clock Connections 34 50 MHz On Board Oscillator uuussssssessee e 34 Auxiliary Clock Oscillator Socket suus esses 34 SMA Clock Input or Output Connector 00 0 34 UCF Constraints oscila i dc p RI HR Epp pA 34 Location iiid e re en Bean 34 Clock Period Constraints nic ea RE PETCVEA a ln 35 Related Resources 35 Chapter 4 FPGA Configuration Options Configuration Mode Jumpers oooooocccccccccocccco ocre 39 Xilinx Platform Flash Configuration PROM s 0005 40 PROG Push B tton SWEDEN RAN 40 DONE Pin LED patada da A Ul eed ae 41 Programming the FPGA or Pl
75. STMicroelectronics M29DW323DT Parallel NOR Flash www xilinx com products boards s3astarter reference_designs htm parallel_flash _programmer This design transforms the Spartan 3A or Spartan 3AN FPGA into a programmer for the 32Mbit STMicroelectronics M29DW323DT parallel NOR Flash memory This memory optionally holds configuration images for the FPGA and provides general non volatile storage for other applications implemented within the FPGA Using a simple terminal program this application provides the following capabilities Erase the memory in part or in full Read the memory to verify contents Download complete configuration images using standard MCS files Manually program individual bytes Display the device identifier and 64 bit unique device numbers e Spartan 3A 3AN Device DNA Reader www xilinx com products boards s3astarter reference designs htmstdna reader This design uses a PicoBlaze processor to read the unique Device DNA identifier embedded in each Spartan 3A 3AN FPGA and then display it on the LCD screen Choose a Spartan 3 Generation Starter Kit Board for your Needs 22 The Spartan 3A and Spartan 3AN Starter Kit boards are best for prototyping Spartan 3A 3AN FPGA applications Depending on specific requirements however Xilinx and third party companies offer development boards that better suit other needs Spartan 3A 3AN FPGA Features and Embedded Processing Functions The Spartan 3A 3AN Starter
76. Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PRO
77. Supports Direct Programming for SPI Serial Flash Memories 2 Right click in the area indicated 3 Select Add SPI Device 98 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Creating and Programming Configuration Images for SPI Serial Flash 4 Select a previously formatted PROM file as shown in Figure 12 7 Add Device El ES Look in o led crazy E ex E3 My Recent Documents ashPROM mcs N mm 3 METAS File name MySPIFlashPROM mcs Open Places Files of type fan Design Files mcs exo y Figure 12 7 Select a Previously Formatted PROM File 5 Click Open 6 Select the Part Name for a supported SPI serial Flash as shown in Figure 12 8 Select Device Part Name Select PROM Part Name UG332_c4_05_101006 Figure 12 8 Select a Supported SPI Flash Memory Device 7 Click OK Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 99 Chapter 12 SPI Serial Flash XILINX 8 The iMPACT software displays the selected SPI Flash PROM as shown in Figure 12 9 iMPACT C Data my designs led crazy led crazy 700a ipf Direct 3 File Edit View Operations Options Output Debug Window Help le El BExXx ix x Ba Boundary Scan TE Slaves erial qa SelectMAP ls Ta Desktop Configu 2a Direct SPI Config xl m25p16 myspiflashprom a gt Ve
78. T C15 FPGA gt PROM Reset input to Atmel AT45DB161D PROM Must be High to read program or erase the PROM Has external 4 7kQ pull up resistor ST SPI WP C13 FPGA gt PROM Write protect input to ST M25P16 PROM Must be High to program the PROM Has external 4 7kQ pull up resistor 92 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX SPI Flash PROM Select Jumpers J1 SPI Flash PROM Select Jumpers J1 The J1 jumper block shown in Figure 12 1 defines which SPI Flash PROM is connected to the FPGA for Master SPI mode configuration and which is optionally available via a separate second SPI slave select signal Table 12 2 indicates how the FPGA s CSO_B signal is steered to one of the SPI Flash PROMs during Master SPI configuration mode The jumpers are designed so that there can be no conflict e Ifboth jumpers are inserted and oriented vertically then the FPGA configures from the Atmel SPI Flash PROM After configuration the FPGA application selects the Atmel PROM using the SPI_SS_B signal and the STMicro PROM using the ALT_SS_B signal e Ifboth jumpers are inserted and oriented horizontally then the FPGA configures from the STMicro SPI Flash PROM After configuration the FPGA application selects the STMicro PROM using SPI_SS_B signal and the Atmel PROM using the ALT_SS_B signal Table 12 2 SPI Flash PROM Select Jumper Settings
79. T LCD_DB lt 1 gt LOC AB18 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 0 gt LOC Y13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO Figure 5 2 UCF Location Constraints for the Character LCD LCD Controller The 2 x 16 character LCD has an internal Sitronix ST7066U graphics controller that is functionally equivalent with the following devices e Samsung S6A0069X or KS0066U e Hitachi HD44780 e SMOS SED1278 Memory Map The controller has three internal memory regions each with a specific purpose DD RAM CG ROM and CG RAM The display must be initialized before accessing any of these memory regions DD RAM The Display Data RAM DD RAM stores the character code to be displayed on the screen Most applications interact primarily with DD RAM The character code stored in a DD RAM location references a specific character bitmap stored either in the predefined CG ROM character set or in the user defined CG RAM character set Figure 5 3 shows the default address for the 32 character locations on the display The upper line of characters is stored between addresses 0x00 and Ox0F The second line of characters is stored between addresses 0x40 and 0x4F Character Display Addresses a esses AA E 2 u jar um pao ja jas as ee o 1 2 3 4 5 6 7 8 9 10 1 12 13 14 15 16 17 40 Figure 5 3 DD RAM Hexadecimal Addresses No Display Shifting Physically the
80. TTL LVTTL DRIVE 4 SLEW SLOW 6 IOSTANDARD 5 IOSTANDARD ool F1 RL Figure 7 2 UCF Location Constraints for DTE RS 232 Serial Port z ET RS232_DCE_RXD LOC E16 IOSTANDARD LVTTL ET RS232_DCE_TXD LOC F15 IOSTANDARD LVTTL DRIVE 4 SLEW SLOW A Figure 7 3 UCF Location Constraints for DCE RS 232 Serial Port www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 8 PS 2 Mouse Keyboard Port The Spartan 3A 3AN Starter Kit board includes a PS 2 mouse keyboard port and the standard six pin mini DIN connector labeled J28 on the board Figure 8 1 shows the PS 2 connector and Table 8 1 shows the signals on the connector Use the primary connections indicated to connect a mouse or keyboard directly to the board Also see Adding a Second PS 2 Port Using a Y Splitter Cable page 69 Secondary Connection Primary Connection requires Y splitter cable SN VAAV PS2 DATA1 V11 PS2 DATA2 Y12 V11 2700 2700 PS2 CLK2 U11 UG334 c8 01 052407 Figure 8 1 PS 2 Connector Location and Signals Table 8 1 PS 2 Connector Pinout PS 2 DIN Pin Signal FPGA Pin Primary data connection PS2 DATA1 M 2 Secondary data connection when using PS 2 splitter cable vn PS2_DATA2 3 4 Primary clock connection 7 PS2_CLKI nr 6 Secondary data connection with using
81. VIDED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX INCONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT AND THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High R
82. adjacent to the BIN_EAST push button It uses a female six pin 90 socket Four FPGA pins connect to the J18 header J18_10 lt 4 1 gt The board supplies 3 3V to the accessory board mounted in the J18 socket on the bottom pin FPGA J18_103 UG334_c15_08_052407 Figure 15 8 FPGA Connections to the J18 Accessory Header J19 Header The J19 header shown in Figure 15 9 is left unpopulated on the board Four FPGA pins connect to the J19 header J19 IO 4 1 The board supplies 3 3V to the accessory board mounted in the J19 socket on the bottom pin FPGA These pins connect to unpopulated mounting holes UG334 c15 09 052407 Figure 15 9 FPGA Connections to the J19 Accessory Header Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 131 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors XILINX 132 J20 Header The J20 header shown in Figure 15 10 is the top most six pin connector along the right edge of the board It uses a female six pin 90 socket Four FPGA pins connect to the J20 header J20_10 lt 4 1 gt The board supplies 3 3V to the accessory board mounted in the J20 socket on the bottom pin UG334_c15_10_052407 Figure 15 10 FPGA Connections to the J20 Accessory Header Digilent Peripheral Modules Digilent Peripheral Modules PMODs are small I O interface boards that offer an ideal way to extend the capabilities of programmable logic and embedded control boards They allow sensit
83. aint File UCF constraints for the amplifier interface including the I O pin assignment and I O standard used NET AD CONV LOC Ye IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET SPI SCK LOC AA20 IOSTANDARD LVTTL SLEW SLOW DRIVE 12 NET AD DOUT LOC D16 IOSTANDARD LVTTL Figure 9 8 UCF Location Constraints for the ADC Interface 76 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Connecting Analog Inputs Connecting Analog Inputs Connect AC signals to VINA or VINB via a DC blocking capacitor Related Resources Refer to the following links for additional information Xilinx PicoBlaze Soft Processor http www xilinx com picoblaze LTC6912 Dual Programmable Gain Amplifiers with Serial Digital Interface http www linear com pc downloadDocument do navId H0 C1 C1154 C1009 C1121 P7596 D5359 LTC1407A 1 Serial 14 bit Simultaneous Sampling ADCs with Shutdown http www linear com pc downloadDocument do navId H0 C1 C1155 C1001 C1158 P2420 D1295 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 77 UG334 v1 0 May 28 2007 Chapter 9 Analog Capture Circuit 78 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Chapter 10 Digital to Analog Converter DAC The Spartan 3A 3AN Starter Kit board includes an SPI compatible four channe
84. and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indicates when an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Voltage Supply The L R and C fields in the status byte correspond to Left Right and Center button presses A 1 indicates that the associated mouse button is being pressed Voltage Supply The PS 2 port on the Spartan 3A 3AN Starter Kit board is powered by 5V Although the Spartan 3A 3AN FPGA is not a 5V tolerant device it can communicate with a 5V device using 270 series current limiting resistors as shown in Figure 8 1 page 65 Adding a Second PS 2 Port Using a Y Splitter Cable Most applications that use the PS 2 port will connect a mouse or a keyboard directly to the Spartan 3A 3AN Starter Kit board connector These applications use the primary FPGA connections to the PS 2 port as shown in Figure 8 1 page 65 However it is possible to include a second PS 2 port by connecting a PS 2 Y splitter cable to the PS 2 connector on the board Figure 8 6 shows an example of such a cable The Spartan 3A 3AN Starter Kit does not include such a cable but one can be purchased from a local electronics supply store or via the web Some example vendors and part numbers are listed below Check var
85. aracters are stored in CG ROM at their equivalent ASCII code addresses www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX z a SS o O l LCD Controller L 230001001 xxxx1010 xxxx1011 xxxx11o0o0 xxxx1101 EEE TO ONTO MMMM anan UG230_c5_02 030306 Figure 5 4 LCD Character Set DB7 Upper Data Nibble po 9000000514171 pgs 9001111001111 pm 701100111100 1 1 0010304010103 xxxxO0000 Bal FI 35 E xxxx0001 Hb ale PF E xxxx0010 2IBIF rr B 200000 1 1 aW LS eun B xxxxOo100 8 44 DIT El Ee E xxxx0101 E SEU Mas xxxx0110 EFI E xxxx0111 BEN sm xxxx1000 S amp H EHBHEEU OUR SKK lt Una SE dE nr TALLE E E E juu Ei 2 T d ri spere sa s near ema Base B B E ia The character ROM contains the ASCII English character set and Japanese katakana characters The controller also provides for eight custom character bitmaps stored in CG RAM These eight custom characters are displayed by storing character codes 0x00 through 0x07 in a DD RAM location CG RAM The Character Generator RAM CG RAM provides space to create eight custom character bitmaps Each custom character location consists of a 5 dot by 8 line bitmap as shown in Figure 5 5 The Set CG RAM Address command initializes the address counter before reading or writing to CG RAM Write CG RAM data using the Write Data to CG RAM or DD RAM
86. ash Programming www xilinx com products boards s3astarter reference designs htmstout 14 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Operating the Default Demonstration Design Operating the Default Demonstration Design The demonstration design programmed onto the Spartan 3A 3AN Starter Kit board provides various output information depending on what I O or display devices are connected The VGA and audio ports provide the richest experience VGA Display If a VGA display is connected to the board then the Starter Kit board displays graphics similar to that shown in Figure 1 3 Until one of the four push buttons around the rotary knob Figure 2 5 page 27 is pressed the display automatically rotates a graphic image and zooms in and out around the image This is called AutoPilot mode A brief text overview describing the board appears along the left edge Blue text at the bottom of the screen presents the menu system Text Description Rotating and Zooming Graphics Rotary Push Button Menu System UG330 ct 03 032207 Figure 1 3 Rotating Zooming Graphics Menu System Displayed on VGA Screen Rotary Knob Push Button Menu System The Spartan 3A 3AN Starter Kit board demonstration design uses the rotary knob and surrounding push button switches shown in Figure 2 5 page 27 to implement a menu system The menu display appears in blue text at the bottom of the VGA outpu
87. ata from CG RAM if the command follows a previous Set CG RAM Address command After the read operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command However a display shift is not executed during read operations Execution Time 40 us The board has an eight bit data interface to the character LCD Other Xilinx boards use a four bit interface As shown in Figure 5 1 the Spartan 3A 3AN Starter Kit board supports both an eight bit and a four bit interface for compatibility reasons Many existing reference designs are already built around a four bit interface Four Bit Data Interface 52 Figure 5 6 illustrates a write operation to the LCD showing the minimum times allowed for setup hold and enable pulse length relative to the 50 MHz clock 20 ns period provided on the board www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Operation loons N cion gt ovas Y woa LCD_RW LCD_E Upper Lower 4 bits 4 bits LCD RS AAA XxX I I I N NN LOD_DB lt 7 4 gt X O 77 OOOO LCD_RW TNA TT TT UON a o LCD E___ A N N 40 us UG330_c5_03_072106 Figure 5 6 Character LCD Interface Timing The data values on LCD_DB lt 7 4 gt and the register select LCD_RS and the read write LCD_RW control signals must be set up and stable at least 40 ns before the enable LCD_E goes High The enable signal must remain High for 230 n
88. atform Flash PROM via USB 41 Connecting the USB Cable 22eeeeeeeeeeeeeeneeeeeeenennnnnn 41 Platform Flash Programming Example in Spartan 3 Generation Configuration User GUIAS ars ir A es eee cece a 42 Chapter 5 Character LCD Screen OvetVleW il a Re 43 Character LCD Interface Signals ur see 44 Voltage Compatibility ae REA ren ee 44 UCF Location Constraints 0 0000 0c ccc ce ee 44 LCD Controller 4 563556 vie ei bec ic phi ee idas 45 Memory Map ii cers ota eons A dti dee eed ee 45 JD RAUM IS oc Ba eens a epo do euet eg eerte tdt e uo oe dics 45 CG ROM umi de tae Bow Grae Rake hy RR Baca a Le EN iii asa 46 CG RAM e bri a vale ener eae sed AU metere e dc atr tec adu so ce ale 47 Command Set crx a A ee prO e es ee aca 48 Disabledi 2 ep 26 2 0020 08820 id ee da en wets 49 Clear Display iris ii a gets te endi eut eng 49 Return Cursor HOME 412i a aX REX x EY rada 49 Entry Mode Sets cedes Seta be E diced ec deter pte et Le a gt 49 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Display On Off un erraten 50 Cursor and Display Shit 22 2 akt ave ii A A id 50 Function Set iive a a A 51 Set CG RAM Address ooooooo eee eee hh hh 51 Set DDRAM Address 2 4544 eub soy RR used Rer ERA a Re ds 51 Read Busy Flag and Address sees nnn 51 Write Data to CG RAM or DD RAM 0 0c hrs 51 Read Data from CG RA
89. cess to SPI serial Flash and parallel NOR Flash PROMs after configuration Enabled during FPGA Configuration Master Serial or JTAG Platform Flash continuously enabled The FPGA application can read additional data from Platform Flash after Master Serial configuration as described in or JTAG application note XAPP694 Reading User Data from Configuration PROMs The FPGA application has no read access to SPI Flash or parallel NOR Flash Always Enabled PROG Push Button Switch The PROG push button switch labeled in Figure 4 1 forces the FPGA to reconfigure from the configuration memory source selected by the Configuration Mode Jumpers page 39 Press and release this button to restart the FPGA configuration process at any time 40 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX DONE Pin LED DONE Pin LED The DONE pin LED labeled in Figure 4 1 lights whenever the FPGA is successfully configured If this LED is not lit then the FPGA is not configured Programming the FPGA or Platform Flash PROM via USB The Spartan 3A 3AN Starter Kit includes embedded USB based programming logic and a USB endpoint with a Type B connector Via a USB cable connection with the host PC the iMPACT programming software directly programs the FPGA the Platform Flash PROM or the on board CPLD Direct programming of the parallel or serial Flash PROMs is not pres
90. control the FPGA s configuration mode Inserting a jumper grounds the associated mode pin Insert or remove individual jumpers to select the FPGA s configuration mode and associated configuration memory source The J26 jumper block is shown in Figure 4 1 Configuration Mode Jumpers Table 4 1 Configuration Mode Jumper Settings Mode Pins J26 Jumper J46 Jumper Configuration Mode M2 M1 MO FPGA Configuration Image Source Settings Setting Internal Master SPI 0 1 1 Spartan 3AN Starter Kit Board only This mode configures a Spartan 3AN FPGA using the internal In System Flash memory This mode is not supported on the Spartan 3A Starter Kit board Master Serial 0 0 0 Platform Flash PROM Set the J46 jumper per Table 4 2 E Master SPI 0 0 1 Select SPI Serial Flash PROM starting at see Chapter 12 address 0 SPI Serial Flash Select specific SPI Flash PROM using Jumper J1 Table 12 2 page 93 DISABLE Disable the Platform Flash PROM via J46 jumper per Table 4 2 Master BPI Up 0 1 0 Parallel NOR Flash PROM starting at see Chapter 11 address 0 and incrementing through address Parallel NOR Flash space PROM Disable the Platform Flash PROM via J46 jumper per Table 4 2 JTAG 1 0 1 Downloaded from host via USB JTAG port a Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 www xilinx com 39 Chapter 4 FPGA Configuration Options XILINX Xilinx Platform F
91. d pins are interspersed with the signal pins for improved signal integrity over any attached cable Power is also supplied via the nominally 3 3V rail labeled VCCO_012 The power connectors are for potential daughter cards that plug into the connector The J15 connector is primarily designed to transmit output data while the J2 connector is primarily designed to receive input data However both headers are equally good at transmitting differential data The Receive header does have special provisions for capturing the receive clock input The pin assignment for the J2 Receive connector appears in Table 15 2 and in Table 15 4 The FPGA ball assignment is listed in parentheses Table 15 2 Receive Header J2 2 4 6 8 10 14 16 18 20 22 24 26 30 RXN_2 12 3 3V 3 3V 3 3V RXN_O RXN_1 GND GND oo GND Be RXP_O RXP_1 GND GND vag GND Bee RXP_2 nom 3 3V 3 3V 3 3V 28 32 34 RXN 3 Feng AXN_4 cun GND GND A8 C10 A11 E RXP 4 AVES GND GND A9 A10 2 A12 27 31 33 1 3 5 7 9 11 13 15 17 19 21 23 25 29 The pin assignment for the J15 Transmit connector appears in Table 15 3 and in Table 15 4 The FPGA ball assignment is listed in parentheses Table 15 3 Transmit Header J15 2 4 6 8 10 14 16 18 20 22 24 26 0 TXN_2 fing 3 3V 3 37 3 3V TXN_O TXN_1 GND GND ew GND 7 TXP_O TXP_1 GND GND Bw GND Be TXP_2 Woe 3 3V 3 3V 3 3V 28 30 3
92. dicated D15 pin Instead this function is shared with the least significant address pin On the Flash memory component this pin is named D15 A 1 which connects to the FPGA s AO address pin After configuration if the FPGA application asserts NF_BYTE High use NE_AO to carry the D15 signal Connect the other higher order data lines to FPGA user I Os Upper 7 bits of a data byte or lower 8 bits of a 16 bit halfword Connects to FPGA pins D 7 1 to support the BPI configuration NOR Flash FPGA Pin Category Signal Name Number NF_D15 T17 NF A0 NF D14 R21 NF D13 T22 NF D12 U22 NF D11 U21 NF D10 V22 NF D9 W22 NF D8 T20 E NF D7 Y9 P NF D6 AB9 NF D5 Y11 NF_D4 AB11 NF_D3 U13 NF_D2 AA17 NF D1 Y17 NF DO AB20 SPI MISO Bit 0 of a data byte and a 16 bit halfword Connects to FPGA pin DO DIN to support the BPI configuration Shared with other SPI peripherals and Platform Flash PROM Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 www xilinx com 85 Chapter 11 Parallel NOR Flash PROM XILINX Table 11 1 FPGA to Flash Connections Continued NOR Flash Category Signal Name NF_BYTE FPGA Pin Number Y21 Function Active Low Flash Byte Enable Connects to FPGA pin LDC2 to support the BPI configuration 0 x8 data 1 x16 data NF_CE W20 Active Low Flash Chip Enable Connects to FPGA pin LDCO to support the
93. ds the configuration image stored at address 0 in Flash at power up or whenever the PROG B button is pressed Spin the rotary knob to select a new FPGA configuration image The blue text at the bottom of the display updates with each click of the rotary knob For example the application displays Buttons Load Configuration x where x corresponds to the bitstream image listed in Table 1 2 Table 1 2 describes the bitstreams preloaded on the board After selecting the desired image press one of the four push button switches that surround the rotary knob This action causes the FPGA to load the selected image from external Flash memory To change to the Scroll or Rotate Graphic mode press the rotary knob www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Operating the Default Demonstration Design Table 1 2 FPGA Configuration Bitstreams Preprogrammed on the Starter Kit Board FPGA Configuration Bitstream FPGA Application Reference Design Example 0 Starter Kit board demonstration design Loaded at power up default www xilinx com products boards s3astarter reference_designs htm demo Device DNA Reader Reads the FPGA s unique Device ID value and displays it on the character LCD 1 screen www xilinx com products boards s3astarter reference_designs htm dna_reader Fractal Generator Computes fractal images in real time and displays on the VGA port A u
94. e FPGA with a special design that performs the SPI PROM programming and uses the JTAG interface as a serial communications port During the process the FPGA s DONE output is High and the DONE LED is lit because the FPGA is configured with the programming logic All pins that are not connected to the SPI Flash PROM or the JTAG interface have an internal pull up resistor to the Vcco voltage supply associated with the pin Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 95 UG334 v1 0 May 28 2007 Chapter 12 SPI Serial Flash XILINX Table 12 5 Summary of SPI Flash PROM Programming Options Direct Method Indirect Method ISE Version Required ISE 9 1i or later IER ic Father Interface Cable Connection Directly to SPI PROM FPGA s JTAG Port High DONE Pin SUMUS during Low FPGA is configured with Programming special programming design Required PROG B Control PROG B Low N A Status of non SPI Pins High impedance because Pulls righ oo a pull up resistor to associated during Programming PROG_B Low Veco supply input Direct Programming Method The iMPACT software supports direct programming of select SPI serial Flash The Spartan 3A 3AN Starter Kit board primarily supports direct programming using the embedded USB JTAG programmer included on the board Optionally the SPI Flash can be programmed using a separate programming cable as well Using Embedded USB JTAG Programmer Follo
95. e memory attached to the FPGA through the FPGA s JTAG port During the programming process the FPGA is configured with a special programming application Consequently the FPGA s DONE pin is High and the DONE LED remains lit throughout the programming process Note Any information displayed on the LCD screen remains on the screen throughout the programming process If it appears that programming was successful but that the DONE pin did not go High at the end double check the mode pin settings Jumper Settings To program the attached and selected SPI PROM using the Indirect method configure the board as described below 1 Disconnect power to the board 2 Insert a jumper in jumper block J1 as shown in Figure 12 4 The figure shows the setting to program the STMicro M25P16 PROM Alternatively set the jumper to program the Atmel AT45DB161D DataFlash PROM 3 Set the FPGA mode select pins for Master SPI mode using jumper J26 as shown in Table 12 4 The location of the J26 jumper appears in Figure 12 1 4 Disable the Platform Flash PROM by removing jumper J46 shown in Figure 12 1 and Table 12 4 5 The PROG_B pin is not used by the Indirect programming mode Be sure that jumper J16 is removed PROG B is left floating 6 Connect the included USB cable to both the Starter Kit board and the computer running iMPACT 7 Re apply power to the board Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 101 UG334 v
96. e signal timings in Table 6 2 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz 1 refresh Figure 6 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpyy and front and back porch intervals Tpp and Tgp is based on observations from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 6 2 640x480 Mode VGA Timing Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7 ms 416 800 521 32 us 800 TIp sp Display time 15 36 ms 384 000 480 25 6 us 640 Tpw Pulse width 64 us 1 600 2 3 84 ys 96 Trp Front porch 320 ps 8 000 10 640 ns 16 Tgp Back porch 928 us 23 200 29 1 92 us 48 gt l 4 1 SM Taisp a s l Sa l Tow Rp UG230 c6 03 021706 Figure 6 3 NGA Control Timing Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row 60 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX UCF Location Constraints A separate counter tracks the vertical timing The vertical sync counter increments with each HS pulse and decoded values generate
97. e to disable the Platform Flash PROM by removing jumper J46 as shown in Table 11 3 Configuration Mode BPI Up Mode Pins M2 M1 MO 0 1 0 Flash FPGA Configuration Image in FPGA starts at address 0 and increments through address space Mode Select Jumper Settings J26 Platform Flash Enable J46 88 www xilinx com Spartan 3A 8AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Creating and Programming Configuration Images for Parallel Flash Creating and Programming Configuration Images for Parallel Flash Refer to the Master BPI Mode chapter in the Spartan 3 Generation Configuration User Guide for information on how to create and format FPGA configuration images for parallel Flash To program the parallel Flash memory see the associated design example e UG332 Spartan 3 Generation Configuration User Guide www xilinx com bvdocs userguides ug332 pdf e Design Example Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www xilinx com products boards s3astarter reference_designs htm parallel_flash programmer Related Resources Refer to the following links for additional information e STMicroelectronics M29DW323DT 32 Mbit Parallel NOR Flash PROM www st com stonline products literature ds 8516 pdf e Design Example Programmer for the STMicroelectronics M29DW323DT Parallel NOR Flash www xilinx com products boards s3as
98. ected SPI Flash PROM To successfully configure the FPGA from the selected external SPI Flash PROM set the following jumpers as described below e Set the FPGA configure mode using the Jumper J26 jumper header shown in Table 12 4 e Disable the Platform Flash PROM using Jumper J46 shown in Table 12 4 Table 12 4 Configuration Mode Jumper Settings for Master SPI Mode J26 J46 Mode Pins Platform Flash Configuration Mode M2 M1 MO Jumper J26 Settings Enable J46 Master SPI 0 0 1 e Select one of the SPI serial Flash PROMs as the SPI configuration source as shown in Table 12 2 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX UCF Location Constraints UCF Location Constraints Figure 12 3 provides the UCF constraints for the SPI serial Flash PROM including the I O pin assignment and the I O standard used some connections shared with SPI Flash DAC ADC and AMP NET SPI_MISO LOC AB20 IOSTANDARD LVTTL NET SPI_MOSI LOC AB14 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET SPI_SCK LOC AA20 IOSTANDARD LVTTL SLEW SLOW DRIVE 12 NET SPI_SS B LOC Y4 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 NET ALT_SS_B LOC Y5 IOSTANDARD LVTTL SLEW SLOW DRIVE 4 write protect and reset controls for Atmel AT45DB161D PROM NET DATAFLASH_WP LOC C14 IOSTANDARD LVTTL SLEW NET DATAFLASH_RST
99. ently supported Connecting the USB Cable The kit includes a standard USB Type A Type B cable similar to the one shown in Figure 4 2 The actual cable color might vary from the picture USB Type B Connector Connects to Starter Kit s USB connector USB Type A Connector Connects to computer s USB connector UG230_c4_04_030306 Figure 4 2 Standard USB Type A Type B Cable The wider and narrower Type A connector fits the USB connector at the back of the computer After installing the Xilinx software connect the square Type B connector to the Spartan 3A 3AN Starter Kit board as shown in Figure 4 3 The USB connector is on the left side of the board immediately next to the Ethernet connector When the board is powered on the Windows operating system automatically recognizes and installs the associated driver software UG334_c4_03_052407 Figure 4 3 Connect the USB Type B Connector to the Starter Kit Board Connector Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 41 UG334 v1 0 May 28 2007 42 Chapter 4 FPGA Configuration Options XILINX When the USB cable driver is successfully installed and the board is correctly connected to the PC a green LED lights up indicating that the programming cable is ready The USB connection also has a red LED which only lights if the Xilinx software is programming firmware updates to the USB interface Platform Flash Programming Example in Spartan 3 Generation Conf
100. etween the FPGA and the Flash memory device Although the XC3S700A AN FPGA only requires just slightly over 2 6 Mbits per uncompressed configuration image the FPGA to Flash interface on the board supports up to a 256 Mbit Flash The Spartan 3A 3AN Starter Kit board ships with a 32 Mbit device Address lines SF_A lt 25 22 gt are not used 84 XILINX In general the Flash memory device connects to the FPGA to support Byte Peripheral Interface BPI configuration as described in Table 11 1 Table 11 1 FPGA to Flash Connections NOR Flash FPGA Pin Category Signal Name Number Function NF_A25 G17 The upper four Flash addresses are not used Sum ee NF_A23 B21 NF_A22 B22 NF_A21 C21 Connects to FPGA pins A 21 0 to support NE_A20 C22 the BPI configuration NF_A19 F21 NF_A18 F22 NF_A17 H20 NF_A16 H21 NF_A15 G22 NF_A14 H22 NF A13 J20 3 NF_A12 i NF A11 J22 NF_A10 K22 NF_A9 N17 NF_A8 N18 NF_A7 N19 NF_A6 N20 NF_A5 N21 NF_A4 N22 NF_A3 P18 NF_A2 R19 NF_A1 T18 NF_AO T17 www xilinx com Spartan 3A 8AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Flash Connections Table 11 1 FPGA to Flash Connections Continued Function Upper 8 bits of a 16 bit halfword when Flash is configured for x16 data NF_BYTE High The Flash does not have a de
101. fferent configuration memory sources that all must function well together The extra configuration functions make the starter kit board more complex than typical FPGA applications The starter kit board also includes an on board USB based JTAG programming interface The on chip circuitry simplifies the device programming experience In typical applications the JTAG programming hardware resides off board or in a separate programming module such as the Xilinx Platform USB cable Voltages for all Applications The Spartan 3A 3AN FPGA typically operates with two supply rails 1 2V and 3 3V The Spartan 3A 3AN Starter Kit board showcases a quadruple output regulator developed by National Semiconductor specifically to power Spartan 3 Generation FPGAs This regulator is sufficient for most standalone FPGA applications Spartan 3A 3AN Starter Kit Design Examples Visit the Spartan 3A 3AN Starter Kit Design Examples web page to download and use the latest applications that specifically target the starter kit board e Spartan 3A 3AN Starter Kit Design Examples Web Page www xilinx com products boards s3astarter reference designs htm The list of designs is ever growing and the applications are often updated to the latest software releases The following list provides a sample of design examples e Spartan 3A 3AN Starter Kit Demo Design Overview www xilinx com products boards s3astarter reference designs htmitdemo This describes the out
102. gnal levels and the 3 3V LVCMOS outputs provided by the FPGA meet the 5V TTL voltage level requirements The 3900 series resistors on the data lines prevent overstressing on the FPGA and StrataFlash I O pins when the character LCD drives a High logic value The character LCD drives the data lines when LCD_RW is High Most applications treat the LCD as a write only peripheral and never read from the display UCF Location Constraints Figure 5 2 provides the UCF constraints for the Character LCD including the I O pin assignment and the I O standard used 44 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX LCD Controller NET LCD_E LOC AB4 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_RS LOC Y14 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_RW LOC W13 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 7 gt LOC Y15 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 6 gt LOC AB16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 5 gt LOC Y16 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 4 gt LOC AA12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 3 gt LOC AB12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NET LCD_DB lt 2 gt LOC AB17 IOSTANDARD LVCMOS33 DRIVE 4 SLEW QUIETIO NE
103. he GAIN settings on the programmable pre amplifier The reference design files provide more information on converting the voltage applied on VINA or VINB to a digital representation see Related Resources page 77 Programmable Pre Amplifier Interface The LTC6912 1 provides two independent inverting amplifiers with programmable gain The purpose of the amplifier is to scale the incoming voltage on VINA or VINB so that it maximizes the conversion range of the DAC namely 1 65 1 25V Table 9 1 lists the interface signals between the FPGA and the amplifier The SPI_MOSI and SPI_SCK signals are shared with other devices on the SPI bus The AMP_CS signal is the active Low slave select input to the amplifier Table 9 1 AMP Interface Signals Signal FPGA Pin Direction Description SPI_MOSI AB14 FPGA gt AMP Serial data Master Output Slave Input Presents eight bit programmable gain settings as defined in Table 9 2 AMP_CS W6 FPGA gt AMP Active Low chip select The amplifier gain is set when the signal returns High SPI SCK AA20 FPGA gt AMP Clock AMP SHDN W15 FPGA gt AMP Active High shutdown reset AMP_DOUT T7 FPGA AMP Serial data Echoes previous amplifier gain settings Can be ignored in most applications Programmable Gain Spartan 3A 3AN Starter Kit Board User Guide Each analog channel has an associated programmable gain amplifier see Figure 9 2 Analog signals presented
104. iguration User Guide The Spartan 3 Generation Configuration User Guide includes step by step instructions some including screen shots on how to prepare the FPGA bitstream and download it to the FPGA or PROM e UG332 Spartan 3 Generation Configuration User Guide www xilinx com bvdocs userguides ug332 pdf For formatting and programming Platform Flash PROMs please refer to the Master Serial Mode chapter www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 5 Character LCD Screen Overview The Spartan 3A 3AN Starter Kit board prominently features a 2 line by 16 character liquid crystal display LCD The FPGA controls the LCD via the eight bit data interface shown in Figure 5 1 The Spartan 3A 3AN Starter Kit board also supports the four bit data interface to remain compatible with other Xilinx development boards Caution When using four bit mode the FPGA must drive the LCD_DB lt 3 0 gt signals High Character LCD FPGA Al Display LCD_DB lt 7 gt 9000 LCD_DB lt 6 gt g 8 9 LCD DB 5 oct 5g LCD_DB lt 4 gt o s LCD_DB lt 3 gt D LCD_DB lt 2 gt 5 LCD_DB lt 1 gt E iu LCD_DB lt 0 gt LCD_RS LCD_RW UG334_c5_01_052407 Figure 5 1 Character LCD Interface Once mastered the LCD is a practical way to display a variety of information using standard ASCII and custom characters However these displays are not fast Scrolling the display at
105. igure 15 2 The 5 0V supply provides a voltage source for any 5V logic on the attached board or alternately provides power to any voltage regulators on the attached board www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Hirose 100 Pin FX2 Edge Connector J17 A separate supply provides the same voltage as that applied to the FPGA s I O Banks 0 1 and 2 called VCCO_012 This supply is 3 3V by default All FPGA I Os that interface to the Hirose connector are in Bank 0 or Bank 1 For improved signal integrity a majority of pins on the B side of the FX2 connector are tied to GND Connector Pinout and FPGA Connections Table 15 1 shows the pinout for the Hirose 100 pin FX2 connector and the associated FPGA pin connections The FX2 connect has two rows of connectors both with 50 connections each shown in the table using light yellow shading The pin assignment for the connector is identical to that used on the Spartan 3E Starter Kit board although the Spartan 3E board pinout includes a few input only pins The Spartan 3A 3AN Starter Kit board pin assignment uses only full I O pins and are backwards compatible with the Spartan 3E Starter Kit board Table 15 1 Hirose 100 Pin FX2 Connector Pinout and FPGA Connections J17 Shared FX2 Connector B FPGA Signal Name F
106. il sw updates home jsp now included with the CORE Generator system e UG086 Xilinx Memory Interface Generator MIG User Guide included with MIG Related Resources Refer to the following links for additional information 114 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Related Resources Xilinx Embedded Development Kit EDK www xilinx com ise embedded_design_prod platform_studio htm MT47H32M16 32M x 16 DDR2 SDRAM Data Sheet download micron com pdf datasheets dram ddr2 512MbDDR2 pdf Multi Channel OPB DDR2 Controller Xilinx IP Core www xilinx com bvdocs ipcenter data_sheet mch_opb_ddr2 pdf Memory Interface Generator MIG Version 1 7 or later www xilinx com memory Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 115 UG334 v1 0 May 28 2007 Chapter 13 DDR2 SDRAM XILINX 116 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 14 10 100 Ethernet Physical Layer Interface The Spartan 3A 3AN Starter Kit board includes a Standard Microsystems LAN8700 10 100 Ethernet physical layer PHY interface and an RJ 45 connector as shown in Figure 14 1 With an Ethernet Media Access Controller MAC implemented in the FPGA the board can optionally connect to a standard Ethernet network All timing is controlled from an on board 25 MHz crystal oscillator RJ 45 Ethernet Connec
107. ints for Flash Address Signals Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 87 UG334 v1 0 May 28 2007 Chapter 11 Parallel NOR Flash PROM XILINX Data Cont Figure 11 3 provides the UCF constraints for the Flash data pins including the I O pin assignment and the I O standard used rol NET NF_D lt 15 gt NET NF_D lt 14 gt NET NF_D lt 13 gt NET NF_D lt 12 gt NET NF_D lt 11 gt NET NF_D lt 10 gt NET NF_D lt 9 gt NET NF_D lt 8 gt NET NF_D lt 7 gt NET NF_D lt 6 gt NET NF_D lt 5 gt NET NF_D lt 4 gt NET NF_D lt 3 gt NET NF_D lt 2 gt NET NF_D lt 1 gt NET SPI_MISO LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC LOC gt LOC AB11 U13 AA17 My LOC y11 AB20 IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR IOSTANDAR kl d BE Dd 1 87 uU U X ug LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 LVCMOS33 DRIVE DRIVE DRIVE DRIVE DRIVE RIVE dg Wu UU UD Ud RIVE LVCMOS33 DRIVE RIVE RIVE RIVE RIVE RIVE RIVE DRIVE use NF_A lt 0 gt on pin T17 when NF_BYTE High R21 T22 U22 U21 y22 w22 T20 Y9 AB9
108. ious vendors and suppliers as prices vary greatly StarTech PS 2 Keyboard Mouse Y splitter Cable KYC1MF American Power Conversion APC Mouse and Keyboard Splitter Cable 62305 1 Belkin Pro Series Notebook Y Cable F3G117 01 Tripp Lite P230 001 QVS CC321Y ComputerCableStore com 8 1718Y 00 5 CablesToGo 08017 9 UG330 c8 02 012507 Figure 8 6 Example PS 2 Y Splitter Cable When using the splitter cable use both sets of FPGA connections listed in Figure 8 1 page 65 and Table 8 1 page 65 The primary connections appear at one side of the Y splitter while the secondary connections appear at the other side of the Y splitter Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 69 UG334 v1 0 May 28 2007 Chapter 8 PS 2 Mouse Keyboard Port XILINX UCF Location Constraints Figure 8 7 provides the UCF constraints for the PS 2 port connecting including the I O pin assignment and the I O standard used Primary connection NET PS2_CLK1 LOC W12 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW NET PS2_DATA1 LOC V11 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Secondary connection requires Y splitter cable NET PS2_CLK2 LOC U11 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW NET PS2_DATA2 LOC Y12 IOSTANDARD LVTTL DRIVE 8 SLEW SLOW Figure 8 7 UCF Location Constraints for PS 2 Port Related Resources Refer to the following links for additional info
109. isk Applications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2007 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PCI Express is a registered trademark of PCI SIG All other trademarks are the property of their respective owners Revision History The following table shows the revision history for this document Date Version Revision 05 28 07 1 0 Initial Xilinx release Spartan 3A 3AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 Table of Contents Preface About This Guide Acknowledgments uc soa eara A Re bd d ASA 10 Guide Contents ccc cc cece cence Re 10 Additional Resources cece cece cece e 11 Chapter 1 Introduction and Overview Getting Statted A A 13 Operating the Default Demonstration Design 0005 15 VGA Displayer neeme e ee A an ee 15 Rotary Knob Push Button Menu System 60 cece een eens 15 Select MultiBoot Configuration Image 6 6 6 ene ee 16 Scroll or Rotate Graphic ee eee e he en 17 Scroll or Scale Graphic sr 2002 FIR eee Se be an He ERR Ved Ra does 17 Restart AutoPilot Speaker Volume Control 0 0 0 0 0c c cece eee eee 17 LCD Screen
110. ive signal conditioning circuits and high power drive circuits to be placed where they are most effective near sensors and actuators PMODs communicate with system boards using six wire cables that can carry up to four digital control signals including SPI and other serial protocols PMODs allow more effective design partitions by routing analog signals and power supplies only where they are needed and away from digital controller boards e Digilent Inc Peripheral Modules http www digilentinc com Products Catalog cfm Cat Peripheral www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Connectorless Debugging Port Landing Pads J34 UCF Location Constraints Figure 15 11 provides the User Constraint File UCF constraints for the accessory headers including the I O pin assignment and the I O standard used 6 pin header J18 These four connections are shared with the FX2 connector NET J18_10 lt 1 gt LOC AA21 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J18_10 lt 2 gt LOC AB21 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J18_IO lt 3 gt LOC AA19 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 NET J18_10 lt 4 gt LOC AB19 IOSTANDARD LVTTL SLEW SLOW DRIVE 8 6 pin header J19 These four connections are shared with the FX2 connector
111. l En el Ed E EG ES EJ 2 Fi m E Back Space gt En el Ed E ES Fi m 66 E074 TAB ETE X 0D E E EA ES EN EN a E 54 51 E EN w El O A OY tu nc J 1c B EJ ES EN EN E ES 4c 52 E072 Z X ES E 1 A Shift 12 2 ai ES E ER ES a pe 4A 59 Alt Space Ctrl 11 29 Es A E014 UG230_c8_03_021806 N Figure 8 3 PS 2 Keyboard Scan Codes The host can also send commands and data to the keyboard Table 8 3 provides a short list of some often used commands Table 8 3 Common PS 2 Keyboard Commands Command Description ED Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs are shown below Write a 1 to the specific bit to illuminate the associated keyboard LED 7 6 5 4 3 2 1 0 Ignored Caps Lock Num Lock Scroll Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code FE Reset Resets the keyboard Spartan 3A 3AN The keyboard sends commands or data to the host only
112. l serial Digital to Analog Converter DAC The DAC device is a Linear Technology LTC2624 quad DAC with 12 bit unsigned resolution The four outputs from the DAC appear on the J21 header which uses the Digilent six pin Peripheral Module format The DAC and the header are located immediately below the Ethernet RJ 45 connector as shown in Figure 10 1 _ Linear Tech LTC2624 Quad DAC SPI_MOSI AB14 SPI_SCK AA20 DAC_CS W7 DAC_CLR AB13 DAC_OUT V7 6 pin DAC Header J21 UG334_c10_01 Fer Figure 10 1 DAC and Associated Stake Pin Header J21 SPI Communication As shown in Figure 10 2 the FPGA uses a Serial Peripheral Interface SPI to communicate digital values to each of the four DAC channels The SPI bus is a full duplex synchronous character oriented channel employing a simple four wire interface A bus master the FPGA in this example drives the bus clock signal SPI_SCK and transmits serial data SPI_MOSI to the selected bus slave the DAC in this example At the same time the bus slave provides serial data SPI_MISO back to the bus master Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 79 UG334 v1 0 May 28 2007 80 Chapter 10 Digital to Analog Converter DAC XILINX DAC CLR i e gt E S p LTC 2624 DAC rere Header J5 REF A pvoural FA i i iA REF B H i QUT i B 3 3V by default LE i Programmab
113. lash Configuration PROM s The Spartan 3A 3AN Starter Kit board includes a Xilinx Platform Flash configuration interface A single 4 Mbit XCFO4S Platform Flash PROM appears in the JTAG chain with the FPGA Caution The J46 jumper shown in Table 4 2 page 40 enables or disables the Plattorm Flash PROM on the board Be aware of potential data contention issues with the SPI serial Flash and the DO line of the parallel NOR Flash depending on the current FPGA Configuration Mode Jumpers shown in Table 4 1 Caution If the J46 jumper shown in Table 4 2 page 40 is set for Always Enabled then the FPGA s INIT B pin controls the Platform Flash PROM s OE RESET input The INIT B pin must be High to read any data other than from the Platform Flash PROM When using the Platform Flash PROM to configure the FPGA the configuration mode jumpers must be set for Master Serial mode as shown in Table 4 2 If using any other configuration mode the Platform Flash PROM must be disabled Table 4 2 Platform Flash Enable Jumper J46 Platform Flash Platform Flash Allowed FPGA Precautions Mode Enable J46 Configuration Mode Contention None Platform Flash disabled The FPGA application has full Disabled Any access to SPI serial Flash and no jumper see Table 4 1 parallel NOR Flash PROMs after configuration None Platform Flash enabled during configuration and disabled after configuration The FPGA application has full ac
114. le reference i H e supplied by adjustable i LP3906 regulator IC18 i i i i FPGA i i i IGND SPI MOSI sn j G DAC CS ileso i SPLSCK SCK SPI Control Interface i i VCC jes UG334_c10_02_052407 Figure 10 2 Digital to Analog Connection Schematics Interface Signals Table 10 1 lists the interface signals between the FPGA and the DAC The SPI_MOSI DAC_OUT and SPI_SCK signals are shared with other devices on the SPI bus The DAC_CS signal is the active Low slave select input to the DAC The DAC_CLR signal is the active Low asynchronous reset input to the DAC Table 10 1 DAC Interface Signals Signal FPGA Pin Direction Description SPI_MOSI AB14 FPGA gt DAC Serial data Master Output Slave Input DAC_CS W7 FPGA DAC Active Low chip select Digital to analog conversion starts when this signal returns High SPI_SCK AA20 FPGA gt DAC Clock DAC_CLR AB13 FPGA gt DAC Asynchronous active Low reset input DAC_OUT V7 FPGA DAC Serial data from the DAC The serial data output from the DAC is primarily used to cascade multiple DACs This signal can be ignored in most applications although it does demonstrate full duplex communication over the SPI bus SPI Communication Details Figure 10 3 shows a detailed example of the SPI bus timing Each bit is transmitted or received relative to the SPI_SCK clock signal The bus is fully static and suppo
115. lowed by one or more data values Before writing any data issue a Set DD RAM Address command to specify the initial seven bit address in the DD RAM See Figure 5 3 for DD RAM locations Write data to the display using a Write Data to CG RAM or DD RAM command The eight bit data value represents the look up address into the CG ROM or CG RAM shown in Figure 5 4 The stored bitmap in the CG ROM or CG RAM drives the 5 x 8 dot matrix to represent the associated character If the address counter is configured to auto increment as described earlier the application can sequentially write multiple character codes and each character is automatically stored and displayed in the next available location Continuing to write characters however eventually falls off the end of the first display line The additional characters do not automatically appear on the second line because the DD RAM map is not consecutive from the first line to the second 54 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Related Resources Disabling the Unused LCD If the FPGA application does not use the character LCD screen drive the LCD_E pin Low to disable it Also drive the LCD_RW pin Low to prevent the LCD screen from presenting data Related Resources Refer to the following links for additional information PowerTip PC1602 D Character LCD Basic Electrical and Mechanical Data www powertipusa com pdf pc16
116. mmand all subsequent read or write operations to the display are to or from DD RAM The addresses for displayed characters appear in Figure 5 3 Execution Time 40 us Read Busy Flag and Address Reads the Busy flag BF to determine if an internal operation is in progress and reads the current address counter contents BF 1 indicates that an internal operation is in progress The next instruction is not accepted until BF is cleared or until the current instruction is allowed the maximum time to execute This command also returns the present value of the address counter The address counter is used for both CG RAM and DD RAM addresses The specific context depends on the most recent Set CG RAM Address or Set DD RAM Address command issued Execution Time 1 us Write Data to CG RAM or DD RAM Writes data into DD RAM if the command follows a previous Set DD RAM Address command or writes data into CG RAM if the command follows a previous Set CG RAM Address command Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 51 UG334 v1 0 May 28 2007 Chapter 5 Character LCD Screen XILINX Operation After the write operation the address is automatically incremented or decremented by 1 according to the Entry Mode Set command The entry mode also determines display shift Execution Time 40 us Read Data from CG RAM or DD RAM Reads data from DD RAM if the command follows a previous Set DD RAM Address command or reads d
117. mple Custom Checkerboard Character with Character Code 0x03 Command Set Table 5 2 summarizes the available LCD controller commands and bit definitions Because the display is set up for four bit operation each eight bit command is sent as two four bit nibbles The upper nibble is transferred first followed by the lower nibble Table 5 2 LCD Character Display Command Set 4 bit mode o z Upper Nibble Lower Nibble Function m o o0 0 x eo a o 3188 88 2 8 B BB Clear Display 0 0 0 0 0 0 0 0 0 1 Return Cursor Home 0 0 0 0 0 0 0 0 1 Entry Mode Set 0 0 0 0 0 0 0 1 I D S Display On Off 0 0 0 0 0 0 1 D C B Cursor and Display Shift 0 0 0 0 0 1 S C R L 48 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Table 5 2 LCD Character Display Command Set 4 bit mode Continued LCD Controller o z Upper Nibble Lower Nibble Function A E Rio o eo o o 388 8 8 8 8 A Function Set 0 0 0 0 1 0 1 0 Set CG RAM Address 0 0 0 1 A5 A4 A3 A2 A1 AO Set DD RAM Address 0 0 1 A6 A5 A4 A3 A2 A1 AO Read Busy Flag and Address 0 1 BF A6 A5 AA A3 A2 Al AO Write Data to CG RAM or DD RAM 1 0 D7 D6 D5 DA D3 D2 D1 DO Read Data from CG RAM or DD RAM 1 1 D7 De D5 DA D3 D2 D1 DO Disabled If the LCD_E enable signal is Low all other inputs to the
118. n blue in Figure 15 6 connects to a differential global clock input pair GCLK7 and GCLK8 Using these global clock 128 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Differential I O Connectors inputs the differential input is converted to a single ended clock signal within the FPGA This clock input then feeds the upper right DCM labeled as DCM_X2Y3 If using for differential inputs set the DIFF_TERM TRUE constraint There are no external termination resistors provided on the board Receive Header J2 34 33 All traces routed with 1000 matched impedance All receive pairs routed with matched trace lengths within 0 25 inches Receive clock a connects to global clock inputs GCLK7 and GCLK8 that feed the top right DCM labeled DCM X2Y3 d e AS qo E oe NN Pr tee tee LASS SPP OP PP CRN SDN CRASSA RRR i inn AAA AAA NOSE AMIA SITE AT ATA RENDER All traces routed with 1000 matched impedance All transmit pairs routed with matched trace lengths within 0 25 inches ESFERA ARE AA HECREHRMERRBRENEH Transmit Header J15 UGa90 ci2 18 012407 Figure 15 6 Differential I O Layout Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 129 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors XILINX 34 Conductor Cable Assemblies 2x17 The J2 and J15 headers were designed specificall
119. n serial cable TALK DATA RSCSTRRDTDCD TALK mmm m DCE DTE RS232_DCE_RXD ANN RS232 DCE TXD RS232 DTE TXD E16 F15 F16 E15 UGS334 c7 01 052407 Figure 7 1 RS 232 Serial Ports Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 63 UG334 v1 0 May 28 2007 Chapter 7 RS 232 Serial Ports XILINX Figure 7 1 shows the connection between the FPGA and the two DB9 connectors The FPGA supplies serial output data using LVTTL or LVCMOS levels to the Maxim device which in turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim device converts the RS 232 serial input data to LVTTL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against inadvertent logic conflicts such as accidentally connecting the board using a null modem cable In this example both the FPGA and the external serial device are driving data on the transmit line Hardware flow control is not supported on the connector The port s DCD DTR and DSR signals connect together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together UCF Location Constraints 64 Figure 7 2 and Figure 7 3 provide the UCF constraints for the DTE and DCE RS 232 ports respectively including the I O pin assignment and the I O standard used NET RS232_DTE_RXD LOC NET RS232_DTE_TXD LOC LV
120. ne 93 Shared SPI Flash and Platform Flash Data Line 000000 c eee eee eee 94 Jumper Settings to Configure FPGA from Selected SPI Flash PROM 94 UCF Location Constraints 22222222ssseeessseeeessnnennnnnnnnn 95 Creating and Programming Configuration Images for SPI Serial Flash 95 SPI Flash PROM Programming Options ssssssssese ee 95 Direct Programming Method 22eeeeeeeeeeeeneeeeeennnnee nenn 96 Using Embedded USB JTAG Programmer 6 6 ccc ees 96 Using a Separate JTAG Parallel Programming Cable Optional 97 Direct SPI Flash Programming Using iMPACT 0 cee eee ee 98 Indirect Programming Method 0006s 101 Jumper Settings qase an 101 Indirect SPI Flash Programming Using iMPACT 6 0 ee eee 102 Related Resources suite shaw we DRA Ae ke ee 106 Chapter 13 DDR2 SDRAM DDR2 SDRAM Connections 00 ccc ccc tenet teens 110 UCF Location Constraints 0 000 e enn n eens 112 Address ii A ERR WR Rea Goatees a E CS RE RS 112 Data san a are eed dick I A Dessen 113 Control iii a A ern ke 113 Reserve FPGA V pap Pins ost kr EE RD e PEE a aan ana a 114 Special Layout Recommendations 2 22222eeeeeneneenennnenn 114 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Related Resources Chapter 14 10 100 Ethernet Physical Layer Interface
121. ng for a 60 Hz 640x480 VGA Display 58 VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive the VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites see Related Resources page 61 Standard VGA support is part of the factory demonstration designs but several extended VGA modes including SVGA are also achievable with faster timing controllers CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCDs use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing light permittivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCDs have evolved to use the same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCDs www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Current through the horizontal deflection coil time Signal Timing for a 60 Hz 640x480 VGA Display Within a CRT display current waveforms pass through the coils to produce magne
122. nt kits Pasture Spartan 3AN Spartan 3A DDR2 SDRAM Spartan 3A Starter Spartan 3A Starter Kit Starter Kit Interface Development Kit Kit Revision D Revision C FOE RWESBARSANSKCUNEG PRPS e PRRs HW SPAR3A SK UNI G Number UNI G Device XC3S700AN XC3S700A Poara Revision D Revision C Revision DDR Requires board Me Supported with 133 MHz crystal oscillator in auxiliary socket modification for y improved performance User UG334 this document UG330 Guide Web Page www xilinx com s3anstarter www xilinx com s3addr2 www xilinx com s3astarter Almost all functionality is identical between the Revision C and Revision D boards although the silkscreen changes make the two boards look different The pictures used in this document are from the Revision D board If you are using the original Revision C version of the board refer to UG330 for pictures and documentation The following figure highlights where to find the board revision code on a Revision C board Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 9 UG334 v1 0 May 28 2007 Preface About This Guide XILINX Board Revision Code REVC UG334_01_052707 Acknowledgments Xilinx wishes to thank the following companies for their support of the Spartan 3A 3AN Starter Kit board Guide Contents 10 STMicroelectronics for the 32 Mbit parallel NOR Flash and 16 Mbit SPI serial Flash memories Atmel for
123. oduces TTL level synchronizing pulses that set the frequency at which current Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 59 UG334 v1 0 May 28 2007 Chapter 6 VGA Display Port XILINX flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3A 3AN Starter Kit board uses 12 bits per pixel producing one of the 4 096 possible colors The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel As shown in Figure 6 2 the VGA controller generates the horizontal sync HS and vertical sync VS timing signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing Th
124. oltage margining One high current 1 8V rail supports the DDR2 SDRAM component itself and supplies the FPGA s I O Bank 3 which connects to the DDR2 SDRAM One high current 0 9V supplies the DDR2 SDRAM termination network Alow current 1 8V supply is voltage divided with resistors to provide a high accuracy 0 9V voltage reference for the DDR2 SDRAM component and to supply the VREF inputs on FPGA I O Bank 3 See Chapter 13 DDR2 SDRAM for additional information www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Measuring Power Across Voltage Supply Jumpers Measuring Power Across Voltage Supply Jumpers All regulator output supplies have an associated series jumper as indicated in Table 17 1 and shown in Figure 17 1 This allows for simple and easy current monitoring using just a multimeter For example to measure the Suspend mode current on the FPGA s Vecaux or Vecint supplies follow these steps Caution The Suspend feature must first be enabled in the actual FPGA application All the example designs initially shipped with the board have the Suspend feature enabled e Disconnect power to the board e Remove the series jumper associated with the supply to be measured shown in Table 17 2 Locate jumper indicated in Figure 17 1 Table 17 2 FPGA Supply Rails and Associated Voltage Supply Jumper Associated Voltage FPGA Supply Rail Supply Jumpe
125. on the VINA or VINB inputs on the J7 header are amplified relative to 1 65V The 1 65V reference is generated using a voltage divider of the 3 3V voltage supply The gain of each amplifier is programmable from 1 to 100 as shown in Table 9 2 Table 9 2 Programmable Gain Settings for Pre Amplifier A3 A2 A1 AO Input Voltage Range B3 B2 B1 BO Minimum Maximum 0 0 0 0 0 1 0 0 0 1 0 4 2 9 2 0 0 1 0 1 025 2 275 www xilinx com 73 UG334 v1 0 May 28 2007 Chapter 9 Analog Capture Circuit XILINX Table 9 2 Programmable Gain Settings for Pre Amplifier Continued A3 A2 A1 AO Input Voltage Range m B3 B2 B1 BO Minimum Maximum 5 0 0 1 1 14 1 9 10 0 1 0 0 1 525 1 775 20 0 1 0 1 1 5875 1 7125 50 0 1 1 0 1 625 1 675 100 0 1 1 1 1 6375 1 6625 SPI Control Interface Figure 9 3 highlights the SPI based communications interface with the amplifier The gain for each amplifier is sent as an eight bit command word consisting of two four bit fields The most significant bit B3 is sent first AMP_DOUT o Slave LTC2624 1 Ao A A As 80 Bi Bs B Gain SPI MOSI FPGA Master SPI SCK A Gain UG334 c9 03 052407 Figure 9 3 SPI Serial Interface to Amplifier The AMP DOUT output from the amplifier echoes the previous gain settings These values can be ignored for most applications
126. opment Board DO SP3E1600E DK UNI G www xilinx com sp3e1600e For PCI Express applications consider the Spartan 3 PCI Express Starter Kit e Spartan 3 PCI Express Starter Kit HW S3PCIE DK www xilinx com s3pcie For simple Spartan 3 FPGA applications consider the fairly basic Spartan 3 Starter Kit board e Spartan 3 Starter Kit HW SPAR3 SK UNI G www xilinx com s3starter Also consider the capable boards offered by Xilinx partners e Spartan 3 and Spartan 3E Board Interactive Search www xilinx com products devboards index htm Spartan 3A and Spartan 3AN FPGAs The Spartan 3AN FPGA platform offers nonvolatile pin compatible versions of the Spartan 3A FPGA platform The Spartan 3AN FPGAs support the same external programming sources as Spartan 3A FPGAs but add an additional internal SPI Flash programming mode The internal SPI Flash can also be used for user data The Spartan 3A 3AN Starter Kit Board supports both external and Spartan 3AN internal configuration options Spartan 3AN FPGAs require Vecayx to be 3 3V while Spartan 3A FPGAs allow VccAUx to be either 2 5V or 3 3V The Spartan 3A 3AN Starter Kit Board uses a default Vecaux of 3 3V Spartan 3A and Spartan 3AN FPGAs have different documentation and availability Verify the latest version of the appropriate documentation on xilinx com Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 23 UG334 v1 0 May 28 2007 Chapter 1 Introduction and
127. outputs 100 pin Hirose FX2 expansion connector with up to 43 FPGA user I Os Compatible with Digilent FX2 add on cards High speed differential I O connectors Receiver Six data channels or five data channels plus clock Transmitter Six data channels or five data channels plus clock Supports multiple differential I O standards including LVDS RSDS mini LVDS Also supports up to 24 single ended I O Uses widely available 34 conductor cables Two six pin expansion connectors for Digilent Peripheral Modules Four output SPI based Digital to Analog Converter DAC Two input SPI based Analog to Digital Converter ADC with programmable gain pre amplifier Stereo audio jack using digital I O pins ChipScope SoftTouch debugging port Rotary encoder with push button shaft Eight discrete LEDs Four slide switches Four push button switches www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Design Trade Offs Design Trade Offs A few system level design trade offs were required in order to provide the Spartan 3A 3AN Starter Kit board with the most functionality Configuration Methods Galore A typical FPGA application uses a single nonvolatile memory to store configuration images A typical Spartan 3AN nonvolatile FPGA application would not require any external memory To demonstrate new Spartan 3A and Spartan 3AN FPGA capabilities the starter kit board has four di
128. own resistor within the UCR There is no active debouncing circuitry on the push button FPGA I O Pin 3 3V Push Button TA BTN_ Signal UG230_c2_03_021206 Figure 2 6 Push Button Switches Require an Internal Pull Down Resistor in the FPGA Input Pin Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 27 UG334 v1 0 May 28 2007 Chapter 2 Switches Buttons and Rotary Knob XILINX PROG_B Push Button Switch The PROG_B push button switch shown in Figure 2 14 page 31 is part of the FPGA s configuration circuitry See PROG Push Button Switch page 40 UCF Location Constraints Figure 2 7 provides the UCF constraints for the four push button switches including the I O pin assignment and the I O standard used and defines a pull down resistor on each input NET BTN_EAST LOC T16 IOSTANDARD LVTTL PULLDOWN NET BTN_NORTH LOC T14 IOSTANDARD LVTTL PULLDOWN NET BTN_SOUTH LOC T15 IOSTANDARD LVTTL PULLDOWN NET BTN_WEST LOC U15 IOSTANDARD LVTTL PULLDOWN Figure 2 7 UCF Constraints for Push Button Switches Rotary Push Button Switch Locations and Labels The rotary push button switch is located in the center of the four individual push button switches as shown in Figure 2 5 page 27 The switch produces three outputs The two shaft encoder outputs are ROT_A and ROT_B The center push button switch is ROT_CENTER Operation The
129. per J46 Platform Flash PROM Set to Disabled or Enable FPGA INIT B during Configuration as ae shown in Table 4 2 page 40 FPGA_INIT_B has no effect If set to Always Enabled then FPGA_INIT_B must be 1 SPI_SS_B SPI Flash PROM selected by 1 Jumper J1 as shown in Table 12 2 page 93 ALT_SS_B SPI Flash PROM selected by 1 Jumper J1 as shown in Table 12 2 page 93 UCF Location Constraints Address Figure 11 2 provides the UCF constraints for the Flash address pins including the I O pin assignment and the I O standard used NET NF_A lt 24 gt LOC A11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 23 gt LOC N11 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 22 gt LOC V12 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 21 gt LOC C21 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 20 gt LOC C22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 19 gt LOC F21 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 18 gt LOC F22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 17 gt LOC H20 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 16 gt LOC H21 IOSTANDARD LVCMOS33 DRIVE 4 SLEW SLOW NET NF_A lt 15 gt LOC G22 IOSTANDARD LVCMOS33 DRIVE 4 SLEW
130. phic In this mode rotate the knob to scale the size of the graphic image zooming in and out Use the four push button switches to scroll the resulting graphic image up down left or right Press the rotary knob to change to the Restart AutoPilot Speaker Volume Control mode Restart AutoPilot Speaker Volume Control Spartan 3A 3AN Starter Kit Board User Guide In this mode rotate the knob to control the speaker output volume Press any of the four push button switches to restart the AutoPilot function Press the rotary knob to change to the Select MultiBoot Configuration Image mode www xilinx com 17 UG334 v1 0 May 28 2007 Chapter 1 Introduction and Overview XILINX 18 LCD Screen Control Option While the demonstration design operates best with an attached VGA display the on board LCD screen tracks similar functionality as shown in Figure 1 5 If no VGA display is attached then the Scroll or Rotate Graphic Scroll or Scale Graphic and Restart AutoPilot Speaker Volume Control modes offer little to no functionality the exception being the volume control assuming that a speaker is attached to the audio jack Start Demonstration Design Power up board Press PROG_B button Welcome to XLNX S3A Starter Kit Wait 1 second Select MultiBoot Select FPGA MultiBoot Configuration F Btns Load Cfg 1 8 al 2o nyo amp Spin Select Cfg 3 y Oo 2 MultiBoot
131. provides a variety of expansion connectors for easy interface flexibility to other off board components The board includes the I O expansion headers shown in Figure 15 1 e A Hirose 100 pin edge connector with 43 associated FPGA user I O pins e Two stake pin headers each that supports up to five differential data channels plus a differential clock or 12 single ended I O signals e Two six pin Peripheral Module connections plus mounting holes for a third module e Landing pads for an Agilent or Tektronix connectorless probe amp iw IA y g Differential Receive Header J2 cw 6 differential pairs high performance Optionally 12 single ended I O Hirose 100 pin FX2 Connector J17 43 I O connections high performance Connectorless Probe Landing Pads For logic analyzer or oscilloscope l lulil lil XILINX SPARTAN 3 f C GENERATION Nesey Differential Transmit Header J15 6 differential pairs high performance Optionally 12 single ended I O 6 pin Accessory Header J19 ounting holes only 6 pin Accessory Header J20 6 pin Accessory Header J18 UG334_c15_01_052407 Figure 15 1 Expansion Headers Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 121 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors XILINX Hirose 100 Pin FX2 Edge Connector J17 122 A 100 pin edge connector is located along the right edge of the board This connector is a
132. ptional_prod cspro htm e Agilent B4655A FPGA Dynamic Probe for Logic Analyzer www home agilent com USeng nav 536902581 0 pc html e Agilent 5404A 6A Pro Series Soft Touch Connector www home agilent com cgi bin pub agilent Product cp_Product jsp NAV_ID 536898227 0 00 e Tektronix P69xx Probe Modules with D Max Technology www tek com products accessories logic analyzers p6800 p6900 html Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 133 UG334 v1 0 May 28 2007 Chapter 15 Expansion Connectors 134 XILINX Table 15 6 provides the connector pinout Only 18 FPGA pins attach to the connector the remaining connector pads are unconnected All 18 FPGA pins are shared with the FX2 connector J17 See Table 15 1 page 123 for more information on how these pins are shared Table 15 6 Connectorless Debugging Port Landing Pads J34 www xilinx com Connectorless Signal Name FPGA Pin Landing Pads FPGA Pin Signal Name FX2_IO1 A13 Al B1 GND GND FX2_IO2 B13 A2 B2 A14 FX2 IO3 GND GND A3 B3 B15 FX2_IO4 FX2_IO5 A15 A4 B4 GND GND FX2_IO6 A16 A5 B5 A17 FX2 IO7 GND GND A6 B6 B17 FX2_IO8 FX2 IO9 A18 A7 B7 GND GND FX2 IO10 C18 A8 B8 A19 FX2 IO11 GND GND A9 B9 B19 FX2 IO12 FX2_IO13 A20 A10 B10 GND GND FX2 IO14 B20 A11 B11 c19 FX2 IO15 GND GND A12 B12 D19 FX2 IO16
133. r Default Voltage VcciNT J9 1 2V VCCAUX Ju 3 3V e Connect a digital multimeter across the jumper as highlighted in Figure 17 2 If the resulting current is negative simply reverse the connections to the jumpers M d Current Set Current R en easure urren e urren ange umper J9 mA 200 mA DC VCCAUX 3 3v Umer J9 Jumper J11 E M Y UG330 c17 02 032207 Figure 17 2 Measuring Current Power Using a Multimeter e Set the meter to measure DC Amperes Initially set the meter to the Ampere range If appropriate switch to a lower range for example 200 mA after initially measuring current in the Ampere range Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 139 UG334 v1 0 May 28 2007 Chapter 17 Voltage Supplies XILINX Caution If the meter offers various current ranges always start with the largest range first Passing too large a current through a meter may damage it Reapply power to the board Record the current measurements across the jumper If the FPGA design supports the power saving Suspend mode measure the current with the SUSPEND switch see SUSPEND Switch page 26 set in both the RUN and SUSPEND positions The default FPGA application shipped with the Starter Kit board does use the Suspend mode For additional information on the Suspend mode see the Power Management Solutions chapter in UG331 Spartan 3 Generation FPGA User Guide Con
134. r Kit board If the USB cable is attached to the board disconnect it Simultaneously connecting both the USB cable and the parallel cable to the PC confuses the iMPACT software Connect one end of the JTAG parallel programming cable to the parallel printer port of the PC Connect the JTAG end of the cable to Header J23 as shown in Figure 12 5a The J23 header connects directly to the SPI Flash pins it is not connected to the JTAG chain The JTAG3 cable directly mounts to Header J23 The labels on the JTAG3 cable face toward the J11 jumpers If using flying leads they must be connected as shown in Figure 12 5b and Table 12 6 Note the color coding for the leads The gray INIT lead is left unconnected Table 12 6 Cable Connections to J23 Header Cable and Labels Connections J23 Header Label SEL SDI SDO SCK GND VCC JTAG3 Cable Label TMS TDI TDO TCK GND VCC Flying Leads Label TMS TDO GND VREF PROG DIN DONE GND VREF Direct SPI Flash Programming Using IMPACT The following steps describe how to program the SPI PROM using the iMPACT software and a Xilinx programming cable 1 Click Direct SPI Configuration from within iMPACT as shown in Figure 12 6 iMPACT C Data my designs led crazy led crazy 700a ipf Direct SP S File Edit View Operations Options Output Debug Window Help PB x BBX Sm iim H Ba Boundary Scan IMPACT Modes UG332_c4_03_101006 Figure 12 6 iMPACT
135. re 3 1 e The board includes an on board 50 MHz clock oscillator e Clocks can be supplied off board via an SMA style connector Alternatively the FPGA can generate clock signals or other high speed signals on the SMA style connector e A 133 MHz clock oscillator is installed in the CLK_AUX socket Optionally substitute a separate eight pin DIP style clock oscillator in the provided socket CLK 50MHZ E12 Platform Flash E VENE MEM CLK_AUX SPARTAN 3 v12 I A E a ur RATION ur aD lt CLK_SMA U12 UG334 c3 01 052407 Figure 3 1 Clock Sources on Starter Kit Board Spartan 3A 8AN Starter Kit Board User Guide www xilinx com UG334 v1 0 May 28 2007 33 Chapter 3 Clock Sources XILINX Clock Connections Each of the clock inputs connect directly to a global buffer input As shown in Table 3 1 each of the clock inputs also optimally connects to an associated DCM Only the CLK_AUX or the CLK_SMA input can use the associated DCM at any time However both inputs are available as clock inputs Table 3 1 Clock Inputs and Associated Global Buffers and DCMs Clock Input FPGA Pin I O Bank Global Buffer Associated DCM LOC CLK_50MHZ El2 0 GCLK5 Top Right DCM_X2Y3 CLK_AUX v12 2 GCLK2 Bottom Right DCM_X2Y0 CLK_SMA U12 2 GCLK3 50 MHz On Board Oscillator The board includes a 50 MHz oscillator with a 40 to 60 output duty cycle The oscillator is accurate to 2500 Hz or 50 ppm
136. re are 80 total character locations in DD RAM with 40 characters available per line Locations 0x10 through 0x27 and 0x50 through 0x67 can be used to store other non display data Alternatively these locations can also store characters that can only be displayed using controller s display shifting functions Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 45 UG334 v1 0 May 28 2007 46 Chapter 5 Character LCD Screen XILINX The Set DD RAM Address command initializes the address counter before reading or writing to DD RAM Write DD RAM data using the Write Data to CG RAM or DD RAM command and read DD RAM using the Read Data from CG RAM or DD RAM command The DD RAM address counter either remains constant after read or write operations or auto increments or auto decrements by one location as defined by the I D set by the Entry Mode Set command CG ROM The Character Generator ROM CG ROM contains the font bitmap for each of the predefined characters that the LCD screen can display shown in Figure 5 4 The character code stored in DD RAM for each character location subsequently references a position with the CG ROM For example a hexadecimal character code of 0x53 stored in a DD RAM location displays the character S The upper nibble of 0x53 equates to DB 7 4 0101 binary and the lower nibble equates to DB 3 0 0011 binary As shown in Figure 5 4 the character S appears on the screen English Roman ch
137. rify gt Erase Blank Check Readback Program Succeeded UG332_c4_06_101006 Figure 12 9 Directly Program Supported SPI Flash PROM 9 Click Program Note Step 14 occurs later 10 Click the Programming Properties option under Category as shown in Figure 12 10 Programming Properties Ea General CPLD nd PROM Properties AZ WV Erase Before Programming Read Protect UG332_c4_07_101006 Figure 12 10 SPI PROM Programming Options 11 Check Verify Unchecking Verify reduces programming time but the IMPACT software can only guarantee correct programming for a verified PROM 100 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Creating and Programming Configuration Images for SPI Serial Flash 12 Check Erase Before Programming Unchecking the Erase option reduces programming time However Xilinx recommends erasing the PROM when downloading a new FPGA bitstream 13 Click OK 14 The iMPACT software indicates successful programming as shown in Figure 12 9 After programming completes 15 Turn off power to the board 16 Remove Jumper J16 to release the FPGA s PROG_B pin 17 Remove the four jumpers connecting jumper blocks J23 and J25 18 Reapply power Indirect Programming Method Indirect programming support is available starting with Xilinx ISE 9 11 Service Pack 2 and later releases In Indirect mode the iMPACT software programs th
138. rmation e PS 2 Mouse Keyboard Protocol www computer engineering org ps2protocol e PS 2 Keyboard Interface www computer engineering org ps2keyboard e PS 2 Mouse Interface www computer engineering org ps2mouse 70 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Chapter 9 Analog Capture Circuit The Spartan 3A 3AN Starter Kit board includes a two channel analog capture circuit consisting of a programmable scaling pre amplifier and an analog to digital converter ADO as shown in Figure 9 1 Linear Tech LTC1407A 1 Dual A D ru SPI_SCK AA20 alsieielsisi AD_CONV Y6 AD_DOUT D16 Linear Tech LTC6912 1 Dual Amp SPI_MOSI AB14 AMP_CS W6 SPI_SCK AA20 AMP SHDN W15 AMP DOUT T7 6 pin ADC Header J22 UGS34 c9 01 052407 Figure 9 1 Analog Capture Circuit and Associated Stake Pin Header J22 The analog capture circuit consists of a Linear Technology LTC6912 1 programmable pre amplifier that scales the incoming analog signal on the J22 header The output of the pre amplifier connects to a Linear Technology LTC1407A 1 ADC Both the pre amplifier and the ADC are serially programmed or controlled by the FPGA Spartan 3A 8AN Starter Kit Board User Guide www xilinx com 71 UG334 v1 0 May 28 2007 Chapter 9 Analog Capture Circuit XILINX i AD i Channel 0 REF 1 65V i SPI M
139. rts clock rates up to the maximum of 50 MHz However check all timing parameters using the LTC2624 data sheet if operating at or close to the maximum speed www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX SPI Communication DAC CS Ve SPI MOS XXXXX 31 AAA SO AA 22 A SPI_SCK __f N fF Ff A DACOUT _ XXPrevious 31 XXNX Previous 30 NANA Previous 29 UG330_c9_03071906 Figure 10 3 SPI Communication Waveforms After driving the DAC_CS slave select signal Low the FPGA transmits data on the SPI_MOSI signal MSB first The LTC2624 captures input data SPI_MOSI on the rising edge of SPI_SCK the data must be valid for at least 4 ns relative to the rising clock edge The LTC2624 DAC transmits its data on the DAC_OUT signal on the falling edge of SPI_SCK The FPGA captures this data on the next rising SPI_SCK edge The FPGA must read the first DAC_OUT value on the first rising SPI_SCK edge after DAC_CS goes Low Otherwise bit 31 is missed After transmitting all 32 data bits the FPGA completes the SPI bus transaction by returning the DAC_CS slave select signal High The High going edge starts the actual digital to analog conversion process within the DAC Communication Protocol Figure 10 4 shows the communications protocol required to interface with the LTC2624 DAC The DAC supports both 24 bit and 32 bit protocol The 32 bit protocol is shown Inside the DAC the SPI interface is formed
140. s for SPI Serial Flash 11 Select Bypass when prompted for the Platform Flash PROM programming file as shown in Figure 12 16 E Assign New Configuration File a O msgs Ongo templates O xst File type All Design Files mes exo isc bsd y None Cancel All C Enable Programming of SPI Flash Device Attached to this FPGA C Enable Programming of BPI Flash Device Attached to this FPGA UG332_c4_28 032907 Figure 12 16 Bypass the Platform Flash PROM 12 As shown in Figure 12 17 the iMPACT software then displays the JTAG chain for the XC3S700A Spartan 3A FPGA followed by the XCF04S Platform Flash PROM A similar display will be seen for the XC3S700AN Spartan 3AN FPGA Click to highlight the FLASH memory attached to the XC35700A FPGA This action enables the command options shown in Step 13 e iMPACT C Datamy designs switches leds default ipf Boundary Scan File Edit View Operations Output Debug Window Help lg B ib IEEE aalBoundary Scan 22 SlaveSerial t maseleciMAP T5 Desktop Configuration Ta Direct SPI Configurati r E SystemACE xc3s700a xcf 4s top level bit bypass PROM File Formatter UG332_c4_25_032907 Figure 12 17 iMPACT Presents JTAG Chain Shows Attached Flash PROM Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 105 UG334 v1 0 May 28 2007 13 Chapter 12 SPI Serial Flash XILINX
141. s or longer the equivalent of 12 or more clock cycles at 50 MHz In many applications the LCD_RW signal can be tied Low permanently because the FPGA generally has no reason to read information from the display Transferring Eight Bit Data over the Four Bit Interface After initializing the display and establishing communication in four bit mode all commands and data transfers to the character display are via eight bits transferred using two sequential four bit operations Each eight bit transfer must be decomposed into two four bit transfers spaced apart by at least 1 us as shown in Figure 5 6 The upper nibble is transferred first followed by the lower nibble An eight bit write operation must be spaced least 40 us before the next communication This delay must be increased to 1 64 ms following a Clear Display command Initializing the Display After power on the display must be initialized to establish the required communication protocol The initialization sequence is simple and ideally suited to the highly efficient eight bit PicoBlaze embedded controller After initialization the PicoBlaze controller is available for more complex control or computation beyond simply driving the display Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 53 UG334 v1 0 May 28 2007 Chapter 5 Character LCD Screen XILINX Power On Initialization The initialization sequence first establishes that the FPGA application wishes to use
142. ser contributed design by Matthias Alles Rotate knob to zoom fractal image press surrounding push 2 buttons to scroll the image www user rhrk uni kl de alles fpga files htm ASCII Terminal Implements a text terminal using an attached VGA display and PS 2 keyboard and 3 will communicate with HyperTerminal on a PC via an RS 232 serial connection Source included in www xilinx com products boards s3astarter reference_designs htm out STMicro M29DW323DT Parallel Flash Programmer Communicates to a PC using HyperTerminal via 4 an RS 232 serial connection Programs erases and reads the STMicro M29DW323DT parallel Flash PROM on the Starter Kit board www xilinx com products boards s3astarter reference designs htm parallel flash programmer Spartan 3AN FPGA Internal Flash Paint Application Use a mouse to create drawings and read or write them to In System Flash Loaded from internal SPI Flash in Spartan 3AN Starter Kit Board Requires setting Mode pins as described in Table 4 1 page 39 for Internal Master SPI mode For Spartan 3AN Starter Kit Board only www xilinx com products boards s3astarter reference_designs htm paint Scroll or Rotate Graphic In this mode rotate the knob to rotate the graphic image clockwise or counterclockwise Use the four push button switches to scroll the graphic image up down left or right Press the rotary knob to change to the Scroll or Scale Graphic mode Scroll or Scale Gra
143. standard straight through 9 pin serial cable connect the PC s 9 pin RS 232 port to the board s DCE connector see Figure 7 1 page 63 demo HyperTerminal File Edit View Call Transfer Help DS 6 28 E XILINX R Spartan 3A TM amp Spartan 3AN TM Starter Kit This complete development kit provides instant access to the capabilities of the Spartan 3 Generation The kit includes the board power supply USB cable and evaluation software Spartan 3A amp Spartan 3AN FPGAs Robust Anti Cloning Security Lowest Cost Connectivity Flexible Power Management Widest 1 0 Standard Selection Dynamic Input Delay Timing Fastest Time to Market Cost Conscious Configuration For more info please visit http www xilinx com Vou may MultiBoot to another FPGA configuration by pressing a number key 1 through 4 to indicate the desired configuration Connected 0 00 09 Auto detect 115200 8 N 1 UG334 c1 06 052707 Figure 1 6 Use HyperTerminal and a Standard Serial Cable to Connect to Board When the demonstration design begins operating it transmits a message using the serial port Press a number key on the PC to load the associated MultiBoot bitstream listed in Table 1 2 Key Components and Features The key features of the Spartan 3A Starter Kit board or the Spartan 3AN Starter Kit board are e Spartan 3A Starter Kit Board Xilinx 700K gate XC35700A Spartan 3A FPGA in the Pb free 484 ball BGA package
144. t The menu functions are highlighted in Table 1 1 and Figure 1 4 Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 15 UG334 v1 0 May 28 2007 Chapter 1 Introduction and Overview XILINX 16 Table 1 1 Function of Each Menu Control Press Knob Rotate Knob Press Push Button Move to next menu selection Depends on current mode as Depends on current mode as next mode shown in Figure 1 4 shown in Figure 1 4 Start Demonstration Design Power up board Press PROG_B button Select MultiBoot Select FPGA MultiBoot Configuration Buttons Load Configuration 1 0 ER Knob Spin Select Configuration es Knob Push More Options E o S MultiBoot f a Press Knob Scroll Rotate Graphic Buttons Scroll Image Knob Spin Rotate Image amp o Knob Push More Options a Press Knob Scroll Scale Graphic a o c x o 0 o a Buttons Scroll Image SE Knob Spin Scale Image Scale Knob Push More Options Press Knob 3 AutoPilot Volume AutoPilot Up lume or oon Egs g O B Buttons Restart AutoPilot s 9 2 Knob Spin Adjust Volume 3060 Knob Push More Options i 9 AutoPilot UGS334 c1 04 052707 Figure 1 4 Rotary Knob Push Button Menu System Select MultiBoot Configuration Image Spartan 3A 3AN FPGAs support a selectable MultiBoot configuration interface If the FPGA configures in one of its Master configuration modes then the FPGA always loa
145. t feed a resistor divider tree This approach Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 57 UG334 v1 0 May 28 2007 Chapter 6 VGA Display Port XILINX provides 4 bit resolution per color generating 12 bit color or 4 096 possible colors The series resistor in combination with the 754 termination built into the VGA cable ensures that the color signals remain in the VGA specified OV to 0 7V range The VGA_HSYNC and VGA_VSYNC signals use LVTTL or LVCMOS33 I O standard drive levels Drive the VGA_R 3 0 VGA_G 3 0 and VGA_B 3 0 signals High or Low to generate the desired colors The scaled analog outputis generated by a resistor divider that converts the FPGA s digital outputs for an individual color Each individual color output supports 16 possible values as described by Equation 6 1 The three separate controls for red green and blue support a maximum of 12 bit color or 4 096 values COLOR yyy AU x COLOR Equation 6 1 For simplicity the FPGA application can also treat the VGA port as a three bit interface by driving all four color outputs with the same digital value The corresponding eight basic color values are shown in Table 6 1 Table 6 1 Example Display Color Codes VGA_R 3 0 VGA_G 3 0 VGA_B 4 0 Resulting Color 0000 0000 0000 0000 0000 1111 0000 1111 0000 0000 1111 1111 1111 0000 0000 1111 0000 1111 1111 1111 0000 1111 1111 1111 White Signal Timi
146. tarter reference_designs htm parallel_flash _programmer Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 89 UG334 v1 0 May 28 2007 Chapter 11 Parallel NOR Flash PROM 90 www xilinx com XILINX Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Chapter 12 SPI Serial Flash The Spartan 3A 3AN Starter Kit board includes two different styles of SPI serial Flash as shown in Figure 12 1 Only one style is available to configure the FPGA After configuration however the FPGA application has full access to both PROMs for data storage or Flash update purposes e STMicroelectronics M25P16 16 Mbit SPI serial Flash PROM e Atmel AT45DB161D 16 Mbit SPI serial DataFlash PROM Atmel AT45DB161D STMicro M25P16 SPI Flash Select Platform Flash Jumpers J1 Jumper J46 JTAG and SPI Programming Blocks J23 J25 FPGA Mode Select Jumpers J26 UG334_c12_01_052407 Figure 12 1 SPI Serial Flash PROMs and Associated Jumpers The SPI serial Flash is useful in a variety of applications The SPI Flash provides a possible means to configure the FPGA a new feature in Spartan 3E and Spartan 3A 3AN FPGAs The SPI Flash is also available to the FPGA after configuration for a variety of purposes such as e Simple non volatile data storage e Storage for identifier codes serial numbers IP addresses etc e Storage of MicroBlaze processor code that can be shadowed into DDR S
147. tep Down DC DC and Dual Linear Regulator with IC Compatible Interface www national com pf LP LP3906 html Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 141 UG334 v1 0 May 28 2007
148. the 16 Mbit SPI serial DataFlash memory Linear Technology for the SPI compatible A D and D A converters and the programmable pre amplifier SMSC for the 10 100 Ethernet PHY National Semiconductor for the four rail voltage regulators that power the FPGA and and all peripheral components Xilinx Inc Configuration Solutions Division for the XCF04S Platform Flash PROM and support for the embedded USB programmer This manual contains the following chapters Chapter 1 Introduction and Overview provides an overview of the key features of the Spartan 3A 3AN Starter Kit board Chapter 2 Switches Buttons and Rotary Knob defines the switches buttons and knobs present on the Spartan 3A 3AN Starter Kit board Chapter 3 Clock Sources describes the various clock sources available on the Spartan 3A 3AN Starter Kit board Chapter 4 FPGA Configuration Options describes the configuration options for the FPGA on the Spartan 3A 3AN Starter Kit board Chapter 5 Character LCD Screen describes the functionality of the character LCD screen Chapter 6 VGA Display Port describes the functionality of the VGA port Chapter 7 RS 232 Serial Ports describes the functionality of the RS 232 serial ports Chapter 8 PS 2 Mouse Keyboard Port describes the functionality of the PS 2 mouse and keyboard port Chapter 10 Digital to Analog Converter DAC describes the functionality of the D
149. the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board DDR2 SDRAM provides an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation UCF Location Constraints Figure 6 4 provides the UCF constraints for the VGA display port including the I O pin assignment the I O standard used the output slew rate and the output drive current NET VGA_R lt 3 gt LOC C8 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_R lt 2 gt LOC B8 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_R lt 1 gt LOC B3 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_R lt 0 gt LOC A3 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_G lt 3 gt LOC D6 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_G lt 2 gt LOC C6 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_G lt 1 gt LOC D5 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_G lt 0 gt LOC C5 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA_B lt 3 gt LOC C9 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA B 2 LOC B9 IOSTANDARD LVTTL DRIVE 8 SLEW FAST NET VGA B 1 L
150. tible with the FX2 connector on the starter kit board e Digilent FX2 Wirewrap Board FX2WW from Digilent Inc http www digilentinc com Products Detail cfm Prod FX2WW e Digilent FX2 Breadboard FX2BB from Digilent Inc http www digilentinc com Products Detail cfm Prod FX2BB e Video Decoder Board VDEC1 from Digilent Inc http www digilentinc com Products Detail cfm Prod VDEC1 Mating Receptacle Connectors The Spartan 3A 3AN Starter Kit board uses a Hirose FX2 100P 1 27DS header connector The header mates with any compatible 100 pin receptacle connector including board mounted and non locking cable connectors e Hirose connectors http www hirose connectors com e FX2Series Connector Data Sheet http www hirose co j p cataloge hp e57220088 pdf www xilinx com Spartan 3A 8AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Hirose 100 Pin FX2 Edge Connector J17 UCF Location Constraints Figure 15 3 provides the UCF constraints for the FX2 connector including the I O pin assignment and the I O standard used assuming that all connections use single ended I O standards FX2 Connector FX2 NET FX2_CLKIN LOC M22 IOSTANDARD LVCMOS33 NET FX2_CLKIO LOC L21 IOSTANDARD LVCMOS33 SLEW FAST DRIVE 8 NET FX2_CLKOUT
151. tic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in Figure 6 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass pixel 0 0 pixel 0 639 gt A C 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time i Stable current ramp Information is displayed during this time Total horizontal time Horizontal display time retrace time tug A Desi front porch gt front porch eooos cod a ES L Horizontal sync signal L back porch sets the retrace frequency UG230_c6_02_021706 Figure 6 2 CRT Display Timing Example The display resolution defines the size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated Modern VGA displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller pr
152. tly there is a close relationship between the memory data pins SD_DQ lt 15 8 gt SD_DQ_ lt 7 0 gt and their associated strobe signals The MIG software automatically assigns pins based on this requirement and the Spartan 3A 3AN Starter Kit board is designed accordingly The MIG core for Spartan 3A 3AN FPGAs includes a loopback signal to calibrate the read strobe timing The loopback signal uses two FPGA pins labeled SD_LOOP_IN and SD_LOOP_OUT For best performance the length of the loop back trace must be equal to the clock delay from the FPGA to the memory plus the strobe delay from the memory back to the FPGA Put another way the loopback trace must be one round trip time to and from the memory Also the loopback signal should be in the center of the data interface pins for best results not near the edge or in another FPGA I O bank The Spartan 3A 3AN Starter Kit board was designed accordingly The Xilinx Memory Interface Generator MIG User Guide provides additional layout recommendations in Appendix A Memory Implementation Guidelines The board layout has been optimized for reaching frequencies above 133 MHz and 167 MHz It can actually achieve the DDR400 performance level of 200 MHz or 400 Mbps per I O with an optimized memory interface controller It is recommended to get the latest updates of the MIG tool that integrates the latest performance enhancements e Memory Interface Generator MIG http www xilinx com xlnx x
153. tor J32 integrated magnetics SMSC LAN8700 10 100 Ethernet PHY 25 MHz Crystal UG334_c14_01_052407 Figure 14 1 10 100 Ethernet PHY with RJ 45 Connector Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 117 UG334 v1 0 May 28 2007 Chapter 14 10 100 Ethernet Physical Layer Interface XILINX Ethernet PHY Connections 118 The FPGA connects to the LAN8700 Ethernet PHY using a standard Media Independent Interface MID as shown in Figure 14 2 A more detailed description of the interface signals including the FPGA pin number appears in Table 14 1 SMSC LAN8700 FPGA 10 100 Ethernet PHY See Table ae TXD 3 0 D8 B2 E11 See Table E_TX_EN TX_EN ETDs TXD4 TX_ER nINIT E TX CLK E ESAE RXD 3 0 oer E RXD lt 4 gt E RX CLK E CRS E COL E MDC RXD4 RX ER RX CLK CRS PHYAD4 COL_MII_CRS DV MDC MDIO E 25 000 MHz E MDIO E NRST nRST UG334 c14 02 052407 Figure 14 2 FPGA Connects to Ethernet PHY via MII Table 14 1 FPGA Connections to the LAN83C185 Ethernet PHY Signal Name a Function E_TXD lt 4 gt B2 Transmit Data to the PHY E_TXD lt 4 gt is also the MII E TXD lt 3 gt F7 Transmit Error E_TXD lt 2 gt E6 E_TXD lt 1 gt E7 E_TXD lt 0 gt F8 E_TX_EN D8 Transmit Enable E_TX_CLK E11 Transmit Clock 25 MHz in 100Base TX mode and 2 5 MHz in 10Base T mode E RXD 4
154. tor band two insulator bands can UG330_c16_02 021507 Figure 16 2 Examples of Miniature Stereo Jacks FPGA Connections The FPGA drives a 3 3V digital signal to each side of the audio jack as indicated in Table 16 1 A monophonic connector only uses the left side channel Table 16 1 Digital Outputs to Stereo Minijack Signal Name FPGA Pins Stereo Jack Mono Jack AUD _L Y10 Left side audio Audio channel AUD_R v10 Right side audio Drive to Hi Z UCF Location Constraints Figure 16 3 provides the UCF constraints for the audio connector Controls VCCAUX supply rail IC19 NET AUD_L LOC Y10 IOSTANDARD NET AUD_R LOC V10 IOSTANDARD Figure 16 3 UCF Constraints for Audio Connector QUIETIO QUIETIO VTTL DRIVE VTTL DRIVE 8 SLEW 8 SLEW Related Resources The demonstration design shipped with the board includes an audio example e Spartan 3A 3AN Starter Kit Demo Design Overview www xilinx com products boards s3astarter reference_designs htm demo e Restoring the Out of the Box Flash Programming www xilinx com products boards s3astarter reference_designs htm out 136 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 17 Voltage Supplies The voltage supplies are located in the upper left corner of the board as shown in Figure 17 1 AC wall adapter connector 5V DC
155. tting The Always Enabled setting for Jumper J46 allows the FPGA to read additional data from the Platform Flash PROM after configuration as described in Xilinx application note XAPP694 Caution The FPGA s INIT_B pin also connects to the Platform Flash PROM s OE RESET pin If the jumper controlling the Platform Flash PROM jumper J46 in Table 4 2 page 40 is set to Always Enabled then the INIT_B signal controls the PROM s active Low output enable OE input or active High RESET input e XAPP694 Reading User Data from Configuration PROMs www xilinx com bvdocs appnotes xapp694 pdf UCF Location Constraints Figure 2 15 provides the UCF constraints for the optional LEDs including the I O pin assignment the I O standard used the output slew rate and the output drive current The ENABLE_SUSPEND constraint must be set to NO in order to use FPGA_AWAKE LED NET FPGA_INIT_B LOC V13 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 The AWAKE LED is only available if Suspend mode is disabled CONFIG ENABLE SUSPEND NO NET FPGA AWAKE LOC AB15 IOSTANDARD LVTTL SLEW QUIETIO DRIVE 4 Figure 2 15 UCF Constraints for Optional Discrete LEDs www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 3 Clock Sources Overview The Spartan 3A 3AN Starter Kit board supports three primary clock input sources as shown in Figu
156. ttp www xilinx com picoblaze e Digilent Inc Peripheral Modules http www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Chapter 11 Parallel NOR Flash PROM As shown in Figure 11 1 the Spartan 3A 3AN Starter Kit board includes a 32 Mbit 4 Mbyte parallel NOR Flash PROM STMicro FPGA M29DW323DT NF_OE NF_WE NF_BYTE NF_STS NF_RP 32 Mbit NF_WP NF_D lt 14 8 gt DQ 14 8 D 7 1 DQ 7 1 Dion SPL MISO Dolo A 21 1 bu arcis A 20 0 AO PEN D15 A 1 A 25 22 UG334_c11_01_052407 Figure 11 1 Connections to 32 Mbit Parallel NOR Flash Memory The parallel NOR Flash PROM provides various functions e Stores a single FPGA configuration in the Flash memory e Stores various different FPGA configurations in the Flash memory and dynamically switches between the various images using the FPGA s MultiBoot feature e Stores and executes MicroBlaze processor code directly from the Flash memory e Stores MicroBlaze processor code in the Flash memory and shadows the code into the DDR2 SDRAM memory before executing the code e Stores non volatile user data from the FPGA application Spartan 3A 3AN Starter Kit Board User Guide www xilinx com 83 UG334 v1 0 May 28 2007 Chapter 11 Parallel NOR Flash PROM Flash Connections Table 11 1 shows the connections b
157. ur X CLK N LOC AB10 MX_CLK_P LOC AA10 IX_N lt 0 gt LOC AA3 TX_P lt 0 gt LOC AB2 TX_N lt 1 gt LOC AA4 IX_P lt 1 gt LOC AB3 X N 2 LOC AB6 X P 2 LOC AA6 X N 3 LOC AB7 PX Pei LOC Y7 U X N 4 LOC AB8 rX_P lt 4 gt LOC AA8 ur Connector RX IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS_33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS_33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 IOSTANDARD LVDS 33 Figure 15 7 UCF Location Constraints for Receive and Transmit Headers 130 www xilinx com Spartan 3A 8AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 7 XILINX Six Pin Accessory Headers Six Pin Accessory Headers The six pin accessory headers provide easy I O interface expansion using the various Digilent Peripheral Modules J18 Header The J18 header shown in Figure 15 8 is located in the bottom right corner of the board along the right edge
158. v1 0 May 28 2007 Chapter 5 Character LCD Screen XILINX 50 Data from CG RAM or DD RAM command The cursor or blink position moves accordingly Bit DBO S Shift 0 Shifting disabled 1 During a DD RAM write operation shift the entire display value in the direction controlled by Bit DB1 I D It appears as though the cursor position remains constant and the display moves Display On Off The display is turned on or off controlling all characters The cursor and cursor position character underscore blink Execution Time 40 us Bit DB2 D Display On Off 0 No characters displayed However data stored in DD RAM is retained 1 Display characters stored in DD RAM Bit DB1 C Cursor On Off The cursor uses the five dots on the bottom line of the character The cursor appears as a line under the displayed character 0 No cursor 1 Display cursor Bit DBO B Cursor Blink On Off 0 No cursor blinking 1 Cursor blinks on and off approximately every half second Cursor and Display Shift Moves the cursor and shifts the display without changing DD RAM contents Shift cursor position or display to the right or left without writing or reading display data This function positions the cursor in order to modify an individual character or to scroll the display window left or right to reveal additional data stored in the DD RAM
159. vert the current measurement Amperes or mA to a power measurement Watts or mW by multiplying the measured result by the supply voltage 12C Voltage Adjustment Interface Each LP3906 regulator has an two wire I C serial interface that optionally controls various functions such as the regulator output voltage As indicated in Table 17 3 the C interface can be controlled by the FPGA application using the I O pins indicated or by some external controller using the through hole mounting pads provided on the board shown in Figure 17 1 140 Table 17 3 12C Voltage Adjustment Interface to Regulator Regulator 12C Control Input FPGA Connection Tarougn bold Connection REG2 SCL SCL D11 REG2 SCL IC18 REG2_SDA SDA F13 REG2 SDA REG1_SCL SCL E13 REG1 SCL IC19 REG1_SDA SDA D13 REG1 SDA Possible Applications For experimentation purposes only Xilinx only recommends adjusting the two supplies listed below By default the Vecaux supply to the FPGA is set to 3 3V as required for Spartan 3AN FPGAs On Spartan 3A FPGAs Vecaux can be either 2 5V or 3 3V with potentially lower power consumption at 2 5V Consequently Vecayx can be reduced to 2 5V by adjusting the LDO1 output on the LP3906 regulator designated IC19 The corresponding I C control signals are REG1_SCL and REG1_SDA By default the reference voltage to Channels C and D on the D A converter is 3 3V However this voltage can be adjusted
160. w these steps to prepare the board for direct SPI Flash programming using the embedded USB JTAG programmer included on the board 1 Disconnect power to the board 2 Connecteither a USB cable between the board and the PC or connect a separate JTAG cable as described in Using a Separate JTAG Parallel Programming Cable Optional page 97 3 Locate the J1 J23 and J25 jumpers in the upper right corner of the board using Figure 12 1 as a guide Figure 12 4 also provides a reference diagram STMicro PROM Atmel PROM SD J1 J1 RoM cSO I CSO SEL ROM CSO csos E rows CS oO O x A oO pees s J Heade E E J25 Heade L L J23 23828 o gt SD S sck PROG B GND J1 6 UGS330 c15 05 032907 Figure 12 4 Jumper Settings for Direct SPI Flash Programming 96 www xilinx com Spartan 3A 3AN Starter Kit Board User Guide UG334 v1 0 May 28 2007 XILINX Creating and Programming Configuration Images for SPI Serial Flash 4 Insert a jumper in jumper block J1 as shown in Figure 12 4 The figure shows the setting to program the STMicro M25P16 PROM Alternatively set the jumper to program the Atmel AT45DB161D DataFlash PROM 5 Insert four jumpers between jumper blocks J25 and J23 as shown in Figure 12 4 These jumpers connect the embedded USB JTAG programmer on the J25 jumper pins to the SPI PROM via the J23 jumper pins 6 Set the FPGA mode select pins for Master SPI mode using jumper J26 as shown in
161. when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 8 2 Starter Kit Board User Guide www xilinx com 67 UG334 v1 0 May 28 2007 Chapter 8 PS 2 Mouse Keyboard Port XILINX Mouse PS 2 compatible mice potentially support two modes In polled mode the host controller interrogates the mouse for activity In streaming mode the mouse reports any movement or key presses Streaming mode is the default operating mode To specifically enter streaming mode the FPGA host must transmit a Set Stream Mode command 0xEA to the mouse The mouse then generates a clock and data signal when moved or when one or more keys are pressed otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a
162. y to connect to 34 conductor flat ribbon cable assemblies that use a 2x17 0 1 inch form factor Table 15 5 Example 34 Conductor Cable Assemblies Distributor Digi Key www digikey com Distributor Manufacturer Part Number Type Length 3M MBA AK 3420K ND Flat ribbon cable multi color twisted 50 80 cm pair gold finish 20 inch C3AAG 3406G ND Flat ribbon cable gray gold finish 15 24 cm CW Industries 6i h C3AAG 3406M ND Flat ribbon cable multi color gold finish 6 inch C3AAG 3418G ND Flat ribbon cable gray gold finish 45 72 cm CW Industries 18 inch C3AAG 3418M ND Flat ribbon cable multi color gold finish 18 inch UCF Location Constraints Figure 15 7 provides the User Constraint File UCF constraints for the Receive and Transmit headers including the I O pin assignment and the I O standard used NET NET NET NET NET NET NET NET NET NET NET High Speed LVDS Receive RX_CLK_N LOC A11 RX_CLK_P LOC A12 RX_N lt 0 gt LOC B4 RX_P lt 0 gt LOC A4 RX_N lt 1 gt LOC A5 RX_P lt 1 gt LOC B6 RX_N lt 2 gt LOC A6 RX_P lt 2 gt LOC A7 RX_N lt 3 gt LOC A8 RX_P lt 3 gt LOC A9 RX_N lt 4 gt LOC C10 RX_P lt 4 gt LOC A10 NET High Speed LVDS Transmit Connector TX NET NET NET NET NET NET NET NET NET NET NET NET ur ur um ur r

Xilinx UG334 Spartan-3A/3AN Starter Kit Board User Guide

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