UG-2864HSWEG01 128X64 Evaluation Kit User Guide
Contents
1. 15 94V 0 3333 ia 158 20688 Figure2 The combination of the module EVK The SSD1306 is COG type package that the connect pads are on the bottom of the module connector When finished assembled the module and EVK then push the locking pad to lock the module See the Figure 1 and Figure2 User can use leading wire to connect EVK with customer s system The example shows as Figure 3 15 ISEB Figure3 EVK with test platform Note 1 It is the internal most positive voltage supply In this sample is connected to power supply Note 2 Those are leading wire connect to control board Those are data pin DO D7 Note 3 Those are leading wire connect to control board Those are control pin DC CS RD WR RES 16 ISEB 6 Power down Power up Sequence To protect OLED panel and extend the panel time the driver IC power up down routine should include a delay period between high voltage and low voltage power sources during turn on off Such that panel has enough time to charge up or discharge before after operation Power up Sequence Vpp on Power up Vpp on Send Display off command Driver IC Initial Setting Display on Clear Screen Power up Vcc Delay 100ms when Vpp 15 stable Vpp pu 4 d m X Vss Ground 7 Send Display on command Power down Sequence Display off2. CIH i 1 luF luF WISIS Il ot U luF YO BSD z TDO Use for TIC Interface CON circuit roc P DO 5CL Bs Dl122 25DA 3 Use for SPI Interface FONS cirat D 3CLE 5 VE D1 2 3DIN 4 I cobs HEADER 202 0p k C 5 C0 s be oC Cd Cd C4 Oe a OO RO p 0 01 t ree G GO GO C Table 7 1 MICU Bus Interface Pin Selection I Interface 6800 parallel 8080 parallel 4 wire Serial 3 wire Serial SSD1306 E E interface interface interface interface Pin Name 2 2 5 8 bit 1s connected to Wss 1 15 connected to Von 1 R1 should be replaced as 560kO while supplying 9V on VCC externally ISEB 3 Symbol define VCC Power supply for panel driving voltage VBAT Power supply for panel driving voltage Embedded Charge Pump VDD Power supply for core logic operation VSS This is ground pin BS0 BS2 bus interface selection pin Page 4 Table7 1 CS This pin is chip select input active LOW RES This pin is reset signal input active LOW D C This is DATA COMMAND control pin When it is Pulled HIGH the data at D 0 7 is treated as data When it is pulled LOW the data at D 0 7
3. ime MACHEN Address and Select setup time E 0 lads Address setup time T 50 Select setup time 10 Tiny We Low puse vidi i pee High pulse width Data hen time 10 Sah wa Table 1 80 Series MPU parallel Interface Write Timing Characteristics READ CHARACTERISTICS Figure 2 80 Series MPU parallel Interface Read Timing Diagram Conditions Related Pins fe paeme ea AME and Select setup time 0 Address and Select hold time 0 Address setup time 50 Address hold time 20 select setup time 10 Select hold time 058 10 Read Low pulse widi h 0 Im Data output delay time ms 200 Data output hold time CL 100pF 215 to DO Table 2 80 Series MPU parallel Interface Read Timing Characteristics Univision et t 4 2 6800 Series MPU parallel Interface PARALLEL INTERFACE CHARACTERISTICS 6800 SERIES MPU D15 to DO Figure 3 68 Series MPU parallel Interface Write Timing Diagram el VDD S 25 Icswsa Chip select D time 10 las Address setup time AQ 50 Address hold time RAN 20 levee White cycle time iewHwWES Write High Time Write Low Time Read cycle time Parameter read Read High Parameter read Read Low Parameter read IPWLRGE Iovase Read cycle time Data read Read High Data read ausm Read Low D
4. off Send Display off command 2 Power down Vppu 3 Delay 100ms when V 1s reach and panel is completely discharges 4 Power down Vpp 17 IRE 7 How to use SSD1306 module 7 1 Initial Step Flow Reset Driver IC RES 0 Delay 10ms RES 1 Driver IC Initial Code Suggest all register set again Display on Clear RAM Start Display ISEB RD recommends Initial Code Internal setting Charge pump WRITE_COMMAND 0xae turn off oled panel WRITE_COMMAND 0x00 set low column address WRITE_COMMAND 0x10 set high column address WRITE_COMMAND 0x40 set start line address WRITE_COMMAND 0x81 set contrast control register WRITE_COMMAND 0xcf WRITE COMMAND 0xa1 set segment re map 95 to 0 WRITE COMMAND 0xa6 set normal display WRITE COMMAND 0xa8 set multiplex ratio 1 to 64 WRITE COMMANDY 0x3f 1 64 duty WRITE COMMAND O0xd3 set display offset WRITE COMMAND 0x00 not offset WRITE COMMAND 0xd5 set display clock divide ratio oscillator frequency WRITE COMMAND 0x80 set divide ratio WRITE COMMAND 0xd9 set pre charge period WRITE 0 1 WRITE COMMAND 0xda set com pins hardware configuration WRITE 0 12 WRITE COMMAND O0xdb set vcomh WRITE 0 40 WRITE COMMAND 0x8d set Charge Pump enable disable WRITE COMMAND 0x14 set 0x10 disa
5. ISEB ATH BRS FH UG 2864HSWEGO1 128 64 Evaluation Kit User Guide Writer James Wang E mail James_Wang univision com tw Version Preliminary ISEB Contents 1 REVISION HISTORY 3 LM ZU ecu u ee near 4 5 SV GEHE u en E 5 4 TIMMING 6 5 nam nn nun 6 4 1 8080 Series MPU parallel 7 4 2 6800 Series MPU parallel 9 4 3 SP LINIEN AO ee een E 10 a ING TOT AC Craig nenn O AE 11 9 EVR USE INIOAUE LION ee E ee anne 14 6 Power down and Power up 17 7 How to use 5501806 Moodle un een een 18 Tal NAL FOW ensemble EE 18 7 2 RD recommend Initial Code for Interface 19 7 2 1 Sub Function for Interface essere 20 AIZE 1 REVISION HISTORY ISEB 2 Schematic wI 1 SS WEGoOl Et Es Ese ss se Is le s ses Fs ls et e a e ID I Ir Ica 13
6. 0 it defines the following data byte as a command If the D C amp bit is set to logic 1 it defines the following data byte as a data which will be stored at the GDDRAM The GDDRAM column address pointer will be increased by one automatically after each data write Acknowledge bit will be generated after receiving each control byte or data byte The write mode will be finished when a stop condition is applied The stop condition is also defined in Figure 6 The stop condition is established by pulling the SDA in from LOW to HIGH while the SCL stays HIGH lisTART START condition STOP condition 12 BREIT BRS FH DATA OUTPUT BY TRANSMITTER Non acknowledge E DATA OUTPUT BY RECEIVER Acknowled ge SCL FROM MASTER START Clock pulse for acknowledgement Condition Flease be noted that the transmission of the data bit has some limitations 1 The data bit which is transmitted during each SCL pulse must keep at a stable state within the HIGH period of the clock pulse Please refer to the Figure 8 for graphical representations Except in start or stop conditions the data line can be switched only when the SCL is LOW 2 Both the data line SDA and the clock line SCL should be pulled up by external resistors Datalineis Change of stable data 13 IRE C158 2066A C158 2068 MH 15 94V 0 5 Figure EVK and OLED Module 14 IRE
7. ata read Data setup time Data hold time Data output access time CL toooes Data output disable time Table 3 68 Series MPU parallel Interface Write Timing Characteristics ISEB 4 3 SPI Interface SERIAL INTERFACE CHARACTERISTICS SCLK DO in i V ngu Figure 4 Serial peripheral interface Timing Diagram VDD 2 BV 25 C o serial clock cycle High pulse width Low pulse width 955 Data setup time Data hold time SID 01 Chip select setup time Chip select hold time zs select nen pulse width ue Kreta te Table 4 Serial peripheral interface Timing Characteristics 10 ISEB 4 4 Interface MPU I C Interface The I C communication interface consists of slave address bit SAO I C bus data signal SDA SDAur D gt for output D and SDA for input and I C bus clock signal SCL D Both the data and clock signals must connected to pull up resistors RES is used for the initialization of device a Slave address bit 5 0 55001300 has to recognize the slave address before transmitting or receiving any information by the l C bus The device will respond to the slave address following by the slave address bit bit and the read write select bit R W bit with the following byte format D bs ba ba bb 011 11 0 SAO R W SA0 bit provides an extension bit fo
8. ble WRITE COMMANDY O0xaf turn on oled panel 19 ISEB External setting WRITE_COMMAND 0xae turn off oled panel WRITE_COMMAND 0x00 set low column address WRITE_COMMAND 0x10 set high column address WRITE_COMMAND 0x40 set start line address WRITE_COMMAND 0x81 set contrast control register WRITE_COMMAND 0x8pf WRITE COMMAND 0xa1 set segment re map 95 to 0 WRITE COMMAND 0xa6 set normal display WRITE COMMAND 0xa8 set multiplex ratio 1 to 64 WRITE COMMANDY 0x3f 1 64 duty WRITE COMMAND 0xd3 set display offset WRITE COMMAND 0x00 not offset WRITE COMMAND 0xd5 set display clock divide ratio oscillator frequency WRITE COMMAND 0x80 set divide ratio WRITE COMMAND 0xd9 set pre charge period WRITE COMMAND 0x22 WRITE COMMAND 0xda set com pins hardware configuration WRITE 0 12 WRITE COMMAND O0xdb set vcomh WRITE 0 40 WRITE COMMAND 0x8d set Charge Pump enable disable WRITE COMMAND 0x10 set 0x14 Enable WRITE COMMANDY O0xaf turn on oled panel 20
9. r the slave address Either 0111100 or 0111101 can be selected as the slave address of 5501300 D C pin acts as SAO for slave address selection RAW bit is used to determine the operation mode of the l C bus interface R W 1 it is in read mode R W 0 it is in write mode l C bus data signal SDA SDA acts as a communication channel between the transmitter and the receiver The data and the acknowledgement are sent through the SDA It should be noticed that the ITO track resistance and the pulled up resistance at SDA pin becomes a voltage potential divider As a result the acknowledgement would not be possible to attain a valid logic 0 level in SDA SDAA are tied together and serve as SDA The SDA pin must be connected to act as SDA The SDA4 4 pin may be disconnected When SDA r pin is disconnected the acknowledgement signal will be ignored in the I C bus I C bus clock signal SCL The transmission of information in the I C bus is following a clock signal SCL Each transmission of data bit is taken place during a single clock period of SCL Co Continuation bit DIC Data Command Selection bit ACK Acknowledgement SAD Slave address bit RAW Read Wnte Selection bit Write mode 5 Start Condition P Stop Condition 011110 Control byte gt Data byte Control byte E Databyte 13 ale S X X Uu PS Y Slave Addre
10. ss m 0 words 1 byte gt bytes MSB 011110 Fle SSD1300 Slave Address elg o o o0 0 o Control byte 11 ISEB Write mode for 1 The master device initiates the data communication by a start condition The definition of the start condition is shown in Figure 6 The start condition 15 established by pulling the SDA from HIGH to LOW while the SCL stays HIGH The slave address is following the start condition for recognition use For the 5501300 the slave address is either 0111100 or b0111101 by changing the SAO to LOW or HIGH D C pin acts as SAD The write mode is established by setting the R W bit to logic 0 An acknowledgement signal will be generated after receiving one byte of data including the slave address and the RAN bit Please refer to the Figure 7 for the graphical representation of the acknowledge signal The acknowledge bit is defined as the SDA line is pulled down during the HIGH period of the acknowledgement related clock pulse After the transmission of the slave address either the control byte or the data byte may be sent across the SDA A control byte mainly consists of Co and D C bits following by six 0 5 a Ifthe Co bit is set as logic 0 the transmission of the following information will contain data bytes only b The D C bit determines the next data byte is acted as a command or a data If the D C bit is set to logic
11. t should be kept NC if it is not used BS 2 0 MCU bus interface selection pins IREF This is segment output current reference A resistor should be connected between this pin and VSS to maintain the IREF current at 12 5 UA FR This pin outputs RAM write synchronization signal Proper timing between MCU data writing and frame display timing can be achieved to prevent tearing effect It should be kept NC if it is not used CL This is external clock input pin When internal clock is enabled i e HIGH in CLS pin this pin is not used and should be connected to VSS When internal clock is disabled i e LOW in CLS pin this pin is the external clock source input pin CLS This is internal clock enable pin When it is pulled HIGH i e connect to VDD internal clock is enabled When it is pulled LOW the internal clock is disabled an external clock source must be connected to the CL pin for normal operation RES This pin is reset signal input When the pin is pulled LOW initialization of the chip is executed Keep this pin HIGH i e connect to VDD during normal operation CS This pin is the chip select input Active LOW ISEB 4 IC INTERFACES DESCRIPTIONS amp TIMMING CHARACTERISTICS 4 1 80 Series MPU parallel Interface WRITE CHARACTERISTICS Figure 1 80 Series MPU parallel Interface Write Timing Diagram VDD u Simi Codes Reed Pins unt Wi
12. will be transferred to the command register In I2C mode this pin acts as SAO for slave address select R W This is read write control input pin connecting to the MCU interface When interface to a 6800 series microprocessor Read mode will be carried out when this pin is pulled HIGH and write mode when low When interface to an 8080 microprocessor this pin when be the data Write input When serial interface is selected this pin must be connected to Vss E RD When interface to a 6800 series microprocessor this pin will be used as the Enable E signal When interface to an 8080 microprocessor this pin receives the Read RD signal 00 07 These are 8 bit bi directional data bus to be connected to the microprocessor s data bus When serial interface mode is selected DO SCLK will be the serial clock input D1 SDIN will be the serial data input D2 should be left opened When 2 mode is selected D1 SDAin AND D2 SDAout should be tied together DO SCL is the I2Cclock input IREF This is segment output current reference pin VCOMH This pin for COM signal deselected level voltage A capacitor should be connected between this pin and VSS VBAT It should be connected to VDD Charge Pump DISABLE or could be connected to individual power voltage supply VBAT 3 4 4 2V Charge Pump ENABLE C1P C1N It should be connected a capacitor C2P C2N It should be connected a capacitor VBREF It should be connected VSS I
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