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MC9S12DJ64 Device User Guide V01.13 Covers also

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1. Internal Pull Pin Name Pin Name Pin Name Pin Name Powered Resistor Description Function Function2 Function3 Function4 by Reset State EXTAL VDDPLL Oscillator Pins XTAL RESET VDDR External Reset TEST Test Input VREGEN Voltage Regulator Enable Input XFC PLL Loop Filter BKGD TAGHI MODC ee Debug Tag High Mode Port AD Input Analog Input AN7 of PAD15 AN15 ETRIG1 ATD1 External Trigger Input of ATD1 Port AD Inputs Analog Inputs PAD 14 08 14 08 AN 6 0 ads 9 Port AD Input Analog Input of 007 ETRIGO ATDO External Trigger Le of ATDO Port AD Inputs Analog Inputs AN 6 0 PAD 06 00 AN 06 00 g np 6 0 PA 7 0 AMAT Port A I O Multiplexed Address Data ADDRI 7 0 PB 7 0 DATA 7 0 Port B I O Multiplexed Address Data Mode PE7 NOACC XCLKS depen Port E I O Access Clock Select dant PE6 IPIPE1 MODB While RESET pin is Port E I O Pipe Status Mode Input 5 IPIPEO MODA Port I O Pipe Status Mode Input PE4 ECLK Port E I O Bus Clock Output PE3 LSTRB TAGLO Port E O Byte Strobe Tag Low PE2 R W Port E I O R W in expanded modes PE1 IRQ Port E Input Maskable Interrupt PEO XIRQ Port E Input Non Maskable Interrupt PH7 KWH7 Port I O Interrupt PH6 KWH6 Port H I O Interrupt PH5 KWH5 Port H I O Interru
2. 29 001 0010 MMC map 3 of 4 HCS12 Module Mapping Control Table 1 4 29 001E 001 MEBI map 2 of 3 HCS12 Multiplexed External Bus Interface 29 001F 001F INT map 2 of 2 HCS12 29 0020 0027 Reserved cra bua Loc kr e ER Ya xcd 29 0028 002F HCS12 Breakpoint 30 0030 0031 map 4 of 4 HCS12 Module Mapping Control 30 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface 30 0034 CRG Clock and Reset Generator 30 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels 31 0080 009F Analog to Digital Converter 10 Bit 8 Channel 34 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel 95 00C8 00CF SCIO Asynchronous Serial Interface 37 0000 0007 SCI Asynchronous Serial Interface 37 0008 00DF SPIO Serial Peripheral Interface 37 00EO0 00E7 IIC Inter IC Bus sce dana dee E RIGHE RE Roe 38 00E8 00EF BDLC Bytelevel Data Link Controller 1850 38 SODEO SDOEF Reserv
3. Signals shown in Bold are not available on the 80 Pin Package 23 MC9S12DJ64 Device User Guide 01 13 24 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 1 5 Device Memory Map Table 1 1 and Figure 1 2 show the device memory map of the MC9S12DJ64 after reset The 1K is mapped twice a 2K address space Note that after reset the bottom 1k of the EEPROM 0000 03FF are hidden by the register space and the 50400 07FF is hidden by the RAM M MOTOROLA Table 1 1 Device Memory Map Address Module Bytes 0000 000F HCS12 Multiplexed External Bus Interface 16 0010 0014 HCS12 Module Mapping Control 5 0015 0016 HCS12 Interrupt 2 0017 0019 Reserved 3 001A 001B Device ID register PARTID 2 001C 001D HCS12 Module Mapping Control 2 001E HCS12 Multiplexed External Bus Interface 1 001F HCS12 Interrupt 1 0020 0027 Reserved 8 0028 002F HCS12 Background Debug 8 0030 0031 HCS12 Module Mapping Control 2 0032 90033 512 Multiplexed External Bus Interface 2 0034 003F Clock and Reset Generator PLL RTI 12 0040 007F Enhanced Capture Timer 16 bit 8 channels 64 0080 009F Analog to Digital Converter 10 bit 8 channels 32 00A0 00C7 Pulse Width Modulator 8 bit 8 channels PWM 40 00C8 00CF Serial Communications Interfa
4. 90083 PorTaDo 6 5 4 5 2 i Write 800 joa Write E EY 0091 ATDoDRoL Bi7 Bite 0 0 O 0 Write 0092 ATDoDR H Pead Bitis 14 13 12 ii 10 9 Pis Write 0093 ATDODRIL Mad Bite 0 0 0 Write G 80094 ead Bitis 14 131 12 10 9 Pis Write 50095 ATDoDRoL Bitz Bite 0 o 0 0 0 0 Write Write EURO nn ns 0097 Bite 0 0 0 0 Write pertes mus er ES 0098 ATDODR4H 2 34 M MOTOROLA 0080 Address 0099 009A 009B 009C 009D 009E 009F 00A0 Address 00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AA 00AB 00AC 00AD 00AE 00AF M MOTOROLA 009F Name ATDODRAL ATDODRSH ATDODRSL ATDODR6H ATDODR6L ATDODR7H ATDODR7L 00C7 Name PWME PWMPOL PWMCLK PWMPRCLK PWMCAE PWMCTL PWMTST Test Only PWMPRSC Test Only PWMSCLA PWMSCLB P
5. 2 of 3 HCS12 Multiplexed External Bus Interface Read mae I 0 0 0 0 9 Write were INT map 2 of 2 HCS12 Interrupt Read pseL7 PSEL6 PSEL5 PSEL4 PSEL3 PSEL2 PSEL Write Reserved 0 0 o j 0 0 0 29 MC9S12DJ64 Device User Guide V01 13 0028 002F BKP HCS12 Breakpoint Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0028 BKPCTO ae BKEN BKFULL BKTAG 9 0 0 0 0029 BKPCT1 BKOMBH BK1MBL BKORWE BKORW BK1RWE BK1RW 002A BKPOX a eee 5 4 BKOV2 BKOVO 002B 1984 gig 14 13 12 11 10 9 Bit 8 Write 002C 1889 gi 6 5 4 3 2 1 Bit 0 Write 002D BKP1X me BK1V5 BKiV4 1 BKiv2 BK1VO 002E BkPiH gitas 14 13 12 11 10 9 Bit 8 Write 002F Bkpip 162 6 4 3 2 1 Bit 0 Write 0030 0031 MMC map 4 of 4 HCS12 Module Mapping Control Address 0030 PPAGE _ PIX5 PIX4 PIX3 PIX2 PIX1 PIXO 0031 Reserved 0032 0033 MEBI map 3 of 3 HCS12 Multiplexed External Bus Interface Address Name icd We a5 Write Read 0034 003F CRG Clock and Reset Generator Address Name Bt7 Bite Bits Bits Bt2 Biti Bit 0 0034 SYN
6. 310 TIE TCIE RIE ILIE SCICR2 PED SPEDS Sel TIE TCIE RIE ILIE FFD2 FFD3 ATDO ATDCTL2 ASCIE FFDO FFD1 ATD1 ATDCTL2 ASCIE DO PIEJ l Bit PIEJ7 6 PIEJ1 PIEJO CE FFCC FFCD Port H I Bit PIEH PIEH7 0 CC M MOTOROLA 71 MC9S12DJ64 Device User Guide 01 13 FFCA FFCB 8 FFC9 Modulus Down Counter underflow Pulse Accumulator B Overflow MCCTL MCZI PBCTL PBOVI CA FFB6 FFB7 wake up 6 FFC7 CRG PLL lock CRGINT LOCKIE 4 FFC5 CRG Self Clock Mode CRGINT SCMIE FFC2 FFC3 BDLC DLCBCR IE FFCO FFC1 Bus IBCR IBIE FFBE FFBF Reserved Reserved FFBC FFBD FFBA FFBB EEPROM ECNFG CCIE CBEIE FFB8 FFB9 FLASH FCNFG CCIE CBEIE CANRIER WUPIE FFB4 FFB5 CANO errors CANRIER CSCIE OVRIE FFB2 FFB3 FFBO FFB1 CANO receive CANO transmit CANRIER RXFIE CANTIER TXEIE2 TXEIEO FFAE FFAF FFAC FFAD FFAA FFAB FFA8 FFA9 FFA6 FFA7 SFFA4 SFFAS FFA2 FFAO FFA1 SFFOE SFFOF FF9C FF9D FF9A FF9B 8 98 5 99 96 FF97 94 FF95 8 2 5 FF90 FF91 Port P FF8C FF8D PWM Emergency Shutdown I Bit FF80 to FF8B Reserved Reserved PIEP PIEP7 0 PWMSDN PWMIE 8C
7. neo we Sen Bec OE 62 2 4 1 VDDX VSSX Power 8 Ground Pins for VO Drivers 63 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator 63 2 4 3 VDD1 VDD2 551 VSS2 Internal Logic Power Supply Pins 63 2 4 4 VDDA VSSA Power Supply Pins for ATDO ATD1 and VREG 63 2 4 5 VRL Reference Voltage Input Pins 64 2 4 6 VDDPLL VSSPLL Power Supply Pins for _ 64 2 4 7 VREGEN On Chip Voltage Regulator Enable 64 Section 3 System Clock Description 1 OVENIEW rU ERR I 65 Section 4 Modes of Operation Dare CL EMULE dox ana 67 42 Chip Configuration Summary nasasa er Rte Eo eee en 67 2 3 Tue lcd ML tU pde Ard a DD Tee 68 4 3 1 Securing the Microcontroller 68 4 3 2 Operation of the Secured Microcontroller 68 4 3 3 Unsecuring the Microcontroller 69 4 4 Low Power Modes 69 4 4 1 x ded doe ipaa oe ce re ok oe S 69 4 4 2 ee ee BB ee 69 4 4 3 NV all ae Eee E 69 4 4 4
8. 62 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Mnemonic Description 112 pin Voltage VDDPLL 43 2 5V Provides operating voltage and ground for tne Phased Locked Loop This allows the supply voltage to the PLL to be VSSPLL 45 OV bypassed independenily Internal power and ground generated by internal regulator VREGEN 97 5 0V Internal Voltage Regulator enable disable 2 4 1 VDDX VSSX Power amp Ground Pins for I O Drivers External power and ground for 1 drivers Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded VDDX and VSSX are the supplies for Ports J K M P T and S 2 4 2 VDDR VSSR Power amp Ground Pins for I O Drivers amp for Internal Voltage Regulator External power and ground for I O drivers and input to the internal voltage regulator Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible Bypass requirements depend on how heavily the MCU pins are loaded VDDR and VSSR are the supplies for Ports A B E and H 2 4 3 VDD1 VDD2 VSS1 VSS2 Internal Logic Power Supply Pins Power is supplied to t
9. 67 Voltage Regulator VREGEN 68 Interrupt Vector Locations 4x ote east 71 Suggested External Component Values 78 Absolute Maximum 05 85 ESD Latch up Test 86 ESD and Latch Up Protection Characteristics 86 Operating ot iss Caged tthe DE LS EE nie 87 Thermal Package Characteristics 89 SV lO CharacterisllbS cd ideas owe C PR ee 90 Supply Current Characteristics 91 ATD Operating Characteristics 93 Electrical 94 ATD Conversion Performance 95 NVM Timing Characteristics net nie aea 98 NVM Reliability Characteristics des ae at ae 99 Voltage Regulator Recommended Load Capacitances 101 Startup Characteristics c coo erro tees 103 Oscillator Characteristics vasos aep Aca Maca D pr nine 104 esci oi euere 108 MSCAN Wake up Pulse Characteristics 109 SPI Master Mode Timing Characteristics
10. Background Debug Tag High and Mode Pin 54 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 55 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins ATD1 55 2 3 9 PADO7 ANO7 ETRIGO Port AD Input Pin of 55 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO 55 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port Pins 55 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port Pins 55 2 3 43 PE7 NOACG XGLKS Port E I O Pin 7 5 rore RR rm Re RR 55 2 3 14 PEO MODB IPIPE1 Port 57 23 15 PED ZMODA IPIPEO BPortE I PIT ceo ar 57 2 3 16 PE4 ECLK Port E I O Pin 4 vinee ERE a 57 2 3 17 PE3 LSTRB TAGLO Port 57 2 3 18 PE2 R W Port E VO Pin end ke ee 57 23 19 PEIFIRO PortElnput Pin sonnis er 57 2 3 20 0 57 M MOTOROLA 5 MC9S12DJ64 Device User Guide V01 13 2 3 21 2 3 22 2 3 23 2 3 24 2 3 25 2 3 26 2 3 27 2 3 28 2 3 29 2 3 30 2 3 31 2 3 32 2 3 33 2 3 34 2 3 35 2 3 36 2 3 37 2 3 38 2 3 39 2 3 40 2 3 41 2 3 42 2 3 43 2 3 44 2 3 45 2 3 46 2 3 47 2 3 48 2 3 49 2 3 50 2 3
11. TXB Port Pin 1 60 Port Pin 0 60 PP7 KWP7 7 1 1 7 60 PP6 KWP6 6 60 PP5 KWP5 5 1 1 5 60 KWP4 PWM4 Port P I O 4 60 PP3 KWP3 PWM3 1 61 PP2 2 2 1 2 61 PP1 KWP1 PWM1 Port P I O Pin 1 61 PPO KWPO PWMO Port P I O 0 61 577550 Pon sy Le er dar 61 SOKO PORS GO PIN ore s ser E eee ee E a 61 PS5 MOSIO Port S I O Pin 5 61 PS47MISOD Port S l O Pin 4 24 00 er IE Eee 61 Bing secs Siok bee ee eek ele an Dei 61 PS2 RXD1 Port 5 2 62 PS1 TXDO Port S VO Pin 1 62 MC9S12DJ64 Device User Guide V01 13 2 357 PS0 Port S VORN Qd e oit asc eer MESE SEU le 62 2358 7 0 1 7 0 Port T I O Pins 7 0 22 E Rute er dee 62 24 Power
12. 4 Junction Case LQFP112 11 5 T Junction to Package LQFP112 2 6 Thermal Resistance QFP 80 single sided Oo ES 2 internal planes Junction to Board QFP80 C W 9 T Junction to Case QFP80 14 C W 10 T Junction to Package Top QFP80 Wor zz 3 C W NOTES 1 The values for thermal resistance are achieved by package simulations 2 PC Board according to EIA JEDEC Standard 51 3 3 PC Board according to EIA JEDEC Standard 51 7 A 1 9 VO Characteristics This section describes the characteristics of all 5V I O pins All parameters are not always applicable e g not all pins feature pull up down resistances M MOTOROLA 89 MC9S12DJ64 Device User Guide V01 13 Table A 6 5V Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 P Input High Voltage 0 65 Vpps Vpps 0 3 V 2 Input Low Voltage VL Vsss 0 3 0 35 Vpps V 3 Input Hysteresis Input Leakage Current pins in high impedance input 4 mode Vin Vops or V i SS5 Output High Voltage pins in output mode 5 Drive 2mA Full Drive 10mA Output Low Voltage pins in output mode 6 p Drive 2mA Full Drive loj 10mA Internal Pull Up Device Current tested at Internal Pull Up D
13. TSTATE1 TSTATEO RXFIE 0146 CANOTFLG 0 2 0 0 TXE2 1 0147 CANOTIER TXEIE2 TXEIE1 TXEIEO 0148 ion 0 0 9 0 2 ABTRQO 0 0 0 0 ABTAK2 1 Write 014 CANOTBSEL iis 0 0 9 TX2 TX1 TXO 90148 no IDAM1 IDAMO ED Read 0 0 0 0 0 0 0 0 014C Reserved Write Read 0 0 0 0 0 0 0 0 014D Reserved Write Cue im RXERR7 RXERR6 RXERRS RXERR4 RXERR3 RXERR2 RXERR1 ie TXERR7 5 TXERR4 TXERR3 2 TXERR1 TXERRO 0150 CANOIDARO Read 0153 CANOIDAR3 Write 0154 CANOIDMRO Read 0157 CANOIDMR3 Write 0158 CANOIDAR4 Read 015B CANOIDAR7 Write 015C CANOIDMR4 Read 015F CANOIDMR7 Write AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 4 2 1 AMO AC7 AC6 AC5 AC4 AC3 AC2 AC1 ACO AM7 AM6 5 4 2 1 AMO 0160 Read FOREGROUND RECEIVE BUFFER see Table 1 2 016F Write D CANOTXFG e FOREGROUND TRANSMIT BUFFER see Table 1 2 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read 1028 ID27 ID26 ID25 ID24 ID23 ID22 ID21 0160 Standard ID
14. User Guide Document Order Number CPU12 Reference Manual 04 CPU12RM AD HCS12 Module Mapping Control MMC Block Guide 04 S12MMCV4 D HCS12 Multiplexed External Bus Interface MEBI Block Guide 03 S12MEBIV3 D HCS12 Interrupt INT Block Guide S12INTV1 D HCS12 Background Debug BDM Block Guide V04 S12BDMV4 D HCS12 Breakpoint Block Guide V01 S12BKPV1 D Clock and Reset Generator CRG Block User Guide 04 S12CRGV4 D Oscillator OSC Block User Guide V02 S120SCV2 D Enhanced Capture Timer 16 Bit 8 Channel ECT 16B8C Block User Guide S12ECT16B8CV1 D Analog to Digital Converter 10 Bit 8 Channel ATD_10B8C Block User Guide 02 S12ATD10B8CV2 D Inter IC Bus Block User Guide V02 S121ICV2 D Asynchronous Serial Interface SCI Block User Guide 02 S12SCIV2 D Serial Peripheral Interface Block User Guide V02 S12SPIV2 D Pulse Width Modulator 8 Bit 8 Channel PWM_8B8C Block User Guide 01 S12PWM8B8CV1 D 64K Byte Flash FTS64K Block User Guide 01 S12FTS64KV1 D 1K Byte EEPROM EETS1k Block User Guide 01 S12EETS1KV1 D Byte Level Data Link Controller J1850 BDLC Block User Guide S12BDLCV1 D Motorola Scalable CAN MSCAN Block User Guide V02 S12MSCANV2 D Voltage Regulator VREG Block User Guide 01 S12VREGV1 D S12PIM9DJ64V1 D M MOTOROLA N MC9S12DJ64 Device User Guide 01 13 18 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 1
15. 2 us 2 MSCAN Wake up dominant pulse pass twup 5 us M MOTOROLA 109 MC9S12DJ64 Device User Guide 01 13 110 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 7 SPI A 7 1 Master Mode Figure A 5 and Figure A 6 illustrate the master mode timing Timing values are shown in Table A 18 551 OUTPUT SCK CPOL 0 OUTPUT SCK CPOL 1 OUTPUT MISO INPUT MOSI OUTPUT MSB OUT2 BIT6 1 x LSB OUT x 1 If configured as output 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure 5 SPI Master Timing CPHA 0 111 M MOTOROLA MC9S12DJ64 Device User Guide 01 13 1 55 OUTPUT SCK 0 OUTPUT SCK CPOL 1 OUTPUT MISO 2 SE sme 3 10 MASTER MSB OUT MASTER LSB OUT PORT DATA 1 If configured as output OUTPUT PORT DATA 2 LSBF 0 For LSBF 1 bit order is LSB bit 1 bit 6 MSB Figure A 6 SPI Master Timing CPHA 1 Table A 18 SPI Master Mode Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted 200pF on all outputs Num C Rating en Min Typ Max Unit P Operating Frequency fous ERUIT Enable Lead Time lleag lsck Enable Lag Time Ec Data Setup Time Inputs Data Hold Time Inputs Data Valid after SCK Edge Data
16. 6 0 0 0 0 PTIT PTIJO Write 026A DDRJ DDRJ7 DDRJ7 0 0 0 0 DDRJ1 DDRJO 026B RDRJ iin RDRJ7 RDRJ6 0 0 0 0 RDRJO 026C PERJ PERJ7 PERJ6 0 9 D 0 PERJ1 PERJO 026D PPSJ ne PPSJ7 PPSJ6 9 PPSJ1 PPSJO 026E PIEJ ind PIEJ7 PIEJ6 0 2 0 PIEJO 026F PIFJ PIFJ7 PIFJ6 0 0 0 0 PIFJ1 0270 1686 9 0 0 0 0 0 0 0 027 Write 45 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 0280 Reserved Address Name eo eel 03FF write OSEE 46 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 1 6 Part ID Assignments The part ID is located in two 8 bit registers PARTIDH and PARTIDL addresses 001A and 001B after reset The read only value is a unique part ID for each revision of the chip Table 1 3 shows the assigned part ID number Table 1 3 Assigned Part ID Numbers Device Mask Set Number Part ID MC9S12DJ64 0L86D 0200 MC9S12DJ64 1L86D 0201 MC9S12DJ64 2L86D 02012 NOTES 1 The coding is as follows Bit 15 12 Major family identifier Bit 11 8 Minor family identifier Bit 7 4 Major mask set revision number including FAB transfers Bit 3 0 Minor non full mask set revision 2 11860 is identical 21860 except improved ESD performance 21860 The device memory sizes are located in
17. Reserved 5 3 Effects of Reset When a reset occurs MCU registers and control bits are changed to known start up states Refer to the respective module Block User Guides for register reset states 5 3 1 pins Refer to the HCS12 Multiplexed External Bus Interface MEBI Block Guide for mode dependent pin configuration of port A B E and K out of reset Refer to the PIM Block User Guide for reset configurations of all peripheral module ports 72 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 NOTE For devices assembled 80 QFP packages all non bonded out pins should be configured as outputs after reset in order to avoid current drawn from floating inputs Refer to Table 2 1 for affected pins 5 3 2 Memory Refer to Table 1 1 for locations of the memories depending on the operating mode after reset The RAM array is not automatically initialized out of reset M MOTOROLA 73 MC9S12DJ64 Device User Guide 01 13 74 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 6 HCS12 Core Block Description 6 1 CPU12 Block Description Consult the CPU12 Reference Manual for information on the CPU 6 2 HCS12 Module Mapping Control MMC Block Description Consult MMC Block Guide for information on the HCS12 Module Mapping Control module 6 3 HCS12 Multiplexed External Bus Interface MEBI Block Description Consult the MEBI Block Guide for information on HCS12 Multiplexed External Bus
18. The setup time can ignored for this operation 3 1 4 Mass Erase Erasing block takes 1 t 20000 _ INVMOP The setup time can be ignored for this operation A 3 1 5 Blank Check The time it takes to perform a blank check on the Flash or EEPROM is dependant on the location of the first non blank word starting at relative address zero It takes one bus cycle per word to verify plus a setup of the command teheck location 10 Table 11 Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted 1 DJ External Oscillator Clock wwos 08 50 MHz 2 D Bus frequency for Programming or Erase Operations maus 1 MHz 3 D Operating Frequency fNvMoP 150 200 kHz 4 Single Word Programming Time tswpgm 462 74 53 us 5 D Burst Programming consecutive word 4 towpgm 20 4 313 6 D Flash Burst Programming Time for 32 Words 4 6784 103553 ws 8 P Mass Erase Time tmass 1005 133 3 ms 9 D Blank Check Time Flash per block tcheck 118 32778 7 10 D Blank Check Time EEPROM per block tcheck 118 20587 NOTES 1 Restrictions for oscillator in crystal mode apply 2 Minimum Programming times are achieved under maximum NVM operating frequency fyymop and maximum bus frequency fous Maximum Erase and Programming times are achieved under particular combinations of
19. 0 0 2 PA2EN PAOEN 32 M MOTOROLA 0040 007F Address 0069 006A 006B 006C 006D 006E 006F 0070 0071 0072 0073 0074 0075 0076 0077 0078 0079 007A 007B 007C 007D 007E 007F M MOTOROLA Name DLYCT ICOVW ICSYS Reserved TIMTST Test Only Reserved Reserved PBCTL PBFLG 2 1 MCCNT hi lo TCOH hi TCOH lo hi lo TC2H hi TC2H lo TC3H hi TC3H lo Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide V01 13 ECT Enhanced Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 DLY1 NOVW7 NOVW6 NOVW5 NOVW3 NOVW2 NOVW1 NOVWO SH37 SH26 SH15 5 04 TFMOD BUFEN LATQ 0 0 0 0 0 0 0 PBEN 0 PBOVI 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0
20. 0107 0108 0109 010A 010B 010C 010F Name FCLKDIV FSEC Reserved FCNFG FPROT FSTAT FCMD Reserved FADDRHI FADDRLO FDATAHI FDATALO Reserved 0110 011B Address 0110 0111 0112 0113 0114 0115 M MOTOROLA Name ECLKDIV Reserved Reserved ECNFG EPROT ESTAT Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide V01 13 Reserved Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0 0 0 0 0 0 0 0 Flash Control Register fts64k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FDIVLD PRDIV8 FDIV5 FDIV4 FDIV3 FDIV2 FDIV1 FDIVO KEYEN NV6 NV5 NVA NV3 NV2 SEC1 SECO 0 0 0 0 0 0 0 0 CBEIE CCIE KEYACC 9 9 NV6 FPHDIS 51 50 FPLDIS 51 FPLSO pvioL 0 BLANK 9 9 CMDB6 5 CMDB2 9 CMDBO 0 0 0 0 0 0 0 0 Bit14 Bit14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 1
21. IPIPEO Port E I O Pin 5 PES is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODA bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPEO This pin is an input with a pull down device which is only active when RESET is low 2 3 16 4 ECLK Port E I O Pin 4 PE4 is a general purpose input or output pin It can be configured to drive the internal bus clock ECLK ECLK can be used as a timing reference 2 3 17 LSTRB TAGLO Port E I O Pin PE3 is a general purpose input or output pin In MCU expanded modes of operation LSTRB can be used for the low byte strobe function to indicate the type of bus access and when instruction tagging is on TAGLO is used to tag the low half of the instruction word being read into the instruction queue 2 3 18 R W Port E I O Pin 2 PE2 is a general purpose input or output pin In MCU expanded modes of operations this pin drives the read write output signal for the external bus It indicates the direction of data on the external bus 2 3 19 PE1 IRQ Port E Input Pin 1 PE is a general purpose input pin and maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 20 PEO XIRQ Port E Input Pin 0 PEO is a general p
22. and bus frequency fp Refer to formulae in Sections A 3 1 1 A 3 1 4 for guidance 4 Burst Programming operations are not applicable to EEPROM 5 Minimum Erase times are achieved under maximum NVM operating frequency fyymop 6 Minimum time if first word in the array is not blank 7 Maximum time to complete check on an erased block 98 MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 3 2 NVM Reliability The reliability of the NVM blocks is guaranteed by stress test during qualification constant process monitors and burn in to screen early life failures The failure rates for data retention and program erase cycling are specified at the operating conditions noted The program erase cycle count on the sector is incremented every time a sector or mass erase event 15 executed Table A 12 NVM Reliability Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Data Retention at an average junction temperature of moe 2 Flash number of Program Erase cycles EEPROM number of Program Erase cycles 40 C T 0 i 7 C EEPROM number of Program Erase cycles 100 000 Cycl 0 C Ty lt 140 C Lil M MOTOROLA 99 MC9S12DJ64 Device User Guide 01 13 100 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 4 Voltage Regulator The on chip voltage regulator is intended to supply the internal logic and oscillator circuits
23. ee N ER ER 70 Section 5 Resets and Interrupts 5 1 quc Eee 71 525 ER 71 5 2 1 Vector 225 225 ee ee dy 71 222 Effects t uos ee er ET 72 5 3 1 DING TC 72 5 3 2 a DN ha eos tes ee 73 Section 6 HCS12 Core Block Description M MOTOROLA 7 MC9S12DJ64 Device User Guide V01 13 61 GPUT2 Block Description Fa RE na 75 6 2 512 Module Mapping Control MMC Block Description 75 6 3 HCS12Multiplexed External Bus Interface MEBI Block Description 75 6 4 HCS12 Interrupt INT Block Description 75 6 5 HCS12 Background Debug Block Description 75 6 5 1 Deviee speeilie information ste ete ra be E 75 6 6 512 Breakpoint Block Description 73 Section 7 Clock and Reset Generator CRG Block Description 7 1 75 Section 8 Oscillator OSC Block Description 8 1 Device specific 76 Section 9 Enhanced Capture Timer ECT Block Description
24. 112 SPI Slave Mode Timing Characteristics 114 Expanded Bus Timing 117 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Derivative Differences and Document References Derivative Differences Table 0 1 shows the availability of peripheral modules on the various derivatives For details about the compatibility within the MC9S12D Family refer also to engineering bulletin EB386 Table 0 1 Derivative Differences Generic device MC9S12DJ64 MC9S12D64 MC9S12A64 CANO 1 1 0 J1850 BDLC 1 0 0 Packages 112LQFP 80QFP 112LQFP 80QFP 112LQFP 80QFP Mask Set L86D L86D L86D Temp Options Package Codes PV FU PV FU PV FU Note MC9S12 DJ64 C FU 7 An errata exists contact Sales office Package Option Temperature Option Device Title Controller Family An errata exists contact Sales office An errata exists contact Sales office Temperature Options 40 C to 85 C V 40 C to 105 C 40 C to 125 C Package Options FU 800 112LQFP Figure 0 1 Order Partnumber Example The following items should be considered when using a derivative M MOTOROLA Registers Interrupts Ports Do not write or read registers after reset address range 50140 017F if using a derivative without CANO see Table 0 1 Do not write or read
25. Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 33 MC9S12DJ64 Device User Guide V01 13 0080 5009 ATDO Analog to Digital Converter 10 Bit 8 Channel 0080 ATDOCTLO ER RD RE D Write ns Write 0082 ATDOCTL2 c ADPU ETRIGP ETRIG ASC Read 0 0083 ATDOCTL3 u S8C S4C S2C SIC FIFO FRZi FRZO 0084 4 ae SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 PRSO Read 0 0085 ATDOCTLS DJM DSGN SCAN MULT 4 CB CA 0086 ATDOSTATO OHR Read 0 o o o o o o 807 U 5 wu S TDOTESTO od Write 008 ATDOTEST4 Write O Read 0 0 0 0 0 0 0 0 v wi 50088 lead CCP6 OCP5 CCF4 CCF3 CCP2 COFI CCFO Write Read 0 0 0 0 0 0 0 0 008 Reserved Wie 5m 008D ATDODIEN 1880 6 5 4 3 2 1 Bit 0 Mie iu irm Ja 1273237 Read 0 0 0 0 0 0 0 0
26. CWAI COPWAI AUTO PRE PCE SCME RTR6 RTR5 RTR4 RTR3 RTR2 RTR1 RTRO 0 0 0 WCOP RSBCK CR2 CR1 CRO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 ECT Enhanced Capture Timer 16 Bit 8 Channels Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 1057 1056 1055 054 1053 1082 lost 1050 0 0 0 0 0 0 0 0 7 6 4 2 1 OC7M7 OC7M6 7 5 7 OC7M3 OC7M2 7 1 OC7MO OC7D7 OC7D6 OC7D5 OC7D3 OC7D1 Bit 15 14 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 TEN TSWAI TSFRZ TFFCA TOV7 Tove 5 TOV4 TOV3 TOVO OM7 OL7 OM6 OL6 OMS OL5 OM4 OL4 OM3 OL3 OL2 OM1 OL1 OMO OLO EDG7B EDG7A EDG6B EDG6A EDG5B EDG5A EDG4B EDG4A EDG3B EDG3A EDG2B EDG2A EDG1B EDG1A EDGOB C5l cal C2l Col TOI TCRE PR2 PR1 PRO C7F C6F C5F C4F C3F C2F 0 0 0 0 0 0 0 31 MC9S12DJ64 Device User Guide 01 13 0040 007F ECT Enhanced Capture Timer 16 Bit 8 Channels Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read 0050 TCO hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read i 0051 T
27. MOTOROLA 107 MC9S12DJ64 Device User Guide 01 13 This is very important to notice with respect to timers serial modules where a pre scaler will eliminate the effect of the jitter to a large extent Table A 16 PLL Characteristics Conditions are shown in Table A 4 unless otherwise noted 2 VCO locking range fvco 8 50 3 Lock Detector transition from Acquisition to Tracking rel 3 4 mode Lock Detection 1 5 p Lock Detector transition from Tracking to Acquisition unt mode PLLON Total Stabilization delay Auto Mode tstab PLLON Acquisition mode stabilization delay lacq PLLON Tracking mode stabilization delay tal fn Fitting parameter VCO loop frequency Charge pump current acquisition mode lich 38 5 Charge pump current tracking mode ien 3 5 EXIIT 15 Jitter fit parameter 22 la NOTES 1 deviation from target frequency 2 fosc 4MHz fgus 25MHz equivalent fyco 50MHz REFDV 03 SYNR 018 Cs 4 7nF Cp 470pF Rs 10KQ 108 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 6 MSCAN Table 17 MSCAN Wake up Pulse Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 P MSCAN Wake up dominant pulse filtered
28. Mappable to any 2K Boundary 1K mapped two times in the 2K address space 4K Bytes RAM Mappable to any 4K Boundary 16K Fixed Flash Page 3E 62 This is dependant on the state of the ROMHM bit 16K Page Window 4 x 16K Flash EEPROM pages 16K Fixed Flash Page 3F 63 XI FFFUU if active 222 440192 27 MC9S12DJ64 Device User Guide V01 13 1 5 1 Detailed Register Map 0000 5000 map 1 of 3 512 Multiplexed External Bus Interface Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0000 PORTA 16930 gi 6 5 4 3 2 1 Bit 0 Write 0001 porta 1984 6 5 4 3 2 1 Bit 0 Write 0002 DDRA 1930 6 5 4 3 2 1 Bit 0 Write 0003 popa 1984 6 5 4 3 2 1 Bit 0 Write Read 0 0 0 0 0 0 0 0 0004 Reserved Read 0 0 0 0 0 0 0 0 0005 Reserved m C Read 0 0 0 0 0 0 0 0 0006 Reserved m M Mn Read 0 0 0 0 0 0 0 0 0007 Reserved 50008 ponte Pead 6 5 4 3 REGES o Write 0009 DDRE 1684 gy 6 5 4 3 Bio Write 000 PEAR iin 0 ppoe LSTRE Rowe 10 D 000B MODE iind MODB MODA LO 0 emk 000C PUCR es m PC PE PUPAE 000D RDRIV di HDPK Rope h2 O RDPB RDPA 000E le dad EST Write Read 0 0 0 0 0 0
29. No external DC load is allowed Table A 13 Voltage Regulator Recommended Load Capacitances Rating Symbol Min Typ Max Unit Load Capacitance on VDD1 2 Civpp 220 nF Load Capacitance on VDDPLL CLVDDfePLL 220 nF M MOTOROLA 101 MC9S12DJ64 Device User Guide 01 13 102 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 5 Reset Oscillator and PLL This section summarizes the electrical characteristics of the various startup scenarios for Oscillator and Phase Locked Loop PLL A 5 1 Startup Table A 14 summarizes several startup characteristics explained in this section Detailed description of the startup behavior can be found in the Clock and Reset Generator CRG Block User Guide Table A 14 Startup Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating release level T POR assert level 0 97 GT Startup from Reset Nosc 5 Interrupt pulse width IRQ edge sensitive mode 20 ns 6 Wait recovery startup time 14 A 5 1 1 POR The release level and the assert level are derived from the Vpp Supply They are also valid if the device is powered externally After releasing the POR reset the oscillator and the clock quality check are started If after a time valid oscillation is detected MCU will start using the internal self clock The fastest startup time
30. Number Date Date Author Description of Changes 16 NOV 19 NOV V01 00 2001 2001 Initial version based on MC9SDP256 2 09 Version In table 5V Characteristics of the electrical characteristics V01 01 18 FEB 18 FEB replaced tPULSE with tpign and tpval in lines Port Interrupt Input 2002 2002 Pulse filtered and Port Interrupt Input Pulse passed respectively 6 MAR 6 MAR V01 03 2 ug Tune V01 04 a voios 20 July 30 July 2002 2002 Table Oscillator Characterisitcs removed Oscillator start up time from POR or STOP row Table 5V I O Characteristics Updated Partial Drive 2mA and Full Drive 10mA Table Operating Characteristics Distinguish Irgrfor 1 and 2 ATD blocks on Table Electrical Characteristics Update to 22 pF Table Operating Conditions Changed Vpp and to 2 35 V min Removed Document number except from Cover Sheet Updated Table Document References Table 5V Characteristics Corrected Input Capacitance to Section Device Pinout 112 pin and 80 pin added in diagrams RXCANO to PJ6 and TXCANO to PJ7 Table PLL Characteristics Updated parameters and f Figure Basic PII functional diagram Inserted XFC pin in diagram Enhanced section XFC Component Selection Added to Sections ATD ECT and PWM freeze mode active BDM mode Added 1L86D to Table Assigned Part ID numb
31. be clipped Table A 8 ATD Operating Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating Symbol Min Typ Max Unit Reference Potential 1 Low Vssa VppA 2 V High 2 2 Differential Reference Voltage Vay VAL 4 50 5 00 5 25 V 3 ATD Clock Frequency ATDCLK 0 5 2 0 MHz ATD 10 Bit Conversion Period 4 D Clock Cycles 10 14 28 Cycles Conv Time at 2 0MHz ATD Clock fATDCLK 0 7 14 us ATD 8 Bit Conversion Period 5 Clock Cycles Conv Time at 2 0MHz Clock 6 D Recovery Time 5 0 Volts 7 Reference Supply current 2 blocks on 8 P Reference Supply current 1 ATD block on NOTES 1 Full accuracy is not guaranteed when differential voltage is less than 4 50V 2 The minimum time assumes a final sample period of 2 ATD clocks cycles while the maximum time assumes a final sample period of 16 ATD clocks A 2 2 Factors influencing accuracy Three factors source resistance source capacitance and current injection have an influence on the accuracy of the ATD A 2 2 1 Source Resistance Due to the input pin leakage current as specified in Table A 6 in conjunction with the source resistance there will be a voltage drop from the signal source to the ATD input The maximum source resistance Rs M MOTOROLA 93 MC9S12DJ64 Device U
32. 0 0 000F Reserved Write un En 0010 0014 MMC map 1 of 4 HCS12 Module Mapping Control Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0010 INITRM ies 15 RAM14 1 RAM12 11 0 19 RAMHAL 0011 INITRG a REG14 REG12 LO 9 0 0012 INITEE EE15 4 cers 2 O0 EEON 0013 MISC e EXSTR1 EXSTRO ROMHM ROMON Read 0 0 0 0 0 0 0 0 0014 Reserved 28 M MOTOROLA 0015 0016 Address Name 0015 ITCR 0016 ITEST 0017 0019 Address Name 0017 0019 Reserved 001A 001B Address Name 001A PARTIDH 001B PARTIDL 001C 001D Address Name 001C MEMSIZO 001D MEMSIZ1 001E 001E Address Name 001E INTCR 001F 001F Address Name 001F HPRIO 0020 0027 Address Name 0020 0027 Reserved M MOTOROLA MC9S12DJ64 Device User Guide V01 13 INT map 1 of 2 HCS12 Interrupt WRINT ADR3 ADR2 ADR1 ADRO Read 1015 1014 1013 02 1011 iio 19 xum aes Er ESOS MEUS Write reg 0 __ eep_swi swol 0 sw2 ram 54 0 rom 0 0 0 540 SS
33. 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 35 MC9S12DJ64 Device User Guide 01 13 00A0 00C7 PWM Pulse Width Modulator 8 Bit 8 Channel Address Name Bt7 Bit6 Bt5 Bit4 Bits 2 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 _ 0 0 0 0 0 0 0 0 Read Bit7 6 5 4 3 2 1 Bit 0 99989 70 0 0 0 0 0 0 0 0084 PWMPERo 10 6 5 4 3 2 1 Bit 0 Write 0085 1 1922 6 5 4 3 2 1 Bit 0 Write 50086 PWMPER2 19324 6 5 4 3 2 1 Bit 0 Write 0087 10 6 5 4 3 2 1 Bit 0 Write 0088 4 1932 pi 6 5 4 3 2 1 Bit 0 Write 0089 PWMPERs 1932 6 5 4 3 2 1 Bit 0 Write 00BA PwMPERe 1932 6 5 4 3 2 1 Bit 0 Write 00BB 7 1932 pi 6 5 4 3 2 1 Bit 0 Write 00BC 19 6 5 4 3 2 1 Bit 0 Write 00BD 19 6 5 4 3 2 1 Bit 0 Write 00BE 2 189 6 5 4 3 2 1 Bit 0 Write 00BF PWMDTY3 1932 6 5 4 3 2 1 Bit 0 Write gooco PWMDTY4 1984 6 5 4 3 2 1 Bit 0 Write 5001 PWMDTYvs 1932 pi 6 5 4 3
34. 2 1 Bit 0 Write 0062 PwMDTYve 19 6 5 4 3 2 1 Bit 0 Write 0003 PWMDTY7 198 pi 6 5 4 3 2 1 Bit 0 Write Read PWM7IN 0004 PWMSDN bs PWMIF PWMIE pmuRstat PWMLVL PWM7INL PWM7ENA Read 0 0 0 0 0 0 0 0 00 5 Reserved Write PE Read 0 0 0 0 0 0 0 0 00 6 Reserved Write el Read 0 0 0 0 0 0 0 0 00 7 Reserved Write ige 36 M MOTOROLA 00C8 00CF Address 00C8 00C9 00CA 00CB 00CC 00CD 00CE 00CF Name SCIOBDH SCIOBDL SCIOCR1 SCIOCR2 SCIOSR1 SCIOSR2 SCIODRH SCIODRL 00D0 00D7 Address 00D0 00D1 00D2 00D3 00D4 00D5 00D6 00D7 Name SCI1BDH SCHBDL SCHCR2 SCHSR1 SCHSR2 SCHDRH SCHDRL 00D8 00DF Address 00D8 00D9 00DA 00DB M MOTOROLA Name SPIOCR1 SPIOCR2 SPIOBR SPIOSR Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write SCIO Asynchronous Serial Interface Bit 7 0 SBR7 LOOPS TIE TDRE R8 R7 T7 SCI1 Asynchronous Serial Interface Bit 7 0 SBR7 LOOPS TIE TDRE R8 R7 T7 Bit 6 0 SBR6 SCISWAI TCIE TC 0 T8 R6 T6 B
35. Controller BDLC SAEJ1850 Class B Data Communications Network Interface Compatible and ISO Compatible for Low Speed 125 Kbps Serial Data Communications in Automotive Applications Inter IC Bus IIC Compatible with I2C Bus standard Multi master operation Software programmable for one of 256 different serial clock frequencies 112 Pin LQFP or 80 QFP package M MOTOROLA 1 3 MC9S12DJ64 Device User Guide V01 13 VO lines with 5V input and drive capability 5V A D converter inputs Operation at SOMHz equivalent to 25MHz Bus Speed Development support Single wire background debug mode BDM On chip hardware breakpoints Modes of Operation User modes Normal and Emulation Operating Modes Normal Single Chip Mode Normal Expanded Wide Mode Normal Expanded Narrow Mode Emulation Expanded Wide Mode Emulation Expanded Narrow Mode Special Operating Modes Special Single Chip Mode with active Background Debug Mode Special Test Mode Motorola use only Special Peripheral Mode Motorola use only Low power modes Stop Mode Pseudo Stop Mode Wait Mode M MOTOROLA 21 MC9S12DJ64 Device User Guide V01 13 1 4 Block Diagram Figure 1 1 shows a block diagram of the MC9S12DJ64 device 22 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Figure 1 1 MC9S12DJ64 Block Diagram 64K Byte Flash EEPROM 4 Byte RAM 1K Byte EEPROM Voltage Regulator Single wire Background Debug Modu
36. ETRIGP ETRIG ASCIE Head 0 ssc sac 326 sic Write Read Write SRES8 SMP1 SMPO PRS4 PRS3 PRS2 PRS1 Head psen SCAN MULT E cc CB Write Read SCF 0 ETORF FIFOR 0 CC2 1 Write Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write Read CCF7 CCF6 CCF5 4 CCF2 CCF1 Write Read 0 0 0 0 0 0 0 Write ASCIF FRZO PRSO CA CCO SC M MOTOROLA 0120 013F Address 012D 012E 012F 0130 0131 0132 0133 0134 0135 0136 0137 0138 0139 013A 013B 013C 013D 013E 013F Name ATD1DIEN Reserved PORTAD1 ATD1DROH ATD1DROL ATD1DR1H ATD1DR1L ATD1DR2H ATD1DR2L ATD1DR3H ATD1DRSL ATD1DR4H ATD1DR4L ATD1DR5H ATD1DR5L ATD1DR6H ATD1DR6L ATD1DR7H ATD1DR7L 0140 017F Address 0140 0141 0142 0143 M MOTOROLA Name CANOCTLO CANOCTL1 CANOBTRO 1 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide V01 13 ATD1 Analog to Digital Co
37. Interface module 6 4 HCS12 Interrupt INT Block Description Consult the INT Block Guide for information on the HCS12 Interrupt module 6 5 HCS12 Background Debug BDM Block Description Consult the BDM Block Guide for information on the HCS12 Background Debug module 6 5 1 Device specific information When the BDM Block Guide refers to alternate clock this is equivalent to Oscillator Clock 6 6 HCS12 Breakpoint BKP Block Description Consult the BKP Block Guide for information on the HCS12 Breakpoint module Section 7 Clock and Reset Generator CRG Block Description Consult the CRG Block User Guide for information about the Clock and Reset Generator module 7 1 Device specific information The Low Voltage Reset feature of the CRG is not available on this device M MOTOROLA 75 MC9S12DJ64 Device User Guide V01 13 Section 8 Oscillator OSC Block Description Consult the OSC Block User Guide for information about the Oscillator module 8 1 Device specific information The XCLKS input signal is active low see 2 3 13 PE7 NOACC XCLKS Port E I O Pin 7 Section 9 Enhanced Capture Timer ECT Block Description Consult the ECT 16B8C Block User Guide for information about the Enhanced Capture Timer module When the ECT 16B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode Section 10 Analog to Digital Converter ATD Block Description There are two Analog to Digital Converter
38. Interrupt PWM Channel 4 PP3 KWP3 PWM3 Port P I O Interrupt PWM Channel 3 PP2 KWP2 PWM2 E Port P I O Interrupt PWM Channel 2 PP1 KWP1 PWM1 Port P I O Interrupt PWM Channel 1 PPO KWPO PWMO Port P I O Interrupt PWM Channel 0 PS7 sso Port S 1 0 SS of SPIO PS6 SCKO Port S I O of SPIO PS5 MOSIO Port S I O MOSI of SPIO 54 MISOO PERS U Port S I O MISO of SPIO PS3 TXD1 PPSS P Port 8 TXD of SCH PS2 RXD1 Port S RXD of SCI1 PS1 TXDO Port S I O TXD of SCIO PSO RXDO Port S RXD of SCIO PT 7 0 IOC 7 0 Disabled Port T I O Timer channels NOTES 1 Refer to PEAR register description in HCS12 Multiplexed External Bus Interface MEBI Block Guide M MOTOROLA 53 MC9S12DJ64 Device User Guide V01 13 2 3 Detailed Signal Descriptions 2 3 1 EXTAL XTAL Oscillator Pins EXTAL XTAL are the crystal driver and external clock pins On reset all the device clocks are derived from the EXTAL input frequency XTAL is the crystal output 2 3 2 RESET External Reset Pin An active low bidirectional control signal it acts as an input to initialize the MCU to a known start up state and an output when an internal MCU function causes a reset 2 3 3 TEST Test Pin This input only pin is reserved for test NOTE The TEST pin must be tied to VSS in all applications 2 3 4 VREGEN Voltage Regulator Enable Pin This input only pin enables or disables th
39. Introduction 1 1 Overview The MC9S12DJ64 microcontroller unit MCU is a 16 bit device composed of standard on chip peripherals including a 16 bit central processing unit HCS12 CPU 64K bytes of Flash EEPROM 4K bytes of RAM bytes of EEPROM two asynchronous serial communications interfaces SCI one serial peripheral interfaces SPD an 8 channel IC OC enhanced capture timer two 8 channel 10 bit analog to digital converters ADC an 8 channel pulse width modulator PWM a digital Byte Data Link Controller BDLC 29 discrete digital I O channels Port A Port B Port K and Port E 20 discrete digital VO lines with interrupt and wakeup capability a CAN 2 0 A B software compatible modules MSCAN12 and an Inter IC Bus The 95 120164 has full 16 bit data paths throughout However the external bus can operate in an 8 bit narrow mode so single 8 bit wide memory can be interfaced for lower cost systems The inclusion of a PLL circuit allows power consumption and performance to be adjusted to suit operational requirements 1 2 Features e HCS12 Core 16 bit HCS12 CPU i Upward compatible with M68HC11 instruction set ii Interrupt stacking and programmer s model identical to M68HC11 iii Instruction queue iv Enhanced indexed addressing MEBI Multiplexed External Bus Interface MMC Module Mapping Control INT Interrupt control Breakpoints BDM Background Debug Mode e CRG low curre
40. K Port K pull up resistors are enabled out of reset i e Bit 7 PUKE in the register PUCR at Base 000C Therefor care must be taken not to clear this bit Port M 7 6 PM7 6 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs Port P6 PP6 must be configured as output or its pull resistor must be enabled to avoid a floating input Port S 7 4 PS7 4 must be configured as outputs or their pull resistors must be enabled to avoid floating inputs PAD 15 8 ATD1 channels Out of reset the ATD1 is disabled preventing current flows in the pins Do not modify the ATD1 registers Document References The Device User Guide provides information about the MC9S12DJ64 device made up of standard HCS 12 blocks and the HCS12 processor core This document is part of the customer documentation A complete set of device manuals also includes all the individual Block Guides of the implemented modules In a effort to reduce redundancy all module specific information is located only in the respective Block Guide If applicable special implementation details of the module are given in the block description sections of this document See Table 0 2 for names and versions of the referenced documents throughout the Device User Guide 16 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Table 0 2 Document References Port Integration Module 9DJ64 Block User Guide 01
41. Read ID10 ID9 ID8 ID7 ID6 ID5 ID4 ID3 CANORIDRO Write Extended ID 1020 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 0161 Standard ID Read ID2 ID1 IDO RTR IDE 0 CANORIDR1 Write Extended ID 1014 ID13 ID12 ID11 ID10 ID9 ID8 ID7 0162 Standard ID Read CANORIDR2 Write 42 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Extended ID Read ID6 ID5 ID4 ID3 ID2 ID1 IDO RTR 0163 Standard ID Read CANORIDR3 Write 0164 CANORDSRO Read DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 016B CANORDSR7 Write 016C CANORDLR Read DLC3 DLC2 DLC1 DLCO Write Read 016D Reserved Write 016E CANORTSRH dn TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 016F CANORTSRL Read TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Write Extended ID Read CANOTIDRO Write ID28 ID27 ID26 ID25 ID24 ID23 ID22 ID21 voire Standard ID Read 1010 ID9 ID8 ID7 ID6 ID5 04 103 Write Extended ID Read Write ID20 ID19 ID18 SRR 1 IDE 1 ID17 ID16 ID15 apiril Standard ID Read RE ID2 ID1 IDO RTR IDE 0 Write Extended ID Read a CANOTIDR2 Write ID14 ID13 ID12 ID11 ID10 ID9 ID8 ID7 Standard ID Read Write Extended ID Read CANOTIDR3 Write ID6 ID5 ID4 ID3 ID2 ID
42. Reference V 8 EXTAL XTAL inputs 3 0 V 9 TEST input VTEST 10 0 V am hs NC a m 12 a AN 13 Storage Temperature Range Ta 65 155 C NOTES 1 Beyond absolute maximum ratings device might be damaged 2 The device contains an internal voltage regulator to generate the logic and PLL supply out of the supply The absolute maximum ratings apply when the device is powered from an external source 3 All digital I O pins are internally clamped to Vssx and Vppx and Vppr Or Vssa and Vppa 4 Those pins are internally clamped to Vssp and 5 This is clamped low to but not clamped high This pin must be tied low in applications M MOTOROLA 85 MC9S12DJ64 Device User Guide 01 13 A 1 6 ESD Protection and Latch up Immunity All ESD testing is in conformity with CDF AEC Q100 Stress test qualification for Automotive Grade Integrated Circuits During the device qualification ESD stresses were performed for the Human Body Model HBM the Machine Model MM and the Charge Device Model A device will be defined as a failure if after exposure to ESD pulses the device no longer meets the device specification Complete DC parametric and functional testing is performed per the applicable device specification at room temperature followed by hot temperature unless specified otherwise in the device
43. WAIT mode 2 3 28 PHO KWHO Port H I O Pin 0 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 29 PJ7 KWJ7 TXCANO PORT J I O Pin 7 PJ7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the serial clock pin SCL of the IIC module It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO 58 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 2 3 30 PJ6 KWJ6 SDA PORT J I O Pin 6 PJ6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as the serial data pin SDA of the IIC module It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO 2 3 31 PJ 1 0 KWJ 1 0 Port J Pins 1 0 and PJO are general purpose input or output pins They can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 32 PK7 ECS ROMCTL Port K I O Pin 7 PK7 is a general purpose input or output pin During MCU expanded modes of operation this pin is used as the emulation chip select output ECS During MCU expanded modes of operation this pin is used to enabl
44. possible is given by nyposc A 5 1 2 SRAM Data Retention Provided an appropriate external reset signal is applied to the MCU preventing the CPU from executing code when VDDS is out of specification limits the SRAM contents integrity is guaranteed if after the reset the PORF bit in the CRG Flags Register has not been set A 5 1 3 External Reset When external reset is asserted for a time greater than the CRG module generates an internal reset and the CPU starts fetching the reset vector without doing a clock quality check if there was an oscillation before reset A 5 1 4 Stop Recovery Out of STOP the controller can be woken up by an external interrupt A clock quality check as after POR is performed before releasing the clocks to the system M MOTOROLA 103 MC9S12DJ64 Device User Guide V01 13 A 5 1 5 Pseudo Stop and Wait Recovery The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in both modes The controller can be woken up by internal or external interrupts After twrs the CPU starts fetching the interrupt vector A 5 2 Oscillator The device features an internal Colpitts and Pierce oscillator The selection of Colpitts oscillator or Pierce oscillator external clock depends on the XCLKS signal which is sampled during reset By asserting the XCLKS input during reset this oscillator can be bypassed allowing the input of a square wave Before asserting the osci
45. 1 IDO RTR Standard ID Read Write 0174 CANOTDSRO Read 017B CANOTDSR7 Write DB7 DB6 DB5 DB4 DB3 DB2 DB1 DBO 017C CANOTDLR i DLC3 017D CANOTTBPR dim PRIO7 PRIO6 PRIO5 PRIO4 PRIO3 PRIO2 PRIO1 PRIOO 017E CANOTTSRH dos TSR15 TSR14 TSR13 TSR12 TSR11 TSR10 TSR9 TSR8 017F CANOTTSRL Read TSR7 TSR6 TSR5 TSR4 TSR3 TSR2 TSR1 TSRO Write 0180 023F Reserved Address Su CNN _0 o o o o o o o 023F M MOTOROLA 43 MC9S12DJ64 Device User Guide V01 13 0240 027F PIM Port Integration Module Address Name Bis 0240 PTT ium 7 6 4 1 PTTO ion Pur Read PTIT7 PTIT6 Prits PTIT4 Prits PTIT2 Prim PTITO Write 0242 DDRT e DDRT7 DDRT7 DDRT5 DDRT4 DDRT3 DDRT2 DDRT1 DDRTO 0243 RDRT v RDRT7 RDRT6 RDRT5 RDRT4 RDRT3 RDRT2 RDRTO 0244 PERT es PERT7 PERT6 PERT5 PERT4 PERT2 PERTO 0245 PPST d PPST7 PPST6 5 5 ppsta PPST3 5 2 PPST1 PPSTO Read 0 0 0 0 0 0 0 0 0246 Reserved 4 45 RE Read 0 0 0 0 0 0 0 0 0247 Reserved E 0248 PTS oO PTS7 56 PTS5 54 PTS3 52 1 50 UN Read PTIS7 Prise Priss PTIS4 PTISS PTIS2 PTIST PTISO Write 024 DDRS e D
46. 1 PB1 ADDR2 DATA2 PB2 ADDR3 DATA3 PB3 ADDR4 DATA4 PB4 9 ADDRBS DATAS PB5 2 ADDR6 DATA6 PB6 30 ADDR7 DATA7 PB7 31 KWH7 PH7 132 KWH6 PH6 33 KWH5 PH5 134 KWH4 PH4 135 XCLKS NOACC PE7 36 MODB IPIPE1 PE6 137 Figure 2 1 50 MODN IPIPEO PES 38 quaque eur a eet ig ECLK PE4 139 96 1 57 580 99 3 PJ6 KWJ6 SDA RXCANO 951 PS6 SCK0 98 3 PJ7 KWJ7 SCL TXCANO 97 94 PS5 MOSIO 93 PS4 MISOO 92 3 PSS TXD1 91 5 PS2 RXD1 90 I PS1 TXDO 89 2 PSO RXDO VRH VDDA PAD15 AN15 ETRIG1 PADO7 ANO7 ETRIGO PAD14 AN14 PADO6 ANO6 PAD13 AN13 05 5 12 12 PADO4 AN04 PAD11 AN11 PADOS ANOS PAD10 AN10 PADO2 AN02 9 9 PADO1 ANO1 08 PADOO ANOO VSS2 VDD2 PA7 ADDR15 DATA15 PA6 ADDR14 DATA14 PAS ADDR13 DATA13 PA4 ADDR12 DATA12 PAS ADDR11 DATA11 PA2 ADDR10 DATA10 PA1 ADDR9 DATA9 MC9S12DJ64 112LQFP 7144 VDDR 441 RESET 42 VDDPLL 7143 VSSPLL 045 EXTAL 17146 XTAL 147 TEST 48 KWH3 PH3 49 VSSR 6140 RWIPE2 C 54 1 1 55 XIRQ PEO 156 KWHO PHO 52 KWH2 PH2 50 KWH1 PH1 151 LSTRB TAGLO PE3 53 Signals shown in Bold are not available on the 80 Pin Package Pin Assignments 112 pin LOFP for MC9S12DJ64 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 PJ7IKWJ7 SCL
47. 10 11 104 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 5 3 Phase Locked Loop The oscillator provides the reference clock for the PLL The PLL s Voltage Controlled Oscillator VCO is also the system clock source in self clock mode A 5 3 1 XFC Component Selection This section describes the selection of the XFC components to achieve a good filter characteristics VDDPLL Phase VCO Toce 1 fref refdv 1 Detector femp Loop Divider Figure A 2 Basic PLL functional diagram The following procedure can be used to calculate the resistance and capacitance values using typical values for f and iy from Table A 16 The grey boxes show the calculation for 50MHz and fief IMHz E g these frequencies are used for fosc 4MHz and a 25 bus clock The VCO Gain at the desired VCO frequency is approximated by 60 50 100 7 9 90 48MHz V The phase detector relationship is given by icn 316 7Hz Q ich 15 the current in tracking mode M MOTOROLA 105 MC9S12DJ64 Device User Guide V01 13 The loop bandwidth should be chosen to fulfill the Gardner s stability criteria by at least a factor of 10 typical values are 50 G 0 9 ensures a good transient response That 1 fref 10 le x 0 9 n ga dt 6 fc lt 25 2 And finally the frequency relationship is def
48. 4 13 12 11 10 9 Bit 8 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 EEPROM Control Register eets1k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EDIVLD PRDIV8 EDIV5 EDIV4 EDIV3 EDIV2 EDIV1 EDIVO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 CBEIE CCIE 0 0 N 0 EPOPEN bii EPDIS EP2 EP1 EPO pvioL 0 BLANK 0 0 39 MC9S12DJ64 Device User Guide V01 13 0110 011B Address Name 0116 ECMD Reserved for 90117 Factory Test 0118 EADDRHI 0119 EADDRLO 011A EDATAHI 011B EDATALO 011C 011F Address Name 011C 011F Reserved 0120 013F Address Name 0120 ATD1CTLO 0121 ATD1CTL1 0122 ATD1CTL2 0123 ATD1CTL3 0124 ATD1CTL4 0125 ATD1CTL5 0126 ATD1STATO 0127 Reserved 0128 ATD1TESTO 0129 ATD1TEST1 012A Reserved 012B ATD1STAT1 012C Reserved 40 EEPROM Control Register eets1k Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 oi 0 CMDB6 5 0 CMDB2 CMDBO Read 0 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write PILE Read 6 5 4 3 2 1 Bit 0 14 13 12 11 10 9 Bit 8 Write Read dae Biz 6 5 4 3 2 1 Bit 0 Reserved for RAM Control Register ATD1 Analog to Digital Converter 10 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Read 0 0 0 0 0 0 0 Write Read 0 0 0 0 0 0 0 Write Read Write ADPU ETRIGLE
49. 49 KWPO PWMO Port P I O Pin 0 PPO is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 0 output 2 3 50 PS7 550 Port S I O Pin 7 PS6 is a general purpose input or output pin It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 51 PS6 5 Port S Pin 6 PS6 is a general purpose input or output pin It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 52 PS5 MOSIO Port S I O Pin 5 PS5 is a general purpose input or output pin It can be configured as master output during master mode or slave input pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 53 PS4 500 Port S I O Pin 4 PS4 is a general purpose input or output pin It can be configured as master input during master mode or slave output pin during slave mode MOSI of the Serial Peripheral Interface 0 SPIO 2 3 54 PS3 TXD1 Port S I O Pin PS3 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 1 SCI M MOTOROLA 61 MC9S12DJ64 Device User Guide V01 13 2 3 55 PS2 RXD1 Port S I O Pin 2 PS2 is a general purpose input or output pin It can be configured as the receive pin RXD of Serial Com
50. 5 2 5 2 75 V PLL Supply Voltage VDDPLL 2 35 25 2 75 V Voltage Difference VDDX to VDDR and VDDA ANDDX 0 1 0 0 1 V Voltage Difference VSSX to VSSR and VSSA Avssx 0 1 0 0 1 V Oscillator fosc 0 5 16 MHz Bus Frequency fbus 0 252 25 MHz MC9S12DJ64C Operating Junction Temperature Range 40 100 C Operating Ambient Temperature Range 3 Ta 40 27 85 C MC9S12DJ64V Operating Junction Temperature Range 40 120 C Operating Ambient Temperature Range 3 Ta 40 27 105 C MC9S12DJ64M Operating Junction Temperature Range 40 140 C Operating Ambient Temperature Range 3 Ta 40 27 125 C NOTES 1 The device contains an internal voltage regulator to generate the logic and PLL supply out of the I O supply The given operating range applies when this regulator is disabled and the device is powered from an external source 2 Some blocks e g ATD conversion and NVMs program erase require higher bus frequencies for proper oper ation 3 Please refer to Section A 1 8 Power Dissipation and Thermal Characteristics for more details about the rela tion between ambient temperature T4 and device junction temperature A 1 8 Power Dissipation and Thermal Characteristics Power dissipation and thermal characteristics are closely related The user must assure that the maximum operating junction temperature 15 not exceeded The average chip junction temperature in C can be obtained from Tat py O
51. 51 2 3 52 2 3 53 2 3 54 2 3 55 2 3 56 PH7 KWH Y RI nes 57 BHO KWH6 Por 58 PHS KWH5 Port H I O Pin 5 58 PH4 Port H I O Pin us aao ee a a E PR 58 PH3 KWH3 Port H 58 PH2 KWH2 Port 2 58 PH1 KWH1 Port H I O PIA ee 58 PHO KWHO Port H 0 58 PJ7 KWJ7 SCL 7 58 KWJ6 SDA PORT J I O Pin6 59 PJ 1 0 KWJ 1 0 Port J I O Pins 1 0 59 PK7 ECS ROMCTL Port 1 7 59 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 59 PM7 Po M Beet ne de ar nd 59 PORN PING ar a ea ern 59 5 SCK0 Port M 5 59 MOSIO Port 4 59 550 Port 60 2 MISOO Port M I O Pin 2 60 PM1
52. BDLC registers after reset address range 00E8 00 if using a derivative without BDLC see Table 0 1 Fill the four CANO interrupt vectors SFFBO FFB7 according to your coding policies for unused interrupts if using a derivative without CANO see Table 0 1 Fill the BDLC interrupt vector SFFC2 FFC3 according to your coding policies for unused interrupts if using a derivative without BDLC see Table 0 1 15 MC9S12DJ64 Device User Guide 01 13 The CANO pin functionality TXCANO RXCANO is not available on port PJ7 PJ6 5 PM3 2 and if using a derivative without CANO see Table 0 1 The BDLC pin functionality TXB is not available on port and if using a derivative without BDLC see Table 0 1 Do not write MODRRI and MODRRO Bit of Module Routing Register PIM 9DJ64 Block User Guide if using a derivative without CANO see Table 0 1 Pins not available in 80 pin QFP package Port H In order to avoid floating nodes the ports should be either configured as outputs by setting the data direction register DDRH at Base 0262 to FF or enabling the pull resistors by writing a FF to the pull enable register PERH at Base 0264 Port J 1 0 Port J pull up resistors are enabled out of reset on all four pins 7 6 and 1 0 Therefore care must be taken not to disable the pull enables on PJ 1 0 by clearing the bits and PERJO at Base 026C Port
53. Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Read PTIP7 6 PTIPT PTIPO Write 025A DDRP e DDRP7 DDRP7 DDRP5 DDRP4 DDRP3 DDRP2 DDRP1 DDRPO 025B RDRP ien RDRP7 RDRP6 RDRP5 RDRP4 RDRP3 RDRP2 RDRPO 025C PERP s 7 PERP6 5 PERP4 PERP2 1 PERPO 025D PPSP 5 7 PPSP6 PPSP5 5 4 PPSP3 5 2 PPSP1 550 Read 025E PIEP Wie 6 5 4 2 PIEP1 Read 025F PIFP Wrte 7 PIFP6 5 PIFP4 PIFP2 PIFP1 Read 0260 PTH Wrte PTH6 PTHS PTH4 PTH2 PTHO iu a Read PTIH7 PTIHG PTIHS PTIH4 PTIH2 PTIHO Write 0262 DDRH e DDRH7 DDRH7 DDRH5 DDRH4 DDRH3 DDRH2 DDRH1 0263 RDRH RDRH7 RDRH6 RDRH5 RDRH3 RDRH2 RDRH1 0264 PERH ii PERH7 PERH6 PERH5 PERH4 PERH3 PERH2 PERHO 0265 PPSH ne PPSH7 PPSH6 PPSH5 5 4 PPSH3 PPSH2 PPSH1 PPSHO Read 0266 PIEH Wrte 6 PIEHS PIEH4 2 Read 0267 PIFH 6 0268 PTJ PTJ6 9 0 0 0 PTJ1 PTJO Write SES an Read
54. CO lo Write Bit 7 6 5 4 3 2 1 Bit 0 0052 TC1 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read 0053 TC1 lo Write Bit 7 6 5 4 3 2 1 Bit 0 Read 0054 TC2 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read 0055 TC2 lo Write Bit 7 6 5 4 3 2 1 Bit 0 0056 TC3 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read i 0057 TC3 lo Write Bit 7 6 5 4 3 2 1 Bit 0 Read 0058 TCA hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read i 0059 TCA lo Write Bit 7 6 5 4 3 2 1 Bit 0 Read 005A TC5 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read i 005B TC5 lo Write Bit 7 6 5 4 3 2 1 Bit 0 005C 6 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read 0050 6 lo Write Bit 7 6 5 4 3 2 1 Bit 0 005E TC7 hi Write Bit 15 14 13 12 11 10 9 Bit 8 Read i 005F TC7 lo Write Bit 7 6 5 4 3 2 1 Bit 0 Read 0 0060 PACTL Write PAEN PAMOD PEDGE CLK1 CLKO PAOVI PAI 0061 5886 20 0 0 PAOVF PAIF Write 1 0062 PACNG hi Write Bit 7 6 5 4 3 2 1 Bit 0 Read i 0063 PACNe lo Write Bit 7 6 5 4 3 2 1 Bit 0 Read 0064 PACN1 hi Write Bit 7 6 5 4 3 2 1 Bit 0 Read 0065 PACNO lo Write Bit 7 6 5 4 3 2 1 Bit 0 0066 1984 Mezi RDMCL 0 0 MCEN MCPRO Write ICLAT FLMC 0067 MCFLG Read MCZF 0 0 0 POLF3 POLF2 POLF1 POLFO Write 0068 ICPAR
55. DOCUMENT NUMBER 9512DJ64DGV1 D MC9S12DJ64 Device User Guide V01 13 Covers also 9512064 9512 64 Original Release Date 19 Nov 2001 Revised 20 May 2003 Motorola Inc Motorola reserves the right to make changes without further notice to any products herein to improve reliability function or design Motorola does not assume any liability arising out of the application or use of any product or circuit described herein neither does it convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where personal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries affiliates and distributors harmless against all claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part M MOTOROLA Revision History Version Revision Effective
56. DRS7 DDRS7 DDRS5 DDRS4 DDRS3 DDRS2 DDRS1 DDRSO 024B RDRS vt RDRS7 RDRS6 RDRS5 RDRS4 RDRS3 RDRS2 RDRS1 RDRSO 024C PERS ines PERS7 PERS6 55 PERS4 PERS3 PERS2 PERS1 PERSO 024D PPSS e PPSS7 PPSS6 555 PPSS4 PPSS3 PPSS2 551 PPSSO 024E WOMS 1 WOMS7 WOMS6 womss WOMS4 WOMS3 woMs2 woMS1 WOMSO Read 0 0 0 0 0 0 0 0 024F Reserved 0250 PTM Bum 7 prme 5 4 PTM3 PTM2 1 PTMO T Read PTIM7 Prime PTIMS Prima PTIM2 PTIMT PTIMO Write 0252 DDRM e DDRM7 DDRM7 DDRM5 DDRM4 DDRM3 DDRM2 DDRM1 DDRMO 0253 RDRM bia RDRM7 RDRM6 RDRM5 RDRM4 RDRM3 RDRM2 RDRM1 RDRMO 0254 PERM 2 7 6 PERM5 4 PERM3 PERM2 0255 5 5 7 PPSM6 5 5 PPSM4 PPSM3 5 2 PPSM1 5 0256 WOMM 1 WOMM7 WOMM6 WOMMS WOMM4 WOMM3 WOMM2 1 WOMMO 0257 MODRR 0 0 0 MODRRO Read 0258 PTP7 6 5 PTP4 PTP2 44 M MOTOROLA 0240 027F PIM Port Integration Module MC9S12DJ64 Device User Guide V01 13 Address Bit 7 Bit 6
57. ED 90 SEATING PLANE NOTES MILLIMETERS DIMENSIONING AND TOLERANCING PER ANSI Y14 5M 1982 DIM MIN MAX 2 CONTROLLING DIMENSION MILLIMETER A 1390 14 10 3 DATUM PLANE H IS LOCATED AT BOTTOM OF B 1390 14 10 LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC C 215 245 BODY AT THE BOTTOM OF THE PARTING LINE D 022 038 4 DATUMS A B D TO BE E 2 00 240 DETERMINED AT DATUM PLANE H JE IE 5 DIMENSIONS 5 AND V TO BE DETERMINED 8 DATUM 6 DIMENSIONS A AND 8 DO NOT INCLUDE E H 0 25 PLANE CHT MOLD PROTRUSION ALLOWABLE J 013 023 PROTRUSION IS 0 25 PER SIDE DIMENSIONS A AND DO INCLUDE MOLD MISMATCH 065 09 AND ARE DETERMINED AT DATUM PLANE H L 12 35 REF 7 DIMENSION D DOES NOT INCLUDE DAMBAR M 5 109 PROTRUSION ALLOWABLE DAMBAR N 17 PROTRUSION SHALL 0 08 TOTAL IN 0 13 0 EXCESS OF THE D DIMENSION AT MAXIMUM P 0 325 BSC Q MATERIAL CONDITION DAMBAR CANNOT oo 79 LOCATED ON THE LOWER RADIUS OR R 013 030 THE FOOT S 1695 1745 T 0 18 DETAIL C Wl sl 1695 1745 W 035 045 X 1 6 REF Figure B 2 80 pin QFP Mechanical Dimensions case no 841B M MOTOROLA 121 MC9S12DJ64 Device User Guide 01 13 122 44 MOTOROLA User Guide End Sheet M MOTOROLA MC9S12D
58. Hold Time Outputs Rise Time Inputs and Outputs Fall Time Inputs and Outputs NOTES 1 The numbers 7 8 in the column labeled are missing This has been done on purpose to consistent between the Master and the Slave timing shown in Table A 19 112 MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 7 2 Slave Mode Figure 7 and Figure A 8 illustrate the slave mode timing Timing values are shown in Table A 19 SS INPUT SCK CPOL 0 INPUT SCK CPOL 1 INPUT gt 9 OUTPUT MSB OUT DEN X SLAVE LSB OUT INPUT MSB IN TEN LSB IN Figure 7 SPI Slave Timing CPHA 0 55 INPUT N N D gt 3 2 2 gt gt ja 1 SCK CPOL 0 INPUT _ SCK 4 1 gt gt lt 2 CPOL 1 INPUT 9 010 gt 8 C 7 HC MOSI Figure A 8 SPI Slave Timing CPHA 1 M MOTOROLA 113 MC9S12DJ64 Device User Guide 01 13 Table 19 SPI Slave Mode Timing Characteristics Conditions are shown in Table A 4 unless otherwise noted CLOAD 200pF on all outputs Smboi Wm Me ie Period tgck 1 fop 2048 tous 2 Enable Lead Time 3 Enable Lag Time teyc 4 Clock SCK High or
59. Hz GT Pulse width E low 4 Pulse width E high 5 Address delay time 6 Address valid time to E rise PWg 7 Muxed address hold time Address hold to data valid 1 10 Read data setup time 11 Read data hold time 12 Write data delay time 14 Write data setup time PWeH tppw ipsw 15 Address access time e m Non multiplexed address delay time Non muxed address valid to E rise PWg tNAp Non multiplexed address hold time Chip select delay time Chip select access time teye tesp tosr Chip select hold time Read write hold time Low strobe delay time Low strobe valid time to E rise PWg sp Low strobe hold time D valid time to E rise tNov ns M MOTOROLA 117 MC9S12DJ64 Device User Guide V01 13 Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table 4 unless otherwise noted 50pF Num C Rating Symbol Min Typ Max Unit IPIPO 1 0 valid time to E rise PWg tpop IPIPO 1 0 delay time PWg tp vy IPIPO 1 0 valid time to E fall NOTES 1 Affected by clock stretch add N x t where N 0 1 2 or 3 depending on the number of clock stretches 118 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Appendix B Package Information B 1 General This section p
60. J64 Device User Guide V01 13 123 MC9S12DJ64 Device User Guide 01 13 FINAL PAGE OF 124 PAGES 124 M MOTOROLA
61. Low Time twsck 5 Data Setup Time Inputs Data Hold Time Inputs III CU Pe Slave MISO Disable Time ldis Data Valid after SCK Edge ty 25 ns 10 Data Hold Time Outputs tho ns D Rise Time Inputs and Outputs t 25 ns 12 Time Inputs and Outputs tf 25 ns 114 M MOTOROLA MC9S12DJ64 Device User Guide 01 13 8 External Bus Timing A timing diagram of the external multiplexed bus is illustrated in Figure A 9 with the actual timing values shown on table Table A 20 All major bus signals are included in the diagram While both a data write and data read cycle are shown only one or the other would occur on a particular bus cycle A 8 1 General Muxed Bus Timing The expanded bus timings are highly dependent on the load conditions The timing parameters shown assume a balanced load across all outputs M MOTOROLA 115 MC9S12DJ64 Device User Guide 01 13 1 2 gt 3 lt 4 ECLK PE4 Addr Data read PA PB Addr Data write PA PB Non Multiplexed Addresses PK5 0 ECS PK7 R W PE2 Figure A 9 General External Bus Timing 116 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Table A 20 Expanded Bus Timing Characteristics Conditions are shown in Table 4 unless otherwise noted 50pF Rating Symbol Min Typ Max Unit P Frequency of operation E clock fo 0 25 0 M
62. R M SYN5 SYN4 SYN3 SYN2 SYN SYNO 0035 REFDV e REFDV3 REFDV2 REFDV1 REFDVO CTFLG Read 0 0 0 0 0 0 0 0 800386 TEST ONLY Write 0037 CRGFLG 4 TIRAGES eo Mp 0038 CRGINT drin 30 M MOTOROLA 0034 Address 0039 003A 003B 003C 003D 003E 003F 0040 Address 0040 0041 0042 0043 0044 0045 0046 0047 0048 0049 004A 004B 004C 004D 004E 004F M MOTOROLA 003F Name CLKSEL RTICTL COPCTL FORBYP TEST ONLY CTCTL TEST ONLY ARMCOP 007F Name TIOS CFORC OC7M OC7D TCNT hi TCNT lo TSCR1 TTOV TCTL1 TCTL2 TCTL3 TCTLA TIE TSCR2 TFLG1 TFLG2 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write MC9S12DJ64 Device User Guide V01 13 CRG Clock and Reset Generator Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLLSEL PSTP SYSWAI ROAWAI
63. Section 10 Analog to Digital Converter ATD Block Description Section 11 Inter IC Bus Block Description Section 12 Serial Communications Interface SCI Block Description Section 13 Serial Peripheral Interface SPI Block Description Section 14 J1850 BDLC Block Description Section 15 Pulse Width Modulator PWM Block Description Section 16 Flash EEPROM 64K Block Description Section 17 EEPROM 1K Block Description Section 18 RAM Block Description Section 19 MSCAN Block Description Section 20 Port Integration Module PIM Block Description 8 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 21 Voltage Regulator VREG Block Description Section 22 Printed Circuit Board Layout Proposals Appendix A Electrical Characteristics u Da 83 A 1 1 Parameter Classification x ben u mac bak pad ees 83 A 1 2 POWER bx RE 83 A 1 3 E RERUM 84 A 1 4 G rrent Jie colt test eier een 84 A 1 5 Absolute Maximum Ratings cq ae sre rr Moose asie gs 85 A 1 6 ESD Protection and Latch up 86 A 1 7 Operating Conditions oh Seek a ce ah eost END LU ee 86 A 1 8 Power Dissipation and Thermal Characteristics 87 A 1 9 LO OharaeteliS GS d er ne 89 Supply CUM GNIS ise botte quoi SD Ep EL ette
64. TXCANO VREGEN PS3 TXD1 PS2 RXD1 PJ6 KWJ6 SDA RXCANO PS1 TXDO PP7 KWP7 PWM7 PMO RXCANO RXB PM1 TXCANO TXB PM2 RXCANO MISOO 0 550 PM4 RXCANO MOSIO PM5 TXCANO SCKO VDDX VSSX st aa X LO aa zz lt lt LO aa PSO RXDO VSSA VRL PWM3 KWP3 PP3 1 VRH PWM2 KWP2 PP2 2 VDDA PWM1 KWP1 PP1 3 PADO7 ANO7 ETRIGO PWMO KWPO PPO 4 PADO6 ANO6 IOCO PTO 5 PADO5 AN05 IOC1 PT1 6 04 4 2 2 y PADO3 AN03 IOC3 PT3 8 PADO2 AN02 VDD1 PADO1 ANO1 VSS1 MC9S12DJ64 PADOO ANOO 80 VSS2 5 VDD2 IOC6 PT6 PA7 ADDR15 DATA15 IOC7 PT7 PA6 ADDR14 DATA14 MODC TAGHI BKGD PA5 ADDR13 DATA13 ADDRO DATAO PBO PA4 ADDR12 DATA12 ADDR1 DATA1 PB1 PA3 ADDR11 DATA11 ADDR2 DATA2 PB2 PA2 ADDR10 DATA10 ADDR3 DATA3 PB3 PA1 ADDR9 DATA9 ADDR4 DATA4 PB4 PAO ADDR8 DATA8 L D XO lt X 1 e o es 285 5299 ca X X EAA cc co lt lt lt 5 Figure 2 2 Pin Assignments in 80 pin QFP for MC9S12DJ64 2 2 Signal Properties Summary Table 2 1 summarizes the pin functionality Signals shown in bold are not available in the 80 pin package M MOTOROLA 51 MC9S12DJ64 Device User Guide 01 13 Table 2 1 Signal Properties
65. WMSCNTA Test Only PWMSCNTB Test Only PWMCNTO PWMCNT1 PWMCNT2 PWMCNT3 Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write Read Write ATDO Analog to Digital Converter 10 Bit 8 Channel MC9S12DJ64 Device User Guide V01 13 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 PWM Pulse Width Modulator 8 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PWME7 PWME6 5 PWME4 PWME3 PWME2 PWME1 PWMEO PPOL7 PPOL6 PPOL5 PPOL4 PPOL3 PPOL2 PPOL1 PPOLO PCLK7 PCLK6 PCLK5 PCLK4 PCLK3 PCLK2 PCLK1 PCLKO PCKB2 PCKB1 PCKBO PCKA2 PCKA1 PCKAO CAE7 CAE6 5 CAE4 2 1 CAEO CON67 CON45 CON23 PSWAI PFRZ 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0
66. an que ne we Rowe e BA 121 MOTOROLA MC9S12DJ64 Device User Guide V01 13 List of Figures Figure 0 1 Figure 1 1 Figure 1 2 Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 3 1 Figure 22 1 Figure 22 2 Figure 22 3 Figure 22 4 Figure A 1 Figure A 2 Figure A 3 Figure A 4 Figure A 5 Figure A 6 Figure A 7 Figure A 8 Figure A 9 Figure B 1 Figure B 2 M MOTOROLA Order Partnumber 15 MC9S12DJ64 Block Diagram 23 MC9S12DJ64 Memory out of Reset 27 Pin Assignments 112 pin LQFP for MC9S12DJ64 50 Pin Assignments 80 QFP for MC9S12DJ64 51 PLL Loop Filter 54 Colpitts Oscillator Connections 7 1 56 Pierce Oscillator Connections 7 0 56 External Glock Connections 56 Glock Connections e s derenn n ee E per tor ee 65 Recommended PCB Layout 112L Colpitts 79 Recommended PCB Layout for 80QFP Colpitts 80 Recommended PCB Layout for 112LQFP Pierce Oscillator 81 Recommended PCB Layout for 80QFP Pierce Oscillator 82 ATD A
67. analog input ANO of the analog to digital converter ATDO It can act as an external trigger input for the ATDO 2 3 10 PAD 06 00 AN 06 00 Port AD Input Pins of ATDO PADO6 PADOO are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDO 2 3 11 PA 7 0 ADDR 15 8 DATA 15 8 Port A I O Pins 7 are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 12 PB 7 0 ADDR 7 0 DATA 7 0 Port I O Pins PB7 PBO are general purpose input or output pins In MCU expanded modes of operation these pins are used for the multiplexed external address and data bus 2 3 13 XCLKS Port E I O Pin 7 PE7 is a general purpose input or output pin During MCU expanded modes of operation the NOACC signal when enabled is used to indicate that the current bus cycle is an unused or free cycle This signal will assert when the CPU is not using the bus The XCLKS is an input signal which controls whether a crystal in combination with the internal Colpitts low power oscillator is used or whether Pierce oscillator external clock circuitry is used The state of this pin is latched at the rising edge of RESET If the input is a logic low the EXTAL pin is configured for an external clock drive or a Pierce Oscillator If input is a logic high a Colpitts oscillator circuit is conf
68. ble A 4 unless otherwise noted Rating Symbol Min Typ Max Unit 1 input Source Resistance Rs 1 Total Input Capacitance 2 Sampling Sampling 3 Disruptive Analog Input Current 4 Coupling Ratio positive current injection 5 Coupling Ratio negative current injection 94 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 2 3 ATD accuracy Table A 10 specifies the ATD conversion performance excluding any errors due to current injection input capacitance and source resistance Table A 10 ATD Conversion Performance Conditions are shown in Table A 4 unless otherwise noted Vay 5 12V Resulting to one 8 bit count 20mV and one 10 bit count 5mV fATDCLK 2 0MHz Mum c L D L D Ws e P 2 10 Bit Differential Nonlinearity 3 P 10 Bit Integral Nonlinearity 4 10 Absolute Error 5 8 Resolution SB NL INL AE SB NL INL AE Counts Counts Counts mV 5 3 PemDmeema riw Tom 5 L7 permenon m 395 Tome 8 1 5 8 Absolute Error 1 5 1 0 Counts NOTES 1 These values include the quantization error which is inherently 1 2 count for any A D converter ELI NETS EUX 1 2 0 For the following definitions see also Figure 1 Differential Non Lineari
69. ccuracy Definitions 96 Basic PLL functional diagram 105 Jitter DEIANIONS s ee ee 107 Maximum bus clock jitter approximation 107 SPI Master Timing 0 111 MC PAST irati ent etch RAUS ee 112 SPI Slave Timing CPHA 0 113 SPI Slave Timing CPHA 1 113 General External Bus 116 112 pin LQFP mechanical dimensions case 987 120 80 pin QFP Mechanical Dimensions case no 841 121 11 MC9S12DJ64 Device User Guide 01 13 12 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 List of Tables Table 0 1 Derivative Differences 15 Table 0 2 Document 17 Table 1 1 Device Memory issus teehee din 25 0000 000F MEBI map 1 of 3 HCS12 Multiplexed External Bus Interface 28 0010 0014 MMC map 1 of 4 HCS12 Module Mapping Control 28 0015 0016 INT map 1 of 2 HCS12 Interrupt 29 SOU 00019 29 001A 001B Device ID Register Table 1 3
70. ce O SCIO 8 0000 0007 Serial Communications Interface 0 5 8 00D8 00DF Serial Peripheral Interface SPIO 8 00E0 00E7 Inter IC Bus 8 00E8 00EF Byte Data Link Controller BDLC 8 00F0 00FF Reserved 16 0100 010F Control Register 16 0110 011B EEPROM Control Register 12 011C 011F Reserved 4 0120 013F Analog to Digital Converter 10 bit 8 channels ATD1 32 0140 017F Motorola Scalable Can CANO 64 0180 023F Reserved 192 0240 027F Port Integration Module PIM 64 0280 Reserved 384 0000 07FF 2 1k Array mapped twice the 2048 0000 array 4096 4000 Sector at start 8000 BFFF Flash EEPROM Page Window 16384 25 MC9S12DJ64 Device User Guide V01 13 Table 1 1 Device Memory Map Size Address Module Bytes Fixed Flash EEPROM array C000 FFFF incl 0 5K 1K 2K Protected Sector at end and 256 bytes of Vector Space at FF80 FFFF 26 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Figure 1 2 MC9S12DJ64 Memory Map out of Reset 0000 0400 0800 1000 EXTERN 4000 8000 C000 SFFOO ne VECTORS FFFF EXPANDED NORMAL SINGLE CHIP M MOTOROLA RRS IR m 2024 SPECIAL SINGLE CHIP XX x 2222 gt lt de REGISTERS Mappable to any 2K Boundary within the first 32K 1K Bytes EEPROM
71. ced references to HCS12 Core Guide by the individual HCS12 Block guides Table Signal Properties corrected pull resistor reset state for PE7 and PE4 PE2 Table Absolute Maximum Ratings corrected footnote on clamp of TEST pin MC9S12DJ64 Device User Guide 01 13 4 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Table of Contents Section 1 Introduction MEC 11 sr PET 19 1 2 2 Featlifes ass ed ene IPSI ee ee oh E ui eee See ee 19 1 3 Mod s of Operation uri e 21 TA Block Diagramm saa eters botas ez CREE MR P 22 15 Device Memory 25 1 5 1 Detailed Register 28 1 6 Part ID Assignments ee er Oe E ERO REA IE E ee esq 47 Section 2 Signal Description 2 1 Device PIDE ibis uu o a en E a a 49 22 SignalPropenles omina satt erteilen ae 51 2 3 Detailed Signal 54 2 3 1 EXTAL XT AL Oscillator Pins o rase eoe de en 54 2 3 2 RESET External Reset 54 2 3 3 at aaa teen 54 2 3 4 VREGEN Voltage Regulator Enable 54 2 3 5 Loop Filter Pin sure a TEES nel 54 2 3 6 BKGD TAGHI
72. controlling whether the internal Flash is visible in the memory ROMON 1 mean the Flash is visible in the memory map The state of the ROMCTL pin is latched into the ROMON bit in the MISC register on the rising edge of the reset signal Table 4 1 Mode Selection BKGD PE6 5 PK7 ROMON MODB MODA Bit Mode Description Special Single Chip BDM allowed and ACTIVE BDM is 0 0 0 x 1 allowed in all other modes but a serial command is required to make BDM active 0 1 0 0 1 1 7 Emulation Expanded Narrow allowed 0 1 0 X 0 Special Test Expanded Wide BDM allowed 0 1 0 1 1 1 0 Emulation Expanded Wide BDM allowed 1 0 0 x 1 Normal Single Chip BDM allowed 0 0 1 0 1 3 3 Normal Expanded Narrow BDM allowed Peripheral BDM allowed but bus operations would cause 1 1 0 x 1 bus conflicts must be used 0 0 1 1 1 1 1 Normal Expanded Wide BDM allowed For further explanation on the modes refer to the HCS12 Multiplexed External Bus Interface Block Guide Table 4 2 Clock Selection Based on 7 PE7 XCLKS Description 1 Colpitts Oscillator selected M MOTOROLA 67 MC9S12DJ64 Device User Guide 01 13 Table 4 2 Clock Selection Based on 7 PE7 XCLKS Description 0 Pierce Oscillator external clock selected Table 4 3 Voltage Regulator VREGEN VREGEN Description 1 Internal Voltage Regulator enabled Internal Voltage R
73. e on chip voltage regulator 2 3 5 XFC PLL Loop Filter Pin PLL loop filter Please ask your Motorola representative for the interactive application note to compute PLL loop filter elements Any current leakage on this pin must be avoided XFC R T MCU nnt VDDPLL VDDPLL Figure 2 3 PLL Loop Filter Connections 2 3 6 BKGD TAGHI Background Debug Tag High and Mode Pin The BKGD TAGHI MODC pin is used as a pseudo open drain pin for the background debug communication In MCU expanded modes of operation when instruction tagging is on an input low on this pin during the falling edge of E clock tags the high half of the instruction word being read into the 54 MOTOROLA MC9S12DJ64 Device User Guide V01 13 instruction queue It is used as aMCU operating mode select pin during reset The state of this pin is latched to the MODC bit at the rising edge of RESET This pin has a permanently enabled pull up device 2 3 7 PAD15 AN15 ETRIG1 Port AD Input Pin of ATD1 15 is a general purpose input pin and analog input AN7 of the analog to digital converter ATD1 It can act as an external trigger input for the ATDI 2 3 8 PAD 14 08 AN 14 08 Port AD Input Pins ATD1 PAD14 PADOS are general purpose input pins and analog inputs AN 6 0 of the analog to digital converter ATDI 2 3 9 07 ETRIGO Port AD Input Pin of PADO7 is a general purpose input pin and
74. e the Flash EEPROM memory in the memory map ROMCTL At the rising edge of RESET the state of this pin is latched to the ROMON bit For a complete list of modes refer to 4 2 Chip Configuration Summary 2 3 33 PK 5 0 XADDR 19 14 Port K I O Pins 5 0 5 are general purpose input or output pins In MCU expanded modes of operation these pins provide the expanded address XADDR 19 14 for the external bus 2 3 34 PM7 Port M I O Pin 7 PM7 is a general purpose input or output pin 2 3 35 PM6 Port M I O Pin 6 PM6 is a general purpose input or output pin 2 3 36 PM5 5 Port M I O Pin 5 PMS is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the serial clock pin SCK of the Serial Peripheral Interface 0 SPIO 2 3 37 4 RXCANO MOSIO Port M I O Pin 4 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the master output during master mode or slave input pin during slave mode MOSI for the Serial Peripheral Interface 0 SPIO M MOTOROLA 59 MC9S12DJ64 Device User Guide V01 13 2 3 38 SSO Port M I O Pin PM3 is a general purpose input or output pin It can be configured as the tran
75. ear the same as if the part was not secured with the exception of BDM operation The BDM operation will be blocked 68 MOTOROLA MC9S12DJ64 Device User Guide V01 13 4 3 2 2 Executing from External Memory The user may wish to execute from external space with a secured microcontroller This is accomplished by resetting directly into expanded mode The internal FLASH and EEPROM will be disabled BDM operations will be blocked 4 3 3 Unsecuring the Microcontroller In order to unsecure the microcontroller the internal FLASH and EEPROM must be erased This can be done through an external program in expanded mode or via a sequence of BDM commands Unsecuring is also possible via the Backdoor Key Access Refer to Flash Block Guide for details Once the user has erased the FLASH and EEPROM the part can be reset into special single chip mode This invokes a program that verifies the erasure of the internal FLASH and EEPROM Once this program completes the user can erase and program the FLASH security bits to the unsecured state This is generally done through the BDM but the user could also change to expanded mode by writing the mode bits through the BDM and jumping to an external program again through BDM commands Note that if the part goes through a reset before the security bits are reprogrammed to the unsecure state the part will be secured again 4 4 Low Power Modes The microcontroller features three main low power modes Con
76. ected by anti parallel diodes for ESD protection NOTE In the following context VDDS is used for either VDDA VDDX VSS5 is used for either VSSA VSSR and VSSX unless otherwise noted IDDS denotes the sum of the currents flowing into VDDX and pins VDD is used for VDDI VDD2 and VDDPLL VSS is used for VSS1 VSS2 VSSPLL IDD is used for the sum of the currents flowing into VDDI and VDD2 A 1 3 Pins There are four groups of functional pins A 1 3 1 5V VO pins Those I O pins have a nominal level of 5V This class of pins is comprised of all port I O pins the analog inputs BKGD and the RESET pins The internal structure of all those pins is identical however some of the functionality may be disabled E g for the analog inputs the output drivers pull up and pull down resistors are disabled permanently A 1 3 2 Analog Reference This group is made up by the VRH and VRL pins A 1 3 3 Oscillator The pins XFC EXTAL XTAL dedicated to the oscillator have a nominal 2 5V level They are supplied by VDDPLL A 1 3 4 TEST This pin is used for production testing only A 1 3 5 VREGEN This pin is used to enable the on chip voltage regulator A 1 4 Current Injection Power supply must maintain regulation within operating Vpps or Vpp range during instantaneous and operating maximum current conditions If positive injection current Vi gt Vpp is greater than Ipps the injection current may flow
77. ed sg dodici xe ruo Qro defe Reo vu reo see 39 0100 010F Flash Control Register fts64k 39 0110 011 EEPROM Control Register 1 39 011 011F Reserved for RAM Control Register 40 0120 013F ATD1 Analog to Digital Converter 10 Bit 8 Channel 40 0140 017F CANO Motorola Scalable CAN MSCAN 41 Table 1 2 Detailed MSCAN Foreground Receive and Transmit Buffer Layout 42 0180 023F Reserved VUL xen Rr d Ga ri 43 0240 027F Port Integration Module 44 M MOTOROLA 13 MC9S12DJ64 Device User Guide 01 13 0280 Table 1 3 Table 1 4 Table 2 1 Table 2 2 Table 4 1 Table 4 2 Table 4 3 Table 5 1 Table 22 1 Table A 1 Table A 2 Table A 3 Table A 4 Table A 5 Table A 6 Table A 7 Table A 8 Table A 9 Table A 10 Table A 11 Table A 12 Table A 13 Table A 14 Table A 15 Table A 16 Table A 17 Table A 18 Table A 19 Table A 20 14 BOSER Reserved NG 46 Assigned een 47 Memory size registers 47 Signal Properties oen ee eer oe ted t ag UA pa 52 MC9S12DJ64 Power and Ground Connection Summary 62 MOdE SEIECHON sa 52 5 it dE d RR er eh ee 67 Clock Selection Based PEZ
78. egulator disabled VDD1 2 and VDDPLL must be supplied externally with 2 5V 4 3 Security The device will make available a security feature preventing the unauthorized read and write of the memory contents This feature allows e Protection of the contents of FLASH e Protection of the contents of EEPROM Operation in single chip mode Operation from external memory with internal FLASH and EEPROM disabled The user must be reminded that part of the security must lie with the user s code An extreme example would be user s code that dumps the contents of the internal program This code would defeat the purpose of security At the same time the user may also wish to put a back door in the user s program An example of this is the user downloads a key through the SCI which allows access to a programming routine that updates parameters stored in EEPROM 4 3 1 Securing the Microcontroller Once the user has programmed the FLASH and EEPROM if desired the part can be secured by programming the security bits located in the FLASH module These non volatile bits will keep the part secured through resetting the part and through powering down the part The security byte resides in a portion of the Flash array Check the Flash Block User Guide for more details on the security configuration 4 3 2 Operation of the Secured Microcontroller 4 3 2 1 Normal Single Chip Mode This will be the most common usage of the secured part Everything will app
79. ers Corrected MEMSIZ1 value in Table Memory size registers Subsection Device Memory Map Removed Flash mapping from 0000 to 3FFF Table Signal Properties Added column Internal Pull Resistor Preface Table Document References Changed to full naming for each block Table Interrupt Vector Locations Column Local Enable Corrected several register and bit names Figure Recommended PCB Layout for 80QFP Corrected VREGEN pin position Thermal values for junction to board and package BGND pin pull up Part Order Information Global Register Table Chip Configuration Summary Modified mode of Operations chapter Section Printed Circuit Board Layout Proposals added Pierce Oscillator examples for 112LQFP and 80QFP MC9S12DJ64 Device User Guide V01 13 Version Revision Effective Number Date Date V01 06 Author Description of Changes NVM electricals updated Subsection Detailed Register Map Address corrections Preface Table Document references added OSC User Guide New section Oscillator OSC Block Description V01 07 25 Sept V01 08 2002 Electrical Characteristics Section General removed preliminary disclaimer Table Supply Current Characteristics changed max Run IDD from 65mA to 50mA changes max Wait IDD from 40mA to 30mA changed max Stop IDD from 50uA to 1000 Section HCS12 Core Block Desciption mentioned alternalte clock of BDM to be equivalent to osc
80. evice Current 8 tested at Internal Pull Down Device Current 9 tested at Internal Pull Down Device Current 10 C tested at 11 D Input Capacitance Injection current 12 Single Pin limit Total Device Limit Sum of all injected currents 13 Port H J P Interrupt Input Pulse filtered 14 PortH J P Interrupt Input Pulse passed NOTES 1 Refer to Section A 1 4 Current Injection for more details 2 Parameter only applies in STOP or Pseudo STOP mode A 1 10 Supply Currents This section describes the current consumption characteristics of the device as well as the conditions for the measurements 90 MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 1 10 1 Measurement Conditions All measurements are without output loads Unless otherwise noted the currents are measured in single chip mode internal voltage regulator enabled and at 25MHz bus frequency using a 4MHz oscillator in Colpitts mode Production testing is performed using a square wave signal at the EXTAL input A 1 10 2 Additional Remarks In expanded modes the currents flowing in the system are highly dependent on the load at the address data and control signals as well as on the duty cycle of those signals No generally applicable numbers can be given A very good estimate is to take the single chip currents and add the currents due to the external loads Table A 7 Su
81. gram or erase operation at frequencies above or below the specified minimum Attempting to program or erase the NVM modules at a lower frequency a full program or erase transition is not assured The Flash and EEPROM program and erase operations are timed using a clock derived from the oscillator using the FCLKDIV and ECLKDIV registers respectively The frequency of this clock must be set within the limits specified as The minimum program and erase times shown in Table A 11 are calculated for maximum fyymop and maximum The maximum times are calculated for minimum fyymop and a fy of 2MHz A 3 1 1 Single Word Programming The programming time for single word programming is dependant on the bus frequency as a well as on the frequency fyymop and can be calculated according to the following formula t HC NM 25 een fous A 3 1 2 Row Programming This applies only to the Flash where up to 32 words in a row can be programmed consecutively by keeping the command pipeline filled The time to program a consecutive word can be calculated as 1 1 4 9 1 NVMOP fbus The time to program a whole row is 1 swpgm 31 Row programming is more than 2 times faster than single word programming 3 1 3 Sector Erase Erasing a 512 byte Flash sector or a4 byte EEPROM sector takes M MOTOROLA 97 MC9S12DJ64 Device User Guide V01 13 1 used era
82. he MCU through VDD and VSS Because fast signal transitions place high short duration current demands on the power supply use bypass capacitors with high frequency characteristics and place them as close to the MCU as possible This 2 5V supply is derived from the internal voltage regulator There is no static load on those pins allowed The internal voltage regulator is turned off if VREGEN is tied to ground NOTE No load allowed except for bypass capacitors 2 4 4 VDDA VSSA Power Supply Pins for ATDO ATD1 and VREG VDDA VSSA are the power supply and ground input pins for the voltage regulator and the two analog to digital converters It also provides the reference for the internal voltage regulator This allows the supply voltage to ATDO ATDI and the reference voltage to be bypassed independently M MOTOROLA 63 MC9S12DJ64 Device User Guide V01 13 2 4 5 VRH VRL Reference Voltage Input Pins VRH and VRL are the reference voltage input pins for the analog to digital converter 2 4 6 VDDPLL VSSPLL Power Supply Pins for PLL Provides operating voltage and ground for the Oscillator and the Phased Locked Loop This allows the supply voltage to the Oscillator and PLL to be bypassed independently This 2 5V voltage is generated by the internal voltage regulator NOTE No load allowed except for bypass capacitors 2 4 7 VREGEN On Chip Voltage Regulator Enable Enables the internal 5V to 2 5V voltage regulator If
83. igured on EXTAL and XTAL Since this pin is an input with a pull up device during reset if the pin is left floating the default configuration is a Colpitts oscillator circuit on EXTAL and XTAL M MOTOROLA 55 MC9S12DJ64 Device User Guide V01 13 Crystal or MCU ceramic resonator C2 VSSPLL Due to the nature of a translated ground Colpitts oscillator DC voltage bias is applied to the crystal Please contact the crystal manufacturer for crystal DC bias conditions and recommended capacitor value Figure 2 4 Colpitts Oscillator Connections PE7 1 MEH Rg CI Crystal or 3 resonator Rs be zero shorted when used with higher frequency crystals Refer to manufacturer s data Figure 2 5 Pierce Oscillator Connections PE7z0 EXTAL 4 CMOS COMPATIBLE EXTERNAL OSCILLATOR V Level MCU VppPLL XTAL not connected Figure 2 6 External Clock Connections PE7z0 M MOTOROLA 56 MC9S12DJ64 Device User Guide 01 13 2 3 14 PE6 MODB IPIPE1 Port E I O Pin 6 PE6 is a general purpose input or output pin It is used as a MCU operating mode select pin during reset The state of this pin is latched to the MODB bit at the rising edge of RESET This pin is shared with the instruction queue tracking signal IPIPE1 This pin is an input with a pull down device which is only active when RESET is low 2 3 15 PE5 MODA
84. illator clock Table 5V I O Characteristics Corrected Input Leakage Current to 1 uA Section Part ID assignment Located on start of next page for better readability 10 Oct 2002 V01 09 Added 9512 64 derivative to cover sheet and Derivative Differences Table Corrected in footnote of Table PLL Characteristics fosc 4MHz V01 10 Renamed Preface section to Derivative Differences and Document references Added details for derivatives missing CANO and or BDLC Table ESD and Latch up Test Conditions changed pulse numbers from 3 to 1 Table ESD and Latch Up Protection Characteristics changed parameter classification from C to T Table 5V I O Characteristics removed foot note from Input Leakage Current Table Supply Current Characteristics updated Stop and Pseudo Stop currents voi 11 V01 12 Subsection Detailed Register Map Corrected several entries Subsection Unsecuring the Microcontroller Added more details Table Operating Conditions improved footnote 1 wording applied footnote 1 to PLL Supply Voltage Tables SPI Master Slave Mode Timing Characteristics Corrected Operating Frequency Appendix NVM Flash and EEPROM Replaced burst programming row programming Table Operating Conditions corrected minimum bus frequency to 0 25MHz Section Feature List ECT features changed to Four pulse accumulators V01 13 MOTOROLA Repla
85. ined as fvco f 2 synr 1 50 ref With the above values the resistance can be calculated The example is shown for a loop bandwidth fc 10kHz 2 n n fe R K 2 x 50 10kHz 316 7Hz 0 29 9kOz 10k The capacitance C can now be calculated as 2 _ 2 0 0516 5 19nF 4 7nF sco The capacitance C should be chosen in the range of 0 20 lt C lt C 10 C 470pF A 5 3 2 Jitter Information The basic functionality of the PLL is shown in Figure 2 With each transition of the clock femp the deviation from the reference clock 15 measured and input voltage to the VCO is adjusted accordingly The adjustment is done continuously with no abrupt changes in the clock output frequency Noise voltage temperature and other factors cause slight variations in the control loop resulting in a clock jitter This jitter affects the real minimum and maximum clock periods as illustrated in Figure A 3 106 M MOTOROLA MC9S12DJ64 Device User Guide 01 13 Figure A 3 Jitter Definitions The relative deviation of thom 15 at its maximum for one clock period and decreases towards zero for larger number of clock periods N Defining the jitter as max N t nom N t nom J N mad For lt 100 the following equation is a good fit for the maximum jitter Is xx XN 1 5 10 20 Figure 4 Maximum bus clock jitter approximation M
86. ir must be decoupled by a ceramic capacitor connected as near as possible to the corresponding pins C1 C6 e Central point of the ground star should be the VSSR pin e Use low ohmic low inductance connections between VSS1 VSS2 and VSSR e VSSPLL must be directly connected to VSSR e Keep traces of VSSPLL EXTAL and XTAL as short as possible and occupied board area for C7 C8 C11 and QI as small as possible Do not place other signals or supplies underneath area occupied by C7 C8 C10 and Q1 and the connection area to the MCU e Central power input should be fed in at the VDDA VSSA pins 78 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Figure 22 1 Recommended Layout 112LQFP Colpitts Oscillator M MOTOROLA 79 MC9S12DJ64 Device User Guide V01 13 Figure 22 2 Recommended PCB Layout for 80QFP Colpitts Oscillator 80 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Figure 22 3 Recommended PCB Layout for 112LQFP Pierce Oscillator MOTOROLA 81 MC9S12DJ64 Device User Guide V01 13 Figure 22 4 Recommended PCB Layout for 80QFP Pierce Oscillator 82 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Appendix A Electrical Characteristics A 1 General This introduction is intended to give an overview on several common topics like power supply current injection etc A 1 1 Parameter Classification The electrical paramete
87. it 3 Bit 2 Bit 1 Bit 0 Read 0 0 0 0 0 0 0 0 00DC Reserved Write 00 sPiopr 198 6 5 4 3 2 1 Bito Write Read 0 0 0 0 0 0 0 0 00DE Reserved Write Read 0 0 0 0 0 0 0 0 00DF Reserved Write 00 0 500 7 Inter IC Bus Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00 0 IBAD ADR7 ADR6 ADR5 ADR4 ADR3 ADR ADRI 0 Read 00E1 IBFD wie BC7 1806 IBC5 IBC4 IBC2 sc IBCO Read CN Hee 0 0 00E2 IBCR EN MSE TXRX TXAK I IBSWAI eas Read IAAS IBB a 0 SRW LA Write 00E4 10 D6 D5 D4 D3 D2 D1 Write Read 0 0 0 0 0 0 0 00E5 Reserved Write Read 0 0 0 0 0 0 0 0 00E6 Reserved Write Read 0 0 0 0 0 0 0 0 00E7 Reserved Write 00E8 00EF BDLC Bytelevel Data Link Controller J1850 Address Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 00EB DLCBCR1 ue IMSG CLKS IE WCM Se an e 1 26 0 13 12 T 10 0 0 Write 00EA DLCBCR2 SMRST DLOOP RX4XE NBFS TEOD TSIFR TMIFR1 TMIFRO 00EB DLCBDR D7 D6 D5 D4 D3 D2 D1 00EC DLCBARD ue 0 RXPOL 0 0 BO2 BO1 BOO 00ED DLCBRSR 9 0 5 R4 R3 R2 R1 RO 00EE Pead 0 Write 00EF DLCBSTAT Read 0 0 0 0 0 0 0 IDLE Write 38 M MOTOROLA 00F0 00FF Address 00 0 00FF Name Reserved 0100 010F Address 0100 0101 0102 0103 0104 0105 0106
88. it 6 0 SBR6 SCISWAI TCIE TC 0 T8 R6 T6 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 Bit 5 0 SBR5 RSRC RIE RDRF 0 0 R5 T5 MC9S12DJ64 Device User Guide V01 13 Bit 4 SBR12 SBR4 M ILIE IDLE R4 T4 Bit 4 SBR12 SBR4 M ILIE IDLE R4 T4 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 Bit 3 SBR11 SBR3 WAKE TE OR 0 0 R3 T3 SPIO Serial Peripheral Interface Bit 7 SPIE 0 0 SPIF Bit 6 SPE 0 SPPR2 Bit 5 SPTIE 0 SPPR1 SPTEF Bit 4 MSTR MODFEN SPPRO MODF Bit 3 CPOL BIDIROE 0 0 Bit 2 SBR10 SBR2 ILT RE NF BRK13 R2 T2 Bit 2 SBR10 SBR2 ILT RE NF BRK13 R2 T2 Bit 2 CPHA SPR2 Bit 1 SBR9 SBR1 PE RWU FE TXDIR R1 T1 Bit 1 SBR9 SBR1 PE RWU FE TXDIR R1 T1 Bit 1 SSOE SPISWAI SPR1 0 RAF RAF Bit 0 SBR8 SBRO PT SBK PF RO TO Bit 0 SBR8 SBRO PT SBK PF RO TO Bit 0 LSBFE SPCO SPRO 37 MC9S12DJ64 Device User Guide V01 13 00D8 00DF SPIO Serial Peripheral Interface Address Name Bit 7 Bit 6 Bit 5 Bit 4 B
89. le VDDPLL Clock and VSSPLL PLL RE on Periodic Interrupt EXTAL Module COP Watchdog Clock Monitor RESET Breakpoints PEO XIRQ PE1 IRQ PE2 R W System ISTRE Integration PE4 ECLK PE5 MODA 6 MODB 7 5 Multiplexed Address Data Bus QN st QN cn T 0 st CO QN lt lt lt lt lt lt lt lt lt lt 4 lt lt lt lt lt lt E Multiplexed lt lt lt lt lt lt lt lt lt lt lt lt lt lt Wide Bus EEEEEEEE 1 Le a a Multiplexed 229322922 Narrow Bus 5555555 Internal Logic 2 5V Driver 5V VDD1 2 VDDX VSS1 2 VSSX alls 1 A D Converter 5V amp PLL 2 5V Voltage Regulator Reference VDDPLL VSSPLL VSSA Voltage Regulator 5V amp I O VDDR VSSR M MOTOROLA ATDO VRH VRL VDDA VSSA VRH VRL VDDA VSSA ATD1 XADDR14 XADDR15 2 XADDR16 XADDR17 XADDR18 XADDR19 Enhanced Capture Timer BDLC 11850 gt RXCAN 1 2
90. llator to the internal system clocks the quality of the oscillation is checked for each start from either power on STOP or oscillator fail specifies the maximum time before switching to the internal self clock mode after POR or STOP if a proper oscillation is not detected The quality check also determines the minimum oscillator start up time typosc The device also features a clock monitor A Clock Monitor Failure is asserted if the frequency of the incoming clock signal is below the Assert Frequency fcMFA Table A 15 Oscillator Characteristics Conditions are shown in Table A 4 unless otherwise noted Rating symbol Mim Typ Crystal oscillator range Colpitts 0 5 C Crystal oscillator range Pierce Startup Current Oscillator start up time Colpitts Clock Quality check time out Clock Monitor Failure Assert Frequency External square wave input frequency External square wave pulse width low E P C D P P D D External square wave pulse width high External square wave rise time External square wave fall time Input Capacitance EXTAL XTAL pins Cin DC Operating Bias in Colpitts Configuration on EXTAL Pin Voceias NOTES 1 Depending on the crystal a damping series resistor might be necessary 2 4MHz 22pF 3 Maximum value is for extreme cases using high Q low frequency crystals 4 XCLKS 0 during reset po 2 3 4 5 6 7 8 9
91. munication Interface 1 SCI 2 3 56 PS1 TXD0 Port S I O Pin 1 PS1 is a general purpose input or output pin It can be configured as the transmit pin TXD of Serial Communication Interface 0 SCIO 2 3 57 PSO Port S I O Pin 0 50 15 a general purpose input or output pin It can be configured as the receive pin RXD of Serial Communication Interface 0 SCIO 2 3 58 PT 7 0 IOC 7 0 Port T I O Pins 7 0 PT7 PTO are general purpose input or output pins They can be configured as input capture or output compare pins IOC7 IOCO of the Enhanced Capture Timer ECT 2 4 Power Supply Pins MC9S12DJ64 power and ground pins are described below NOTE All VSS pins must be connected together in the application Table 2 2 MC9S12DJ64 Power and Ground Connection Summary Mnemonic Description 112 pin Voltage lt VDD1 2 13 65 2 5V Internal power and ground generated by internal regulator VSS1 2 14 66 OV VDDR 41 5 0V External power and ground supply to pin drivers and internal VSSR 40 0 voltage regulator VDDX 107 5 0V Ext d d S xternal power and ground su pin drivers VSSX 106 ov 3 BEER VDDA 83 5 0V Operating voltage and ground for the analog to digital converters and the reference for the internal voltage regulator VSSA 86 OV allows the supply voltage to the A D to be bypassed independently VRL 85 OV P Reference voltages for the analog to digital converter VRH 84 5 0V
92. nt Colpitts or Pierce oscillator PLL reset clocks COP watchdog real time interrupt clock monitor e 8 bit and 4 bit ports with interrupt functionality Digital filtering Programmable rising or falling edge trigger e Memory 64K Flash EEPROM 1K byte EEPROM M MOTOROLA 19 MC9S12DJ64 Device User Guide 01 13 20 4Kbyte RAM Two 8 channel Analog to Digital Converters 10 bit resolution External conversion trigger capability 1M bit per second CAN 2 0 A B software compatible module Five receive and three transmit buffers Flexible identifier filter programmable as 2 x 32 bit 4 x 16 bit or 8 x 8 bit Four separate interrupt channels for Rx Tx error and wake up Low pass filter wake up function for self test operation Enhanced Capture Timer 16 bit main counter with 7 bit prescaler 8 programmable input capture or output compare channels Four 8 bit or two 16 bit pulse accumulators 8 PWM channels Programmable period and duty cycle 8 61 8 channel or 16 bit 4 channel Separate control for each pulse width and duty cycle Center aligned or left aligned outputs Programmable clock select logic with a wide range of frequencies Fast emergency shutdown input Usable as interrupt inputs Serial interfaces Two asynchronous Serial Communications Interfaces SCI Synchronous Serial Peripheral Interface SPI Byte Data Link
93. nverter 10 Bit 8 Channel Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Bit 7 6 5 4 3 2 1 Bit 0 0 0 0 0 0 0 0 0 Bit7 6 5 4 3 2 1 BIT 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bits Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Bit15 14 13 12 11 10 9 Bit8 Bit7 Bit6 0 0 0 0 0 0 Motorola Scalable MSCAN Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXACT cswai SYNCH time wure SLPRQ INITRO CANE CLKSRC LOOPB LISTEN SJWO BRP5 BRP4 BRP3 BRP1 BRPO SAMP TSEG22 TSEG21 5 20 TSEG13 TSEG12 TSEG11 TSEG10 41 MC9S12DJ64 Device User Guide V01 13 0140 017F Motorola Scalable MSCAN Address Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 0144 CANORFLG LES TAO STATE TSTATO CHA 0145 CANORIER CSCIE 1
94. on on resets and interrupts 5 2 Vectors 5 2 1 Vector Table Table 5 1 lists interrupt sources and vectors in default order of priority Table 5 1 Interrupt Vector Locations FFFC FFFD FFFA FFFB Clock Monitor fail reset COP failure reset Vector Address Interrupt Source er Local Enable FFFE FFFF Reset None None PLLCTL CME 5 9 Unimplemented instruction trap None rate select FFFO FFF1 Real Time Interrupt SFFFO sw FFF4 FFF5 X Bit None FFF2 IRQ I Bit IRQCR IRQEN F2 CRGINT RTIE FFDE FFDF Enhanced Capture Timer overflow FFEE FFEF Enhanced Capture Timer channel 0 I Bit TIE EE FFEC FFED Enhanced Capture Timer channel 1 TIE C11 EC FFEB Enhanced Capture Timer channel 2 FFE8 FFE9 Enhanced Capture Timer channel 3 I Bit E8 FFE6 FFE7 Enhanced Capture Timer channel 4 I Bit TIE CAI E6 4 5 Enhanced Capture Timer channel 5 TIE C5l E4 FFE2 Enhanced Capture Timer channel 6 I Bit TIE C61 E2 FFEO 1 Enhanced Capture Timer channel 7 I Bit TIE C71 EO TSRC2 TOI DE FFDC FFDD Pulse accumulator A overflow I Bit PACTL PAOVI DC FFDA FFDB Pulse accumulator input edge I Bit PACTL PAI DA FFD8 FFD9 SPIO SPICR1 SPIE SPTIE D8 SCICR2
95. ormation about the EEPROM module Section 18 RAM Block Description This module supports single cycle misaligned word accesses Section 19 MSCAN Block Description Consult the MSCAN Block User Guide for information about the Motorola Scalable CAN Module Section 20 Port Integration Module PIM Block Description Consult the PIM 9DJ64 Block User Guide for information about the Port Integration Module Section 21 Voltage Regulator VREG Block Description Consult the VREG Block User Guide for information about the dual output linear voltage regulator M MOTOROLA 77 MC9S12DJ64 Device User Guide V01 13 Section 22 Printed Circuit Board Layout Proposals Table 22 1 Suggested External Component Values Component Purpose Type Value 1 VDD1 filter ceramic X7R 100 220nF VDD filter cap ceramic X7R 100 220nF VDDA filter cap ceramic X7R 100nF VDDR filter cap X7R tantalum VDDPLL filter cap ceramic X7R VDDX filter cap X7R tantalum OSC load cap See PLL specification chapter 11 Cpe DC cutoff cap Colpitts mode only if recommended by quartz manufacturer R1 PLL loop filter res See PLL specification chapter R2 Rg PLL loop filter res Pierce mode only Rs PLL loop filter res Q1 Quartz The PCB must be carefully laid out to ensure proper operation of the voltage regulator as well as of the MCU itself The following rules must be observed e Every supply pa
96. out of VDDS and could result in external power supply going out of regulation Ensure external VDD5 load will shunt current greater than maximum injection current This will be the greatest risk when the MCU is not consuming power e g if no system clock is present or if clock rate is very low which would reduce overall power consumption 84 MOTOROLA A 1 5 Absolute Maximum Ratings MC9S12DJ64 Device User Guide V01 13 Absolute maximum ratings are stress ratings only A functional operation under or outside those maxima is not guaranteed Stress beyond those limits may affect the reliability or cause permanent damage of the device This device contains circuitry protecting against damage due to high static voltage or electrical fields however 1 is advised that normal precautions be taken to avoid application of any voltages higher than maximum rated voltages to this high impedance circuit Reliability of operation is enhanced if unused inputs are tied to an appropriate logic voltage level e g either or 5 Table A 1 Absolute Maximum Ratings Num Rating Symbol Min Max Unit 1 Regulator and Analog Supply Voltage Vpps 0 3 6 0 V 2 Digital Logic Supply Voltage 2 Voo 0 3 3 0 V 3 Supply Voltage 2 VDDPLL 0 3 3 0 V 4 Voltage difference VDDX to VDDR and VDDA 03 3 5 Voltage difference VSSX to VSSR and VSSA Ayssx 0 3 V 6 Digital I O Input Voltage EIER 7 Analog
97. pply Current Characteristics Conditions are shown in Table A 4 unless otherwise noted Num Rating Symbol Min Typ Max Unit Run supply currents f Single Chip Internal regulator enabled Wait Supply current All modules enabled PLL on only RTI enabled 0 0 Pseudo Stop Current RTI and COP disabled 2 40 C 27 70 85 Temp Option 100 105 V Temp Option 120 125 Temp Option 140 Pseudo Stop Current RTI and COP enabled 2 Stop Current 70 85 Temp Option 100 105 V Temp Option 120 125 Temp Option 140 M MOTOROLA 91 MC9S12DJ64 Device User Guide 01 13 NOTES 1 PLL off 2 At those low power dissipation levels T4 assumed 92 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 A 2 ATD Characteristics This section describes the characteristics of the analog to digital converter A 2 1 ATD Operating Characteristics The Table A 8 shows conditions under which the ATD operates The following constraints exist to obtain full scale full range results VssA lt lt lt lt Vppa This constraint exists since the sample buffer amplifier can not drive beyond the power supply levels that it ties to If the input level goes outside of this range it will effectively
98. pt PH4 KWH4 PERH Port H I O Interrupt Disabled PH3 KWH3 PPSH Port H I O Interrupt PH2 KWH2 Port I O Interrupt PH1 KWH1 Port I O Interrupt PHO KWHO Port H I O Interrupt 52 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Internal Pull Pin Name PinName Pin Name Pin Name Powered Resistor Description Function Function2 Function3 Function4 by Reset State PJ7 KWJ7 SCL TXCANO nn Interrupt SCL of TX of PJ6 KWJ6 SDA RXCANO VDDX PPSJ 2 I O Interrupt SDA of RX of PJ 1 0 KWJ 1 0 Port J I O Interrupts Port K I O Emulation Chip Select PK7 ECS ROMCTL Up ROM On Enable PK 5 0 XADDR 19 14 Port K I O Extended Addresses PM7 Port I O PM6 Port 5 SCK Port M I O TX of CANO SCK of SPIO 4 RXCANO MOSI Port M I O RX of CANO MOSI of SPIO PM3 TXCANO S88 Port M I O TX of CANO SS of SPIO PM2 RXCANO MISOO Port M I O RX of CANO MISO of SPIO PM1 TXCANO TXB Port M I O TX of CANO RX of BDLC PMO RXCANO RXB Port M I O RX of CANO RX of BDLC PP7 KWP7 PWM7 Disabled ur Interrupt Channel 7 of PP6 KWP6 PWM6 Port P I O Interrupt PWM Channel 6 PP5 KWP5 PWM5 Port P I O Interrupt PWM Channel 5 4 KWP4 PWMA VDO Port I O
99. rovides the physical dimensions of the MC9S12DJ64 packages M MOTOROLA 119 MC9S12DJ64 Device User Guide 01 13 B 2 112 package as X L MORN u ii r 0 13 SECTION J1 J1 1A1 ROTATED 90 COUNTERCLOCKWISE x s1 NOTES 1 MENSIONING AND TOLERANCING PER SME Y14 5M 1994 MENSIONS IN MILLIMETERS ATUMS L M AND N TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS S AND V TO BE DETERMINED AT EATING PLANE DATUM T MENSIONS A AND B DO NOT INCLUDE OLD PROTRUSION ALLOWABLE ROTRUSION IS 0 25 PER SIDE DIMENSIONS AND B INCLUDE MOLD MISMATCH MENSION D DOES NOT INCLUDE DAMBAR ROTRUSION ALLOWABLE DAMBAR ROTRUSION SHALL NOT CAUSE THE D MENSION TO EXCEED 0 46 2 gt 3 4 VDOROO gt O 5 UVVOYFrVESV SEATING PLANE 0 25 22 000 BSC GAGE PLANE 11 000 BS 0 250 Bi LE 6 LK LP _R2 LS 51 61 82 931 11 VIEW AB Figure B 1 112 pin LQFP mechanical dimensions case no 987 120 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 B 3 80 pin QFP package DETAIL A amp 02 c OIDO DETAIL A D DETAIL C 0200 AB 9 DO DATUM VIEW ROTAT
100. rs shown in this supplement are guaranteed by various methods To give the customer a better understanding the following classification is used and the parameters are tagged accordingly in the tables where appropriate NOTE This classification is shown in the column labeled C in the parameter tables where appropriate Those parameters are guaranteed during production testing on each individual device Those parameters are achieved by the design characterization by measuring a statistically relevant sample size across process variations Those parameters are achieved by design characterization on a small sample size from typical devices under typical conditions unless otherwise noted All values shown in the typical column are within this category Those parameters are derived mainly from simulations A 1 2 Power Supply The MC9S12DJ64 utilizes several pins to supply power to the I O ports A D converter oscillator PLL and internal logic The VDDA VSSA pair supplies the A D converter and the resistor ladder of the internal voltage regulator The VDDX VSSX VDDR and VSSR pairs supply the I O pins VDDR supplies also the internal voltage regulator VDDI VSS1 VDD2 and VSS2 are the supply pins for the digital logic VDDPLL VSSPLL supply the oscillator and the PLL VSS1 and VSS2 are internally connected by metal M MOTOROLA 83 MC9S12DJ64 Device User Guide 01 13 VDDA VDDX VDDR as well as VSSA VSSX VSSR are conn
101. s ATD1 and ATDO implemented on the MC9S12DJ64 Consult the 10 8 Block User Guide for information about each Analog to Digital Converter module When the 10B8C Block User Guide refers to freeze mode this is equivalent to active mode Section 11 Inter IC Bus Block Description Consult the IIC Block User Guide for information about the Inter IC Bus module Section 12 Serial Communications Interface SCI Block Description There are two Serial Communications Interfaces 5 and SCIO implemented the MC9S12DJ64 device Consult the SCI Block User Guide for information about each Serial Communications Interface module Section 13 Serial Peripheral Interface SPI Block Description 76 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Consult the SPI Block User Guide for information about each Serial Peripheral Interface module Section 14 J1850 BDLC Block Description Consult the BDLC Block User Guide for information about the J1850 module Section 15 Pulse Width Modulator PWM Block Description Consult the 8B8C Block User Guide for information about the Pulse Width Modulator module When the 8B8C Block User Guide refers to freeze mode this is equivalent to active BDM mode Section 16 Flash EEPROM 64K Block Description Consult the FTS64K Block User Guide for information about the flash module Section 17 EEPROM 1K Block Description Consult the EETS1K Block User Guide for inf
102. ser Guide 01 13 specifies results in an error of less than 1 2 LSB 2 5mV at the maximum leakage current If device or operating conditions are less than worst case or leakage induced error is acceptable larger values of source resistance is allowed A 2 2 2 Source Capacitance When sampling an additional internal capacitor is switched to the input This can cause a voltage drop due to charge sharing with the external and the pin capacitance For a maximum sampling error of the input voltage ILSB then the external filter capacitor 2 1024 Cins A 2 2 3 Current Injection There are two cases to consider 1 A current is injected into the channel being converted The channel being stressed has conversion values of 3FF FF 8 bit mode for analog inputs greater than and 000 for values less than unless the current is higher than specified as disruptive condition 2 Current is injected into pins in the neighborhood of the channel being converted A portion of this current is picked up by the channel coupling ratio K This additional current impacts the accuracy of the conversion depending on the source resistance The additional input voltage error on the converted channel be calculated as Vggg K Rg With being the sum of the currents injected into the two pins adjacent to the converted channel Table A 9 ATD Electrical Characteristics Conditions are shown in Ta
103. smit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 It can be configured as the slave select pin SS of the Serial Peripheral Interface 0 SPIO 2 3 39 2 RXCANO MISOO Port M I O Pin 2 PM2 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the master input during master mode or slave output pin during slave mode MISO for the Serial Peripheral Interface 0 SPIO 2 3 40 PM1 TXCANO TXB Port M I O Pin 1 PMI is a general purpose input or output pin It can be configured as the transmit pin TXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the transmit pin TXB of the BDLC 2 3 41 RXCANO RXB Port M I O Pin 0 is a general purpose input or output pin It can be configured as the receive pin RXCAN of the Motorola Scalable Controller Area Network controller 0 CANO It can be configured as the receive pin RXB of the BDLC 2 3 42 PP7 KWP7 PWM7 Port P I O Pin 7 PP7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 7 output 2 3 43 PP6 KWP6 PWM6 Port P I O Pin 6 PP6 is a general purpose input or output pin It can be configured to genera
104. specification Table A 2 ESD and Latch up Test Conditions Model Description Symbol Value Unit Series Resistance Ri 1500 Ohm Storage Capacitance 100 human Body Number of Pulse per pin positive 1 negative 1 Series Resistance R1 0 Ohm Storage Capacitance 200 Machine Number of Pulse per pin positive 3 negative 3 Minimum input voltage limit 2 5 Latch up Maximum input voltage limit 7 5 Table A 3 ESD and Latch Up Protection Characteristics Rating Symbol Min Max Unit Human Body Model HBM 2000 V T Machine Model 200 V T Charge Device Model CDM 500 V Latch up Current at Ta 125 C 4 T positive ILAT 100 mA negative 100 Latch up Current at 27 C 5 positive 200 mA negative 200 7 Operating Conditions This chapter describes the operating conditions of the device Unless otherwise noted those conditions apply to all the following data 86 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 NOTE Please refer to the temperature rating of the device C V M with regards to the ambient temperature T4 and the junction temperature For power dissipation calculations refer to Section A 1 8 Power Dissipation and Thermal Characteristics Table A 4 Operating Conditions Rating Symbol Min Typ Max Unit Regulator and Analog Supply Voltage 5 4 5 5 5 25 V Digital Logic Supply Voltage 1 Vpp 2 3
105. sult the respective Block User Guide for information on the module behavior in Stop Pseudo Stop and Wait Mode An important source of information about the clock system is the Clock and Reset Generator User Guide CRG 4 4 1 Stop Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static mode Wake up from this mode can be done via reset or external interrupts 4 4 2 Pseudo Stop This mode is entered by executing the CPU STOP instruction In this mode the oscillator is still running and the Real Time Interrupt RTI or Watchdog COP sub module can stay active Other peripherals are turned off This mode consumes more current than the full STOP mode but the wake up time from this mode is significantly shorter 4 4 3 Wait This mode is entered by executing the CPU WAI instruction In this mode the CPU will not execute instructions The internal CPU signals address and data bus will be fully static All peripherals stay active For further power consumption the peripherals can individually turn off their local clocks M MOTOROLA 69 MC9S12DJ64 Device User Guide V01 13 4 4 4 Run Although this is not a low power mode unused peripheral modules should not be enabled in order to save power 70 M MOTOROLA Section 5 Resets and Interrupts 5 1 Overview MC9S12DJ64 Device User Guide V01 13 Consult the Exception Processing section of the CPU12 Reference Manual for informati
106. te an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 6 output 2 3 44 PP5 KWP5 PWM5 Port P I O Pin 5 PP5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 5 output 2 3 45 4 PWM4 Port P I O Pin 4 PP4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 4 output 60 MOTOROLA MC9S12DJ64 Device User Guide V01 13 2 3 46 PP3 KWP3 PWM3 Port P I O Pin PP3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 3 output 2 3 47 2 KWP2 PWM2 Port P I O Pin 2 PP2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 2 output 2 3 48 PP1 KWP1 PWM1 Port P I O Pin 1 1 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode It can be configured as Pulse Width Modulator PWM channel 1 output 2 3
107. te f ore ett oen 90 A 2 ATD Characteristics a ke 93 A 2 1 ATD Operating Characteristics 93 2 2 Factors influencing 93 2 3 a uite 95 AG INV Hash and EEPROM s tkt ie sen ee 97 3 1 IV RMIT zusehen een air 97 A 3 2 NVM 99 A 4 8 2 818 6 101 Reset Oscilatorand PER RECO ESSE Y Fera e SEO s 103 A 5 1 lat EE 103 A 5 2 erro dcr PEEL 104 A 5 3 Phase Loops aep ernennen 105 Pros Duel nn ole Oe ah DIE dO e 109 Au gt OPUS ellie keh A EAE 111 A 7 1 Master Mode eae lng 111 7 2 Slave Mol atom toe tutta ard x 113 u External Bus 115 8 1 General Muxed Bus Timing op d p t ht ee PEE EO atiis 115 Appendix B Package Information M MOTOROLA 9 MC9S12DJ64 Device User Guide 01 13 B 1 B 2 B 3 10 General o duco A nal 119 112pm EQEP Packages 4 uu t o iti art EZ 120 80 pin QFP package eyes oS aa
108. this pin is tied low VDD1 2 and VDDPLL must be supplied externally 64 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 3 System Clock Description 3 1 Overview The Clock and Reset Generator provides the internal clock signals for the HCS12 Core and all peripheral modules Figure 3 1 shows the clock connections from the CRG to all modules Consult the CRG Block User Guide and OSC Block User Guide for details on clock generation Core Clock om EXTAL ATDO 1 SCIO SCI1 CANO ECT WM all OSC CRG XTAL BDLC Figure 3 1 Clock Connections 65 M MOTOROLA MC9S12DJ64 Device User Guide 01 13 66 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 4 Modes of Operation 4 1 Overview Eight possible modes determine the operating configuration of the MC9S12DJ64 Each mode has associated default memory map and external bus configuration Three low power modes exist for the device 4 2 Chip Configuration Summary The operating mode out of reset is determined by the states of the MODC MODB and MODA pins during reset Table 4 1 The MODC MODB and MODA bits in the MODE register show the current operating mode and provide limited mode switching during operation The states of the MODC MODB and MODA pins are latched into these bits on the rising edge of the reset signal The ROMCTL signal allows the setting of the ROMON bit in the MISC register thus
109. two 8 bit registers MEMSIZO and MEMSIZI addresses 001C and 001D after reset Table 1 4 shows the read only values of these registers Refer to HCS12 Module Mapping Control MMC Block Guide for further details Table 1 4 Memory size registers Register name Value MEMSIZO MEMSIZ1 M MOTOROLA 47 MC9S12DJ64 Device User Guide 01 13 48 44 MOTOROLA MC9S12DJ64 Device User Guide V01 13 Section 2 Signal Description This section describes signals that connect off chip It includes a pinout diagram a table of signal properties and detailed discussion of signals It is built from the signal description sections of the Block Guides of the individual IP blocks on the device 2 1 Device Pinout The MC9S12DJ64 is available in 112 pin low profile quad flat pack LQFP and in a 80 pin quad flat pack QFP Most pins perform two or more functions as described in the Signal Descriptions Figure 2 1 and Figure 2 2 show the pin assignments M MOTOROLA 49 MC9S12DJ64 Device User Guide 01 13 12 3 PPA KWP4 PWMA 11 3 PP5 KPW5 PWM5 10 3 PP6 KWP6 PWM6 09 PP7 KWP7 PWM7 08 O PK7 ECS ROMCTL PWM3 KWP3 PP3 PWM2 KWP2 PP2 PWM1 KWP1 PP1 PWMO KWPO PPO XADDR17 PK3 XADDR16 PK2 XADDR15 PK1 XADDR14 PKO 10C1 PT1 IOC2 PT2 VDD1 VSS1 5 5 IOC6 PT6 IOC7 PT7 XADDR19 PK5 XADDR18 PK4 KWJ1 PJ1 KWJ0 PJ0 MODC TAGHI BKGD ADDRO DATAO PBO ADDR1 DATA
110. ty DNL is defined as the difference between two adjacent switching steps DNL i 1 1LSB The Integral Non Linearity INL is defined as the sum of all DNLs n V V _ n 0_ INL n DNL gg n 95 M MOTOROLA MC9S12DJ64 Device User Guide 01 13 10 Bit Resolution 3FF 3FE 3FD 3FC 3FB 3FA 3F9 3F8 3F7 3F6 3F5 3F4 3F3 DNL LSB 10 Bit Absolute Error Boundary A 8 Bit Absolute Error Boundary N N N N 2 FE deal Transfer Curve FD 100 8 Bit Resolut N 7 4 10 Bit Transfer Curve N 8 Bit Transfer Curve Un 45 Figure A 1 ATD Accuracy Definitions gt 5055 5060 5065 5070 5075 5080 5085 5090 5095 5100 5105 5110 5115 5120 Vin mV NOTE Figure A 1 shows only definitions for specification values refer to Table A 10 96 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 NVM Flash and EEPROM NOTE Unless otherwise noted the abbreviation Non Volatile Memory is used for both Flash and EEPROM A 3 1 NVM timing The time base for all NVM program or erase operations is derived from the oscillator A minimum oscillator frequency fyymosc is required for performing program or erase operations The NVM modules do not have any means to monitor the frequency and will not prevent pro
111. urpose input pin and the non maskable interrupt request input that provides a means of applying asynchronous interrupt requests This will wake up the MCU from STOP or WAIT mode 2 3 21 PH7 KWH7 Port H I O Pin 7 PH7 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode M MOTOROLA 57 MC9S12DJ64 Device User Guide V01 13 2 3 22 PH6 KWH6 Port H I O Pin 6 PH6 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 23 PH5 KWH5 Port H I O Pin 5 5 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 24 PHA KWHA Port H Pin 2 PH4 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 25 PH3 KWH3 Port H I O Pin PH3 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 26 PH2 KWH2 Port H I O Pin 2 PH2 is a general purpose input or output pin It can be configured to generate an interrupt causing the MCU to exit STOP or WAIT mode 2 3 27 PH1 KWH1 Port H I O Pin 1 PHI is a general purpose input or output pin It can be configured to generate an interrupt causing MCU to exit STOP or
112. ya Junction Temperature C M MOTOROLA 87 MC9S12DJ64 Device User Guide 01 13 Ambient Temperature C Ta Pp Total Chip Power Dissipation W Oja Package Thermal Resistance C W The total power dissipation can be calculated from Pp INT HO PINT Chip Internal Power Dissipation W Two cases with internal voltage regulator enabled and disabled must be considered 1 Internal Voltage Regulator disabled Pint Ypo VppPLL 2 Roson is the sum of all output currents on I O ports associated with VDDX For Rpson 15 valid V RDSON ier outputs driven low respectively V V RDSON DA for outputs driven high OH 2 Internal voltage regulator enabled Pint Ippg is the current shown in Table 7 and not the overall current flowing into VDDR which additionally contains the current flowing into the external loads with output high 2 Pio Roson is the sum of all output currents on I O ports associated with VDDX and VDDR 88 M MOTOROLA MC9S12DJ64 Device User Guide V01 13 Table A 5 Thermal Package Characteristics Rating Min Typ Max Unit Thermal Resistance LQFP112 single sided C W Thermal Resistance LQFP112 double sided PCB C W with 2 internal planes 3 Junction to Board LQFP112

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