Xilinx UG130 Spartan-3 FPGA Starter Kit Board User Guide
Contents
1. Each port offers some ability to program the FPGA on the Spartan 3 Starter Kit Board For example port A1 provides additional logic to drive the FPGA and Platform Flash JTAG chain Similarly ports A2 and B1 provide connections for Master or Slave Serial mode configuration Finally port B1 also offers Master or Slave Parallel configuration mode Each 40 pin expansion header shown in Figure 13 2 uses 0 1 inch 100 mil DIP spacing Pin 1 on each connector is always GND Similarly pin 2 is always the 5V DC output from the switching power supply Pin 3 is always the output from the 3 3V DC regulator Pin 39 Pin 3 3 3V Pin 1 GND Pin 39 Pin 40 7 Pin 4 Pin 2 VU Pin 40 5V UG130 c12 02 042504 Figure 13 2 40 pin Expansion Connector The pinout information for each connector appears below The tables include the connections between the FPGA and the expansion connectors plus the signal names used in the detailed schematic in Figure A 1 48 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Expansion Connectors A1 Connector Pinout XILINX The A1 expansion connector is located along the top edge of the board on the left as indicated by FPGA connections are specified in parentheses Table 13 2 Pinout for A1 Expansion Connector in Figure 1 2 Table 13 2 provides the pinout for the A1 connector The2. Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V DBO N7 L5 ADR1 SRAM IC10 IOO SRAM AO DB1 T8 N3 ADR2 SRAM IC10 IO1 SRAM A1 DB2 R6 M4 ADR3 SRAM IC10 IO2 SRAM A2 DB3 T5 M3 ADR4 SRAM IC10 IO3 SRAM A3 DB4 R5 L4 ADR5 SRAM IC10 104 SRAM A4 DB5 C2 G3 WE SRAM IC10 IO5 SRAM WE DB6 C1 K4 OE SRAM IC10 IO6 SRAM OE DB7 B1 P9 CSA SRAM IC10 IO7 FPGA DOUT BUSY LSBCLK M7 M10 MA1 DBO MA1 DB1 F3 G4 MA1 DB2 SRAM A6 SRAM A5 MA1 DB3 E3 F4 MA1 DB4 SRAM A8 SRAM A7 MA1 DB5 G5 E4 MA1 DB6 SRAM A10 SRAM A9 MA1 DB7 H4 H3 MA1 ASTB SRAM A12 SRAM A11 MA1 DSTB J3 WEN MAI WRITE SRAM A14 SRAM A13 MAI WAIT K5 K3 MA1 RESET SRAM A16 SRAM A15 MAI INT L3 JTAG Isolation JTAG Isolation SRAM A17 TMS C13 C14 TCK FPGA JTAG TMS FPGA JTAG TCK TDO ROM Platform Flash Header J7 pin 3 TDO A JTAG TDO Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 www xilinx com 49 SC XILINX Chapter 13 Expansion Connectors and Boards The A1 expansion connector shares connections with the 256Kx16 SRAM devices specifically the SRAM address lines the OE and WE control signals and the eight least significant data lines to SRAM IC10 only Similarly the JTAG chain is available on pins 36 through 40 Pin 20 is the FPGA DOUT BUSY configuration signal and toggles dur
3. Address Bit FPGA Pin A1 Expansion Connector Pin A17 L3 35 A16 K5 33 A15 K3 34 A14 Ja 81 A13 J4 32 A12 H4 29 A11 H3 30 A10 G5 27 A9 E4 28 A8 E3 25 A7 F4 26 A6 F3 23 A5 G4 24 A4 L4 14 A3 M3 12 A2 M4 10 A1 N3 8 AO L5 6 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Write Enable and Output Enable Control Signals XILINX Write Enable and Output Enable Control Signals Both 256Kx16 SRAMs share common output enable OE and write enable WE control lines as shown in Table 2 2 These control signals also connect to the A1 Expansion Connector refer to Expansion Connectors page 47 Table 2 2 External SRAM Control Signal Connections to Spartan 3 FPGA Signal FPGA Pin A1 Expansion Connector Pin OE K4 18 WE G3 16 SRAM Data Signals Chip Enables and Byte Enables The data signals chip enables and byte enables are dedicated connections between the FPGA and SRAM Table 2 3 shows the FPGA pin connections to the SRAM designated IC10 in Figure A 8 Table 2 4 shows the FPGA pin connections to SRAM IC11 To disable an SRAM drive the associated chip enable pin High Table 2 3 SRAM IC10 Connections Signal FPGA Pin A1 Expansion Connector Pin IO15 R1 IO14 P1 IO13 L2 IO12 J2 1011 H1 1010 F2 109 P8 108 D3 IO7 Bl 19 106 Cl 17 105 C2 15 IO4 R5 13 IO3 T5
4. Dod T d Tp TpisP bi g l Ree E i r Tew Pr UG130 c5 03 051305 Figure 5 3 VGA Control Timing www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 VGA Signal Timing XILINX Generally a counter clocked by the pixel clock controls the horizontal timing Decoded counter values generate the HS signal This counter tracks the current pixel display location on a given row A separate counter tracks the vertical timing The vertical sync counter increments with each HS pulse and decoded values generate the VS signal This counter tracks the current display row These two continuously running counters form the address into a video display buffer For example the on board fast SRAM is an ideal display buffer No time relationship is specified between the onset of the HS pulse and the onset of the VS pulse Consequently the counters can be arranged to easily form video RAM addresses or to minimize decoding logic for sync pulse generation Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 25 UG130 v1 2 June 20 2008 XILINX Chapter 5 VGA Port 26 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 6 PS 2 MouselKeyboard Port The Spartan 3 FPGA Starter Kit board includes a PS 2 mouse keyboard port and the standard 6 pin mini DIN connector labeled J3 on the board and indicated as i
5. RIN1 ROUT1 DOUT2 DIN2 GND RIN2 ROUT2 Recei LD7 LD6 LD5 eceiver FPGA pin number Transmitter 8 SES J1 Header Auxiliary Serial Port UG130 c7 01 072104 Figure 7 1 RS 232 Serial Port Figure 7 1 shows the connection between the FPGA and the DB9 connector including the Maxim MAX3232 RS 232 voltage converter indicated as 7 in Figure 1 2 The FPGA supplies serial output data as LVTTL or LVCMOS levels to the Maxim device which in Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 33 UG130 v1 2 June 20 2008 3 XILINX 34 Chapter 7 RS 232 Serial Port turn converts the logic value to the appropriate RS 232 voltage level Likewise the Maxim device converts the RS 232 serial input data to LVTTL levels for the FPGA A series resistor between the Maxim output pin and the FPGA s RXD pin protects against accidental logic conflicts A detailed schematic appears in Figure A 7 Hardware flow control is not supported on the connector The port s DCD DTR and DSR signals connect together as shown in Figure 7 1 Similarly the port s RTS and CTS signals connect together The FPGA connections to the Maxim RS 232 translator appear in Table 7 1 Table 7 1 Accessory Port Connections to the Spartan 3 FPGA Signal FPGA Pin RXD T13 TXD R13 RXD A N10 TXD A T14 An auxiliary RS 232 serial channel from the Maxim device i
6. 9 dec 9 NEZI 9 dzz1 9 Ne21 9 dz 9 NIZI Ela 9 9 d6T1 9 NEI 9 J3un 9 get 9 9 dat 9 N9T1 9 di 1 9 TOI 9 ueg O I UG130 ApA 05 051305 Z J3un Z opt Z N t Z d6 1 Z N6 1 ZC dbz Z NrZ1 ZC dezT Z d3un Z NEZI ZC dgl ai ZC dizi Z NIZ1 Z dez1i Z NOZI Z del ZC N6eT1 Z Jdun Z dZTl ZC NZT1 Z d i Z NSTI 6 dii Z TOI z 1 Clock Sources ions FPGA I O Connecti 5 A Figure Spartan 3 FPGA Starter Kit Board User Guide www xilinx com UG130 v1 2 June 20 2008 SC XILINX T 434n T NATI Idle T NIO1 T 4aun 01 OI zor TOI a dszT SECH 0595 2005 891 8 410 TNTET 0 An240 0 0 1 GES peie2ogS 97 4380 01 ES zor tor 8 I ueg 1 9 ued 1 58 8 9 1388ug 3 4O0uing 99 4seutbuy SC XILINX toe asea ey 002 21 2 48qunN iusun2og 0 008 paeog CG 1 DUI 006 iubr4fidoj p4eog gs 093 699 EIER 23 283 199 Ski G 9 z SS SR E44 E44 T 9 cH 9 7 SL E FC EC 63 JnIO 0 4n12 1NI2 6 6 6 SL ML 26
7. lights up when power is properly applied to the board If the jumpers in the J8 header and JP1 header are properly set and there is a valid configuration data file in the Platform Flash memory then the DONE indicator LED shown as 3 in Figure 1 2 also lights up The AC wall adapter is directly compatible for North America Japan and Taiwan locales Other locations might require a socket adapter to convert from the North American standard to the local power socket standard The AC wall adapter operates from 100V to 240V AC input at 50 or 60 Hz Voltage Regulators There are multiple voltages supplied on the Spartan 3 Starter Kit Board as summarized in Table 12 1 Table 12 1 Voltage Supplies and Sources Voltage Source Supplies 5V DC AC Wall Adapter 5V switching power supply 3 3V regulator in Figure 1 2 Optionally PS 2 port via jumper JP2 setting Pin 1 VU on A1 A2 B1 expansion connectors 3 3V DC National Semiconductor LM1086CS ADJ3 3V 2 5V and 1 2V regulators regulator in Figure 1 2 Veco supply input for all FPGA I O banks Most components on the board Pin 3 on A1 A2 B1 expansion connectors 2 5V DC STMicroelectronics LF25CDT 2 5V regulator Supply input to FPGA in Figure 1 2 1 2V DC Fairchild Semiconductor FAN1112 1 2V Vecint supply input to FPGA regulator in Figure 1 2 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 45 UG130 v1 2 June 2
8. www xilinx com 63 3 XILINX SPARTAN 3 MAKE IT YOUR ASIC http www xilinx com products boards s3 sk promo htm PN 0402292 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008
9. Figure 6 2 the attached keyboard or mouse writes a bit on the data line when the clock signal is High and the host reads the data line when the clock signal is Low Table 6 2 PS 2 Bus Timing Symbol Parameter Min Max Tck Clock High or Low time 30 us 50 us Tsu Data to clock setup time 5 us 25 us THLD Clock to data hold time 5 us 25 us Tek Tek Edge 0 T edi 10 CLK PS2C d Nu DATA PS2D mme O start bit T OP DN UG130_c6_02_042404 Figure 6 2 PS 2 Bus Timing Waveforms The following site contains additional information on the PS 2 bus protocol e PS 2 Mouse Keyboard Protocol http www computer engineering org ps2protocol The keyboard uses open collector drivers so that either the keyboard or the host can drive the two wire bus If the host never sends data to the keyboard then the host can use simple input pins A PS 2 style keyboard uses scan codes to communicate key press data Nearly all keyboards in use today are PS 2 style Each key has a single unique scan code that is sent whenever the corresponding key is pressed The scan codes for most keys appear in Figure 6 3 If the key is pressed and held the keyboard repeatedly sends the scan code every 100 ms or so When a key is released the keyboard sends a F0 key up code followed by the scan code of the released key The keyboard sends the same scan code regardless if a key has different shift
10. LEDs and Four Character 7 Segment Display Figure A 3 Voltage Regulators JP2 Jumper Setting for PS 2 Port Voltage Figure A 4 FPGA Configuration Interface Platform Flash JTAG Connections Jumper JP1 Figure A 5 FPGA I O Connections Clock Sources Figure A 6 Power Decoupling Capacitors Figure A 7 RS 232 Serial Port VGA Port PS 2 Port Parallel Cable IV JTAG Interface Figure A 8 2x256Kx16 Fast Asynchronous SRAM Interface Figure A 9 Digilent JTAG3 Low Cost JTAG Download Debug Cable Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 53 UG130 v1 2 June 20 2008 DUT ojoeuuoo V ulm pejeus osje 21 OLD WWHS O stg Lep 14513 13M0 sien J0j2euuoo V ulm suonoeuuoo peJeus e eu s ouuoo 43M AO pue seul sseippe WWHS b OZ ZI ZI 31eG esee eu 0 609 49qnN iueunoo p4eeg CS 1 8 1 198uS Mey 40uing 9 99 DUI eTrbrd vgez iubrahdo5 p4eog 65 Appendix A Board Schematics SC XILINX 0 6 8 9 8 T get 96H eat Ca get 994 get 691 eat 8 9U d AN 194 V3297INI cUW OO000000000000000000000000000000000000000
11. and non shift characters and regardless whether the Shift key is pressed or not The host determines which character is intended Some keys called extended keys send an E0 ahead of the scan code and furthermore they may send more than one scan code When an extended key is released a E0 F0 key up code is sent followed by the scan code www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Keyboard ESC 76 XILINX F1 FA F5 F6 F7 F8 F9 F11 F12 f 05 OC 03 OB 83 OA 01 78 07 EO 75 Ke 3 4 p 6 8 s i83 K ES Em Ke 26 25 36 3D i83 K ES Em E074 id BE 4 E E 2 M M Ba E 5D EO 6B SR r leie BABABBBBES 58 16 18 23 28 34 33 38 42 48 6 2 5A ESO V B N M gt gt 1 A Shift ES Ea 2 E 2A 32 31 3a 41 49 4a 59 Ctrl 14 Alt Space Alt Ctrl 11 29 E011 E014 UG130 c6 03 042404 Figure 6 3 PS 2 Keyboard Scan Codes The host can also send data to the keyboard Table 6 3 provides a short list of some often used commands Table 6 3 Common PS 2 Keyboard Commands Command ED Description Turn on off Num Lock Caps Lock and Scroll Lock LEDs The keyboard acknowledges receipt of an ED command by replying with an FA after which the host sends another byte to set LED status The bit positions for the keyboard LEDs appear in Table 6 4 Write a 1 to the specific bit to illumi
12. as shown in Figure 10 2 When the jumper is in this position the Platform Flash is always enabled After FPGA configuration completes the FPGA application drives the INIT B pin High FPGA pin N9 Consequently the Platform Flash data pointer is not reset and points to the additional data following the FPGA configuration data To read any subsequent data the FPGA application generates additional clock pulses on the RCLK signal from FPGA pin A14 After configuration the FPGA s CCLK output is three stated with a pull up resistor to Vecaux 2 5V The Platform Flash presents serial data on the FPGA s DIN pin pin M11 Spartan 3 FPGA Platform Flash py JP1 DIN DO DO OE RESET Flash Read INIT B DONE CCLK USER 1 0 xx FPGA pin number UG130_c10_02_060404 Figure 10 2 Read Additional Data from Platform Flash by Setting the JP1 Jumper The resistor between the CCLK output and FPGA pin A14 prevents any accidental conflicts between the two signals www xilinx com 39 UG130 v1 2 June 20 2008 XILINX Chapter 10 Platform Flash Configuration Storage Additional FPGA logic is required to read the Platform Flash data as described in the following application note e XAPP694 Reading User Data from Configuration PROMs www xilinx com support documentation application notes xapp694 pdf Disable Option If the JP1 jumper is removed then the Platform Flash is disabled potentially allowing configuration via an
13. timings signals and coordinates the delivery of video data on each pixel clock The pixel clock defines the time available to display one pixel of information The VS signal defines the refresh frequency of the display or the frequency at which all information on the display is redrawn The minimum refresh frequency is a function of the display s phosphor and electron beam intensity with practical refresh frequencies in the 60 Hz to 120 Hz range The number of horizontal lines displayed at a given refresh frequency defines the horizontal retrace frequency VGA Signal Timing 24 The signal timings in Table 5 3 are derived for a 640 pixel by 480 row display using a 25 MHz pixel clock and 60 Hz 1 refresh Figure 5 3 shows the relation between each of the timing symbols The timing for the sync pulse width Tpw and front and back porch intervals Tgp and Tgp are based on observations from various VGA displays The front and back porch intervals are the pre and post sync pulse times Information cannot be displayed during these times Table 5 3 640x480 Mode VGA Timing Vertical Sync Horizontal Sync Symbol Parameter Time Clocks Lines Time Clocks Ts Sync pulse time 16 7 ms 416 800 521 32 us 800 Tpigp Display time 15 36 ms 384 000 480 25 6 us 640 Tpw Pulse width 64 us 1 600 2 3 84 us 96 Trp Front porch 320 us 8 000 10 640 ns 16 Tpp Back porch 928 us 23 200 29 1 92 us 48
14. to save 20 additional I O pins Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 17 UG130 v1 2 June 20 2008 XILINX Chapter 3 Four Digit Seven Segment LED Display 18 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 4 Switches and LEDs Slide Switches The Spartan 3 FPGA Starter Kit board has eight slide switches indicated as in Figure 1 2 The switches are located along the lower edge of the board toward the right edge The switches are labeled SW7 through SWO Switch SW7 is the left most switch and SWO is the right most switch The switches connect to an associated FPGA pin as shown in Table 4 1 A detailed schematic appears in Figure A 2 Table 4 1 Slider Switch Connections Switch SW7 SW6 SW5 SWA SW3 SW2 SW1 SWO FPGA Pin K13 K14 J13 J14 H13 H14 G12 F12 When in the UP or ON position a switch connects the FPGA pin to Vcco a logic High When DOWN or in the OFF position the switch connects the FPGA pin to ground a logic Low The switches typically exhibit about 2 ms of mechanical bounce and there is no active debouncing circuitry although such circuitry could easily be added to the FPGA design programmed on the board A 4 7KQ series resistor provides nominal input protection Push Button Switches The Spartan 3 Starter Kit board has four momentary contact push button switches indicated as in Figure
15. xilinx com 3 Voltage Regulators Figure A 56 XILINX 6 8 g g t4ouing 99 48eurbu3 Jn2v0 0 J 270 0 J 270 0 Zi H3 912 00Z 21 21 ap esee eu 0 608 49qunN iueun2oQg paeog 585 1 00 007 Duy p4eog 65 6 WON eu Buran61r uo2 ueum spoy er4eg SAPIS 129195 Oi 8r 40 I300H Pue 8300 Uo peipeisur eq pinoys s 4201q Bur ious EI uorieanDr uo2 petias su aui 550000 oi Zdf pue dr jO 5 6 sutd uo pajjeisur sue soo q buri2oug 4JepeaH e2ej4aiu 7 y uey 4euie4 uoriisod paeoq fesydried e WO4 USATAIP Bureg 94e seus gylf eui ueum ureu2 UP2S aui aie duo2 oi 4f uo 001 pue Ig useenieq pe qeisur eq eng Y201q Buriaous H 59 Tg pue zu SJ0128uuo2 OL 0300 sJsdun i2e eg epo Ugdj aiels i nejep aedun ou uarjuoj 910N 9SINTII duMSH ASNa LNOd dI 1 LINI NIET 8 90 NIG amp N2Z1 UO uoriean6rjuo 2 Te raes 8 90tid air 1 abe 58 224 ASPPSH e2e 481uI 7 GI ToL pog Jedung AOL SWL E suoriounj 041u0j suori2unj uote 51 pue 041003 ged 5 aan gat T Ko AIL SCH oar Doo oal A_04_051305 Ap UG130 A Jumper JP1 ions JTAG Connect 5 Interface Platform Flash tion FPGA Configura Figure A 4 57 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide U
16. 0 2008 3 XILINX 46 Chapter 12 Power Distribution Overall the 5V DC switching power adapter that connects to AC wall power powers the board A 3 3V regulator powered by the 5V DC supply provides power to the inputs of the 2 5V and 1 2V regulators Similarly the 3 3V regulator feeds all the Vcco voltage supply inputs to the FPGA s I O banks and powers most of the components on the board The 2 5V regulator supplies power to the FPGA s VccAux supply inputs The VccAUx voltage input supplies power to Digital Clock Managers DCMs within the FPGA and supplies some of the I O structures In specific all of the FPGA s dedicated configuration pins such as DONE PROG B CCLK and the FPGA s JTAG pins are powered by Vecaux The FPGA configuration interface on the board is powered by 3 3V Consequently the 2 5V supply has a current shunt resistor to prevent reverse current Finally a 1 2V regulator supplies power to the FPGA s Vccnr voltage inputs which power the FPGA s core logic The board uses three discrete regulators to generate the necessary voltages However various power supply vendors are developing integrated solutions specifically for Spartan 3 FPGAs Figure A 3 provides a detailed schematic of the various voltage regulators Similarly Figure A 6 shows the power decoupling capacitors www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 SC XILINX Chapter 13 Expansion Connector
17. 0 60 Hz AC Wall Adapter Included UG130_c1_01_042504 Figure 1 1 Xilinx Spartan 3 Starter Kit Board Block Diagram e PS 2 style mouse keyboard port Gi e Four character seven segment LED display 9 e Eight slide switches e Eight individual LED outputs e Four momentary contact push button switches 9 8 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Component Locations XILINX 50 MHz crystal oscillator clock source bottom side of board see Figure 1 3 Socket for an auxiliary crystal oscillator clock source Gei FPGA configuration mode selected via jumper settings Gei Push button switch to force FPGA reconfiguration FPGA configuration happens automatically at power on LED indicates when FPGA is successfully configured 3 Three 40 pin expansion connection ports to extend and enhance the Spartan 3 Starter Kit Board 3 See compatible expansion cards at www xilinx com products boards DO SPAR3 DK boards daughtercards htm Compatible with Digilent Inc peripheral boards www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral FPGA serial configuration interface signals available on the A2 and B1 connectors PROG B DONE INIT B CCLK DONE JTAG port for low cost download cable Digilent JTAG download debugging cable connects to PC parallel port JTAG download debug port compatible wit
18. 1 D back porch e back porch s Horizontal sync signal E front porch sets the retrace frequency UG130 c5 02 051305 Figure 5 2 CRT Display Timing Example The size of the beams the frequency at which the beam traces across the display and the frequency at which the electron beam is modulated determine the display resolution Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 23 UG130 v1 2 June 20 2008 SC XILINX Chapter 5 VGA Port Modern VGA displays support multiple display resolutions and the VGA controller dictates the resolution by producing timing signals to control the raster patterns The controller produces TTL level synchronizing pulses that set the frequency at which current flows through the deflection coils and it ensures that pixel or video data is applied to the electron guns at the correct time Video data typically comes from a video refresh memory with one or more bytes assigned to each pixel location The Spartan 3 Starter Kit board uses three bits per pixel producing one of the eight possible colors shown in Table 5 2 The controller indexes into the video data buffer as the beams move across the display The controller then retrieves and applies video data to the display at precisely the time the electron beam is moving across a given pixel As shown in Figure 5 2 the VGA controller generates the HS horizontal sync and VS vertical sync
19. 1 IO2 R6 9 IO1 T8 7 100 N7 5 CE1 chip enable IC10 P7 UB1 upper byte enable IC10 T4 LB1 lower byte enable IC10 P6 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com UG130 v1 2 June 20 2008 13 SC XILINX 14 Table 2 4 SRAM IC11 Connections Signal FPGA Pin 1015 N1 1014 M1 1013 K2 IO12 C3 IO11 F5 IO10 G1 IO9 E2 108 D2 107 D1 106 El 105 G2 104 1 103 K1 102 M2 101 N2 100 P2 CE2 chip enable IC11 N5 UB2 upper byte enable IC11 R4 LB2 lower byte enable IC11 P5 www xilinx com Chapter 2 Fast Asynchronous SRAM Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 3 Four Digit Seven Segment LED Display The Spartan 3 FPGA Starter Kit board has a four character seven segment LED display controlled by FPGA user I O pins as shown in Figure 3 1 Each digit shares eight common control signals to light individual LED segments Each individual character has a separate anode control input A detailed schematic for the display appears in Figure A 2 The pin number for each FPGA pin connected to the LED display appears in parentheses To light an individual signal drive the individual segment control signal Low along with the associated anode control signal for the individual character In Figure 3 1 for example the left most character displays the value 2 The digital values
20. 1 2 These push buttons are located along the lower edge of the board toward the right edge The switches are labeled BTN3 through BTNO Push button switch BTN3 is the left most switch BTNO the right most switch The push button switches connect to an associated FPGA pin as shown in Table 4 2 A detailed schematic appears in Figure A 2 Table 4 2 Push Button Switch Connections Push Button BTN3 User Reset BTN2 BTN1 BTNO FPGA Pin L14 L13 M14 M13 Pressing a push button generates a logic High on the associated FPGA pin Again there is no active debouncing circuitry on the push button The left most button BTN3 is also the default User Reset pin BTN3 electrically behaves identically to the other push buttons However when applicable BTN3 resets the provided reference designs Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 19 UG130 v1 2 June 20 2008 SC XILINX LEDs 20 Chapter 4 Switches and LEDs The Spartan 3 Starter Kit board has eight individual surface mount LEDs located above the push button switches indicated by 12 in Figure 1 2 The LEDs are labeled LED7 through LEDO LED7 is the left most LED LEDO the right most LED Table 4 3 shows the FPGA connections to the LEDs Table 4 8 LED Connections to the Spartan 3 FPGA LED LD7 LD6 LD5 LD4 LD3 LD2 LD1 LDO FPGA Pin P11 P12 N12 P13 N14 L12 P14 K12 The cathode of each LED connects to gr
21. 1 DSTB H16 J16 MB1 WRITE MB1 WAIT K16 K15 MB1 RESET MB1 INT L15 B3 PROG B FPGA PROG B DONE R14 N9 INIT FPGA DONE FPGA INIT B CCLK T15 M11 DIN FPGA CCLK Connects to A14 via 3902 resistor Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 51 UG130 v1 2 June 20 2008 SC XILINX Chapter 13 Expansion Connectors and Boards Expansion Boards Various expansion boards plug into the A1 A2 or B1 connectors as listed below 52 Spartan 3 Starter Kit Expansion Boards www xilinx com products boards DO SPAR3 DK boards daughtercards htm Digilent Expansion Boards www digilentinc com Products Catalog cfm Nav1 Products amp Nav2 Peripheral amp Cat Peripheral Digilent Breakout Probe Header TPH1 http www digilentinc com Products Catalog cfm Cat Accessory Digilent Breadboard DBB1 http www digilentinc com Products Catalog cfm Cat Accessory Digilent Wire wrap Board DWR1 http www digilentinc com Products Catalog cfm Cat Accessory Digilent SPP EPP ECP Parallel Port PIO1 http www digilentinc com Products Catalog cfm Nav1 Products amp Cat Older www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Appendix A Board Schematics This appendix provides the schematics for the Spartan 3 FPGA Starter Kit Board Figure A 1 A1 A2 and B1 Expansion Connectors Figure A 2 Slide Switches Push Buttons
22. 16AL 10T 10 ns SRAMs Configurable memory architecture Single 256Kx32 SRAM array ideal for MicroBlaze code images Two independent 256Kx16 SRAM arrays Individual chip select per device Individual byte enables 3 bit 8 color VGA display port 9 pin RS 232 Serial Port DB99 pin female connector DCE connector RS 232 transceiver level translator 7 Uses straight through serial cable to connect to computer or workstation serial port Second RS 232 transmit and receive channel available on board test points Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 7 UG130 v1 2 June 20 2008 XILINX Chapter 1 Introduction Digilent Low Cost 63 Parallel Port to JTAG Included Cable Parallel Cable IV 22 Low Cost JTAG 22 MutliPro Desktop Tool Download Cable JTAG Connector Connector A1 Expansion XILINX Header XCFO02S 2Mbit Configuration A2 Expansion 69 PROM gt Header Platform Flash B1 Expansion 19 Option Jumpers Header 256Kx16 Configuration 18 10ns SRAM DONE LED 256Kx16 0 PROGRAM 10ns SRAM A XILINX Push Button 8 color XC35200 Configuration VGA Port Spartan 3 Mode Select FPGA Jumpers 6 RS 232 Port RS 232 Serial Port Driver Auxiliary GB 6 Oscillator Socket Oscillator D I 4 Character 7 LED Segment A Push Button 8 Slide Switches 4 8 LEDs vcco LED Regulator Regulator Regulator 5 VDC 2A Supply 100 240V AC Input 5
23. 2 169 QE9 6223 269 689 889 S23 929 4nN1 ANTA gt 22 282 989 G89 ang 999 922 ANTAA 8 0 JPTIO O 1nN12 6 6 S22 pe 223 229 8 8 129 2 023 693 1 292 k 63 0 Z L 619 0 0 0 4 L 819 219 1 193 Jk 8 z 919 19 EI 2 0 8 4 2 Ru 89 Z3 G9 3 If Hf WH e 3 2i SE EIN EH 1j 33 ea kO oaan oaan 099N oaan oaan oaan Dm oaan oaan oaan 099N ogan oaan Dm oaan oaan ogan oaan oaan Dm oaan 099N oaan ogan x x x x x x x ANT99N ANI99N 1 ANI99N ANI99N ANI99N ANI99N 1 fAtddng 490 Qnagaoaaoaaaaaaaaaoaaaoaoaaoaaaaaoagaaoaaaooaaaoaaogco m t EES PIN Kl KEE ES x fas as x Yu 91L Lo E Power Decoupl A 06 051305 UG130 Ap tors ing Capac 6 A Figure 59 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide
24. ED AS IS WITH ALL FAULTS AND THE ENTIRE RISK AS TO ITS FUNCTION AND IMPLEMENTATION IS WITH YOU YOU ACKNOWLEDGE AND AGREE THAT YOU HAVE NOT RELIED ON ANY ORAL OR WRITTEN INFORMATION OR ADVICE WHETHER GIVEN BY XILINX OR ITS AGENTS OR EMPLOYEES XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DESIGN INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE TITLE AND NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOST DATA AND LOST PROFITS ARISING FROM OR RELATING TO YOUR USE OF THE DESIGN EVEN IF YOU HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES THE TOTAL CUMULATIVE LIABILITY OF XILINX IN CONNECTION WITH YOUR USE OF THE DESIGN WHETHER IN CONTRACT OR TORT OR OTHERWISE WILL IN NO EVENT EXCEED THE AMOUNT OF FEES PAID BY YOU TO XILINX HEREUNDER FOR USE OF THE DESIGN YOU ACKNOWLEDGE THAT THE FEES IF ANY REFLECT THE ALLOCATION OF RISK SET FORTH IN THIS AGREEMENT cc THAT XILINX WOULD NOT MAKE AVAILABLE THE DESIGN TO YOU WITHOUT THESE LIMITATIONS OF LIABILITY The Design is not designed or intended for use in the development of on line control equipment in hazardous environments requiring fail safe controls such as in the operation of nuclear facilities aircraft navigation or communications systems air traffic control life support or weapons systems High Risk App
25. G130 v1 2 June 20 2008 ICS Board Schemati Appendix A 8 8 1884s 3 oH 4o0uing 99 1488utbu3 002 21 2 een esee eH 0 009 49equnwN iueunoo p4eog 65 1 DUI wiet 002 iubra4Rdoj p4eog CG wuert ZA 1299 8 der 1299 8 NET EN 8d 80 9 die a S NIET G dEl G N ET G jdun G d6ez1 D NEZI Z0 8 d821 90 8 Nez D dZ D jdun G NZZ1 8 S3 8 4191 a tWMau G N1807 1 OI CDI TOI G AUER 1 V3129 T dzE1 St 5 1239 T NZE1 Ka T J3Un T NIET T de 1 T Ne 1 T de21 T Ne21 T d821 T N82Z1 WEEN Wa T deri v d0 1 ZQ v NET v dezT v NEZI d821 N8Z1 1d d oc v di81 1 y 1 1 zor TOI y ueg 2139 8 88 9 199 0 d r Q9 i3Hn 0 die 9 NI 1 9 deen Fwa 9 dez1 9 NeZ1 9 d821 9 N8Z1 9 dZZ1 DNA oj oj bu o of Z dev1 d A3un Z NOHT d d6 1 Z N6 1 Z dre Z NvZ1 d dezi Z NEZI Z dzi Z Ne21 Z die Z NIZ1 d dec d NOZI Z deT1 d A3un Z NEI Z dl E NTI Z J3un Z d9T1 Z N9T1 Z dre Z NIO1 TOI 2 weg 1 dar j3Hn NOT der NGC decl 6 J3Uun dec NECI decl 6 Nez dizl NIZI dec NOZI d611 E N6eT1 Jdun dZTl E NZTI d9T1 N9T1 d191 N1071 TOI 6 ueg 0 I ND m Oo 9 434N 9 dar 9 NOHT 9 d6 1 9 N6 1 9 dre 9 J3Un 9 NZI
26. MOOR 0 HISU IUW HISU IUN OQOOO0O000000000000000000000000000000000000 ac MOON OM UG130_ApA_01_051305 ion Connectors and B1 Expans A2 A1 1 Figure Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 54 UG130 v1 2 June 20 2008 XILINX 8 2 199ug 007 21 Z sieg se j y DUT yueTIbIq 00Z p4eog 65 SIN HN a a Lo om UG130 ApA 02 051305 Figure A 2 Slide Switches Push Buttons LEDs and Four Character 7 Segment Display 55 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Appendix A Board Schematics SC XILINX B E 5 6 006 2 eie g g 6 009 JSQUNN iueun2og HUE 40uing paeog CG 1 6 2 6 99 88UBU3 DUI ualra poez iubi4fdoj p4eog 665 UG130 ApA 03 042704 mes ZI9I ZIIINUJ 93 2 8402 40 n t INIDON JA 100 NI UNS 1096247 2 Z angr Jnr g anzz 28d N 2 gi T 0 hiddns 2900 pieoqhs IND ES ES As c xnu33n XIN 1S99881N7 0676 OJIN 10 NIN UG130 v1 2 June 20 2008 Spartan 3 FPGA Starter Kit Board User Guide JP2 Jumper Setting for PS 2 Port Voltage www
27. P1 DEFAULT The FPGA automatically boots from the Platform lt 0 0 0 gt E Flash xn Oo Or Mo M1 M2 The FPGA attempts to boot from a serial configuration source attached to either expansion connector A2 or B1 Slave Serial GND J8 Another device connected to either the A2 or B1 expansion eld B 8 w connector provides serial data and clock to load the FPGA 2 MO M1 M2 Master Parallel rGND J8 JP1 The FPGA attempts to boot from a parallel configuration source 11 0 w EEE attached to the B1 expansion connector E a Mo M1 M2 Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 www xilinx com 36 Program Push Button DONE Indicator LED XILINX Table 9 1 Header J8 Controls the FPGA Configuration Mode Continued Configuration Header J8 Jumper JP1 Mode Description M0 M1 M2 Settings Setting Slave Parallel GND J8 JP1 Another device connected to the B1 expansion connector 01 1 BE w ERES provides parallel data and clock to load the FPGA Ho MO M1 M2 JTAG The FPGA waits for configuration via the four wire JTAG GND J8 EEE JP1 lt 1 0 1 gt el ul interface E Mo M1 M2 Program Push Button DONE Indicator LED The Spartan 3 Starter Kit Board includes two FPGA configuration functions located near the VGA connector and the AC power input connector as shown in Figure 9 1 The PROG push button shown as 57 in Figure 9 1 drives the FPGA s PROG B progr
28. Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX XILINX Xilinx is disclosing this Document and Intellectual Property hereinafter the Design to you for use in the development of designs to operate on or interface with Xilinx FPGAs Except as stated herein none of the Design may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of the Design may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes Xilinx does not assume any liability arising out of the application or use of the Design nor does Xilinx convey any license under its patents copyrights or any rights of others You are responsible for obtaining any rights you may require for your use or implementation of the Design Xilinx reserves the right to make changes at any time to the Design as deemed desirable in the sole discretion of Xilinx Xilinx assumes no obligation to correct any errors contained herein or to advise you of any correction if such be made Xilinx will not assume any liability for the accuracy or correctness of any engineering or technical support or assistance provided to you in connection with the Design THE DESIGN IS PROVID
29. UG130 v1 2 June 20 2008 Appendix A Board Schematics SC XILINX 99 8 42 1899UuS 007 21 z eie esee eu g g Moy 0 609 ASQUNN iueun2o 40uing p4eog S 1 Duy 002 iubr4hdoj3 p48908H ES 6 8 4 9 9 6 4 T 140d U9n 011 21 0 0 8 UG130 ApA 07 051305 LINIZON ZX N9 IN 9x0N9 SxON9 3NOQ OQl x0N9 5199 3231 Ex0N9 9OHd SWL ZxON9 TONS aoloauuog JYI I9 I 4ed Seu 40128uuO2 ZSq p4eoqfay peo ON i4od je148S fi40sa22e 40 pesf pue eui UT 5 5 40128uuO2 If eu uo peddens 54e y GXL pue 2J0 9q pue z 3 A n 1310N 401238uuo2 330 Ee O t I0 SO I OD sag eTews4 ZETEXEW NIU INIO zinoa nunod 5 ES e3 29 19 19 68 TLNOY ZNIQ INIG Parallel Cable IV JTAG Interface 7 RS 232 Serial Port VGA Port PS 2 Port Figure A Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 60 UG130 v1 2 June 20 2008 SC XILINX 8 8 199us 6 002 2 eie sses sy g g 6 009 48qunw iueunoog 40uing 508 CS 1 99 99 A 08 051305 p DUI 00Z iubr4fdoj5 p4eog 65 UG130 Aj JnZv0 0 Jn270 0 3 2v0 0 3 Z2v0 0 1276 6 d 2v0 0 J 2990 6 J3n270 0 uojoeuuoo V ulm paseys ose ae OLD INVHS 01 slg erep 1ub
30. al Clock Managers DCMs e Chapter 3 Using Digital Clock Managers DCMs in Spartan 3 FPGAs www xilinx com support documentation user_guides ug331 pdf The oscillator socket indicated as 5 in Figure 1 2 accepts oscillators in an 8 pin DIP footprint Table 8 1 Clock Oscillator Sources Oscillator Source FPGA Pin 50 MHz ICA T9 Socket IC8 D9 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 35 UG130 v1 2 June 20 2008 XILINX Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings In most applications for the Spartan 3 FPGA Starter Kit Board the FPGA automatically boots from the on board Platform Flash memory whenever power is applied or the PROG push button is pressed However the board supports all the available configuration modes via the J8 header indicated as Gei in Figure 1 2 Table 9 1 provides the available option settings for the J8 header Additionally the JP1 jumper setting is required when using Master Serial configuration mode as further described in Platform Flash Jumper Options JP1 The default jumper settings for the board are e All jumpers in the J8 header are installed e The JP1 jumper is in the Default position Table 9 1 Header J8 Controls the FPGA Configuration Mode Golitiguration Header J8 Jumper JP1 i Mode Settinas Settin Description lt MO M1 M2 gt 8 Master Serial GND J8 CN J
31. amming pin When pressed the PROG push button forces the FPGA to reconfigure and reload it configuration data The DONE LED shown as 9 in Figure 9 1 connects to the FPGA s DONE pin and lights up when the FPGA is successfully configured DONE PROG UG130 c9 03 042704 Figure 9 1 The PROG Button and the DONE LED Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 37 UG130 v1 2 June 20 2008 XILINX Chapter 10 Platform Flash Configuration Storage The Spartan 3 FPGA Starter Kit board has an XCF02S serial configuration Flash PROM to store FPGA configuration data and potentially additional non volatile data including MicroBlaze application code To configure the FPGA from Platform Flash memory all three jumpers must be installed on the J8 header indicated as Gei in Figure 1 2 Platform Flash Jumper Options JP1 The Platform Flash has three optional settings controlled by the JP1 jumper which is located in the upper right hand corner of the board adjacent to the Platform Flash configuration PROM The JP1 jumper is indicated as in Figure 1 2 A detailed schematic is provided in Figure A 4 Table 10 1 summarizes the available options which are described in more detail below Table 10 1 Jumper JP1 Controls the Platform Flash Options Jumper 1 Option Setting Description Default S JP1 The FPGA boots from Platform Flash No additional data storage is available Flash R
32. an 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Expansion Connectors XILINX B1 Connector Pinout The B1 expansion connector is located on the right edge of the board as indicated by 9 in Figure 1 2 Table 13 4 provides the pinout for the B1 connector The FPGA connections are specified in parentheses Most of the B1 expansion connector pins connect only with the FPGA and are not shared Pins 36 through 40 include the signals required to configure the FPGA in Master or Slave Serial mode These same pins plus pins 5 7 9 11 13 15 17 19 and 20 provide the signals required to configure the FPGA in Master or Slave Parallel mode Table 13 4 Pinout for B1 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V Veco 3 3V Veco all banks C10 PB ADRO PB DBO T3 E10 PB ADR1 FPGA RD WR B config PB DB1 N11 C11 PB ADR2 FPGA D1 config PB DB2 P10 D11 PB ADR3 FPGA D2 config PB DB3 R10 C12 PB ADR4 FPGA D3 config PB DB4 T7 D12 PB ADR5 FPGA D4 config PB DB5 R7 E11 PB WE FPGA D5 config PB DB6 N6 B16 PB OE FPGA D6 config PB DB7 M6 R3 PB CS FPGA D7 config FPGA CS_B config PB CLK C15 C16 MB1 DBO MB1 DB1 D15 D16 MB1 DB2 MB1 DB3 E15 E16 MB1 DB4 MB1 DB5 F15 G15 MB1 DB6 MB1 DB7 G16 H15 MB1 ASTB MB
33. ast Asynchronous SRAM Address Bus Connections Write Enable and Output Enable Control Signals SRAM Data Signals Chip Enables and Byte Enables Chapter 3 Four Digit Seven Segment LED Display Chapter 4 Switches and LEDs Slide Switches Push Button Switches Chapter 5 VGA Port Signal Timing for a 60Hz 640x480 VGA Display VGA Signal Timing assed 0 End ere d eC tape EE Chapter 6 PS 2 Mouse Keyboard Port laa ee ee a MOUSE dansante freres A Mollape SUPPLY int ea eai e ARR eed dg Reed Chapter 7 RS 232 Serial Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions FPGA Configuration Mode Settings Program Push Button DONE Indicator LED Spartan 3 FPGA Starter Kit Board User Guide www xilinx com UG130 v1 2 June 20 2008 SC XILINX Chapter 10 Platform Flash Configuration Storage Platform Flash Jumper Options JP1 38 Default Opio ioris cerea eee e ERR EE CR LSE ited 38 Flash Read Option i i oce RECO ebd RC eee C DER RARE CHARGE td 39 sable Opon eoe d ee EI SUPR FR ER wee ede E RE E 40 Chapter 11 JTAG Programming Debugging Ports TEAG Heade
34. d and moving down represents a negative value The XS and YS bits in the status byte define the sign of each value where a 1 indicates a negative value Y values YS 0 X values X values XS 1 XS 0 Y values YS 1 UG130 c6 05 042404 Figure 6 5 The Mouse Uses a Relative Coordinate System to Track Movement The magnitude of the X and Y values represent the rate of mouse movement The larger the value the faster the mouse is moving The XV and YV bits in the status byte indicate when the X or Y values exceed their maximum value an overflow condition A 1 indicates when 30 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Voltage Supply XILINX an overflow occurs If the mouse moves continuously the 33 bit transmissions repeat every 50 ms or so The L and R fields in the status byte indicate Left and Right button presses A 1 indicates that the associated mouse button is being pressed The following site contains additional information on interfacing to a PS 2 style mouse e The PS 2 Mouse Interface http www computer engineering org index php title PS 2_Mouse_Interface Voltage Supply Spartan 3 FPGA Starter Kit Board User Guide Most modern keyboards and mice work equally well from a 3 3V or 5V supply The voltage supply for the PS 2 port is selectable via the JP2 jumper indicated as in Figure 1 2 located immediately above the PS 2 connector along the r
35. driving the display in this example are shown in blue The AN3 anode control signal is Low enabling the control inputs for the left most character The segment control inputs A through G and DP drive the individual segments that comprise the character A Low value lights the individual segment a High turns off the segment A Low on the A input signal lights segment a of the display The anode controls for the remaining characters AN 2 0 are all High and these characters ignore the values presented on A through G and DP AN3 E13 AN2 F14 AN1 G14 ANO D14 J1 c N15 P16 00 00 UG130_c3_01_042704 Figure 3 1 Seven Segment LED Digit Control Table 3 1 lists the FPGA connections that drive the individual LEDs comprising a seven segment character Table 3 2 lists the connections to enable a specific character Table 3 3 shows the patterns required to display hexadecimal characters Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 15 UG130 v1 2 June 20 2008 XILINX Chapter 3 Four Digit Seven Segment LED Display Table 3 1 FPGA Connections to Seven Segment Display Active Low Segment FPGA Pin A E14 B G13 C N15 D P15 E R16 F F13 G N16 DP P16 Table 3 2 Digit Enable Anode Control Signals Active Low Anode Control AN3 AN2 AN1 ANO FPGA Pin E13 F14 G14 D14 Table 3 3 Display Characters and Resulting LED Segment Contr
36. ead gp1 The FPGA boots from Platform Flash which is permanently enabled The FPGA can read additional data from Platform Flash Disable JP1 Jumper removed Platform Flash is disabled Other configuration data source Esa provides FPGA boot data Default Option For most applications this is the default jumper setting As shown in Figure 10 1 the Platform Flash is enabled only during configuration when the FPGA s DONE pin is Low When the DONE pin goes High at the end of configuration the Platform Flash is disabled and placed in low power mode Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 38 UG130 v1 2 June 20 2008 Flash Read Option Spartan 3 FPGA DIN DO INIT B DONE CCLK SC XILINX Platform Flash JP1 Dd DO Default OE RESET CE CLK UG130_c10_01_060704 Figure 10 1 Default Platform Flash Option Flash Read Option Spartan 3 FPGA Starter Kit Board User Guide The Spartan 3 Starter Kit Board includes a 2Mbit Platform Flash configuration PROM The XC35200 FPGA on the board only requires slightly less than 1Mbit for configuration data The remainder of the Platform Flash is available to store other non volatile data such as revision codes serial numbers coefficients an Ethernet MAC ID or code for an embedded processor such as MicroBlaze within the FPGA To allow the FPGA to read from Platform Flash after configuration the JP1jumper must be properly positioned
37. ears in Figure A 8 ISSI 256Kx16 SRAM 10 ns see Table 2 3 CJ 4 I O 15 0 A 17 0 GE C10 UB LB WE OE Spartan 3 FPGA ISSI 256Kx16 SRAM 10 ns see Table 2 4 lt gt see Table 21 gt xx FPGA pin number UG130 c2 01 042604 Figure 2 1 FPGA to SRAM Connections Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 11 UG130 v1 2 June 20 2008 3 XILINX Chapter 2 Fast Asynchronous SRAM The SRAM array forms either a single 256Kx32 SRAM memory or two independent 256Kx16 arrays Both SRAM devices share common write enable WE output enable OE and address A 17 0 signals However each device has a separate chip select enable CE control and individual byte enable controls to select the high or low byte in the 16 bit data word UB and LB respectively The 256Kx32 configuration is ideally suited to hold MicroBlaze instructions However it alternately provides high density data storage for a variety of applications such as digital signal processing DSP large data FIFOs and graphics buffers Address Bus Connections 12 Both 256Kx16 SRAMs share 18 bit address control lines as shown in Table 2 1 These address signals also connect to the A1 Expansion Connector see Expansion Connectors page 47 Table 2 1 External SRAM Address Bus Connections to Spartan 3 FPGA
38. ents Table B 1 lists the major components on the Spartan 3 FPGA Starter Kit Board including full part numbers and links to complete device data sheets Table B 1 Major Components and Data Sheet Links Device Vendor Part Number Description Data Sheet Link O Xilinx Inc XC3S200 4FT256C Spartan 3 FPGA IC1 http www xilinx com support documentation data_sheets ds099 pdf 9 Xilinx Inc XCF02SVO20C Platform Flash Configuration Flash PROM IC9 http www xilinx com support documentation data sheets ds123 pdf Integrated Silicon IS61LV25616AL 10T 256Kx16 Fast Asynchronous SRAM IC10 IC11 Solutions Inc ISSI http www issi com pdf 61LV25616AL pdf Maxim Intersil MAX3232 ICL3232 Dual Channel RS 232 Voltage Translator IC14 http pdfserv maxim ic com en ds MAX3222 MAX3241 pdf http www ntersil com data fn fn4805 pdf 3 Epson SG 8002JF 50 MHz Crystal Oscillator IC4 http www eea epson com portal pls portal docs 1 793426 PDF Interex APA 101M 05 5V Switching Regulator G National LM1086CS ADJ 3 3V Regulator IC5 Semiconductor http www national com mpf LM LM1086 html Gi STMicroelectronics LF25CDT 2 5V Regulator IC3 http www st com stonline books pdf docs 2574 pdf Fairchild FAN1112 1 2V Regulator IC12 Semiconductor http www fairchildsemi com ds FA FAN1112 pdf Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008
39. expansion board connected to one of the expansion connectors 40 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 11 JTAG Programmingl Debugging Ports The Spartan 3 FPGA Starter Kit board includes a JTAG programming and debugging chain Both the Spartan 3 FPGA and the Platform Flash devices are part of the JTAG chain as shown in Figure 11 1 Additionally there are two JTAG headers for driving the JTAG signals from various supported JTAG download and debugging cables A Digilent JTAG3 low cost parallel to JTAG cable is included as part of the kit and connects to the J7 header Digilent JTAG3 Parallel Cable 3 Header J7 Parallel Cable IV MultiPro Spartan 3 FPGA PlatformFlash Desktop XC3S400FT256C XCF02S oo Header J5 x JTAG Header J7 Header pin number UG130 cii 01 042504 Figure 11 1 Spartan 3 Starter Kit Board JTAG Chain This J7 JTAG header consists of 0 1 inch stake pins and is indicated as in Figure 1 2 located toward the top edge of the board directly below the two expansion connectors The Digilent low cost parallel port to JTAG cable fits directly over the J7 header stake pins as shown in Figure 11 2 When properly fitted the cable is perpendicular to the board Make sure that the signals at the end of the JTAG cable align with the labe
40. h the Xilinx Parallel Cable IV and MultiPRO Desktop Tool AC power adapter input for included international unregulated 5V power supply Power on indicator LED Gei On board 3 3V 2 5V and 1 2V G3 regulators Component Locations Figure 1 2 and Figure 1 3 indicate the component locations on the top side and bottom side of the board respectively Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 9 UG130 v1 2 June 20 2008 Chapter 1 Introduction A1 Expansion Connector A2 Expansion Connector HIE EE EHE EHE e HELLE E E E EG E gt Daa EA ES A EM XX A 6s Ya A Be 2Mbit oo PlatformFlash G7 XILINX 1 XC3S200 LONE FPGA PROG POWER POWER eg RS ug130 01 02 042704 B1 Expansion Connector 2 Pn m 1 Figure 1 2 Xilinx Spartan 3 Starter Kit Board Top Side 256Kx16 SRAM 256Kx16 SRAM ug130_c1_03_042704 Figure 1 3 Xilinx Spartan 3 Starter Kit Board Bottom Side 10 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 2 Fast Asynchronous SRAM The Spartan 3 FPGA Starter Kit board has a megabyte of fast asynchronous SRAM surface mounted to the backside of the board The memory array includes two 256Kx16 ISSI IS61LV25616AL 10T 10 ns SRAM devices as shown in Figure 2 1 A detailed schematic app
41. he Spartan 3 Starter Kit uses only stake pins The outline of the keyed connector appears around the J5 header as shown in Figure 11 3 When properly inserted the keyed header matches the outline on the board and the ribbon cable crosses over the top edge of the board The red colored lead indicates pin 1 on the cable and should be on the left side 42 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 XILINX Red trace sf indicates pin 1 Parallel Cable IV Notch on outline JTAG matches key on header 06180 011 098 4 Figure 11 3 Use 14 Pin Ribbon Cable to Connect Parallel Cable IV or the MultiPro Desktop Tool to the J5 Header Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 43 UG130 v1 2 June 20 2008 A XILINX Chapter 11 JTAG Programming Debugging Ports 44 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 12 Power Distribution AC Wall Adapter The Spartan 3 FPGA Starter Kit includes an international ready AC wall adapter that produces a 5V DC output Connect the AC wall adapter to the barrel connector along the left edge of the board indicated as in Figure 1 2 There is no power switch to the board To disconnect power remove the AC adapter from the wall or disconnect the barrel connector The POWER indicator LED shown as Gei in Figure 1 2
42. he following site contains more information on PS 2 keyboard interfaces e The PS 2 Keyboard Interface http www computer engineering org index php title PS 2_Keyboard_Interface Mouse A mouse generates a clock and data signal when moved otherwise these signals remain High indicating the Idle state Each time the mouse is moved the mouse sends three 11 bit words to the host Each of the 11 bit words contains a 0 start bit followed by 8 data bits LSB first followed by an odd parity bit and terminated with a 1 stop bit Each data transmission contains 33 total bits where bits 0 11 and 22 are 0 start bits and bits 10 21 and 32 are 1 stop bits The three 8 bit data fields contain movement data as shown in Figure 6 4 Data is valid at the falling edge of the clock and the clock period is 20 to 30 KHz Mouse status byte p X direction byte SH E Y direction byte e 1 o elei v pjvspervv e 1 o Tal xt x2 xa a gt 6 d ET Start bit Stop bit Stop bit Stop bit Idle state Start bit Start bit Idle state UG130 c6 04 042404 Figure 6 4 PS 2 Mouse Transaction As shown in Figure 6 5 a PS 2 mouse employs a relative coordinate system wherein moving the mouse to the right generates a positive value in the X field and moving to the left generates a negative value Likewise moving the mouse up generates a positive value in the Y fiel
43. ht permitivity through the crystal on a pixel by pixel basis Although the following description is limited to CRT displays LCD displays have evolved to use the 22 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 Signal Timing for a 60Hz 640x480 VGA Display XILINX Current through the horizontal deflection coil time same signal timings as CRT displays Consequently the following discussion pertains to both CRTs and LCD displays Within a CRT display current waveforms pass through the coils to produce magnetic fields that deflect electron beams to transverse the display surface in a raster pattern horizontally from left to right and vertically from top to bottom As shown in Figure 5 2 information is only displayed when the beam is moving in the forward direction left to right and top to bottom and not during the time the beam returns back to the left or top edge of the display Much of the potential display time is therefore lost in blanking periods when the beam is reset and stabilized to begin a new horizontal or vertical display pass pixel 0 639 640 pixels are displayed each time the beam traverses the screen VGA Display Retrace No information pixel 479 0 pixel 479 639 is displayed during this time Stable current ramp Information is displayed during this time Total horizontal time DUC Horizontal display time retrace time de
44. ight edge The 3 3V setting is preferred as the FPGA s output signals operate from the 3 3V supply The JP2 jumper should be positioned as shown in Table 6 5 by default Table 6 5 PS 2 Port Supply Voltage Options PS 2 Port Jumper JP2 Supply Voltage Setting 3 3V gt JP2 DEFAULT s 5V gt JP2 T 2 Some older keyboards and mice are 5V only Consequently the JP2 jumper should be set for 5V operation as shown in Table 6 5 The Spartan 3 FPGA can tolerate 5V signals due to the 270Q series resistors on the PS 2 data and clock signals connected to the FPGA See the schematic in Figure A 7 for more details www xilinx com 31 UG130 v1 2 June 20 2008 XILINX Chapter 6 PS 2 Mouse Keyboard Port 32 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 7 RS 232 Serial Port The Spartan 3 FPGA Starter Kit board has an RS 232 serial port The RS 232 transmit and receive signals appear on the female DB9 connector labeled J2 indicated as in Figure 1 2 The connector is a DCE style port and connects to the DB9 DTE style serial port connector available on most personal computers and workstations Use a standard straight through serial cable to connect the Spartan 3 Starter Kit board to the PC s serial port Pin 5 Pin 9 DB9 DB9 Serial Port Connector Connector Maxim MAX3232 front view RS232 Voltage Translator Spartan 3 FPGA DOUT1 gt DINI
45. ing the FPGA configuration process A2 Connector Pinout The A2 expansion connector is located along the top edge of the board on the right as indicated by in Figure 1 2 Table 13 3 provides the pinout for the A2 connector The FPGA connections are specified in parentheses Most of the A2 expansion connector pins connect only with the FPGA and are not shared Pin 35 connects to the auxiliary clock socket if an oscillator is installed in the socket Pins 36 through 40 include the signals required to configure the FPGA in Master or Slave Serial mode Table 13 3 Pinout for A2 Expansion Connector Schematic Name FPGA Pin Connector FPGA Pin Schematic Name GND VU 5V Veco 43 3V Veco all banks E6 PA IO1 PA IO2 D5 C5 PA IO3 PA IO4 D6 C6 PA IO5 PA IO6 E7 C7 PA IO7 PA IO8 D7 C8 PA IO9 PA IO10 D8 C9 PA IO11 PA IO12 D10 A3 PA IO13 PA IO14 B4 A4 PA IO15 PA IO16 B5 A5 PA IO17 PA IO18 B6 B7 MA2 DB0 MA2 DB1 A7 B8 MA2 DB2 MA2 DB3 A8 A9 MA2 DB4 MA2 DB5 B10 A10 MA2 DB6 MA2 DB7 B11 B12 MA2 ASTB MA2 DSTB A12 B13 MA2 WRITE MA2 WAIT A13 B14 MA2 RESET MA2 INT GCK4 D9 B3 PROG B Oscillator socket FPGA PROG_B DONE R14 N9 INIT FPGA DONE FPGA INIT_B CCLK T15 M11 DIN FPGA CCLK Connects to A14 via 390Q resistor 50 www xilinx com Spart
46. le Jamo esimeylT 40199uu09 V UM Suonoeuuoo peueys e eu souoo 43M 30 pue saul sseJppe WYHS ALON ER 1 sg 3ueg uo zg1 pue zgn z35 g ueg uo 197 pue gn 129 5 0 9 n ig 0 GJ as od cri cn ad Fas ca an o G ueg e 19905 uo 6OI T4 Z pue 9 fg ueq G iesus 6 4 pue 9 xueq fG ieaus 5 4 pue 9 3ueq G 19905 eeg aj aja aaa a ccc pue 9 3ueq G i1eaus 9525 a a d 4 41 4 4 41 1 41 411 is Rs A A A A A cd pakaka gt 21 24 2424 61 2x256Kx16 Fast Asynchronous SRAM Interface www xilinx com 8 Figure A Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 T T 1884 6002 9 6 PFT 95e818 ebeir 1 au uerrPrgd egoz z00Z ur do Appendix A Board Schematics SC XILINX 21qe2 jo pue Jd ie pei2ous side buriue 4boag gbeip SANTO zJ T9 94e ZId Tid 6d 1910N w 1601 1 ioo jo 5 5 o GZTZSZTIN ZTZMZE IN Sa 1 ZTZMZEN 6 9 UZ2I AA oc WE UG130 ApA 09 042604 Figure A 9 Digilent JTAG3 Low Cost JTAG Download Debug Cable Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 62 UG130 v1 2 June 20 2008 XILINX Appendix B Reference Material for Major Compon
47. lications Xilinx specifically disclaims any express or implied warranties of fitness for such High Risk Applications You represent that use of the Design in such High Risk Applications is fully at your risk 2004 2008 Xilinx Inc All rights reserved XILINX the Xilinx logo and other designated brands included herein are trademarks of Xilinx Inc PowerPC is a trademark of IBM Corp and used under license PCI PCI X and PCI EXPRESS are registered trademarks of PCI SIG All other trademarks are the property of their respective owners Some portions reproduced by permission from Digilent Inc Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 The following table shows the revision history for this document Version Revision 04 26 04 1 0 Initial Xilinx release 06 07 04 1 0 1 Minor modifications for printed release 07 21 04 1 0 2 Added information on auxiliary serial port connections to Chapter 7 05 13 05 1 1 Clarified that SRAM IC10 shares eight lower data lines with A1 connector 06 20 08 1 2 Corrected A1 pins in Table 2 2 Updated links Spartan 3 FPGA Starter Kit Board User Guide www xilinx com UG130 v1 2 June 20 2008 Table of Contents Preface About This Guide Guide Contents EE Chapter 1 Introduction Key Components and Features Component Locations 0 e eener eye best A 4 vx d e P RR oe ER A og Chapter 2 F
48. line has a series resistor to provide 3 bit color with one bit each for Red Green and Blue The series resistor uses the 75Q VGA cable termination to ensure that the color signals remain in the VGA specified OV to 0 7V range The HS and VS signals are TTL level Drive the R G and B signals High or Low to generate the eight possible colors shown in Table 5 2 Table 5 2 3 Bit Display Color Codes Red R Green G Blue B Resulting Color 0 0 0 Bak 0 0 1 Blue 0 1 0 Green 0 1 1 Cyan 1 0 0 Red 1 0 1 Magenta 1 1 0 Yellow VGA signal timing is specified published copyrighted and sold by the Video Electronics Standards Association VESA The following VGA system and timing information is provided as an example of how the FPGA might drive VGA monitor in 640 by 480 mode For more precise information or for information on higher VGA frequencies refer to documents available on the VESA website or other electronics websites e Video Electronics Standards Association http www vesa org e VGA Timing Information http www epanorama net documents pc vga timing html Signal Timing for a 60Hz 640x480 VGA Display CRT based VGA displays use amplitude modulated moving electron beams or cathode rays to display information on a phosphor coated screen LCD displays use an array of switches that can impose a voltage across a small amount of liquid crystal thereby changing lig
49. ls listed on the board The other end of the Digilent cable connects to the PC s parallel port The Digilent cable is directly compatible with the Xilinx iMPACT software The schematic for the Digilent cable appears in Figure A 9 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 41 UG130 v1 2 June 20 2008 A XILINX Chapter 11 JTAG Programming Debugging Ports 17 5 30 UG130 c11 02 042704 Figure 11 2 Digilent JTAG Cable Provided with Kit Connects to the J7 Header The J7 header also supports the Xilinx Parallel Cable 3 PC3 download debugging cable when using the flying leaders Again make sure that the signals at the end of the JTAG cable align with the labels listed on the board Figure A 4 provides a detailed schematic of the J7 header and the JTAG programming chain Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 The J5 header shown as Ga in Figure 1 2 supports the Xilinx download debugging cable listed below e Parallel Cable IV PC IV http www xilinx com products devkits HW PC4 htm Use the 14 pin ribbon cable supplied with both cables to connect to the J5 header DO NOT use the flying leads that are also provided with some cables Although the MultiPro Desktop Tool and the Parallel Cable IV support multiple FPGA configuration modes the Spartan 3 Starter Kit board only supports the JTAG configuration method The header is designed for a keyed socket However t
50. n Figure 1 2 Figure 6 1 shows the PS 2 connector and Table 6 1 shows the signals on the connector Only pins 1 and 5 of the connector attach to the FPGA A detailed schematic appears in Figure A 7 UG130 c6 01 042404 Figure 6 1 PS 2 DIN Connector Table 6 1 PS 2 Connections to the Spartan 3 FPGA PS 2 DIN Pin Signal FPGA Pin 1 DATA PS2D M15 2 Reserved 3 GND GND 4 Voltage Supply 5 CLK PS2C M16 6 Reserved Both a PC mouse and keyboard use the two wire PS 2 serial bus to communicate with a host device the Spartan 3 FPGA in this case The PS 2 bus includes both clock and data Both a mouse and keyboard drive the bus with identical signal timings and both use 11 bit words that include a start stop and odd parity bit However the data packets are organized differently for a mouse and keyboard Furthermore the keyboard interface allows bidirectional data transfers so the host device can illuminate state LEDs on the keyboard The PS 2 bus timing appears Table 6 2 and Figure 6 2 The clock and data signals are only driven when data transfers occur and otherwise they are held in the idle state at logic High The timings define signal requirements for mouse to host communications and Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 27 UG130 v1 2 June 20 2008 3 XILINX Keyboard 28 Chapter 6 PS 2 Mouse Keyboard Port bidirectional keyboard communications As shown in
51. nate the associated keyboard LED Table 6 4 Keyboard LED Control 7 6 5 4 3 2 1 0 Caps Num Scroll denoted Lock Lock Lock EE Echo Upon receiving an echo command the keyboard replies with the same scan code EE F3 Set scan code repeat rate The keyboard acknowledges receipt of an F3 by returning an FA after which the host sends a second byte to set the repeat rate FE Resend Upon receiving a resend command the keyboard resends the last scan code sent FF Reset Resets the keyboard The keyboard sends data to the host only when both the data and clock lines are High the Idle state Because the host is the bus master the keyboard checks whether the host is sending data before driving the bus The clock line can be used as a clear to send signal If the host pulls the clock line Low the keyboard must not send any data until the clock is released The keyboard sends data to the host in 11 bit words that contain a 0 start bit followed by eight bits of scan code LSB first followed by an odd parity bit and terminated with a 1 stop bit When the keyboard sends data it generates 11 clock transitions at around 20 to 30 kHz and data is valid on the falling edge of the clock as shown in Figure 6 2 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 29 UG130 v1 2 June 20 2008 XILINX Chapter 6 PS 2 Mouse Keyboard Port T
52. ol Values Character a b c d e f g 0 0 0 0 0 0 0 1 1 0 0 1 1 1 1 2 0 0 1 0 0 1 0 3 0 0 0 0 1 1 0 4 1 0 0 1 1 0 0 5 0 1 0 0 1 0 0 6 0 1 0 0 0 0 0 7 0 0 0 1 1 1 1 8 0 0 0 0 0 0 0 9 0 0 0 0 1 0 0 A 0 0 0 1 0 0 0 b 1 1 0 0 0 0 0 C 0 1 1 0 0 0 1 d 1 0 0 0 0 1 0 E 0 1 1 0 0 0 0 F 0 1 1 1 0 0 0 16 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 SC XILINX The LED control signals are time multiplexed to display data on all four characters as shown in Figure 3 2 Present the value to be displayed on the segment control inputs and select the specified character by driving the associated anode control signal Low Through persistence of vision the human brain perceives that all four characters appear simultaneously similar to the way the brain perceives a TV display ANS AN2 AN1 BGDERGDP DISP3 2 pisPt DISPO UG130 c3 02 042404 Figure 3 2 Drive Anode Input Low to Light an Individual Character This scanning technique reduces the number of I O pins required for the four characters If an FPGA pin were dedicated for each individual segment then 32 pins are required to drive four 7 segment LED characters The scanning technique reduces the required I O down to 12 pins The drawback to this approach is that the FPGA logic must continuously scan data out to the displays a small price
53. ound via a 27062 resistor To light an individual LED drive the associated FPGA control signal High which is the opposite polarity from lighting one of the 7 segment LEDs www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 5 VGA Port The Spartan 3 FPGA Starter Kit board includes a VGA display port and DB15 connector indicated as in Figure 1 2 Connect this port directly to most PC monitors or flat panel LCD displays using a standard monitor cable Pin 5 Pin 10 Pin 15 DB15 VGA Connector DB15 front view Connector 2700 E ANN o R R12 270Q n ANN oG T12 2700 2 AAN o B Ri Horizontal Sync O HS R9 Vertical Sync vs T10 xx FPGA pin number V GND UG130_c5_01_042604 Figure 5 1 VGA Connections from Spartan 3 Starter Kit Board As shown in Figure 5 1 the Spartan 3 FPGA controls five VGA signals Red R Green G Blue B Horizontal Sync HS and Vertical Sync VS all available on the VGA connector The FPGA pins that drive the VGA port appear in Table 5 1 A detailed schematic is in Figure A 7 Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 21 UG130 v1 2 June 20 2008 XILINX Chapter 5 VGA Port Table 5 1 VGA Port Connections to the Spartan 3 FPGA Signal FPGA Pin Red R R12 Green G T12 Blue B R11 Horizontal Sync HS R9 Vertical Sync VS T10 Each color
54. rage Chapter 11 JTAG Programming Debugging Ports Chapter 12 Power Distribution Chapter 13 Expansion Connectors and Boards Appendix A Board Schematics Appendix B Reference Material for Major Components Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 5 UG130 v1 2 June 20 2008 XILINX Preface About This Guide 6 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 1 Introduction The Xilinx Spartan 3 FPGA Starter Kit provides a low cost easy to use development and evaluation platform for Spartan 3 FPGA designs Key Components and Features Figure 1 1 shows the Spartan 3 Starter Kit board which includes the following components and features 200 000 gate Xilinx Spartan 3 XC3S200 FPGA in a 256 ball thin Ball Grid Array package XC35200FT256 1 4 320 logic cell equivalents Twelve 18K bit block RAMs 216K bits Twelve 18x18 hardware multipliers Four Digital Clock Managers DCMs Up to 173 user defined I O signals 2Mbit Xilinx XCFO2S Platform Flash in system programmable configuration PROM 1Mbit non volatile data or application code storage available after FPGA configuration Jumper options allow FPGA application to read PROM data or FPGA configuration from other sources 1M byte of Fast Asynchronous SRAM bottom side of board see Figure 1 3 2 Two 256Kx16 ISSI IS61LV256
55. s and Boards Expansion Connectors The Spartan 3 FPGA Starter Kit board has three 40 pin expansion connectors labeled A1 A2 and B1 The A1 and A2 connectors indicated as and respectively in Figure 1 2 are on the top edge of the board Connector Al is on the top left and A2 is on the top right The Bl connector indicated as Gei in Figure 1 2 is along the right edge of the board A1 Expansion Connector A2 Expansion Connector E x O E 5 Al mm z 5 x Li mm n UG130 c12 01 042704 Figure 13 1 Spartan 3 Starter Kit Board Expansion Connectors Table 13 1 summarizes the capabilities of each expansion port Port A1 supports a maximum of 32 user I O pins while the other ports provide up to 34 user I O pins Some pins are shared with other functions on the board which may reduce the effective I O count for specific applications For example pins on the A1 port are shared with the SRAM address signals with the SRAM OE and WE control signals and with the eight least significant data signals to SRAM IC10 only Spartan 3 FPGA Starter Kit Board User Guide www xilinx com 47 UG130 v1 2 June 20 2008 XILINX Chapter 13 Expansion Connectors and Boards Table 13 1 Expansion Connector Features Connector User 1 0 SRAM JTAG Serial Configuration Parallel Configuration A1 32 Address y OE WE Data 7 0 to IC10 only A2 34 B1 34 y y
56. s available on two 0 1 inch stake pins indicated as J1 in the schematic and in Figure 1 2 The J1 stake pins are in the lower left corner of the board to the right of the DB9 serial connector below the Maxim RS 232 voltage translator and to the left of the individual LEDs The transmitter output from the Maxim device drives the bottom stake pin while the receiver input connects to the top stake pin The FPGA auxiliary RS 232 connections to the Maxim device appear in Table 7 1 with signals RXD A and TXD A Ignore the pin numbers listed on the silkscreen markings next to the stake pins as these apply to the connections to the DB9 connector Place a jumper across the stake pins for an easy loop back test Alternately create custom serial ports by attaching the stake pins to other types of serial connectors such as male or female DB9 or DB25 cable connectors or even create null modem connections www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Chapter 6 Clock Sources The Spartan 3 FPGA Starter Kit board has a dedicated 50 MHz Epson SG 8002 F series clock oscillator source and an optional socket for another clock oscillator source Figure A 5 provides a detailed schematic for the clock sources The 50 MHz clock oscillator is mounted on the bottom side of the board indicated as 12 in Figure A 5 Use the 50 MHz clock frequency as is or derive other frequencies using the FPGAs Digit
57. t DU cesis ds quee pis dug het he ortae aci ien eei id 41 Parallel Cable IV MultiPro Desktop Tool JTAG Header J5 42 Chapter 12 Power Distribution AC Wall Adapteta315 ier ECra d CER CUR bor C eco Cena ea 45 Voltage Regulatosse uie dup Ek libanais edi Race COMPE a dede d 45 Chapter 13 Expansion Connectors and Boards Expansion Connectors duds sos orbes reci sepu sheni neme remi ER Ed e E 47 AT Connector EInoit ite eode 0 Edict dati ds 49 A2 Connector PINOUE at ierre serii kaki Mb ute Vat Xue veda eate ves Vat 50 bI Connector Pinot cope oa ee pea depend e dus dae s edd 51 Expansion 09708 si 4 0 VEER e teg bed eo ee OE e d gets 52 Appendix A Board Schematics Appendix B Reference Material for Major Components 4 www xilinx com Spartan 3 FPGA Starter Kit Board User Guide UG130 v1 2 June 20 2008 XILINX Preface About This Guide This user guide describes the components and operation of the Spartan 3 FPGA Starter Kit Board Guide Contents This manual contains the following chapters Chapter 1 Introduction Chapter 2 Fast Asynchronous SRAM Chapter 3 Four Digit Seven Segment LED Display Chapter 4 Switches and LEDs Chapter 5 VGA Port Chapter 6 PS 2 Mouse Keyboard Port Chapter 7 RS 232 Serial Port Chapter 8 Clock Sources Chapter 9 FPGA Configuration Modes and Functions Chapter 10 Platform Flash Configuration Sto
Download Pdf Manuals
Related Search