Home

TeSys T LTM R Motor Management Controller

1. LOAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 4 LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback Latch HMI Keypad info LOAD_BIT 1020 12 Aux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Aux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 1639507 12 2006 289 Pre Defined Structured Text Programs Structured Text Program cont d Generate Global Stop in Temp Reg 4 5 LOAD_TMP BIT 3 1 ND_BIT 455 2 R_TMP_BIT 13 14 R_BIT 456 5 R_BIT 453 1 R_BIT 453 2 ET TMP_BIT 4 5 OAD_NOT_TMP_BIT 3 0 D_NOT_TMP BIT D_NOT_TMP BIT R_TMP_BIT 4 5 ET TMP_BIT 4 5 OAD_NOT_BIT 1200 0 ND_BIT 456 4 R_TMP_BIT 4 5 ET TMP_BIT 4 5 D TOAG OO Sek 3 2 no EEE gt no HMI Active
2. 0 PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC 1 HMT 2 TS terminal strip Temp 4 as state bits group 1 fl 0 Control Transfer in process 1 LO1 PLC fallback value ff 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value 5 Global Stop 6 Stop1 7 Stop2 8 Run1 9 Run2 10 Forward 11 Reverse 1 12 Reversing Timer Active Temp 5 as state bits group 2 Temp 9 10 11 as Forward Reverse Timer 1639507 12 2006 229 Pre Defined Structured Text Programs Structured Text Program cont d Temp 12 as INPUT History 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 4 HMI Run 2 LA 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONSET status Low to High timer Temp 52 as ONSET status High to Low timer Temp 53 Latch Temp 54 as ONSET status 704 Runil Run2 Jd Save Requested Control in Temp 2 LOAD_BIT 683 8 TS HMI SET_TMP BIT 0 1 Debounce TS HMI in scratch LOAD_BIT 457 5 LI6 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced
3. Generate Run 1 PLC mode LOAD_TMP_BIT 12 1 Input history AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 0 Save previous history LOAD_BIT 704 0 PLC Network Runl AND_TMP_BIT 12 12 Power up Done AND_NOT_TMP_BIT 4 6 NOT Stop 1 SET_TMP_BIT 12 1 Save new history AND_NOT_TMP BIT 12 0 NOT previous history AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl HMI mode LOAD_TMP_BIT 12 3 Input history SET_TMP_BIT 12 0 Save previous history LOAD_TMP_BIT 13 12 HMI Runl SET_TMP_BIT 12 3 Save new history AND_NOT_TMP_ BIT 12 0 NOT previous history AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 1 NOT HMI Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl TS mode LOAD_TMP_BIT 12 5 Input history SET_TMP_BIT 12 0 Save previous history LOAD_BIT 457 0 UI1 SET_TMP_BIT 12 5 Save new history AND_NOT_TMP BIT 12 0 NOT previous history AND_TMP_BIT 3 2 TS active AND_NOT_TMP_BIT 4 6 NOT Stop 1 OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl 1639507 12 2006 279 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 1 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 4 8 SI
4. LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 12 7 Mode Change 1 SET_TMP_BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 1 HMI requested SET_TMP_BIT 3 1 HMI Active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active 1639507 12 2006 217 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 COMP_K_REG 0 COMP_K_REG 3 LOAD_K BIT 1 Z R_TMP_BIT 4 Puno OAD_K_BIT 1 D R_TMP_BIT 4 QNO MP_K_REG 4 A D_K_BIT 1 ea O AND_TMP_BIT 0 R_TMP_BIT 4 ano Gd Al 3 OMP_K_REG 5 BIT 1 Es o Pp iw N BIT 4 no wv id D_TMP_BIT 0 ET_TMP_BIT 4 TM P_B T m 0 ET_TMP_BIT 4 Pp BIT 4 TM P_BIT 0 ET_TMP_BIT 4 0 LOAD_TMP_ BIT 0 2 AND_BIT 1200 12 SET_TMP BIT 4 1 LOAD_TMP_ BIT 0 2 AND_BIT 1200 13
5. SET 1 1 LOAD_NOT_TMP_ BIT 4 0 not Transfer AND_TMP_BIT 2 2 342 _TMP_BIT TS active TS requested in Process in Process 1639507 12 2006 263 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 COMP_K_REG 0 0 LOAD BIT 1200 12 R_BIT 1200 13 D_TMP BIT 0 2 TMP BIT 4 1 K_REG 1 0 _K_BIT 1 D_ TMP BIT 0 2 TMP BIT 4 1 ET TMP BIT 4 1 ee 3 Qn O SH ue E O D 0 Z nO vs PLC fallback mode HOLD 0 last LO1 command last LO2 command equal LO1 PLC fallback STEP 1 fallback to ON equal logical or with previous value LO1 PLC fallback OFF 2 no ON 3 no ON OFF 4 no OFF ON 5 no Generate HMI Fallback Values LOAD_REG 645 COMP_K_REG 0 0 LOAD BIT 1200 12 R_BIT 1200 13 D_TMP BIT 0 2 ET TMP BIT 4 3 K_REG 1 0 _K_BIT 1 D_ TMP BIT 0 2 TMP BIT 4 3 ET TMP _BIT 4 3 o z Qn fe z to N O D 0 Z nO Ps HMI fallback mode HOLD 0 last LO1 command last LO2 command equal LO1 HMI fallback STEP 1 fallback to ON equal action action action action needed needed needed needed logical or with previous value LO1 HMI fallback OFF 2 no 22 QNK3 2522 no ON
6. Latch comm loss values in scratch 0 LOAD_BIT 456 8 PLC Comm Loss SET_TMP_BIT 0 0 save in scratch bit 0 LOAD_BIT 456 7 HMI Comm Loss SET_TMP_BIT 0 1 save in scratch bit 1 1639507 12 2006 207 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop1 and Stop2 Commands Generate Stopl LOAD_TMP_BIT 4 5 Global Stop OR_BIT 453 1 Diag Fault 1 OR_BIT 453 2 Diag Fault 2 SET_TMP_ BIT 4 6 save partial Stopl LOAD_NOT_BIT 1200 12 NOT alread on AND_BIT 456 4 Rapid Cycle OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 1 NOT LO1 PLC fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 3 NOT LO1 HMI fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 0 PLC active AND_NOT_BIT 704 0 NOT PLC Runl AND_TMP_BIT 4 8 Run 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 13 12 NOT HMI Run 1 AND_TMP_BIT 4 8 Run 1 AND_NOT_TMP_BIT 0 1 NOT HMI Comm Loss from scratch OR_TMP
7. 66 1639507 12 2006 Structured Text Language SET_NV_BIT The SET_NV_BIT command sets the value of the 1 bit accumulator to a specified non volatile register bit Arguments Representation 2 SET_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments SET_NOT_BIT The SET_NOT_BIT command sets the inverted value of the 1 bit accumulator to a specified register bit Arguments Representation 2 SET_NOT_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments 1639507 12 2006 67 Structured Text Language SET_NOT_TMP_BIT The SET_NOT_TMP_BIT command sets the inverted value of the 1 bit accumulator to a specified temporary register bit Arguments Representation 2 SET_NOT_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the
8. Input arguments Argument Type Description TmpReg UINT The temporary register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 Output arguments The OR_NV_REG command makes a logical OR link between the non volatile register value and the accumulator content in logic memory The OR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked non volatile register If any compared bit equals 1 the result of the OR process for that bit location is also 1 if all compared bits equal 0 the result of the OR process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 OR_NV_REG NVReg Input arguments Argument Type Description NVReg UINT The non volatile space register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 Output arguments 78 1639507 12 2006 Structured Text Language XOR_K The XOR_K command makes a logical OR link between a 16 bit constant value and the accumulator content in logic memory The result is saved in the 16 bit accumulator The XOR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked 16 bit
9. Temp 12 as INPUT History 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 las 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONSET status Low to High timer Temp 52 as ONSET status High to Low timer Temp 53 Latch Temp 54 as ONSET status 704 Runil Run2 Save Requested Control in Temp 2 LOAD_BIT 683 8 TS HMI SET_TMP_ BIT 0 1 Debounce TS HMI in scratch LOAD_BIT 457 5 LI6 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control Fl 274 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Look for control transfer LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD _NOT_TMP_BIT 1 2 Not equal SET_TMP_BIT 4 0 Transfer in Process Manage Bump Bumpless LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SE
10. Select Logic Functions Download Program to Device or click the icon to transfer the logic file from custom logic editor to the controller LTM CONF Default File Edit Link Settings Logic Functions Tools View Help AT D EET fi gE New Logic File Device Information Untitled1 FA Save Logic File pB Settings ri s Save Logic File As ax amo omr sone HB Statistics 3 oa x Close Logic File e TS HMI in scratch 45 Monitoring sm Ica i aasa aromes zoe Ee Custom Logic z a Download Program to Device DEES 3 Upload Program from Device Nea eames f Function Blocks 12 sev aM BIT 2 P Control a3 LOAD_TMP_BIT 4 0 t Transfer in Process 1639507 12 2006 161 Connection to the LTM R Controller Custom Logic Program Transfer and Execution Overview Transfer Validity Check Custom Logic Program Selection Custom Logic Program Replacement Invalid Program Corrupted Program Custom logic programs may be uploaded to or downloaded from the LTM R controller via LTM CONF configuration software Only one custom logic program may be loaded into the LTM R controller at a time During the upload or download of a custom logic program outputs are turned off and logic execution is stopped A specific mechanism is used to upload or download a custom logic file This mechanism uses a size register checksum and custom logic ID see Characteristics
11. TMP_BIT 4 12 IT 52 0 BIT TMP_BIT TMP_BIT BIT 4 1 BIT 52 T 4 8 T 4 6 E eet te E LO 1 LOAD_NOT_TMP_BIT 4 12 OR_NOT_TMP_BIT 52 0 AND_TMP_BIT 4 9 AND_NOT_ AND_NOT_ SET_TMP SET_TMP LATCH 52 TMP_BIT TMP_BIT BIT 4 1 BIT 52 T 4 7 T 4 10 LOAD_TMP_BIT 52 0 SET_TMP_BIT 4 14 Set Outputs to IMPR LOAD_TMP_BIT 4 10 SET_BIT 1200 12 SET_BIT 1200 9 NOT Reversing Timer Active Last direction forward Runl NOT Stopl NOT Reverse save Forward set last direction forward NOT NOT Reversing Timer Active T last direction forward Ran2 NOT NOT T Stop2 Forward save Reverse set last direction reverse last direction latch Latch value 1 forward save Last Direction Process Output 1 Forward Output 1 Aux 1 LED 1639507 12 2006 259 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT SET_BIT 1200 13 SET_BIT 1200 10 SET_BIT 1200 5 4 11 EX 4 Br FI LOAD_TMP_BIT 4 10 OR_TMP_BIT 4 11 SET_BIT 1200 0 SET_NOT_BIT 1200 1 x ah ah Et OAD_TMP_BIT 4 12 SET_BIT 1200 4 LOAD_BIT 455 3 BIT 1200 14 OAD_BIT 455 2 NOT_BIT 1200 15 OAD_BIT 457 4 BIT 1200 OAD_TMP BIT BIT 1200 OAD_TMP BIT TMP BIT 4 TMP BIT 4 ET_BIT 1200 n Cd d WE za d J WE 5
12. LOAD_BIT 455 3 SET_BIT 1200 14 LOAD_BIT 455 2 SET_NOT_BIT 1200 15 LOAD_BIT 457 4 SET_BIT 1200 2 LOAD_TMP_BIT 3 0 SET_BIT 1200 6 LOAD_TMP_BIT 4 6 OR_TMP_BIT 4 7 SET_BIT 1200 11 Process Output 1 Runl NOT Stop 1 Output 1 Aux 1 LED Motor Run Motor Stop Process Output 2 Run2 NOT Stop 2 Output 2 Aux 2 LED Process other outputs IMPR Alarm status Output 3 Alarm IMPR Fault status Outpur 4 Fault Reset Input LI5 Logic Reset PLC active Logic Local Remote Stop 1 Stop 2 Stop LED 1639507 12 2006 227 Pre Defined Structured Text Programs Structured Text Program cont d Manage Power UP Done LOAD _NOT_TMP_BIT 4 5 OR_TMP_BIT 4 0 SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 228 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 2 Wire Reverser Mode Overview The structured text program for the 2 wire reverser mode is defined below Structured Text Program LOGIC_ID 6 2 WIRE REVERSER MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode
13. LOAD_TMP_BIT 3 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT 4 15 SET_TMP_BIT 4 15 Run 1 Run 2 Direct Transfer Enable NOT PLC active save Swapping PLC active Run 1 NOT last direction Two Wire Swap save Two Wire Swap PLC active Run 2 last direction Two Wire Swap save Two Wire Swap PLC active Run 1 Run 2 Two Wire Swap save Two Wire Swap 1639507 12 2006 257 Pre Defined Structured Text Programs Structured Text Program cont d Manage forward reverse timer OAD_REG 541 Forward Reverse Time value LOAD_NOT_TMP_BIT 51 3 Get NOT history bit ON_SET_TMP_REG 9 51 Timer Value LOAD_NOT_TMP BIT 4 10 NOT Forward AND_NOT_TMP_BIT 4 11 NOT High Reverse OR_TMP_BIT 4 13 swapping OR_TMP_BIT 11 2 already timing OR_TMP_BIT 4 15 Two Wire Swap OR_NOT_TMP_BIT 12 12 NOT Power up Done SET_TMP_BIT 11 0 Enable Timer TIMER_TENTHS 9 10 11 Process forward reverse timer update Swapping flags LOAD_TMP_BIT 11 0 Enabled AND_TMP_BIT 11 2 timing SET_TMP_ BIT 4 12 Reversing Timer Active SET_TMP_BIT 4 15 Two Wire Swap FA 258 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Forward and Reverse status bits LOAD_NOT OR_TMP_B AND_TMP_ AND_NOT_ AND_NOT s s T_TMP_ T_TMP_ fH fy
14. block performs an unsigned multiplication of two 16 bit register values The The following table describes the Multiplication block characteristics FBD symbol Inputs outputs Description or example Inputs X 16 bit unsigned register value 0 to 65 535 Z h Z l Overflow Y 16 bit unsigned register value 0 to 65 535 Outputs Z h 16 most significant bits of the 32 bit product Z h X Y 65 536 Z I 16 least significant bits of the 32 bit product Z l X Y Z h 65 536 Example Assuming X 20 000 and Y 10 Z h 3 and Z 3 392 because 200 000 3 65 536 3392 A The block performs an unsigned division of two 16 bit register values The following table describes the Division block characteristics FBD symbol Inputs outputs or example Description Inputs X h 16 most significant bits of an unsigned register value 0 to 65 535 X l 16 least significant bits of an unsigned register value 0 to 65 535 Y 16 bit unsigned register divisor 0 to 65 535 Outputs Z h 16 most significant bits of the 32 bit quotient Z h X Y 65 536 Z l 16 least significant bits of the 32 bit quotient Z l X Y Z h 65 536 Error ON or OFF value which is set ON when a division by zero occurs This value is initialized to OFF Example Assuming X h 3 X I 3 392 and Y 40 Z h 0 and
15. A logic command is an instruction which identifies the operation to be performed using the argument s In the example above the LOAD_BIT command loads the value of the argument into an internal register called the accumulator There are two types of arguments e Setup commands These set up or test for the necessary conditions to perform an action for example LOAD and AND commands e Actions commands These commands direct the LTM R controller to perform an action based on info in the setup instructions for example assignment commands such as COMP Note When you type a logic command it is automatically recognized and displayed in blue 38 1639507 12 2006 Structured Text Language Argument Comments Synthax Commands Saving An argument is a number address or bit representing a value that the LTM R controller can manipulate in an instruction For example in the sample program above the second instruction 2 LOAD_BIT 683 8 includes a logic command LOAD_BIT and 2 argurments 683 and 8 This instructs the LTM R controller to load the value of register 683 bit 8 into the accumulator A logic command can have from zero to three arguments depending on the type of logic command Using instructions with commands and arguments the LTM R controller program can e Define the status of controller inputs and outputs such as sensors push buttons and relays e Activate basic logic functions su
16. Inputs Outputs Address Description Address Description T 12 12 Power Up T 4 8 Run1 T 3 0 T 3 1 T 3 2 Active Source 704 0 PLC Run 1 T 13 12 HMI Run 1 457 0 TS Run 1 T 12 0 Edge Detected1 T 4 12 No Lock Outs 456 8 PLC Loss 457 6 HMI Loss T4 8 PLC FB Run LO1 T 4 10 HMI FB Run LO1 T 12 7 Bump LO1 in process 12 11 Bumpless in process Generate Run2 Inputs Outputs Address Description Address Description T 12 12 Power Up T 4 9 Run2 T 3 0 T 3 1 T 3 2 Active Source 704 1 PLC Run 2 T 13 13 HMI Run 2 457 1 TS Run 2 T 12 0 Edge Detected1 T 4 12 No Lock Outs 456 8 PLC Loss 457 6 HMI Loss T4 9 PLC FB Run LO2 T 4 11 HMI FB Run LO2 T 12 9 Bump LO2 in process 12 11 Bumpless in process 1639507 12 2006 177 Programming Approach Set Logic Outputs to IMPR Inputs Outputs Address Description Address Description T 4 8 Run 1 1200 12 LO1 T4 9 Run 2 1200 13 LO2 T 4 6 Stop 1 1200 14 LO3 T 4 7 Stop 2 1200 15 LO4 455 2 Warn 1200 0 Run 455 3 Fault 1200 1 Stop 457 4 LI5 Reset 1200 2 Reset T 3 0 PLC Active 1200 5 Direction 1200 6 Remote 1200 7 FLA Set 1200 8 Ext Fault 1200 9 Aux1 LED 1200 10 Aux2 LED 1200 11 Stop LED Manage Power UP Done Inputs Outputs Address Description Address Description T4 5 Global Stop T 12 12 Power up T 4 0 Transfer Active Clear PLC
17. LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 0 TMP BIT 3 0 LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 1 TMP BIT 3 1 rT A rT A LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 2 SET_TMP_BIT 3 2 rT A 0 not Transfer in Process PLC requested PLC active not Transfer in Process HMI requested HMI Active not Transfer in Process TS requested TS active 1639507 12 2006 247 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 PLC fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 1 LO1 PLC fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 2 LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SET_TMP_BIT 4 1 LO1 PLC fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 2 logical or with previous value SET_TMP_BIT 4 2 LO2 PLC fallback 248 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generat
18. Output arguments LOAD_NV_BIT The LOAD_NV_BIT command loads the Boolean value 0 or 1 of a non volatile register bit into the 1 bit Boolean accumulator Arguments Representation 2 LOAD_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments 1639507 12 2006 57 Structured Text Language LOAD_NOT_BIT The LOAD_NOT_BIT command e inverts the Boolean value 0 or 1 of a specified register bit then e loads that value into the 1 bit Boolean accumulator Arguments Representation 2 LOAD_NOT_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments LOAD_NOT_TMP_BIT The LOAD_NOT_TMP_BIT command e inverts the Boolean value 0 or 1 of a specified temporary register bit then e loads it into the 1 bit Boolean accumulator Arguments Representation 2 LOAD_NOT_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The tempor
19. Argument Type Description Output arguments RegAddr UINT The address of the register to be set any valid writable LTM R register OnhHistory BOOL Argument 2 Bit 3 contains the bit accumulator value from the previous scan The ON_SET_TMP_REG command copies the value of the 16 bit accumulator to a temporary register to 1 on detecting the rising edge of an input signal that sets the bit accumulator value when the OnHistory bit value is 0 The OnHistory bit holds the value of the bit accumulator 0 or 1 from the previous scan Arguments Representation 2 ON_SI ET_TMP_REG TmpReg TmpReg Input arguments Argument Type Description Output arguments RegAddr UINT Argument 1 the address of the register to be set An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 OnHistory BOOL Argument 2 Bit 3 contains the bit accumulator value from the previous scan 1639507 12 2006 83 Structured Text Language ON_SET_NV_REG The ON_SET_NV_REG command copies the value of the 16 bit accumulator to a non volatile register to 1 on detecting the rising edge of an input signal that sets the bit accumulator value to 1 when the OnHistory bit value is 0 The OnHistory bit holds the value of the bit accumulator 0 or 1 from the pre
20. ET_T LOAD_TMP_BIT 4 4 AND_1 AND_1 T_T AND_NOT_TMP_BIT 12 9 SET_TMP_BIT 4 9 TM OR_TMP_ S M M M OR_TMP_ SI TM P BIT BIT P BIT P BIT P BIT BIT P BIT P BIT 7 a m a 3 0 0 0 4 4 9 9 Sal 0 1 4 4 9 9 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 3wire latch NOT Mode Change 2 save final Run 2 240 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage forward reverse timer LOAD_REG 541 LOAD_K_ BIT 1 SET_NOT_TMP_BIT 51 3 OR_TMP_BIT AND_TMP_BIT SET_TMP_BI1 L OR_TMP_BIT AND_TMP_BI1 MP _BIT TMP BI nO oe 3 ON_SET_TMP_REG 9 51 LOAD_NOT_TMP_BIT 4 8 4 6 T 4 10 0 0 i OAD_NOT_TMP_BIT 4 9 4 7 r 4 11 0 0 r 0 0 LOAD_NOT_TMP_BIT 4 10 AND_NOT_TMP_BIT 4 11 AND_TMP_BI1 OR_TMP_BIT OR_NOT_TMP SET_TMP_BI1 U A a T 11 2 0 0 BIT 12 12 T 11 0 TIMER_TENTHS 9 10 11 update Lockout Timing LOAD_TMP_BIT 11 0 AND_TMP_BI1 SET_TMP_BI1 r 11 2 T 4 12 Forward Reverse Time value Force a rising edge Fo
21. Math logic commands Math commands perform unsigned math functions using the 16 bit accumulator and temporary registers Math commands are executed when the 1 bit accumulator transitions from 0 to 1 Math commands include Command Argument 1 Argument 2 Argument 3 Description ON_ADD Temporary register value Temporary register status Argi Arg1 16 bit accumulator Status bits 0 Overflow 3 On History most significant word least significant word status ON_SUB Temporary register Temporary register Arg1 Arg1 16 bit accumulator Status value status bits 0 Underflow 3 On History ON_MUL Temporary register Temporary register Temporary register Arg1 Arg2 16 bit accumulator x most significant word least significant word status Arg2 Status bits 3 On History ON_DIV Temporary register Temporary register Temporary register Arg1 Arg2 Arg1 Arg2 16 bit accumulator Status bits 3 On History Argument not applicable to logic command 52 1639507 12 2006 Structured Text Language 2 2 Logic Commands Logic Commands Overview Summary This section describes in detail the logic commands and arguments provided by the custom logic editor What s in this This section contains the following topics Section Topic Page Program Logic Commands 54 Boolean Logic Commands 55 Register Logic Commands 69
22. Read these instructions carefully and look at the equipment to become familiar with the device before trying to install operate or maintain it The following special messages may appear throughout this documentation or on the equipment to warn of potential hazards or to call attention to information that clarifies or simplifies a procedure The addition of this symbol to a Danger or Warning safety label indicates that an electrical hazard exists which will result in personal injury if the A instructions are not followed This is the safety alert symbol It is used to alert you to potential personal injury hazards Obey all safety messages that follow this symbol to avoid possible injury or death A DANGER DANGER indicates an imminently hazardous situation which if not avoided will result in death or serious injury A WARNING WARNING indicates a potentially hazardous situation which if not avoided can result in death serious injury or equipment damage A CAUTION CAUTION indicates a potentially hazardous situation which if not avoided can result in injury or equipment damage 1639507 12 2006 Safety Information PLEASE NOTE Electrical equipment should be installed operated serviced and maintained only by qualified personnel No responsibility is assumed by Schneider Electric for any consequences arising out of the use of this material 2007 Schneider Electric All R
23. 86 1639507 12 2006 Structured Text Language TIMER_K_SEC The TIMER_K_SEC command e counts time in seconds up to the number of counts specified by a constant value e calculates and tracks the time remaining in a temporary register e is enabled by and reports its counting status to a and temporary register Arguments Representation 3 TIMER_K_SEC KValue TmpReg TmpReg Input arguments Argument Type Description KValue UINT Argument 1 the number of counts An integer value from 0 to 65 535 Enable BOOL Argument 3 Bit 0 the rising edge of this bit starts the timer Output arguments EndTime UINT Argument 2 a calculation of the time remaining An integer from 0 to 65 535 TimedOut BOOL Argument 3 Bit 1 indicates that timing has stopped This bit is set when Argument 2 expires This bit is cleared when e Argument 3 Bit 0 is cleared e power is cycled Timing BOOL Argument 3 Bit 2 indicates that timing is ongoing This bit is cleared when Argument 2 expires EnableHistory BOOL Argument 3 Bit 3 Status of the Enable bit in the previous scan 1639507 12 2006 87 Structured Text Language TIMER_K_TENTHS The TIMER_K_TENTHS commana e counts time in tenths of seconds up to the number of counts specified by a constant value e calculates and tracks the time remaining in a temporary register e is enabled by and reports its coun
24. AND_BIT 683 10 Bumpless SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfert in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 o Look for Edge l SET_TMP_BIT 4 0 Transfert in Process OR_TMP_BIT 12 8 Mode Wait 1 SET_TMP_BIT 12 7 Mode Change 1 LOAD_TMP_BIT 4 0 Transfert in Process OR_TMP_BIT 12 10 Mode Wait 2 SET_TMP_BIT 12 9 Mode Change 2 i LOAD_NOT_TMP_BIT 4 0 not Transfert in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 o PLC active zl LTM CONF Connected Conversion Logic Command The software automatically converts every element in Text view to the corresponding element in Grid view The left column lists the logic commands used in the program You can change the type of logic command by clicking a box and modifying the value in it An arrow indicates which logic command you can choose 1639507 12 2006 41 Structured Text Language Arguments Click a value in one of the argument columns to change its value using the up and down arrows or the number pad Note If you enter a value higher than permitted the highest permitted value will be entered Comments Comments are displayed in the Description column Inserting an To insert an instruction Instruction Step Action 1 Choose the command box above or below the area where you want your instruction to be entere
25. NOT LO1 already on Rapid Cycle Global Stop Diag Fault 1 Diag Fault 2 Stop LED 1639507 12 2006 213 Pre Defined Structured Text Programs Structured Text Program cont d Manage Power UP Done LOAD _NOT_TMP_BIT 4 5 OR_TMP_BIT 4 0 SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 214 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 3 Wire Independent Mode Overview The structured text program for the 3 wire independent mode is defined below Structured Text Program LOGIC_ID 5 3 WIR 5 IND EP ENDENT MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode terminal strip 0 PLC 1 HMI 2 TS Temp 3 as Active Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process value value value value 1 LO1 PLC fallback Ld 2 L02 PLC fallback 3 L01 HMI fallback 4 L02 HMI fallback 5 Global Stop 6 Stop1 7 Stop2 8 Runl 9 Run2 Temp 5 as state bits group 2 Temp 12 as INPU
26. Not bumpless Look for Edge Transfer in Process Mode Change 1 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BI1 SET AND_TMP_BIT 2 0 T B IT 3 0 LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 rT A T A LOAD_NOT_TMP_BI1 AND_TMP_BIT Wn ae _TMP_BIT 2 r A 0 0 not Transfer in Process PI PI LC requested LC active not Transfer in Process HMI requested HMI Active not Transfer in Process TS requested TS active 1639507 12 2006 193 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD REG 682 COMP_K_REG 0 AND_BIT 1200 SET_TMP_BIT AND_BIT 1200 SET_TMP_BIT COMP_K_REG 3 LOAD_K BIT 1 D_TMP BIT R_TMP_BIT 4 ET_TMP_BIT OAD_K_BIT 1 D TMP BIT Z Puno ET_TMP_BIT MP_K_REG 4 AD_K_BIT 1 AND_TMP_BIT QNO ea O P BIT OMP_K_REG 5 _BIT 1 TMP BIT _TMP_BIT 4 ET_TMP_BIT ano Gd Al 3 Es o Pp iw N no wv id R_TMP_BIT 4 R_TMP_BIT 4 ee LOAD_TMP_BIT 0 2 12 4 1 LOAD_TMP_BIT 0 2 13 4 2 0 PLC HO equal last LO1 P equal last LO2 P fallback mode LD 0 LO1 command LC fallback LO2 command LC fallback STEP 1 no action needed OFF 2 no action n
27. Process Outputs 3 Warn and Ouput4 Fault If IMPR Warn status active Set LO3 ON 1200 14 If IMPR Fault status active Set LO4 OFF 1200 15 Process Logic Reset T Local Reset command active Set Logic Reset 1200 2 Process Remote Status T PLC active Set Remote Control Source active 1200 6 Process STOP Logic T Stop 1 Temp 4 6 OR Stop 2 Temp 4 7 active Set Stop LED ON 1200 11 Manage Power UP Done I NO global Stops OR Control Source Active Set Power up Done Temp Register 12 12 Clear PLC Control on Control Transfer I Control Source Transfer active AND No Bumpless Cfg Mask off Reg 704 Run1 Run2 174 1639507 12 2006 Programming Approach 3 Wire Independent Operating Mode Allocation Tables Overview Allocations Tables Each allocation table defines the inputs and outputs values in each section of the 3 wire independent operating mode The allocation tables for each section of the 3 wire independent operating mode are described below Manage Requested and Active Control Source Inputs Outputs Address Description Address Description 457 5 Remote T 2 0 Remote Request 683 8 TS HMI T 2 1 HMI Request T 2 2 TS Request T 3 0 Remote Active T3 1 HMI Active T3 2 TS Active Manage Bump and Bumpless Inputs Outputs Address Description Address Description 683 10 Bumpless T4 0 Transfer Active T 12 11 Bum
28. fallback to ON equal logical or with previous value LO1 PLC fallback OFF ON 5 fallback to ON equal logical or with previous value LO2 PLC fallback 1639507 12 2006 303 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values COMP_K_REG SET_TMP_BI1 ET_TMP_BI1 COMP_K_REG LOAD_K_BIT D_TMP_BI1 R_TMP_BIT ET_TMP_BI1 _K_REG K_BIT D_TMP_BI1 _TMP_BIT ET_TMP_BI1 Qunoep O Q zZ y N Di O D 0 Z no nw E ig Latch HMI Keypad info SET_TMP_BI1 SET_TMP_BI1 SET_TMP_BI1 LOAD_REG 645 0 O LOAD_TMP_BIT 0 2 AND_BIT 1200 12 T 4 3 LOAD_TMP_BIT 0 2 AND_BIT 1200 13 S T 4 4 4 0 1 r 0 2 LOAD_BIT 1020 12 T 13 12 LOAD_BIT 1020 13 P 13 513 LOAD_BIT 1020 14 rT 13 14 HMI fallback mode HOLD 0 equal last LO1 command LO1 HMI fallback equal last LO2 command LO2 HMI fallback STEP 1 no OFF 2 no ON 3 no ON OFF 4 fallback to ON equal logical or with p LO1 HMI fallback OFF ON 5 fallback to ON equal logical or with p LO2 HMI fallback Aux 1 Aux 2 Stop action needed action needed action needed revious value revious value 304 1639507 12 2006 Pre Defined Structured
29. include partial Global Stop Save final Global Stop Latch comm loss values in scratch 0 Ih LOAD_BIT 456 8 SET_TMP_BI1 T 0 0 LOAD_BIT 456 7 SET_TMP_BI1 r 0 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 1639507 12 2006 277 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop1 and Stop2 Commands Generate Stopl LOAD_TMP_BIT 4 5 Global Stop OR_NOT_TMP_BIT 12 12 NOT Powerup Done SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 1 NOT LO1 PLC fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 3 NOT LO1 HMI fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP BIT 4 6 save partial Stopl LOAD_TMP_ BIT 3 0 PLC active AND_NOT_BIT 704 0 NOT PLC Runl AND_TMP_BIT 4 8 Run 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save final Stopl Generate Stop2 NA 278 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands
30. 1639507 12 2006 187 Pre Defined Structured Text Programs Structured Text Program contd Generate Run1 and Run2 Commands Generate Run 1 PLC mode LOAD_TMP_BIT 12 1 Input history AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP BIT 12 0 Save previous history LOAD_BIT 704 0 PLC Network Runl AND_TMP_BIT 12 12 Power up Done SET TMP BIT 12 1 Save new history AND_NOT_TMP_BIT 12 0 NOT previous history AND_TMP_BIT 3 0 PLC active OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl PLC Fallback LOAD_TMP_BIT 4 1 PLC fallback value AND_TMP_BIT 3 0 PLC active AND_TMP_BIT 0 0 PLC Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Run 1 HMI Fallback NA 3wire latch AND_NOT_TMP_BIT 4 13 NOT Swapping AND_NOT_TMP_BIT 12 7 NOT Mode Change 1 SET_TMP_BIT 4 8 save final Run 1 188 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 11 SET_TMP_BI1 T 12 0 LOAD_BIT 704 1 AND_TMP_BI1 SET_TMP_BI1 P22 r 12 2 AND_NOT_TMP_BIT 12 0 AND_TMP_BI OR_TMP_BIT SET_TMP_BI1 T 3 0 4 9 r 4 9 LOAD_TMP_BIT 4 2 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT SET_TMP_BI1 B30 r 0 0 4 9 r 4 9 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 9 SET_TMP_BIT 4 9
31. 4 9 TMP BIT 4 9 LOAD_TMP_BIT 12 4 AND_NOT_TMP_BIT 12 11 AND_NOT_TMP_BIT 4 7 SE ET_TMP_BI T 12 0 LOAD_TMP_BIT 13 13 4 AN SET AN AND_TMP_BIT OR_TMP_BIT MP_BI MP_BI H o o Ha M232 T 12 4 OT_TMP_BIT 12 0 Pst 4 9 SET_TMP_BIT T 4 9 LOAD_TMP_BIT 12 6 AND_NOT_TMP_BIT 12 11 AND_NOT_TMP_BIT 4 7 SET_TMP_BI1 rT 12 0 LOAD_BIT 457 1 TMP_BI MP_BI im ATE b Ea MP_BIT R_TMP_BIT T 12 12 rT 12 6 OT_TMP_BIT 12 0 32 4 9 no ET TMP BI r 4 9 Generate Run 2 PLC mode Input history NOT Bumpless in Process NOT Stop2 Save previous history PLC Network Run2 Power up Done Save new history NOT previous history PLC active Include previous result save partial Run2 HMI mode Input history NOT Bumpless in Process NOT Stop2 Save previous history HMI Run2 Power up Done Save new history NOT previous history HMI active Include previous result save partial Run2 TS mode Input history NOT Bumpless in Process NOT Stop2 Save previous history U12 Power up Done Save new history NOT previous history TS active Include previous result save partial Run2 1639507 12 2006 239 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 2 AND_TM AND_1
32. AND_TMP_BI AND_TMP_BI OR_TMP_BIT r 3 0 rT 0 0 4 9 SET_TMP_BI1 l 4 9 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback NA 3wire latch NOT Stop 1 NOT Swapping NOT Mode Change 1 save final Run 1 Generate Run 2 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Run2 Power up Done NOT Stop2 Save new history NOT previous history PLC active NOT Stop2 NOT PLC Comm Loss from scratch Include previous result save partial Run2 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 1639507 12 2006 199 Pre Defined Structured Text Programs Structured Text Program cont d AND_NOT_TMP_BIT AND_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP BIT 4 9 4 7 4 13 12 9 Set Outputs to IMPR LOAD_TMP BIT 4 8 AND_NOT_TMP BIT 4 6 SET _BIT 1200 12 SET_BIT 1200 9 E 122 LOAD_TMP BIT 4 9 AND_NOT_TMP_ BIT 4 7 SET_BIT 1200 13 SET _BIT 1200 10 E4 E LOAD_BIT 455 3 ET_BIT 1200 14 OAD_BIT 455 2 ET_NOT_BIT 1200 15 OAD_BIT 457 4 BIT 1200 OAD_TMP BIT BIT 1200 D_TMP BIT TMP BIT 4 T BIT 1200 n vM E NDEWE za a 3 3 3 5 oO D fon PAP DW YD nO H
33. Custom Logic Pre Defined Operating Modes Programs 163 LTM R Controller Programming Approach 165 LTM R Controller Programming Strategy for the 3 Wire Independent Operating Mode 166 3 Wire Independent Mode Programming Example 2 05 168 3 Wire Independent Operating Mode Temporary Registers Allocation 170 3 Wire Independent Operating Mode Program Sections 173 3 Wire Independent Operating Mode Allocation Tables 175 Pre Defined Operating Modes Structured Text Programs 179 Structured Text Program for 2 Wire Overload Mode 0005 180 Structured Text Program for 3 Wire Overload Mode 0055 191 Structured Text Program for 2 Wire Independent Mode 202 Structured Text Program for 3 Wire Independent Mode 215 Structured Text Program for 2 Wire Reverser Mode 2 55 229 Structured Text Program for 3 Wire Reverser Mode 2 55 245 Structured Text Program for 2 Wire 2 Step Mode 000000 es 261 Structured Text Program for 3 Wire 2 Step Mode 0020 00 ee 273 Structured Text Program for 2 Wire 2 Speed Mode 2 005 285 Structured Text Program for 3 Wire 2 Speed Mode 0005 300 Serr ee eee eee eee ee Ce eee er ee 317 ikaeatr bated oats wea ub bate wa Wana ae aw ane 321 Safety Information WAA Important Information NOTICE
34. Generate Run 2 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Run2 Power up Done Save new history NOT previous history PLC active Include previous result save partial Run2 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback NA 3wire latch NOT Swapping NOT Mode Change 2 save final Run 2 1639507 12 2006 189 Pre Defined Structured Text Programs Structured Text Program cont d Set Outputs to IMPR Process Output 1 LOAD_TMP_BIT 4 8 Run1 AND_NOT_TMP_BIT 4 6 NOT Stop 1 SET_BIT 1200 12 Output 1 SET_BIT 1200 9 Bux 1 LED Process Output 2 LOAD_TMP_BIT 4 9 Run2 AND_NOT_TMP_BIT 4 7 NOT Stop 2 SET_BIT 1200 13 Output 2 SET_BIT 1200 10 Kux 2 LED Process other outputs LOAD_BIT 455 3 IMPR Alarm status SET_BIT 1200 14 Output 3 Alarm LOAD_BIT 455 2 IMPR Fault status SET_NOT_BIT 1200 15 Output 4 Fault LOAD_BIT 457 4 Reset Input LI5 SET_BIT 1200 2 Logic Reset LOAD_TMP_BIT 3 0 PLC active SET_BIT 1200 6 Logic Local Remote LOAD_TMP_BIT 4 5 Global Stop SET_BIT 1200 11 Stop LED Manage Power UP Done LOAD_NOT_TMP_BIT 4 5 OR_TMP_BIT 4 0 SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Contr
35. Include previous result save partial Runl HMI mode Input history NOT Bumpless in Process NOT Stopl Save previous history HMI Run1 Power up Done Save new history NOT previous history HMI active Include previous result save partial Runl 1639507 12 2006 293 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 5 Be 12 ET TMP BII AD D_TMP_BI1 MP_BIN Ww Bo Fa E d 4 2u Z J MP BIN MP_BIT MP BIN no a H E 4 4 8 D_NOT_TMP_BIT 12 11 D_NOT_TMP_BIT 4 6 r 12 0 BIT 457 0 ips eel T 12 5 D_NOT_TMP BIT 12 0 hes oe 8 LOAD_TMP_BIT 4 1 AND_TMP_BI1 AND_TMP_BI1 gt TMP a OR BIT SET_TMP_BI1 3 0 4 4 8 0 0 8 LOAD_TMP_BIT 4 3 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT SET_TMP_BI1 A ek 0 1 4 4 8 8 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 TS mode Input history NOT Bumpless in Process NOT Stopl Save previous history TS Runt Power up Done Save new history NOT previous history TS active Include previous result save partial Runl PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss
36. Lockout Timer Include previous result save partial Run2 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 212 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 9 SET_TMP_BIT 4 9 Set Outputs to IMPR LOAD_TMP_BIT 4 8 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 12 SET_BIT 1200 9 SET_BIT 1200 0 SET_NOT_BIT 1200 1 LOAD_TMP_BIT 4 9 AND_NOT_TMP_BIT 4 7 T_BIT 1200 13 T_BIT 1200 10 LOAD_BIT 455 3 ET_BIT 1200 14 OAD_BIT 455 2 ET_NOT_BIT 1200 15 S L S LOAD_BIT 457 4 S L S ET_BIT 1200 OAD_TMP_BIT ET_BIT 1200 AWN io LOAD_NOT_BIT AND_BIT 456 4 OR_TMP_BIT 4 5 OR_BIT 453 1 OR_BIT 453 2 SET_BIT 1200 11 1200 12 3wire latch NOT Swapping NOT Mode Change 2 save final Run 2 Process Output 1 Run1 NOT Stop 1 Output 1 Aux 1 LED Motor Run Motor Stop Process Output 2 Run2 NOT Stop 2 Output 2 Aux 2 LED Process other outputs IMPR Alarm status Output 3 Alarm IMPR Fault status Output 4 Fault Reset Input LI5 Logic Reset PLC active Logic Local Remote
37. Non Volatile Latch FBD Function Block 131 NOP 54 NOT NOT FBD Function Block 133 O ON_ADD 93 ON_DIV 96 ON_MUL 95 ON_SET_NV_REG 84 ON_SET_REG 83 1639507 12 2006 323 Index ON_SET_TMP_REG 83 ON_SUB 94 OR OR FBD Function Block 133 OR_BIT 62 OR_K 77 OR_NOT_BIT 64 OR_NOT_NV_BIT 65 OR_NOT_TMP_BIT 65 OR_NV_BIT 63 OR_NV_REG 78 OR_REG 77 OR_TMP_BIT 63 OR_TMP_REG 78 Output 108 Outputs Blocks 134 P PCode 104 Pre defined operating modes 15 Program validity 162 Programming sections 173 Programming Strategy 166 Programming strategy 168 173 175 Q Quick Watch 110 R Register Non volatile register 25 Register 1200 27 Register 1201 27 Register 1202 27 Register 1203 27 Register 1204 27 Register 1205 27 Registers 1301 to 1399 25 Temporary register 25 170 Temporary registers 4 bit 13 172 Temporary registers 50 to 54 172 Register 1200 113 Register 457 114 Register 458 113 Register Bit In Register Bit In FBD Function Block 126 Register Bit Out Register Bit Out FBD Function Block 134 Register NV Bit In Register NV Bit In FBD Function Block 126 Register NV Bit Out Register NV Bit Out FBD Function Block 135 Register NV Word In Register NV Word In FBD Function Block 127 Register NV Word Out Register NV Word Out FBD Function Block 135 Register Temp Bit In Register Temp Bit In FBD Function Block 127 Register Temp Bit Out Register Temp Bit Out F
38. Set Outputs to IMPR LOAD_TMP_BIT 4 10 SET_BIT 1200 12 SET_BIT 1200 9 Fa a Cd update Lockout Timing flag Enabled timing Reversing Timer Active High Speed status bits NOT timing status last Speed Run1 NOT_Stop1 NOT High Speed save Low Speed set last Speed NOT timing status NOT last Speed Run2 NOT_Stop2 NOT Low Speed save High Speed set last Speed last Speed latch Process Output 1 Low Speed Output 1 Aux 1 LED 298 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Process Output 2 LOAD_TMP_BIT 4 11 High Speed SET_BIT 1200 13 Output 2 SET_BIT 1200 10 Aux 2 LED SET_BIT 1200 7 select FLA 2 LOAD_TMP_BIT 4 10 Low Speed OR_TMP_BIT 4 11 High Speed SET_BIT 1200 0 Motor Run SET_NOT_BIT 1200 1 Motor Stop LOAD_TMP_BIT 4 12 Reversing Timer SET_BIT 1200 4 Transition Timer Process other outputs LOAD_BIT 455 3 IMPR Alarm status SET_BIT 1200 14 Output 3 Alarm LOAD _ BIT 455 2 IMPR Fault status SET_NOT_BIT 1200 15 Output 4 Fault LOAD_BIT 457 4 Reset Input LI5 SET_BIT 1200 2 Logic Reset LOAD_TMP_BIT 3 0 PLC active SET_BIT 1200 6 Logic Local Remote LOAD_TMP_BIT 4 5 Global Stop OR_TMP_ BIT 11 2 timing SET_BIT 1200 11 Stop LED Manage Power UP Done LOAD_NOT_TM
39. Two Wire Swap 1639507 12 2006 313 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_NOT_TMP BIT 4 12 OR_TMP_BIT 53 0 AND_TMP_BIT 4 8 AND_NOT_TMP BIT 4 6 AND_NOT_TMP_ BIT 4 11 ET _TMP_BIT 4 10 ET_TMP BIT 53 1 LOAD_NOT_TMP_BIT 4 12 OR_NOT_TMP_BIT 53 0 AND_TMP_BIT 4 9 OT_TMP_BIT 4 7 OT_TMP_BIT 4 10 ET TMP_BIT 4 11 ET_TMP_BIT 53 2 js Z is Z LATCH 53 LOAD_TMP_BIT 53 0 SET_TMP_BIT 4 14 Set Outputs to IMPR LOAD_TMP_BIT 4 10 SET_BIT 1200 12 SET_BIT 1200 9 5 cA Manage Speed 1 and Speed 2 status bits NOT Lockout Active Last Speed Speed 1 Run1 NOT Stop1 NOT High Speed save Low Speed set last speed Low NOT Lockout Timer Active NOT last Speed Low Run2 NOT Stop2 NOT Low Speed save High Speed set last Speed High last speed latch Latch value 1 Low Speed save Last Speed Process Output 1 Low Speed Output 1 Aux 1 LED 314 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Process Output 2 LOAD_TMP_BIT 4 11 High Speed SET_BIT 1200 13 Output 2 SET_BIT 1200 10 Aux 2 LED SET_BIT 1200 7 select FLA 2 LOAD_TMP_BIT 4 10 Low Speed OR_TMP_BIT 4 11 High Speed SET_BIT 1200 0 Motor Run SET_NOT_BIT 1200 1 Motor Stop LOAD_TMP_BIT 4 12 Reve
40. fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LOL HMI fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback 1639507 12 2006 219 Pre Defined Structured Text Programs Structured Text Program cont d Latch HMI Keypad info LOAD_BIT 1020 12 Aux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Aux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 13 14 HMI Stop Key OR_BIT 456 5 Load Shed OR_NOT_BIT 457 3 NOT LI4 SET_TMP_ BIT 4 5 Save partial Global Stop LOAD _NOT_TMP_BIT 3 0 NOT PLC active AND_NOT_TMP_BIT 3 1 NOT HMI active AND_NOT_TMP_BIT 3 2 NOT TS active OR_TMP_BIT 4 5 include partial Global Stop SET_TMP_BIT 4 5 Save final Global Stop Ed uatch comm loss values in scratch 0 LOAD_BIT 456 8 PLC Comm Loss SET_TMP_ BIT 0 0 save in scratch bit 0 LOAD_BIT 456 7 HMI Comm Loss SET_TMP BIT 0 1 save in scratch bit 1 220 1639507 12 2006 Pre Defined Structured Text Progr
41. 0 LOAD_BIT 1200 12 last LO1 command OR_BIT 1200 13 last LO2 command AND_TMP_BIT 0 2 equal SET_TMP_BIT 4 3 LO1 HMI fallback COMP_K_REG 1 0 STEP 1 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback OFF 2 no action needed ON 3 no action needed ON OFF 4 no action needed OFF ON 5 no action needed 276 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Latch HMI Keypad info LOAD_BIT 1020 12 SET_TMP_BI1 e ES LOAD_BIT 1020 13 SET_TMP_BI1 SET_TMP_BI1 l 13 13 LOAD_BIT 1020 14 T 13 14 Aux 1 Aux 2 Stop Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 13 14 R_NOT_BIT LOAD_NOT_TMP_BIT 3 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT SET_TMP_BI1 457 3 O OR_BIT 456 5 OR_BIT 453 1 OR_BIT 453 2 SET_TMP BIT 4 5 Syed 3 2 4 5 r 4 5 LOAD_NOT_BIT 1200 0 AND_NOT_BI1 T 1200 4 AND_BIT 456 4 OR_TMP_BIT SET_TMP_BI1 4 5 T 4 5 HMI Stop Key NOT LI 4 Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on NOT Transition Timing Rapid Cycle
42. 1 OR_K KValue Input arguments Argument Type Description KValue UINT A constant value from 0 to 65 535 Output arguments OR_REG The OR_REG command makes a logical OR link between the register value and the accumulator content in logic memory The OR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked register If any compared bit equals 1 the result of the OR process for that bit location is also 1 if all compared bits equal 0 the result of the OR process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 OR_REG RegAddr Input arguments Argument Type Description RegAddr UINT The register address any valid LTM R register Output arguments 1639507 12 2006 77 Structured Text Language OR_TMP_REG OR_NV_REG The OR_TMP_REG command makes a logical OR link between the temporary register value and the accumulator content in logic memory The OR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked temporary register If any compared bit equals 1 the result of the OR process for that bit location is also 1 if all compared bits equal 0 the result of the OR process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 OR_TMP_REG TmpReg
43. AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 1 HMI active OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 2 TS active OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save final Stopl 186 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD _TMP_BIT 4 5 SET_TMP BIT 4 7 LOAD_TMP_BIT 0 0 AND_TMP_BIT 3 0 AND_NOT_TMP_BIT 4 2 OR_TMP_BIT 4 7 SET_TMP_BIT 4 7 LOAD_TMP_BIT 0 1 AND_TMP_BIT 3 1 AND_NOT_TMP_BIT 4 4 OR_TMP_BIT 4 7 SET_TMP BIT 4 7 LOAD_TMP_BIT 3 0 AND_NOT_BIT 704 1 AND_TMP_BIT 4 9 AND_NOT_TMP_BIT 0 0 OR_TMP_BIT 4 7 SET_TMP BIT 4 7 LOAD_TMP_BIT 3 1 OR_TMP_BIT 4 7 SET_TMP BIT 4 7 LOAD_TMP_BIT 3 2 OR_TMP_BIT 4 7 SET_TMP BIT 4 7 Generate Stop2 Global Stop save partial Stop7 PLC Comm Loss from scratch PLC active NOT LO2 PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop2 save partial Stop2 PLC active NOT PLC Run2 Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save partial Stop2 HMI active Include partial Stop2 save partial Stop2 TS active Include partial Stop2 save final Stop2
44. Compares the value of Argument 1 to the 16 register address register bit accumulator content and sets status address Argument 2 bits as follows BIT 1 ON if accumulator lt Argument 1 BIT 2 ON if accumulator Argument 1 BIT 3 ON if accumulator gt Argument 1 COMP_NV_REG Non volatile Temporary Compares the 16 bit accumulator content register address register and sets status Argument 2 bits as follows address BIT 1 ON if accumulator lt Argument 1 BIT 2 ON if accumulator Argument 1 BIT 3 ON if accumulator gt Argument 1 AND_K Constant value 0 to 65 535 Makes a logical AND link between the constant value and the accumulator content The result is stored in the 1 bit Boolean accumulator Argument not applicable to logic command 46 1639507 12 2006 Structured Text Language Command Argument 1 Argument 2 Argument 3 Description AND_REG Register address Makes a logical AND link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator AND_TMP_REG Temporary Makes a logical AND link between the register address temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator AND_NV_REG Non volatile Makes a logical AND link between the non register address volatile register value and the 16 bit accumulato
45. IMPR Fault status HMI Stop Key Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on Rapid Cycle include partial Global Stop Save final Global Stop Latch comm loss values in scratch 0 LOAD_BIT 456 8 SET_TMP BIT 0 0 LOAD BIT 456 7 SET_TMP_BIT 0 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 290 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 5 SET_TMP_BIT 4 6 LOAD_TMP_BIT 0 0 AND_TMP_BIT AND_NOT_TMP OR_TMP_BIT SET_TMP BIT 4 3 0 BIT 4 1 6 4 6 LOAD _TMP_BIT 0 1 AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT SET_TMP_BIT 4 Seek BIT 4 3 6 4 6 LOAD _NOT_BIT 704 0 OR_NOT_BIT 704 6 AND_TMP_BIT 3 0 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 0 0 OR_TMP_BIT SET_TMP_BIT 4 6 4 6 LOAD_TMP_BIT 3 1 AND_NOT_TMP_BIT 13 12 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 0 1 OR_TMP_BIT SET_TMP_BIT LOAD_TMP_BIT 4 s6 4 6 Sey AND_NOT_BIT 457 0 AND_TMP_BIT 4 8 OR_TMP_BIT SET_TMP_BIT 4 6 4 6 Generate Stopl and Stop2 Commands Generate Stopl Global Stop save partial Stopl PLC Comm Loss from scratch PLC active NOT LO1 PLC
46. SET_TMP BIT 4 2 0 PLC HOLD 0 equal last PLC runl LO1 PLC fallback equal last PLC run2 LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 fallback to ON equal 1 logical or wi fallback mode command command th previous LO1 PLC fallback fallback to ON equal 1 logical or wi th previous LO2 PLC fallback ON OFF 4 fallback to ON equal 1 logical or wi th previous LO1 PLC fallback OFF ON 5 fallback to ON equal 1 logical or wi th previous LO2 PLC fallback value value value value 218 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values LOAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last HMI runl command SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last HMI run2 command SET_TMP_BIT 4 4 LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed COMP_K_REG 3 0 ON 3 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LOL HMI fallback LOAD_K_BIT 1
47. cont d TS mode LOAD_TMP_BIT 12 6 ET_TMP_BIT 12 0 AD_BIT 457 1 _TMP_BIT 12 6 D_NOT_TMP_BIT 12 0 D_TMP_BIT 3 2 D_NOT_TMP_BIT 4 7 D_NOT_TMP_BIT 4 12 R_TMP_BIT 4 9 ET_TMP_BIT 4 9 n E O a a 2 n 22E no LOAD_TMP_BIT 4 2 AND_TMP_BIT 3 AND_TMP_BIT 0 OR_TMP_BIT 4 9 SI 0 0 ET_TMP_BIT 4 9 LOAD_TMP_BIT 4 4 AND_TMP_BIT 3 1 D_TMP_BIT 0 1 R_TMP_BIT 4 9 z ET_TMP_BIT 4 9 n o AND_NOT_TMP_BIT 4 7 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 9 SET_TMP_BIT 4 9 Input history Save previous history LI2 Save new history NOT previous history TS active NOT Stop 2 Lockout Timer Include previous result save partial Run2 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 3wire latch NOT Stop 2 NOT Swapping NOT Mode Change 2 save final Run 2 226 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Set Outputs to IMPR LOAD_TMP_BIT 4 8 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 12 T_BIT 1200 9 BIT 1200 0 T NOT_BIT 1200 1 Ei za d S S S ea LOAD_TMP_BIT 4 9 AND_NOT_TMP_BIT 4 7 SET_BIT 1200 13 SET_BIT 1200 10
48. option Background Enables you to set the background color of the workspace Choose between the colors available in Color by clicking on the box where the color is displayed the Custom Web and System tabs Background Enables you to insert an image from your hard disk drive or Any image you select as the background Image Path any removable device and to define it as the background Note Only possible when the background type is set to image Background Enables you to set the background type Choose between a flat color gradient or Type image background Enable Shows or hides the context menu True or false Context Menu Enable Shows or hides tooltips True or false Tooltip Gradient Enables you to set the color of the bottom of the gradient Choose between the colors available in Bottom the Custom Web and System tabs Note Only possible when the background type is set to gradient Gradient Top Enables you to set the color of the top of the gradient Choose between the colors available in the Custom Web and System tabs Note Only possible when the background type is set to gradient Gradient Enables you to set the type of gradient Choose between horizontal vertical forward Mode diagonal and backward diagonal modes Note Only possible when the background type is set to gradient Restrict to Enables you to choose whether the FBD program should True or false Canvas be kept inside the canvas Show Grid
49. save partial Runl HMI mode LOAD_TMP_BIT 12 3 Input history SET_TMP_BIT 12 0 Save previous history LOAD_TMP_BIT 13 12 HMI Runt SET_TMP_BIT 12 3 Save new history AND_NOT_TMP_ BIT 12 0 NOT previous history AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 1 NOT HMI Comm Loss from scratch AND_NOT_TMP_BIT 4 12 Lockout Timer OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl 1639507 12 2006 223 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 5 SET_TMP_BIT 12 0 OAD_BIT 457 0 ET_TMP_BIT 12 5 D_NOT_TMP_BIT 12 0 D_TMP_BIT 3 2 D_NOT_TMP_BIT 4 6 D_NOT_TMP_BIT 4 12 R_TMP_BIT 4 8 ET_TMP_BIT 4 8 E 2 n 22E no LOAD_TMP BIT 4 1 AND_TMP_BIT 3 AND_TMP_BIT 0 OR_TMP_BIT 4 8 SI 0 0 ET_TMP_BIT 4 8 LOAD_TMP_BIT 4 3 AND_TMP_BIT 3 1 AND_TMP_BIT 0 1 OR_TMP_BIT 4 8 S ET_TMP_BIT 4 8 3wire latch AND_NOT_TMP_BIT 4 6 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 TS mode Input history Save previous history UI1 Save new history NOT previous history TS active NOT Stop 1 Lockout Timer Include previous result save partial Runl PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback va
50. the result of the OR process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 OR_NOT_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments 1639507 12 2006 65 Structured Text Language SET_BIT The SET_BIT command sets the value of the 1 bit accumulator to a specified register bit Arguments Representation 2 SET_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments SET_TMP_BIT The SET_TMP_BIT command sets the value of the 1 bit accumulator to a specified temporary register bit Arguments Representation 2 SET_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments
51. 16 bit register values The following table describes the Add block characteristics FBD symbol Inputs outputs Description or example Inputs X 16 bit unsigned register value 0 to 65 535 A Y 16 bit unsigned register value 0 to 65 535 x Overflow Outputs Z 16 bit unsigned register result Z X Y Overflow ON or OFF value which when set ON caries Y Z a value of 65 536 The value is initialized to OFF Example Assuming X 60 000 and Y 7 000 the overflow will be ON because 60 000 7 000 67 000 which is superior to 65 536 The result Z is then equal to 1 464 1 464 65 356 67 000 m The block performs an unsigned subtraction of two 16 bit register values The following table describes the Subtraction block characteristics FBD symbol Inputs outputs Description or example Inputs X 16 bit unsigned register value 0 to 65 535 a Y 16 bit unsigned register value 0 to 65 535 x ea Outputs Z 16 bit unsigned register result Z X Y Underflow ON or OFF value which when set ON Y Z caries a value of negative 65 536 The value is initialized to OFF Example Assuming X 5 and Y 10 the underflow will be ON because the result is negative The result Z is then equal to 65 531 65 531 65 536 5 1639507 12 2006 123 Function Block Diagram Language Multiplication Block Characteristics Division Block Characteristics
52. 1639507 12 2006 183 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values LOAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 4 LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed COMP_K_REG 3 0 ON 3 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback 184 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Latch HMI Keypad info LOAD_BIT 1020 12 Bux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Bux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop
53. 8 iw z T n sa E o Z o jE T gt l gt HMI mode LOAD_TMP_ BIT 12 3 SET_TMP_BIT 12 0 LOAD_TMP_BIT 13 12 SET_TMP_BIT 12 3 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 1 AND_NOT_TMP_BIT 4 6 AND_NOT_TMP_BIT 0 1 AND_NOT_TMP_BIT 4 12 OR_TMP_BIT 4 8 SET_TMP BIT 4 8 Generate Run 1 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Runt NOT PLC Network Run2 Power up Done NOT Stop 1 Save new history NOT previous history PLC active NOT Stop 1 NOT PLC Comm Loss from scratch Include previous result save partial Runl Input history Save previous history HMI Run1 Save new history NOT previous history HMI active NOT Stop 1 NOT HMI Comm Loss from scratch Lockout Timer Include previous result save partial Runl 1639507 12 2006 253 Pre Defined Structured Text Programs Structured Text Program cont d OAD_BIT 457 0 AND_NOT_TMP_BI1 AND_TMP_ AND_NOT_TMP_BI1 pum O R_NOT_TMP_ Z Ss OR_TMP_BIT 4 8 BET 3 22 SET_TMP_BIT 12 5 ET_TMP_BIT 0 2 OAD_TMP_BIT 4 14 BIT 4 12 MP_BIT 0 2 SET_TMP BIT 4 8 LOAD_TMP_BIT 4 1 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 4 8 SI LOAD_TMP_BIT 4 3 AND_TMP_BIT D_TMP BIT MP BIT 4 8 Z nO zo A
54. AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 272 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 3 Wire 2 Step Mode Overview The structured text program for the 3 wire 2 step mode is defined below Structured Text Program LOGIC_ID 9 3 WIRE TWO STEP MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC Vea 1 HMIpartial 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 N A L02 PLC fallback value 3 L01 HMI fallback value fof 4 N A L02 HMI fallback value 5 Global Stop 6 Stop1 7 N A Stop2 8 Run1 9 N A Run2 10 Step 1 11 Step 2 12 Step Timer Active Temp 5 as state bits group 2 O Idle Wait for Run 1 as 1 Output 1 Waiting for Current gt 10 2 Step 1 Waiting for Step Timer or cur lt 3 Lockout Waiting for transition timer 541 4 Output 2 Waiting for stop command 5 Threshold Current Detected Temp 6 7 8 as Step 1 timer 1639507 12 2006 273 Pre Defined Structured Text Programs Structured Text Program cont d Temp 9 10 11 as Lockout timer
55. AND_REG The AND_REG command makes a logical AND link between the register value and the accumulator content in logic memory The AND process compares each bit in the 16 bit accumulator with the corresponding bit in the linked register If both bits equal 1 the result of the AND process for that bit location is also 1 in all other cases the result of the AND process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 AND_REG RegAddr Input arguments Argument Type Description RegAddr UINT The register address any valid LTM R register Output arguments 1639507 12 2006 75 Structured Text Language AND_TMP_REG AND_NV_REG The AND_TMP_REG command makes a logical AND link between the temporary register value and the accumulator content in logic memory The AND process compares each bit in the 16 bit accumulator with the corresponding bit in the linked temporary register If both bits equal 1 the result of the AND process for that bit location is also 1 in all other cases the result of the AND process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 AND_TMP_REG TmpReg Input arguments Argument Type Description TmpReg UINT The temporary register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Lo
56. AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 2 SET_TMP_BIT 3 2 LOAD_REG 682 COMP_K_REG 0 0 LOAD_BIT 1200 12 OR_BIT 1200 13 AND_TMP_BIT 0 2 SET_TMP_BIT 4 1 COMP_K_REG 1 0 2 WIRE TWO STEP MODE PS HMI debounce TS HMI in scratch LI6 debounce LI6 in scratch PLC Control _ LI6 debounced TS HMI debounced HMI Control _ LI6 debounced TS HMI debounced TS Control Transfert in Process save old Transfert in Process Requested Mode is it Active Mode Not egual Transfert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not Bumpless _ Look for Edge Transfert in Process Mode Wait 1 Mode Change 1 Transfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process PLC requested PLC active not Transfert in Process HMI requested HMI active not Transfert in Process TS requested TS active PLC fallback mode HOLD 0 Gast LO1 command Last L02 command egual L01 PLC fallback STEP 1 LTM CONF Connected 1639507 12 2006 37 Structured Text Language Instruction elements Logic Command The following is a part of the program described above 1 LOGIC ID 400 LOAD_BIT 683 3 3 SET TMP T i LOAD MII Sle gt 2 LOAD BIT 683 8 5 SETTMPBITO 0 6i SET TMP BIT2 0 L Areument s L Logic Command Line Number
57. Arguments for SET_TMP_BIT expect 2 Errors In the example above 2 mistakes were made Elements The Error window indicates e the line numbers with errors and e adescription of the error 106 1639507 12 2006 Structured Text Language Error Types The following list describes the different types of errors that may occur e syntax and structure errors logic commands without corresponding addresses resources used by the program that are not available program size is too big 1639507 12 2006 107 Structured Text Language Output Window Overview You can access the Output window from either the Error or the PCode window To do this click the tab on the left of the Error or PCode tab at the very bottom of the screen The following illustration shows the Output window LTM CONF Default File Edit Link Settings Logic Functions Tools View Help BEERE Peak Telemecanique gt Tesys T Device Information Untitled1 if Settings LOGIC_ID 400 2 WIRE TWO STEP MODE LE PP LOAD BIT 683 8 TS HMI pi Statistics SET_TMP_BIT 0 1 debounce TS HMI in scratch amp Monitoring LOAD_BIT 516 5 I1 Ure SET_TMP_BIT 0 0 debounce LI6 in scratch gt Parameters SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP BIT 0 0 UI6 debounced EF Custom Logic AND_TEP_BIT 0 1 TS HMI debounced i SET_TMP_BIT 2 1 HMI Control RE Structured Text LOAD_NOT_TMP BIT 0 0 _ LI6 debounced AND_NOT TMP BIT 0 1 _ TS HMI de
58. Bit 22 Write NOT B3 Temporary os Create Diagram and Hit Compile a Function Blocks gt Logic Outputs 1639507 12 2006 Introduction to Custom Logic Editor Using the Custom Logic Editor Overview The custom logic editor enables you to create and validate your own custom logic program to match with your needs Once it is made the LTM R controller s firmware loads and execute instructions you created 1639507 12 2006 21 Introduction to Custom Logic Editor Task Flow The following diagram shows all of the tasks to Diagram and modification of a custom logic program se Approach p 165 be carried out during the creation e LTM R Controller Programming Note The order defined is provided as an example The order you use will depend on your own work methods Custom Logic Define your requirements for a customized application Editor y LTM R controller Connect to the PC then power on the LTM R controller y Configuration Configure all LTM R controller s parameters with LTM CONF and select custom mode Do you want to create a new progra Programming Approach m or edit an existing one Y Creation of a Custom Logic Program Assign values to registers using logic commands Modification of a Custom Logic Program Select one of the 10 pre defined operating modes and edit values y Err
59. Comm Loss from scratch Include partial Stopl save partial Stopl TS active NOT TS Run 1 Run 1 Include partial Stopl save final Stop1 1639507 12 2006 235 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 5 SET_TMP_BIT 4 7 MP_BIT 0 0 D_TMP_BIT 3 0 OT_TMP_BIT 4 2 P_BIT 4 7 MP_BIT 4 7 pee fe gage is Puno zal Al AD_TMP_BIT 0 1 D_TMP_BIT 3 1 D_NOT_TMP_BIT 4 4 P_BIT 4 7 MP_BIT 4 7 TMP_BIT 3 0 NOT_BIT 704 1 TMP_BIT 4 9 AND_NOT_TMP_BIT 0 0 R_TMP_BIT 4 7 ET_TMP_BIT 4 7 nO N OAD_TMP_BIT 3 1 OT_TMP_BIT 13 13 D_TMP_BIT 4 9 OT_TMP_BIT 0 1 _TMP_BIT 4 7 ET_TMP_BIT 4 7 22E H nO ps Ze Et OAD_TMP BIT 3 2 ND_NOT_BIT 457 1 D_TMP BIT 4 9 TMP BIT 4 7 T TMP BIT 4 7 2 2 no zo Ss za Generate Stop2 Global Stop save partial Stop7 PLC Comm Loss from scratch PLC active NOT LO2 PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop2 save partial Stop2 PLC active NOT PLC Run2 Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save partial Stop2 HMI active NOT HMI Run 2 Run 2 NOT HMI Comm Loss from scratch Include partial Stop2 save partial Stop2 TS active NOT TS Ru
60. Done Save new history NOT previous history HMI active Include previous result save partial Run2 TS mode Input history NOT Bumpless in Process NOT Stop2 Save previous history TS Run2 Power up Done Save new history NOT previous history TS active Include previous result save partial Run2 1639507 12 2006 295 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 2 AND_1 AND_1 ET _1 LOAD_TMP_BIT 4 4 AND_1 AND_1 ET_ AND_NOT_TMP_BIT 12 9 OR_TMP_BIT S MP BI MP BI OR_TMP_BIT S MP BI MP BI MP BI MP BI a 7 3 0 0 0 4 4 9 9 Syed 0 1 4 4 9 9 SET_TMP_BIT 4 9 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 3wire latch NOT Mode Change 2 save final Run 2 296 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Speed Change timer Hel LOAD_K_RI ea G 1 LOAD_TMP_BIT 4 1 ON_SET_TMP_REG LOAD_REG 541 LOAD_TMP_BIT 4 OR_NOT_TMP_BIT 0 N_SET_TMP_REG LOAD_NOT_TMP_B OR_TMP_BIT 4 6 AND_TMP_B
61. Language COMP_K_REG COMP_REG The COMP_K_REG command compares the accumulator content to the Argument 1 constant value and sets one of the following bits in a temporary register bit O not used bit 2 if the accumulator equals the constant value e e bit 1 if the accumulator is less than the constant value e e bit 3 if the accumulator is greater than the constant value Arguments Representation 2 COMP _ K_REG KValue TmpReg Input arguments Argument Type Description KValue UINT Argument 1 a constant value from 0 to 65 535 Output arguments LT BOOL Argument 2 Bit 1 accumulator lt constant EQ BOOL Argument 2 Bit 2 accumulator constant GT BOOL Argument 2 Bit 3 accumulator gt constant The COMP_REG command compares the accumulator content to the value of the Argument 1 register and sets one of the following bits in a temporary register bit O not used bit 1 if the accumulator is less than the register value bit 2 if the accumulator equals the register value bit 3 if the accumulator is greater than the register value Arguments Representation 2 COMP_REG RegAddr TmpReg Input arguments Argument Type Description RegAddr UINT Argument 1 any valid LTM R register Output arguments LT BOOL Argument 2 Bit 1 accumulator lt register EQ BOOL Argument 2 Bi
62. Logic ID Type IMPR Register Type IMPR Register Logic ID Type TemporaryRegister Bonners a3 PCode LTM CONF Connected 104 1639507 12 2006 Structured Text Language PCode Window Elements The following table lists the different elements which make up the PCode window Item Description Total tokens Size of PCode in 16 bits word Count including checksum logic ID and all logic commands and arguments Checksum Module 16 summation of all logic commands and arguments Logic Command Each logic command in the program and its related Pcode Argument Each argument in the program and the type of register temporary non volatile or data that it refers to or affects Note Logic commands and arguments are listed in the same order as in the structured text language program 1639507 12 2006 105 Structured Text Language Error Window Overview When a structured text language program is compiled it may contain errors In this case the Error window is displayed LTM CONF Default File Edit Link Settings Logic Functions Tools View Help BATE Be 78 Tesys T E Device Information E gt Settings 4 Statistics HB Monitoring HB Parameters Custom Logic Structured Text 4 5 Function Blocks LTM CONF Connected Error Window CEFE Untitled1 if LOGIC_ID 40
63. Low to High timer Temp 52 as ONSET status High to Low timer Temp 53 Latch Temp 54 as ONSET status 704 Runil Run2 Td Save Requested Control in Temp 2 Lb LOAD_BIT 683 8 TS HMI SET_TMP_ BIT 0 1 Debounce TS HMI in scratch LOAD_BIT 457 5 U16 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control 246 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 LOAD_NOT_TMP BIT 1 2 SET_TMP_BIT 4 0 Manage Bump Bumpless 1 LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 SET_TMP_BIT 12 7 SI ra T TMP BIT 12 9 Look for control transfer Transfer in Process save old Transfer in Process Requested Mode is it Active Mode Not equal Transfer in Process Transfer in Process NOT Bumpless in Process Bumpless in Process one scan Transfer in Process Not bumpless Look for Edge Transfer in Process Mode Change 1 Mode Change 2 Save Active Control Mode in Temp Reg 3
64. OR_NOT_NV_BIT SET_BIT SET_TMP_BIT SET_NV_BIT SET_NOT_BIT SET_NOT_TMP_BIT SET_NOT_NV_BIT 1639507 12 2006 55 Structured Text Language LOAD_K_BIT The LOAD_K_BIT command loads a constant Boolean value 0 or 1 into the 1 bit Boolean accumulator Arguments Representation 1 LOAD_K_BIT KValue Input arguments Argument Type Description KValue BOOL A constant value 0 or 1 Output arguments LOAD_BIT The LOAD_BIT command loads the Boolean value 0 or 1 of a register bit into the the 1 bit Boolean accumulator Arguments Representation 2 LOAD_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit number an integer from 0 to 15 Output arguments 56 1639507 12 2006 Structured Text Language LOAD_TMP_BIT The LOAD_TMP_BIT command loads the Boolean value 0 or 1 of a temporary register bit into the 1 bit Boolean accumulator Arguments Representation 2 LOAD_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15
65. PLC Runl Low Speed PLC active Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save final Stop2 1639507 12 2006 307 Pre Defined Structured Text Programs Structured Text Program cont d Generate Run1 and Run2 Commands Generate Run 1 PLC mode LOAD_TMP_BIT 12 1 Input history AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP BIT 12 0 Save previous history LOAD_BIT 704 0 PLC Network Runl AND_BIT 704 6 PLC Low Speed AND_TMP_ BIT 12 12 Power up Done AND_NOT_TMP_BIT 4 6 NOT Stop 1 SET_TMP_ BIT 12 1 Save new history AND_NOT_TMP_BIT 12 0 NOT previous history AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl HMI mode LOAD_TMP_BIT 12 3 Input history SET_TMP BIT 12 0 Save previous history LOAD_TMP_BIT 13 12 HMI Runt SET_TMP_BIT 12 3 Save new history AND_NOT_TMP_BIT 12 0 NOT previous history AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 1 NOT HMI Comm Loss from scratch AND_NOT_TMP_BIT 4 12 Lockout Timer OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Runl 308 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BI
66. Process Save previous history PLC Network Run2 Power up Done Save new history NOT previous history PLC active Include previous result save partial Run2 1639507 12 2006 211 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 4 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 0 TMP_BIT 13 13 D_TMP_BIT 12 12 ET_TMP_BIT 12 4 D_NOT_TMP_BIT 12 0 D_TMP_BIT 3 1 D_NOT_TMP_BIT 4 12 BIT 4 9 MP_BIT 4 9 BS 5 5 2u Be no mw H Is ue LOAD_TMP_BIT 12 6 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 0 OAD_BIT 457 1 D_TMP_BIT 12 12 T_TMP_BIT 12 6 D_NOT_TMP_BIT 12 0 D_TMP_BIT 3 2 D_NOT_TMP_BIT 4 12 BIT 4 9 MP_BIT 4 9 E Z apl 2u Be no Hw H Is ue LOAD_TMP_BIT 4 2 AND_TMP_BIT 3 AND_TMP_BIT 0 OR_TMP_BIT 4 9 SI 0 0 ET_TMP_BIT 4 9 LOAD_TMP_BIT 4 4 AND_TMP_BIT 3 1 AND_TMP_BIT 0 1 OR_TMP_BIT 4 9 S ET_TMP_BIT 4 9 HMI mode Input history NOT Bumpless in Process Save previous history HMI Run2 Power up Done Save new history NOT previous history HMI active Lockout Timer Include previous result save partial Run2 TS mode Input history NOT Bumpless in Process Save previous history LI2 Power up Done Save new history NOT previous history TS active
67. Quick Watch window For example in the figure above if you click 1200 the number of the register that was added it will be displayed in binary code The following functions are also available in the Quick Watch window Functionality Description Stay on Top When active the Quick Watch window remains in the foreground regardless of which application is active It enables you to navigate in the software or in another program while still monitoring the added registers Opacity Enables you to adjust the opacity of the Quick Watch window Registers you choose to monitor are appended to the Quick Watch window An index number is assigned to each register The local value corresponds to the value that LTM CONF configuration software assigns to this register The device value corresponds to the value which is stored in the LTM R controller The Quick Watch window displays actual Device Values only while a Parameters view window i e All Parameters Configurable Parameters is open 1639507 12 2006 111 Structured Text Language LTM R Controller Logic Simulator Overview Logic Simulator Interface LTM CONF programming software comes with the LTM R controller logic simulator It enable to test the functionning of a custom logic program before transferring it into the LTM R controller To open the logic simulator navigate in the top level menu bar to Tools Logic Simulator T
68. R controller It details how to physically connect the device to the controller including what connection accessories can be used as well as describing how to transfer logic files between the LTM R controller and the custom logic editor This chapter contains the following topics Topic Page Hardware Connection 154 Initialization and Connection 156 Transferring Logic Files between the LTM R Controller and Custom Logic Editor 158 Custom Logic Program Transfer and Execution 162 1639507 12 2006 153 Connection to the LTM R Controller Hardware Connection Overview This section describes how to physically connect the LTM R controller to a PC running Powersuite or LTM CONF The PC requires its own power source and must be connected to the RJ45 port on the LTM R controller or the HMI interface port RJ45 on the expansion module when attached to the LTM R controller Configurations The PC can be connected in a 1 to 1 configuration to a single LTM R controller or in a 1 to many configuration to multiple controllers Connecting to a The diagrams below show a 1 to 1 connection from a PC running LTM CONF to the PC running LTM R controller with and without the expansion module LTM CONF Software in 1 to 1 Mode PC running LTM COMF software Power cable VW3 A8 106 LTM R controller Expansion module kOND 1
69. Register bit Sets inverted value of the 1 bit Boolean register no 0 15 accumulator into a non volatile register bit address Argument not applicable to logic command 1639507 12 2006 45 Structured Text Language Register logic Register commands evaluate and control 16 bit values Register commands commands include Command Argument 1 Argument 2 Argument 3 Description LOAD_K_REG Constant value Loads a constant value into the 16 bit 0 to 65 535 accumulator LOAD_REG Register address Loads a copy of a register into the 16 bit accumulator LOAD_TMP_REG_ Temporary Loads a copy of a temporary register into the register address 16 bit accumulator LOAD_NV_REG Non volatile Loads a copy of a non volatile register into register address the 16 bit accumulator COMP_K_REG Constant value Temporary Compares the 16 bit accumulator value to 0 to 65 535 register Argument 1 constant and sets status address Argument 2 bits as follows BIT 1 ON if accumulator lt Argument 1 BIT 2 ON if accumulator Argument 1 BIT 3 ON if accumulator gt Argument 1 COMP_REG Register address Temporary Compares the value of Argument 1 to the 16 register bit accumulator content and sets status address Argument 2 bits as follows BIT 1 ON if accumulator lt Argument 1 BIT 2 ON if accumulator Argument 1 BIT 3 ON if accumulator gt Argument 1 COMP_TMP_REG Temporary Temporary
70. SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control 230 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Look for control transfer LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG COMP_TMP_REG 3 tf 3 LOAD_NOT_TMP_BIT 1 2 SET_TMP_BIT 4 0 Manage Bump Bumpless 1 LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 SE TJ T_TMP_BIT 12 7 SET_TMP_BIT 12 9 Lib Transfer in Process save old Transfer in Process Requested Mode is it Active Mode Not equal Transfer in Process Transfer in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfer in Process Not bumpless Look for Edge Transfer in Process Mode Change 1 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 0 TMP _BIT 3 0 LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 rT A rT A LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 2 SET_TMP_BIT 3 2 rT A 0 not PI P LC LC not HMI HMI not TS requested TS active Transfer in Process requested active
71. Stop2 NA 266 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands he LOAD_TMP_BI AND_NOT_TMP SET_TMP BIT LOAD_BIT 70 AND_TMP_BIT SET_TMP BIT D_NOT_TMP D_TMP BIT _TMP BIT ET TMP BIT BBB n LOAD_TMP_BI AND_NOT_TMP_ SET_TMP_BIT LOAD_TMP_BI AND_TMP_BIT SET_TMP_BIT AND_NOT_TMP_BIT 12 AND_TMP_BIT OR_TMP_BIT SET_TMP_BIT LOAD_TMP_BI AND_NOT_TMP_BIT 12 SET_TMP_BIT LOAD_BIT 45 AND_TMP_BIT SET_TMP_BIT AND_NOT_TMP_BIT 12 AND_TMP_BIT OR_TMP_BIT SET_TMP_BIT P12 BIT 12 12 0 4 0 12 12 12 1 BIT 12 3 0 4 8 4 8 T 12 3 12 0 T 13 512 12 12 12 3 3 1 4 8 4 8 T 12 5 12 0 120 12 12 12 5 3 2 4 8 4 8 BIT 12 11 11 11 Generate Run 1 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Runl Power up Done Save new history NOT previous history PLC active Include previous result save partial Runl HMI mode Input history NOT Bumpless in Process Save previous history HMI Runt Power up Done Save new history NOT previous history HMI active Include previous result save partial Runl TS mode Input history NOT Bumpless in Process Save previous history UI1 Power up Done Save new history NOT previo
72. Structured Text Programs Structured Text Program contd Temp 12 as INPUT History Lf Leb Lil Temp 50 as ONS Temp 51 as ONS Temp 52 as ONS Temp 53 Latch Temp 54 as ONS 1 PLC Run 1 PLC Run 2 HMI Run 1 HMI Run 2 TS Run 1 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done nu W Lot io Temp 50 as general status registers status transition time value status Low to High timer T status High to Low timer Ep 5 43 He 3 BJ E J Save Requested Control in Temp 2 LOA S ET LOA SET SET LOA D BIT 683 8 TS HMI TMP BIT 0 1 Debounce TS HMI in scratch D BIT 457 5 LI6 TMP_BIT 0 0 Debounce LI6 in scratch TMP BIT 2 0 PLC Control D_NOT_TMP_BIT 0 0 LI6 debounced TMP_BIT 0 1 TS HMI debounced TMP BIT 2 1 HMI Control D_NOT_TMP_BIT 0 0 LI6 debounced NOT_TMP_BIT 0 1 TS HMI debounced TMP_BIT 2 2 TS Control status 704 Runl Run2 1639507 12 2006 301 Pre Defined Structured Text Programs Structured Text Program cont d Look for control transfer LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP_ BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD_
73. Text Programs Structured Text Program cont d Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 13 14 OR_NOT_BIT 457 3 OR_BIT 456 5 OR_BIT 453 1 OR BIT 453 2 SET_TMP BIT 4 5 LOAD_NOT_TMP_BIT 3 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT 4 5 SET_TMP BIT 4 5 LOAD_NOT_BIT 1200 0 AND_BIT 456 4 OR_TMP_BIT 4 5 SET_TMP BIT 4 5 Se S62 HMI Stop Key NOT Stop Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on Rapid Cycle include partial Global Stop Save final Global Stop Latch comm loss values in scratch 0 LOAD BIT 456 8 SET_TMP_BIT 0 0 LOAD BIT 456 7 SET_TMP_BIT 0 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 1639507 12 2006 305 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop1 and Stop2 Commands SET_TMP_BIT LOAD_TMP_BIT D_TMP BIT T_TMP_ _TMP_BIT 4 P_BIT Huno Oo H W gsal o EL gig 24206 P BIT T_TMP_ _TMP_BIT 4 ET_TMP_BIT 0 Z no zo Ss as Ow z 0 je Z ET_TMP_BIT 4 6 0 3 0 BIT 4 1 6 4 6 Sd BIT 4 3 6 4 4 6 6 LOAD_TMP_BIT 4 5 OR_NOT_TMP_BIT 12
74. Timer Logic Commands 85 Latch Logic Commands 89 Counter Logic Commands 91 Math Logic Commands 93 1639507 12 2006 53 Structured Text Language Program Logic Commands Overview LOGIC_ID NOP Program logic commands are used to identify the logic file to the custom logic editor The following commands can be used e LOGIC_ID e NOP The LOGIC_ID statement acts as an identifier for the logic file LOGIC_ID see p 17 values have an integer value range of 0 to 511 as follows e 0 255 reserved for default logic files e 256 511 available for custom logic files Arguments Representation 1 LOGIC_ID ID Input argument Argument Type Description ID UINT An integer from 0 to 511 Output arguments The NOP command performs no operation Use the NOP command as a placeholder in a logic file to replace a pre existing command or to reserve space for a future command Arguments Representation 0 NOP The NOP command has no arguments 54 1639507 12 2006 Structured Text Language Boolean Logic Commands Overview The custom logic editor uses the following boolean logic commands LOAD_K_BIT LOAD_BIT LOAD_TMP_BIT LOAD_NV_BIT LOAD_NOT_BIT LOAD_NOT_TMP_BIT LOAD_NOT_NV_BIT AND_BIT AND_TMP_BIT AND_NV_BIT AND_NOT_BIT AND_NOT_TMP_BIT AND_NOT_NV_BIT OR_BIT OR_TMP_BIT OR_NV_BIT OR_NOT_BIT OR_NOT_TMP_BIT
75. Transfer in Process requested Active Transfer in Process 1639507 12 2006 231 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 PLC fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 1 LO1 PLC fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 2 LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SET_TMP_BIT 4 1 LO1 PLC fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 2 logical or with previous value SET_TMP_BIT 4 2 LO2 PLC fallback 232 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values LOAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_B
76. a non volatile register value The following table describes the Register NV Word In block characteristics FBD symbol Inputs outputs Description Read Non Volatile Inputs a Any non volatile register from 0 to 63 Outputs Value from 0 to 65 535 1 The tmp block enables the reading and use of a temporary register bit value The following table describes the Register Temp Bit In block characteristics FBD symbol Inputs outputs Description a b Read Temporary Inputs a Any temporary register from 0 to 299 b Bit position from 0 to 15 Outputs Value 0 or 1 ON 1 and OFF 0 Se The Limp block enables the reading and use of a temporary register value The following table describes the Register Temp Word In block characteristics FBD symbol Read Non Volatile Inputs outputs Description Inputs a Any temporary register from 0 to 299 Outputs Value from 0 to 65 535 1639507 12 2006 127 Function Block Diagram Language Function Blocks Overview The FBD editor uses various Function blocks Counter Counter NV Volatile Latch Non volatile Latch Mux TimerSeconds TimerTenthSeconds Access To access Function blocks click on the Function blocks bar in the Toolbox The following menu is then displayed in the Toolbox To H mals t Ch l
77. accumulator content in logic memory If the value of either the bit accumulator or the register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0 the result of the OR process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 OR_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments 62 1639507 12 2006 Structured Text Language OR_TMP_BIT The OR_TMP_BIT command makes a logical OR link between a temporary register bit value and the accumulator content in logic memory If the value of either the bit accumulator or the temporary register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0 the result of the OR process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 OR_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments OR_NV_BIT The OR_NV_BI
78. and FBD languages implement the following different types of commands Program logic commands Boolean logic commands Register logic commands Timer logic commands Counter logic commands Latch logic commands Math logic commands 18 1639507 12 2006 Introduction to Custom Logic Editor Structured Text Editor LTM CONF Default The following illustration shows the structured text editor integrated in PowerSuite File Edit Link Settings Logic Functions Tools View Help gt Tesys T f Device Information f Settings f Statistics f Monitoring i Parameters 5 3 Custom Logic Function Blocks Faas Se emass Untitled if Untitled2 if Untitled if Telemecanique a LOGIC_ID 400 LOAD_BIT 683 8 SET_TMP_BIT 0 1 LOAD_BIT 516 5 SET_TMP_BIT 0 0 SET_TMP_BIT 2 0 LOAD_NOT_TMP BIT 0 0 AND_TEP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 1 LOAD_NOT_TMP BIT 1 2 SET_TMP_BIT 4 0 LOAD_TMP_BIT 4 0 AND_NOT_TMP BIT 12 11 AND_BIT 683 10 1 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 OR_TMP_BIT 12 8 SET_TMP_BIT 12 7 LOAD_TMP_BIT 4 0 OR_TMP_BIT 12 10 SET_TMP_BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 LOAD_NOT_TMP BIT 4 0 AND_TMP_BIT 2 2 SET_TMP_BIT 3
79. and indicates whether it was successful In the example above 2 errors were encountered so you are prompted to view the Errors window You can access the Error window by clicking the tab on the right of the Output tab at the very bottom of the screen or select View gt Error Window in the top level menu bar 1639507 12 2006 109 Structured Text Language Quick Watch Window Overview The Quick Watch window enables you to easily monitor the registers you select Quick Watch x Index Address Local Value Device Value 1 1200 0 0 2 51 75 0 51 Add Watch v Stay onTop Opacity Close Adding a The following table explains how to add a register in the Quick Watch window Register in the Quick Watch Window 1 Click View in the top level menu bar 2 Click on Quick Watch Window Result The Quick Watch window opens Type a register number in the box on the left of the Add Watch button 4 Click Add Watch Result The register is added and its local and device values are shown 5 Repeat step 3 and 4 for every register you want to add to the list 110 1639507 12 2006 Structured Text Language Register Value Quick Watch Window Functions Index Local Value Device Value Click a number in one of the boxes to display its value in binary code in the middle of the
80. bit register address 0 to 65 535 The custom logic program can modify the values of 3 types of registers e Control program registers e Temporary registers e Non volatile registers The list of commands for the control program is saved in an area of the internal memory of the LTM R controller The format of this logic memory is illustrated in the following table Memory Item Range Description location 0 Logic Program Size n 0 to 8192 16 bit word 0 means a pre defined operating mode is used 1 Logic Checksum 0 to 65 535 Sum of program memory from offset 2 to n 2 2 Logic Function ID 0 to 255 is reserved for standard LTM R controller Identifier of the custom modes e g 2 Overload 4 Independent etc logic program within 256 is reserved for full custom logic not based on the LTM R controller a standard LTM R motor controller mode 257 to 511 is reserved for custom logic based on a standard motor controller mode e g 258 Custom Overload 260 Custom Independent etc Logic Command Argument 1 One word of logic Logic Command Argument 2 Depending on the logic command see p 53 type function 5 Logic Command Argument 3 n 2 Logic Command Argument n One word of logic function Logic Memory Limits Register Locations The program size is dependent on the number of logic commands While in the text editor a command and its arguments will occupy a single line in the memory i
81. by a single program line and consists of three components e Line number e Logic command Mnemonics e Argumeni s 36 1639507 12 2006 Structured Text Language Example of a Structured Text Program in Text View LTM CONF Default File Edit Link The following is an example of a program created with the structured text editor in Text view Settings Logic Functions Tools View Help gt Tesys T H Device Information A Settings f Statistics f Monitoring H Parameters E gt Custom Logic Structured Text gt Function Blocks PEAS SS aE Untitled1 if Untitled2 if Untitled3 if Telemecanique 10 a 12 13 14 15 16 17 18 19 20 2 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 LOGIC_ID 400 LOAD_BIT 683 8 SET_TMP_BIT 0 1 LOAD_BIT 516 5 SET_TMP_BIT 0 0 SET_TMP_BIT 2 0 LOAD_NOT_TMP BIT 0 0 AND_TEP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 1 LOAD_NOT_TMP BIT 1 2 SET_TMP_BIT 4 0 LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 1 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 OR_TMP_BIT 12 8 SET_TMP_BIT 12 7 LOAD_TMP_BIT 4 0 OR_TMP_BIT 12 10 SET_TMP_BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0
82. constant and yields these results When 2 bits are compared if one bit equals 1 and the other equals 0 the result of the XOR process is 1 in all other cases the result of the XOR process is 0 When more than 2 bits are compared if there is an odd number of 1 states the result of the XOR process is 1 if there is an even number of 1 states the result of the XOR process is 0 Arguments Representation 1 OXR_K KValue Input arguments Argument Type Description KValue UINT A constant value from 0 to 65 535 Output arguments 1639507 12 2006 79 Structured Text Language XOR_REG The XOR_REG command makes a logical exclusive OR link between the register value and the accumulator content in logic memory The result is saved in the 16 bit accumulator The XOR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked register and yields these results When 2 bits are compared if one bit equals 1 and the other bit equals 0 the result of the XOR process is 1 in all other cases the result of the XOR process is 0 When more than 2 bits are compared if there is an odd number of 1 states the result of the XOR process is 1 if there is an even number of 1 states the result of the XOR process is 0 A
83. fallback value Include partial Stopl save partial Stopl HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stopl save partial Stopl NOT PLC Runt NOT Low Speed PLC active Run 1 NOT PLC Comm Loss from scratch Include partial Stopl save partial Stopl HMI active NOT HMI Run 1 Run 1 NOT HMI Comm Loss from scratch Include partial Stopl save partial Stopl TS active NOT TS Run 1 Run 1 Include partial Stopl save final Stop1 1639507 12 2006 291 Pre Defined Structured Text Programs Structured Text Program cont d E D iw TMP BIT 4 5 ET TMP_BIT 4 7 TMP_BIT 0 0 TMP BIT 3 0 D_NOT_TMP BIT 4 2 TMP BIT 4 7 P BIT 4 7 MP_BIT 0 1 P BIT 3 1 T TMP BIT 4 4 BIT 4 7 ET TMP_BIT 4 7 nt Beet sas D Wn BESS Gus 4 gt l 5 e 628485 no 8 Ss as je OAD_NOT_BIT 704 0 R_BIT 704 6 MP BIT 3 0 D_TMP BIT 4 9 OT_TMP_BIT 0 0 P_BIT 4 7 MP BIT 4 7 BEES 0 o a in nO tf o H 2 g Et OAD_TMP BIT 3 1 ND_NOT_TMP_BIT 13 13 D_TMP BIT 4 9 D_NOT_TMP_BIT 0 1 MP BIT 4 7 MP BIT 4 7 gt Be no Hw H LOAD_TMP_BIT 3 2 AND_NOT_BIT 457 1 AND_TMP_BIT 4 9 OR_TMP_BIT 4 7 S 8 T_TMP_BIT 4 7 Ea Generate Stop2 Global Stop save partial Stop2 PLC Comm Loss from scratch PLC act
84. following programming steps to the Set LTRM Outputs section Load_bit 457 1 Load the Status of logic input 457 1 into the accumulator Set_bit 1200 8 Set the bit to cause an LTM R external fault condition Compile the program and save the file under a new name Test the program in the logic simulator see p 112 to verify the desired behavior of the inputs and outputs Download the program from PC into the LTM R controller and wire the LTM R controller for use as desired 1639507 12 2006 169 Programming Approach 3 Wire Independent Operating Mode Temporary Registers Allocation Overview Usually at the beginning of the program the initial comments describe the temporary address locations needed to perform specific functions of the program 170 1639507 12 2006 Programming Approach Temporary The following comments describe the temporary registers allocation for the 3 wire Registers independent operating mode Allocation LOGIC_ID 5 3 WIRE INDEPENDENT MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC 1 HMI ah 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value ae 3 L01 HMI fallback value 4 L02 HMI fallback valu
85. it The following window is displayed Properties c W Aj HE Z I Block ID 0 Comments Non volatile Register Register Address 15 In the Comment zone in the white box on the right of Comments you can enter a comment Select any object or any free location in the workspace to save the comment Most blocks have a specific settings tab In this tab you have to set the block s specific settings These settings are described in detail in the help for each of the FBD blocks The properties of each block can be displayed in 2 different ways e by category clicking on z e by alphabetical order clicking on Z 1639507 12 2006 141 Function Block Diagram Language FBD Resource Management At a Glance The LTM R controller memory is equipped with the following resources e Logic memory space size equal to 8192 e 300 temporary registers e 64 non volatile registers Reserved When a custom logic program is developed using the structured text editor all Resources resources are available whereas when using the FBD editor some temporary and non volatile registers are reserved for use by the FBD compiler Register The following table lists all reserved registers and their allocation It also indicates Allocation how these registers are controlled Register type Address Controlled by Descr
86. logical or wi th previous LO2 HMI fallback ON OFF 4 fallback to ON equal logical or wi th previous LO1 HMI fallback OFF ON 5 fallback to ON equal logical or wi th previous LO2 HMI fallback value value value value 1639507 12 2006 195 Pre Defined Structured Text Programs Structured Text Program cont d Latch HMI Keypad info LOAD_BIT 1020 12 Aux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Aux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 13 14 HMI Stop Key OR_NOT_BIT 457 3 NOT Stop OR_BIT 456 5 Load Shed SET_TMP_ BIT 4 5 Save partial Global Stop LOAD_NOT_TMP_BIT 3 0 NOT PLC active AND_NOT_TMP_BIT 3 1 NOT HMI active AND_NOT_TMP_BIT 3 2 NOT TS active OR_TMP_BIT 4 5 include partial Global Stop SET_TMP_BIT 4 5 Save final Global Stop Ed uatch comm loss values in scratch 0 LOAD_BIT 456 8 PLC Comm Loss SET_TMP_ BIT 0 0 save in scratch bit 0 LOAD_BIT 456 7 HMI Comm Loss SET_TMP BIT 0 1 save in scratch bit 1 196 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stopl and Stop2 Commands LOAD_TMP_BIT 4 5 SET_TMP BIT LOAD_TMP_BIT 0 0 AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT
87. n unnumbered program line Comments must be inserted after a double slash such as COMMENTS GO HERE Register which is used to store and provide access to the custom logic program Device In the broadest terms any electronic unit that can be added to a network More specifically a programmable electronic unit e g PLC numeric controller or robot or I O card 1639507 12 2006 317 Glossary F FBD Function Block Diagram FBD mode allows graphic programming based on the use of predefined function blocks FBD editor A program editor used to create and edit logic programs based on the FBD language Also called graphical editor FLC full load current Also known as rated current The current the motor will draw at the rated voltage and rated load The controller has two FLC settings FLC1 Motor Full Load Current Ratio and FLC2 Motor High Speed Full Load Current Ratio each set as a percentage of FLC max H HMI Human Machine Interface L Logic command Logic memory A structured text program consists of a series of logic commands Each instruction consists of the logic command itself mnemonic plus up to 3 arguments Part of the internal memory where the custom logic program is stored Mnemonic A structured text program consists of a series of logic commands Each instruction consists of the mnemonic plus up to 3 arguments 318 1639507 12 2006 Glossary Non volatile Regis
88. of this bit decreases the Count by a value of 1 Set BOOL Argument 3 Bit 6 the rising edge of this bit sets the Count equal to the PresetValue Output arguments Count UINT Argument 1 the count An integer from 0 to 65 535 Zero BOOL Argument 3 Bit 0 indicates that the Count value is 0 LT BOOL Argument 3 Bit 1 indicates that the Count value is less than the PresetValue EQ BOOL Argument 3 Bit 2 indicates that the Count value equals the PresetValue GT BOOL Argument 3 Bit 3 indicates that the Count value is greater than the PresetValue IncHistory BOOL Argument 3 Bit 7 indicates the status of the Increment bit Argument 3 Bit 4 from the previous scan DechHistory BOOL Argument 3 Bit 8 indicates the status of the Decrement bit Argument 3 Bit 5 from the previous scan SetHistory BOOL Argument 3 Bit 9 indicates the status of the Set bit Argument 3 Bit 6 from the previous scan 92 1639507 12 2006 Structured Text Language Math Logic Commands Overview The custom logic editor uses the following math commands ON_ADD ON_SUB ON_MUL ON_DIV ON_ADD The ON_ADD command performs unsigned addition when the bit accumulator transitions from 0 to 1 It adds the value from Argument 1 to the 16 bit accumulator value then posts the result back to the Value in Argument 1 A status register e indicates a
89. pair hited ihe pts OS eee de Paks ude els 40 Logic Commands 2 50 4080004 204 dae eae Bee IN Gee ee et ee a 43 Logic Command wis scree ae ep dak oP PRA Betta eae 53 Program Logic Commands 000 cece eet 54 Boolean Logic Commands 000 cece 55 Register Logic Commands aaan eee eee 69 Timer Logic Commands 000 c cece cette eee 85 Latch Logic Commands 00 0 cece teen ae 89 Counter Logic Commands 0000 cece ete eee 91 Math Logic Commands 0 0 cece tte teas 93 Structured Text Program Examples 0 000 e cece eee eee ae 97 How to Check Timers and Multiply Commands 0 0000 eee eee 98 How to Create a Truth Table 0 eee 99 Compiling and Simulation of a Structured Text Language Program 102 Introduction st 3 ea Pe ek dele Ma eM ed ee EEN de 103 PCode WINJOW anaiss tac cone il aaa ara nn E ane So eee Sa RA OA 104 Error WindOW 08 i048 oeage i ees Vai FS iy 106 Chapter 3 3 1 3 2 3 3 3 4 3 5 Chapter 4 Output Window si asesi teen eee 108 Quick Watch Window 0002 0c cece cette eee 110 LTM R Controller Logic Simulator 0000 cece eee ee 112 Function Block Diagram Language 00 5 115 Overview of FBD Language 0 ccc eee tees 116 Introduction to the FBD Editor 0 0 0 cee eee 117 FBD Editor Toolbox 2 2 ett ee 120 FBD Elements 20403 Sette iat dw B
90. the LTM R controller Controller memory includes data registers located at addresses ranging from 0 to1399 Each register is a 16 bit word and is either e read only with values that cannot be edited or e read write with values that can be edited Using the custom logic editor you can access and edit some of the LTM R controller variables See the sections on Communication Variables in the Use chapter of the Motor Management Controller TeSys T LTM R User s Manual for a description of these variables and communication protocol registers In structured text language the following logic commands can be used to edit the values of read write data registers Logic Command Can write to SET_BIT 1 bit in a read write data register SET_NOT_BIT 1 bit in a read write data register ON_SET_REG All bits of a 16 bit read write data register Registers 1200 to 1205 are used by the LTM CONF programming software to access internal register data within the LTM R controller These registers are also the custom logic registers accessible from the communication ports These registers are described in the following sections The table below lists these registers Register Definition CONFIG LTMR Range value Access Access 1200 LTM R logic interface 1201 Logic version 1202 Logic memory space available Read R W 0 to 65 535 1203 Logic memory used 1204 Temporary registers available 1205
91. 0 Manage Output 1 State set Step 1 time period check for 10 FLC LOAD_REG 466 COMP_K_REG 10 0 LOAD_TMP_BIT 0 3 AND_TMP_BIT 5 1 OR_TMP_BIT 5 2 SET_TMP_BIT 5 2 LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP_BIT 5 1 Oo ol U1 e WN Manage Step 1 LOAD_TMP_BIT 5 2 SET_TMP_BIT 8 0 TIMER_TENTHS 6 7 8 State 5 Look for current over LOAD_REG 466 COMP_REG 644 0 LOAD_TMP_BIT 0 3 OR_TMP_BIT 0 2 AND_TMP_BIT 5 2 OR_TMP_BIT 5 5 AND_TMP_BIT SET_TMP_BIT 5 2 5 35 Clear the history bit Lockout 1 Time value set current time period 5 1 Average Current over 10 greater than Output 1 State Step 1 State Step 1 State SFLC NOT NOT Idle State Step 1 State NOT Lockout State NOT Output 2 State Output 1 State lt 2 Step 1 State enable Step 1 timer process timer threshold Average Current Threshold Level greater than equal to Step 1 State Threshold Current Detected Step 1 State Threshold Current Detected SFLC 1639507 12 2006 269 Pre Defined Structured Text Programs Structured Text Program cont d Look for current under threshold Average Current Threshold Level LOAD_REG 466 COMP_REG 644 0 LOAD_TMP_BIT 0 1 AND_TMP_BIT 5 5 OR_TMP_BIT 8 1 S AND_TMP_BIT 5 2 OR_TMP_BIT 5 3 T
92. 0 LOAD_BIT 683 8 SET_TMP_BIT 0 1 LOAD_BIT 516 5 SET_TMP_BIT 0 0 SET_TMP_BIT 2 0 LOAD_NOT_TMP_BIT 0 0 AND_TEP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 LOAD_NOT_TMP_BIT 1 LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 SET_TMP_BIT 12 7 4 OR_TMP_BIT 12 10 SET_TMP_BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 2 Line N Description 2 WIRE TWO STEP MODE TS HMI debounce TS HMI in scratch 1 1 LI6 debounce LI6 in scratch PLC Control _ LI6 debouncea TS HMI debounced HMI Control UI6 debounced TS HMI debounced TS Control Transfert in Process save old Transfert in Process Requested Mode ie Active Mode egual nsrert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not Bumpless Look for Edge Transfert in Process edt 1 age 1 cansfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process requested active not Transfert in Process HMI requested HMI active not Transfert in Process TS requested 17 Invalid Logic Statement format should be Mnemonic Arg1 Arg2 28 Invalid Number of
93. 0 10 SET_BIT 1200 5 LOAD_TMP_BIT 4 10 OR_TMP_BIT 4 11 SET_BIT 1200 0 SET_NOT_BIT 1200 1 LOAD_TMP_BIT 4 12 SET_BIT 1200 4 LOAD BIT 455 3 SET_BIT 1200 14 LOAD BIT 455 2 SET_NOT_BIT 1200 15 LOAD BIT 457 4 SET_BIT 1200 LOAD_TMP_BIT BIT 1200 LOAD_TMP_BIT OR_TMP_BIT 4 12 SET_BIT 1200 11 io POW ND uo Process Output 1 Forward Output 1 Aux 1 LED Process Output 2 Reverse Output 2 Aux 2 LED Phase Reverse Forward Reverse Motor Run Motor Stop Reversing Timer Transition Timer Process other outputs IMPR Alarm status Output 3 Alarm IMPR Fault status Output 4 Fault Reset Input LI5 Logic Reset PLC active Logic Local Remote Global Stop Reversing Timer Active Stop LED 1639507 12 2006 243 Pre Defined Structured Text Programs Structured Text Program cont d Manage Power UP Done LOAD_NOT_TMP_BIT 4 12 Wait for power up timer OR_TMP_BIT 12 12 Latch ON until next power up SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Run1 and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 244 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program
94. 07 12 2006 47 Structured Text Language Command Argument 1 Argument 2 Argument 3 Description AND_REG Register address Makes a logical AND link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator AND_TMP_REG Temporary Makes a logical AND link between the register address temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator AND_NV_REG Non volatile Makes a logical AND link between the non register address volatile register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_K Constant value Makes a logical OR link between the 0 to 65 535 constant value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_REG Register address Makes a logical OR link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_TMP_REG Temporary Makes a logical OR link between the register address temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_NV_REG Non volatile Makes a logical exclusive OR link between register address the non volatile register value and the 16 bit accumulator content The result is stored in the 16
95. 1 uw ws a 1 aw 11 aw a 1 11 aw 2 WIRE TWO STEP MODE TS HMI debounce TS HMI in scratch 71 LI6 debounce LI6 in scratch PLC Control _ UI6 debouncea TS HMI debounced HMI Control 71 LI6 debounced TS HMI debounced TS Control Transfer in Process save old Transfer in Process Requested Mode is it Active Mode Not equal Transfer in Process Transfer in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfer in Process Not Bumpless Look for Edge Transfer in Process Mode Wait 1 Mode Change 1 Transfer in Process Mode Wait 2 Mode Change 2 not Transfer in Process PLC requested PLC active not Transfer in Process HMI requested HMI active not Transfer in Process TS requested TS active PLC fallback mode HOLD 0 Gast LOL command Last L02 command equal L01 PLC fallback STEP 1 LTM CONF ES Connected A progress bar briefly appears as your PC connects to the controller and the word Connected appears in the task bar when the connection process successfully completes When the LTM R controller is connected you can e upload custom logic files from the controller to LTM CONF software for editing e download edited custom logic files from LTM CONF software to the controller 1639507 12 2006 157 Connection to the LTM R Controller Transferring Logic Files between the LTM R Controller and Cu
96. 1 IMPR 13 LO 2 IMPR 23 LO 3 IMPR 33 LO 4 IMPR 95 lv Enable Inputs 457 0 LI 1 IMPR R1 457 1 LI 2 IMPR R2 457 2 LI 3 IMPR Spare 457 3 LI 4 IMPR STPn 457 4 LI 5 IMPR RST 457 5 LI 6 IMPR L R 457 6 LI7 KE 457 7 LI8 KE 457 8 LI9 KE 457 9 LI 10 KE Address Data 704 0 Write IMPR Reg Open Logic Function File 112 1639507 12 2006 Structured Text Language Register View Logic Primitives Window View Window Registers 1200 and 458 4 kinds of registers are displayed by the logic simulator e LTM R controller registers e Temporary registers e Non volatile registers e Logic memory Those registers can not be displayed in the same time The Register View enables you to choose which ones you wish to monitor In the example above the content of the logic memory is displayed Note By default registers values are displayed in decimal code Tick the Hex box if you would prefer them to be in hexadecimal code The Logic Primitives window displays the compiled PCode see p 104 Note The PCode may read or write to any READ WRITE register that is accessible by serial port communications The logic simulator displays the content of LTM R controller registers 1200 to 1225 in hexadecimal code See part 1 on the illustration above Registers 1200 to 1205 see p 26 are the custom logic registers The logic simulator displays the status of registe
97. 12 0 MP_BIT 0 1 OAD_NOT_BIT 704 0 R_NOT_BIT 704 6 MP_BIT 3 0 D_TMP BIT 4 8 NOT_TMP_ BIT 0 0 OR_TMP_BIT 4 6 s Generate Stop1 Global Stop NOT Powerup Done save partial Stopl PLC Comm Loss from scratch PLC active NOT LO1l PLC fallback value Include partial Stop1 save partial Stopl HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop1 save partial Stopl NOT PLC Runt NOT Low Speed PLC active Run 1 NOT PLC Comm Loss from scratch Include partial Stopl save final Stopl 306 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BI OR_NOT_TMP_ SET_TMP_BIT LOAD_TMP_BI AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT SET_TMP BIT LOAD_TMP_BI AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT SET_TMP_BIT LOAD_NOT_BI OR_BIT 704 AND_TMP_BIT AND_TMP_BIT AND_NOT_TMP OR_TMP_BIT SET_TMP BIT T 4 5 BIT 12 12 4 7 T 0 0 3 0 BIT 4 2 4 7 4 7 T 0 1 341 BIT 4 4 4 7 4 7 T 704 0 6 3 0 4 9 BIT 0 0 4 7 4 7 Generate Stop2 Global Stop NOT Powerup Done save partial Stop7 PLC Comm Loss from scratch PLC active NOT LO2 PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop2 save partial Stop2 NOT
98. 13 12 13 13 and 13 14 Generate Stop Commands Manage Global Stop Detect Global Stop Inputs SET Global Stop in Temp Reg 4 5 Latch comm loss values for use in Stop and Run Commands Detect PLC and HMI Comm Loss Save status to Temp Reg bit 0 0 and 0 1 Generate Stop1 Commands Detect Stopl input status Save Stopl command to Temp Reg 4 6 Generate Stop2 Commands Detect Stop 2 input status Save Stop2 Command to Temp Reg 4 7 1639507 12 2006 173 Programming Approach Program Sections cont d Generate Run 1 And Run 2 Commands Generate Run 1 PLC HMI TS Mode Save previous Runl history in Temp Reg 12 0 Save new Run2 history in Temp Reg 12 1 PLC 12 3 HMI or 12 5 TS T new Run1 command Save partial Run 1 to Temp Reg 4 8 3wire latch Runl Detect No Runl inhibits Save final Run 1 to Temp Reg 4 8 Generate Run 2 PLC HMI TS Mode Save previous Run2 history in Temp Reg 12 0 Save new Run2 history in Temp Reg 12 2 PLC 12 4 HMI or 12 6 TS T new Run2 command Save partial Run2 to Temp Reg 4 9 3wire latch Run 2 Detect no Run2 inhibits Save final Run 2 to Temp Reg 4 9 Set Outputs to IMPR Process Output 1 T Runl Temp 4 8 active and NO Stop 1 command Temp 4 6 SET Output 1 1200 12 Auxl LED 1200 9 Motor Run 1200 0 Motor Stop 1200 1 Process Output 2 IF Run2 Temp 4 9 active and NO Stop 2 Command 4 7 SET Output 2 1200 13 and Aux 2 LED ON 1200 10
99. 1639507 TeSys TLTMR Motor Management Controller Custom Logic Editor User s Manual 1639507 1 0 12 2006 mixi Bile Edt Link Settings Tools View Help PHO S aea ee TeSys T Device Information fei Settings m Custom Logic E Telemecanique LTMCONF Wk Disconneci ted a brand of ie Telemecanique www telemecanique com Table of Contents Chapter 1 Chapter 2 2 1 2 2 2 3 2 4 Safety Information 2 00 e eee eee eee 7 About the BOOK shia hehe aia tet ere aD he ees 9 Introduction to Custom Logic Editor 2005 11 Introduction to the LTM R Controller 0 0 0 0 0 c eects 12 Operating Modes 0 so 55 fie ace n ae ate wad ay Peeper ees ele Gee 15 Presentation of the Custom Logic Editor 0 000 ee eee eee 16 Using the Custom Logic Editor 20 0 cece eee 21 Characteristics of the Custom Logic Program 0 cece eee eee 24 Definition of the Custom Logic Variables 0 000 cece eee eee eee 25 Definition of the LTM R Variables 0 0 eee ee eee 26 Structured Text Language 2 0ee eee eee eee eee 29 Creating a Structured Text Program 1 2 0 cece ete 30 Introducing the Structured Text Editor 0 0 0 cece eee eee eee 31 Structured Text Editor User Interfaces 0000 c eee eee eee 33 NOX VIOW haus raian he yaa gs ea Bok ghee Rete Beas De A A Pas 36 Grid View sitesi eae
100. 2 LOAD_REG 682 COMP_K_REG 0 0 LOAD_BIT 1200 12 OR_BIT 1200 13 AND_TMP_BIT 0 2 SET_TMP_BIT 4 1 COMP_K_REG 1 0 2 WIRE TWO STEP MODE 7 PS HMr debounce TS HMI in scratch LI6 debounce LI6 in scratch PLC Control _ LI6 debounced TS HMI debounced HMI Control LI6 debounced TS HMI debounced TS Control Transfert in Process save old Transfert in Process Requested Mode is it Active Mode _ Not egual Transfert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not Bumpless Look for Edge Transfert in Process Mode Wait 1 Mode Change 1 Transfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process PLC requested PLC active not Transfert in Process HMI requested HMI active not Transfert in Process TS requested TS active PLC fallback mode HOLD 0 bast LO1 command Last L02 command egual L01 PLC fallback STEP 1 LTM CONF Connected 1639507 12 2006 19 Introduction to Custom Logic Editor FBD Editor The following illustration shows the FBD editor integrated in PowerSuite Function Block Editor 2 0 BE File Edit Compile View Tools About Toolbox lt Ta Computation ia Inputs a 1 fe 1 1 See See 1 IN LTMR NV NV _ LTMR Tmp _ 16 Tmp r Bit 2 0 Write Temporary 24 Write Temporary MIRBGister
101. 2 2 LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 1 LOAD_NOT_TMP BIT 12 SET_TMP_BIT 4 0 LOAD_TMP_BIT 4 0 AND_NOT_TMP BIT 12 11 AND_BIT 683 10 1 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 OR_TMP_BIT 12 8 SET_TMP_BIT 12 7 LOAD_TMP_BIT 4 0 OR_TMP_BIT 12 10 SET_TMP BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0 AND_TMP BIT 2 1 SET_TMP_BIT 3 1 LOAD NOT_TMP_BIT 4 0 AND_TMP_BIT 2 2 PCode a D xX 2 WIRE TWO STEP MODE TS HMI debounce TS HMI in scratch J LI6 debounce LI6 in scratch PLC Control _ LI6 debounced TS HMI debounced HMI Control _ LI6 debounced TS HMI debounced TS Control Transfert in Process save old Transfert in Process Requested Mode is it Active Mode Not egual Transfert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not Bumpless Look for Edge Transfert in Process Mode Wait 1 Mode Change 1 Transfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process PLC requested PLC active not Transfert in Process HMI requested HMI active not Transfert in Process TS requested Description rC 740 42436 400 2 683 8 21 0 Total Tokens CheckSum Argument O LOAD_BIT Argument 0 Argument 1 SET_TMP_BIT Argument 0 Type WordConstant
102. 22 COMP_K_REG 100 0 Is result 100 LOAD_TMP_ BIT 10 2 timer 2 timing AND_TMP_BIT 0 2 100 SET_BIT 1200 13 Don t switch LO2 if MUL did not work OK 98 1639507 12 2006 Structured Text Language How to Create a Truth Table Overview Creating a Truth Table with a Structured Text Program Customizing your application you may need to create a truth table The following diagram gives the structured Text program in Text View of the creation of a truth table LOGIC_ID 444 by Truth table example I H N H Ww Output 0 O O Oo Our rPRODOrRFrROOS rPOrROrFOrF Oo O O GO HOOH NYHA OP WDNR OC LOAD_BIT 516 0 SET INPUTS SET_TMP BIT 1 1 LOAD BIT 516 1 SET_TMP BIT 1 2 L s OAD_BIT 516 2 ET_TMP_BIT 1 3 3x1 TRUTH TABLE TEMPLATE Inputs defined as bits 1 1 through 1 3 Output defined as bit 1 15 LOAD_K_BIT 0 default output OFF SET_TMP_BIT 1 15 save partial result RRRRKKKKKKKKAKEOK Tnputs 1 2 3 are OFF OFF OFF LOAD_NOT_TMP_BIT 1 1 include this SECTION AND_NOT_TMP_BIT 1 2 if output is to be ON AND_NOT_TMP_BIT 1 3 REMOVE if output to be OFF SET_TMP_BIT 1 15 save partial result 1639507 12 2006 99 Structured Text Language Creating a Truth Table with a Structured Text Program cont d L
103. 3 TMP BIT 12 4 D_NOT_TMP_BIT 12 0 TMP BIT 3 1 D_NOT_TMP_BIT 4 D_NOT_TMP_BIT 0 1 D_NOT_TMP_BIT 4 12 R_TMP_BIT 4 9 ET_TMP_BIT 4 9 N t A 3 2p E2 EHO D 0 E 4 gt on Pe D nO LOAD_TMP_BIT 12 6 SET_TMP_BIT 12 0 OAD_BIT 457 1 ET_TMP_BIT 12 6 D_NOT_TMP_BIT 12 0 _TMP_BIT 3 2 D_NOT_TMP_BIT 4 7 D_NOT_TMP_BIT 4 12 R_TMP_BIT 4 9 ET_TMP_BIT 4 9 s Lp AEE D 5 gt gt nO Generate Run 2 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Runt NOT PLC Low Speed Power up Done NOT Stop 2 Save new history NOT previous history PLC active NOT Stop2 NOT PLC Comm Loss from scratch Include previous result save partial Run2 HMI mode Input history Save previous history HMI Run2 Save new history NOT previous history HMI active NOT Stop 2 NOT HMI Comm Loss from scratch Lockout Timer Include previous result save partial Run2 TS mode Input history Save previous history LI2 Save new history NOT previous history TS active NOT Stop 2 Lockout Timer Include previous result save partial Run2 310 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 2 AND_TMP_BIT AND_TMP_BIT 3 0 0 0 OR_TMP_BIT 4 4 SET_TMP
104. 3 SET_TMP_BIT 11 0 TIMER_TENTHS 9 10 11 LOAD_TMP BIT 11 2 SET_TMP BIT 4 12 LOAD_TMP_ BIT 11 1 AND_TMP_BIT 5 3 OR_TMP_BIT 5 4 n tj ET_TMP_BIT 5 4 LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP_BIT 5 3 ou uw BN Look for current under threshold Average Current Threshold Level less than Threshold Current Detected timed out Step 1 State Lockout State Lockout State SFLC NOT NOT Idle State Output 1 State NOT Lockout State NOT Output 2 State Step 1 State Step 1 State enable Lockout timer process timer timing Lockout timer timed out Lockout State Step 2 State Step 2 State NOT Idle State NOT Output 1 State NOT Step 1 State NOT Output 2 State Lockout State 282 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Manage Output 2 State LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT 5 1 AND_NOT_TMP_BIT 5 2 AND_NOT_TMP_BIT 5 3 SET_TMP_BIT 5 4 Set Outputs to IMPR LOAD_TMP_BIT 5 1 OR_TMP_BIT 5 2 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 12 SET_BIT 1200 9 5 4 NOT Idle State NOT Output 1 State NOT Step 1 State NOT Lockout State Output 2 State Process Output 1 Output 1 State Step 1 State NOT Stop 1 Output 1 Aux 1 LED Process Outpu
105. 3 0 0 0 ET_TMP_BIT 4 8 LOAD_TMP_BIT 4 3 AND_TMP_BIT 3 MP_BIT 0 MP BIT 4 8 ET TMP _BIT 4 8 2 oO EH n o 8 AND_NOT_TMP_BIT 4 6 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 Manage Idle State LOAD_TMP_BIT 4 8 AND_TMP_BIT 5 0 OR_TMP_BIT 5 1 SET_TMP_BIT 5 1 Li s OAD_TMP_BIT 4 8 T_NOT_TMP_BIT 5 0 1s Set up Step 1 Timer LOAD_K_BIT 1 SET_NOT_TMP BIT 0 3 LOAD_REG 643 ON_SET_TMP_REG 6 0 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Stop 1 NOT Swapping NOT Mode Change 1 save final Run 1 Generate Run 2 NA 5 0 Run 1 Tdle State Output 1 State Output 1 State Run 1 Idle State Clear the history bit Step 1 Time value set current time period 280 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Set up Lockout Timer SET_NOT_TMP_BIT 0 3 LOAD_REG 541 ON_SET_TMP_R G 9 0 Manage Output 1 State set Step 1 time period check for 10 FLC LOAD _REG 466 COMP_K_REG 10 0 LOAD_TMP_BIT 0 3 AND_TMP_BIT 5 1 OR_TMP_BIT 5 2 SET_TMP_BIT 5 2 n r LOAD_NOT_1 AN
106. 3 Wire 2 Speed Mode 300 1639507 12 2006 179 Pre Defined Structured Text Programs Structured Text Program for 2 Wire Overload Mode Overview The structured text program for the 2 wire overload mode is defined below Structured Text Program LOGIC_ID 2 2 WIRE OVERLOAD MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 4 as state bits group 1 ffs 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value Td 5 Global Stop 6 Stop1 7 Stop2 8 Runl 9 Run2 Temp 5 as state bits group 2 Temp 12 as INPUT History 1 PLC Run 1 2 PLC Run 2 fas 3 HMI Run 1 4 HMI Run 2 5 TS Run 1 Lb 6 TS Run 2 7 Mode Change 1 8 180 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONS Temp 52 as ONS Temp 53 Latch p T status Low to High timer T status High to Low timer EEF EE Temp 54 as ONSET status
107. 54 1639507 12 2006 Connection to the LTM R Controller Connecting toa PC running LTM CONF Software in 1 to Many Mode Connection Accessories The diagram below shows a 1 to many connection from a PC running LTM CONF software to up to 8 controllers with or without the expansion module PC running LTM CONF software Power cable VW3 A8 106 T junction boxes VW3 A8 306 TFee Communication cable VW3 A83 06Ree line terminators VW3 A8 306 R LTM R controller Expansion module NO ROD The following table lists connection accessories Designation Description Reference With 0 3 m 1 ft integrated cable VW3 A8 306 TFO3 T junction boxes With 1 m 3 2 ft integrated cable VW3 A8 306 TF10 Line terminators for R 150Q VW3 A8 306 R RJ45 connector Power cable Length 1 m 3 2 ft VW3A8106 PC only RS 232 to RS 485 converter Length 0 3 m 1 ft Communication cables VW3 A8 306 R03 Length 1 m 3 2 ft VW3 A8 306 R10 1639507 12 2006 155 Connection to the LTM R Controller Initialization and Connection Initialization When you connect the LTM R controller to the PC the controller automatically initializes This initialization process enables the controller and the PC to exchange identification information During this process the custom logic editor indicates Wait unt
108. 6 265 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 5 SET_TMP_BIT 4 6 TMP_BIT 0 0 TMP BIT 3 0 D_NOT_TMP BIT 4 1 BIT 4 6 P_BIT 4 6 MP_BIT 0 1 P_ BIT 3 1 T TMP BIT 4 3 TMP BIT 4 6 ET TMP _BIT 4 6 eee ggg _ ou n BeESES 66s 41 aay oy Ree 68H zn nO zo Ss as D OAD_TMP_BIT 3 0 ND_NOT_BIT 704 0 D_TMP_BIT 4 8 D_NOT_TMP_BIT 0 0 MP_BIT 4 6 TMP_BIT 4 6 gt 2 2 no Hw H jo OAD_TMP_BIT 3 1 ND_NOT_TMP_BIT 13 12 D_TMP_BIT 4 8 D_NOT_TMP_BIT 0 1 MP_BIT 4 6 TMP_BIT 4 6 gt 2 2 no mw LOAD_TMP_BIT 3 2 AND_NOT_BIT 457 0 AND_TMP_BIT 4 8 OR_TMP_BIT 4 6 SI zo T_TMP_BIT 4 6 B Generate Stop1 and Stop2 Commands Generate Stopl Global Stop save partial Stopl PLC Comm Loss from scratch PLC active NOT LO1l PLC fallback value Include partial Stop1 save partial Stopl HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop1 save partial Stopl PLC active NOT PLC Runt Run 1 NOT PLC Comm Loss from scratch Include partial Stopl save partial Stopl HMI active NOT HMI Run 1 Run 1 NOT HMI Comm Loss from scratch Include partial Stopl save partial Stopl TS active NOT TS Run 1 Run 1 Include partial Stopl save final Stopl Generate
109. 7 12 2006 Structured Text Language Introduction Compiling Overview Compiling a Program You must compile the structured text language program before you can download it to the LTM R controller Compiling includes a check for program errors such as e syntax and structure errors e symbols without corresponding addresses e resources used by the program that are not available e whether the program fits in available controller memory Once you finish editing the program follow these steps to compile it Step Action 1 Click Logic Functions in the top level menu bar 2 Click Compile in the displayed window If no errors are detected the PCode window is displayed Otherwise the Errors window is displayed 1639507 12 2006 103 Structured Text Language PCode Window Overview LTM CONF Default File Edit Link Settings When a custom logic program is compiled successfully the PCode Pseudo Code window is displayed Logic Functions Tools View Help z8 Tesys T B Device Information ae Settings lt gt Statistics gt Monitoring 45 Parameters aa Custom Logic Structured Text 45 Function Blocks Paes SS eR MSs Untitled if LOGIC_ID 400 LOAD_BIT 683 8 SET_TMP_BIT 0 1 LOAD_BIT 516 5 SET_TMP_BIT 0 0 SET_TMP_BIT 2 0 LOAD_NOT_TMP BIT 0 0 AND_TEP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP BIT
110. 704 Runl Run2 Save Requested Control in Temp 2 LOAD_BIT 683 8 TS HMI SET_TMP_BIT 0 1 Debounce TS HMI in scratch LOAD BIT 457 5 LI6 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control Look for control transfer LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD _NOT_TMP_BIT 1 2 Not equal SET_TMP_BIT 4 0 Transfer in Process 1639507 12 2006 181 Pre Defined Structured Text Programs Structured Text Program cont d Manage Bump Bumpless LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP BIT 12 7 Mode Change 1 SET_TMP_BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC ac
111. AD_TMP_BIT 0 0 4 7 30 BIT 4 2 4 7 P BIT 4 7 MP BIT 0 1 gt BIT T TMP 3 1 BIT 4 4 4 7 4 7 OAD_TMP BIT 3 0 T 704 1 r 4 9 D_NOT_TMP_BIT 0 0 AST no Hw H TMP BI T 4 7 Generate Stop2 Global Stop NOT Powerup Done save partial Stop7 PLC Comm PLC active NOT LO2 Include Loss from scratch PLC fallback value partial Stop2 save partial Stop2 HMI Comm HMI active NOT LO1 Include Loss from scratch HMI fallback value partial Stop2 save partial Stop2 PLC acti NOT PLC Run 2 ve Run2 NOT PLC Comm Loss from scratch Include partial Stop2 save final Stop2 222 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands Generate Run 1 PLC mode LOAD_TMP_BIT 12 1 Input history AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 0 Save previous history LOAD BIT 704 0 PLC Network Runl AND_TMP_BIT 12 12 Power up Done AND_NOT_BIT 456 4 NOT Rapid Cycle AND_NOT_TMP_BIT 4 6 NOT Stop 1 SET_TMP_BIT 12 1 Save new history AND_NOT_TMP BIT 12 0 NOT previous history AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8
112. BD Function Block 136 Register Temp Word In Register Temp Word In FBD Function Block 127 Register Temp Word Out Register Temp Word Out FBD Function Block 136 Register View 113 Register Word In Register Word In FBD Function Block 126 Register Word Out Register Word Out FBD Function Block 135 Resource management 142 S Saving 39 Logic files 159 Scan 168 Selecting FBD Blocks 145 SET_BIT 66 SET_NOT_BIT 67 SET_NOT_NV_BIT 68 SET_NOT_TMP_BIT 68 SET_NV_BIT 67 SET_TMP_BIT 66 Simulator 112 324 1639507 12 2006 Index Start a Trace 114 Structured text editor Editing a structured text file 31 Using the structured text editor 31 Structured text program 30 Substraction Substraction FBD Function Block 123 T TeSys T Motor management system 12 Text view 36 Timer Seconds Timer Seconds FBD Function Block 132 Timer TenthSeconds Timer TenthSeconds FBD Function Blocks 132 TIMER_K_SEC 87 TIMER_K_TENTHS 88 TIMER_SEC 85 TIMER_TENTHS 86 Toolbox Computation Blocks 122 FBD Editor Toolbox 120 Function Blocks 128 Inputs Blocks 125 Logic Blocks 133 Outputs Blocks 134 Transferring Execution 162 Logic files 158 LTM R controller to PC 158 PC to LTM R controller 160 V Variables Custom logic variables 25 LTM R variables 26 View window 113 Volatile Latch Volatile Latch FBD Function Block 130 W Wiring requirements 168 Workspace Appearance options 149 Gr
113. BIT 2 1 NOT_TMP_BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 Look for control trans LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 1 LOAD_NOT_TMP_ BIT 1 2 SET_TMP_BIT 4 0 E O D O a a Process e tatus registers tus transition time value tus Low to High timer tus High to Low timer tus 704 Runi Run2 in Temp 2 TS HMI Debounce TS HMI in scratch LI6 Debounce LI6 in scratch PLC Control LI6 debounced TS HMI debounced HMI Control LI6 debounced TS HMI debounced TS Control fer Transfer in Process save old Transfer in Process Requested Mode is it Active Mode Not equal Transfer in Process 286 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Bump Bumpless LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 SET_TMP BIT 12 7 SET_TMP_BIT 12 9 Transfer in Process NOT Bumpless in Process Bumpless new Bumpless in Process one scan Transfer in Process Not bumpless Look for Edge Transfer in Process Mode Change 1 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BI1 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_N
114. BIT 457 1 12 6 T 12 0 T 4 7 4 7 4 13 12 9 TS mode Input history Save previous history LI2 Save new history NOT previous history TS active NOT Stop 2 temp NOT Last Dir Forward Lockout Timer temp Include previous result save partial Run2 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 3wire latch NOT Stop 2 NOT Swapping NOT Mode Change 2 save final Run 2 256 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Direct Transfer Mechanism force opposite direction on swap LOAD_TMP_BIT 4 14 AND_TMP_BIT 4 13 OR_TMP_BIT 4 9 SET_TMP_BIT 4 9 last direction Swapping Run 2 Run 2 force opposite direction on swap LOAD _NOT_TMP_BIT 4 14 AND_TMP_BIT 4 13 OR_TMP_BIT 4 8 SET_TMP_BIT 4 8 NOT last direction Swapping Run 1 Run 1 look for both directions ON LOAD_TMP_BIT 4 8 AND_TMP_BIT 4 9 AND_BIT 683 9 AND_NOT_TMP_BIT 3 0 SET_TMP_BIT 4 13 LOAD_TMP_BIT 3 0 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 4 14 OR_TMP_BIT 4 15 SET_TMP_BIT 4 15 LOAD_TMP_BIT 3 0 AND_TMP_BIT 4 9 AND_TMP_BIT 4 14 OR_TMP_BIT 4 15 SET_TMP_BIT 4 15
115. C 1 HMI 2 TS terminal strip Temp 4 as state bits group 1 Lt 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value 5 Global Stop 6 Stop1 7 Stop2 8 Run1 9 Run2 Temp 5 as state bits group 2 Temp 12 as INPUT History 1 PLC Run 1 Td 2 PLC Run 2 3 HMI Run 1 tb 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 202 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Fel 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONS Temp 51 as ONS Temp 52 as ONS Temp 53 Latch Temp 54 as ONS T status transition time value status Low to High timer T status High to Low timer EJ EEE EF PI 5 status 704 Runl Run2 CY E J Save Requested Control in Temp 2 LOAD_BIT 683 8 TS HMI SET_TMP_BIT 0 1 Debounce TS HMI in scratch LOAD BIT 457 5 LI6 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control Look for control tr
116. Control on Control Transfer Inputs Outputs Address Description Address Description T 4 0 Transfer Active 704 Commands 683 10 Bumpless T 54 ON Set 704 Command Reg Note Single bit designations are represented by an address and decimal For example 457 4 is address 457 bit 4 Sixteen bit word designations are represented by the designation R followed by the address number without a decimal For example R682 is the 16 bit word at address 682 178 1639507 12 2006 Pre Defined Operating Modes Structured Text Programs B At a Glance Overview The LTM R controller supports 10 pre defined operating modes See the section Motor Control Functions in the LTM R Motor Management Controller Reference Manual The following chapter shows the structured text program for each pre defined operating mode What s in this This chapter contains the following topics Chapter Topic Page Structured Text Program for 2 Wire Overload Mode 180 Structured Text Program for 3 Wire Overload Mode 191 Structured Text Program for 2 Wire Independent Mode 202 Structured Text Program for 3 Wire Independent Mode 215 Structured Text Program for 2 Wire Reverser Mode 229 Structured Text Program for 3 Wire Reverser Mode 245 Structured Text Program for 2 Wire 2 Step Mode 261 Structured Text Program for 3 Wire 2 Step Mode 273 Structured Text Program for 2 Wire 2 Speed Mode 285 Structured Text Program for
117. Creating a control program for a LTM R controller consists of writing a series of instructions logic commands in one of the custom logic programming languages The primary purpose of the custom logic editor is to modify the commands used in the control program that e manage local remote control source e define LTM R controller I O logic assignment e Direct timers such as those used to manage the transitions from low voltage to high voltage contactor in a two step reduced voltage starter used to implement the start stop and reset function of a motor controller e manage faults e manage resets The custom logic editor enables you to modify the behavior of the LTM R controller pre defined logic programs operating modes to meet individual application needs The custom logic editor allows you to create programs with different types of languages and then transfer the application to run on a LTM R controller The modifications may range from minor revisions to complete re writes of the LTM R controller pre defined logic programs 16 1639507 12 2006 Introduction to Custom Logic Editor Logic ID Custom Pre Defined Programs There are 2 ways to create a custom logic program e either you edit a pre defined logic program what we will call a custom pre defined program e or you build a new program from scratch what we will call a full custom program The logic ID you must assign to your program has to meet t
118. D_BIT 1200 13 COMP_K_REG 3 LOAD_K_BIT 1 AND_TMP_BIT 0 OR_TMP_BIT 4 SET_TMP_BIT 4 LOAD_K BIT 1 AND_TMP_BIT 0 OR_TMP_BIT 4 SET_TMP BIT 4 2 0 PLC fallback mode HOLD 0 equal last PLC runl command LO1 PLC fallback equal last PLC run2 command LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 fallback to ON equal logical or with previous value LO1 PLC fallback fallback to ON equal logical or with previous value LO2 PLC fallback ON OFF 4 fallback to ON equal logical or with previous value LO1 PLC fallback OFF ON 5 fallback to ON equal logical or with previous value LO2 PLC fallback 1639507 12 2006 205 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values LOAD_REG 645 COMP_K_REG 0 0 LOAD TMP BIT 0 2 AND_BIT 1200 12 SET_TMP BIT 4 3 LOAD_TMP BIT 0 2 AND_BIT 1200 13 COMP_K_REG 3 LOAD_K BIT 1 D R_TMP_BIT 4 Hno Bai 4 OAD_K_BIT 1 AND_TMP_BIT 0 OR_TMP_BIT 4 SET_TMP BIT 4 COMP_K_REG 4 LOAD_K BIT 1 AND_TMP_BIT 0 R_TMP_BIT 4 Qno za OMP_K_REG 5 _BIT 1 Ee oO D 0 N AND_TMP_BIT 0 BIT 4 n oO Ps H E as ND_TMP_BIT 0 MP_BI
119. D_NOT_BIT 58 LOAD_NOT_NV_BIT 59 LOAD_NOT_TMP_BIT 58 LOAD_NV_BIT 57 LOAD_NV_REG 71 LOAD_REG 70 LOAD_TMP_BIT 57 LOAD_TMP_REG 71 Logic Blocks 133 Logic command Grid view 41 Text view 38 Logic Commands 43 322 1639507 12 2006 Index logic commands AND_BIT 59 AND_K 75 AND_NOT_BIT 61 AND_NOT_NV_BIT 62 AND_NOT_TMP_BIT 61 AND_NV_BIT 60 AND_NV_REG 76 AND_REG 75 AND_TMP_BIT 60 AND_TMP_REG 76 COMP_K_REG 72 COMP_NV_REG 74 COMP_REG 72 COMP_TMP_REG 73 COUNTER 91 COUNTER_NV 92 LATCH 89 LATCH_NV 90 LOAD_BIT 56 LOAD_K_BIT 56 LOAD_K_REG 70 LOAD_NOT_BIT 58 LOAD_NOT_NV_BIT 59 LOAD_NOT_TMP_BIT 58 LOAD_NV_BIT 57 LOAD_NV_REG 71 LOAD_REG 70 LOAD_TMP_BIT 57 LOAD_TMP_REG 71 LOGIC_ID 54 NOP 54 ON_ADD 93 ON_DIV 96 ON_MUL 95 ON_SET_NV_REG 84 ON_SET_REG 83 ON_SET_TMP_REG 83 ON_SUB 94 OR_BIT 62 OR_K 77 OR_NOT_BIT 64 OR_NOT_NV_BIT 65 OR_NOT_TMP_BIT 65 OR_NV_BIT 63 OR_NV_REG 78 OR_REG 77 OR_TMP_BIT 63 OR_TMP_REG 78 SET_BIT 66 SET_NOT_BIT 67 SET_NOT_NV_BIT 68 SET_NOT_TMP_BIT 68 SET_NV_BIT 67 SET_TMP_BIT 66 TIMER_K_SEC 87 TIMER_K_TENTHS 88 TIMER_SEC 85 TIMER_TENTHS 86 XOR_K 79 XOR_NV_REG 82 XOR_REG 80 XOR_TMP_REG 81 Logic Primitive window 113 Logic Simulator 112 LOGIC_ID 54 M Memory Logic memory characteristics 24 Multiplication Multiplication FBD Function Block 124 Mux Mux FBD Function Block 131 N Non Volatile Latch
120. D_NOT_TMP_BI1 AND_NOT_TMP_BI1 AND_NOT_TMP_BI1 SET_TMP BIT 5 1 MP_BIT 5 0 a 7 n no n oo ul Pwd Manage Step 1 LOA State 5 D_TMP_BIT 5 2 OR_NOT_TMP_BIT 12 12 SET_TMP_BIT 8 0 TIMER_TENTHS 6 7 8 Look for current over LOAD _REG 466 COMP_REG 644 0 LOAD_TMP_BIT 0 3 OR_TMP_BIT 0 2 AND_TMP_BIT 5 2 OR_TMP_BIT 5 5 AND_TMP_BIT 5 2 SET_TMP_BIT 5 5 Clear the history bit Lockout 1 Time value set current time period 5 1 Average Current over 10 greater than Output 1 State Step 1 State Step 1 State SFLC 7 NOT NOT Idle S Step 1 NOT Lockou NOT Output Output 1 S tate State t State 2 State tate n n Ds Step 1 State NOT Power up Done enable Step 1 timer process timer threshold Average Current Threshold Level greater than equal to Step 1 State Threshold Current Detected Step 1 State Threshold Current Detected SFLC 1639507 12 2006 281 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_REG 466 COMP_REG 644 0 LOAD_TMP_BIT 0 1 AND_TMP_BIT 5 5 R_TMP_BIT 8 1 ND_TMP_BIT 5 2 R_TMP_ BIT 5 3 ET TMP BIT 5 3 gt O no LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT 5 1 AND_NOT_TMP_BIT 5 3 AND_NOT_TMP_BIT 5 4 SET_TMP_BIT 5 2 Manage Lockout State LOAD_TMP_BIT 5
121. ET_TMP_BIT 4 9 Generate Run 2 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Run2 NOT PLC Network Run1 Power up Done NOT Stop 2 Save new history NOT previous history PLC active NOT Stop2 NOT PLC Comm Loss from scratch Include previous result save partial Run2 HMI mode Input history Save previous history HMI Run2 Save new history NOT previous history HMI active NOT Stop 2 NOT HMI Comm Loss from scratch Lockout Timer Include previous result save partial Run2 1639507 12 2006 255 Pre Defined Structured Text Programs Structured Text Program cont d S ET_TM OAD ET oA E M P_BIT E P_BIT n Be iw MP 0 BIT Be js Z H 3 P_BIT EE oO gt 0 Zz 8 Z O TMP P_BIT BIT P_BIT o B S T D 2 no ta o 3 LOAD_TMP_BIT 4 2 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT SET_TMP_BI1 LOAD_TMP_BIT 4 4 AND_TMP_BI1 D_TMP_BI1 BIT Z A n no R_TMP_ ET_TMP_BI1 AND_NOT_TMP_BIT AND_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP BIT 4 9 a 4 4 3 0 4 4 NOT_TMP_BIT Pe 3 2 OT_TMP_BI1 9 9 r 0 2 OT_TMP_BIT 4 14 BIT 4 12 T 0 2 9 0 0 9 Sed 0 1 4 4 9 9 LOAD_TMP_ BIT 12 6 r 12 0
122. Enables you to choose whether the accurate grid is visible True or false Note This grid must not be confused with the grid line which is accessed from the top level View menu bar Snap Enables you to choose whether the objects are snapped True or false with the grid When set to true if you move objects they will move along the grid step 150 1639507 12 2006 Function Block Diagram Language Graph Options The following table lists all the possible graph customization options Graph option Description Possible choices Allow Add Connection Enables you to choose whether connections can be True or false added to the workspace Allow Add Shape Enables you to choose whether blocks can be added to True or false the workspace Allow Delete Shape Enables you to choose whether blocks can be deleted True or false Allow Move Shape Enables you to choose whether blocks can be moved in True or false the workspace Locked Enables you to choose whether the FBD program can be True or false edited Display Grid You may wish to display the grid lines In order to do so select View gt Display Grid 1639507 12 2006 151 Function Block Diagram Language 152 1639507 12 2006 Connection to the LTM R Controller At a Glance Overview What s in this Chapter This chapter describes how to connect the HMI device running custom logic editor to the LTM
123. INT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments 60 1639507 12 2006 Structured Text Language AND_NOT_BIT AND_NOT_TMP_BIT The AND_NOT_BIT command e inverts the Boolean value 0 or 1 of a specified register bit then e makes a logical AND link between it and the accumulator content in logic memory If the bit accumulator equals 1 and the inverted linked register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 AND_NOT_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments The AND_NOT_TMP_BIT command e inverts the Boolean value 0 or 1 of a specified temporary register bit then e makes a logical AND link between it and the accumulator content in logic memory If the bit accumulator equals 1 and the inverted linked temporary register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result i
124. IT 3 AND_NOT_TMP_BI1 AND_NOT_TMP_BI1 OR_TMP_BIT 4 15 s P_BIT 4 9 ET TMP BIT 4 1 OR_TMP_BIT 4 15 SI L5 Run 1 Run 2 Direct Transfer Enable NOT PLC active save Swapping PLC active Run 1 NOT last speed Two Wire Swap save Two Wire Swap PLC active Run 2 last direction Two Wire Swap save Two Wire Swap PLC active Run 1 Run 2 Two Wire Swap save Two Wire Swap 312 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Speed Le LOAD_K_RI G G LOAD_TMP_BIT 4 1 ON_SET_TMP_REG 9 LOAD_REG 541 LOAD_TMP_BIT 4 1 OR_NOT_TMP_BIT 12 12 ON_SET_TMP_REG 9 LOAD_NOT_TMP_BIT 4 10 AND_NOT_TMP_BIT 4 11 OR_TMP_BIT OR_TMP_BIT OR_TMP_BIT OR_NOT_TMP_BIT 12 12 4 13 11 2 4 15 SET_TMP_BIT 11 TIMER_TENTHS 9 10 11 update Swapping flags 1 1 0 LOAD_TMP_BIT 11 0 AND_TMP_BI1 SET_TMP_BI1 Kili T 4 12 AJ SET_TMP_BIT r 4 15 Change timer Low to High Time value 1s Low Speed Timer Value Low to High High to Low Time value High Speed NOT Power up Done Timer Value High to Low NOT Low Speed NOT High Speed swapping already timing Two Wire Swap NOT Power up Done Enable Timer Process lockout timer Enabled timing Lockout Timer Active
125. IT 4 SET_TMP_BIT 0 LOAD_NOT_TMP_B OR_TMP_BIT 4 7 D_TMP BIT 4 TMP_BIT 0 0 TMP_BIT 0 Z nO oe ti E LOAD_NOT_TMP_B 0 94 noL SLL 12 12 95 402 IT 4 8 10 0 IT 4 9 11 0 IT 4 10 AND_NOT_TMP_BIT 4 11 AND_TMP_BIT 11 OR_TMP_BIT 0 0 OR_NOT_TMP_BIT SET_TMP BIT 11 TIMER_TENTHS 2 12 12 0 9 10 11 Low to High Time value 1s Low Speed Timer Value Low to High High to Low Time value High Speed NOT Power up Done Timer Value High to Low NOT Runt Stopl Low Speed save partial result in scratch NOT Run2 Stop2 High Speed include partial result save partial result in scratch NOT Low Speed NOT High Speed already timing include partial result NOT Power up Done Enable Timer Process Speed Change timer 1639507 12 2006 297 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 11 0 AND_TMP_BIT 11 2 SET_TMP_BIT 4 12 Manage Low Speed and LOAD_NOT_TMP_BIT 11 2 OR_TMP_BIT 53 0 AND_TMP_BIT 4 8 NOT_TMP_BIT 4 6 NOT_TMP_BIT 4 11 ET_TMP_BIT 4 10 ET_TMP_BIT 53 1 LOAD _NOT_TMP_BIT 11 2 OR_NOT_TMP_BIT 53 0 AND_TMP_BIT 4 9 OT_TMP_BIT 4 7 OT_TMP_BIT 4 10 ET TMP_BIT 4 11 ET_TMP BIT 53 2 js Z js Z LATCH 53 is
126. IT 4 4 LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback Latch HMI Keypad info LOAD_BIT 1020 12 Aux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Aux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 1639507 12 2006 233 Pre Defined Structured Text Programs Structured Text Program cont d Generate Global Stop in Temp Reg 4 5 LOAD_TMP BIT 3 1 ND_BIT 455 2 R_TMP_BIT 13 14 R_BIT 456 5 R_BIT 453 1 R_BIT 453 2 ET TMP_BIT 4 5 OAD_NOT_TMP_BIT 3 0 D_NOT_TMP BIT D_NOT_TMP BIT R_TMP_BIT 4 5 ET TMP_BIT 4 5 OAD_NOT_BIT 1200 0 ND_BIT 456 4 R_TMP_BIT 4 5 ET TMP_BIT 4 5 D TOAG OO Sek 3 2 no EEE gt no HMI Active NOT IMPR Fault status HMI Stop Key Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on Rapid Cycle include partial Global Stop Sa
127. Independent Operating Mode 166 3 Wire Independent Mode Programming Example 168 3 Wire Independent Operating Mode Temporary Registers Allocation 170 3 Wire Independent Operating Mode Program Sections 173 3 Wire Independent Operating Mode Allocation Tables 175 1639507 12 2006 165 Programming Approach LTM R Controller Programming Strategy for the 3 Wire Independent Operating Mode Overview Comments Initial Comments 3 Wire Independent Mode Structure 3 Wire Independent Mode Sections Purpose of the Programming Strategy General Rules The 3 wire independent operating mode program is made up of several parts Usually a program is divided as follows 1 Temporary registers allocation 2 Program in itself logic commands and arguments divided by sections and explained by comments The Comments are indicated by marked in the program The initial comments describe the temporary address locations see 3 Wire Independent Operating Mode Temporary Registers Allocation p 170 needed to perform specific functions of the program While there are several hundred logic commands and arguments there are essentially 9 sections see 3 Wire Independent Operating Mode Program Sections p 173 for the 3 wire independent operating mode program Each of the 9 sections includes a summary comment that labels each section of the program The general strategy for each section is des
128. K_REG 1 0 77 a ue 11 11 tt ws a a 11 a 11 11 a 11 egual FS Control Transfert in Process save old Transfert in Process Requested Mode is it Active Mode Not egual Transfert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not Bumpless Look for Edge Transfert in Process Mode Wait 1 Mode Change 1 Transfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process PLC requested PLC active not Transfert in Process HMI requested HMI active not Transfert in Process TS requested TS active PLC fallback mode HOLD 0 Last L01 command Last L02 command L01 PLC fallback STEP 1 LTM CONF ES Connected 32 1639507 12 2006 Structured Text Language Structured Text Editor User Interfaces overview There are two different ways to create a program with the structured text editor You can choose to use either the Text or the Grid view Text View The following illustration shows the structured text editor in Text view LTM CONF Default File Edit Link Settings Logic Functions Tools View Help get oS Telemecanique Tesys T Device Information Untitled if Untitied2 if Untitled3 if Settings 1 LOGIC_ID 400 2 WIRE TWO STEP MODE POES LOAD_BIT 683 8 ti TS HMI Statistics SET_TMP_BIT 0 1 debounce TS HMI in scratch B Monit
129. MI active NOT HMI Run 2 Run 2 NOT HMI Comm Loss from scratch Include partial Stop2 save partial Stop2 TS active NOT TS Run 2 Run 2 Include partial Stop2 save final Stop2 1639507 12 2006 209 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP BIT 12 1 AND_NOT_TMP BIT 12 11 SET_TMP_BIT 12 0 OAD_BIT 704 0 TMP BIT 12 12 ET TMP BIT 12 1 OT_TMP_BIT 12 0 MP BIT 3 0 P_BIT 4 8 ET_TMP_BIT 4 8 E Z S n Eg OU i 2 no zo Ss LOAD_TMP BIT 12 3 AND_NOT_TMP BIT 12 11 SET_TMP_BIT 12 0 AD TMP BIT 13 12 D_TMP BIT 12 12 TMP BIT 12 3 NOT_TMP_ BIT 12 0 P BIT 3 1 T TMP BIT 4 12 BIT 4 8 MP BIT 4 8 BS ry 2u Gu ed N UU UO Be O nO td o HW i858 ue LOAD_TMP_ BIT 12 5 AND_NOT_TMP BIT 12 11 SET_TMP_BIT 12 0 OAD_BIT 457 0 D_TMP BIT 12 12 TMP BIT 12 5 NOT_TMP_ BIT 12 0 P BIT 3 2 T TMP BIT 4 12 BIT 4 8 P BIT 4 8 E Z PA a 2u Gu ed N UU U Be Q no Hw HI is lt Generate Runl and Run2 Commands Generate Run 1 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Runt Power up Done Save new history NOT previous history PLC active Include previous result save partial Runl HMI mode Input
130. MP BI ESA 25i S 5 J w zo mv Z P_BIT MP_BIT MP BIN no aw H a 4 4 8 D_NOT_TMP_BIT 12 11 D_NOT_TMP_BIT 4 6 r 12 0 BIT 457 0 r 12 12 12 5 NOT_TMP_BIT 12 0 M PB 8 LOAD_TMP_BIT 4 1 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT SET_TMP_BI1 E A a 3 0 4 4 8 0 0 8 LOAD_TMP_BIT 4 3 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT SET_TMP_BI1 7 m A Zeck 0 1 4 4 8 8 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 TS mode Input history NOT Bumpless in Process NOT Stopl Save previous history UI1 Power up Done Save new history NOT previous history TS active Include previous result save partial Runl PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Mode Change 1 save final Run 1 238 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 2 BEOEE 4 n ti E 4 Be o o HA R_TMP_BIT O n za l D_NOT_TMP_BIT 12 11 D_NOT_TMP_BIT 4 7 _TMP_BIT 12 0 AD_BIT 704 1 MP_BIT 12 12 MP_BIT 12 2 OT_TMP_BIT 12 0 MP_BIT 3 0
131. MP_BIT 5 3 a sh LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT 5 1 AND_NOT_TMP_BIT 5 3 AND_NOT_TMP_BIT 5 4 SET_TMP_BIT 5 2 Manage Lockout State LOAD_TMP_BIT 5 3 OR_NOT_TMP_BIT 12 12 SET_TMP_BIT 11 0 TIMER_TENTHS 9 10 11 LOAD_TMP_BIT 11 2 SET_TMP_BIT 4 12 LOAD_TMP_BIT 11 1 AND_TMP_BIT 5 3 OR_TMP_BIT 5 4 n tj ET_TMP_BIT 5 4 LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT 5 1 AND_NOT_TMP_BIT 5 2 AND_NOT_TMP_BIT 5 4 SET TMP BIT 5 3 less than Threshold Current Detected timed out Step 1 S Lockou Lockou NOT Idle NOT Outpu NOT Lockout State NOT Outpu Step 15 Step 1 S NOT Power up Done enable Lockout timer process timing Lockout timed ou tate State State tate tate timer timer Lockout State Step 2 S Step 2 S NOT Idle NOT Output 1 State NOT Step 1 State NOT Output 2 State tate tate State Lockout State State t 1 State t 2 State 270 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Manage Output 2 State LOAD_NOT_TMP_BIT 5 0 AND_NOT_TMP_BIT 5 1 AND_NOT_TMP_BIT 5 2 AND_NOT_TMP_BIT 5 3 SET_TMP_BIT 5 4 Set Outputs to IMPR LOAD_TMP_BIT 5 1 OR_TMP_BIT 5 2 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 12 SET_BIT 1200 9 5 4 NO
132. ND_NOT_TMP_BI1 AND_NOT_TMP_BI1 AND_NOT_TMP_BI1 3 0 0 0 ET_TMP_BIT 4 8 ET_TMP_BIT 4 8 SET_TMP BIT 4 8 LOAD_TMP_BIT 12 5 SET_TMP_BIT 12 0 12 0 4 6 AND_NOT_TMP_BIT 4 12 4 6 4 13 12 7 TS mode Input history Save previous history UI1 Save new history NOT previous history TS active NOT Stop 1 Last Dir Forward Lockout Timer temp Lockout Timer Include previous result save partial Runl PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Stop 1 NOT Swapping NOT Mode Change 1 save final Run 1 254 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 0 LOAD_BIT 704 1 J Zl AND_NOT_BIT 704 0 AND_TMP_BIT 12 12 AND_NOT_TMP_BIT 4 SET_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 AND_TMP_BIT 3 0 AND_NOT_TMP_BIT 4 AND_NOT_TMP_BIT 0 OR_TMP_BIT 4 9 SET_TMP_BIT 4 9 LOAD_TMP_BIT 12 4 SET_TMP_BIT 12 0 LOAD_TMP_BIT 13 13 SET_TMP_BIT 12 4 AND_NOT_TMP_BIT 12 AND_TMP_BIT 3 1 AND_NOT_TMP_BIT 4 AND_NOT_TMP_BIT 0 AND_NOT_TMP_BIT 4 OR_TMP_BIT 4 9 S
133. NOT_TMP_BIT 1 2 Not equal SET_TMP_BIT 4 0 Transfer in Process Eh Manage Bump Bumpless LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 12 7 Mode Change 1 SET_TMP BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 1 HMI requested SET_TMP_BIT 3 1 HMI Active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active FA 302 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 COMP_K_REG LOAD_TMP_BI1 0 0 P02 AND_BIT 1200 12 SET_TMP BIT LOAD_TMP_BI1 4 1 r 0 2 AND_BIT 1200 13 SET_TMP BIT 4 2 PLC fallback mode HOLD 0 equal last LO1 command LO1 PLC fallback equal last LO2 command LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed ON OFF 4
134. NV_REG The XOR_NV_REG command makes a logical XOR link between the non volatile register value and the accumulator content in logic memory The result is saved in the 16 bit accumulator The XOR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked non volatile register and yields these results When 2 bits are compared if one bit equals 1 and the other equals 0 the result of the XOR process is 1 in all other cases the result of the XOR process is 0 When more than 2 bits are compared if there is an odd number of 1 states the result of the XOR process is 1 if there is an even number of 1 states the result of the XOR process is 0 Arguments Representation 1 XOR_NV_REG NVReg Input arguments Argument Type Description NVReg UINT The non volatile space register number an integer value ranging from 0 to 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 Output arguments 82 1639507 12 2006 Structured Text Language ON_SET_REG ON_SET_TMP_REG The ON_SET_REG command copies the value of the 16 bit accumulator to a register on detecting the rising edge of an input signal that sets the bit accumulator value to 1 when the OnHistory bit value is 0 The OnHistory bit holds the value of the bit accumulator 0 or 1 from the previous scan Arguments Representation 2 ON_SET_REG RegAddr TmpReg Input arguments
135. Non volatile registers available 26 1639507 12 2006 Introduction to Custom Logic Editor Register 1200 Register 1201 Register 1202 Register 1203 Register 1204 Register 1205 Register 1200 is the custom logic interface register It enables you to configure I O assignment using the custom logic editor For example you can change the reset input from the default I5 to 19 The following table describes each bit in this register Bit number Description 0 Motor Run Command Default Terminals 11 and 12 1 Motor Stop Command Default Terminal 14 2 Reset Command Default Terminal 15 3 Step 2 Active 4 Transition Timer Active 5 Phase Direction Reversed 6 Remote Control Default Terminal 16 7 FLA Select O FLA1 1 FLA2 8 External Fault O No Fault 1 Fault 9 Aux 1 LED PowerSuite and HMI 10 Aux 2 LED PowerSuite and HMI 11 Stop LED PowerSuite and HMI 12 Logic Output 1 LTM R 13 Logic Output 2 LTM R 14 Logic Output 3 LTM R 15 Logic Output 4 LTM R Register 1201 indicates the custom logic capability version The version number identifies a specific group logic commands supported by the LTM R controller Register 1202 defines the logic memory space available that is the number of non volatile LTM R controller logic memory words 16 bits available to save logic commands Register 1203
136. OAD_NOT_TMP BIT 1 1 AND_NOT_TMP BIT 1 2 AND_TMP_BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 LEERE kkk kkk kkk kk kk LOAD_NOT_TMP BIT 1 1 AND_TMP_BIT 1 2 AND_NOT_TMP BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 RRR RRK k kkk kkk kk g kk Lh LOAD_NOT_TMP BIT 1 1 AND_TMP_BIT 1 2 AND_TMP_BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 LEFFE kk kkk kkk kkkh kk LOAD_TMP BIT 1 1 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 LEERE R kk kkk k kk k k D k k ip LOAD_TMP BIT 1 1 AND_NOT_TMP_ BIT 1 2 AND_TMP_BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 aw Ce vs z aw CY 1 2 T3 include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result Inputs 1 2 3 are OFF ON OFF include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result Inputs 1 2 3 are OFF ON ON include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result Inputs 1 2 3 are ON OFF OFF include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result Inputs 1 2 3 are ON OFF ON include this SECTION if output is to be ON REMOVE if output to b
137. OFF 4 no OFF ON 5 no action action action action needed needed needed needed 264 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Latch HMI Keypad info LOAD_BIT 1020 12 SET_TMP_BI1 T 13 12 LOAD_BIT 1020 13 SET_TMP_BI1 T 13 13 LOAD_BIT 1020 14 SET_TMP_BI1 T 13 14 Aux 1 Aux 2 Stop Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 3 1 AND_BIT 455 2 OR_TMP_BIT 13 14 OR_BIT 456 5 OR_BIT 453 1 OR_BIT 453 2 SET_TMP_BIT 4 5 LOAD_NOT_TMP_BIT 3 0 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT SET_TMP_BI1 3al 3 62 4 5 T 4 5 LOAD_NOT_BIT 1200 0 AND_NOT_BI1 T 1200 4 AND_BIT 456 4 OR_TMP_BIT 4 5 SET_TMP_BI1 r 4 5 HMI Active IMPR Fault status HMI Stop Key Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on NOT Transition Timing Rapid Cycle include partial Global Stop Save final Global Stop Latch comm loss values in scratch 0 LOAD_BIT 456 8 SET_TMP_BI1 T 0 0 LOAD_BIT 456 7 SET_TMP_BI1 r 0 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 1639507 12 200
138. OT_TMP_BI1 AND_TMP_BIT 2 1 TMP BIT 3 1 rT A rT A LOAD_NOT_TMP_BI1 AND_TMP_BIT SET_TMP BIT wh 2 2 rT A 0 not PI PI LC LC not HMI HMI not TS requested TS active Transfer in Process requested active Transfer in Process requested Active Transfer in Process 1639507 12 2006 287 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 PLC fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 1 LO1 PLC fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 2 LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SET_TMP_BIT 4 1 LO1 PLC fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 2 logical or with previous value SET_TMP_BIT 4 2 LO2 PLC fallback 288 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values
139. P_BIT 4 12 Wait for power up timer OR_TMP_BIT 12 12 Latch ON until next power up SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 1639507 12 2006 299 Pre Defined Structured Text Programs Structured Text Program for 3 Wire 2 Speed Mode Overview The structured text program for the 3 wire 2 speed mode is defined below Structured Text Program LOGIC_ID 11 Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI 2 TS terminal strip ge Lie 3 WIRE TWO SPEED MODE Temp 3 as Active Control Mode O PLC 1 HMI 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process ie 2 3 4 01 PLC fallback value 102 PLC fallback value L01 HMI fallback value L02 HMI fallback value 5 Global Stop 6 Stopl1 7 Stop2 8 9 Run1 Run2 10 Speed 1 11 Speed 2 12 Lockout Timer Active 13 Swapping 14 Last Speed 15 Two Wire Swap Temp 5 as state bits group 2 Temp 9 10 11 as Lockout Timer 300 1639507 12 2006 Pre Defined
140. S terminal strip Temp 4 as state bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 N A L02 PLC fallback value 3 L01 HMI fallback value fof 4 N A L02 HMI fallback value 5 Global Stop 6 Stop1 7 N A Stop2 8 Run1 9 N A Run2 10 Step 1 11 Step 2 12 Step Timer Active Temp 5 as state bits group 2 O Idle Wait for Run 1 as 1 Output 1 Waiting for Current gt 10 2 Step 1 Waiting for Step Timer or cur lt 3 Lockout Waiting for transition timer 541 4 Output 2 Waiting for stop command 5 Threshold Current Detected Temp 6 7 8 as Step 1 timer 1639507 12 2006 261 Pre Defined Structured Text Programs Structured Text Program cont d Temp 12 as INPUT Hist 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 las 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 ff 10 11 Bumpless in 12 Power up Don Temp 50 as general s Temp 50 as ONSET sta Temp 51 as ONSET sta Temp 52 as ONSET sta Temp 53 Latch Temp 54 as ONSET sta Save Requested Control LOAD_BIT 683 8 SET_TMP_BIT 0 1 LOAD_BIT 457 5 SET_TMP_BIT 0 0 SET_TMP_BIT 2 0 LOAD_NOT_TMP_BIT 0 0 AND_TMP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP_BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 Temp 9 10 11 as Lockout ti
141. SET_TMP BIT LOAD _TMP_BIT 0 1 AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT SET_TMP BIT LOAD_TMP_BIT 3 0 AND_NOT_BIT 704 0 4 4 4 6 3 0 BIT 4 1 lt 6 4 6 SaL BIT 4 3 6 4 6 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 0 0 OR_TMP_BIT SET_TMP_BIT 4 6 4 6 Generate Stopl Global Stop save partial Stopl PLC Comm PLC active Loss from scratch NOT LO1 PLC fallback value Include partial Stopl save par HMI Comm HMI active NOT LO1 tial Stop1 Loss from scratch HMI fallback value Include partial Stopl save par tial Stop1 PLC active NOT PLC Run 1 NOT PLC Comm Loss from scratch Run Include partial Stopl save final Stop1 1639507 12 2006 197 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop2 LOAD_TMP_BIT 4 5 Global Stop SET_TMP_ BIT 4 7 save partial Stop7 LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 2 NOT LO2 PLC fallback value OR_TMP_BIT 4 7 Include partial Stop2 SET_TMP BIT 4 7 save partial Stop2 LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 4 NOT LO1 HMI fallback value OR_TMP_BIT 4 7 Include partial Stop2 SET_TMP_ BIT 4 7 save partial Stop2 LOAD_TMP_BI
142. SET_TMP_BIT 13 14 Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 3 1 HMI Active AND_BIT 455 2 IMPR Fault status OR_TMP_BIT 13 14 HMI Stop Key OR_BIT 456 5 Load Shed SET_TMP_BIT 4 5 Save partial Global Stop LOAD_NOT_TMP BIT 3 0 NOT PLC active AND_NOT_TMP_BIT 3 1 NOT HMI active AND_NOT_TMP_BIT 3 2 NOT TS active OR_TMP_BIT 4 5 include partial Global Stop SET_TMP_BIT 4 5 Save final Global Stop Latch comm loss values in scratch 0 LOAD_BIT 456 8 PLC Comm Loss SET_TMP_BIT 0 0 save in scratch bit 0 LOAD_BIT 456 7 HMI Comm Loss SET_TMP_BIT 0 1 save in scratch bit 1 1639507 12 2006 185 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop1 and Stop2 Commands Generate Stopl LOAD_TMP_BIT 4 5 Global Stop SET_TMP BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 1 NOT LO1 PLC fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_BIT 4 3 NOT LO1 HMI fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 0 PLC active AND_NOT_BIT 704 0 NOT PLC Runl AND_TMP_BIT 4 8 Run 1
143. T 12 5 SET_TMP_BIT 12 0 LOAD BIT 457 0 SET_TMP_BIT 12 5 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 2 AND_NOT_TMP_BIT AND_NOT_TMP_BIT OR_TMP_BIT 4 8 SET_TMP BIT 4 8 4 6 4 1 2 LOAD_TMP_BIT 4 1 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 4 8 SET_TMP_BIT 4 8 3 0 0 0 LOAD_TMP_BIT 4 3 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 4 8 SET_TMP_BIT 4 8 3L 0 1 AND_NOT_TMP_BIT 4 6 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 TS mode Input history Save previous history LI1 Save new history NOT previous history TS active NOT Stop 1 Lockout Timer Include previous result save partial Run1 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Stop 1 NOT Swapping NOT Mode Change 1 save final Run 1 1639507 12 2006 309 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP BIT 12 2 AND_NOT_TMP BIT 12 11 ET_TMP_BIT 12 0 n BEES T I G D Q D t 2 Q 2u P_BIT 3 0 NOT_TMP_BIT 4 7 T_TMP_BIT 0 0 P_BIT 4 9 MP_BIT 4 9 22E nO td W HI 4H Hs 5 O D 0 TMP_BIT 12 4 TMP BIT 12 0 TMP_BIT 13 1
144. T 3 0 PLC active AND_NOT_BIT 704 1 NOT PLC Run2 AND_TMP_BIT 4 9 Run 2 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 7 Include partial Stop2 SET_TMP_BIT 4 7 save final Stop2 Generate Runl and Run2 Commands Generate Run 1 PLC mode LOAD_TMP_BIT 12 1 Input history AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP BIT 12 0 Save previous history LOAD_BIT 704 0 PLC Network Runl AND_TMP_BIT 12 12 Power up Done AND_NOT_TMP_BIT 4 6 NOT _ Stop1 SET_TMP_BIT 12 1 Save new history AND_NOT_TMP_BIT 12 0 NOT previous history AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 6 NOT Stop 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 8 Include previous result SET_TMP_BIT 4 8 save partial Run1 198 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 1 AND_TMP_BI1 AND_TMP_BI1 OR_TMP_BIT B 330 rT 0 0 4 8 SET_TMP_BI1 AND_NOT_TMP_BIT AND_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP BIT 4 8 T 4 8 4 6 4 13 12 7 LOAD_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 11 SET_TMP_BI1 ma J 4l MP_BIT zz ie Haz MP BIT vn t H S Z rT 12 0 OAD_BIT 704 1 Let eo OT_TMP_BIT 4 7 ed gee OT_TMP_BIT 12 0 D TMP BIT BEEE OR_TMP_BIT BP 330 D_NOT_TMP_ BIT 4 7 D_NOT_TMP_ BIT 0 0 4 9 SET_TMP_BIT 4 9 LOAD_TMP_BIT 4 2
145. T 4 ET_TMP_BIT 4 ET_TMP_BIT 4 SET_TMP BIT 4 4 0 HMI fallback mode HOLD 0 equal last HMI runl command LO1 HMI fallback equal last HMI run2 command LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed ON 3 fallback to ON equal 1 logical or with previous LO1 HMI fallback fallback to ON equal 1 logical or with previous LO2 HMI fallback ON OFF 4 fallback to ON equal 1 logical or with previous LO1 HMI fallback OFF ON 5 fallback to ON equal 1 logical or with previous LO2 HMI fallback value value value value 206 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Latch HMI Keypad info LOAD_BIT 1020 12 Bux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Bux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 Generate Global Stop in Temp Reg 4 5 LOAD_TMP_BIT 3 1 HMI Active AND_BIT 455 2 IMPR Fault status OR_TMP_BIT 13 14 HMI Stop Key OR_BIT 456 5 Load Shed SET_TMP_BIT 4 5 Save partial Global Stop LOAD_NOT_TMP BIT 3 0 NOT PLC active AND_NOT_TMP_BIT 3 1 NOT HMI active AND_NOT_TMP_BIT 3 2 NOT TS active OR_TMP_BIT 4 5 include partial Global Stop SET_TMP_BIT 4 5 Save final Global Stop
146. T History 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 1639507 12 2006 215 Pre Defined Structured Text Programs Structured Text Program cont d 9 Mode Change 2 10 Ta 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONSET status Low to High timer Temp 52 as ONSET status High to Low timer Temp 53 Latch Temp 54 as ONSET status 704 Runl Run2 Save Requested Control in Temp 2 FA LOAD_BIT 683 8 TS HMI SET_TMP_BIT 0 1 Debounce TS HMI in scratch LOAD_BIT 457 5 LI6 SET_TMP_BIT 0 0 Debounce LI6 in scratch SET_TMP_BIT 2 0 PLC Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control Look for control transfer Fd LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD_NOT_TMP_BIT 1 2 Not equal SET_TMP_ BIT 4 0 Transfer in Process 216 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Bump Bumpless
147. T Idle State NOT Output 1 State NOT Step 1 State NOT Lockout State Output 2 State Process Output 1 Output 1 State Step 1 State NOT Stop 1 Output 1 Aux 1 LED Process Output 2 LOAD_TMP_BIT 5 4 Step 2 S NOT Stop tate 1 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 13 SET_BIT 1200 10 SET_BIT 1200 3 LOAD_TMP_BIT 5 OR_TMP_BIT 5 2 OR_TMP_BIT 5 4 SET_BIT 1200 0 s s T_NOT_BIT 1200 1 T_NOT_BIT 1200 11 LOAD_TMP_BIT 4 12 SET_BIT 1200 4 Output 2 Aux 2 LED In Step 2 Process Motor Run Stop Output 1 State Step 1 State Step 2 State Motor Run Motor Stop Stop LED Reversing Timer Transition Timer 1639507 12 2006 271 Pre Defined Structured Text Programs Structured Text Program cont d Process other outputs LOAD_BIT 455 3 IMPR Alarm status SET_BIT 1200 14 Output 3 Alarm LOAD_BIT 455 2 IMPR Fault status SET_NOT_BIT 1200 15 Outpur 4 Fault LOAD_BIT 457 4 Reset Input LI5 SET_BIT 1200 2 Logic Reset LOAD_TMP_BIT 3 0 PLC active SET_BIT 1200 6 Logic Local Remote Manage Power UP Done LOAD_NOT_TMP_BIT 4 12 Wait for power up timer OR_TMP_BIT 12 12 Latch ON until next power up SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC
148. T command makes a logical OR link between a non volatile register bit value and the accumulator content in logic memory If the value of either the bit accumulator or the non volatile register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0 the result of the OR process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 OR_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments 1639507 12 2006 63 Structured Text Language OR_NOT_BIT The OR_NOT_BIT command e inverts the Boolean value 0 or 1 of a specified register bit then e makes a logical OR link between it and the accumulator content in logic memory If the value of either the bit accumulator or the inverted register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0 the result of the OR process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 OR_NOT_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register ad
149. T_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 12 7 Mode Change 1 SET_TMP_ BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_ TMP BIT 3 0 PLC active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 1 HMI requested SET_TMP_BIT 3 1 HMI Active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active 1639507 12 2006 275 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values fa LOAD_REG 682 PLC fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_BIT 1200 12 last LO1 command OR_BIT 1200 13 last LO2 command AND_TMP_BIT 0 2 equal SET_TMP_BIT 4 1 LO1 PLC fallback COMP_K_REG 1 0 STEP 1 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SETUTMP BIT 4 1 LO1 PLC fallback OFF 2 no action needed ON 3 no action needed ON OFF 4 no action needed OFF ON 5 no action needed Generate HMI Fallback Values OAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD
150. Z l 5 000 because X h 65 536 X I 3 65 536 3392 and 200 000 Y 5 000 0 65 536 5 000 124 1639507 12 2006 Function Block Diagram Language Inputs Blocks Overview Access Constant Bit Block Constant Word Block The FBD editor uses various inputs blocks Constant Bit Constant Word Register Bit In Register Word In Register NV Bit In Register NV Word In Register Temp Bit In Register Temp Word In To access Inputs blocks click on the Inputs bar in the Toolbox This is then displayed in the Toolbox 1 fie 1 1 fic fie 1 Te IN LTMR NV NV LTMR Tmp Tmp The 1 block is used to set other blocks inputs to O or 1 The following table describes the Constant Bit block characteristics FBD symbol Inputs outputs Description Inputs a Constant bit value 0 or 1 ON 1 and OFF 0 tant Outputs Constant value 0 or 1 ON 1 and OFF 0 a Out Se The L N block is used to set other blocks inputs values The following table describes the Constant Word block characteristics FBD symbol Inputs outputs Description Inputs a Constant register value from 0 to 65 535 int Outputs Constant register value from 0 to 65 535 a Out 1639507 12 2006 125 Function Block Diagram Language Register Bit In Block Register Word In Block Register NV Bit In Block 1 LTMR The block en
151. _BIT 9 9 LOAD_TMP_BIT 4 4 AND_TMP_BIT AND_TMP_BIT R_TMP_BIT 4 ET_TMP_BIT O S Si 0 1 9 4 9 AND_NOT_TMP_BIT 4 7 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 9 SET_TMP_BIT 4 9 Manage Direct PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run2 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run2 3wire latch NOT Stop 2 NOT Swapping NOT Mode Change 2 save final Run 2 Transfer Mechanism force opposite speed on swap LOAD_TMP_BIT 4 14 AND_TMP_BI OR_TMP_BIT 4 4 SET_TMP_BIT 9 T 4 13 9 last speed Swapping Run 2 Run 2 force opposite speed on swap LOAD_NOT_1 AND_TMP_BI1 R_TMP BIT 4 O S ET_TMP_BIT 8 4 MP BIT 4 14 a FOLE 8 NOT last speed Swapping Run 1 Run 1 1639507 12 2006 311 Pre Defined Structured Text Programs Structured Text Program cont d look for both speeds ON LOAD_TMP_BIT 4 8 AND_TMP_BIT 4 9 gt ND_BIT 683 9 AND_NOT_TMP_BIT 3 0 ed D T no mw is lt 0 SET_TMP_BIT 4 13 LOAD _TMP_BIT 3 0 P BIT 4 8 D_NOT_TMP BIT 4 14 BIT 4 15 P BIT 4 15 LOAD_TMP_BIT 3 0 DT D_TMP_BIT 4 1 ed ET_TMP_BIT 4 1 LOAD_TMP_B
152. _BIT LOAD_NOT_TMP_BIT AND_TMP_BIT SET_TMP_BIT LOAD_NOT_TMP_BIT AND_NOT_TMP_BIT SET_TMP_BIT LOAD_TMP_BIT SET_TMP_BIT LOAD_TMP_REG COMP_TMP_REG LOAD_NOT_TMP_BIT SET_TMP_BIT LOAD_TMP_BIT AND_NOT_TMP_BIT AND_BIT SET_TMP_BIT LOAD_TMP_BIT AND_NOT_BIT AND_NOT_TMP_BIT SET_TMP_BIT OR_TMP_BIT SET_TMP_BIT LOAD_TMP_BIT OR_TMP_BIT SET_TMP_BIT LOAD_NOT_TMP_BIT AND_TMP_BIT SET_TMP_BIT D fo o SCSONFOSBA 2 0000 0 a RRAONSORNDONDONOZO N FN LTM CONF Connected Default Settings Switching from Text View to Grid View When you choose to open a logic file or to create a new one the logic file will always open in Text view There are two ways to change between Text view and Grid view e Inthe upper menu bar click on View and choose Text view or Grid view or e right click on the file name and choose a view 34 1639507 12 2006 Structured Text Language Editing several programs You can create or modify several custom logic programs at the same time Just click on the file name to switch between them For instance in the Text view above click either untitled1 lf untitled2 If or untitled3 If depending on the program you wish to edit 1639507 12 2006 35 Structured Text Language Text View Introduction A program written in list language consists of a series of instructions executed sequentially by the controller Each list instruction is represented
153. _BIT 4 6 Include partial Stopl SET_TMP_ BIT 4 6 save partial Stopl 208 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 3 2 AND_NOT_BIT 457 0 AND_TMP_BIT 4 8 OR_TMP_BIT 4 SET_TMP_BIT 6 4 6 LOAD_TMP_BIT 4 5 SET_TMP_BIT 4 7 LOAD_TMP_BIT 0 0 AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT 4 SET_TMP_BIT Six Gi 4 0 7 BIT 4 2 LOAD_TMP_BIT 0 1 AND_TMP_BIT AND_NOT_TMP_ OR_TMP_BIT 4 SET_TMP_BIT St 7 4 1 7 BIT 4 4 LOAD_TMP_BIT 3 0 AND_NOT_BIT 704 1 AND_TMP_BIT 4 9 AND_NOT_TMP_BIT 0 0 OR_TMP_BIT 4 SET_TMP_BIT 7 4 7 LOAD_TMP_BIT 3 1 AND_NOT_TMP_BIT AND_TMP_BIT 4 9 AND_NOT_TMP_BIT OR_TMP_BIT 4 7 SET_TMP_BIT 4 7 LOAD_TMP_BIT 3 AND_NOT_BIT 457 AND_TMP_BIT 4 9 OR_TMP_BIT 4 7 SET_TMP_BIT 4 7 Al EP L33 E02 2 1 TS active NOT TS Run 1 Run 1 Include partial Stopl save final Stopl Generate Stop2 Global Stop save partial Stop7 PLC Comm Loss from scratch PLC active NOT LO2 PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop2 save partial Stop2 PLC active NOT PLC Run2 Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save partial Stop2 H
154. a HMI Fallback NA 3wire latch NOT Stop 2 NOT Swapping NOT Mode Change 2 save final Run 2 Process Output 1 Run1 NOT Stop 1 Output 1 Aux 1 LED Process Output 2 Run2 NOT Stop 2 Output 2 Bux 2 LED Process other outputs IMPR Alarm status Output 3 Alarm IMPR Fault status Output 4 Fault Reset Input LI5 Logic Reset PLC active Logic Local Remote Stop 1 Stop 2 Stop L eal iw 200 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Manage Power UP Done LOAD_NOT_TMP_BIT 4 5 OR_TMP_BIT 4 0 SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 1639507 12 2006 201 Pre Defined Structured Text Programs Structured Text Program for 2 Wire Independent Mode Overview The structured text program for the 2 wire independent mode is defined below Structured Text Program LOGIC_ID 4 2 WIRE INDEPENDENT MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI jah 2 TS terminal strip Temp 3 as Active Control Mode 0 PL
155. a Ei 3 WE za Ei J R R PPAR DWND fon NOOE Manage Power UP Done LOAD_NOT_TMP_BIT 4 12 OR_TMP_BIT 12 12 SET_TMP_BIT 12 12 Process Output 2 Reverse Output 2 Aux 2 LED Phase Reverse Forward Reverse Motor Run Motor Stop Reversing Timer Transition Timer Process other outputs IMPR Alarm status Output 3 Alarm IMPR Fault status Output 4 Fault Reset Input LI5 Logic Reset PLC active Logic Local Remote Stop 1 Stop 2 Reversing Timer Active Stop LED Wait for power up timer Latch ON until next power up Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 LOAD_K_REG 65532 AND_REG 704 ON_SET_REG 704 54 HN 4 Control Source Transfer NOT Bumpless OXFFFC mask off Runl and Run2 Run bits on Bump Control Change 260 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 2 Wire 2 Step Mode Overview The structured text program for the 2 wire 2 step mode is defined below Structured Text Program LOGIC_ID 8 2 WIRE TWO STEP MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC Vea 1 HMIpartial 2 T
156. ables the reading and use of a register bit value from the LTM R controller R W addresses 0 to 1399 The following table describes the Register Bit In block characteristics FBD symbol Inputs outputs Description Inputs a Any LTM R controller register from 0 to 1399 that can be accessed via serial communication ports b Bit position from 0 to 15 Outputs Value 0 or 1 ON 1 and OFF 0 Sie LTMR The block enables the reading and use of a register value from the LTM R controller R W addresses 0 to 1399 The following table describes the Register Word In block characteristics FBD symbol Inputs outputs Description Inputs a Any LTM R controller register from 0 to 1399 that can be accessed via serial communication ports Outputs Value from 0 to 65 535 1 The LNV block enables the reading and use of a non volatile register bit value The following table describes the Register NV Bit In block characteristics FBD symbol Inputs outputs Description Inputs a Any non volatile register from 0 to 63 b Bit position from 0 to 15 Outputs Value 0 or 1 ON 1 and OFF 0 Non Volatile 126 1639507 12 2006 Function Block Diagram Language Register NV Word In Block Register Temp Bit In Block Register Temp Word In Block Si The NV block enables the reading and use of
157. ams Structured Text Program cont d Generate Stop1 and Stop2 Commands Generate Stopl LOAD_TMP_BIT 4 5 Global Stop OR_NOT_TMP_BIT 12 12 NOT Powerup Done OR_BIT 453 1 Diag Fault 1 OR_BIT 453 2 Diag Fault 2 SET_TMP_BIT 4 6 save partial Stopl LOAD_NOT_BIT 1200 12 NOT alread on AND_BIT 456 4 Rapid Cycle OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 1 NOT LO1 PLC fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_ BIT 4 3 NOT LO1 HMI fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 0 PLC active AND_NOT_BIT 704 0 NOT PLC Runt AND_TMP_BIT 4 8 Run 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save final Stopl 1639507 12 2006 221 Pre Defined Structured Text Programs Structured Text Program cont d OR_NOT_ E 2E is s 24 O 8 ae BIT Huno o m gt bi ge 0 3 lw BIT P_BI no GSE js Ss 24 Q Ba H 3 Do ND_NOT_BI1 D_TMP_BI 2E MP_BIT D TMP_BIT T_TMP LOAD_TMP_BIT 4 5 TMP_BIT 12 12 SET_TMP_BIT O
158. ansfer LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD _NOT_TMP_BIT 1 2 Not equal SET_TMP_BIT 4 0 Transfer in Process 1639507 12 2006 203 Pre Defined Structured Text Programs Structured Text Program cont d Manage Bump Bumpless LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP BIT 12 7 Mode Change 1 SET_TMP_BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 1 HMI requested SET TMP BIT 3 1 HMI Active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active 204 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 COMP_K_REG 0 LOAD_TMP_BIT 0 2 0 AND_BIT 1200 12 SET_TMP BIT 4 1 LOAD_TMP_BIT 0 2 AN
159. aph options 149 Options 148 X XOR_K 79 XOR_NV_REG 82 XOR_REG 80 XOR_TMP_REG 81 1639507 12 2006 325 You can download this technical publication and other technical information from our website at http www telemecanique com Visit http www schneider electric com for your nearest Schneider Electric affiliate 2006 Schneider Electric All Rights Reserved 12 2006
160. ary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments 58 1639507 12 2006 Structured Text Language LOAD_NOT_NV_BIT The LOAD_NOT_NV_BIT command e inverts the Boolean value 0 or 1 of a selected non volatile register bit then e loads it into the 1 bit Boolean accumulator Arguments Representation 2 LOAD_NOT_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments AND_BIT The AND_BIT command makes a logical AND link between a register bit value and the accumulator content in logic memory If the bit accumulator equals 1 and the linked register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 AND_BIT RegAddr BitNo Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 BitNo UINT The bi
161. bit Boolean accumulator XOR_K Constant value Makes a logical exclusive OR link between 0 to 65 535 the constant value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator XOR_REG Register address Makes a logical exclusive OR link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator XOR_TMP_REG Temporary Makes a logical exclusive OR link between register address the temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator Argument not applicable to logic command 48 1639507 12 2006 Structured Text Language Command Argument 1 Argument 2 Argument 3 Description XOR_NV_REG Non volatile Makes a logical exclusive OR link between register address the non volatile register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator ON_SET_REG Register address Temporary When the 1 bit Boolean accumulator transitions register from 0 to 1 the 16 bit accumulator is stored into a address register Argument 1 Status bit 3 Argument 2 is used to remember the previous state of the 1 bit accumulator ON_SET_TMP_RE Temporary Temporary When the 1 bit Boolean accumulator transitions G register address register from 0 to 1 the 16 bit accumulator is stored into address a temporary r
162. bounced 45 Function Blocks SET_TMP_BIT 2 2 TS Control LOAD_TMP_BIT 4 0 Transfert in Process SET_TMP_BIT 0 0 save old Transfert in Process LOAD_TMP_REG 2 Requested Mode it Active Mode LOAD_NOT_TMP_BIT 1 2 gt gual 3 c in Process LOAD_TMP_BIT 4 0 Transfert in Process AND_NOT TMP BIT 12 11 NOT Bumpless in Process AND_BIT 683 10 Bumpless SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD TMP BIT 4 0 Transfert in Process AND_NOT_BIT 683 10 Not Bumpless AND_NOT TMP BIT 0 0 Look for Edge SET_TMP BIT 4 0 Transfert in Process a a wait 1 SET_TMP_BIT yge 1 _ st rt in Process OR_TMP_BIT 12 10 Mode Wait 2 SET_TMP BIT 12 9 Mode Change 2 LOAD_NOT_TMP BIT 4 0 not Transfert in Process AND_TMP BIT 2 0 PLC requested SET_TMP BIT 3 0 PLC active LOAD_NOT_TMP BIT 4 0 not Transfert in Process AND_TMP BIT 2 1 HMI requested SET_TMP_BIT 3 1 HMI active LOAD_NOT TMP BIT 4 0 not Transfert in Process AND_TMP BIT 2 2 TS requested Output 03 08 2006 14 32 01 03 08 2006 14 32 01 Please Wait 03 08 2006 14 32 01 03 08 2006 14 32 01 03 08 2006 14 32 01 Build Failed 2 Errors 03 08 2006 14 32 01 See Error windows for the list of errors Output O LTM CONF Connected 108 1639507 12 2006 Structured Text Language Output Window The Output window shows the logs associated with the compilation of the structured Elements text language program
163. c Editor At a Glance Overview What s in this Chapter This chapter provides a description of the custom logic editor This chapter contains the following topics Topic Page Introduction to the LTM R Controller 12 Operating Modes 15 Presentation of the Custom Logic Editor 16 Using the Custom Logic Editor 21 Characteristics of the Custom Logic Program 24 Definition of the Custom Logic Variables 25 Definition of the LTM R Variables 26 1639507 12 2006 11 Introduction to Custom Logic Editor Introduction to the LTM R Controller Overview TeSys T Motor Management System The TeSys T Motor Management System offers protection control and monitoring capabilities for single phase and 3 phase AC induction motors The system is flexible and modular and can be configured to meet the needs of applications in industry The system is designed to meet the needs for integrated protections systems with open communications and global architecture More accurate sensors and solid state full motor protection ensures better utilization of the motor Complete monitoring functions enable analysis of motor operating conditions and faster reaction to prevent system downtime The system offers diagnostic and statistics functions and configurable warnings and faults allowing better prediction of component maintenance and provides data to continuously improve the entire syst
164. ch as timers and counters Perform arithmetic logical comparisons and numerical operations e Read or write to the LTM R controller s internal registers or to individual bits in those registers Note When you type an argument it is automatically recognized and displayed in the color assigned to the arguments In the Text view of the structured text editor it is possible to add comments to the program At the end of each line after the arguments typing indicates to the program that the text that will be added is not part of the program but is a comment Note When you type the custom logic editor automatically recognizes the text after it as comments and displays it in green You can either leave blanks between arguments or use commas or dots Keyboard commands and shortcuts are the same as those for Windows operating systems press Del or Delete to delete a character or line press Enter to go to the next line etc To save the program you edited or created click Logic Functions in the top level menu bar and choose Save Logic File or Save Logic File As 1639507 12 2006 39 Structured Text Language Grid View Introduction The structured text editor has a Grid View which like the text view allows you to edit or create a program Grid view allows you to create each instruction by selecting in a drop down menu fashion from a list of available commands or typing int
165. ch register to insure that the state of the inputs are latched and do not change during the period in which the LTM R controller microprocessor executes the sequential logic Note Address locations used as scratch address locations may be used in one section of the program for one purpose and then used in later sections of the program for a second purpose 1639507 12 2006 167 Programming Approach 3 Wire Independent Mode Programming Example Overview The purpose of this example is to familiarize you by using the wiring diagrams and description of the pre defined operating modes in the LTM R user s manuals with the relationship between the LTM R controller physical and logical inputs and outputs used to control a Direct across the line FVNR motor starter You will find that use of the recommended power and control wiring diagrams is essential to implementing the logic contained in the predefined operating mode Pcode What we want to do in this example is to make the LTM R Terminal Strip input 3 generate an external fault condition External fault bit will then activate fault bit 455 2 disabling LO4 on the next scan Wiring The control circuit requires LO4 in series with LI4 to cause a STOP command which Requirements disables the firmware latch on LO1 which is wired in series with the contactor coil Program Scan The following table describes the actions performed by the LTM R contro
166. ck mode COMP_K_REG 0 0 HOLD 0 LOAD_BIT 1200 12 Last L01 command OR_BIT 1200 13 Last L02 command AND_TMP_BIT 0 2 egual SET_TMP_BIT 4 1 L01 PLC fallback COMP_K_REG 1 0 STEP 1 LTM CONF 4 Connected 1639507 12 2006 33 Structured Text Language Grid View LTM CONF Default File Edit Link Settings The following illustration shows the structured text editor in Grid view Logic Functions Tools View Help Baers S er RE Tesys T i Device Information gt Settings 413 Statistics ae Monitoring ae Parameters bea Custom Logic Function Blocks Telemecanique Untitled if Mnemonics Argument 01 Argument 02 Argument 03 Description P Structured Text i 400 2 WIRE TWO STEP MODE TS HMI Debounce TS HMI in scratch LI6 Debounce LI6 in scratch PLC Control LI6 debounced TS HMI debounced HMI Control LI6 debounced TS HMI debounced TS Control Transfert in Process save old Transfert in Process Requested Mode is it Active Mode Not equal Transfert in Process Transfert in Process NOT Bumpless in Process Bumpless Bumpless in Process one scan Transfert in Process Not bumpless Look for Edge Transfert in Process Mode Wait 1 Mode Change 1 Transfert in Process Mode Wait 2 Mode Change 2 not Transfert in Process PLC requested PLC active LOGIC_ID LOAD_BIT SET_TMP_BIT LOAD_BIT SET_TMP_BIT SET_TMP
167. cribed further in this chapter see 3 Wire Independent Operating Mode Program Sections p 173 followed by an address table see 3 Wire Independent Operating Mode Allocation Tables p 175 section which defines the inputs and outputs in each segment of the Pcode program This information is intended to help you to understand the program s objectives well enough to quickly locate the section of the code and the variables that you wish to modify Example In the 3 wire independent mode make the LTM R Terminal Strip input 3 generate an external fault condition External fault bit will activate fault bit 455 2 disabling LO4 on the next scan There are several general programming techniques used in the operating modes However some rules are common to all of them e The default state for all custom logic memory addresses is zero e lf the logic does not direct the state of the bit as True the status of the bit is considered to be False and set to zero e The LTM R controller scans the logic program from top to bottom 166 1639507 12 2006 Programming Approach New Commands Debounced Bits Some programming functions are only active when a new command is detected To detect a new command the status of the variable as a result of the previous scan is saved to history The status of the variable in the current scan is compared to the status of the last scan Several bits are debounced into a temporary scrat
168. d 2 Right click and select either Insert row below or Insert row above Change the command and its assigned values to those required for your new instruction By default the command added in the new row is LOGIC_ID Deleting an To delete an instruction Instruction bois Step Action 1 Left click on the command box of the row you want to delete 2 Right click and select Delete row 42 1639507 12 2006 Structured Text Language Logic Commands Overview All controller configuration files consist of a series of logic commands Each logic command consists of the command itself plus up to 3 arguments Each logic command performs its operation linked to either a 1 bit Boolean accumulator value range 0 1 or a 16 bit unsigned accumulator value range 0 65 535 The custom logic editor provides the following kinds of logic commands Boolean Register Timers Latch Counters Math 1639507 12 2006 43 Structured Text Language Boolean logic Boolean commands evaluate and control simple Boolean On Off values Boolean commands commands include Command Argument 1 Argument 2 Argument 3 Description LOAD_K_BIT Constant Loads a constant value into the 1 bit Boolean value 0 or 1 accumulator LOAD_BIT Register Register bit Loads a internal control register bit from the address address no 0 15 identified in Argument 1 and the bit identified in Ar
169. defines the logic memory used that is the number of non volatile LTM R logic memory words 16 bits used by logic commands which are currently stored in the LTM R controller Register 1204 defines the number of temporary registers provided by the LTM R controller Register 1205 defines the number of non volatile registers provided by the LTM R controller 1639507 12 2006 27 Introduction to Custom Logic Editor 28 1639507 12 2006 Structured Text Language At a Glance Overview What s in this Chapter The structured text editor enables you to create a custom logic program based on the structured text programming language This chapter contains the following sections Section Topic Page 2 1 Creating a Structured Text Program 30 2 2 Logic Commands 53 2 3 Structured Text Program Examples 97 2 4 Compiling and Simulation of a Structured Text Language Program 102 1639507 12 2006 29 Structured Text Language 2 1 Creating a Structured Text Program At a Glance Summary This section describes the creation of a program with the structured text editor Use the structured text editor to modify the pre defined operating program by e changing the input and output assignments of the logic functions and e adding new logic functions that will change the step by step instructions of the original program Create a new p
170. dicates that the Count value is greater than the PresetValue IncHistory BOOL Argument 3 Bit 7 indicates the status of the Increment bit Argument 3 Bit 4 from the previous scan DecHistory BOOL Argument 3 Bit 8 indicates the status of the Decrement bit Argument 3 Bit 5 from the previous scan SetHistory BOOL Argument 3 Bit 9 indicates the status of the Set bit Argument 3 Bit 6 from the previous scan 1639507 12 2006 91 Structured Text Language COUNTER_NV The COUNTER_NV command increments or decrements a count value provides a method for setting the count value to a preset value indicates when the count value equals 0 indicates the relationship between the count value and the preset value equal to greater than or less than e saves the increment decrement and set status from the previous scan Use the COUNTER_NV command instead of the COUNTER command to retain the count during a power cycle Arguments Representation 3 COUNTER NVReg KValue NVReg Input arguments Argument Type Description PresetValue UINT Argument 2 a preset integer from 0 to 65 535 Used to e set the count value equal to the PresetValue e compare the count value to the PresetValue Increment BOOL Argument 3 Bit 4 the rising edge of this bit increases the Count by a value of 1 Decrement BOOL Argument 3 Bit 5 the rising edge
171. dress an integer from 0 to 1399 BitNo UINT The bit location an integer from 0 to 15 Output arguments 64 1639507 12 2006 Structured Text Language OR_NOT_TMP_BIT The OR_NOT_TMP_BIT command e inverts the Boolean value 0 or 1 of a specified temporary register bit then e makes a logical OR link between it and the accumulator content in logic memory If the value of either the bit accumulator or the inverted temporary register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0 the result of the OR process is 0 The result is saved in the 1 bit accumulator OR_NOT_NV_BIT Arguments Representation 2 OR_NOT_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments The OR_NOT_NV_BIT command e inverts the Boolean value 0 or 1 of a selected non volatile register bit then e makes a logical OR link between it and the accumulator content in logic memory If the value of either the bit accumulator or the inverted non volatile register bit equals 1 the result of the OR process is also 1 if the values of all compared bits equal 0
172. e 5 Global Stop 6 Stopl fd 7 Stop2 8 Run1 TEA 9 Run2 10 Unused 11 Unused 12 Unused 13 Swapping in process always 0 in this program Temp 5 as state bits group 2 Unused in this program Temp 12 as INPUT History 1 PLC Run 1 Ef 2 PLC Run 2 3 HMI Run 1 Lt 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Bump Mode Change for Output 1 8 Unused 9 Bump Mode Change for Output 2 ae 10 Unused aa 11 Bumpless mode in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONSET status Low to High timer Temp 52 as ONSET status High to Low timer Temp 53 Latch Temp 54 as Mask off Reg 704 Run1 Run2 in bumped transfers 1639507 12 2006 171 Programming Approach Temporary The bit 13 of the temporary register 4 swapping in process is always to 0 in the 3 Register 4 bit 13 wire independent operating mode This bit is used in the 2 wire 2 speed see p 229 3 wire 2 speed see p 300 2 wire reverser see p 229 and 3 wire reverser see p 245 pre defined operating modes In these programs the PCode manages whether or not a STOP is required to change or SWAP a command from LO1 to LO2 Temporary Temporary address locations 50 51 52 53 are used in the 2 speed reverser or 2 Register 50 to 54 step pre defined operating modes In these programs the PCode must detect that the approp
173. e HMI Fallback Values LOAD_REG 645 HMI fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 3 LO1 HMI fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 4 LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed ON 3 no action needed COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 3 logical or with previous value SET_TMP_BIT 4 3 LO1 HMI fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 4 logical or with previous value SET_TMP_BIT 4 4 LO2 HMI fallback Latch HMI Keypad info LOAD_BIT 1020 12 Aux 1 SET_TMP_BIT 13 12 LOAD_BIT 1020 13 Aux 2 SET_TMP_BIT 13 13 LOAD_BIT 1020 14 Stop SET_TMP_BIT 13 14 1639507 12 2006 249 Pre Defined Structured Text Programs Structured Text Program cont d Generate Global Stop in Temp Reg 4 5 LOAD_TMP BIT 13 14 R_NOT_BIT 457 3 R_BIT 456 5 R_BIT 453 1 R_BIT 453 2 ET TMP_BIT 4 5 OAD_NOT_TMP_BIT 3 0 D_NOT_TMP BIT D_NOT_TMP BIT R_TMP_BIT 4 5 ET TMP_BIT 4 5 OAD_NOT_BIT 1200 0 ND_BIT 456 4 R_TMP_BIT 4 5 ET TMP_BIT 4 5 EUOG 00O O 3 1 3 2 Be Puno gt n
174. e OFF include previous result save partial result 100 1639507 12 2006 Structured Text Language Creating a Truth Table with a Structured Text Program cont d LL RRRRRRRRERERERKE GRE LOAD_TMP_BIT 1 1 AND_TMP_BIT 1 2 AND_NOT_TMP_BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 LL RERRRRRRRRERERET RR LOAD_TMP_BIT 1 1 AND_TMP_BIT 1 2 AND_TMP_BIT 1 3 OR_TMP_BIT 1 15 SET_TMP_BIT 1 15 LOAD_TMP_BIT 1 15 SET_BIT 517 3 Inputs 1 2 3 are ON ON OFF include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result Inputs 1 2 3 are ON ON ON include this SECTION if output is to be ON REMOVE if output to be OFF include previous result save partial result SET OUTPUT 1639507 12 2006 101 Structured Text Language 2 4 Compiling and Simulation of a Structured Text Language Program At a Glance Summary The following section describes how to compile a structured text language program It also describes the user interface windows involved in the compiling of the program and the logic simulator What s in this This section contains the following topics Section Topic Page Introduction 103 PCode Window 104 Error Window 106 Output Window 108 Quick Watch Window 110 LTM R Controller Logic Simulator 112 102 163950
175. e in your applications e Checking timers and multiply commands e Creating a truth table What s in this This section contains the following topics Section Topic Page How to Check Timers and Multiply Commands 98 How to Create a Truth Table 99 1639507 12 2006 97 Structured Text Language How to Check Timers and Multiply Commands Overview Checking Timers and Multiply Commands with a Structured Text Program Customizing your application you may need to check timers and multiply commands The following diagram gives the structured text program in Text View of how to check timers and multiply commands LOGIC_ID 256 A very simple test that checks timers and MUL multiply command It should switch LO1 and LO2 ON OFF if OK LOAD_K_BIT 1 SET_TMP_BIT 15 3 LOAD_TMP_REG 15 ON_SET_TMP_REG 5 11 ON_SET_TMP_REG 8 12 LOAD_NOT_TMP_BIT 10 2 timer 2 not timing SET_TMP_BIT 7 0 TIMER_TENTHS 5 6 7 LOAD_NOT_TMP_BIT 7 2 timer 1 not timing SET_TMP_BIT 10 0 TIMER_TENTHS 8 9 10 LOAD_TMP_BIT 7 2 SET _BIT 1200 12 Switch LO1 if timer 1 is working LOAD_K_REG 50 Load value of 50 LOAD_K_BIT 1 SET_NOT_TMP_BIT 23 3 Clear history bit ON_SET_TMP_REG 22 23 Save the 50 in temporary register 22 LOAD_K_REG 2 Load value of 2 SET_NOT_TMP_BIT 23 3 ON_MUL 21 22 23 Multiply 50x2 LOAD_TMP_REG
176. e outline Write Temporary Select one of the following commands e Edit gt Copy e Edit gt Cut e Edit gt Paste Result Cut deletes the selected blocks and stores them in the clipboard Copy duplicates the selected blocks in the clipboard and Paste duplicates the clipboard contents on the workspace Note The keyboard shortcuts Ctrl A Ctrl C Ctrl V and Ctrl X can also be used to copy the selected blocks and either paste or delete them 146 1639507 12 2006 Function Block Diagram Language 3 5 FBD Editor Display Options At a Glance Summary The following section describes the differents FBD editor display options What s in this This section contains the following topics Section i Topic Page Other Display Options 148 Workspace Appearance and Graph Options 149 1639507 12 2006 147 Function Block Diagram Language Other Display Options Summary Zoom Display Options Links Display Options Inputs Outputs Display Options You can customize the following display options to suit your requirements e Zoom e Links e Inputs Outputs To access zoom options click View in the top level menu bar 3 options are offered e Zoom Out to see more of the program at once shortcut F3 e Zoom In to focus on the program in more detail e Zoom To 50 75 100 150 200 or 400 to have a customized view of the program T
177. e program 138 1639507 12 2006 Function Block Diagram Language Creation of Links between Blocks Ata Glance General Rules After you have positioned the blocks in the workspace you can link them together To do this you link a block s output to the input of another block You can also loop an output back to the input of the same block There are some basic rules that apply when placing and connecting blocks e One or more connecting wires attached together form a wire node This is indicated in the workspace by a red dot If wires cross without a red connection dot it means they are not connected e Only one output can be attached to each wire node Connections between boolean and register data are prohibited e Data typically flows from left to right 1639507 12 2006 139 Function Block Diagram Language Link between The following procedure describes how to link blocks together BIOCKS Step Action 1 Place the mouse over the first block Result One or more squares become visible on the block border and the type of output analog or boolean is indicated 2 Click the left mouse button and hold it down With the button held down move the cursor over the input of the block you want to link to Result One or more squares become visible on the block border If the square is green a connection between the two blocks is possible A red square indicate
178. eeded ON 3 fallback to ON equal 1 logical or wi th previous LO1 PLC fallback fallback to ON equal 1 logical or wi th previous LO2 PLC fallback ON OFF 4 fallback to ON equal 1 logical or wi th previous LO1 PLC fallback OFF ON 5 fallback to ON equal 1 logical or wi th previous LO2 PLC fallback value value value value 194 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate HMI Fallback Values LOAD_REG 645 COMP_K_REG 0 LOAD_TMP_BIT 0 2 AND_BIT 1200 SET_TMP_BIT LOAD_TMP_BIT 0 2 AND_BIT 1200 SET_TMP_BIT COMP_K_REG 3 LOAD_K BIT 1 AND_TMP_BIT OR_TMP_BIT 4 SET_TMP_BIT LOAD_K_BIT 1 AND_TMP_BIT OR_TMP_BIT 4 SET_TMP BIT COMP_K_REG 4 LOAD_K BIT 1 AND_TMP_B OR_TMP_BI SET_TMP_B COMP_K_RE LOAD_K_BI B I B U w AND_TM H z d OR_TMP_BIT 4 SET_TMP_ 0 12 4 3 oid 4 4 0 HMI fallback mode HOLD 0 equal last LO1 command LO1 HMI fallback equal last LO2 command LO2 HMI fallback STEP 1 no action needed OFF 2 no action needed ON 3 fallback to ON equal logical or wi th previous LO1 HMI fallback fallback to ON equal
179. egister Argument 1 Status bit 3 Argument 2 is used to remember the previous state of the 1 bit accumulator ON_SET_NV_REG Non volatile Temporary When the 1 bit Boolean accumulator transitions register address register from 0 to 1 the 16 bit accumulator is stored into a address non volatile register Argument 1 Status bit 3 Argument 2 is used to remember the previous state of the 1 bit accumulator Argument not applicable to logic command 1639507 12 2006 49 Structured Text Language Timer logic commands Timers have a range of 0 to 65 535 and measure time in intervals of seconds or tenths of seconds Argument 1 specifies the time period Argument 2 is a calculated end time The first four bits of the status register Argument 3 describe timer operations as follows e bit 0 enable input bit the rising edge of this bit starts the timer and sets bit 2 e bit 1 timed out status bit cleared by clearing bit 0 or by cycling power e bit 2 timing status bit expiration of the time period clears bit 2 and sets bit 1 e bit 3 enable history Timer commands include Command Argument 1 Argument 2 Argument 3 Description TIMER_SEC Temporary register time period Temporary register calculated end time Temporary register status Counts in seconds the time period input in Arg1 as described by status register bits O0 Enable 1 Timed Out 2 Timing 3 Enable Histo
180. em The two main hardware components of the system are the LTM R controller and the LTM E expansion module Components such as external motor load current transformers and ground current transformers add additional range to the system The system can be configured and controlled using either a HMI Operator Terminal a PLC ora PC The LTM R PC configuration utility LTM CONF is required to configure the LTM R controller with custom logic programs 12 1639507 12 2006 Introduction to Custom Logic Editor LTM R controller The microprocessor based LTM R controller is the central component in the system that manages the control protection and monitoring functions of single phase and 3 phase ac induction motors e The pre defined functions are those which fit the applications most frequently used in motor starter applications They are ready to use and are implemented by simple parameter setting after the LTM R controller has been commissioned e The pre defined control and monitoring functions can be adapted for particular needs The LTM CONF utility allows a programmer to e edit pre defined control functions e alter the default LTM R controller I O logic assignments The pre defined control program performs 3 main actions e acquisition of input data e the protection function fault and warning state e external logic data from logic inputs e telecommunication commands TC received from the control sou
181. er by loading a corrupt function over it or by data loss in the memory then the LTM R controller issues a minor internal fault as soon as the corruption is detected 162 1639507 12 2006 Appendices Custom Logic Pre Defined Operating Modes Programs Overview The LTM R supports 10 pre defined operating modes The following chapter contains shows their program in structured text language What s in this The appendix contains the following chapters Appendix Chapter Chapter Name Page A LTM R Controller Programming Approach 165 B Pre Defined Operating Modes Structured Text Programs 179 1639507 12 2006 163 Appendices 164 1639507 12 2006 LTM R Controller Programming Approach A At a Glance Overview These appendices include the Pcode files used for the 10 pre defined operating modes To help introduce the general programming strategy for each of the 10 pre defined operating mode this chapter includes a summary of the strategy used for one program the 3 wire independent operating mode which is the most commonly used While the other programs may have more or less program steps a general understanding of this program will help you in your attempt to analyze any of the 10 programs for the pre defined operating modes What s in this This chapter contains the following topics Chapter Topic Page LTM R Controller Programming Strategy for the 3 Wire
182. es a general description of FBD language Use the FBD language to customize a pre defined operating mode or to create a new program to suit the requirements of a specific application created using FBD What s in this This section contains the following topics Section Topic Page Introduction to the FBD Editor 117 FBD Editor Toolbox 120 116 1639507 12 2006 Function Block Diagram Language Introduction to the FBD Editor Overview The FBD editor is a feature of TeSys configuration software Use the FBD editor to view an existing FBD file or to create a new FBD file using FBD language rather than an instruction based text programming language Creating an FBD To open the FBD editor navigate in the configuration software tree on the left of the screen Program to Custom Logic Function Blocks This will open the FBD editor in the main window Each FBD file when you save it has a file extension of Gef 1639507 12 2006 117 Function Block Diagram Language FBD Editor User The FBD editor is available even when the configuration software is not connected Interface to the LTM R controller However many of the menu items will be enabled only when an FBD program is open in the FBD editor When an FBD file is open the FBD editor looks like this Function Block Editor 2 0 BE File Edit compile View Tools About Toolbox Computat
183. final Stopl 1639507 12 2006 251 Pre Defined Structured Text Programs Structured Text Program cont d Gene LOAD_T OAD_T D_ TM O 3 2E iw sz 8 as Ol H F uno oO PHI 3 2 iw a 0 sg 2 W Q gt o no Hw A lz 2 D_TM Be no mw H TM lt OR_NOT_ SET_TMP_BIT MP rate Stop2 MP_BIT 4 5 TMP_BIT 12 12 4 7 MP_BIT 0 0 P_BIT 3 0 T_TMP_BIT 4 2 BIT 4 7 P_BIT 4 7 MP_BIT 0 1 P_BIT 3 1 T_TMP_ BIT 4 4 BIT 4 7 P_BIT 4 7 OAD_TMP_BIT 3 0 ND_NOT_BIT 704 1 P_BIT 4 9 D_NOT_TMP_BIT 0 0 BIT 4 7 P_BIT 4 7 Global Stop NOT Powerup Done save partial Stop7 PLC Comm Loss PLC active NOT LO2 from scratch PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss HMI active NOT LOL from scratch HMI fallback value Include partial Stop2 save partial Stop2 PLC active NOT PLC Run2 Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save final Stop2 252 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands he LOAD_TMP_BIT 12 1 AND_NOT_TMP BIT 12 11 SET_TMP_BIT 12 0 LOAD BIT 704 0 OT_BIT 704 1 MP BIT 12 12 OT_TMP_ BIT 4 6 MP BIT 12 1 OT_TMP_BIT 12 0 MP BIT 3 0 NOT_TMP_ BIT 4 6 OT_TMP_BIT 0 0 OR_TMP_BIT 4 8 SET_TMP BIT 4
184. for 3 Wire Reverser Mode Overview The structured text program for the 3 wire reverser mode is defined below Structured Text Program LOGIC_ID 7 3 WIRE REVERSER MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode Temp Temp O PLC 1 HMI 2 TS 3 as Ac O PLC 1 HMT 2 TS 4ass terminal strip tive Control Mode terminal strip tate bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value 5 Global Stop 6 Stopl 7 Stop2 8 Runl 9 Run2 10 Forward 11 Reverse 12 Reversing Timer Active 13 Swapping 14 Last Direction 15 Two Wire Swap 1639507 12 2006 245 Pre Defined Structured Text Programs Structured Text Program cont d Temp 5 as state bits group 2 Temp eee 0 11 as Forward Reverse Timer Temp 12 as INPUT History 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 10 11 Bumpless in Process 12 Power up Done Temp 50 as general status registers Temp 50 as ONSET status transition time value Temp 51 as ONSET status
185. from scratch Include previous result save partial Run 1 3wire latch NOT Mode Change 1 save final Run 1 294 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 2 zz SI Cd D_NOT_TMP BIT 12 11 D_NOT_TMP_ BIT 4 7 T TMP BIT 12 0 LOAD_BIT 704 0 ee Be R_TMP_BIT nO LOAD_TMP_BIT 12 4 AND_NOT_TMP_BIT D TMP BIT 12 12 D NOT_BIT 704 6 ET TMP BIT 12 2 D_NOT_TMP BIT 12 0 D_TMP_BIT 3 0 4 9 ET_TMP_BIT 4 9 T2221 AND_NOT_TMP_BIT 4 7 SET_TMP_BIT 12 0 LOAD _TMP_BIT 13 13 AND_TMP_BIT 12 12 SET_TMP BIT 12 4 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 1 OR_TMP_BIT 4 9 SET_TMP_BIT 4 9 LOAD_TMP_BIT 12 6 TMP BIT BS EE D_TMP_BI1 T TMP BIN n eI Bee D TMP BIT R_ TMP BIT TMP BIT O n za l D_NOT_TMP_BIT 12 11 D_NOT_TMP_BIT 4 7 rT 12 0 AD_BIT 457 1 M 12 12 P2456 D_NOT_TMP_BIT 12 0 P32 4 9 r 4 9 Generate Run 2 PLC mode Input history NOT Bumpless in Process NOT Stop2 Save previous history PLC Network Run2 Power up Done NOT Low Speed Save new history NOT previous history PLC active Include previous result save partial Run2 HMI mode Input history NOT Bumpless in Process NOT Stop2 Save previous history HMI Run2 Power up
186. g timers and compare functions can be used if you need larger values or multiple thresholds 1639507 12 2006 129 Function Block Diagram Language Counter NV Block Characteristics The function performs a comparative count saving both the count and status to non volatile registers The following table describes the Counter NV block characteristics FBD symbol Inputs outputs Description Inputs K 16 bit unsigned constant 0 to 65 535 which specifies a preset count value Inc ON OFF input value The counter value increments by one when this input transitions from OFF to ON Count value shall roll over from 65 535 to 0 Dec ON OFF input value The counter value decrements by one when this input transitions from OFF to ON Count value shall roll over from 0 to 65 535 Set ON OFF input value The count value is set to preset value when this input transitions from OFF to ON Outputs Count 16 bit unsigned counter value 0 to 65 535 This value is saved in non volatile memory and initialized to the previous value on power up lt K ON OFF temporary bit which is ON if counter value is less than K K ON OFF temporary bit which is ON if counter value is equal to K gt K ON OFF temporary bit which is ON if counter value is greater than K Note The Counter block range is 0 to 65 535 Cascading timers and compare functions can be used if you need larger values
187. gic Temporary Space register at address 1204 Output arguments The AND_NV_REG command makes a logical AND link between the non volatile register value and the accumulator content in logic memory The AND process compares each bit in the 16 bit accumulator with the corresponding bit in the linked non volatile register If both bits equal 1 the result of the AND process for that bit location is also 1 in all other cases the result of the AND process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 AND_NV_REG NVReg Input arguments Argument Type Description NVReg UINT The non volatile space register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 Output arguments 76 1639507 12 2006 Structured Text Language OR_K The OR_K command makes a logical OR link between a 16 bit constant value and the accumulator content in logic memory The OR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked 16 bit constant If any compared bit equals 1 the result of the OR process for that bit location is also 1 if all compared bits equal 0 the result of the OR process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation
188. gument 2into the 1 bit Boolean accumulator LOAD_TMP_BIT Temporary Register bit Loads a temporary register bit into the 1 bit register no 0 15 Boolean accumulator address LOAD_NV_BIT Non volatile Register bit Loads a non volatile register bit into the 1 bit register no 0 15 Boolean accumulator address LOAD_NOT_BIT Register Register bit Loads an inverted Boolean value of a register bit address no 0 15 into the 1 bit Boolean accumulator LOAD_NOT_TMP_BIT Temporary Register bit Loads an inverted Boolean value of a temporary register no 0 15 register bit into the 1 bit Boolean accumulator address LOAD_NOT_NV_BIT Non volatile Register bit Loads an inverted Boolean value of a non volatile register no no 0 15 register bit into the 1 bit Boolean accumulator address AND_BIT Register Register bit Loads the result of a logical AND link between address no 0 15 the register bit value and the accumulator content The result is stored in the 1 bit Boolean accumulator AND_TMP_BIT Temporary Register bit Loads the result of a logical AND link between the register no 0 15 temporary register bit value and the accumulator content address The result is stored in the 1 bit Boolean accumulator AND_NV_BIT Non volatile Register bit Loads the result of a logical AND link between the non register no 0 15 volatile register bit value and the accumulator content address The result is stored in the 1 bi
189. he following rules Your program must If it is have a Logic ID in the range Oto 1 unused 2 to 11 a pre defined operating mode program 2 wire overload 3 wire independent etc 12 to 255 a pre defined program reserved for future used 256 to 257 a full custom program 258 to 267 a custom pre defined program 268 to 511 a custom pre defined program reserved for future used As explained above a custom pre defined program is a modified version of a pre defined operating mode program When configured with one of the pre defined operating modes the LTM R motor controller manages the control functions using both the firmware in the LTM R controller microprocessor and the PCode When configured with a custom pre defined program the LTM R controller retains the functions controlled by the LTM R controller microprocessor Those functions include the following characteristics that are inherent to the parent pre defined operating mode e restrictions to what can be written to register 704 network command register e display of the operating state in presentation mode Fwd Reverse Low Speed High Speed for example e automatic adjustment of power amp power factor measurement in 2 step mode with Star Delta starting selected e restrictions on which fallback modes may be set through the menus e specific behaviors regarding the start cycle in 2 step mode e restrictions on whether the transi
190. he logic simulator is then displayed In the right bottom corner see below click on the Load If File button to import your program you previously compiled The logic simulator with a loaded custom logic file is then displayed LTMR Logic Simulateur ViewWin 0x8002 00 00 Rev 1 15 1200 IMPR Logic Intf 1201 Logic Version 1202 Logic mem Avail 1203 Logic mem Used 1204 Temp Reg s Avail 1205 Non Vol Avail 1206 View Win Status 1207 View Win Type 1208 View Win Offset 1209 View Win Comd 1210 View Win 0 1211 View Win 1 1212 View Win 2 1213 View Win 3 1214 View Win 4 1215 View Win 5 1216 View Win 6 1217 View Win 7 1218 View Win 8 1219 View Win 9 1220 View Win 10 1221 View Win 11 1222 View Win 12 1223 View Win 13 1224 View Win 14 1225 View Win 15 Register View C LTMR Reg s Start A Trace C Temp Reg s C NV Reg s Logic Reg s Hex Refresh 873 45668 264 L19 Logic Primitives Refresh 0 Size 873 p 1 Checksum 45668 z 2 LogicID 264 3 LOAD_BIT 683 8 6 SET_TMP_BIT 0 1 9 LOAD_BIT 516 5 12 SET_TMP_BIT 0 0 15 SET_TMP_BIT 2 0 18 LOAD_NOT_TMP_BIT 0 0 21 AND_TMP_BIT 0 1 24 LOAD_NOT_TMP_BIT 0 0 Motor Run Motor Stop Reset In Step 2 Trans Timer Phase Error Remote FLA1 FLA2 External fault Aux1 LED Aux2 LED Stop LED Output 1 Output 2 Output 3 Output 4 LO
191. history NOT Bumpless in Process Save previous history HMI Runl Power up Done Save new history NOT previous history HMI active Lockout Timer Include previous result save partial Runl TS mode Input history NOT Bumpless in Process Save previous history UI1 Power up Done Save new history NOT previous history TS active Lockout Timer Include previous result save partial Runl 210 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 1 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 3 0 0 0 4 8 SET_TMP_BIT 4 8 LOAD_TMP_BIT 4 3 AND_TMP_BIT AND_TMP_BIT OR_TMP_BIT 3 1 0 1 4 8 SET_TMP_BIT 4 8 AND_NOT_TMP_BIT 4 13 AND_NOT_TMP_BIT 12 7 SET_TMP_BIT 4 8 LOAD_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 0 LOAD_BIT 704 1 AND_TMP_BIT 12 12 SET_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT OR_TMP_BIT SET_TMP_BIT r 3 0 4 59 r 4 9 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Swapping NOT Mode Change 1 save final Run 1 Generate Run 2 PLC mode Input history NOT Bumpless in
192. ights Reserved 1639507 12 2006 About the Book Z At a Glance Document Scope Validity Note Related Documents Product Related Warnings This document describes the custom logic editor It is provided with LTM CONF configuration utility to manage TeSys T LTM R controllers Information in this document only applies to custom logic editor that comes with LTM CONF configuration utility included in the CD Title of Documentation Reference Number TeSys T LTM R Modbus User s Manual 1639501 TeSys T LTM R Profibus User s Manual 1639502 TeSys T LTM R CANopen User s Manual 1639503 TeSys T LTM R DeviceNet User s Manual 1639504 You can download this technical publication and other technical information from our website at http www telemecanique com A WARNING UNINTENDED EQUIPMENT OPERATION The application of this product requires expertise in the design and programming of control systems Only persons with such expertise should be allowed to program and apply this product Follow all local and national safety codes and standards Failure to follow this instruction can result in death serious injury or equipment damage 1639507 12 2006 About the Book User Comments We welcome your comments about this document You can reach us by e mail at techpub schneider electric com 10 1639507 12 2006 Introduction to Custom Logi
193. il initialization is complete 156 1639507 12 2006 Connection to the LTM R Controller Connection After initialization the LTM R controller should automatically connect to the PC To verify that the controller is connected check the task bar in the custom logic editor If the task bar reads Not connected then select Connect on the Link menu or click the Connect icon LTM CONF Default File Edit Link Settings Logic Functions Tools EC Ck r Device Information 269 Sli ob gt Settings 0 Statistics gt Monitoring at Parameters E Custom Logic Structured Tex 10 SET_TMP_BIT 2 0 LOAD_NOT_TMP BIT 0 0 AND_TEP_BIT 0 1 SET_TMP_BIT 2 1 LOAD_NOT_TMP BIT 0 0 AND_NOT_TMP BIT 0 1 SET_TMP_BIT 2 2 LOAD_TMP_BIT 4 0 _TMP_BIT 0 0 TMP_REG 2 TMP _REG 3 1 NOT_TMP BIT 1 2 f TMP_BIT 4 0 LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 1 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 OR_TMP_BIT 12 8 SET_TMP_BIT 12 7 LOAD_TMP_BIT 4 0 OR_TMP_BIT 12 10 SET_TMP_BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 LOAD_NOT_TMP_BIT 4 0 D_TMP_BIT 2 2 T TMP BIT 3 2 LOAD_BIT 1200 12 OR_BIT 1200 13 AND_TMP_BIT 0 2 SET_TMP_BIT 4 1 COMP_K_REG 1 0 11 aw 11 uw a 1
194. in toolbar when the structured text editor is open Result The PCode Pseudo Code window notifies you when the logic file has successfully compiled The PCode window is a feature of LTM CONF programming software Download the completed logic file from the custom logic editor to the LTM R controller using the logic functions menu Download Program to Device command 1639507 12 2006 119 Function Block Diagram Language FBD Editor Toolbox At a Glance Computation Blocks Inputs Blocks Function Blocks Logic Blocks Outputs Blocks To create an FBD program the different functions to be inserted in the workspace are available in the toolbox Each of the tabs in the toolbox groups a function type When you click one of the tabs it displays the list of available blocks Note You can navigate between the different tabs holding the Ctrl key and pressing the Tab key The following figure shows the Computation blocks 2K The following figure shows the Inputs blocks 1E wv oe Sele Ze LTMR NV NV LTMR Tmp Tmp The following figure shows the Function blocks The following figure shows the Logic blocks AND NOT OR The following figure shows the Outputs blocks 1 1 16 16 i 16 LTMR NV NV LTMR Tmp Tmp 120 1639507 12 2006 Function Block Diagram Language 3 2 FBD Elements FBD Elements Overview Summary This section describe
195. ing conditions must be met e Atleast one setting in the logic file must be different from the corresponding setting in the controller i e the software only overwrites settings with different values e Current must not be detected that is online current must be less than 10 of FLC If these conditions are not met the file cannot be transferred to the controller Note When you transfer a configuration file from the PC to the LTM R controller the software checks to confirm that the LTM R controller and the configuration file both use the same e current range and e network protocol If there is a mismatch the software asks if you wish to proceed If you elect to proceed the software transfers all matching parameters excluding parameters that fail a range check When the transfer is complete the software displays the names and addresses of parameters that failed the range check and were not transferred 160 1639507 12 2006 Connection to the LTM R Controller File Transfer Procedure PC to LTMR Controller To transfer a logic file from the custom logic editor to the LTM R controller Step Action 1 Ensure that the LTM R controller is connected to the PC See p 157 2 Ensure that the file to be transferred is in the Main window To open a file select the Open Configuration command in either the icon bar or the File menu Then navigate to the desired location and click Open 3 a
196. ion Inputs a 1 fie 1 1 fel fic 1 IN LTMR NV NV LTMR Tmp S16 im Tmp Temporary Ki DE Create Diagram and Hit Compile a Function Blocks d Logic _ Outputs Workspace FBD programs are edited and created in the workspace The workspace is made up of 2 elements e blocks and e wires to link the blocks 118 1639507 12 2006 Function Block Diagram Language How to Create and Use a FBD Program Follow these steps to create an and use an FBD program Step Action 1 Select Settings Motor Motor Operating Mode to use the custom logic editor in the configuration software Set the operating mode to Custom Navigate in the configuration software tree on the left of the screen to Custom Logic Function Blocks Result The FBD editor opens Create your FBD program using blocks and link them with wires in the workspace Use the Compile to structured text command in the FBD editor s Compile menu to validate the FBD file when you have finished editing it Result The FBD program compiles to structured text Minimize the FBD editor window and navigate in the configuration software tree on the left of the screen in LTM CONF configuration software to Custom Logic Structured Text Result The program is automatically copied into the structured text editor and has a glf extension Compile this program by clicking Compile in the menu displayed in the LTM CONF ma
197. iption KValue UINT A constant value from 0 to 65 535 Output arguments LOAD_REG The LOAD_REG command loads a copy of a register into the accumulator in logic memory Arguments Representation 1 LOAD_REG RegAddr Input arguments Argument Type Description RegAddr UINT The register address an integer from 0 to 1399 Output arguments 70 1639507 12 2006 Structured Text Language LOAD_TMP_REG The LOAD_TMP_REG command loads a copy of a temporary register into the accumulator in logic memory Arguments Representation 1 LOAD_TMP_REG TmpReg Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 Output arguments LOAD_NV_REG The LOAD_NV_REG command loads a copy of a non volatile register into the accumulator in logic memory Arguments Representation 1 LOAD_NV_REG NVReg Input arguments Argument Type Description NVReg UINT The non volatile space register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 Output arguments 1639507 12 2006 71 Structured Text
198. iption range Temporary 0 69 The user Temporary storage of bit and registers assigned by the user when creating an FBD program Temporary 70 299 LTM CONF Reserved temporary registers for use by the compiler Non volatile 0 31 The user Non volatile bits or registers assigned by the user when creating an FBD program Non volatile 32 63 LTM CONF Reserved non volatile registers for use by the compiler 142 1639507 12 2006 Function Block Diagram Language Compiling an FBD program At a Glance Saving an FBD Program Converting to Structured Text Compiling Structured Text As custom logic functions are based on the structured text language compiling an FBD program is a 2 step process First the FBD program is converted into a structured text compatible file i e If This file is then compiled and downloaded into the LTM R controller or simulator using the structured text editor tools provided with LTM CONF programming software Before compiling the FBD program you must save it To save the program you created or edited click File in the top level menu bar and choose Save As Note The file you saved will have a Gef extension To compile into structured text the program you created or edited click Compile in the top level menu bar and choose To structured Text A window is displayed at the bottom of the workspace with the corresponding structured text program Note You can not convert a
199. ive NOT LO2 PLC fallback value Include partial Stop2 save partial Stop2 HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stop2 save partial Stop2 NOT PLC Run2 Low Speed PLC active Run 2 NOT PLC Comm Loss from scratch Include partial Stop2 save partial Stop2 HMI active NOT HMI Run 2 Run 2 NOT HMI Comm Loss from scratch Include partial Stop2 save partial Stop2 TS active NOT TS Run 2 Run 2 Include partial Stop2 save final Stop2 292 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands he LOAD_TMP_BIT 12 1 AND_NOT_TMP_BIT 12 11 AND_NOT_TMP_BIT 4 6 SET_TMP BIT 12 LOAD_BIT 704 0 AND_TMP_BIT 12 AND_BIT 704 SET_TMP BIT 12 6 0 12 1 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 0 4 4 OR_TMP_BIT SET_TMP_BIT 8 8 LOAD_TMP_BIT 12 3 AND_NOT_TMP_BIT 12 11 AND_NOT_TMP_BIT 4 6 SET_TMP_BIT 12 0 LOAD_TMP_BIT 13 12 AND_TMP_BIT 12 12 SET_TMP_BIT 12 3 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 1 4 4 OR_TMP_BIT SET_TMP_BIT 8 8 Generate Run 1 PLC mode Input history NOT Bumpless in Process NOT Stopl Save previous history PLC Network Runt Power up Done Low Speed Save new history NOT previous history PLC active
200. l LE soft ioh a F F rc RA EW Note Placing cursor over the icon will reveal a tool tip defining the icon This will help you distinguish which type of counter latch mux or timer is represented by that icon 128 1639507 12 2006 Function Block Diagram Language Counter Block Characteristics CA The D function performs a comparative count saving both the count and status to temporary registers The following table describes the Counter block characteristics FBD symbol Inputs outputs Description Inputs K 16 bit unsigned constant 0 to 65 535 which specifies a preset count value Inc ON OFF input value The counter value increments by one when this input transitions from OFF to ON Count value shall roll over from 65 535 to 0 Dec ON OFF input value The counter value decrements by one when this input transitions from OFF to ON Count value shall roll over from 0 to 65 535 Set ON OFF input value The count value is set to preset value when this input transitions from OFF to ON Outputs Count 16 bit unsigned counter value 0 to 65 535 Count is initialized to zero on power up lt K ON OFF temporary bit which is ON if counter value is less than K K ON OFF temporary bit which is ON if counter value is equal to K gt K ON OFF temporary bit which is ON if counter value is greater than K Note The Counter block range is 0 to 65 535 Cascadin
201. l program Stage In operation the LTM R controller 1 scans the address inputs 2 executes program saved to memory logic addresses 3 sets the status of output addresses and directs the physical and logic outputs of the LTMR according to the state of the logic outputs in register 1200 Program Use the section see 3 Wire Independent Operating Mode Program Sections Sections p 173 titles to familiarize yourself with the general strategy for the 3 wire Pcode control program For more complex modifications you may wish to become more familiar with some of the common programming techniques as noted below 168 1639507 12 2006 Programming Approach Using the Program Sections To make the LTM R Terminal Strip input 3 generate an external fault condition Step Action 1 Locate the main section of the Pcode which manages the behavior of the LTM R controller outputs see Program Sections p 173 Result You will find that the section of the program titled Set Logic Outputs in the LTM R includes the logic output to initiate an LTM R external fault at address 1200 8 Locate the address representing the status of physical input 3 using the variables map in the LTMR user manual Result You will find that the address bit is 457 2 Open the PCode for the 3 wire independent operating mode see p 215 into the structured text editor see Introducing the Structured Text Editor p 31 Add the
202. ling a program 103 Computation Blocks 122 Connected 157 Connection 154 Connetion to the LTM R controller 153 Constant Bit Constant Bit FBD Function Block 125 Constant Word Constant Word FBD Function Block 125 COUNTER 91 Counter Counter FBD Function Block 129 Counter NV Counter NV FBD Function Block 130 COUNTER_NV 92 Custom logic editor Boolean logic commands 44 Commands 43 Counter logic commands 51 Latch logic commands 51 Math logic commands 52 Register logic commands 46 Timer logic commands 50 Custom operating modes 15 Custom pre defined program 17 1639507 12 2006 321 Index D Data transfer 24 Display Options 148 Division Division FBD Function Block 124 E Error 106 F FBD Resource management 142 FBD Blocks Deleting 146 Duplicating 146 Inserting 138 Linking 139 Properties 141 Selecting 145 FBD Blocks Properties 141 FBD editor Creating an FBD file 117 Using the FBD language 117 FBD Editor Toolbox 120 FBD Elements Computation Blocks 122 Function Blocks 128 Inputs Blocks 125 Logic Blocks 133 Outputs Blocks 134 FBD language 115 116 FBD Program How to Edit a FBD Program 119 Full custom program 17 Function Block Diagram 115 Function Blocks 128 G Grid view 40 Initialization 156 Inputs Blocks 125 Inserting FBD Blocks 138 L LATCH 89 LATCH_NV 90 Linking FBD Blocks 139 LOAD_BIT 56 LOAD_K_BIT 56 LOAD_K_REG 70 LOA
203. logic file you intend to transfer to the LTM R controller A saved copy provides both a record of these settings and a backup that can be used to re transfer configuration settings if the initial transfer fails Use the e Save command to save your changes to the open configuration file e Save As command to save a copy of the displayed configuration to a separate file Note If you opened the file containing the factory default configuration settings you cannot make and save changes to this file Instead you must use the Save As command to save your changes under another file name By default the configuration software stores saved files in a folder named Configurations This folder is located on your hard drive in the same place the configuration software was installed To designate a different default file storage folder Step Action 1 In the Settings menu select Preferences The Preferences dialog opens 2 In the Preferences dialog open the Configuration tab 3 In the Configuration tab type in the folder name and path for saving configuration files 4 Click OK to close the Preferences dialog and save your changes 1639507 12 2006 159 Connection to the LTM R Controller File Transfer PC After you have edited and compiled your logic file you can transfer the file to the toLTMR LTM R controller Before the configuration software will make this transfer the Controller follow
204. lue HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 NOT Stop 1 NOT Swapping NOT Mode Change 1 save final Run 1 224 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 2 AND_NOT_TMP_BIT 12 11 SET_TMP_BIT 12 0 LOAD_BIT 704 1 MP_BIT 12 12 OT_TMP_BIT 4 7 MP_BIT 12 2 NOT_TMP_BIT 12 0 D_TMP_BIT 3 0 D_NOT_TMP_BIT 4 7 D_NOT_TMP_BIT 0 0 OR_TMP_BIT 4 9 SET_TMP_BIT 4 9 ie gl AND_ AN J ae o Z LOAD_TMP_BIT 12 4 SET_TMP_BIT 12 0 LOAD_TMP_BIT 13 13 SET_TMP_BIT 12 4 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 1 AND_NOT_TMP_BIT 4 7 AND_NOT_TMP_BIT 0 1 AND_NOT_TMP_BIT 4 12 OR_TMP_BIT 4 9 SET_TMP_BIT 4 9 Generate Run 2 PLC mode Input history NOT Bumpless in Process Save previous history PLC Network Run2 Power up Done NOT Stop 2 Save new history NOT previous history PLC active NOT Stop2 NOT PLC Comm Loss from scratch Include previous result save partial Run2 HMI mode Input history Save previous history HMI Run2 Save new history NOT previous history HMI active NOT Stop 2 NOT HMI Comm Loss from scratch Lockout Timer Include previous result save partial Run2 1639507 12 2006 225 Pre Defined Structured Text Programs Structured Text Program
205. mands Overview COUNTER The custom logic editor uses the following counter logic commands e COUNTER e COUNTER_NV The COUNTER command increments or decrements a count value provides a method for setting the count value to a preset value indicates when the count value equals 0 indicates the relationship between the count value and the preset value equal to greater than or less than e saves the increment decrement and set status from the previous scan Arguments Representation 3 COUNTER TmpReg KValue TmpReg Input arguments Argument Type Description PresetValue UINT Argument 2 a preset integer from 0 to 65 535 Used to e set the count value equal to the PresetValue compare the count value to the PresetValue Increment BOOL Argument 3 Bit 4 the rising edge of this bit increases the Count by a value of 1 Decrement BOOL Argument 3 Bit 5 the rising edge of this bit decreases the Count by a value of 1 Set BOOL Argument 3 Bit 6 the rising edge of this bit sets the Count equal to the PresetValue Output arguments Count UINT Argument 1 the count An integer from 0 to 65 535 Zero BOOL Argument 3 Bit 0 indicates that the Count value is 0 LT BOOL Argument 3 Bit 1 indicates that the Count value is less than the PresetValue EQ BOOL Argument 3 Bit 2 indicates that the Count value equals the PresetValue GT BOOL Argument 3 Bit 3 in
206. mands that reside in the read only memory of the LTM R controller The LTM R controller uses the commands contained in the pre defined operating mode control program to 1 scan the LTM R controller s inputs including configuration parameters device settings physical and logic inputs 2 execute the logic commands 3 direct the LTM R controller s logical outputs such as R W status registers and physical outputs such as the LEDs The installation of the programming software includes 10 pre defined logic files one for each combination of e Operating Mode overload independent reverser 2 speed 2 step and e Control Wiring selection 2 wire maintained or 3 wire impulse The setting for custom operating mode enables you to create your own control program using the custom logic editor in LTM CONF configuration software To select Custom Operating Mode navigate to Settings gt Motor gt Motor Operating Mode then set the Operating Mode to Custom 1639507 12 2006 15 Introduction to Custom Logic Editor Presentation of the Custom Logic Editor Overview Purpose of the Custom Logic Editor A programmable controller reads inputs solves logic based on a control program and writes to outputs You can customize LTM R controller pre defined control programs using the custom logic editor The custom logic editor is a powerful programming tool that is only available in LTM CONF configuration utility
207. ment 2 expires This bit is cleared when e Argument 3 Bit 0 is cleared power is cycled Timing BOOL Argument 3 Bit 2 indicates that timing is ongoing This bit is cleared when Argument 2 expires EnableHistory BOOL Argument 3 Bit 3 Status of the Enable bit in the previous scan 1639507 12 2006 85 Structured Text Language TIMER_TENTHS The TIMER_TENTHS command e counts time in tenths of seconds up to the number of counts specified by a temporary register e calculates and tracks the time remaining in a 2nd temporary register e is enabled by and reports its counting status to a 3 temporary register Arguments Representation 3 TIMER_MS TmpReg TmpReg TmpReg Input arguments Argument Type Description TmpReg UINT Argument 1 the number of counts An integer from 0 to 65 535 Enable BOOL Argument 3 Bit 0 the rising edge of this bit starts the timer Output arguments EndTime UINT Argument 2 a calculation of the time remaining An integer from 0 to 65 535 TimedOut BOOL Argument 3 Bit 1 indicates that timing has stopped This bit is set when Argument 2 expires This bit is cleared when e Argument 3 Bit 0 is cleared e power is cycled Timing BOOL Argument 3 Bit 2 indicates that timing is ongoing This bit is cleared when Argument 2 expires EnableHistory BOOL Argument 3 Bit 3 status of the Enable bit in the previous scan
208. mer ory Process e tatus registers tus transition time value tus Low to High timer tus High to Low timer tus 704 Runl Run2 in Temp 2 TS HMI Debounce TS HMI in scratch LI6 Debounce LI6 in scratch PLC Control LI6 debounced TS HMI debounced HMI Control LI6 debounced TS HMI debounced TS Control 262 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Look for control transfer LOAD_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 0 0 save old Transfer in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD _NOT_TMP_BIT 1 2 Not equal SET_TMP_BIT 4 0 Transfer in Process Manage Bump Bumpless LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_TMP_ BIT 12 11 NOT Bumpless in Process AND_BIT 683 10 Bumpless SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfer in Process AND_NOT_BIT 683 10 Not bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfer in Process SET_TMP_BIT 12 7 Mode Change 1 SET_TMP_BIT 12 9 Mode Change 2 Save Active Control Mode in Temp Reg 3 LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC active AND_T SET LOAD NOT_TMP_BIT 4 0 not Transfer T HMI requested 2 rd w w G _TMP HMI Active
209. n 2 Run 2 Include partial Stop2 save final Stop2 236 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Runl and Run2 Commands he LOAD_TMP_BIT 12 1 OT_TMP_BIT 12 11 OT_TMP_BIT 4 6 AND_N AND_N SET_TMP BIT 12 LOAD_BIT 704 0 AND_TMP_BIT 12 SET_TMP BIT 12 0 12 1 AND_NOT_TMP_BIT 12 0 AND_TMP_BIT 3 OR_TM P BIT 4 8 SET_TMP BIT 4 0 8 LOAD_TMP_BIT 12 3 OT_TMP_BIT 12 11 OT_TMP_BIT 4 6 D_N D_N AERE DT ETT n zj zz D_T nO sa TMP BIT 12 AD TMP BIT 13 12 MP BIT 12 MP BIT 12 MP BIT 3 R_TMP BIT 4 8 TMP BIT 4 0 12 3 D_NOT_TMP_BIT 12 0 1 8 Generate Run 1 PLC mode Input history NOT Bumpless in Process NOT Stopl Save previous history PLC Network Runt Power up Done Save new history NOT previous history PLC active Include previous result save partial Runl HMI mode Input history NOT Bumpless in Process NOT Stopl Save previous history HMI Run1 Power up Done Save new history NOT previous history HMI active Include previous result save partial Runl 1639507 12 2006 237 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 12 5 BE E 4 P TMP BIN AD MP_BIN
210. n overflow if the result of the addition process exceeds 65 535 and e indicates the status of the bit accumulator from the previous scan Arguments Representation 2 ON_ADD TmpReg TmpReg Input arguments Argument Type Description Value UINT Argument 1 the amount to be added to the 16 bit accumulator An integer from 0 to 65 535 Output arguments Value UINT Argument 1 the result of the addition procedure An integer from 0 to 65 535 Overflow BOOL Argument 2 Bit 0 indicates that the addition operation resulted in a value greater than 65 535 In this event the true sum of the operation equals the value output to Argument 1 65 536 OnHistory BOOL Argument 2 Bit 3 Status of the bit accumulator in the previous scan 1639507 12 2006 93 Structured Text Language ON_SUB The ON_SUB command performs unsigned subtraction when the bit accumulator transitions from 0 to 1 It subtracts the 16 bit accumulator value from the value in Argument 1 then posts the result back to the value in Argument 1 A status register e indicates an underflow if the result of the subtraction process is less than 0 and e indicates the status of the bit accumulator from the previous scan Arguments Representation 2 ON_SUB TmpReg TmpReg Input arguments Argument Type Description Value UINT Argument 1 the amount from which
211. nction Block Diagram Language Inserting FBD Blocks At a Glance To create an FBD program you must insert blocks into the workspace then link them together All types of blocks can be placed in the workspace Inserting Blocks The following procedure describes how to insert a block from the toolbox into the workspace from the Toolbox Step Action 1 Select View gt Toolbox or left click on the toolbox tab in the upper left corner 2 Select the type of block to insert e Computation e Inputs e Function Blocks e Logic e Outputs Left click on the icon corresponding to the block to insert Drag and drop the block from the toolbox to the workspace Position the block in the required location on the workspace oO oO Repeat steps 2 to 5 to insert all the blocks required for the program Inserting Blocks The following procedure describes how to insert a block directly from the workspace Action Right click anywhere on a blank space in the workspace Result A menu opens and enables you to choose the type of block you wish to insert Select the type of block to insert e Computation e Inputs e Function Blocks e Logic e Outputs Left click on the block you wish to insert from the Ste Workspace E 1 2 4 Position the block in the required location in the workspace Repeat steps 1 to 5 to insert all the blocks required for th
212. ned value from 0 to 65 535 Outputs a Any non volatile register from 0 to 63 1639507 12 2006 135 Function Block Diagram Language Register Temp Bit Out Block Register Temp Word Out Block 1 The a block is used to set a temporary register bit value to 0 or 1 The following table describes the Register Temp Bit Out block characteristics FBD symbol Inputs outputs Description Temporary Inputs 0 or 1 ON 1 and OFF 0 Outputs a Any temporary register from 0 to 299 b Bit position from 0 to 15 Se The L P block is used to set a temporary register value The following table describes the Register Temp Word Out block characteristics FBD symbol Inputs outputs Description Write Temporary Inputs 16 bit unsigned value from 0 to 65 535 Outputs a Any temporary register from 0 to 299 136 1639507 12 2006 Function Block Diagram Language 3 3 Programming with the FBD Language At a Glance Summary This section describes how to create and modify a program using the FBD language What s in this This section contains the following topics ion Section Topic Page Inserting FBD Blocks 138 Creation of Links between Blocks 139 FBD Blocks Properties 141 FBD Resource Management 142 Compiling an FBD program 143 1639507 12 2006 137 Fu
213. nfiguration and customization process is displayed below LTM CONF PC LTM R Controller Compiles the configuration Configuration file LTM R communi Transfer p cation variables Editor p Compiles the Firmware Custom Logic logic file Editor p 10 pre defined operating modes i Structured Text Editor Control Program Graphical Editor Temporary registers 0 to 63 Non volatile registers 0 to 149 Logic memory 0 to 8192 Note If one of the pre defined operating modes is chosen in register 540 the PC transfers settings data to the LTM R controller addresses then the LTM R controller firmware loads the pre defined operating program from its ROM into the logic memory If the custom mode is selected the PC transfers settings data to the LTM R controller registers and the LTM R controller firmware Then the PC loads the control program from the logic file to the logic memory locations 14 1639507 12 2006 Introduction to Custom Logic Editor Operating Modes Overview Pre Defined Operating Modes Custom Operating Mode The LTM R controller supports 10 pre defined operating modes and 1 custom operating mode See the section Motor Control Functions in the TeSys T LTM R Motor Management Controller User s Manual Each pre defined operating mode is a list of com
214. o HMI Stop Key NOT Stop Load Shed Diag Fault 1 Diag Fault 2 Save partial Global Stop NOT PLC active NOT HMI active NOT TS active include partial Global Stop Save partial Global Stop NOT already on Rapid Cycle include partial Global Stop Save final Global Stop Latch comm loss values in scratch 0 LOAD_BIT 456 8 SET_TMP BIT 0 0 LOAD BIT 456 7 SET_TMP_BIT 0 1 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 250 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate Stop1 and Stop2 Commands Generate Stop1 LOAD_TMP_BIT 4 5 Global Stop OR_NOT_TMP_BIT 12 12 NOT Powerup Done SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 0 PLC Comm Loss from scratch AND_TMP_BIT 3 0 PLC active AND_NOT_TMP_BIT 4 1 NOT LO1 PLC fallback value OR_TMP_BIT 4 6 Include partial Stop1 SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 0 1 HMI Comm Loss from scratch AND_TMP_BIT 3 1 HMI active AND_NOT_TMP_ BIT 4 3 NOT LO1 HMI fallback value OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save partial Stopl LOAD_TMP_BIT 3 0 PLC active AND_NOT_BIT 704 0 NOT PLC Runt AND_TMP_BIT 4 8 Run 1 AND_NOT_TMP_BIT 0 0 NOT PLC Comm Loss from scratch OR_TMP_BIT 4 6 Include partial Stopl SET_TMP_BIT 4 6 save
215. o a cell the arguments and comments needed to complete the instruction You may prefer this method because it is more structured using the programming rules and may help you avoid common syntax errors 40 1639507 12 2006 Structured Text Language Example of a Program in Grid View The following illustration is an example of a program in Grid view ONF Defa Bik File Edit Link Settings Logic Functions Tools View Help LEERE FIJA EE emecaniaue 7 Tesys T Sy Device Information Untitled if 4 gt x HB Settings Mnemonics Argument 01 Argument 02 Argument 03 Description Ef Statistics LOGIC_ID 400 2 WIRE TWO STEP MODE 5 Monitoring LOAD_BIT 683 8 TS HMI HB Parameters _ SET_TMP_BIT 0 1 Debounce TS HMI in scratch f LOAD_BIT 516 5 LI6 Ex Custom Logic SET_TMP_BIT 0 0 Debounce LI6 in scratch E SET_TMP_BIT 2 0 PLC Control LS Function Blocks LOAD_NOT_TMP_BIT 0 0 LI6 debounced AND_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 1 HMI Control LOAD_NOT_TMP_BIT 0 o LI6 debounced AND_NOT_TMP_BIT 0 1 TS HMI debounced SET_TMP_BIT 2 2 TS Control LOAD_TMP_BIT 4 0 Transfert in Process l SET_TMP_BIT 0 0 save old Transfert in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD_NOT_TMP_BIT 1 2 Not equal O SET_TMP_BIT 4 0 Transfert in Process LOAD_TMP_BIT 4 0 Transfert in Process _ AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process
216. o access links display options click Tool in the top level menu bar 3 options are offered You can e Renumber links to aid in understanding the program s execution e Show all links to see which blocks are linked together e Hide all links to have a better overall view of the blocks When you click a link its Properties window opens and enables you to customize e the link color e the text that will appear next to the link The following procedure describes how to access and change Inputs Outputs display options Step Action 1 Position the mouse over a block Result One or more squares become visible on the block border It also indicates if the output is analog or boolean 2 Click on this square Result The display options appear 3 Choose if you want the label to be displayed and what text should appear 148 1639507 12 2006 Function Block Diagram Language Workspace Appearance and Graph Options Summary The FBD editor enables you to customize the workspace by changing its appearance and graph options Appearance and To access Appearance and Graph Options left click anywhere in the workspace Graph Options except on a object 1639507 12 2006 149 Function Block Diagram Language Appearance The following table lists all the possible appearance customization options Options Appearance Description Possible choices
217. of the Custom Logic Program p 24 code to ensure that an incomplete or corrupt logic function can be detected LTM CONF configuration software will not allow a logic file to be uploaded with a bad checksum however interrupting the connection during the upload will be detected by the checksum mechanism Once a custom logic file is uploaded to the LTM R controller that program may be selected by choosing Custom from the motor controller mode selection menu or by writing its logic ID see p 17 code to register 540 In the situation where a custom logic program is replaced by another one with a different logic ID code and the installed custom program is selected when the new program is uploaded the value in register 540 is automatically changed to the new logic ID code In cases when a standard motor controller mode is currently active i e Logic ID 2 through 11 the value in register 540 does not change If the custom logic program that is stored in memory has a bad checksum an invalid size or invalid logic ID or if there is no program stored in memory it is impossible to select Custom from the motor controller mode selection menu Writing a logic ID value to register 540 that does not match one of the pre defined operating modes or the logic ID of the valid checksummed custom logic program in memory is blocked by the LTM R controller If the custom logic program in memory is already selected and becomes corrupted eith
218. ol Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 190 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 3 Wire Overload Mode Overview The structured text program for the 3 wire overload mode is defined below Structured Text Program LOGIC_ID 3 3 WIR F OV ERLOAD MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode terminal strip 0 PLC 1 HMI 2 TS Temp 3 as Active Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value 5 Global Stop 6 Stop1 7 Stop2 8 Run1 9 Run2 Temp 5 as state bits group 2 Temp 12 as INPUT History 1 PLC Run 1 as 2 PLC Run 2 3 HMI Run 1 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 1639507 12 2006 191 Pre Defined Structured Text Programs Structured Text Program cont d 9 Mode Change 2 10 11 Bumpless in 12 Power up Don Temp 50 as general s Temp 50 as ONSET sta Temp 51 as ONSET sta Temp 52 a
219. or equals the non volatile register value e e e e bit 3 if the accumulator is greater than the non volatile register value Arguments Representation 2 COMP_NV_REG NVReg TmpReg Input arguments Argument Type Description NVReg UINT Argument 1 non volatile register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 Output arguments NA BOOL Argument 2 Bit 0 comparison of the register to the accumulator is invalid LT BOOL Argument 2 Bit 1 register lt accumulator EQ BOOL Argument 2 Bit 2 register accumulator GT BOOL Argument 2 Bit 3 register gt accumulator 74 1639507 12 2006 Structured Text Language AND_K The AND_K command makes a logical AND link between a 16 bit constant value and the accumulator content in logic memory The AND process compares each bit in the 16 bit accumulator with the corresponding bit in the linked 16 bit constant If both bits equal 1 the result of the AND process for that bit location is also 1 in all other cases the result of the AND process for that bit location is 0 The result is saved in the 16 bit accumulator Arguments Representation 1 AND_K KValue Input arguments Argument Type Description KValue UINT A constant value from 0 to 65 535 Output arguments
220. or multiple thresholds Volatile Latch Block l fe Characteristics The function records and retains signal history in a temporary register The following table describes the Volatile Latch block characteristics FBD symbol Inputs outputs Description Inputs Set ON OFF input value The latch value is set ON when this input transitions from OFF to ON Set Clear ON OFF input value The latch value is set OFF when this input transitions from OFF to ON Outputs Q ON or OFF latch value which represents the state of this latch This value remains ON OFF until the next rising edge of Set or Clear This value is initialized to OFF 130 1639507 12 2006 Function Block Diagram Language Non Volatile Latch Block Characteristics Mux Block Characteristics The IF function records and retains signal history in a non volatile register The following table describes the Non Volatile Latch block characteristics FBD symbol Inputs outputs Description Inputs Set ON OFF input value The latch value is set ON when this input transitions from OFF to ON Clear ON OFF input value The latch value is set OFF when this input transitions from OFF to ON Outputs Q ON or OFF non volatile register bit value that represents the state of this latch This value remains ON OFF until the next rising edge of Set or Clear This value is saved in non
221. oring LOAD_BIT 516 5 UI SET_TMP_BIT 0 0 debounce LI6 in scratch 6 Parameters SET_T P BIT 2 0 PLC Control H LOAD_NOT_TMP BIT 0 0 lad LI6 debounced El Custom Logic AND_TEP_BIT 0 1 TS HMI debounced i SET_TMP_BIT 2 1 HMI Control Structured Text LOAD_NOT_TMP BIT 0 0 _ LI6 debounced 7 AND_NOT_TMP_BIT 0 1 TS HMI debounced Function Blocks SET_TMP_BIT 2 2 TS Control LOAD_TMP_BIT 4 0 Transfert in Process SET_TMP_BIT 0 0 save old Transfert in Process LOAD_TMP_REG 2 Requested Mode COMP_TMP_REG 3 1 is it Active Mode LOAD_NOT_TMP BIT 1 2 Not egual SET_TMP_BIT 4 0 Transfert in Process LOAD_TMP_BIT 4 0 Transfert in Process AND_NOT_TMP_BIT 12 11 NOT Bumpless in Process AND_BIT 683 10 1 Bumpless SET_TMP_BIT 12 11 Bumpless in Process one scan LOAD_TMP_BIT 4 0 Transfert in Process AND_NOT_BIT 683 10 Not Bumpless AND_NOT_TMP_BIT 0 0 Look for Edge SET_TMP_BIT 4 0 Transfert in Process OR_TMP_BIT 12 8 Mode Wait 1 SET_TMP_BIT 12 7 Mode Change 1 LOAD_TMP_BIT 4 0 Transfert in Process OR_TMP_BIT 12 10 Mode Wait 2 SET_TMP_BIT 12 9 Mode Change 2 LOAD_NOT_TMP BIT 4 0 not Transfert in Process AND_TMP_BIT 2 0 PLC requested SET_TMP_BIT 3 0 PLC active LOAD_NOT_TMP_BIT 4 0 not Transfert in Process AND_TMP_BIT 2 1 HMI requested SET_TMP_BIT 3 1 HMI active LOAD_NOT_TMP_BIT 4 0 not Transfert in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active LOAD_REG 682 PLC fallba
222. ors Correct syntax errors if present y modification Saving and Compilation Compile the custom logic program to validate the S y Validation Use the custom logic simulator to validate the new program y Transfer Transfer the new program into the LTM R controller 22 1639507 12 2006 Introduction to Custom Logic Editor Firmware s Task The following diagram shows all of the tasks that the firmware will carry out once the Flow Diagram custom logic program has been downloaded Configuration Registers Reading The firmware reads configuration registers with predefined logic program selection y Registers Access The firmware loads the control program into the LTM R controller logic memory registers y Custom logic Registers Configuration Firmware configures non volatile and temporary registers for use with the control program y Exiting program LTM R controller exits system configuration state y Ready State The LTM R controller firmware is configured to perform primary protection monitoring and control functions 1639507 12 2006 23 Introduction to Custom Logic Editor Characteristics of the Custom Logic Program Introduction Logic Memory Characteristics Data transfered to or from the LTM R controller is in the form of 16 bit registers The registers are numerically ordered and referenced by a 16
223. peed Mode Overview The structured text program for the 2 wire 2 speed mode is defined below Structured Text Program LOGIC_ID 10 2 WIRE TWO SPEED MODE Temp register allocation Temp 0 and Temp 1 as scratch Temp 2 as Requested Control Mode 0 PLC 1 HMI 2 TS terminal strip Temp 3 as Active Control Mode 0 PLC 1 HMT 2 TS terminal strip Temp 4 as state bits group 1 0 Control Transfer in process 1 LO1 PLC fallback value 2 L02 PLC fallback value 3 L01 HMI fallback value 4 L02 HMI fallback value 5 Global Stop 6 Stop1 7 Stop2 8 Run1 9 Run2 10 Low Speed 11 High Speed 12 Lockout Timer Active Temp 5 as state bits group 2 Temp 9 10 11 as Speed change timer Temp 12 as INPUT History 1 PLC Run 1 2 PLC Run 2 3 HMI Run 1 1639507 12 2006 285 Pre Defined Structured Text Programs Structured Text Program cont d Lh 4 HMI Run 2 5 TS Run 1 6 TS Run 2 7 Mode Change 1 8 9 Mode Change 2 10 11 Bumpless in 12 Power up Don Temp 50 as general s Temp 50 as ONSET sta Temp 51 as ONSET sta Temp 52 as ONSET sta Temp 53 Latch Temp 54 as ONSET sta Save Requested Control LOAD_BIT 683 8 SET_TMP_BIT 0 1 OAD_BIT 457 5 T TMP BIT 0 0 ET TMP BIT 2 0 LOAD_NOT_TMP_BIT 0 0 AND_TMP_BIT 0 1 SET_TMP_
224. pless in process T 12 7 Bump LO1 in process T 12 9 Bump LO2 in process Manage Communications Loss Fallback Values Inputs Outputs Address Description Address Description R682 PLC Fallback T4 1 PLC FB LO1 Settings T4 3 PLC FB LO2 R645 HMI FB Settings T 4 2 HMI FB LO1 T4 4 HMI FB LO2 1639507 12 2006 175 Programming Approach Latch HMI Keypad input Inputs Outputs Address Description Address Description 1020 14 HMI Run 1 T 13 12 HMI Run 1 1020 12 HMI Run 2 T 13 13 HMI Run 2 1020 13 HMI STOP T 13 14 HMI STOP Manage Global Stop Inputs Outputs Address Description Address Description T 13 14 HMI STOP T4 5 Global STOP 456 5 Load Shed Generate Stop1 Commands Inputs Outputs Address Description Address Description T4 5 Global Stop T 4 6 STOP 1 453 1 Diag 1 453 2 Diag 2 456 4 RC Timer 456 8 PLC Loss 457 6 HMI Loss T 4 1 PLC FB STOP T4 3 HMI FB STOP 1200 12 Logic Stop Generate Stop2 Commands Inputs Outputs Address Description Address Description T4 5 Global Stop T 4 7 STOP 1 456 8 PLC Loss 457 6 HMI Loss T4 2 PLC FB STOP T 4 4 HMI FB STOP 1639507 12 2006 Programming Approach Generate Run1
225. r content The result is stored in the 16 bit Boolean accumulator OR_K Constant value Makes a logical OR link between the 0 to 65 535 constant value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_REG Register address Makes a logical OR link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_TMP_REG Temporary Makes a logical OR link between the register address temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator OR_NV_REG Non volatile Makes a logical exclusive OR link between register address the non volatile register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator XOR_K Constant value Makes a logical exclusive OR link between 0 to 65 535 the constant value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator XOR_REG Register address Makes a logical exclusive OR link between the register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator XOR_TMP_REG Temporary Makes a logical exclusive OR link between register address the temporary register value and the 16 bit accumulator content The result is stored in the 16 bit Boolean accumulator Argument not applicable to logic command 16395
226. rce e logic processing by the control or monitoring function e utilization of the processing results e activation of logic outputs e activation of LEDs e telecommunication signals TS sent via a communications link The control and monitoring function process is displayed below Predefined Control Monitoring Functions TS Logic Inputs me TC l o gt Protection Functions p i TC w Custom Logic Equations TS LTM R Logic Functions OutputCommands System Status HMI commands I O Control Logic Logic Outputs A Signal LEDs Note Custom logic equations in the diagram above correspond to the control program which is loaded into the LTM R controller s logic memory 1639507 12 2006 13 Introduction to Custom Logic Editor Logic Control Program Actors The LTM R controller provides 6 logic inputs 2 logic outputs 1 warning relay and 1 fault relay By adding an expansion module you can add 4 more logic inputs Selecting a pre defined operating mode automatically assigns the logic inputs to functions and defines the relationship between logic inputs and outputs Using the custom logic editor you can change these assignments Using LTM CONF configuration utility you have to configure parameters and edit the program file The co
227. rce history bit off Timer Value NOT Runt Stop 1 Forward save partial result in scratch NOT Run2 Stop 2 Reverse include partial result save partial result in scratch NOT Forward NOT Reverse already timing include partial result NOT Power up Done Enable Timer Process forward reverse timer flag Enabled timing Reversing Timer Active 1639507 12 2006 241 Pre Defined Structured Text Programs Structured Text Program cont d Manage Forward and Reverse status bits LOAD_NOT_TMP BIT 4 12 OR_TMP_BIT 52 0 AND_TMP_BIT 4 8 AND_NOT_TMP BIT 4 6 AND_NOT_TMP BIT 4 11 SET_TMP_BIT 4 10 SET_TMP_BIT 52 1 LOAD _NOT_TMP_BIT 4 12 OR_NOT_TMP BIT 52 0 AND_TMP_BIT 4 9 AND_NOT_TMP BIT 4 7 AND_NOT_TMP BIT 4 10 SET_TMP BIT 4 11 SET_TMP_BIT 52 2 LATCH 52 NOT Reversing Timer Active Last direction forward Run1 NOT Stop1 NOT Reverse save Forward set last direction forward NOT Reversing Timer Active NOT last direction forward Run2 NOT Stop2 NOT Forward save Reverse set last direction reverse last direction latch 242 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program contd Set Outputs to IMPR LOAD_TMP_BIT 4 10 SET_BIT 1200 12 SET_BIT 1200 9 LOAD_TMP_BIT 4 11 SET_BIT 1200 13 SET_BIT 120
228. rguments Representation 1 XOR_REG RegAddr Input arguments Argument Type Description RegAddr UINT The register address any valid LTM R register Output arguments 80 1639507 12 2006 Structured Text Language XOR_TMP_REG The XOR_TMP_REG command makes a logical exclusive OR link between the temporary register value and the accumulator content in logic memory The result is saved in the 16 bit accumulator The XOR process compares each bit in the 16 bit accumulator with the corresponding bit in the linked temporary register and yields these results When 2 bits are compared if one bit equals 1 and the other equals 0 the result of the XOR process is 1 in all other cases the result of the XOR process is 0 When more than 2 bits are compared if there is an odd number of 1 states the result of the XOR process is 1 if there is an even number of 1 states the result of the XOR process is 0 Arguments Representation 1 XOR_TMP_REG TmpReg Input arguments Argument Type Description TmpReg UINT The temporary register number an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 Output arguments 1639507 12 2006 81 Structured Text Language XOR_
229. riate transition timers have elapsed before allowing a SWAP a command from LO1 to LO2 These comments are shown in the 3 wire independent operating mode PCode to help you to locate where in the other programs you should use these temporary addresses in the event you would like to use the Pcode from those programs in a similar manner within the 3 wire independent operating mode 172 1639507 12 2006 Programming Approach 3 Wire Independent Operating Mode Program Sections Overview Program Sections The 3 wire independent operating mode is made up of 9 sections Each section of the program enables the LTM R controller to perform an action or to define a specific function The function of each section is described below Manage Requested and Active Control Source Detect Local Remote settings and save Requested Control Source in Temp Reg 2 Detect if Request NOT equal Active source Save Transfer in Process Temp 4 0 Save Active Control Source in Temp Reg 3 Manage Bump Bumpless transfers Save active transfers as bumpless transfer in process in Temp Reg 12 11 Detect Bump config Save bump transfer in process in Temp Reg 12 7 Temp Reg 12 9 Manage Communications Loss Fallback Values Save PLC Fallback Settings for LO1 and LO2 in Temp Reg 4 1 and 4 2 Save HMI Fallback Settings for LO1 and LO2 in Temp Reg 4 3 and 4 4 Latch HMI Keypad input Latch HMI Aux1 Aux2 and Stop Inputs into in Temp Reg
230. rogram by designing the step instructions tailored to the specific requirements of the application What s in this This section contains the following topics Section Topic Page Introducing the Structured Text Editor 31 Structured Text Editor User Interfaces 33 Text View 36 Grid View 40 Logic Commands 43 30 1639507 12 2006 Structured Text Language Introducing the Structured Text Editor Overview Editing a Structured Text Program How to Edit a Structured Text Program The structured text editor is a feature of TeSys configuration software Use the structured text editor to view an existing logic file or to create a new logic file using a instruction based text language rather than a graphics based programming language The easiest way to create a new logic file is to begin with a logic file for one of the the pre defined operating modes Your installation of the custom logic editor comes with 10 pre defined logic files one for each combination of e operating mode 2 speed 2 step independent overload reverser and e control wiring selection 2 wire 3 wire Each logic file bears a descriptive name e g 3 wire reverser and a file extension of If Follow these steps to create a structured text program from a pre defined operating mode program Step Action 1 Navigate to Settings gt Motor Motor Operating Mode to use the logic editor in the configuration software Set
231. rs 1200 and 458 See part 2 on the illustration above The LTM R controller firmware then reads those PCode register values to direct device functions and physical outputs For more information about those registers see the sections on Communication Variables in the Use chapter of the Motor Management Controller TeSys T LTM R User s Manual The logic simulator displays an X in each output status checkbox to indicate that a bit value of 1 exists in the output status register 1639507 12 2006 113 Structured Text Language Register 457 Writing toa Register address Start a Trace Refresh The logic simulator enables to write values to register 457 bits see part 3 on the illustration above For more information about this register see the sections on Communication Variables in the Use chapter of the Motor Management Controller TeSys T LTM R User s Manual To be allowed to write to register 457 tick the Enable Inputs box Ticking a box on the left of a register bit will assign a value of 1 to this bit Untick this box to assign 0 to this bit Example If you tick the 3 first boxes bits 457 0 457 1 and 457 2 will get the value of 1 Click on the upper refresh button and then check the value of register 457 You can see that it has the value of 7 which is in binary code 0000000000000111 The logic simulator enables to write data to any register address see part 4 on the illustration above Follow
232. rsing Timer SET_BIT 1200 4 Transition Timer Process other outputs LOAD_BIT 455 3 IMPR Alarm status SET_BIT 1200 14 Output 3 Alarm LOAD_BIT 455 2 IMPR Fault status SET_NOT_BIT 1200 15 Output 4 Fault LOAD_BIT 457 4 Reset Input LI5 SET_BIT 1200 2 Logic Reset LOAD_TMP_BIT 3 0 PLC active SET_BIT 1200 6 Logic Local Remote LOAD_TMP_BIT 4 6 Stop 1 OR_TMP_BIT 4 7 Stop 2 OR_TMP_BIT 4 12 Lockout Timer Active SET_BIT 1200 11 Stop LED Manage Power UP Done LOAD_NOT_TMP_BIT 4 12 Wait for power up timer OR_TMP_BIT 12 12 Latch ON until next power up SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 1639507 12 2006 315 Pre Defined Structured Text Programs 316 1639507 12 2006 Glossary A Accumulator Internal register which is used to store the last logic command result There are 2 different accumulators the 16 bit accumulator and the 1 bit accumulator Argument A number or an address representing a value that a program can manipulate in a logic command Cc Comments Comments are texts you enter to document the purpose of a program For List Custom logic register programs enter text on
233. ry TIMER_TENTHS Temporary register time period Temporary register calculated end time Temporary register status Counts in tenths of seconds the time period input in Arg1 as described by status register bits O0 Enable 1 Timed Out 2 Timing 3 Enable History TIMER_K_SEC Constant value 0 to 65 535 time period Temporary register calculated end time Temporary register status Counts in seconds the time period input in Arg1 as described by status register bits O0 Enable 1 Timed Out 2 Timing 3 Enable History TIMER_K_TENTHS Constant value 0 to 65535 time period Temporary register calculated end time Temporary register status Counts in tenths of seconds the time period input in Arg1 as described by status register bits O0 Enable 1 Timed Out 2 Timing 3 Enable History 50 1639507 12 2006 Structured Text Language Latch logic Latch commands include commands Command Argument 1 Argument 2 Argument 3 Description LATCH Temporary register Records and retains in a status temporary register a history of a signal Status bits 0 State 1 Set 2 Clear 3 Set History 4 Clear History LATCH_NV Non volatile Records and retains in a non register status volatile register a history of a signal Status bits 0 State 1 Set 2 Clear 3 Set History 4 Clear History Argument not applicable
234. s Blocks Function Symbol in Symbol in the Description the Toolbox workspace AND QUAND If all the inputs ON or OFF values respectively 1 or 0 are A active ON or not connected the output is active AND B B Oui If at least one input is inactive the output is inactive z AND Note unconnected inputs are assumed to be ON NOT nor If the input ON or OFF values respectively 1 or 0 is ON the output is OFF NOT a ido it If the input is OFF the output is ON NOT V OR ER If at least one input ON or OFF values respectively 1 or 0 is A ON the output is ON OR B If all the inputs are OFF or not connected the output is OFF c Out x OR Note unconnected inputs are assumed to be OFF 1639507 12 2006 133 Function Block Diagram Language Outputs Blocks Overview Access Register Bit Out Block The FBD editor uses various Outputs blocks Register Bit Out Register Word Out Register NV Bit Out Register NV Word Out Register Temp Bit Out Register Temp Word Out To access Outputs blocks click on the Outputs bar in the Toolbox This menu is then displayed in the Toolbox 1 41 fel fel 1 fo LTMR NV NV LTMR Tmp Tmp 1 The E block is used to set an LTM R controller register bit value to O or 1 from the LTM R controller R W addresses 0 to 1399 The following table describes the Register Bit Out block characteristics FBD symbol Inputs outputs Descrip
235. s ONSET sta Temp 53 Latch Temp 54 as ONSET sta Save Requested Control LOAD_BIT 683 8 ET_TMP_BIT 0 1 OAD_BIT 457 5 m PM P_BIT 0 7 0 T TM P_ BIT 2 i 0 LOAD_NOT_TMP_BIT 0 0 AND_TMP_BIT 0 1 ET_ BER 221 LOAD_NOT_TMP_BIT 0 0 AND_NOT_TMP_BIT 0 1 SET_TMP_BIT 2 2 n E n d 3 z J ed U Look for control trans LOAD_TMP_BIT 4 0 LOAD_TMP_RE COMP_TMP_REG 3 1 LOAD_NOT_TMP BIT 1 2 SET_TMP BIT 4 0 Process e tatus registers tus transition time value tus Low to High timer tus High to Low timer tus 704 Runi Run2 in Temp 2 TS HMI Debounce TS HMI in scratch LI6 Debounce LI6 in scratch PLC Control LI6 debounced TS HMI debounced HMI Control LI6 debounced TS HMI debounced TS Control fer Transfer in Process save old Transfer in Process Requested Mode is it Active Mode Not equal Transfer in Process 192 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Manage Bump Bumpless LOAD_TMP_BIT 4 0 AND_NOT_TMP_BIT 12 11 SET_TMP_BI1 M LLL LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT S S w a 3 _TMP_BIT 4 0 _TMP_BIT 0 0 TMP BIT 12 7 z S _TMP_BIT 12 9 Transfer in Process NOT Bumpless in Process Bumpless in Process one scan Transfer in Process
236. s in detail the FBD elements provided by the FBD editor and their inputs outputs What s in this This section contains the following topics Section Topic Page Computation Blocks 122 Inputs Blocks 125 Function Blocks 128 Logic Blocks 133 Outputs Blocks 134 1639507 12 2006 121 Function Block Diagram Language Computation Blocks Overview The FBD editor uses various Computation blocks e Compare e Add e Division e Multiplication e Substraction Access To access computation blocks click on the Computation bar in the Toolbox This is then displayed in the Toolbox 2 H k Compare Block Characteristics gt The lt block compares two 16 bit register values The following table describes the Compare block characteristics FBD symbol Inputs outputs Description Inputs X 16 bit unsigned register value 0 to 65 535 Y 16 bit unsigned register value 0 to 65 535 Outputs X lt Y ON OFF 0 or 1 temporary bit that is ON if the value X is less than the value Y X Y ON OFF 0 or 1 temporary bit that is ON if the value X is equal to the value Y X gt Y ON OFF 0 or 1 temporary bit that is ON if the value X is greater than the value Y 122 1639507 12 2006 Function Block Diagram Language Add Block Characteristics Subtraction Block Characteristics The block performs an unsigned addition of two
237. s saved in the 1 bit accumulator Arguments Representation 2 AND_NOT_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments 1639507 12 2006 61 Structured Text Language AND_NOT_NV_BIT OR_BIT The AND_NOT_NV_BIT command e inverts the Boolean value 0 or 1 of a selected non volatile register bit then e makes a logical AND link between it and the accumulator content in logic memory If the bit accumulator equals 1 and the linked non volatile register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 AND_NOT_1 V_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments The OR_BIT command makes a logical OR link between a register bit value and the
238. s that a connection is not possible The type of output analog or boolean is also indicated Write Temporary Note Inputs and outputs have to be of the same type a boolean output is linked to another boolean output If the inputs or outputs are not the same the FBD editor will display a pop up window to indicate that origins and destinations are not of the same type 4 Release the mouse button Result A line and a number are shown between the two linked blocks 5 Repeat steps 1 to 4 to link all the blocks Link Number There are 2 types of wires e The boolean wire which will have a number beginning with B e The register wire which will have a number beginning with R The wire number is automatically incremented in chronological order 140 1639507 12 2006 Function Block Diagram Language FBD Blocks Properties Ata Glance Comments Settings Properties Display Each of the blocks has a properties window To display this window left click on a block The Properties window consists of several tabs separated in one or two categories depending on the type of block e General settings which contain the block ID and comments common to all types of blocks e Specific settings depending on the type of block register settings for registers counter settings for counters etc For example if you wish to display a non volatile register properties choose a non volatile register block and left click on
239. s the parameter for custom logic temporary space TheLTM R controller provides registers in non volatile memory for use by logic commands Because these registers exist in non volatile memory they retain their value settings when power to the controller is cycled Variables can be stored in non volatile registers from 0 to 63 Thus 64 non volatile registers are available The LTM R controller defines each custom logic register by an integer describing its address in custom logic memory space The value of this integer begins at address 0 and the maximum address is equal to 1 less than the number of memory locations available for non volatile registers in the LTM R controller The LTM R controller lists the number of non volatile registers available as a value in the LTM R control register 1205 which is the parameter for custom logic non volatile space Registers 1301 to 1399 are the General Purpose Registers for logic functions They are used to exchange information between external sources such as the PLC and the custom logic applications These registers are read write and can be edited either by the custom logic functions or via the communication port 1639507 12 2006 25 Introduction to Custom Logic Editor Definition of the LTM R Variables Overview LTM R Variables Accessing Variables Custom Logic Registers Custom logic commands can be used to change the values of read write data registers of
240. stom Logic Editor File Transfer LTM R Controller to PC To transfer logic files from the LTM R controller to the custom logic editor Step Action 1 Ensure that the LTM R controller is connected to the PC See p 157 2 nE Select Logic Functions Upload Program from Device or click the icon to transfer the logic file from the LTM R controller to the custom logic editor LTM CONF Default Fie Edit Link Settings Tools View Help Biel B25 SF B Nen Looi Tie i Device Information Untitled1 H Save Logic File f Settings 1 Save Logic File As AIRE TWO STEP MODE Ha ravi t B Statistics ae oe Lede Fi ers fied AEN H6 Monitoring 5o 7 eee acon H5 Parameters s EA Compile trol R 7 W 5 debounced ae Custom Logic a Download Program to Device iese SEEE Upload Program from Device LI6 debounced H a AN YHMI debounced Function Blocks 12 set INP BIT 2 2 FP TS Control 13 LOAD_TMP_BIT 4 0 Mt Transfer in Process 14 SET_TMP_BIT 0 0 Pati save old Transfer in Process 3 When the logic file has been transferred you can use custom logic editor to change configuration settings 4 After your logic file edits are complete save your work to a file Select the Save command in either the icon bar or the File menu navigate to the desired location and click Save 158 1639507 12 2006 Connection to the LTM R Controller Saving Files Save a copy of any
241. structured text program file into a FBD file Follow these steps in order to compile the structured text program just created into Pcode Step Action 1 Minimize the FBD editor window and navigate in the configuration software tree on the left of the screen in LTM CONF configuration software to Custom Logic Structured Text Result The program is automatically copied into the structured text editor and has a glf extension Compile this program by clicking Compilein the Logic Functions menu Refer to Compiling of a structured text see Compiling and Simulation of a Structured Text Language Program p 102 program section in this manual for further information about compiling simulation errors check etc 1639507 12 2006 143 Function Block Diagram Language 3 4 Manipulating FBD Blocks At a Glance Summary This section describes the manner in which blocks in the workspace can be manipulated including how to select move duplicate or delete blocks What s in this This section contains the following topics Section Topic Page How to Select Blocks 145 How to Delete and Duplicate Objects 146 144 1639507 12 2006 Function Block Diagram Language How to Select Blocks At a Glance How to Select One or More Blocks When you add blocks to the workspace you can select them to reposition them within the workspace The follo
242. t 2 LOAD_TMP_BIT 5 4 Step 2 S NOT Stop tate 1 AND_NOT_TMP_BIT 4 6 SET_BIT 1200 13 SET_BIT 1200 10 SET_BIT 1200 3 LOAD_TMP_BIT 5 OR_TMP_BIT 5 2 OR_TMP_BIT 5 4 SET_BIT 1200 0 s s T_NOT_BIT 1200 1 T_NOT_BIT 1200 11 LOAD_TMP_BIT 4 12 SET_BIT 1200 4 Output 2 Aux 2 LED In Step 2 Process Motor Run Stop Output 1 State Step 1 State Step 2 State Motor Run Motor Stop Stop LED Reversing Timer Transition Timer 1639507 12 2006 283 Pre Defined Structured Text Programs Structured Text Program cont d Process other outputs LOAD_BIT 455 3 IMPR Alarm status SET_BIT 1200 14 Output 3 Alarm LOAD_BIT 455 2 IMPR Fault status SET_NOT_BIT 1200 15 Outpur 4 Fault LOAD_BIT 457 4 Reset Input LI5 SET_BIT 1200 2 Logic Reset LOAD_TMP_BIT 3 0 PLC active SET_BIT 1200 6 Logic Local Remote Manage Power UP Done LOAD_NOT_TMP_BIT 4 12 Wait for power up timer OR_TMP_BIT 12 12 Latch ON until next power up SET_TMP_BIT 12 12 Power up Done Clear PLC Control on Control Transfer LOAD_TMP_BIT 4 0 Control Source Transfer AND_NOT_BIT 683 10 NOT Bumpless LOAD_K_REG 65532 OXFFFC AND_REG 704 mask off Runl and Run2 ON_SET_REG 704 54 Run bits on Bump Control Change 284 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program for 2 Wire 2 S
243. t 2 accumulator register GT BOOL Argument 2 Bit 3 accumulator gt register 72 1639507 12 2006 Structured Text Language COMP_TMP_REG The COMP_TMP_REG command compares the accumulator content to the value of the Argument 1 temporary register and sets one of the following bits in a temporary register bit O not used bit 1 if the accumulator is less than the temporary register value bit 2 if the accumulator equals the temporary register value bit 3 if the accumulator is greater than the temporary register value Arguments Representation 2 COMP_TMP_REG TmpReg TmpReg Input arguments Argument Type Description TmpReg UINT Argument 1 temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 Output arguments LT BOOL Argument 2 Bit 1 accumulator lt temporary register EQ BOOL Argument 2 Bit 2 accumulator temporary register GT BOOL Argument 2 Bit 3 accumulator gt temporary register 1639507 12 2006 73 Structured Text Language COMP_NV_REG The COMP_NV_REG command compares the accumulator content to the value of the Argument 1 non volatile register and sets one of the following bits in a temporary register bit O not used bit 1 if the accumulator is less than the non volatile register value bit 2 if the accumulat
244. t Boolean accumulator AND_NOT_BIT Register Register bit Loads the result of a logical AND of the inverted address no 0 15 register bit and the 1 Bit Boolean Accumulator The result is stored in the 1 bit Boolean accumulator AND_NOT_TMP_BIT Temporary Register bit Loads the result of a logical AND of the inverted register no 0 15 temporary register bit and the 1 Bit Boolean address Accumulator The result is stored in the 1 bit Boolean accumulator Argument not applicable to logic command 44 1639507 12 2006 Structured Text Language Command Argument 1 Argument 2 Argument 3 Description AND_NOT_NV_BIT Non volatile Register bit Loads the result of a logical AND of the inverted register no 0 15 non volatile register bit and the 1 Bit Boolean address Accumulator The result is stored in the 1 bit Boolean accumulator OR_BIT Register Register bit Makes a logical OR link between the register bit value address no 0 15 and the accumulator content The result is stored in the 1 bit Boolean accumulator OR_TMP_BIT Temporary Register bit Makes a logical OR link between the temporary register no 0 15 register bit value and the accumulator content The address result is stored in the 1 bit Boolean accumulator OR_NV_BIT Non volatile Register bit Makes a logical OR link between the non volatile register no 0 15 register bi
245. t ee Gea eta wie we 121 FBD Elements Overview 000 cece cee ee 121 Computation BlockS 1 2 2 0 0c c cette eee 122 Inputs BIOCKS Seti eh eee ee a ie 125 Function BIOCKS i searen 2 af ake le ep Babes a pha a alr ek ee 128 Logie Blocks s mra ao a dd id Bo Eg a ee Ae ee he oD 133 Outputs Blocks i ree season cans pees ete Gad ea aaa en ton a 134 Programming with the FBD Language 0s eee eee eee eee 137 Inserting FBD Blocks 0 cee eens 138 Creation of Links between Blocks 00000 cece teeta 139 FBD Blocks PropertieS 0 0 c cece ttt 141 FBD Resource Management 0 2 0c ee eee eee 142 Compiling an FBD program 1 eee 143 Manipulating FBD Blocks 0 0 eee eee 144 How to Select BlockS 1 2 0 0 cette eee 145 How to Delete and Duplicate Objects 0 cece ee 146 FBD Editor Display Options 00 0 c eee eee 147 Other Display Options 2 0 00 c eect eee 148 Workspace Appearance and Graph Options 0 0 e ee ee aes 149 Connection to the LTM R Controller 153 Hardware Connection 0 00 e cette teens 154 Initialization and Connection u sssaaa aaaeeeaa 156 Transferring Logic Files between the LTM R Controller and Custom Logic Editor 158 Custom Logic Program Transfer and Execution ssassn anaana 162 Appendices Appendix A Appendix B Glossary Index
246. t location an integer from 0 to 15 Output arguments 1639507 12 2006 59 Structured Text Language AND_TMP_BIT AND_NV_BIT The AND_TMP_BIT command makes a logical AND link between a temporary register bit value and the accumulator content in logic memory If the bit accumulator equals 1 and the linked temporary register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 AND_TMP_BIT TmpReg BitNo Input arguments Argument Type Description TmpReg UINT The temporary register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments The AND_NV_BIT command makes a logical AND link between a non volatile register bit value and the accumulator content in logic memory If the bit accumulator equals 1 and the linked non volatile register bit equals 1 the result of the AND process is also 1 in all other cases the result of the AND process is 0 The result is saved in the 1 bit accumulator Arguments Representation 2 AND_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg U
247. t value and the accumulator content The address result is stored in the 1 bit Boolean accumulator OR_NOT_BIT Register Register bit Makes an logical OR of the inverted register bit address no 0 15 and the 1 Bit Boolean accumulator The result is stored in the 1 bit Boolean accumulator OR_NOT_TMP_BIT Temporary Register bit Makes an logical OR of the inverted temporary register no 0 15 register bit and the 1 Bit Boolean accumulator The address result is stored in the 1 bit Boolean accumulator OR_NOT_NV_BIT Non volatile Register bit Makes an logical OR of the inverted non volatile register no 0 15 register bit and the 1 Bit Boolean accumulator The address result is stored in the 1 bit Boolean accumulator SET_BIT Register Register bit Sets value of the 1 bit Boolean accumulator into address no 0 15 a register bit SET_TMP_BIT Temporary Register bit Sets value of the 1 bit Boolean accumulator into a register no 0 15 temporary register bit address SET_NV_BIT Non volatile Register bit Sets value of the 1 bit Boolean accumulator into a non register no 0 15 volatile register bit address SET_NOT_BIT Register Register bit Sets inverted value of the 1 bit Boolean accumulator address no 0 15 into a register bit SET_NOT_TMP_BIT Temporary Register bit Sets inverted value of the 1 bit Boolean register no 0 15 accumulator into a temporary register bit address SET_NOT_NV_BIT Non volatile
248. t will occupy as many memory locations as there are arguments The command timer 0 1 980 will occupy 4 memory locations The control program the temporary registers and the non volatile registers are stored in different areas of the internal memory of the LTM R controller 24 1639507 12 2006 Introduction to Custom Logic Editor Definition of the Custom Logic Variables Introduction Temporary Registers Non Volatile Registers Registers 1301 to 1399 The custom logic editor enables you to implement commands in the control program which direct the LTM R controller to read or write to the temporary or non volatile or control program registers The controller provides registers in temporary memory that can be accessed by logic commands Because these registers exist in temporary or volatile memory they do not retain their value settings when power to the controller is cycled Variables can be stored in temporary registers from 0 to 299 Thus 300 temporary registers are available The LTM R controller defines each custom logic register by an integer describing its address in custom logic memory space The value of this integer begins at address 0 and the maximum address is equal to 1 less than the number of memory locations available for temporary registers in the LTM R controller The LTM R controller lists the number of temporary registers available as a value in the LTM R control register 1204 which i
249. ted to the controller When a logic file is open and the configuration software is connected to the controller the structured text editor and logic functions menu look like this LTM CONF Default Settings Tools File Edit Link PEA oe s2 82 New Logic File View Help Telemecanique Tey Ema i Open Logic File 1 4 Device Information Untitled1 Save Logic File wi Settings 2 Save Logic File As HE Statistics sz x Close Logic File LO NIRE TWO STEP MODE HMI e TS HMI in scratch b HB Monitoring H Parameters SE s Compile e LI6 in scratch trol Le gt Custom Logic amp amp Download Program to Device Structured Text uc Upload Program from Device an 5 debounced debounced trol LI6 debounced HMI debounced Function Blocks SET TMP BIT 2 2 LOAD_TMP_BIT 4 0 SET_TMP_BIT 0 0 LOAD_TMP_REG 2 COMP_TMP_REG 3 1 LOAD_NOT_TMP BIT 1 2 SET_TMP_BIT 4 0 LOAD_TMP BIT 4 0 AND_NOT_TMP_BIT 12 11 AND_BIT 683 10 1 SET_TMP_BIT 12 11 LOAD_TMP_BIT 4 0 AND_NOT_BIT 683 10 AND_NOT_TMP_BIT 0 0 SET_TMP_BIT 4 0 OR_TMP_BIT 12 8 SET_TMP_BIT 12 7 LOAD_TMP BIT 4 0 OR_TMP_BIT 12 10 SET_TMP_BIT 12 9 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 0 SET_TMP_BIT 3 0 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 1 SET_TMP_BIT 3 1 LOAD_NOT_TMP_BIT 4 0 AND_TMP_BIT 2 2 SET_TMP_BIT 3 2 LOAD_REG 682 COMP_K_REG 0 0 LOAD_BIT 1200 12 OR_BIT 1200 13 AND_TMP_BIT 0 2 SET_TMP_BIT 4 1 COMP_
250. ter in the non volatile memory which can be accessed by logic commands register When power to the controller is cycled it retains its value settings P PLC programmable logic controller S Structured text A program editor used to create and edit structured text programs editor Structured text A program written in instruction structured text language is composed of a series of language instructions executed sequentially by the LTM R controller Each instruction is composed of a line number a logic command and an some argumeni s T Temporary Register in the temporary memory which can be accessed by logic commands register When power to the controller is cycled it does not retain its value settings Ww Workshop In the FBD editor the place where the FBD elements are linked together 1639507 12 2006 319 Glossary 320 1639507 12 2006 Index Numerics 1 to1 configuration 154 1 to many configuration 154 A Accumulator 43 Add Add FBD Function Block 123 Allocation tables 175 AND AND FBD Function Block 133 AND_BIT 59 AND_K 75 AND_NOT_BIT 61 AND_NOT_NV_BIT 62 AND_NOT_TMP_BIT 61 AND_NV_BIT 60 AND_NV_REG 76 AND_REG 75 AND_TMP_BIT 60 AND_TMP_REG 76 Argument Grid view 42 Text view 39 C Comments 166 Grid view 42 Text view 39 COMP_K_REG 72 COMP_NV_REG 74 COMP_REG 72 COMP_TMP_REG 73 Compare Compare FBD Function Block 122 Compiling 103 143 Compi
251. the 16 bit accumulator is subtracted An integer from 0 to 65 535 Output arguments Value UINT Argument 1 the result of the subtraction process An integer from 0 to 65 535 Underflow BOOL Argument 2 Bit 0 indicates that the subtraction operation resulted in a value less than 0 In this case the true result of the operation equals the value output to Argument 1 65 536 OnHistory BOOL Argument 2 Bit 3 Status of the bit accumulator in the previous scan 94 1639507 12 2006 Structured Text Language ON_MUL The ON_MUL command performs unsigned multiplication when the bit accumulator transitions from 0 to 1 The ON_MUL procedure multiplies the value from Argument 2 against the 16 bit accumulator value then posts the result back to Argument 1 most significant word and Argument 2 least significant word A status register indicates the status of the bit accumulator from the previous scan Arguments Representation 3 ON_MUL TmpReg TmpReg TmpReg Input argument Argument Type _ Description Value UINT Argument 2 the amount to be multiplied by the value in the 16 bit accumulator An integer from 0 to 65 535 Output arguments Product UINT Argument 1 amp Argument 2 the result of the multiplication procedure Argument 1 holds the most significant word Argument_2 holds the least significant word An integer from 0 to 65 535 OnHis
252. the operating mode to Custom Open the predefined logic file that is closest to your application s requirements see LTM R Controller Programming Approach p 165 Then use the structured text editor s logic commands see p 43 to alter the default logic file to suit your application s needs 4 Use the Compile command in the logic functions menu or on the icon bar to validate the custom logic file when you finished editing the logic file Result The PCode Pseudo Code window notifies you whether the logic file compiled successfully The PCode window is a feature of LTM CONF programming software 5 Download after the logic file is compiled the completed logic file from the custom logic editor to the controller using the logic functions menu Download Program to Device command 1639507 12 2006 31 Structured Text Language Custom Logic Editor User Interface To open the structured text editor navigate in the configuration software tree on the left of the screen to Custom Logic Structured Text This will e open the structured text editor in the main window and e enable the logic functions menu The structured text editor is available regardless of whether the configuration software is connected to the controller However many of the logic functions menu items will be enabled only when e a logic file is open in the structured text editor and e the configuration software is connec
253. these steps to assign a value to a register Step Action Untick the Enable Inputs box Specify to which register you wish write data in the Address box Specify which value you wish to assign in the Data box Click on the Write IMPR Reg button AJOJN The Start a Trace box is an integrated debugging tool which captures the 1 bit and the 16 bit accumulator content When you load your If file into the logic simulator it emulates the LTM R controller behavior However values are assigned when you load the file regardless of changes you made in the logic simulator Click the upper refresh button to take into acounts the changes made to registers values Click the bottom refresh button to refresh the PCode 114 1639507 12 2006 Function Block Diagram Language At a Glance Overview What s in this Chapter This chapter describes how to use the FBD Function Block Diagram programming language with LTM CONF programming software This chapter contains the following sections Section Topic Page 3 1 Overview of FBD Language 116 3 2 FBD Elements 121 3 3 Programming with the FBD Language 137 3 4 Manipulating FBD Blocks 144 3 5 FBD Editor Display Options 147 1639507 12 2006 115 Function Block Diagram Language 3 1 Overview of FBD Language At a Glance Summary This section provid
254. time It is OFF after time period expires or Enable is OFF Note Both outputs can never be simultaneously ON Timer FE TenthSeconds m se Block The mesw function measures time in intervals of seconds The following table Characteristics describes the Timer TenthsSeconds block characteristics FBD symbol Timing diagram Inputs Description outputs Inputs Time 16 bit unsigned value 0 to 65 535 that specifies time periods in tenths of seconds a a a Enable ON OFF input value The time period is Timing S s loaded on the rising edge of the Enable input Enable Timing Time measuring continues while Enable is ON a er py ee Timing stops and outputs are OFF when Enable is OFF Time Outputs Timed ON OFF value that turns ON while Enable is ON and time period expires It is OFF while measuring time or while Enable is OFF Timing ON OFF value which is ON while Enable is ON and while measuring time It is OFF after time period expires or Enable is OFF Note Both outputs can never be simultaneously ON 132 1639507 12 2006 Function Block Diagram Language Logic Blocks Overview Access Logic Functions The FBD editor uses various Logic blocks e AND e NOT e OR To access Logic blocks click on the Logic blocks bar in the Toolbox This menu is then displayed in the Toolbox AND NOT OR The following table shows the various Logic function
255. ting status to a and temporary register Arguments Representation 3 TIMER_K_MS KValue TmpReg TmpReg Input arguments Argument Type Description KValue UINT Argument 1 the number of counts An integer from 0 to 65 535 Enable BOOL Argument 3 Bit 0 the rising edge of this bit starts the timer Output arguments EndTime UINT Argument 2 a calculation of the time remaining An integer from 0 to 65 535 TimedOut BOOL Argument 3 Bit 1 indicates that timing has stopped This bit is set when Argument 2 expires This bit is cleared when e Argument 3 Bit O is cleared power is cycled Timing BOOL Argument 3 Bit 2 indicates that timing is ongoing This bit is cleared when Argument 2 expires EnableHistory BOOL Argument 3 Bit 3 Status of the Enable bit in the previous scan 88 1639507 12 2006 Structured Text Language Latch Logic Commands Overview LATCH The Custom Logic Editor uses the following latch commands e LATCH e LATCH_NV The LATCH command e stores a Boolean value 0 or 1 in a temporary register e provides a method for setting and clearing the stored value e saves the clear and set status from the previous scan Arguments Representation 1 LATCH TmpReg Input arguments Argument Type Description Set BOOL _ Bit 1 turns On the latch and sets the value of the State bit Bit 0
256. tion Inputs 0 or 1 ON 1 and OFF 0 Outputs a Any LTM R controller register value from 0 to 1399 which can be written via serial communication ports b Bit position from 0 to 15 134 1639507 12 2006 Function Block Diagram Language Register Word Out Block Register NV Bit Out Block Register NV Word Out Block fe The LTMR block is used to set an LTM R controller register value from the LTM R controller R W addresses 0 to 1399 The following table describes the Register Word Out block characteristics FBD symbol Inputs outputs Description Inputs 16 bit unsigned value from 0 to 65 535 Outputs a Any LTM R controller register from 0 to 1399 which can be written via serial communication ports 1 The LNY block is used to set a non volatile register bit value to O or 1 The following table describes the Register NV Bit Out block characteristics FBD symbol Inputs outputs Description Non Volatile Inputs 0 or 1 ON 1 and OFF 0 Outputs a Any non volatile register from 0 to 63 b Bit position from 0 to 15 Se The LAV block is used to set a non volatile register value The following table describes the Register NV Word Out block characteristics FBD symbol Inputs outputs Description Write Non Volatile Inputs 16 bit unsig
257. tion timer may be set through the menus Other behaviors such as interlocking bump bumpless and direct indirect transitions are managed solely by the custom logic functions and can be modified in either a custom pre defined program or a full custom one 1639507 12 2006 17 Introduction to Custom Logic Editor Custom Logic Editor Programming Languages Custom Logic Editor Programming Tools Logic Commands The custom logic editor provides 2 styles of programming languages e Structured text language which is a list instruction language e Function Block Diagram FBD which is an object oriented programming language Note A third programming language a ladder logic language will be added in a future revision of the configuration utility The custom logic editor includes 2 types of programming editors e The structured text editor which is used to create structured text programs The structured text editor is also referred to as the Text editor e TheFBD editor which is used to create Function Block Diagram FBD programs The FBD editor is also referred to as the graphical editor Note A third programming editor a ladder logic editor will be added in a future revision of the configuration utility Each programming method will satisfy your programming objectives however the custom logic editor allows you to choose the style of programming method that you prefer Both structured text
258. tive LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 1 HMI requested SET TMP BIT 3 1 HMI Active LOAD_NOT_TMP_BIT 4 0 not Transfer in Process AND_TMP_BIT 2 2 TS requested SET_TMP_BIT 3 2 TS active 182 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Generate PLC Fallback Values LOAD_REG 682 PLC fallback mode COMP_K_REG 0 0 HOLD 0 LOAD_TMP_BIT 0 2 equal AND_BIT 1200 12 last LO1 command SET_TMP_BIT 4 1 LOL PLC fallback LOAD_TMP_BIT 0 2 equal AND_BIT 1200 13 last LO2 command SET_TMP_BIT 4 2 LO2 PLC fallback STEP 1 no action needed OFF 2 no action needed COMP_K_REG 3 0 ON 3 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SET_TMP_BIT 4 1 LO1 PLC fallback LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 2 logical or with previous value SET_TMP_BIT 4 2 LO2 PLC fallback COMP_K_REG 4 0 ON OFF 4 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 1 logical or with previous value SET_TMP_BIT 4 1 LO1 PLC fallback COMP_K_REG 5 0 OFF ON 5 LOAD_K_BIT 1 fallback to ON AND_TMP_BIT 0 2 equal OR_TMP_BIT 4 2 logical or with previous value SET_TMP_BIT 4 2 LO2 PLC fallback
259. to 1 Clear BOOL _ Bit 2 turns Off the latch and sets the value of the State bit Bit 0 to 0 Output arguments State BOOL Bit 0 the state 0 or 1 of the latch SetHistory BOOL Bit 3 contains the status of the Set bit Bit 1 from the previous scan OnHistory BOOL Bit 4 contains the status of the Clear bit Bit 2 from the previous scan 1639507 12 2006 89 Structured Text Language LATCH_NV The LATCH_NV command e stores a Boolean value 0 or 1 in a non volatile register e provides a method for setting and clearing the stored value e saves the clear and set status from the previous scan Use the LATCH_NV command instead of the LATCH commana to retain the latch state during a power cycle Arguments Representation 1 LATCH_NV NVReg Input arguments Argument Type Description Set BOOL Bit 1 turns On the latch and sets the value of the State bit Bit 0 to 1 Clear BOOL Bit 2 turns Off the latch and sets the value of the State bit Bit 0 to 0 Output arguments State BOOL Bit 0 the state 0 or 1 of the latch SetHistory BOOL Bit 3 contains the status of the Set bit Bit 1 from the previous scan OnHistory BOOL Bit 4 contains the status of the Clear bit Bit 2 from the previous scan 90 1639507 12 2006 Structured Text Language Counter Logic Com
260. to logic command Counter logic Counters have a range of 0 to 65 535 and transition to 0 upon counting to the commands maximum value of 65 535 Counters perform a comparison between the counted value Arg1 and a constant value Arg2 The first 10 bits of the status register Arg3 describe counter operations as follows e bit 0 indicates that the count Arg1 is O e bit 1 indicates that the count Arg1 is less than the constant value Arg2 e bit 2 indicates that the count Arg1 is equal to the constant value Arg2 e bit 3 indicates that the count Arg1 is greater than the constant value Arg2 e bit 4 increments counter Arg1 on detection of rising edge of input e bit 5 decrements counter Arg1 on detection of rising edge of input e bit 6 sets counter Arg1 equal to constant value Arg2 e bit 7 increment history e bit 8 decrement history e bit 9 set history Latch commands include Command Argument 1 Argument 2 Argument 3 Description COUNTER Temporary register Constant value Temporary register Performs a comparative count count 0 to 65 535 initial status saving both the count and value status to temporary registers COUNTER_NV Non volatile Constant value Non volatile register Performs a comparative count register count 0 to 65 535 initial status saving both the count and value status to non volatile registers 1639507 12 2006 51 Structured Text Language
261. tory BOOL Argument 3 Bit 3 Status of the bit accumulator in the previous scan 1639507 12 2006 95 Structured Text Language ON_DIV The ON_DIV command performs unsigned division when the bit accumulator transitions from 0 to 1 The ON_DIV procedure divides the combined value of Argument 1 and Argument 2 by the 16 bit accumulator value then posts the result back to Argument 1 most significant word and Argument 2 least significant word A status register indicates e an overflow if division is by 0 e the status of the bit accumulator from the previous scan Arguments Representation 3 ON_DIV TmpReg TmpReg TmpReg Input argument Argument Type Description Value UINT Argument 2 the amount to be multiplied by the value in the 16 bit accumulator An integer from 0 to 65 535 Output arguments Product UINT Argument 1 amp Argument 2 the result of the division procedure Argument 1 holds the most significant word Argument_2 holds the least significant word An integer from 0 to 65 535 Overflow BOOL Argument 3 Bit 0 indicates division by 0 OnHistory BOOL Argument 3 Bit 3 Status of the bit accumulator in the previous scan 96 1639507 12 2006 Structured Text Language 2 3 Structured Text Program Examples At a Glance Summary This section shows the structured text program of 2 typical situations which you may need to us
262. us history TS active Include previous result save partial Run1 1639507 12 2006 267 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 1 AND_TMP_BIT 3 0 AND_TMP_BIT 0 0 _TMP_BIT 4 8 ET_TMP_BIT 4 8 no zo Ss as AND_NOT_TMP BIT 4 13 AND_NOT_TMP BIT 12 7 SET_TMP BIT 4 8 Manage Idle State LOAD_TMP_BIT 4 8 AND_NOT_TMP_BIT 4 6 AND_TMP_BIT 5 0 OR_TMP_BIT 5 1 TMP BIT 5 1 s 1 LOAD_TMP_BIT 4 8 D_NOT_TMP_BIT s Da CY a Al 4 ET_NOT_TMP_BIT 5 a 6 0 Set up Step 1 Timer LOAD_K_BIT 1 SET_NOT_TMP BIT 0 3 LOAD_REG 643 ON_SET_TMP_REG 6 0 PLC Fallback PLC fallback value PLC active PLC Comm Loss from scratch Include previous result save partial Run 1 HMI Fallback HMI fallback value HMI active HMI Comm Loss from scratch Include previous result save partial Run 1 3wire latch NOT Swapping NOT Mode Change 1 save final Run 1 Generate Run 2 NA 5 0 Run 1 NOT Stopl Tdle State Output 1 State Output 1 State Run 1 NOT Stopl1 Tdle State Clear the history bit Step 1 Time value set current time period 268 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d Set up Lockout Timer SET_NOT_TMP_BIT 0 3 LOAD_REG 541 ON_SET_TMP_REG 9
263. value of the Custom Logic Temporary Space register at address 1204 BitNo UINT The bit location an integer from 0 to 15 Output arguments SET_NOT_NV_BIT The SET_NOT_NV_BIT command sets the inverted value of the 1 bit accumulator to a specified non volatile register bit Arguments Representation 2 SET_NOT_NV_BIT NVReg BitNo Input arguments Argument Type Description NVReg UINT The non volatile space register number An integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 BitNo UINT The bit location an integer from 0 to 15 Output arguments 68 1639507 12 2006 Structured Text Language Register Logic Commands Overview Register commands evaluate and control 16 bit values The custom logic editor uses the following register commands LOAD_K_REG LOAD_REG LOAD_TMP_REG LOAD_NV_REG COMP_K_REG COMP_REG COMP_TMP_REG COMP_NV_REG AND_K AND_REG AND_TMP_REG AND_NV_REG OR_K OR_REG OR_TMP_REG OR_NV_REG XOR_K XOR_REG XOR_TMP_REG XOR_NV_REG ON_SET_REG ON_SET_TMP_REG ON_SET_NV_REG 1639507 12 2006 69 Structured Text Language LOAD_K_REG The LOAD_K_REG command loads a constant 16 bit value into the accumulator in logic memory Arguments Representation 1 LOAD_K_REG KValue Input arguments Argument Type Descr
264. ve final Global Stop Latch comm loss values in scratch 0 LOAD_BIT 456 8 SET_TMP BIT 0 0 LOAD BIT 456 7 SET_TMP_BIT 0 1 PLC Comm Loss save in scratch bit 0 HMI Comm Loss save in scratch bit 1 234 1639507 12 2006 Pre Defined Structured Text Programs Structured Text Program cont d LOAD_TMP_BIT 4 5 SET_TMP_BIT 4 6 LOAD_TMP_BIT 0 0 AND_TMP_BIT 3 0 AND_NOT_TMP_BIT 4 1 OR_TMP_BIT 4 6 SET_TMP_BIT 4 6 LOAD_TMP_BIT 0 1 AND_TMP_BIT 3 1 AND_NOT_TMP_BIT 4 3 OR_TMP_BIT 4 6 SET_TMP_BIT 4 6 LOAD_TMP_BIT 3 0 AND_NOT_BIT 704 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 0 0 OR_TMP_BIT 4 6 SET_TMP_BIT 4 6 LOAD_TMP_BIT 3 1 AND_NOT_TMP_BIT 13 12 AND_TMP_BIT 4 8 AND_NOT_TMP_BIT 0 1 OR_TMP_BIT 4 6 SET_TMP_BIT 4 6 LOAD_TMP_BIT 3 2 AND_NOT_BIT 457 AND_TMP_BIT 4 8 OR_TMP_BIT 4 6 SET_TMP_BIT 4 6 0 0 Generate Stopl and Stop2 Commands Generate Stopl Global Stop save partial Stopl PLC Comm Loss from scratch PLC active NOT LO1 PLC fallback value Include partial Stopl save partial Stopl HMI Comm Loss from scratch HMI active NOT LO1 HMI fallback value Include partial Stopl save partial Stopl PLC active NOT PLC Runt Run 1 NOT PLC Comm Loss from scratch Include partial Stopl save partial Stopl HMI active NOT HMI Run 1 Run 1 NOT HMI
265. vious scan Arguments Representation 1 ON_SET_NV_REG NVReg NVReg Input arguments Argument Type Description Output arguments RegAddr UINT Argument 1 an integer ranging from 0 to the value equalling 1 less than the value of the Custom Logic NonVolatile Space register at address 1205 OnHistory BOOL Argument 2 Bit 3 contains the bit accumulator value from the previous scan 84 1639507 12 2006 Structured Text Language Timer Logic Commands Overview The custom logic editor uses the following Timer commands e TIMER_SEC e TIMER_MS e TIMER_K_SEC e TIMER_K_MS TIMER_SEC The TIMER_SEC command e counts time in seconds up to the number of counts specified by a temporary register e calculates and tracks the time remaining in a 2nd temporary register e is enabled by and reports its counting status to a 3 temporary register Arguments Representation 3 TIMER_SI EC TmpReg TmpReg TmpReg Input arguments Argument Type Description TmpReg UINT Argument 1 the number of counts An integer from 0 to 65 535 Enable BOOL Argument 3 Bit 0 the rising edge of this bit starts the timer Output arguments EndTime UINT Argument 2 a calculation of the time remaining An integer from 0 to 65 535 TimedOut BOOL Argument 3 Bit 1 indicates that timing has stopped This bit is set when Argu
266. volatile memory and initialized to previous state on power up i The iat function enables you to choose between two 16 bit unsigned values The following table describes the Mux block characteristics FBD symbol Inputs outputs Description Inputs A 16 bit unsigned value 0 to 65 535 B 16 bit unsigned value 0 to 65 535 A B ON OFF 0 or 1 input value that selects value A or B Outputs Out Selected 16 bit value If A B is OFF then Out A If A B is ON then Out B 1639507 12 2006 131 Function Block Diagram Language Timer Seconds Block Characteristics Fe Basta TIMER A C The function measures time in intervals of seconds The following table describes the Timer Seconds block characteristics FBD symbol Timing diagram Inputs Description outputs Inputs Time 16 bit unsigned value 0 to 65 535 that Enable specifies time period in seconds E lt L Enable ON OFF input value The time period is loaded Timing on the rising edge of the Enable input Time Enable Timing Timed measuring continues while Enable is ON Timing stops and outputs are OFF when Enable is OFF Time Outputs Timed ON OFF value which turns ON while Enable is ON and time period expires It is OFF while measuring time or while Enable is OFF Timing ON OFF value that is ON while Enable is ON and while measuring
267. wing table describes how to select one or more blocks If you would like to select Then An isolated block Left click on the block Several contiguous blocks Frame the blocks to be selected by defining a selection zone Result All of the selected blocks are highlighted with an orange outline Write Temporary Several blocks in different areas of the workspace Press the Shift key then click on the blocks to be selected while continuing to hold down the Shift key Result All of the selected blocks are highlighted with an orange outline All objects including wires Select Edit gt Select All 1639507 12 2006 145 Function Block Diagram Language How to Delete and Duplicate Objects At a Glance Sometimes it may be necessary to delete a block or duplicate a block in the workspace How to Delete The following table describes how to delete one or more blocks aon Step Action 1 Select the block s to be deleted Result The selected blocks are highlighted with an orange outline Write Temporary Press the Delete or backspace key or select Edit gt Delete Result The selected blocks are deleted Howto Cut Copy The following table describes how to cut copy or paste one or more blocks or Paste Blocks Step Action 1 Select the block s to be manipulated Result The selected blocks are highlighted with an orang

TeSys T LTM R Motor Management Controller

Contents

Download Pdf Manuals

Related Search

Related Contents