RT-DAC4/PCI Multi I/O Board User's Manual
Contents
1. 0xE0 Aux amp OxFFFD Write Word BaseAddress OxEO Aux Clear Ext1 intr request iAux 0x0002 Write Word BaseAddress OxEO Aux Reinit software interrupt if IntrSource amp 0x04 ExtO AfxMessageBox External 0 Interrupt Source Aux ReadWord BaseAddress 0xE0 Aux amp OxFFFE Write Word BaseAddress OxEO Aux Clear Ext0 intr request Aux Ox0001 WriteWord BaseAddress OxEO Aux Reinit software interrupt return 0 Interrupt functions I O space byte offset 224 Function reads writes interrupt flags Used bits D7 value of 1 enables local interrupt generation Value of 0 disables D6 not used D5 value of 1 generates local software interrupt RT DAC4 PCI User s manual D4 value of 1 enables local software interrupt generation If local software interrupt occurred previously setting this bit to 0 clears the interrupt request D3 value of 1 enables local timer interrupt generation If local timer interrupt occurred previously setting this bit to 0 clears the interrupt request D2 value of 1 enables local COS interrupt generation If local software COS occurred previously setting this bit to 0 clears the interrupt request D1 value of 1 enables local interrupt generation requested by the external ExtIntl signal If local ExtInt1 interrupt occurred previously setting this bit to 0 clears the interrupt request DO value of2. C API function name RT DAC4 PCI User s manual read write the current wave generator channel D3 DO wave generator channel number RitdacPCI_ ReadGeneratorL RtdacPCI_ ReadGeneratorH RitdacPCI_ WriteGeneratorL RtdacPCL WriteGeneratorH read write the duration of the L state D27 DO defines the number of periods of the base wave when the output is L RitdacPCI_ ReadGeneratorL RitdacPCI_ WriteGeneratorL read write the duration of the H state D27 DO defines the number of periods of the base wave when the output is H RtdacPCI_ ReadGeneratorH RidacPCI_ WriteGeneratorH page 16 INTECO WWW 6 7 Encoders The RT DAC4 PCI board includes four 32 bit incremental encoder input channels denoted as ENCO ENC3 Each channel counts the changes of two input waves The initial value of each encoder counter can be set to zero in a programmable way The appropriate encoder input channel has to be selected by writing a given value to the 1 O offset equal to128 The I O space offset equal to 132 is used to reset encoder counters The bits of the 132 I O offset reset the corresponding encoders single write action to the 132 offset can reset all the encoder counters The I O space offset equal to 136 is used to read the current encoder counter value For example to reset encoder ENC2 start counting and read data the following C statements can be executed _outpd BaseAdar 132 4 set the third bit only E
3. 8 XILINX FPGA CHIP PROGRAMMING The RT DACA PCI board is equipped with a XILINX FPGA chip The user can reprogram the logic design of the FPGA chip A new logic can perform quite different functions For example the user can build a new logic which can perform e 32 PWM outputs or hardware implemented digital filters or hardware implemented FFT algorithm or fast data acquisition from A D converters or fast analog signal generators using D A converters or data encryption and decryption or finite state machines or microprocessor cores and much more The design of a new logic requires a more extended RT DAC4 PCI board description The description is included in the RT DAC4 PCI FPGA Programming Guide distributed separately RT DAC4 PCI User s manual page 27
4. RTDACPCI_INTR_STATUS 232 E8 Interrupt timer period RTDACPCI INTR PERIOD 236 EC Change of state LSW mask RTDACPCI COS MASK L 240 FO Change of state MSW mask RTDACPCI COS MASK H 244 F4 Change of state before value RTDACPCIL COS BEFORE 248 FS Change of state after value RTDACPCI_COS_AFTER 6 1 Before using a C API functions To use C API functions in a user application the following statements have to be included at the beginning of the C source file RT DAC4 PCI User s manual page 10 INTECO WWW define RTDAC PCI VERSION API define RTDAC PCI COUNTER API define RTDAC PCI TIMER API define RTDAC PCI DIGITALDIRECTIONS API define RTDAC PCI DIGITAL IO API define RTDAC PCI PWM API define RTDAC PCI GENERATOR API define RTDAC PCI ENCODER API define RTDAC PCI AD API define RTDAC PCI DA API define RTDAC PCI INTR API define RTDAC PCI FIFO API define RTDAC PCI FREQM API For PLC API I O access functions define inp A ReadByte A define inpw A ReadWord A define inpd A ReadDWord A define _outp A B WriteByte A B define _outpw A B WriteWord A B define _outpd A B WriteDWord A B include rtdacpci c The statements define the macro definitions required by the rtdacpci c file The API functions are implemented in the rtdacapi c To be able to establish the communication with the RT DAC PCI board there are required functions to access the I O address space of the board Th
5. 1 enables local interrupt generation requested by the external ExtInt0 signal If local ExtIntO interrupt occurred previously setting this bit to 0 clears the interrupt request page 22 viv INTECO C API function name T O space byte offset 228 Function Used bits C API function name T O space byte offset 232 Function Used bits C API function name T O space byte offset 236 Function Used bits C API function name T O space byte offset 240 Function Used bits C API function name T O space byte offset 244 Function Used bits C API function name T O space byte offset 248 Function RT DAC4 PCI User s manual RtdacPCI ReadIntrFlags RtdacPCI WriteIntrFlags reads interrupt status D11 value of 1 indicates that local interrupt has occurred D10 not used D9 value of 1 indicates that the software interrupt request is queued D8 value of 1 indicates that the timer interrupt request is queued D7 value of 1 indicates that the COS interrupt request is queued D6 value of 1 indicates that the ExtInt1 interrupt request is queued DS value of 1 indicates that the ExtIntO interrupt request is queued D4 value of 1 indicates that the current PCI interrupt is caused by the software interrupt source D3 value of 1 indicates that the current PCI interrupt is caused by the timer interrupt source D2 value of 1 indicates that the current PCI inte
6. 150 016 DIO 15 GND 170 018 GND 5V 190 020 3 3V CN4 D1016 10 02 DIO 17 D1018 30 04 DIO 19 D I O Digital Input Output D 1020 90 06 D9 21 aa D1022 70 08 D023 GND Digital ground D1024 90 010 D025 DO 26 110 012 D1027 D1 0 28 130 014 D1029 D1030 150 016 D1031 GND 170 018 GND 5V 190 020 3 3V CN5 PWMO 10 02 PWM1 30 04 PWM2 50 06 PWM and COUNTER Es 70 08 outputs GENo 90 010 GND Gem 110 o12 Alpins Extinto 130 014 Extintt 150 016 CNTO 170 018 CNT1 190 020 CN6 ENCO A 10 02 ENCO B 30 04 or ENC1 A 50 06 Encoder inputs ENC1 B 70 08 ENC2 A 90 010 GND ENC2 B 110 012 AlPins ENC3 A 130 014 ENC3 B 150 016 Reserved 170 018 Reserved 190 020 Fig 4 RT DAC4 PCI I O connectors The further information included in section 5 can be used by advanced users RT DAC4 PCI User s manual page 8 INTECO viv 6 REGISTER STRUCTURE AND FORMAT Table 2 shows the offset of each registers and the control words relative to the I O base address of the RT DAC4 PCI board This information is necessary to configure RT DAC4 PCI board to serve ones own system It is assumed that each offset in Table 2 reserves 4 bytes in the I O address space Some functions do not require all of 32 information bits In such a case the most significant bits have to be neglected The functionality description given below corresponds only to meaningful bits The convention applied is that the most sign
7. D conversion result ADResult ADResult 8 OxFFF mask only 12 bits _outpd BaseAddr 164 0x7 set CONVST RD and CS to 1 or the following API function can be called ADResult RtdacPCI AD BaseAddr 3 1 RT DAC4 PCI User s manual page 18 INTECO WWW A D converter functions I O space byte offset 160 Function select the channel and gain Used bits D3 D0 the analog input channel see Table 4 D6 D4 the analog amplifier gain see Table 3 C API function name RtdacPCI_AD I O space byte offset 164 Function sets the A D control or reads the A D end of conversion signal Used bits when write DO the CONVST signal D1 the CS signal D2 the RD signal when read DO the EOC signal C API function name RtdacPCI_AD I O space byte offset 168 Function reads the A D conversion results Used bits D11 DO the result of the last A D conversion C API function name RtdacPCI_AD 6 9 D A Conversion The RT DAC4 PCI board is equipped with four channel 12 bit D A converter The converter is controlled by the Al AO LDAC R W and CS signals The signals are controlled by the I O offset 192 A1 at D4 AO at D3 LDAC at D2 R W at D1 and CSF at DO The Al and AO signals select a appropriate output channel The R Wit signal is used to store data in the D A converter buffer The rising edge of the LDAC signal moves data from the D A converter buffer to the D A converter The in
8. Generators Block AVD control amp data XILINX ao Handling FPGA Module D A control data pr A D D A CONVERTERS Control Module J Fig 2 The default structure of the Xilinx FPGA chip PLX BUS The next section contains the basic information necessary to install and test the board The information and specification how to reprogram XILINX FPGA is not included in this guide Please relate to RI DAC4 PCI FPGA Programming Guide distributed by INTECO separately RT DAC4 PCI User s manual page 5 WWW INTECO 2 BOARD INSTALLATION The RT DACA PCI setup contains RT DAC4 PCI board RT DAC4 PCI Testing Software 2 ribbon cables RT DAC4 PCI User s Manual this manual terminal wiring board optional The RT DAC4 PCI board contains sensitive electric components which can be easily damaged by static electricity therefore the board should be kept in its original anti static packing until it is installed During installation the board should be handled carefully only by the edges to avoid static electric discharge To install the board turn off the computer and remove the cover find an empty 32 bit PCI slot and remove the metal bracket check jumper settings for your configuration see section 4 insert the RT DAC4 PCI board into the expansion slot firmly and evenly then secure the bo
9. operate in high speed and the 12 bit mode allows PWM to achieve high accuracy of the output In the 12 bit mode a single PWM period contains 4095 impulses of the output prescaler frequency The time of logic output 1 is set by a number from 0 to 4095 In the 8 bit mode a PWM period contains 255 impulses of the output prescaler frequency The time of logic 1 is set by a number from O to 255 The 8 bit mode is used for high speed The 12 bit mode gives a high accuracy The input base frequency of the PWM channels is set by default to 40MHz 30MHz or 20MHz It depends on board version This frequency is divided by the counter called prescaler which creates the PWM base period and the period of the H state The valid prescaler value is a number taken from the range 0 65535 The frequency of the PWM wave is calculated by the formula base for 8 bit mod fewu prescaler 1 255 E Tate gt for 12 bit mode Sewu prescaler 1 4095 Dividers 40 30 20 MHz PWM prescaler Mod 255 or 4095 PWM i Output Wave PWM width Comparator gt Fig 5 Block diagram of the PWM generator To set the correct wave of a PWM channel the number of channel have to be written to the I O space offset 96 The I O offset equal to 100 sets the PWM mode the I O offset equal to 104 sets the prescaler value and the I O offset equal to
10. val WaitForSingleObject eventHandle 10000 _ except EXCEPTION EXECUTE HANDLER RT DAC4 PCI User s manual page 21 WWW INTECO if val WAIT TIMEOUT val WAIT FAILED AfxMessageBox try Timeout else if IntrResponse BoardNo 1 lt 0 AfxMessageBox Intrrupt Response Error ResetEvent eventHandle IntrSource ReadWord BaseAddress OxE4 amp 0x1F if IntrSource 8 0x10 Software interrupt AfxMessageBox Software Interrupt Source Aux ReadWord BaseAddress OxE0 Aux amp OxFFEF Write Word BaseAddress OxEO Aux Clear software intr request Aux 0x0010 WriteWord BaseAddress OxEO Aux Reinit software interrupt if IntrSource amp 0x08 Timer interrupt AfxMessageBox Timer Interrupt Source Aux ReadWord BaseAddress 0xE0 Aux amp OxFFF7 Write Word BaseAddress OxE0 Aux Clear timer intr request Aux 0x0008 WriteWord BaseAddress OxEO Aux Reinit software interrupt if IntrSource amp 0x04 COS interrupt AfxMessageBox COS Interrupt Source Aux ReadWord BaseAddress 0xE0 Aux amp OxFFFB Write Word BaseAddress OxE0 Aux Clear COS intr request Aux 0x0004 WriteWord BaseAddress OxEO Aux Reinit software interrupt if IntrSource amp 0x04 Ext1 AfxMessageBox External 1 Interrupt Source Aux ReadWord BaseAddress
11. 108 determines the PWM duty cycle For example to set PWM2 to 12 bit mode prescaler to 1200 and duty cycle to 50 the following C statements can be executed _outpd BaseAdar 96 2 select PWM2 as the current PWM channel _outpd BaseAdar 100 1 select the 12 bit mode of the current channel _outpd BaseAdar 104 1200 set prescaler to 1200 _outpd BaseAdar 108 2047 set duty cycle to 50 2047 is 50 of 4095 or the following API function can be called RtdacPCI PWMWrite BaseAdar 2 1 1200 2047 PWM functions I O space byte offset 96 Function read write the current PWM channel Used bits D3 DO PWM channel number C API function name RtdacPCI_PWM Channel RtdacPCI_PWM Write T O space byte offset 100 Function read write the mode of the current PWM channel Used bits DO 0 defines the 8 bit mode 1 defines the 12 bit PWM mode C API function name RtdacPCI PWMMode RT DAC4 PCI User s manual page 15 WWW INTECO I O space byte offset 104 Function Used bits C API function name I O space byte offset 108 Function Used bits C API function name RtdacPCI PWMWrite read write the prescaler for the current PWM channel D15 DO the divider value RtdacPCI_PWMPrescaler RtdacPCI_PWMWrite read write the width value of the current PWM channel D7 DO for the 8 bit mode D11 DO for the 12 bit mode RtdacPCI PWMWidth RtdacPCI_PWMWrite 6 6 Digi
12. 9030 I O space The second is RT DAC4 PCI logic I O space The base address of the internal PLX9030 I O space is returned by the mex pcibarl MATLAB function as well as by the call to the BoardLocationEx basic API function The base address of the RT DAC4 PCI logic I O space is returned by the mex_baseaddress MATLAB function or by the call to the BoardLocation basic API function The internal PLX9030 I O space is responsible for the parameters of the PCI bridge including the PCI interrupt generation The RT DAC4 PCI logic generates interrupt signal which triggers the PLX9030 chip This signal is denoted as the local interrupt If local interrupt is active the PLX9030 can generate the INTA PCI interrupt The parameters of the PCI INTA interrupt are set by the location which offset in the internal PLX9030 I O space is equal to 4C hex The name of this location is INTCSR The bits of the INTCSR have the following meaning 0 Local interrupt enable Value of 1 indicates enabled interrupt generation by the RT DAC4 PCI logic Value of 0 indicates disabled I Local interrupt polarity Value of 1 indicates active high Value of 0 indicates active high 2 Local interrupt status Value of 1 indicates interrupt active Value of 0 indicates interrupt not active 3 5 reserved 6 PCI interrupt enable Value of 1 enables PCI interrupt 7 Software interrupt Value of 1 generates software interrupt 8 Local interrupt select enable
13. COS after state page 23 INTECO W Used bits D31 DO reads which state at the CN3 and the CN4 connectors was active immediately after the COS generation The D31 D16 bits store the state of the CN4 and the D15 DO bits store the state of the CN3 connector C API function name RtdacPCI ReadIntrCOSAfter RT DAC4 PCI User s manual page 24 INTECO WWW 7 LOW LEVEL API FUNCTIONS It was developed the DLL library which contain functions used to detect the RT DAC4 PCI location and to allow the access to the board resources The library is distributed as three files RTDACAPI DLL RTDACAPI LIB and RTDACAPI H The first file contains the functions The second file is used during static DLL linking The last file contains the declarations of exported functions The API DLL allows to detect the location of the RT DAC4 PCI boards available in the system and allows access to the I O address space The access to the I O address space is prohibited in the Windows NT 2000 XP operating systems and the API DLL allows to exceed these limitations A special kernel mode device driver called by the API DLL functions performs operations which are forbidden in user mode applications The API interface contains the following functions see the RTDACAPI H file int NoOfDetectedBoards void Returns the number of RT DAC4 PCI boards detected in the system int BoardLocation int Boardldx int BusNo int SlotNo int VendorlD int
14. DevicelD int BaseAdaress Determines the bus number slot number vendor ID device ID and base address of the RT DAC4 PCI board given by the Boardldx input argument The Boardldx can vary from 1 to the number of detected boards returned by the NoOfDetectedBoards function The function returns O value if succeed or 1 if failed int BoardLocationEx int Boardldx int BusNo int SlotNo int VendorlD int DevicelD int BaseAddress int PCIBAR1 Determines the bus number slot number vendor ID device ID base address and the PCIBAR1 location of the RT DAC4 PCI board given by the Boardlax input argument The Boardldx can vary from I to the number of detected boards returned by the NoOfDetectedBoards function The function returns 0 value if succeed or 1 if failed int WriteByte int port int value unsigned short WriteWord int port unsigned int value unsigned long WriteDWord int port unsigned int value Output the value byte WriteByte word WriteWord or double word WriteDWord at the port port The functions return the data output int ReadByte int port unsigned int ReadWord int port unsigned long ReadDWord int port Input a byte ReadByte a word ReadWord or a double word ReadDWord from the port port int IntrInit int Boardldx Interrupt initialisation function The Boardldx can vary from 1 to the number of detected boards returned by the NoOfDetectedBoards function and defines wh
15. NC2 is reset I _outpd BaseAdar 132 0 set reset flags to zero for all encoders normal operation of encoder counters _ outpd BaseAdar 128 2 select ENC2 as the current encoder Counter _inpd BaseAdar 136 read current counter value or the following API functions can be called RtdacPCI ResetEncoder BaseAdar 2 1 RtdacPCI ResetEncoder BaseAdar 2 0 Counter RtdacPCl_ReadEncoder BaseAdar 2 Encoder functions I O space byte offset 128 Function read write the current encoder channel Used bits D3 DO the encoder channel number C API function name RtdacPCI ReadEncoder I O space byte offset 132 Function reset encoder counters Used bits D3 DO four bits responsible for resetting four encoder counters If a bit is set the corresponding encoder counter is set to zero C API function name RtdacPCI_EncoderReset I O space byte offset 136 Function reads the current encoder counter value Used bits D31 DO for the 8 bit mode C API function name RtdacPCI_ReadEncoder RT DAC4 PCI User s manual page 17 INTECO WWW 6 8 A D Conversion The RT DAC4 PCI is equipped with 16 multiplexed analog inputs The output of the analog multiplexer is connected to the input of the digital programmable analog amplifier The 160 I O offset is used to select an input channel and an amplifier gain The Table 3 and the Table 4 show the setting for the D6 D4 and D3 D0 bits Tab
16. Value of 1 indicates enabled edge triggerable interrupt Value of 0 indicates enabled level trigerrable interrupt Operates only in high polarity mode 9 reserved 10 Local edge trigerrable interrupt clear Writing 1 to this bit clears local interrupt 11 15 reserved The interrupts can be level or edge triggered The RT DAC4 PCI logic uses only edge triggering The IntrInit procedure from the board basic API enables local interrupt bit 0 set to 1 sets high polarity mode bit 1 set to 1 enables PCI interrupts bit 6 set to 1 and enables edge local interrupt trigger bit 8 set to 1 The IntrResponse procedure clears interrupt by setting the bit 10 to 1 Each interrupt requests are stored in the RT DAC4 PCI register Only one of the requested local interrupts can generate the PCI interrupt The PCI handling procedure must be able to distinguish which local interrupt source has generated the PCI interrupt and which interrupt requests are queued The I O offset equal to 224 activates the interrupt sources and clears the interrupt requests The I O offset equal to 228 is used to read which local interrupt source has generated the current PCI interrupt and the queued interrupts The I O offset 232 defines the period of the interrupt timer The timer is applied to periodically generation of interrupts The period of the timer is defined in 25ns units Be sure not to define too short interrupt period because it may degrade the performance
17. alue RTDACPCI TIMER Digital 1 0 64 40 Digital I O directions of 16 least significant digital I O lines RTDACPCI DIG IO DIR L 68 44 Digital I O directions of 16 most significant digital I O lines RTDACPCI DIG IO DIR H 72 48 Digital input output values of 16 least significant digital I O lines RTDACPCI DIG IO VALUE L 76 4C Digital input output values of 16 most significant digital I O lines RTDACPCI DIG IO VALUE H RT DAC4 PCI User s manual page 9 viv INTECO PWM 96 60 PWM index RTDACPCI_PWM_IDX 100 64 PWM mode RTDACPCI_PWM_MODE 104 68 PWM prescaler RTDACPCI_PWM_PRESCALER 108 6C PWM channel width RTDACPCI_PWM_WIDTH Digital signal generators 112 70 Generator index RTDACPCI WAVE IDX 116 74 Duration of the H state RTDACPCI WAVE L 120 78 Duration of the L state RTDACPCI WAVE H Encoders 128 80 Encoder index RTDACPCI ENCODER IDX 132 84 Reset encoder counters RTDACPCI RESET 136 88 Encoder counter RTDACPCI_ENCODER A D conversion 160 AO A D channel and gain RTDACPCI_AD_MUX 164 A4 A D control signals ADSTART CS RD RTDACPCI_AD_CONTROL 168 A8 Conversion result RTDACPCI AD RESULT D A conversion 192 CO D A control signals LDAC CS Al AO WR RTDACPCI_DA_CONTROL 196 C4 D A channel RTDACPCI_DA Interrupts 224 EO Interrupt flags RTDACPCI INTR FLAGS 228 E4 Interrupt status
18. ard with the bracket screw and install the cover turn on the computer install driver for the board see section 3 or CD DRIVERVreadme txt install the Testing Software or install RT CON package test the board 3 DRIVER INSTALLATION The driver for RTDAC4 PCI board has to be installed because the board is of the PCI type The way of driver installation depends on operating system The user with administrator privileges must install the drivers for Windows XP and Windows 7 3 1 Installation Administrator privileges are required for driver installation Start Windows XP 7 System detects new PCI device Select Next then Display a list Select Other Devices then Next Select Have a disk then Browse Select path CD driver WinW7x86 RTDAC4_PCI9030 inf then Open Select OK and Next and Next Select Finish If Windows propose to restart the computer select Yes RT DAC4 PCI User s manual page 6 INTECO viv 4 JUMPER SETTINGS The RT DAC4 PCI board is equipped with two jumpers for configuration setting The board layout is shown in Fig 3 CN3 CNS RT DAC4 PCI Fig 3 The layout of the RT DAC4 PCI board 4 1 Output range selection JP1 RT DAC4 PCI is equipped with four analogue output channels The user can set the output range for all channels The JP1 jumper supports all channels Table 1 Table 1 D A range selection Pin 0 10V 10 10V 10 0V 1 2 closed x 3 4 clo
19. ated to real time data acquisition and control in the Windows 95 98 NT 2000 environment The board uses a PCI bus and supports real time operations without introducing latencies caused by the Windows default timing system The board contains a Xilinx FPGA chip that can be reprogrammed to introduce a new functionality of digital inputs outputs without any hardware modification The default configuration of the FPGA chip accepts signals from incremental encoders and generates PWM outputs typical for mechatronic control applications 1 2 Specification Analog section Analog Inputs Channels 16 single ended multiplexed Resolution 12 bit Input ranges 10V programmable gain xl x2 x4 x8 x16 Conversion time 1 6us Trigger software hardware Reference voltage on board Analog Outputs Channels 4 Resolution 12 bit Output range OV 10V 10V 0V 10V Settling time 6us to 0 01 Reference voltage on board Digital section version 1 11 Digital Input Output Channels 32 bi directional direction setting Direction bi directional direction is individual software programmable Input voltage Vin 2 0V 3 6V Vi 0 5V 0 8V Output voltage Vou 2 4V min Vo 0 4V max Output current 2mA 24mA per channel Standard LVTTL Digital Timer Counter 16 bit counter 2 channels counts external signal 32 bit timer 2 channels co
20. ce bene doe ncue cee tamed soe noe soee nine Se oeaeos sees nave ou ouaeveuvaonens E Er Er 14 6 5 PM 15 6 6 DIGITAL SIGNAL GENERATORS rrrrervrererererererererererererererererevererererererererereverererevererereverevereverevereveveveveverere 16 6 7 ENCODERS oe ae te ttre cca cca E a E ute hanes Coe agreshGe tue sade acve ures hans ecotncee duoc tenses nevesete heneucoeacredGe terete 17 6 8 ATT CONVERSION 2202205 2acecetnces ese nteexadeddeceabenened dod advesebantvasnadddvssvbe navesdedgdvecveaatbedscsddueesbencuetdotadvesveentuemeds 18 6 9 DAI CONVERSION 20 5 redekasse desanteevsdcndvesabe neces aae tess a e tones ae ea a e aa aae ea 19 6 10 INTERRUPTS noren con EE EERE A EE E E ER E ERE EOE 20 Te LOW LEVEL API FUNCTIONS qisseoseerssenssressenensneseeseneanendaresesesrensendenenesvsnennsvaderesesnsd oensenseeesere nsensendese see 25 8 XILINX FPGA CHIP PROGRAMMING eesosensvnvvvseesensnnnnvnsenesensnnnnnnnnnnsennnnnnvnsenssensnnnnnnnnnenennnnnnnnnnnssenenee 27 RT DAC4 PCI User s manual page 1 INTECO W NOTES MATLAB Simulink RTW and RTWT are registered trademarks of The MathWorks Inc Windows NT 2000 XP 7 are registered trademarks of Microsoft Corporation Copyright OINTECO 2002 2013 All rights reserved Copyright 2000 PLX Technology Inc RT DAC4 PCI User s manual page 2 INTECO viv 1 GENERAL INFORMATION 1 1 Introduction The RT DAC4 PCI is a multifunction analog and digital timing I O board dedic
21. e communication is performed by the functions from the PLX library the PlxApi631 dll file The RT DAC PCI functions are implemented in the rtdacapi dll library For convenience also the rtdacapi lib and rtdacapi h files are available The names of the I o access functions are ReadByte address read a single byte from the address location ReadWord address read a single word from the address location ReadDWord address read a double word from the address location WriteB yte address value writes a single byte value to the address location Write Word address value writes a single word value to the address location WriteDWord address value writes a double word value to the address location The following Visual Studio projects are given as examples e RT DAC PCI Test VS 2010 project of the test program e Common RTDAC PCI API PLX IO VS 2010 project to build the RTDACAPI dll 6 2 Version management The RT DAC4 PCI board is equipped with XILINX FPGA All functions of the board are implemented as the FPGA project except the PCI communication functions The FPGA logic can be easily changed and tailored to the user requirements The bitstream version function I O address offset 0 enables one to distinguish different logic versions Table 2 The I O address offset equal to 4 allows one to read current number of digital signal generators counter timer PWM and encoder channels For example to read the number of available chan
22. here are 32 digital I O lines at the RT DAC4 PCI board Digital I O lines are LVTTL compatible The direction of each digital I O can be configured separately The default configuration of the RT DAC4 PCI includes four PWM outputs and four input channels of the incremental encoders The PWM outputs and encoders inputs turn the PC into a digital controller to be used in control of manipulators servo systems etc Two digital signal generators can be applied to generate signals with an arbitrary duty cycle PCI interrupts are born in the interrupt generation block They come out from different sources software timer two external signals and change of state at thirty two digital inputs Reprogramming the XILINX FPGA chip can change functions of the digital section of the board The interior of the FPGA chip is presented in Fig 2 Beside digital 1 O and interrupts there are the FPGA logic which implements A D and D A control functions and the board controller The FPGA chip is connected to a hardware oscillator which gives a high counting resolution Different versions of the board operate at different frequencies typically 40 MHz The board is equipped with six 20 pin ribbon cable connectors The detailed block diagram of the RT DAC4 PCI board including connectors is given in sections 3 and 4 ncoder x 4 nx 2 xtInt x 2 G PWM x4 G Ge D IO x 32 Digital I O PWM Incremental Encoders Signal Interrupt Module Module Module
23. ich board initialises interrupts The function enables interrupt generation and defines that the interrupt trigger is rising edge of the LINTil local bus signal The function returns 0 value if succeed or 1 otherwise int IntrAttach int Boardldx HANDLE eventHandle RT DAC4 PCI User s manual page 25 INTECO WWW This function attaches the object eventHandle to the interrupt handling procedure The Boardldx can vary from 1 to the number of detected boards returned by the NoOfDetectedBoards function and defines which board is considered The function enables interrupt generation and defines that the interrupt trigger is rising edge of the LINTi1 local bus signal The function returns 0 value if succeed r a negative value otherwise int IntrResponse int Boardldx This function clears the internal PLX9030 interrupt request flag It is called by the user interrupt handling procedure The Boardldx can vary from 1 to the number of detected boards returned by the NoOfDetectedBoards function and defines which board is considered The function returns O value if succeed or 1 value otherwise IntrClose int Boardldx This function terminates interrupt generation by the board The Boardldx can vary from 1 to the number of detected boards returned by the NoOfDetectedBoards function and defines which board is considered The function returns O value if succeed or 1 otherwise RT DAC4 PCI User s manual page 26 INTECO WWW
24. ificant bit is denoted D31 and the least significant bit DO The RT DAC4 PCI access functions are defined in the rtdacpci c file This file contains the API macro definitions see Table 2 and C API functions referred to the description of the board functions Notice The rtdacpci c file is accessible after installation of the RT CON toolbox or installation of Testing Software In the examples of the next sections it is assumed that the BaseAddr variable is the base I O space address of the board The RT DAC4 PCI board is located in the I O address space of the microprocessor The offset can vary because the PCI bus controller determines its value automatically The current base address of the board can be detected by Testing Software or by the MATLAB mex_baseaddress function Table 2 1 O address space map Byte offset Description Decimal Hexadecimal API macro definition Version management 0 00 XILINX bitstream version read only RTDACPCI_BITSTREAM_VERSION 4 04 Number of digital signal generators counters timers PWM and encoders read only RTDACPCI_NO_OF_CHANNELS 8 08 Application name read only RTDACPCI_APPLICATION_NAME Counter timer 32 20 Counter index RTDACPCI_COUNTER_IDX 36 24 Load a new counter value RTDACPCI_COUNTER_LOAD 40 28 Counter value RTDACPCI_COUNTER 44 2C Timer index RTDACPCI TIMER IDX 48 30 Load a new timer value RTDACPCI_TIMER_LOAD 52 34 Timer v
25. ion read write current counter number Used bits D3 DO counter number C API function name RtdacPCI_ReadCounter I O space byte offset 36 Function reset the counter value Used bits DO when equal to 0 the counter counts input impulses When equal to 1 the current counter is set to zero C API function name RtdacPCI_ReadCounter I O space byte offset 40 Function reads the current counter value Used bits D16 DO the counter value C API function name RtdacPCI_ReadCounter I O space byte offset 44 Function read write the current timer number Used bits D3 DO the timer number C API function name RidacPCI_ReadTimer I O space byte offset 48 Function reset the timer value Used bits DO when equal to 0 the timer counts the input clock impulses When equal to 1 the current timer is set to zero C API function name RitdacPCI_ReadTimer I O space byte offset 52 Function reads the current timer value Used bits D31 DO the timer value C API function name RtdacPCI ReadTimer RT DAC4 PCI User s manual page 13 INTECO WWW 6 4 Digital I O The RT DAC4 PCI board contains 32 digital input output lines The digital I O lines are connected to the D 1 00 D 1 031 pins of the CN3 and CN4 connectors The direction of each line can be set separately The direction is determined by the value written to the I O offsets 64 and 68 The I O offset 64 determines the directi
26. le 3 Gain setting The RT DAC4 PCI board is equipped with the parallel 12 bit A D converter The A D converter control is performed by the I O offset 164 The end of conversion EOC flag is accessible at offset 164 The A D conversion results are available at I O offset 168 The A D control word offset 164 contains three signals RD D2 CS D1 and CONVST DO The low state of the CS signal is used to enable the A D converter When the CS signal is high the converter is disabled The RD signal is used to read the last A D conversion results The A D conversion starts if the rising edge of the CONVST signal occurs The conversion can be started when the CS signal is high The EOC signal available to read at I O offset 164 DO when read offset 164 detects the termination of the A D conversion When the EOC is equal to 0 the conversion results are ready to be read For example to start A D conversion of the analog input 3 set the gain to 1 and read the conversion results the following C statements can be executed _outpd BaseAddr 160 0x03 set gain and channel number _outpd BaseAddr 164 0x6 set CONVST to 0 DO set to 0 _outpd BaseAddr 164 0x7 set CONVST to 1 _outpd BaseAddr 164 0x5 set CS to 0 D1 set to 0 _outpd BaseAddr 164 0x1 set CS to 0 and RD to 0 D1 and D2 set to 0 while _inpd BaseAddr 164 amp 1 0 wait for EOC equal to 0 ADResult _inpa BaseAddr 168 read A
27. lock diagram of the RT DAC4 PCI board The board contains the analog input multiplexer connected to 16 single ended analog input channels Voltage ranges are defined from 10V to 10V bipolar The RT DAC4 PCI board includes the software programmable gain amplifier that can be configured for the voltage gains 1 2 4 8 16 to accommodate low level and high level analoge input signals Connectors digital I O Digital O PWM Encoders Interrupts AD Converter I lt Programmable gain XILINX K FPGA PLX PCI Bridge 16 channels MUX A D D A ChO gt Converters i Buffers D A Ch3 Range selection PCI Bus Fig 1 General block diagram of the RT DAC4 PCI board RT DAC4 PCI User s manual page 4 INTECO WWW The board is equipped with 12 bit successive approximation A D converters that give the 5 mV resolution within input range 10V Finer resolution can be achieved by the gain definition using gain The A D conversion time of the RT DAC4 PCI board is equal to 1 6 us This means that Troughoutput Rate is greater than 500kSPS The board contains four 12 bits D A converters connected to four analog output channels All channels can be hardware configured to operate in the unipolar or bipolar mode Each analog output channel can sink up to 10 mA T
28. mp BusNo SlotNo amp VendorID amp DevicelD amp BaseAdadress if ret 0 return RTDAC BaseAddress BaseAddress clear all interrupt requests WriteByte BaseAddress 224 0 Call API interrupt initialisation procedure if ret Intrlnit 1 lt 0 ErrorAction enable local interrupt generation and enable local timer interrupt WriteByte BaseAddress 224 0x88 set timer period to 1kHz 40000 impulses of 25ns period WriteDWord BaseAddress 232 40000 hThread CreateThread NULL no security attributes 0 use default stack size LPTHREAD_START_ROUTINE ThreadFunc thread function NULL no thread function argument 0 use default creation flags amp IDThread returns thread identifier if hThread NULL ErrorAction The body of the thread is presented below DWORD WINAPI ThreadFunc VOID HANDLE eventHandle DWORD val int IntrSource int IAux Set priority of the current process and thread optional SetPriorityClass GetCurrentProcess REALTIME_PRIORITY_CLASS SetThreadPriority GetCurrentThread THREAD_PRIORITY_TIME_CRITICAL Clear all interrupt requests and set active interrupt sources Aux ReadWord BaseAddress 0xE0 Write Word BaseAddress OxE0 0 WriteWord BaseAddress OxE0 Aux for if IntrAttach BoardNo 1 amp eventHandle lt 0 AfxMessageBox Interrupt Attach Error ErrorAction try f
29. nels relating to digital signal generators counters timers PWM and encoders the following C statements can be executed NoOfChans inpd BaseAddr 8 OxFFFFF read no of channels NoOfGenerators NoOfChans gt gt 16 amp OxF NoOfCounters NoOfChans gt gt 12 amp OxF NoOfTimers NoOfChans gt gt 8 amp OxF NoOfPWM NoOfChans gt gt 4 amp OxF RT DAC4 PCI User s manual page 11 INTECO WWW NoOfEncoders NoOfChans amp OxF or the following API functions can be called NoOfGenerators RtdacPCI ReadNoOfGenerators BaseAdar NoOfCounters RtdacPCl_ReadNoOfCounters BaseAdar NoOfTimers RtdacPCl_ReadNoOfTimers BaseAdar NoOfPWM RtdacPCI PWMNoOfChans BaseAdar NoOfEncoders RtdacPCI ReadNoOfEncoders BaseAdar Version management functions I O space byte offset 0 Function read version of FPGA bitstream Used bits D15 DO C API function name RtdacPCI_BitstreamVersion I O space byte offset 4 Function read number of digital signal generators counters timers PWM outputs and encoders Used bits D19 D16 number of generators D15 D12 number of counters D11 D8 number of timers D7 D4 number of PWM outputs D3 D0 number of encoders C API function name RtdacPCI ReadNoOfGenerators RtdacPCI ReadNoOfCounters RtdacPCI ReadNoOfTimers RtdacPCI PWMNoOfChans RtdacPCI ReadNoOfEncoders I O space byte offset 8 Function read application name Ret
30. o 1 the line is an input C API function name RtdacPCI WriteDigIOConfig RtdacPCI ReadDigIOConfig I O space byte offset 68 Function read write the directions of the D 1 016 to D 1 03 1 digital I O signals Used bits D15 DO define the directions of 16 most significant digital I O lines Each bit defines the direction of the appropriate digital line When set to 0 the line works as output when set to 1 the line is input C API function name RtdacPCI WriteDigIOConfig RtdacPCI ReadDigIOConfig I O space byte offset 72 Function read write the state of the D 1 00 to D 1 015 digital I O signals Used bits D15 D0 reads the state of 16 least significant digital inputs or sets the state of digital outputs C API function name RtdacPCI_WriteDig RtdacPCI_ReadDig I O space byte offset 76 Function read write the state of the D I 016 to D 1 03 1 digital I O signals Used bits D15 DO reads the state of 16 most significant digital inputs or sets the state of digital outputs C API function name RtdacPCI_WriteDig RtdacPCI_ReadDig RT DAC4 PCI User s manual page 14 INTECO WWW 6 5 PWM The RT DAC4 PCI board includes four output PWM channels denoted PWMO to PWM3 The base PWM period and the period of the H state of each channel are selected separately see Fig 5 The counters of the base PWM period and the H state period can work in the 12 or 8 bit mode The 8 bit mode allows PWM to
31. of the computer system The I O offsets 236 and 240 are used to define which digital inputs are considered when the change of state interrupt is generated The I O location 236 is responsible for digital signals from the CN3 connector and the location 240 is responsible for the CN4 signals Only digital signals defined as input are applied to detect the COS When the COS interrupt is generated the state of digital inputs before and after the interrupt generation moment can be read from the I O locations 244 and 248 respectively Let us configure the interrupt block to generate interrupts from all available interrupt sources The frequency of the timer interrupt will be set to 1kHz The following steps have to be performed e clear of all interrupt sources RT DAC4 PCI User s manual page 20 t h INTECO e thread creation To implement the interrupt handling procedure it is recommended to create a thread The thread operates as interrupt handling procedure e enabling required interrupt sources Setting interrupt timer period if timer interrupt source enabled To simplify the programming the basic API functions will be applied see section 7 for details The following statements perform all actions required by interrupt services HANDLE hThread ULONG IDThread char Str 200 int ret int BusNo SlotNo VendorID DevicelD BaseAddress int RTDAC_BaseAddress if NoOfDetectedBoards lt 1 return ret BoardLocation 1 a
32. on of D I O0 to D I O15 The I O offset 68 determines the direction of D 1 016 to D 1 031 When a bit of the direction control word is set to 0 the appropriate digital line is configured as output The value 1 sets the digital line as input The input lines can be read and output lines can be set by the I O offset 72 and 76 The I O offset 72 determines the state of D 1 00 to D I O15 The I O offset 68 determines the state of D 1 016 to D 1 031 For example to set lines D I O0 D 1 015 as outputs and to set D 1 016 to D I O31 as inputs set all output lines to logic state 1 and read all 16 inputs the following C statements can be executed _ outpd BaseAdar 64 0x0000 set directions of D 1 00 to D 015 _outpd BaseAdar 68 OxFFFF set directions of D 1 016 to D I O 31 _outpd BaseAdar 76 OxFFFF set all outputs to 1 Diginp _inpd BaseAdar 72 8 OxFFFF read digital inputs or the following API functions can be called RtdacPCI WriteDiglOConfig BaseAdar OxFFFFOOOO RtdacPCI WriteDiglO BaseAdar OxFFFF0000 Diginp RtdacPCI ReadDiglO BaseAdar Digital I O functions I O space byte offset 64 Function read write the directions of the D 1 00 to D 1 015 digital I O signals Used bits D15 DO define the directions of the 16 least significant digital I O lines Each bit defines the direction of the appropriate digital line When set to 0 the line works as output when set t
33. put data for the D A converter are written to the I O offset 196 The CS signal enables the D A converter The data movement controlled by the LDAC signal can be performed even if CS is disabled To set a new output voltage equivalent to the digit 1500 at the D A channel 2 the following C statements can be executed _outpd BaseAddr 192 0x14 set A1A0 to 10 2 LDAC to 1 R W to 0 and CS to 0 _outpd BaseAdar 196 1500 set data to the D A buffer Update D A converter the new analog voltage will appear _outpd BaseAdar 192 0x11 set A1A0 to 10 2 LDAC to 0 RW to 0 and CS to 1 outpd BaseAdar 192 0x15 set A1A0 to 10 2 LDAC to 1 R W to 0 and CS to 1 or the following API function can be called RtdacPCI DA BaseAdar 2 1500 D A converter functions I O space byte offset 192 Function writes the D A converter control signals Used bits D4 D3 the Al and AO signals D2 the LDAC signal D1 the R W signal DO the CS signal RT DAC4 PCI User s manual page 19 INTECO WWW C API function name RtdacPCI DA I O space byte offset 196 Function sets D A data Used bits D11 D0 data for the D A converter C API function name RtdacPCI DA 6 10 Interrupts The RT DAC4 PCI board is able to generate the INTA PCI interrupt The parameters of the interrupts are set in two I O locations The first one is the internal PLX
34. ro INtelligent TEchnology for COntrol AAA E mail inteco inteco com pl RT DAC4 PCI Multi I O Board Board version 1 11 User s Manual Krak w 2013 INTECO viv Table of contents 1 GENERAL INFORMATION sc cssssssscisscccscesssscacessescecescouessessestacoceovsecesosscdsecsevesdossessocessosveseeseccesessosseccassscesess 3 1 1 TINTER ODUG TION ES 3 1 2 SPECIFICA MON aaa 3 2 BOARD INSTALLATION besscssccssessesssscctecocsecsssessecsecoscetcesaseccssesvesoscenbessesessacsssoesessecesbeuseeeabenss dessecdecsasesssess 6 3 DRIVER INSTALLATION sscssiccscsossciscosccccssvoscesscssescsccssteoscesccs coscsosccccsssscsvscesuccuececocscesecovecescsessecvecsansessscss 6 3 1 INSTALLATION iii 6 4 JUMPER SETTINGS AS ceca cesbscunsecocecsanovsctascsocseecssvdcnssecesecssusseudeecsoecoscsdsovesesessves 7 4 1 OUTPUT RANGE SELECTION J P is 7 4 2 DIP SWITCHES FOR FPGA PROGRAMMING errrvrvrvrervrerererererererererererererererererererererererererererererererererereverererere 7 5 CONNECTOR PIN ASSIGNMENT S essessesssessssnnvnvnnesessnnnnnnnenssnnsnnnnnnennenessnnnennennnnnnennnnnnvnnenssensnnnnnnensenennnne 8 6 REGISTER STRUCTURE AND FORMAT eesovevvvevesessnnnvnvenssensnnnnnnennenessnnnsnnennnsenensnnnnnnnenssensnnnnnnensenennnne 9 6 1 BEFORE USING A C API FUNCTIONS wes cccevesvsceovsctecursesvcceevscbscusresveceeteatecustessccbenvebscusvenveceenvetecustesvecbersebecs 10 6 2 VERSION MANAGEMENT eins 11 6 3 COUNTER TIMER di 13 6 4 A en
35. rrupt is caused by the COS interrupt source D1 value of 1 indicates that the current PCI interrupt is caused by the ExtInt1 interrupt source DO value of 1 indicates that the current PCI interrupt is caused by the ExtInt0 interrupt source RtdacPCI_ ReadIntrStatus read write period of the interrupt timer D27 DO define the period of the interrupt timer The period is defined in units equal to 25ns RtdacPCIL WritelntrPeriod RitdacPCI_ReadIntrPeriod read write COS mask D15 DO defines which inputs from the CN3 connector are used to detect change of state and to generate the interrupt Value of 1 means that the respective signal is applied to generate the COS interrupt Value of 0 means that the respective signal does not influence the COS block RtdacPCI_ReadIntrCOSMask RtdacPCI_WriteIntrCOSMask read write COS mask D15 D0 defines which inputs from the CN4 connector are used to detect change of state and to generate the interrupt Value of 1 means that the respective signal is applied to generate the COS interrupt Value of 0 means that the respective signal does not influence the COS block RtdacPCI ReadIntrCOSMask RtdacPCL WritelntrCOSMask read COS before state D31 DO reads which state at the CN3 and the CN4 connectors was active immediately before the COS generation The D31 D16 bits store the state of the CN4 and the D15 DO bits store the state of the CN3 connector RtdacPCI ReadIntrCOSBefore read
36. sed 1 2 closed 4 5 closed 2 3 closed 4 5 closed All others N A 4 2 Dip switches for FPGA programming The SW1 and SW2 switches allow a user to choose a programming method of XILINX FPGA If you are using the default XILINX FPGA configuration do not change the settings of these switches The default settings are defined as follows Dipswitch Settings Dipswitch Settings SWI SW2 SW1l 1 close SW2 1 Open SWI 2 close SW2 2 Open SW1 3 close SW2 3 Open SW1 4 open SW2 4 Open RT DAC4 PCI User s manual page 7 t b INTECO 5 CONNECTOR PIN ASSIGNMENTS RT DAC4 PCI is equipped with two 20 pin I O connectors CN1 CN2 accessible from the rear bracket and four 20 pin I O connectors CN3 CN4 CN5 and CN6 on the board see Fig 3 Fig 4 shows the pin assignment of each connector CNI A O GNDA All 1 GND A A I Analog Input AE ENDE GND A Analog Ground All4 GND A ANS GND A ANG GND A ANZ GND A A 8 GNDA A 9 GNDA CN2 A N 10 GNDA A 11 GND A A 12 GND A A I Analog Input Al 13 GND A A O Analog Output All 14 GND A A 115 GND A A O 0 GNDA A O 1 GNDA A O 2 GND A A O 3 GNDA CN3 Doo 100 DVO1 DIO2 30 04 D103 D I O Digital Input Output DOT pou EL gt DVO6 70 08 DVO7 GND Digital ground Dos 90 010 DIOS DIO 10 110 012 DVO11 DO 12 130 014 DIO 13 DIO 14
37. tal signal generators The RT DAC4 PCI board includes two outputs of digital signal generators denoted as GENO and GENI The output waves are generated on the basis of the default 40 MHz frequency wave signal The software sets the durations of the L and H states of the generated waves independently To set the correct output wave the channel number must be selected by setting an appropriate value to the I O space offset equal to 112 The I O offset equal to 116 sets the duration of the L state and the I O offset equal to 120 sets the duration of the H state of the generated output For example to set the GENI to generate the wave kept at the L state 100 time periods of the base wave long and kept at the H state 300 time periods long the following C statements have to be executed _outpd BaseAdar 112 1 select GEN1 channel _outpd BaseAdar 116 100 set duration of the L state _outpd BaseAdar 120 300 set duration of the H state or the following API function can be called RtdacPCl_WriteGeneratorL BaseAdar 1 100 RtdacPCI WriteGeneratorH BaseAdar 1 300 If the base wave frequency on the board is 40MHz then GENI generates the 100kHz wave with the duty cycle equal to 75 Digital signal generator functions I O space byte offset 112 Function Used bits C API function name I O space byte offset 116 Function Used bits C API function name I O space byte offset 120 Function Used bits
38. unts internal clock signal frequency depends on a current version of the board Digital Signal Generator Channels 2 Resolution 28 bits of the H state 28 bits of the L state Max frequency 20 MHz Duty cycle Software configurable RT DAC4 PCI User s manual page 3 WWW INTECO PWM Outputs Channels 4 Resolution 8 12 bits software selected Base Frequency programmable depends on a current version of the board Incremental encoders Channels 4 Output 32 bit counter Interrupts PCI interrupt INTA Interrupt sources 2 external inputs software timer arbitrary change of state Pulse width 25ns min generating COS interrupt PCI features Supports PCI v2 2 compliant Supports both version of PCI slots 3 3V and 5V and can work with all computers equipped with PCI buses Digital section with the default FPGA chip configuration Software support The included Testing Software allows initial tests of the board under Windows 95 98 NT 2000 Advanced users can access all the functions of the board using the standard programming languages supported with optionally included DLL library The board is compatible with the RT CON real time development toolbox distributed by INTECO The toolbox integrates input output RT DAC4 PCI board capabilities to MATLAB Simulink functionality and creates an ideal design and application environment Fig 1 presents the b
39. urns four characters logic name Used bits D31 DO C API function name RtdacPCI AppName RT DAC4 PCI User s manual page 12 INTECO WWW 6 3 Counter timer RT DACA PCI includes 32 bit timer and 16 bit channels counter The channel timer counts pulses of the internal board clock The frequency of the clock depends on the board version 40 MHz is the default value The channel counter counts external pulses To access the appropriate timer or counter the channel must be selected by setting an appropriate value to the I O offset The offset equal to 32 is used for counters the offset 44 is used for timers The I O offset equal to 36 is used to reset counters The I O offset equal to 48 is used to reset timers The I O offset 40 is used to read current counter value The I O offset 52 is used to read current timer value For example to reset timer O and start counting of the internal clock impulses the following C statements can be executed outpd BaseAdar 44 0 select timer 0 _outpd BaseAdar 48 1 reset current timer _outpd BaseAdar 48 0 return to counting mode TmrValue inpd BaseAdadr 52 read current timer value or the following API functions can be called RtdacPCI ResetTimer BaseAdar 0 1 reset timer 0 RtdacPCI ResetTimer BaseAdar 0 0 set timer 0 to counting mode TmrValue RtdacPCl_ReadTimer BaseAdar 0 Counter timer functions I O space byte offset 32 Funct
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