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RocketIO™ Transceiver User Guide

1. Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D16 3 01 0000 011011 0011 100100 1100 D17 3 01 000 00011 1100 000 00 D18 3 01 0010 010011 1100 0100 00 D19 3 01 001 10010 1100 0010 00 D20 3 01 0100 001011 1100 0010 00 D21 3 01 010 01010 1100 01010 00 D22 3 01 0110 011010 1100 011010 00 D23 3 01 011 11010 001 000101 00 D24 3 01 1000 10011 001 001100 00 D25 3 01 100 00110 1100 100110 00 D26 3 01 1010 010110 1100 010110 00 027 3 01 101 10110 001 00100 00 028 3 01 1100 001110 1100 00 0 00 029 3 01 110 01110 001 01000 00 030 3 01 1110 011110 001 10000 00 031 3 01 111 01011 001 010100 00 D0 4 100 00000 00111 0010 011000 0 D1 4 100 00001 011101 0010 00010 0 D2 4 100 00010 01101 0010 010010 0 D3 4 100 0001 10001 110 0001 0010 D4 4 00 00100 10101 0010 001010 0 D5 4 00 0010 01001 110 01001 0010 D6 4 00 00110 011001 110 011001 0010 07 4 00 001
2. Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D19 0 000 1001 10010 101 10010 0100 D20 0 000 10100 001011 101 001011 0100 D21 0 000 1010 01010 101 01010 0100 D22 0 000 10110 011010 101 011010 0100 D23 0 000 1011 11010 0100 000101 10 D24 0 000 11000 10011 0100 001100 10 D25 0 000 1100 00110 101 100110 0100 D26 0 000 11010 010110 101 010110 0100 D27 0 000 1101 10110 0100 00100 0 D28 0 000 11100 001110 101 00 0 0100 D29 0 000 1110 01110 0100 01000 0 D30 0 000 11110 011110 0100 10000 0 D31 0 000 1111 01011 0100 010100 10 D0 1 001 00000 00111 100 011000 100 D1 1 001 0000 011101 100 00010 100 D2 1 001 00010 01101 100 010010 100 D3 1 001 0001 10001 100 000 00 D4 1 001 00100 10101 100 001010 100 D5 1 001 0010 01001 100 0100 00 D6 1 001 00110 011001 100 01100 00 D7 1 001 0011 11000 100 000 00 D8 1 001 01000 11001 100 000110 100 D9 1 001 0100 00101 100 011010 100 D10 1 001 01010 010101 100 01010 00 D11 1 001 0101 10100 100 0100 100
3. Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D18 5 01 01010 010011 1010 0100 010 D19 5 0 001 10010 1010 0010 1010 D20 5 0 0100 001011 1010 0010 010 D21 5 0 010 01010 1010 01010 1010 D22 5 0 0110 011010 1010 011010 1010 D23 5 0 011 11010 1010 000101 1010 D24 5 0 1000 10011 1010 001100 1010 D25 5 0 100 00110 1010 100110 1010 D26 5 0 1010 010110 1010 010110 1010 D27 5 0 101 10110 1010 00100 010 D28 5 0 1100 001110 1010 00 0 1010 D29 5 0 110 01110 1010 01000 010 D30 5 0 1110 011110 1010 10000 010 D31 5 0 111 01011 1010 010100 1010 D0 6 10 00000 00111 0110 011000 0110 D1 6 10 00001 011101 0110 00010 0110 D2 6 10 00010 01101 0110 010010 0110 D3 6 10 0001 10001 0110 0001 0110 D4 6 10 00100 10101 0110 001010 0110 D5 6 10 0010 01001 0110 01001 0110 D6 6 10 00110 011001 0110 011001 0110 D7 6 10 0011 11000 0110 000 0110 D8 6 10 01000 11001 0110 000110 0110 D9 6 10 0100 00101 0110 011010 0110 D10 6 10 01010 010101 0110 010101 0110 D11 6 10 0101 10100 0110 0100 0110 D12 6 10 01100 001101 0110 001101 0110 D13 6 10 0110 01100 0110 01100 0110 D14 6 10 01110 011100 0110 011100 0110 D15 6 10 0111 010111 0110 01000 0110 D16 6 10 10000 011011 0110 00100 0110 D17
4. 70 RXLOSSOFSYNC FSM 75 Channel Bonding 76 CRC Packet Format nas socer Pepe pa Mie eee esed 81 USER MODE FIBRE CHAN Mode 83 Ethernet Mode Robb ead 83 Infiniband eer DER DER shuwa 84 Local Route Header ecnin nesen tiese concen Up rhe 85 Serial and Parallel Loopback 89 RXDATA Aligned Correctly 90 Realignment 91 Chapter 3 Analog Design Considerations Figure 3 1 Differential 99 Figure 3 2 Alternating K28 5 with No Pre Emphasis 101 RocketlO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 11 XILINX Figure 3 3 K28 5 with 5 101 Figure 3 4 Eye Diagram 10 Pre Emphasis 20 FR4 Worst Case Conditions 102 Figure 3 5 Eye Diagram 33 Pre Emphasis 20 FR4 Worst Case Conditions 102 Figure 3 6 Power Supply Circuit Using LT1963 Regulator 105 Figure 3 7 Power Filtering Network for On
5. Attribute Default Default Default GT AURORA GT CUSTOM GT ETHERNET TX DATA WIDTH NO 2 NO TX DIFF CTRL 5000 500 5000 TX_PREEMPHASIS 00 0 00 Notes 1 All GT CUSTOM attributes are modifiable 2 Modifiable attribute for specific primitives 3 Depends on primitive used either 1 2 or 4 4 Attribute value only when RX_DATA_WIDTH is 4 When RX_DATA_WIDTH is 1 or 2 attribute value is 2 5 Attribute value only when RX_DATA_WIDTH is 4 When RX_DATA_WIDTH is 1 or 2 attribute value is 0 6 CRC_EOP and CRC_SOP are not applicable for this primitive Table 1 8 Default Attribute Values GT_FIBRE_CHAN GT_INFINIBAND and GT_XAUI Attribute Default Default Default GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI ALIGN_COMMA_MSB FALSE FALSE FALSE CHAN_BOND_LIMIT 1 16 16 CHAN_BOND_MODE OFF OFF OFF CHAN_BOND_OFFSET 0 8 8 CHAN_BOND_ONE_SHOT TRUE FALSE 0 FALSE CHAN BOND SEQ 1 1 00000000000 00110111100 00101111100 CHAN BOND SEQ 1 2 00000000000 Lane ID Modify with 00000000000 Lane ID CHAN BOND SEQ 1 3 00000000000 00001001010 00000000000 CHAN BOND SEQ 1 4 00000000000 00001001010 00000000000 CHAN BOND SEQ 21 00000000000 00110111100 00000000000 CHAN BOND SEQ 2 2 00000000000 Lane ID Modify with 00000000000 Lane ID CHAN BOND SEQ 2 3 00000000000 00001000101 00000000000 CHAN BOND SEQ 2 4 00000000000 00001000101 00000000000 CHAN BOND SEQ 2 USE FALSE TRUE FALSE CHAN BOND SEQ LEN 1 4 1 CHAN BOND WAIT 7 8 8 CLK COR INSERT IDLE FLAG F
6. Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D17 2 010 1000 00011 010 000 010 D18 2 010 01010 010011 010 0100 010 D19 2 010 1001 10010 010 10010 010 D20 2 010 10100 001011 010 0010 010 D21 2 010 1010 01010 010 01010 010 D22 2 010 10110 011010 010 011010 010 D23 2 010 1011 11010 010 000101 010 D24 2 010 11000 10011 010 001100 010 D25 2 010 1100 00110 010 100110 010 D26 2 010 11010 010110 010 010110 010 D27 2 010 1101 10110 010 001001 010 D28 2 010 11100 001110 010 00 0 010 D29 2 010 1110 01110 010 010001 010 D30 2 010 11110 011110 010 100001 010 D31 2 010 1111 01011 010 010100 010 D0 3 011 00000 00111 001 011000 00 D1 3 011 0000 011101 001 00010 00 D2 3 011 00010 01101 001 010010 00 D3 3 011 0001 10001 1100 0001 00 D4 3 011 00100 10101 001 001010 00 D5 3 011 0010 01001 1100 01001 00 D6 3 011 00110 011001 1100 011001 00 D7 3 011 0011 11000 1100 000 00 D8 3 011 01000 11001 0011 000110 1100 D9 3 011 0100 00101 1100 011010 00 D10 3 011 01010 010101 1100 010101 00 D11 3 011 0101 10100 1100 0100 00 D12 3 011 01100 001101 1100 001101 00 D13 3 011 0110 01100 1100 01100 00 D14 3 011 01110 011100 1100 011100 00 D15 3 01 0111 010111 0011 01000 1100 132 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Valid Data Characters XILINX
7. Horizontal ellipsis Repetitive material that has allow block block name been omitted loci loc2 locn Online Document The following conventions are used in this document Convention Meaning or Use Example See the section Additional Cross reference link to a Resources for details Blue text location in the current m document Refer to Title Formats in Chapter 1 for details Pad dad Cross reference link to a See Figure 2 5 in the Virtex II location in another document Handbook Go to http www xilinx com Blue underlined text Hyperlink to a website URL for the latest speed files www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 lt XILINX Chapter 1 RocketIO Transceiver Overview Basic Architecture and Capabilities The RocketIO transceiver is based on Mindspeed s SkyRail technology Figure 1 1 page 20 depicts an overall block diagram of the transceiver Up to 24 transceiver modules are available on a single Virtex II Pro FPGA depending on the part being used Table 1 1 shows the RocketIO cores available by device Table 1 1 Number of RocketlO Cores per Device Type RocketlO RocketlO Device Device Cores Cores Cores XC2VP2 4 XC2VP30 8 XC2VP100 0 or 20 XC2VP4 4 XC2VP40 0 or 12 XC2VP125 0 20 or 24 XC2VP7 8 XC2VP50
8. will signal when either comma character is received COMMA 10B MASK PCOMMA 10B VALUE MCOMMA 10B VALUE The RocketIO transceiver allows the user to define a comma character using these three attributes The 10B MASK bits are used in conjunction with PCOMMA 10B VALUE to define a plus comma or MCOMMA 10B VALUE to define a minus comma to define some number of recognized comma characters High bits in the mask condition the corresponding bits in 10B VALUE or 10 VALUE to matter while Low bits in the mask function as a don t care conditioner For example with COMMA 10B MASK set to 1111111000 meaning the three least significant bits don t matter and PCOMMA 10B VALUE is 0011111000 the comma detection unit will recognize the following characters as plus commas 0011111000 K287 0011111001 K28 1 0011111010 K28 5 0011111011 through 0011111111 not valid comma characters Using the same value in 10B VALUE but setting 10B MASK to 1111111111 meaning all the bits in PCOMMA 10B VALUE matter the comma detection unit will recognize only the 0011111000 K28 7 sequence which matches the value of PCOMMA 10B VALUE exactly DEC PCOMMA DETECT DEC MCOMMA DETECT DEC VALID COMMA ONLY These signals only pertain to the 8B 10B decoder not the comma alignment circuitry The DEC DETECT and DEC DETECT control the 8B 10B decoder to
9. E ERA us sana 75 RXTLOSSOFSYING detente hate woh dee PES PEE ERE 75 Channel Bonding Channel Alignment 76 uyay nec Bake Sus atus a kuka nh ele Ea deca een ar ad ugh aa 76 Channel Bonding Alignment Operation 77 Ports and Ati butes a ede station un dees eae dc eg dus 78 CHAN_BOND_MODE eie i aida EE E Ea E eee eee n 78 c upo uk e u eee took dec cele E 78 CHAN BOND ONE 5 78 CHAN_BOND_SEQ _ CHAN BOND SEQ LEN CHAN BOND SEQ 2 USE ie teess ie Tiis eet na teer mad er a esie Mie eei qala a 79 CHAN BOND WAIT CHAN BOND OFFSET CHAN BOND LIMIT echter den ee eed ae ee 79 CHBONDDONE Pr e e Mth fee ta cette tee 80 CHBONDI CHBONDOS TFT 80 RXCLKCORCNT RXEOSSOESYING 55 dere eens tem dates E Mea desta 80 Troubleshooting Ep po tpe Ded eei ede eod cee 80 CRC Cyclic Redundancy 81 Overview ere bae aerae eee eer ea es 81 CRE Operations dete det 81 CRC Generation road er aska er he e Rai dae dere a aes 81 GRE Latency 5223 81 Po
10. SERDES 10B Serial Baud Rate FALSE 1 0 Gbps 3 125 Gbps TRUE 600 Mbps 1 0 Gbps PACKAGE PINS MULTI GIGABIT TRANSCEIVER CORE FPGA FABRIC RXRECCLK RXPOLARITY RXREALIGN RXCOMMADET ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC RXCRCERR RXDATA 15 0 RXDATA 31 16 RXP RXNOTINTABLE 3 0 RXN Comma i RXDISPERR 3 0 Deserializer Detect RXCHARISK 3 0 Realign Decoder RXCHARISCOMMA 3 0 RXRUNDISP 3 0 RXBUFSTATUS 1 0 ENCHANSYNC CHBONDDONE CHBONDI 3 0 CHBONDO 3 0 RXLOSSOFSYNC gt TXBUFERR TXFORCECRCERR TXDATA 15 0 TXDATA 31 16 i TXBYPASSS8B10B 3 0 TXCHARISK 3 0 dd TXCHARDISPMODE 3 0 TXN Serializer Output Polarity XCHARDISPVAL 3 0 TXKERR 3 0 TXRUNDISP 3 0 TXPOLARITY TXINHIBIT LOOPBACK 1 0 TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLK 2 5V TX BREFCLK2 RXUSRCLK Termination Supply TX RXUSRCLK2 TXUSRCLK TXUSRCLK2 VTBX Termination Supply RX Channel Bonding and Clock Correction Serial Loopback Path Parallel Loopback Path GNDA rx Rx GND AVCCAUXTX VTTX DS083 2 04 090402 Figure 1 1 RocketlO Transceiver Block Diagram 20 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 RocketlO Transceiver Instantiations XILINX Table 1 4 lists the sixteen gigabit trans
11. counter is set to a high value whenever the elastic buffer is reinitialized that is upon asserted RXRESET or RXREALIGN Count down is enabled whenever a comma is known to have come through the comma detection circuit that is upon an asserted RXREALIGN or RXCOMMADET always posedge usrclk2 begin if rxreset begin wait to sync lt 4 b1111 count lt 1 b0 end else if rxrealign begin wait to sync lt 4 b1111 count lt 1 b1 end else begin if count amp amp wait to sync 4 b0000 wait to sync lt wait to sync 4 b0001 if rxcommadet count lt 151 end end This process maintains output sync which indicates when outgoing aligned data should be properly aligned with the comma in aligned data 31 24 Output aligned data is considered to be in sync when a comma is seen on rxdata as indicated by rxchariscomma3 or 1 after the counter wait to sync has reached 0 indicating that commas seen by the comma detection circuit have had time to propagate to aligned data after initialization of the elastic buffer always posedge usrclk2 begin if rxreset rxrealign sync 1 b0 else if wait to sync 4 b0000 6 rxchariscomma3 rxchariscommal sync lt 1 1 end RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 93 1 800 255 7778 7 XILINX Chapter 2 Digital Design Considerations This
12. RocketIO transceiver does not compute the 16 bit variant CRC used for Infiniband and thus does not fulfill the Infiniband CRC requirement Infiniband CRC can be computed in the FPGA fabric AIL CRC formats have minimum allowable packet sizes These limits are larger than those set by the user mode and are defined by the specific protocol Fabric Interface Buffers Overview Transmitter and Elastic Receiver Buffers Both the transmitter and the receiver include buffers FIFOs in the data path This section gives the reasons for including the buffers and outlines their operation Transmitter Buffer FIFO The transmitter buffer s write pointer TXUSRCLK is frequency locked to its read pointer Therefore clock correction and channel bonding are not required The purpose of the transmitter s buffer is to accommodate a phase difference between TXUSRCLK and REFCLK Proper operation of the circuit is only possible if the FPGA clock TXUSRCLK is frequency locked to the reference clock REFCLK Phase variations of up to one clock cycle are allowable A simple FIFO suffices for this purpose A FIFO depth of four permits reliable operation with simple detection of overflow or underflow which might occur if the clocks are not frequency locked Overflow or underflow conditions are detected and signaled at the interface Receiver Buffer The receiver buffer is required for two reasons To accommodate the slight diff
13. This must be done for each MGT Figure 2 17 shows this recommendation GT std PCOMMA CONTROL ENPCOMMAALIGN RXRECCLK MCOMMA CONTROL ENMCOMMAALIGN UGO024 39 013103 Figure 2 17 Synchronizing Comma Align Signals to RXRECCLK www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 SERDES Alignment XILINX Figure 2 18 and Figure 2 19 show floorplanner layouts for the two examples given above HH 11 11 54 44 3H 1 6 F 1 6 D 1 7 asg G 1 5 a g wen m m 7 0 a p ug024_43_031303 Figure 2 18 Top MGT Comma Control Flip Flop Ideal Locations Y 1 5 as Y 1 a atg AAAA DGAA 1111 1 8867 7 0 m m gt A D 1 5 m Q gt m m gt y gt ug024_44_031303 Figure 2 19 Bottom MGT Comma Control Flip Flop Ideal Locations RocketlO Transceiver User Guide www xilinx com 67 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations PCOMMA_DETECT MCOMMA_DETECT These two control attributes define when signals that comma has been received When only PCOMMA DETECT is TRUE RXCOMMADET signals when a plus comma is received but not a minus comma When only MCOMMA DET is TRUE RXCOMMADET signals when a minus comma is received but not a plus comma If both attributes are TRUE
14. VTRX supplies The ferrite beads are mounted at the sixteen L n locations the capacitors are mounted at the sixteen C n locations Figure 3 11 shows the bottom PCB layer with lands for the capacitors and ferrite beads of the AVCCAUXTX and AVCCAUXRX supplies The ferrite beads are mounted at the sixteen L n locations the capacitors are mounted at the sixteen C n locations Siw wie wie wie wie wie wie wie wv wie wie wie wie wie wie wie uw ug024_041_022403 Figure 3 10 Example Power Filtering PCB Layout for Eight MGTs Top Layer ug024 042 022403 Figure 3 11 Example Power Filtering PCB Layout for Eight MGTs Bottom Layer All AVCCAUXTX and AVCCAUXRX pins in a Virtex II Pro device must be connected to 2 5 V regardless of whether or not they are used See Powering the RocketIO Transceivers and Ihe POWERDOWN Port page 113 for details www xilinx com RocketlO Transceiver User Guide 108 1 800 255 7778 06024 v2 2 November 7 2003 PCB Design Requirements XILINX High Speed Serial Trace Design Routing Serial Traces All RocketIO transceiver I Os are placed on the periphery of the BGA package to facilitate routing and inspection since JTAG is not available on serial I O pins Two output input impedance options are available in the RocketIO transceivers 500 and 750 Controlled impedance traces with a corresponding impedance should be used to connect the RocketIO transceiver to other
15. 48 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Clocking XILINX Components Declarations component BUFG port in std_logic O out std logic end component component IBUFG port I in std logic out std logic component component DCM port CLKIN in std_logic CLKFB in std_logic DSSEN in std_logic PSINCDEC in std_logic PSEN in std_logic PSCLK in std_logic RST in std_logic CLKO out std_logic CLK90 out std_logic CLK180 out std logic CLK270 out std logic CLK2X out std logic CLK2X180 out std logic CLKDV out std logic CLKFX out std logic CLKFX180 out std logic LOCKED out std logic PSDONE out std logic STATUS out std logic vector end component Signal Declarations signal GND std_logic signal CLK0_W std_logic signal CLK2X180_W std_logic signal USRCLK2 M W std logic signal USRCLK M W std logic begin GND lt 0 USRCLK2 M USRCLK2 M W USRCLK M lt USRCLK M W DCM Instantiation U DCM DCM port map CLKIN gt EFCLK 7 downto 0 RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 49 XILINX Chapter 2 Digital Design Considerations gt USRCLK_M DSSEN gt GND PSINCDEC gt GND PSEN
16. 8 0 BB9 BB8 BB7 13 12 BB6 BB11 BB10 GT_X8_Y1 9 8 A7 A13 A12 11 10 9 0 AW7 AW6 BB5 BB4 BB3 BB9 BB8 BB7 AW5 AW4 BB2 BB6 GT_X9_Y1 A7 A6 5 4 5 4 2 9 8 7 10 0 BB5 BB4 BB3 BB2 GT_X10_Y1 A5 A4 A3 A2 GT_X11_Y0 GT X11_Y1 RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 119 XILINX Chapter 4 Simulation and Implementation 120 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 lt XILINX Appendix A RocketIO Transceiver Timing Model This appendix explains all of the timing parameters associated with the RocketIO transceiver core It is intended to be used in conjunction with Module 3 of the Virtex II Pro Data Sheet and the Timing Analyzer TRCE report from Xilinx software For specific timing parameter values refer to the data sheet There are many signals entering and exiting the RocketIO core Refer to Figure A 1 The model presented in this section treats the RocketIO core as a black box Propagation delays internal to the RocketIO core logic are ignored Signals are characterized with setup and hold times for inputs and with clock to valid output times for outputs There are five clocks associated with the RocketIO core but only three of these clocks RXUSRCLK RXUSRCLK2 and TXUSRCLK2 have I O
17. These two signals determine how fast an invalid character advances the RXLOSSOFSYNC FSM counter before loss of sync is considered to have occurred RX_LOS_INVALID_INCR determines how quickly the occurrence of invalid characters is forgotten in the presence of subsequent valid characters For example RX_LOS_INVALID_INCR 4 means that four consecutive valid characters after an invalid character will reset the counter RX_LOS_THRESHOLD determines when the counter has reached the point where the link is considered to be out of sync RX_LOSS_OF_SYNC_FSM The transceiver s FSM is driven by RXRECCLK and uses status from the data stream prior to the elastic buffer This is intended to give early warning of possible problems well before corrupt data appears on RXDATA LOSS SYNC FSM a TRUE FALSE attribute indicates what the output of the RXLOSSOFSYNC port see below means RXLOSSOFSYNC If RX LOSS OF SYNC FSM FALSE then RXLOSSOFSYNC 1 High indicates that the transceiver has received an invalid character and RXLOSSOFSYNC 0 High indicates that a channel bonding sequence has been recognized If RX LOSS OF SYNC FSM TRUE then the two bits of RXLOSSOFSYNC reflect the state of the RXLOSSOFSYNC FSM The state machine diagram in Figure 2 21 and the three subsections following describe the three states of the RXLOSSOFSYNC FSM SYNC ACQUIRED count RX LOS THRESHOLD count RX LOS THRESHOLD valid
18. Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 23 1 800 255 7778 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 5 GT_CUSTOM GT AURORA GT FIBRE 2 GT ETHERNET O GT INFINIBAND and GT XAUI Primitive Ports Continued Port RXN 1 0 I Port Size 1 Definition Serial differential port FPGA external RXNOTINTABLE 9 O 1 2 4 Status of encoded data when the data is not a valid character when asserted High Applies to the byte mapping scheme Serial differential port FPGA external RXPOLARITY Similar to TXPOLARITY but for RXN and RXP When de asserted assumes regular polarity When asserted reverses polarity RXREALIGN Signal from the PMA denoting that the byte alignment with the serial data stream changed due to a comma detection Asserted High when alignment occurs RXRECCLK Clock recovered from the data stream by dividing its speed by 20 RXRESET Synchronous RX system reset that recenters the receive elastic buffer It also resets 8B 10B decoder comma detect channel bonding clock correction logic and other internal receive registers It does not reset the receiver PLL RXRUNDISP 1 2 4 Signals the running disparity 0 negative 1 positive in the received serial data If 8B 10B encoding is bypassed it remains as the second bit received Bit b of the 10 bit encoded data see
19. uuu Ere HCM edle E 17 Online Document lese rr res 18 Chapter 1 RocketlO Transceiver Overview Basic Architecture and 19 RocketIO Transceiver Instantiations 21 HDL Code Examples sv ama cage eres rex e pb Ed eta eg eta 21 List of Available Ports 22 Primitive Attributes 26 Modifiable Primitives 31 byte Mapping 35 Chapter 2 Digital Design Considerations MDC a7 Clock Signals i s ertet pe petes 37 juges dq 38 Clock Ratio oreste messa M EL ATEM UE 40 Digital Clock Manager DCM 40 Example 1a Two Byte Clock with DCM 41 Example 1b Two Byte Clock without DCM 44 Example 2 Four Byte 44 Example 3 One Byte 48 Half Rate Clocking Scheme 52 Multiplexed Clocking Scheme with DCM 53 Multiplexed Clocking Sche
20. with subscript string defining the timing relationship SIGNAL name of RocketIO signal synchronous to the clock ParameterName Format Setup time before clock edge Hold time after clock edge where x C Control inputs D Data inputs Setup Hold Time Examples Tacceg RRST Tgege RRST Setup hold times of RX Reset input relative to rising edge of RXUSRCLK2 Setup hold times of TX Data inputs relative to rising edge of TXUSRCLK2 Clock to Output Delays Basic Format ParameterName_SIGNAL where ParameterName T with subscript string defining the timing relationship SIGNAL name of RocketIO signal synchronous to the clock ParameterName Format Delay time from clock edge to output where x CO Control outputs DO Data outputs ST Status outputs Output Delay Time Examples Rising edge of RXUSRCLK to Channel Bond outputs Tacgpo RDAT Rising edge of RXUSRCLK2 to RX Data outputs _ Rising edge of TXUSRCLK2 to TX Buffer Err output RocketlO Transceiver User Guide www xilinx com 123 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Appendix RocketlO Transceiver Timing Model Clock Pulse Width ParameterName Format Minimum pulse width High state Minimum pulse width Low state where x REF REFCLK TX TXUSRCLK TQ TXUSRCLK2 RX R
21. See Figure 2 10 However the transceiver must still be reset when clocks are switched IBUFGDS REFCLK_P GT_std_2 REFCLK_N REFCLK2_P REGENS REFCLK2 REFCLKSEL REFCLKSEL TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK REFCLK2 N BUFGMUX 00024 05b 021503 Figure 2 10 Multiplexed REFCLK without DCM RocketlO Transceiver User Guide www xilinx com 53 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations RXRECCLK is a recovered clock derived by dividing by 20 the received data stream bit rate whether full rate or half rate If clock correction is bypassed it is not possible to compensate for differences in the clock embedded in the received data and the REFCLK created USRCLKs In this case is used to generate the RXUSRCLKs as shown in Figure 2 11 0 1 REFCLKSEL REFCLK TXUSRCLK TXUSRCLK2 IBUFGDS RXUSRCLK RXUSRCLK2 RXRECCLK 06024 38 112202 Figure 2 11 Using RXRECCLK to Generate RXUSRCLK RXUSRCLK2 Note Bypassing the RX elastic buffer is not recommended as the skew created by the DCM and routing to global clock resources is uncertain and may cause unreliable performance Clock Dependency All signals used by the FPGA fabric to interact between user logic and the transceiver depend on an edge of USRCLK2 These signals all have setup and hold times with respect to this clock For specific ti
22. TX CRC FORCE VALUE 85 TX CRC USE 82 TX DATA WIDTH 87 TX DIFF CTRL 88 Attributes table 26 BREFCLK and REF CLK V SEL 29 39 and REFCLKSEL 23 39 and serial speed 37 pin numbers 39 when amp how to use 38 Buffers Fabric Interface 86 ports and attributes 86 transmitter and elastic receiver 86 Byte Mapping 35 C Channel Bonding Alignment 76 operation 77 ports and attributes 78 troubleshooting 80 Vitesse channel bonding sequence receive 63 transmit 62 Characters valid tables 129 Clock Correction Recovery clock recovery 70 overview 69 ports and attributes 71 Clock Data Recovery CDR parameters 103 Clocking 37 clock and data recovery 70 clock correction recovery 69 clock dependency 54 clock descriptions 121 clock pulse width 124 clock ratio 40 clock recovery 70 clock signals 37 clock synthesizer 69 clock to output delays 123 code examples 1 byte clock 48 2 byte clock 41 4 byte clock 44 half rate clocking scheme 52 multiplexed clocking scheme with DCM 53 without DCM 53 Control Characters valid table 137 Coupling AC and DC 111 CRC Cyclic Redundancy Check 81 D generation 81 latency 81 operation 81 ports and attributes 82 support limitations 85 Data Characters valid table 129 Deserializer 65 Deterministic Jitter DJ 103 Differential Receiver 103 Differential Trace Design 109 H Half Rate Clocking Scheme 52 HDL Code Examples Verilog 1 by
23. e Appendix A RocketIO Transceiver Timing Model Timing parameters associated with the RocketIO transceiver core e Appendix B 8B 10B Valid Characters Valid data and K characters Appendix C Related Online Documents Bibliography of online Application Notes Characterization Reports and White Papers For More Information For a complete menu of online information resources available on the Xilinx website visit http www xilinx com virtex2pro or refer to Appendix C Related Online Documents For a comprehensive listing of available tutorials and resources on network technologies and communications protocols visit http www iol unh edu training Additional Resources For additional information go to http support xilinx com The following table lists some of the resources you can access from this website You can also directly access these resources using the provided URLs Resource Tutorials Description URL Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xlnx xil ans browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Device specific information on Xilinx devic
24. 024 4 00 11000 10011 0010 001100 0 025 4 00 1100 00110 110 100110 0010 026 4 00 11010 010110 110 010110 0010 027 4 00 1101 10110 0010 00100 0 028 4 00 11100 001110 110 00 0 0010 029 4 00 1110 01110 0010 01000 0 030 4 00 11110 011110 0010 10000 0 031 4 00 1111 01011 0010 010100 0 D0 5 01 00000 00111 1010 011000 1010 D1 5 01 0000 011101 1010 00010 1010 D2 5 01 00010 01101 1010 010010 1010 D3 5 01 0001 10001 1010 000 010 D4 5 01 00100 10101 1010 001010 1010 D5 5 01 0010 01001 1010 0100 010 D6 5 01 00110 011001 1010 01100 010 D7 5 01 0011 11000 1010 000 010 D8 5 01 01000 11001 1010 000110 1010 D9 5 01 0100 00101 1010 011010 1010 D10 5 01 01010 010101 1010 01010 010 D11 5 01 0101 10100 1010 0100 1010 D12 5 01 01100 001101 1010 00110 010 D13 5 01 0110 01100 1010 01100 1010 D14 5 01 01110 011100 1010 011100 1010 D15 5 01 0111 010111 1010 01000 1010 D16 5 0 0000 011011 1010 00100 1010 D17 5 0 000 100011 1010 00011 1010 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Valid Data Characters XILINX
25. 15 8 Outputs aligned data 31 0 Properly aligned 32 std logic ALIGNED DATA sync Indicator that aligned data is properly aligned aligned rxisk 3 0 properly aligned 4 std logic RXCHARISK Inputs These are all RocketIO inputs or outputs as indicated usrclk2 RXUSRCLK2 rxreset RXRESET rxdata 31 0 RXDATA 31 0 commas aligned to 31 24 or 15 8 rxisk 3 0 RXCHARISK 3 0 rxrealign RXREALIGN rxcommadet RXCOMMADET rxchariscomma3 RXCHARISCOMMA 3 rxchariscommal RXCHARISCOMMA 1 RARY IEEE IEEE std logic 1164 11 IEEE STD LOGIC ARITH ALL IEEE Numeric STD all IEEE STD LOGIC UNSIGNED ALL ITY align comma 32 IS PORT aligned data OUT std logic vector 31 DOWNTO 0 aligned rxisk OUT std logic vector 3 DOWNTO 0 Sync OUT std logic usrclk2 IN std logic rxreset IN std logic rxdata IN std logic vector 31 DOWNTO 0 rxisk IN std logic vector 3 DOWNTO 0 rxrealign IN std logic rxcommadet IN std logic rxchariscomma3 IN std logic rxchariscommal IN std logic END ENTITY align comma 32 RocketlO Transceiver User Guide www xilinx com 95 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations ARCHITECTURE translated align_comma_32 IS SIGNAL rxdata_reg std_logic_vector 15 DOWNTO 0 SIGNAL rxisk_reg std_logic_vector 1 DOWNTO 0 SIGNAL byte sync std logic SIGNAL w
26. Date 11 20 01 Version 1 0 Revision Initial Xilinx release 01 23 02 1 1 Updated for typographical and other errors found during review 02 25 02 1 2 Part of Virtex II Pro Developer s Kit March 2002 Release 07 11 02 13 Updated PCB Design Requirements Added Appendix A RocketIO Transceiver Timing Model Changed Cell Models to Appendix B 09 27 02 1 4 Added additional IMPORTANT NOTE regarding ISE revisions at the beginning of Chapter 1 Added material in section CRC Cyclic Redundancy Check Added section Other Important Design Notes New pre emphasis eye diagrams in section Pre emphasis Techniques Numerous parameter additions previously shown as TBD in MGT Package Pins 10 16 02 1 5 Corrected pinouts for FF1152 package device column 2VP20 30 LOC Constraints rows GT X0 YO GT 1 Corrected section CRC Latency and Table 2 20 to express latency in terms of TXUSRCLK and RXUSRCLK cycles Corrected sequence of packet elements in Figure 2 30 11 20 02 1 6 Table 1 2 Added support for XAUI Fibre Channel Corrected max PCB drive distance to 40 inches Reorganized content sequence in Chapter 2 Digital Design Considerations Table 1 5 Additional information in RXCOMMADET definition Code corrections in VHDL Clock templates Data Path Latency section expanded and reformatted Corrections in clocking scheme drawings Ad
27. Figure 2 25 Figure 2 26 Figure 2 27 Figure 2 28 Figure 2 29 Figure 2 30 REFCLK BREFCLK Selection 39 Two Byte Clock with 41 Two Byte Clock without 44 Fout Byte Clock ieu duet 44 One Byte Clock sort ea 48 One Byte Data Path Clocks SERDES_10B 52 Two Byte Data Path Clocks SERDES 10B 52 Four Byte Data Path Clocks SERDES 10B 52 Multiplexed REFCLK with DCM 53 Multiplexed REFCLK without 53 Using RXRECCLK to Generate and RXUSRCLK2 54 8B 10B Data 59 10 Bit TX Data with 8 10 Bypassed 63 10 Bit RX Data Map with 8B 10B Bypassed 63 8B 10B Parallel to Serial Conversion 64 4 Byte Serial Struct ur u eee 64 Synchronizing Comma Align Signals to 66 Comma Control Flip Flop Ideal Locations 67 Bottom Comma Control Flip Flop Ideal Locations 67 Clock Correction in
28. Transceiver User Guide www xilinx com 111 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations Reference Clock A high degree of accuracy is required from the reference clock For this reason it is required that one of the oscillators listed in this section be used Epson EG 2121CA 2 5V LVPECL Outputs See the Epson Electronics America website for detailed information The power supply circuit specified by the manufacturer must be used The circuit shown in Figure 3 17 must be used to interface the oscillator s LVPECL outputs to the LVDS or LVPECL inputs of the transceiver reference clock Alternatively the LVDS_25_DCI input buffers may be used to terminate the signals on chip as shown in Figure 3 18 EG2121CA 2 5V PECL 1000 777 UG024_025a_110603 Figure 3 17 LVPECL Reference Clock Oscillator Interface EG2121CA 2 5V PECL 1000 777 09024 025c 112202 Figure 3 18 LVPECL Reference Clock Oscillator Interface On Chip Termination Pletronics LV1145B LVDS Outputs See the Pletronics website for detailed information The circuit shown in Figure 3 19 must be used to interface the oscillator s LVDS outputs to the LVDS inputs of the transceiver reference clock Alternatively the LVDS 25 DCI input buffer may be used to terminate the signals on chip as shown in Figure 3 20 LV1145B 2 5V LVDS 06024 025b 050102 Figure 3 19 LVDS Reference
29. gt GND PSCLK gt GND RST gt RST CLKO gt CLK0_W CLK2X180 gt CLK2X180_W LOCKED gt LOCK BUFG Instantiation U_BUFG IBUFG port map I gt REFCLKIN gt REFCLK a U2_BUFG BUFG port map I gt CLKO W O gt USRCLK_M_W U4_BUFG BUFG port map I gt gt 2 180 W USRCLK2 M W end ONE BYTE CLK arch Verilog Template Module Description Device ONE BYTE Verilog Submodule DCM for 1 byte GT Virtex II Pro Family module ONE_BYTE_CLK REFCLKIN REFCLK USRCLK M USRCLK2 M DCM LOCKED input REFCLKIN output REFCLK output J USRCLK M output USRCLK2 M output DCM LOCKED wire REFCLKIN wire REFCLK wire USRCLK M wire USRCLK2 M wire DCM LOCKED wire REFCLKINBUF wire Clk i 50 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Clocking XILINX wire clk_2x_180 DCM 1 CLKFB USRCLK M CLKIN REFCLKINBUF DSSEN 1 b0 PSCLK 1 50 PSEN 1 b0 PSINCDEC 1 b0 RST 1 b0O CLKO clk i CLK90 C CLK180 CLK270 o9 CLK2X C CLK2X180 clk2x_180 CLKDV CLKFX CLKFX180 Cy LOCKED DCM_LOCKED PSDONE STATUS BUFG buf1 I clk2x 180 O USRCLK2 M BUFG bu
30. only used when the 8B 10B decoder is enabled Vitesse Disparity Example 62 To support other protocols the transceiver can affect the disparity mode of the serial data transmitted For example Vitesse channel to channel alignment protocol sends out K28 5 28 5 K28 5 K28 5 or K28 5 K28 5 28 5 28 5 instead of 28 5 K28 5 28 5 28 5 or K28 5 K28 5 K28 5 K28 5 logic must assert TXCHARDISPVAL to cause the serial data to send out two negative running disparity characters Note bypassing 8B 10B encoding decoding the remaining 10 bits will be the 10 bit encoded version of the channel bonding sequence This is the same as the clock correction sequence shown in Table 2 15 page 72 Transmitting Vitesse Channel Bonding Sequence TXBYPASS8B10B TXCHARISK TXCHARDISPMODE TXCHARDISPVAL TXDATA 01 O 0 10111100 28 5 or 28 5 0101 10111100 28 5 or 28 5 0 1 0 0 10111100 28 5 or 28 5 0101 10111100 28 5 or K28 5 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 8B 10B Encoding Decoding XILINX The RocketIO core receives this data but for cases where TXCHARDISPVAL is set High during data transmission the disp_err bit in CHAN_BOND_SEQ must also be set High Receiving Vitesse Channel Bonding Sequence On the RX side the definition of the channel bonding sequence uses the disp_err bit to spec
31. sequence CCS or IDLE sequence otherwise the CRC will mistake the CCS or IDLE for SOP EOP Note These attribute are not applicable to the other CRC formats RXCHECKINGCRC RXCRCERR These two signals are status ports for the CRC circuitry RXCHECKINGCRC is asserted within several USRCLKs of the EOF being received from RXDATA This signals that the CRC circuitry has identified the SOF and the EOF If a CRC error occurred RXCRCERR will be asserted at the same time that RXCHECKINGCRC goes High TXFORCECRCERR TX_CRC_FORCE_VALUE To test the CRC logic in either the MGT or the FPGA fabric TXFORCECRCERR and TX_CRC_FORCE_VALUE may be used to invoke a CRC error When TXFORCECRCERR is asserted High for at least one USRCLK2 cycle during data transmission between SOP and EOP the CRC circuitry is forced to XOR TXDATA with TX_CRC_FORCE_VALUE creating a bit error This should cause the receiver to register that a CRC error has occurred RocketlO CRC Support Limitations There are limitations to the CRC support provided by the RocketIO transceiver core RocketIO CRC support is implementable for single channel use only Computation and byte striping of CRC across multiple bonded channels is not supported For that usage the CRC logic can be implemented in the FPGA fabric RocketlO Transceiver User Guide www xilinx com 85 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations
32. signal the RXCHARISCOMMA port if a plus comma or minus comma is received This is described in the table below DEC VALID COMMA ONLY for most applications should be set to TRUE If valid data is being transmitted and hence received then an invalid comma would arise only in the case of a bit error in which case RXCHARISCOMMA would not be asserted in the presence of bit errors If set to FALSE then RXCHARISCOMMA will be asserted for invalid K characters RXREALIGN This status signal indicates whenever the serial data is realigned from a comma character in the data stream This signal will not necessarily go High after the transceiver is reset If 68 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Clock Recovery XILINX ENPCOMMAALIGN and ENMCOMMAALIGN are both set to zero then this signal should not go High See Table 2 13 RXCHARISCOMMA This signal is similar to RXCHARISK except that it signals that a specific byte of RXDATA is acomma character However this definition only holds true for when 8B 10B encoding decoding is enabled This port is controlled by the DEC attributes and is shown in Table 2 13 If the 8B 10B decoder is bypassed this port is undefined RXCOMMADET This signal indicates if a comma character has been detected in the serial data The definition of this port is defined by the PCOMMA_DETECT and MCOMMA_DETECT attributes This signal is clocked off RX
33. 0 REFCLKSEL SERDES_10B TRUE IBUFGDS DCM REFCLK_P Pa S RXUSRCLK TXUSRCLK2 TxusRCLK RXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 2 8 Four Byte Data Path Clocks SERDES_10B TRUE GT_std_4 BUFG 06024 31 013103 52 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Clocking Z XILINX Multiplexed Clocking Scheme with DCM Following configuration of the FPGA some applications might need to change the frequency of its REFCLK depending on the protocol used Figure 2 9 shows how the design can use two different reference clocks connected to two different DCMs The clocks are then multiplexed before input into the RocketIO transceiver User logic can be designed to determine during autonegotiation if the reference clock used for the transceiver is incorrect If so the transceiver must then be reset and another reference clock selected IBUFGDS GT_std_2 REFCLK REFCLK2 REFCLKSEL TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK REFCLK_P REFCLK_N REFCLK2_P REFCLK2_N REFCLKSEL Use of 2 DCMs is required to maintain correct IBUFG DCM BUFGMUX topology for clock skew compensation UG024_05a_112202 Figure 2 9 Multiplexed REFCLK with DCM Multiplexed Clocking Scheme without DCM As with Example 1b Two Byte Clock without DCM the DCMs shown in Figure 2 9 may be removed if TXDATA and RXDATA are not clocked off the FPGA
34. 0 or 16 XC2VP20 8 XC2VP70 16 or 20 The transceiver module is designed to operate at any serial bit rate in the range of 600 Mbps to 3 125 Gbps per channel including the specific bit rates used by the communications standards listed in Table 1 2 The serial bit rate need not be configured in the transceiver as the operating frequency is implied by the received data the reference clock applied and the SERDES_10B attribute see Table 1 3 Table 1 2 Communications Standards Supported by RocketlO Transceiver Mode Channels Bit Rate Lanes Gbps 1 06 Fibre Channel 1 2 12 Gbit Ethernet 1 1 25 XAUI 10 Gbit Ethernet 4 3 125 XAUI 10 Gbit Fibre Channel 2 4 3 1875 Infiniband 1 4 12 2 5 Aurora Xilinx protocol 1 2 3 4 0 600 3 125 Custom Mode 1 2 3 4 0 600 3 125 Notes 1 One channel is considered to be one transceiver 2 Supported with the GT CUSTOM primitive Certain attributes must be modified to comply with the XAUI 10GFC specifications including but not limited to CLK COR SEQ and BOND SEQ 3 Bit rate is possible with the following topology specification maximum 6 FR4 and one Molex 74441 connector RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 19 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 3 Serial Baud Rates and the SERDES 10B Attribute
35. 15 0 RXDATA 31 16 RXNOTINTABLE 3 0 UU RXP RXN Comma Deserializer Detect Realign A Channel Bonding and Clock Correction gt RXDISPERR 3 0 RXCHARISK 3 0 RXCHARISCOMMA 3 0 RXRUNDISP 3 0 RXBUFSTATUST 1 0 ENCHANSYNC CHBONDDONE CHBONDI 3 0 CHBONDO 3 0 RXLOSSOFSYNC RXCLKCORCNT Serial Loopback Path Parallel Loopback Path M TXP TXN Serializer Output Polarity TXBUFERR TXFORCECRCERR TXDATA 15 0 TXDATA 31 16 TXBYPASS8B10B 3 0 TXCHARISK 3 0 TXCHARDISPMODE 3 0 TXCHARDISPVAL 3 0 TXKERR 3 0 TXRUNDISP 3 0 m TXPOLARITY GNDA rx Rx GND AVCCAUXTX 25V TX VTTX Termination Supply TX Figure A 1 RocketlO Transceiver Block Diagram m TXINHIBIT LOOPBACK 1 0 TXRESET RXRESET REFCLK REFCLK2 REFCLKSEL BREFCLK BREFCLK2 RXUSRCLK RXUSRCLK2 TXUSRCLK TXUSRCLK2 DS083 2_04_090402 122 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Timing Parameters XILINX Timing Parameters Parameter designations are constructed to reflect the functions they perform as well as the I Osignals to which they are synchronous The following subsections explain the meaning of each of the basic timing parameter designations used in the tables Setup Hold Times of Inputs Relative to Clock Basic Format ParameterName_SIGNAL where ParameterName
36. 32 bits wide However when the attribute is set to FALSE the decoder is disabled In this mode the received data is 10 20 or 40 bits wide and the extra bits are provided by RXCHARISK and RXRUNDISP shown in Table 2 10 If this pair is not matched the data is not received correctly Figure 2 12 shows the encoding decoding blocks of the transceiver and how the data passes through these blocks Table 2 10 shows the significance of 8B 10B ports that change purpose depending on whether 8B 10B is bypassed or enabled Transceiver Module Physical Coding Sublayer Physical Media Attachment Mindspeed 32 16 8 bits F 8B 10B Transmit DX XDATA R 7 ez 77 Encode Serializer Buffer TX TX Clock Generator E Channel Bondin S 5 2 20X Multiplier Clock Correction Receiver Clock Recovery 32 16 8 bits Elastic 8B 10B Deserializer Receive RXx 4 MADANA Buffer EJ Comma Detect Buffer RX J UG024_09_031203 Figure 2 12 8B 10B Data Flow RocketIOTM Transceiver User Guide www xilinx com 59 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Table 2 10 8 10 Bypassed Signal Significance Chapter 2 Digital Design Considerations Function TXBYPASS8B10B 0 8B 10B encoding is enabled not bypassed 1 2 or 4 bi
37. 57 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations 8B 10B Encoding Decoding Overview The RocketIO transceiver has the ability to encode eight bits into a 10 bit serial stream using standard 8B 10B encoding This guarantees a DC balanced edge rich serial stream facilitating DC or AC coupling and clock recovery Table 2 10 page 60 shows the significance of 8B 10B ports that change purpose depending on whether 8B 10B is bypassed or enabled 8B 10B Encoder A bypassable 8B 10B encoder is included in the transmitter The encoder uses the same 256 data characters and 12 control characters shown in Appendix B 8B 10B Valid Characters that are used for Gigabit Ethernet XAUI Fibre Channel and InfiniBand The encoder accepts 8 bits of data along with a K character signal for a total of 9 bits per character applied If the K character signal is High the data is encoded into one of the twelve possible K characters available in the 8B 10B code See Table B 2 page 137 If the K character input is Low the 8 bits are encoded as standard data If the K character input is High and a user applies other than one of the twelve possible combinations TXKERR indicates the error 8B 10B Decoder An optional 8B 10B decoder is included in the receiver A programmable option allows the decoder to be bypassed When it is bypassed the 10 bit character order is as shown in Figure 2 14 page 6
38. For packets that are already 64 bytes or longer pad bits are not used Note that CRC generation for IDLE requires that the transmitted K28 5 be left justified in the MGT s internal two byte data path Observing the following restrictions assures correct alignment of the packet delimiters e 4 byte data path K28 5 must appear in TXDATA 31 24 or TXDATA 15 8 e 2 byte data path K28 5 must appear in TXDATA 15 8 e 1 byte data path K28 5 must be strobed into the MGT on rising TXUSRCLK2 only when TXUSRCLK is High Note Minimum data length for this mode is defined by the protocol requirements Note For correct operation of the Gigabit Ethernet CRC function transmitted and received frames must comply with the 802 3 specification regarding Gigabit Ethernet This includes the preamble maximum length INFINIBAND The Infiniband CRC is the most complex mode and is not supported in the CRC generator Infiniband CRC contains two computation types an invariant 32 bit CRC the same as in Ethernet protocol and a variant 16 bit CRC which is not supported in the hard core Infiniband CRC must be implemented entirely in the FPGA fabric There are also two Infiniband Architecture IBA packets a local and a global Both of these IBA packets are shown in Figure 2 26 Local IBA soP iRH Bru Packet Ri R2 Variant CRC EOP Payload Global IBA sop LRH GRH Packet Ri Ro Variant CRC EOP Payload 06024 1
39. HOP SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS 06024 08 020802 Figure 4 2 2 50 Implementation 116 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 MGT Package Pins XILINX MGT Package Pins The MGT is a hard core placed in the FPGA fabric all package pins for the MGTs are dedicated on the Virtex II Pro device This is shown in the package pin diagrams in the Virtex II Pro Platform FPGA User Guide When creating a design LOC constraints must be used to implement a specific MGT on the die This LOC constraint also determines which package pins are used Table 4 1 shows the correlation between the LOC grid and the package pins themselves The pin numbers are TXNPAD TXPPAD RXPPAD and RXNPAD respectively The power pins are adjacent to these pins the package pin diagrams of the Llser Guide Table 4 1 LOC Grid amp Package Pins Correlation for FG256 456 amp FF672 LOC FG256 FG456 FF672 Constraints 5ypo oyp4 2VP2 2VP4 2VP7 2VP2 2VP4 2VP7 GT XO YO T4 T5 T6 T7 AB7 ABS AB3 AF18 AF17 AF23 AF22 9 AB10 AB5 AB6 AF16 AF15 AF21 AF20 GT XO A4 A5 A6 7 9 4 5 18 17 23 22 7 10 6 16 15 21 20 GT X1 YO T10 T11 T12 AB13 AB14 AB7 ABS AF12 AF11 AF18 AF17 T13 AB15 AB16 AB9 AB10 AF10 AF9 AF16 AF15 GT X1 Yl A10 A1
40. OF INFRINGEMENT AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TO ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE c Copyright 2002 Xilinx Inc All rights reserved X F X F F HF HF x F RocketlO Transceiver User Guide www xilinx com 91 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX Chapter 2 Digital Design Considerations k k k k k k k k k k KOK k ck kck ck KR KOK kckck kckckckckck ck kck ck KOR KOK kckckckckckckckck ck kck ck kck KE Virtex II Pro RocketIO comma alignment module This module reads RXDATA 31 0 from a RocketIO transceiver and copies it to its output realigning it if necessary so that commas are aligned to the MSB position 31 24 The module assumes ALIGN MSB is TRUE So that the comma is already aligned to 31 24 or 15 8 Outputs aligned data 31 0 Properly aligned 32 bit ALI
41. Related Online Documents The documents described in this Appendix are accessible on the Xilinx website at www xilinx com Document links shown in blue are clickable in this PDF file providing easy access to the most current revision of each document Application Notes XAPP648 Serial Backplane Interface to a Shared Memory This application note utilizes the Virtex II Pro RocketIO transceivers and the Xilinx Aurora Protocol Engine to provide a multi ported interface to a shared memory system in a backplane environment Multiprocessor systems are often encountered in backplane systems and distributed processing applications require access to a shared memory across a backplane bus Utilization of a hardware test and set lock mechanism along with a software protocol to test fora semaphore grant prior to accessing the shared memory guarantees atomic access to the shared memory XAPP649 SONET Rate Conversion in Virtex II Pro Devices The RocketIO transceivers have several modes of operation but all modes rely on the internal transmitter clock being multiplied by 20 for data transmission For example a 20 bit data stream passed to the unit at 125 MHz is serialized and retransmitted at 2 5 Gbps At a 156 25 MHz input the output is at its maximum speed of 3 125 Gbps The parallel data stream applied to the RocketIO transceiver can either be 20 bits direct or it can be written as 16 bits to which 8b 10b coding is applied to generate t
42. Slave Channel Bonding Attribute 78 Table 2 20 Effects of CRC on Transceiver 82 Table 2 21 Global and Local Headers 84 Table 2 22 Serial Speed Ranges as a Function of SERDES_10B 87 Table 2 23 LOOPBACK 89 Table 2 24 32 bit RXDATA Aligned versus 90 RocketlO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 14 Chapter 3 Analog Design Considerations Table 3 1 Differential Transmitter Parameters 99 Table 3 2 Pre emphasis 100 Table 3 3 Differential Receiver Parameters 103 Table 3 4 CDR Parameters ceecee eere aa wa ee Rer edes taie iet ded lectis 104 Table 3 5 Transceiver Power Supplies 105 Table 3 6 V gx and for AC and DC Coupled Environments 111 Chapter 4 Simulation and Implementation Table 4 1 LOC Grid amp Package Pins Correlation for FG256 456 amp FF672 117 Table 4 2 LOC Grid amp Package Pins Correlation for FG676 FF896 and FF1152 118 Table 4 3 LOC Grid amp Package Pins Correlation for FF1
43. UNISIM VCOMPONENTS ALL pragma translate on entity FOUR BYTE CLK is port REFCLKIN in std logic RST in std logic USRCLK M out std logic USRCLK2 M out std logic REFCLK out std logic LOCK out std logic end FOUR BYTE CLK Components Declarat component BUFG port architecture FOUR BYTE CLK arch of ions I in std logic O out std logic component component port in std logic O out std logic component component DCM FOUR_BYTE_CLK is port CLKIN in std_logic CLKFB in std_logic DSSEN in std_logic PSINCDEC std_logic PSEN in std_logic PSCLK in std_logic RST in std_logic CLK0 out std_logic CLK90 out std_logic CLK180 out std_logic CLK270 out std_logic CLK2X out std logic CLK2X180 out std logic RocketlO Transceiver User Guide www xilinx com 45 06024 v2 2 November 7 2003 1 800 255 7778 7 XILINX 46 Chapter 2 Digital Design Considerations CLKDV out std_logic CLKFX out std_logic CLKFX180 out std logic LOCKED out std logic PSDONE out std logic STATUS out std logic vector 7 downto 0 component Signal Declarations signal GND Signal CLKO_W signal CLKDV_W std_logic std_logic std_logic signal USRCLK2 M W std logic begin USRCLK2 M U GND lt SRCLK2 M W 0s DCM Instantiation U DCM
44. WAIT Integer 0 31 controls frequency of repetition of clock correction operations This attribute specifies the minimum number of RXUSRCLK cycles without clock correction that must occur between successive clock corrections If this attribute is zero no limit is placed on how frequently clock correction can occur CLK COR SEQ 11 bit vectors that define the sequence for clock correction The attribute used depends on the CLK COR SEQ LEN and CLK COR SEQ 2 USE CLK COR SEQ 2 USE TRUE FALSE controls use of second clock correction sequence FALSE Clock correction uses only one clock correction sequence defined by CLK COR SEQ 1 1 4 TRUE Clock correction uses two clock correction sequences defined by CLK COR SEO 1 1 4 and CLK COR SEQ 2 1 4 as further constrained by CLK COR SEQ LEN CLK COR SEQ LEN Integer that defines the length of the sequence the transceiver matches to detect opportunities for clock correction It also defines the size of the correction since the transceiver executes clock correction by repeating or skipping entire clock correction sequences CLK CORRECT USE TRUE FALSE controls the use of clock correction logic FALSE Permanently disable execution of clock correction rate matching Clock RXUSRCLK must be frequency locked with RXRECCLK in this case TRUE Enable clock correction normal mode COMMA 10B MASK This 10 bit vector defines the mask that is ANDed with the i
45. and RXN can be interchanged through the RXPOLARITY port This can be useful in the event that printed circuit board traces have been reversed Ports and Attributes Comma definition can be accomplished using the attributes discussed below This method of definition makes the MGT extremely flexible in implementing different protocols ALIGN_COMMA_MSB This attribute determines where the commas will reside in the parallel received data The comma indicates to the deserializer how to parallelize the data However with the multiple data path widths available the PCS portion must determine where to place the comma in the parallel data bytes When ALIGN_COMMA_MSB is FALSE the PCS may place the comma in any of the RXDATA bytes In the 1 byte mode of course there is only one location in which the comma can be placed In the 2 byte and 4 byte paths some uncertainty exists as to which byte will contain the comma as shown in Table 2 12 RocketlO Transceiver User Guide www xilinx com 65 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 66 Chapter 2 Digital Design Considerations When ALIGN_COMMA_MSB is TRUE the PCS places the comma into the most significant byte MSB of RXDATA in the 2 byte mode Because the PCS is optimized for the 2 byte mode some uncertainty exists in the 4 byte mode as to which byte will contain the comma as shown in Table 2 12 See Receive Data Path 32 bit Alignment for more details on this case Ta
46. clock that is representative of the incoming data rate The derived clock RXRECCLK is presented to the FPGA fabric at 1 20th the incoming data rate whether full rate or half rate This clock is generated and remains locked as long as it remains within the specified component range This range is shown in Table 3 4 A sufficient number of transitions must be present in the data stream for CDR to work properly The CDR circuit is guaranteed to work with 8B 10B encoding Further CDR RocketlO Transceiver User Guide www xilinx com 103 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations requires approximately 5 000 transitions upon power up to guarantee locking to the incoming data rate Once lock is achieved up to 75 missing transitions can be tolerated before lock to the incoming data stream is lost Table 3 4 CDR Parameters Parameter Min Typ Max Units Conditions Frequency Range Serial input diff 300 1 562 5 MHz RXP RXN TDCREF REFCLK duty cycle 45 50 55 TRCLK TFCLK REFCLK rise and 400 600 ps Between 20 fall time see and 80 voltage Virtex II Pro Data levels Sheet Module 3 TGJTT REFCLK total 40 ps 3 125 Gbps m 2 jitter peak to peak 50 n 2 5 Gbps 120 ps 1 06 Gbps TLOCK Clock recovery 10 us From system frequency acquisition reset Much less time time is needed to lock if loss of sync oc
47. component component IBUFG port I in std logic RocketlO Transceiver User Guide www xilinx com 06024 v2 2 November 7 2003 1 800 255 7778 41 XILINX Chapter 2 Digital Design Considerations O out std logic component component DCM port CLKIN in std_logic CLKFB in std_logic DSSEN in std_logic PSINCDEC std_logic PSEN in std_logic PSCLK in std_logic RST in std_logic CLKO out std_logic CLK90 out std_logic CLK180 out std_logic CLK270 out std_logic CLK2X out std logic CLK2X180 out std logic CLKDV out std logic CLKFX out std logic CLKFX180 out std logic LOCKED out std logic PSDONE out std logic STATUS out std logic vector 7 downto O0 component Signal Declarations signal GND signal CLKO_W std_logic std_logic begin GND lt 0 DCM Instantiation U_DCM DCM port map CLKIN gt REFCLK CLKFB gt USRCLK_M DSSEN gt GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST gt RST CLKO gt CLKO_W LOCKED gt LOCK ju BUFG Instantiation U BUFG IBUFG port map I gt REFCLKIN gt REFCLK 4 42 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Clocking XILINX U2_BUFG BUFG port map gt CLK0 W O gt USRCLK_M end TWO_BYTE_CLK_arch Verilog Template Mo
48. e i f g h j EIE First received Last received UG024_10b_051602 Figure 2 14 10 Bit RX Data Map with 8B 10B Bypassed RocketlO Transceiver User Guide www xilinx com 63 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations 8B 10B Serial Output Format The 8B 10B encoding translates a 8 bit parallel data byte to be transmitted into a 10 bit serial data stream This conversion and data alignment are shown in Figure 2 15 The serial port transmits the least significant bit of the 10 bit data a first and proceeds to j This allows data to be read and matched to the form shown in Appendix B 8B 10B Valid Characters H G F E D C B A Parallel 8B 10B a b C d i f g h j sea oper pepe pepe eee First transmitted Last transmitted UG024_10_021102 Figure 2 15 8B 10B Parallel to Serial Conversion The serial data bit sequence is dependent on the width of the parallel data The most significant byte is always sent first regardless of the whether 1 byte 2 byte or 4 byte paths are used The least significant byte is always last Figure 2 16 shows a case when the serial data corresponds to each byte of the parallel data TXDATA 31 24 is serialized and sent out first followed by TXDATA 23 16 TXDATA 15 8 and finally TXDATA 7 0 The 2 byte path transmits TXDATA 15 8 and then TXDATA 7 0 H3 A3 Ho A2 H4 Ho Ao TXDATA
49. embedded RocketIO multi gigabit transceivers MG s for the creation of high speed serial links from chip to chip across a backplane or from system to system Each MGT has separate transmit and receive functions full duplex and can be operated at baud rates from 600 Mbps to 3 125 Gbps Additionally every RocketIO MGT block is fully independent and contains a complete set of common SerDes serializer deserializer functions This allows Virtex II Pro devices to support many existing and emerging serial I O standards at data rates up to 10 Gbps including e XAUI 10 Gigabit Attachment Unit Interface RocketlO Transceiver User Guide www xilinx com 141 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX Appendix C Related Online Documents PCI Express e Serial RapidIO e Fibre Channel e Gigabit Ethernet e Aurora Xilinx proprietary link layer protocol This document presents characterization data taken on Virtex II Pro devices to verify the performance of the MGTs with respect to these standards and the product specification Virtex Il Pro RocketlO MGT HSSDC2 Cable Characterization White Papers RocketIO multi gigabit transceivers MGTs in Virtex II Pro Platform FPGAs are capable of sending serial data at rates from 600 Mbps to 3 125 Gbps Many links taking advantage of this technology involve some length of cable through which these signals travel At these speeds cable has the effect of degrading the qua
50. half of Figure 2 22 the shaded P bytes represent these special characters Each receiver recognizes the P channel bonding character and remembers its location in the buffer At some point one transceiver designated as the Master instructs all the transceivers to align to the channel bonding character P or to some location relative to the channel bonding character After this operation the words transmitted to the FPGA core are properly aligned RRRR SSSS TTTT etc as shown in the bottom right portion of Figure 2 22 To ensure that the channels remain properly aligned following the channel bonding operation the Master transceiver must also control the clock correction operations described in the previous section for all channel bonded transceivers Channel Bonding Alignment Operation Channel bonding is the technique of tying several serial channels together to create one aggregate channel Several channels are fed on the transmit side by one parallel bus and reproduced on the receive side as the identical parallel bus The maximum number of serial differential pairs that can be bonded is 24 For implementation guidelines see Implementation Tools page 115 Channel bonding allows those primitives that support it to send data over multiple channels Among these primitives are GT_CUSTOM GT_INFINIBAND GT_XAUI and GT_AURORA To bond channels together there is always one Master The other channels can either be a SLAVE 1
51. is in an FF672 package which has eight transceivers total four on the top edge rows A B and four on the bottom edge rows Figure 3 8 shows the top PCB layer with lands for the capacitors and ferrite beads of the VITX and VTRX supplies The ferrite beads are mounted at the eight L n locations the capacitors are mounted at the eight C n locations Figure 3 9 shows the bottom PCB layer with lands www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 PCB Design Requirements EZ XILINX for the capacitors and ferrite beads of the AVCCAUXTX and AVCCAUXRX supplies The ferrite beads are mounted at the eight L n locations the capacitors are mounted at the eight C n locations 06024 27 022202 Figure 3 8 Example Power Filtering PCB Layout for Four MGTs Layer UG024_28_022202 Figure 3 9 Example Power Filtering PCB Layout for Four MGTs Bottom Layer Figure 3 10 and Figure 3 11 show an example layout of the power filtering network for eight transceivers The device is in an FF1152 package which has sixteen transceivers total eight on the Row A edge and eight on the Row AP opposite edge Figure 3 10 shows the top PCB layer with lands for the capacitors and ferrite beads of the VTTX and RocketlO Transceiver User Guide www xilinx com 107 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations
52. not To determine if channel bonding was successful check both this signal and RXCLKCORCNT CHBONDI CHBONDO These two 4 bit ports are used by the Master to control its clock correction and channel bonding as well as those of any Slaves bonded to it CHBONDO of the Master is connected to CHBONDI of a SLAVE 1 HOP The signal is then daisy chained from SLAVE 1 HOP CHBONDO to a SLAVE 2 5 CHBONDI See Figure 4 1 and Figure 4 2 page 116 and Table 2 18 page 77 for examples The three least significant bits correlate to the value of the RXCLKCORCNT port These four bits allow the Master to control when the Slaves perform clock correction This keeps channels from going out of sync if for instance one Slave repeated a CCS while another skipped RXCLKCORONT RXLOSSOFSYNC These signals are mainly used for clock correction However they can convey some information relevant to channel bonding as well Refer to RXCLKCORCNT and RXLOSSOFSYNC page 75 Troubleshooting Factors that influence channel bonding include e Skew between Master and Slave CBS arrival time both Master lags Slave and Slave lags Master cases The larger the separation the larger BOND WAIT needs to be e Arrival time between consecutive CBSes The smaller the separation is between consecutive CBSes the smaller BOND WAIT needs to be set to ensure that the Master aligns to the intended sequence instead of the one after or the on
53. possible options three for valid commas and three for any comma Note that all bytes 1 2 or 4 at the RX FPGA interface each have their own individual 8B 10B indicators K character disparity error out of band error current running disparity and comma detect 58 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 8B 10B Encoding Decoding XILINX Ports and Attributes TXBYPASS8B10B RX_DECODE_USE One port and one attribute enable 8B 10B encoding decoding in the transceiver TXBYPASS8B10B is a byte mapped port that is 1 2 or 4 bits wide depending on the data width of the transceiver primitive being used These bits correlate to each byte of the data path To enable 8B 10B encoding in the transmitter these bits must be set Low In this mode the transmit data input to the TXDATA port is non encoded data of either 8 16 or 32 bits wide However if other encoding schemes are preferred the encoder capabilities can be bypassed by setting all bits High In this mode the data input to TXDATA is either 10 20 or 40 bits wide The extra bits are fed through the TXCHARDISPMODE and TXCHARDISPVAL buses shown in Table 2 10 The decoder is controlled by the attribute DECODE USE When this attribute is set to TRUE the decoder is enabled and should coincide with TXBYPASS8B10B being set Low In this mode the received data output from the RXDATA port is decoded data either 8 16 or
54. pre emphasis are shown in four scope screen captures Figure 3 2 through Figure 3 5 on the pages following The STRONG notation in Figure 3 3 is used to show that the waveform is greater in voltage magnitude at this point than the LOGIC or normal level i e no pre emphasis A second characteristic of RocketIO transceiver pre emphasis is that the STRONG level is reduced after some time to the LOGIC level thereby minimizing the voltage swing necessary to switch the differential pair into the opposite state Lossy transmission lines cause the dissipation of electrical energy This pre emphasis technique extends the distance that signals can be driven down lossy line media and increases the signal to noise ratio at the receiver It should be noted that high pre emphasis settings are not appropriate for short links a fraction of the maximum length of 40 inches of FR4 Excessive pre emphasis can actually degrade the bit error rate BER of a multi gigabit link Careful simulation and or lab testing of the system should always be used to verify that the optimal pre emphasis setting is in use Consult the Virtex II Pro RocketIO Multi Gigabit Transceiver Characterization Summary for more detailed information on the waveforms to be expected at the various pre emphasis levels The four levels of pre emphasis are shown in Table 3 2 Table 3 2 Pre emphasis Values Attribute Values Emphasis 0 10 1 20 2 25 3 33 ww
55. 0 0110 D0 7 11 00000 00111 000 011000 0 D1 7 11 0000 011101 000 00010 0 D2 7 11 00010 01101 000 010010 0 D3 7 11 0001 10001 1110 0001 000 D4 7 11 00100 10101 000 001010 0 D5 7 11 0010 01001 1110 01001 000 D6 7 11 00110 011001 1110 011001 0001 D7 7 11 0011 11000 1110 000 000 D8 7 11 01000 11001 0001 000110 1110 D9 7 11 0100 00101 1110 011010 000 D10 7 11 01010 010101 1110 010101 0001 D11 7 11 0101 10100 1110 0100 1000 D12 7 11 01100 001101 1110 001101 0001 D13 7 11 0110 01100 1110 01100 1000 D14 7 11 01110 011100 1110 011100 1000 D15 7 11 0111 010111 000 01000 0 D16 7 1 0000 011011 000 00100 0 D17 7 1 000 00011 011 000 000 D18 7 1 0010 010011 011 0100 0001 D19 7 1 001 10010 1110 0010 000 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Valid Control Characters K Characters XILINX Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D20 7 1 0100 001011 0111 001011 000 D21 7 1 010 01010 1110 101010 0001 D22 7 1 0110 011010 1110 011010 000 D23 7 1 011 11010 0001 000101 0 D24 7 1 1000 10011 000 001100 0 D25 7 1 100 00110 1110 100110 0001 D26
56. 000 1100000000 1100000000 DETECT TRUE TRUE TRUE 10B VALUE 0011111000 0011111000 0011111000 PCOMMA DETECT TRUE TRUE TRUE REF CLK V SEL 0 0 0 RX BUFFER USE TRUE TRUE TRUE RX USE FALSE FALSE FALSE RX_DATA_WIDTH NO NO NO 34 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Byte Mapping Table 1 8 Default Attribute Values and GT_XAUI Continued GT_FIBRE_CHAN GT_INFINIBAND XILINX Attribute Default Default Default GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI RX_DECODE_USE TRUE TRUE TRUE RX_LOS_INVALID_INCR 10 10 10 RX_LOS_THRESHOLD 40 40 40 RX LOSS SYNC TRUE TRUE TRUE SERDES_10B FALSE FALSE FALSE TERMINATION_IMP 50 50 5000 TX_BUFFER_USE TRUE TRUE TRUE TX_CRC_FORCE_VALUE 11010110 11010110 11010110 TX_CRC_USE FALSE FALSE FALSE TX WIDTH NO NO NO TX DIFF CTRL 500 50000 50000 TX_PREEMPHASIS 00 00 00 Notes 1 Modifiable attribute for specific primitives 2 Depends on primitive used either 1 2 or 4 3 CRC_EOP and CRC_SOP are not applicable for this primitive Byte Mapping Most of the 4 bit wide status and control buses correlate to a specific byte of TXDATA or RXDATA This scheme is shown in Table 1 9 This creates a way to tie all the signals together regardless of the data path width needed for the GT CUSTOM All other primit
57. 011111xxx if DEC DETECT is TRUE and or on 1100000xxx if DEC MCOMMA DETECT is TRUE regardless of the settings of the xxx bits TRUE Raise RXCHARISCOMMA only on valid characters that are in the 8B 10B translation MCOMMA 10B VALUE This 10 bit vector defines minus comma for the purpose of raising RXCOMMADET and realigning the serial bit stream byte boundary This definition does not affect 8B 10B encoding or decoding Also see 10 MASK MCOMMA_DETECT TRUE FALSE indicates whether to raise or not raise RXCOMMADET when minus comma is detected PCOMMA 10B VALUE This 10 bit vector defines plus comma for the purpose of raising RXCOMMADET and realigning the serial bit stream byte boundary This definition does not affect 8B 10B encoding or decoding Also see 10 MASK PCOMMA_DETECT TRUE FALSE indicates whether to raise or not raise RXCOMMADET when plus comma is detected REF_CLK_V_SEL 1 0 Selects BREFCLK BREFCLK2 for 2 5 Gbps or greater serial speeds 0 Selects REFCLK REFCLK2 for serial speeds under 2 5 Gbps RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 29 1 800 255 7778 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 6 RocketlO Transceiver Attributes Continued Attribute Description RX_BUFFER_USE Always set to TRUE RX_CRC_USE TRUE FALSE determines if CRC is used or not TX_C
58. 1 A13 A14 7 8 9 A12 All 18 17 12 13 15 16 10 10 9 16 15 GT X2 YO AB13 14 AF12 AF11 AB15 AB16 AF10 AF9 GT_X2_Y1 13 14 A12 11 15 16 10 9 GT X3 YO 17 18 AF7 AF6 AB19 AB20 AF5 AF4 GT_X3_Y1 A17 A18 A7 5 19 20 A4 RocketlO Transceiver User Guide www xilinx com 117 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 4 Simulation and Implementation Table 4 2 LOC Grid amp Package Pins Correlation for FG676 FF896 and FF1152 FG676 FF896 FF1152 LOC Constraints 2VP20 2VP7 2VP20 2VP30 2VP40 2VP20 2VP30 2VP30 2VP40 2VP50 GT X0_Y0 AF7 AF6 TBD AK27 26 AK27 AK26 AP29 AP28 AP33 AP32 AP33 AP32 AF5 AF4 AK25 AK24 AK25 AK24 AP27 AP26 AP31AP30 AP31AP30 GT X0_Y1 A7 A6 A5 TBD A27 A26 A27 A26 A29 A28 A33 A32 A33 A32 A4 A25 A24 A25 A24 A27 A26 A31 A30 A31 A30 GT X1_Y0 AF12 AF11 TBD AK20 AK19 AK20 AK19 21 20 29 28 29 28 AF10 AF9 18 17 AK18 AK17 19 AP18 AP27 AP26 AP27 AP26 GT X1 Y1 A12 All TBD A20 A19 A20 A19 A21 A20 A29 A28 A29 A28 A10 A9 A18 A17 A18 A17 A19 A18 A27 A26 A27 A26 GT X2 YO AF18 AF17 TBD AK14 AK13 14 AK13 17 AP16 AP21 20 AP25 AP24 AF16 AF15 AK12 AK12 AK11 AP15 AP14 A
59. 1 11000 110 000 0010 08 4 00 01000 11001 0010 000110 1101 D9 4 00 0100 00101 110 011010 0010 D10 4 00 01010 010101 110 010101 0010 D11 4 00 0101 10100 110 0100 0010 D12 4 00 01100 001101 110 001101 0010 D13 4 00 0110 01100 110 01100 0010 D14 4 00 01110 011100 110 011100 0010 D15 4 00 0111 010111 0010 01000 0 D16 4 100 10000 011011 0010 00100 0 RocketlO Transceiver User Guide www xilinx com 133 06024 v2 2 November 7 2003 1 800 255 7778 XILINX 134 Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj 017 4 00 1000 00011 110 000 0010 018 4 00 10010 010011 110 0100 0010 019 4 00 1001 10010 110 0010 0010 020 4 00 10100 001011 110 0010 0010 021 4 00 1010 01010 110 01010 0010 022 4 00 10110 011010 110 011010 0010 023 4 00 1011 11010 0010 000101 0
60. 10 100 01000 00 D30 1 00 1110 011110 100 10000 00 D31 1 00 111 01011 100 010100 100 D0 2 010 00000 00111 010 011000 010 D1 2 010 00001 011101 010 00010 010 D2 2 010 00010 01101 010 010010 010 D3 2 010 0001 10001 010 0001 010 D4 2 010 00100 10101 010 001010 010 D5 2 010 0010 01001 010 01001 010 D6 2 010 00110 011001 010 011001 010 D7 2 010 0011 11000 010 000 010 D8 2 010 01000 11001 010 000110 010 D9 2 010 0100 00101 010 011010 010 D10 2 010 01010 010101 010 010101 010 D11 2 010 0101 10100 010 0100 010 D12 2 010 01100 001101 010 001101 010 D13 2 010 0110 01100 010 01100 010 D14 2 010 01110 011100 010 011100 010 D15 2 010 0111 010111 010 01000 010 D16 2 010 10000 011011 010 00100 010 RocketlO Transceiver User Guide www xilinx com 131 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters Continued
61. 25 and 33 which designated by 0 1 2 and 3 respectively Pre emphasis is discussed in greater detail in Chapter 3 Analog Design Considerations LOOPBACK To facilitate testing without the requirement to apply patterns or measure data at gigahertz rates two programmable loopback features are available One option serial loopback places the gigabit transceiver into a state where transmit data is directly fed back to the receiver An important point to note is that the feedback path is at the output pads of the transmitter This tests the entirety of the transmitter and receiver The second loopback path is a parallel path that checks only the digital circuitry When the parallel option is enabled the serial loopback path is disabled However the transmitter outputs remain active and data is transmitted over the serial link If TXINHIBIT is asserted TXN is forced High and TXP is forced Low until TXINHIBIT is de asserted LOOPBACK allows the user to send the data that is being transmitted directly to the receiver of the transceiver Table 2 23 shows the three loopback modes 88 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Miscellaneous Signals XILINX Table 2 23 LOOPBACK Modes Input Value Mode Description Normal Mode is selected during normal operation The transmitted data is sent out the differential transmit ports 00 Normal Mode TXN TXP and are
62. 3 The decoder uses the same table that is used for Gigabit Ethernet Fibre Channel and InfiniBand The decoder separately detects both disparity errors and out of band errors A disparity error occurs when a 10 bit character is received that exists within the 8B 10B table Table B 1 page 129 but has an incorrect disparity An out of band error occurs when a 10 bit character is received that does not exist within the 8B 10B table It is possible to obtain an out of band error without having a disparity error The proper disparity is always computed for both legal and illegal characters The current running disparity is available at the RXRUNDISP signal The 8B 10B decoder performs a unique operation if out of band data is detected Should this occur the decoder signals the error passes the illegal 10 bits through and places them on the outputs This can be used for debugging purposes if desired The decoder also signals reception of one of the twelve valid K characters Table B 2 page 137 by way of the RXCHARISK port In addition a programmable comma detect is included The comma detect signal RXCOMMADET registers a comma on the receipt of any plus comma minus comma or both Since the comma is defined as a 7 bit character this includes several out of band characters RXCHARISCOMMA allows the decoder to detect only the three defined commas K28 1 K28 5 and K28 7 as plus comma minus comma or both In total there are six
63. 31 24 TXDATA 23 16 TXDATA 15 8 TXDATA 7 0 8B 10B a2 j2 a1 j1 ao jo LSB3 LSBo LSB LSBo 1St Sent 2nd Sent 3rd Sent 4th Sent Encoded Encoded Encoded Encoded U024_11_020802 Figure 2 16 4 Byte Serial Structure HDL Code Examples Transceiver Bypassing of 8B 10B Encoding 8B 10B encoding can be bypassed by the transceiver The TXBYPASS8B10B is set to 1111 the RXDECODE attribute is set to FALSE to create the extra two bits needed for a 10 bit data bus and TXCHARDISPMODE TXCHARDISPVAL RXCHARISK and RXRUNDISP are added to the 8 bit data bus Please use the Architecture Wizard to create instantiation templates This wizard creates code and instantiation templates that define the attributes for a specific application 64 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 SERDES Alignment XILINX SERDES Alignment Overview Serializer The multi gigabit transceiver multiplies the reference frequency provided on the reference clock input REFCLK by 20 or by 10 if half rate operation is selected Data is converted from parallel to serial format and transmitted on the TXP and TXN differential outputs The electrical polarity of TXP and TXN can be interchanged through the TXPOLARITY port This option can either be programmed or controlled by an inputat the FPGA core TX interface This facilitates recovery from situations where printed circuit board traces have been rev
64. 4 020802 Figure 2 26 nfiniband Mode CRC is calculated with certain bits masked LRH depending whether the packet is local or global The size of these headers is shown in Table 2 21 Table 2 21 Global and Local Headers Packet Description Size LRH Local Routing Header 8 Bytes GRH Global Routing Header 40 Bytes BTH IBA Transport Header 12 Bytes www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 CRC Cyclic Redundancy Check XILINX The CRC checks the LNH Link Next Header of the LRH LRH is shown in Figure 2 27 along with the bits the CRC uses to evaluate the next packet 8 Ba a Bs Bo B11 Big 11 IBA Global Packet 1 0 IBA Local Packet 0 1 Raw Packet CRC does not insert remainder 0 0 Raw Packet CRC does not insert remainder UG024_15_020802 Figure 2 27 Local Route Header Note Minimum data length for this mode is defined by the protocol requirements Because of the complexity of the CRC algorithms and implementations especially with Infiniband a more in depth discussion is beyond the scope of this manual CRC START OF PACKET CRC END OF PACKET When implementing USER MODE CRC Start of Packet SOP and End of Packet EOD must be defined for the CRC logic These delimiters must be one of the defined K characters see Table B 2 page 137 These must be different than a clock correction
65. 4 and CHAN BOND SEQ 2 1 4 as further constrained by BOND SEQ LEN CHAN BOND SEQ LEN Integer 1 4 defines length in bytes of channel bonding sequence This defines the length of the sequence the transceiver matches to detect opportunities for channel bonding CHAN BOND WAIT Integer 1 15 that defines the length of wait in bytes after seeing channel bonding sequence before executing channel bonding RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 27 1 800 255 7778 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 6 RocketlO Transceiver Attributes Continued Attribute CLK COR INSERT IDLE FLAG Description TRUE FALSE controls whether RXRUNDISP input status denotes running disparity or inserted idle flag FALSE RXRUNDISP denotes running disparity when RXDATA is decoded data TRUE RXRUNDISP is raised for the first byte of each inserted repeated clock correction Idle sequence when RXDATA is decoded data CLK COR KEEP IDLE TRUE FALSE controls whether or not the final byte stream must retain at least one clock correction sequence FALSE Transceiver can remove all clock correction sequences to further recenter the elastic buffer during clock correction TRUE In the final RXDATA stream the transceiver must leave at least one clock correction sequence per continuous stream of clock correction sequences CLK COR REPEAT
66. 517 and FF1704 119 Appendix A RocketlO Transceiver Timing Model Table A 1 RocketIO Clock 121 Table A 2 Parameters Relative to the RX User Clock RKUSRCLK 124 Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 125 Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 125 Table A 5 Miscellaneous Clock Parameters 126 Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters 129 Table B 2 Valid Control Characters K Characters 137 Appendix C Related Online Documents www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 lt XILINX Preface About This Guide The RocketIO Transceiver User Guide provides the product designer with the detailed technical information needed to successfully implement the RocketIO multi gigabit transceiver in Virtex II Pro Platform FPGA designs RocketlO Features The RocketIO transceiver s flexible programmable features allow a multi gigabit serial transceiver to be easily integrated into any Virtex II Pro design Guide Contents Variable speed full duplex transceiver allowing 600 Mbps to 3 125 Gbps baud transfer rates Monolithic clock synthesis and clock recovery syst
67. 6 10 1000 100011 0110 000 0110 D18 6 10 01010 010011 0110 0100 0110 RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 135 XILINX 136 Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D19 6 10 1001 10010 0110 10010 0110 D20 6 10 10100 001011 0110 001011 0110 D21 6 10 1010 01010 0110 01010 0110 D22 6 10 10110 011010 0110 011010 0110 D23 6 10 1011 11010 0110 000101 0110 D24 6 10 11000 10011 0110 001100 0110 D25 6 10 1100 00110 0110 100110 0110 D26 6 10 11010 010110 0110 010110 0110 D27 6 10 1101 10110 0110 001001 0110 D28 6 10 11100 001110 0110 00 0 0110 D29 6 10 1110 01110 0110 010001 0110 D30 6 10 11110 011110 0110 100001 0110 D31 6 10 1111 01011 0110 01010
68. 7 IIE 1000 D TTT IITA Ts 06024 026 120202 Figure 3 6 Power Supply Circuit Using LT1963 Regulator The required voltage regulator is the Linear Technology LT1963 device or equivalent The regulator must be used in the circuit specified by the manufacturer Figure 3 6 shows the schematic for the adjustable version of the LT1963 device with values for a 2 5 V supply as would be used for AVCCAUXRX and AVCCAUXTX Alternatively fixed output voltage devices in the same series may be used such as the LT1963 2 5 If the fixed version is used SENSE should be connected to OUT All characterization work was done using the LT1963 device If another part is used instead of the LT1963 it must meet the following requirements RocketlO Transceiver User Guide www xilinx com 105 06024 v2 2 November 7 2003 1 800 255 7778 XILINX 106 Chapter 3 Analog Design Considerations e Mustbea linear regulator e Must have output noise no greater than 40 uV RMS from 10 Hz to 100 KHz e Must regulate to within 2 of the nominal output voltage 50 mV Termination voltages may be of any value in the range of 1 8 V to 2 625 V In cases where the RocketIO transceiver is interfacing with a transceiver from another vendor termination voltage may be dictated by the specifications of the other transceiver In cases where the RocketIO transceiver is interfacing with another RocketIO transceiver an
69. 7 1 1010 010110 1110 010110 000 D27 7 1 101 10110 0001 00100 0 D28 7 1 1100 001110 1110 00 0 000 D29 7 1 110 01110 0001 01000 0 D30 7 1 1110 011110 000 10000 0 D31 7 1 111 01011 000 010100 0 Valid Control Characters K Characters Table B 2 Valid Control Characters K Characters Special Bits Current RD Current RD Code Name HGF EDCBA abcdei fghj abcdei fghj K28 0 000 00 001111 0100 110000 1011 K28 1 00 00 001111 100 0000 0110 K28 2 010 00 001111 010 0000 1010 K28 3 0 00 001111 001 0000 1100 K28 4 00 00 001111 0010 10000 110 K28 5 0 00 001111 1010 0000 010 K28 6 0 00 001111 0110 0000 100 K28 7 0 11 11100 001111 1000 0000 0 K23 7 1 011 11010 1000 000101 0 K27 7 1 101 10110 1000 001001 0 K29 7 1 110 01110 1000 010001 0 K30 7 1 1110 011110 1000 100001 0 Notes 1 Used for testing and characterization only Do not use in protocols RocketlO Transceiver User Guide www xilinx com 137 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Appendix B 8B 10B Valid Characters 138 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 87 XILINX Appendix C
70. 9 BB38 GT_X1_Y1 A32 A31 A30 A32 A31 A30 A37 A36 A35 A41 A40 A39 A29 A29 A34 A38 GT X2 YO AW24 AW23 AW28 AW27 AW32 AW31 BB33 BB32 BB37 BB36 AW22 AW21 AW26 AW25 AW30 AW29 _ BB31 BB30 BB35 BB34 GT X2 Y1 A24 23 A22 A28 A27 A26 A32 A31 A30 A33 A32 A31 A37 A36 A35 A21 A25 A29 A30 A34 GT X3 YO AW19 AW18 AW24 AW23 AW28 AW27 29 BB28 BB33 BB32 AW17 AW16 AW22 AW21 AW26 AW25 BB27 BB26 BB31 BB30 GT_X3_Y1 A19 A18 A17 24 A23 A22 28 A27 A26 29 A28 A27 A33 A32 A31 A16 A21 A25 A26 A30 GT X4 YO AW11 AW10 AW19 AW18 AW24 AW23 25 BB24 BB29 BB28 AW9 AW8 AW17 AW16 AW22 AW21 BB23 BB22 BB27 BB26 GT_X4_Y1 A11 A10 9 A19 A18 A17 24 A23 A22 25 A24 A23 29 A28 27 8 16 21 22 26 GT X5 YO AW7 AW6 AW15 AW14 AW19 AW18 21 BB20 BB25 BB24 AW5 AW4 AW13 AW12 AW17 AW16 BB19 BB18 BB23 BB22 GT_X5_Y1 AZ 5 A4 A15 A14 A13 A19 A18 A17 21 A20 A19 25 A24 A23 A12 A16 A18 A22 GT X6 YO AW11 AW10 AW15 AW14 17 16 BB21 BB20 AWO AW8 AW13 AW12 BB15 14 BB19 BB18 GT X6 Y1 11 10 A9 15 A14 A13 A17 A16 A15 A21 A20 A19 8 14 18 GT X7 YO AW7 AW6 AW11 AW10 BB13 BB12 BB17 BB16 AW5 AW4 AW9 AW8 BB11 BB10 BB15 BB14 GT_X7_Y1 AZ 5 4 11 A10 9 A13 A12 11 17 A16 A15 8 10 14
71. A GT CUSTOM GT ETHERNET CLK COR SEQ 2 2 00000000000 00000000000 00000000000 CLK COR SEQ 2 3 00000000000 00000000000 00000000000 CLK COR SEQ 2 4 00000000000 00000000000 00000000000 CLK COR SEQ 2 USE FALSE FALSE FALSE CLK COR SEQ LEN 40 1 2 CORRECT USE TRUE TRUE TRUE 10B MASK 1111111111 1111111000 1111111000 END OF PKT K29 7 K29 7 Note 6 CRC FORMAT USER MODE USER MODE ETHERNET START OF PKT K27 7 K27 7 Note 6 MCOMMA DETECT TRUE TRUE TRUE DETECT TRUE TRUE TRUE DEC VALID COMMA ONLY TRUE TRUE TRUE 10B VALUE 1100000101 1100000000 1100000000 DETECT TRUE TRUE TRUE 10 VALUE 0011111010 0011111000 0011111000 PCOMMA_DETECT TRUE TRUE TRUE REF_CLK_V_SEL 0 0 0 RX_BUFFER_USE TRUE TRUE TRUE RX_CRC_USE FALSE 2 FALSE FALSE 2 RX_DATA_WIDTH N 2 NO RX DECODE USE TRUE TRUE TRUE RX LOS INVALID INCR 10 1 10 RX LOS THRESHOLD 40 4 40 RX LOSS SYNC TRUE TRUE TRUE SERDES_10B FALSE 2 FALSE FALSE 2 TERMINATION_IMP 500 50 500 TX_BUFFER_USE TRUE TRUE TRUE TX_CRC_FORCE_VALUE 110101100 11010110 110101100 TX USE FALSEO FALSE FALSE 32 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Modifiable Primitives XILINX Table 1 7 Default Attribute Values GT AURORA GT CUSTOM GT ETHERNET Continued
72. ALSE FALSE FALSE RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 33 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 8 Default Attribute Values GT_FIBRE_CHAN GT_INFINIBAND and XAUI Continued Attribute Default Default Default GT_FIBRE_CHAN GT_INFINIBAND GT_XAUI CLK_COR_KEEP_IDLE FALSE FALSE FALSE CLK COR REPEAT WAIT 20 10 10 CLK COR SEQ 1 1 00110111100 00100011100 00100011100 CLK COR SEQ 1 2 0001001010 00000000000 00000000000 CLK COR SEQ 1 3 0001011010 00000000000 00000000000 CLK COR SEQ 1 4 0001011010 00000000000 00000000000 CLK COR SEQ 2 1 00000000000 00000000000 00000000000 CLK COR SEQ 2 2 00000000000 00000000000 00000000000 CLK COR SEQ 2 3 00000000000 00000000000 00000000000 CLK COR SEQ 2 4 00000000000 00000000000 00000000000 CLK COR SEQ 2 USE FALSE FALSE FALSE CLK COR SEQ LEN 4 1 1 CORRECT USE TRUE TRUE TRUE 10B MASK 1111111000 1111111000 1111111000 CRC END OF PKT Note 3 Note 3 K29 7 0 FORMAT FIBRE CHAN INFINIBAND USER MODE START OF PKT Note 3 Note 3 K27 70 MCOMMA DETECT TRUE TRUE TRUE DEC DETECT TRUE TRUE TRUE VALID ONLY TRUE TRUE TRUE Lane ID INFINBAND ONLY NA 00000000000 NA 10B VALUE 1100000
73. Amplifier The RocketIO transceiver is implemented in Current Mode Logic CML CML output consists of transistors configured as shown in Figure 3 1 CML uses a positive supply and Offers easy interface requirements In this configuration both legs of the driver Vp and sink current with one leg always sinking more current than its complement The CML output consists of a differential pair with 500 or optionally 750 source resistors The signal swing is created by switching the current in a common drain differential pair The differential transmitter specification is shown in Table 3 1 page 99 Table 3 1 Differential Transmitter Parameters Parameter Min Typ Max Units Conditions Vout Serial output differential 800 1600 mV Output differential peak to peak TXP TXN voltage is programmable Output termination 1 8 2 625 V voltage supply Common mode output 1 5 2 5 V voltage range Viskgw Differential output skew 15 ps RocketlO Transceiver User Guide www xilinx com 99 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations Pre emphasis Techniques 100 In pre emphasis the initial differential voltage swing is boosted to create a stronger rising or falling waveform This method compensates for high frequency loss in the transmission media that would otherwise limit the magnitude of this waveform The effects of
74. Bit Error Rate Tester This application note describes the implementation of a RocketIO transceiver bit error rate tester BERT reference design demonstrating a serial link 1 0 Gbps to 3 125 Gbps between two RocketIO multi gigabit transceivers MGT embedded in a single Virtex II Pro FPGA To build a system an CoreConnect infrastructure connects the PowerPCTM405 processor PPC405 to external memory and other peripherals using the processor local bus PLB and device control register DCR buses The reference design uses a two channel Xilinx bit error rate tester XBERT module for generating and verifying high speed serial data transmitted and received by the RocketIO transceivers The data to be transmitted is constructed using pseudorandom bit sequence PRBS patterns The receiver in XBERT module compares the incoming data with the expected data to analyze for errors The XBERT supports several different types of user selectable PRBS patterns Frame counters in the receiver are used to track the total number of data words frames received and total number of data words with bit errors The processor reads the status and counter values from the XBERT through the PLB Interface then sends out the information to the UART XAPP662 In Circuit Partial Reconfiguration of RocketlO Attributes 140 This application note describes in circuit partial reconfiguration of RocketIO transceiver attributes using the Virtex II Pro internal configu
75. CLK BREFCLK GCLK5P N GCLK7S Bottom P GCLK2S P GCLKOP BREFCLK2 BREFCLK2 N GCLK3P N GCLKI1S Anattribute REF CLK V SEL anda port REFCLKSEL determine which reference clock is used for the MGT PMA block Figure 2 1 shows how REFCLK and are selected through use of REFCLKSEL and REF CLK V SEL refclk refclk2 REFCLKSEL brefclk brefclk2 Figure 2 1 REF CLK V SEL refclk out to PCS and PMA ug024 35 091802 REFCLK BREFCLK Selection Logic Table 2 3 shows the BREFCLK pin numbers for all packages Note that these pads must be used for BREFCLK operations Table 2 3 BREFCLK Pin Numbers Top Bottom Package BREFCLK BREFCLK2 BREFCLK BREFCLK2 Pin Number Pin Number Pin Number Pin Number FG256 A8 B8 B9 A9 R8 T8 T9 R9 FG456 C11 D11 D12 C12 W11 Y11 Y12 W12 FF672 B14 C14 C13 B13 AD14 AE14 AE13 AD13 FF896 F16 G16 G15 F15 AH16 AJ16 AJ15 AH15 FF1152 H18 J18 J17 H17 AK18 AL18 AL17 AK17 FF1148 N A N A N A N A FF1517 E20 D20 J20 K20 AR20 AT20 AL20 AK20 1704 G22 F22 F21 G21 AU22 AT22 AT21 AU21 FF1696 N A N A N A N A RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 39 XILINX Chapter 2 Digital Design Considerations Clock Ratio USRCLKO clocks the data buffers The ability to send receive parallel data to from the transceiver at three differ
76. CM Example 2 Four Byte Clock If a 4 byte or 1 byte data path is chosen the ratio between USRCLK and USRCLK2 changes The time it take for the SERDES to serialize the parallel data requires the change in ratios The DCM example Figure 2 4 is detailed for a 4 byte data path If 3 125 Gbps is required REFCLK is 156 MHz and USRCLK2 M runs at only 78 MHz including the clocking for any interface logic Both USRCLK and USRCLK2 are aligned on the falling edge since USRCLK M is 180 out of phase when using local inverters with the transceiver Note These local MGT clock input inverters shown and noted in Figure 2 4 are not included in the FOUR BYTE CLK templates Clocks for 4 Byte Data Path MGT DCM for 4 Byte Data Path _std_ CLKDV_DIVIDE 2 REFCLK REFCLKSEL IBUFGDS DCM BUFG REFCLK TXUSRCLK REFCLK N CLKIN CLKDV TXUSRCLK2 RXUSRCLK CLKFB RXUSRCLK2 TXUSRCLK 1 TXUSRCLK2 RST CLK0 o RXUSRCLK RXUSRCLK2 MGT clock input invert ers acceptable skew UG024_03_112202 Figure 2 4 Four Byte Clock 44 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Clocking XILINX VHDL Template Module Description FOUR_BYTE_CLK VHDL submodule DCM for 4 byte Virtex II Pro Family library IEEE use IEEE std logic 1164 all pragma translate off library UNISIM use
77. Clock Oscillator Interface LV1145B 2 5V LVDS D 06024 0254 112202 Figure 3 20 LVDS Reference Clock Oscillator Interface On Chip Termination 112 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Other Important Design Notes XILINX Other Important Design Notes Powering the RocketlO Transceivers IMPORTANT All RocketIO transceivers in the FPGA whether instantiated in the design or not must be connected to power and ground Unused transceivers may be powered by any 2 5 V source and passive filtering is not required Refer to Power Conditioning page 104 for detailed information on powering instantiated RocketIO transceivers The maximum power consumption per port is 350 mW at 3 125 Gbps operation The POWERDOWN Port POWERDOWN is a single bit primitive port see Table 2 5 page 40 that allows shutting off the transceiver in case it is not needed for the design or will not be transmitting or receiving for a long period of time When POWERDOWN is asserted the transceiver does not use any power The clocks are disabled and do not propagate through the core The 3 state TXP and TXN pins are set High Z while the outputs to the fabric are frozen but not set High Z Any given transceiver that is not instantiated in the design will automatically be set to the POWERDOWN state by the Xilinx ISE development software and will consume no power An instantiated transceiver howe
78. D12 1 001 01100 001101 100 00110 00 D13 1 001 0110 01100 100 01100 100 D14 1 001 01110 011100 100 011100 100 D15 1 001 0111 010111 100 01000 100 D16 1 00 0000 011011 100 00100 100 D17 1 00 000 100011 100 00011 100 130 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Valid Data Characters XILINX Table B 1 Valid Data Characters Continued Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D18 1 00 0010 010011 100 0100 00 D19 1 00 001 10010 100 0010 100 D20 1 00 0100 001011 100 0010 00 D21 1 00 010 01010 100 01010 100 D22 1 00 0110 011010 100 011010 100 D23 1 00 011 11010 100 000101 100 D24 1 00 1000 10011 100 001100 100 D25 1 00 100 00110 100 100110 100 D26 1 00 1010 010110 100 010110 100 D27 1 00 101 10110 100 00100 00 D28 1 00 1100 001110 100 00 0 100 D29 1 00 110 011
79. DCM port map CLKIN gt REFCLK CLKFB gt USRCLK2_M_W DSSEN gt GND PSINCDEC gt GND PSEN gt GND PSCLK gt GND RST gt RST CLKO gt CLKO_W CLKDV gt CLKDV_W LOCKED gt LOCK BUFG Instan U BUFG IBUFG port map I gt gt Ju U2 BUFG BUFG port map T gt gt 3 U3_BUFG BUFG port map gt gt Ju tiation REFCLKIN REFCLK CLKO W USRCLK M CLKDV W USRCLK2 M W end FOUR BYTE CLK arch www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Clocking XILINX Verilog Template Module Description es Device FOUR_BYTE_CLK Verilog Submodule DCM for 4 byte GT Virtex II Pro Family module FOUR BYTE CLK input output output output output wire wire wire wire wire wire wire wire REFCLKIN K USRCLK M USRCLK2 M DCM LOCKED e i REFCLKIN REFCLK USRCLK_M USRCLK2_M DCM_LOCKED USRCLK_M REFCLKINBUF 1 bo 1 b0 1 b0 1 b0 1 b0 clk i Jy clkdv2 DCM_LOCK REFCLKIN REFCLK USRCLK M USRCLK2 M DCM LOCKED REFCLKINBUF clkdv2 elk i DCM demi CLKFB CLKIN DSSEN PSCLK PSEN PSINCDEC RST CLKO CLK90 CLK180 CLK270 CLK2X CLK2X180 CLKDV CL
80. DLE is set to TRUE at least one IDLE sequence must remain after clock correction has been completed This limits the clock correction logic to remove only two of the three IDLE sequences If CLK COR KEEP IDLE is FALSE then all three IDLEs can be removed Table 2 14 illustrates the relationship between the number of IDLE sequences removed the inherent stability of REFCLK and the number of bytes allowed between clock correction sequences Table 2 14 Data Bytes Allowed Between Clock Corrections as a Function of REFCLK Stability and IDLE Sequences Removed Bytes Allowed Between Clock Correction Sequences REFCLK Remove 1 IDLE 2 Remove 2 IDLE Remove 3 IDLE Remove 4 IDLE Stability Sequence Sequences Sequences Sequences 100 ppm 5 000 10 000 15 000 20 000 50 ppm 10 000 20 000 30 000 40 000 20 ppm 25 000 50 000 75 000 100 000 Notes 1 All numbers are approximate 2 IDLE the defined clock correction sequence CLK CORRECT USE This attribute controls whether the PCS will repeat skip the clock correction sequences CCS from the elastic buffer to compensate for differences between the clock recovered from serial data and the reference clocks When this attribute is set to TRUE the clock correction is enabled If set to FALSE clock correction is disabled When clock correction is disabled RXRECCLK must drive the receive logic in the fabric Otherwise the elastic buffer may over underflow www
81. ERA 123 Setup Hold Times of Inputs Relative to 123 Clock to Output Delays 2224 2206s e hn OR d E saa 123 8 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 XILINX Clock Pulse Width 124 Timing Parameter Tables and 124 Appendix B 8B 10B Valid Characters Valid Data Characters 129 Valid Control Characters K Characters 137 Appendix C Related Online Documents Application Notes eco sore o mE 139 648 Serial Backplane Interface to a Shared 139 649 SONET Rate Conversion in Virtex II Pro Devices 139 XAPP651 SONET and OTN Scramblers Descramblers 139 XAPP652 Word Alignment and SONET SDH Deframing 140 XAPP660 Partial Reconfiguration of RocketIO Pre emphasis and Differential Swing Control Attributes 140 XAPP661 RocketIO Transceiver Bit Error Rate Tester 140 XAPP662 In Circuit Partial Reconfiguration of RocketIO Attributes 140 XAPP669 PPC405 PPE Reference System Using Virtex II Pro RocketIO Transceivers 141 XAPP670 Minimizing Receiver Elastic Buf
82. FCLK out std logic DCM LOCKED in std logic RST out std logic end gt reset architecture RTL of gt reset is signal startup count std logic vector 7 downto 0 begin process USRCLK2 M DCM LOCKED begin if USRCLK2 M event and USRCLK2 M 1 then if DCM LOCKED 0 then startup count 00000000 elsif DCM LOCKED 1 then Startup count lt startup count 00000001 end if end if if USRCLK2 M event and USRCLK2 M 1 then if DCM LOCKED 0 then RST lt 141 elsif startup count 00000010 then RST lt 705 end if end if end process end RTL www xilinx com RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 1 800 255 7778 Reset Power Down XILINX Verilog Template Module gt_reset Description Verilog Submodule 7 reset for4 byte GT Device Virtex II Pro Family module gt_reset USRCLK2_M DCM_LOCKED RST input USRCLK2_M input DCM_LOCKED output RST wire USRCLK2_M wire DCM_LOCKED reg RST reg 7 0 startup_counter always 8 posedge USRCLK2_M if DCM LOCKED startup counter 8 h0 else if startup counter 8 h02 startup counter lt startup counter 1 always posedge USRCLK2 M or negedge DCM LOCKED if DCM LOCKED RST lt 1 b1 else RST lt startup counter 8 h02 endmodule RocketlO Transceiver User Guide www xilinx com
83. Figure 2 13 page 63 for each byte specified by the byte mapping section 24 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 List of Available Ports XILINX Table 1 5 GT_CUSTOM GT AURORA GT_FIBRE_CHAN 2 GT ETHERNET O GT INFINIBAND and GT XAUI Primitive Ports Continued Port TXCHARISK 9 1 0 I Port Size 1 2 4 Definition If 8B 10B encoding is enabled this control bus determines if the transmitted data is a K character or a Data character A logic High indicates a K character TXDATA 9 8 16 32 Transmit data that can be 1 2 or 4 bytes wide depending on the primitive used TXDATA 7 0 is always the last byte transmitted The position of the first byte depends on selected TX data path width TXFORCECRCERR Specifies whether to insert error in computed CRC When TRUE the transmitter corrupts the correctly computed CRC value by XORing with the bits specified in attribute TX CRC FORCE VALUE This input can be used to test detection of CRC errors at the receiver TXINHIBIT If a logic High the TX differential pairs are forced to be a constant 1 0 TXN 1 TXP 0 TXKERR 1 2 4 If 8B 10B encoding is enabled this signal indicates High when the K character to be transmitted is not a valid K character Bits correspond to the byte mapping scheme TXN Transmit diff
84. Figure 2 14 page 63 RXUSRCLK Clock from a DCM or a BUFG that is used for reading the RX elastic buffer It also clocks CHBONDI and CHBONDO in and out of the transceiver Typically the same as TXUSRCLK RXUSRCLK2 Clock output from a DCM that clocks the receiver data and status between the transceiver and the FPGA core Typically the same as TXUSRCLK2 The relationship between RXUSRCLK and RXUSRCLK2 depends on the width of RXDATA TXBUFERR Provides status of the transmission FIFO If asserted High an overflow underflow has occurred When this bit becomes set it can only be reset by asserting TXRESET 558 10 9 1 2 4 This control signal determines whether the 8B 10B encoding is enabled or bypassed If the signal is asserted High the encoding is bypassed This creates a 10 bit interface to the FPGA core See the 8B 10B section for more details TXCHARDISPMODE 1 2 4 If 8B 10B encoding is enabled this bus determines what mode of disparity is to be sent When 8B 10B is bypassed this becomes the first bit transmitted Bit a of the 10 bit encoded TXDATA bus section see Figure 2 13 page 63 for each byte specified by the byte mapping TXCHARDISPVAL 1 2 4 If 8B 10B encoding is enabled this bus determines what type of disparity is to be sent When 8B 10B is bypassed this becomes the second bit transmitted Bit b of the 10 bit encoded TXDATA bus section see
85. GN COMMA MSB FALSE FALSE FALSE BOND LIMIT 16 16 1 BOND MODE CHAN_BOND_OFFSET 8 8 0 CHAN_BOND_ONE_SHOT FALSE FALSE TRUE CHAN BOND SEQ 1 1 00101111100 00000000000 00000000000 CHAN BOND SEQ 1 2 00000000000 00000000000 00000000000 CHAN BOND SEQ 1 3 00000000000 00000000000 00000000000 CHAN BOND SEQ 1 4 00000000000 00000000000 00000000000 BOND SEQ 2 1 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 2 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 3 00000000000 00000000000 00000000000 CHAN BOND SEQ 2 4 00000000000 00000000000 00000000000 BOND SEQ 2 USE FALSE FALSE FALSE CHAN BOND SEQ LEN 1 1 1 CHAN BOND WAIT 8 8 7 CLK COR INSERT IDLE FLAG FALSEO FALSE FALSEO CLK COR KEEP IDLE FALSE 2 FALSE FALSE 2 CLK_COR_REPEAT_WAIT 1 2 1 10 CLK COR SEQ 1 1 0011111011 00000000000 00110111100 CLK COR SEQ 1 2 0011111011 00000000000 00001010000 CLK COR SEQ 1 3 001111101116 00000000000 00000000000 CLK COR SEQ 1 4 00111110111 00000000000 00000000000 CLK COR SEQ 2 1 00000000000 00000000000 00000000000 RocketlO Transceiver User Guide www xilinx com 31 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 1 RocketlO Transceiver Overview Table 1 7 Default Attribute Values GT_AURORA GT_CUSTOM GT_ETHERNET Continued Attribute Default Default Default GT_AUROR
86. GNED DATA sync Indicator that aligned data is properly aligned aligned rxisk 3 0 properly aligned 4 bit RXCHARISK Inputs These are all RocketIO inputs or outputs as indicated usrclk2 RXUSRCLK2 rxreset RXRESET rxisk 3 0 RXCHARISK 3 0 rxdata 31 0 RXDATA 31 0 commas aligned to 31 24 or 15 8 rxrealign RXREALIGN rxcommadet RXCOMMADET rxchariscomma3 RXCHARISCOMMA 3 rxchariscommal RXCHARISCOMMA 1 module align comma 32 aligned data aligned rxisk sync usrclk2 rxreset rxdata rxisk rxrealign rxcommadet rxchariscomma3 rxchariscommal output 31 0 aligned data output 3 0 aligned rxisk output sync reg 31 0 aligned data reg Sync input usrclk2 input rxreset input 31 0 rxdata input 3 0 rxisk input rxrealign input rxcommadet input rxchariscomma3 input rxchariscommal reg 15 0 rxdata reg reg 1 0 rxisk reg reg 3 0 aligned rxisk reg byte sync 92 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Other Important Design Notes XILINX reg 3 0 wait_to_sync reg count This process maintains wait to sync and count which are used only to maintain output sync this provides some idea of when the output is properly aligned with the comma in aligned data 31 24
87. Generation RocketIO transceivers support a 32 bit invariant CRC fixed 32 bit polynomial shown below for Gigabit Ethernet Fibre Channel Infiniband and user defined modes 3 26 2 22 16 12 10 8 7 5 4 2 il X X x x X X X X x x X X X X 1 The CRC recognizes the SOP Start of Packet EOP End of Packet and other packet features to identify the beginning and end of data These SOP and EOP are defined by CRC_FORMAT for ETHERNET INFINIBAND and FIBRE_CHAN and in these cases the user does not need to set CRC_START_OF_PKT and CRC_END_OF_PKT Where CRC_FORMAT is USER_MODE user defined CRC_START_OF_PKT and CRC END OF PKT are used to define SOP and EOP 4 Bytes 06024 07 021102 Figure 2 29 Packet Format The transmitter computes 4 byte CRC on the packet data between the SOP and EOP excluding the CRC placeholder bytes The transmitter inserts the computed CRC just before the EOP The transmitter modifies trailing Idles or EOP if necessary to generate correct running disparity for Gigabit Ethernet and Fibre Channel The receiver recomputes CRC and verifies it against the inserted CRC Figure 2 23 shows the packet format for CRC generation The empty boxes are only used in certain protocols Ethernet The user logic must create a four byte placeholder for the CRC by placing it in TXDATA Otherwise data is overwritten CRC Latency Enabling CRC increases the transmission latency from TXDATA to TXP and TXN The enabling o
88. HOP or SLAVE_2_HOPS SLAVE 1 HOP is a Slave toa Master that can also be daisy chained to a SLAVE_2_HOPS A SLAVE_2_HOPS can only be a Slave to a SLAVE_1_HOP and its CHBONDO does not connect to another transceiver To designate a transceiver as a Master or a Slave the attribute CHAN_BOND_MODE must be set to one of three designations Master SLAVE_1_HOP or SLAVE_2_HOPS To shut off channel bonding set the transceiver attribute to off The possible values that can be used are shown in Table 2 18 Table 2 18 Bonded Channel Connections Mode CHBONDI CHBONDO OFF NA NA MASTER NA Slave 1 CHBONDI SLAVE_1_HOP Master CHBONDO Slave 2 CHBONDI SLAVE_2_HOPS Slave 1 CHBONDO NA The channel bonding sequence is similar in format to the clock correction sequence This sequence is set to the appropriate sequence for the primitives supporting channel bonding The GT_CUSTOM is the only primitive allowing modification to the sequence These sequences are comprised of one or two sequences of length up to 4 bytes each as set by CHAN_BOND_SEQ_LEN and CHAN BOND SEQ 2 USE Other control signals include the attributes e CHAN BOND WAIT e CHAN BOND OFFSET RocketlO Transceiver User Guide www xilinx com 77 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations e BOND LIMIT e CHAN BOND ONE 5 Typical values for these attributes are BOND WAIT 8 BO
89. KFX CLKFX180 LOCKED PSDONE STATUS BUFG buf1 I clkdv2 O USRCLK2_M BUFG buf2 RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 47 XILINX Chapter 2 Digital Design Considerations USRCLK M IBUFG buf3 REFCLKIN 0 REFCLKINBUF Jus endmodule Example 3 One Byte Clock This is the 1 byte data path width clocking scheme example USRCLK2 M is twice as fast as USRCLK M It is also phase shifted 180 for falling edge alignment Clocks for 1 Byte Data Path MGT DCM for 1 Byte Data Path LS REFCLK GT std 1 peaks REFCLKSEL fit i TXUSRCLK DCM REFCLK RXUSRCLK CLKIN CLK2X180 TXUSRCLK2 BEFBENREN CLKFB RXUSRCLK2 LI LJ LJ LJ RXUSRCLK2 RST RXUSRCLK UG024_04_112202 Figure 2 5 One Byte Clock VHDL Template Module ONE_BYTE_CLK Description VHDL submodule DCM for 1 byte GT Device Virtex II Pro Family library IEEE use IEEE std logic 1164 all pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity ONE BYTE CLK is port REFCLKIN in std logic RST in std logic USRCLK M out std logic USRCLK2 M out std logic REFCLK out std logic LOCK out std logic end ONE BYTE CLK E architecture ONE BYTE CLK arch of ONE BYTE CLK is
90. ND OFFSET BOND WAIT CHAN BOND LIMIT 2 x BOND WAIT Lower values are not recommended Use higher values only if channel bonding sequences are farther apart than 17 bytes Table 2 19 shows different settings for CHAN BOND ONE SHOT ENCHANSYNC in Master and Slave applications Table 2 19 Master Slave Channel Bonding Attribute Settings Master Slave BOND ONE 5 TRUE or FALSE as desired FALSE ENCHANSYNC Dynamic control as desired Tie High Ports and Attributes 78 CHAN BOND MODE An MGT can be designated as one of three types when used in a channel bonding scheme The type is designated by BOND the three values of which are MASTER SLAVE 1 and SLAVE 2 HOPS A fourth mode OFF is used when channel bonding is not being performed The Master always controls for itself and for Slaves of either type when channel bonding and clock correction will occur Masters are always connected directly to a SLAVE 1 and indirectly to a SLAVE 2 HOPS via daisy chain through a SLAVE 1 HOP This topology improves the timing characteristics of the CHBONDO and CHBONDI buses ENCHANSYNC ENCHANSYNC controls when channel bonding is enabled Table 2 19 shows the recommended settings for Master and Slaves To counter the possibility of a bit error causing a false channel bonding sequence to occur this port is usually de asserted once a group of channels have been
91. November 7 2003 1 800 255 7778 XILINX RX_DATA_WIDTH WIDTH ae EH ES ad eee a kee SRS 87 SERDES oe se pr ied parra e e tue 87 TERMINATION SPEO Ue Y EROR 87 TXPOLARITY RXPOLARITY ausa px ER See a as ein Gre PC Ip I UT E Petite 88 TX DIFF CTRL EMPHASIS onto aei GU qha coho ganar eset Gane E oe Roin 88 LOOPBACK 2723x231 023 koe que bdo dr au kya paca qe ica eed aun 88 Other Important Design 90 Receive Data Path 32 bit 90 32 bit Alignment 91 bn MD end 91 edad 94 Chapter 3 Analog Design Considerations Serial VO Description ususse pex X REVERRAVATRA KREFERA Ra RR a Rea 99 Pte emphasis Techniques Ron nde ON RC ERG Rt on ena 100 Differential Receiver 103 Un E 103 Clock and Data Reebvety i2 idees nixa Rai edd obe uly be ede RATHER Cea 103 PCB Design 104 Power Conditioning ede e e eed 104 Voltage Regulation uu Las t
92. OL Toegc TPOL Control inputs TXPOLARITY _ TINH Control inputs TXINHIBIT Tocck_LBK Tecxe_LBK Control inputs LOOPBACK 1 0 125 XILINX Appendix RocketlO Transceiver Timing Model Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 Continued Parameter Function Signals Control inputs TXRESET Control inputs TXCHARISK 93 0 Control inputs TXCHARDISPMODE 8 0 TCDV Tocgc TCDV Control inputs TXCHARDISPVAL 3 0 Data inputs CONFIGIN TaGpck TDAT Tockp Data inputs TXDATA 31 0 Clock to Out _ Status outputs TXBUFERR Status outputs TXKERR 3 0 Tcckpo TRDIS Data outputs TXRUNDISP 3 0 Tcckpo CFGOUT Data outputs CONFIGOUT Clock TporwH Clock pulse width High state TXUSRCLK2 TTX2PWH Clock pulse width Low state TXUSRCLK2 Table A 5 Miscellaneous Clock Parameters Parameter Function Signals Clock TREFPWH Clock pulse width High state REFCLK TREFPWL Clock pulse width Low state REFCLK D TBREFPWH Clock pulse width High state 2 TBREFPWL Clock pulse width Low state BREFCLK Clock pulse width High state TXUSRCLK TIX2PWL Clock pulse width Low state T
93. OLARITY 88 TXRUNDISP 61 Ports table 22 Power Supply passive filtering 106 power conditioning 104 voltage regulation 105 Pre emphasis available values 100 overview 100 scope screen captures 101 102 R Random Jitter RJ 103 Receive Data Path 32 bit Alignment 90 Receiver Buffer 86 Reference Clock generating 112 oscillator Epson for LVPECL 112 oscillator Pletronics for LVDS 112 Reset Power Down 55 RocketIO transceiver additional resources 16 analog design considerations 99 application notes 139 attributes table 26 basic architecture and capabilities 19 block diagram 20 122 channel bonding channel align ment 76 characterization reports 141 clocking 37 communications standards support ed 19 CRC Cyclic Redundancy Check 81 default attribute values tables 31 design notes analog 113 digital 90 digital design considerations 37 modifiable primitives 31 number of MGTSs per device type 19 PCB design requirements 104 ports table 22 powering 113 related online documents 139 reset power down 55 simulation and implementation 115 valid control characters K charac ters 137 valid data characters 129 white papers 142 Routing Serial Traces 109 5 SERDES Alignment overview 65 ports and attributes 65 Serial I O Description 99 Serializer 65 Setup Hold Times of Inputs Relative to Clock 123 Simulation Models 115 SmartModels 115 Synchronization Logic overview 74 ports and attribute
94. OND MODE STRING OFF MASTER SLAVE 1 HOP SLAVE 2 HOPS OFF No channel bonding involving this transceiver MASTER This transceiver is master for channel bonding Its CHBONDO port directly drives CHBONDI ports on one or more SLAVE 1 HOP transceivers SLAVE 1 This transceiver is a slave for channel bonding SLAVE 1 HOP s CHBONDI is directly driven by a MASTER transceiver CHBONDO port SLAVE 1 HOP s CHBONDO port can directly drive CHBONDI ports one or more SLAVE 2 HOPS transceivers SLAVE 2 HOPS This transceiver is a slave for channel bonding SLAVE 2 HOPS CHBONDI is directly driven by a SLAVE 1 CHBONDO port 26 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Primitive Attributes XILINX Table 1 6 RocketlO Transceiver Attributes Continued Attribute CHAN_BOND_OFFSET Description Integer 0 15 that defines offset in bytes from channel bonding sequence for realignment It specifies the first elastic buffer read address that all channel bonded transceivers have immediately after channel bonding CHAN_BOND_WAIT specifies the number of bytes that the master transceiver passes to RXDATA starting with the channel bonding sequence before the transceiver executes channel bonding alignment across all channel bonded transceivers CHAN_BOND_OFFSET specifies the first elastic buffer read address that all channel bonded transceivers have immedi
95. P19 AP18 AP23 AP22 GT X2 Y1 A18 A17 TBD A14 A13 A14 A13 A17 A16 A21 A20 A25 A24 A16 A15 A12 A11 A12 A11 A15 A14 A19 A18 A23 A22 GT X3 YO AF23 AF22 TBD AK7 AK6 AK7 AK6 AP9 AP8 AP17 AP16 AP21 AP20 AF21 AF20 AK5 AK4 AK5 AK4 AP7 AP6 AP15 AP14 AP19 AP18 GT_X3_Y1 A23 A22 TBD A7 5 A7 A6 A5 9 8 17 16 21 20 21 20 4 4 6 15 14 19 18 GT 4 YO AP9 AP8 AP17 AP16 AP7 AP6 AP15 AP14 GT X4 Y1 9 8 7 17 16 6 A15 A14 GT X5 YO AP5 APA AP13 AP12 AP3 AP2 AP10 GT X5 Y1 A5 4 13 12 2 A11 A10 GT X6 YO AP9 AP8 AP7 AP6 GT X6 Y1 9 8 7 6 GT X7 YO AP5 APA AP3 AP2 GT X7 Y1 5 4 A3 A2 GT X8 YO GT X8 Y1 GT X9 0 GT X9 Y1 118 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 MGT Package Pins XILINX Table 4 3 LOC Grid amp Package Pins Correlation for FF1517 and FF1704 FF1517 FF1704 LOC Constraints 2VP70 2VP40 2VP50 2VP70 2VP100 2VP125 GT X0 YO AW36 AW35 AW36 AW35 AW36 AW35 41 BB40 AW34 AW33 AW34 AW33 AW34 AW33 _ BB39 BB38 GT X0 Y1 A36 A35 A34 A36 A35 A34 6 A35 A34 A41 A40 A39 A33 A33 A33 A38 GT X1 YO AW32 AW31 AW32 AW31 BB37 BB36 BB41 BB40 AW30 AW29 AW30 AW29 BB35 BB34 BB3
96. PCB Design Requirements XILINX GNDA Vin gt 3VDC To operate properly the RocketIO transceiver requires a certain level of noise isolation from surrounding noise sources For this reason it is required that both dedicated voltage regulators and passive high frequency filtering be used to power the RocketIO circuitry Table 3 5 Transceiver Power Supplies Power mW Supply 2 5V DC AC Description Coupled Coupled AVCCAUXRX 90 90 Analog RX supply AVCCAUXTX 130 130 Analog TX supply VTRXO 4 y 37 5 0 RX termination supply VTTX 3750 750 TX termination supply cNDA LAE Notes 1 Power at max data rate Power figures shown do not include power requirements of VcciNr 28 mW and VccAux 48 mW which power the PCS and PMA respectively 2 See section and DC Coupling page 111 and Table 3 6 for VTRX supply restrictions and DC coupled cases 3 These numbers are based on VTTX at 2 5V for the DC and AC coupled cases VTRX at 2 5V for the DC coupled case and 1 8V for the AC coupled case Voltage Regulation The transceiver voltage regulator circuits must not be shared with any other supplies including FPGA supplies Vecinp Veco Vecaux and Vggp Voltage regulators may be shared among transceiver power supplies of the same voltage however each supply pin must still have its own separate passive filtering network See Figure 3
97. RC_USE RX_DATA_WIDTH TX_DATA_WIDTH Integer 1 2 or 4 Relates to the data width of the FPGA fabric interface RX_DECODE_USE This determines if the 8B 10B decoding is bypassed FALSE denotes that it is bypassed RX_LOS_INVALID_INCR Power of two in a range of 1 to 128 that denotes the number of valid characters required to cancel out appearance of one invalid character for loss of sync determination RX LOS THRESHOLD Power of two in a range of 4 to 512 When divided by RX LOS INVALID INCR denotes the number of invalid characters required to cause FSM transition to sync lost state RX LOSS OF SYNC FSM TRUE FALSE denotes the nature of RXLOSSOFSYNC output TRUE RXLOSSOFSYNC outputs the state of the FSM bits See RXLOSSOFSYNC page 23 for details SERDES 10B Denotes whether the reference clock is 1 10 or 1 20 the serial bit rate TRUE 1 10 FALSE 1 20 FALSE supports a serial bitstream range of 1 0 Gbps to 3 125 Gbps TRUE supports a range of 600 Mbps to 1 0 Gbps See Half Rate Clocking Scheme page 52 TERMINATION IMP Integer 50 or 75 Termination impedance of either 500 or 750 Refers to both the RX and TX TX BUFFER USE Always set to TRUE TX CRC FORCE VALUE 8 bit vector Value to corrupt TX CRC computation when input TXFORCECRCERR is High This value is XORed with the correctly computed CRC value corrupting the CRC if TX CRC FORCE VALUE is nonzero
98. RECCLK and to reliably have the signal pulse for all the data width configurations this pulse may change with respect to the USRCLKs Table 2 13 Effects of Comma Related Ports and Attributes Affects Affects Affects Character Port or Attribute Alignment and RXCHARISCOMMA RXCOMMADET RXREALIGN DEC_VALID_COMMA_ONLY DEC_PCOMMA_DETECT DEC_MCOMMA_DETECT PCOMMA_10B_VALUE 4 4 MCOMMA_10B_VALUE PCOMMA_DETECT 4l DETECT ENPCOMMAALIGN 4 ENMCOMMAALIGN Clock Recovery Overview Clock Synthesizer Synchronous serial data reception is facilitated by a clock data recovery circuit This circuit uses a fully monolithic Phase Locked Loop PLL which does not require any external components The clock data recovery circuit extracts both phase and frequency from the incoming data stream The recovered clock is presented on output RXRECCLK at 1 20 of the serial received data rate The gigabit transceiver multiplies the reference frequency provided on the reference clock input REFCLK by 20 No fixed phase relationship is assumed between REFCLK RXRECCLK and or any other clock that is not tied to either of these clocks When the 4 byte or 1 byte receiver data path is used RXUSRCLK and RXUSRCLK2 have different frequencies 1 2 and each edge of the slower clock is aligned to a falling edge of the faster clock The same relationships apply to TXUSRCLK and TXUSRCLK2 See Table 2 5 page 40 for details R
99. RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 XILINX XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT 2064 XC3090 XC4005 XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex Il EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx Inc The Programmable Log
100. This can be used to test CRC error detection in the receiver downstream TX DIFF CTRL An integer value 400 500 600 700 or 800 representing 400 mV 500 mV 600 mV 700 mV or 800 mV of voltage difference between the differential lines Twice this value is the peak peak voltage TX PREEMPHASIS An integer value 0 3 that sets the output driver pre emphasis to improve output waveform shaping for various load conditions Larger value denotes stronger pre emphasis See pre emphasis values in Table 3 2 page 100 30 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 Modifiable Primitives Modifiable Primitives XILINX As shown in Table 1 7 and Table 1 8 only certain attributes are modifiable for any primitive These attributes help to define the protocol used by the primitive Only the GT_CUSTOM primitive allows the user to modify all of the attributes to a protocol not supported by another transceiver primitive This allows for complete flexibility The other primitives allow modification of the analog attributes of the serial data lines and several channel bonding values Table 1 7 Default Attribute Values GT_AURORA GT_CUSTOM GT_ETHERNET Attribute Default Default Default GT_AURORA GT CUSTOM GT ETHERNET ALI
101. USTOM primitives Each mode has a Start of Packet SOP and End of Packet EOP setting to determine where to start and end the CRC monitoring USER MODE allows the user to define the SOP and EOP by setting the CRC START OF PKT END OF PKT to one of the valid K characters Table B 2 page 137 The CRC is controlled by USE and TX CRC USE Whenever these attributes are set to TRUE CRC is used The four modes are defined in the subsections following USER MODE USER MODE is the simplest CRC methodology The CRC checks for the SOP and calculates CRC on the data and leaves the four remainders directly before the EOP The CRC form for the user defined mode is shown in Figure 2 24 along with the timing for when RXCHECKINGCRC and RXCRCERR are asserted High with respect to the incoming data To check the CRC error detection logic in a testing mode such as serial loopback a CRC error can be forced by setting TXFORCECRCERR to High which incorporates an error into the transmitted data When that data is received it appears corrupted and the receiver signals an error by asserting RXCRCERR High at the same time RXCHECKINGCRC goes High User logic determines the procedure that is invoked when a CRC error occurs Note Data length must be greater than 20 bytes for USER MODE CRC generation For CRC to operate correctly at least four gap bytes are required between EOP of one packet and SOP of the next packet The gap may
102. XUSRCLK RX2 RXUSRCLK Pulse Width Examples Trx2pwL Minimum pulse width TX2 clock Low state TrerpwH Minimum pulse width Reference clock High state Timing Parameter Tables and Diagram The following four tables list the timing parameters as reported by the implementation tools relative to the clocks given in Table A 1 along with the RocketIO signals that are synchronous to each clock No signals are synchronous to REFCLK or TXUSRCLK A timing diagram Figure A 2 illustrates the timing relationships Table A 2 Parameters Relative to the RX User Clock RXUSRCLK page 124 Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 page 125 Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 page 125 Table A 5 Miscellaneous Clock Parameters page 126 Table A 2 Parameters Relative to the RX User Clock RXUSRCLK Parameter Function Signals Setup Hold _ _ Control inputs CHBONDIQ 3 0 Clock to Out Control outputs CHBONDOJ3 0 Clock TRxPWH Clock pulse width High state RXUSRCLK TRXPWL Clock pulse width Low state RXUSRCLK 124 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Timing Parameter Tables and Diagram XILINX Table A 3 Parameters Relative to the RX User Clock2 RXUSRCLK2 Parameter Function Signals Setup Hold T
103. XUSRCLK 8 Notes 1 REFCLK is not synchronous to any RocketIO signals 2 BREFCLK is not synchronous to any RocketIO signals 3 TXUSRCLK is not synchronous to RocketIO signals 126 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Timing Parameter Tables and Diagram 1 2 xGWL TxawH CLOCK Z N Z Tacck 1 CONTROL f N INPUTS CONTROL OUTPUTS DATA N OUTPUTS N INPUTS UG012_106_02_100101 Figure 2 RocketlO Transceiver Timing Relative to Clock Edge RocketlO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 127 XILINX Appendix RocketlO Transceiver Timing Model 128 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 7 XILINX 8B 10B Valid Characters Appendix B 8B 10B encoding includes a set of Data characters and K characters Eight bit values are coded into 10 bit values keeping the serial line DC balanced K characters are special Data characters designated with a CHARISK K characters are used for specific informative designations Table B 1 and Table B 2 show the Data and K tables of valid characters Valid Data Characters Table B 1 Valid Data Cha
104. Y OF THE align comma 32 ck k k k k k ckckck k k k K k k k kckckckck ck ck ck lt k k k k k k ck ck ck k k k k lt k ck ck k ck ck ck k ck k kk amp k k k k lt k k ck ck k k k k k ck k k k k ck k ck k k k ck ck k k k k k k k k k k k lt kk OR INFORMATION AS IS A COURTESY YOU SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES BY PROVIDING THIS DESIGN CODI J Bj XILINX EXPRESSLY DISCLAIMS ANY 94 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 Other Important Design Notes XILINX LIB USE use use use IMPLEMENTATION INCLUDING BUT NOT LIMITED ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FREE FROM CLAIMS OF INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE c Copyright 2002 Xilinx Inc All rights reserved k k k k k k k k k KK kck ck k k amp k k k k k k k k k k k k k k k k ck k KKK Virtex II Pro RocketIO comma alignment module This module reads RXDATA 31 0 from a RocketIO transceiver and copies it to its output realigning it if necessary so that commas are aligned to the MSB position 31 24 module assumes ALIGN MSB is TRUE So that the comma is already aligned to 31 24 or
105. ack it can be used instead of CLK180 to clock USRCLK or USRCLK2 of the transceiver with the use of the transceiver s local inverter saving a global buffer BUFG 40 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Clocking XILINX Example 1a Two Byte Clock with DCM The following HDL codes are examples of a simple clock scheme using 2 byte data with both USRCLK and USRCLK2 at the same frequency USRCLK_M is the input for both USRCLK and USRCLK2 Clocks for 2 Byte Data Path MGT DCM for 2 Byte Data Path REFCLK IBUFGDS REFCLK_P RXUSRCLK TXUSRCLK2 RXUSRCLK2 Figure 2 2 Two Byte Clock with DCM VHDL Template Module TWO_BYTE_CLK Description VHDL submodule DCM for 2 byte GT Device Virtex II Pro Family GT_std_2 REFCLKSEL REFCLK TXUSRCLK2 RXUSRCLK2 TXUSRCLK RXUSRCLK ug024 02a 112202 library IEEE use IEEE std logic 1164 all pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity TWO BYTE CLK is port REFCLKIN in std logic RST in std logic USRCLK M out std logic REFCLK out std logic LOCK out std logic end TWO BYTE architecture TWO BYTE CLK arch of TWO BYTE CLK is Components Declarations component BUFG port I in std logic O out std logic end
106. ait to sync std logic vector 3 DOWNTO 0 SIGNAL count std logic SIGNAL rxdata hold std logic vector 31 DOWNTO 0 SIGNAL rxisk hold std logic vector 3 DOWNTO 0 SIGNAL sync hold std logic BEGIN aligned data rxdata hold aligned rxisk rxisk hold sync lt sync hold This process maintains wait to sync and count which are used only to maintain output sync this provides some idea of when the output is properly aligned with the comma in aligned data 31 24 The counter is set to a high value whenever the elastic buffer is reinitialized that is upon asserted RXRESET or RXREALIGN Count down is enabled whenever a comma is known to have come through the comma detection circuit that is upon an asserted RXREALIGN or RXCOMMADET PROCESS usrclk2 BEGIN IF usrclk2 EVENT AND usrclk2 1 THEN IF rxreset 1 THEN wait to sync 1111 count lt 0 ELSE IF rxrealign 1 THEN wait_to_syne lt 1111 count lt 17 ELSE IF count l THEN IF wait to sync 0000 THEN wait to sync wait to sync 0001 END IF END IF IF rxcommadet 1 THEN count 2 t Tuta END IF END IF END IF END IF END PROCESS This process maintains output sync which indicates when outgoing aligned data should be properly aligned with the comma in aligned data 31 24 Output aligned data is 96 ww
107. alue Mu 06024 23 042503 Figure 3 15 AC Coupled Serial Link DC coupling direct connection is preferable in cases where RocketIO transceivers are interfaced with other RocketIO transceivers or other Mindspeed transceivers that have compatible differential and common mode voltage specifications Passive components are not required when DC coupling is used This is illustrated in Figure 3 16 Zo 1000 Differential 02 HX Pd UG024_24_042503 Figure 3 16 DC Coupled Serial Link RocketIO differential receiver produces the best bit error rates when its common mode voltage falls between 1 6V and 1 8V When the receiver is AC coupled to the line is the sole determinant of the receiver common mode voltage and therefore must be set to a value within this range When two transceivers both terminated with 2 5V are DC coupled the common mode voltage will establish itself at around 1 7V to 1 8V and Vrrx voltages for different coupling environments are summarized in Table 3 6 Table 3 6 Vqgy and for AC and DC Coupled Environments Coupling VIRX 1 6V to 1 8V 2 5 5 DC 2 5V 5 0 2 5V 5 0 Notes 1 The recommended voltage for DC coupled implementations is 2 5V However any voltage is valid as long as a VIRX b Vrgx and Vrrx are within the specifications shown in Table 3 5 page 105 RocketlO
108. apter 3 Explanatory material added regarding settings when AC DC coupling is used Table 4 1 Corrected pinouts for FG256 and FG456 Table 4 3 Corrected pinouts for FF1517 XC2VP70 11 07 03 22 Section Clock Signals in Chapter 2 Added material that states the reference clock must be provided at all times any added jitter on the reference clock will be reflected on the RX TX I O Figure 2 3 Added a BUFG after the IBUFGDS reference clock buffer Section BUFFER USE in Chapter 2 Corrected erroneous USRCLK2 to RXUSRCLK RXUSRCLK2 Table 2 20 Added footnotes qualifying the maximum receive side latency parameters given in the table Section FIBRE CHAN in Chapter 2 Added specification for minimum data length 24 bytes not including CRC placeholder Section ETHERNET in Chapter 2 Added note indicating that Gigabit Ethernet 802 3 frame specifications must be adhered to Table 2 23 Corrected External to Internal loopback Improved explanation of Parallel Mode loopback Added Figure 2 28 Serial and Parallel Loopback Logic Section Clock and Data Recovery in Chapter 3 Corrected text to make clear that is always 1 20th the incoming data rate and that CDR requires minimum number of transitions to achieve and maintain a lock on the received data Section Voltage Regulation in Chapter 3 Added material defining voltage regulator requirements when a de
109. at share a reference plane If the signal layers do not share a reference plane a capacitor of value 0 01 uF should be connected across the two reference layers close to the vias where the signals change layers If both of the reference layers are DC coupled if they are both ground they can be connected with vias close to where the signals change layers To control crosstalk serial differential traces should be spaced at least five trace separation widths from all other PCB routes including other serial pairs A larger spacing is required if the other PCB routes carry especially noisy signals such as TTL and other similarly noisy standards The RocketIO transceiver is designed to function at 3 125 Gbps through 40 inches of PCB with two high bandwidth connectors Longer trace lengths require either a low loss dielectric or considerably wider serial traces Differential Trace Design The characteristic impedance of a pair of differential traces depends not only on the individual trace dimensions but also on the spacing between them The RocketIO transceivers require either 1000 or 1500 differential trace impedance depending on whether the 500 or 75Q termination option is selected To achieve this differential impedance requirement the characteristic impedance of each individual trace must be slightly higher than half of the target differential impedance A field solver should be used to determine the exact trace geometry suited to the spe
110. ately after channel bonding alignment as a positive offset from the beginning of the matched channel bonding sequence in each transceiver For optimal performance of the elastic buffer CHAN_BOND_WAIT and CHAN_BOND_OFFSET should be set to the same value typically 8 CHAN_BOND_ONE_SHOT TRUE FALSE that controls repeated execution of channel bonding FALSE Master transceiver initiates channel bonding whenever possible whenever channel bonding sequence is detected in the input as long as input ENCHANSYNC is High and RXRESET is Low TRUE Master transceiver initiates channel bonding only the first time it is possible channel bonding sequence is detected in input following negated RXRESET and asserted ENCHANSYNC After channel bonding alignment is done it does not occur again until RXRESET is asserted and negated or until ENCHANSYNC is negated and reasserted Always set Slave transceivers CHAN_BOND_ONE_SHOT to FALSE CHAN BOND SEQ 11 bit vectors that define the channel bonding sequence The usage of these vectors also depends on BOND SEQ LEN and BOND SEQ 2 USE See Receiving Vitesse Channel Bonding Sequence page 63 for format CHAN BOND SEQ 2 USE Controls use of second channel bonding sequence FALSE Channel bonding uses only one channel bonding sequence defined by CHAN BOND SEQ 1 1 4 TRUE Channel bonding uses two channel bonding sequences defined by CHAN BOND SEQ 1 1
111. be matched as closely as possible The equation that produces this maximum lag time result is lag time ns 1 serial speed Gbps number of lag bytes 10 bits byte or for schemes that do not use 8B 10B encoding 1 serial speed Gbps number of 10 bit lag characters 10 bits character In the example above 1 3 125 Gbps 4 5 bytes 10 bits byte 14 4 ns The recommended setting of 8 is set for protocols such as Infiniband and XAUI which can repeat the CBS every 16 and 17 bytes respectively However CHAN BOND WAIT can grow accordingly if CBSes are spaced farther apart RocketlO Transceiver User Guide www xilinx com 79 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations CHAN_BOND_OFFSET CHAN_BOND_WAIT CHAN_BOND_OFFSET measures the number of bytes past the beginning of the channel bonding sequence However this value must always equal CHAN_BOND_WAIT CHAN_BOND_LIMIT 2X CHAN_BOND_WAIT CHAN BOND LIMIT defines the expiration time after which the Slave will invalidate the most recently seen CBS location in the RX buffer For proper alignment this value must always be set to two times CHAN BOND WAIT CHBONDDONE This port indicates when a channel alignment has occurred in the MGT When it is asserted RXDATA is valid after RXCLKCORCNT goes to a 101 Note The Slave s RXCLKCORONT will go to 101 regardless of whether the channel bonding was successful or
112. ble 2 12 Possible Locations of Comma Character Data Path Width ALIGN COMMA MSB 1 byte 2 bytes 4 bytes 7 0 15 8 7 0 31 24 23 16 15 8 7 0 TRUE Y Y Y Y FALSE Y Y ENPCOMMAALIGN ENMCOMMAALIGN These two alignment ports control how the PMA aligns incoming serial data It can align on a minus comma negative disparity a plus comma positive disparity both or neither if comma alignment is not desired These signals are latched inside the transceiver with RXRECCLK Care must be taken not to de assert these signals at the improper time Comma detection may be vulnerable to spurious realignment if RXRECCLK occurs at the wrong time To avoid this problem ENPCOMMAALIGN and ENMCOMMAALIGN should be passed through a flip flop that is clocked with RXRECCLK These flip flops should be located near the MGT and RXRECCLK should use local interconnect not global clock resources to reduce skew For both top and bottom edges the best slices to use are in the CLB immediately to the left of the transceiver next to the bottom of the transceiver For the top side of the chip this is the fourth CLB row for the bottom side the bottom CLB row For example for the XC2VP7 here are the best slices to use for two of the transceivers e For GT X0YI top edge the best slices are SLICE X15Y72 and SLICE X15Y73 e For GT X0YO bottom edge the best slices are SLICE X14Y0 and SLICE 14 1
113. ble 2 3 BREFCLK Pin 39 Table 2 4 Data Width Clock 40 Table 2 5 DCM Outputs for Different DATA WIDTHs 40 Table 2 6 Latency through Various Transmitter Components Processes 54 Table 2 7 Latency through Various Receiver Components Processes 55 Table 2 8 Reset and Power Control Descriptions 55 Table 2 9 Power Control 55 Table 2 10 8 10 Bypassed Signal Significance 60 Table 2 11 Running Disparity 61 Table 2 12 Possible Locations of Comma 66 Table 2 13 Effects of Comma Related Ports and Attributes 69 Table 2 14 Data Bytes Allowed Between Clock Corrections as a Function of REFCLK Stability and IDLE Sequences 71 Table 2 15 Clock Correction Sequence Data Correlation for 16 Bit Data Port 72 Table 2 16 Applicable Clock Correction 72 Table 2 17 RXCLKCORCNT 74 Table 2 18 Bonded Channel Connections 77 Table 2 19 Master
114. ceiver primitives provided These primitives carry attributes set to default values for the communications protocols listed in Table 1 2 Data widths of one two and four bytes are selectable for each protocol Table 1 4 Supported RocketlO Transceiver Primitives Primitives Description Primitive Description GT CUSTOM deed er GT XAUI 2 2 ZEE E GT FIBRE CHAN 2 1 INFINIBAND 1 2 1 byte GT_FIBRE_CHAN_4 GT INFINIBAND 2 2l 2 byte GT ETHERNET 1 GT INFINIBAND 4 12 pay byte datapath CTAURORA4 foye data path There are two ways to modify the RocketIO transceiver e Static properties can be set through attributes in the HDL code Use of attributes are covered in detail in Primitive Attributes page 26 e Dynamic changes can be made by the ports of the primitives The RocketIO transceiver consists of the Physical Media Attachment PMA and Physical Coding Sublayer PCS The PMA contains the serializer deserializer SERDES TX and RX buffers clock generator and clock recovery circuitry The PCS contains the 8B 10B encoder decoder and the elastic buffer supporting channel bonding and clock correction The PCS also handles Cyclic Redundancy Check CRC Refer again to Figure 1 1 showing the RocketIO transceiver top level block diagram and FPGA interface signals RocketlO Transceiver Instantiations For
115. channel bonding is implemented Because of the delay limitations on the CHBONDO to CHBONDI ports linking of the Master to aSlave 1 hop must run either in the X or Y direction but not both In Figure 4 1 the two Slave 1 hops are linked to the master in only one direction To navigate to the other slave a Slave 2 hops both X and Y displacement is needed This slave needs one level of daisy chaining which is the basis of the Slave 2 hops setting Figure 4 2 shows the channel bonding mode and linking for a 2VP50 which optionally contains more transceivers 16 per chip RocketlO Transceiver User Guide www xilinx com 115 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 4 Simulation and Implementation MASTER SLAVE_1_HOP CHBONDI CHBONDO CHBONDI CHBONDO Top of device Bottom of device CHBONDI CHBONDO CHBONDI CHBONDO SLAVE_1_HOP SLAVE_2_HOPS UG024_08_020802 Figure 4 1 2VP2 Implementation SLAVE_1_HOP SLAVE_1_HOP SLAVE_1_HOP MASTER SLAVE_1_HOP SLAVE_1_HOP SLAVE_1_HOP CHBONDI CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBOND CHB NDO CHBONDI CHBONDO CHBOND CHBONDO CHBOND CHBONDO SLAVE 1 HOP CHBONDI CHBONDO Top of device Bottom of device CHBONDO CHBONDI CHBONDO CHBONDO CHBOND CHBONDO CHBONDI CHBONDO CHBOND CHBONDO CHBOND CHBONDO CHBONDI SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 2 HOPS SLAVE 1
116. cific application Figure 3 12 This task should not be left up to the PCB vendor RocketlO Transceiver User Guide www xilinx com 109 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations W I W 7 9 mil 0 201 mm 5 0 mil 0 127 20 500 Reference Plane UG024_21_042903 Figure 3 12 Single Ended Trace Geometry Trace lengths up to 20 in FR4 may be of any width provided that the differential impedance is 1000 or 1500 Trace lengths between 20 and 40 in must be at least 8 mils wide and have a differential impedance of 1009 or 1500 For information on other dielectric materials please contact your Xilinx representative or the Xilinx Hotline Differential impedance of traces on the finished PCB should be verified with Time Domain Reflectometry TDR measurements Tight coupling of differential traces is recommended Tightly coupled traces as opposed to loosely coupled maintain a very close proximity to one another along their full length Since the differential impedance of tightly coupled traces depends heavily on their proximity to each other it is imperative that they maintain constant spacing along their full length without deviation If it is necessary to separate the traces in order to route through a pin field or other PCB obstacle it can be helpful to modify the trace geometry in the vicinity of the obstacle to correct for the impedance discontin
117. coded or a 10 bit unencoded sequence These sequences require that the encoding scheme allows the comma detection and alignment circuitry to properly align data in the elastic buffer See CLK CORRECT USEF above The bit definitions are the same as shown earlier in the Vitesse channel bonding example See Receiving Vitesse Channel Bonding Sequence Table 2 15 Clock Correction Sequence Data Correlation for 16 Bit Data Port Attribute Settings TXDATA 10 Bit Data Mode Character CHARISK hex CLK COR SEQ 8 Bit Data Mode 8B 10B Bypass CLK COR SEQ11 00110111100 10011111010 K28 5 1 BX CLK COR SEQ 1 2 00010010101 11010100010 D214 0 95 CLK COR SEQ 13 00010110101 11010101010 D21 5 0 B5 CLK COR SEQ14 00010110101 11010101010 D21 5 0 B5 COR_SEQ_LEN To define the CCS length this attribute takes the integer value 1 2 3 or 4 Table 2 16 shows which sequences are used for the four possible settings of CLK_COR_SEQ_LEN Table 2 16 Applicable Clock Correction Sequences CLK_COR_SEQ_1 CLK_COR_SEQ_2 GLK SEQ That Are Applicable That Are Applicable 1 1_1 2_1 2 11 12 21 22 3 11 12 13 21 22 23 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Clock Recovery XILINX Table 2 16 Applicable Clock Correction Sequences CLK COR SEQ 1 CLK COR SEQ 2 CLK_COR_SEGQ_LEN That Are Applicable That Are Appl
118. com 89 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations Other Important Design Notes Receive Data Path 32 bit Alignment The RocketIO transceiver uses the attribute ALIGN_COMMA_MSB to align protocol delimiters with the use of comma characters special K characters K28 5 K28 1 and K28 7 for most protocols Setting ALIGN_COMMA_MSB to TRUE FALSE determines where the comma characters appear on the RXDATA bus When ALIGN COMMA MSB is set to FALSE the comma can appear in any byte lane of RXDATA in the 2 and 4 byte primitives When ALIGN MSBis set to TRUE the comma appears in RXDATA 15 8 for the 2 byte primitives and in either RXDATA 15 8 or RXDATA 31 24 for the 4 byte primitives See ALIGN_COMMA_MSB page 65 In the case of a 4 byte primitive the transceiver sets comma alignment with respect to its 2 byte internal data path but it does not constrain the comma to appear only in RXDATA 31 24 Logic must be designed in the FPGA fabric to handle comma alignment for the 32 bit primitives when implementing certain protocols Note that FPGA logic is not required for 1 byte and 2 byte configurations One such protocol is Fibre Channel Delimiters such as IDLES SOF and EOF are four bytes long and are assumed by the protocol logic to be aligned on a 32 bit boundary The Fibre Channel IDLE delimiter is four bytes long and is composed of characters K28 5 D21 4 D21 5 an
119. compatible transceivers In chip to chip PCB applications 500 termination and 1000 differential transmission lines are recommended When routing a differential pair the complementary traces must be matched in length to as close a tolerance as is feasible Length mismatches produce common mode noise and radiation Severe length mismatches produce jitter and unpredictable timing problems at the receiver Matching the differential traces to within 50 mils 1 27 mm produces a robust design Since signals propagate in FR4 PCB traces at approximately 180 ps per inch a difference of 50 mils produces a timing skew of roughly 9 ps Use SI CAD tools to confirm these assumptions on specific board designs All signal traces must have an intact reference plane beneath them Stripline and microstrip geometries may be used The reference plane should extend no less than five trace widths to either side of the trace to ensure predictable transmission line behavior Routing of a differential pair is optimally done in a point to point fashion ideally remaining on the same PCB routing layer As vias represent an impedance discontinuity layer to layer changes should be avoided wherever possible It is acceptable to traverse the PCB stackup to reach the transmitter and receiver package pins If serial traces must change layers care must be taken to ensure an intact current return path For this reason routing of high speed serial traces should be on signal layers th
120. contain clock correction sequences provided that at least 4 bytes of gap remain after all clock corrections RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 CRC Cyclic Redundancy Check XILINX FIBRE_CHAN The FIBRE_CHAN CRC is similar to USER_MODE CRC Figure 2 24 with one exception In FIBRE_CHAN SOP and EOP are predefined protocol delimiters Unlike USER_MODE FIBRE_CHAN does not need to define the attributes CRC_START_OF_PKT and CRC_END_OF_PKT Both USER_MODE and FIBRE_CHAN however disregard SOP and EOP in CRC computation oor RXCHECKINGCRC a L RXCRCERR 1 06024 12 022803 Figure 2 24 USER MODE FIBRE CHAN Mode Designs should generate only the EOP frame delimiter for a beginning running disparity RD that is negative These are the frame delimiters that begin with K28 5 D21 4 or K28 5 D10 4 Never generate the EOP frame delimiter for a beginning RD that is positive These are the frame delimiters that begin with K28 5 D21 5 or K28 5 D10 5 When the RocketIO CRC determines that the running disparity must be inverted to satisfy Fibre Channel requirements it will convert the second byte of the EOP frame delimiter D21 4 or D10 4 to the value required to invert the running disparity D21 5 or D10 5 Note that CRC generation for EOP requires that the transmitted K28 5 be left justified in the MGT s internal two byte data path Observin
121. curs TUNLOCK cycles PLL length 75 non Requirement transitions when bypassing 8B 10B Notes 1 BREFCLK for speeds of 2 5 Gbps or greater 2 Jitter measured at BGA ball 3 Tr ock from a loss of sync state depends on serial speed and length of sequence used Please see the Characterization Report for more details An additional feature of CDR is its ability to accept an external precision clock REFCLK which either acts to clock incoming data or to assist in synchronizing the derived RXRECCLK For further clarity TXUSRCLK is used to clock data from the FPGA core to the TX FIFO The FIFO depth accounts for the slight phase difference between these two clocks If the clocks are locked in frequency then the FIFO acts much like a pass through buffer PCB Design Requirements 104 In order to ensure reliable operation of the RocketIO transceivers certain requirements must be met by the designer This section outlines these requirements governing power filtering networks high speed differential signal traces and reference clocks Any designs that do not adhere to these requirements will not be supported by Xilinx Inc Power Conditioning Each RocketIO transceiver has five power supply pins all of which are sensitive to noise Table 3 5 summarizes the power supply pins their names associated voltages and power requirements RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778
122. d the user logic must be clocked with RXRECCLK Miscellaneous Signals Ports and Attributes Several ports and attributes of the MGT have very unique functionality The following do not have large roles in the other functionality discussed so far RX_DATA_WIDTH TX_DATA_WIDTH These two attributes define the data width in bytes of RXDATA and TXDATA respectively The possible values of each attribute are 1 2 and 4 which correspond to 8 16 and 32 bit data buses when 8B 10B encoding decoding is used See 8B 10B Encoding Decoding page 58 The bus widths are 10 20 and 40 bits when 8B 10B encoding decoding is bypassed SERDES_10B This attribute allows the MGT to expand its serial speed range The normal operational speed range of 800 Mbps to 3 125 Gbps 20 times the reference clock rate is obtained when this attribute is set to FALSE When set to TRUE the MGT serial data will run at 10 times the reference clock rate producing a speed range of 622 Mbps to 1 Gbps Table 2 22 Serial Speed Ranges as a Function of SERDES_10B SERDES_10B Reference Clock Range Serial Speed Range TRUE 60 100 MHz 600 Mbps 1 0 Gbps FALSE 50 156 25 MHz 1 0 Gbps 3 125 Gbps TERMINATION IMP Receive Termination On chip termination is provided at the receiver eliminating the need for external termination The receiver includes programmable on chip termination circuitry for 500 default or 75O impedance Rock
123. d 021 5 The comma K28 5 is transmitted in TXDATA 31 24 which the protocol logic expects to be received in RXDATA 31 24 Using Table B 1 page 129 and Table B 2 page 137 the IDLE delimiter can be translated into a hexadecimal value 0xBC95B5B5 that represents the 32 bit RXDATA word On the 32 bit RXDATA interface the received word is either 32 bit aligned or misaligned as shown in Table 2 24 In the table pp indicates a byte from a previous word of data Table 2 24 32 bit RXDATA Aligned versus Misaligned RXDATA RXDATA RXDATA RXDATA 31 24 23 16 15 8 7 0 32 bit aligned BC 95 B5 B5 CHARISCOMMA 1 0 0 0 32 bit misaligned pp pp BC 95 CHARISCOMMA 0 0 1 0 When RXDATA is 32 bit aligned the logic should pass RXDATA though to the protocol logic without modification A properly aligned data flow is shown in Figure 2 29 TXDATA X BC95B5B5 X FDB53737 X 45674893 RXDATA BC95B5B5 X FDB53737 Y 45674893 ALIGNED DATA pppppppp X BC95B5B5 X FDB53737 X 45674893 ug024 33 091602 Figure 2 29 RXDATA Aligned Correctly 90 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Other Important Design Notes XILINX When RXDATA is 32 bit misaligned the word requiring alignment is split between consecutive RXDATA words in the data stream as shown in Figure 2 30 RXDATA_REG in the figure refers to the design example code in 32 bit Align
124. d 31 DOWNTO 0 rxdata 31 DOWNTO 0 rxisk hold 3 DOWNTO 0 lt rxisk 3 DOWNTO 0 byte sync lt 0 ELSE IF rxchariscommal OR byte sync 1 THEN rxdata hold 31 DOWNTO 0 lt rxdata reg 15 DOWNTO 0 amp rxdata 31 DOWNTO 16 rxisk hold 3 DOWNTO 0 lt rxisk reg 1 DOWNTO 0 amp rxisk 3 DOWNTO 2 byte sync 1 ELSE rxdata hold 31 DOWNTO 0 rxdata 31 DOWNTO 0 rxisk hold 3 DOWNTO 0 lt rxisk 3 DOWNTO 0 END IF RocketlO Transceiver User Guide www xilinx com 97 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations END IF END IF END PROCESS END ARCHITECTURE translated 98 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 XILINX Chapter 3 Analog Design Considerations Serial I O Description The RocketIO transceiver transmits and receives serial differential signals This feature operates at a nominal supply voltage of 2 5 VDC A serial differential pair consists of a true Vp and a complement Vj set of signals The voltage difference represents the transferred data Thus Vp VN Differential switching is performed at the crossing of the two complementary signals Therefore no separate reference level is needed A graphical representation of this concept is shown in Figure 3 1 CML Output Driver U024_06_020802 Figure 3 1 Differential
125. data 4 RXRECCLK cycles channel alignment r comma realignment valid data lt 4 RXRECCLK cycles invalid data no comma received RESYNC LOSS_OF_SYNC comma received UG024_40_031803 Figure 2 21 RXLOSSOFSYNC FSM States SYNC_ACQUIRED RXLOSSOFSYNC 00 In this state a counter is decremented by 1 but not past 0 for a valid received symbol and incremented by RX_LOS_INVALID_INCR for an invalid symbol If the count reaches or RocketlO Transceiver User Guide www xilinx com 75 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations exceeds RX_LOS_THRESHOLD the FSM moves to state LOSS_OF_SYNC Otherwise if a channel bonding alignment sequence has just been written into the elastic buffer or if a comma realignment has just occurred the FSM moves to state RESYNC Otherwise the FSM remains in state SYNC_ACQUIRED RESYNC RXLOSSOFSYNC 01 The FSM waits in this state for four RXRECCLK cycles and then goes to state SYNC_ACQUIRED unless an invalid symbol is received in which case the FSM goes to state LOSS_OF_SYNC LOSS_OF_SYNC RXLOSSOFSYNC 10 The FSM remains in this state until a comma is received at which time it goes to state RESYNC Channel Bonding Channel Alignment Overview 76 Some gigabit I O standards such as XAUI specify the use of multiple transceivers in parallel for even higher data rates Words of data are split into bytes with each by
126. dicated routing to improve Jitter for serial speeds of 2 5 Gbps or greater See Table 2 2 page 38 for usage cases BREFCLK2 I 1 Alternative to BREFCLK Can be selected by REFCLKSEL CHBONDDONEO 1 Indicates receiver has successfully completed channel bonding when asserted High 4 The channel bonding control that is used only by slaves which is driven by a transceiver s CHBONDO port CHBONDO O 4 Channel bonding control that passes channel bonding and clock correction control to other transceivers CONFIGENABLE I 1 Reconfiguration enable input unused CONFIGIN I 1 Data input for reconfiguring transceiver unused CONFIGOUT O 1 Data output for configuration readback unused ENCHANSYNCO I 1 Comes from the core to the transceiver and enables the transceiver to perform channel bonding ENMCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on minus comma High realigns serial bitstream byte boundary when minus comma is detected ENPCOMMAALIGN I 1 Selects realignment of incoming serial bitstream on plus comma High realigns serial bitstream byte boundary when plus comma is detected LOOPBACK I 2 Selects the two loopback test modes Bit 1 is for serialloopback and bit 0 is for internal parallel loopback POWERDOWN I 1 Shuts down both the receiver and transmitter sides of the transceiver when asserted High This decreases the power consumption while the transceiver is shut down This input is asynchronou
127. dition of drawings showing clocking schemes without using DCM Table B 1 Corrections in Valid Data Characters Table 3 4 Data added Corrections made to power regulator schematic Figure 3 6 Table 2 23 Data added corrected 12 12 02 Added clarifying text regarding trace length vs width 03 25 03 2 0 Reorganized existing content Added new content Added Appendix C Related Online Documents Added Index 06024 v2 2 November 7 2003 www Xilinx com RocketlO Transceiver User Guide 1 800 255 7778 Date Version Revision 06 12 03 2 1 Table 1 2 Added qualifying footnote to XAUI 10GFC Table 1 5 Corrected definition of RXRECCLK Section RocketIO Transceiver Instantiations in Chapter 1 added text briefly explaining what the Instantiation Wizard does Table 2 14 Changed numerics from exact values to rounded off approximations nearest 5 000 and added footnote calling attention to this Section Clocking in Chapter 2 added text recommending use of an IBUFGDS for reference clock input to FPGA fabric Section RXRECCLK in Chapter 2 Deleted references to SERDES_10B attribute and to divide by 10 RXRECCLK is always 1 20th the data rate Section CRC FORMAT in Chapter 2 Corrected minimum data length for USER MODE to greater than 20 Table 3 5 Clarified the significance of the voltages shown in this table Section AC and DC Coupling in Ch
128. dule TWO BYTE CLK Description Verilog Submodule DCM for 2 byte GT Device Virtex II Pro Family module TWO BYTE CLK REFCLKIN REFCLK USRCLK M DCM LOCKED input REFCLKIN output REFCLK output USRCLK M output LOCKED wire REFCLKIN wire REFCLK wire USRCLK M wire DCM LOCKED wire REFCLKINBUF wire Clk i DCM dcmi CLKFB USRCLK M CLKIN REFCLKINBUF DSSEN 1 b0 PSCLK 1 b0 PSEN 1 b0 1 b 1 b PSINCDI Q y RST 0 LKO LK90 LK180 LK270 Ei Q LK2X LK2X180 LKDV LKFX LKFX180 LOCKED PSDONE STATUS 292928928499 g lt Et Q Q A BUFG buf1 RocketlO Transceiver User Guide www xilinx com 43 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations ciki 0 USRCLK M IBUFG buf2 REFCLKIN REFCLKINBUF ee endmodule Example 1b Two Byte Clock without DCM If TXDATA RXDATA are not clocked off the FPGA using the respective USRCLK2s then the DCM may be removed from the two byte clocking scheme as shown in Figure 2 3 MGT for 2 Byte Data Path no DCM GT_std_2 REFCLKSEL REFCLK TXUSRCLK2 RXUSRCLK2 IBUFGDS BUFG TXUSRCLK RXUSRCLK ug024 02b 091803 Figure 2 3 Two Byte Clock without D
129. e 106 Figure 3 8 Example Power Filtering PCB Layout for Four MG Is Top Layer 107 Figure 3 9 Example Power Filtering PCB Layout for Four MG Ts Bottom Layer 107 Figure 3 10 Example Power Filtering PCB Layout for Eight MGTs Top Layer 108 Figure 3 11 Example Power Filtering PCB Layout for Eight MGTs Bottom Layer 108 Figure 3 12 Single Ended Trace 110 Figure 3 13 Microstrip Edge Coupled Differential 110 Figure 3 14 Stripline Edge Coupled Differential 110 Figure 3 15 AC Coupled Serial 111 Figure 3 16 DC Coupled SerialLink 111 Figure 3 17 LVPECL Reference Clock Oscillator 4 112 Figure 3 18 LVPECL Reference Clock Oscillator Interface On Chip Termination 112 Figure 3 19 LVDS Reference Clock Oscillator 112 Figure 3 20 LVDS Reference Clock Oscillator Interface On Chip Termination 112 Chapter 4 Simulation and Implementation Figure 4 1 2VP2 116 Figure 4 2 2VP50 Implementation 116 Appendix A RocketlO Transceiver Timing Model Figure A 1 Rocke
130. e RX and TX PLLs from working Therefore a reference clock must be provided at all times The reference clock also clocks a Digital Clock Manager DCM or a BUFG to generate all of the other clocks for the MGT Never run a reference clock through a DCM since unwanted jitter will be introduced Any additional jitter on the reference clock will be transferred to the transceiver s RX and TX serial I O It is recommended that all reference clock sources into the FPGA be LVDS or LVPECL IBUFGDS The DCI or DT attributes of LVDS are optional Refer to the Virtex II Pro Platform FPGA User Guide Chapter 3 Design Considerations for a complete listing and discussion of IBUFGDS and other available I O primitives Also see section Reference Clock in Chapter 3 of this Guide Typically TXUSRCLK RXUSRCLK and TXUSRCLK2 RXUSRCLK2 The transceiver uses one or two clocks generated by the DCM As an example USRCLK and USRCLK2 clocks run at the same speed if the 2 byte data path is used The USRCLK must always be frequency locked to the reference clock of the RocketIO transceiver when SERDES 10B FALSE full rate operation Note The reference clock must be at least 50 MHz for full rate operation only 60 MHz for half rate operation with a duty cycle between 45 and 55 and should have a frequency stability of 100 ppm or better with jitter as low as possible Module of the Virtex Il Pro data sheet gives further details Table 2 1 Clock P
131. e before There are several possibilities that could cause unsuccessful channel bonding e Slave s CBS lagging the master by too much Essentially the Slave does not see a CBS when CHBONDO is asserted e Master CBS lags the slave by too much In this case the slave s CBS sequence has exceeded BOND LIMIT and has expired e CBS sequences appear more frequently than BOND LIMIT allows causing the Slave to align to a CBS before or after the expected one 80 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 CRC Cyclic Redundancy Check XILINX CRC Cyclic Redundancy Check Overview Cyclic Redundancy Check CRC is a procedure to detect errors in the received data RocketIO transceiver CRC logic supports the 32 bit invariant CRC calculation used by Infiniband Fibre Channel and Gigabit Ethernet CRC Operation On the transmitter side the CRC logic recognizes where the CRC bytes should be inserted and replaces four placeholder bytes at the tail of a data packet with the computed CRC For Gigabit Ethernet and Fibre Channel transmitter CRC can adjust certain trailing bytes to generate the required running disparity at the end of the packet This is discussed further in the FIBRE CHAN and ETHERNET sections under CRC_FORMAT page 82 On the receiver side the CRC logic verifies the received CRC value supporting the same standards as above CRC
132. e characteristics including readback boundary scan configuration length count and debugging http support xilinx com xlnx xweb xil publications Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil tt home jsp 16 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Conventions Conventions XILINX This document uses the following conventions An example illustrates each typographical and online convention Port and Attribute Names Input and output ports of the RocketIO transceiver primitives are denoted in upper case letters Attributes of the RocketIO transceiver are denoted in upper case letters with underscores Trailing numbers in primitive names denote the byte width of the data path These values are preset and not modifiable When assumed to be the same frequency RXUSRCLK and TXUSRCLK are referred to as USRCLK and can be used interchangeably This also holds true for RXUSRCLK2 TXUSRCLK2 and USRCLK2 Comma Definition A comma is a K character used by the transceiver to align the serial data on a byte half word boundary depending on the protocol used so that the serial data is cor
133. ecck_RRST TecKc_RRST Control input RXRESET Tecck_RPOL Tecxc_RPOL Control input RXPOLARITY _ _ Control input ENCHANSYNC Clock to Out Tocxsr_RNIT Status outputs RXNOTINTABLE 3 0 Tocxsr_RDERR Status outputs RXDISPERR 3 0 Tocxsr_RCMCH Status outputs RXCHARISCOMMA 3 0 ALIGN Status output RXREALIGN Tacksr CMDT Status output RXCOMMADET Status outputs RXLOSSOFSYNC 1 0 Tec RCCCNT Status outputs RXCLKCORCNT 2 0 Tacksr RBSTA Status outputs RXBUFSTATUS 1 0 Tecxst_RCCRC Status output RXCHECKINGCRC Toecxst_RCRCE Status output RXCRCERR Status output CHBONDDONE Status outputs RXCHARISK 3 0 Tecxsr_RRDIS Status outputs RXRUNDISP 3 0 TockpoRDAT Data outputs RXDATA 31 0 Clock TRX2PWH Clock pulse width High state RXUSRCLK2 TRX2PWH Clock pulse width Low state RXUSRCLK2 Table A 4 Parameters Relative to the TX User Clock2 TXUSRCLK2 Parameter Setup Hold Function Signals Control inputs CONFIGENABLE _ _ Control inputs TXBYPASS8B10B 3 0 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 TCRCE Control inputs TXFORCECRCERR TP
134. em eliminating the need for external components Automatic lock to reference function Five levels of programmable serial output differential swing 800 mV to 1600 mV peak peak allowing compatibility with other serial system voltage levels Four levels of programmable pre emphasis AC and DC coupling Programmable 500 750 on chip termination eliminating the need for external termination resistors Serial and parallel TX to RX internal loopback modes for testing operability Programmable comma detection to allow for any protocol and detection of any 10 bit character The RocketIO Transceiver User Guide contains these sections Preface About This Guide This section Chapter 1 RocketIO Transceiver Overview An overview of the transceiver s capabilities and how it works Chapter 2 Digital Design Considerations Ports and attributes for the six provided communications protocol primitives VHDL Verilog code examples for clocking and reset schemes transceiver instantiation 8B 10B encoding CRC channel bonding Chapter 3 Analog Design Considerations RocketIO serial overview pre emphasis jitter clock data recovery PCB design requirements RocketlO Transceiver User Guide www xilinx com 15 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Preface About This Guide e Chapter 4 Simulation and Implementation Simulation models implementation tools debugging and diagnostics
135. ember 7 2003 XILINX Similarly if RXUSRCLK is slower than RXRECCLK the buffer fills up over time The clock correction logic corrects for this by incrementing the read pointer to skip over a removable byte sequence that need not appear in the final FPGA core byte stream This is shown in the bottom buffer Figure 2 20 where the solid read pointer increments to the value represented by the dashed pointer This accelerates the emptying of the buffer preventing its overflow The transceiver design skips a single byte sequence when necessary to partially empty a buffer If attribute CLK COR REPEAT WAIT is 0 the transceiver can also skip four consecutive removable byte sequences in one step to further empty the buffer when necessary These operations require the clock correction logic to recognize a byte sequence that can be freely repeated or omitted in the incoming data stream This sequence is generally an IDLE sequence or other sequence comprised of special values that occur in the gaps separating packets of meaningful data These gaps are required to occur sufficiently often to facilitate the timely execution of clock correction The clock correction logic has the ability to remove up to four IDLE sequences during a clock correction How many IDLEs are removed depends on several factors including how many IDLEs are received and whether CLK COR IDLE is TRUE or FALSE For example if three IDLEs are received and CLK COR KEEP I
136. ent widths requires the user to change the frequency of USRCLK2 This creates a frequency ratio between USRCLK and USRCLK2 The falling edges of the clocks must align Table 2 4 shows the ratios for each of the three data widths Table 2 4 Data Width Clock Ratios Data Width Frequency Ratio of USRCLK USRCLK2 1 byte 1 20 2 byte 1 1 4 byte 210 Notes 1 Each edge of the slower clock must align with the falling edge of the faster clock Digital Manager DCM Examples With at least three different clocking schemes possible on the transceiver a DCM is the best way to create these schemes Table 2 5 shows typical DCM connections for several transceiver clocks REFCLK is the input reference clock for the DCM The other clocks are generated by the DCM The DCM establishes a desired phase relationship between TXUSRCLK 2 etc in the FPGA core and at the pad NOTE The reference clock may be any of the four MGT clocks including the BREFCLKs Table 2 5 DCM Outputs for Different DATA WIDTHs SERDES 108 px DATA wiprH PEFCLK RXUSRCLK RXUSRCLK2 FALSE 1 CLKIN CLKO CLK2X180 FALSE 2 CLKIN CLK0 CLK0 FALSE 4 CLKIN CLK180 CLKDV divide by 2 TRUE 1 CLKIN CLKDV divide by 2 CLK1800 TRUE 2 CLKIN CLKDV divide by 2 CLKDV divide by 2 TRUE 4 CLKIN CLKFX180 divide by 2 CLKDV divide by 4 Notes 1 Since CLKO is needed for feedb
137. er e Pee edes S rd He e led 105 Passive Filtering siepe ot sawas Mind merle e 106 High Speed Serial Trace Design 109 Routing Serial Traces aasawa aaa s mend ee ee ass Mas wie 109 Differential Trace Design 334 eder een bd hci pe Rd eate de ened eet 109 AC anid DC Coupling iuh pbi eesis puer eae eee e ueste tede eara 111 Reference Clock uod E sua io Race ied oed ecc ee E te ce 112 Epson EG 2121CA 2 5V LVPECL Outputs 112 Pletronics LV1145B LVDS Outputs 112 Other Important Design 113 Powering the RocketIO Transceivers 113 The POWERDOWN Port z uet e Rr Rp ex ou baw erras add edd 113 Chapter 4 Simulation and Implementation Simulation Models reete d e ce pb de ded 115 5SmartModels ciere bs oret eei eee e bere A drole 115 mE 115 Implementation Tools 22s I e ER C YER 115 e RE ERR E a RR PX HE EP 115 MGT Package dao pel o OE ACIE o e ec o e a Po DE 117 Appendix A RocketlO Transceiver Timing Model Timing Parameters RA RIA Eee C
138. erence in frequency between the recovered clock RXRECCLK and the internal FPGA core clock RXUSRCLK clock correction e To allow realignment of the input stream to ensure proper alignment of data being read through multiple transceivers channel bonding The receiver uses an elastic buffer where elastic refers to the ability to modify the read pointer for clock correction and channel bonding Ports and Attributes 86 TXBUFERR When High this port indicates that a transmit buffer underflow or overflow has occurred Once set High TXRESET must be asserted to clear this bit TX BUFFER USE This attribute allows the user to bypass the transmit buffer A value of FALSE bypasses the buffer while a TRUE keeps the buffer in the data path This attribute should always be set to TRUE www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Miscellaneous Signals XILINX RXBUFSTATUS This 2 bit port indicates the status of the receiver elastic buffer RXBUFSTATUS 1 High indicates if an overflow underflow error has occurred Once set High RXRESET must be asserted to clear this bit RXBUFSTATUS 0 High indicates that the elastic buffer is at least half full RX BUFFER USE When set to FALSE this attribute causes the receive buffer to be bypassed It should normally be set to TRUE since channel bonding and clock correction use the receive buffer for realignment When the buffer is bypasse
139. erential port FPGA external Transmit differential port FPGA external TXPOLARITY Specifies whether or not to invert the final transmitter output Able to reverse the polarity on the TXN and TXP lines Deasserted sets regular polarity Asserted reverses polarity TXRESET Synchronous TX system reset that recenters the transmit elastic buffer It also resets 8B 10B encoder and other internal transmission registers It does not reset the transmission PLL TXRUNDISP 9 1 2 4 Signals the running disparity after this byte is encoded Low indicates negative disparity High indicates positive disparity TXUSRCLK Clock output from a DCM or a BUFG that is clocked with a reference clock This clock is used for writing the TX buffer and is frequency locked to the reference clock TXUSRCLK2 Clock output from a DCM that clocks transmission data and status and reconfiguration data between the transceiver an the FPGA core The ratio between TXUSRCLK and TXUSRCLK2 depends on the width of TXDATA Notes 1 The GT_CUSTOM ports are always the maximum port size 2 GT FIBRE CHAN and GT ETHERNET ports do not have the three CHBOND or ENCHANSYNC ports 3 The port size changes with relation to the primitive selected and also correlates to the byte mapping 4 External ports only accessible from package pins RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www
140. ersed Deserializer The RocketIO transceiver core accepts serial differential data on its RXP and RXN inputs The clock data recovery circuit extracts clock phase and frequency from the incoming data stream and re times incoming data to this clock The recovered clock is presented on output RXRECCLK at 1 20 of the received serial data rate The receiver is capable of handling either transition rich 8B 10B streams or scrambled streams and can withstand a string of up to 75 non transitioning bits without an error Word alignment is dependent on the state of comma detect bits If comma detect is enabled the transceiver recognizes up to two 10 bit preprogrammed characters Upon detection of the character or characters is driven High and the data is synchronously aligned If a comma is detected and the data is aligned no further alignment alteration takes place If a comma is received and realignment is necessary the data is realigned and RXREALIGN is asserted The realignment indicator is a distinct output The transceiver continuously monitors the data for the presence of the 10 bit character s Upon each occurrence of the 10 bit character the data is checked for word alignment If comma detect is disabled the data is not aligned to any particular pattern The programmable option allows a user to align data on plus comma minus comma both or a unique user defined and programmed sequence The electrical polarity of RXP
141. etlO Transceiver User Guide www xilinx com 87 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations Transmit Termination On chip termination is provided at the transmitter eliminating the need for external termination Programmable options exist for 500 default and 75 termination TXPOLARITY RXPOLARITY TXINHIBIT A differential pair has a positive designated and a negative designated component If for some reason the polarity of these components is switched between two transceivers the data will not be passed properly If this occurs TXPOLARITY will invert the definition of the TXN and TXP pins On the receiver side of the MGT the RXPOLARITY port can invert the definition of RXN and RXP For some protocols the MGT must turn off the TXN TXP pins The TXINHIBT port shuts off the transmit pins and forces them to a constant value TXN 0 TXP 1 Asserting TXINHIBIT also disables internal serial loopback TX_DIFF_CTRL PRE_EMPHASIS These two attributes control analog functionality of the MGT The TX_DIFF_CTRL attribute is used to compensate for signal attenuation in the link between transceivers It has five possible values of 400 500 600 700 and 800 mV These values represent the peak to peak amplitude of one component of the differential pair the full differential peak to peak amplitude is two times these values The EMPHASIS attribute has four values 10 20
142. f CRC does not affect the latency from RXP and RXN to RXDATA The typical and maximum latencies expressed in TXUSRCLK RXUSRCLK cycles are shown in Table 2 20 For timing diagrams expressing these relationships please see Module 3 of the Virtex II Pro Data Sheet RocketlO Transceiver User Guide www xilinx com 81 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Table 2 20 Effects of CRC on Transceiver Latency Chapter 2 Digital Design Considerations TXDATA to TXP and TXN RXP and RXN to RXDATA TXUSRCLK Cycles in RXUSRCLK Cycles Typical Maximum Typical Maximum CRC Disabled 8 11 25 42 2 CRC Enabled 14 17 25 420 Notes 1 See Table 2 6 and Table 2 7 for all MGT block latency parameters 2 This maximum may occur when certain conditions are present and clock correction and channel bonding are enabled If these functions are both disabled the maximum will be near the typical values 3 To further reduce receive side latency refer to Appendix C Related Online Documents Ports and Attributes 82 TX_CRC_USE RX_CRC_USE These two attributes control whether the MGT CRC circuitry is enabled or bypassed When set to TRUE CRC is enabled When set to FALSE CRC is bypassed and must be implemented in the FPGA fabric CRC_FORMAT There are four possible CRC modes USER_MODE FIBRE_CHAN ETHERNET and INFINIBAND This attribute is modifiable only for the GT_XAUI and GT_C
143. f2 I cik i j O USRCLK M IBUFGbuf3 I REFCLKIN REFCLKINBUF endmodule RocketlO Transceiver User Guide www xilinx com 51 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations Half Rate Clocking Scheme Some applications require serial speeds between 600 Mbps and 1 Gbps The transceiver attribute SERDES_10B which sets the REFCLK multiplier to 10 instead of 20 enables the half rate speed range when set to TRUE With this configuration the clocking scheme also changes The figures below illustrate the three clocking scheme waveforms when SERDES_10B TRUE Clocks for 1 Byte Data Path SERDES_10B TRUE GT_std_1 CLKDV divide by 2 REFCLKSEL IBUFGDS DCM REFCLK REFCLK_P CLKIN CLKDV TXUSRCLK RXUSRCLK RST CLK0 RXUSRCLK2 TXUSRCLK2 MGT clock input invert RXUSRCLK2 ers acceptable skew UG024_29_013103 Figure 2 6 One Byte Data Path Clocks SERDES_10B TRUE Clocks for 2 Byte Data Path 0 REFCLKSEL SERDES_10B TRUE IBUFGDS REFCLK_P V TXUSRCLK REFCLK REFCLK_N u GER RXUSRCLK TXUSRCLK2 RXUSRCLK2 RXUSRCLK RXUSRCLK2 Figure 2 7 Two Byte Data Path Clocks SERDES 10B TRUE CLKDV divide by 2 06024 30 013103 Clocks for 4 Byte Data Path 222 y
144. fer Delay in the Virtex II Pro Transceiver oi seca ee cet eere Peek Pe ce dont ea ai eel 141 Characterization 255552222202 534 ERR PCR Ir ineo aca 141 Virtex II Pro RocketIO Multi Gigabit Transceiver Characterization Summary 141 Virtex II Pro RocketIO HSSDC2 Cable Characterization 142 White PAp rS sos xr debba sa teg eta aa qa eed ddp aaa 142 WP157 Usage Models for Multi Gigabit Serial Transceivers 142 WP160 Emulating External SERDES Devices with Embedded RocketIO Transceivers 142 lidex 143 RocketlO Transceiver User Guide www xilinx com 9 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX 10 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Schedule of Figures Chapter 1 RocketlO Transceiver Overview Figure 1 1 RocketIO Transceiver Block 20 Chapter 2 Digital Design Considerations Figure 2 1 Figure 2 2 Figure 2 3 Figure 2 4 Figure 2 5 Figure 2 6 Figure 2 7 Figure 2 8 Figure 2 9 Figure 2 10 Figure 2 11 Figure 2 12 Figure 2 13 Figure 2 14 Figure 2 15 Figure 2 16 Figure 2 17 Figure 2 18 Figure 2 19 Figure 2 20 Figure 2 21 Figure 2 22 Figure 2 23 Figure 2 24
145. ffer where the shaded area represents buffered data not yet read Received data is inserted via the write pointer under control of RXRECCLK The FPGA core reads data via the read pointer under control of RXUSRCLK The half full half empty condition of the buffer gives a cushion for the differing clock rates This operation continues indefinitely regardless of whether or not meaningful data is being received When there is no meaningful data to be received the incoming data consists of IDLE characters or other padding If RXUSRCLK is faster than RXRECCLK the buffer becomes more empty over time The clock correction logic corrects for this by decrementing the read pointer to reread a repeatable byte sequence This is shown in the middle buffer Figure 2 20 where the solid read pointer decrements to the value represented by the dashed pointer By decrementing the read pointer instead of incrementing it in the usual fashion the buffer is partially refilled The transceiver inserts a single repeatable byte sequence when necessary to refill a buffer If the byte sequence length is greater than one and if attribute CLK COR REPEAT WAIT is 0 then the transceiver can repeat the same sequence multiple times until the buffer is refilled to the half full condition www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Clock Recovery Ports and Attributes RocketIOTM Transceiver User Guide UG024 v2 2 Nov
146. g the following restrictions assures correct alignment of the packet delimiters e 4 byte data path K28 5 must appear in 31 24 or TXDATA 15 8 e 2 byte data path K28 5 must appear in TXDATA 15 8 l byte data path K28 5 must be strobed into the MGT on rising TXUSRCLK2 only when TXUSRCLK is High Note Minimum data length for this mode is 24 bytes not including the CRC placeholder ETHERNET The Ethernet CRC is more complex Figure 2 25 The SOP EOP and Preamble are neglected by the CRC The extension bytes are special K characters in special cases The extension bytes are untouched by the CRC as are the Trail bits which are added to maintain packet length sor sor Sara Tess Ro ss Ra EOP n Bytes 2 to 3 Bytes 00024 13 101602 Figure 2 25 Ethernet Mode Designs should generate only the K28 5 D16 2 IDLE sequence for transmission never K28 5 D5 6 When the RocketIO CRC determines that the running disparity must be inverted to satisfy Gigabit Ethernet requirements it will convert the first K28 5 D16 2 IDLE following a packet to K28 5 D5 6 performing the necessary conversion RocketlO Transceiver User Guide www xilinx com 83 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 84 Chapter 2 Digital Design Considerations Note As noted in Figure 2 25 pad bits are used to assure that the header data and CRC total to the 64 byte minimum packet length
147. h multi chip solution Links to Xilinx information resources for the Virtex II Pro Platform FPGA and embedded RocketIO transceiver are presented in the final section www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Index Numerics 8B 10B Encoding Decoding bypassing 64 decoder 58 encoder 58 overview 58 ports and attributes 59 serial output format 64 8B 10B Valid Characters 129 A AC and DC Coupling 111 Attributes amp Ports by function 8B 10B encoding decoding 59 buffers fabric interface 86 channel bonding 78 clock correction 71 CRC 82 SERDES alignment 65 synchronization logic 74 Attributes defined ALIGN_COMMA_MSB 65 CHAN_BOND_SEQ_LEN 79 CHAN_BOND_LIMIT 79 CHAN_BOND_MODE 78 CHAN_BOND_OFFSET 79 CHAN_BOND_ONE_SHOT 78 CHAN BOND SEQ 79 CHAN BOND SEQ 2 USE 79 CHAN BOND WAIT 79 CLK COR INSERT IDLE FLAG 73 CLK COR KEEP IDLE 73 CLK COR REPEAT WAIT 73 CLK COR SEQ 72 CLK COR SEQ LEN 72 CLK CORRECT USE 71 COMMA 10B MASK 68 CRC END OF PACKET 85 CRC FORMAT 82 CRC START OF PACKET 85 DEC MCOMMA DETECT 68 DEC PCOMMA DETECT 68 DEC VALID COMMA ONLY 68 MCOMMA 10B VALUE 68 MCOMMA DETECT 68 PCOMMA 10B VALUE 68 PCOMMA DETECT 68 PRE EMPHASIS 88 RX BUFFER USE 72 87 RX CRC USE 82 RX DATA WIDTH 87 RX DECODE USE 59 RX LOS INVALID INCR 75 RX LOS THRESHOLD 75 RX LOSS OF SYNC FSM 75 SERDES 10B 87 TERMINATION IMP 87 TX BUFFER USE 86
148. he 20 bits required However there is a class of applications typically in SONET processing systems where the data path is 16 bits wide running at 155 52 MHz The designer would ideally apply the data directly to the RocketIO transceiver for onward transmission at 155 52 x 16 2 48832 Gbps Since this cannot be done in Virtex II Pro devices this application note describes the logic necessary to perform this function This application note is divided into two sections the first is the logic necessary for the data width conversion and the second describes the clocking characteristics required by the RocketIO transceiver XAPP651 SONET and OTN Scramblers Descramblers Both SONET and OTN are standards for data transmission over fibre optic links This implies a need for clock recovery at the receiver which in turn requires a guaranteed minimum number of transitions in the incoming serial data stream The mechanism to achieve this transition density similar for both SONET and OTN is known as scrambling RocketlO Transceiver User Guide www xilinx com 139 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX Appendix C Related Online Documents The scrambling and descrambling function is independent of the serial data rate used Serial data for transmission is added to the output of a pseudo random number generator running at the same clock frequency The same circuit is used in the receiver to recover the original data trans
149. hronized on the data For applications using the 8B 10B encoding scheme the RX_LOSS_OF_SYNC FSM does this It can be programmed to lose sync after a specified number of invalid data characters are received Ports and Attributes 74 Clock correction count RXCLKCORCNT is a three bit signal It signals if clock correction has occurred and whether the elastic buffer realigned the data by skipping or repeating data in the buffer It also signals if channel bonding has occurred Table 2 17 defines the eight binary states of RXCLKCORCNT Table 2 17 RXCLKCORCNT Definition RXCLKCORCNT 2 0 Significance 000 No channel bonding or clock correction occurred for current RXDATA dod Elastic buffer skipped one clock correction sequence for current RXDATA 010 Elastic buffer skipped two clock correction sequence for u current RXDATA 011 Elastic buffer skipped three clock correction sequence for i current RXDATA 00 Elastic buffer skipped four clock correction sequence for i current RXDATA 101 Elastic buffer executed channel bonding for current 10 Elastic buffer repeated two clock correction sequences for current RXDATA 43 Elastic buffer repeated one clock correction sequences for current RXDATA www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Synchronization Logic XILINX RX_LOS_INVALID_INCR RX_LOS_THRESHOLD
150. ic Company is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xilinx Inc does not represent
151. icable 4 11 12 13 14 2 1 2 2 2 3 24 Notes 1 Applicable only if CLK COR SEQ 2 USE is set to TRUE CLK COR INSERT IDLE FLAG CLK COR KEEP IDLE CLK COR REPEAT WAIT These attributes help control how clock correction is implemented CLK COR INSERT IDLE FLAG is a TRUE FALSE attribute that defines the output of the RXRUNDISP port When set to TRUE RXRUNDISP is raised for the first byte of each inserted repeated clock correction sequence 8B 10B decoding enabled When set to FALSE default RXRUNDISP denotes the running disparity of RXDATA 8B 10B decoding enabled CLK COR KEEP IDLE is a TRUE FALSE attribute that controls whether or not the final byte stream must retain at least one clock correction sequence When set to FALSE default the clock correction logic is allowed to remove all clock correction sequences if needed to recenter the elastic buffer When set to TRUE it forces the clock correction logic to retain at least one clock correction sequence per continuous stream of clock correction sequences Example Elastic buffer is 75 full and clock correction is needed IDLE is the defined clock correction sequence Data stream written into elastic buffer DO IDLE IDLE IDLE IDLE D1 D2 Data stream read out of elastic buffer CLK_COR_KEEP_IDLE FALSE DO D1 D2 Data stream read out of elastic buffer CLK_COR_KEEP_IDLE TRUE CLK COR REPEAT WAIT is an integer attribute 0 31
152. ide for simple 500 750 transmission line connection The differential receiver parameters are shown in Table 3 3 Table 3 3 Differential Receiver Parameters Parameter Min Typ Max Units Conditions Serial input differential peak VIN to peak RXP RXN 175 2000 mV Vi Common mode input voltage 500 2500 mV range Tiskew Differential input skew 75 ps Receive data total jitter 1 Tyror tolerance peak to peak pee Receive data deterministic Jitter tolerance peak to peak ui Notes 1 UI Unit Interval Jitter Jitter is defined as the short term variations of significant instants of a signal from their ideal positions in time ITU Jitter is typically expressed in a decimal fraction of Unit Interval UT e g 0 3 UI Total Jitter Deterministic Jitter DJ Random Jitter RJ Deterministic Jitter DJ is data pattern dependant jitter attributed to a unique source e g Inter Symbol Interference ISI due to loss effects of the media DJ is linearly additive Random Jitter RJ is due to stochastic sources such as substrate power supply etc RJ is additive as the sum of squares and follows a bell curve Clock and Data Recovery The serial transceiver input is locked to the input data stream through Clock and Data Recovery CDR a built in feature of the RocketIO transceiver CDR keys off the rising and falling edges of incoming data and derives a
153. ify the flipped disparity 10 bit literal value disp_err char_is_k 8 bit_byte_value CHAN_BOND_SEQ 1 1 0 0 1 10111100 matches 28 5 or 28 5 CHAN BOND SEQ 12 0 1 10111100 matches K28 5 or K28 5 CHAN BOND SEQ 13 0 0 1 10111100 matches K28 5 or 28 5 CHAN BOND SEQ 1 4 0 1 10111100 matches K28 5 or 28 5 CHAN BOND SEQ LEN 4 CHAN BOND SEQ 2 USE FALSE 8B 10B Bypass Serial Output When 8B 10B encoding is bypassed the TXCHARDISPVAL and TXCHARDISPMODE bits become bits b and a respectively of the 10 bit encoded data that the transceiver must transmit to the receiving terminal Figure 2 13 illustrates the TX data map during 8B 10B bypass TXCHARDISPMODE 0 TXCHARDISPVAL 0 TXDATA 7 TXDATA O a b lc e i f g nh lj Er pe ps eee First transmitted Last transmitted 06024 10a 051602 Figure 2 13 10 Bit TX Data Map with 8B 10B Bypassed During receive when 8B 10B decoding is enabled the running disparity of the serial transmission can be read by the transceiver from the RXRUNDISP port while the RXCHARISK port indicates presence of a K character When 8B 10B decoding is bypassed these bits remain as Bits b and a respectively of the 10 bit encoded data that the transceiver passes on to the user logic Figure 2 14 illustrates the RX data map during 8B 10B bypass RXCHARISK 0 RXRUNDISP O RXDATA T RXDATA O a b c d
154. ives with specific data width paths and all byte mapped ports are affected by this situation For example a 1 byte wide data path has only 1 bit control and status bits TXKERR O0 correlating to the data bits TXDATA 7 0 Footnote 3 in Table 1 5 shows the ports that use byte mapping Table 1 9 Control Status Bus Association to Data Bus Byte Paths Control Status Bit Data Bits 0 7 0 1 15 8 2 23 16 3 31 24 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 35 XILINX Chapter 1 RocketlO Transceiver Overview 36 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 87 XILINX Chapter 2 Digital Design Considerations Clocking Clock Signals There are eight clock inputs into each RocketIO transceiver instantiation Table 2 1 REFCLK and are reference clocks generated from an external source presented to the FPGA as differential inputs The reference clocks connect to the REFCLK or BREFCLK ports of the RocketIO multi gigabit transceiver MGT While only one of these reference clocks is needed to drive the MGT BREFCLK or BREFCLK2 must be used for serial speeds of 2 5 Gbps or greater See BREFCLK page 38 The PLL architecture for the transceiver uses the reference clock as the interpolation source to clock the serial data Removing the reference clock will stop th
155. lity of the signals both distorting the waveforms and reducing their amplitude This report illustrates the effects that an industry standard cable the HSSDC2 has on waveforms transmitted from a Virtex II Pro device WP157 Usage Models for Multi Gigabit Serial Transceivers Abstract location http www xilinx com publications whitepapers This document provides an overview of the various usage models for high speed point to point serial transceiver technology While not intending to represent all the applications of this technology it provides a basic categorization and description of some of the most common uses WP160 Emulating External SERDES Devices with Embedded RocketlO Transceivers 142 Abstract location http www xilinx com publications whitepapers The Virtex II Pro Platform FPGA provides an attractive single chip solution to serial transceiver design problems that previously required multiple devices This white paper describes several different dedicated external SERDES devices and presents alternative design solutions using the Virtex II Pro Platform FPGA with RocketIO transceivers The four external devices discussed here are the Vitesse single channel VSC7123 the Vitesse quadchannelVSC7216 01 the Texas Instruments TLK3101 and the Mindspeed CX27201 The features offered by each of these devices are presented along with a discussion of how the RocketIO transceiver can afford an alternative to eac
156. lock Recovery ni bike dias eee RR apa RR RR ORE 69 Ula IAE E T 69 Clock Synthesizer bec Dr dare dees ed dre e 69 Clock and Data Recovery u aasan ri Ree dnd et 70 Clock Corftectloti py u y e as 70 Ports anid Attributes oo u agustus pak 40 71 CLK CORRECT USE y v cee Sei rack HENCE P he CY Hd ee 71 RX 0 55 dus es e ede duse o e eene toe hasqa aa Ca wq 72 CLK COR EO eu RETI TT EET IER a 72 CER COR SEQ EEN ere u whee ia a hes eth 72 CLK_COR_INSERT_IDLE_FLAG CLK_COR_KEEP_IDLE COR REPEAT WAIT u eec mee Sk Pod woe o ed 73 Synchronization ipd pe e e edel e M edere Ede d 74 OVerVIeW i siden a b FE a ud deus 74 6 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 XILINX Ports and Attributes RR ERE ne 74 eke debe Fu Re wad E CES Maks 74 RX_LOS_INVALID_INCR RX LOS THRESHOLD 6 eR eee eae Rae 75 RX LOSS OF SYNC FSM 060550 howe ieee oe bee
157. me without DCM 53 e t d cea ETE Yd 54 Clock Dependency a ea e eh rper aed eme eee Ron en eed denied arale da 54 Data Path Latency 2 doc asa yp HERE PA 54 Reset Power Down 55 8B 10B 58 OVERVIEW sede Fer KR n sles 58 8B 10B 22 22 2 4 0 E RR ME 6 66 666 58 RocketlO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 8B 10B 0 e rte kau cadet shu ua 58 Ports and 59 TXBYPASS8B10B RX DECODE USE se 5 das A E Gs 59 TXCHARDISPVAL 4 4 0 60 Ew Mat e 61 TXRUNDISP nasa OS MORSE qasa e Yd ERU NUN dr aue Eg 61 TXKBRR RR echoes EN mus ma awqa eem eg sed edt ede d k i dore n 61 RXCHARISK RXRUNDISP ssi iub ERA bua kiq buka v PINE 61 RXDISPERR 5 RERO GG EEG Da P mE A Pd REA 62 RXNOTINTABLE dcr beo pe tex eeu e S Der S ns 62 Vitesse Di
158. ment Design page 91 ug024 34 091602 Figure 2 30 Realignment of RXDATA This conditional shift delay operation on RXDATA also must be performed on the status outputs RXDISPERR RXCHARISK 5 and RXRUNDISP in order to keep them properly synchronized with RXDATA It is not possible to adjust RXCLKCORCNT appropriately for shifted delayed RXDATA because RXCLKCORCNT is summary data and the summary for the shifted case cannot be recalculated 32 bit Alignment Design The following example code illustrates one way to create the logic to properly align 32 bit wide data with a comma in bits 31 24 For brevity most status bits are not included in this example design however these should be shifted in the same manner as RXDATA and RXCHARISK Note that when using a 40 bit data path 8B 10B bypassed a similar realignment scheme may be used but it cannot rely on RXCHARISCOMMA for comma detection Verilog EER k k k k k k k k k k k k k k k k k K k k k K K K k k K k KOK KO KOK K R K K K KOK K K KOK k K K K kc IS PROVIDING 5 DESIGN CODE INFORMATION AS IS AS A COURTESY TO YOU SOLELY FOR USE IN DEVELOPING PROGRAMS AND SOLUTIONS FOR XILINX DEVICES BY PROVIDING THIS DESIGN CODE OR INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS
159. ming values see Module 3 of the Virtex II Pro data sheet The timing relationships are further discussed and illustrated in Appendix A RocketlO Transceiver Timing Model Data Path Latency With the many configurations of the MGT both the transmit and receive latency of the data path varies Below are several tables that provide approximate latencies for common configurations Table 2 6 Latency through Various Transmitter Components Processes Component Process Latency 1 Byte Data Path 2 Byte Data Path 4 Byte Data Path TX Fabric GT Interface 2 5 TXUSRCLK2 cycles 1 TXUSRCLK2 cycle 1 25 TXUSRCLK2 cycles 1 25 TXUSRCLK cycles 1 TXUSRCLK cycle 2 5 TXUSRCLK cycles included 7 TXUSRCLK cycles TX CRC bypassed 1 TXUSRCLK cycle included 1 TXUSRCLK cycle 8B 10B Encoder bypassed 1 TXUSRCLK cycle TX FIFO 4 TXUSRCLK cycles 0 5 SERDES_10B FALSE SERDES_10B TRUE 1 5 TXUSRCLK cycles 0 5 TXUSRCLK cycles approx 54 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Reset Power Down XILINX Table 2 7 Latency through Various Receiver Components Processes Component Process Latency RX SERDES 1 5 recovered clock RXRECCLK cycles 2 5 or 3 5 recovered clock cycles a some bits bypass one register depending on comma alignment included 1 recovered clock cycle 8B 10B Decoder bypassed 1 rec
160. mitted Obviously the pseudo random number generators at each end of the link must be in phase This is achieved using a known pattern of framing information which is actually transmitted unscrambled This is covered in more detail in XAPP652 XAPP652 Word Alignment and SONET SDH Deframing This application note describes the logic to perform basic word alignment and deframing specifically for SONET SDH systems where data is being processed at 16 bits or 64 bits per clock cycle XAPP660 Partial Reconfiguration of RocketlO Pre emphasis and Differential Swing Control Attributes This application note describes a pre engineered solution for Virtex II Pro devices using the PowerPC 405 core to perform a partial reconfiguration of the RocketlIO multi gigabit transceivers MGTs pre emphasis and differential swing control attributes This solution is ideal for applications where these attributes must be modified to optimize the MGT signal transmission for various system environments while leaving the rest of the FPGA design unchanged The hardware and software elements of this solution can be easily integrated into any Virtex II Pro design The associated reference design supports the following devices XC2VP4 XC2VP7 XC2VP20 and XC2VP50 The design discussed in this document uses the PPC405 core device control register DCR bus interface to implement a simple solution with a minimum of FPGA resources XAPP661 RocketlO Transceiver
161. ncoming serial bit stream before comparison against PCOMMA 10B VALUE and MCOMMA 10B VALUE 28 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Primitive Attributes XILINX Table 1 6 RocketlO Transceiver Attributes Continued Attribute END OF PKT Description NOTE This attribute is only valid when CRC FORMAT USER MODE K28 0 K28 1 K28 2 K28 3 K28 4 K28 5 K28 6 K28 7 23 7 K27 7 K29 7 K30 7 End of packet EOP K character for USER MODE CRC Must be one of the 12 legal K character values CRC FORMAT ETHERNET INFINIBAND FIBRE CHAN USER MODE CRC algorithm selection Modifiable only for GT AURORA n GT XAUI n and GT CUSTOM USER MODE allows user definition of Start of Packet SOP and End of Packet EOP K characters CRC START OF PKT NOTE This attribute is only valid when CRC FORMAT USER MODE K28 0 K28 1 K28 2 K28 3 K28 4 K28 5 K28 6 K28 7 K23 7 27 7 K29 7 K30 7 Start of packet SOP K character for USER MODE CRC Must be one of the twelve legal K character values DEC MCOMMA DETECT TRUE FALSE controls the raising of per byte flag RXCHARISCOMMA on minus comma DEC PCOMMA DETECT TRUE FALSE controls the raising of per byte flag RXCHARISCOMMA on plus comma DEC VALID COMMA ONLY TRUE FALSE controls the raising of RXCHARISCOMMA on an invalid comma FALSE Raise RXCHARISCOMMA on 0
162. nsmitted serial data 60 In the encoding configuration the disparity of the serial transmission can be controlled with the TXCHARDISPVAL and TXCHARDISPMODE ports When TXCHARDISPMODE is set High the running disparity is set before encoding the specific byte TXCHARDISPVAL determines if the disparity is negative set Low or positive set High Table 2 11 illustrates this www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 8B 10B Encoding Decoding XILINX Table 2 11 Running Disparity Control TXCHARDISPMODE Function TXCHARDISPVAL 00 Maintain running disparity normally Invert normally generated running disparity before 01 5 encoding this byte 10 Set negative running disparity before encoding this byte 11 Set positive running disparity before encoding this byte When TXCHARDISPMODE is set Low the running disparity is maintained if TXCHARDISPVAL is also set Low but the disparity is inverted before encoding the byte when TXCAHRDISPVAL is set High Most applications will use the mode where both TXCHARDISPMODE and TXCHARDISPVAL are set Low Some applications may use other settings if special running disparity configurations are required such as in the Vitesse Disparity Example below In the bypassed configuration TXCHARDISPMODE 0 becomes bit 9 of the 10 bits of encoded data TXCHARDISPMODE 1 3 are bits 19 29 and 39 in the 20 and 40 bit wide bu
163. ocketlO Transceiver User Guide www xilinx com 69 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX 70 Chapter 2 Digital Design Considerations Clock and Data Recovery The clock data recovery CDR circuits lock to the reference clock automatically if the data is not present For proper operation TXUSRCLK must have the exact same frequency as REFCLK REFCLK RXUSRCLK and the incoming stream RXRECCLK must not exceed 100 ppm of frequency variation It is critical to keep power supply noise low in order to minimize common and differential noise modes into the clock data recovery circuitry See PCB Design Requirements page 104 for more details Clock Correction Clock RXRECCLK the recovered clock reflects the data rate of the incoming data Clock RXUSRCLK defines the rate at which the FPGA core consumes the data Ideally these rates are identical However since the clocks typically have different sources one of the clocks is faster than the other The receiver buffer accommodates this difference between the clock rates See Figure 2 20 Read Write RXUSRCLK RXRECCLK L E Nominal condition buffer half full Read Write Buffer less than half full emptying Repeatable sequence Read Write Buffer more than half full filling up DS083 2 15 100901 Removable sequence Figure 2 20 Clock Correction in Receiver Nominally the buffer is always half full This is shown in the top bu
164. orts Clock I Os Description BREFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel to serial conversion 20X BREFCLK2 Input Alternative to BREFCLK RocketlO Transceiver User Guide www xilinx com 37 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations Table 2 1 Clock Ports Continued Clock Description RXRECCLK Output Recovered clock from serial data stream divided by 20 Clocks data into the elastic buffer REFCLK Input Reference clock used to read the TX FIFO and multiplied by 20 for parallel to serial conversion 20X REFCLK2 Input Alternative to REFCLK REFCLKSEL Input Selects which reference clock is used 0 selects REFCLK 1 selects REFCLK2 RXUSRCLK Input Clock from FPGA used for reading the RX Elastic Buffer Clock signals CHBONDI and CHBONDO into and out of the transceiver This clock is typically the same as TXUSRCLK TXUSRCLK Input Clock from FPGA used for writing the TX Buffer This clock must be frequency locked to REFCLK for proper operation RXUSRCLK2 Input Clock from FPGA used to clock RX data and status between the transceiver and FPGA fabric The relationship between RXUSRCLK2 and RXUSRCLK depends on the width of the receiver data path RXUSRCLK2 is typically the same as TXUSRCLK2 TXUSRCLK2 Input Clock from FPGA used to clock TX data and status between the t
165. overed clock cycle RX FIFO 18 RXUSRCLK cycles 0 5 1 Byte Data Path 2 Byte Data Path 4 Byte Data Path RX GT Fabric Interface 2 5 RXUSRCLK2 cycles 1 RXUSRCLK2 cycle 1 25 RXUSRCLK2 cycles 1 25 RXUSRCLK cycles 1 RXUSRCLK cycle 2 5 RXUSRCLK cycles Reset Power Down The receiver and transmitter have their own synchronous reset inputs The transmitter reset recenters the transmission FIFO and resets all transmitter registers and the 8B 10B encoder The receiver reset recenters the receiver elastic buffer and resets all receiver registers and the 8B 10B decoder Neither reset signal has any effect on the PLLs After the DCM locked signal is asserted the resets can be asserted The resets must be asserted for two USRCLK2 cycles to ensure correct initialization of the FIFOs Although both the transmit and receive resets can be attached to the same signal separate signals are preferred This allows the elastic buffer to be cleared in case of an over underflow without affecting the ongoing TX transmission The following example is an implementation that resets all three data width transceivers Additional reset and power control descriptions are given in Table 2 8 and Table 2 9 Table 2 8 Reset and Power Control Descriptions Ports Description RXRESET Synchronous receive system reset recenters the receiver elastic buffer and resets the 8B 10B decoder comma detect channel bonding clock correction logic and other receiver regi
166. process generates aligned_data with commas aligned in 31 24 assuming that incoming commas are aligned to 31 24 or 15 8 Here you could add code to use ENPCOMMAALIGN and ENMCOMMAALIGN to enable a move back into the byte_sync 0 state always begin if rxreset begin posedge usrclk2 or posedge rxreset rxdata_reg lt 16 h0000 aligned_data lt 32 h0000_0000 rxisk_reg lt 2 b00 aligned_rxisk lt 4 b0000 byte sync lt 1 b0 end else begin rxdata reg 15 0 lt rxdata 15 0 rxisk reg 1 0 rxisk 1 0 if rxchariscomma3 begin aligned data 31 0 rxdata 31 0 aligned rxisk 3 0 rxisk 3 0 byte sync lt 1 b0 end else if rxchariscommal byte sync begin aligned data 31 0 lt rxdata reg 15 0 rxdata 31 16 aligned rxisk 3 0 byte sync end else begin rxisk reg 1 0 rxisk 3 2 lt 1 b1 I aligned data 31 0 lt rxdata 31 0 aligned rxisk rxisk end end end endmodule VHDL AS OR X X F X Xo X XILINX IS PROVIDING THIS DESIGN CODE INFORMATION AS ONE POSSIBLE IMPLEMENTATION OF THIS FEATUR APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION THAT THIS IMPLEMENTATION IS FREE FROM ANY CLAIMS AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION WARRANTY WHATSOEVER WITH RESPECT TO THE ADEQUAC
167. racters Data Byte Bits Current RD Current RD Name HGF EDCBA abcdei fghj abcdei fghj D0 0 000 00000 00111 0100 011000 10 D1 0 000 00001 011101 0100 00010 10 D2 0 000 00010 01101 0100 010010 10 D3 0 000 0001 10001 101 10001 0100 D4 0 000 00100 10101 0100 001010 10 D5 0 000 0010 01001 1011 01001 0100 D6 0 000 00110 011001 1011 011001 0100 D7 0 000 0011 11000 101 000 0100 D8 0 000 01000 11001 0100 000110 1011 D9 0 000 0100 00101 101 00101 0100 D10 0 000 01010 010101 1011 010101 0100 D11 0 000 0101 10100 101 110100 0100 D12 0 000 01100 001101 101 001101 0100 D13 0 000 0110 01100 101 01100 0100 D14 0 000 01110 011100 101 011100 0100 D15 0 000 0111 010111 0100 01000 10 D16 0 000 10000 011011 0100 00100 10 D17 0 000 1000 100011 101 000 0100 D18 0 000 10010 010011 101 0100 0100 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 129 XILINX Appendix B 8B 10B Valid Characters Table B 1 Valid Data Characters Continued
168. ransceiver and FPGA fabric The relationship between TXUSRCLK2 and TXUSRCLK depends on the width of the transmission data path Notes 1 TXUSRCLK and TXUSRCLK2 must be driven by clock sources even if only the receiver of the MGT is being used Table 2 2 Reference Clock Usage Data Rate Routing 600 Mbps 2 500 Gbps Can Route Can Route 2 499 Gbps 3 125 Gbps Across Chip Through BUFG REFCLK BREFCLK Note 1 Note 1 Notes 1 Because of dedicated routing to reduce jitter BREFCLK cannot be routed through the fabric BREFCLK At speeds of 2 5 Gbps or greater REFCLK configuration introduces more than the maximum allowable jitter to the RocketIO transceiver For these higher speeds BREFCLK configuration is required The BREFCLK configuration uses dedicated routing resources that reduce jitter BREFCLK must enter the FPGA through dedicated clock I O BREFCLK can connect to the BREFCLK inputs of the transceiver and the CLKIN input of the DCM for creation of 38 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Clocking XILINX USRCLKs If all the transceivers on a Virtex II Pro FPGA are to be used two BREFCLKs must be created one for the top of the chip and one for the bottom These dedicated clocks use the same clock inputs for all packages Top P GCLK4S P GCLK6P BREF
169. ration access port ICAP The solution uses Virtex II Pro device with an IBM PowerPC 405 PPC405 processor to perform partial reconfiguration of the RocketIO multi gigabit transceivers MGTs pre emphasis and differential swing control attributes These attributes must be modified to optimize the www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Characterization Reports XILINX signal transmission prior to and after a system has been deployed in the field This solution is also ideal for characterization calibration and system testing The hardware and software elements of this solution can be easily integrated into any Virtex II Pro design already utilizing the PLB or OPB bus structures The reference design uses a Xilinx intellectual property interface IPIF connecting to either the PLB or OPB buses This design also provides for a terminal interface using a serial port connection allowing attribute settings to be changed through command line entries Design modules are also included to facilitate bit error rate tests BERT and pseudo random binary sequence PRBS diagnostics 669 405 PPE Reference System Using Virtex II Pro RocketlO Transceivers The PPC405 Packet Processing Engine PPE Reference System using Virtex II Pro RocketIO transceivers addresses the need in the digital communications market for highspeed data transfer Serial protocol
170. rectly decoded into parallel data Typographical The following typographical conventions are used in this document Courier font Meaning or Use Messages prompts and program files that the system displays Example speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design name Helvetica bold Commands that you select from a menu File Open Keyboard shortcuts Cirl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name design_name Braces A list of items from which you must choose one or more lowpwr on off RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 17 7 XILINX 18 Preface About This Guide Convention Verticalbar Meaning or Use Separates items in a list of choices Example lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 Name IOB 2 Name QOUT CLKIN
171. rts and Attributes uu ete mre 82 TX_CRC_USE RX CRG USE 4 paene e eoe hik ede es den adeeb ees 82 CRC FORMA Ds uo uyawan h dee uae tee ater tase ha sak 82 5 CRE END OFE PACKET smua titi ettet eset E a 85 RXCHECKINGCRC Z gett cara am teeta ch Perinat mL 85 TXFORCECRCERR TX CRC FORCE VALUE 54 045 85 RocketIO CRC Support Limitations 2 85 Fabric Interface Buffers 86 Overview Transmitter and Elastic Receiver Buffers 86 Transmitter 222222 04 c e YG Vedas bale Bales 86 Receiver Butter sxc soya yas ea e d qe aequas te 86 Portsand Attributes sess rege ERE DeR PA S d ERRARE SR 86 TXBUFPERR 2k Gk ee pakki he eS Re ed ET KG RE eS 86 TX BUFFER USE ooh dee eee ade Pda ER oe de Peed 86 RXBUFPFSTATUS REFERRE MEA Deke 87 RX BUFFER USB etes eb RAS waqu cea eee RO 87 Miscellaneous 87 Portsand Attributes cers sce p ERES RANA RA eERSA OE REST 87 RocketlO Transceiver User Guide www xilinx com 7 UG024 v2 2
172. s REFCLK I 1 High quality reference clock driving transmission reading TX FIFO and multiplied for parallel serial conversion and clock recovery frequency is accurate to 100 ppm This clock originates off the device is routed through fabric interconnect and is selected by REFCLKSEL REFCLK2 I 1 An alternative to REFCLK Can be selected by REFCLKSEL 22 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 List of Available Ports XILINX Table 1 5 GT_CUSTOM GT AURORA GT_FIBRE_CHAN GT ETHERNET 2 GT INFINIBAND and GT XAUI Primitive Ports Continued Port REFCLKSEL 1 0 I Port Size 1 Definition Selects the reference clock to use Low selects REFCLK if REF_CLK_V_SEL 0 selects BREFCLK if REF_CLK_V_SEL 1 High selects REFCLK2 if REF_CLK_V_SEL 0 selects BREFCLK2 if REF_CLK_V_SEL 1 See REF_CLK_V_SEL page 29 RXBUFSTATUS Receiver elastic buffer status Bit 1 indicates if an overflow underflow error has occurred when asserted High Bit 0 indicates that the buffer is at least half full when asserted High RXCHARISCOMMA 1 2 4 Similar to RXCHARISK except that the data is a comma RXCHARISK 1 2 4 If 8B 10B decoding is enabled it indicates that the received data is K character when asserted High Included in Byte mapping If 8B 10B decoding is bypassed it remains as
173. s 74 T Timing Parameters 123 Total Jitter DJ RJ 103 Transmitter and Elastic Receiver Buffers 86 144 www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 XILINX Transmitter Buffer FIFO 86 U User Guide conventions online references 18 port and attribute names 17 typographical 17 V Vitesse Disparity Example 62 Voltage Regulation 105 RocketIOTM Transceiver User Guide www xilinx com 145 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX 146 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003
174. s can be controlled by complex logic but are more simply handled microprocessor in this case the IBM PowerPC 405 405 processors embedded in the Virtex II Pro FPGA This reference system is an example of a high speed serial link packet processing engine implemented in Virtex II Pro FPGAs The Embedded Development Kit EDK is used exclusively in the design and implementation of both hardware and software in this reference system This reference design has been verified on the Memec Design Virtex II Pro P4 Development Board Instructions are included to allow the reader to reproduce the design on this board XAPP670 Minimizing Receiver Elastic Buffer Delay in the Virtex Il Pro RocketlO Transceiver This application note describes a design that reduces latency through the receive elastic buffer of the Virtex II Pro RocketIO transceiver This note is only applicable for designs that do not use the clock correction or channel bonding features of the RocketIO transceiver These operations can still be done in the fabric if needed Characterization Reports Characterization Reports and SPICE models can be accessed from the Xilinx SPICE Suite http www xilinx com xlnx xil prodcat product jsp title spice models Online registration required Follow the instructions on the web page to register Virtex Il Pro RocketlO Multi Gigabit Transceiver Characterization Summary Virtex II Pro devices contain up to twenty four
175. s that are synchronous to them The following table gives a brief description of all of these clocks For an in depth discussion of clocking the RocketIO core refer to Chapter 2 Digital Design Considerations Table 1 RocketlO Clock Descriptions CLOCK SIGNAL DESCRIPTION REFCLK Main reference clock for RocketIO transceiver TXUSRCLK Clock used for writing the TX buffer Frequency locked to REFCLK TXUSRCLK2 Clocks transmission data and status and reconfiguration data between the transceiver and the FPGA core Relationship between TXUSRCLK2 and TXUSRCLK depends on width of transmission data path RXUSRCLK Clock used for reading the RX elastic buffer Clocks CHBONDI and CHBONO into and out of the transceiver Typically the same as TXUSRCLK RXUSRCLK2 Clocks receiver data and status between the transceiver and the FPGA core Typically the same as TXUSRCLK2 Relationship between RXUSRCLK2 and RXUSRCLK depends on width of receiver data path RocketlO Transceiver User Guide www xilinx com 121 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Appendix RocketlO Transceiver Timing Model PACKAGE PINS MULTI GIGABIT TRANSCEIVER CORE FPGA FABRIC POWERDOWN VTRX Termination Supply RX gt RXRECCLK m RXPOLARITY RXREALIGN gt RXCOMMADET m ENPCOMMAALIGN ENMCOMMAALIGN RXCHECKINGCRC RXCRCERR RXDATA
176. sent to another transceiver without being sent to its own receiver logic During normal operation LOOPBACK should be set to 00 Internal Parallel Mode allows testing the transmit and Internal Parallel receive interface logic PCS without having to go into the Mode PMA section of the transceiver or to another transceiver See Figure 2 28 01 Internal Serial Mode is used to check that the entire transceiver is working properly including testing 8 10 encoding decoding This emulates what another transceiver would receive as data from this specific transceiver design Since the TXP TXN pins are still being driven during this loopback mode PCB traces on these pins should be Internal Serial terminated to remove reflections otherwise loopback bit Mode errors could result Termination can be accomplished by any of a variety of methods Two examples Connect SMA terminators on the TXP TXN SMA connectors if applicable or simply use 500 resistors on the transmitter backplane pins Connect the unterminated TXP TXN to the RXP RXN of another instantiated transceiver allowing its receiver inputs to terminate the transmitter outputs 10 TXDATA TX PCS TX SERIALIZER TXP TXN PARALLEL LOOPBACK 01 SERIAL LOOPBACK 10 RXDATA RX PCS RX DESERIALIZER RXP RXN UG024_25_110503 Figure 2 28 Serial Parallel Loopback Logic RocketIOTM Transceiver User Guide www xilinx
177. ses TXCHARDISPVAL becomes bits 8 18 28 and 38 of the transmit data See Figure 2 13 TXCHARISK TXCHARISK is a byte mapped control port that is used only when the 8B 10B encoder is implemented This port controls whether the byte of TXDATA is to be encoded as a control K character when asserted High or as a data character when de asserted When 8B 10B encoding is bypassed this port is undefined TXRUNDISP TXRUNDISP is a status port that is byte mapped to TXDATA This port indicates the running disparity after the byte of TXDATA is encoded When High the disparity is positive When Low the disparity is negative TXKERR TXKERR is a status port that is byte mapped to TXDATA This port is defined only if 8B 10B encoding is enabled If a bit is asserted High it means that TXDATA and TXCHARISK have combined to create an invalid control K character The transmission reception and decode of this invalid character will create unexpected RXDATA results in the RocketIO receiver or in other transceivers RXCHARISK RXRUNDISP RXCHARISK and RXRUNDISP are dual purpose ports for the receiver depending whether 8B 10B decoding is enabled Table 2 10 shows this dual functionality When decoding is enabled the ports function as byte mapped status ports for the received data RocketlO Transceiver User Guide www xilinx com 61 06024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations In
178. sparity Example 62 Transmitting Vitesse Channel Bonding Sequence 62 Receiving Vitesse Channel Bonding Sequence 63 8B 10B Bypass Serial Output erros casas nn 63 8B 10B Serial Output Format 2 64 HDL Code Examples Transceiver Bypassing of 8B 10B Encoding 64 SERDES Alignment L2 cp Leda rr RO ERU hho Re 65 OVervIew ba aue padecer Seca Dd act d e qas 65 Sele ard ce etm cei tas fe t gua un t 65 Desetializer 4 Lipa eee Me a UE a oye 65 Ports and Attributes toe ete ep eet er ed e e ER eae ku 65 ALIGN COMMA 65 ENPCOMMAALIGN ENMCOMMAALIGN yy su uy i e hh han 66 PCOMMA_DETECT MCOMMA DETECT Z uou ue a eru SWE SR 68 COMMA_10B_MASK PCOMMA_10B_VALUE VALUE sewe ienser tas CR e cq i ex Ra cce 68 DEC PCOMMA DETECT DEC DETECT DEC VALID COMMA ONLY 68 2 dre ta cte oot deside es e ee e qtue e n Genie dro e Cate ae UR u 68 RXCHARISCOMMA 4 0 69 55 I eed oq a oue bte ee 69 C
179. sters The PLL is unaffected TXRESET Synchronous transmit system reset recenters the transmission FIFO and resets the 8B 10B encoder and other transmission registers The PLL is unaffected POWERDOWN Shuts down the transceiver both RX and TX sides In POWERDOWN mode transmit output pins TXP TXN are undriven but biased by the state of transmit termination supply VTTX If VTTX is unpowered TXP TXN float to a high impedance state Receive input pins RXP RXN respond similarly to the state of receive termination supply VTRX Table 2 9 Power Control Descriptions POWERDOWN Transceiver Status 0 Transceiver in operation 1 Transceiver temporarily powered down Notes 1 Unused transceivers are automatically configured as powered down by the implementation tools RocketlO Transceiver User Guide www xilinx com 55 UG024 v2 2 November 7 2003 1 800 255 7778 7 XILINX Chapter 2 Digital Design Considerations VHDL Template Module gt_reset 56 Description VHDL submodule reset for GT Device Virtex II Pro Family LIBRARY IEEE USE IEEE std logic 1164 all use IEEE STD LOGIC ARITH ALL use IEEE Numeric STD all use IEEE STD LOGIC UNSIGNED ALL pragma translate off library UNISIM use UNISIM VCOMPONENTS ALL pragma translate on entity gt reset is port USRCLK2 M in std logic LOCK in std logic RE
180. successfully aligned CHAN BOND ONE SHOT As with ENCHANSYNC many applications will require that the channels be aligned only once CHAN BOND ONE SHOT TRUE allows the Master to initiate a channel bonding only once This remains true even if more channel bonding sequences are received The channels may be aligned again if RXRESET is asserted and then deasserted and ENCHANSYNC is deasserted and then reasserted CHAN BOND ONE SHOT may be set to FALSE when very few channel bonding sequences appear in the data stream For Slave instantiations this attribute should always be set to FALSE See Table 2 19 When the channel bonding sequence appears frequently in the data stream however it is recommended that this attribute be set to TRUE in order to prevent the RX buffer from over or underflowing www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Channel Bonding Channel Alignment XILINX CHAN BOND SEQ CHAN BOND SEQ LEN CHAN BOND SEQ 2 USE The channel bonding sequence CBS is similar in format to the clock correction sequence The CBS is set to the appropriate sequence for the primitives supporting channel bonding GT CUSTOM is the only primitive allowing modification to the sequence These sequences are comprised of one or two sequences of length up to 4 bytes each as set by CHAN BOND SEQ LEN and CHAN BOND SEQ 2 USE These CBSes should be unique from other delimiters in
181. tIO Transceiver Block Diagram 122 Figure A 2 RocketIO Transceiver Timing Relative to Clock Edge 127 Appendix B 8B 10B Valid Characters Appendix C Related Online Documents 12 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Schedule of Tables Chapter 1 RocketlO Transceiver Overview Table 1 1 Number of RocketIO Cores per Device Type 19 Table 1 2 Communications Standards Supported by RocketIO Transceiver 19 Table 1 3 Serial Baud Rates and the SERDES 10B Attribute 20 Table 1 4 Supported RocketIO Transceiver 21 Table 1 5 CUSTOMO GT AURORA GT FIBRE CHAN O GT ETHERNET O GT INFINIBAND and GT XAUI Primitive Ports 22 Table 1 6 RocketIO Transceiver Attributes 26 Table 1 7 Default Attribute Values GT AURORA GT CUSTOM GT ETHERNET 31 Table 1 8 Default Attribute Values GT FIBRE CHAN GT INFINIBAND and GT XAUJ uyu eect tec oO a nukata 33 Table 1 9 Control Status Bus Association to Data Bus Byte Paths 35 Chapter 2 Digital Design Considerations Table 2 1 Clock Ports cce sakes Lees data dee 37 Table 2 2 Reference Clock 38 Ta
182. te clock 50 2 byte clock 43 32 bit alignment design 91 4 byte clock 47 VHDL 1 byte clock 48 2 byte clock 41 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 www xilinx com 1 800 255 7778 143 XILINX 32 bit alignment design 94 4 byte clock 45 High Speed Serial Trace Design 109 HSPICE 115 Implementation Tools 115 J Jitter and BREFCLK 38 and use of DCM with REFCLK 37 deterministic and random defined 103 parameters 103 104 PCB trace length mismatch 109 K K Characters valid table 137 L Latency Data Path 54 M MGT Package Pins 117 Miscellaneous Signals 87 Modifiable Primitives table 31 Multiplexed Clocking Scheme with DCM 53 without DCM 53 P Par 115 Passive Filtering 106 PCB Design Requirements 104 Ports amp Attributes by function 8 10 encoding decoding 59 buffers fabric interface 86 channel bonding 78 clock correction 71 CRC 82 SERDES alignment 65 synchronization logic 74 Ports defined CHBONDDONE 80 CHBONDI 80 CHBONDO 80 ENCHANSYNC 78 ENMCOMMAALIGN 66 ENPCOMMAALIGN 66 LOOPBACK 88 POWERDOWN 113 RXBUFSTATUS 87 RXCHARISCOMMA 69 RXCHARISK 61 RXCHECKINGCRC 85 RXCLKCORCNT 74 80 RXCOMMADET 69 RXCRCERR 85 RXDISPERR 62 RXLOSSOFSYNC 75 80 RXNOTINTABLE 62 RXPOLARITY 88 RXREALIGN 68 RXRECCLK 54 RXRUNDISP 61 TXBUFERR 86 TXBYPASS8B10B 59 TXCHARDISPMODE 60 TXCHARDISPVAL 60 TXCHARISK 61 TXFORCECRCERR 85 TXINHIBIT 88 TXKERR 61 TXP
183. te sent over a separate channel transceiver See Figure 2 22 In Transmitters Full word SSSS sent over four channels one byte per channel Channel lane 0 Channel lane 1 Plots Channel 2 ER Channel V In Receivers Rea sa 5 RXUSRCLK RXUSRCLK _ __ _ Remis _ _ _ hamis Before channel bonding After channel bonding DS083 2_16_010202 Figure 2 22 Channel Bonding Alignment The top half of the figure shows the transmission of words split across four transceivers channels or lanes RRRR SSSS and TTTT represent words sent over the four channels The bottom left portion of the figure shows the initial situation in the FPGA s receivers at the other end of the four channels Due to variations in transmission delay especially if www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Channel Bonding Channel Alignment XILINX the channels are routed through repeaters the FPGA core might not correctly assemble the bytes into complete words The bottom left illustration shows the incorrect assembly of data words PQPP QRQQ RSRR etc To support correction of this misalignment the data stream includes special byte sequences that define corresponding points in the several channels In the bottom
184. that controls frequency of repetition of clock correction operations This attribute specifies the minimum number of cycles without clock correction that must occur between successive clock corrections For example if this attribute is 3 then at least three RXUSRCLK cycles without clock correction must occur before another clock correction sequence can occur If this attribute is 0 no limit is placed on how frequently clock correction can occur Example Elastic buffer is 2576 full clock correction is needed and one sequence is repeated per clock correction IDLE is the defined clock correction sequence Data stream written into elastic buffer DO IDLE IDLE IDLE D1 D2 RocketIOTM Transceiver User Guide www xilinx com 73 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 2 Digital Design Considerations Data stream read out of elastic buffer CLK COR REPEAT WAIT 0 DO IDLE IDLE IDLE IDLE IDLE IDLE D1 D2 Data stream read out of elastic buffer CLK COR REPEAT WAIT 1 DO IDLE IDLE IDLE IDLE IDLE D1 D2 The percent that the buffer is full together with the value of CLK_COR_REPEAT_WAIT determines how many times the clock correction sequence is repeated during each clock correction Synchronization Logic Overview For some applications it is beneficial to know if incoming data is valid or not and if the MGT is sync
185. that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2003 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes RocketlIO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 RocketIOTM Transceiver User Guide UG024 v2 2 November 7 2003 The following table shows the revision history for this document
186. the 8B 10B decoding configuration RXCHARISK asserted High indicates the received byte of data is a control K character Otherwise the received byte of data is a data character See Appendix B 8B 10B Valid Characters The RXRUNDISP port indicates the disparity of the received byte is either negative or positive RXRUNDISP asserted High indicates positive disparity This is used in cases like the Vitesse Disparity Example below When CLK_COR_INSERT_IDLE_FLAG TRUE RXRUNDISP is asserted to flag the presence of an inserted clock correction sequence In the bypassed configuration RXCHARISK and RXRUNDISP are additional data bits for the 10 20 or 40 bit buses similar to the configuration on the transmit side RXCHARISK 0 3 relates to bits 9 19 29 and 39 while RXRUNDISP pertains to bits 8 18 28 and 38 of the data bus See Figure 2 14 RXDISPERR RXDISPERR is a status port for the receiver that is byte mapped to RXDATA When a bit in RXDISPERR is asserted High it means that a disparity error has occurred in the received data This usually indicates data corruption bit errors or transmission of an invalid control character It can also occur in cases where normal disparity is not required such as in the Vitesse Disparity Example RXNOTINTABLE RXNOTINTABLE is a status port for the receiver that is byte mapped to RXDATA When it is asserted High it means that the received data is not in the 8B 10B tables This port is
187. the data stream including Clock Correction Sequence IDLE Start of Frame and End of Frame As with clock correction there are multiple sequences that can be defined GT CUSTOM only The primary CBS is defined by BOND SEQ 1 where a number from 1 to 4 If a second CBS is required CHAN BOND SEQ 2 USE must be set to TRUE and CHAN BOND SEQ 2 used to define the second CBS otherwise CHAN BOND SEQ 2 USE should be left at its default value FALSE See Receiving Vitesse Channel Bonding Sequence page 63 for the bit breakdown of the sequence definition Finally CHAN BOND SEQ LEN defines the CBS length as 1 to 4 bytes When set to anything other than 4 only those sequences are defined For example if CHAN BOND SEQ LEN is set to 2 only BOND SEQ 1 1 and CHAN BOND SEQ 1 2 need to be defined CHAN BOND WAIT CHAN BOND OFFSET CHAN BOND LIMIT These three attributes define how the Master performs channel alignment of the RX buffer The typical values of these attributes are CHAN BOND WAIT 8 CHAN BOND WAIT roughly defines the maximum number of bytes by which the Slave can lag the Master Due to internal pipelining the equation should be CHAN BOND WAIT 3 5 bytes of bytes Slave may lag Master For example if CHAN BOND WAIT 8 the Slave may lag the Master by 4 5 bytes While this type of lag is equivalent to approximately 14 ns at3 125 Gbps it is recommended that channel links
188. the different clocking schemes several things must change including the clock frequency for USRCLK and USRCLK2 discussed in Digital Clock Manager DCM Examples in Chapter 2 The data and control ports for GT CUSTOM must also reflect this change in data width by concatenating zeros onto inputs and wires for outputs for Verilog designs and by setting outputs to open and concatenating zeros on unused input bits for VHDL designs HDL Code Examples Please use the Architecture Wizard to create instantiation templates This wizard creates code and instantiation templates that define the attributes for a specific application RocketlO Transceiver User Guide www xilinx com 21 UG024 v2 2 November 7 2003 1 800 255 7778 X XILINX List of Available Ports The RocketIO transceiver primitives contain 50 ports with the exception of the 46 port GT_ETHERNET and GT_FIBRE_CHAN primitives The differential serial data ports RXN RXP TXN and TXP are connected directly to external pads the remaining 46 ports are all accessible from the FPGA logic 42 ports for GT_ETHERNET and GT_FIBRE_CHAN Chapter 1 RocketlO Transceiver Overview Table 1 5 contains the port descriptions of all primitives Table 1 5 GT_CUSTOM GT AURORA GT_FIBRE_CHAN GT ETHERNET GT INFINIBAND and GT XAUI Primitive Ports Port yo Definition Size BREFCLK I 1 This high quality reference clock uses de
189. the first bit received Bit a of the 10 bit encoded data see Figure 2 14 page 63 RXCHECKINGCRC CRC status for the receiver Asserts High to indicate that the receiver has recognized the end of a data packet Only meaningful if RX CRC USE TRUE RXCLKCORCNT Status that denotes occurrence of clock correction or channel bonding This status is synchronized on the incoming RXDATA See RXCLKCORCNT page 74 RXCOMMADET Signals that a comma has been detected in the data stream To assure signal is reliably brought out to the fabric for different data paths this signal may remain High for more than one USRCLK USRCLK2 cycle RXCRCERR Indicates if the CRC code is incorrect when asserted High Only meaningful if _ CRC USE TRUE RXDATA O 8 16 32 Up to four bytes of decoded 8B 10B encoding or encoded 8B 10B bypassed receive data RXDISPERR 9 1 2 4 If8B 10B encoding is enabled it indicates whether disparity error has occurred on the serial line Included in Byte mapping scheme RXLOSSOFSYNC Status related to byte stream synchronization RX_LOSS_OF_SYNC_FSM If RX_LOSS_OF_SYNC_FSM TRUE RXLOSSOFSYNC indicates the state of the FSM Bit 1 Loss of syne High Bit 0 Resync state High If RX_LOSS_OF_SYNC_FSM FALSE RXLOSSOFSYNC indicates Bit 1 Received data invalid High Bit 0 Channel bonding sequence recognized High RocketlO
190. ts mapped to number of bytes of data path width 8B 10B encoding bypassed disabled 1 2 or 4 bits mapped to number of bytes 1 of data path width Function 8B 10B Enabled Function 8B 10B Bypassed TXCHARDISPMODE oo Maintain running disparity normally Part of 10 bit encoded byte TXCHARDISPVAL see Figure 2 13 Invert the normally generated running TXCHARDISPMODE 0 01 disparity before encoding this byte Cor 1 2 3 Set negative running disparity before TXCHARDISPVAL O0 encoding this byte or 1 2 3 Set positive running disparity before TXDATA 7 0 encoding this byte or 15 8 23 16 31 24 RXCHARISK Received byte is a K character Part of 10 bit encoded byte Fi 2 14 RXRUNDISP Pmaeee dats running dsparys RXCHARISKIO or 1 2 3 RXRUNDISP 0 1 Indicates running disparity is or 1 DI POSITIVE RXDATA 7 0 15 8 23 16 31 24 RXDISPERR Disparity error occurred on current Unused byte TXCHARISK Transmitted byte is a K character Unused RXCHARISCOMMA Received byte is a comma Unused TXCHARDISPVAL TXCHARDISPMODE TXCHARDISPVAL and TXCHARDISPMODE are dual purpose ports for the transmitter depending upon whether 8B 10B encoding is enabled Table 2 10 shows this dual functionality When encoding is enabled these ports function as byte mapped control ports controlling the running disparity of the tra
191. uity increase the individual trace width where trace separation occurs Figure 3 13 and Figure 3 14 show examples of PCB geometries that result in 100O differential impedance W 6 29 mil 0 160 mm Wo 6 29 mil 0 160 mm S 10 mil 0 254 mm H 5 0 mil 0 127 mm 201 55 30 Zoo 55 30 ZopIFF 1000 e Wyre S F Wo gt Reference Plane UG024_22_042903 Figure 3 13 Microstrip Edge Coupled Differential Pair Reference Plane 110 Dielectric Reference Plane W 3 0 mil 0 076 Wo 3 0 mil 0 076 mm S 6 85 mil 0 174 mm 10 0 mil 0 254 mm 10 0 mil 0 254 mm 201 64 80 Zo2 64 80 ZopIFF 1000 UG024_22a_042903 Figure 3 14 Stripline Edge Coupled Differential Pair www xilinx com 1 800 255 7778 RocketlO Transceiver User Guide 06024 v2 2 November 7 2003 PCB Design Requirements XILINX AC and DC Coupling AC coupling use of DC blocking capacitors in the signal path should be used in cases where transceiver differential voltages are compatible but common mode voltages are not Some designs require AC coupling to accommodate hot plug in and or differing power supply voltages at different transceivers This is illustrated in Figure 3 15 Capacitors of value 0 01 uF in a 0402 EIA package are suitable for AC coupling at 3 125 Gbps when 8B 10B encoding is used Different data rates and different encoding schemes may require a different v
192. ver will consume some power even if it is not engaged in transmitting or receiving Therefore when a transceiver is not to be used for an extended period of time the POWERDOWN port should be asserted High to reduce overall power consumption by the Virtex II Pro FPGA Deasserting the POWERDOWN port restores the transceiver to normal functional status RocketlO Transceiver User Guide www xilinx com 113 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations 114 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 87 XILINX Chapter 4 Simulation and Implementation Simulation Models SmartModels SmartModels are encrypted versions of the actual HDL code These models allow the user to simulate the actual functionality of the design without having access to the code itself A simulator with SmartModel capability is required to use SmartModels The models must be extracted before they can be used For information on how to extract the SmartModels under ISE 5 1i see Solution Record 15501 HSPICE HSPICE is an analog design model that allows simulation of the RX and TX high speed transceiver To obtain these HSPICE models go to the SPICE Suite Access web page at http support xilinx com support software spice spice request htm Implementation Tools Par For place and route the transceiver has one restriction This is required when
193. vice other than the LT1963 is used Section AC and DC Coupling in Chapter 3 Added footnote to Table 3 6 clarifying voltage compliance Figure 3 17 and section Epson EG 2121CA 2 5V LVPECL Outputs in Chapter 3 Added material specifying the optional use of an LVPECL buffer as an alternative to the LVDS buffer previously specified Table 4 2 Added pinouts for FG676 package XC2VP20 and XC2VP30 Table A 5 Added BREFCLK parameters and TpREFPWL Section Application Notes in Appendix C Included new Xilinx Application Notes XAPP648 XAPP669 and XAPP670 Various non technical edits and corrections RocketlIO Transceiver User Guide www xilinx com UG024 v2 2 November 7 2003 1 800 255 7778 Table of Contents Schedule of 11 Schedule of Tables 13 Preface About This Guide RocketIO Features 15 G ide Contents Cpu BY 15 For More 16 Additional Resources 16 Conventions ort Sh use qua 17 Port and Attribute 17 Typographical
194. w xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Pre emphasis Techniques XILINX mber 5Gb s Diff TX 1 800 25C VSEL 11 RDIV 1 SPEED I TESTEN 1 E MN 00 hannel 2 Channel 1 N cE le d DALAS EET OA i D 1 I I TE 00024 17 020802 Figure 3 2 Alternating K28 5 with Pre Emphasis 3 1256b s Diff TX Jv SC T 11 RDIV 1 SPEED 1 TESTEN 1 EMN x pire FT Channel 2 Channel 1 200mV div wn lo sias ia E High LogicLow 090024 18 020802 Figure 3 3 28 5 with Pre Emphasis RocketlO Transceiver User Guide www xilinx com 101 UG024 v2 2 November 7 2003 1 800 255 7778 XILINX Chapter 3 Analog Design Considerations ug024_36_031803 Figure 3 4 Eye Diagram 10 Pre Emphasis 20 4 Worst Case Conditions ug024_37_031803 Figure 3 5 Eye Diagram 33 Pre Emphasis 20 FR4 Worst Case Conditions 102 www xilinx com RocketlO Transceiver User Guide 1 800 255 7778 UG024 v2 2 November 7 2003 Differential Receiver XILINX Differential Receiver The differential receiver accepts the Vp and VN signals carrying out the difference calculation Vp Vy electronically All input data must be differential and nominally biased to a common mode voltage of 0 5 V 2 5 V or AC coupled Internal terminations prov
195. w xilinx com RocketlO Transceiver User Guide 1 800 255 7778 06024 v2 2 November 7 2003 Other Important Design Notes XILINX considered to sync when a comma is seen rxdata as indicated by rxchariscomma3 or 1 after the counter wait_to_sync has reached 0 indicating that commas seen by the comma detection circuit have had time to propagate to aligned data after initialization of the elastic buffer PROCESS usrclk2 BEGIN IF usrclk2 EVENT AND usrclk2 1 THEN IF rxreset OR rxrealign 1 THEN sync hold 0 ELSE IF wait to sync 0000 THEN IF rxchariscomma3 OR rxchariscommal 1 THEN sync hold lt 1 END IF END IF END IF END IF END PROCESS This process generates aligned data with commas aligned in 31 24 assuming that incoming commas are aligned to 31 24 or 15 8 Here you could add code to use ENPCOMMAALIGN and ENMCOMMAALIGN to enable a move back into the byte sync 0 state PROCESS usrclk2 rxreset BEGIN IF rxreset 1 THEN rxdata reg 0000000000000000 rxdata hold 00000000000000000000000000000000 rxisk reg 00 rxisk hold 0000 byte sync lt 0 ELSIF usrclk2 EVENT AND usrclk2 1 THEN rxdata reg 15 DOWNTO 0 rxdata 15 DOWNTO 0 rxisk reg 1 DOWNTO 0 lt rxisk 1 DOWNTO 0 IF rxchariscomma3 1 THEN rxdata hol
196. xilinx com 25 1 800 255 7778 XILINX Chapter 1 RocketlO Transceiver Overview Primitive Attributes The primitives also contain attributes set by default to specific values controlling each specific primitive s protocol parameters Included are channel bonding settings for primitives supporting channel bonding clock correction sequences and CRC Table 1 6 shows a brief description of each attribute Table 1 7 and Table 1 8 have the default values of each primitive Table 1 6 RocketlO Transceiver Attributes Attribute Description ALIGN COMMA MSB TRUE FALSE controls the alignment of detected commas within the transceiver s 2 byte wide data path FALSE Align commas within a 10 bit alignment range As a result the comma is aligned to either RXDATA 15 8 byte or RXDATA 7 0 byte in the transceivers internal data path TRUE Aligns comma with 20 bit alignment range As a result aligns on the RXDATA 15 8 byte Notes 1 If protocols like Gigabit Ethernet are oriented in byte pairs with commas always in even first byte formation this can be set to TRUE Otherwise it should be set to FALSE 2 For 32 bit data path primitives see 32 bit Alignment Design page 91 3 This attribute is only modifiable in the GT CUSTOM primitive CHAN BOND LIMIT Integer 1 31 that defines maximum number of bytes a slave receiver can read following a channel bonding sequence and still successfully align to that sequence CHAN B
197. xilinx com 71 1 800 255 7778 XILINX 72 Chapter 2 Digital Design Considerations Clock correction may be used with other encoding protocols but they must have a 10 bit alignment scheme This is required so the comma detection logic can properly align the data in the elastic buffer allowing the clock correction logic to properly read out data to the FPGA fabric RX_BUFFER_USE The RX_BUFFER_USE attribute controls if the elastic buffer is bypassed or not Most applications use this buffer for clock correction and channel bonding See Channel Bonding Channel Alignment page 76 It is recommended that this attribute always be set to TRUE since this buffer allows a way to cross the clock domains of and the fabric 2 CLK COR SEQ To accommodate many different protocols the MGT features programmability that allows it to detect a 1 2 or 4 byte clock correction sequence CCS such as may be used in Gigabit Ethernet 2 byte or Fibre Channel 4 byte The attributes CLK COR SEQ and CLK COR SEQ LEN below define the CCS that the PCS recognizes Both SEO 1 and SEQ 2 can be used at the same time if multiple CCSes are required As shown in Table 2 15 the example CCS has two possible modes one for when 8B 10B encoding is used the other for when 8B 10B encoding is bypassed The most significant bit of the CCS determines whether it is applicable to an 8 bit en
198. y termination voltage my be used The logical choice is 2 5 V as this voltage is already available on the board for the AVCCAUXTX and AVCCAUXRX supplies The LT1963 circuit s output capacitors 330 uF and 1 uF may be placed anywhere on the board preferably close to the output of the LT1963 device Refer to the manufacturer s Web page at http www linear tech com for further information about this device Passive Filtering To achieve the necessary isolation from high frequency power supply noise passive filter networks are required on the power supply pins The topology of these capacitor and ferrite bead circuits is given in Figure 3 7 2 5V BLM18AG102SN1 r AVCCAUXRX 0 22uF BLM18AG102SN1 7 AVCCAUXTX 0 22uF VTT BLM18AG102SN1 NMA VTTX 0 22uF VTR BLM18AG102SN1 VTRX 0 22uF GNDA UG024_20_022002 Figure 3 7 Power Filtering Network for One Transceiver Each transceiver power pin requires one capacitor and one ferrite bead The capacitors must be of value 0 22 pF in an 0603 EIA SMT package of X7R dielectric material at 10 tolerance rated to at least 5 V These capacitors must be placed within 1 cm of the pins they are connected to The ferrite bead is the Murata BLM18AG102SN1 These components may not be shared under any circumstances Figure 3 8 and Figure 3 9 show an example layout of the power filtering network for four transceivers The device

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