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Xilinx Timing Constraints User Guide

1. eese 66 Clock Signal CLOCK SIGNAL XCF Syntax i e nen 66 Clock Signal CLOCK SIGNAL XCF Syntax Example oooocoocooccooccoomo 66 MultizCycle Patbii incubo E bte dli dieta sura 66 Multi Cycle Path XCF Syntax 6 cee hn 67 Multi Cycle Path XCF Syntax Example sese eee 67 Maximum Delay MAXDELAY 0 06606 es 67 Maximum Delay MAXDELAY VHDL Syntax 0 eee ee 67 Maximum Delay MAXDELAY VHDL Syntax Example eee 67 Maximum Delay MAXDELAY Verilog Syntax csse 68 Maximum Delay MAXDELAY Verilog Syntax Example eese 68 Maximum Skew MAXSKEW 0 0 cece IH 68 Maximum Skew MAXSKEW VHDL Syntax cesses 68 Maximum Skew MAXSKEW VHDL Syntax Example lese 68 Maximum Skew MAXSKEW Verilog Syntax esee 69 Maximum Skew MAXSKEW Verilog Syntax Example 0 00000 eee 69 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 Offset OFFSET esses sess sss en 69 Offset OFFSET XCF Syntax iex pa t gobs E e EE EE RD era ke da 69 Offset OFFSET XCF Syntax Example 6 6 ce ne 70 Period PERIOD susi dia 70 Period PERIOD VHDL Syntax csse nen 70 Period PERIOD VHDL Syntax Example eee 70 Period PERIOD Verilog Syntax esse e 70 Period PERIOD Verilog Syntax Example lese 71 TIMESPEC PERIOD XCF Syntax esee nn 71 NET PERIOD XCF Staind ton A d C CFA q E Ya E eRe p ah 71 Sy
2. The Multi Cycle Path constraint specifies a timing constraint between two groups For more information see Chapter 3 Timing Constraint Principles 66 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX XST Timing Constraints Multi Cycle Path XCF Syntax TIMESPEC TSname FROM group1 TO group2 value where e TSname must always begin with TS Any alphanumeric character or underscore may follow e group is the source timing group e group2 is the destination timing group e value is ns by default Other possible values are MHz or another timing specification such as TS_C2S 2 or TS_C2S 2 XST supports the FROM TO constraint with the following limitations e FROM THRU TO is not supported e Linked timing specification is not supported e Pattern matching for predefined groups is not supported such as TIMESPEC TS 1 FROM FFS machine TO FFS 2 ns Multi Cycle Path XCF Syntax Example TIMESPEC TS MY PathA FROM my src grp TO my dst grp 23 5 ns TIMESPEC TS DQS_UNUSED FROM FFS TO control unused dqs TIG Maximum Delay MAXDELAY Note Maximum Delay MAXDELAY applies to the nets in FPGA devices only The Maximum Delay MAXDELAY attribute defines the maximum allowable delay on a net For more information see the Constraints Guide Maximum Delay MAXDELAY VHDL Syntax attribute maxdelay of signal name
3. XST Timing Constraints Timing Specifications TIMESPEC XCF Syntax Examples Defining a Maximum Allowable Delay Timing Specifications TIMESPEC XCF Syntax Example Defining a Clock Period XCF Syntax Example Specifying Derived Clocks XCF Syntax Example Ignoring Paths XCF Syntax Example Defining a Maximum Allowable Delay Timing Specifications TIMESPEC XCF Syntax Example TIMESPEC TSidentifier FROM source_group TO dest_group allowable_delay units Defining a Clock Period XCF Syntax Example Defining a clock period allows more complex derivative relationships to be defined as well as a simple clock period TIMESPEC TSidentifier PERIOD TNM_reference value units HIGH LOW high_or_low_time hi_lo_units INPUT_JITTER value where identifier is a reference identifier with a unique name TNM_reference is the identifier name attached to a clock net or a net in the clock path using a TNM constraint value is the required clock period units is an optional field to indicate the units for the allowable delay The default units are nanoseconds ns but the timing number can be followed by micro ms ps ns GHz MHz or kHz to indicate the intended units HIGH or LOW can be optionally specified to indicate whether the first pulse is to be High or Low high_or_low_time is the optional High or Low time depending on the preceding keyword If an actual time is s
4. attribute syn tcol of Dpram10240x8 component is ClkA gt DoutA 7 0 6 0 attribute syn tsu2 of Dpram10240x8 component is EnB AddrB gt C1kB 3 0 attribute syn tco2 of Dpram10240x8 component is C1kB gt DoutB 7 0 13 0 Other code E syn_tcon sdc File Syntax define_attribute v blackboxModule syn_tcon clock gt bundle value where v indicates that the directive is attached to the view blackboxModule is the symbol name of the black box nis a numerical suffix that lets you specify different clock to output timing delays for multiple signals bundles is an optional exclamation mark indicating that the clock is active on its falling negative edge clock is the name of the clock signal bundle is a collection of buses and scalar signals The objects of a bundle must be separated by commas with no intervening spaces A valid bundle is A B C which lists three signals value is the clock to output delay value in ns 90 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in HDL syn_tcon sdc File Syntax Example define_attribute v RCV_CORE syn_tcol CLK gt R_DATA_OUT 63 0 20 define attribute v RCV_CORE syn tco2 CLK gt DATA _VALID 30 lt n gt syn_tsun The syn_tsun directive supplies information on timing setup delay required for input pins relative to the clock in a black box The s
5. e Time Group Example Two Predefined Group of FFS e Time Group Example Three Predefined Group on a Hierarchical Instance e Time Group Example Four Combining Time Groups e Time Group Example Five Removing Time Groups e Time Group Example Six Clock Edges Time Group Example One Predefined Group of RAMs Following is an example of a time group created with a search string and a predefined group of RAMs in a multicycle constraint e INST my core TNM RAMS my rams This time group my rams is the RAM components of the hierarchical block my core e TIMSPEC TSO1 FROM FFS TO my rams 14 24ns e NET clock enable TNM NET RAMS address fast rams This time group fast rams is the RAM components driven by net name of clock enable with an output net name of address e TIMSPEC TS01 FROM FFS TO fast rams 12 48ns OR e TIMESPEC TSO1 FROM FFS TO RAMS address 12 48ns The Destination time group is based upon RAM components with an output net name of address Time Group Example Two Predefined Group of FFS Following is an example of a time group created with a search string and a predefined group of FFS in a multi cycle constraint TIMESPEC TS01 FROM RAMS TO FFS macro A Qdata 14 25ns The Destination time group is based upon Flip Flop components with an output net named macro A Qdata Time Group Example Three Predefined Group on a Hierarchical Instance Following is a
6. synthesis syn black box black box tri pins PAD Here is an example with a list of multiple pins module bb1 D E tril tri2 tri3 Q synthesis syn black box black box tri pins tril tri2 tri3 For a bus specify the port name followed by all the bits on the bus module bb1 D bus1 E GIN GOUT Q synthesis syn_black_box black_box_tri_pins bus1 7 0 black_box_tri_pins VHDL Syntax attribute black_box_tri_pins of object objectType is portList where e object is a component declaration or architecture Data type is string e portList is a spaceless comma separated list of the tristate output port names black_box_tri_pins VHDL Syntax Example library ieee use ieee std logic 1164 all package my components is component BBDLHS port D in std logic E in std logic GIN in std logic GOUT in std logic PAD inout std logic Q out std logic end component attribute syn black box boolean attribute syn black box of BBDLHS component is true 82 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in HDL attribute black_box_tri_pins string attribute black_box_tri_pins of BBDLHS component is PAD end package my_components Multiple pins on the same component can be specified as a list attribute black box tri pins of bbl component is tri tri2 tri3 To apply this directive to a port that is a bus
7. About Timing Group Creation with TNM TNM_NET Attributes All design elements with same TNM TNM_NET attribute are considered a timing group A design element may be in multiple timing groups INM TNM_NET The TNM TNM_NET attributes can be applied to e Net Connectivity NET e nstance Module INST e Instance Pin PIN Note To ensure correct timing analysis Xilinx recommends that you place only one TNM TNM_NET on each element driver pin or macro driver pin Net Connectivity NET Identifying groups by net connectivity allows the grouping of elements by specifying a net or signal that eventually drives synchronous elements and pads This method is a good way to identify multi cycle path elements that are controlled by a clock enable and can be constrained as a FROM TO multi cycle constraint This method uses TNM_NET timing net or TNM timing name on a net of the design The timing name attribute is commonly used on HDL port declarations which are directly connected to pads www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Constraint System If a timing name attribute is placed on a net or signal the constraints parser traces the signal or net downstream to the synchronous elements A timing name is an attribute that can be used to identify the elements that make up a time group that can be then used in a timing constraint Those synchronous elements are then tagged with the same
8. Source IntA_3 FF Destination OutB_3 FF Requirement 2 000ns Data Path Delay 3 443ns Levels of Logic 0 Clock Path Skew 0 020ns Source Clock clk2x rising at 0 000ns Destination Clock clk2x falling at 2 000ns Clock Uncertainty 0 200ns CLKDV CLKFX Clock Domain Since the clocks produced by the DCM PLL DLL PMCD are related the timing tools take this relationship into consideration during analysis The CLKDV and CLKFX outputs can be used to make clock signals that are derivatives of the original input clock signal as shown in Table 3 1 Transformation of PERIOD Constraint Through DCM The clock is driven by two different outputs of the DCM DLL PLL PMCD component The timing analysis tool reports the active edges of the clock and the corresponding time for the data path between the synchronous elements Timing Constraints User Guide www xilinx com 117 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX The simple design of a CLKDV clock domain with the DIVIDE BY factor set to 2 is shown in Figure 6 9 CIKDV DCM output schematic This clock domain has twice the requirement as the original requirement but the phase shifting is the same as the phase shifting of the original requirement X11101 Figure 6 9 CIkDV DCM output schematic Timing Report Example Slack setup path 1 909ns requirement data path clock path skew uncertainty Source XorC_7 FF Destination Out
9. Timing Constraints User Guide www xilinx com 33 UG612 v 11 1 1 April 29 2009 34 Chapter 3 Timing Constraint Principles XILINX When you place a TNM constraint on a net use a qualifier to narrow the list of elements in the time group A qualified TNM is traced forward until it reaches the first synchronous element that matches the qualifier type The qualifier types are the predefined time groups If that type of synchronous element matches the qualifier the synchronous element is given that TNM attribute Whether or not there is a match the TNM is not traced through the synchronous element Predefined Time Groups The following keywords are predefined time groups FFS All SLICE and IOB edge triggered flip flops and shift registers PADS All I O pads DSPS All DSP48 in Virtex 4 devices All DSP48E in Virtex 5 devices RAMS All single port and dual port SLICE LUT RAMs and block Rams MULTS All synchronous and asynchronous multipliers in the following devices VirtexII Pro VirtexII ProX Virtex 4 Virtex 5 HSIOS All GT and GT10 in the following devices VirtexII Pro VirtexII ProX Virtex4 All GTP in Virtex 5 devices CPUS All PPC405 in the following devices VirtexII Pro VirtexII ProX Virtex 4 All PPC450 in Virtex 5 devices LATCHES All SLICE level sensitive latches BRAMS_PORTA Port A of all dual port block RAMs www xilinx com Timing Constraints User Gu
10. 3 Clock Uncertainty 0 180ns Dual Data Rate Example A dual data rate example of the OFFSET OUT constraint has the initial clock edge at zero ns and half the PERIOD constraint which correlates to the two edges of the clock The timing report displays the Clock Arrival time for each edge of the clock Since the timing analysis tools do not automatically adjust any of the clock phases during analysis the constraints must be manually adjusted for each clock edge The timing analysis tools offer two options to manage the falling edge Clock Arrival time The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold Option One The first option is to create two time groups one for rising edge synchronous elements and the second for the falling edge synchronous elements When you create an OFFSET OUT constraint for each time group the second OFFSET OUT constraint has a different requirement The falling edge OFFSET OUT constraint requirement equals the original requirement plus one half the PERIOD constraint If the original requirement is 3 ns witha PERIOD of 10 the falling edge OFFSET OUT constraint requirement is 8 ns This compensates for the Clock Arrival time associated with the falling edge synchronous elements Timing Constraints User Guide www xilinx com 133 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX 134 Option Two The second option is t
11. A DCM phase shifted clock CLK90 example of the OFFSET IN constraint has an initial clock edge at zero ns based upon the PERIOD constraint Since the clock is phase shifted by the DCM the timing report displays the Clock Arrival time as the phase shifted amount If the CLK90 output is used then the phase shifted amount is one quarter of the PERIOD In this example the PERIOD constraint has the initial clock arrival on the rising edge but the clock arrival value is at 2 5ns The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold in the example report below In Figure 6 14 Timing Diagram for Phase Shifted Clock in OFFSET IN Constraint the OFFSET requirement is three ns before the initial clock edge Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET IN 3 ns BEFORE clock 124 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX OFFSET IN Constraints clock_in 10 ns pos pom clk90 data X11106 Figure 6 14 Timing Diagram for Phase Shifted Clock in OFFSET IN Constraint Timing Report Example Slack 2 308ns requirement data path clock path clock arrival uncertainty Source reset PAD Destination my_oddrA_ODDR_inst FFO FF Destination Clock clock90_bufg rising at 2 500ns Requirement 3 000ns Data Path Delay 2 784ns Levels of Logic 1 Clock Path Del
12. OR e Click the SCOPE icon on the toolbar For each of the TCL timing constraint type there is an equivalent SCOPE spreadsheet interface For more information see the Synplify User s Guide SCOPE and Timing Constraints gt Scope Constraints Forward Annotation The synthesis tool generates vendor specific constraint files that can be forwarded and annotated with the place and route tools The constraint files are generated by default To disable this feature deselct the Project gt Implementation Option gt Implementation Results gt Write Vendor Constraint File option The constraint file generated for Xilinx place and route tools has an ncf file extension ncf The timing constraints described in the TCL and SCOPE sections are forward annotated to Xilinx in this file In addition to these constraints the synthesis tool forward annotates relationships between different clocks See the following sections for more information e I O Timing Constraints e Clock Groups e Relaxing Forward Annotated I O Constraints e Digital Clock Manager Delay Locked Loop I O Timing Constraints By default the synthesis tool forward annotates the define_input_delay and define_output_delay timing constraints to the Xilinx ncf file The syn_forward_io_constraints attribute controls forward annotation A value of 1 or true default enables forward annotation A value of 0 or false disables it Use this attribute at the t
13. SYSTEM JITTER 150ps 22500ps DCM Discrete Jitter 120ps DCM Phase Error Ops Clock Uncertainty 185ps Timing Constraints User Guide www xilinx com 137 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX Following is an example of a PERIOD constraint with the INPUT_JITTER keyword TIMESPEC TS Clk0 PERIOD clk0 4 ns HIGH 60 INPUT_JITTER 200 ps PRIORITY 1 Following is an example of the SYSTEM JITTER constraint SYSTEM JITTER 150 ps Clock jitter consists of both random and discrete jitter components Because the INPUT JITTER and SYSTEM JITTER are random jitter sources and typically follow a Gaussian distribution the combination of the two is added in a quadratic manner to represent the worst case combination Note Because the DCM Jitter is a discrete jitter value it is added directly to the clock uncertainty In the analysis of clock uncertainty all jitter components both random and discrete are specified as peak peak values Peak peak values represent the total range by which the arrival time of a clock signal varies in the presence of jitter In a worst case analysis only the delay variation that causes a decrease in timing slack is used For this reason only the peak jitter value or one half the peak to peak value is used for each setup and hold timing check The phase error component of clock uncertainty is a value representing the phase variat
14. define clock CLK1 period 10 0 clockgroup default clkgroup define clock CLK3 period 5 0 clockgroup default clkgroup uncertainty 0 2 name INT REF3 define clock virtual CLK2 period 20 0 clockgroup g2 define clock CLK4 period 20 000 clockgroup g3 rise 1 000 fall 11 000 ref rise 0 000 ref fall 10 000 define clock Pin Level Constraint Examples define clock i myInst1 Q period 10 000 clockgroup default rise 0 200 fall 5 200 name myff1 define clock i myInst2 Q period 12 000 clockgroup default rise 0 400 fall 5 400 name myff2 define clock delay The define_ clock delay command defines the delay between the clocks By default the synthesis tool automatically calculates clock delay based on the clock parameters you define with the de ine clock command However if you use de ine clock delay the specified delay value overrides any calculations made by the synthesis tool The results shown in the Clock Relationships section of the Timing Report are based on calculations made using this constraint define clock delay Syntax define clock delay rise fall clockName1 rise fall clockName2 delayValue where e rise fall specifies the clock edge e clockName specifies the clocks to constrain The clock must be already defined with define clock e delayValue specifies the delay in nanoseconds between the two clocks You can also specify a value false which defines the path as a false path
15. micro ms or if the High or Low time is an actual time measurement Ignoring Paths XCF Syntax Example Note This form is not supported for CPLD devices There are situations in which a path that exercises a certain net should be ignored because all paths through the net instance or instance pin are not important from a timing specification point of view TIMESPEC TSidentifier FROM source group TO dest group TIG where e identifier is an ASCII string made up of the characters A Z a z 0 9 and _ e source group and dest group are user defined or predefined groups The following statement says that the timing specification TS 35 calls for a maximum allowable delay of 50 ns between the groups here and there TIMESPEC TS 35 FROM here TO there 50 The following statement says that the timing specification TS 70 calls for a 25 ns clock period for clock a with the first pulse being High for a duration of 15 ns TIMESPEC TS 70 PERIOD clock a 25 high 15 Timing Name TNM Timing Name TNM is a basic grouping constraint Use TNM to identify the elements that make up a group which you can then use in a timing specification TNM tags specific predefined groups as members of a group to simplify the application of timing specifications to the group The RISING and FALLING keywords may also be used with TNMs For more information see Chapter 3 Timing Constraint Principles Timin
16. Clock Phase between DCM outputs shows CLK0 and CLK90 signals where the phase difference is 90 degrees FF_OF FF_90 DCM e gt clk20 ol gt clk20_90g X11098 Figure 6 6 Clock Phase between DCM outputs Another cause of the Minimum PERIOD value differing from the first path listed in the timing report is a cross clock domain analysis of phase shifted clocks Note If the phase difference between the two clock domains is 90 degrees the total data delay is multiplied by four to get to a full period value If the data path is 1 5ns for this clock90 constraint the equivalent full period value is 6 ns In addition for this example the data path goes from a falling edge of CLKO clock signal to the rising edge of CLK90 clock signal and the timing analysis includes the two phase information from CLKO to do the analysis as shown in Figure 6 7 Clock Edge Relationship The original PERIOD constraint was set to 20 ns but this cross clock domain analysis has the new requirement of 15 ns to compensate for the phase difference between the two clocks as shown in Figure 6 6 Clock Phase between DCM outputs L 1 5 ns gt 0 10 20 30 40 CLKO 5 15 25 35 CLK90 X11099 Figure 6 7 Clock Edge Relationship Timing Report Example Slack setup path 5 398ns requirement data path clock path skew uncertainty Source IntB_2 FF Destination XorB_2 FF Requirement 8 000ns
17. For example define output delay portb 7 0 10 00 ref clock2 f e routeisanadvanced option that includes route delay when the synthesis tool tries to meet the clock frequency goal Output Pad Clock Domain Default By default define output delay constraints with no reference clock are constrained against the global frequency instead of the start clock for the path to the port The synthesis tool assumes the register and pad are not in the same clock domain This change affects the timing report and timing driven optimizations on any logic between the register and the pad You must specify the clock domain for all output pads on which you have set output delay constraints For the pads for which you do not specify a clock add the re option to the define output delay constraint define output delay LDCOMP 0 50 improve 0 00 route 0 25 ref CLK1 r define_path_delay The define_path_delay constraint specifies point to point delay in nanoseconds ns for maximum and minimum delay constraints You can specify the start end or through points using the rom to or through options or any combination of these options If you specify both de ine path delay max and define_multicycle_path for the same path the synthesis tool uses the more restrictive of the two constraints When you specify define_path_delay and you also define input or output delays the synthesis tool adds the input or output delays to the path delay The t
18. Manually Related Synchronous Clock Domains In some cases the relationship between synchronous clock domains can not be automatically determined by the tools for example when related clocks enter the FPGA device on separate pins In this case Xilinx recommends that you e Define a separate PERIOD constraint for each input clock e Define a manual relationship between the clocks Once you define the manual relationship all paths between the two synchronous domains are automatically analyzed The analysis takes into account all frequency phase and uncertainty information The Xilinx constraints system allows you to define complex manual relationships between clock domains using the PERIOD constraint including clock frequency and phase transformations To define complex manual relationships between clock domains using the PERIOD constraint e Define the PERIOD constraint for the primary clock e Define the PERIOD constraint for the related clock using the first PERIOD constraint as a reference For more information on using the PERIOD constraint to define clock relationships see PERIOD Constraints in Chapter 3 Timing Constraint Principles Two related clocks enter the FPGA device through separate external pins as shown in Figure 2 6 Two related clocks entering the FPGA device through separate external pins e The first clock CLK1X is the primary clock e The second clock CLK2X180 is the related clock Tra
19. OFFSET subtracts this time from the clock PERIOD to determine the time available for the data to propagate from the synchronous element to the pad You can visualize this time as the data leaving the edge of the device before the next clock edge arrives at the edge www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Clock Skew Clock Skew of the device This OFFSET OUT 2 ns BEFORE clock_pad constraint reads that the Data to be registered in the Downstream Device is available on the FPGA s output Pad some time period BEFORE the clock pulse is seen by the Downstream Device For the purposes of the OFFSET constraint syntax assume no skew on CLK between the chips The following equation defines this relationship TQ TData20ut TClock lt TPeriod Toffset_OUT_BEFORE where TO Intrinsic Flip Flop Clock to Out TClock Total Clock path delay to the Flip Flop TData20ut Total Data path delay from the Flip Flop TPeriod Single Cycle PERIOD Requirement Toffset_OUT_BEFORE Overall Clock to Out Requirement The analysis of the OFFSET OUT constraint involves ensuring that the maximum delay along the reference path CLK_SYS to COMP and the maximum delay along the data path COMP to Q_OUT do not exceed the clock period minus the specified offset A PERIOD or FREQUENCY is required for OFFSET OUT constraints with the BEFORE keyword Clock skew analysis is included in both a setup and hold a
20. allow block block name been omitted loci loc2 locn Online Document The following conventions are used in this document Convention Meaning or Use Example f link 1 See the section Additional Cross re erence in toa ocation Resources for details Blue text in the current file or in another file in the current document Refer to Title Formats in Chapter 1 for details www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Conventions Convention Meaning or Use Example Cross reference link to a location See Figure 2 5 in the Virtex II ei in another document Platform FPGA User Guide Go to http www xilinx com for the latest speed files Blue underlined text Hyperlink to a website URL Timing Constraints User Guide www xilinx com 5 UG612 v 11 1 1 April 29 2009 Preface About the Timing Constraints User Guide XILINX 6 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 Preface About the Timing Constraints User Guide Timing Constraints User Guide Contents ooooococcocccccccccccccco 3 Additional Resources 0 0 c ccc nent t ene e 3 Conventions Vid A ee edad ee baie 3 Typographical carita assi ion iia dis ias aes 4 Online Documents nana A o bE EXC ERE EE 4 Chapter 1 Introduction to the Timing Constraints User Guide Chapter 2 Timing Constraint Methodology
21. ii I re E ee dee due a dre aos e 30 PHASE Keyword sssi sie oe cage e ea p e er pertes epe lead 31 DLL DCM PLL Manipulation with PHASE 6 6 ee 31 Timing Group Creation with TNM TNM_NET Attributes ooooooooooo 32 About Timing Group Creation with TNM TNM NET Attributes 32 Net Connectivity NED 2eSebeecc tee erR4 cda de kis 32 Predefined Time STOUPS iia estia aute C sedet aue eq e A ee Bane 34 Propagation Rules for TNM_NET 0 cece e 35 Instance or EDerarchy i ta ia eat 36 Instance Pins dubi Ax RAE RA GRAN Rx EVE nr o ded Ae ean 39 Grouping Constraints 0 0 0 6 6c ne cent tenet Ta 40 Patter Matching Vx yee tele RU E ERE RP Y E Ged ea pea 42 Time Group Exatiples i23 sas da eee dete a eee Rae b st dre aa 43 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 Constraint Priorities lesse Re es 44 TN Constraints oos d en at bs A RO E d ipu 46 About Timing Constraints sssseeesssseeee nee 46 Timing Constraint Exceptions secs esere seneese ee nnn 46 Setting Timing Constraint Requirements 0 0 nsss cece cette eee 46 PERIOD Constraints tna A eate pog tede ia did Beg ends 47 About PERIOD Constraints lees 47 Related TIMESPEC PERIOD Constraints 0 0 000 ccc eee eee eens 48 Paths Covered by PERIOD Constraints eese 49 OFFSET Constraints e exer ideal n de eed wee a ti 51 About OFFSET Constraints 0 een eee t
22. set the syn_keep directive Verilog or VHDL on the signal define_false_path Syntax Example The following example shows the syntax for setting define_false_path between registers define false path from i myInstl1 reg through n myInst2_net to i myInst3 reg The constraint is defined from the output pin of myInst1_reg through net myInst2_net to the input of myInst3_reg If an instance is instantiated a pin level constraint applies on the pin as defined However if an instance is inferred the pin level constraint is transferred to the instance For through points specified on pins the constraint is transferred to the connecting net You cannot define a through point on a pin of an instance that has multiple outputs When specifying a pin on a vector of instances you cannot refer to more than one bit of that vector define_input_delay The define_input_delay constraint specifies the external input delays on top level ports in the design It is the delay outside the chip before the signal arrives at the input pin The define_input_delay constraint is used to model the interface of the inputs of the FPGA device with the outside environment The synthesis tool cannot detect the input delay unless you specify it in a timing constraint define_input_delay Syntax define_input_delay disable inputportName default ns route ns ref clockName edge comment textString where e disable disables a previou
23. signal is value units where e value isa positive integer Valid units are ps ns micro ms Gattribute maxdelay string Hz MHz and KHz The default is ns Maximum Delay MAXDELAY VHDL Syntax Example entity top yann mem data path iobs 0 is port CLK in std logic das delayed out std logic vector 31 downto 0 READ EN DELAYED RISE out std logic vector 31 downto 0 READ EN DELAYED FALL out std logic vector 31 downto 0 attribute maxdelay string attribute maxdelay of READ EN DELAYED RISE signal is 800 ps attribute maxdelay of READ EN DELAYED FALL signal is 800 ps end entity Timing Constraints User Guide www xilinx com 67 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX Maximum Delay MAXDELAY Verilog Syntax MAXDELAY value units Maximum Delay MAXDELAY Verilog Syntax Example module mig_22 inout 7 0 cntrl10_ddr2_dq output 14 0 cntr10 ddr2 a input sys_clk_p input sys_clk_n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntrl0_ddr2_dqs ee wire clk_0 wire clk_90 wire clk_200 MAXDELAY 800 ps wire read_en reg sys_rst source code End module Maximum Skew MAXSKEW Maximum Skew MAXSKEW controls the amount of skew on a net Skew is the difference between the delays of all loads driven by the net For more
24. 0 118 OFFSET IN Constraints 0 000 00 ence cette ene eee 120 OFFSET IN BEFORE Constraints lesser 121 OFFSET IN AFTER Constraints 0 0 0 0 ccc cence ence een ene 128 OFFSET OUT Constraints 0 0 00000 ss 128 OFFSET OUT AFTER Constraints aean ccc eee 129 OFFSET OUT BEFORE Constraints l l 134 Clock SKEW ee Lb tee ebd bunt rta quede dta quede ir 135 Clock Unc rtainty eia epe up A 137 Asynchronous Reset Paths uuuuuuusssssssss eee 138 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 7 XILINX Chapter 1 Introduction to the Timing Constraints User Guide The Timing Constraints User Guide addresses timing closure in high performance applications The Guide is designed for all FPGA designers from beginners to advanced The high performance of today s Xilinx devices can overcome the speed limitations of other technologies and older devices Designs that formerly only fit or ran at high clock frequencies in an ASIC device are finding their way into Xilinx FPGA devices In addition designers must have a proven methodology for obtaining their performance objectives This Guide discusses The fundamentals of timing constraints including PERIOD Constraints OFFSET Constraints FROM TO Multi Cycle Constraints The ability to group elements and provided a better understanding of the constraint system software
25. 1 1 April 29 2009 7 XILINX Timing Constraints Note l the two PERIOD constraints are not related in this method the cross clock domain data paths is not covered or analyzed by any PERIOD constraint In Figure 3 12 Unrelated clock domains since CLKA and CLKB are not related or asynchronous to each other the data paths between register four and register five are not analyzed by either PERIOD constraint FLoP1 7 BA pi opo E pops BUS 7 0 D gt ES S Unconstrained Data Path L gt amp p Constrained Data Path X11072 Figure 3 12 Unrelated clock domains Paths Covered by PERIOD Constraints The PERIOD constraint covers paths only between synchronous elements Pads are not included in this analysis NGDBuild issues a warning if you have pad elements in the PERIOD time group Analysis between unrelated or asynchronous clock domains is also not included The PERIOD constraint analysis includes the setup and hold analysis on synchronous elements The setup analysis ensures that the data changes at the destination synchronous element prior to the clock arrival Note The data must become valid at its input pins at least a setup time before the arrival of the active clock edge at its pin The equation for the setup analysis is the data path delay plus the synchronous element setup time minus the clock path skew Setup Time Data Path Delay Synchronous Element Setup Time Cl
26. 29 2009 7 XILINX XST Timing Constraints Asynchronous Register ASYNC_REG The Asynchronous Register ASYNC_REG constraint can be attached only on registers or latches with asynchronous input D input or the CE input For more information see the Constraints Guide Asynchronous Register ASYNC_REG VHDL Syntax attribute ASYNC_REG string attribute ASYNC_REG of instance_name signal is TRUE FALSE Asynchronous Register ASYNC_REG VHDL Syntax Example architecture behavioral of top yann mem infrastructure is begin signal sys rst std logic attribute ASYNC REG string attribute ASYNC REG of sys rst signal is TRUE source code End behavioral Asynchronous Register ASYNC REG Verilog Syntax ASYNC REG TRUE FALSE Asynchronous Register ASYNC REG Verilog Syntax Example module mig 22 inout 7 0 cntrl10 ddr2 dq output 14 0 cntr10 ddr2 a input sys_clk_p input sys_clk_n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntrl10 ddr2 das ps wire clk 0 wire clk 90 wire clk 200 ASYNC REG TRUE reg sys rst source code End module Clock Signal CLOCK SIGNAL Note Clock Signal applies to all FPGA devices Clock Signal does not apply to CPLD devices If a clock signal goes through combinatorial logic before being connected to the clock input of a flip flop XST cannot identify which input pin or internal signal i
27. About Timing Constraint Methodology 0 e eee eee n Basic Constraints Methodology sss sees 12 Input Timing Constraints AMM 12 About Input Timing Constraints 0 6666 e 13 System Synchronous Inputs 0 00 13 Source Synchronous Inputs ss eenei eies enn nee eee 14 Register To Register Timing Constraints 0 0 0 00 cece ee eee 16 About Register To Register Timing Constraints 000 eee eee eee 16 Automatically Related Synchronous DCM PLL Clock Domains 17 Manually Related Synchronous Clock Domains 000 0c eee eee 18 Asynchronous Clock Domains 00666 19 Output Timing Constraints 0 000 000 20 System Synchronous Output 0 0 eee eee eee 21 Source Synchronous Outputs 2 eee eee ee 22 Timing EXcepllOns iioii seen erpa nE uaea nea kaaa aai a 24 False Paths s osa x tek et e a pic Y a ERR AG E RR a le 24 Multi Cycle Paths ciis ve e a rr eR 25 Chapter 3 Timing Constraint Principles Constraint Syslem svedese the d o exte Re eer ER reei enaiga kA pq rab da 27 About the Constraint System seisce sciana ne 27 DLL DCM PLL BUFR PMCD Components eee e 28 About DLL DCM PLL BUFR PMCD Components ococccooccocccoccooccoo 28 Transformation Conditions ccc cece eee s 28 New PERIOD Constraints on DCM Outputs isses ee 29 Synchronous Elements isa ep e v a 30 Analysis with NET PERIOD
28. Data Path Delay 2 542ns Levels of Logic 1 Clock Path Skew 0 000ns Source Clock clkO falling at 2 000ns Destination Clock clk90 rising at 10 000ns Slack setup path 13 292ns requirement data path clock path skew uncertainty Source IntC_2 FF Destination XorB_2 FF Requirement 15 000ns Data Path Delay 2 594ns Levels of Logic 1 Clock Path Skew 0 086ns Source Clock clkO falling at 10 000ns www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX PERIOD Constraints Destination Clock clk90 rising at 25 000ns Clock Uncertainty 0 200ns Clk2x Clock Domain Since the clocks produced by the DCM PLL DLL PMCD are related the timing tools take this relationship into consideration during analysis A simple design of a CLK2X clock domain is illustrated in Figure 6 8 Clk2x DCM output schematic The clock is driven by the same clock source which is an output of a DCM DLL PLL PMCD component The timing analysis tool reporst the active edges of the clock and the corresponding time for the data path between the synchronous elements This clock domain has the requirement of the original requirement but the phase shifting is the same as the phase shifting of the original requirement CLK2X_DLL CLK2X BUFG X11100 Figure 6 8 Clk2x DCM output schematic Timing Report Example Slack setup path 1 663ns requirement data path clock path skew uncertainty
29. IN std logic Timing Constraints User Guide www xilinx com 83 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX attribute syn_black_box boolean attribute syn_black_box of bbram entity is true attribute syn_isclock boolean attribute syn_isclock of clk signal is true attribute syn_gatedclk_clock_en string attribute syn_gatedclk_clock_en of clk signal is en end entity bbram architecture bb of bbram is attribute syn_force_seq_prim boolean attribute syn_force_seq_prim of bb architecture is true begin end architecture bb syn_gatedclk_clock _en The syn_gatedc1k_clock_en directive specifies the enable pin to be used in fixing the gated clocks To use the syn gatedclk clock en directive with a black box you must also identify the clock signal with the syn_isclock directive and indicate that the fix gated clocks algorithm can be applied with the syn orce seq prim directive The data type is String syn gatedclk clock en Verilog Syntax object synthesis syn gatedclk clock en value where e object is the module name e value is the name of the enable pin syn_gatedclk_clock _en Verilog Syntax Example module bbe ena clk data_in data_out synthesis syn_black_box synthesis syn force seq prim 1 input clk synthesis syn isclock 1 synthesis syn gatedclk clock en ena input data in ena
30. Information about the analysis of the basic constraints with clock skew and clock uncertainty Specifying timing constraints in XST Specifying timing constraints in Synplify Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 Chapter 1 Introduction to the Timing Constraints User Guide 10 www xilinx com XILINX Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Chapter 2 Timing Constraint Methodology This chapter discusses Timing Constraint Methodology and includes e About Timing Constraint Methodology e Basic Constraints Methodology e Input Timing Constraints e Register To Register Timing Constraints e Output Timing Constraints e Timing Exceptions About Timing Constraint Methodology You must have a proven methodology in order to meet your design objectives This chapter outlines the process to e Understand the design requirements e Constrain the design to meet these requirements Before starting a design you must understand e The performance requirements of the system e The features of the target device This knowledge allows you to use proper coding techniques utilizing the features of the device to give the best performance The FPGA device requirements depend on the system and the upstream and downstream devices Once the interfaces to the FPGA device are known the internal requirements can be outlined H
31. LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2002 2009 Xilinx Inc All rights reserved XILINX the Xilinx logo the Brand Window and other designated brands included herein are trademarks of Xilinx Inc All other trademarks are the property of their respective owners www xilinx com 7 XILINX Preface About the Timing Constraints User Guide This chapter provides general information about this Guide and includes e Timing Constraints User Guide Contents e Additional Resources e Conventions Timing Constraints User Guide Contents The Timing Constraints User Guide contains the following chapters e Chapter 1 Introduction to the Timing Constraints User Guide e Chapter 2 Timing Constraint Methodology e Chapter 3 Timing Constraint Principles e Chapter 4 Specifying Timing Constraints in XST e Chapter 5 Specifying Timing Constraints in Synplify e Chapter 6 Timing Constraint Analysis Additional Resources For additional documentation see the Xilinx website at http www xilinx com support documentation index htm To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support mysupport htm Conventions This document uses the following conventions An example illustrates each convention e Typographical e Onlin
32. Multipliers e High speed input outputs The predefined group keywords can be used globally and to create user defined sub groups The predefined time groups are considered reserved keywords that define the types of synchronous elements and pads in the FPGA device For more information see Predefined Time Groups The user defined time group name is case sensitive and can overlap with other user defined time group and with predefined time groups An example of design elements being is multiple time groups In those cases a register is in the FFS predefined time group but is also in the c1k time group which is associated with the PERIOD constraint Use the following keywords to define user defined time groups TNM TNM_NET TIMEGRP If the instance or net associated with the user defined time group matches internal reserved words the time group or constraint is rejected The same is true for the user defined time group name In all the constraints files NCF UCE and PCF instances or variable names that match internal reserved words may be rejected unless the names are enclosed in double quotes If the instance or net name does match an internal reserved word enclose the name in double quotes Double quotes are mandatory if the instance or net name contains special characters such as the tilde or dollar sign Xilinx recommends using double quotes on all net and instances All elements with the same TNM or TNM_NE
33. PERIOD e PHASE Keyword e DLL DCM PLL Manipulation with PHASE About DLL DCM PLL BUFR PMCD Components When a TIMESPEC PERIOD specification on the input pad clock net is traced or translated through the DCM DLL PLL BUFR PMCD component also known as a clock modifying block the derived or output clocks are constrained with new PERIOD constraints In order to generate the destination element timing group during transformation each clock output pin of the clock modifying block is given e Anew TIMESPEC PERIOD constraint e A corresponding TNM_NET constraint The new TIMESPEC PERIOD constraint is based upon the manipulation of the clock modifying block component The transformation e Takes into account the phase relationship factor of the clock outputs e Performs the appropriate multiplication or division of the PERIOD requirement value Transformation Conditions The transformation occurs when e The TIMESPEC PERIOD constraint is traced into the CLKIN pin of the clock modifying block component and e The following conditions are met The group associated with the PERIOD constraint is used in exactly one PERIOD constraint The group associated with the PERIOD constraint is not used in any other timing constraints including FROM TO multicycle or OFFSET constraints www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Constraint System The group associated with t
34. THRU TO e THRU TO e FROM THRU e FROM e TO e FROM THRU THRU THRU TO A FROM TO constraint can cover the multi cycle paths that cover the path between clock domains For example one clock covers a portion of the design and another clock covers Timing Constraints User Guide www xilinx com 55 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX the rest but there are paths that go between these two clock domains as shown in Figure 3 22 Multicycle constraint covers a cross clock domain path You must have a clear idea of the design specifics and take into account the multiple clock domains FLOP FLOP FLOP ADATA Os Os OUS ai FLOP bh 9 FLOP gt ce Unconstrained Data Path BUFG de Constrained Data Path X11082 Figure 3 22 Multicycle constraint covers a cross clock domain path The cross clock domain paths between unrelated PERIOD constraints are analyzed in the Unconstrained Paths report If these paths are related incorrectly or if they require a different timing requirement then create a multicycle or FROM TO constraint The FROM TO constraint can be a specific value related to another TIMESPEC identifier or TIG Timing Ignore A path can be ignored during timing analysis with the label of TIG If the clocks are unrelated by the definition of the constraints but have valid paths between them then create a FROM TO constraint to constrain t
35. This compensates for the Clock Arrival time associated with the falling edge synchronous elements The negative value is legal in the constraints language 126 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET IN Constraints Option Two The second option is to create one time group and one corresponding OFFSET IN constraint with the original constraint requirement for each clock edge The only addition is the RISING FALLING keyword if the PERIOD constraint has the HIGH keyword The analysis with the RISING FALLING keywords is based upon the active clock edge for the synchronous element The requirement for the rising clock edge elements is set in the OFFSET IN RISING constraint The requirement for the falling clock edge elements are set in the OFFSET IN FALLING constraint In this example since the PERIOD constraint has the clock arrival on both the rising edge and falling edge the clock arrival value is O ns and 5 ns In Figure 6 16 Timing Diagram for Dual Data Rate in OFFSET IN Constraint the OFFSET requirement is three ns before the initial clock edge Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET IN 3 ns BEFORE clock RISING OFFSET IN 3 ns BEFORE clock FALLING Cik data_rising data_falling t 3ns 02 5 X11108 Figure 6 16 Timing Diagram for Dual Data Rate in OFFSET IN Constraint Timing Report
36. analyzes all delays on all paths that terminate at a pin with a setup and hold analysis relative to the clock net A typical analysis includes the data paths of Intrinsic Clock to Out delay of the synchronous elements Routing and Logic delay Intrinsic Setup hold delay of the synchronous elements Clock Skew between the source and destination synchronous elements Clock Phase DCM Phase and Negative Edge Clocking Clock Duty Cycles Timing Constraints User Guide www xilinx com 47 UG612 v 11 1 1 April 29 2009 48 Chapter 3 Timing Constraint Principles XILINX The PERIOD constraint includes e Clock path delay in the clock skew analysis for global and local clocks e Local clock inversion e Setup and hold time analysis e Phase relationship between related clocks Note Related Derived clocks can be a function of another clock and e DCM Jitter Duty Cycle Distortion and DCM Phase Error for Virtex 4 DCM Jitter PLL Jitter Duty Cycle Distortion and DCM Phase Error for Virtex 5 and new families as Clock Uncertainty e User Defined System and Clock Input Jitter as Clock Uncertainty e Unequal clock duty cycles non 50 e Clock phase including DCM phase and negative edge clocking Related TIMESPEC PERIOD Constraints Xilinx recommends that you associate a PERIOD constraint with every clock The preferred way to define PERIOD constraints is to use the TIMESPEC Period Constraint TIMESPEC allows you to define derived clock
37. be approximately one half cycle This insures that the DQ clock enables are de asserted before any possible DOS glitch at the end of the read post amble can arrive at the input to the IDDR This value is clock frequency dependent INST gen dqs u iob dqgs u iddr dq ce TNM TNM DQ CE IDDR INST gen dq u iob dqg gen stg2 u iddr dq TNM TNM DOS FLOPS TIMESPEC TS DQ CE FROM TNM DQ CE IDDR TO TNM DQS FLOPS TS SYS CLK 2 The requirement is based upon the system clock Timing Constraints User Guide www xilinx com 119 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX Example Two Constrain the paths from a select pin of a MUX to the next stage of capturing synchronous elements This value is clock frequency dependent NET c1k0 TNM FFS TNM_CLKO NET c1k90 TNM FFS TNM CLK90 MUX Select for either rising falling CLKO for 2nd stage read capture INST u phy calib 0 gen rd data sel u ff rd data sel TNM TNM RD DATA SEL TIMESPEC TS MC RD DATA SEL FROM TNM RD DATA SEL TO TNM CLKO TS SYS CLK 4 This requirement is based upon the system clock Example Three Constrain the path between DOS gate driving IDDR and the clock enable input to each of the DO capture IDDR in that DOS group Note that this requirement is frequency dependent and the user set the following requirement INST gen dqgs u iob dqs u iddr dq ce
38. bundle isa collection of buses and scalar signals To assign values to bundles use the following syntax The values are in ns clock gt bundle value e is an optional exclamation mark indicating a negative edge for a clock The objects of a bundle must be separated by commas with no spaces between A valid bundle is A B C which lists three signals syn_tcon Verilog Syntax Example Following is an example defining syn_tcon with other black box constraints module ram32x4 z d addr we clk synthesis syn black box syn_tcol clk gt z 3 0 4 0 syn_tpdl addr 3 0 gt z 3 0 8 0 syn_tsul addr 3 0 gt clk 2 0 syn tsu2 we clk 3 0 output 3 0 z input 3 0 d input 3 0 addr input we input clk endmodule syn tcon VHDL Syntax attribute syn tcon of object objectType is clock bundle value where e bundle isa collection of buses and scalar signals To assign values to bundle use the following syntax The values are in ns clock gt bundle value e is an optional exclamation mark indicating a negative edge for a clock The objects of a bundle must be separated by commas with no spaces between A valid bundle is A B C which lists three signals In VHDL there are ten predefined instances of each of these directives in the synplify library for example syn tcol syn tco2 syn tco3 syn tcol10 If you are entering the timing directives in the source code and you require
39. covers path In addition to usinge multicycle constraints in the Pad to Pad path multicycle constraints can be used to define a slow exception of the design This is an exception from the PERIOD constraint which constrains the majority of the design Figure 3 25 Slow Exception Multicycle constraint overlaps a PERIOD constraint shows the use of a FROM TO slow exception in conjunction with a PERIOD The top graphic uses FROM TO only and is not OU TID DU 11 gt NET CLK PERIOD 30ns IN FROM FLOP1 TO FLOP2 30 FROM FLOP2 TO FLOPS 30 gt gt gt CL gt gt b 30 ns 60 ns NET CLK PERIOD 30ns Figure 3 25 Slow Exception Multicycle constraint overlaps a PERIOD constraint recommended The bottom graphic uses PERIOD with a FROM TO slow exception This is the recommended method A Clock Enable net can define a slow exception as shown in Figure 3 26 Slow Time Group overlaps the Fast Time Group for a FROM TO exception NET clk en TNM slow exception NET clk TNM normal TIMESPEC TS01 PERIOD normal 8 ns TIMESPEC TS02 FROM slow exception TO slow exception TS01 2 E HE 30 ns 60 ns D IN Q ee 1 TNM FAST PCE TNM FAST TNM SLOW OUT TNM FAST TNM SLOW CLK EN X11086 Figure 3 26 Slow Time Group overlaps the Fast Time Group for a FROM TO exception Timing Constraints User Guide www xilinx com 57 UG612 v 11 1 1 A
40. define clock delay Syntax Example Define clock delay rise clk0 rise clk2x 2 define compile point Thedefine compile point command defines a compile point in a top level constraint file Use one define compile point command for each compile point you define Note The de ine compile point command is available only for Synplify Pro and Synplify Premier define compile point Syntax define compile point disable regionName moduleName type locked cpfile comment textString Timing Constraints User Guide www xilinx com 95 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX where e disable disables a previous compile point definition e type specifies the type of compile point This must be locked e cpfile is for Synplicity internal use only define_compile_point Syntax Example define compile point v work prgm cntr type locked define current design The define current design command e Specifies the compile point region or module to which the constraints that follow it apply e Must be the first command in a compile point constraint file Note The define current design command is available only for Synplify Pro and Synplify Premier define current design Syntax define current design regionName libraryName moduleName define current design Syntax Example define current design libl prgm_cntr Objects in all constraints that follow th
41. device as shown in Figure 2 8 Output timing constraints from input clock pad to the output data pad www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Output Timing Constraints lu Cikin 1 i OFFSET OUT AFTER l l l Data 1 I Valid Data Data 2 I Valid Data X11054 Figure 2 8 Output timing constraints from input clock pad to the output data pad When analyzing the OFFSET OUT constraint the timing tools automatically take all internal factors affecting the delay of the clock and data paths into account These factors include e Frequency and phase transformations of the clock e Clock uncertainties e Data path delay adjustments For more information see OFFSET OUT Constraints in Chapter 3 Timing Constraint Principles System Synchronous Output The system synchronous output interface is an interface in which a common system clock is used to both transfer and capture the data Since this interface uses a common system clock only the data is transmitted from the FPGA device to the receiving device as shown in Figure 2 9 Simplified System Synchronous output interface with associated SDR timing Receiving Device Transmit Capture Edge Edge 1 System Clock I 1 System Clock x11055 Figure 2 9 Simplified System Synchronous output interface with associated SDR timing If these paths must be constrained the global OFFSET OUT const
42. eeeeeeeee eee 77 Timing Name Net TNM NET seeseeeeeeeeee en 77 Timing Name Net TNM NET XCF Syntax sese e 77 Timing Name Net TNM NET XCF Syntax Example esee 77 Chapter 5 Specifying Timing Constraints in Synplify Synplify Timing Constraints oyo ia ir Ead e punire a 79 Specifying Timing Constraints in HDL 0 0 0 0 e eee eee 80 black box pad pi esee di etes 81 black box pad pin Verilog Syntax 6 6 cee eee eee 81 black box pad pin Verilog Syntax Example 6 00 0 cee cece eee eee 81 black box pad pin VHDL Syntax esee n 81 black box pad pin VHDL Syntax Example see 81 black box tric PINS uec teste et eet ente dete en eda usd a tor edes c peteret ara 82 black box tri pins Verilog Syntax isses e 82 black box tri pins Verilog Syntax Example sese 82 black box tri pins VHDL Syntax 1 6 eee tenes 82 black box tri pins VHDL Syntax Example lese 82 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 Syn forc seq prim caia sii eds 83 syn force seq prim VerilogSyntax esee en 83 syn force seq prim Verilog Syntax Example sees 83 syn force seq prim VHDL Syta ksi aak k aari a aa EAA en 83 syn force seq prinVHDL Syntax Example lesen 83 syn gatedclk clock en civic noc c Rer teer ker EE IEEE reris 84 syn gatedclk clock en Verilog Syntax sese 84 syn gatedclk
43. element When you create clock to pad requirements be sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET OUT constraint For the following example see Figure 6 6 Clock Phase between DCM outputs If the register is clocked by the net from the CLK90 pin of the DCM which has a PERIOD of 20 ns the OFFSET value should be adjusted by 5 ns less than the original constraint e Original Constraint NET PAD_OUT OFFSET OUT 15 AFTER PADCLKIN e Modified Constraint NET PAD_OUT OFFSET OUT 10 AFTER PADCLKIN www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET OUT Constraints OFFSET OUT AFTER Constraints The OFFSET OUT AFTER constraint defines the time available for the data to propagate from the synchronous element to the pad as shown in Figure 6 17 Circuit Diagram with Calculation Variables for OFFSET OUT AFTER constraints You can visualize this time as the data leaving the edge of the device after the current clock edge arrives at the edge of the device This OFFSET OUT 2 ns AFTER clock pad constraint reads that the Data to be registered in the Downstream Device is available on the FPGA device s data output pad some time period 2 ns AFTER the reference clock pulse is seen by the FPGA device at the clock pad T_DATA_OUT 2 OFFSET OUT CLK T_CLK_OUT X11109 Figure 6 17
44. element paths e Input requirements with Global OFFSET IN constraints Constrains interfacing inputs to synchronous elements paths e Output requirements with Global OFFSET OUT constraints Constraints interfacing synchronous elements to outputs to paths e Combinatorial path requirements with Pad to Pad constraint You can use more specific path constraints for multi cycle or static paths A multi cycle path is a path between two registers or synchronous elements with a timing requirement that is a multiple of the clock PERIOD constraint for the registers or synchronous elements A static path does not include clocked elements such as Pad to Pad paths Timing Constraint Exceptions Once the foundation of timing constraints is laid then the exceptions need to be specified and constrained e Use FROM TO multi cycle constraints to create exceptions to the PERIOD constraints e Use Pad Time Group based OFFSET constraints and NET based OFFSET constraints to create exceptions to the Global OFFSET constraints Setting Timing Constraint Requirements Xilinx recommends that you set the timing constraint requirements to the exact timing requirement value required for a path as opposed to over tightening the requirement Specifying tighter constraint requirements can cause e Lengthened Place and Route PAR or implementation runtimes e Increased memory usage e Degradation in the quality of results www xilinx com Timing Constraints User Guide U
45. following files e UCF e NGC e EDN e EDIF EDF The timing analysis is on timing constraints which are applied to logical paths The logic paths typically start and stop at pads and synchronous elements The grouped elements signify the starting and ending points for timing analysis These starting and ending points can be based upon predefined groups user defined groups or both The timing groups are ideal for identifying groups of logic that operate at different speeds or have different timing requirements 40 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Constraint System The time groups are used in the timing analysis of the design The user defined and predefined time group informs the timing analysis tools the start and end points for each path being analyzed The time groups are used in the following constraints e PERIOD e OFFSET IN e OFFSET OUT e FROM TO Multi cycle e TIG Timing Ignore When using a specific net or instance name you must use its full hierarchical path name This allows the implementation tools to find the net or instance The pattern matching wildcards can be used to specify when creating time groups with predefined time group qualifiers This is done by using placing a pattern in parenthesis after the time group qualifier The predefined groups can reference all the following among others e Flip flops e Latches e Pads e RAMs e CPUs e
46. information see the Constraints Guide Maximum Skew MAXSKEW VHDL Syntax attribute maxskew string attribute maxskew of signal_name signal is allowable_skew units where e allowable_skew is the timing requirement e valid units are ms micro ns or ps The default is ns Maximum Skew MAXSKEW VHDL Syntax Example entity top_yann_mem_infrastructure is port SYS_CLK_P in std_logic SYS_CLK_N in std_logic CLK200_P in std_logic CLK200_N in std_logic CLK out std_logic REFRESH_CLK Out std_logic sys_rst out std_logic J attribute maxskew string attribute maxskew of sys_rst signal is 3 ns end entity 68 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX XST Timing Constraints Maximum Skew MAXSKEW Verilog Syntax MAXSKEW allowable skew units where e allowable_skew is the timing requirement e valid units are ms micro ns or ps The default is ns Maximum Skew MAXSKEW Verilog Syntax Example module mig_22 inout 7 0 cntrl10_ddr2_dq output 14 0 cntrl0_ddr2_a input sys_clk_p input sys_clk_n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntr10_ddr2_dgs jt wire clk 0 wire clk 90 wire clk 200 MAXSKEW 3 ns wire read en reg sys rst source code End module Offset OFFSET The Offset OFFSET constraint specifies the timing relationship between an ext
47. initial clock edge at 0 ns based upon the PERIOD constraint Since the clock is phase shifted by the DCM the timing report displays the Clock Arrival time as the phase shifted amount If the CLKO output is phase shifted by a user specified amount the phase shifted amount is a percentage of the PERIOD In this example the PERIOD constraint has the initial clock arrival on the rising edge but the clock arrival value is at the fixed phase shifted amount as seen in the example timing report The Clock Arrival time corresponds to the phase shifting amount The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold In Figure 6 21 the OFFSET requirement is five ns 132 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET OUT Constraints Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET OUT 5 ns AFTER clock clock_in Lio ns R clkO data X11113 Figure 6 21 Timing Diagram of Fixed Phase Shifted Clock in OFFSET OUT Constraint Timing Report Example Slack 0 535ns requirement clock arrival clock path data path uncertainty Source OutD 7 FF Destination OutD 7 PAD Source Clock clock3 std bufg rising at 0 600ns Requirement 5 000ns Data Path Delay 3 405ns Levels of Logic 1 Clock Path Delay 0 280ns Levels of Logic
48. input clock To specify the input timing e Define the clock PERIOD constraint for the input clock associated with the interface e Define the global OFFSET IN constraint for the interface Example A timing diagram for an ideal System Synchronous SDR interface is shown in Figure 2 2 Timing diagram for an ideal System Synchronous SDR interface The interface has a clock period of 5 ns The data for both bits of the bus remains valid for the entire period Transmit Capture Edge Edge I l anm PERIOD 5 ns SysClk l I 1 14 OFFSET IN BEFORE 5ns I l m VWAUD25ns X11048 Figure 2 2 Timing diagram for an ideal System Synchronous SDR interface The global OFFSET IN constraint is OFFSET IN value VALID value BEFORE clock In the OFFSET IN constraint the OFFSET IN lt value gt determines the time from the capturing clock edge to the time in which data first becomes valid In this system synchronous example the data becomes valid 5 ns prior to the capturing clock edge In the OFFSET IN constraint the VALID lt value gt determines the duration in which data remains valid In this example the data remains valid for 5 ns For this example the complete OFFSET IN specification with associated PERIOD constraint is NET SysCLk TNM_NET SysClk TIMESPEC TS_SysClk PERIOD SysClk 5 ns HIGH 50 OFFSET IN 5 ns VALID 5 ns BEFORE SysClk Th
49. module or macro are part of the named time group Use the keep_hierarchy attribute to ensure that the design hierarchy is maintained This feature is illustrated in e Figure 3 5 The TNM on the upper left hierarchy is traced down to the lower level element e Figure 3 6 Grouping via Instances www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Constraint System TNM FFS FLOPS RAMS MEM X11065 Figure 3 5 The TNM on the upper left hierarchy is traced down to the lower level element TNM FLOPS TNM FLOPS X11066 Figure 3 6 Grouping via Instances You can use wildcard characters to transverse the hierarchy of a design e A question mark represents one character e An asterisk represents multiple characters Timing Constraints User Guide www xilinx com 37 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX The following example uses a wildcard character to transverse the hierarchy where Levell is a top level module Level1 Transverses all blocks in Levell and below Level1 Transverses all blocks in Levell but no further The instances described below are either Symbols on a schematics or A symbol name as it appears in the EDIF netlist An example of the wildcard transversing the design hierarchy is shown in Figure 3 6 Grouping via Instances for the following insta
50. modules even though the modules do not interact with each other Since these modules do not interact with each other you can use a TIG Timing Ignore constraint or set the FROM TO constraint to a large requirement Figure 3 30 Common Bus is the Through Point shows an example NET DATA BUS TPTHRU DataBus TIMESPEC TS TIG FROM FFS THRU DataBus TO FFS TIG OR TIMESPEC TS data bus FROM FFS THRU DataBus TO FFS 123ns Timing Constraints User Guide www xilinx com 59 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX 60 Control Status Register Registers Status_Enable Control_Enable DATA_BUS 7 0 X11090 Figure 3 30 Common Bus is the Through Point In addition to using a TPTHRU constraint you can apply a TPSYNC constraint to specific pins or combinatorial logic in order to force the timing analysis to stop or start at a non synchronous point The TPSYNC constraint defines non synchronous points as synchronous points for multicycle constraints and analysis The path to a three state buffer for example can be constrained with the TPSYNC constraint Figure 3 31 Constraint to Three state Buffer with FROM TO shows an example of constraining the path to the three state buffer NET 3M17 Blue TPSYNC Blue_S TIMESPEC TS_1A FROM FFS TO Blue_S 15 Figure 3 31 Constraint to Three state Buffer with FROM TO 3M17 BLUE X
51. more than ten different timing delay values for any one of the directives declare the additional directives with an integer greater than 10 syn tcon VHDL Syntax Examples attribute syn tcoll1 string attribute syn tcoll of bitreg component is clk gt do0 dol 2 0 attribute syn tcol2 string attribute syn tcol2 of bitreg component is clk gt do2 do3 1 8 Timing Constraints User Guide www xilinx com 89 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX The following example assigns syn_tcon along with other black box constraints A USE clause for the Synplify Attributes package was included earlier to make the timing constraint definitions visible here architecture top of top is component Dpram10240x8 port Port A C1kA EnA WeA in std logic AddrA in std logic vector 13 downto 0 DinA in std logic vector 7 downto 0 DoutA out std logic vector 7 downto 0 Port B CIkB EnB in std logic AddrB in std logic vector 13 downto 0 DoutB out std logic vector 7 downto 0 end component attribute syn black box boolean attribute syn tsul string attribute syn tsu2 string attribute syn tcol string attribute syn tco2 string attribute syn isclock boolean attribute syn black box of Dpram10240x8 component is true attribute syn tsul of Dpram10240x8 component is EnA WeA AddrA DinA gt ClkA 3 0
52. option with to or from to get a specific path To keep the signal name intact throughout synthesis when you use this option set the syn_keep directive Verilog or VHDL on the signal max sets the maximum allowable delay for the specified path This is an absolute value in nanoseconds ns and is shown as max analysis in the timing report define_path_delay Syntax Examples define path delay from i dmux alu 5 to i regs mem regfile 15 0 max 0 800 The following example sets a max delay of 2 ns on all paths to the falling edge of the flip flops clocked by c1k1 define path delay to c clk1 f max 2 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL The following example sets the path delay constraint on the pins between registers define path delay from i myInstl_reg through t myInst2_net Y to i myInst3 reg max 0 123 The constraint is defined from the output pin of myInst1 through pin Y of net myInst2 to the input pin of myInst3 If the instance is instantiated a pin level constraint applies on the pin as defined If the instance is inferred the pinlevel constraint is transferred to the instance For through points specified on pins the constraint is transferred to the connecting net You cannot define a through point on a pin of an instance that has multiple outputs When specifying a pin on a vector of inst
53. output data out endmodule syn gatedclk clock en VHDL Syntax attribute syn gatedclk clock en of object objectType is value where e object is the entity name of the black box syn gatedclk clock en VHDL Syntax Example architecture top of top is component bbram port myclk in bit opcode in bit vector 2 downto 0 a b in bit vector 7 downto 0 rambus out bit vector 7 downto 0 end component attribute syn black box boolean 84 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in HDL attribute syn_black_box of bbram component is true attribute syn_force_seq_prim boolean attribute syn_force_seq_prim of bbram component is attribute syn_isclock boolean attribute syn_isclock of myclk signal is true attribute syn_gatedclk_clock_en string attribute syn_gatedclk_clock_en of bbram signal is Other code syn_gatedclk_clock_en_polarity true ena The syn_gatedclk_clock_en_polarity directive indicates the polarity of the clock enable port on a black box This allows the synthesis tool to apply the algorithm to fix gated clocks If you do not set any polarity with this attribute the synthesis tool assumes a positive polarity by default syn_gatedclk_clock_en_polarity Verilog Syntax object synthesis syn_gatedclk_clock_en_polarity where e object is the module name of the black box 1 0 The valu
54. pin connectivity allows you to group elements by specifying a pin that eventually drives synchronous elements and pads This method uses TNM timing name on a pin of the design If a TNM attribute isplaced on a pin the constraints parser traces the pin downstream to the synchronous elements A TNM is an attribute that can be used to identify the elements that make up a time group that can be then used in a timing constraint Timing Constraints User Guide www xilinx com 39 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX An example of this method is shown in Figure 3 8 INM placed on Macro Pin traces downstream to synchronous elements X11068 Figure 3 8 TNM placed on Macro Pin traces downstream to synchronous elements When placing a TNM constraint on a pin a qualifier can be used to narrow the list of elements in the time group A qualified TNM is traced forward until it reaches the first synchronous element hat matches the qualifier type The qualifier types are the predefined time groups If that type of synchronous element matches the qualifier the synchronous element is given that TNM attribute Whether or not there is a match the TNM is not traced through the synchronous element For more information see Predefined Time Groups Grouping Constraints Grouping constraints allow you to group similar elements together for timing analysis They can be defined in the
55. relationships with other TIMESPEC PERIOD constraints An example of this complex derivative relationship is done automatically through the DLL DCM PLL BUFR PMCD Components component outputs The derived relationship is defined with one TIMESPEC PERIOD in terms of another TIMESPEC PERIOD When a data path goes from one clock domain to another clock domain and the PERIOD constraints are related the timing tools perform a cross clock domain analysis This is very common with the outputs from the DLL DCM PLL BUFR PMCD Components For more information see Constraint System Note During cross clock domain analysis of related PERIOD constraints the PERIOD constraint on the destination element covers the data path In Figure 3 11 Related PERIOD Constraints TS_PERIOD 1 is related to TS_PERIOD 2 The data path is analyzed by TS_PERIOD 2 Period 1 Period 2 X11071 Figure 3 11 Related PERIOD Constraints When PERIOD constraints are related to each other the design tools can determine the inter clock domain path requirements as shown in Figure 3 12 Unrelated clock domains Following is an example of the PERIOD constraint syntax The TS_Period_2 constraint value is a multiple of the TS_Period_1 TIMESPEC TIMESPEC TS Period 1 PERIOD clkl_in_grp 20 ns HIGH 50 TIMESPEC TS Period 2 PERIOD clk2 in grp TS Period 1 2 www xilinx com Timing Constraints User Guide UG612 v 11
56. specify all the bits on the bus attribute black box tri pins of bbl component is bus1 7 0 syn force seq prim The syn force seq prim directive iindicates that gated clocks should be fixed for this black box and the fix gated clocks algorithm can be applied to the associated primitive The syn force seq prim directive is available only in Synplify Pro and Synplify Premier To use the syn force seq prim directive with a black box you must also identify the clock signal with the syn isclock directive and the enable signal with the syn gatedclk clock en directive The data type is Boolean syn force seq prim Verilog Syntax object synthesis syn force seq prim 1 where e object is the module name of the black box syn force seq prim Verilog Syntax Example module bbe ena clk data in data out synthesis syn black box synthesis syn force seq prim 1 input clk synthesis syn isclock 1 synthesis syn gatedclk clock en ena input data in ena output data out endmodule syn force seq prim VHDL Syntax attribute syn force seq prim of object objectType is true where e object is the entity name of the black box syn force seq primVHDL Syntax Example library ieee use ieee std logic 1164 all entity bbram is port addr IN std logic VECTOR 6 downto 0 din IN std logic VECTOR 7 downto 0 dout OUT std logic VECTOR 7 downto 0 clk IN std logic en IN std logic we
57. the positive and negative clock skew being truncated to zero for setup and hold checks respectively The report displays the clock path to the source and the clock path to the destination Review the paths to determine if the design has one of the causes of clock skew that were previously mentioned The timing analysis tools subtract the clock path delays to produce the clock skew as reported in the timing report Note The DLY file produced by Reportgen after PAR can also be used to determine the values used to calculate the clock skew value that was reported When calculating the clock path delay the timing analysis tool traces the clock path to a common driver In Figure 6 26 Clock Skew Example the common driver of the clock path is at the DCM If the tools can not find a common driver the analysis starts at the clock pads In ck path delay the timing analysis tool traces the clock path to a common driver In Figure 3 15 Hold Violation Clock Skew gt Data Path the clock path delay from the www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Clock Uncertainty DCM to the destination element is 0 860 0 860 0 639 2 359 and the clock path delay from the DCM to the source element is 0 852 0 860 0 639 2 351 The total clock skew is 2 359 2 351 0 008 ns FF_OF FF_90 Tiopi 0 825 clk20 net 0 639 net 0 852 gt clk20 net 0 860 clk20_9
58. timing name attribute The timing name attribute name is then used in a TIMESPEC or Timing Constraint An example is the clock net in following schematic is traced forward to the two flip flops in Figure 3 2 INM on the CLOCK pad or net traces downstream to the Flip Flops amp gt D ES OUT1 me ees D 5 oH ET OUT2 X11062 Figure 3 2 TNM on the CLOCK pad or net traces downstream to the Flip Flops Flagging a common input typically a clock signal or clock enable signal can be used to group flip flops latches or other synchronous elements The TNM is traced forward along the path through any number of gates buffers or combinatorial logic until it reaches a flip flop input latch or synchronous element Those elements are added to the specified TNM or time group Using TNM on a net that traces forward to create a group of flip flops is shown in Figure 3 3 TNM on the CLK net traced through combinatorial logic to synchronous elements flip flops IPAD IBUF A0 ANO TNM FLOPS pe O D D OBUF SUD Z D Q BITO IN O BITOO O FD Eo XNOR c gt Exa b IBUF IPAD BINO pm O B0 1 o LL uo em o OP rp Q arri BITO O 5 AND d gt Lo gt O p3 D OBUF D a BIT2 INO BITo2 o QPAD INV el gt Ex b GCLK IPAD p CLKIN gt CLK l O CLKN INV X11063 Figure 3 3 TNMon the CLK net traced through combinatorial logic to synchronous elements flip flops
59. to specify these constraints e Single Through Point e Single List of Through Points e Multiple Through Points e Multiple Lists of Through Points 104 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL You can also define these constraints in the appropriate SCOPE panels or in the Product of Sums POS interface When a port and a net have the same name preface the name of the through point with e n nets L t hierarchical ports e p top level ports For example n regs mem 2 or t dmux bdpol The n prefix must be specified to identify nets Otherwise the associated timing constraint is not be applied for valid nets Single Through Point You can specify a single through point define false path through regs mem 2 In this example the constraint is applied to any path that passes through e regs mem 2 Single List of Through Points If you specify a single list of through points the through option e Behaves as an OR function e Applies to any path that passes through any of the points in the list define path delay through regs mem 2 prgcntr pc 7 dmux alub 0 max 5 min 1 In this example the constraint is applied to any path through e regs mem 2 OR e prgentr pc 7 OR e dmuxalub 0 Multiple Through Points To specify multiple points for the same constraint precede each
60. uncer tainty Source IntA 1 FF Destination XorA 1 FF Requirement 8 000ns Data Path Delay 4 036ns Levels of Logic 1 Clock Path Skew 0 000ns Source Clock Clk0 rising at 0 000ns Destination Clock Clk0 rising at 8 000ns Clock Uncertainty 0 060ns Two Phase Clock Domain The analysis of a data path that uses both edges of the clock as in Figure 6 3 Two Phase Clock is known as a two phase clock The clock is driven by the same clock source which can be a PAD DCM DLL PLL PMCD component with only one output or DCM DLL PLL PMCD component with outputs that are 180 degrees out of phase CLKO and CLK180 or CLK90 and CLK270 but the design uses both edges of the clock The timing analysis tool does report the active edges of the clock driver and the corresponding time for the data path between the synchronous elements During analysis the requirement time is reduced by half the original requirement as shown in Figure 6 4 Relationship between Single Phase and Two Phase Clocks X11095 Figure 6 3 Two Phase Clock Since the timing report is sorted by the slack value the worst slack valued path is listed first in the report for each constraint Note When the worst slack value path does not match the Minimum Period value this is usually caused when the slack value on a two phase path is not the largest or worst slack value The corresponding path to the Minimum Period value is down in the list of paths for t
61. using the FROM TO constraint with the DATAPATHONLY keyword see FROM TO Multi Cycle Constraints in Chapter 3 Timing Constraint Principles Timing Constraints User Guide www xilinx com 19 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX Example Two unrelated clocks enter the FPGA device through separate external pins as shown in Figure 2 7 Two unrelated clocks entering the FPGA device through separate external pins e The first clock CLKA is the source clock e The second clock CLKB is the destination clock X11053 Figure 2 7 Two unrelated clocks entering the FPGA device through separate external pins The syntax for this example is NET CLKA TNM_NET FFS GRP_A NET CLKB TNM_NET FFS GRP_B TIMESPEC TS_Example FROM GRP_A TO GRP_B 5 ns DATAPATHONLY Output Timing Constraints 20 Output timing covers the data path from a register inside the FPGA device to the external pin of the FPGA device The OFFSET OUT constraint specifies the output timing The best way to specify the output timing requirements depends on the type source system syncronous and SDR DDR of the interface The OFFSET OUT constraint defines the maximum time allowed for data to be transmitted from the FPGA device The output delay path begins at the input clock pin of the FPGA device and continues through the output register to the data pins of the FPGA
62. valid at the data output port of the FPGA device In this system synchronous example the output data must become valid at least 5 ns after the input clock edge For this example the complete OFFSET OUT specification is NET ClkIn TNM NET ClkIn OFFSET OUT 5 ns AFTER ClkIn This global constraint covers both the data bits of the bus e datal e data2 Source Synchronous Outputs The source synchronous output interface is an interface in which a clock is regenerated and transmitted along with the data from the FPGA device The regenerated clock is transmitted along with the data The interface is primarily limited in performance by 22 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Output Timing Constraints system noise and the skew between the regenerated clock and the data bits as shown in Figure 2 11 Simplified Source Synchronous output interface with associated DDR timing In this interface the time from the input clock edge to the output data becoming valid is not as important as the skew between the output data bits In most cases it can be left unconstrained e a 1 1 i 1 CkOut l 1 1 Data 1 Rising Data Falling Data X11057 Figure 2 11 Simplified Source Synchronous output interface with associated DDR timing The global OFFSET OUT constraint is the most efficient way to specify the output timing for a source synchronous interface
63. zero ns based upon the PERIOD constraint e The second clock edge is one half the PERIOD constraint The timing report displays the Clock Arrival time for each edge of the clock In this example the clock arrival for the PERIOD LOW constraint is on the falling edge Therefore the clock arrival time for the falling edge synchronous elements is zero The rising edge synchronous elements are half the PERIOD constraint The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET OUT Constraints In Figure 6 19 Timing Diagram of Two Phase in OFFSET OUT Constraint the OFFSET requirement is three ns Constraint Syntax Example TIMESPEC TS_clock PERIOD clock 10 ns LOW 50 OFFSET IN 3 ns AFTER clock clk_in m P Sns data X11111 Figure 6 19 Timing Diagram of Two Phase in OFFSET OUT Constraint Timing Report Example Slack 0 865ns requirement clock arrival clock path data path uncertainty Source OutD_7 FF Destination OutD lt 7 gt PAD Source Clock clock3_std_bufg falling at 0 000ns Requirement 3 000ns Data Path Delay 3 405ns Levels of Logic 1 Clock Path Delay 0 280ns Levels of Logic 3 Clock Uncertainty 0 180ns Phase Shifted Example A DCM phase shifted CLK90 example of the OFFSET OUT constraint has the init
64. 000000 PHASE 5 000000 nS HIGH 50 000000 If the Iransformation Conditions are not met e The PERIOD constraint is not placed on the output or derived clocks of the clock modifying block component and e An error or warning message is reported in the NGDBuild report Error Message Example Following is an example of an error message ERROR NgdHelpers 702 The TNM PAD CLK drives the CLKIN pin of CLKDLL SI1 This TNM cannot be traced through the CLKDLL because it is not used in exactly one PERIOD specification This TNM is used in the following user groups and or specifications TS PAD CLK PERIOD PAD CLK 20000 000000 pS HIGH 50 000000 TS 01 FROM PAD CLK TO PADS 20000 000000 ps Timing Constraints User Guide www xilinx com 29 UG612 v 11 1 1 April 29 2009 30 Chapter 3 Timing Constraint Principles XILINX Note The original TIMESPEC PERIOD constraint is reported in the timing report and shows 0 items analyzed The newly created TIMESPEC PERIOD constraints contain all the paths associated with the clock modifying block component If the PERIOD constraint is not translated and then traces only to the clock modifying block component the timing report show 0 items analyzed No other PERIOD constraints are reported If the PERIOD constraint traces to other synchronous elements the analysis includes only those synchronous elements Synchronous Elements Synchronous elements include e Flip Fl
65. 0g net 0 639 TgiOo 0 860 Tdcmino 4 197 ud e 21118 Figure 6 26 Clock Skew Example Clock Uncertainty In addition to the Clock Skew affecting the margin on the PERIOD constraint requirement clock uncertainty also affects it Note Clock uncertainty is used to increase the timing accuracy by accounting for system board level and DCM clock jitter The SYSTEM_JITTER constraint and INPUT_JITTER keyword on the PERIOD constraint inform the timing analysis tools that the design has external jitter affecting the timing of this design as shown in Figure 6 27 Input Jitter on Clock Signal r Period 10 ns 7 Input Jitter 1 ns Figure 6 27 Input Jitter on Clock Signal X11119 During the analysis for Virtex 4 device families and newer the DCM Jitter DCM Phase Error and DCM Duty Cycle Distortion Jitter are also included in the clock uncertainty The individual components that make up clock uncertainty are reported in 9 1i and newer The timing analysis tools calculate the clock uncertainty for the source and destination of a data path and combine them together to form the total clock uncertainty The following is the equation for DCM Clock Uncertainty Clock Uncertainty V INPUT JITTER SYSTEM JITTER DCM Descrete Jitter 2 DCM Phase Error DCM Discrete Jitter and DCM Phase Error are provided in the speed files for Virtex 4 devices and newer Examples INPUT JITTER 200ps 40000ps
66. 11091 Paths Covered by FROM TO Constraints The FROM TO constraint defines a timing requirement between two time groups It is intended to be used in conjunction with the PERIOD and OFFSET IN OUT constraints and to define the fast and slow exceptions It is very versatile as shown in the following examples for a simple design in Figure 3 32 All paths constrained on a sample design TIMESPEC TS_C2S FROM FFS TO FFS 12 ns TIMESPEC TS_P2S FROM PADS TO FFS 10 ns TIMESPEC TS_P2P FROM PADS TO PADS 13 ns TIMESPEC TS_C2P FROM FFS TO PADS 8 ns TS_P28 EN TS_C2P O E OUT 1 cek gt 5 CO GO ape i TS_P2P X11092 Figure 3 32 All paths constrained on a sample design www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Timing Constraint Syntax When changing analysis from PERIOD to FROM TO the number of paths analyzed can be larger than when a path is covered with a PERIOD constraint but the number of Unconstrained Path does not increase The destination TIMEGRP for the FROM TO constraint probably contains distributed Dual Port Synchronous RAMs Paths to this RAM are both synchronous and asynchronous For example the path to the data input D is synchronous but the paths to the read address inputs DPRA are asynchronous A PERIOD constraint constrains only synchronous paths but a FROM TO constraint constrains both
67. 2 Timing Diagram of Simple OFFSET IN Constraint the OFFSET requirement is three ns before the initial clock edge The equation used in timing analysis is Slack Requirement Data Path Clock Path Clock Arrival Constraint Syntax Example TIMESPEC TS clock PERIOD clock grp 10 ns HIGH 50 OFFSET IN 3 ns BEFORE clock clock in mw l gt k 3 ns data X11104 Figure 6 12 Timing Diagram of Simple OFFSET IN Constraint Timing Report Example Slack 0 191ns requirement data path clock path clock arrival uncertainty Source reset PAD Destination my_oddrA_ODDR_inst FFO FF Destination Clock clock0_ddr_bufg rising at 0 000ns Requirement 3 000ns Data Path Delay 2 784ns Levels of Logic 1 Clock Path Delay 0 168ns Levels of Logic 3 Clock Uncertainty 0 239ns Two Phase Example A two phase or both clock edge example of the OFFSET IN constraint has an initial clock edge which correlates to the two edges of the clock e The first clock edge is zero ns based upon the PERIOD constraint e The second clock edge is one half the PERIOD constraint The timing report displays the Clock Arrival time for each edge of the clock The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold in the example report below In this example the PERIOD constraint has the clock arrival on the falling edge based upon the FALLING keyw
68. C 7 FF Requirement 4 000ns Data Path Delay 1 810ns Levels of Logic 0 Clock Path Skew 0 000ns Source Clock clkO rising at 0 000ns Destination Clock clkdv rising at 4 000ns Clock Uncertainty 0 281ns FROM TO Multi Cycle Constraints The analysis of the FROM TO multi cycle constraint includes the clock skew between the source and destination synchronous elements Clock skew is calculated based upon the clock path to the destination synchronous element minus the clock path to the source synchronous element The clock skew analysis is done automatically for all clocks being constrained The analysis includes setup analysis for all device families and setup and hold analysis on Virtex 5 devices and newer In order to ignore the clock skew in FROM TO constraints use the DATAPATHONLY keyword DATAPATHONLY indicates that the FROM TO constraint does not take clock skew or phase information into consideration during the analysis of the design This keyword results in only the data path between the group being considered and analyzed Setup paths are sorted by slacks based upon the following equation Tsu slack constraint requirement Tclock skew Tdata path Tsu The setup analysis of a FROM TO is done by default The hold analysis is reported for Virtex 5 devices and newer by default For older devices the environment variable XIL TIMING HOLDCHECKING YES must be set to enable the hold analysis 118 www xilinx com Timing Constra
69. Circuit Diagram with Calculation Variables for OFFSET OUT AFTER constraints The following equation defines this relationship Q TData20ut TClock lt Toffset OUT AFTER where TO Intrinsic Flip Flop Clock to Out TClock Total Clock path delay to the Flip Flop TData20ut Total Data path delay from the Flip Flop Toffset_OUT_AFTER Overall Clock to Out Requirement The analysis of this constraint involves ensuring that the maximum delay along the reference path CLK_SYS to COMP and the maximum delay along the data path COMP to Q_ OUT do not exceed the specified offset The OFFSET RISING FALLING keyword can be used to override the HIGH LOW keyword defined by the PERIOD constraint This is very useful for DDR design with a 50 duty cycle when the signal is capturing data on the rising and falling clock edges or producing data on a rising and falling clock edges For example if the PERIOD constraint is HIGH and the OFFSET constraint is FALLING the clock arrival time of the falling edged synchronous elements is set to zero Following is an example of OFFSET OUT set to RISING or FALLING TIMEGRP DATA_OUT OFFSET OUT 10 AFTER CLK FALLING TIMEGRP DATA_OUT OFFSET OUT 10 AFTER CLK RISING Simple Example A simple example of the OFFSET OUT constraint has the initial clock edge at zero ns based upon the PERIOD constraint The timing report displays the initial clock edge as the Clock Arriva
70. Data to be registered in the FPGA device ise available on the FPGA s input Pad some time period 2ns AFTER the reference clock edge is seen by the Upstream Device For the purposes of the OFFSET constraint syntax assume no skew on CLK between the chips The following equation defines this relationship TData TSetup TClock lt TPeriod Toffset_IN_AFTER where TSetup Intrinsic Flip Flop setup time TClock Total Clock path delay to the Flip Flop TData Total Data path delay from the Flip Flop TPeriod Single Cycle PERIOD Requirement Toffset_IN_AFTER Overall Setup Requirement A PERIOD or FREQUENCY constraint is required for OFFSET IN constraints with the AFTER keyword OFFSET OUT Constraints 128 This section discusses OFFSET OUT Constraints and includes e OFFSET OUT AFTER Constraints e OFFSET OUT BEFORE Constraints The OFFSET OUT constraint defines the Clock to Pad timing requirements The OFFSET OUT constraint is an external clock to data specification and takes into account the clock delay clock edge and DLL DCM introduced clock phase when analyzing the clock to out requirements Clock to Out clock_delay clock_to_out data_delay clock_arrival Clock arrival time takes into account any clock phase generated by the DLL DCM or clock edge If the timing report does not display a clock arrival time the timing analysis tools did not analyze a PERIOD constraint for that specific synchronous
71. ET overrides a global OFFSET specified for the same I O Net specific OFFSET overrides both global and group OFFSET if used This priority rule allows you to start with global OFFSETs and then to create group or net specific OFFSET constraint for I O with special timing requirements Note Use global and group OFFSET constraints to reduce memory usage and runtime Using wildcards in net specific OFFSET constraint creates multiple net specific OFFSET constraints not a group OFFSET constraint A group OFFSET constraint can include both a register group and a pad group Group OFFSET allows you to group pads or registers or both to use the same requirement The register group can be used to identify path source or destination that has different requirements from or to a single pad on a clock edge The pad group can be used to identify path sources or destinations that have different requirements from or to a group of pads on the same clock edge You can group and constrain the pads and registers all at once which is useful if a clock is used on the rising and falling edge for inputs and outputs The rising and falling groups require different group OFFSET constraints In Figure 3 21 OFFSET with different Time groups registers A B and C are different time groups TIMEGRP AB RISING FFS TIMEGRP C FALLING FFS even though these registers have the same data and clock source This allows you to perform two different timing analyses for these r
72. Example for OFFSET IN 3 ns BEFORE clock RISING Slack 0 101ns requirement data path clock path clock arrival uncertainty Source DataA lt 3 gt PAD Destination TmpAa_3 FF Destination Clock clock0_ddr_bufg rising at 0 000ns Requirement 3 000ns Data Path Delay 2 654ns Levels of Logic 2 Clock Path Delay 0 006ns Levels of Logic 3 Clock Uncertainty 0 239ns Timing Report Example for OFFSET IN 3 ns BEFORE clock FALLING Slack 0 101ns requirement data path clock path clock arrival uncertainty Source DataA lt 3 gt PAD Destination TmpAa_3 FF Destination Clock clock0 ddr bufg falling at 0 000ns Requirement 3 000ns Data Path Delay 2 654ns Levels of Logic 2 Clock Path Delay 0 006ns Levels of Logic 3 Clock Uncertainty 0 239ns Timing Constraints User Guide www xilinx com 127 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX OFFSET IN AFTER Constraints The OFFSET IN AFTER constraint describes the time used by the data external to the FPGA device OFFSET IN subtracts this time from the PERIOD declared for the clock to determine the time available for the data to propagate from the pad to the setup at the synchronous element You can visualize this time as the difference of data arriving at the edge of the device after the current clock edge arrives at the edge of the device This OFFSET IN 2 ns AFTER clock_pad constraint reads that the
73. G612 v 11 1 1 April 29 2009 XILINX Timing Constraints PERIOD Constraints This section discusses PERIOD Constraints and includes About PERIOD Constraints Related TIMESPEC PERIOD Constraints Paths Covered by PERIOD Constraints About PERIOD Constraints The PERIOD Clock Period Specification constraint is a fundamental timing and synthesis constraint PERIOD constraints Define each clock within the design Cover all synchronous paths within each clock domain Cross checks clock domain paths between related clock domains Define the duration of the clock Can be configured to have different duty cycles The PERIOD constraint is preferred over FROM TO constraints because the PERIOD constraint covers a majority of the paths and decreases the runtime of the implementation tools The Clock Period Specification defines The timing between synchronous elements FFS RAMS LATCHES HSIOs CPUs DSPS and PADS clocked by a specific clock net that is terminated at a registered clock pin as shown in Figure 3 10 PERIOD Constraints Covering Register to Register Paths The timing between related clock domains based upon the destination clock domain FLOP 77 9 p opo 7E 9 ni ops ADATA d M B CK BUFG FLOP4 di B FLOP5 CDATA X11070 Figure 3 10 PERIOD Constraints Covering Register to Register Paths The PERIOD constraint on a clock net
74. IOD Constraint Through DCM Table 3 1 Transformation of PERIOD Constraint Through DCM Output Pin PERIOD Value PHASE Shift value ICIKO TSCIKIN 1 Noe CLK90 TS CLKIN 1 PHASE clk0 period 1 4 CLK180 TS CLKIN 1 PHASE clk0_period Y CLK270 TS_CLKIN 1 PHASE clk0_period 34 CLK2x TS_CLKIN 2 None CLK2x180 TS_CLKIN 2 PHASE clk2x period Y CLKDV TS_CLKIN clkdv_divide None clkdv_divide value of CLKDV_DIVIDE property default 2 0 Timing Constraints User Guide www xilinx com 31 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX 32 Table 3 1 Transformation of PERIOD Constraint Through DCM Cont d CLKFX TS_CLKIN clkfx_factor None clkfx_factor value of CLKFX_MULTIPLY property default 4 0 divided by value of CLKFX_DIVIDE property default 1 0 CLKFX180 TS_CLKIN clkfx_factor PHASE clkfx_period Ya clkfx_factor value of CLKFX MULTIPLY property default 4 0 divided by value of CLKFX_DIVIDE property default 1 0 Timing Group Creation with TNM TNM_NET Attributes This section discusses Timing Group Creation with TNM TNM_NET Attributes and includes e About Timing Group Creation with TNM TNM_NET Attributes e Net Connectivity NET e Predefined Time Groups e Propagation Rules for TNM NET e Instance or Hierarchy e Instance Pin
75. In the DDR interface one OFFSET OUT constraint is defined for each edge of the output interface clock These constraints cover the paths of all output data bits that are transmitted by registers triggered with the specified output clock edge To specify the input timing e Define a time name INM for the output clock to create a time group which contains all output registers triggered by the output clock e Define the global OFFSET OUT constraint for the rising edge RISING of the interface e Define the global OFFSET OUT constraint for the falling edge FALLING of the interface Example A timing diagram for an ideal Source Synchronous DDR interface is shown in Figure 2 12 Timing diagram for an ideal Source Synchronous DDR The interface has a clock period of 5 ns with a 50 50 duty cycle The data for both bits of the bus remains valid for the entire period Timing Constraints User Guide www xilinx com 23 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX 1 I4 PERIOD 5ns 3 I SysClk OFFSET IN OFFSET IN f y 1 25ns 1 25ns 1 l VALID 2 5 ns gt VALID 2 5 ns e X11058 Figure 2 12 Timing diagram for an ideal Source Synchronous DDR In the OFFSET OUT constraint OFFSET 0UT lt value gt determines the maximum time from the rising clock edge at the input clock port until the data first becomes v
76. NABLE REG SR R for recovery time and ENABLE REG SR O for output time These path tracing controls enable the path from the asynchronous reset pin through the synchronous element and the reset recovery time of the synchronous element 138 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009
77. NX Following is an example of the OFFSET IN with the VALID keyword TIMEGRP DATA_IN OFFSET IN TIMEGRP DATA_IN OFFSET IN VALID 3 BEFORE CLK RISING VALID 3 BEFORE CLK FALLING 1 1 OFFSETIN BEFORE DataExt cos ow i I I I 1 l VALID Data I I I I Le VALID Duration CIkExt X11103 Figure 6 11 OFFSET IN Constraint with VALID Keyword The OFFSET Constraint is analyzed with respect to the rising clock edge which is specified with the HIGH keyword of the PERIOD constraint Set the OFFSET constraint to RISING or FALLING to override the HIGH or LOW setting defined by the PERIOD constraint This is extremely useful for DDR design with a 50 percent duty cycle when the signal is capturing data on the rising and falling clock edges or producing data on rising and falling clock edges For example if the PERIOD constraint is set to HIGH and the OFFSET constraint is set to FALLING the falling edged synchronous elements have the clock arrival time set to zero Following is an example of the OFFSET IN constraint set to RISING and FALLING TIMEGRP DATA_IN OFFSET IN 1 VALID 3 BEFORE CLK FALLING TIMEGRP DATA_IN OFFSET IN 1 VALID 3 BEFORE CLK RISING The equation for external setup included in the OFFSET IN analysis of the FPGA device is External Setup Data Delay Flip Flop Setup time Prorated ver
78. O falling at 3 000ns Clock Uncertainty 0 060ns Multiple Clock Domains A cross clock domain path is a path that has two different clocks for the source and destination synchronous elements One clock drives the source and a different clock drives the destination If the source clock PERIOD constraint is related to the destination clock PERIOD constraint the destination clock PERIOD constraint covers the cross clock domain analysis Xilinx recommends relating the clocks via PERIOD constraints so that the analysis properly includes the cross clock domain paths If the clocks are not related the cross clock domain paths are not analyzed Xilinx recommends using a FROM TO or multicycle constraint to either flag it as a false path or multi cycle path Clocks from DCM outputs Since the clock signals produced by a DCM DLL PLL PMCD are related to each other the PERIOD constraints should also be related This can be done in one of two ways e Allow NGDBuild to create new PERIOD constraints based upon the input clock signal PERDIOD constraint 114 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 PERIOD Constraints e Manually create PERIOD constraints based upon the output clock signals of the DCM DLL PLL PMCD and manually relate the PERIOD constraints ClkO Clock Domain Since the clocks produced by the DCM PLL DLL PMCD are related the timing tools take this relationship into consideration during analysi
79. SPEC TS_C1k2X180 PERIOD C1k2X180 TS_C1k1X 2 PHASE 1 25 ns Asynchronous Clock Domains Asynchronous clock domains are those in which the source and destination clocks do not have a frequency or phase relationship Since the clocks are not related it is not possible to determine the final relationship for setup and hold time analysis For this reason Xilinx recommends that you use proper asynchronous design techniques to ensure the successful capture of data One example of proper asynchronous design technique is to use a FIFO design element to capture and transfer data between asynchronous clock domains While not required in some cases you may wish to constrain the maximum data path delay in isolation without regard to clock path frequency or phase relationship The Xilinx constraints system allows you to constrain the maximum data path delay without regard to source and destination clock frequency and phase relationship This requirement is specified using the FROM TO constraint with the DATAPATHONLY keyword To constrain of the maximum data path delay without regard to source and destination clock frequency and phase relationship e Define a time group for the source synchronous elements e Define a time group for the destination synchronous elements e Define the maximum delay of the data paths using the FROM TO constraint between the two time groups with DATAPATHONLY keyword For more information on
80. T attributes are considered a timing group For more information about TNM and TNM_NET attributes see Constraint System Timing Constraints User Guide www xilinx com 41 UG612 v 11 1 1 April 29 2009 42 Chapter 3 Timing Constraint Principles XILINX The TIMEGRP attribute is to combine existing time groups pre defined or user defined together or remove common elements from existing time groups and create a new user defined time group The TIMEGRP attribute is also a method for creating a new time group by pattern matching grouping a set of objects that all have output nets that begin with a given string Use the following keywords to create subsets of an existing time group e Rising edge synchronous elements RISING e Falling edge synchronous elements FALLING e Remove common elements EXCEPT Use the EXCEPT keyword with a TIMEGRP attribute to remove elements from an already created time group The overlapping items to be removed from the original time group must be in the excluded or EXCEPT time group If the excluded time group does not overlap with the original time group none of the design elements are removed In that case the new time group contains the same elements as the original time group In addition to using TIMEGRP to include multiple time groups or exclude multiple time groups it also can be used to create sub groups using the RISING and FALLING keywords Use RISING and FALLING to create groups ba
81. TNM TNM DO CE IDDR INST gen dq u iob dqg gen stg2 u iddr dq TNM TNM DQS FLOPS TIMESPEC TS DQ CE FROM TNM DQ CE IDDR TO TNM DQS FLOPS 1 60 ns This requirement is based upon a system clock of 333 MHz OFFSET IN Constraints This section discusses OFFSET IN Constraints and includes e OFFSET IN BEFORE Constraints e OFFSET IN AFTER Constraints The OFFSET IN constraint defines the Pad To Setup timing requirement OFFSET IN is an external clock to data relationship specification It takes into account the clock delay clock edge and DLL DCM introduced clock phase when analyzing the setup requirement data_delay setup clock_delay clock_arrival Clock arrival takes into account any clock phase generated by the DLL DCM or clock edge Note If the timing report does not display a clock arrival time for an OFFSET constraint then the timing analysis tools did not analyze a PERIOD constraint for that specific synchronous element When you create pad to setup requirements make sure to incorporate any phase or PERIOD adjustment factor into the value specified for an OFFSET IN constraint For the following example see the schematic in Figure 3 3 INM on the CLK net traced through combinatorial logic to synchronous elements flip flops If the net from the CLK90 pin of the DLL DCM clocks a register then the OFFSET value should be adjusted by one quarter of the PERIOD constraint value For exampl
82. TNM_NET is placed on If the TNM_NET is on a NET the name_qualifier is a net name If the TNM_NET is an instance INST the name_qualifier is an instance name identifier can be any combination of letters numbers or underscores The identifier cannot be any the following reserved words FFS RAMS LATCHES PADS CPUS HSIOS MULTS RISING FALLING TRANSHI TRANSLO or EXCEPT XST supports TNM_NET with the limitation that only a single pattern is supported for predefined groups Table 4 1 TNM NET Support Limitations Supported NET PADCLK TNM_NET FFS GRP1 Not supported NET PADCLK TNM NET FFS machine xcounter TG1 f Timing Name Net TNM_NET XCF Syntax Example NET clk TNM_NET FFS my_flop Grpl INST clk TNM_NET FFS my_macro Grp2 Timing Constraints User Guide www xilinx com 77 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST 78 www xilinx com XILINX Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Chapter 5 Specifying Timing Constraints in Synplify This chapter discusses how to specify timing constraints in e Hardware Description Language HDL code e An SDC Tel file e ASCOPE spreadsheet For information on how to specify timing constraints for the Xilinx Synthesis Tool XST see Chapter 4 Specifying Timing Constraints in XST The sections below give syntax examples for ind
83. Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR
84. a FROM THRU TO constraint NET 3M17 On the Way TPTHRU abc TIMESPEC TS mypath FROM my src grp THRU abc TO my dest grp 9 ns Constrain from time group my src grp through thru group abc to the time group my dest grp tobe9ns Themy src grpconstrains the FIFO shown in Figure 3 28 NET TPTHRU example with previous FROM THRU TO constraint example 58 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Timing Constraints The my_dest_grp constrains the registers shown in Figure 3 28 NET TPTHRU example with previous FROM THRU TO constraint example MY_REG_O MYFIFO MY_REG_1 MY_REG_2 X11088 Figure 3 28 NET TPTHRU example with previous FROM THRU TO constraint example False Paths or Timing Ignore TIG Constraint A NET TIG constraint covers a specific net and marks nets that are to be ignored for timing analysis purposes A FROM TO TIG covers several paths between two synchronous groups or pad groups and marks all the nets going between the synchronous groups that are to be ignored for timing analysis purposes An example is shown in Figure 3 29 Timing Ignore on a path between two flip flops NETA NET C Ignored Paths X11089 Figure 3 29 Timing Ignore on a path between two flip flops You can also use the FROM THRU TO constraint to define a non synchronous path such as using a common bus for several modules The timing analysis constrains between these
85. a clock period of 40 ns to the net named CLOCK with the first pulse being HIGH and having duration of 25 nanoseconds NET CLOCK PERIOD 40 HIGH 25 The following statement assigns a clock period of 5 ns in the style of TIMESPEC NET infrastructure0 SYS CLK IN TNM NET SYS CLK TIMESPEC TS SYS CLK PERIOD SYS CLK 5 ns HIGH 50 System Jitter SYSTEM JITTER System Jitter SYSTEM JITTER specifies the system jitter of the design System Jitter SYSTEM JITTER depends on various design conditions such as the number of flip flops changing at one time and the number of I Os changing System Jitter SYSTEM JITTER applies to all clocks within a design System Jitter SYSTEM JITTER can be combined with the INPUT JITTER keyword on the PERIOD constraint to generate the Clock Uncertainty value shown in the timing report For more information see Chapter 3 Timing Constraint Principles System Jitter SYSTEM JITTER VHDL Syntax attribute SYSTEM JITTER string attribute SYSTEM JITTER of component name signal name entity name label name component signal entity label is value ps where System System value is a numerical value The default is ps Jitter SYSTEM JITTER VHDL Syntax Example entity top yann mem is port ecntrl0 DDR2 DO inout std logic vector 71 downto 0 SYS CLK P in std logic SYS CLK N in std logic CLK200 P in std logic CLK200 N in st
86. al case in which a path between two registers is clocked by a common clock enable signal In this example the clock enable is toggled at a rate that is one half of the reference clock CLK1 5 Enable X11060 Figure 2 14 Path between two registers clocked by a common clock enable signal The generic syntax for defining a multi cycle path between time groups is TIMESPEC TSid FROM MC GRP TO MC GRP value In the FROM TO multi cycle example the MC GRP defines the set of registers which are driven by a common clock enable signal All paths that begin in the MC GRP and end in the MC GRP have the multi cycle timing requirement applied to them Paths into and out of the MC GRP are analyzed with the appropriate PERIOD specification The specific syntax for this example is NET CLK1 TNM NET CLK1 TIMESPEC TS CLK1 PERIOD CLK1 5 ns HIGH 50 NET Enable TNM NET FFS MC GRP TIMESPEC TS Example FROM MC GRP TO MC GRP TS CLK1 2 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Chapter 3 Timing Constraint Principles This chapter Discusses the fundamentals of timing constraints including PERIOD Constraints OFFSET Constraints FROM TO Multi Cycle Constraints Discusses the ability to group elements in order to provide a better understanding of the constraint system
87. alid at the data output port of the FPGA device When lt value gt is omitted from the OFFSET OUT constraint the constraint becomes a report only specification which reports the skew of the output bus The REFERENCE_PIN keyword defines the regenerated output clock as the reference point against which the skew of the output data pins is reported For this example the complete OFFSET OUT specification for both the rising and falling clock edges is NET CLkIn TNM NET ClkIn OFFSET OUT AFTER ClkIn REFERENCE PIN ClkOut RISING OFFSET OUT AFTER ClkIn REFERENCE PIN ClkOut FALLING Timing Exceptions 24 Using the global definitions of the input register to register and output timing constraints properly constrains the majority of the paths In certain cases a small number of paths contain exceptions to the global constraint rules The most common types of exceptions are e False Paths e Multi Cycle Paths False Paths In some cases you may want to remove a set of paths from timing analysis if you are sure that these paths do not affect timing performance One common way to specify the set of paths to be removed from timing analysis is to use the FROM TO constraint with the timing ignore TIG keyword This allows you to e Specify a set of registers in a source time group e Specify a set of registers in a destination time group e Automatically remove all paths between those t
88. ances you cannot refer to more than one bit of that vector define reg input delay Thedefine reg input delay constraint speeds up paths feeding a register by a given number of nanoseconds The synthesis tool attempts to meet the global clock frequency goals for a design as well as the individual clock frequency goals set with define clock Use this constraint to speed up the paths feeding a register define reg input delay Syntax define reg input delay registerName route ns comment textString where e registerName is asinglebit an entire bus or e aslice of a bus e route is an advanced user option to tighten constraints during resynthesis You can use route when the place and route timing report shows the timing goal is not met because of long paths to the register define_reg_output_delay The define_reg_output_delay constraint speeds up paths coming from a register by a given number of nanoseconds The synthesis tool attempts to meet the global clock frequency goals for a design as well as the individual clock frequency goals set with define_clock Use this constraint to speed up the paths coming from a register define_reg_output_delay Syntax define_reg_output_delay registerName route ns comment textString where e registerName is Asingle bit An entire bus or A slice of a bus Timing Constraints User Guide www xilinx com 103 UG612 v 11 1 1 April 29 2009 Chapter 5 Spe
89. arrival uncertainty Source DataD 9 PAD Destination TmpAa 1 FF Destination Clock clocki1 fixed bufg rising at 4 500ns Requirement 3 000ns Data Path Delay 2 492ns Levels of Logic 2 Clock Path Delay 0 038ns Levels of Logic 3 Clock Uncertainty 0 239ns Dual Data Rate Example A Dual Data Rate example of the OFFSET IN constraint has an initial clock edge at zero ns and half the PERIOD constraint which correlates to the two clock edges The timing report displays the Clock Arrival time for each edge of the clock Since the timing analysis tools do not automatically adjust any of the clock phases during analysis the constraints must be manually adjusted for each clock edge The timing analysis tools offer two options to manage the falling edge Clock Arrival time The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold in the example report below Option One The first option is to create two time groups one for rising edge synchronous elements and the second for the falling edge synchronous elements Then create an OFFSET IN constraint for each time group the second OFFSET IN constraint has a different requirement The falling edge OFFSET IN constraint requirement equals the original requirement minus one half the PERIOD constraint Therefore if the original requirement is 3 ns with a PERIOD of 10 ns the falling edge OFFSET IN constraint requirement is 2 ns
90. ated with a PERIOD constraint TNM_NET propagates forward through the clock modifying block to synchronous elements or pads PADCLK D INTCLK bc IPAD IBUF X11064 Figure 3 4 Differences between TNM and TNM NET In the design shown in Figure 3 4 Differences between TNM and TNM NET a TNM associated with the IPAD signal includes only the PAD symbol as the member of a time group A TNM NET associated with the IPAD signal includes all the synchronous elements after the IBUF as members of a time group Following are examples of different ways to create time groups using the IPAD signal e NET PADCLK TNM PAD grp Use the padc1k net to define the time group PAD grp Contains the IPAD element e NET PADCLK TNM FFS FF grp Use the padc1k net to define the time group FF grp Contains no flip flop elements e NET PADCLK TNM NET FFS FF2 grp Timing Constraints User Guide www xilinx com 35 UG612 v 11 1 1 April 29 2009 36 Chapter 3 Timing Constraint Principles XILINX Use the padc1k net to define the time group FF2_grp Contains all flip flop elements associated with this net In the design shown in Figure 3 4 Differences between TNM and TNM_NET a TNM associated with the IBUF output signal can only include the synchronous elements after the IBUF as members of a time group Following are examples of time groups that use only the IBUF output signal e NET INTCLK TNM FFS FF1_grp Use the intcl
91. ay 0 168ns Levels of Logic 3 Clock Uncertainty 0 239ns Fixed Phase Shifted Example A DCM fixed phase shifted clock example of the OFFSET IN constraint has an initial clock edge at zero ns based upon the PERIOD constraint Since the clock is phase shifted by the DCM the timing report displays the Clock Arrival time as the phase shifted amount If the CLKO output is phase shifted by a user specified amount then the phase shifted amount is a percentage of the PERIOD In the following example the PERIOD constraint has the initial clock arrival on the rising edge but the clock arrival value is at the fixed phase shifted amount as seen in the example timing report The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold in the example report below In Figure 6 15 Timing Diagram of Fixed Phase Shifted Clock in OFFSET IN Constraint the OFFSET requirement is three ns before the initial clock edge Timing Constraints User Guide www xilinx com 125 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET IN 3 ns BEFORE clock clock_in T 0 al Lm E Sns clk90 data X11107 Figure 6 15 Timing Diagram of Fixed Phase Shifted Clock in OFFSET IN Constraint Timing Report Example Slack 4 269ns requirement data path clock path clock
92. cifying Timing Constraints in Synplify XILINX e route is an advanced user option to tighten constraints during resynthesis You can use route when the place and route timing report shows the timing goal is not met because of long paths to the register Specify From To Through Points This section discusses e From To Points e Through Points e Clocks as From To Points From To Points From specifies the starting point for the timing exception To specifies the ending point for the timing exception See Table 5 2 Objects That Can Serve as Starting and Ending Points Table 5 2 Objects That Can Serve as Starting and Ending Points From Points To Point Clocks Clocks Registers Registers Top level input or bi directional ports Top level output or bi directional ports Instantiated library primitive cells gate cells Black box outputs Black box inputs You can specify multiple from points in a single exception This is most common when specifying exceptions that apply to all the bits of a bus For example you can specify constraints From A 0 15 to B Inthis case there is an exception starting at any of the bits of A and ending on B Similarly you can specify multiple to points in a single exception and specify both multiple starting points and multiple ending points such as From A 0 15 to B 0 15 Through Points Although through points are limited to nets there are many ways
93. clock This application of the OFFSET IN constraint is called the global method It is the most efficient way to specify input timing System Synchronous Inputs In a system synchronous interface a common system clock both transfers and captures the data This interface uses a common system clock The board trace delays and clock skew limit the operating frequency of the interface The lower frequency also results in the system synchronous input interface typically being an SDR application In the system synchronous SDR application example shown in Figure 2 1 Simplified System Synchronous interface with associated SDR timing the data is transmitted from the source device on one rising clock edge and captured in the FPGA device on the next rising clock edge Source Device Transmit Capture Edge Edge 1 l System Clock l 1 i System Clock X11047 Figure 2 1 Simplified System Synchronous interface with associated SDR timing The global OFFSET IN constraint is the most efficient way to specify the input timing for a system synchronous interface In this method one OFFSET IN constraint is defined for each system synchronous input interface clock This single constraint covers the paths of Timing Constraints User Guide www xilinx com 13 UG612 v 11 1 1 April 29 2009 14 Chapter 2 Timing Constraint Methodology XILINX all input data bits that are captured in synchronous elements triggered by the specified
94. clock _en Verilog Syntax Example nannu nunun cece 84 syn gatedclk clock en VHDL Syntax ls nen 84 syn gatedclk clock en VHDL Syntax Example lesen 84 syn_gatedclk_clock_en_polarity 0 or 85 syn gatedclk clock en polarity Verilog Syntax 0 6 6 ccc ec eee eee 85 syn gatedclk clock en polarity Verilog Syntax Example llle 85 syn gatedclk clock en polarity VHDL Syntax esee 85 syn gatedclk clock en polarity VHDL Syntax Example llle 85 syn isclock issues cbe Ret Pen dt Pace dis 86 syn_isclock Verilog Syntax celeb cate e REIP REDE d eae a 86 syn isclock Verilog Syntax Example cl ne 86 syn isclock VADE Syntax iva dai ad Eee 86 syn isclock VHDL Syntax Example lesse ne 86 SO oe DER bes eet 87 syn tpdn Verilog Syhtax sanis ai etx e eet in in cia 87 syn tpdn Verilog Syntax Example 0 ccc ne 87 syn tpdn VHDE Synt x veaa dE A A AR it eet re 87 syn tpdn VHDL Syntax Examples sessa esera srami rinii siaa skaai eia eeka a 87 sde Tile Syntax tds hE pio ative eds dore EE EE EE bp EEE E oa ied 88 sde File Syntax example viii lts aia 88 SODA AA A A ad AA eas 88 syh _tcon Verilog Syntax citar da ca pr teehee tee a a 89 syn_tcon Verilog Syntax Example 0 6 00 ccc cece ne 89 s n teon VHDE Syntax sessir eyot nenia beac bee dees eee Ae Veet Yaa 89 syn_tcon VHDL Syntax Examples ocoococccooccoccoccon nen 89 syn tconsde File Syntax 20ccsessis
95. constraints This situation can occur when two clock signals from the DCM drive the same BUFGMUX as shown in Figure 3 9 PRIORITY with a BUFGMUX component CLKO 100 Mhz Frequency X11069 Figure 3 9 PRIORITY with a BUFGMUX component Following are examples of a PERIOD constraint using the PRIORITY keyword TIMESPEC TS Clk0 PERIOD clk0 grp 10 ns HIGH 50 PRIORITY 2 TIMESPEC TS Clk2X PERIOD clk2x grp TS_C1k0 2 PRIORITY 1 Timing Constraints User Guide www xilinx com 45 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX Timing Constraints 46 This section discusses Timing Constraints and includes e About Timing Constraints e PERIOD Constraints e OFFSET Constraints e EROM TO Multi Cycle Constraints About Timing Constraints Timing constraints provide a basis for the design of timing goals This is done with global timing constraints that set timing requirements that cover all constrainable paths Creating global constraints for a design is the easiest way to provide coverage of constrainable connections in a design and to guide the implementation tools to meeting timing requirements for all paths Global constraints constrain the entire design Following are the fundamental timing constraints needed for every design e Clock definitions with a PERIOD constraint for each clock Constrains synchronous element to synchronous
96. crae r Wu nena nEn n 105 Multiple Through POS 0420 A ee dare pas 105 Multiple Lists of Through Points 0 6 cece eens 106 Clocks as From To Points 0 000000 ccc cee RR s 106 Clocks as From To Points Syntax 0 0 nn 106 Multi Cycle Path Clock Points doce dies Peed iS bees pde b ter 107 False Path Clock Bolnts 2c Rer RR sehen er ADR ERA i Rei d 107 Path Delay Clock Pots i e ds esee E va e pda 107 Specifying Timing Constraints in a SCOPE Spreadsheet 108 Forward Amnotati0M 000 cence tenn nee nns 108 I O Timing Constraints 6 6 iiaii aaa a ei a 108 Clock Groups tacete piik pie eeatt ot er qoe here e Re POR e ia gato 108 Relaxing Forward Annotated I O Constraints 109 Digital Clock Manager Delay Locked Loop 6 6 60 cece cence eee 109 Chapter 6 Timing Constraint Analysis PERIOD Constraints o 111 Gated Clocks io eren E aede edat e rates 111 Single Clock Domain epairen nitrato UI ep Ue EU eben hebt used ege a 112 Two Phase Clock Domain sseeeeeeee ete tenn ene 113 Multiple Clock Domains serei ep eepe i K a ee pe aae R E A E E EE 114 Clocks from DCM outputs ee erennere pei een E E 114 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 ClkO Clock DOMAIN coso rta tia da E 115 CIK90 Clock Domain o 115 CIK2x Clock Domiait 5i dd Ye ek OMe 117 CLKDV CLKFX Clock Domain o 117 FROM TO Multi Cycle Constraints 00 0
97. d 1 25 ns prior to the falling clock edge In the OFFSET IN constraint the VALID lt value gt determines the duration in which data remains valid In this example both the rising and falling data remains valid for 2 5 ns For this example the complete OFFSET IN specification with associated PERIOD constraint is NET SysCLk TNM_NET SysClk TIMESPEC TS_SysClk PERIOD SysClk 5 ns HIGH 503 OFFSET IN 1 25 ns VALID 2 5 ns BEFORE SysClk RISING OFFSET IN 1 25 ns VALID 2 5 ns BEFORE SysClk FALLING This global constraint covers both the data bits of the bus e datal e data2 Register To Register Timing Constraints 16 This section discusses Register To Register Timing Constraints and includes e About Register To Register Timing Constraints e Automatically Related Synchronous DCM PLL Clock Domains e Manually Related Synchronous Clock Domains e Asynchronous Clock Domains About Register To Register Timing Constraints Register to register or synchronous element to synchronous element path constraints cover the synchronous data paths between internal registers The PERIOD constraint e Defines the timing requirements of the clock domains e Analyzes the paths within a single clock domain e Analyzes all paths between related clock domains e Takes into account all frequency phase and uncertainty differences between the clock domains during analysis For more
98. d logic Jur attribute SYSTEM JITTER string attribute SYSTEM JITTER of top yann mem entity is 10 ps end entity Jitter SYSTEM JITTER Verilog Syntax SYSTEM JITTER value ps where 72 value is a numerical value The default is ps www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX XST Timing Constraints System Jitter SYSTEM_JITTER Verilog Syntax Example module mig_22 inout 7 0 cntrl10_ddr2_dq output 14 0 cntr10 ddr2 a input SyS Clk p input Sys clk n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntrl0_ddr2_dqs La SYSTEM_JITTER 10 ps wire clk 0 The clk 0 is assigned with system jitter of 10 ps wire clk 90 wire clk 200 wire read en reg sys rst source code End module System Jitter SYSTEM JITTER XCF Syntax MODEL entity name SYSTEM JITTER value ps System Jitter SYSTEM JITTER XCF Syntax Example MODEL top vann mem SYSTEM JITTER 10 Timing Ignore TIG Note Timing Ignore TIG applies to FPGA devices only Timing Ignore TIG does not apply to CPLD devices Timing Ignore TIG is a basic timing constraint and a synthesis constraint Timing Ignore TIG causes paths that fan forward from the point of application of TIG to be treated as if they do not exist for the purposes of the timing model during implementation For more information
99. define_io_standard Syntax define io standard disable enable objectName delay type input delay output delay columnTclName value columnTclName value where e delay type is either input_delay or output_delay define_io_standard Syntax Example define_io_standard DATA1 7 0 delay_type input_delay syn_pad_type LVCMOS_33 syn_io_slew high syn_io_drive 12 syn_io_termination pulldown www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL define_multicycle_path The define multicycle path constraint Specifies a path that is a timing exception because it uses multiple clock cycles Provides extra clock cycles to the designated paths for timing analysis and optimization define_multicycle_path Syntax define multicycle path start end from startPoint to endPoint through throughPoint clockCycles comment textString where e start end specifies the clock cycles to use for paths with different start and end clocks This option determines the clock period to use as the multiplicand in the calculation for clock distance If you do not specify a start or end option the end clock is the default e from specifies the start point for the multi cycle timing exception The rom point defines a timing start point It can be any of the following Clocks c Registers i Top level input or bi directional po
100. design information the exact UCF syntax for each design element and constraint isused by the implementation tools The Constraints Editor allows you to create timing groups and timing constraints for the design The clocks and IOs are supplied so the exact spelling of the names is not needed You only need to define the timing requirements and not the syntax of the constraints When creating specific time groups element names are provided and exceptions to the global constraints can be made using those groups Since the Constraints Editor does not create time groups or constraints with wildcards you must manually modify the UCF to condense the size of the time groups The condensing of the size of the time groups in the UCF is done with wildcards on the unique portions of the design element and the common portion remains Timing Constraints User Guide www xilinx com 61 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX Following is an example of condensed time groups INST my_bus TNM my_output_bus_grp The asterisk wildcard causes the constraint system to apply the TNM attribute to all instances with the base name my_bus 62 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Chapter 4 Specifying Timing Constraints in XST This chapter discusses how to specify timing constraints in the Xilinx Synthesis Tool XST either in Hardware Description La
101. domains and automatically perform an analysis for any paths between these clock domains Example The circuit of an input clock driving a DCM is shown inFigure 2 5 The input clock of the design goes to a DCM example I 1 LL PERIOD 5ns 3 1 Y a a OFFSET IN OFFSET IN I li 1 i 1 25ns S125 ns li I 1 I VALID 2 5 ns gt VALID 2 5 ns X11050 Figure 2 5 The input clock of the design goes to a DCM example The PERIOD constraint syntax for this example is NET ClockName TNM NET TNM NET Name TIMESPEC TS name PERIOD TNM NET Name PeriodValue HIGH HighValue In the PERIOD constraint the PeriodValue defines the duration of the clock period In this case the input clock to the DCM has a period of 5 ns The HighValue of the PERIOD constraint defines the percent of the clock waveform that is HIGH In this example the waveform has a 50 50 duty cycle resulting ina HighValue of 50 The syntax for this example is NET ClkIn TNM NET ClkIn TIMESPEC TS ClkIn PERIOD ClkIn 5 ns HIGH 50 Timing Constraints User Guide www xilinx com 17 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX Based on the input clock PERIOD constraint given above the DCM automatically e Creates two output clock constraints for the DCM outputs e Performs analysis between the two domains
102. e the PERIOD constraint value is 20 ns and is from the CLK90 of the DCM the OFFSET IN value should be adjusted by an additional 5 ns e Original Constraint NET PAD IN OFFSET IN 10 BEFORE PADCLKIN e Modified Constraint NET PAD_IN OFFSET IN 15 BEFORE PADCLKIN Note The clock net name required for OFFSET constraints is the clock net name attached to the IPAD In above example the clock pad is PADCLKIN not CLK90 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET IN Constraints OFFSET IN BEFORE Constraints The OFFSET IN BEFORE constraint defines the time available for data to propagate from the pad and setup at the synchronous element as shown in Figure 6 10 Circuit Diagram with Calculation Variables for OFFSET IN BEFORE constraints You can visualize this as the time that the data arrives at the edge of the device before the next clock edge arrives at the device This OFFSET IN 2 ns BEFORE clock_pad constraint reads that the data is valid at the input data pad some time period 2 ns BEFORE the reference clock edge arrives at the clock pad The tools automatically calculate and control internal data and clock delays to meet the flip flop setup time T_DATA_IN T_CLK_IN OFFSET IN X11102 Figure 6 10 Circuit Diagram with Calculation Variables for OFFSET IN BEFORE constraints The following equation defines the set
103. e Document Timing Constraints User Guide www xilinx com 3 UG612 v 11 1 1 April 29 2009 Typographical Preface About the Timing Constraints User Guide XILINX The following typographical conventions are used in this document Convention Courier font Meaning or Use Messages prompts and program files that the system displays Example speed grade 100 Courier bold Literal commands that you enter in a syntactical statement ngdbuild design_name Helvetica bold Commands that you select from a menu File gt Open Keyboard shortcuts Ctrl C Italic font Variables in a syntax statement for which you must supply values ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter They are required in bus specifications such as bus 7 0 ngdbuild option_name design_name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 IOB 2 QOUT CLKIN Name Name Horizontal ellipsis Repetitive material that has
104. e can be 1 or 0 A value of 1 indicates positive polarity of the enable signal active high and a value of 0 indicates negative polarity active low If the attribute is not defined the synthesis tool assumes a positive polarity by default syn gatedclk clock en polarity Verilog Syntax Example module bbel ena clk data in data out synthesis syn black box synthesis syn force seq prim 1 input clk synthesis syn isclock 1 synthesis syn gatedclk clock en ena synthesis syn gatedclk clock en polarity 0 input data in ena output data out endmodule syn gatedclk clock en polarity VHDL Syntax attribute syn gatedclk clock en polarity of object false syn gatedclk clock en polarity VHDL Syntax Example library ieee use ieee std logic 1164 all use ieee std logic arith all use ieee std logic unsigned all entity bbel is port ena in std logic Clk in std logic data in in std logic data out out std logic attribute syn black box boolean attribute syn force seq prim boolean attribute syn gatedclk clock en polarity boolean objectType is true Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 85 Chapter 5 Specifying Timing Constraints in Synplify XILINX attribute syn_gatedclk_clock_en_polarity of clk signal is false attribute syn_gatedclk_clock_en string attribute syn_isclock boolean attribute sy
105. e large depending on the relationship between the two clocks Since the PHASE keyword defines the difference between the two clocks this becomes the timing constraint requirement for the cross clock domain path analysis If the PHASE keyword value is too small it is impossible to meet the cross clock domain path analysis D Q D Q D Q REG REG REG CLK CLK CLK A A A Ck_div Figure 6 1 Gated Clock with Divide down Flip Flop X11093 Single Clock Domain A single clock domain is easy to understand and analyze All the synchronous elements are on the same clock domain and are analyzed on the rising edge of the clock or all elements are analyzed on the falling edge of the clock The clock source is driven by the same clock source which can be a PAD or DCM DLL PLL PMCD component with only one output Note The timing analysis tool reports the active edges of the clock driver and the corresponding time for the data path between the synchronous elements 112 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX PERIOD Constraints A simple design is shown in Figure 6 2 Single Clock Domain Schematic The PERIOD constraint is analyzed from the User Constraints File UCF DATA_IN Pus CLK P sure DATA OUT Pour X11094 Figure 6 2 Single Clock Domain Schematic Timing Report Example Slack setup path 3 904ns requirement data path clock path skew
106. e the timing requirements are met However when a requirement is over constrained or specified as a value greater than the design requirement the effort spent by the tools to meet this constraint increases significantly This extra effort results in increased memory use and tool runtime More importantly over constraint can result in loss of performance not only for the constraint in question but for other constraints as well For this reason Xilinx recommends that you specify the constraint values using the actual design requirements Xilinx recommends that you always comment the constraints file This allows other designers to understand why each constraint is used Include in your comments e Source of the constraint e Whether the PERIOD constraint is based on an external clock This Guide uses XCF constraint syntax examples This format passes the design requirements to the implementation tools However the easiest way to enter design constraints is to use Constraints Editor Constraints Editor e Provides a unified location in which to manage all the timing constraints associated with a design e Provides assistance in creating timing constraints from the design requirements in XCF syntax Input Timing Constraints This section discusses Input Timing Constraints and includes e About Input Timing Constraints e System Synchronous Inputs e Source Synchronous Inputs 12 www xilinx com Timing Constraints U
107. ed group that consists of existing groups created by means of TNM constraints predefined groups or other TIMEGRP attributes Time Group TIMEGRP XCF Syntax Example TIMEGRP Top Group GroupA GroupB GroupC Timing Specifications TIMESPEC Timing Specifications TIMESPEC is a basic timing related constraint Timing Specifications TIMESPEC serves as a placeholder for timing specifications which are called TS attribute definitions A TS attribute defines the allowable delay for paths in your design Every TS attribute begins with the letters TS and ends with a unique identifier that can consist of letters numbers or the underscore character _ Timing Specifications TIMESPEC XCF Syntax TIMESPEC TSidentifier PERIOD timegroup_name value units TIMESPEC TSidentifier FROM source group TO dest group value units where e TSidentifier is a unique name for the TS attribute e value is a numerical value It defines the maximum delay for the attribute Nanoseconds are the default units for specifying delay time in TS attributes You can also specify delay with other units such as picoseconds or megahertz e units can be ms micro ps ns Keywords such as FROM TO and TS appear in the documentation in upper case However you can specify them in the TIMESPEC primitive in either upper or lower case 74 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX
108. ees only the original PERIOD constraint and not the newly transformed PERIOD constraints PHASE Keyword The PHASE keyword is used in the relationship between related clocks The timing analysis tools use this relationship for the OFFSET constraints and cross clock domain path analysis The PHASE keyword can be entered in the UCF NCF or through the translation of the DCM DLL PLL components during NGDBuild Note f the phase shifted value of DCM PLL DLL component is changed in FPGA Editor the change is not reflected in the PCF file The timing analysis tools use the PHASE keyword value in the PCF to emulate the DLL DCM PLL phase shift value In order to see the change that was made in FPGA Editor the PCF must also be modified manually with the corresponding change DLL DCM PLL Manipulation with PHASE Table 3 1 Transformation of PERIOD Constraint Through DCM displays the new DCM DLL PLL component output clock net derived TIMESPEC PERIOD constraints based upon the original PERIOD TS_CLKIN constraints TS_CLKIN is expressed as a time value If TS_CLKIN is expressed as a frequency value the multiply and divide operations are reversed If the DCM attributes FIXED_PHASE_SHIFT or VARIABLE_PHASE_SHIFT are used the amount of the phase shifted value is included in the PHASE keyword value The DCM attributes FIXED_PHASE_SHIFT or VARIABLE_PHASE_SHIFT phase shifting amount on the DCM is not reflected in Table 3 1 Transformation of PER
109. efine input delay iii ilie ike e xx x vel er bee dives vale mated 97 define input dela Synta ics cass ban rd ie oe A eee eg ae ASA 97 define input delay Syntax Examples 0 0 cece eee ene 98 define 3o standatd eis os a a EU CEPET ERE hI iaa 98 define io standard Syntax cesede t sesse reya etes cee ee ehh 98 define io standard Syntax Example esses ees 98 detmne multicycle path sisse see tede re be mer cer cs 99 define_multicycle_path SyNtaX oooocoococccooccooccaccor nen 99 define multicycle path Syntax Examples sse 100 define output delay ssssssssssssss n 100 define output delay Syntax sissen eaa enka aae ein ehh 100 define output delay Syntax Examples sies ee 101 Output Pad Clock Domain Default eee 101 define path delay ici ze Rer e per e ee PEU EE ER o RR E 101 define path delay Syntax esses nnn 102 define path delay Syntax Examples esee 102 define reg input delay ioci uu ku e yu e ar vee eve vue erri aes 103 define reg input delay Syntax 0 0 cece cece nnn 103 define reg output delay i cies secre he re ER p e Y erga 103 define reg output delay Syntax 6 nen 103 Specify From To Through Points 0 0 eee eee 104 From T0 Pots cio A DECKER EGA DOS BESEGG Caps 104 Through Points ua e be pee RE eC CERE UP exce Fate eer 104 Single Through Ponta d oae t ebat ate wp AD epa ete s 105 Single List of Through Points asseris s
110. eger greater than 10 Timing Constraints User Guide www xilinx com 91 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX syn_tsun VHDL Syntax Examples attribute syn_tsull string attribute syn_tsull of bitreg component is di0 dil gt clk 2 0 attribute syn_tsul2 string attribute syn_tsul2 of bitreg component is di2 di3 gt clk 1 8 where e bundle is a collection of buses and scalar signals To assign values to bundles use the following syntax The values are in ns bundle clock value e lisanoptional exclamation mark indicating a negative edge for a clock The objects of a bundle must be separated by commas with no spaces between A valid bundle is A B C which lists three signals In addition to the syntax used in the code below you can also use the following Verilog style syntax to specify this attribute attribute syn tsul of inputfifo coregen component is rd clk gt dout 48 0 3 0 The following example assigns syn_tsun together with other black box constraints A USE clause for the Synplify Attributes package was included earlier to make the timing constraint definitions visible here architecture top of top is component rcf16x4z port ad0 adl ad2 ad3 in std logic dio dil di2 di3 in std logic clk wren wpe in std logic tri in std logic do0 dol do2 do3 out std logic end component attr
111. egisters NET CLK PERIOD 20nS OFFSET IN 4nS BEFORE CLK TIMEGRP AB OFFSET IN 6nS BEFORE CLK TIMEGRP C DATA CLK X11081 Figure 3 21 OFFSET with different Time groups Note For CPLD designs the clock inputs referenced by the OFFSET constraints must be explicitly assigned to a global clock pin using either a BUFG symbol or applying the BUFG CLK constraint to an ordinary inpu Otherwise the OFFSET constraint is not used during timing driven optimization of the design www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Timing Constraints FROM TO Multi Cycle Constraints This section discusses FROM TO Multi cycle Constraints and includes e About FROM TO Multi Cycle Constraints e False Paths or Timing Ignore TIG Constraint e Paths Covered by FROM TO Constraints About FROM TO Multi Cycle Constraints A multi cycle path is path that is allowed to take multiple clock cycles These types of paths are typically covered by a PERIOD constraint by default They may cause errors since a PERIOD is a one cycle constraint To eliminate these errors remove the paths from the PERIOD constraint by putting a specific multi cycle constraint on the path A multi cycle constraint is applied by using a FROM TO constraint FROM TO constraints e Havea higher priority than a PERIOD constraint e Removes the specified paths from the PERIOD to the FROM TO constraint Mult
112. elated synchronized clocks to the same clock group and unrelated clocks in different groups The synthesis tool calculates the relationship between clocks in the same clock group and analyzes all paths between them Paths between clocks in different groups are ignored false paths e rise fall specifies a non default duty cycle By default the synthesis tool assumes that the clock is a 50 duty cycle clock with the rising edge at 0 and the falling edge at period 2 If you have another duty clock cycle specify the appropriate Rise At and Fall At values e route is an advanced user option that improves the path delays of all registers controlled by this clock The value of route is the difference between the synthesis timing report path delays and the value in the Place and Route timing report The route constraint applies globally to the clock domain and can over constrain registers where constraints are not needed Before you use this option evaluate the path delays on individual registers in the optimization timing report and try to improve the delays by applying the constraints define reg input _ delay and define reg output delay only on the registers that need them 94 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in an SDC File TCL define_clock Syntax Examples In the following example a clock is defined on the Q pins of instances myInst1 and myInst2
113. enn ha 51 Paths Covered by OFFSET Constraints cesses 53 FROM TO Multi Cycle Constraints sssssssee ee 55 About FROM TO Multi Cycle Constraints lees 55 False Paths or Timing Ignore TIG Constraint 0 0 0 ee eee 59 Paths Covered by FROM TO Constraints 66 0 en 60 Timing Constraint Syntax 2 00 66 rr eee 61 Creating Timing Constraints celokestet esee em Rr RR Rar ess 61 Chapter 4 Specifying Timing Constraints in XST Specifying Timing Constraints in HDL or XCF Lusuusussuse 63 Specifying Timing Constraints in HDL 0 63 Specifying Timing Constraints in XCF 0 0 or 63 Enabling the Command Line Switch 0 0 0 c cece eee eee 64 XST Timing Constraints 20540s050deeneseesy rr tod aee ddr rada vs 64 Asynchronous Register ASYNC REG 2 2 ccc ene 65 Asynchronous Register ASYNC_REG VHDL Syntax 0 0 06 00 c eee eee 65 Asynchronous Register ASYNC_REG VHDL Syntax Example o o ooo ooo ooo 65 Asynchronous Register ASYNC_REG Verilog Syntax llle eese 65 Asynchronous Register ASYNC_REG Verilog Syntax Example oo ooo ooo 65 Clock Signal CLOCK SIGNAL sese n ee 9 eere Ea 65 Clock Signal CLOCK SIGNAL VHDL Syntax lle 65 Clock Signal CLOCK SIGNAL VHDL Syntax Example eese 66 Clock Signal CLOCK SIGNAL Verilog Syntax sees 66 Clock Signal CLOCK SIGNAL Verilog Syntax Example
114. erface of the outputs of the FPGA device with the outside environment The default delay outside the FPGA device is 0 0 ns Output signals typically drive logic that exists outside the FPGA device but the synthesis tool cannot detect the delay for that logic unless you specify it with a timing constraint define output delay Syntax define output delay disable outputportName default ns route ns ref clockName edge comment textString where e disable disables a previous delay specification on the named port e outputportName is the name of the output port e default sets a default input delay for all outputs 100 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL Use this option to set a delay for all outputs You can then set define_output_delay on individual outputs to override the default constraint This example sets a default output delay of 8 0 ns The delay is outside the FPGA device define_output_delay Syntax Examples define_output_delay default 8 0 The following example overrides the default and sets the output delay on output_a to 10 0 ns Accordingly output_a drives 10 ns of combinational logic before the relevant clock edge define_output_delay output_a 10 0 where e ref defines the clock name and edge that controls the event The value must be one of the following r rising edge e f falling edge
115. ernal clock and its associated data in or data out pin OFFSET is used only for pad related signals and cannot be used to extend the arrival time specification method to the internal signals in a design For more information see Chapter 3 Timing Constraint Principles Offset OFFSET XCF Syntax OFFSET IN OUT offset time units BEFORE AFTER clk name TIMEGRP group name where e offset time units is the difference in time between the capturing clock edge and the start of the data to be captured The time can be specified with or without explicitly declaring the units If no units are specified the default value is nanoseconds The valid values are ps ns micro and ms e BEFORE AFTER defines the timing relationship of the start of data to the clock edge The best method of defining the clock and data relationship is to use the BEFORE option BEFORE describes the time the data begins to be valid relative to the capturing clock edge Positive values of BEFORE indicate the data begins prior to the capturing clock edge Negative values of BEFORE indicate the data begins following the capturing clock edge e clk name defines the fully hierarchical name of the input clock pad net e The Valid keyword is not applicable to the Offset constraint Timing Constraints User Guide www xilinx com 69 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX Offset OFFSET XCF Syn
116. ertainty Jitter Both equations also include the Clock to Out time of the synchronous source element as a portion of the data path delay In Figure 3 15 Hold Violation Clock Skew Data Path and Figure 3 16 Hold Violation Waveform since the positive clock skew is greater than the data path delay the timing analysis issues a hold violation DATA OUT DATA IN eK X11075 Figure 3 15 Hold Violation Clock Skew gt Data Path CLK at source FF j mt La ft LT at destination FF l S Input EP at source input FF l ua j Hund DATA DATAO Y DATA at source output FF DATA l 1 DATA 1 l at destination input FF DATAO DATA1 DATA_OUT DATAO DATA1 at destination output FF X11076 Figure 3 16 Hold Violation Waveform Note The timing report does not list the hold paths unless the path causes a hold violation 50 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Timing Constraints To report the hold paths for each constraint use the fastpaths switch in trce or Report Fast Paths Option in Timing Analyzer An example of setup and hold times from the device data sheet is shown in Figure 3 17 Setup Hold times from Data Sheet Note Historically the setup and hold analysis in the timing report is smaller than the values in the device data sheet The values in the data sheet cover every pin and synchronous elemen
117. et a FROM TO constraint is needed to analyze this data path Internal clocks generated by a DCM PLL DLL PMCD BUFR are exceptions to this rule The FROM T1O constraint provides similar analysis as the OFFSET constraints in the following situations e Calculate whether a setup time is violated at a synchronous element whose data or clock inputs are derived from internal nets e Specify the delay of an external output net derived from the Q output of an internal synchronous element that is clocked from an internal net Paths Covered by OFFSET Constraints The OFFSET constraints cover the following paths and are shown in Figure 3 20 Circuit Diagram of OFFSET Constraints e From input pads to synchronous elements OFFSET IN e From synchronous elements to output pads OFFSET OUT Note If the clock net that clocks a synchronous element does not come from an input pad for example it is derived from another clock or from a synchronous element then the OFFSET constraint does not return any paths during timing analysis OFFSET IN OFFSET OUT b X nop FLOP gop 74 77777 7 po B E B CLK gt i F 77777 BUFG I E ocu FLOP sor t a gt BUS 7 0 amp da R OUT2 B amp Combinatorial Logic X11080 CDATA Figure 3 20 Circuit Diagram of OFFSET Constraints The OFFSET constraint is analyzed with respect to only a single clock edge If the OFFSET Constraint needs to analyze mult
118. g Name TNM XCF Syntax NET INST PIN net or pin or inst name TNM predefined group identifier where e predefined group can be all the members or a subset of a predefined group using the keywords FFS RAMS LATCHES PADS CPUS HSIOS BRAMS PORTA BRAMS PORTB DSPS and MULTS e identifier can be any combination of letters numbers or underscores 76 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX XST Timing Constraints Timing Name TNM XCF Syntax Example NET clk TNM FFS my_flop Grpl INST clk TNM FFS my_macro Grp2 Timing Name Net TNM_NET Timing Name Net TNM_NET identifies the elements that make up a group which can then be used in a timing specification TNM_NET is essentially equivalent to TNM on a net except for input pad nets For more information see Chapter 3 Timing Constraint Principles Timing Name Net TNM_NET XCF Syntax NET INST net_name TNM_NET predefined_group identifier where e predefined_group can be all the members of a predefined group using the keywords FFS RAMS PADS MULTS HSIOS CPUS DSPS BRAMS_PORTA BRAMS_PORTB or LATCHES A subset of elements in a predefined_group can be defined as follows predefined group name qualifierl name qualifiern name qualifierncan be any combination of letters numbers or underscores The name_qualifier type net or instance is based on the element type that
119. g Timing Constraints in Synplify XILINX 110 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Chapter 6 Timing Constraint Analysis This chapter discusses Timing Constraint Analysis and includes PERIOD Constraints FROM TO Multi Cycle Constraints OFFSET IN Constraints OFFSET OUT Constraints Clock Skew Clock Uncertainty Asynchronous Reset Paths Use the trce command to analyze timing constraints You can run the tree command from Timing Analyzer or from the command line The following sections show the analysis of the timing constraints PERIOD Constraints This section discusses PERIOD Constraints and includes Gated Clocks Single Clock Domain Two Phase Clock Domain Multiple Clock Domains Clocks from DCM outputs Clk0 Clock Domain CIk90 Clock Domain CIk2x Clock Domain CLKDV CLKEX Clock Domain PERIOD constraints constrain those data paths from synchronous elements to synchronous elements The most common examples are single clock domain two phase clock domain and multiple clock domains A timing report example is provided for each common type of path a PERIOD constraint may cover in your design Gated Clocks The PERIOD constraint does not analyze gated or internally derived clocks correctly If the clock is gated or goes through a LUT Look Up Table the timing analy
120. he PERIOD constraint Since the timing tools take the original requirement and reduce it by half for the two phase clock the total delay for a two phase clock is then doubled to give a Timing Constraints User Guide www xilinx com 113 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX full period equivalent This full period equivalent is then used as the Minimum Period value l 1 1 Single Phase Maximum l l Two Phase Maximum X11096 Figure 6 4 Relationship between Single Phase and Two Phase Clocks A two phase clock example has a requirement of half the PERIOD constraint If the PERIOD constraint is set to 6 ns and the timing analysis cuts the original requirement in half to 3ns for the two phase data paths If the two phase data path has a worst case delay as 1 309 ns the full period equivalent is 2 618 ns The slack on this two phase data path is 1 691 ns 3 ns 1 309 ns If a full phase data path delay is 2 ns which corresponds to a slack value of 4 ns the two phase data path is not first in the timing report but the Minimum Period value is 2 618ns Timing Report Example Slack setup path 1 096ns requirement data path clock path skew uncertainty Source IntA_1 FF Destination XorA_1 FF Requirement 3 000ns Data Path Delay 4 036ns Levels of Logic 1 Clock Path Skew 0 000ns Source Clock clkO rising at 0 000ns Destination Clock clk
121. he PERIOD constraint is not referenced or related to any other user group definition New PERIOD Constraints on DCM Outputs If the Transformation Conditions are met the TIMESPEC TS_c1k20 PERIOD Clk20 grp 20 ns HIGH 50 constraint is translated into the following constraints based upon the clock structure shown in Figure 3 1 New PERIOD Constraints on DCM Outputs CLKO TS_c1k20_0 PERIOD c1k20_0 TS_c1k20 1 000000 HIGH 50 000000 CLK90 TS clk20 90 PERIOD c1k20_90 TS_c1k20 1 000000 PHASE 5 000000 nS HIGH 50 000000 DCM clk20 clk20_0 clk20_90 X11061 Figure 3 1 New PERIOD Constraints on DCM Outputs The following message appears in the NGDBuild design b1d or MAP design mrp report INFO XdmHelpers 851 TNM clk20 grp used in period specification TS clk20 was traced into DCM instance my dcm The following new TNM groups and period specifications were generated at the DCM output s Clk0 TS clk20 O PERIOD clk20 0 TS_c1k20 1 000000 HIGH 50 000000 Clk90 TS clk20 90 PERIOD clk20 90 TS clk20 1 000000 PHASE 5 000000 nS HIGH 50 000000 If the CLKIN DIVIDE BY 2 attribute is set to TRUE for the DCM in Figure 3 1 New PERIOD Constraints on DCM Outputs the translated PERIOD constraints are adjusted accordingly The following constraints are the result of this attribute CLKO TS clk20 O PERIOD c1k20_0 TS_c1k20 2 000000 HIGH 50 000000 CLK90 TS clk20 90 PERIOD c1k20_90 TS_c1k20 2
122. hem To constrain the paths between two clock domains create time groups based upon each clock domain then create a FROM TO for each direction that the paths pass between the two clock domains Following is an example of a cross clock domain using a FROM TO constraint See Figure 3 23 Cross Clock Domain Path analyzed between CLK A clock domain and CLK B clock domain TIMESPEC TS clk1 to clk2 FROM clk1 TO clk2 8 ns Constrain from time group 1kA to time group c1kB to be 8 ns DATA gt E Bi i 5 CK AL gt ckB gt X11083 Figure 3 23 Cross Clock Domain Path analyzed between CLK A clock domain and CLK B clock domain One of the fundamental FROM TO constraints is the Pad to Pads path or asynchronous paths of the design The FROM PADS TO PADS constraint constrains purely combinatorial paths with the start and endpoints are the Pads of the design These types of paths are traditionally left unconstrained since the paths are asynchronous See Figure 3 24 Pad to Pad Multicycle constraint covers path Following is an example of this type of constraint TIMESPEC TS Pad2Pad FROM PADS TO PADS 14 4 ns 56 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Timing Constraints Unconstrained Data Path CDATA BUFG l Constrained Data Path X11084 Figure 3 24 Pad to Pad Multicycle constraint
123. ial clock edge at zero ns based upon the PERIOD constraint Since the clock is phase shifted by the DCM the timing report displays the Clock Arrival time as the phase shifted amount If the CLK90 output is used the phase shifted amount is one quarter of the PERIOD The Clock Arrival time corresponds to the phase shifting amount which is 2 5 ns in this case The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold In Figure 6 20 Timing Diagram of Phase Shifted Clock in OFFSET OUT Constraint the OFFSET requirement is five ns Timing Constraints User Guide www xilinx com 131 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET OUT R ns AFTER clock clock_in 10 ns l pul us clk90 data X11112 Figure 6 20 Timing Diagram of Phase Shifted Clock in OFFSET OUT Constraint Timing Report Example Slack 1 365ns requirement clock arrival clock path data path uncertainty Source OutD_7 FF Destination OutD lt 7 gt PAD Source Clock clock3_std_bufg rising at 2 500ns Requirement 5 000ns Data Path Delay 3 405ns Levels of Logic 1 Clock Path Delay 0 280ns Levels of Logic 3 Clock Uncertainty 0 180ns Fixed Phase Shifted Example A DCM fixed phase shifted example of the OFFSET OUT constraint has the
124. ibute syn tcol of rcfl6x4z component is ad0 adi ad2 ad3 gt do0 do1 do2 do3 2 1 attribute syn tpd2 of rcfl6x4z component is tri gt do0 do1 do2 do3 20 s attribute syn tsul of rcfl6x4z component is ad0 ad1 ad2 ad3 gt clk 1 2 attribute syn_tsu2 of rcfl6x4z component is wren wpe gt clk 0 0 Other code syn_tsun sdc File Syntax define attribute v blackboxModule syn tsun bundle gt clock value where e v indicates that the directive is attached to the view e blackboxModule is the symbol name of the black box e nA is a numerical suffix that lets you specify different clock to output timing delays for multiple signals bundles e isan optional exclamation mark indicating that the clock is active on its falling negative edge e clock is the name of the clock signal 92 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in an SDC File TCL e bundle is a collection of buses and scalar signals The objects of a bundle must be separated by commas with no intervening spaces A valid bundle is A B C which lists three signals e valueInput is the clock setup delay value in ns syn tsun sdc File Syntax Example define attribute v RTRV MOD syn tsu4 RTRV_DATA 63 0 gt CLK 20 Specifying Timing Constraints in an SDC File TCL Constraint files have an sac file extension They can include timing constra
125. icycle constraints e Havea higher priority than PERIOD and OFFSET constraints It pulls paths out of the lower priority constraints and the paths are analyzed by the multicycle constraints e Can be tighter or looser than lower priority constraints e Constrain a specific path The specific path can be within the same clock domain but have a different requirement than the PERIOD constraint Alternatively the specific path with a data path which crosses clock domains are constrained with a multicycle constraint A FROM TO constraint begins at a synchronous element and ends at a synchronous element For example if a portion of the design needs to run slower than the PERIOD requirement use a FROM TO constraint for the new requirement The multi cycle path can also mean that there is more than one cycle between each enabled clock edges When using a FROM TO constraint you must specify the constrained paths by declaring the start and end points which must be pre specified time groups such as PADS FFS LATCHES RAMS user specified time groups or user specified synchronous points see TPSYNC FROM or TO is optional when constraining a specific path A FROM multicycle constraint covers a fromor source time group to the next synchronous elements or pads elements A TO multicycle constraint covers all previous synchronous elements or pad elements to a to or destination time group Following are some possible combinations e FROM TO e FROM
126. ide UG612 v 11 1 1 April 29 2009 XILINX Constraint System e BRAMS_PORTB Port B of all dual port block RAMs The TNM_NET is equivalent to TNM on a net but produces different results on pad nets The Translate Process or NGDBuild command never transfers a TNM_NET constraint from the attached net to an input pad as it does with the TNM constraint You can use TNM NET only with nets If TNM_NET is used with any other objects such as a pin or instance a warning is generated and TNM_NET definition is ignored A TNM attribute on a pad net or the net between the IPAD and the IBUE the constraints parser traces the signal or net upstream to the pad element as shown in Figure 3 4 Differences between TNM and TNM_NET The TNM_NET attribute is traced through the buffer to the synchronous elements In HDL designs the IBUF output signal is the same as the IPAD or port name so there are not differences between the TNM_NET and TNM attributes In this case both timing name attributes trace downstream to the synchronous elements Propagation Rules for TNM_NET The propagation rules for TNM_NET are e If applied to a pad net TINM_NET propagates forward through the IBUF elements and any other combinatorial logic to synchronous elements or pads e Ifapplied to a clock pad net TNM_NET propagates forward through the clock buffer to synchronous elements or pads e Ifapplied to an input clock net of a DCM DLL PLL PMCD BUFR and associ
127. identifier is a reference identifier that has a unique name TNM reference is the identifier name that is attached to a clock net or a net in the clock path using the TNM or TNM NET constraint When a TNM_NET constraint is traced into the CLKIN input of a DLL DCM or PLL component new PERIOD specifications may be created at the DLL DCM PLL outputs period is the required clock period units is an optional field to indicate the units for a clock period The default is nanoseconds ns but the timing number can be followed by ps ms micro or to indicate the intended units HIGH or LOW indicates whether the first pulse is to be High or Low HIGH and LOW values are not taken into account during timing estimation and optimization They are propagated to the final netlist only if WRITE TIMING CONSTRAINTS yes high or low time is the optional HIGH or LOW time depending on the preceding keyword If an actual time is specified it must be less than the period If no high or low time is specified the default duty cycle is 50 percent Timing Constraints User Guide www xilinx com 71 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX hi lo units is an optional field to indicate the units for the duty cycle The default is nanoseconds ns but the high or low time number can be followed by ps micro ms or if the HIGH or LOW time is an actual time measurement The following statement assigns
128. ify Pro and Synplify Premier only Specifying Timing Constraints in HDL The following sections list each type of HDL timing constraints in detail e black box tri pins e syn force seq prim e syn gatedclk clock en Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 80 www xilinx com 7 XILINX Specifying Timing Constraints in HDL e syn_gatedclk_clock_en_polarity e syn_isclock e syn tpdn e syn tcon e syn tsun black box pad pin Theblack box pad pin directive specifies pins on a user defined black box component as I O pads visible to the environment outside the black box If more than one port is an I O pad list the ports e Inside double quotes separated by commas e Without enclosed spaces black_box_pad_pin Verilog Syntax object synthesis syn black box black box pad pin portList where e portList isa spaceless comma separated list of the names of the ports on black boxes that are I O pads black box pad pin Verilog Syntax Example module BBDLHS D E GIN GOUT PAD Q synthesis syn black box black box pad pin GIN 2 0 Q black box pad pin VHDL Syntax attribute black box pad pin of object objectType is portList where e object is an architecture or component declaration of a black box Data type is string e portList isa spaceless comma separated list of the black box port names that are I O pads black box pad pin VHDL Syntax Examp
129. ime groups from analysis To specify the timing ignore TIC constraint for this method define e A set of registers for the source time group e A set of registers for the destination time group e AFROM TO constraint with a TIG keyword to remove the paths between the groups www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Timing Exceptions Example A hypothetical case in which a path between two registers does not affect the timing of the design and is desired to be removed from analysis is shown in Figure 2 13 Path between two registers that does not affect the timing of the design X11059 Figure 2 13 Path between two registers that does not affect the timing of the design The generic syntax for defining a timing ignore TIG between time groups is TIMESPEC TSid FROM SRC_GRP TO DST_GRP TIG In the FROM TO TIG example the SRC_GRP defines the set of source registers at which path tracing begins The DST_GRP defines the set of destination registers at which the path tracing ends All paths that begin in the SRC_GRP and end in the DST_GRP are ignored The specific syntax for this example is NET CLK1 TNM_NET FFS GRP_1 NET CLK2 TNM NET FFS GRP 2 TIMESPEC TS Example FROM GRP 1 TO GRP 2 TIG Multi Cycle Paths In a multi cycle path data is transferred from source to destination synchronous elements a
130. iming constraint that is forward annotated includes the I O delay with the path delay This could result in Timing Constraints User Guide www xilinx com 101 UG612 v 11 1 1 April 29 2009 102 Chapter 5 Specifying Timing Constraints in Synplify XILINX discrepancies with the Xilinx place and route tool which ignores the I O delays and reports the path delay only define_path_delay Syntax define path delay disable from startPoint to endPoint through throughPoint max delayValue comment textString where disable disables the constraint rom specifies the starting point of the path The rom point defines a timing start point It can be any of the following Clocks c Registers i Top level input or bi directional ports p Black box outputs i to specifies the ending point of the path The to point must be a timing end point It can be any of the following clocks c registers i top level output or bi directional ports p black box inputs i You can combine this option with from or through to get a specific path through specifies the intermediate points for the timing exception Intermediate points can be combinational nets n hierarchical ports t pins on instantiated cells t By default the intermediate points are treated as an OR list The exception is applied if the path crosses any points in the list You can combine this
131. iming exceptions it automatically attaches object type qualifiers to the object names For more information see the Synplify Reference Guide define_multicycle_path Syntax Examples define_multicycle_path from i regs addr 4 0 to i special_regs w 7 0 2 define_multicycle_path to i special_regs inst 11 0 2 define_multicycle_path from p porta 7 0 through n prgmentr pc_sel44 0 to p portc 7 0 2 define_multicycle_path from i special_regs trisc 7 0 through t uc_alu aluz Q through t special_net Q 2 The following example shows the syntax for setting a multi cycle path constraint between registers define multicycle path from i myInst1_reg through n myInst2 net to i myInst3 reg 2 The constraint is defined from the output ofmyInst1_reg through netmyInst2_net to the input pin myInst3 reg lfthe instance is instantiated a pin level constraint applies on the pin as defined However if the instance is inferred the pin level constraint is transferred to the instance For through points specified on pins the constraint is transferred to the connecting net You cannot define a through point on a pin of an instance that has multiple outputs When specifying a pin on a vector of instances you cannot refer to more than one bit of that vector define output delay The define output delay constraint e Specifies the delay of the logic outside the FPGA device driven by the top level outputs e Models the int
132. information see PERIOD Constraints in Chapter 3 Timing Constraint Principles The application and methodology for constraining synchronous clock domains falls under several common cases These categories include e Automatically Related Synchronous DCM PLL Clock Domains e Manually Related Synchronous Clock Domains e Asynchronous Clock Domains www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Register To Register Timing Constraints By allowing the tools to automatically create clock relationships for DLL DCM PLL output clocks and manually defining relationships for externally related clocks all synchronous cross clock domain paths are covered by the appropriate constraints and properly analyzed Using PERIOD constraints that follow this methodology eliminates the need for additional cross clock domain constraints Automatically Related Synchronous DCM PLL Clock Domains The most common type of clock circuit is one in which e The input clock is fed into a DLL DCM PLL e The outputs are used to clock the synchronous paths in the device In this case the recommended methodology is to define a PERIOD constraint on the input clock to the DLL DCM PLL By placing the PERIOD constraint on the input clock the Xilinx tools automatically e Derive anew PERIOD constraint for each of the DLL DCM PLL output clocks e Determine the clock relationships between the output clock
133. ints general attributes and vendor specific attributes You can manually create constraint files in a text editor using Tcl commands but you typically use the SCOPE spreadsheet to generate the file automatically The following sections lists each type of Tcl timing constraints in detail e define clock e define clock delay e define compile point e define current design e define false path e define input delay e define io standard e define multicycle path e define output delay e define path delay e define reg input delay e define reg output delay define clock The define clock constraint defines a clock with a specific duty cycle and frequency or clock period goal You can have multiple clocks with different clock frequencies Set the default frequency for all clocks with the set option frequency Tcl command in the project file If you do not specify a global frequency the timing analyzer uses a default Use the define clock timing constraint to override the default and specify unique clock frequency goals for specific clock signals Additionally you can use de ine clock to set the clock frequency for a clock signal output of clock divider logic The clock name is the output signal name for the register instance define clock Syntax define clock disable virtual clockObject freq MHz period ns clockgroup domain rise value fall value route ns name cloc
134. ints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX FROM TO Multi Cycle Constraints Hold analyses are performed on register to register paths by taking the data path Tcko Troute_total Tlogic_total and subtracting the clock skew Tdest clk Tsxrc_clk and the register hold delay Th In the TWR report slack is used to evaluate the hold check e Negative slack indicates a hold violations e Positive slack means there is no hold violation The following equation is used for hold slack calculations Hold Slack Tdata Tskew Th The detailed path is reported under the constraint that contains that data path The path is listed by the slack with respect to the requirement There is a Th identifier of the hold path delay type This Th appears after the hold delay type to help identify race conditions and hold violations Hold analyses are performed on all global and local clock resources The data path is not adjusted to show possible variances in the PVT across the silicon Hold violations are generally not seen as a very short data path delay and a large clock skew is needed before this problem occurs If a hold violation does occur the current protocol of PAR and the timing engines is to reduce the clock skew and increase the clock delay for a specific data path if necessary This means that PAR can change the routing to fix a hold violation The hold slack is not related to the constraint requirement This may be conf
135. ion between two clock signals Because this value is discrete and represents the actual phase difference between the DCM clocks it is added directly to the clock uncertainty value Following is the equation for PLL Clock Uncertainty Clock Uncertainty V INPUT JITTER SYSTEM JITTER PLL Descrete Jitter 2 PLL Phase Error PLL Discrete Jitter and PLL Phase Error are provided in the speed files for Virtex 5 devices In the analysis of clock uncertainty all jitter components both random and discrete are specified as peak peak values Peak peak values represent the total range by wyhich the arrival time of a clock signal varies in the presence of jitter In a worst case analysis only the delay variation that causes a decrease in timing slack is used Note Only the peak jitter value or one half the peak to peak value is used for each setup and hold timing check The phase error component of clock uncertainty is a value representing the phase variation between two clock signals Because this value is discrete and represents the actual phase difference between the PLL clocks it is added directly to the clock uncertainty value Asynchronous Reset Paths The analysis of asynchronous reset paths including the recovery time and reset pin to output time is not included in the PERIOD constraint analysis by default Note In order to see asynchronous reset set paths a path tracing control PTC needs to be enabled which is E
136. iple clock phases or clock edges as in source synchronous designs or Dual Data Rate applications then the OFFSET constraint must be manually adjusted by the clock phase The OFFSET constraint does not optimize paths clocked by an internally generated clock Use FROM TO or multi cycle constraints for these paths taking into account the clock delay Timing Constraints User Guide www xilinx com 53 UG612 v 11 1 1 April 29 2009 54 Chapter 3 Timing Constraint Principles XILINX Use the following option to obtain I O timing analysis on internal clocks or derived clocks e Create a FROM TO or multi cycle constraint on these paths e Or determine if the internal clock is related to an external clock signal Change the requirement based upon the relationship between the two clocks For example the internal clock is a divide by two version of the external clock and the original requirement of the OFFSET OUT with the internal clock was 10 ns then the requirement of the OFFSET OUT with the external clock is 20 ns You can specify OFFSET constraints in three levels of coverage e A Global OFFSET applies to all inputs or outputs for a specific clock e A Group OFFSET identifies a group of input or outputs clocked by a common clock that have the same timing requirement e A Net pecific OFFSET specifies the timing by each input or output Note OFFSET constraints with a more specific scope override a more general scope A group OFFS
137. is command relate to prgm entr define false path The define false path constraint defines paths to ignore remove during timing analysis and give lower or no priority during optimization The false paths are also passed on to supported place and route tools define false path Syntax define false path from startPoint to endPoint through throughPoint comment textString where e from specifies the starting point for the false path The From point defines a timing start point It can be any of the following Clocks c Registers i Top level input or bi directional ports p Black box outputs i For more information see the Synplify User s Guide e to specifies the ending point for the false path 96 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL The to point defines a timing end point It can be any of the following Clocks c Registers i Top level output or bi directional ports p Black box inputs i e through specifies the intermediate points for the timing exception Intermediate points can be any of the following Combinational nets n Hierarchical ports t Pins on instantiated cells t By default the through points are treated as an OR list The constraint is applied if the path crosses any points in the list To keep the signal name intact through synthesis
138. is global constraint covers both the data bits of the bus e datal e data2 Source Synchronous Inputs In a source synchronous input interface a clock is regenerated and transmitted along with the data from the source device along similar board traces This clock is then used to capture the data in the FPGA device The board trace delays and board skew no longer limit the operating frequency of the interface The higher frequency also results in the source synchronous input interface typically being a dual data rate DDR application In www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Input Timing Constraints this source synchronous DDR application example shown in Figure 2 3 Simplified Source Synchronous input interface with associated DDR timing unique data is transmitted from the source device on both the rising and falling clock edges and captured in the FPGA device using the regenerated clock Source Device Clock 1 I Data 1 Rising Data Falling Data Data 2 Rising Data Falling Data X11049 Figure 2 3 Simplified Source Synchronous input interface with associated DDR timing The global OFFSET IN constraint is the most efficient way to specify the input timing for a source synchronous interface In the DDR interface one OFFSET IN constraint is defined for each edge of the input interface clock These constraints cover the paths of all input data bits that are cap
139. ividual Xilinx timing constraints in VHDL and Verilog For more information see the Xilinx Synthesis and Simulation Design Guide Synplify Reference Guide and Synplify User s Guide This chapter includes e Synplify Timing Constraints e Specifying Timing Constraints in HDL e Specifying Timing Constraints in an SDC File TCL e Specifying Timing Constraints in a SCOPE Spreadsheet e Forward Annotation Synplify Timing Constraints You can specify timing constraints by using one of the following methods e Write source code attributes or directives You must enter black box timing directives in the source code Do not include any other timing constraints in the source code The source code becomes less portable and you must recompile the design for the constraints to take effect You can also enter attributes through the SCOPE interface but you must use source code for directives e Write Tcl commands in an sdc file You can create the sdc file manually in a text editor Use the SCOPE spreadsheet to generate the constraint syntax e Usea SCOPE spreadsheet The SCOPE Synthesis Constraints Optimization Environment spreadsheet can automatically generate constraint files in Tcl format Use this method for specifying constraints wherever possible You can use it for most constraints except for source code directives Timing Constraints User Guide www xilinx com 79 UG612 v 11 1 1 April 29 2009 Chap
140. k net to define the time group FF1_grp Contains all flip flop elements associated with this net e NET INTCLK TNM NET RAMS Raml_grp Use the intclk net to define the time group Ram1_grp Contains all distributed and block RAM elements associated with this net Instance or Hierarchy When a TNM attribute is placed on a module or macro the constraints parser traces the macro or module down the hierarchy to the synchronous elements and pads The attribute transverses through all levels of the hierarchy rather than forward along a net or signal This feature is illustrated in e Figure 3 2 TNM on the CLOCK pad or net traces downstream to the Flip Flops e Figure 3 3 TNM on the CLK net traced through combinatorial logic to synchronous elements flip flops Those synchronous elements are then tagged with the same TNM attribute The TNM attribute name is then used in a TIMESPEC or timing constraint This method uses a TNM on a block of the design Multiple instances of the same TNM attribute are used to identify the time group A macro or module is an element that performs some general purpose higher level function It typically has a lower level design that consists of primitives or elements other macros or modules or both connected together to implement the higher level function A TNM constraint attached to a module or macro indicates that all elements inside the macro or module at all levels of hierarchy below the tagged
141. kName comment textString where e disable disables a previous clock constraint Timing Constraints User Guide www xilinx com 93 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX e virtual specifies arrival and required times on top level ports that are enabled by clocks external to the chip or block that you are synthesizing When specifying name for the virtual clock the field can contain a unique name not associated with any port or instance in the design e clockObject is a required parameter that specifies the clock object name Clocks can be defined on the following Top level input ports p Nets n Hierarchical ports t Instances i For Xilinx technologies specify the define_clock constraint on an instance Output pins of instantiated cells t Internal pins of instantiated cells t Clocks defined on any of the following WILL NOT be honored Top level output ports Input pins of instantiated gates Pins of inferred instances e name specifies a name for the clock if you want to use a name other than the clock object name This alias name is used in the timing reports e freq defines the frequency of the clock in MHz You can specify either req or period but not both e period specifies the period of the clock in ns Specify either period or freq but not both e clockgroup allows you to specify clock relationships You assign r
142. l time Timing Constraints User Guide www xilinx com 129 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX 130 The resulting timing report displays the e Data path e Clock path e Clock Arrival time shown in bold in the sample report below If the timing report does not display a Clock Arrival time the timing analysis tools did not recognize a PERIOD constraint for that particular synchronous element In Figure 6 18 Timing Diagram of simple OFFSET OUT constraint the OFFSET requirement is three ns The equation used in timing analysis is Slack Requirement Clock Arrival Clock Path Data Path Constraint Syntax Example TIMESPEC TS_clock PERIOD clock_grp 10 ns HIGH 50 OFFSET OUT 3 ns AFTER clock clock_in L 10 ns 3ns data X11110 Figure 6 18 Timing Diagram of simple OFFSET OUT constraint Timing Report Example Slack 0 865ns requirement clock arrival clock path data path uncertainty Source OutD 7 FF Destination OutD 7 PAD Source Clock clock3 std bufg rising at 0 000ns Requirement 3 000ns Data Path Delay 3 405ns Levels of Logic 1 Clock Path Delay 0 280ns Levels of Logic 3 Clock Uncertainty 0 180ns Two Phase Example In a two phase use of both edges example of the OFFSET OUT constraint the initial clock edge correlates to the two edges of the clock e The first clock edge is at
143. le library ieee use ieee std logic 1164 all package my components is component BBDLHS port D in std logic E in std logic GIN in std logic vector 2 downto 0 Q out std logic end component attribute syn black box boolean attribute syn black box of BBDLHS component is true attribute black box pad pin string attribute black box pad pin of BBDLHS component is GIN 2 0 0 end package my components Timing Constraints User Guide www xilinx com 81 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX black_box_tri_pins The black_box_tri_pins directive specifies that an output port on a component defined as a black box is a tristate The black box tri pins directive eliminates multiple driver errors when the output of a black box has more than one driver A multiple driver error is issued unless you use the black_box_tri_pins directive to specify that the outputs are tristates If there is more than one port that is a tristate list the ports e Inside double quotes separated by commas e Without enclosed spaces black_box_tri_pins Verilog Syntax object synthesis syn_black_box black_box_tri_pins portList where e portList is a spaceless comma separated list of multiple pins black box tri pins Verilog Syntax Example Folllowing isa black box tri pins Verilog syntax example with a single port name module BBDLHS D E GIN GOUT PAD O
144. lysis shown in Figure 6 24 Rising to Falling Setup Hold Analysis the positive clock skew is less but the Tho window is smaller and minimizes the chance for a hold violation Therefore a two phase clock is less likely to have a hold violation and can handle more positive clock skew than a single phase clock path CLKs Tho Tsu CLKp X11116 Figure 6 24 Rising to Falling Setup Hold Analysis Note During hold analysis negative clock skew is truncated to zero for Virtex 4 devices and older Virtex 5 devices and newer utilize the negative and positive clock skew in the hold analysis Negative clock skew is used during the setup analysis for this path During analysis of setup and hold the negative clock skew and positive clock skew respectively decrease the margin on the PERIOD constraint requirement as shown in Figure 6 25 Positive and Negative Clock Skew To determine how the timing analysis tools calculated the total clock skew for a path use the Analyze gt Against User Specified Paths command in Timing Analyzer Select the source and destination of the path in question and analyze from the clock source to the two elements in the path Source Clock Positive Clock Skew Negative Clock Skew 1 Tho X11117 Figure 6 25 Positive and Negative Clock Skew In the above figure e Tsu and Tho represent the active edge the setup hold violation calculation is done one respectively e The dashed lines show
145. mination is based upon the constraint prioritization or which constraint appears later in the PCF file if there are overlapping constraints of the same priority If the design has two PERIOD constraints that cover the same paths the later PERIOD constaint in the PCF file covers or analyzes these paths The previous PERIOD constraints show 0 items analyzed in the timing report In order to force the timing analysis tools to use the previous PERIOD constraints instead of the later one use the PRIORITY keyword on the PERIOD constraints In addition to the PRIORITY keyword a multi cycle or FROM TO constraint can be used to cover these paths In order to prioritize within a constraint type or to avoid a conflict between two timing constraints that cover the same path the PRIORITY keyword must be used with a value The value for the PRIORITY can range from 255 to 255 The lower the value the higher the priority The value does not affect which paths are placed and routed first It only affects which constraint covers and analyzes the path with two timing constraints of equal priority Use the following syntax to define the priority of a timing constraint e TIMESPEC TS 01 FROM A grp TO B grp 10 ns PRIORITY 5 TS 01 hasalower priority than TS 02 e TIMESPEC TS 02 FROM A grp TO B grp 20 ns PRIORITY 1 The PRIORITY keyword can be applied only to TIMESPEC constraints with TSidentifiers for example TS03 and not MAXDELAY MAXSKEW or OFFSET
146. n example of a time group created with the predefined group on a hierarchical instance e INST macroA TNM LATCHES latch grp This time group latch_grp consists of the latch components of the hierarchical instance macroA Timing Constraints User Guide www xilinx com 43 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX INST macroB TNM RAMS memory grp This time group memory_grp consists of the RAM components of the hierarchical instance macroB INST tester TNM overall grp This time group overall grp consists of synchronous components such as RAMS FFS LATCHES and PADS of the hierarchical instance tester Time Group Example Four Combining Time Groups The following example shows how to define a new time group by combining it with other time groups TIMEGRP larger grp small grp medium grp Combines small grp and medium grp into a larger group called larger grp TIMEGRP memory and latch grp latch grp memory grp Combine the elements of latch grp and memory grp Time Group Example Five Removing Time Groups Following are examples using the EXCEPT keyword with the TIMEGRP attribute TIMEGRP new time group Original time group EXCEPT a few items time grp Removes the elements of a few items time grp rom Original time group TIMEGRP medium grp small grp EXCEPT smaller grp Creates a time group medium grp from the elements of small grp and removes
147. n_isclock of clk signal is true attribute syn_gatedclk_clock_en of clk signal is ena attribute syn_force_seq_prim of clk signal is true end bbel architecture arch_bbel of bbel is attribute syn_black_box boolean attribute syn_black_box of arch_bbel architecture is true attribute syn_force_seq_prim of arch_bbel architecture is true begin end arch_bbel syn_isclock The syn_isclock directive specifies an input port on a black box as a clock Use the syn_isclock directive to specify that an input port on a black box is a clock even though its name does not correspond to a recognized name Using the syn_isclock directive connects it to a clock buffer if appropriate The data type is Boolean syn_isclock Verilog Syntax object synthesis syn_isclock 1 where e object is an input port on a black box syn_isclock Verilog Syntax Example module ram4 myclk out opcode a b synthesis syn_black_box output 7 0 out input myclk synthesis syn_isclock 1 input 2 0 opcode input 7 0 a b Other code syn_isclock VHDL Syntax attribute syn_isclock of object objectType is true where e object is a black box input port syn_isclock VHDL Syntax Example library synplify entity ram4 is port myclk in bit opcode in bit_vector 2 downto 0 a b in bit vector 7 downto 0 rambus out bit vector 7 downto 0 attribute syn isclock boolean attribute syn isclock of m
148. nalysis Clock skew is calculated based upon the clock path delay to the destination synchronous element minus the clock path delay to the source synchronous element In the majority of designs with a large clock skew the skew can be attributed to one of the following e One or both clocks using local routing e One or both clocks are gated e DCM drives one clock and not the other clock Clock skew is not the same as Phase Phase is the difference in the clock arrival times indicated by the source clock arrival time and the destination clock arrival time in the timing report Clock arrival times are based upon the PHASE keyword in the PERIOD constraint Clock skew is not included in the clock arrival times In the rising to rising setup hold analysis shown in Figure 6 23 Rising to Rising Setup Hold Analysis the positive clock skew greatly increases the chance of a hold violation and helps the setup calculation Note During setup analysis positive clock skew is truncated to zero for Virtex 4 devices and older Virtex 5 devices and newer utilize the positive and negative clock skew in the setup analysis Positive clock skew is used during the hold analysis for this path CLKg Tho CLKp X11115 Figure 6 23 Rising to Rising Setup Hold Analysis Timing Constraints User Guide www xilinx com 135 UG612 v 11 1 1 April 29 2009 136 Chapter 6 Timing Constraint Analysis XILINX In the rising to falling setup hold ana
149. nces 38 INST All synchronous elements are in this time group INST All synchronous elements are in this time group INST Top level elements or modules are in this time group Al B1 C1 INST A1 All elements one or more levels of hierarchy below the A1 hierarchy are in this time group A21 A22 83 AS INST A1 All elements one level of hierarchy below the A1 hierarchy are in this time group A21 A22 INST A1 All elements two or more levels of hierarchy below the A1 hierarchy are in this time group A3 As INST A1 All elements two levels of hierarchy below the A1 hierarchy are in this time group A3 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Constraint System e INST A1 All elements three or more levels of hierarchy below the A1 hierarchy are in this time group Al e INST A1 All elements three levels of hierarchy below the A1 hierarchy are in this time group Al e INST 22 All elements with instance name of 22 are in this time group A22 B22 C22 e INST 22 All elements with instance name of 22 and elements one level of hierarchy below are in this time group A22 83 A4 B22 B3 C22 C3 A1 B1 C1 A21 A22 B21 B22 C21 C22 A3 83 03 A4 X11067 Figure 3 7 Transversing hierarchy with wildcards Instance Pin Identifying groups by
150. nguage HDL code or in an XST Constraints File XCF For information on how to specify timing constraints for Synplify see Chapter 5 Specifying Timing Constraints in Synplify For more information see the Xilinx Synthesis and Simulation Design Guide and XST Users Guide This chapter includes e Specifying Timing Constraints in HDL or XCF e XST Timing Constraints Specifying Timing Constraints in HDL or XCF You can specify timing constraints either in your Hardware Description Language HDL code or in an XST Constraints File XCF To specify timing constraints before synthesis e Specify the timing constraints into your design HDL VHDL Verilog Schematic OR e Specify the timing constraints in an XCF Specifying Timing Constraints in HDL When you specify timing constraints in your HDL code they are written in the style of the attributes Specifying Timing Constraints in XCF XST supports an XST Constraints File XCF syntax to specify synthesis and timing constraints Timing Constraints User Guide www xilinx com 63 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX The constraint file method allows you to use the native XCF timing constraint syntax Using the XCF syntax XST supports constraints such as e TNM NET e TIMEGRP e PERIOD e TIG e FROM TO This includes wildcards and hierarchical names XCF syntax has the following limitation
151. nsmit Edge Related Path I PERIOD 5 ns I I CLK1X 1 1 1 I 1 1 CLK2X180 CLK2X180 C ur X11052 Figure 2 6 Two related clocks entering the FPGA device through separate external pins 18 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Register To Register Timing Constraints The PERIOD constraint syntax for this example is NET PrimaryClock TNM_NET TNM_Primary NET RelatedClock TNM_NET TNM_Related TIMESPEC TS primary PERIOD TNM Primary PeriodValue HIGH HighValue TIMESPEC TS related PERIOD TNM_Related TS Primary relation PHASE value In the related PERIOD definition the PERIOD value is defined as a time unit period relationship to the primary clock The relationship is expressed in terms of the primary clock TIMESPEC In this example CLK2X180 operates at twice the frequency of CLK1X which results in a PERIOD relationship of one half In the related PERIOD definition the PHASE value defines the difference in time between the rising clock edge of the source clock and the related clock In this example since the CLK2X180 clock is 180 degrees shifted the rising edge begins 1 25 ns after the rising edge of the primary clock The syntax for this example is NET C1k1X TNM NET C1k1X NET C1k2X180 TNM NET C1k2X180 TIMESPEC TS Clk1X PERIOD C1k1X 5 ns TIME
152. o create one time group and one corresponding OFFSET OUT constraint with the original constraint requirement The only addition is the FALLING keyword for the falling edged elements and the RISING keyword for the rising edge elements In Figure 6 22 Timing Diagram of Dual Data Rate in OFFSET OUT Constraint the OFFSET requirement is three ns 8 ns 3 ns CLK 10ns 3 ns DATA RISING DATA FALLING t 0ns 3 8 X11114 Figure 6 22 Timing Diagram of Dual Data Rate in OFFSET OUT Constraint Timing Report Example of OFFSET OUT 3 ns AFTER clock RISING Slack 0 783ns requirement clock arrival clock path data path uncertainty Source OutA_4 FF Destination OutA lt 4 gt PAD Source Clock clock0_ddr_bufg rising at 0 000ns Requirement 3 000ns Data Path Delay 3 372ns Levels of Logic 1 Clock Path Delay 0 172ns Levels of Logic 3 Clock Uncertainty 0 239ns Timing Report Example of OFFSET OUT 8 ns AFTER clock FALLING Slack 0 783ns requirement clock arrival clock path data path uncertainty Source OutA_4 FF Destination OutA lt 4 gt PAD Source Clock clock0 ddr bufg falling at 0 000ns Requirement 3 000ns Data Path Delay 3 372ns Levels of Logic 1 Clock Path Delay 0 172ns Levels of Logic 3 Clock Uncertainty 0 239ns OFFSET OUT BEFORE Constraints The OFFSET OUT BEFORE constraint defines the time used by the data external to the FPGA
153. ock Path Skew Since the clock jitter or Clock Uncertainty increases the clock path delay the needed setup margin is larger as shown in Figure 3 13 Reduced Setup Margin by Clock Uncertainty Jitter Input Example REG REG Example e I Setup I I I 1 I Margin L Setup Clock Margin Uncert I I Data Valid Data X11073 Figure 3 13 Reduced Setup Margin by Clock Uncertainty Jitter The hold analysis ensures that the data changes at the destination synchronous element after the clock arrival Timing Constraints User Guide www xilinx com 49 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX Note The data must stay valid at its input pins at least a hold time after the arrival of the active clock edge at its pin The equation for the hold analysis is the clock path skew plus the synchronous element hold time minus the data path delay A hold time violation occurs when the positive clock skew is greater than the data path delay Hold Time Clock Path Skew Synchronous Element Hold Time Data Path Delay Since The clock jitter or Clock Uncertainty increases the clock path delay the needed hold margin is larger as shown in Figure 3 14 Reduce Hold Margin by Clock n s n Uncertainty Jitter Input Example REG REG Example e Hold 1 Margin 1 1 I Clock Hold Uncert Margin 1 1 X11074 Figure 3 14 Reduce Hold Margin by Clock Unc
154. op level of a VHDL or Verilog file or use the Attributes panel of the SCOPE spreadsheet to add the attribute as a global object Clock Groups If two clocks are in the same clock group the synthesis tool writes out the Xilinx ncf file for forward annotation so that one clock is a fraction of the other 108 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Forward Annotation In the following example c1k1 is derived as a fraction of 1k2 which signals the place and route tool that the two clocks are part of the same clock group NET clk2 TNM NET clk2 TIMESPEC TS clk2 PERIOD clk2 10 000 ns HIGH 50 00 NET clki1 TNM NET ciki TIMESPEC TS clk1 PERIOD clk1 TS clk2 2 000000 HIGH 50 00 In the following example the clocks are declared independently so the place and route tool considers the clocks separately for timing calculation NET clk2 TNM NET clk2 TIMESPEC TS clk2 PERIOD clk2 10 000 ns HIGH 50 00 NET clki1 TNM NET clk1 TIMESPEC TS clk1 PERIOD c1k1 20 000 ns HIGH 50 00 Relaxing Forward Annotated l O Constraints Ifthe xc use timespec for io attribute is enabled 1 then I O constraints are forward annotated using the Xilinx TIMESPEC FROM TOcommand In this case there is no relaxation of the constraints For more information see the Synplify Reference G
155. ops e Latches e Distributed RAM e Block RAM e Distributed ROM e ISERDES e OSERDES e PPC405 e PPC440 e MULT18X18 e DSP48 e MGTs GT GT10 GT11 GTP e SRL16 e EMAC e FIFO 16 18 amp 36 e PCIE e TEMAC Analysis with NET PERIOD When a NET PERIOD constraint is applied to the input clock pad or net this constraint is not translated through the clock modifying block component This can result in zero items or paths analyzed for these constraints The NET PERIOD is analyzed only during MAP PAR and Timing analysis When MAP timing and PAR call the timing tools the timing tools do the clock modifying block manipulation for placement and routing but not for the timing analysis timing reports When a TIMESPEC PERIOD constraint is traced into an input pin on a clock modifying block NGDBuild or the translate process transforms the original TIMESPEC PERIOD constraint into new TIMESPEC PERIOD constraints based upon the derived output clocks The NGDBuild report design b1d indicates this transformation MAP PAR and Timing Analyzer use the new derived clock TIMESPEC PERIOD constraints that are propagated to the Physical Constraints File PCF The original TIMESPEC PERIOD is unchanged during this transformation It is used as a reference for the new TIMESPEC PERIOD constraints www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Constraint System Note Constraints Editor s
156. ord Therefore the clock arrival time for the falling edge synchronous elements ia zero The rising edge synchronous elements is onw half the Timing Constraints User Guide www xilinx com 123 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX PERIOD constraint If both edges are used as in Dual Data Rate two OFFSET constraints are created one for each clock edge In Figure 6 13 Timing Diagram with Two Phase OFFSET IN Constraint the OFFSET requirement is three ns before the initial clock edge If the PERIOD constraint is set to HIGH and the OFFSET IN constraint is set to FALLING the following constraints produce the same example report TIMESPEC TS_clock PERIOD clock 10 ns HIGH 50 OFFSET IN 3 ns BEFORE clock RISING OFFSET IN 3 ns BEFORE clock FALLING Constraint Syntax Example TIMESPEC TS_clock PERIOD clock 10 ns LOW 50 OFFSET IN 3 ns BEFORE clock clock_in 10 ns ans data X11105 Figure 6 13 Timing Diagram with Two Phase OFFSET IN Constraint Timing Report Example Slack 0 231ns requirement data path clock path clock arrival uncertainty Source DataD 9 PAD Destination TmpAa 1 FF Destination Clock clock0 ddr bufg falling at 0 000ns Requirement 3 000ns Data Path Delay 2 492ns Levels of Logic 2 Clock Path Delay 0 038ns Levels of Logic 3 Clock Uncertainty 0 239ns Phase Shifted Example
157. ow to meet these requirements depends on the device and its features You should understand e The device clocking structure e RAM and DSP blocks e Any hard IP contained within the device For more information see the device User Guide Timing constraints communicate all design requirements to the implementation tools This also implies that all paths are covered by the appropriate constraint This chapter provides general guidelines that explain the strategy for identifying and constraining the most common timing paths in FPGA devices as efficiently as possible Timing Constraints User Guide www xilinx com 11 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX Basic Constraints Methodology Timing requirements fall into into several global categories depending on the type of path to be covered The most common types of path categories include e Input paths e Synchronous element to synchronous element paths e Path specific exceptions e Output Paths A Xilinx timing constraint is associated with each of these global constraint types The most efficient way to specify these constraints is to begin with global constraints and add path specific exceptions as needed In many cases only the global constraints are required The FPGA device implementation tools are driven by the specified timing requirements They assign device resources and expend the appropriate amount of effort necessary to ensur
158. pecified it must be less than the period If no High or Low time is specified the default duty cycle is 50 percent hi_lo_units isan optional field to indicate the units for the duty cycle The default is nanoseconds ns but the High or Low time number can be followed by ps micro ms nsor ifthe High or Low time is an actual time measurement Specifying Derived Clocks XCF Syntax Example TIMESPEC TSidentifier PERIOD TNM_reference another_PERIOD_identifier number HIGH LOW high_or_low_time hi_lo_units INPUT_JITTER value where TNM_reference is the identifier name attached to a clock net or a net in the clock path using a TNM constraint another PERIOD identifier is the name of the identifier used on another period specification number is a floating point number Timing Constraints User Guide www xilinx com 75 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX e HIGH or LOW can be optionally specified to indicate whether the first pulse is to be High or Low e high_or_low_time is the optional High or Low time depending on the preceding keyword If an actual time is specified it must be less than the period If no High or Low time is specified the default duty cycle is 50 percent e hi_lo_units is an optional field to indicate the units for the duty cycle The default is nanoseconds ns but the High or Low time number can be followed by ps
159. pin e hierarchical port The following example disables all paths to the falling edge of the flipflops clocked by clk1 and through bit 9 of the hierarchical net define false path to c clk1 f through n MYINST mybus2 9 Path Delay Clock Points When you specify a clock as a romor to point for the path delay constraint the constraint is set on all paths of the registers clocked by the specified clock The following example sets a max delay of 2 ns on all paths to the falling edge of the flip flops clocked by 1k1 define path delay to c clk1 f max 2 You cannot specify a clock as a through point However you can set a constraint rom or toa clock and through an object e net e pin e hierarchical port Timing Constraints User Guide www xilinx com 107 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX The following example sets a max delay of 0 2 ns on all paths from the rising edge of the flip flops clocked by 1k1 and through bit 9 of the hierarchical net define path delay from c clkl r through n MYINST mybus2 9 max 2 Specifying Timing Constraints in a SCOPE Spreadsheet The SCOPE Synthesis Constraints Optimization Environment window is a spreadsheet like interface for entering and managing timing constraints and synthesis attributes To create and open a new SCOPE dialog e Choose File gt New gt Constraint file SCOPE from the Project view
160. point with the through option define path delay through regs mem 2 through prgcntr pc 7 through dmux alub 0 max 5 min 1 Timing Constraints User Guide www xilinx com 105 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX In this example the constraint operates as an AND function and applies to paths through e regs_mem 2 AND e prgcntr pc 7 AND e dmux alub 0 Multiple Lists of Through Points If you specify multiple through lists the constraint e Behaves as an AND OR function e Is applied to the paths through all points in the lists Multiple Lists of Through Points Example One define false path through A1 A2 An through B1 B2 B3 In this example the constraint applies to all paths that pass through e Alor A2or An AND e BlorB2or B3 Multiple Lists of Through Points Example Two define_multicycle_path through net1 net2 through net3 net4 2 In this example all paths that pass through the following nets are constrained at 2 clock cycles netl AND net3 OR net1 AND net4 OR net2 AND net3 OR net2 AND net4 Clocks as From To Points You can specify clocks as rom to points in your timing exception constraints Clocks as From To Points Syntax define timing exception from to c clock_name edge where e timing exception is one of the following constraint types multicycle path false path path delay e c clock_name edge is
161. pril 29 2009 Chapter 3 Timing Constraint Principles XILINX Use a TIG constraint to ignore a path between flopa and lopb passing through net netand See Figure 3 27 Ignore a path between registers To create this from the FROM TO TIG constraint 1 Tag lopa for time group FFA_grp 2 Tag lopb for time group FFB_grp 3 Create the following constraint TIMESPEC TS_FFA_to_FFB FROM FFA_grp TO FFB_grp TIG 30 ns 60 ns NET CLK PERIOD 30ns IN OUT FROM FLOP1 TO FLOP2 30 FROM FLOP2 TO FLOP3 30 5S re CL gt gt b 30 ns 60 ns OUT FROM FLOP2 TO FLOP3 60 D NET CLK PERIOD 30ns X11085 Figure 3 27 Ignore a path between registers If a specific path needs to be constrained at a faster or slower than the PERIOD constraint create a FROM TO for that path If there are multiple paths between a source and destination synchronous elements create a FROM THRU TO constraint to capture specific paths This constraint applies to a specific path that begins at a source time group passes through intermediate points and ends at a destination time group The source and destination time groups can be either user defined or predefined time groups The intermediate points of the path are defined using the TPTHRU constraint There is no limitation on the number of intermediate points in a FROM TO constraint FROM THRU TO Constraint Example Following is an example of
162. raint Increases the amount of time for input signals to arrive at synchronous elements clock and data paths are in parallel Subtracts the clock path delay from the data path delay for inputs Reduces the amount of time for output signals to arrive at output pins clock and data paths are in series Adds the clock path delay to the data path delay for outputs Includes clock phase introduced by a DLL DCM for each individual synchronous element defined by the associated PERIOD constraint Includes clock phase introduced by a rising or falling clock edge The initial clock edge for analysis of OFFSET constraints is defined by the HIGH LOW keyword of the PERIOD constraint HIGH keyword gt the initial clock edge is rising LOW keyword gt the initial clock edge is falling www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Timing Constraints The initial clock edge for analysis of OFFSET constraints can override the PERIOD constraints default clock edge with the following keywords of the OFFSET constraints e RISING keyword gt the initial clock edge is rising e FALLING keyword gt the initial clock edge is falling The OFFSET constraints define the relationship between the external clock pad and the external data pads The common component between the external clock pad and the external data pads are the synchronous elements If the synchronous element is driven by an internal clock n
163. raint is the most efficient way to specify the output timing for the system synchronous interface In the global Timing Constraints User Guide www xilinx com 21 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX method one OFFSET OUT constraint is defined for each system synchronous output interface clock This single constraint covers the paths of all output data bits sent from registers triggered by the specified input clock To specify the output timing e Define a time name INM for the output clock to create a time group which contains all output registers triggered by the input clock e Define the global OFFSET OUT constraint for the interface Example A timing diagram for a System Synchronous SDR output interface is shown in Figure 2 10 Timing diagram for System Synchronous SDR output interface The data in this example must become valid at the output pins a maximum of 5 ns after the input clock edge at the pin of the FPGA device Input Clock Edge I OFFSET OUT AFTER 5ns 1 I Data 1 Valid Data Data 2 I Valid Data X11056 Figure 2 10 Timing diagram for System Synchronous SDR output interface The global OFFSET OUT constraint for the system synchronous interface is OFFSET OUT value AFTER clock In the OFFSET OUT constraint OFFSET OUT lt value gt determines the maximum time from the rising clock edge at the input clock port until the data first becomes
164. re in ns bundle gt bundle value The objects of a bundle must be separated by commas with no spaces between A valid bundle is A B C which lists three signals syn_tpdn VHDL Syntax Examples In VHDL there are ten predefined instances of each of these directives in the synplify library for example syn_tpd1 syn_tpd2 syn tpd3 syn tpd10 If you are entering the timing directives in the source code and you require more than ten different timing delay values for any one of the directives declare the additional directives with an integer greater than ten Timing Constraints User Guide www xilinx com 87 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX attribute syn _tpdl1 string attribute syn tpd11 of bitreg component is di0 dil gt do0 dol 2 0 attribute syn tpd12 string attribute syn tpd12 of bitreg component is di2 di3 gt do2 do3 1 87 The following example assigns syn tpdntogether with some of the black box constraints A USE clause for the Synplify Attributes package was included earlier to make the timing constraint definitions visible here architecture top of top is component rcf16x4z port ad0 adl ad2 ad3 in std logic dio dil di2 di3 in std logic clk wren wpe in std logic tri in std logic do0 dol do2 do3 out std logic end component attribute syn tpdl of rcfl6x4z component is ad0 adi ad2 ad3 g
165. rts p Black box outputs i e to specifies the end point for the multi cycle timing exception The to point defines a timing start point It can be any of the following Clocks c Registers i Top level input or bi directional ports p Black box outputs i through specifies the intermediate points for the timing exception Intermediate points can be Combinational nets n Hierarchical ports t Pins on instantiated cells t By default the intermediate points are treated as an OR list The exception is applied if the path crosses any points in the list For more information see Specify From To Through Points You can combine this option with to or from to get a specific path To keep the signal name intact throughout synthesis when you use this option set the syn_keep directive Verilog or VHDL on the signal e clockCycles is the number of clock cycles to use for the path constraint Timing Constraints User Guide www xilinx com 99 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX Timing exception constraints must contain object types in the specification Timing exceptions such as multi cycle path and false path constraints require that you explicitly specify the object type n or i in the instance name parameter For example define_multicycle_path from i inst2 lowreg_output 7 to i inst1 DATAO 7 2 If you use SCOPE to specify t
166. s e Nested model statements are not supported e Instance or signal names listed between the BEGIN MODEL statement and the END statement are only those visible inside the entity Hierarchical instance or signal names are not supported Enabling the Command Line Switch Timing constraints supported by XST can also be applied using the g1ob opt command line switch Using the g1lob opt command line switch is the same as selecting Process gt Properties gt Synthesis Options gt Global Optimization Goal Using this method allows you to apply global timing constraints to the entire design You cannot specify a value for these constraints XST optimizes them for the best performance These constraints are overridden by constraints specified in the constraints file XST Timing Constraints The sections below give syntax examples for individual Xilinx timing constraints in VHDL Verilog and an XCF file Not all constraints give examples of all three methods e Asynchronous Register ASYNC_REG e Clock Signal CLOCK_SIGNAL e Multi Cycle Path e Maximum Delay MAXDELAY e Maximum Skew MAXSKEW e Offset OFFSET e Period PERIOD e System Jitter SYSTEM_JITTER e Timing Ignore TIG e Time Group TIMEGRP e Timing Specifications TIMESPEC e Timing Name TNM e Timing Name Net INM_NET 64 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April
167. s 5 ns end entity Period PERIOD Verilog Syntax PERIOD applies only to a specific clock signal PERIOD period units where e period is the required clock period e units is an optional field to indicate the units for a clock period The default is nanoseconds ns but the timing number can be followed by ps ns or micro to indicate the intended units 70 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX XST Timing Constraints Period PERIOD Verilog Syntax Example module mig_22 inout 7 0 cntrl10_ddr2_dq output 14 0 cntrl0_ddr2_a input sys_clk_p input sys_clk_n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntrl0_ddr2_dqs MG PERIOD 5 ng wire clk 0 The clk 0 is assigned with the period of 5 ns wire clk 90 wire clk 200 wire read en reg sys rst source code End module TIMESPEC PERIOD XCF Syntax This is the primary method for specifying Period PERIOD XCF syntax Xilinx recommends this version TIMESPEC TSidentifier PERIOD TNM reference period units HIGH LOW high or low time hi lo units INPUT JITTER value units NET PERIOD XCF Syntax This is the secondary method for specifying Period PERIOD XCF syntax Xilinx DOES NOT recommend this version NET net name PERIOD period units HIGH LOW high or low time hi lo units where
168. s The synchronous element clock pin is driven by the same clock net from a DCM DLL PLL PMCD component output The timing analysis tool reports the active edges of the clock and the corresponding time for the data path between the synchronous elements The example in Figure 6 5 CIk0 DCM output schematic shows a CLKO clock circuit with a simple design This clock domain has the same requirement and phase shifting as the original requirement CLKO_DLL X11097 Figure 6 5 Clk0 DCM output schematic Timing Report Example Slack setup path 3 904ns requirement data path clock path skew uncertainty Source IntA_1 FF Destination XorA_1 FF Requirement 8 000ns Data Path Delay 4 036ns Levels of Logic 1 Clock Path Skew 0 000ns Source Clock c1k0 rising at 0 000ns Destination Clock clkO rising at 8 000ns Clock Uncertainty 0 060ns CIk90 Clock Domain Since the clocks produced by the DCM PLL DLL PMCD are related the timing tools take this relationship into consideration during analysis The synchronous element clock pins are driven by different clock nets from a DCM DLL PLL PMCD component outputs The timing analysis tool reports the active edges of the clock and the corresponding time for the data path between the synchronous elements The example in Timing Constraints User Guide www xilinx com 115 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX Figure 6 6
169. s delay specification on the named port e inputportName is the name of the input port e default sets a default input delay for all inputs Timing Constraints User Guide www xilinx com 97 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifying Timing Constraints in Synplify XILINX 98 Use this option to set an input delay for all inputs You can then set define_input_delay on individual inputs to override the default constraint This example sets a default input delay of 3 0 ns define_input_delay default 3 0 This example overrides the default and sets the delay on input_a to 10 0 ns define_input_delay input_a 10 0 e ref recommended is the clock name and edge that triggers the event The value must include either the rising edge or falling edge e r rising edge e f falling edge For example define_input_delay portb 7 0 10 00 ref clock2 f e route is an advanced option thT includes route delay when the synthesis tool tries to meet the clock frequency goal Use the route option on an input port when the place and route timing report shows that the timing goal is not met because of long paths through the input port define_input_delay Syntax Examples define input delay porta 7 0 7 8 ref clki r define_input_delay default 8 0 define_input_delay disable resetn define_io_standard The define_io_standard constraint specifies a standard I O pad type to use for specific Actel Altera and Xilinx device families
170. s the real clock signal Clock Signal CLOCK SIGNAL allows you to define the clock signal Clock Signal CLOCK SIGNAL VHDL Syntax attribute clock signal string attribute clock signal of signal name signal is yes no Timing Constraints User Guide www xilinx com 65 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST Clock Signal CLOCK_SIGNAL VHDL Syntax Example entity top_yann_mem is port cntrl0_DDR2_DQ inout std logic vector 71 downto 0 SYS CLK P in std logic SYS CLK N in std logic CLK200 P in std logic CLK200 N in std logic attribute clock signal string attribute clock signal of clk200 p signal is yes end entity Clock Signal CLOCK SIGNAL Verilog Syntax clock signal yes no Clock Signal CLOCK SIGNAL Verilog Syntax Example module mig 22 inout 7 0 cntrl10 ddr2 dq output 14 0 cntr10 ddr2 a input sys_clk_p input sys_clk_n input c1k200_p input Clk200 n input Sys reset in n inout 0 0 cntrl0_ddr2_dqs clock signal yes wire clk 0 wire clk 90 wire clk 200 reg sys rst source code End module Clock Signal CLOCK SIGNAL XCF Syntax BEGIN MODEL entity name END Clock Signal CLOCK SIGNAL XCF Syntax Example BEGIN MODEL top yann mem NET CLK200 P clock signal yes END Multi Cycle Path NET primary clock signal clock signal yes no true false XILINX
171. sed upon the synchronous element triggered clocking edge rising or falling edges Pattern Matching Pattern matching on either net or instance names can define the user defined time group Use wildcard characters to define a user defined time group of symbols whose associated net name or instance name matches a specific pattern Wildcards are used to generalize the group selection of synchronous elements Wildcards can also be used to shorten and simplify the full hierarchical path to the synchronous elements Pattern matching is as follows e Asterisk Matches any string of zero or more characters e Question Mark Matches a single character Table 3 2 Pattern Matching Examples String Indicates Examples DATA any net or instance namethat DATA1 DATA22 and begins with DATA DATABASE NUMBER any net names that begin NUMBER1 or NUMBERS but with NUMBER and ends with not NUNMBER or NUMBER12 one single character A pattern may contain more than one wildcard character For example AT specifies any net name that e Begins with one or more characters followed by AT and e Ends with any one character www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Constraint System Following are examples of net names included in AT e BAT2 e CAT4 e THATS Time Group Examples Following are time group examples e Time Group Example One Predefined Group of RAMs
172. see Chapter 3 Timing Constraint Principles Timing Ignore TIG XCF Syntax NET net name TIG PIN ff inst RST TIG TS 1 INST instance name TIG TS 2 TIG TSidentifierl TSidentifiern where e identifier refers to a timing specification that should be ignored When attached to an instance TIG is pushed to the output pins of that instance When attached to a net TIG pushes to the drive pin of the net When attached to a pin TIG applies to the pin Timing Constraints User Guide www xilinx com 73 UG612 v 11 1 1 April 29 2009 Chapter 4 Specifying Timing Constraints in XST XILINX Timing Ignore TIG XCF Syntax Example NET main_ 0 top_ 0 ddr2_controller_ 0 load_mode_reg TIG The following statement specifies that the timing specifications TS_fast and TS_even_faster are ignored on all paths fanning forward from the net RESET NET RESET TIG TS_fast TS_even_faster Time Group TIMEGRP Time Group TIMEGRP is a basic grouping constraint In addition to naming groups using the TNM identifier you can also define groups in terms of other groups You can place TIMEGRP constraints in a constraints file such as an XST Constraint File XCF or Netlist Constraints File NCF For more information see Chapter 3 Timing Constraint Principles Time Group TIMEGRP XCF Syntax TIMEGRP newgroup existing_grp1 existing grp2 existing grp3 where e newgroup is a newly creat
173. ser Guide UG612 v 11 1 1 April 29 2009 7 XILINX Input Timing Constraints About Input Timing Constraints Input timing covers the data path from the external pin of the FPGA device to the internal register that captures that data The constraint used to specify the input timing is the OFFSET IN constraint The best way to specify the input timing requirements depends on the type source system synchronous and single data rate SDR or double data rate DDR of the interface The OFFSET IN constraint defines the relationship between the data and the clock edge used to capture that data at the pins of the FPGA device When analyzing the OFFSET IN constraint the timing analysis tools automatically take all internal factors affecting the delay of the clock and data into account These factors include e Frequency and phase transformations of the clock e Clock uncertainties e Data delay adjustments In addition to the automatic adjustments you may also add additional input clock uncertainty to the PERIOD constraint associated with the interface clock For more information on adding INPUT_JITTER see PERIOD Constraints in Chapter 3 Timing Constraint Principles The OFFSET IN constraint is associated with a single input clock By default the OFFSET IN constraint covers all paths from the input pads of the FPGA device to the internal synchronous elements that capture that data and are triggered by the specified OFFSET IN
174. sion of Clock Path Delay The longer the clock path delay the smaller the external setup time becomes The prorated clock path delay is used to obtain an accurate setup time analysis The general prorating factors are 85 for Global Routing and 80 for Local Routing Note The prorated clock path delays are not used for families older than Virtex I device families The equation for external hold included in the OFFSET IN analysis of the FPGA device is External Hold Clock Path Delay Flip Flop Hold time Prorated version of Data Delay If the data delay is longer than the clock delay the result is a smaller hold time The prorated data delays are similar to the prorated values in the setup analysis Note The prorated data delays are not used for families older than Virtex Il device families Simple Example A simple example of the OFFSET IN constraint has an initial clock edge at zero ns based upon the PERIOD constraint The timing report displays the initial clock edge as the Clock Arrival time 122 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX OFFSET IN Constraints The resulting timing report displays the e Data path Clock path e Clock Arrival time shown in bold in the example report below If the timing report does not display a Clock Arrival time then the timing analysis tools did not recognize a PERIOD constraint for that particular synchronous element In Figure 6 1
175. sis traces back Timing Constraints User Guide www xilinx com 111 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILINX through each input of the LUT to the source synchronous elements or pads of the signals and reports the corresponding Clock Skew Note The result of a clock derived from a LUT is that the Clock Skew is very large depending on the levels of logic or number of LUTs If the clock has been divided by using internal logic and not by a DCM the PERIOD constraint on the clock pin of the Divide down Flip Flop does not trace through this flip flop to the CIk_div signal as shown in Figure 6 1 Gated Clock with Divide down Flip Flop Note The timing analysis does not include the downstream synchronous elements which are driven by the new gated clock signal Unless a global buffer is used the new clock derived from the Divide down Flip Flop is on local routing If a PERIOD constraint is placed on the output of the Divide down Flip Flop shown as the clk div signal in Figure 6 1 Gated Clock with Divide down Flip Flop and is related back to the original PERIOD constraint the timing analysis includes the downstream synchronous elements To ensure that the relationship and the cross clock domain analysis is correct the difference between the divided clock and the original clock needs to be included in the PERIOD constraint with the PHASE keyword The Clock Skew can b
176. stem Jitter SYSTEM JITTER sarsies soye srias e 72 System Jitter SYSTEM JITTER VHDL Syntax esee e 72 System Jitter SYSTEM_JITTER VHDL Syntax Example 0 0 00 0c ee eens 72 System Jitter SYSTEM JITTER Verilog Syntax 6 6 eee eee 72 System Jitter SYSTEM JITTER Verilog Syntax Example 000000000 73 System Jitter SYSTEM JITTER XCF Syntax 0 ee ne 73 System Jitter SYSTEM JITTER XCF Syntax Example 0 0 0 eee eee eee 73 Timing Ignore TIG iii zesieku ca es Raed OR GG E CERE KR E Rad 73 Timing Ignore TIG XCF Syntax eese e 73 Timing Ignore TIG XCF Syntax Example sse ee 74 TimeGroup IIMEGRDP cose me ee eem be e e pee eres 74 Time Group TIMEGRP XCF Syntax eseeeeeeeee e en 74 Time Group TIMEGRP XCF Syntax Example sse 74 Timing Specifications TIMESPEC sssssssesessese e 74 Timing Specifications TIMESPEC XCF Syntax esee 74 Timing Specifications TIMESPEC XCF Syntax Examples eese 75 Defining a Maximum Allowable Delay Timing Specifications TIMESPEC XCF Syntax Example sese nnn 75 Defining a Clock Period XCF Syntax Example sese 75 Specifying Derived Clocks XCF Syntax Example ccc cece eee ee 75 Ignoring Paths XCF Syntax Example 1 6 0 eee ne 76 Timing Name INM iiic n ace a e RG eer acera 76 Timing Name INM XCF Syntax sao esrcresa rsads eai nn 76 Timing Name INM XCF Syntax Example
177. subsystem This chapter includes Constraint System Constraint Priorities Timing Constraints Timing Constraint Syntax Creating Timing Constraints Constraint System This section discusses the Constraint System and includes About the Constraint System DLL DCM PLL BUFR PMCD Components Timing Group Creation with TNM TNM_NET Attributes Grouping Constraints About the Constraint System The constraint system is that portion of the implementation tools NGDBUILD that parses and understands the physical and timing constraints for the design The constraint system Parses the constraints from the following files and delivers this information to the other implementation tools NCF XCF Timing Constraints User Guide www xilinx com 27 UG612 v 11 1 1 April 29 2009 28 Chapter 3 Timing Constraint Principles XILINX EDN EDF EDIF NGC NGO e Confirms that the constraints are correctly specified for the design e Applies the necessary attributes to the corresponding elements e Issues error and warning messages for constraints that do not correlate correctly with the design DLL DCM PLL BUFR PMCD Components This section discusses DLL DCM PLL BUFR PMCD Components and includes e About DLL DCM PLL BUFR PMCD Components e Transformation Conditions e New PERIOD Constraints on DCM Outputs e Synchronous Elements e Analysis with NET
178. t but the timing report is specific to your design for a specific pin or synchronous element Setup 0 96ns Hold 0 39ns gt Data must be Valid Setup and Hold Times With Respect to Clock at IOB input Register Pad no delay Tiopick Tioickp Al 0 88 0 39 0 96 0 39 1 11 0 45 X11077 Figure 3 17 Setup Hold times from Data Sheet OFFSET Constraints This section discusses OFFSET Constraints and includes e About OFFSET Constraints e Paths Covered by OFFSET Constraints About OFFSET Constraints The OFFSET constraint is a fundamental timing constraint OFFSET constraints are used to define the timing relationship between an external clock pad and its associated data in or data out pad This relationship is also known as constraining the Pad to Setup or Clock to Out paths on the device These constraints are important for specifying timing interfaces with external components Note The pad to Setup OFFSET IN BEFORE constraint allows the external clock and external input data to meet the setup time on the internal flip flop Note The Clock to Out OFFSET OUT AFTER constraint gives you more control over the setup hold requirement of the downstream devices and with respect to the external output data pad and the external clock pad The OFFSET IN BEFORE and OFFSET OUT AFTER constraints allow you to specify the internal data delay from the input pads or to the output pads with respect to the clock Alternati
179. t do0 do1 do2 do3 2 1 attribute syn tpd2 of rcf16x4z component is tri gt do0 do1 do2 do3 2 0 s attribute syn tsul of rcfl6x4z component is ad0 ad1 ad2 ad3 gt clk 1 2 attribute syn_tsu2 of rcfl6x4z component is wren wpe gt clk 0 0 Other code sdc File Syntax define_attribute v blackboxModule syn_tpdn bundle gt bundle value where e vs indicates that the directive is attached to the view e blackboxModule is the symbol name of the black box e nis anumerical suffix that lets you specify different input to output timing delays for multiple signals bundles bundle isa collection of buses and scalar signals The objects of a bundle must be separated by commas with no intervening spaces A valid bundle is A B C which lists three signals e value is input to output delay value in ns sdc File Syntax example define attribute v MEM syn_tpdl MEM_RD gt DATA_OUT 63 0 20 syn tcon The syn tcon directive supplies the clock to output timing delay through a black box The syn tcon directive can be entered as an attribute using the Attribute panel of the SCOPE editor The information in the object attribute and value fields must be manually entered 88 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in HDL syn_tcon Verilog Syntax object syn tcon clock gt bundle value where e
180. t a rate less than the clock frequency defined in the PERIOD specification This occurs most often when the synchronous elements are gated with a common clock enable signal By defining a multi cycle path the timing constraints for these synchronous elements are relaxed over the default PERIOD constraint The multi cycle path constraint can be defined with respect to the PERIOD constraint identifier PS c1 amp k125 and state the multiplication or the number of period cycles TS c1k125 3 The implementation tools are then able to appropriately prioritize the implementation of these paths One common way to specify the set of multi cycle paths is to define a time group using the clock enable signal This allows you to e Define one time group containing both the source and destination synchronous elements using a common clock enable signal e Automatically apply the multi cycle constraint to all paths between these synchronous elements To specify the FROM TO multi cycle constraint for this method define e A PERIOD constraint for the common clock domain e Asetofregisters based on a common clock enable signal e AFROM TO multi cycle constraint describing the new timing requirement Timing Constraints User Guide www xilinx com 25 UG612 v 11 1 1 April 29 2009 26 Chapter 2 Timing Constraint Methodology XILINX Example Figure 2 14 Path between two registers clocked by a common clock enable signal shows a hypothetic
181. tax Example OFFSET IN 2 ns BEFORE CLK200_N OFFSET IN 3 85 ns BEFORE SYS CLK P OFFSET OUT 4 ns AFTER CLK200_N OFFSET OUT 7 ns AFTER SYS CLK P NET main 00 top 00 iobs 00 data path iobs 00 v4 dq iob 0 DDR DQ TNM DDR2 DQ Grp OFFSET OUT 6 7 ns AFTER SYS CLK P TIMEGRP DDR2 DQ Grp OFFSET IN 3 2 ns BEFORE SYS CLK P TIMEGRP DDR2 DQ Grp Period PERIOD Period PERIOD is a basic timing constraint and synthesis constraint A clock period specification checks timing between all synchronous elements within the clock domain as defined in the destination element group The period specification is attached to the clock net The timing analysis tools automatically take into account any inversions of the clock net at register clock pins clock phase and includes all synchronous item types in the analysis It also checks for hold violations For more information see Chapter 3 Timing Constraint Principles Period PERIOD VHDL Syntax Period PERIOD applies only to a specific clock signal attribute period string attribute period of signal name signal is period units Period PERIOD VHDL Syntax Example entity top yann mem is port ecntrl0 DDR2 DO inout std logic vector 71 downto 0 SYS CLK P in std logic SYS CLK N in std logic CLK200 P in std logic CLK200 N in std logic attribute period string attribute period of SYS CLK P signal i
182. ter 5 Specifying Timing Constraints in Synplify XILINX If there are multiple timing exception constraints on the same object the synthesis tool uses the guidelines described in Conflict Resolution for Timing Exceptions in the Synplify Reference Guide to determine which constraint takes precedence Table 5 1 Constraint Types for Each Timing Constraint Entry in Synplify lists the timing constraints and related commands in alphabetical order according to the methods used to enter them The timing constraints for HDL are all directives Table 5 1 Constraint Types for Each Timing Constraint Entry in Synplify HDL Tcl sdc File SCOPE black_box_tri_pins define_clock Clocks Panel define_ clock_delay Clock to Clock Panel define compile point Compile Points Panel define current design define false path False Paths Panel define input delay Inputs Outputs Panel define io standard I O Standard Panel define multicycle path Multicycle Paths Panel define output delay Inputs Outputs Panel define path delay Max Delay Paths Panel define reg input delay Registers Panel define reg output delay Registers Panel syn force seq prim syn gatedclk clock en syn gatedclk clock en pol arity syn isclock syn tpdn syn tcon syn tsun This constraint is available in Synpl
183. the elements of smaller grp TIMEGRP all except mem and latches grp overall grp EXCEPT memory and latch grp Removes the common elements between memory and latch grp and overall grp Time Group Example Six Clock Edges Following is an example of defining a sub group based upon the triggering clock edge TIMEGRP rising clk grp RISING clk grp Creates a time group rising clk grp and includes all the rising edged synchronous elements of clk_grp TIMEGRP rising clk grp FALLING clk grp Creates rising clk grpand includes all the falling edged synchronous elements of Clk grp Constraint Priorities During design analysis the timing analysis tools determine which constraint analyzes which path Each constraint type has different priority levels Following are the constraint priorities from highest to lowest Timing Ignore TIG FROM THRU TO 44 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Constraint Priorities Source and Destination are User Defined Groups Source or Destination are User Defined Groups Source and Destination are Pre defined Groups e FROM TO Source and Destination are User Defined Groups Source or Destination are User Defined Groups Source and Destination are Pre defined Groups e OFFSET Specific Data IOB NET OFFEST Time Group of Data IOBs Grouped OFFSET All Data IOBs Global OFFSET e PERIOD Note This deter
184. the name of the clock and clock edge r or If you do not specify a clock edge both edges are used by default 106 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 XILINX Specifying Timing Constraints in an SDC File TCL Multi Cycle Path Clock Points When you specify a clock as a rom or to point the multicycle path constraint applies to all registers clocked by the specified clock The following example allows two clock periods for all paths from the rising edge of the flip flops clocked by 1k1 define multicycle path from c clk1 r 2 You cannot specify a clock as a through point However you can set a constraint rom or to a clock and through an object e net e pin e hierarchical port The following example allows two clock periods for all paths to the falling edge of the flip flops clocked by 1k1 and through bit 9 of the hierarchical net define multicycle path to c clk1 f through n MYINST mybus2 9 2 False Path Clock Points When you specify a clock as a rom or to point the false path constraint is set on all registers clocked by the specified clock The timing analyzer ignores all false paths The following example disables all paths from the rising edge of the flip flops clocked by c1k1 define false path from c c1k1 r You cannot specify a clock as a through point However you can set a constraint rom or toa clock and through an object e net e
185. the synchronous and asynchronous paths to this RAM For example a path from an FF to the D input of this RAM is a synchronous path Constraining this data path is covered by a PERIOD or a FROM TO constraint A path from a flip fop to the DPRA input of this RAM is an asynchronous path to the read address input and is covered only by a FROM TO constraint Timing Constraint Syntax The grouping constraint syntax is conversational and easy to understand For more information see the TNM TNM_NET and TIMEGRP constraints in the Constraints Guide The PERIOD constraint syntax is conversational and easy to understand For more information see the PERIOD constraint in the Constraints Guide The OFFSET IN OUT constraint syntax is conversational and easy to understand For more information see the OFFSET constraint in the Constraints Guide The multicycle constraint syntax is conversational and easy to understand For more information see the FROM TO Multicycle constraint in the Constraints Guide Creating Timing Constraints Timing constraints are added to the design in two methodologies e Add timing constraints through the HDL design Specifying Timing Constraints in XST Specifying Timing Constraints in Synplify e Add timing constraints through Constraints Editor UCF The Constraints Editor uses the design information from the NGD file to create constraints in the UCF Since Constraints Editor parses the NGD file for the
186. tured in registers triggered by the specified input clock edge To specify the input timing e Define the clock PERIOD constraint for the input clock associated with the interface e Define the global OFFSET IN constraint for the rising edge RISING of the interface e Define the global OFFSET IN constraint for the falling edge FALLING of the interface Example A timing diagram for an ideal Source Synchronous DDR interface is shown in Figure 2 4 Timing diagram for ideal Source Synchronous DDR The interface has a clock period of 5 ns with a 50 50 duty cycle The data for both bits of the bus remains valid for the entire 15 period EE T l OFFSET IN OFFSET IN A I 125ns gt 2125ns li ASS AAA li 1 l 1 1 lu 1 VALID 2 5 ns VALID 2 5 ns Figure 2 4 Timing diagram for ideal Source Synchronous DDR Timing Constraints User Guide www xilinx com 15 UG612 v 11 1 1 April 29 2009 Chapter 2 Timing Constraint Methodology XILINX The global OFFSET IN constraint for the DDR case is OFFSET OFFSET IN value VALID value BEFORE clock RISING IN value VALID value BEFORE clock FALLING In the OFFSET IN constraint OFFSET IN lt value gt determines the time from the capturing clock edge in which data first becomes valid In this source synchronous input example the rising data becomes valid 1 25 ns prior to the rising clock edge The falling data also becomes vali
187. uide The synthesis tool constrains input to register register to register and register to output paths with the FREQUENCY constraint However if the PERIOD constraint is too tight for the input to register or register to output paths the synthesis tool tries to relax the constraints to these paths Digital Clock Manager Delay Locked Loop The synthesis tool can take advantage of the Frequency Synthesis and Phase Shifting features of Digital Clock Manager DCM and Delay Locked Loop DLL for Xilinx devices If you are using a DLL or DCM for on chip clock generation you need only define the clock at the primary inputs The synthesis tool propagates clocks through any number of DLLs or DCMs It automatically generates clocks at the outputs of a DLL or DCM as needed taking into account any phase shift or frequency change To specify the phase shift and frequency multiplication parameters use Xilinx standard properties such as e duty_cycle_correction e clkdv_divide e clkfx multiply e clkfx divide The synthesis tool also takes into account the fact that these clocks are related synchronized to each other and puts them in the same clock group However only the clock at the input of a DLL DCM is forward annotated in the ncf file The back end tools understand the DLL and DCMs and do their own clock propagation across them Timing Constraints User Guide www xilinx com 109 UG612 v 11 1 1 April 29 2009 Chapter 5 Specifyin
188. up relationship TData TSetup TClock lt Toffset_IN_BEFORE where TSetup Intrinsic Flip Flop setup time TClock Total Clock path delay to the Flip Flop TData Total Data path delay from the Flip Flop Toffset_IN_BEFORE Overall Setup Requirement The OFFSET IN requirement value is used as a setup time requirement of the FPGA device during the setup time analysis The VALID keyword is used in conjunction with the requirement to create a hold time requirement during a hold time analysis The VALID keyword specifies the duration of the incoming data valid window and the timing analysis tools do a hold time analysis By default the VALID value is equal to the OFFSET time requirement which specifies a zero hold time requirement see Figure 6 11 OFFSET IN Constraint with VALID Keyword If the VALID keyword is not specified no hold analysis is done by default In order to receive hold analysis without the VALID keyword use the fastpaths option trce fastpaths during timing analysis The following equation defines the hold relationship TClock TData Thold lt Toffset_IN_BEFORE_VALID where Thold Intrinsic Flip Flop hold time TClock Total Clock path delay to the Flip Flop TData Total Data path delay from the Flip Flop Toffset_IN_BEFORE_VALID Overall Hold Requirement Timing Constraints User Guide www xilinx com 121 UG612 v 11 1 1 April 29 2009 Chapter 6 Timing Constraint Analysis XILI
189. using when reviewing the slack and the minimum delay NS period for the constraint The hold slack is related to the relationship between the clock skew and the data path delay Only the slack from setup paths affects the minimum delay ns period for the constraint The FROM TO constraint requirement should account for any known external skew between the clock sources if the endpoint registers do not share a common clock or the clocks are unrelated to each other If the registers share any single common clock source the skew is calculated only for the unique portions of the clock path to the synchronous elements If no common clock source points are found the skew is the difference between the maximum and minimum clock paths The clock skew is reported in the path header but the delay details to the source clock pin and destination clock pin are not included To determine these delays use Analyze Against User Specified Paths by defining Endpoints in Timing Analyzer Specify the clock pad input as the source Specify the registers or synchronous elements in the hold setup analysis as the destination The clock delay from the pad to each register clock pin is reported This custom analysis also works for DLL DCM PLL clock paths To obtain the clock skew subtract the destination clock delay from the source clock delay The paths are sorted by total path delay and not slack Example One Constrain the DOS path from an IDDR to the DQ CE pins to
190. vecade sugges nin aa edente 90 syn_tcon sdc File Syntax Example 6 ccc eee eens 91 SVD ISU AA Vad Oho A Pe hea Sy tie T 91 syn tsun Verilog Syntax it cee hice dae ees EN PE Ct RT ao ak 91 syn tsun Verilog Syntax Example csse en 9 syn tsun VADE SYNTAX sacs dates tio rco cete eed e adea des apod 91 syn_tsun VHDL Syntax Examples csse ne 92 Syl tsun sde File Syntax rra curi A AAA ede ea 92 syn tsun sdc File Syntax Example cse e 93 Specifying Timing Constraints in an SDC File TCL 93 define clock A 93 define clock Syntax 24e tne s e es eR Rm quete uem eque ra a Ra 93 define clock Syntax Examples esee nen 95 define Clock delay ee eoi dt eer etre d descend a eden bung Melee 95 define clock delay Syntax ii i ede bb aderit e e hereto ber 95 define clock delay Syntax Example lesse 95 define compile point baa sek et a erben 95 define compile pointSyntax c l nn 95 define compile point Syntax Example 0 0 6 96 Timing Constraints User Guide www xilinx com UG612 v 11 1 1 April 29 2009 define current design iss e cris ber RE WP pP E LEN REY 96 define current design Syntax o ooocooccoccoocnonccrcon na 96 define current design Syntax Example sese 96 define false path isses sente rer I her eei rd Eee ERE e E een 96 define false path Syntax osos dkbeso baiana capa 96 define false path Syntax Example lees ee 97 d
191. vely the OFFSET IN AFTER and OFFSET OUT BEFORE constraints allow you to specify external data and clock relationship for the timing on the path to the input pads and to the output pads for the Xilinx device The timing software determines the internal requirements without the need of a FROM PADS TO FFS or FROM FFS TO PADS constraint Timing Constraints User Guide www xilinx com 51 UG612 v 11 1 1 April 29 2009 Chapter 3 Timing Constraint Principles XILINX 52 For examples see Figure 3 18 Timing Reference Diagram of OFFSET IN Constraint Figure 3 19 Timing Reference Diagram of OFFSET OUT Constraint T IN_AFTER TIN BEFORE gt DATA IN Tp CLK SYS l l X11078 Figure 3 18 Timing Reference Diagram of OFFSET IN Constraint Tour BEFORE Q OUT X11079 Figure 3 19 Timing Reference Diagram of OFFSET OUT Constraint The OFFSET constraint Includes clock path delay in the analysis for each individual synchronous element Includes paths for all synchronous element types FFS RAMS LATCHES etc Allows a global syntax that allows all inputs or outputs to be constrained with respect to an external clock Analyzes setup and hold time violation on inputs The OFFSET constraint automatically accounts for the following clocking path delays when defined and analyzed with the PERIOD constraint Provides accurate timing information and uses the jitter defined on the associated PERIOD const
192. yclk signal is true Other code 86 www xilinx com Timing Constraints User Guide UG612 v 11 1 1 April 29 2009 7 XILINX Specifying Timing Constraints in HDL syn_tpdn The syn_tpdn directive supplies information on timing propagation for combinational delay through a black box The syn_tpdn directive can be entered as an attribute using the Attribute panel of the SCOPE editor The information in the object attribute and value fields must be manually entered syn_tpdn Verilog Syntax object syn tpdn bundle gt bundle value where e bundle is a collection of buses and scalar signals To assign values to bundles use the following syntax The values are in ns bundle gt bundle value The objects of a bundle must be separated by commas with no intervening spaces A valid bundle is A B C which lists three signals syn_tpdn Verilog Syntax Example The following example defines syn_tpdn along with other black box timing constraints module ram32x4 z d addr we clk synthesis syn_black_box syn_tpdl addr 3 0 gt z 3 0 8 0 syn_tsul addr 3 0 gt clk 2 0 syn_tsu2 we gt clk 3 0 output 3 0 z input 3 0 d input 3 0 addr input we input clk endmodule syn tpdn VHDL Syntax attribute syn_tpdn of object objectType is bundle gt bundle value f where e bundle is a collection of buses and scalar signals To assign values to bundle use the following syntax The values a
193. yn_t sun directive can be entered as an attribute using the Attribute panel of the SCOPE editor The information in the object attribute and value fields must be manually entered syn_tsun Verilog Syntax object syn_tsun bundle gt clock value where e bundle is a collection of buses and scalar signals To assign values to bundles use the following syntax The values are in ns bundle gt clock value e is an optional exclamation mark indicating a negative edge for a clock The objects of a bundle must be separated by commas with no spaces between A valid bundle is A B C which lists three signals syn_tsun Verilog Syntax Example The following example defines syn_tsun together with other black box constraints module ram32x4 z d addr we clk synthesis syn_black_box syn_tpdl addr 3 0 gt z 3 0 8 0 syn_tsul addr 3 0 gt clk 2 0 syn_tsu2 we gt clk 3 0 output 3 0 z input 3 0 d input 3 0 addr input we input clk endmodule syn_tsun VHDL Syntax attribute syn_tsun of object objectType is bundle gt clock value In VHDL there are ten predefined instances of each of these directives in the synplify library for example syn_tsul syn tsu2 syn tsu3 syn_tsul0 If you are entering the timing directives in the source code and you require more than ten different timing delay values for any one of the directives declare the additional directives with an int

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