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Version 2.0 User's Guide - Computer Science and Engineering

1. sc_in lt bool gt clock sc_in lt bool gt reset Sc in bool din Sc out bool dout void do ffa if reset dout false else if clock event dout din SC CTOR dffa SC_METHOD do_ffa sensitive reset sensitive pos clock Shifter The next few examples add more complexity This module implements a very basic 8 bit shifter block the shifter can be loaded with a new value by placing a value on input din setting input load to 1 and causing a positive edge to occur on input clk The shifter will shift the data left or right depending on the value of input LR If LR equals 0 the shifter will shift its contents right by 1 bit If LR equals 1 the shifter will shift its contents left by 1 bit 166 SystemC 2 0 User s Guide Shifter Here is the VHDL description library ieee use ieee std logic 1164 11 entity shift is port din in std logic vector 7 downto 0 clk in std logic load in std logic LR in std logic dout inout std logic vector 7 downto 0 end shift architecture rtl of shift is signal shiftval std logic vector 7 downto 0 begin nxt process load LR din dout begin if load 1 then shiftval lt din elsif LR 70 then shiftval 6 downto 0 lt dout 7 downto 1 shiftval 7 lt 70 elsif LR 71 then shiftval 7 downto 1 lt dout 6 downto 0 shiftval 0 lt 0
2. gt The figure above shows a fifo module with a number of ports The ports on the left are input ports or inout ports while the ports on the right are output ports Each port has an identifying name Graphic symbols like the one shown above typically do not contain port types so it is not clear from the symbol which port types are present The SystemC description of these ports is shown below SC_MODULE fifo sc_in lt bool gt load 40 SystemC 2 0 User s Guide Module Signals sc in bool read sc inout int data sc_out lt bool gt full sc_out lt bool gt empty rest of module not shown Each port on the block diagram has a matching port statement in the SystemC description Port modes sc_in sc_out and sc_inout are predefined by the SystemC class library Module Signals Signals can be local to a module and are used to connect ports of lower level mod ules together These signals represent the physical wires that interconnect devices on the physical implementation of the design Signals carry data while ports deter mine the direction of data from one module to another Signals aren t declared with a mode such as in out or inout The direction of the data transfer is dependent on the port modes of the connecting components FIGURE 1 Filter Design Sample f 5 L din dou sl Mult q q Coeff ep b mi out cl
3. Data Types In the first example a range of a large sc bv object is assigned a smaller sc bv object In the second example a small sc bv object is assigned the concatenation of two fields from a larger bv object In the final example a concatenated range of a smaller bv object is assigned a range from a large bv object The operations supported by bv are shown in the table below TABLE 6 Arbitrary Length Bit Vector Operators Bitwise amp lt lt gt gt Assignment amp l A Equality l Bit Selection x Part Selection range Concatenation Reduction and reduce or reduce xor reduce A single bit can be selected from an bv object using the bit selection operator An example is shown below sc bit y sc bv 8 x y 6 More than one bit can be selected using part selection Part selection uses the range function to specify the range of bits to select An example is shown below Sc bv 16 x sc bv 8 5 y y x range 0 7 Notice that bv types cannot have arithmetic performed directly on them To per form arithmetic functions first assign sc bv objects to the appropriate SystemC integer Perform the arithmetic operation on the integer type If the application war 94 SystemC 2 0 User s Guide Arbitrary Length Logic Vector rants then copy the results of the arithmetic operations back to the sc bv type The operator is
4. case main st if key 71 next state review st else if key 72 next_state send_st else next_state main_st break case review_st if key 71 next state repeat st else if key 72 1 next_state save_st else if key 73 1 next_state erase_st SystemC 2 0 User s Guide 193 else if key next_state main_st else next state review st break case repeat_st play SC LOGIC 1 next state review st break case save st save SC LOGIC 1 next state review st break case erase st erase SC LOGIC 1 next state review st break case send st next state address st break case address st address SC LOGIC 1 if key next_state record_st else next_state address_st break case record_st if key 75 1 194 SystemC 2 0 User s Guide Memory next state else next_state record_st break begin_rec_st case begin_rec_st recrd SC_LOGIC_1 next_state message_st break case message_st recrd SC_LOGIC_1 if key next_state send_st else next_state message_st break end switch end method void stmach setstate current state next state Memory The last module is a very simple memory model The memory device has an enable port to a
5. framenum 1 retry 0 start false buffer get data fromApp transmit cc include transmit h input port input port output port output port Method Process int transmit get_data_fromApp int result SystemC 2 0 User s Guide Transmit Module result rand cout lt lt Generate Sending Data Value result Xo return result void transmit send data if timeout s info buffer s seq framenum Si EeUtry retry retrytt tpackout s start_timer true cout lt lt Transmit Sending packet no lt lt s seq x CART else packin tpackin if packin tpackold if packin seq framenum buffer get data fromApp retry 0 tpackold tpackin s info buffer s seq framenum S retty retry retrytt tpackout s start_timer true cout lt lt Transmit Sending packet no lt lt s seq lt lt NS Module SystemC 2 0 User s Guide 19 Starting with a Simple Example A module is the basic container object for SystemC Modules include ports con structors data members and function members A module starts with the macro SC MODULE and ends with a closing brace A large design will typically be divided into a number of modules that represent logical areas of functionality of the design Ports Module transmit has three input one output and one
6. An executable specification ensures unambiguous interpretation of the specifi cation Whenever implementers are in doubt about the design they can run the executable specification to determine what the system is supposed to be doing Anexecutable specification helps validate system functionality before imple mentation begins An executable specification helps create early performance models of the sys tem and validate system performance The testbench used to test the executable specification can be refined or used as is to test the implementation of the specification This can provide tremendous benefits to implementers and drastically reduce the time for implementation verification SystemC 2 0 User s Guide SystemC Highlights SystemC Highlights SystemC supports hardware software co design and the description of the architec ture of complex systems consisting of both hardware and software components It supports the description of hardware software and interfaces in a C environ ment The following features of SystemC version 2 0 allow it to be used as a co design language Modules SystemC has a notion of a container class called a module This is a hierarchical entity that can have other modules or processes contained in it Processes Processes are used to describe functionality Processes are contained inside modules SystemC provides three different process abstractions to be used by hardware and
7. C C Model C C Model An example model that implements this system in C C is shown below frame data global data frame storage for Channel void transmit void Transmits frames to Channel int framenum sequence number for frames frame s Local frame packet buffer Buffer to hold intermediate data event t event Event to trigger actions in transmit framenum 1 initialize sequence numbers get data fromApp amp buffer Get initial data from Application while true s info buffer Put data into frame to be sent s seq framenum Set sequence number of frame send_data_toChannel amp s Pass frame to Channel to be sent start timer s seq Start timer to wait for acknowledge If timer times out packet was lost wait for event amp event Wait for events from channel and timer if event new frame Got an event check which kind get data fromChannel s Read frame from channel if s ack framenum Did we get the correct acknowledge get data fromApp amp buffer Yes then get more data from application else send old packet again inc framenum Increase framenum for new frame SystemC 2 0 User s Guide Starting with a Simple Example void receiver void int framenum frame r S event t event framenum 1 while true Gets frames from channel Scratchpad frame n
8. J jump out of aloop 64 L learning SystemC 2 local data members 20 SystemC 2 0 User s Guide local methods 54 local variables 44 local watching 67 logic vector 95 resolved 75 values 95 loop exit 64 M mapping named 43 positional 42 MAX NBITS 91 memory 178 195 memory initialization 48 method 47 delayed 64 65 to_string 97 method process 54 methods local 54 mode port 40 module 3 constructors 47 instance 47 instance name 48 instantiation 49 lower level 42 ports 40 processes 46 signals 41 top level 43 module instantiation 79 module pointer declarations 43 multiple driver 76 multiple driver resolution 75 N named binding port 79 named mapping 43 object clock 62 80 operator auto decrement 89 autoincrement 89 concatenation 89 overloading 98 operator overloading 16 output port 40 overloaded operator 16 overloading operator 98 overloading equals 16 P part select 93 port 3 array port 74 binding 72 inout 40 71 input 71 mode 71 named binding 79 output 40 71 scalar 73 special case binding 72 78 value 72 port binding special case 72 port declaration syntax 73 port mode 40 port statement 41 port types C 73 SystemC 73 Ports module 40 ports 71 positional mapping 42 process 3 activation 62 basic 54 clocked thread 59 method 54 registration 46 SystemC 2 0 User s Guide iii sensitivity 47 sensitivity list 56 thread 56
9. Sc fixed 32 3 SC RND SC WRAP Output Sc fixed 4 2 SC RND SC WRAP pstate Sc fixed 32 0 SC RND SC WRAP pcoeff Sc fixed 32 3 SC RND SC WRAP sum int i FIR filter output pcoeff amp coeff 0 pstate amp state 0 sum pcoeff Input for i 0 i NumberOfCoefficients 1 1 sum sum pcoefftt pstatet Output sum shift state pstate amp state NumberOfCoefficients 2 pcoeff pstate 1 for i 0 i lt NumberOfCoefficients 2 pstat pcoeff pstate Input return Output SystemC 2 0 User s Guide 151 Fixed Point Types 152 SystemC 2 0 User s Guide CHAPTER 8 Simulation and Debugging Using SystemC After you write a system description in SystemC you typically want to simulate it as the next step in the design flow This chapter describes the simulation control facilities provided by SystemC to start and stop a simulation query the current time and understand the order in which various processes are executed Writing a system description in SystemC gives you the advantage of using standard C development tools for compiling and debugging This chapter describes the additional facilities that can help you debug SystemC programs Advanced Topic SystemC Scheduler NOTE This section is outdated For up to date information please refer to Section 5 3 in the Functional Specificat
10. When the operator is used any extra bits are removed and sign bits are added and extended as necessary An example is shown below SC uint 8 uintl uint2 sc int 16 intl int2 uintl int2 convert int to uint intl uint2 convert uint to int In the first statement an integer is converted to an unsigned integer The absolute value of int2 will be assigned to uintl If int2 is a negative value only the magnitude will be assigned to uint1 Since int2 is 16 bits while uintl is 8 bits uint2 will be con verted to a 64 bit unsigned number and then truncated to 8 bits before assignment to uintl In the second statement uint2 is assigned to intl First uint2 will be converted to a 64 bit signed value then truncated and assigned to intl Type int and uint can be used with C integer types without restriction C integer types can be freely mixed with SystemC types Speed Issues As previously mentioned when SystemC integers are used 64 bits of precision are used However if no more than 32 bits are ever needed simulation speed can be 90 SystemC 2 0 User s Guide Arbitrary Precision Signed and Unsigned Integer Types increased by using 32 bits for the underlying precision This is accomplished by compiling with a special compiler flag D 32BIT This compile flag will limit the size of the underlying arithmetic precision to 32 bits instead of 64 Arbitrary Precision Signed and Unsigned Intege
11. end if end process end rtl SystemC Implementation The SystemC implementation of the shifter uses process shifty to perform the shift ing and loading operations This process is an SC METHOD process sensitive only to the positive edge of input clk A designer could use an SC_CTHREAD process for this example and the behavior would be the same However and SC_CTHREAD process is less efficient and the simulation will run slower SystemC 2 0 User s Guide 167 Whenever the clock has a positive edge process shifty will activate and check the value of input load If load is 1 the current value of din is assigned to shiftval the local value of the shifter at all times Local value shiftval is needed because the value of output ports cannot be read Notice that at the end of the process shiftval is assigned to dout If load is not active the process will check the value of input LR and perform the appropriate action based on the value of LR To perform the actual shifting opera tion notice that process shifty uses the range method Here is the SystemC implementation shift h include systemc h SC MODULE shift Sc lt 5 bv 8 gt din Sc in bool clk sc_in lt bool gt load sc_in lt bool gt LR sc_out lt sc_bv lt 8 gt gt dout sc_bv lt 8 gt shiftval void shifty SC_CTOR shift SC METHOD shifty sensitive_pos clk shift cc include shift h void
12. SYSTEMC Version 2 0 User s Guide Update for SystemC 2 0 1 Copyright c 1996 2002 by all Contributors All Rights reserved Copyright Notice Copyright c 1996 2002 by all Contributors All Rights reserved This software and documentation are furnished under the SystemC Open Source License the License The software and documentation may be used or copied only in accordance with the terms of the License agreement Right to Copy Documentation The License agreement permits licensee to make copies of the documentation Each copy shall include all copyrights trademarks service marks and proprietary rights notices if any Destination Control Statement All technical data contained in this publication is subject to the export control laws of the United States of America Disclosure to nationals of other countries contrary to United States law is prohibited It is the reader s responsibility to determine the applicable regulations and comply to them Disclaimer THE CONTRIBUTORS AND THEIR LICENSORS MAKE NO WARRANTY OF ANY KIND WITH REGARD TO THIS MATERIAL INCLUDING BUT NOT LIMITED TO THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE Trademarks SystemC and the SystemC logo are trademarks of Synopsys Inc Bugs and Suggestions Please report bugs and suggestions about this document to http www systemc org Contents CHAPTER 1 CHAPTER 2 Introduction I Using Executable Specif
13. This quantization mode will perform an SC RND operation if the two nearest rep resentable numbers are not an equal distance apart Otherwise rounding to zero will be performed For positive numbers this means that the redundant bits are simply deleted For negative numbers the MSB of the deleted bits is added to the remain ing bits A graph showing this effect is shown below 4 3q 7 2q 2 e lt q 2q 3q x 4 2 The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SC RND ZERO Examples Two exampes are shown below The first shows quantization of a positive number and the second the quantization of a negative number sc fixed 4 2 x Sc fixed 3 2 SC RND ZERO y x 1 25 108 SystemC 2 0 User s Guide SC RND ZERO y x quantization occurs here 01 01 1 25 value of x after assignment 01 0 1 quantized value of y Value 1 25 is outside the representation range of sc_fixed lt 3 2 SC_RND_ZERO gt so quantization will be performed Since this is a positive number the redundant bits are simply deleted The next example shows the same types with a negative number Sc fixed 4 2 x Sc fixed 3 2 SC RND ZERO y 1 25 x quantization occ
14. erase_st else if key next_state main_st else next_state review_st break case repeat_st play SC_LOGIC_1 next_state review_st break 176 SystemC 2 0 User s Guide State Machine case save st save SC LOGIC 1 next state review st break case erase st erase SC LOGIC 1 next state review st break case send st next state address st break case address st address 5 LOGIC 1 if key next_state record_st else next_state address_st break case record_st if key 75 1 next_state begin_rec_st else next_state record_st break case begin_rec_st recrd SC_LOGIC_1 next_state message_st break case message_st recrd SC_LOGIC_1 if key next_state send_st else SystemC 2 0 User s Guide 177 next state message st break end switch end method void stmach setstate current_state next_state Memory The last module is a very simple memory model The memory device has an enable port to activate the device and a readwr port to determine whether or not the device is being written to or read from The memory module has a single data inout bus that either delivers the addressed item or accepts data to write to a location When the enable input is 0 the output of the ram device will be all Z hi impedance a
15. If a different priority is needed then local watching blocks will need to be nested Local watching only works in SC CTHREAD processes e The signals in the watching expressions are sampled only on the active edges of the process In an SC CTHREAD process this means only when the clock that the process is sensitive to changes e Globally watched events have higher priority than locally watched events To show an example of local watching let s modify the microcontroller bus exam ple from the SC CTHREAD description on page 60 and allow the bus controller to be interrupted during the memory to databus transfer but not during the databus to memory transfer We will add local watching to the second part of the while loop where data is transferred from the memory to the databus The new example is shown below watchbus cc include bus h void bus xfer while true wait for a new address to appear wait until newaddr delayed true got a new address so process it taddr addr datardy false cannot accept new address now data8 taddr range 7 0 68 SystemC 2 0 User s Guide Local Watching start true new addr for memory controller wait wait 1 clock between data transfers data8 taddr range 15 8 start false wait data8 taddr range 23 16 wait data8 taddr range 31 24 now wait for ready signal from memory controller wait until ready
16. SystemC 2 0 User s Guide 41 Modules and Hierarchy The example in Figure 1 shows the data path of a simple filter design There are three lower level modules instantiated in the filter design sample coeff and mult modules The module ports are connected by three local signals q s and c Note Instantiation means that an instance of an object is created It is the same as declaring a new object in Positional Connection There are two ways to connect signals to ports in SystemC named mapping positional mapping First let s examine the example in Figure 1 using positional mapping The SystemC description for this example looks as follows ilter h include systemc h include mult h include coeff h include sample h SC_MODULE filter sample 51 coeff cl mult xmi sc_signal lt sc_uint lt 32 gt gt q S C SC_CTOR filter sl new sample s1 51 9 5 cl new coeff cl c1 ml new mult m1 m1 SystemC 2 0 User s Guide Module Signals The four include files at the beginning of the module give the designer access to the SystemC classes and the declarations of the instantiated modules The top level of the design and the module are both named filter The top level module does not have any ports which is legal for the top of the design Below the include statements are pointer declarations that allow allocatio
17. be generated by one process and results checked by another The stimulus can be embedded in the main program and results checked in another process The check ing can be embedded in the main program etc There is no clear right way to doa testbench it is dependent on the user application A typical testbench might look as follows Main Module Device Under Results Stimulus Test i Checking The stimulus module will provide stimulus to the Device Under Test DUT and the Results Checking module will look at the device output and verify the results are correct 1 Described in Chapter 4 Processes SystemC 2 0 User s Guide 49 Modules and Hierarchy The stimulus module can be implemented by reading stimulus from a file or as an SC THREAD process or an SC CTHREAD process The same is true of the results checking module Some designers combine the stimulus and results check ing modules into one module Also the results checking module can be left out if the designer does manual analysis of the output results For some designs this tech nique works well because the output results are easy to check For example if the device under test is a graphics manipulation device and the stimulus is a picture to be manipulated the designer just needs to look at the output picture to verify that the results are as expected An example testbench for the counter examp
18. not operator the return type is the type of the operand The bits in the two s complement mantissa are inverted to get the mantissa of the result For binary operators the type of the result is the maximum aligned type the longest width of the two operands The two operands are aligned by the binary point The maximum word length and maximum fractional word length are taken Both operands are converted to this type before performing the bitwise and or or xor operation Bit Selection As with other types that have already been discussed bit selection is performed with The return type of this operation is type sc fxnum bitref which behaves like sc bit Bit selection can be used for reading and writing a single bit of a fixed point type 146 SystemC 2 0 User s Guide Part Selection Part Selection Part selection is performed with the range method as with other types The return type of the part selection is sc fxnum subref which behaves like sc bv Part selec tion can be performed on both sides of an assignment statement allowing both read ing and writing of a part Type Casting Type casting is very important for fixed point types Type casting is performed dur ing initialization if required and assignment Type casting will first use quantiza tion to reduce then number of bits of the LSB side of the operand Next overflow handling is performed to reduce the number of bits at the MSB side of the ope
19. the designer creates the C model verifies that the C model works as expected and then translates the design manually into an HDL This process is very tedious and error prone Disconnect Between System Model and HDL Model After the model is converted to HDL the HDL model becomes the focus of devel opment The C model quickly becomes out of date as changes are made Typically changes are made only to the HDL model and not implemented in the C model Multiple System Tests Tests that are created to validate the C model functionality typically cannot be run against the HDL model without conversion Not only does the designer have to convert the C model to HDL but the test suite has to be converted to the HDL envi ronment as well For the parts of the original model to be implemented in software the model has to be rewritten with calls to an RTOS The model is the simulated and verified with an RTOS emulator Though parts of the original code can be reused the change in abstraction from the original model to an RTOS based model requires significant manual recoding and verifying the changes becomes a significant problem SystemC Design Methodology The SystemC design approach offers many advantages over the traditional approach for system level design The SystemC design methodology for hardware is shown in the figure below SystemC 2 0 User s Guide z Introduction SystemC Model Rest of Process This technique has
20. 2 S8XXXXX 0 125 0 109375 0 0 234375 T 1 1 SX 0 25 0 0 0 25 x is an arbitrary binary digit O or 1 s is a sign extended digit O or 1 104 SystemC 2 0 User s Guide Quantization Modes Quantization Modes As mentioned previously quantization effects are used to determine what happens to the LSBs of a fixed point type when more bits of precision are required than are available For instance if the result of a multiplication operation generates more LSB precision than can be represented by the result type quantization will occur After quantization the result is a function of the deleted bits and remaining bits of the original fixed point number The quantization modes available are shown by the table below Quantization Mode Name Rounding to plus infinity SC RND Rounding to zero SC RND ZERO Rounding to minus infinity SC RND MIN INF Rounding to infinity SC RND INF Convergent rounding SC RND CONV Truncation SC TRN Truncation to zero SC TRN ZERO Operations performed on fixed point data types are done using arbitrary precision After the operation is complete the resulting operand is cast to fit the fixed point data type object The casting operation will apply the quantization behavior of the target object to the new value and assign the new value to the target object For instance in the example below the new value is calculated with 12 bits of precis
21. 94 bus controller 59 bus resolution 75 C model manual conversion 4 checking results 51 clock 3 51 asynchronous to signal 156 clocked thread process 62 data members 80 duty cycle 80 81 first edge 80 81 first value 80 frequency 81 name 80 object 80 period 80 SystemC 2 0 User s Guide signal 82 clock object 62 clock period 80 clocked thread process 59 synthesis 59 compatibility SystemC 0 9 7 concatenation 93 concatenation operator 89 condition 54 constructor example 20 constructors module 47 counter 169 187 counter module 45 cycle based simulation 3 153 D data 9 data members local 20 data protocol duplex 9 simplex 9 simplex C model 11 simplex SystemC model 15 debug 4 153 157 160 declarations module pointer 43 design methodology refinement 6 SystemC 5 traditional 4 dff 163 181 asynchronous reset 165 182 driver disable 76 96 duty cycle 80 E equals overload 16 event 56 signal 54 event handlers 68 executable specification 2 exiting a loop 64 expression watching 65 66 F fixed precision integer operations 87 operators 88 size 87 fixed precision integers 87 flag D 32BIT 91 flip flop 47 frequency clock 81 G global watching 67 graphic symbol 40 H hierarchical design structure 72 implicit state machines 59 initialization memory 48 inout port 40 instance module 47 instance name module 48 instantiation 42 module 49 integer arbitrary precision 91 ISDB 4
22. Integer Word Length 103 Quantization Modes 105 SC_RND 106 SC RND ZERO 108 SC RND MIN INF 110 SC RND INF 112 SC RND CONV 114 SC TRN 117 SC TRN ZERO 119 Overflow Modes 121 MIN and MAX 121 SC SAT 122 SC SAT ZERO 124 SC SAT SYM 126 SC WRAP 128 SC WRAP n bits 0 128 SC WRAP n bits 0 130 SystemC 2 0 User s Guide CHAPTER 8 APPENDIX A APPENDIX B SC WRAP SM 132 SC WRAP SM n bitsz0 132 SC WRAP SM n bits 0 134 SC WRAP SM n bitsz1 135 Fast Fixed Point Types 139 Simple Examples 140 Typesc fxtype params 140 sc fxtype context 142 Operators 146 BitSelection 146 Part Selection 147 Type Casting 147 Useful State Information 147 Converting Fixed Point Types to Strings 148 Arrays of Fixed Point Types 149 Simulation and Debugging Using SystemC Advanced Topic SystemC Scheduler 153 Simulation Control 154 Tracing Waveforms 157 Debugging SystemC 160 VHDL Designer s Guide 163 DFF Examples 163 Shifter 166 Counter 169 State Machine 171 Memory 178 Verilog Designers Guide 181 153 vi SystemC 2 0 User s Guide DFF Examples 181 Asynchronous Reset D Flip Flop 182 Shifter 184 Counter 187 State Machine 189 Memory 195 SystemC 2 0 User s Guide viii SystemC 2 0 User s Guide CHAPTER 1 Introduction NOTE This document does not yet describe the new SystemC 2 0 specific language features Please refer to the Functional Specification for S
23. a number of advantages over the current design methodology including the following Refinement Methodology With the SystemC approach the design is not converted from a C level description to an HDL in one large effort The design is slowly refined in small sections to add the necessary hardware and timing constructs to produce a good design Using this refinement methodology the designer can more easily implement design changes and detect bugs during refinement Written in a Single Language Using the SystemC approach the designer does not have to be an expert in multiple languages SystemC allows modeling from the system level to RTL if necessary 6 SystemC 2 0 User s Guide Compatibility with Earlier Versions of SystemC The SystemC approach provides higher productivity because the designer can model at a higher level Writing at a higher level can result in smaller code that is easier to write and simulates faster than traditional modeling environments Testbenches can be reused from the system level model to the RTL model saving conversion time Using the same testbench also gives the designer a higher confi dence that the system level and the RTL model implement the same functionality Though the current release of SystemC does not have the appropriate constructs to model RTOS future version will That will enable a similar refinement based design methodology for the software parts of the system Software designers wi
24. as unique SystemC data types to model systems C data types are discussed in C books so they will not be discussed here The SystemC data types include the following Sc bit 2 value single bit type sc logic 4 value single bit type sc int 1 to 64 bit signed integer type sc uint 1 to 64 bit unsigned integer type Sc bigint arbitrary sized signed integer type biguint arbitrary sized unsigned integer type bv arbitrary sized 2 value vector type sc arbitrary sized 4 value vector type sc fixed templated signed fixed point type sc ufixed templated unsigned fixed point type sc fix untemplated signed fixed point type SystemC 2 0 User s Guide 63 Data Types sc ufix untemplated unsigned fixed point type Each of these types will be discussed in more detail in the next sections The fixed point types are described in more detail in the next chapter Type sc bit Type sc bit is a two valued data type representing a single bit A variable of type sc bit can have the value O false 17 only This type is useful for model ing parts of the design where Z hi impedance or X unknown values are not needed There are a number of logical and comparison operators that work with sc bit including TABLE 2 sc bit Operators Bitwise amp and K or xor not Assignment amp l A Equality l For those not familiar with the special
25. be shown The first two use signed numbers and the last two unsigned numbers The first example shows quantization of a positive number and the second quantization of a negative number Sc lt 4 2 gt x 114 SystemC 2 0 User s Guide SC RND CONV Sc fixed 3 2 SC RND CONV y x 75 x quantization occurs here 00 11 value of x after assignment 01 0 1 value of y after quantization Value 75 is outside the representable range for the result type so quantization will occur The redundant bits are removed and the result is rounded towards plus infin ity because the LSB of the remaining bits is 1 The next example uses the same types and a negative number sc fixed 4 2 x Sc fixed 3 2 SC RND CONV y 21 255 quantization occurs here X 10 11 1 25 value of x after assignment 11 0 1 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization will be performed The LSB of the remaining bits is 1 so the result is rounded towards plus infinity The final examples shows the same quantization mode with an unsigned type sc_ufixed lt 14 9 gt x sc_ufixed lt 13 9 SC_RND_CONV gt y x 38 28125 y x quantization occurs here 000100110 01001 38 28125 LSB O 000100110 0100 38 25 minus infinity Here is an unsigned type with a different LSB value SystemC 2 0 User s Guide
26. can go to other states such as repeat erase record etc Out put signals play recrd erase save and address are triggered as each of these states are entered thereby controlling the voicemail system Here is the VHDL implementation SystemC 2 0 User s Guide 171 package vm pack is type t vm state is main st save st erase st address st begin rec st type t key is 0 1 72 03 4 Np y atus o WOES OEE YII ys end vm pack use work vm pack all library ieee use ieee std logic 1164 11 entity stmach is port clk in std logic key in t key play recrd rase save address out std logic end stmach architecture rtl of stmach is Signal next state current state review st repeat st send st record st message st Nr 6 t vm state begin process current state key begin play lt 0 save lt 0 erase lt 70 recrd lt 0 address lt 0 case current_state is when main_st gt if key 1 then next state review st elsif key 72 then next_state lt send_st else next_state lt main_st end if 172 SystemC 2 0 User s Guide State Machine gt when review_st if key 71 next_state elsif key next_state elsif key next_state elsif key next_state else next_state end if when repeat_st play lt 71 next_state lt when save_st gt sav
27. car on the East West side road will trigger the sensor causing the highway light to go from green to yellow to red and the side road to change from red to green The model uses two different time delays The green to yellow delay is longer than the yellow to red delay to represent the way that a real traffic light works The starting state of the model will wait for an event on the road sensor When this occurs the NS North South lights will change to yellow and the model will wait for the yellow to red delay After the delay the NS lights are changed to red and the EW East West lights are changed to green The model will now wait for the green to yellow delay to allow the cars to have time to cross the highway After this delay is complete the EW lights are changed to yellow and finally to red The module waits one more long delay after the highway light goes back to green so that another car will not trip the sensor immediately The module has SC THREAD process named control lights As can be seen from the constructor it is sensitive to the roadsensor shorttimer and longtimer input ports In the steady state condition the process will be waiting for events on the roadsensor input The Thread Process is the most general process and can be used to model nearly anything An SC METHOD process to model this same design would require more 58 SystemC 2 0 User s Guide Clocked Thread Process typing and be more difficult t
28. copies the calculated next state to the current state every positive clock edge on input clk stmach h include systemc h 174 SystemC 2 0 User s Guide State Machine enum vm state main st erase st s record st review st repeat st save st end st address st begin rec st message st SC MODULE stmach sc_in lt bool gt clk sc_in lt char gt key sc_out lt sc_logic gt play sc_out lt sc_l sc_out lt sc_l sc_out lt sc_l sc_out lt sc_l ogic gt recrd ogic gt erase ogic gt save ogic gt address sc_signal lt vm_state gt next_state sc_signal lt vm_state gt current_state void getnextst void setstate SC CTOR stmach SC METHOD sensitive SC METHOD getnextst lt lt key lt lt current state setstate sensitive pos clk stmach cc include stmach h void stmach getnextst play SC_LOGIC_0 recrd SC LOGIC 0 erase SC LOGIC 0 save SC LOGIC 0 SystemC 2 0 User s Guide 175 address SC LOGIC 0 switch current state case main st if key 71 next state review st else if key 72 next state send st else next state main st break case review_st if key 71 next_state repeat_st else if key 72 1 next_state save_st else if key 73 1 next_state
29. creates the WIF file named my trace awif the awif extension is automatically added Similarly an ISDB trace file can be created At the end of simulation the trace files need to be closed or errors can result Close the trace files with one of the following functions Sc close isdb trace file my trace file Sc close wif trace file my trace file Sc close trace file my trace file Call the function appropriate to the type of file that was created Call this function just before the return statement in your sc main routine Tracing Scalar Variable and Signals SystemC provides tracing functions for scalar variables and signals All tracing functions have the following in common The function is named sc trace Their first argument is a pointer to the trace file data structure sc trace file Their second argument is a reference or a pointer to a variable being traced Their third argument is a reference to a string For example the following illustrates how a signal of type int and a variable of type float are traced 158 SystemC 2 0 User s Guide Tracing Waveforms sc_signal lt int gt a float b Sc trace trace file a MyA Sc trace trace fite b In this example trace file is a pointer of type sc trace file that was created earlier MyA is the name of the int variable as it would appear in the waveform viewer and B is the name of the floa
30. data transfer medium can model wired and wireless networks It can be a simple or complex model of data and error rates to match the actual physical medium A block diagram of the system is shown below SystemC 2 0 User s Guide 9 Starting with a Simple Example Packets L __ Transfer Transmit Medium Receive Acknowledge The transmitter sends data packets to the data transfer medium The data transfer medium receives those packets and sends them on to the receiver The data transfer medium can introduce errors to represent the actual error rate of the physical medium The receiver receives the data packets from the data transfer medium and analyzes the data packets for errors If the data packet has no errors the receiver generates an acknowledge packet and sends the acknowledgement packet back to the data trans fer medium The data transfer medium receives the acknowledge packet and sends this packet to the transmitter The data transfer medium can introduce errors when sending the acknowledge packet that causes the acknowledge packet to not be prop erly received After the transmitter has received the acknowledge packet for the previously sent data packet the transmitter sends the next packet This process con tinues until all data packets are sent This protocol works well for sending data in one direction across a noisy medium 10 SystemC 2 0 User s Guide
31. invoked when a new packet arrives on the rpackin port The first step in the process is to copy rpackin to the local variable packin for packet field access The receiver block like the transmit block compares the new packet value with the old packet value to determine if a new packet has been received A debug message is printed and the process checks to see if the sequence number of the incoming packet matches the expected fra menum If so the packet data is placed on the dout port where it will be sent to the display module Next the framenum variable is incremented to reflect the next fra menum expected If a packet is successfully received an acknowledge packet needs to be sent back to the transmit module A local packet named s has its sequence number filled in with framenum After the sequence number field is updated packet s is assigned to port rpackout SystemC 2 0 User s Guide 27 Starting with a Simple Example Display Module The display module is used to format and display the packet data received by the receiver module In this example the data is a very simple type long value This makes the display module very simple However as the simplex protocol is more completely implemented the data being sent could grow in complexity to the point that more complex display formatting is needed The display module is shown below display h include systemc h include packet h SC MODULE display sc_i
32. is used to see if an acknowledgement packet was received from the channel If the values differ an acknowledgement packet has been received from the channel Notice that tpackin was copied to local variable packin Using a local variable allows you to access to the packet fields that cannot be accessed directly from the port The sequence number of the packet is checked against the last sent packet to see if they match If they match a correct acknowledgement was received and the next piece of data can be sent The buffer will be filled with the next piece of data and the framenum is incremented Field retry is also reset to O which is the initial value If no acknowledgement packet was received the process was triggered by an event from the timeout port This means the timer block completed its count or timed SystemC 2 0 User s Guide 21 Starting with a Simple Example out If a timeout event occurs that means the packet was sent but no acknowledge was received In this case the packet must be transmitted again A local packet named s has all of its fields filled with the new data values to be sent and it is assigned to tpackout Notice that retry is incremented each time the packet is sent This number is required to ensure the uniqueness of each packet Whenever a packet is written the timer is started by the transmit process by setting the start timer signal to true In summary the transmit module sends a new packe
33. microcontroller with a 32 bit internal data path but only one 8 bit external data path to get data to and from the controller Every address and data transaction will have to be multiplexed out over the 8 bit bus 8 bits at a time This is a perfect application for an implicit state machine and an SC CTHREAD process SystemC 2 0 User s Guide 59 Processes addr 32 start newaddr Bus gt Controller Memory data8 Controller data 8 8 32 8 3 datardy ready 34 wea A 32 bit address will be passed to the bus controller process This 32 bit address will be multiplexed byte by byte through the 8 bit data bus to form the 32 bit address in the memory controller After the address has been sent the bus controller will wait until the ready signal from the memory controller is active and start receiving the 32 bits of data from the memory controller After all of the data is received the bus controller will send the data back to the microcontroller on the 32 bit data bus Each of these transfers takes 4 cycles of the clock to transfer the 32 bit data 8 bits at a time The bus controller will initially wait for the newaddr signal to become active When newaddr becomes active a new address is present on the addr inputs The start sig nal is sent to the memory controller with the first byte of the
34. of bits available Value MAX will then be assigned to the result value for a positive overflow and MIN for a negative overflow condition A graph showing the behavior for a 3 bit type is shown below 5 3 4 o e 12 1 P 2 7 gt 3 7 e e 4 5 The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of the result The X axis is the original value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit type SC_SAT Examples Assume that the arithmetic precision is sc_fixed lt 4 4 gt and the result is sc_fixed lt 3 3 SC_TRN SC_SAT gt Then the example below will behave as shown sc lt 4 4 gt x Sc fixed 3 3 SC TRN SC SAT y 122 SystemC 2 0 User s Guide SC SAT 6 x overflow handling occurs here 0110 6 value of x after assignment 011 3 value of y after overflow handling An overflow condition exists because 6 is outside the representation range for a signed 3 bit type Therefore the value MAX 3 is assigned to the result Below is the same types using a negative value sc lt 4 4 gt x Sc fixed 3 3 SC TRN SC SAT y X 5 y x overflow handling occurs here 1011 5 value of x after assignment 100 4 value of y after overflow handling Value 5 is outside th
35. overloaded to allow assignment of a sc bv type to a SystemC integer and vice versa The operator will convert bv objects to sc 1v objects and vice versa Strings of 0 and 1 characters can be assigned to type sc bv objects For instance to set a 16 bit sc_bv to all 1 s you can use the following statement sc bv 16 val val 1111111111111111 Only the characters 0 and 1 can be used in assignments to bv objects Arbitrary Length Logic Vector Different data types are used to model the types of data used in a typical design Types sc logic and sc bit work well for modeling single bits accurately Types sc int sc uint sc bigint and biguint work well for modeling parts of the design where arithmetic operations can occur but no tristate busses However for parts of the design that need to be modeled with tristate capabilities yet contain items that are wider than 1 bit SystemC contains a type called sc_lv lt n gt This type represents an arbitrary length vector value where each bit can have one of four val ues These values are exactly the same as the four values of type sc logic Type sc_lv lt n gt is really just a variable sized array of sc logic objects To declare a signal of type sc_lv lt n gt use the following syntax signal sc 1 lt 64 gt gt databus extra space is required This declaration describes a 64 bit wide signal called databus in which each of the bits of the si
36. port assigned and read Resolved Logic Vectors Bus resolution becomes an issue when more than one driver is driving a signal SystemC uses a Resolved Logic Vector signal type to handle this issue Take a look at the example below with three drivers x y w driving signal g Module A Module y Z 8 0 1 Module C w Z SystemC 2 0 User s Guide 75 Ports and Signals Modules a b and c are driving signal g through ports x y and w respectively Port X is driving a 0 value and ports y w are driving Z values The resolution of these values will be assigned to signal g In this example the resolved value will be 0 Ports y and w have their drivers disabled and are driving Z values Therefore the 0 value from port x will win Another interesting case is shown below Module A x Module B y 1 g X 1 Module C w Z In this case ports x and y are driving a value while port w is not However ports x and y are driving opposite values Since values 0 and 1 are the same strength or pri ority the final value of signal g cannot be determined and the value assigned will be X The resolution function used is shown in the table below TABLE 1 Resolution of logic values 0 1 Z X 0 0 X 0 X 1X 1 1 X 2101 7 X XX X X X 76 SystemC 2 0 User s Guide Resolved Vector Signals To create a resolved logic vector p
37. receiver module and sends them to the transmit module Process receive_data is sensitive to events on port tpackin Thus when a new packet is sent from the transmit module process receive_data is invoked and analyzes the packet Process send_ack is sensitive to events on port rpackin When the receiver module sends an acknowledge packet to the channel module the value of port rpackin is updated and causes process send_ack to be invoked Constructor In the channel constructor we can see that both processes are SC METHOD pro cesses 24 SystemC 2 0 User s Guide Receiver Module Implementation of Methods Let s take a closer look at process receive data The first step is to copy tpackin to a local variable so that the packet fields can be accessed A message is printed for debugging purposes A random number is generated to add noise to the channel The packet is assigned to the output packet and another debugging message is printed displaying the random number value Finally an if statement determines whether the packet passes through as received or if the packet is altered by adding noise If the random number is within the specified range the sequence number of the packet is set to 0 This means the packet was corrupted The last two statements of the process receive data copies the altered or unaltered packet to output port rpack out You can modify the range of random numbers generated and the range of numbers
38. rl receiver receive clock rpackout PAC rpackin PACKETA4 KET3 dout DOUT rclk RCLK Hh hn display dl display dl DOUT timer tml timer tml START TIMEOUT CLOCK signal tracing trace file creation sc simplex External Signals CLOCK signal Sc trace t Sc trace Sc trace START start race file tf sc create vcd trace file 1 TIMEOUT timeout sc trace t packetl PACKET2 packet2 Sc trace tf PACKET3 packet3 Sc trace tf 4 packet4 Fh FH Fh Fh FH EF sc_trace t Sc trace DOUT dout 32 SystemC 2 0 User s Guide Putting it all together The main routine sc start 10000 SC close trace file tf return 0 Include Files Notice that the sc main file includes all of the other modules in the design You instantiate each of the lower level modules and connect their ports with signals to create the design in sc main To instantiate a lower level module the interface of the module must be visible Including the h file from the instantiated module pro vides the necessary visibility Argument to sc main The main routine takes the following arguments int sc main int argc char argv The argc argument is a count of the nu
39. software designers Ports Modules have ports through which they connect to other modules Sys temC supports single direction and bidirectional ports Signals SystemC supports resolved and unresolved signals Resolved signals can have more than one driver a bus while unresolved signals can have only one driver Rich set of port and signal types To support modeling at different levels of abstraction from the functional to the RTL SystemC supports a rich set of port and signal types This is different than languages like Verilog that only support bits and bit vectors as port and signal types SystemC supports both two valued and four valued signal types Rich set of data types SystemC has a rich set of data types to support multiple design domains and abstraction levels The fixed precision data types allow for fast simulation the arbitrary precision types can be used for computations with large numbers and the fixed point data types can be used for DSP applications SystemC supports both two valued and four valued data types There are no size limitations for arbitrary precision SystemC types Clocks SystemC has the notion of clocks as special signals Clocks are the timekeepers of the system during simulation Multiple clocks with arbitrary phase relationship are supported Cycle based simulation SystemC includes an ultra light weight cycle based simulation kernel that allows high speed simulation Multiple abstraction leve
40. that modify the packet sequence number to control the amount of noise injected The send process triggered by events on port rpackin is very similar to the receive data process It assigns rpackin to the local packet ackin so the fields of the packet can be examined Next a debug message is written and a random number representing the noise in the channel for acknowledgements is generated This pro cess also uses a specified range to modify the sequence number field of the packet Finally the packet is assigned to tpackout where it will be passed to the transmit module Receiver Module The receiver module accepts packets from the channel module and passes the data received to the virtual application In this design the virtual application is a display modeled in the display module When the receiver module successfully receives a packet it send an acknowledgement packet back to the transmit module Incoming packet sequence numbers are compared with an internal counter to ensure the cor rect packets are being transmitted The receiver module is shown below xeceiver h SystemC 2 0 User s Guide 25 Starting with a Simple Example include packet h SC MODULE receiver Sc in packet type rpackin Sc out packet type rpackout sc out long dout sc lt 1 gt rclk int framenum packet type packin packold packet type s int retry void receive data Constructor
41. the result The X axis is the starting value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit type Notice that while the graph looks somewhat like a saw tooth waveform positive numbers do not dip below 0 and negative numbers do not cross 1 SC WRAP SM n bits 1 Example This example will cast a 5 bit representation of the number 12 to a 3 bit number using the SC WRAP SM overflow mode with n bits equal to 1 Here s the origi nal value sc ufixed 5 5 x sc ufixed 3 3 SC TRN SC WRAP 5 1 gt y x 12 y x overflow processing occurs here 01100 12 136 SystemC 2 0 User s Guide SC WRAP SM n bits 1 This value is first truncated to 3 bits 100 4 The original sign bit is copied to the MSB position 000 0 The two remaining LSB bits are xor ed with the original sign bit 1 and the new sign bit 0 011 3 This algorithm can be applied to any number that cannot be exactly represented by 3 bits The table below summarizes the overflow behavior for 3 bits Original Result valuein value in Decimal Binary 9 001 8 000 7 000 6 001 5 010 4 011 3 011 2 010 1 001 0 000 1 111 2 110 3 101 4 100 5 100 6 101 SystemC 2 0 User s Guide 137 Fixed Point Types Original Result valuein value Decimal Binary 7 110 8 111 9 111 138 SystemC 2 0 User s Guide Fast Fixed Point Types Fast Fixed Po
42. to this packet For better error handling this number will uniquely identify the packet dur ing data transfers The third field in the packet is the retry field This field contains the number of times the packet has been sent Other constructs in the packet h and packet cc files will be discussed later Let s now take a look at the first block the transmit block Transmit Module Notice that the transmit module includes the packet h file which includes sys temc h The systemc h file gives the design access to all of the SystemC class meth ods and members The packet h file gives the design access to the packet definition and methods associated with the packet Note In C function members are similar to C functions and data members are similar to C variables The SystemC description of the transmit module described in the sections that fol low is shown below SystemC 2 0 User s Guide 17 Starting with a Simple Example transmit h include SC_MODULE packet h transmit Sc in packet type tpackin sc in bool timeout Sc out packet type tpackout Sc inout bool start timer sc in bool clock int buffer int framenum packet type packin packet type s int retry bool start tpackold void send_data int get data fromApp Constructor SC_CTOR transmit SC_METHOD send_data sensitive lt lt timeout sensitive_pos lt lt clock
43. trace function using the basic data or signal trace functions SystemC provides For example the trace function for arrays of type sc signal int are void trace sc trace file tf sco signal int v const sc string amp NAME int len char stbuf 20 for int i 0 i len itt Sprintf stbuf d i sc trace tf v i NAME stbuf This trace function has one additional argument which is the length of the array to be traced SystemC has predefined trace functions for all SystemC defined vector types sc_int lt gt sc_uinit lt gt sc_biginit lt gt sc_bigunit lt gt sc_lv lt gt and so forth Debugging SystemC Because each thread or clocked thread process generates a new thread of execution debugging the simulation can be more difficult than with a typical linearly executed C program The execution threads in the simulation means the simulation pro ceeds in a nonlinear fashion It may be difficult to determine the code that will be executed next You may want to debug only your code not the SystemC class libraries The easiest way to debug a design is to place a breakpoint at the beginning of a process that you are interested in debugging When the simulation stops at one of these breakpoints simulation will halt and you can debug the appropriate process as required 160 SystemC 2 0 User s Guide Debugging SystemC SystemC 2 0 User s Guide 161 Simulat
44. trigger 54 types 53 wait statements 46 process execution waiting 63 process sensitivity 54 processes 53 module 46 R RAM 48 range method 89 refinement methodology 6 reset 66 resolved logic vector 75 77 results checking 51 S sl 79 sc bigint 91 sc biguint 91 sc bit 84 sc bv 93 sc clock 63 sc create vdc trace file 157 sc create wif trace file 158 SC CTHREAD 59 SC CTOR 43 sc cycle 155 sc initialize 155 sc int 88 sc logic 85 operators 85 values 85 sc lv 93 95 sc main 154 SC METHOD 47 49 55 SC MODULE 39 sc signal 43 77 Sc start 154 SC THREAD 58 sc uint 88 scheduler 153 steps 154 sensitive pos 47 sensitivity list clocked thread process 62 shift register 166 184 signal 3 82 event 54 timing 80 trace 157 signal assignment 72 signal binding 72 78 signal driver 76 signal vector 77 signals module 41 signed fixed integer 87 simulation 153 153 157 control 154 cycle based 3 simulation control 153 state machine 171 189 implicit 59 struct module syntax 40 synchronizing events 80 T testbench 2 49 counter 50 thread process 56 sensitivity list 56 suspension 56 timing signals 80 top level module 43 trace 4 signal 157 variable 157 waveform 157 trace file creation 157 tracing aggregate signals 159 aggregate variables 159 scalar signals 158 scalar variables 158 SystemC 2 0 User s Guide signal arrays 160 variable arrays 160 triggering a process 54 type user
45. true Normal process function The process will execute the normal process functionality until the watched condi tion becomes true When this happens the loop will be exited and execution of the process will start at the beginning In this example execution would start with the statement shown below if reset true If reset is true then data would be set to 0 and execution of the loop would start again from the first statement Watching expressions are tested at every active edge of the execution of the pro cess Therefore these signals are tested at the wait or wait_until calls in the infi nite loop 66 SystemC 2 0 User s Guide Local Watching One unexpected consequence of control exiting the while loop and starting again at the beginning of the process is that all of the variables defined locally within the process will lose their value If a variable value is needed to be kept between invo cations of the process declare the variable in the process module and not local to the process Multiple watches can be added to a process The data type of the watched object must be of type bool If multiple watches are added to a process be sure to test which watch expression triggered the exit from the loop Then perform the appro priate watch action based on the expression that triggered the exit This type of watching is called global watching and cannot be disabled If you need to watch different signals a
46. type As the value of x increases the value of y increases to 132 SystemC 2 0 User s Guide SC WRAP SM n bits 0 MAX and then slowly starts to decrease until MIN is reached The result is a saw tooth like waveform SC WRAP SM n bits 0 Examples For the next few examples the starting value is a four bit representation of the value 4 If the target for this value is a 3 bit signed type the value 4 will overflow the type and overflow processing will occur Here is the starting value sc lt 4 4 gt x Sc fixed 3 3 SC TRN SC WRAP SM y x 4 y x overflow processing occurs here 0100 4 First the MSB is deleted to produce a 3 bit result 100 4 Next the new sign bit is calculated The new sign bit is the least significant bit of the deleted bits For this example only 1 bit was deleted and its value is 0 Therefore the new sign bit is 0 Now the sign bit of the new value 1 is compared with the calculated sign bit 0 If these bits are different then the rest of the bits will be inverted for this example the sign bits are different and the other bits will be inverted as shown below 011 3 The sign magnitude wrap values with n bits equal to 0 for 3 bit numbers are shown by the table below Original Result valuein value Decimal Binary 8 111 7 000 6 001 010 SystemC 2 0 User s Guide 133 Fixed Point Types Original Result valuein value Decimal Binar
47. variables that are in scope during the entire simulation can be traced This means all signals and data members of modules can be traced Variables local to a function cannot be traced e Variables and signals of scalar array and aggregate types can be traced Different types of trace files can be created during the same simulation run Asignal or variable can be traced any number of times in different trace for mats Creating the Trace File The first step in tracing waveforms is creating the trace file The trace file is usually created at the top level after all modules and signals have been instantiated For tracing waveforms using the VCD format the trace file is created by calling the Sc create vcd trace file function with the name of the file as an argument This SystemC 2 0 User s Guide 157 Simulation and Debugging Using SystemC function returns a pointer to a data structure that is used during tracing For exam ple Sc trace file my trace file my trace file sc create vcd trace file my trace creates the VCD file named my trace vcd the vcd extension is automatically added A pointer to the trace file data structure is returned You need to store this pointer so it can be used in calls to the tracing routines To create a WIF file the sc create wif trace file function needs to be called For example Sc trace file trace file my trace file sc create wif file my trace
48. 0 value of y after overflow handling Value 6 is outside the representable range for the 3 bit result type specified so over flow processing will occur and return the value 0 Here is an example of a negative value sc_fixed lt 4 4 gt x Sc fixed 3 3 SC TRN SC SAT ZERO y X 5 y x overflow handling occurs here 1011 5 value of x after assignment 000 0 value of y after overflow handling Value 5 is outside the representable range for the 3 bit type specified so the return value will be saturated to 0 This last example uses an unsigned type sc ufixed 5 5 x Sc ufixed 3 3 SC TRN SC SAT ZERO y x 14 y x overflow processing occurs here 01110 14 value of x after assignment 000 0 value of y after overflow handling Value 14 is outside the range of 3 bits unsigned so overflow processing will occur and return the value 0 SystemC 2 0 User s Guide 125 Fixed Point Types SC SAT SYM In twos complement notation one more negative value than positive value can be represented When using SC SAT overflow mode the absolute value of MIN is one more than MAX Sometimes it is desirable to have the MIN and MAX value sym metrical around zero The SC SAT SYM overflow mode will perform this func tion as required Positive overflow will generate MAX and negative overflow will generate MAX for signed numbers A graph showing this behavior is shown below y
49. 115 Fixed Point Types ufixed 14 9 x Sc ufixed 13 9 SC RND CONV y x 38 34375 y x quantization occurs here 000100110 01011 38 34375 LSB 1 000100110 0110 38 375 plus infinity 116 SystemC 2 0 User s Guide SC TRN SC TRN This quantization mode is the default for fixed point types and will be used if no other value is specified The result is always rounded towards minus infinity The redundant bits are always deleted no matter whether the number is positive or nega tive The result value is the first representable number lower than the original value This is shown by the graph below P Ems 4 2 F A The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SC TRN Examples The first two examples use an arithmetic precision of sc fixed 4 2 with a result value of sc fixed 3 2 SC gt Notice that the specification of SC 15 not required as it is the default but makes it quite clear which quantization mode is being used The first example shows a positive number sc fixed 4 2 x Sc fixed 3 2 SC TRN y SystemC 2 0 User s Guide 117 Fixed Point Types x 1 25 y x quantization occurs here 01 01 1 25 value of x a
50. 3 sc ufixed 7 7 x 5 ufixed 5 5 SC TRN SC WRAP 3 y x 50 y x overflow processing occurs here 0110010 50 value of x after assignment 11110 30 value of y after overflow handling The 3 MSB bits are saturated to 1 as specified by n bits The other bits are copied starting from the LSB side of the starting value to the result value SystemC 2 0 User s Guide 131 Fixed Point Types SC WRAP SM The SC WRAP SM overflow mode uses sign magnitude wrapping This overflow mode behaves in two different styles depending on the value of parameter n bits When n_bits is 0 no bits are saturated With n bits greater than 0 n bits MSB bits are saturated to 1 SC WRAP SM n bits 0 This mode will first delete any MSB bits that are outside the result word length The sign bit of the result is set to the value of the least significant deleted bit If the most significant remaining bit is different from the original MSB then all the remaining bits are inverted If the MSBs are the same the other bits are copied from the original value to the result value A graph showing the result of this overflow mode is shown below The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of the result The X axis is the starting value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit
51. 3 next state reg 0 3 current state reg play recrd rase save address always posedge clk current_state next_state always key or current_state begin play 1 b0 recrd 1 b0 erase 1 b0 save 1 b0 address 1 b0 case current_state main_st begin if key one next_state review_st else if key two next_state send_st else next_state main_st end review_st begin if key one next_state repeat_st else if key two next_state save_st else if key three next_state erase_st else if key pound next_state main_st else next_state review_st end repeat_st begin 190 SystemC 2 0 User s Guide State Machine play 1 b1 next state end save st begin save 1 b1 next_state end erase_st begin erase tepis t state nex end send st begin t state nex end review st review st review st address st address st begin add if ress key next state else next state end record st if key next state else next state end begin rec st recrd dps next state end message st recrd dE ed if next state else next state end endcase end endmodule TAE pound begin five begin record st address st begin rec st record st begin message st key pound send st message st SystemC 2 0 User s Guide 191 SystemC State Machine The SystemC imple
52. 5 3 o e 1 Ao 2 7 e e e 3 7 VA 4 5 The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of the result The X axis is the original value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit type An value above MAX is set to MAX for positive num bers For negative numbers any value smaller than MAX is set to MAX SC SAT SYM Examples For the next two examples arithmetic precision is specified as sc_fixed lt 4 4 gt and the result precision is sc fixed 3 3 SC TRN SC SAT SYM 126 SystemC 2 0 User s Guide SC SAT SYM sc lt 4 4 gt x Sc fixed 3 3 SC TRN SC SAT SYM y 6 y x overflow handling occurs here 0110 6 value of x after assignment 011 3 value of y after overflow handling Value 6 is outside the range of values for a 3 bit signed value so the result is satu rated to MAX 3 Here is a negative number example 1011 5 101 3 Value 5 is outside the representable range for 3 bits so overflow processing will occur The overflow mode will return MAX 3 as the result Here is an example using an unsigned type sc ufixed 5 5 x Sc ufixed 3 3 SC TRN SC SAT SYM y x 14 y x overflow processing occurs here 01110 14 value of x after assignment Lid 7 value
53. C model the designer can analyze the total data rate effective data rate error recovery error recovery time and numerous other factors The designer can modify parameters such as frame rate size error range size data packet size timer length to verify that the protocol works and analyze the effects of these parameters SystemC Model Using SystemC the designer can design at a high level of abstraction using C high level techniques and refine the design down to a level that allows hardware or software implementation The block diagram for the SystemC implementation is shown below Timer Packets Transmit Channel Receive Display Acknowledge This block diagram is slightly different than the C model because the SystemC implementation is a more complete model The SystemC description contains the transmit block the receiver block the channel block a timer block and a display block The transmit the receiver and the channel blocks are the same as the C implementation The display block emulates the application interface on the receiver side and the timer block generates timeout events Packets are generated by a function in the transmit block and are sent through the channel to the receiver SystemC 2 0 User s Guide 15 Starting with a Simple Example block The receiver block sends data to the display block where the data is dis p
54. C 2 0 User s Guide 13 Starting with a Simple Example the timer times out If the transmitter does not receive an acknowledge after the timer has timed out then the transmitter determines that the data frame was not suc cessfully sent and it will resend the packet When the transmitter sends a data packet and starts the timer the transmitter waits for events to occur These events can be timeout events from the timer or they can be new frame events from the channel If the event received is a new frame event the transmit function gets the frame from the channel and examines the sequence number of the frame to determine if the acknowledge is for the frame just sent If the sequence number is correct the frame has been successfully received Then the transmitter gets the next piece of data to send and increments the sequence number of the frame The transmitter sends the data frame and waits again for events If the timeout event was received the test for a new frame event fails and the trans mitter resends the frame This process continues until the frame is successfully sent The receiver function also has temporary storage to keep track of local data At the first invocation it initializes the frame sequence number to 1 similar to the trans mitter function This allows the two functions to get synchronized The receiver function has a main loop that waits only for new frame events After a new frame is received the receiv
55. F for fixed notation and SC_E for scientific notation The default is SC_F for types sc_fixed sc_ufixed sc_fix and sc_ufix and the corresponding fast versions Arrays of Fixed Point Types When declaring a single fixed point object each object can receive constructor arguments For arrays of fixed point types this is not the case For arrays the default constructor will be used for each element The constructor arguments are passed through the current context in use For sc_fix sc_ufix and the corresponding fast types setup a context before the array declaration as shown below Sc fxtype context 1 16 1 SC RND CONV SC SAT SYM sc fix a 10 This will create an array of 10 fixed point types that are 16 bits long have 1 integer point use SC CONV for quantization and SC SAT SYM for overflow For sc fixed ufixed and the corresponding fast types the arguments are passed as previously described This is shown below Sc lt 32 32 gt a 10 sc ufixed fast 16 1 SC RND CONV SC SAT SYM b 4 The first statement creates an array of 10 signed fixed point types 32 bits long with 32 bits left of the binary point The second statement creates an array of 4 unsigned fixed point types 16 bits long 1 bit to the left of the binary point that uses the SC RND CONV quantization mode and the SC SAT SYM overflow mode SystemC 2 0 User s Guide 149 Fixed Point Types For the sc fixed and ufixed type
56. In this example port data of module PCI is directly connected to port din of module fifo For this case no local signal is required Ports and signals also come in different sizes as hinted to earlier Scalar ports have a single dimension A scalar port can be one of the following types C built in types long int char short float double SystemC types e sc int n sc uint n sc bigint n sc biguint n sc bit sc logic e sc lt gt e sc lt gt sc fixed sc ufixed e sc fix sc ufix User defined structs Input output and inout ports are described using the following syntax as we have seen in a number of examples already SystemC 2 0 User s Guide 73 Ports and Signals Sc in porttype input port of type porttype out porttype output port of type porttype sc inout porttype inout port of type porttype Type porttype can be any of the types mentioned above Types will be described in more detail in Chapter 6 Data Types Reading and Writing Ports and Signals You can use the read and write methods or the assignment operator for reading and writing ports and signals Using the assignment operator makes your code more concise and more like HDL code because you read and write directly to the ports Use the read and write methods explicitly to clarify the exact intent of your code even though your code is slight
57. SC WRAP d c 1 This statement will turn off the c 1 context so parameter set param2 will be active again sc fix e Parameter set param2 is used so this declaration is equivalent to sc fix 32 3 SC RND SC SAT e c 2 end This statement will turn off the c 2 context so the built in default values will now be used sc fix f This declaration uses the built in default values so this declaration is equivalent to sc fix 32 32 SC SC WRAP f SystemC 2 0 User s Guide 145 Fixed Point Types Operators There are a number of operators defined for fixed point types as shown in the table below Operator class Operators in class Bitwise amp Arithmetic lt lt gt gt Equality Ec Relational lt gS SSS Assignment x 4 lt lt gt gt 6 All of the normal arithmetic and equality operators are supported including an arithmetic shift left lt lt and arithmetic shift right gt gt The difference between the arithmetic shifts and the standard bit shifts are that the arithmetic shifts preserve the sign bit A small set of bitwise operators are defined for fixed point types These operators are defined to work exclusively on signed or unsigned operands No mixing of signed and unsigned operands is allowed Also no mixing with any other type is allowed For the
58. SC_CTOR receiver SC METHOD receive data sensitive pos rclk framenum 1 retry 1 receiver cc include receiver h void receiver receive data packin rpackin if packin packold return input port output port output port Method Process cout lt lt Receiver got packet no packin seq lt lt if packin seq framenum dout packin info retrytt S retry retry s seq framenum 1 SystemC 2 0 User s Guide Receiver Module rpackout s packold packin Ports The receiver module has four ports two input port and two output ports Input port rpackin accepts packets from the channel Input rclk is the receiver block clock sig nal Output port rpackout is used to send acknowledge packets to the channel where they may be passed to the transmit module Output port dout transfers the data value contained in the packet to the display module for printing Constructor The receiver module contains one SC METHOD process named receive data which is sensitive to positive edge transitions on input port rclk Notice in the receiver module constructor that variable framenum is initialized to 1 Module transmit also initializes a framenum variable to 1 so both transmit and receiver are synchronized at the start of packet transfer Implementation of Methods As we have already seen process receive data is
59. SYSTEMC lib TARGET ARCH CFLAGS Wall DEBUG S OPT S INCDIR S LIBDIR LIBS lsystemc 1m LIBS vest of file not shown 5 By default the simulation is built with debugging turned on Modify the DEBUG line to turn on or off the debugging options as desired 6 To compile the design enter the following in the command line unix gmake or unix make Compiling the Example for Windows The SystemC distribution includes project and workspace files for Visual C If you use these project and workspace files the SystemC source files are available to your new project For Visual C 6 0 the project and workspace files are located in directory systemc 2 0 msvc60 This directory contains two subdirectories systemc and examples The systemc directory contains the project and workspace files to compile the sys temc lib library Double click on the systemc dsw file to launch Visual C with the workspace file The workspace file will have the proper switches set to compile for Visual C 6 0 Select Build systemc lib under the Build menu or press F7 to build systemc lib The examples directory contains the project and workspace files to compile the SystemC examples Go to one of the examples subdirectories and double click on 36 SystemC 2 0 User s Guide Executing the Example the dsw file to launch Visual C with the workspace file The workspace file will have the proper sw
60. TS is defined in sc constants h This constant specifies the maximum number of bits to be used for SystemC 2 0 User s Guide 9 Data Types an arbitrary precision integer operation Defining this variable provides a 2 3X per formance increase The default value is 512 but can be changed if larger operands are required The same operators used for Fixed Precision Integers are also available for Arbi trary Precision Integers These operators are shown in the table below TABLE 5 Arbitrary Precision Integer Operators Bitwise amp gt gt lt lt Arithmetic Assignment A Equality Relational lt gt gt Autoincrement Autodecrement Bit Select x Part Select range These operators use arbitrary precision for the underlying operations unlike the fixed precision types The real difference between the two types is the underlying precision and the slower simulation speed Arbitrary Precision Integer types can have much greater precision but may simulate much slower so their use should be limited to only where needed Types sc_biguint sc_bigint sc_int sc_uint and C integer types can all be mixed together in expressions Also the operator can be used to convert from one type to another 92 SystemC 2 0 User s Guide Arbitrary Length Bit Vector Arbitrary Length Bit Vector SystemC also contains a 2 valued arbitrary length
61. ack to the SystemC scheduler When a method process is invoked it executes until it returns Users are strongly recommended to not write infinite loops within a method process as control will never be returned back to the simulator SystemC 2 0 User s Guide 55 Processes Thread Processes Thread Process can be suspended and reactivated The Thread Process can contain wait functions that suspend process execution until an event occurs on one of the signals the process is sensitive to An event will reactivate the thread process from the statement the process was last suspended The process will continue to execute until the next wait The input signals that cause the process to reactivate are specified by the sensitivity list The sensitivity list is specified in the module constructor with the same syntax used in the Method Process example A sample Thread Process is shown below traff h include systemc h SC MODUL Gl traff input ports in bool roadsensor in bool clock output ports Sc out bool NSreg sc out bool NSyellow Sc out bool NSgreen Sc out bool EWreg gt gt Sc out boo Sc out boo EWyellow EWgreen void control lights int x Constructor SC CTOR traff SC THREAD control lights Thread Process 56 SystemC 2 0 User s Guide Thread Processes se
62. ad use read when a type conversion is happening from an input port else countvalt t dout countval 188 SystemC 2 0 User s Guide State Machine State Machine The next example is a state machine This example represents a state machine within a voicemail controller The state machine will start in the main state and then transition to a send state or review state depending on user inputs From the review or send states the user can go to other states such as repeat erase record etc Out put signals play recrd erase save and address are triggered as each of these states are entered thereby controlling the voicemail system Here is the Verilog implementation def v parameter main st 4 0000 review_st 4 0001 repeat_st 4 0010 save_st 47 0011 erase_st 4 50100 send_st 4 b0101 address_st 4 0110 record_st 4 0111 begin rec st 4 b1000 message st 4 p1001 parameter zero 4 0000 one 4 0001 two 4 p0010 three 4 b0011 four 4 p50100 five 4 p0101 six 4 p0110 seven 4 b0111 eight 4 b1000 nine 4 b1001 star 4 1010 pound 4 b1011 statemach v module stmach clk key play recrd rase save address include def v SystemC 2 0 User s Guide 189 input clk input 0 3 key output play recrd rase save address reg 0
63. address on the data8 bus Successive bytes are passed on bus8 until all of the bytes have been sent The bus controller will now wait for the ready signal from the memory controller This signal tells the bus controller that the data from the memory controller is ready Now the bus controller will transfer a byte at a time from bus8 to a temporary loca tion in the bus controller Once the entire data value is received the data value is transferred to output data and the datardy signal activated The SystemC description of the bus controller is shown below bus h include systemc h SC_MODULE bus sc_in_clk clock 60 SystemC 2 0 User s Guide Clocked Thread Process in bool newaddr sc_in lt sc_uint lt 32 gt gt addr sc_in lt bool gt ready sc_out lt sc_uint lt 32 gt gt data sc_out lt bool gt start sc_out lt bool gt datardy sc_inout lt sc_uint lt 8 gt gt data8 sc_uint lt 32 gt tdata Sc uint 32 taddr void xfer SC CTOR bus SC CTHREAD xfer clock pos datardy initialize true ready to accept bus cc include bus h void bus xfer while true new address wait for a new address to appear wait_until newaddr delayed true got a new address so process it taddr addr read datardy false cannot accept new address now data8 taddr range 7 0 start true wait new addr for m
64. alues The last two statements will add a and b assign the result to Output and return the result If any quantization or overflow handling is needed it will be performed when the assignment to Output takes place The last statement assigns Output to the return value of the function If needed more quantization and overflow handling could also occur when this statement executes Complex Context Example Contexts have the ability to be turned on and off This can be very useful when using a number of different default values throughout your design To declare a context but don t use it right away use the SC LATER argument This is shown below fxtype params parami 12 3 not specified arguments are coming from the actual context fxtype params param2 32 3 SC RND SC SAT sc fxtype params param3 16 16 SC TRN SC SAT ZERO SystemC 2 0 User s Guide 143 Fixed Point Types First three sets of sc fxtype params objects have been created to hold the different values for the different contexts fxtype context 1 1 5 LATER only declaration of a context sc fxtype context c 2 param2 declaration of a context and the parameter specified in param2 are the new default one fxtype context c 3 param3 SC LATER only declaration of a context Next three contexts are created using each of the parameter sets created The SC LATER argument for parameter sets param a
65. an asynchronous reset input module dffa clock reset din dout input clock reset din output dout reg dout always G8 posedge clock or reset begin if reset dout lt 1 b0 else dout din end endmodule SystemC Implementation The SystemC model looks similar to the normal D flip flop discussed in the last section but now has the reset signal in the process sensitivity list Positive edges on the clock input or changes in value of the reset signal will cause process do_ffa to activate The process first checks the value of reset If reset is equal to 1 the flip flop output is set to 0 If reset is not active the process will look for a positive edge on input clock This is accomplished by using the event method on the clock input port This method works just like the event method in VHDL It will be true if an event has just occurred on input clock Here is the corresponding SystemC implementation dffa h include systemc h SC MODULI Gl dffa sc_in lt bool gt clock sc_in lt bool gt reset SystemC 2 0 User s Guide 183 Sc in bool din Sc out bool dout void do ffa if reset dout false else if clock event dout din SC CTOR dffa SC_METHOD do_ffa sensitive reset sensitive_pos clock Shifter The next few examples add more complexity This module implements a very basic 8 bit shifter block the shifter
66. and port types sc lt gt sc out bool and sc inout bool More complex expressions are possible using boolean expressions For instance the statement below is also legal wait until clock delayed true amp amp reset delayed false Watching SC CTHREAD processes just like SC THREAD processes typically have infi nite loops that will continuously execute A designer typically wants some way to initialize the behavior of the loop or jump out of the loop when a condition occurs This is accomplished through the use of the watching construct The watching con struct will monitor a specified condition When this condition occurs control is transferred from the current execution point to the beginning of the process where the occurrence of the watched condition can be handled The watching construct is only available for SC CTHREAD processes An example is shown below datagen h include systemc h SC MODULE data gen SC in clk clk sc_inout lt int gt data sc_in lt bool gt reset 64 SystemC 2 0 User s Guide Watching void gen data SC CTOR data SC CTHREAD gen data clk pos watching reset delayed true datagen cc include datagen h void gen data if reset true data 0 while true data data 1 wait data data 2 wait data data 4 wait This module is a
67. are also available For instance the operator will allow a more terse description of the following statement X X y traditional way 88 SystemC 2 0 User s Guide Fixed Precision Unsigned and Signed Integers x y terse method To select one bit of an integer use the bit select operator as shown below sc_logic mybit sc_uint lt 8 gt myint mybit myint 7 To select more than one bit use the range method as shown below sc_uint lt 4 gt myrange sc_uint lt 32 gt myint myrange myint range 7 4 Finally the concatenation operator can be used to make a larger value from one or more smaller values An example is shown below sc_uint lt 4 gt inta sc_uint lt 4 gt intb sc_uint lt 8 gt intc intc inta intb Operands inta and intb are concatenated together to form an 8 bit integer and then assigned to integer intc The auto increment and auto decrement operators are another method of making the description more concise and terse The auto increment operator will increment the operand it is attached to and the auto decrement operator will decrement the oper and For instance instead of writing SystemC 2 0 User s Guide 69 Data Types The auto increment operator will allow Variable of type uint unsigned can be converted to type sc int signed with the assignment operator In the same way variables of type int can be con verted to sc
68. as of the design or the entire design to be synchronized by the same clock In the example below the sc_main routine of a design creates a clock and connects the clock to instantiated components within the main module int sc_main int argc char argv sc_signal lt int gt val sc_signal lt sc_logic gt load sc_signal lt sc_logic gt reset sc_signal lt int gt result Sc clock ckl ck1i 20 0 5 0 true filter fl filter fl clk ckl signal fl val val f1 load load fl reset reset fl out result vest of sc main not shown 80 SystemC 2 0 User s Guide Clocks In this example the top level routine sc_main instantiates a module called filter and declares some local signals that will connect filter with other module instantiations Notice that a clk signal is not declared instead a clock object is instantiated its parameters are setup and its signal method is used to provide the clock signal Function ck1 signal is mapped to the clk port of the filter object In this example the clock is named ck1 and the clock frequency is specified as 20 time units Every 20 time units the clock will make a complete transition from true to false and back to true as shown by the following figure FIGURE 2 Clock Waveform clock The duty cycle of the clock is the ratio of the high time to the entire clock period In this example the duty cycle is specified a
69. assignment operators of C C here is how these work In a typical language the designer might write a amp b a a a b In C this can also be written as amp b a b Values are assigned using the character literals 1 and 0 When performing bool ean operations type sc bit objects can be mixed with the C C bool type Objects of type sc bit are good for representing single bits of a design where logical opera 64 SystemC 2 0 User s Guide Type sc logic tions will be performed To declare an object of type sc bit use the following syn tax sc bit s Type sc logic A more general single bit type is sc logic This type has 4 values 0 false X unknown and Z hi impedance or floating This type can be used to model designs with multi driver busses X propagation startup values and float ing busses Type sc logic has the most common values used in VHDL and Verilog simulations at the RTL level Type logic has a number of logical comparison and assignment operators that can be used with objects of this type These include the following TABLE 3 sc logic Operators Bitwise amp and or xor not Assignment amp Equality These operators are implemented such that operands of type logic be mixed with operands of type sc bit One of the operands must be type sc logic the other operands can be sc logic
70. be the sum of the word length of each operand Limited precision fixed point types should be used whenever possible to achieve the best simulation performance Apply the guidelines from above to make sure that the limited precision types will be appropriate for your design SystemC 2 0 User s Guide 139 Fixed Point Types Simple Examples Here are some simple examples to show how the fixed point types will be used The first example is a simple adder with floating point inputs and output types xpadder h include systemc h float adder float a float b sc_fixed_fast lt 4 2 SC_RND SC_WRAP gt Inputa a sc_fixed_fast lt 6 3 SC_RND SC_WRAP gt Inputb b Sc fixed fast 7 4 SC RND SC WRAP Output Output Inputa Inputb return Output This example is a simple adder with two floating point input argument and 1 float ing point output return value The declarations of Inputa and Inputb declare fixed point input types and conversions from floating point types The declaration of Out put specifies a fast fixed point type whose bit width is one greater than the biggest input operand The assignment to variable Output performs the add operation and the return statement will assign the new result to the function output value When the assignment is performed the fast fixed point type is converted back to a float This example allows the designer to easily change the bit widths overflow modes and quantizati
71. bit number and the result will be 5 bits Parameter n bits is equal to 3 This will cause the first 3 MSBs of the new value to be saturated to MAX or MIN Here s the starting value sc ufixed 9 9 x Sc ufixed 5 5 SC TRN SC WRAP SM 3 y x 234 y x overflow processing occurs here 011101010 234 This value is first truncated to 5 bits 01010 10 The original sign bit 0 is copied to the MSB of the new value Next bits 4 3 and 2 are converted to MAX because n bits is equal to 3 The sign bit is not saturated to 1 because the sign does not change in this mode 01110 14 The original value of the bit at position 2 starting with 0 at right was 0 The remaining bits at the LSB side 10 are xor ed with this value and the inverse value of the original sign bit 01 The final result is shown below 01101 13 SC WRAP SM n bits 1 This overflow mode behaves similarly to the mode where n bits equals 0 except that positive numbers stay positive and negative number stay negative The first bit on the MSB side of the new value will receive the sign bit of the original value The other bits are copied and xor ed with the original and the new value of the result sign bit This behavior is shown in the graph below SystemC 2 0 User s Guide 135 Fixed Point Types The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of
72. built in comparison operators are used to determine whether or not a value changed which generate an event For user defined types such as packet_type used in the simplex example in Chapter 2 the designer needs to provide the operator Looking back at packet h we see the following SystemC 2 0 User s Guide 97 Data Types inline bool operator const packet type amp rhs const return rhs info info amp amp rhs seq seq amp amp rhs retry retry This method defines the fields that are to be compared and how the comparison is made An event occurs if the comparison result indicates that the previous packet and new packet are different Tracing a User Defined Type Notice that the packet h file from Chapter 2 also traces the signals of user defined type packet_type Because this type has a number of fields you need to specify tracing of each field to see the contents of the packet This process is not automatic You can define a special user trace method that is called when an object of this type is traced This user method can be defined in the user defined type Looking back at files packet h and packet cc from Chapter 2 we can see that the user defined type packet_type has an sc_trace method defined in packet h This method defines how to trace an object of type packet_type The declaration of the method the argument types and the return value in the packet h file is shown below extern void sc_trace
73. busses The ram module contains two SC METHOD processes One for reading the ram and one for writing the ram Notice that the process that writes the ram also has to be sensitive to changes on input port data so that the proper value gets written into the ram ram h include systemc h SC MODULE ram sc_in lt sc_int lt 8 gt gt addr 196 SystemC 2 0 User s Guide Memory sc in bool enable Sc in bool readwr sc inout rv 16 data void read data void write data Sc lv 16 ram data 250 SC ram SC METHOD read data sensitive addr enable readwr SC METHOD write data sensitive addr enable readwr data include ram h void data if enable amp amp readwr data ram data addr read else data ZZ2ZZ2Z2Z2222222222 void ram write_data if enable amp amp readwr ram data addr read data SystemC 2 0 User s Guide 197 198 SystemC 2 0 User s Guide Index Symbols delayed method 64 neg method 63 pos method 63 range 89 signal method 82 string method 97 A abstraction level 3 arbitrary precision integer 91 operators 92 array port 74 signal 75 assignment deferred 72 Z value 97 autodecrement operator 89 autoincrement operator 89 B bit select 93 bit vector 93 operators
74. c h Sc fxtype params myparams SC RND SC SAT Sc fxtype context mycontext myparams SC fix fast adder sc fix fast a sc fix fast b Sc fix fast Output a wl 1 a iwl 1 specify output wl and iwl to be one larger than wl and iwl of a Output a return Output This example uses the sc_fix_fast type in an adder The first two declarations setup the quantization mode and overflow mode used in the description The first state 142 SystemC 2 0 User s Guide Type sc fxtype context ment will declare an fxtype params object myparams to specify the fixed point default parameter values Notice that the wl and iwl parameters were not specified so the current default parameter values will be used The second statement creates a new sc fxtype context object and initializes the context with the default values of the sc fxtype params object created earlier This context will now be active for all fixed point objects created in the scope of this declaration The declaration of adder specifies two input parameters and the output as Sc fix fast types When these types are declared they will pick up the overflow mode and quantization mode setup in context mycontext by default The declaration of Output specifies that the word length and integer word length will be one longer than the word length and integer word length of input a Notice the use of methods wl and iwl to return the current v
75. can be loaded with a new value by placing a value on input din setting input load to 1 and causing a positive edge to occur on input clk The shifter will shift the data left or right depending on the value of input LR If LR equals 0 the shifter will shift its contents right by 1 bit If LR equals 1 the shifter will shift its contents left by 1 bit Here is the Verilog description module shift din clk load LR dout input 0 7 din input clk load LR output 0 7 dout wire 0 7 dout reg 0 7 shiftval 184 SystemC 2 0 User s Guide Shifter assign dout shiftval always posedge clk begin if load shiftval din else if LR begin shiftval 0 6 shiftval 1 7 shiftval 7 1 b0 end else if LR begin shiftval 1 7 shiftval 0 6 shiftval 0 1 b0 end end endmodule SystemC Implementation The SystemC implementation of the shifter uses process shifty to perform the shift ing and loading operations This process is an SC METHOD process sensitive only to the positive edge of input clk A designer could use an SC CTHREAD process for this example and the behavior would be the same However and SC CTHREAD process is less efficient and the simulation will run slower Whenever the clock has a positive edge process shifty will activate and check the value of input load If load is 1 the current value of din is assigned to shiftval the local value of the shifter at all ti
76. count 0 SystemC 2 0 User s Guide 29 Starting with a Simple Example timer cc include timer h void timer runtimer while true if start cout Timer timer start detected lt lt endl count 5 need to make this a constant timeout false start false else if count gt 0 count timeout false else timeout true wait Ports The timer module has one input port one inout port and one output port Port start is an inout port of type bool The transmit module activates the timer by setting start to true The timer module starts the count and resets the start signal to false Port clock is an input port of type bool that is used to provide a time reference signal to the timer module Output port timeout connects to the transmit module and alerts the transmit module when the timer expires This means that either the packet or acknowledge were lost during transmission and the packet needs to be transmitted again Constructor The timer module contains one process called runtimer This process is sensitive to the positive edge of port clock 30 SystemC 2 0 User s Guide Putting it all together The main routine Implementation of Methods If the value of the start signal is 1 the timer is started When the timer is started a debug message is written out the value of variable count is set to the timer delay value and output p
77. ctivate the device and a readwr port to determine whether or not the device is being written to or read from The memory module has a single data inout bus that either delivers the addressed item or accepts data to write to a location When the enable input is 0 the output of the ram device will be all Z hi impedance and no read or write operations can be performed To read a location set enable to 1 readwr to 0 and apply the appropriate address To write a location set enable to l readwr to 1 addr to the appropriate location to write and data to the data value to write SystemC 2 0 User s Guide 195 Here is the Verilog model module ram addr enable readwr data input 0 7 addr input enable readwr inout 0 15 data reg 0 15 ram data 0 255 assign data enable amp readwr ramdata addr 16 bz always 8 addr or enable or readwr or data begin if enable amp readwr ramdata addr data end endmodule SystemC Implementation The SystemC implementation has similar port types to the VHDL model but opti mized for SystemC Notice that addr is an int of 8 bits This is the most efficient implementation for object of less than 64 bits Also notice that port data is an sc inout rv type The port needs to be inout and needs the ability to tristate the output A resolved vector type will allow the output to tristate and still be able to connect to tristate
78. d SystemC models This section will present a number of Verilog models and then the SystemC models for the same design The Verilog designer can then compare and contrast the models to get a better understanding of how to write SystemC models DFF Examples D flip flops are one of the basic building blocks of RTL design Here are a few examples of some Verilog D flip flops and the corresponding SystemC models for comparison Synchronous D Flip Flop Here is the Verilog model for a standard RTL D flip flop module dff din clock dout input din input clock output dout reg dout SystemC 2 0 User s Guide 181 always posedge clock dout din endmodule SystemC Implementation dff h include systemc h 5 MODULE dff sc_in lt bool gt din sc_in lt bool gt clock sc_out lt bool gt dout void doit dout din SC CTOR dff SC METHOD doit sensitive pos clock Asynchronous Reset D Flip Flop D Flip Flop with Asynchronous Reset One of the most common flip flops used in designs is the Dff with asynchronous reset These flip flops help the designer get a design to start at a known state easily By providing an active reset signal at design power up the designer can reset the flip flops of the design to a known state 182 SystemC 2 0 User s Guide Asynchronous Reset D Flip Flop Here is the Verilog description for a D flip flop with
79. d be needed for each event Finally the W END macro marks the end of the local watching block any state ments outside of this macro will only be subject to global watching not local watch ing Triggering Processes with Events In order to generate an event and trigger a process the port the process is sensitive to must have an event An important point to remember when trying to trigger a process is that in order to generate an event the input signal must change value In the simplex example from Chapter 2 the retry field was added to the packet struc ture so that successive transmissions of the same packet would cause events The retry field was updated on every packet transmission causing the new packet value to be different from the old and generating an event 70 SystemC 2 0 User s Guide CHAPTER 5 Ports and Signals Ports of a module are the external interface that pass information to and from a module and trigger actions within the module Signals create connections between module ports allowing modules to communicate A port can have three different modes of operation Input e Output nOut An input port transfers data into a module An output port transfers data out from a module and an inout port transfers data both into and out of a module depending on module operation SystemC 2 0 User s Guide 7I Ports and Signals A signal connects the port of one module to the port of another m
80. d to develop DSP software SystemC contains signed and unsigned fixed point data types that can be used to accurately model hardware The SystemC fixed point data types are accurate to the bit level and support a number of features that allow a high level of modeling These features include modeling quantization and overflow behavior at a high level There are 4 basic types used to model fixed point types in SystemC These are sc fixed sc ufixed e sc fix sc ufix SystemC 2 0 User s Guide 101 Fixed Point Types Types sc fixed and ufixed uses static arguments to specify the functionality of the type while types sc fix and ufix can use argument types that are nonstatic Static arguments must be known at compile time while nonstatic arguments can be variables Types sc fix and can use variables to determine word length integer word length etc while types fixed and sc ufixed are setup at compile time and do not change Types sc fixed and fix specify a signed fixed point data type Types ufixed and sc ufix specify an unsigned fixed point data type An object of a fixed point type is declared with the following syntax e sc fixed wl iwl q mode o mode n bits x e sc ufixed wl iwl q mode o mode n bits e sc fix x list of options sc ufix y list of options The arguments to sc fixed and ufixed are used as follows wl Total word length u
81. defined 16 U unsigned fixed integer 87 user defined type 16 V variable local 67 trace 157 variables local 44 VCD 4 157 vector signal 77 vector signal syntax 77 W BEGIN 67 W DO 67 W END 67 W ESCAPE 67 wait 56 wait until 63 expression 63 wait until 63 watching 64 event handlers 68 expression 65 66 global 67 local 67 local watching block 68 nesting local watching 68 priority 68 watching expression data type 67 testing 66 waveform trace 4 157 WIF 4 157 SystemC 2 0 User s Guide vi SystemC 2 0 User s Guide
82. delayed true W BEGIN watching reset delayed Active value of reset will trigger watching W DO the rest of this block is as before now transfer memory data to databus tdata range 7 0 data8 read wait tdata range 15 8 data8 read wait tdata range 23 16 data8 read wait tdata range 31 24 data8 read data tdata datardy true data is ready new addresses ok W_ESCAPE if reset SystemC 2 0 User s Guide 69 Processes datardy false W END The second half of the model has been altered as shown by the statements in bold Macro W BEGIN marks the beginning of the watched area Inside the watched area is a watching expression of signal reset More than one watching expression can be put into the declaration area After macro W DO is the statement area for the process functionality of the mod ule These statements are exactly the same as in the original model The difference is that if signal reset becomes active execution will be transferred to the handler statement area and not to the next statement in the block The W ESCAPE macro marks the beginning of the handler area This is the area where statement execution will be transferred if one of the watched events becomes active Inside this area we have one handler for the reset event that is being watched If there were more events being watched then a corresponding handler woul
83. deleted bits is nonzero A graph showing this quantization mode is shown below The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SystemC 2 0 User s Guide 119 Fixed Point Types SC TRN ZERO Examples Two examples will be shown The first one uses a signed number and the last one an unsigned number The first example shows quantization of a negative number and the second quantization of an unsigned number sc lt 4 2 gt x Sc fixed 3 2 SC TRN ZERO y 1 255 x quantization occurs here 10 11 1 25 value of x after assignment 11 0 1 value of y after quantization Value 1 25 is outside the range of values of the result type so quantization will be performed The LSB of the starting value is removed and the sign bit added to the LSBs This occurs because the starting number was negative If the starting value had been positive the result would have been a truncation of the redundant bits Here is another example using an unsigned type sc ufixed 15 8 x sc ufixed 12 8 SC ZERO y x 38 30859375 y x quantization occurs here 00100110 0100111 38 30859375 00100110 0100 38 25 This quantization mode for unsigned works the same as truncation because there are no negati
84. e lt 71 next_state lt when erase_st erase lt 71 next_state lt ll V when send st next state when address st address lt 71 if key W next_state else next_state end if when record_st if key 5 then lt repeat st 2 then lt save st 3 then lt erase st then lt main st lt review st gt review_st review_st gt review_st address_st gt Te then lt record st lt address st gt then next_stat else lt begin_rec_st SystemC 2 0 User s Guide 173 next state record st end if when begin rec st gt recrd lt 1 next state message st when message st gt recrd lt 1 if key then next state send st else next state lt message st end if end case end process process begin wait until clk event and clk 1 current state next state end process end rtl SystemC State Machine The SystemC implementation uses two enum types to represent the state of the state machine and the state of the key values passed to the state machine The state machine implementation consists of two SC METHOD processes SC METHOD processes are by far the most efficient processes and should be used where possible Process getnextst calculates the new state of the state machine based on the current state and the input values Process setstate
85. e range for a 3 bit signed type The value MIN 4 is assigned to the result For unsigned types the MAX value is always assigned as shown below sc ufixed 5 5 x Sc ufixed 3 3 SC TRN SC SAT y x 14 y x overflow processing occurs here 01110 14 value of x after assignment 111 7 value of y after overflow handling Value 14 is outside the range of 3 bits unsigned so MAX 7 is assigned to the result SystemC 2 0 User s Guide 123 Fixed Point Types SC SAT ZERO This overflow mode will set the result to O for any input value that is outside the representable range of the fixed point type If the result value is greater than MAX or smaller than MIN the result will be 0 This is shown in the graph below The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of the result The X axis is the original value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit type Any value above MAX or below MIN is set to 0 SC SAT ZERO Examples For these examples the arithmetic precision used is sc fixed 4 4 and the result typeissc fixed 3 3 SC TRN SC SAT ZERO sc lt 4 4 gt x sc fixed 3 3 SC TRN SC SAT ZERO y 124 SystemC 2 0 User s Guide SC SAT ZERO 6 y x overflow handling occurs here 0110 6 value of x after assignment 000
86. e use the Fixed Precision Integers over Arbitrary Precision Inte gers for the fastest simulation speed Type int n is a Fixed Precision Signed Integer while type sc uint n is a Fixed Precision Unsigned Integer The signed type is represented using a 2 s com plement notation The underlying operations use 64 bits but the result size is deter mined at object declaration For instance the following declaration declares a 64 bit unsigned integer and a 48 bit unsigned integer SystemC 2 0 User s Guide 67 Data Types Sc lt 64 gt x Sc uint 48 Integer types have a very rich set of operators that work with them as shown by the list below TABLE 4 Fixed Precision Integer Operators Bitwise amp gt gt lt lt Arithmetic a Assignment EN E E N Equality Relational lt gt gt Autoincrement Autodecrement Bit Select x Part Select range Concatenation Bitwise operators work on bit by bit The not operator will invert all bits and the shift operators will shift left lt lt or right gt gt an operand by the speci fied number of bits An example is shown below Sc lt 16 gt x y 2 Z xX amp y perform and operation on x and y bit by bit z x gt gt 4 assign x shifted right by 4 bits to z With the addition of arithmetic operators for SystemC Integer types new assign ment operators
87. e wait function calls Processes look very much like normal C methods and functions with slight exceptions Processes are methods that are registered with the SystemC kernel There are a number of different types of processes including method processes thread processes and clocked thread processes Process types are discussed in Chapter 4 Processes The process type determines how the process is called and executed Processes can contain calls to a function named wait that will halt exe cution of the process at different points Signal value changes cause the process to receive events and execute statements in a process An example process is shown below include systemc h SC MODULE dff Sc in bool din sc lt 1 gt clock Sc out bool dout void doit SC CTOR dff SC METHOD doit sensitive pos clock LI dfivce include dff h 46 SystemC 2 0 User s Guide Module Constructors void dff doit dout din This module describes a flip flop device The module has a clock input clock a data input din and a data output dout When a rising edge 0 to 1 value occurs on the clock input object input port data is assigned to output port dout The value change on input clock triggers method doit to execute Let s take a closer look at how this occurs in SystemC Process doit is described as a method in the module This method will be ca
88. ed to x Then y is assigned the value x However the value of x is outside the range of repre sentation for y so quantization will occur 106 SystemC 2 0 User s Guide SC RND sc fixed 4 2 x sc fixed 3 2 SC RND y 1 25 quantization will occur here x 01 01 1 25 representation of x value 01 1 1 5 quantized y value Value 1 25 is outside the range that can be exactly represented by the result fixed point type sc_fixed lt 3 2 SC_RND gt Therefore quantization will occur When the MSB of the deleted bits is added to the remaining bits the result will be 1 5 Here is another example using the same types but a negative value sc fixed 4 2 x sc fixed 3 2 SC RND y hie x quantization will occur here X 10 11 1 25 representation of x value 11 0 1 quantized y value Again 1 25 is outside the representable range for the result type so quantization occurs The MSB of the deleted bits is added to the remaining bits causing the result to be 1 The last example shows the result with unsigned types sc ufixed 10 8 x Sc ufixed 12 8 SC RND 5 y x 38 30859375 y x quantization will occur here 00100110 01001111 38 30859375 x value 00100110 0101 383125 quantized y value The MSB of the deleted bits is added to the remaining bits to return the result SystemC 2 0 User s Guide 107 Fixed Point Types SC RND ZERO
89. emory controller wait 1 clock between data transfers data8 taddr range 15 8 start false wait SystemC 2 0 User s Guide 61 Processes data8 taddr range 23 16 data8 taddr range 31 24 now wait for ready signal from memory controller wait until ready delayed true now transfer memory data to databus tdata range 7 0 data8 read tdata range 15 8 data8 read tdata range 23 16 data8 read tdata range 31 24 data tdata datardy true data is ready new addresses ok data8 read Notice that the constructor for module bus contains one SC_CTHREAD process The SC_CTHREAD process is different from the SC_THREAD process in a num ber of ways First the SC_CTHREAD process specifies a clock object When other process types are described in a module constructor they only have the name of the process specified but the SC_CTHREAD process has the name of the process and the clock that triggers the process An SC_CTHREAD does not have a separate sensitivity list like the other process types The sensitivity list is just the specified clock edge The SC_CTHREAD process will be activated whenever the specified clock edge occurs In this example the positive edge of the clock is specified so pro cess xfer will execute on every positive edge of the clock Notice also that the constructor for the module bus uses the initialize function of port datardy to in
90. ensitive rpackin channel cc include channel h void channel receive data Tnt i2 packin tpackin cout lt lt Channel Received packet seq no lt lt packin seq lt lt n i rand packout packin cout lt lt Channel Random number lt lt i lt lt endl if 1 gt 1000 i lt 5000 packout seq 0 rpackout packout void channel send_ack Int x ackin rpackin cout lt lt Channel Received Ack for packet SystemC 2 0 User s Guide 23 Starting with a Simple Example lt lt ackin seq lt lt i rand ackout ackin if i gt 10 amp amp i lt 500 ackout seq 0 tpackout ackout Ports The channel description contains four ports two input ports and two output ports Port tpackin accepts packets from the transmit module and port rpackin accepts acknowledge packets from the receiver Port tpackout sends acknowledge packets to the transmit module and port rpackout sends data packets to the receiver Data and Function Members Notice the four local packet variable declarations to hold the values of the packet ports Local variables are necessary so you can access the packet internal data fields The channel description has two processes Process receive_data is used to get data from the transmit module and pass the data to the receiver module Process send_ack gets acknowledge packets from the
91. er gets the frame from the channel and analyzes the contents If the sequence number of the frame matches the framenum variable then the expected frame was sent and received properly The receiver increments the fra menum to get ready for the next frame The receiver generates an acknowledgement frame containing the sequence number minus 1 Because the frame sequence number is already incremented the acknowl edgement frame needs to subtract 1 from the framenum to acknowledge the last frame received If the wrong frame was received the acknowledgement contains an improper sequence number to inform the transmitter that the proper frame was not correctly transmitted The last two functions in the C C model send data to the channel and get data from the channel These two functions are very simple in this model but they could be complex depending on the factors to be analyzed Function send data to channel simply copies the received frame from the transmitter to a local variable Function get data from channel reads the data from the local variable but adds noise to the data so some frames are not passed intact Noise is 14 SystemC 2 0 User s Guide SystemC Model generated by a random number generator that selectively zeroes the sequence num ber of the frame The amount of noise is dependent on the total range of the sequence numbers and the range of numbers that cause the sequence number to be zeroed Using the C
92. er s Guide Fixed Precision Unsigned and Signed Integers assignment occurs the result of the assignment is undefined and a runtime warning is issued Fixed Precision Unsigned and Signed Integers Some systems need arithmetic operations on fixed size arithmetic operands The Signed and Unsigned Fixed Precision Integer types provide this functionality in SystemC The C int type is machine dependent but usually 32 bits If the designer were only going to use 32 bit arithmetic operations then this type would work However the SystemC integer type provides integers from 1 to 64 bits in signed and unsigned forms The underlying implementation of the fixed precision type is a 64 bit integer All operations are performed with a 64 bit integer and then converted to the appropriate result size through truncation If the designer multiplies two 44 bit integers the maximum result size is 64 bits so only 64 bits are retained If the result is now assigned to a 44 bit result 20 bits are removed If more precision is needed use Arbitrary Precision Integers described in the next section The fastest simulation speed will be obtained by using the built in C data types int long etc However these types only work for a fixed data size of 8 16 or 32 bits The second fastest simulation speed can be obtained by using the Fixed Precision Integers The slow est simulation time will come from using the Arbitrary Precision Integers So whenever possibl
93. esent the values of the result The X axis is the starting value and the Y axis is the result From this graph we can see that MAX 3 and MIN 4 for a 3 bit type Values outside the positive representable range remain positive Values outside the negative representable range remain negative Notice that positive numbers wrap around to 0 while negative values wrap around to 1 130 SystemC 2 0 User s Guide SC WRAP n bits gt 0 SC_WRAP n_bits gt 0 Examples The original type for the next 2 examples is a signed 4 bit type The result type is a signed 3 bit type Parameter n bits is set to 1 which will saturate 1 MSB bit sc lt 4 4 gt x sc fixed 3 3 SC TRN SC 1 gt y x 5 y x overflow handling occurs here 0101 5 value of x after assignment 001 1 value of y after overflow handling Value 5 is outside the representable range of 3 bits Overflow will occur and the result wrapped to 1 still a positive number The next example shows a negative number sc lt 4 4 gt x sc fixed 3 3 SC TRN SC 1 gt y X 5 y x overflow handling occurs here 1011 5 value of x after assignment 111 1 vlaue of y after overflow handling Value 5 is outside the range for 3 bits so overflow will occur The sign bit will be retained and one bit saturated so the result will be 1 The next example uses an unsigned type This time n bits is specified as
94. etely described in SystemC the commands to build the simulator need to be specified The following sections provide procedures for com piling under UNIX and Windows Compiling the Example for UNIX The following steps are needed to compile the design for the UNIX environment 1 Create a new directory for the design and create all the design files in it 2 Copy file Makefile and Makefile defs from the SystemC installation examples directory into the new directory 3 Edit the Makefile so that the list of files includes all of the design source files An example Makefile is shown below TARGET ARCH gccsparcOS5 MODULE demo SRCS channel cc display cc packet cc receiver cc timer cc transmit cc main cc OBJS S SRCS cc 0 include Makefile defs Edit the SRCS line to list all of the source files in the design Don t remove the line include Makefile defs The MODULE line specifies the name of the executable to run when the compi lation is done In this example the compilation creates a program named demo 4 Open the Makefile defs and make sure that the SYSTEMC line points to the current location of the SystemC class libraries An example is shown below SystemC 2 0 User s Guide 35 Starting with a Simple Example TARGET ARCH gccsparcOS5 GC gt OPT DEBUG g SYSTEMC remote dtg403 dperry systemc 2 0 INCDIR I I I SYSTEMC include LIBDIR L L L
95. fter assignment 01 0 1 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization will be performed The quantization simply truncates the redundant bits before assign ment In this case the LSB is removed to create the necessary result The next example uses a negative number sc fixed 4 2 x Sc fixed 3 2 SC gt y x 1 25 y x quantization occurs here 10 11 1 25 value of x after assignment 10 1 71 5 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization will occur The LSB is simply removed creating the value 1 5 The next example shows the same quantization mode with an unsigned value sc ufixed 10 8 x sc_ufixed lt 12 8 SC_TRN gt y x 38 30859375 y x quantization occurs here 00100110 01001111 38 30859375 00100110 0100 38 25 The 4 LSBs are simply removed to create the new value 116 SystemC 2 0 User s Guide SC TRN ZERO SC TRN ZERO For positive numbers this quantization mode is exactly the same as SC For negative numbers the result is rounded towards zero The result is the first repre sentable number lower in absolute value than the starting value This is accom plished by deleting the redundant bits on the right side and adding the sign bit to the LSBs of the remaining bits However this only occurs if at least one of the
96. gnal can have the value 0 1 X and Z This signal can be driven by a number of sources to model a tristate bus It is very important to note that the extra space after the first gt is required to allow the declaration to compile SystemC 2 0 User s Guide 95 Data Types The operations that can be performed on an sc lv object are exactly the same as those for an sc bv object The only difference is the speed of the simulation The design implemented with sc bv will simulate much faster than the design imple mented with sc lv Notice that sc_lv types cannot have arithmetic performed directly on them To per form arithmetic functions first assign sc lv objects to the appropriate SystemC inte ger Perform the arithmetic operation on the integer type If the application warrants then copy the results of the arithmetic operations back to the lv type The operator is overloaded to allow assignment of asc lv type to a SystemC integer and vice versa To convert an 1 type to an arithmetic type use the operator This is shown below Sc uint 16 uint16 sc int 16 int160 sc lv 16 1v16 1 16 uintl16 convert uint to lv int16 l1v16 convert lv to int The first statement converts an unsigned integer to a logic vector 16 bits wide The second statement converts a logic vector to a 16 bit signed integer Any X s or Z s in the logic vector will produce a runtime warning and the results wi
97. ications 2 SystemC Highlights 3 Current System Design Methodology 4 SystemC Design Methodology 5 Compatibility with Earlier Versions of SystemC 7 Starting with a Simple Example 9 Simplex Data Protocol 9 C C Model 11 SystemC Model 15 User Defined Packet Type 16 Transmit Module 17 Channel Module 22 Receiver Module 25 SystemC 2 0 User s Guide iii Display Module 28 Timer Module 29 Putting it all together The main routine 31 Compiling the Example for UNIX 35 Compiling the Example for Windows 36 Executing the Example 37 CHAPTER 3 Modules and Hierarchy 39 Module Ports 40 Module Signals 41 Internal Data Storage 44 Processes 46 Module Constructors 47 TestBenches 49 CHAPTER 4 Processes 53 Basics 54 Method Process 54 Thread Processes 56 Clocked Thread Process 59 Wait Until 63 Watching 64 Local Watching 67 CHAPTER 5 Ports and Signals 71 Reading and Writing Ports and Signals 74 Array Ports and Signals 74 Resolved Logic Vectors 75 Resolved Vector Signals 77 Signal Binding 78 iv SystemC 2 0 User s Guide CHAPTER 6 CHAPTER 7 Clocks 80 Data Types 83 Typesc bit 84 Typesc logic 85 Fixed Precision Unsigned and Signed Integers 87 Speed Issues 90 Arbitrary Precision Signed and Unsigned Integer Types 91 Arbitrary Length Bit Vector 93 Arbitrary Length Logic Vector 95 Logic Vector Speed Issues 97 User Defined Type Issues 97 Fixed Point Types 101 Word Length and
98. ilt you run the simulation by executing the simulation executable created in the compilation step The simulation executable is a batch program that executes the simulation For example to run a simulation for a module named demo simply type demo at the command prompt and press return If you built a console application in Visual C you can run the application in a Win dows Command Prompt window by typing the name of the project created The duration of the simulation is specified by method sc start in the sc main mod ule The data created by the simulation is specified with the sc trace commands in the sc main module SystemC 2 0 User s Guide 37 Starting with a Simple Example When the simulation is complete a trace file of the traced signals is created You can use tools to view waveforms and tables from this data and analyze the results of simulation and determine whether or not the simulation succeeded 38 SystemC 2 0 User s Guide CHAPTER 3 Modules and Hierarchy Modules are the basic building block within SystemC to partition a design Mod ules allow designers to break complex systems into smaller more manageable pieces Modules help split complex designs among a number of different designers in a design group Modules allow designers to hide internal data representation and algorithms from other modules This forces designers to use public interfaces to other modules and the entire system becomes easier
99. imulation to initialize variable and signal values In SystemC the constructor of a module is 20 SystemC 2 0 User s Guide Transmit Module called at initialization and all initialization that needs to be performed is defined in the constructor The constructor initializes variable framenum to 1 which is used as the sequence number in all packets Variable retry is initialized to 0 and variable start is initial ized to false Then the buffer used to hold data is initialized by getting the first piece of data Implementation of Methods Let s now take a look at the transmit cc file This file implements the two methods declared in the header file One method is a process i e it executes concurrently with all other processes the other is not Method get data fromApp is a local method that generates a new piece of data to send across the channel In the implementation you can see that this method calls the random number generator rand to generate a new data value to send Because we are validating the effects of noise on the protocol the data values sent are not important at this stage of the design The method send data is a process because it is declared as such in the construc tor for module transmit The process checks first to see if timeout is true Timeout will be true when the timer has completed Next the process checks to see if the current value of port tpackin is equivalent to the old value This check
100. inout ports as shown below in packet type tpackin input port in bool timeout input port Sc out packet type tpackout output port SC inout bool start timer inout port Sc in bool clock input port Port tpackin is used to receive acknowledgement packets from the channel Port timeout is used to receive the timeout signal from the timer module and lets the transmit module know that the acknowledge packet was not received before the timer times out The clock port is used to synchronize the different modules together so that events happen in the correct order Output port tpackout is the port that module transmit uses to send packets to the channel Inout port start timer is used by the transmit module to start the timer after a packet has been sent to the channel Data and Function Members After the port statements local data members used within the module are declared The function members send data and get data fromApp are declared in the transmit h file and implemented in the transmit cc file This is the standard way to describe functionality in C and SystemC Constructor The module constructor identifies process send data as an SC METHOD pro cess which is sensitive to clock and timeout The constructor also initializes the variables used in the module This is an important step In HDL languages such as VHDL and Verilog all processes are executed once at the beginning of s
101. int Types The standard fixed point types described previously use arbitrary precision in cal culations This adds extra overhead that in most cases might not be needed Sys temC provides limited precision fixed point types to speed simulation when limited precision is all that s required With standard fixed point types the mantissa can be virtually any size With limited precision fixed point types the mantissa is limited to 53 bits Limited precision fixed point types are implemented with double precision floating point values The range of representation of limited precision fixed point types is limited by the size of the double precision floating point value representation The 4 limited precision fixed point types are listed below sc fixed fast sc ufixed fast sc fix fast sc ufix fast The limited precision types have exactly the same interface as the arbitrary preci sion fixed point types The same parameter names types and order are used to form both kinds of fixed point types Also limited precision and arbitrary precision types can be mixed freely To get bit true behavior for a design follow these guidelines Make sure that the result of any operation with fast fixed point types does not generate a word length greater than 53 bits When adding or subtracting two operands the result word length will be 1 more than the maximum aligned word length When multiplying two operands the resulting bit length will
102. ion and 4 bits right of the binary point When writing to the second fixed point object with only 2 bits to the right of the binary point 2 bits will have to be removed How these bits are removed is a function of the quantization mode XXXXXXXX XXXX 12 bits 4 right of binary point XXXXXXXX XX 10 bits 2 right of binary point The next sections are going to describe each of the quantization modes in more detail SystemC 2 0 User s Guide 105 Fixed Point Types SC RND The SC RND mode will round the value to the closest representable number This is accomplished by adding the MSB of the removed bits to the remaining bits The effect is to round towards plus infinity A graph showing the effect of this rounding is shown below The x axis is the result of the previous arithmetic operation and the y axis is the value after quantization y oo 4 2 3q 24 lt 4 47 et 2 9 24 3q 4 e 7 The diagonal line shows the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be rounded to the y value of the line The graph is given in terms of q which is the smallest quantization unit of the target object SC_RND Examples The first example will show the SC_RND quantization mode with a positive num ber Two objects x and y are declared as sc_fixed types A value is assign
103. ion and Debugging Using SystemC 162 SystemC 2 0 User s Guide Appendix A VHDL Designer 5 Guide This section will focus on helping VHDL designers learn how to write different types of models in SystemC This section will present several complete models in SystemC and VHDL so that the VHDL designer can compare and contrast these models and learn how to write better SystemC models DFF Examples D flip flops are one of the basic building blocks of RTL design Here are a few examples of some VHDL D flip flops and the corresponding SystemC models for comparison Synchronous D Flip Flop Here is the VHDL Model for a standard RTL D flip flop library ieee use ieee std logic 1164 11 entity dff is port clock in std logic din in std logic dout out std logic SystemC 2 0 User s Guide 163 end dff architecture rtl of dff is begin process begin wait until clock event and clock 1 dout din end process end rtl Here is a corresponding SystemC model SystemC Implementation dff h include systemc h SC MODULI Gl dff sc_in lt bool gt din sc_in lt bool gt clock sc_out lt bool gt dout void doit dout din SC dff SC METHOD doit sensitive pos clock 164 SystemC 2 0 User s Guide DFF Examples D Flip Flop with Asynchronous Reset One of the most common flip flops used in designs is
104. ion for SystemC 2 0 document SystemC simulation is cycle based processes are executed and signals are updated at clock transitions The SystemC library includes a cycle based scheduler that han dles all events on signals and it schedules processes when the appropriate events happen at their inputs SystemC simulation follows the evaluate update paradigm where all processes that are ready to be executed are executed and only then are their output signals updated SystemC 2 0 User s Guide 153 Simulation and Debugging Using SystemC The scheduler in SystemC executes the following steps during simulation 1 All clock signals that change their value at the current time are assigned their new values 2 All SC METHOD SC THREAD processes with inputs that have changed are executed The entire body of SC METHOD function processes are executed while SC THREAD processes are executed until the next wait statement sus pends execution of the process SC METHOD SC THREAD processes are not executed in a fixed order All SC CTHREAD processes that are triggered have their outputs updated and they are saved in a queue to be executed later in step 5 All outputs of SC METHOD SC THREAD processes that were executed in step 1 are also updated 4 Steps 2 and 3 are repeated until no signal changes its value 5 AIL SC CTHREAD processes that were triggered and queued in step 3 are exe cuted There is no fixed execution order of these pr
105. ion for object of less than 64 bits Also notice that port data is an inout rv type The port needs to be inout and needs the ability to tristate the output A resolved vector type will allow the output to tristate and still be able to connect to tristate busses The ram module contains two SC METHOD processes One for reading the ram and one for writing the ram Notice that the process that writes the ram also has to be sensitive to changes on input port data so that the proper value gets written into the ram ram h include systemc h SC MODULE ram SystemC 2 0 User s Guide 179 Sc in sc int 8 gt addr sc lt 1 gt enable Sc lt 1 gt readwr sc inout rv 16 data void read data void write data Sc lv 16 ram data 250 SC ram SC_METHOD read_data sensitive lt lt addr lt lt enable lt lt readwr SC_METHOD write_data sensitive lt lt addr lt lt enable lt lt readwr lt lt data include ram h void data if enable amp amp readwr data ram data addr read else data void ram write data if enable amp amp readwr 01 2222222222222222 ram data addr read data 180 SystemC 2 0 User s Guide Appendix B Verilog Designers Guide This section is for Verilog designers wanting to learn how to write goo
106. itches set to compile for Visual C 6 0 Select Build exam ple exe under the Build menu or press F7 to build the example executable To create a new design first create a new project by using the New menu item under the File menu Select the Projects tab on the dialog box that appears and select Win32 Console Application Create an empty project For your own SystemC applications make sure that the Run Time Type Informa tion switch is on by using the Settings menu item under the Project menu Select the C C tab and select the C Language category Make sure that the Enable Run Time Type Information RTTI checkbox is checked Also make sure that the SystemC header files are included by selecting the C C tab selecting the Preprocessor category and typing the path to the SystemC src directory in the text entry field labeled Additional include directories The exam ples use e g src Next add the source files to the project by using the Add To Project gt Files menu item under the Project menu Make sure that the files are added to the new project directory just created Do the same for the systemc lib library before building your SystemC application Now use the Compile and Build menu selections to compile and build the SystemC application When the application has been built the design can be run from Visual C to debug the application Executing the Example After the simulation executable is bu
107. itialize it to true In case a port is not yet bound this is the only 62 SystemC 2 0 User s Guide Wait Until way to initialize it A direct assignment to the port or calling the write function of the port will cause an error The latter two ways of initializing a port only works if the port is already bound When the process first starts execution will stop at the first wait until method A wait until function will suspend execution until the expression passed as an argu ment is true Once the newaddr signal has become true the process will assume that a new address value exists on port addr One point to keep in mind is that signals assigned new values by an SC CTHREAD process will be not be available until after the next clock edge occurs The addr value will now be placed on output signal data8 one byte at a time When the first value of addr is output the start signal is activated to let the memory con troller know that a new address is coming Once all of the address values have been sent the process will now wait for the ready signal to come back from the memory controller signaling that the memory data is ready to be read The SC CTHREAD process will continue to be activated every clock edge but execution will not con tinue until the wait until condition becomes true See the wait until description in the next section Once the wait until condition becomes true the process will continue by reading the da
108. l Ports din and dout are 8 bit vector ports Internally an int named countval is used to hold the value of the counter When clear is a 1 countval is set to 0 When load is a 1 countval is set to the value on port din Notice the read method used when the port is read This method is used because an implicit type conversion is happening when din is assigned to countval This method helps SystemC determine the type of the port easier so that the correct conversion func tion can be called counter h include systemc h SC MODULE counter sc_in lt bool gt clock sc_in lt bool gt load sc_in lt bool gt clear sc_in lt sc_int lt 8 gt gt din sc_out lt sc_int lt 8 gt gt dout int countval 170 SystemC 2 0 User s Guide State Machine void onetwothree SC counter SC METHOD onetwothree sensitive_pos clock counter cc include counter h void counter onetwothree if clear countval 0 else if load countval din read use read when a type conversion is happening from an input port else countvaltt dout countval State Machine The next example is a state machine This example represents a state machine within a voicemail controller The state machine will start in the main state and then transition to a send state or review state depending on user inputs From the review or send states the user
109. layed Let s examine each block to see the descriptions and how they work User Defined Packet Type Before we describe the blocks we need to look at the underlying packet data struc ture that passes data from module to module The packet type is defined by a struct as shown below packet h file ifndef PACKETINC define PACKETINC include systemc h struct packet_type long info int seq int retry inline bool operator const packet type amp rhs const return rhs info info amp amp rhs seq seq amp amp rhs retry retry extern void sc trace sc trace file tf const packet type amp v const sc string amp NAME packet cc file include packet h 16 SystemC 2 0 User s Guide Transmit Module void sc trace sc trace file tf const packet type amp v const sc string amp NAME sc trace tf v info NAME info sc trace tf v seq NAME seq sc trace tf v retry retry The struct has three fields info seq and retry Field info carries the data sent in the packet The goal of this simulation is to measure the protocol behavior with respect to noise not the data transfer characteristics Therefore the info field for data is of type long Future versions of this data packet type could use a struct type for the data The second field is named seq and represents the sequence number assigned
110. le described on page 44 is shown below count stim h include systemc h SC MODULE count stim Sc out bool load sc_out lt int gt din input port sc_in lt bool gt clock input port sc_in lt int gt dout void stimgen SC CTOR count stim SC THREAD stimgen sensitive pos clock count stim cc include count stim h void count stim stimgen while true load true load 0 din 0 wait count up value 1 50 SystemC 2 0 User s Guide TestBenches load false wait count up value 2 wait count up value 3 wait count up value 4 wait count up value 5 wait count up value 6 wait count up value 7 The testbench will drive the load and din inputs of the count module The clock input of the count module and the clock input of the count stim module will be generated from a clock object located in the main routine discussed in the next section The first two statements in the while loop of the process will load the value 0 into the count module The count module is loaded when the load input is true The value loaded into the count module is the value of din When the load signal goes to false and a positive edge occurs on input clock the counter will count up After the first wait call the load input will be set to false allowing the counter to count up Successive clocks will all
111. lk of the controller This is an example of a special case binding in which a port is bound directly to another port instead of a signal The second port binding is shown below sl gt en lstat This statement binds port en of s1 to local signal Istat This is an example of Named Mapping as discussed in Named Connection on page 43 Positional Mapping is discussed in Positional Connection on page 42 SystemC 2 0 User s Guide 79 Ports and Signals Clocks Clock objects are special objects in SystemC They generate timing signals used to synchronize events in the simulation Clocks order events in time so that parallel events in hardware are properly modeled by a simulator on a sequential computer A clock object has a number of data members to store clock settings and methods to perform clock actions To create a clock object use the following syntax se clock clockl cGlockl 20 0 5 2 true This declaration will create a clock object named clock with a period of 20 time units a duty cycle of 50 the first edge will occur at 2 time units and the first value will be true All of these arguments have default values except for the clock name The period defaults to 1 the duty cycle to 0 5 the first edge to 0 and the first value to true Typically clocks are created at the top level of the design in the testbench and passed down through the module hierarchy to the rest of the design This allows are
112. ll reap similar benefits as hardware designers Compatibility with Earlier Versions of SystemC SystemC 2 0 is fully backwards compatible with earlier versions of SystemC except SystemC versions 0 9x The following syntax and classes from SystemC 0 9x are no longer supported sc bool vector sc logic vector sc array sc 2d sc signal bool vector sc signal logic vector sc signal array sc signal resolved vector sc channel sc sync 5 sc async SystemC 2 0 User s Guide 7 Introduction 8 SystemC 2 0 User s Guide CHAPTER 2 Starting with a Simple Example This section shows you a simple data protocol model example written first in C C The same model is then implemented in SystemC to show the highlights of using SystemC along with instructions for compiling executing and debugging the design SystemC syntax and details about usage are described in subsequent chapters Simplex Data Protocol The simplex data protocol is a simple data protocol used to transfer data from one device to another in a single direction A duplex data protocol would transfer data in both directions The simplex data protocol can detect transfer errors and it can resend data packets to successfully complete the data transfer if errors are detected The basic design consists of a transmitter a receiver and a model representing the data transfer medium or channel The
113. ll be undefined A common function needed to properly model a tristate bus is the ability to turn off all drivers to the bus To perform this step assign a string of Z values to the sc lv object This is shown below Sc lv 16 if enable busl inl else busl ZZZZZZZZZZZZZZZZ 96 SystemC 2 0 User s Guide Logic Vector Speed Issues This assignment will assign Z value to all 16 locations of bus1 The character string has to be at least as long as the logic vector object The character string can contain any combination of the four values 0 1 X and Z So another legal string for bus would be the following busl 01 201 201 201 2 To print a human readable character string of the value from an sc 1 object use the to_string method as shown sc_lv lt 32 gt bus2 cout lt lt bus lt lt bus2 to string Logic Vector Speed Issues The bit vector type will always simulate faster than the logic vector type When cre ating a design try to use the bit vector types over the logic vector types as much as possible The logic vector type will be needed to model the cases where the reset behavior of the design is important or the vector will be used in a tristate environ ment For all other cases the bit vector type should be used to create the fastest sim ulation User Defined Type Issues Comparison Operator For scalar types the
114. lled whenever a positive edge occurs on port clock This behavior is described by the following statements in the constructor for mod ule dff SC METHOD doit sensitive pos clock The first statement specifies that module dff contains a process named doit It also specifies that this process is an SC METHOD process An SC METHOD process is triggered by events and executes all of the statements in the method before returning control to the SystemC kernel more about processes later The second statement specifies that the process is sensitive to positive edge changes on input port clock The process runs once when the first event positive edge on clock is received It executes the assignment of din to dout and then returns control to the SystemC ker nel Another event causes the process to be invoked again and the assignment statement is executed again Module Constructors The final item that makes up a module is the constructor The module constructor creates and initializes an instance of a module The constructor creates the internal data structures that are used for the module and initializes these data structures to known values The module constructors in SystemC are implemented such that the SystemC 2 0 User s Guide 47 Modules and Hierarchy instance name of the module is passed to the constructor at instantiation creation time This helps identify the module when errors occur or when reporting info
115. lock load clear din dout input clock load clear input 0 7 din output 0 7 dout wire 0 7 dout reg 0 7 countval assign dout countval always 8 posedge clock begin if clear countval 0 else if load countval d else countval countval 1 end endmodule SystemC Implementation Here is the SystemC implementation of the counter Input ports clock load and clear are of type bool Ports din and dout are 8 bit vector ports Internally an int named countval is used to hold the value of the counter When clear is a 1 countval is set to 0 When load is a 1 countval is set to the value on port din Notice the read method used when the port is read This method is used because an implicit type conversion is happening when din is assigned to countval This method helps SystemC determine the type of the port easier so that the correct conversion func tion can be called counter h SystemC 2 0 User s Guide 187 include systemc h SC MODULE counter sc_in lt bool gt clock sc_in lt bool gt load sc_in lt bool gt clear sc_in lt sc_int lt 8 gt gt din sc_out lt sc_int lt 8 gt gt dout int countval void onetwothree SC_CTOR counter SC METHOD onetwothree sensitive_pos clock counter cc include counter h void counter onetwothree if clear countval 0 else if load countval din re
116. ls SystemC supports untimed models at different lev els of abstraction ranging from high level functional models to detailed clock cycle accurate RTL models It supports iterative refinement of high level models into lower levels of abstraction SystemC 2 0 User s Guide 3 Introduction Communication protocols SystemC provides multi level communication semantics that enable you to describe SoC and system I O protocols with differ ent levels for abstraction Debugging support SystemC classes have run time error checking that can be turned on with a compilation flag e Waveform tracing SystemC supports tracing of waveforms in VCD WIF and ISDB formats Current System Design Methodology The current system design methodology starts with a system engineer writing a C or C model of the system to verify the concepts and algorithms at the system level After the concepts and algorithms are validated the parts of the C C model to be implemented in hardware are manually converted to a VHDL or Verilog description for actual hardware implementation This is shown in the figure below C C System Level Model E Manual Conversion VHDL Verilog Refine Results Rest of Process SystemC 2 0 User s Guide SystemC Design Methodology There are a number of problems with this approach Manual Conversion from C to HDL Creates Errors With the current methodology
117. ly more verbose The read and write meth ods are called by an implicit conversion defined within the port class If you need an implicit type conversion because the type that you are reading or writing is different from the port type for example if a port is a bool and you are reading or writing an int it is important that you use the read and write meth ods C automatically applies only one implicit type conversion at any particular location and you need two implicit conversions to read and write a different type than the port type Array Ports and Signals For some applications an array of ports might be desirable For instance computer generated design descriptions might use an array of ports for mapping configurable sized objects To declare an array port or signal the same syntax as C is used An example is shown below Sc in sc logic a 32 creates ports a 0 to a 31 74 SystemC 2 0 User s Guide Resolved Logic Vectors of type logic This declaration creates an array of ports named a 0 to a 31 of type sc logic Each port has to be individually bound to a port assigned and read Signal arrays can be created using similar syntax An example signal array is shown below Sc signal sc logic i 16 creates signals i 0 to i 15 of type sc logic This statement creates an array of signals named i 0 to i 15 of type sc logic Each signal has to be individually bound to a
118. mC 2 0 User s Guide 155 Simulation and Debugging Using SystemC Using this capability you can inject events asynchronously with respect to the clock into the system as shown in the following drawing FIGURE 4 Signal Asynchronous to Clock clock reset To implement this you can write the following in sc main Sc initialize Let the clock run for 10 cycles for int i 0 i lt 200 i clock 1 sc 1 clock 0 sc cycle 1 0 0 Inject asynchronous reset clock 1 sc cycle 5 reset 1 sc cycle clock 0 sc_cycle 10 clock 1 sc_cycle 5 reset 0 156 SystemC 2 0 User s Guide Tracing Waveforms sc cycle 5 clock 0 e 1 Sc cycl 0 Now let the clock run indefinitely for clock 1 5 cycle 10 clock 0 sc_cycle 10 Note that sc cycle can only be called from the top level similar to sc start Tracing Waveforms SystemC provides functions that let you create a VCD Value Change Dump ASCII WIF Waveform Intermediate Format or ISDB Integrated Signal Data Base file that contains the values of variables and signals as they change during simulation The waveforms defined in these files can be viewed using standard waveform viewers that support the VCD WIF or ISDB formats In generating waveforms note the following e Only
119. mber of command line arguments and the argv is an array containing the arguments as char strings This is the standard C way of parsing command line arguments to programs Signals After the sc main statement the local signals are declared to connect the module ports together Four signals are needed for packet type to cross connect the trans mit receiver and channel modules There are two clock declarations clock and rclk Clock is used as the transmitter clock and will synchronize the transmit block and the timer block Rclk is used as the receiver clock and will synchronize the receiver block and the display block Module Instantiation After the declaration statements the modules in the design are instantiated The transmit channel receiver display and timer are instantiated and connected SystemC 2 0 User s Guide 33 Starting with a Simple Example together with the locally declared signals This completes the implementation of the design Positional and Named Connections In the sc main file two different types of connections were used to connect signals to the module instantiations Modules transmit channel and receiver used named connections named connection connects a port name to a signal name Notice that the port names were in lowercase and the signal names in uppercase Modules display and timer used positional connections to connect signals to the module instantiations With this style of connecti
120. mentation uses two enum types to represent the state of the state machine and the state of the key values passed to the state machine The state machine implementation consists of two SC METHOD processes SC METHOD processes are by far the most efficient processes and should be used where possible Process getnextst calculates the new state of the state machine based on the current state and the input values Process setstate copies the calculated next state to the current state every positive clock edge on input clk stmach h include systemc h enum vm state main st review st repeat st save st erase st send st address st record st begin rec st message st SC MODULE stmach sc_in lt bool gt clk sc_in lt char gt key sc_out lt sc_logic gt play sc_out lt sc_logic gt recrd sc_out lt sc_logic gt erase sc_out lt sc_logic gt save sc_out lt sc_logic gt address sc_signal lt vm_state gt next_state sc_signal lt vm_state gt current_state void getnextst void setstate SC CTOR stmach SC METHOD getnextst 192 SystemC 2 0 User s Guide State Machine sensitive key current state SC METHOD setstate sensitive pos clk stmach cc include stmach h void stmach getnextst play 5 0 0 recrd SC LOGIC 0 erase 5 LOGIC 0 save SC LOGIC 0 address SC LOGIC 0 switch current state
121. mes Local value shiftval is needed because the value of output ports cannot be read Notice that at the end of the process shiftval is assigned to dout If load is not active the process will check the value of input LR and perform the appropriate action based on the value of LR To perform the actual shifting opera tion notice that process shifty uses the range method Here is the SystemC implementation shift h SystemC 2 0 User s Guide 185 include systemc h SC MODULE shift sc_in lt sc_bv lt 8 gt gt din sc_in lt bool gt clk sc_in lt bool gt load sc_in lt bool gt LR sc_out lt sc_bv lt 8 gt gt dout sc_bv lt 8 gt shiftval void shifty SC CTOR shift SC_METHOD shifty sensitive_pos clk shift include void shi shift h ft shifty if load hi ls hi hi An DAD OD Fh Fh D hh O H dout tval din if LR tval range 0 6 shiftval tval 7 00 if LR tval range 1 7 shiftval tval 0 70 shiftval l range 1 7 L range 0 6 186 SystemC 2 0 User s Guide Counter Counter The next example is an 8 bit counter This counter can be set to a value by setting the value of input load to 1 and placing the value to load on input din The counter can be cleared by setting input clear to a 1 Below is the Verilog implementation module counter c
122. n lt long gt din input port void print data Constructor SC CTOR display SC METHOD print data Method process to print data sensitive din display cc include display h void display print data cout lt lt Display Data Value Received Data din An 28 SystemC 2 0 User s Guide Timer Module This module only has one input port named din It accepts data values from the receiver module When a new value is received process print data is invoked and writes the new data item to the output stream Timer Module The timer module implements a timer for packet retransmission The delay allows a packet to propagate to the receiver and the acknowledge to propagate back before a retransmit occurs Setting the delay properly is a key factor in determining the max imum data rate in a noisy environment Without the timer the transmitter would not know when to retransmit a packet that was lost in transmission The delay value is a parameter that can easily be modified to find the optimum value The timer module is shown below timer h include systemc h SC MODULE timer Sc inout bool start input port out bool timeout output port Sc in bool clock input port int count void runtimer Constructor SC CTOR timer SC THREAD runtimer Thread process sensitive pos clock sensitive start
123. n of the objects to be instantiated in the design You declare a pointer variable for each object that will be instantiated later Next the local signal are declared using SystemC template class sc signal The type of the signal being passed is entered between the angle brackets In this example the type of the signal is a SystemC data type sc uint Notice that there is an extra space inserted between the 32 gt and the gt in the declaration This is required to allow the description to compile The three modules in this design are instantiated in the constructor SC Each instantiation contains two line of SystemC description The first line creates a new object and a pointer to the object The second line uses the object pointer to map signals to the object ports This style of mapping is called positional mapping Each signal in the mapping matches the port of the instantiated module on a posi tional basis The first signal listed in the mapping connects to the first port in the instantiation the second signal connects to the second port etc The order and num ber of ports in this style of mapping is very important If the order is not followed properly signals of one type can get connected to ports of another type This will produce a runtime error Positional connections can work very well for small instantiations with few ports to make the description small However for instantiations with a large number of por
124. n ports are bound to other signals or ports both types must match The exam ple below shows a port bound to another port special case and a port bound to a signal statemach h include systemc h SC MODULE state machine Sc in sc logic clock Sc in sc logic en Sc out sc logic dir Sc out sc logic status other module statements controller h include statemach h SC MODULE controller Sc in sc logic clk Sc out sc logic count Sc in sc logic status Sc out sc logic load Sc out sc logic clear 5 signal so logic lstat Sc signal sco logic down state machine 51 SC CTOR controller 76 SystemC 2 0 User s Guide Signal Binding other module statements sl new state machine 51 51 gt 1 special case port to port binding sl gt en lstat port en bound to signal lstat sl dir down port dir bound to signal down sl gt st status special case port to port binding This example shows a controller module with a number of input and output ports The module also includes local signals Istat and down The controller module instantiates module state machine with an instance label of s1 Below the state machine instance are the port binding statements The first statement sl gt clock clk binds port clock of instance s1 to external port c
125. n returns the current simulation time in a vari able of type double To aid in debugging during simulation variables ports and signal values can be read and printed The printed value of a port or a signal is the current value of the port or signal not a value just written to it Advanced Simulation Control Techniques You have the option to use a different method to generate clocks and control simu lation than using sc start To do that you have to first call initialize to initial ize the SystemC scheduler Then you can set signals to values by writing to them and calling the routine sc cycle to simulate the result of setting the signals This function takes a variable of type double as an argument It calls the SystemC sched uler simulates until the current effects of the signal writes are propagated through out the system It then advances simulation time by the amount given as the argument to the function For example if the default time unit is 1 ns sc cycle 10 advances the simulation time by 10 ns For examples assume you have defined a clock as Sc clock clk my clock 20 0 5 You can simulate the generation of clocks for 200 default time units by calling sc start 200 On the other hand you can generate the clock yourself by doing the following Sc signal bool clock sc initialize for int i 0 i lt 200 i clock 1 sc_cycle 10 clock 0 sc_cycle 10 Syste
126. nce apart If not SC RND quantization mode is applied Other wise the number is rounded towards plus infinity if positive or minus infinity if negative For positive numbers the MSB of the deleted bits is added to the remain ing bits For negative numbers the redundant bits are deleted A graph showing this behavior is shown below The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SC RND INF Examples Three examples will be shown The first two use signed numbers and the last one an unsigned number The first example shows quantization of a positive number and the second quantization of a negative number 112 SystemC 2 0 User s Guide SC RND INF sc lt 4 2 gt x Sc fixed 3 2 SC RND gt y 1 25 quantization occurs here X 01 01 1 25 value of x after assignment 01 1 1 5 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization will occur Since this is a positive number the MSB of the deleted bits is added to the remaining bits resulting in the value 1 5 Here s the same quantization mode with a negative number sc fixed 4 2 x Sc fixed 3 2 SC RND gt y x 1 25 y x quantization occurs here 10 11 1 25 value of
127. nd no read or write operations can be performed To read a location set enable to 1 readwr to 0 and apply the appropriate address To write a location set enable to I readwr to 1 addr to the appropriate location to write and data to the data value to write The model is implemented in VHDL with a single process so that a variable can be used to store the memory data Notice that the SystemC implementation uses two processes one for read and one for write Here is the VHDL model library ieee use ieee std_logic_1164 all use ieee std_logic_unsigned all entity ram is port enable in std logic readwr in std_logic addr in std_logic_vector 7 downto 0 data inout std_logic_vector 15 downto 0 178 SystemC 2 0 User s Guide Memory end ram architecture rtl of ram is begin process addr enable readwr subtype datal 6 is std logic vector 15 downto 0 type ramtype is array 0 to 255 of datalo variable ramdata ramtype begin if enable 1 then if readwr 70 then data lt ramdata conv integer addr elsif readwr 1 then ramdata conv integer addr data end if else data lt ZZZZZ4Z4ZZ4242424442442 end end process end rtl SystemC Implementation The SystemC implementation has similar port types to the VHDL model but opti mized for SystemC Notice that addr is an int of 8 bits This is the most efficient implementat
128. nd param3 mean that these parameter sets will not be currently active These sets can be activated later by using a begin method on variables c 1 and c 3 This will be shown below sc fix a is equivalent to sc fix 32 3 SC RND SC SAT a because param2 is the default parameter set l begin parameters specified in paraml are from now on the new default ones This is because paraml has only word length and integer word length speciifed the quantization and overflow modes are the built in ones SC TRN SC WRAP sc fix b is equivalent to sc fix 12 3 SC TRN SC WRAP b because parameter set 1 is now active 3 begin This will activate parameter set param3 making the default sc fix c This declaration will use parameter set param3 just activated so this declaration is equivalent to sc fix 16 16 SC TRN SC SAT ZERO 144 SystemC 2 0 User s Guide Type sc fxtype context sc fixed 13 5 zz This declaration is equivalent to sc fixed 13 5 SC TRN SC WRAP zz The context has no influence for fixed point types sc fixed and sc ufixed the built in defaults are always used c 3 end This will turn off the c 3 context so paramter set param3 is no longer valid Parameter set parami will now be activated again sc fix d Parameter set paraml is used so this declaration is equivalent to sc fix 12 3 SC TRN
129. ned number The third example shows an unsigned number sc lt 4 2 gt x Sc fixed 3 2 SC RND MIN gt y 110 SystemC 2 0 User s Guide SC RND MIN INF x 1 25 y x quantization occurs here 01 01 1 25 value of x after assignment 01 0 1 value of y after quantization Value 1 25 is outside the representable range of the result type so quantization will occur For positive numbers the redundant bits are simply deleted resulting in the value 1 The next example uses the same types but a negative number sc fixed 4 2 x Sc fixed 3 2 SC RND MIN gt y 12 255 quantization occurs here X 10 11 1 25 value of x after assignment 10 1 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization occurs The result number is rounded towards minus infinity by removing the redundant bits This produces the result 1 5 The last example uses an unsigned number Sc ufixed 14 9 x sc ufixed 13 9 SC RND ZERO y x 38 28125 y x quantization occurs here 000100110 01001 38 28125 x after assign 000100110 0100 38 25 y after quantization For unsigned types the redundant bits are simply deleted SystemC 2 0 User s Guide 111 Fixed Point Types SC RND INF This quantization mode also checks to see that the two nearest representable num bers are equal dista
130. nsitive roadsensor sensitive pos clock traff cc include traff h void traff control lights NSred false llow false NSgreen EWred true llow false EWgreen false true while true while roadsensor fals wait NSgreen NSyellow true NSred false for i20 i 5 wait false i NSgreen false NSyellow false NSred true EWgreen EWyellow EWred false for 0 1 lt 50 wait set set true false i i NSgreen NSyellow NSred EWgreen false EWyellow true EWred false false false true set times up for road sensor triggered set NS to yellow yellow interval over NS to red EW to green EW green EW to yellow SystemC 2 0 User s Guide 57 Processes for 0 i 5 i times up for EW yellow wait NSgreen true set EW to red NSyellow false set NS to green NSred false EWgreen false EWyellow false EWred true for i20 i 50 i wait one more long wait interval before allowing a sensor again This module is a simple traffic light controller There is a main highway running North South that normally has a green light A highway sensor exists on the East West road that crosses the highway A
131. o understand and maintain Each change of state in the traffic light controller would have to be declared as a state in a state machine Thread processes are implemented as co routines and with the SystemC class library This implementation is slower than SC METHOD processes If simulation speed is a current goal of the simulation limit the SC THREAD processes as needed to maintain the highest simulation speed Clocked Thread Process Clocked Thread Processes are a special case of a Thread Process Clocked Thread Processes help designers describe their design for better synthesis results Clocked Thread Processes are only triggered on one edge of one clock which matches the way hardware is typically implemented with synthesis tools Clocked threads can be used to create implicit state machines within design descriptions An implicit state machine is one where the states of the system are not explicitly defined Instead the states are described by sets of statements with wait function calls between them This design creation style is simple and easy to understand An explicit state machine would define the state machine states in a declaration and use a case statement to move from state to state To illustrate the Clock Thread Process a bus controller example will be presented The example is a bus controller for a microcontroller application It is a very simple design so that the design can be described easily Let s assume that we have a
132. occur Returns false if no quantization on To use one of the methods append the method name to the variable name with a as shown below if myvariable is zero do something In this example if myvariable is O the if statement will be true Converting Fixed Point Types to Strings The value of a fixed point type can be converted to a character string with the to stringO method This method takes two arguments The first argument specifies the number representation of the result and the second specifies fixed or scientific format The number representation argument is specified by one of the arguments from the table below Value Description Prefix SC DEC decimal sign magnitude SC BIN binary two s complement 0b SC BIN US binary unsigned Obus SC_BIN_SM binary sign magnitude Obsm SC_OCT octal two s complement 0o SC OCT US octal unsigned 0ous SC OCT SM octal sign magnitude 0osm SC HEX hexadecimal two s complement Ox SC_HEX_US hexadecimal unsigned Oxus 148 SystemC 2 0 User s Guide Arrays of Fixed Point Types SC HEX SM hexadecimal sign magnitude Oxsm SC CSD canonical signed digit Ocsd To specify how a number is represented use the following syntax varname to_string number representation format Both arguments are optional The default number representation is SC_DEC The second argument format can be SC_
133. ocesses Their outputs are updated at the next active edge when step 3 is executed and therefore are saved internally 6 Simulation time is advanced to the next clock edge and the scheduler goes back to step 1 If processes communicate using signals the process execution order should not affect the simulation results However if global variables and pointers are used process execution order affects the simulation results Note that these simulation semantics are similar to Verilog simulation semantics with deferred signal assign ments and VHDL simulation semantics Simulation Control You can only start simulation after you instantiate and properly connect all modules and signals In SystemC simulation starts by calling sc start from the top level namely the main routine The sc start function takes a variable of type dou ble as an argument and simulates the system for as many default time units as the value of the variable If you want the simulation to continue indefinitely provide a negative value for the argument to this function This routine generates all the clock signals at the appropriate times and calls the SystemC scheduler 154 SystemC 2 0 User s Guide Simulation Control Simulation can be stopped anytime from within any process by calling stop The function does not take arguments You can determine the current time during simulation by calling sc simulation time This functio
134. odule The signal transfers data from one port to another as if the ports were directly connected When a port is read the value of the signal connected to the port is returned When a port is written the new value will be written to the signal when the process perform ing the write operation has finished execution or has been suspended This is done so that all operations within the process will work with the same value of the signal This is to prevent some processes seeing the old value while other processes see the new value during execution All processes executing during a time step will see the old value of the signal These signal semantics are the same as VHDL signal opera tion and Verilog deferred assignment behavior Ports are always bound to a signal except for one special case when a port is bound directly to another port Ports are always bound to only one signal That signal may be a complex signal such as a structure but it is still treated as one signal Signal binding occurs during module instantiation When building a hierarchical design structure modules are instantiated within other modules to form the hierarchy of the design The special case binding men tioned earlier occurs when a top level module port is directly bound to a lower level module port during instantiation This is shown in the figure below PCI data din Fifo No signal required 72 SystemC 2 0 User s Guide
135. of y after overflow handling Value 14 is outside the range for a 3 bit unsigned type so overflow mode will return MAX 7 as the result SystemC 2 0 User s Guide 127 Fixed Point Types SC WRAP With the wrap overflow modes the value of an arithmetic operand will wrap around from MAX to MIN as MAX is reached The unsigned case is similar to the way a counter would work in hardware When the MAX value is reached the counter would wrap around to 0 again There are two different cases within the SC WRAP overflow mode The first is with the n bits parameter set to 0 or having a default value of 0 The second is when the n bits parameter is a nonzero value SC WRAP bits 0 The first case is the default overflow mode With this overflow mode any MSB bits outside the range of the target type are deleted The graph below shows the behav ior of this overflow mode x e The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots represent the values of the result The X axis is the starting value and the Y axis is the result From this graph we can see that MAX 3 and 128 SystemC 2 0 User s Guide SC WRAP n_bits 0 MIN 4 for a 3 bit type Notice that as the input value approaches the MAX value the next value is the MIN value Also the next value smaller than MIN is MAX SC WRAP n bits 0 Examples The next two examples assume the
136. on a list of signals is passed to the instantiation and the first signal in the list connects to the first port the second sig nal to the second port etc Using Trace The program can now be built and run To make is easier to determine if the design works as intended you can create a trace file with the built in signal tracing meth ods in SystemC The first trace command shown below creates a trace file named simplex vcd into which the results of simulation can be written Sc trace file tf sc create vcd trace file simplex Next a set of trace commands trace the signals and variables of a module as follows 5 trace tf CLOCK signal clock sc trace tf TIMEOUT timeout These commands write the value of the signal specified to the trace file previously created The last argument specifies the name of the signal in the trace file After simulation is executed you can examine the results stored in the trace file with a number of visualization tools that generate waveforms and tables of results Simulation Start After the trace commands the following function call instructs the simulation ker nel to run for 10 000 default time units and stop 34 SystemC 2 0 User s Guide Compiling the Example for UNIX sc start 10000 Alternatively you can use an sc_start value of 1 as shown below sc start 1 This command tells the simulation to run forever After the example is compl
137. on modes to get the desired adder behavior The designer can simu late the behavior before implementation to see if the adder is functionally what is needed for the end product Type fxtype params fxtype params is used to configure the parameters of types sc fix fast sc ufix fast fix and sc ufix Remember these types do not need to have their parameters determined at compile time as do types sc fixed sc ufixed Sc fixed fast and sc ufixed fast Therefore to set the parameters for these types 140 SystemC 2 0 User s Guide Type sc fxtype params declare an object of type sc fxtype params initialize the parameter values as desired and pass the sc fxtype params object as an argument to the fix fast etc declarations The fxtype params object has the same arguments passed to an object of type sc fixed fast These include wl word length iwl integer word length q mode quantization mode o mode overflow mode n bits saturated bits These arguments are exactly as described in the last few sections For instance a Sc fxtype params object could be created as follows Sc fxtype params small add params 8 4 SC RND SC SAT This creates an object called small add params that contains the following param eter values wlz8 iwl 4 q_mode SC RND o mode SC SAT e n bits 0 default Any combination of arguments are allowed but the
138. ool gt load Sc in int din input port in bool clock input port out int dout output port int count val internal data storage void count up SC CTOR count SC METHOD count up Method process sensitive pos clock count cc include count h void count count up if load count_val else count_val din count_val 1 could also write count_val dout count_val The example above implements an integer counter On a rising edge of port clock the process count_up executes If the load input is true port din is loaded into the counter Otherwise the counter increments its value by 1 The count_val variable is used to store the intermediate value of the counter It is local storage not visible outside the counter module SystemC 2 0 User s Guide 45 Modules and Hierarchy Processes So far the interface and storage of modules have been discussed but not the part of the module that provides the functionality The real work of the modules are per formed in processes Processes are functions that are identified to the SystemC ker nel and called whenever signals these processes are sensitive to change value A process contains a number of statements that implement the functionality of the process These statements are executed sequentially until the end of the process occurs or the process is suspended by one of th
139. or sc bit Values are assigned to logic objects using the character literals shown below e 0 false value e Lor true value SystemC 2 0 User s Guide 85 Data Types e X unknown or indeterminate value e Z hi impedance or floating value An example assignment is shown below sc logico x object declaration SS Lee assign 1 value x UE s assign a Z value The comparison operators and are implemented so that a designer can com pare two sc logic objects sc logic object and sc bit object or an logic object and one of the character literal values The following comparisons are imple mented sc bit x sc logic y z X y sc bit and logic y 2 sc logic and sc logic Sa sc logic and character literal The assignment operator allows assigning a character literal value or another sc logic object to an sc logic object Additionally an bit can be converted to an sc logic through the assignment The following assignments are conversions Sc bit x sc logic y x y sc logic to sc bit x bit to sc logic M ll The first assignment will convert an sc_logic type to an sc_bit type Since an sc_bit object has 2 values while an sc logic type has 4 values the values Z and X can not be converted to an bit If the value of the sc logic object is Z or X when 86 SystemC 2 0 Us
140. order cannot be changed A variable of type fxtype params can be initialized by another variable of type sc fxtype params One variable of type fxtype params can also be assigned to another Individual argument values can be read and written using methods with the same name as the arguments shown above Here s an example Sc fxtype params small add params 8 4 SC RND SC SAT x small add params wl x 8 SystemC 2 0 User s Guide 141 Fixed Point Types small add params iwl 4 sets iwl to 4 The first statement will create a sc fxtype params object with wl 8 iwl 4 q mode SC RND and o mode SC SAT The second statement will read the value of wl and the third statement will set the value of iwl Type sc fxtype context fxtype context is used to configure the default behavior of fixed point types This type will set the default values for parameters to declaration of types Sc fix fast sc ufix fast sc fix and sc ufix This type allows the designer to cre ate a set of default parameter values and define when these values are used When a new sc fxtype context object is created the values specified as arguments become the new default values The old default values are stored When the new context goes out of scope the old default values are restored An example using both the sc fxtype params and sc fxtype context is shown below xpadder2 h include system
141. original value is a signed 4 bit type and the result is a signed 3 bit type Here is a positive number example sc lt 4 4 gt x Sc fixed 3 3 SC TRN SC WRAP y x 4 x overflow handling occurs here 0100 4 100 4 Value 4 is outside the representable range for 3 bits The MSB is deleted resulting in the value 4 Here is a negative value example sc_fixed lt 4 4 gt x Sc fixed 3 3 SC TRN SC WRAP y X 5 y x overflow handling occurs here 1011 5 011 3 Again 5 is outside the representable range for a 3 bit number so the MSB is deleted resulting in the positive value 3 Here is an unsigned type example sc ufixed 5 5 x sc ufixed 3 3 SC TRN SC WRAP y x 27 y x overflow processing occurs here 11011 27 011 3 SystemC 2 0 User s Guide 129 Fixed Point Types The two MSBs are deleted to fit the result into a 3 bit value SC WRAP bits gt 0 When n bits is greater than 0 the designer is specifying that n bit MSB bits are to be saturated or set to 1 The sign bit is retained so that positive numbers remain pos itive and negative numbers remain negative The bits that are not saturated are sim ply copied from the original value to the result value A graph showing this behavior for 3 bits with n bits 1 is shown below The diagonal line represents the ideal value if infinite bits are available for repre sentation The dots repr
142. ort timeout is set to false The false value signifies that the timer is running and has not timed out yet The timer process then resets the start signal to 0 If variable count is greater than 0 the timer is still counting down Variable count is decremented and port timeout stays false If variable count is equal to 0 the timer has expired and timeout is set to true At this point the transmit module knows that the packet was lost and retransmits the packet Putting it all together The main routine The sc_main routine is the top level routine that ties all the modules together and provides the clock generation and tracing capabilities The sc_main routine is shown below main cc include packet h include timer h include transmit h include channel h include receiver h include display h int sc main int argc char argv Sc signal packet type PACKET1 PACKET2 PACKET3 PACKET4 sc_signal lt long gt DOUT sc_signal lt bool gt TIMEOUT START sc_clock CLOCK clock 20 transmit clock SystemC 2 0 User s Guide 31 Starting with a Simple Example Sc clock RCLK rclk 15 ransmit tl1 transmit l tpackin PACKET2 1 timeout TIMEOUT 1 tpackout PACKET1 t t t t tl start timer START tl clock CLOCK channel 1 tpackin PACKE rpackin PACKE tpackout PACK K rpackout PAC receive
143. ort use the following syntax Sc in rv n x input resolved logic vector n bits wide Sc out lt gt y output resolved logic vector n bits wide Sc inout rv n z inout resolved logic vector n bits wide The only limitation on the size of n is underlying system limitations Resolved Logic Vector ports should only be used where absolutely necessary as extra simula tion overhead is added versus standard ports Typically a standard port with a scalar or vector type should be used for better simulation efficiency Resolved Vector Signals Signals are used to interconnect ports Vector signals can be used to connect vector ports The vector signal types are the same as the vector port types The currently supported vector signal type is sc signal rv This is a resolved vector of sc logic signals An example is shown below Sc signal rv n sig3 resolved logic vector signal n bits wide Signals of this type can be used to connect to resolved logic vector ports NOTE Do not initialize or write to a resolved vector signal outside of a process This will cause undesired behavior SystemC 2 0 User s Guide 77 Ports and Signals Signal Binding As mentioned previously each port is bound to a single signal When reading a port the variable assigned the port value must have the same type as the port type For example a port of type logic cannot be read into an int variable or signal Whe
144. ow the counter to keep counting up until the end of the while loop is reached At this point execution will start at the beginning of the while loop and the counter will be loaded with 0 Since the count module is a simple design the stimulus for it is trivial More com plex designs will have more complex stimulus This style of test bench will support more complex stimulus As mentioned earlier stimulus can also be read from a file This has the added benefit of changing the stimulus without recompiling the design A separate module could be used to check that the counter values were correct or each of the wait statements could have a result checking statement like the follow ing wait count up value 2 if dout 2 printf counter failed at value 2 SystemC 2 0 User s Guide 51 Modules and Hierarchy 52 SystemC 2 0 User s Guide CHAPTER 4 Processes Processes are the basic unit of execution within SystemC Processes are called to emulate the behavior of the target device or system Three types of SystemC pro cesses are available Methods e Threads e Clocked Threads Each of these processes has unique behavior and are discussed in the next few sec tions In atypical programming language methods are executed sequentially as control is transferred from one method to another to perform the desired function Typical programming languages can be used to model sequential behavior of sy
145. r Types There are cases in HDL based design where operands need to be larger than 64 bits For these types of designs sc int and sc will not work For these cases use type Sc biguint arbitrary size unsigned integer or sc bigint arbitrary sized signed inte ger These types allow the designer to work on integers of any size limited only by underlying system limitations Arithmetic and other operators also use arbitrary precision when performing operations Of course this extra functionality comes at a price These types execute more slowly than their fixed precision counterparts and therefore should only be used when necessary While bigint and biguint will work with any operand sizes they should only be used on operands larger than 64 bits or for operations where more than 64 bits of precision are required Type sc bigint is 2 s complement signed integer of any size Type sc biguint is an unsigned integer of any size When using arbitrary precision integers the precision used for the calculations depends on the sizes of the operands used Look at the example below Sc biguint 128 bl Sc biguint 64 b2 Sc biguint 150 b3 1 2 In this example b1 a 128 bit integer is multiplied by b2 a 64 bit integer The result will be a 192 bit integer However since b3 is only 150 bits wide 42 bits will be removed from the result before assignment to b3 For performance reasons a variable named NBI
146. rand Sign extension and zero fill are used in cases where the operand is not reduced but extended Type casting can be configured to be on or off The default value of the cast switch is obtained from the current sc fxtype context object in use Casting can be turned on or off through an argument during declaration or by modifying or creating a new context Here s an example sc ufixed 16 16 d SC OFF This declaration specifies d as an unsigned 16 bit fixed point type in which casting is turned off Values for the cast switch are SC OFF and SC ON The default value is SC ON Turning casting off will turn off fixed point handling of the operand The operand will be treated as a large float value The bit accurate behavior of the operand will not be available when casting is turned off Useful State Information There are some useful methods to query the state of a fixed point object These methods return a boolean value depending on the value of a fixed point object The following methods are supported SystemC 2 0 User s Guide 147 Fixed Point Types e is neg returns true if object has a negative value otherwise returns false e is zero returns true if object is zero value otherwise returns false overflow returns true if last write to this object caused overflow to occur Returns false if no overflow e quantization flag returns true if last write to this object caused quantization to
147. rma tion from the module Example constructors have already been looked at briefly but let s take a more detailed look at slightly more complex constructors Below is an example RAM ram h include systemc h SC MODULE ram Sc in int addr SC in int datain sc lt 1 gt rwb Sc out int dout int memdata 64 local memory storage ant ud void ramread void ramwrite SC_CTOR ram SC METHOD ramread sensitive addr rwb SC METHOD ramwrite Sensitive addr datain rwb for i20 i 64 memdata i 0 rest of module not shown This example implements a RAM memory device The RAM can be written to and read from the two processes read and write The constructor contains declara 48 SystemC 2 0 User s Guide TestBenches tions for each of the processes Both are described as SC METHOD type pro cesses The for loop is used to initialize the memory to 0 values When a RAM module is instantiated the constructor will be called data allocated for the module and the two processes registered with the SystemC kernel Finally the for loop will be executed which will initialize all the memory locations of the newly created ram module TestBenches Testbenches are used to provide stimulus to a design under test and check design results The testbench can be implemented in a number of ways The stimulus can
148. s 0 5 This means that the clock will be true for 10 time units and false for 10 time units If the duty cycle were specified as 0 25 then the clock would be true for 5 time units and false for 15 time units The next parameter of the clock object is the start time of the first edge This is a time offset from 0 of the first edge expressed in time units In this example the specified value is 2 time units The last argument is the starting value of the clock object The clock object will toggle the clock signal at appropriate times but this value is used to specify the first value of the clock Based on the parameters speci fied the clock object will produce a clock signal as shown in Figure 2 below SystemC 2 0 User s Guide 61 Ports and Signals FIGURE 3 Offset Clock Waveform clock END 02 12 22 32 42 52 When binding the clock to a port the designer must use the clock signal generated by the clock object to map to a port This done by using the signal method of the clock object Notice that the clk port of filter is mapped to ck1 signal This is the clock signal generated by the clock object For SC CTHREAD processes the clock object is directly mapped to the clock input of the process and the signal method is not required 82 SystemC 2 0 User s Guide CHAPTER 6 Data Types SystemC provides the designer the ability to use any and all C data types as well
149. s and the corresponding fast types the cast switch must be setup properly in the context as it cannot be passed as an argument Larger Example This example is a 17 coefficient FIR filter This function takes one argument named Input of type sc fixed 4 2 5C RND SC WRAP and returns a value of type sc fixed 32 3 SC RND SC WRAP The input value and the last 16 input values are successively multiplied by the 17 input coefficents The input value is then stored in the state array to be used as one of the 16 values in the next calculation As a new value is received the values in the state array are shifted to make room for the new value include systemc h Sc fixed 32 3 SC RND SC WRAP fir fx sc fixed 4 2 SC RND SC WRAP Input const int NumberOfCoefficients 17 static sc_fixed lt 4 2 SC_RND SC_WRAP gt state NumberOfCoefficients 1 static sc_fixed lt 32 0 SC_RND SC_WRAP gt coeff NumberOfCoefficients 1 05162989348173e 02 3 84160084649920 03 1 86606831848621 02 3 90706136822701 02 2 2 1 2 64619290828705 0 3 91649864614010 0 1 44576489925385 0 2 5e 01 2 84146755933762e 0 2 1 43584483861923e 0 44576489925385e 0 3 91649864614010e 0 2 64619290828705e 0 3 90706136822701e 0 1 86606831848621e 0 3 84160084649920e 0 1 05162989348173 02 WNNNNFRF EF 150 SystemC 2 0 User s Guide Arrays of Fixed Point Types
150. sc_trace_file tf const packet_type v const sc string amp NAME Notice that the second argument is of type packet type which makes this method unique File packet cc contains the implementation of the trace method as shown below void sc trace sc trace file tf const packet type amp v const sc string amp NAME sc trace tf v info NAME info sc trace tf v seq seq sc trace tf v retry NAME retry 98 SystemC 2 0 User s Guide User Defined Type Issues The implementation of the trace method has a trace for each field of the struct This method is called by the designer to perform a trace on a signal of type packet type and is automatically created by the compiler Each call to the trace method will per form a trace on all of the fields of the user defined type SystemC 2 0 User s Guide 99 Data Types 100 SystemC 2 0 User s Guide CHAPTER 7 Fixed Point Types When designers model at a high level floating point numbers are useful to model arithmetic operations Floating point numbers can handle a very large range of val ues and are easily scaled In hardware floating point data types are typically con verted or built as fixed point data types to minimize the amount of hardware needed to implement the functionality To model the behavior of fixed point hardware designers need bit accurate fixed point data types Fixed point types are also use
151. sed for fixed point representation Equivalent to the total number of bits used in the type iwl Integer word length specifies the number of bits that are to the left of the binary point in a fixed point number q mode quantization mode this parameter determines the behavior of the fixed point type when the result of an operation generates more precision in the least sig nificant bits than is available as specified by the word length and integer word length parameters o mode overflow mode this parameter determines the behavior of the fixed point most significant bits when an operation generates more precision in the most signif icant bits than is available n bits number of saturated bits this parameter is only used for overflow mode and specifies how many bits will be saturated if a saturation behavior is specified and an overflow occurs X y object name name of the fixed point object being declared 102 SystemC 2 0 User s Guide Word Length and Integer Word Length The designer can configure the fixed point data type to perform a number of differ ent types of operations The designer will pass different values of the parameters shown above These parameter values will be used during the construction of the fixed point type to create the desired data type These types can be the basis for adders subtractors multipliers accumulators FFTs etc All of these devices can be built with bit accurate res
152. sfer medium This description is not a complete implementation of the entire algorithm but only a fragment to show the typical style of a C C model Some of the model complexity is hidden in the wait event function calls These calls are needed to take advantage of a scheduling mechanism built into the operating system or you can implement a user defined scheduling system In either case this is a complex task The transmit function at the beginning of the C C model has local storage to keep frames and local data and then it calls the function get data fromApp This function gets the first piece of data to send from the transmitter to the receiver The next statement is a while loop that continuously sends data packets to the receiver In a real system this while loop would have a termination condition based on how many packets were sent However in this example the designer wants to determine the data rate with varying noise on the channel rather than sending real packets from one place to another The statements in the while loop fill in the data fields of the packet the sequence number of the packet and send the packet to the channel The sequence number is used to uniquely identify the data packet so the correct acknowledge packets can be sent After the transmitter sends the packet to the channel a timer is started The timer allows the receiver to receive the frame and send back an acknowledge before the System
153. shift shifty 168 SystemC 2 0 User s Guide Counter if load shiftval din else if LR shiftval range 6 0 shiftval range 7 1 shiftval 7 0 else if LR shiftval range 7 1 shiftval range 6 0 shiftval 0 0 dout shiftval Counter The next example is an 8 bit counter This counter can be set to a value by setting the value of input load to 1 and placing the value to load on input din The counter can be cleared by setting input clear to a 1 Below is the VHDL implementation library ieee use ieee std use ieee std entity counter is port clock in std load in std clear in std din std dout end counter logic 1164 11 logic unsigned all logic logic _ logic logic vector 7 downto 0 inout std logic vector 7 downto 0 architecture rtl of counter is Signal countval begin process load clear begin if clear 1 then std logic vector 7 downto 0 din dout countval lt 00000000 elsif load 1 then SystemC 2 0 User s Guide 169 countval lt din else countval lt dout 00000001 end if end process process begin wait until clock event and clock 71 dout lt countval end process end rtl SystemC Implementation Here is the SystemC implementation of the counter Input ports clock load and clear are of type boo
154. simple data generator that will generate data output values that increase in value whenever a new clock edge is detected If the designer wants the value of data to start again from 0 the watching expression needs to reset the design In the constructor of the example is the following statement watching reset delayed true This statement specifies that signal reset will be watched for this process If signal reset changes to true then the watching expression will be true and the SystemC scheduler will halt execution of the while loop for this process and start the execu tion at the first line of the process SystemC 2 0 User s Guide 65 Processes The delayed function is required for the signal in a watching expression in order for the description to compile properly The delayed function allows the compiler to identify signals that are used in watching expressions A lazy evaluation algo rithm is used for these signals which dramatically increases simulation perfor mance This behavior allows the designer to reset a design or jump out of a loop without having to check the reset condition at each wait statement To enable this behavior for a particular process the watching statement must be added to the constructor and the implementation of the method must look like below void data gen gen data variable declarations watching code if reset true data 0 infinite loop while
155. stems very easily However electronic systems are inherently parallel with lots of parallel activity constantly taking place Modeling these parallel activities with a sequential language can be difficult Typical solutions to these problems brought about the creation of special Hardware Description Languages such Verilog and VHDL for SystemC 2 0 User s Guide 53 Processes modeling the hardware part of the system and linking in C or C descriptions for the software part of the design SystemC has the concept of Methods Threads and Clocked Threads to model the parallel activities of a system Basics Some processes behave just like functions the process is started when called and returns execution back to the calling mechanism when complete Other processes are called only once at the beginning of simulation and are either actively executing or suspended waiting for a condition to be true The condition can be a clock edge or a signal expression or combination of both Processes are not hierarchical so no process will call another process directly Pro cesses can call methods and functions that are not processes Processes have sensitivity lists i e a list of signals that cause the process to be invoked whenever the value of a signal in this list changes Processes cause other processes to execute by assigning new values to signals in the sensitivity list of the other process To trigger a process a signal in the sensi
156. t different times then use local watching discussed in the next section Local Watching Local watching allows you to specify exactly which section of the process is watch ing which signals and where the event handlers are located This functionality is specified with 4 macros that define the boundaries of each of the areas A blank example is shown below W BEGIN put the watching declarations here watching watching W DO This is where the process functionality goes W ESCAPE This is where the handlers for the watched events go if W_END SystemC 2 0 User s Guide 67 Processes The W BEGIN macro marks the beginning of the local watching block Between the W BEGIN and W DO macros are where all of the watching declarations are placed These declarations look the same as the global watching events Between the W DO macro and the W ESCAPE macro is where the process functionality is placed This is the code that gets executed as long as none of the watching events occur Between the W ESCAPE and the W END macros is where the event han dlers reside The event handlers will check to make sure that the relevant event has occurred and then perform the necessary action for that event The W END macro ends the local watching block There are a few interesting things to note about local watching All of the events in the declaration block have the same priority
157. t to the channel The timer is started to keep track of how long ago the packet was sent to the channel If the acknowledge packet does not return before the timer times out then the packet or acknowledge were lost and the packet needs to be transmitted again Channel Module The channel module accepts packets from the transmitter and passes them to the receiver The channel also accepts acknowledge packets from the receiver to send back to the transmit module The channel adds some noise to the transmission of packets to model the behavior of the transmission medium This causes the packets to fail to be properly received at the receiver module and acknowledge packets fail to get back to the transmit module The amount of noise added is dependent on the type of transfer medium being modeled The SystemC channel description is shown below channel h include packet h SC_MODULE channel Sc in packet type tpackin input port in packet type rpackin input port Sc out packet type tpackout output port Sc out packet type rpackout output port packet type packin SystemC 2 0 User s Guide Channel Module packet type packout packet type ackin packet type ackout void receive data void send ack Constructor SC CTOR channel Hi SC METHOD receive data Method Process sensitive tpackin SC METHOD send ack Method Process s
158. t variable The trace function registers creates a list of the signals and variables to be traced The actual tracing happens during simulation and is handled by the SystemC sched uler Note that calls to the sc trace functions are made only after the processes and signals are instantiated and after the trace file is opened Tracing Variables and Signals of Aggregate Type The trace functions defined in SystemC can accept signals or variables of scalar types only To trace variables of aggregate type you need to define special trace functions for variables of these types using the basic trace functions that are provide in SystemC For example consider the structure struct bus unsigned address bool read_write unsigned data You need to define a trace function for this structure as follows void sc trace sc trace file tf const bus amp v const Sc string amp NAME Sc trace tf v address NAME address sc trace tf v read write NAME rw Sc trace tf v data NAME data SystemC 2 0 User s Guide 159 Simulation and Debugging Using SystemC When called this trace function traces the data structure by tracing individual fields of the structure Note that each individual field of the structure is given a unique name by appending the field name to the structure name Tracing Variable and Signal Arrays To trace a variable or signal array you need to define a specialized
159. ta values from port data8 into temporary data structure tdata Once all of the data values have been read tdata is transferred to output data and the datardy signal is set to true signaling the microcontroller that the data is ready to be read An SC CTHREAD process can only be triggered by one clock edge In the exam ple above a clock is passed to the bus module through port clock Port clock is an sc in clk port The pos or neg method of this port is passed to the SC CTHREAD constructor to specify the clock edge that triggers the process Wait Until In an SC CTHREAD process wait until methods can be used to control the exe cution of the process The wait until method will halt the execution of the process until a specific event has occurred This specific event is specified by the expres sion to the wait until method An example wait until method is shown below SystemC 2 0 User s Guide 63 Processes wait until roadsensor delayed true This statement will halt execution of the process until the new value of roadsensor is true The delayed method is required to get the correct value of the object A compilation error will result if the delayed method is not present Only a boolean expression is allowed as argument of the wait until function and only boolean signal objects can be used in the boolean expressions Boolean signal objects include clock type sc clock signal type sc signal bool
160. the Dff with asynchronous reset These flip flops help the designer get a design to start at a known state easily By providing an active reset signal at design power up the designer can reset the flip flops of the design to a known state Here is the VHDL for a D flip flop with an asynchronous reset input library ieee use ieee std logic 1164 11 entity dffa is port clock in std logic reset in std logic din in std logic dout out std logic end dffa architecture rtl of dffa is begin process reset clock begin if reset 1 then dout lt 70 elsif clock event and clock 1 then dout lt din end if end process end rtl The SystemC model looks similar to the normal D flip flop discussed in the last section but now has the reset signal in the process sensitivity list Positive edges on the clock input or changes in value of the reset signal will cause process do ffa to activate The process first checks the value of reset If reset is equal to 1 the flip flop output is set to 0 If reset is not active the process will look for a positive edge on input clock This is accomplished by using the event method on the clock input port This method works just like the event method in VHDL It will be true if an event has just occurred on input clock SystemC 2 0 User s Guide 165 Here is the corresponding SystemC implementation dffa h include systemc h SC MODULE dffa
161. tivity list of the process must have an event occur The event on the signal is the triggering mechanism to activate the process An event on a signal is a change in the value of the signal If a signal has a current value of 1 and a new assignment updates the value to 0 an event will occur on the signal Any processes sensitive to that signal will recognize that there was an event on that signal and invoke the process Method Process When events value changes occur on signals that a process is sensitive to the pro cess executes method executes and returns control back to the simulation kernel A simple method is shown below rcv h include systemc h include frame h 54 SystemC 2 0 User s Guide Method Process SC MODULE rcv sc in frame type xin Sc out int id void extract id SC CTOR rcv SC METHOD extract id sensitive xin rcv cc include rcv h include frame h void rcv extract id frame type frame frame xin if frame type 1 id frame ida else id frame idb This example shows a module called rcv that has an input named xin and an output named id The module contains a single method named extract_id The method is sensitive to any changes on input xin When input xin changes method extract_id is invoked Method extract_id will execute and assign a value to port id When the method terminates control is returned b
162. to change and easier to main tain For example a designer can decide to completely change the internal data rep resentation and implementation of a particular module However if the external interface and internal function remain the same the users of the module do not know that the internals were changed This allows designers to optimize the design locally Modules are declared with the SystemC keyword SC MODULE as shown by the example below SC MODULE transmit The identifier after the SC MODULE keyword is the name of the module which is transmit in this example This syntax uses a macro named SC MODULE to declare a new module named transmit Another way to declare a module is the following SystemC 2 0 User s Guide 39 Modules and Hierarchy struct transmit sc module This form of declaration resembles a typical C declaration of a struct or a class The macro SC MODULE provides an easy and very readable way to describe the module A module can contain a number of other elements such as ports local signals local data other modules processes and constructors These elements implement the required functionality of the module Module Ports Module Ports pass data to and from the processes of a module You declare a port mode as in out or inout You also declare the data type of the port as any C data type SystemC data type or user defined type Load gt Read gt Fifi Empty Data
163. ts connecting with positional connection can be confusing For these cases it is better to use named connection Named Connection The same design with named mapping is shown below include systemc h include mult h include coeff h SystemC 2 0 User s Guide 43 Modules and Hierarchy include sample h SC MODULE filter sample 51 coeff cl mult 1 sc_signal lt sc_uint lt 32 gt gt q s SC CTOR filter 1 new sample 51 1 gt din q 1 gt dout s new coeff 1 1 gt out c Q new mult m1 gt 5 1 gt 1 gt 9 q This example uses named connection for the component instantiations The first named connection connects port din of module s1 sample to signal q of module fil ter The second named connection connects port dout of module s1 to signal s of module filter Using named connection the designer can create the signal to port connections in any order Internal Data Storage For storage of data within a module the designer can declare local variables Inter nal data storage can be of any legal C type SystemC type or user defined type Local storage is not visible outside the module unless the designer specifically makes the data visible count h 44 SystemC 2 0 User s Guide Internal Data Storage include systemc h SC_MODULE count sc_in lt b
164. uide 1 Introduction these necessary classes and allows designers to continue to use the familiar C language and development tools If you are familiar with the C programming language you can learn to program with SystemC by understanding the additional semantics introduced by the Sys temC classes no additional syntax has to be learned If you are one of the many that are more familiar with the C programming language you need to learn some C syntax in addition to the semantics introduced by the classes The use of C has been kept to a minimum in SystemC If you are familiar with the Verilog and VHDL hardware description languages and the C programming language learning SystemC will be easy This document describes how to use the SystemC Class Library version 2 0 to cre ate an executable specification for your system level designs Using Executable Specifications There are many benefits to creating an accurate executable specification of your complex system at the beginning of your design flow These benefits are e An executable specification avoids inconsistency and errors and helps ensure completeness of the specification This is because in creating an executable specification you are essentially creating a program that behaves the same way as the system The process of creating the program unearths inconsistencies and errors and the process of testing the program helps ensure completeness of the specification
165. ults A simple fixed point declaration is shown below Sc fixed 8 4 SC RND SC SAT val Word Length and Integer Word Length Two of the arguments specified to the fixed point data type were word length wl and integer word length iwl Word length must be greater than 0 Integer word length can be positive or negative and larger than the word length For instance if the word length is specified as 5 bits but the integer word length is 7 then two zeroes will be added to the end of the object This is shown below 00 Ax word length 5 integer word length 7 If the integer word length is a negative value then sign bits after the binary point will be extended For instance if wl 5 and iwl 2 then two sign bits will be added to the object as shown below SystemC 2 0 User s Guide 103 Fixed Point Types SSXXXXX word length 5 integer word length 2 More typical cases will not add bits For instance if wl 5 and iwl 3 then the fol lowing will result XXX XX word length 5 integer word length 3 More examples of wordlength integer wordlength combinations are shown in the table below Internal Range Range Index wi iwl representation signed unsigned 1 5 7 00 64 60 0 124 2 5 5 XXXxx 16 15 0 31 3 5 3 XXX XX 4 3 75 0 7 75 4 5 1 1 0 9375 0 1 9375 5 5 0 XXXXX 0 5 0 46875 0 0 96875 6 5
166. umber Temp frames to save information Event to cause actions in receiver Start framenum at 1 wait for event amp event Wait for data from channel if get data fromChannel r if send data toApp amp r info inc framenum s ack Send back r seg framenum event new frame Event arrived see if it is a frame event If so get the data from channel Is this the frame we expect Yes then send data to application Get ready for the next frame framenum 1 an acknowledge that frame was received properly send data toChannel amp s void send data toChannel frame amp f data f void get data fromChannel frame amp f Int dx Copy frame to storage Send acknowledge Stores data for channel area Gets data from channel 12 SystemC 2 0 User s Guide C C Model i rand Generate a random number to cause receive errors if i gt 10 i lt 500 the random number is between 10 and 500 mess up the sequence number in the packet data seq 0 This will cause the packet reception to fail protocol should resend packet f data Copy data out of channel The C C model contains a transmit function a receiver function and two data transfer medium or channel functions These channel functions get data from and put data to the channel data tran
167. urs here 10 11 1 25 value of x after assignment 11 0 7 1 quantized value of y Value 1 25 is outside the representation range of the result type so quantization will occur Since this value is a negative number the MSB of the deleted bits will be added to the remaining bits Value 1 25 will be rounded to 1 The last example shows an unsigned value ufixed 14 9 x sc ufixed 13 9 SC RND ZERO y 38 298125 quantization occurs here x 000100110 01001 38 28125 x value after assign 000100110 0100 38 25 quantized y value The last example is a positive number by default so the redundant bits are deleted SystemC 2 0 User s Guide 109 Fixed Point Types SC RND MIN INF This quantization mode will also perform a check to see if the nearest 2 represent able numbers are equal distance apart If not the SC RND quantization is per formed Otherwise this mode will round towards minus infinity by eliminating the redundant bits of the LSB of the number A graph showing this effect is shown below The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SC RND MIN INF Examples The next two examples show the result of the SC MIN INF quantization mode with a positive and a negative number sig
168. ve values with unsigned numbers 120 SystemC 2 0 User s Guide Overflow Modes Overflow Modes In this section we will examine what happens when the result of an operation gener ates more bits on the MSB side of a number than are available for representation Overflow occurs when the result of an operation is too large or too small for the available bit range Overflow modes within the fixed point types of SystemC give the designer high level control over the result of an overflow condition Overflow modes are specified by the o mode and n bits parameters to a fixed point type The supported overflow modes are listed in the table shown below Overflow Mode Name Saturation SC SAT Saturation to zero SC SAT ZERO Symmetrical saturation SC SAT SYM Wrap around SC WRAP Sign magnitude wrap around SC WRAP SM MIN and MAX Throughout the discussion of overflow modes we will be using the terms MIN and MAX MIN is the smallest negative number that can be represented and MAX is the largest positive number that can be represented with the available bit width The next few sections will discuss each of the overflow modes and their effect on the result of a cast operation SystemC 2 0 User s Guide 121 Fixed Point Types SC SAT This overflow mode will convert the specified value to MAX for an overflow or MIN for an underflow condition The maximum and minimum values will be deter mined from the number
169. vector to be used for large bit vector manipulation If the designer does not need tristate capability and no arithmetic operations are to be performed directly on the data then sc bv 15 the ideal type for the object The sc bv type will simulate faster than the sc Iv type yet still allow data manipulations on very large vectors Type biguint could also be used for these operations but type sc biguint is optimized for arithmetic operations not bit manipulation operations and type bv will simulate faster The bv type introduces some new operators that perform bit reduction These operators take the entire set of bits of the operand and generate a single bit result For instance to find out if databus is all O s the following operation could be per formed Sc bv 64 databus 5 logic result result databus or reduce If databus contains 1 or more 1 values the result of the reduction will be 1 If no 1 values are present the result of the reduction will be 0 indicating that databus is all 0 Bit selection part selection and concatenation all work with sc bv objects Remem ber these operators work on both sides of an assignment operator and in expres sions The following expressions are legal Sc bv 16 datal6 Sc bv 32 data32 data32 range 15 0 datalo datal6 data32 range 7 0 data32 range 23 16 datal6 range 3 0 datal6 range 15 12 data32 range 7 0 SystemC 2 0 User s Guide 93
170. x after assignment 10 1 15 value of y after quantization Value 1 25 is outside the representable range for the result type so quantization will occur Since this is a negative number the redundant bits will be deleted return ing the value 1 5 The last example shows the SC RND INF quantization mode with an unsigned number ufixed 14 9 x Sc ufixed 13 9 SC RND ZERO y 38 28125 x quantization occurs here X 000100110 01001 38 28125 x after assignment 000100110 0101 38 3125 y after quantization For unsigned values the MSB of the deleted bits is added to the remaining bits SystemC 2 0 User s Guide 113 Fixed Point Types SC RND CONV This quantization mode will check to see if the two closest representable numbers are equal distance apart If not the SC RND quantization mode is applied Other wise this mode checks the LSB of the remaining bits If the LSB is 1 this mode will round towards plus infinity If the LSB is 0 this mode will round towards minus infinity This behavior is shown by the graph below 4 x 2 3q 7 aq e 7 qT7 4 24 34 3 4 EA 7 The diagonal line represents the ideal number representation given infinite bits The small horizontal lines show the effect of the rounding Any value within the range of the line will be converted to the value of the y axis SC RND CONV Examples Four examples will
171. y 4 011 3 011 2 010 1 001 0 000 1 111 2 110 3 101 4 100 5 100 6 101 7 110 This table shows what happens when the original values in the left cell of the table are converted to result values in the table cells on the right Notice that the original values are listed in decimal to show greater range SC_WRAP_SM n_bits gt 0 The second overflow behavior within the SC_WRAP_SM overflow mode is the case when n_bits is greater than 0 A sign magnitude wrap will still be performed but now n_bits MSB bits will be saturated In fact the first n_bits MSB bits on the MSB side of the result number will are saturated to MAX for positive numbers and to MIN for negative numbers This means that all of the bits except for the sign bit will be saturated to a 1 for positive numbers and all of the bits will be saturated to 1 for negative numbers Positive number remain positive and negative numbers remain negative When n bits is equal to 1 one bit to the right of the sign bit is saturated and the remaining bits are copied These remaining bits are xor ed with the original and new value of the sign bit of the result number If n bits is greater than 1 the unsat 134 SystemC 2 0 User s Guide SC WRAP SM n bits 1 urated bits are xor ed with the original value of the least significant saturated bit and the inverse value of the original sign bit SC WRAP SM n bits 3 Examples For this example the original number is a 9
172. ystemC 2 0 document SystemC is a C class library and a methodology that you can use to effectively create a cycle accurate model of software algorithms hardware architecture and interfaces of your SoC System On a Chip and system level designs You can use SystemC and standard C development tools to create a system level model quickly simulate to validate and optimize the design explore various algorithms and provide the hardware and software development team with an executable spec ification of the system An executable specification is essentially a C program that exhibits the same behavior as the system when executed C or C are the language choice for software algorithm and interface specifica tions because they provide the control and data abstractions necessary to develop compact and efficient system descriptions Most designers are familiar with these languages and the large number of development tools associated with them The SystemC Class Library provides the necessary constructs to model system architecture including hardware timing concurrency and reactive behavior that are missing in standard C Adding these constructs to C would require proprietary extensions to the language which is not an acceptable solution for the industry The C object oriented programming language provides the ability to extend the lan guage through classes without adding new syntactic constructs SystemC provides SystemC 2 0 User s G

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