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M Series User Manual - Physics at Oregon State University

1. AI8 34 68 AIO Al 24 34 68 Al 16 Al1 33 67 Al GND Al 17 33 67 Al GND Al GND 32 66 Al9 AI GND 32 66 Al 25 AI 10 31 65 Al2 Al 26 31 65 Al 18 AI3 30 64 Al GND AI 19 30 64 AI GND AI GND 29 63 Al 11 AI GND 29 63 Al 27 Al4 28 62 Al SENSE Al 20 28 62 Al SENSE 2 Al GND 27 61 Al 12 AI GND 27 61 Al 28 Al 13 26 60 AIS AI 29 26 60 AI21 Al6 25 59 AI GND AI 22 25 59 AI GND AI GND 24 58 Al 14 AI GND 24 58 AI 30 Al 15 23 57 AI7 AI 31 23 57 Al 23 AO 0 22 56 Al GND AO 2 22 56 AI GND AO 1 21 55 AO GND AO3 21 55 AO GND APFI 0 20 54 AO GND APFI 1 20 54 AO GND P0 4 19153 D GND P0 12 19 53 D GND D GND 18 52 P0 0 D GND 18 52 P0 8 PO 1 17151 PO 5 P0 9 17151 P0 13 P0 6 16 50 D GND P0 14 16 50 D GND D GND 15 49 PO2 D GND 15 49 P0 10 5 V 14 48 PO 7 5V 14 48 P0 15 D GND 13 47 P0 3 D GND 13 47 PO 11 D GND 12 46 PFI 11 P2 3 D GND 12 46 P0 27 PFI 0 P1 0 11 45 PFI 10 P2 2 P0 16 11 45 P0 26 PFI 1 P1 1 10 44 D GND P0 17 10 44 D GND D GND 9 43 PFI2 P1 2 D GND 9 43 P0 18 5 V 8 42 PF
2. O National Instruments Corporation Figure 8 1 M Series PFI Circuitry M Series User Manual Chapter 8 PFI When a terminal is used as a timing input or output signal it is called PFI x where x is an integer from 0 to 15 When a terminal is used as a static digital input or output it is called P1 x or P2 x On the I O connector each terminal is labeled PFI x P1 or PFI x P2 The voltage input and output levels and the current drive levels of the PFI signals are listed in the specifications of your device Using PFI Terminals as Timing Input Signals M Series User Manual Use PFI terminals to route external timing signals to many different M Series functions Each PFI terminal can be routed to any of the following signals e AI Convert Clock e AI Sample Clock e AI Start Trigger AI Reference Trigger AI Pause Trigger e AI Sample Clock Timebase e AO Start Trigger e AO Sample Clock e AO Sample Clock Timebase e AO Pause Trigger e Counter input signals for either counter Source Gate Aux HW_Arm A B Z e DI Sample Clock DO Sample Clock Most functions allow you to configure the polarity of PFI inputs and whether the input is edge or level sensitive 8 2 ni com Chapter 8 PFI Exporting Timing Output Signals Using PFI Terminals You can route any of the following timing signals to any PFI terminal configured as an output 3 AI Convert Clock AI Hold Complete Ev
3. Enable P0 31 Synch Lu Enable Figure 6 3 DI Change Detection 3 Note DI change detection is supported by NI DAQ 8 0 and later You can enable the DIO change detection circuitry to detect rising edges falling edges or either edge individually on each DIO line The DAQ devices synchronize each DI signal to 80MHzTimebase and then sends the signal to the change detectors The circuitry ORs the output of all enabled change detectors from every DI signal The result of this OR is the Change Detection Event signal M Series User Manual 6 8 ni com Chapter 6 Digital I O The Change Detection Event signal can do the following e Drive any RTSI lt 0 7 gt PFI lt 0 15 gt or PXI_STAR signal e Drive the DO Sample Clock or DI Sample Clock e Generate an interrupt The Change Detection Event signal also can be used to detect changes on digital output events Applications The DIO change detection circuitry can interrupt a user program when one of several DIO signals changes state You also can use the output of the DIO change detection circuitry to trigger a DI or counter acquisition on the logical OR of several digital signals To trigger on a single digital signal refer to the Triggering with a Digital Source section of Chapter 11 Triggering By routing the Change Detection Event signal to a counter you also can capture the relative time betwe
4. The timings in this table are measured at the pin of the M Series device For example ts specifies the minimum period of a signal driving a PFI RTSI or PXI_STAR pin when that signal is internally routed to Counter n Source National Instruments Corporation B 41 M Series User Manual Appendix B Timing Diagrams Gate Pulse Width Figure B 46 and Table B 31 show the timing requirements for Counter n Gate The requirements depend on the gating mode t All Counter n Gate ty e a Figure B 46 Counter n Gate Pulse Width Timing Diagram Table B 31 Counter n Gate Pulse Width Timing Timing Description Gating Mode Min ns Max ns t7 Counter n Gate Pulse Edge 12 0 Width Counter n Gate Pulse Level One Source Period Width The timings in this table are measured at the pin of the M Series device That is ty specifies the minimum pulse width of a signal driving a PFI RTSI or PXI_STAR pin when that signal is internally routed to Counter n Gate M Series User Manual Gate to Source Setup and Hold The counter can be modeled as a set of flip flops where the D input is Count Enable and the clock input is Selected Source as shown in Figure B 40 This section shows the setup and hold requirements for two different cases A PFI pin drives Counter n Source and a different PFI pin drives Counter n Gate e The general c
5. N Filter Clocks Pulse Width Pulse Width Needed to Pass Guaranteed to Pass Guaranteed to Not Filter Setting Signal Filter Pass Filter 125 ns 5 125 ns 100 ns 6 425 us 257 6 425 us 6 400 us 2 55 ms 101 800 2 55 ms 2 54 ms Disabled National Instruments Corporation M Series User Manual Chapter 7 Counters The filter setting for each input can be configured independently On power up the filters are disabled Figure 7 29 shows an example of a low to high transition on an input that has its filter set to 125 ns N 5 RTSI PFI or PXI_STAR Terminal Filter Clock 40 MHz Filtered Input Filtered input goes high when terminal is sampled 1 1 2 3 4 1 2 3 4 5 high on five consecutive filter clocks Prescaling M Series User Manual Figure 7 29 Filter Example Enabling filters introduces jitter on the input signal For the 125 ns and 6 425 us filter settings the jitter is up to 25 ns On the 2 55 ms setting the jitter is up to 10 025 us When a PFI input is routed directly to RTSL or a RTSI input is routed directly to PFI the M Series device does not use the filtered version of the input signal Refer to the KnowledgeBase document Digital Filtering with M Series for more information about digital filters and counters To access this KnowledgeBase go to ni c
6. PO_i PO gt e DI Waveform PFI RTSI gt e a Acquisition FIFO or PXI_STAR PFI_i RTSL i or PXI_STAR_i Other Internal PFI Output Signals Figure B 36 Digital Waveform Acquisition Timing Circuitry Figure B 37 and Tables B 22 and B 23 describe the digital waveform acquisition timing delays and requirements Your inputs must meet the requirements to ensure proper behavior i ty 1 gt t2 t2 PFI RTSI rd o or PXI_STAR i tg it gt eel PFI_i RTSI_i _ ff A or PXI_STAR_i d i i tai ity DI Sample Clock 1 ts loteo Po _X L i ity it lt gt O m PO_i X bi to DK PFI Output Figure B 37 Digital Waveform Acquisition Timing Delays National Instruments Corporation B 33 M Series User Manual Appendix B Timing Diagrams Table B 22 DI Timing Delays Timing Delay From To Min ns Max ns t3 PFI PFI_i 5 2 6 2 18 2 22 0 RTSI RTSLi 2 0 25 5 0 6 0 PXI_STAR PXI_STAR_i 1 5 3 5 ty PFL i DI Sample 3 5 9 RTSL i Clock PXI_STAR_i or other internal signal ty PO PO_i 47 20 1 tg DI Sample PFI output 8 0 29 8 Clock ty PFI output PFI output One period of 80 MHz Timebase Two periods of 80 MHz high low Timebase The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition
7. L Al lt 0 n gt 2 o o DIFF RSE or NRSE O O Al SENSE Al GND N7 AI Terminal Configuration Selection Input Range Selection Al Lowpass Filter ADC Al FIFO Al Data Figure 4 1 M Series Analog Input Circuitry Analog Input Circuitry 1 0 Connector You can connect analog input signals to the M Series device through the I O connector The proper way to connect analog input signals depends on the analog input ground reference settings described in the Analog Input Ground Reference Settings section Also refer to Appendix A Device Specific Information for device I O connector pinouts MUX Each M Series device has one analog to digital converter ADC The multiplexers MUX route one AI channel at a time to the ADC through the NI PGIA National Instruments Corporation 4 1 M Series User Manual Chapter 4 Analog Input Ground Reference Settings The analog input ground reference settings circuitry selects between differential referenced single ended and non referenced single ended input modes Each AT channel can use a different mode Instrumentation Amplifier NI PGIA The NI programmable gain instrumentation amplifier NI PGIA is a measurement and instrument class amplifier that minimizes settling times for all input ranges The NI PGIA can amplify or attenuate an AI signal to ensure that you use the maximum resolution of the ADC M Series de
8. Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTR OB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1 B 46 PFI 11 May Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6225 Specifications Refer to the NI 622x Specifications for more detailed information about the NI 6225 device NI 6225 Accessory and Cabling Options This section describes some cable and accessory options for the NI 6225 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your NI 6225 device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your NI 6225 device to control SCXI Connector 1 cannot be used to control SCXI You also can use an NI 6225 device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary National Instruments Corporation A 23 M Series User Manual Appendix Device Specific Information M Series User Manual Refer to the SCXT Advisor available by going to ni com info and e
9. ao SampleClock lt gt Delay From Start Trigger Figure 5 6 ao SampleClock and ao StartTrigger National Instruments Corporation 5 11 M Series User Manual Chapter 5 Analog Output AO Sample Clock Timebase Signal The AO Sample Clock Timebase ao SampleClockTimebase signal is divided down to provide a source for ao SampleClock You can route any of the following signals to be the AO Sample Clock Timebase ao SampleClockTimebase signal e 20 MHz Timebase e 100 kHz Timebase e PXI CLKI0 e PFI lt 0 15 gt RTSI lt 0 7 gt e PXI STAR e Analog Comparison Event an analog trigger ao SampleClockTimebase is not available as an output on the I O connector You might use ao SampleClockTimebase if you want to use an external sample clock signal but need to divide the signal down If you want to use an external sample clock signal but do not need to divide the signal then you should use ao SampleClock rather than ao SampleClockTimebase Getting Started with AO Applications in Software You can use an M Series device in the following analog output applications e Single point on demand generation Finite generation e Continuous generation e Waveform generation You can perform these generations through programmed I O interrupt or DMA data transfer mechanisms Some of the applications also use start triggers and pause triggers 33 Note For more information about programming an
10. NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 84 ni com Appendix Device Specific Information NI 6281 NI 6281 Pinout Figure A 21 shows the pinout of the NI 6281 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 85 M Series User Manual Appendix Device Specific Information M Series User Manual gt gt gt gt gt gt gt gt gt gt gt gt ao m Zz ao m FI 11 P2 3 FI 10 P2 2 GND 12 P1 2 3 P1 3 14 P1 4 13 P2 5 115 P2 7 Fl 7 P1 7 PFI 8 P2 0 D GND D GND 7 7 TU BB D a 0 EI TI a Pa PJ ed SA AO 0 AO 1 APFI 0 PO 4 D GND PO 1 P0 6 D GND 5 V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5 V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 CONNECTOR 0 Al 0 15 TERMINAL 68 TERMINAL 34 TERMINAL 35 TERMINAL 1 Figure A 21 NI 6281 Pinout Table A 21 Default NI DAQmx Counter Timer Pins Counter Timer Signal De
11. The three primary ways to transfer data across the PCI bus are direct memory access DMA interrupt request IRQ and programmed I O The two primary ways to transfer data across the USB bus are USB Signal Stream and programmed I O Direct Memory Access DMA DMA is a method to transfer data between the device and computer memory without the involvement of the CPU This method makes DMA the fastest available data transfer method NI uses DMA hardware and software technology to achieve high throughput rates and increase system utilization DMA is the default method of data transfer for DAQ devices that support it USB Signal Stream USB Signal Stream is a method to transfer data between the device and computer memory using USB bulk transfers without intervention of the microcontroller on the NI device NI uses USB Signal Stream hardware and software technology to achieve high throughput rates and increase system utilization in USB devices Interrupt Request IRQ Programmed 1 0 M Series User Manual IRQ transfers rely on the CPU to service data transfer requests The device notifies the CPU when it is ready to transfer data The data transfer speed is tightly coupled to the rate at which the CPU can service the interrupt requests If you are using interrupts to transfer data at a rate faster than the rate the CPU can service the interrupts your systems may start to freeze Programmed I O is a data transfer mechanism where th
12. BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required National Instruments Corporation A 5 M Series User Manual Appendix Device Specific Information Cables In most applications you can use the following cables SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost s
13. Figure B 26 START Trigger Input Delay Path Signal_i 5 Selected Start Sync Sample Clock Timebase Figure B 27 START Trigger Timing Diagram O National Instruments Corporation B 27 M Series User Manual Appendix B Timing Diagrams Table B 15 START Trigger Timing from Signal_i to Selected Start Timing From To Min ns Max ns t Signal_i Selected Start 2 9 9 8 Table B 16 START Trigger Setup and Hold Timing Timing Parameter Min ns Max ns t Setup 1 5 tg Hold 0 Pause Trigger The analog output Pause Trigger can be used to pause an ongoing generation It is received on the rising edge of Sync Sample Clock Timebase Selected Pause Signal_i gt To Internal Logic Sync Sample Clock Timebase Figure B 28 Pause Trigger Input Delay Path a i id CD a Signal_i i i i t gt Selected Pause i 10 tp i ic i mii J to Sync Sample Clock Timebase i HER Figure B 29 Pause Trigger Timing Diagram M Series User Manual B 28 ni com Output Timing National Instruments Corporation B 29 Appendix B Timing Diagrams Table B 17 Pause Trigger Timing from Signal_i to Selected Pause Timing From To Min ns Max ns to Signal_i Selected Pause 1 7 7 8 Table B 1
14. Measurement Studio ANSI C without NI Application Software NET Languages without NI Application Software Device Documentation and Specifications Training Courses nt unes Technical Support on the Web Chapter 1 Getting Started Installing NI DAQmx sociema ai Installing Other Software Installing the Hardware Device Pints st baud wit band nie nement en Device Specifications Device Accessories and Cables ooooonccnonccnocacoccconccnonoconncons Chapter 2 DAQ System Overview DAQ Hardware siens dore cavescdascevesvencarcdseste DAQ STC2 and DAQ 6202 dococonooccccoocncoonncccnnnncnno Calibration Circuitry Signal Conditioning ss Sensors and Transducers coooocccnooccnononncnoncnonanancnnns Custom Cabling eee a a Programming Devices in Software National Instruments Corporation vii M Series User Manual Contents Chapter 3 Connector Information T O Connector Signal Descriptions 3 1 M Series and E Series Pinout Comparison 3 4 5 V Power SOUTCC ss ss sn rinitis sors eiii dires es 3 6 Disk Drive Power Connector 3 6 When to Use the Disk Drive Power Connector oooooonccnnooocnncnonononnnononannnnnconno 3 6 Disk Drive Power Connector Installation ooooocnnnnooncnnnononanannncnnnnnnnnncnonos 3 7 RISI Connector Pinout sites sedcostaueassseleceesesondokeacgessanteacdsvente 3 8 Chapter 4 Analog Input Analog Input Crett
15. ts T i x f Figure B 52 Generating Different Clocks Using an External Reference Clock and the PLL Table B 37 Generating Different Clocks Using an External Reference Clock and the PLL reference clock RTSI lt 0 7 gt STAR_TRIG PXI_CLK10 Through PLL_OUT Timing From To Min ns Max ns t4 80 MHz Timebase 20 MHz Timebase 1 5 5 0 ts The source of the external 80 MHz Timebase 1 0 5 5 National Instruments Corporation B 49 M Series User Manual Troubleshooting Analog Input This section contains common questions about M Series devices If your questions are not answered here refer to the National Instruments KnowledgeBase at ni com kb I am seeing crosstalk or ghost voltages when sampling multiple channels What does this mean You may be experiencing a phenomenon called charge injection which occurs when you sample a series of high output impedance sources with a multiplexer Multiplexers contain switches usually made of switched capacitors When a channel for example AI 0 is selected in a multiplexer those capacitors accumulate charge When the next channel for example AI 1 is selected the accumulated current or charge leaks backward through channel 1 If the output impedance of the source connected to AI 1 is high enough the resulting reading can somewhat
16. Figure 7 11 Method 1 Method 1b Measure Low Frequency with One Counter Averaged In this method you measure several periods of your signal using a known timebase This method is good for low to medium frequency signals You can route the signal to measure F1 to the Gate of a counter You can route a known timebase Ft to the Source of the counter The known timebase can be 80MHzTimebase For signals that might be slower than 0 02 Hz use a slower known timebase You can configure the counter to make K 1 buffered period measurements Recall that the first period measurement in the buffer should be discarded 7 10 ni com Chapter 7 Counters Average the remaining K period measurements to determine the average period of Fl The frequency of Fl is the inverse of the average period Figure 7 12 illustrates this method Intervals Measured UT To toe TK A A A F1 4 Gate F1 Ft Source 12 Ni No 1 NKk Fe UUU UUU Buffered Period Measurement N No Nk 1 A Period of F1 x verage Period o K Fi K x Ft Frequency of F1 N No Nk Figure 7 12 Method 1b Method 2 Measure High Frequency with Two Counters In this method you measure one pulse of a known width using your signal and derive the frequency of your signal from the result This method is good for high frequency signals In this method you route a pulse of known duratio
17. Index NI 6289 accessory options A 98 cabling options A 98 pinout A 96 specifications A 98 NI support and services E 1 NI DAQ documentation xviii device documentation browser xxi NI DAQmx default counter terminals 7 30 enabling duplicate count prevention 7 38 NI DAQmx Base documentation xix NI DAQm x for Linux documentation xix NI PGIA 4 2 non buffered hardware timed acquisitions 4 12 hardware timed generations 5 5 non cumulative buffered edge counting 7 4 non referenced single ended connections using with floating signal sources 4 19 using with ground referenced signal sources 4 24 when to use with floating signal sources 4 15 when to use with ground referenced signal sources 4 21 NRSE connections using with floating signal sources 4 19 using with ground referenced signal sources 4 24 when to use with floating signal sources 4 15 when to use with ground referenced signal sources 4 21 0 on demand acquisitions 4 11 edge counting 7 2 timing 4 11 M Series User Manual 1 10 options 2 4 order of channels for scanning 4 9 other internal source mode 7 39 other software 1 1 output signal glitches C 3 output signals minimizing glitches 5 4 output terminal routing analog comparison events 11 3 outputs using RTSI as 9 5 overview 2 1 P pause trigger 7 32 analog input internal timing diagram B 19 PCI Express See also PCIe 6251 See also PCIe 6259 disk drive power co
18. Output Timebase FREQ OUT 7 Divisor 5 Figure 7 27 Frequency Generator Output Waveform National Instruments Corporation 7 23 M Series User Manual Chapter 7 Counters Frequency Output can be routed out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFI terminals are set to high impedance at startup The FREQ OUT signal also can be routed to DO Sample Clock and DI Sample Clock In software program the frequency generator as you would program one of the counters for pulse train generation For information about connecting counter signals refer to the Default Counter Timer Pinouts section Frequency Division The counters can generate a signal with a frequency that is a fraction of an input signal This function is equivalent to continuous pulse train generation For information about connecting counter signals refer to the Default Counter Timer Pinouts section Pulse Generation for ETS In this application the counter produces a pulse on the output a specified delay after an active edge on Gate After each active edge on Gate the counter cumulatively increments the delay between the Gate and the pulse on the output by a specified amount Thus the delay between the Gate and the pulse produced successively increases 3 Note ETS Equivalent Time Sampling M Series User Manual The increase in the delay
19. PCI Express eXtensions for Instrumentation The PXI implementation of PCI Express a scalable full simplex serial bus standard that operates at 2 5 Gbps and offers both asynchronous and isochronous data transfers G 14 ni com PXI_STAR Q quadrature encoder range real time RSE RTSI RTSI bus Glossary A special set of trigger lines in the PXI backplane for high accuracy device synchronization with minimal latencies on each PXI slot Only devices in the PXI Star controller Slot 2 can set signal on this line For additional information concerning PXI star signal specifications and capabilities read the PXI Specification located at www pxisa org specs An encoding technique for a rotating device where two tracks of information are placed on the device with the signals on the tracks offset by 90 from each other This makes it possible to detect the direction of the motion The maximum and minimum parameters between which a sensor instrument or device operates with a specified set of characteristics This may be a voltage range or a frequency range 1 Displays as it comes in no delays 2 A property of an event or system in which data is processed and acted upon as it is acquired instead of being accumulated and processed at a later time 3 Pertaining to the performance of a computation during the actual time that the related physical process transpires so results of the computation can be used in guiding the
20. SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Sy Note PCI Express users should consider the power limits on certain SCC modules without an external power supply Refer to the NI 625x Specifications and the Disk Drive Power Connector section of Chapter 3 Connector Information for information about power limits and increasing the current the device can supply on the 5 V terminal Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digi
21. Tinsertion Trigger Tpetay Trigger gt DFF getup THotd EXt t Tinsertion Trigger Tpelay Trigger Tinsertion CIK Thetay CIK gt DFFyo1a For setup calculations use the maximum timing parameters For hold calculations use the minimum timing parameters In order to account for the worst case skew between different input terminals use the range given in the input delay tables in the Input Timing section in a way that provides the most conservative results e For setup calculations use Tinsertion Trigger gt Tinsertion CIK For hold calculations use Tinsertion CIK gt Tinsertion Trigger O National Instruments Corporation B 45 M Series User Manual Appendix B Timing Diagrams Output Delays Refer to the Figure B 40 for the M Series counter timer circuitry Figure B 49 and Table B 34 show the output delays Selected Source Out_o PFI RTSI Counter n Internal Out PFI RTSI Counter n Source Selected Gate PFI RTSI Counter n Gate Figure B 49 Output Delays Table B 34 Output Delays Timing Timing Line Min ns Max ns to 1 0 4 0 ti PFI 7 5 28 2 RTSI 6 5 18 0 ti PFI 8 5 32 2 RTSI 7 5 22 0 t PFI 7 5 28 7 RTSI 6 5 18 0 M Series User Manual B 46 ni com Appendix B Timing Diagrams Gating Modes Gating mode refers to how the counter timer uses the Gate input Some timing operation
22. D Selected Start K p POUT T gt RTSI Terminal 5 Selected Pause Trigger i gt i Pause Trigger and Other Counters Terminal gt Sl and Such of Timer Core l Sample Clock Timebase Counter i 7 7 Sync Sample Clock Timebase Block POUT H gt 0 gt Terminal SI_TC y p_Al_Convert i ath i Convert Clock Timebase ole Counter i ae Sync Convert Clock Timebase Block Start Terminal gt e Selected Sample Clock O ih Terminal i D POUT M Series User Manual Figure B 1 M Series Analog Input Timing Engine The signals used in this diagram and in the following sections are Terminal Refers to any device terminal such as PFI or RTSI These terminals are used as inputs and as outputs for signals 1 Refers to any internal signal available to the analog input timing engine for use In the case of signals coming from an external terminal this would be the signal after is been through the first input buffer _i also can refer to other internal signals such as internal timebases or signals coming from other blocks POUT driven to an output terminal B 2 Refers to any output signal right before is ni com Convert Clock Timebase and Sync Convert Clock Timebase Sample Clock Timebase and Sync Sample Clock Timebase Selected Start and Start Selected Reference Trigger and Reference Trigger National Instruments Corporation Appendix B Convert Clock Timebase is the source signal
23. NC No Connect gt gt gt gt gt gt gt gt gt gt gt gt GND GND 19 26 GND 17 24 NC No Connect D GND D GND P0 24 P0 23 P0 31 P0 29 P0 20 P0 19 P0 18 D GND P0 26 P0 27 P0 11 P0 15 P0 10 D GND P0 13 P0 8 D GND NC NC Al GND Al 23 AI 30 Al GND Al 21 Al 28 Al SENSE 2 Al 27 Al GND Al 18 Al 25 Al GND Al 16 Figure A 22 NI 6284 Pinout Table A 22 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 O National Instruments Corporation A 91 M Series User Manual Device Specific Information Table A 22 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6284 Specifications Refer to the NI 628x Specifications for more detailed information about the NI 6284 device NI 6284 Accessory and Cabling Options This section describes some cable and accessory
24. Timing Diagrams p_Al_ Convert Figure B 8 Convert Clock and Any Internal Signal Timing Diagram Table B 4 Convert Clock and Any Internal Signal Timing Timing Description Line Min ns Max ns to _ito PFI 22 2 52 1 p_AI_Convert in external RTSI 22 1 51 8 convertmode STAR 21 5 49 1 Start Start is the signal that starts an AI acquisition This signal can come from an external source through an external terminal or from an internal source One possible internal source is a software generated pulse A multiplexer selects from all the possible sources all of them at _i level and outputs a signal called Selected Start Selected Start then gets sent to the two timing levels in the AI section the Convert Clock Timebase and the Sample Clock Timebase timing level for synchronization to each clock Once the Convert Clock Timebase timing domain has received a valid Start the AI timing engine is ready to start generating converts as soon as it receives a Sample Clock beginning of a sample Once the Sample Clock Timebase domain has received a valid Start the AI timing engine is ready to start generating Sample Clocks National Instruments Corporation B 11 M Series User Manual Appendix B Timing Diagrams Selected Reference Trigger Reference Trigger Terminal Le gt Terminal i POUT Terminal z Terminal e gt gt De RTSI Selected Pause Trigger Termina
25. 1 0 Connector Instrumentation Amplifier Measured Voltage m Input Multiplexers 0 AI SENSE par M Series Device Configured in DIFF Mode Figure 4 10 Differential Connections for Ground Referenced Signal Sources With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground shown as Vem in the figure AI and AI must both remain within 11 V of AI GND O National Instruments Corporation 4 23 M Series User Manual Chapter 4 Analog Input Using Non Referenced Single Ended NRSE Connections for Ground Referenced Signal Sources Figure 4 11 shows how to connect ground reference signal sources in NRSE mode Ground Referenced Signal Source Common Mode Noise and Ground Potential 1 0 Connector ies Al lt 0 15 gt or Al lt 16 n gt o O D So o os o Instrumentation Amplifier Input Multiplexers Measured Voltage m Al SENSE AIGND or Al SENSE 2 M Series Device Configured in NRSE Mode Figure 4 11 Single Ended Connections for Ground Referenced Signal Sources NRSE Configuration AI and AI must both remain within 11 V of AI GND To measure a single ended ground referenced signal source you must use the NRSE ground refer
26. 7 18 types of analog triggers 11 3 U upgrading from E Series to M Series D 1 USB Signal Streams 10 1 JSB bulk transfers 10 4 USB signal stream as a transfer method 10 4 changing data transfer methods 10 5 USB 6251 fuse replacement A 45 LED patterns A 44 pinout A 43 specifications A 44 USB 6251 Mass Termination accessory options A 48 cabling options A 48 fuse replacement A 50 LED patterns A 50 pinout A 46 specifications A 48 USB 6259 fuse replacement A 73 LED patterns A 72 pinout A 70 specifications A 72 USB 6259 Mass Termination accessory options A 76 cabling options A 76 fuse replacement A 79 LED patterns A 78 pinout A 74 specifications A 76 using low impedance sources 4 8 short high quality cabling 4 9 M Series User Manual Index the disk drive power connector PCI Express 3 6 using PFI terminals as static digital I Os 8 3 as timing input signals 8 2 to export timing output signals 8 3 using RTSI as outputs 9 5 terminals as timing input signals 9 6 W waveform generation digital 6 5 signals 5 7 waveform triggering 6 3 Web resources E 1 X X1 encoding 7 15 X2 encoding 7 16 X4 encoding 7 16 M Series User Manual 1 16 ni com
27. 7 gt terminal All PFIs are set to high impedance at startup National Instruments Corporation 7 27 M Series User Manual Chapter 7 Counters Counter n Aux Signal The Counter n Aux signal indicates the first edge in a two signal edge separation measurement Routing a Signal to Counter n Aux Each counter has independent input selectors for the Counter n Aux signal Any of the following signals can be routed to the Counter n Aux input e RTSI lt 0 7 gt e PFI lt 0 15 gt e ai ReferenceTrigger e ai StartTrigger e PXI STAR e Analog Comparison Event In addition Counter 1 Internal Output Counter 1 Gate Counter 1 Source or Counter 0 Gate can be routed to Counter 0 Aux Counter 0 Internal Output Counter 0 Gate Counter 0 Source or Counter 1 Gate can be routed to Counter 1 Aux Some of these options may not be available in some driver software Counter n A Counter n B and Counter n Z Signals M Series User Manual Counter n B can control the direction of counting in edge counting applications Use the A B and Z inputs to each counter when measuring quadrature encoders or measuring two pulse encoders Routing Signals to A B and Z Counter Inputs Each counter has independent input selectors for each of the A B and Z inputs Any of the following signals can be routed to each input e RTSI lt 0 7 gt e PFI lt 0 15 gt e PXI STAR e Analog Comparison Event Routing Counter n Z Signal to an Outp
28. AO lt 0 3 gt can be individually set to one of the following e 10V e 45V e APFI lt O0 1 gt You can connect an external signal to APFI lt 0 1 gt to provide the AO Reference The AO Reference can be a positive or negative voltage If AO Reference is a negative voltage the polarity of the AO output is inverted The valid ranges of APFI lt 0 1 gt are listed in the device specifications You can use one of the AO lt 0 3 gt signals to be the AO reference for a different AO signal However you must externally connect this channel to APFI 0 or APFI 1 NI 628x Only On NI 628x devices the AO Offset of each analog output can be individually set to one of the following OV AO GND 5 V APFI lt 0 1 gt AO lt 0 3 gt You can connect an external signal to APFI lt 0 1 gt to provide the AO Offset You can route the output of one of the AO lt 0 3 gt signals to be the AO Offset for a different AO lt 0 3 gt signal For example AO 0 can be routed to be the AO Offset of AO 1 This route is done on the device no external connections are required You cannot route an AO channel to be its own offset On NI 628x devices the AO Reference of each analog output can be individually set to one of the following e 10V e 45V National Instruments Corporation 5 3 M Series User Manual Chapter 5 Analog Output e APFI lt 0 1 gt e AO0 lt 0 3 gt You can connect an external signal to APFI lt
29. Al7 Al GND AO GND AO GND D GND PO 0 PO 5 D GND PO 2 PO 7 P0 3 PF PF 11 P2 3 10 P2 2 D GND PF PFI PF PFI PF PFI PF 2 P1 2 3 P1 3 4 P1 4 13 P2 5 15 P2 7 7 P1 7 8 P2 0 DGND DGND o 00 W Lo E Q Mm Q o wm D Q a w a o R w le Q wo N Q D D o 2 m N Q o mM oo a Le D a a N R a E N oO a o N D a a N a R N al wo o a D a er a o o IN a S m P E XA En w D a N A nfojajoalo ojo 3 2 Q Le CONNECTOR 0 Al 0 15 GND 15 TERMINAL 68 AO 0 AO 1 NC P0 4 D GND PO 1 P0 6 D GND 5V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 gt gt gt gt gt gt gt SS SS A 19 TERMINAL 34 TERMINAL 35 TERMINAL 1 S NC No Connect Figure A 2 NI 6221 68 Pin Pinout Table A 2 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 ni com Appendix Device Specific Infor
30. DAQ system 2 1 DAQ 6202 2 2 DAQ STC2 2 2 data acquisition methods 4 11 generation methods 5 4 transfer methods 10 4 changing 10 5 DMA 10 4 IRQ 10 4 programmed I O 10 4 USB signal stream 10 4 Declaration of Conformity NI resources E 1 default counter terminals 7 30 NI DAQnx counter timer pins 7 30 pins 7 30 detection troubleshooting C 3 device information A 1 multiple synchronization 9 3 NI 6220 A 2 NI 6250 A 33 NI 6251 A 38 NI 6254 A 52 NI 6255 A 58 National Instruments Corporation 1 5 Index NI 6259 A 64 NI 6221 A 7 NI 6224 A 15 NI 6225 A 21 NI 6229 A 27 NI 6280 A 80 NI 6281 A 85 NI 6284 A 90 NI 6289 A 96 pinouts 1 1 specifications 1 2 A 1 DI change detection 6 8 DI Sample Clock signal 6 4 di SampleClock 6 4 diagnostic tools NI resources E 1 DIFF connections using With floating signal sources 4 16 using with ground referenced signal sources 4 23 when to use with floating signal sources 4 15 when to use with ground referenced signal sources 4 21 differential analog input troubleshooting C 1 differential connections using with floating signal sources 4 16 using with ground referenced signal sources 4 23 when to use with floating signal sources 4 15 when to use with ground referenced signal sources 4 21 digital waveform acquisition 6 3 waveform generation 6 5 digital I O 6 1 block diagram 6 1 circuitry 6 1 connecting signals 6 9
31. First signal must go above high threshold High threshold Level Hysteresis Hysteresis CAPE is lt Low threshold Level o Then signal must go below low threshold before Analog Comparison Event asserts Analog Comparison Event r Figure 11 6 Analog Edge Triggering with Hysteresis Falling Slope Example Analog Window Triggering An analog window trigger occurs when an analog signal either passes into enters or passes out of leaves a window defined by two voltage levels Specify the levels by setting the window Top value and the window Bottom value Figure 11 7 demonstrates a trigger that asserts when the signal enters the window Analog Comparison Event Figure 11 7 Analog Window Triggering Mode Entering Window M Series User Manual 11 6 ni com Chapter 11 Triggering Analog frigger Accuracy The analog trigger circuitry compares the voltage of the trigger source to the output of programmable trigger DACs When you configure the level or the high and low limits in window trigger mode the device adjusts the output of the trigger DACs Refer to the specifications document for your device to find the accuracy or resolution of these DACs which also shows the accuracy or resolution of analog triggers To improve accuracy do the following National Instruments Corporation Use an AI channel with a small input ran
32. Input Timing Diagram Table B 12 Input Timing Timing From To Min ns Max ns 4 PFI PFI i 4 1 6 4 15 2 19 2 RTSI RTSLi 0 9 2 2 2 0 3 0 STAR STAR_i 0 9 2 8 The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition maximum or minimum timing This difference can be useful when two external signals will be used together and the relative timing between the signals is important Internal Analog Output Timing National Instruments Corporation B 25 The analog output timer has two internal clocks that are referenced Sample Clock Timebase and Sync Sample Clock Timebase How they are generated depends on how the analog output timer is configured If the analog output timing engine is configured to operate with an external Sample Clock analog output internal clock timing can be derived from Table B 13 M Series User Manual Appendix B Timing Diagrams Sync Sample Clock Timebase Sample Clock Timebase Signal i A o ts E A la i A M Series User Manual Figure B 24 External Update Source Clock Insertions Timing Diagram Table B 13 External Update Source Clock Insertions Timing Timing From To Min ns Max ns t2 Signal_i Sample Clock 11 6 30 0 Timebase ts Signal_i Sync Sample Clock 1 5 7 0 Timebase If the Sample Clock is being
33. PFI 5 B Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6221 37 Pin Specifications Refer to the NI 622x Specifications for more detailed information about the NI 6221 37 pin device NI 6221 37 Pin Accessory and Cabling Options This section describes some cable and accessory options for the NI 6221 37 pin device Refer to ni com for other accessory options including new devices Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SH37F 37M cable to connect a NI 6221 37 pin device to a connector block such as the following CB 37FH DIN mountable connector block with 37 screw terminals e CB 37F LP Low profile connector block with 37 screw terminals RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices National Instruments Corporation A 13 M Series User Manual Appendix Device Specific Information Cables In most applications you can use the following cables SH37F 37M 1 37 pin female to male shielded I O cable 1 m e SH37F 37M 2 37 pin female to male shielded I O cable 2 m Custom Cabling and Connectivity Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solut
34. Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXT Advisor available by going to ni com info and entering the info code rdscad for more information A 4 ni com Appendix Device Specific Information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output
35. Start DT gt gt Terminal v gt LU Selected Start RTSI Selected Pause Trigger Pause Trigger SI Start 2 Sample Clock Timeb Al ample Clock Timebase Counter gt Sync Sample Clock Timebase Block O D SITC gt SI2 Convert Clock Timebase Gauntar SI2_TC Block Sync Convert Clock Timebase Start 4 Terminal Dec lt gt gt Terminal Figure B 2 Input Timing and the Analog Input Timing Engine Terminal p_Al_Convert Nadia Sample Clock q Terminal Figure B 3 Input Timing Diagram Table B 1 Input Timing Timing Line To Min ns Max ns t PFI PFLi 4 2 6 4 15 2 19 2 RTSI RTSLi 0 9 2 2 2 0 3 0 STAR STAR_i 0 9 2 8 The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition maximum or minimum timing This difference can be useful when two external signals will be used together and the relative timing between the signals is important National Instruments Corporation B 5 M Series User Manual Appendix B Timing Diagrams Internal Timing M Series User Manual Al Timing Clocks The analog input timing engine has two levels of timing that control an AI acquisition The first level is the convert leve
36. Terminal E Series Terminal Terminal Differences 11 PFIO AI START TRIG PFI 0 P1 0 On E Series devices as an input this terminal can either TRIG1 be a PFI input or the analog trigger input On M Series devices as an input this terminal can only be a PFI input Analog triggers use the APFI lt 0 1 gt terminals E Series devices can drive this terminal with the AI START TRIG signal M Series devices as an output can drive this terminal with the AI START TRIG signal You also can route many other internal timing signals to this terminal On M Series devices you also can use this terminal as the digital I O signal P1 0 Also refer to Chapter 8 PFI 16 P0 6 P0 6 On both E Series and M Series devices these terminals are digital I O signals You can individually configure each signal as an input or output 48 P0 7 P0 7 On E Series devices P0 6 and P0 7 also can control the up down signal of general purpose Counters 0 and 1 respectively On M Series devices you have to use one of the PFI terminals to control the up down signal of general purpose Counters 0 and 1 20 AO EXT REF APFI 0 On E Series devices this terminal is the external EXTREF reference input for the AO circuitry On M Series devices this terminal can be used as the external reference input for the AO circuitry the external offset for the AO circuitry or the analog trigger input These functions are not available on all devices Re
37. USB 6251 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6251 device USB 6251 LED Patterns The USB 6251 device has two LEDs labeled ACTIVE and READY The ACTIVE LED indicates activity over the bus The READY LED indicates whether or not the device is configured Table A 10 shows the behavior of the LEDs Table A 10 USB 6251 LED Patterns ACTIVE LED READY LED USB 6251 State Off Off The device is either not connected to the host computer or not powered Off On The device is configured but there is no activity over the bus On On The device is configured and there is activity over the bus Blinking On M Series User Manual A 44 ni com Appendix Device Specific Information USB 6251 Fuse Replacement USB 6251 devices have a replaceable 2A 250V 5 x 20 mm fuse To remove the fuse from the USB 6251 complete the following steps 1 Loosen the four flathead Phillips screws that attach the back lid to the enclosure and remove the lid 2 Replace the fuse while referring to Figure A 10 for the fuse location os SE 7 Fuse Figure A 10 USB 6251 Fuse Location 3 Replace the lid and screws National Instruments Corporation A 45 M Series User Manual Appendix Device Specific Information USB 62
38. When to Use Differential Connections with Ground Referenced Signal Sources Use DIFF input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the device are greater than 3 m 10 ft e The input signal requires a separate ground reference point or return signal e The signal leads travel through noisy environments e Two analog input channels AI and AI are available DIFF signal connections reduce noise pickup and increase common mode noise rejection DIFF signal connections also allow input signals to float within the common mode limits of the NI PGIA Refer to the Using Differential Connections for Ground Referenced Signal Sources section for more information about differential connections When to Use Non Referenced Single Ended NRSE Connections with Ground Referenced Signal Sources Only use non referenced single ended input connections if the input signal meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft e The input signal can share a common reference point with other signals National Instruments Corporation 4 21 M Series User Manual Chapter 4 Analog Input DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In
39. accessories for your M Series device NI offers cables and accessories for many applications However if you want to develop your own cable adhere to the following guidelines for best results e For AI signals use shielded twisted pair wires for each Al pair of differential inputs Connect the shield for each signal pair to the ground reference at the source e Route the analog lines separately from the digital lines e When using a cable shield use separate shields for the analog and digital sections of the cable Failure to do so results in noise coupling into the analog signals from transient digital signals For more information about the connectors used for DAQ devices refer to the KnowledgeBase document Specifications and Manufacturers for Board Mating Connectors by going to ni com info and entering the info code rdspmb Programming Devices in Software M Series User Manual National Instruments measurement devices are packaged with NI DAQ driver software an extensive library of functions and VIs you can call from your application software such as LabVIEW or LabWindows CVI to program all the features of your NI measurement devices Driver software has an application programming interface API which is a library of VIs functions classes attributes and properties for creating applications for your device 2 6 ni com Chapter 2 DAQ System Overview NI DAQ 7 3 and later includes two NI DAQ drivers Traditi
40. for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable 1 TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 19 M Series User Manual Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions M Series User Manual A 20 ni com Appendix Device Specific Information NI 6225 NI 6225 Pinout Figure A 5 shows the pinout of the NI 6225 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions sect
41. glitch GND ground H hardware hardware triggering National Instruments Corporation G 9 Glossary The condition where a common mode voltage exists or may exist between earth ground and the instrument or circuit of interest Neither the high nor the low side of a circuit is at earth potential Signal sources with voltage signals that are not connected to an absolute reference of system ground Also called non referenced signal sources Some common examples of floating signal sources are batteries transformers and thermocouples Frequency Output signal The number of alternating signals that occur per unit time Feet 1 A built in execution element comparable to an operator function or statement in a conventional language 2 A set of software instructions executed by a single line of code that may have input and or output parameters and returns a value when executed An unwanted signal excursion of short duration that is usually unavoidable See ground 1 A pin 2 An electrically neutral wire that has the same potential as the surrounding earth Normally a noncurrent carrying circuit intended for safety 3 A common reference point for an electrical system The physical components of a computer system such as the circuit boards plug in devices chassis enclosures peripherals and cables A form of triggering where you set the start time of an acquisition and gather data at a known position in t
42. the accuracy of the measurement decreases as the frequency increases Consider a frequency measurement on a 50 kHz signal using an 80 MHz Timebase This frequency corresponds to 1600 cycles of the National Instruments Corporation 7 13 M Series User Manual Chapter 7 Counters 80 MHz Timebase Your measurement may return 1600 1 cycles depending on the phase of the signal with respect to the timebase As your frequency becomes larger this error of 1 cycle becomes more significant Table 7 1 illustrates this point Table 7 1 Frequency Measurement Method 1 Task Equation Example 1 Example 2 Actual Frequency to Measure F1 50 kHz 5 MHz Timebase Frequency Ft 80 MHz 80 MHz Actual Number of Timebase Ft F1 1600 16 Periods Worst Case Measured Number Ft F1 1 1599 15 of Timebase Periods Measured Frequency Ft F1 Ft F1 50 125 kHz 5 33 MHz Error Ft F1 Ft F1 F1 125 kHz 333 kHz Error Ft Ft F1 1 0 06 6 67 M Series User Manual e Method 1b measuring K periods of F1 improves the accuracy of the measurement disadvantage of Method 1b is that you have to take K 1 measurements These measurements take more time and consume some of the available PCI or PXI bandwidth e Method 2 is accurate for high frequency signals However the accuracy decreases as the frequency of the signal to measure decreases At very low frequencies Method 2 may be too inaccurate for your applicati
43. 1 PFI 12 P2 4 PFI 14 P2 6 NC No Connect CONNECTOR 0 TERMINAL 68 Y TERMINAL 34 Al 0 15 CONNECTOR 1 71 78 69 68 75 66 65 TE GND 55 54 61 52 Al 16 79 TERMINAL 35 TERMINAL 1 TERMINAL 1 51 58 49 48 47 38 37 TERMINAL 34 TERMINAL 35 Y Gl Gs GND 35 34 41 32 23 30 21 20 27 18 17 24 TERMINAL 68 gt 5 gt ES gt ES gt ES gt Pal gt ES gt el gt Es gt Bal gt ES gt Pal gt ES gt Pal gt E gt Bl gt E gt OD J DO NMD PABAfO D gt y NI o rgi 76 167 74 173 64 GND 63 162 53 1 60 59 150 57 156 139 146 45 136 SENSE 2 143 42 133 40 131 22 129 28 119 26 125 gt ei gt E gt E gt E gt gt E gt Ex E gt 5 gt x 5 gt 5 gt Er x gt gt 16 M Series User Manual Figure A 5 NI 6225 Pinout Table A 5 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 A 22 ni com Appendix Device Specific Information Table A 5 Default NI DAQmx Counter Timer Pins Continued
44. 10 4 Direct Memory Access DMA ss 10 4 USB Signal Stream ss men ne llei 10 4 Interrupt Request IRQ seirer e e i E aS 10 4 Programmed Os ss e E A O R E TT aE 10 4 Changing Data Transfer Methods 10 5 PEVPCTE PXI Devices uan 10 5 USB DEVICES a in te ae 10 5 Chapter 11 Triggering Triggering with a Digital Source ss 11 1 Triggering with an Analog Source ss 11 2 APET lt O T gt Terminals cic sn dial ito dra nd 11 2 Analog Input Channels 888208 ent no 11 3 Analog Trigger Actions eee pins 11 3 Routing Analog Comparison Event to an Output Terminal ooo 11 3 Analog Erie per Types issus ra mb en rides dessertes 11 3 Analog Edge TM iii anna nine 11 4 Analog Edge Triggering with Hysteresis 11 4 Analog Edge Trigger with Hysteresis Rising Slope 11 5 Analog Edge Trigger with Hysteresis Falling Slope 11 5 Analog Window Triggering ss 11 6 Analog Trigger Accra iii is 11 7 Appendix A Device Specific Information A O tee lke A 2 NEO ut dt dadas tdt A 7 NOA NR aa A 15 NO aaa A 21 IA ve hice E het A 27 A O E A 33 IND G25 ii sz A 38 M Series User Manual xiv ni com Appendix B Timing Diagrams Appendix C Troubleshooting Appendix D Upgrading from E Series to M Series Appendix E Technical Support and Professional Services Glossary Index Device Pinouts Figure A 1 NI 6220 Pinout seein Figure A 2 NI 6221 68 Pin Pin
45. 21 55 AO GND PO 3 47 13 D GND AO 2 22156 Al GND PFI 11 P2 3 46 12 D GND TERMINAL 35 at pl TERMINAL 68 Al31 23157 A123 PFI 10 P2 2 45 11 PFI 0 P1 0 AI GND 24 58 Al 30 D GND 44 10 PFI1 P1 1 AI 22 25 59 Al GND PFI 2 P1 2 43 9 D GND AI 29 26 60 AI 21 PFI 3 P1 3 42 8 45V ALGND 27 61 A128 PFI 4 P1 4 41 7 D GND Al20 28 62 Al SENSE 2 PFI 13 P2 5 40 6 PFI5 P1 5 AI GND 29 63 A127 PFI 15 P2 7 39 5 PFI 6 P1 6 Al 19 30 64 Al GND PFI 7 P1 7 38 4 D GND Al 26 31 65 A118 PFI 8 P2 0 37 3 PFI9 P2 1 AI GND 32 66 Al 25 D GND 36 2 PFI 12 P2 4 A117 33 67 A GND D GND 35 1 PFI 14 P2 6 A124 34 68 A116 Figure A 15 PCI PCle PXI 6259 Pinout Table A 15 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 O National Instruments Corporation A 65 M Series User Manual Appendix Device Specific Information Table A 15 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 3 Not
46. 3 Note For more information about programming digital I O applications and triggers in software refer to the NI DAQmx Help or the LabVIEW 8 x Help M Series User Manual 6 10 ni com Counters M Series devices have two general purpose 32 bit counter timers and one frequency generator as shown in Figure 7 1 The general purpose counter timers can be used for many measurement and pulse generation applications Input Selection Muxes Counter 0 NI AR Fo RF ST RF OS Input Selection Muxes Counter 0 Source Counter 0 Timebase ia RAS Counter 0 Internal Output Counter 0 Aux Counter 0 HW Arm Counter 0 A Counter 0 TC Counter 0 B Counter 0 Up_Down F Counter 0 Z Counter 1 Counter 1 Source Counter 1 Timebase N lt 4 Counter 1 Gat Counter 0 Internal Output Counter 1 Aux A Counter 1 HW Arm A Counter 1 A Counter 0 TC Counter 1 B Counter 1 Up_Down A Counter 1 Z Input Selection Muxes Frequency Generator E D Frequency Output Timebase Freq Out National Instruments Corporation Figure 7 1 M Series Counters 7 1 M Series User Manual Chapter 7 Counters The counters have seven input signals although in most applications only a few inputs are used For information about connecting counter signals refer to the Default Counter Timer Pinouts section Counter Input Applications Counting Edges M Series Use
47. 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1 B 46 PFI 11 Sy Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6229 Specifications Refer to the NI 622x Specifications for more detailed information about the NI 6229 device NI 6229 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with two 68 pin connectors such as the NI 6229 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and later supports SCXI in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold National Instruments Corporation A 29 M Series User Manual Appendix M Series User Manual Device Specific Information You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Ref
48. 6 4 ni com Chapter 6 Digital 1 0 e PXISTAR e Analog Comparison Event an analog trigger You can sample data on the rising or falling edge of di SampleClock Routing DI Sample Clock to an Output Terminal You can route di SampleClock out to any PFI terminal The PFI circuitry inverts the polarity of di SampleClock before driving the PFI terminal Digital Waveform Generation You can generate digital waveforms on the Port 0 DIO lines The DO waveform generation FIFO stores the digital samples M Series devices have a DMA controller dedicated to moving data from the system memory to the DO waveform generation FIFO The DAQ device moves samples from the FIFO to the DIO terminals on each rising or falling edge of a clock signal do SampleClock You can configure each DIO signal to be an input a static output or a digital waveform generation output The FIFO supports a retransmit mode In the retransmit mode after all the samples in the FIFO have been clocked out the FIFO begins outputting all of the samples again in the same order For example if the FIFO contains five samples the pattern generated consists of sample 1 2 3 4 5 1 2 3 4 5 1 and so on DO Sample Clock Signal Use the DO Sample Clock do SampleClock signal to update the DO terminals with the next sample from the DO waveform generation FIFO M Series devices do not have the ability to divide down a timebase to produce an internal DO Sample Cl
49. A quadrature encoder can have up to three channels channels A B and Z X1 Encoding When channel A leads channel B in a quadrature cycle the counter increments When channel B leads channel A in a quadrature cycle the counter decrements The amount of increments and decrements per cycle depends on the type of encoding X1 X2 or X4 Figure 7 15 shows a quadrature cycle and the resulting increments and decrements for X1 encoding When channel A leads channel B the increment occurs on the rising edge of channel A When channel B leads channel A the decrement occurs on the falling edge of channel A M Series User Manual Chapter 7 Counters ChA l eee ChB l 1 coe Counter Value 5 X 6 X 7 T X 6 X 5 Figure 7 15 X1 Encoding X2 Encoding The same behavior holds for X2 encoding except the counter increments or decrements on each edge of channel A depending on which channel leads the other Each cycle results in two increments or decrements as shown in Figure 7 16 ChA eu es oe Counter Value 5X 6 X 7 X 8 X 9 9X 8X 7X 6 X5 Figure 7 16 X2 Encoding X4 Encoding Similarly the counter increments or decrements on each edge of channels A and B for X4 encoding Whether the counter increments or decrements depends on which channel leads the other Each cycle r
50. AI lt 48 55 gt AI lt 40 47 gt AI lt 56 63 gt AI lt 64 71 gt AI lt 72 79 gt For more information about routing NI 6225 signals to the NI PGIA in NRSE mode refer to the KnowledgeBase document NI 6225 Using Channels 64 Through 79 in NRSE Mode by going to ni com info and entering the info code 6225NRSE M Series User Manual Notice that some M Series devices do not support the AI lt 16 79 gt signals 4 6 ni com Chapter 4 Analog Input For differential measurements AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0 For a complete list of signal pairs that form differential input channels refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information A Caution The maximum input voltages rating of AI signals with respect to ground and for differential signals with respect to each other are listed in the specifications document for your device Exceeding the maximum input voltage of AI signals distorts the measurement results Exceeding the maximum input voltage rating also can damage the device and the computer NI is not liable for any damage resulting from such signal connections AI ground reference setting is sometimes referred to as AJ terminal configuration Configuring Al Ground Reference Settings in Software You can program channels on an M Series device to acquire with different ground references To
51. AI GND 32 66 al25 D GND 36 2 PFI12 P24 Al 17 33 67 AI GND D GND 35 1 PFI14 P2 6 AI 24 34 68 Al16 NC No Connect NC No Connect Figure A 13 NI 6254 Pinout Table A 13 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 National Instruments Corporation A 53 M Series User Manual Device Specific Information Table A 13 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6254 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6254 device NI 6254 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with two 68 pin connectors such as the NI 6254 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation appl
52. Ala ing ais a ph a oa alada 6 2 Digital Waveform Triggering ss 6 3 Digital Waveform Acquisiti0N ss 6 3 DESample Clock malicia 6 4 Using an Internal Source ooooconccnoccoonnononnnonnnonononcnnnonnonn cono nn non ncnncnnnons 6 4 Using an External Source ss 6 4 Routing DI Sample Clock to an Output Terminal 6 5 Digital Waveform Generation ssl enr Sian denied cidos 6 5 DO Sample Clock Signal 6 5 Using an Internal Source ss 6 6 Using an External Source ss 6 6 M Series User Manual X ni com Contents Routing DO Sample Clock to an Output Terminal 6 6 VO Protection ses satire aadecet casas dt Sade estes made 6 7 Programmable Power Up States ss 6 7 DI Change Detection sess sfr tte tee aeons aun toners dette 6 8 Applications cta Litas add lara ete lo ab eee 6 9 Connecting Digital I O Signals ss 6 9 Getting Started with DIO Applications in Software 6 10 Chapter 7 Counters Counter Input Applications ustensiles 7 2 Counting Ed peSant A is 7 2 Single Point On Demand Edge Counting cocoonocnnonnnnnnancnncnncnnonanono 7 2 Buffered Sample Clock Edge Counting 0 eee eee eeeeeeeeees 7 3 Non Cumulative Buffered Edge Counting oooooconocnncnnoncnnnonnninccnnonnos 7 4 Controlling the Direction of Counting oocooconcccocnnanconnnnncnnnonacanonanonnnns 7 4 Pulse Width Measurement 200 0 cece ceceseeeeeesecesesseeeseeseeeeeessenseeseenseeaeenaes 7 5 Single Pulse Width Measurement 7 5 Buff
53. Configured in DIFF Mode M Series User Manual Figure 4 6 Differential Connections for Floating Signal Sources with Balanced Bias Resistors Both inputs of the NI PGIA require a DC path to ground in order for the NI PGIA to work If the source is AC coupled capacitively coupled the NI PGIA needs a resistor between the positive input and AI GND If the source has low impedance choose a resistor that is large enough not to significantly load the source but small enough not to produce significant input offset voltage as a result of input bias current typically 100 kQ to 4 18 ni com Chapter 4 Analog Input 1 MQ In this case connect the negative input directly to AI GND If the source has high output impedance balance the signal path as previously described using the same value resistor on both the positive and negative inputs be aware that there is some gain error from loading down the source as shown in Figure 4 7 AC Coupling AC Coupled l of Al Floating Signal Vs Source o Al o Al SENSE o Al GND Figure 4 7 Differential Connections for AC Coupled Floating Sources with Balanced Bias Resistors Using Non Referenced Single Ended NRSE Connections for Floating Signal Sources National Instruments Corporation 4 19 It is important to connect the negative lead of a floating signals source to AI GND either directly or through a resistor Otherwise the source m
54. D GN PO 1 P0 6 DGN 5V DGN D GN D D PFI 0 P1 0 PFI 1 P1 1 D GN 5 V D GN D D PFI 5 P1 5 PFI 6 P1 6 D GN D PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 iN O CONNECTOR 0 Al 0 15 TERMINAL 68 TERMINAL 34 TERMINAL 35 TERMINAL 1 GA Figure A 8 PCI PCle PXI 6251 Pinout Table A 8 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 CTROB 45 PFI 10 O National Instruments Corporation A 39 M Series User Manual Appendix Device Specific Information Table A 8 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 3 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help M Series User Manual PCI PCle PXI 6251 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6251 device PCI PCle PXI 6251 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with one 68
55. DAC conversion In NI DAQmx software timed generations are referred to as on demand timing Software timed generations are also referred to as immediate or static operations They are typically used for writing a single value out such as a constant DC voltage 5 4 ni com Chapter 5 Analog Output Hardware Timed Generations With a hardware timed generation a digital hardware signal controls the rate of the generation This signal can be generated internally on your device or provided externally Hardware timed generations have several advantages over software timed acquisitions e The time between samples can be much shorter e The timing between samples can be deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or non buffered A buffer is a temporary storage in computer memory for to be generated samples Non Buffered In non buffered acquisitions data is written directly to the DACs on the device Typically hardware timed non buffered operations are used to write single samples with good latency and known time increments between them Buffered In a buffered acquisition data is moved from a PC buffer to the DAQ device s onboard FIFO using DMA or interrupts for PCI PCle PXI devices or USB Signal Streams for USB devices before it is written to the DACs one sample at a time Buffered acquisitions typically allow for much faster transfer rates than non buffer
56. DAQ Device Signal Source DAQ Device NRSE Al ALS Al SENSE Al SENSE Al GND Al GND Single Ended Signal Source DAQ Device Referenced RSE NOT RECOMMENDED Al Signal S DA i O gnal Source Q Device e co ALS es Al GND Va V e Bl _4ALGND Ground loop potential Va Vg are added to measured signal Refer to the Analog Input Ground Reference Settings section for descriptions of the RSE NRSE and DIFF modes and software considerations Refer to the Connecting Ground Referenced Signal Sources section for more information M Series User Manual 4 14 ni com Chapter 4 Analog Input Connecting Floating Signal Sources What Are Floating Signal Sources A floating signal source is not connected to the building ground system but has an isolated ground reference point Some examples of floating signal sources are outputs of transformers thermocouples battery powered devices optical isolators and isolation amplifiers An instrument or device that has an isolated output is a floating signal source When to Use Differential Connections with Floating Signal Sources Use DIFF input connections for any channel that meets any of the following conditions e The input signal is low level less than 1 V e The leads connecting the signal to the device are greater than 3 m 10 ft e The input signal requires a separate ground reference point or return signal e The signal
57. M Series devices You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 94 ni com Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for
58. M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 64 ni com Appendix Device Specific Information ALO 68 34 A18 P0 30 1 35 D GND AI GND 67 33 A11 Po 28 2 36 D GND Al 9 66 32 AI GND P0 25 3 37 P0 24 Al2 65 31 Al 10 a D GND 4 38 Po 23 AI GND 64 30 A13 T oH PO 22 5 39 Po 31 AI 11 63 29 AI GND 57 be P0 21 6 40 Po 29 Al SENSE 62 28 Al 4 us C DGND 7 41 Po 20 Al 12 61 27 AI GND 57 gs 5V 8 42 Po 19 Al5 60 26 A113 a O DGND 9 43 Po 18 AI GND 59 25 Al6 O Po 17 10 44 D GND Al 14 58 24 AI GND Po 16 11145 Po 26 Al7 57 23 Al 15 TERNINAL 68 l E TERMINAL 35 DGND 12 46 Po 27 Al GND 56 22 AOO D GND 13 47 Po 11 AO GND 55 21 A01 TERMINAL 34 TERMINALI pE 14 48 Po 15 AO GND 54 20 APFIO DGND 15 49 Po 10 D GND 53 19 Po 4 Po t4 16 50 D GND PO 0 52 18 D GND PO 9 17 51 Po 13 PO 5 51 17 PO D GND 18 52 Po s D GND 50 16 PO 6 po 12 19 53 DGND PO 2 49 15 D GND APFI1 20 54 AO GND F0 7 48 14 ISSN TERMINAL 1 TERMINAL 34 203
59. O ajuojo o i a NC No Connect AI 8 Al 1 Al GND Al 10 Al3 Al GND Al 4 Al GND Al 13 Al6 Al GND Al 15 NC NC NC PO 4 D GND PO 1 P0 6 D GND 5 V D GND D GND PFI 0 P1 0 PEINE D GND 5 V D GND PELSPIS PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 TERMINAL 68 TERMINAL 34 TERMINAL 1 TERMINAL 35 P0 30 P0 28 P0 25 D GND P0 22 P0 21 D GND 5V D GND P0 17 P0 16 Ta _ TERMINAL 35 D GND D GND TERMINALI sy D GND P0 14 P0 9 D GND P0 12 NC CONNECTOR 1 Al 16 31 y CONNECTOR 0 Al 0 15 TERMINAL 34 NC TERMINAL 68 AI 31 AI GND Al 22 AI 29 AI GND Al 20 Al GND Al 19 Al 26 Al GND Al 17 Al 24 6lz ess NC No Connect oa 35 36 37 38 39 40 41 42 9 43 10 44 11145 12 46 13 47 14 48 15 49 16 50 17 51 18 52 19 53 20 54 21 55 22 56 23 57 24 58 25 59 26 60 27 61 28 62 29 63 30 64 31 65 32 66 33 67 34 68 O0 J DO NO AJO D D GND D GND P0 24 P0 23 P0 31 P0 29 P0 20 P0 19 P0 18 D GND P0 26 P0 27 P0 11 P0 15 P0 10 D GND P0 13 P0 8 D GND NC NC AI GND Al 23 Al 30 Al GND Al 21 Al 28 Al SENSE 2 Al 27 AI GND Al 18 Al 25 Al GND Al 16 M Series User Manual Table A 4 Def
60. OR PERSONS INCLUDING THE RISK OF BODILY INJURY AND DEATH SHOULD NOT BE RELIANT SOLELY UPON ONE FORM OF ELECTRONIC SYSTEM DUE TO THE RISK OF SYSTEM FAILURE TO AVOID DAMAGE INJURY OR DEATH THE USER OR APPLICATION DESIGNER MUST TAKE REASONABLY PRUDENT STEPS TO PROTECT AGAINST SYSTEM FAILURES INCLUDING BUT NOT LIMITED TO BACK UP OR SHUT DOWN MECHANISMS BECAUSE EACH END USER SYSTEM IS CUSTOMIZED AND DIFFERS FROM NATIONAL INSTRUMENTS TESTING PLATFORMS AND BECAUSE A USER OR APPLICATION DESIGNER MAY USE NATIONAL INSTRUMENTS PRODUCTS IN COMBINATION WITH OTHER PRODUCTS IN A MANNER NOT EVALUATED OR CONTEMPLATED BY NATIONAL INSTRUMENTS THE USER OR APPLICATION DESIGNER IS ULTIMATELY RESPONSIBLE FOR VERIFYING AND VALIDATING THE SUITABILITY OF NATIONAL INSTRUMENTS PRODUCTS WHENEVER NATIONAL INSTRUMENTS PRODUCTS ARE INCORPORATED IN A SYSTEM OR APPLICATION INCLUDING WITHOUT LIMITATION THE APPROPRIATE DESIGN PROCESS AND SAFETY LEVEL OF SUCH SYSTEM OR APPLICATION Compliance Compliance with FCC Canada Radio Frequency Interference Regulations Determining FCC Class The Federal Communications Commission FCC has rules to protect wireless communications from interference The FCC places digital electronics into two classes These classes are known as Class A for use in industrial commercial locations only or Class B for use in residential or commercial locations All National Instruments NI products are FCC Class A products Depending on where i
61. P GND AO 0 D GND 204 TERMINAL 34 TERMINAL 4 45 NC D GND P0 4 P0 14 D GND P0 9 P0 1 D GND PO 6 P0 12 D GND NC 45 V AO 3 TERMINAL 1 TERMINAL 34 D GND AO 2 D GND TERMINAL 35 nl LUE TERMINAL 68 AI 31 PFI 0 P1 0 AI GND PFI 1 P1 1 O Al 22 D GND SA NE AI 29 5 V AI GND D GND AI 20 PFI 5 P1 5 AI GND PFI 6 P1 6 Al 19 D GND Al 26 PFI 9 P2 1 AI GND PFI 12 P2 4 Al 17 PFI 14 P2 6 AI 24 NC No Connect DOINID aA A jvj D GND D GND P0 24 P0 23 P0 31 P0 29 P0 20 P0 19 P0 18 D GND P0 26 P0 27 PO 11 PO 15 PO 10 D GND P0 13 P0 8 D GND AO GND AO GND GND 123 30 GND 21 128 SENSE 2 127 GND 118 25 GND 16 gt E gt Ef gt Ef gt ir a gt E gt NC No Connect M Series User Manual Figure A 6 NI 6229 Pinout Table A 6 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 A 28 ni com Appendix Device Specific Information Table A 6 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTR OB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX
62. P0 25 D GND P0 26 D GND P0 27 D GND P0 28 D GND P0 29 D GND P0 30 D GND P0 31 D GND O National Instruments Corporation Figure A 16 USB 6259 Pinout A 71 M Series User Manual Appendix Device Specific Information Table A 16 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 81 PFI 8 CTR 0 GATE 83 PFI 9 CTR 0 AUX 85 PFI 10 CTR 0 OUT 89 PFI 12 CTROA 81 PFI 8 CTROZ 83 PFI 9 CTROB 85 PFI 10 CTR 1 SRC 76 PFI 3 CTR 1 GATE 77 PFI 4 CTR 1 AUX 87 PFI 11 CTR 1 OUT 91 PFI 13 CTR 1 A 76 PFI 3 CTR1IZ 77 PFI 4 CTR 1B 87 PFI 11 ay Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help USB 6259 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6259 device USB 6259 LED Patterns The USB 6259 device has two LEDs labeled ACTIVE and READY The ACTIVE LED indicates activity over the bus The READY LED indicates whether or not the device is configured Table A 17 shows the behavior of the LEDs M Series User Manual A 72 ni com Appendix Device Specific Information Table A 17 USB 6259 LED Patterns ACTIVE LED READY LED USB 6259 State Off Off The device is either not connected to the host computer or not powered Off On T
63. P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 45 44 43 42 41 40 39 38 37 36 35 njojasjoafjo ufofo 3 Z 5 o AI8 Al1 Al GND Al1 Al3 Al GND Al 4 Al GND Al1 Al6 Al GND Al1 NC NC APFI 0 PO 4 DG PO 1 P0 6 DG 5V DG DG PF PF DG 5V DG PF PF DG PF PF PF NC No Connect 0 CONNECTOR 0 Al 0 15 3 DO 5 TERMINAL 68 TERMINAL 34 ND ND ND ND TERMINAL 35 TERMINAL 1 0 P1 0 1 P1 1 ND S ND 5 P1 5 6 P1 6 ND 9 P2 1 12 P2 4 14 P2 6 Figure A 7 NI 6250 Pinout Table A 7 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR O SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 A 34 ni com Appendix Device Specific Information Table A 7 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pi
64. Sample Clock Signal to an Output Terminal 4 29 Other Timing Requirements 4 29 AI Sample Clock Timebase Signal 4 30 AT Convert Clock Signal ccoo iii Adaro 4 31 Using an Internal Source 4 31 Using n External Source hais necia 4 32 Routing AI Convert Clock Signal to an Output Terminal 4 32 Using a Delay from Sample Clock to Convert Clock 4 32 Other Timing Requirements 4 33 AI Convert Clock Timebase Signal 4 35 AI Hold Complete Event Signal ss 4 35 AL Start Trigger Signal suisses usines rites 4 35 Using a Digital Source 2 0 nreti niian 4 35 Using an Analog Source ss 4 36 Routing AI Start Trigger to an Output Terminal oooonnnnnnnninnninnnn 4 36 AI Reference Trigger Signal 0 ee ssesessseeecceneceecessesesenseneconsseecseeeneesees 4 36 Using a Digital Source ss 4 37 Using an Analog Source cocooonccnocconononconononcnnonncnnnonannn cnn nonn oran cano rancia 4 37 Routing Al Reference Trigger Signal to an Output Terminal 4 38 Al Pause Trigger Signal initie dentiste 4 38 Using a Digital Source 28h sans 4 38 Using an Analog Source coocoonccnccnoccnonconononconcnononnnonnnnn cnn nono cnn n cano ronca 4 38 Routing Al Pause Trigger Signal to an Output Terminal 4 38 Getting Started with AI Applications in Software 4 39 O National Instruments Corporation ix M
65. Sample Clock signal 5 10 AO Sample Clock Timebase signal 5 12 AO Start Trigger signal 5 8 ao PauseTrigger 5 9 ao SampleClock 5 10 ao StartTrigger 5 8 APFI terminals 1 2 ni com applications counter input 7 2 counter output 7 20 edge counting 7 2 arm start trigger 7 32 avoiding scanning faster than necessary 4 10 buffered edge counting 7 3 non cumulative 7 4 buffered hardware timed acquisitions 4 12 buffered hardware timed generations 5 5 buffered period measurement 7 7 buffered pulse width measurement 7 5 buffered semi period measurement 7 9 buffered two signal edge separation measurement 7 19 bus interface 10 1 RTSI 9 4 C cables 2 5 choosing for your device 1 2 NI 6220 A 4 NI 6221 37 pin A 13 NI 6221 68 pin A 9 NI 6224 A 17 NI 6225 A 23 NI 6229 A 29 NI 6280 A 82 NI 6281 A 87 NI 6284 A 92 NI 6289 A 98 NI 6250 A 35 NI 6254 A 54 NI 6255 A 60 PCI PCle PXI 6251 A 40 PCI PCle PXI 6259 A 66 National Instruments Corporation 1 3 Index USB 6251 Mass Termination A 48 USB 6259 Mass Termination A 76 cabling 2 5 custom 2 6 calibration 2 3 calibration certificate NI resources E 2 calibration circuitry 2 3 cascading counters 7 33 Change Detection Event signal 6 8 changing data transfer methods between DMA and IRQ 10 5 between USB signal stream and programmed I O 10 5 channel scanning order 4 9 channel Z behavior 7 16 channels analog input 11 3 sam
66. Series User Manual Contents Chapter 5 Analog Output Analog Output Circuitry serres enterrer ne te ne et ner tete set st esse 5 1 AO Offset and AO Reference Selection 5 2 Minimizing Glitches on the Output Signal 5 4 Analog Output Data Generation Methods 5 4 Software Timed Generations ss 5 4 Hardware Timed Generations ss 5 5 Non Bullered cia tee ea 5 5 Bere A OT nt Te svecpsarseeestenn tutte utiess 5 5 Analog Output Triggering ss 5 6 Connecting Analog Output Signals ss 5 6 Analog Output Timing Signals ss 5 7 AQ Start Tre ser Signal tdt Mie e 5 8 Using a Digital Source nn nt tone it 5 8 Using aM Analog Sources ti hottes test 5 8 Routing AO Start Trigger Signal to an Output Terminal 5 8 AO Pause Trigger Sinaloa tic 5 9 Using a Digital Source mnn r ann e font 5 10 Using an Analog Source sun 5 10 Routing AO Pause Trigger Signal to an Output Terminal 5 10 AQ Sample Clock Signal sn nn eee er net des 5 10 Using an Internal Source oo eee eee csceseeseeeeeceeeseseeeeseeseeeseeaeee 5 10 Using an External Source startna e ETERA 5 11 Routing AO Sample Clock Signal to an Output Terminal 5 11 Other Timing Requirements 5 11 AO Sample Clock Timebase Signal 5 12 Getting Started with AO Applications in Software 5 12 Chapter 6 Digital 1 0 Static DIO sessilis een Aceh
67. TERMINAL 1 AI 51 14 48 also AO GND 54 20 APFIO AI 58 15 49 also D GND 53 19 Po 4 Al 49 16 50 A157 P0 0 52 18 D GND Al 48 17 51 aise P0 5 51 17 Po 1 Al 47 18 52 AI 39 D GND so 16 Po 6 AI 38 19153 alae PO 2 49 15 D GND AI 87 2054 A145 PO 7 48 14 5V AI 44 21155 alse PO 3 47 13 D GND TERMINAI TERMINAL 34 Ai and 22 56 al SENSE 2 PFI 11 P2 3 46 12 D GND TERMINAL 35 nl LE TERMINAL 68 AI 35 23157 A143 PFI 10 P2 2 45 11 PFIO P1 0 AI 34 24 58 A1 42 D GND 44 10 PFI1 P1 1 Al 41 25159 A133 PFI 2 P1 2 43 9 DGND AI 32 26 60 A1 40 PFI 3 P1 3 42 8 45V AI 23 27 61 A131 PFI 4 P1 4 41 7 DGND AI 30 28 62 al22 PFI 13 P2 5 40 6 PFI5 P1 5 AI 21 29 63 A1 29 PFI 15 P2 7 39 5 PFI6 P1 6 AI 20 30 64 A1 28 PFI 7 P1 7 38 4 DGND AI 27 31165 A119 PFI 8 P2 0 37 3 PFI9 P2 1 AI 18 32 66 A1 26 D GND 36 2 PFI12 P24 Al 17 33 671 A125 D GND 35 1 PFI14 P2 6 AI 24 34 68 A1 16 UOU NC No Connect Figure A 14 NI 6255 Pinout Table A 14 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 National Instruments Corporation A 59 M Series User Manual Appendix Device Specific Information Table A 14 Default NI D
68. Terminal D SIL TC p_Al_Convert C Clock Timeb ae onvert Clock Timebase Counter a Block Sync Convert Clock Timebase Start r Selected Sample Clock f Terminal Terminal Taa bz Selected Sample Clock i 1 1 bog tog gt Sync Convert Clock Timebase FJ iT L i 30 Eat Sample Clock 1 i t POUT Figure B 16 Sample Clock Timing Diagram National Instruments Corporation B 17 M Series User Manual Appendix B Timing Diagrams Table B 8 Sample Clock Timing Timing Description Line Min ns Max ns to7 Delay to PFI 3 5 8 9 Selected Sample Clock RTSI 34 8 6 STAR 2 8 5 9 tog Selected Sample Clock Setup 1 5 time to Sync Convert Clock Timebase bo Selected Sample Clock Holdtime 0 to Sync Convert Clock Timebase t30 Sync Convert Clock Timebase to 2 4 5 8 Sample Clock t31 Sample Clock PFI 2 4 SS to POUT RTSI 3 2 6 8 The AI timing engine also can export a signal related to the Sample Clock called AI_Sample_In_Progress This signal asserts with the Sample Clock and stays asserted until after the last convert of the sample It is useful for external simultaneous sample and hold signal conditioning Sample Clock Convert Clock POUT tao lt lag gt M Series User Manual Figure B 17 Al_Sample_In_Progress T
69. Trigger Reference Trigger Terminal He gt g gt Terminal e y Start Terminal ec gt De Terminal Selected Start Terminal Selected Pause Trigger q o Pause Trigger SI Start Terminal SI Sample Clock Timebase Counter Sync Sample Clock Timebase EIGER Terminal p_Al_ Convert SI2 Convert Clock Timebase Counter SI2_TC lt Block Sync Convert Clock Timebase Start 1 A Terminal Selected Sample Clock Terminal gt Figure B 6 Convert Clock and the Analog Input Timing Engine National Instruments Corporation B 9 M Series User Manual Appendix B Timing Diagrams Sync Convert Clock Timebase Convert Clock Timebase ip tro p_Al_Convert 2 thy POUT Figure B 7 Convert Clock Timing Diagram Table B 3 Convert Clock Timing Timing Description Line Min ns Max ns tg Delay from _i PFI 6 4 15 9 to Sync Convert Clock RTSI 6 0 15 6 ne STAR 5 7 12 9 to Delay from _i PFI 16 2 39 1 to Convert Clock RTSI 16 0 38 8 HORS STAR 15 5 36 1 tio Delay from Convert Clock 6 0 13 0 Timebase to p_AI_Convert ty Delay from PFI 4 6 10 8 Convert Clock Timebase to RTSI 4 6 10 5 Convert Clock when exported to an external terminal POUT M Series User Manual B 10 ni com Appendix B
70. Trigger Terminal Le 99 ae De Terminal Q gt i Terminal 5 Start gt Terminal gt RTSI Selected Pause Trigger Terminal Le 99 lt gt Pause Trigger SI Start Terminal Se gt SI Sample Clock Timebase Counter N poe Sync Sample Clock Timebase Block OF gt Terminal D SI_TC y j p_Al_Convert O gt SI2 Convert Clock Timebase Counter 812 TC Sync Convert Clock Timebase Blook 1 Start Selected Sample Clock Terminal ec gt E D gt Terminal e Figure B 11 Sample Clock Timebase Timing and the Analog Input Timing Engine O National Instruments Corporation B 13 M Series User Manual Appendix B Timing Diagrams Selected Start a i tao i tig Sync Sample Clock Timebase toy gt SI Start Figure B 12 Sample Clock Timebase Timing Diagram Table B 6 Sample Clock Timebase Timing Timing Description Line Min ns Max ns tig Delay to PFI 3 4 8 8 Selected Start RTSI 3 3 8 5 STAR 2 7 5 7 tio Selected Start Setup Hold Time 1 5 to Sync Sample Clock Timebase bo Selected Start Setup Hold Time 0 to Sync Sample Clock Timebase toy Sync Sample Clock Timebase to 0 9 2 2 SL Start Reference Trigger Use the Reference Trigger to stop the acquisition It is normally used in pretrigger acquisitions it is necessary to acquire data before and aft
71. Value 0 Figure 7 3 Single Point On Demand Edge Counting with Pause Trigger Buffered Sample Clock Edge Counting With buffered edge counting edge counting using a sample clock the counter counts the number of edges on the Source input after the counter is armed The value of the counter is sampled on each active edge of a sample clock A DMA controller transfers the sampled values to host memory The count values returned are the cumulative counts since the counter armed event That is the sample clock does not reset the counter You can route the counter sample clock to the Gate input of the counter You can configure the counter to sample on the rising or falling edge of the sample clock Figure 7 4 shows an example of buffered edge counting Notice that counting begins when the counter is armed which occurs before the first active edge on Gate Counter Armed Sample Clock Sample on Rising Edge source 11414 41 41 4 41 4 Counter Value 0 1 2 3 4 5 6 l 7 i 3 El Buffer H Figure 7 4 Buffered Sample Clock Edge Counting National Instruments Corporation 7 3 M Series User Manual Chapter 7 Counters M Series User Manual Non Cumulative Buffered Edge Counting Non cumulative edge counting is similar to buffered sample clock edge counting However the counter resets after each active edge of the Sample Clock You
72. a computer USB or 1394 FireWire port SCXI modules are considered DAQ devices Data acquisition system timing controller chip The general concept of acquiring data as in begin data acquisition or data acquisition and control See also DAQ A technique for moving digital data from one system to another Options for data transfer are DMA interrupt and programmed I O For programmed I O transfers the CPU in the PC reads data from the DAQ device whenever the CPU receives a software signal to acquire a single data point Interrupt based data transfers occur when the DAQ device sends an interrupt to the CPU telling the CPU to read the acquired data from the DAQ device DMA transfers use a DMA controller instead of the CPU to move acquired data from the device into computer memory Even though high speed data transfers can occur with interrupt and programmed I O transfers they require the use of the CPU to transfer data DMA transfers are able to acquire data at high speeds and keep the CPU free for performing other tasks at the same time Decibel The unit for expressing a logarithmic measure of the ratio of two signal levels dB 20log10 V1 V2 for signals in volts Direct current although the term speaks of current many different types of DC measurements are made including DC Voltage DC current and DC power A plug in data acquisition product card or pad that can contain multiple channels and conversion devices Plug in
73. can route the Sample Clock to the Gate input of the counter Figure 7 5 shows an example of non cumulative buffered edge counting Counter Sample Clock di Sample on Rising Edge i i i __ SOURCE F 41467 41474 4141 Counter Value 0 11 2 4 2 3 11 2 3 1 2 BB e Buffer i 3 Figure 7 5 Non Cumulative Buffered Edge Counting Notice that the first count interval begins when the counter is armed which occurs before the first active edge on Gate Note that if you are using an external signal as the Source at least one Source pulse should occur between each active edge of the Gate signal This condition ensures that correct values are returned by the counter If this condition is not met consider using duplicate count prevention described in the Duplicate Count Prevention section Controlling the Direction of Counting In edge counting applications the counter can count up or down You can configure the counter to do the following e Always count up e Always count down e Count up when the Counter n B input is high count down when it is low For information about connecting counter signals refer to the Default Counter Timer Pinouts section 7 4 ni com Chapter 7 Counters Pulse Width Measurement In pulse width measurements the counter measures the width of a
74. com info and enter the info code rdmseis D 1 M Series User Manual Technical Support and Professional Services Visit the following sections of the National Instruments Web site at ni com for technical support and professional services National Instruments Corporation Support Online technical support resources at ni com support include the following Self Help Resources For answers and solutions visit the award winning National Instruments Web site for software drivers and updates a searchable KnowledgeBase product manuals step by step troubleshooting wizards thousands of example programs tutorials application notes instrument drivers and so on Free Technical Support All registered users receive free Basic Service which includes access to hundreds of Application Engineers worldwide in the NI Developer Exchange at ni com exchange National Instruments Application Engineers make sure every question receives an answer For information about other technical support options in your area visit ni com services or contact your local office at ni com contact Training and Certification Visit ni com training for self paced training eLearning virtual classrooms interactive CDs and Certification program information You also can register for instructor led hands on courses at locations around the world System Integration If you have time constraints limited in house technical resources or othe
75. computer can determine the value DAQ devices such as the M Series multifunction I O MIO devices SCXI signal conditioning modules and switch modules Megahertz A unit of frequency 1 MHz 10 Hz 1 000 000 Hz The numerical prefix designating 10 M Series User Manual Glossary MIO MITE module monotonicity multichannel multifunction DAQ multiplex mux NI NI DAQ M Series User Manual Multifunction I O DAQ module Designates a family of data acquisition products that have multiple analog input channels digital I O channels timing and optionally analog output channels An MIO product can be considered a miniature mixed signal tester due to its broad range of signal types and flexibility Also known as multifunction DAQ MXI Interface To Everything A custom ASIC designed by National Instruments that implements the PCI bus interface The MITE supports bus mastering for high speed data transfers over the PCI bus A board assembly and its associated mechanical parts front panel optional shields and so on A module contains everything required to occupy one or more slots in a mainframe SCXI and PXI devices are modules A characteristic of a DAC in which the analog output always increases as the values of the digital code input to it increase Pertaining to aradio communication system that operates on more than one channel at the same time The individual channels might contain identical in
76. device using the Device Document Browser at any time by inserting the CD After installing the National Instruments Corporation xxi M Series User Manual About This Manual Device Document Browser device documents are accessible from Start All Programs National Instruments NI DAQ gt Browse Device Documentation Training Courses If you need more help getting started developing an application with NI products NI offers training courses To enroll in a course or obtain a detailed course outline refer to ni com training Technical Support on the Web For additional support refer to ni com support or zone ni com ay Note You can download these documents at ni com manuals DAQ specifications and some DAQ manuals are available as PDFs You must have Adobe Acrobat Reader with Search and Accessibility 5 0 5 or later installed to view the PDFs Refer to the Adobe Systems Incorporated Web site at www adobe com to download Acrobat Reader Refer to the National Instruments Product Manuals Library at ni com manuals for updated documentation resources M Series User Manual xxii ni com Getting Started M Series devices feature up to 80 analog input AT channels two counters up to 48 lines of digital input output DIO and up to four analog output AO channels If you have not already installed your device refer to the DAQ Getting Started Guide For specifications arranged by M Series device family refer to the specifica
77. devices with two 68 pin connectors such as the NI 6289 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and later supports SCXI in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold M Series User Manual A 98 ni com Appendix Device Specific Information You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by going to ni com info and
78. do the following Use a common clock or timebase to drive the timing engine on multiple devices e Share trigger signals between devices Many National Instruments DAQ motion vision and CAN devices support RTSL In a PCI system the RTSI bus consists of the RTSI bus interface and a ribbon cable The bus can route timing and trigger signals between several functions on as many as five DAQ vision motion or CAN devices in the computer In a PXI system the RTSI bus consists of the RTSI bus interface and the PXI trigger signals on the PXI backplane This bus can route timing and trigger signals between several functions on as many as seven DAQ devices in the system RTSI Connector Pinout Figure 9 2 shows the RTSI connector pinout and Table 9 1 describes the RTSI signals Terminal 34 Terminal 33 Terminal 1 Figure 9 2 M Series RTSI Pinout M Series User Manual 9 4 ni com Chapter 9 Digital Routing and Clock Generation Table 9 1 RTSI Signal Descriptions RTSI Bus Signal Terminal RTSI 7 34 RTSI 6 32 RTSI 5 30 RTSI 4 28 RTSI 3 26 RTSI 2 24 RTSI 1 22 RTSIO 20 Not Connected Do not connect 1 18 signals to these terminals D GND 19 21 23 25 27 29 31 33 Using RTSI as Outputs RTSI lt 0 7 gt are bidirectional terminals As an output you can drive any of the following signals to any RTSI terminal e al StartTrigger e ai ReferenceTri
79. from a digital source The action can affect the following e Analog input acquisition e Analog output generation e Counter behavior e Digital waveform acquisition and generation Triggering with an Analog Source Some M Series devices can generate a trigger on an analog signal To find your device triggering options refer to the specifications document for your device Figure 11 2 shows the analog trigger circuit Analog Input Channels e PGIA ADC APFI lt 0 1 gt m gt Al Circuitry Analog Comparison Analog Event Mux Trigger gt AO Circuitry Detection Analog Trigger Circuitry Output gt Counter Circuitry Figure 11 2 Analog Trigger Circuit You must specify a source and an analog trigger type The source can be either an APFI lt 0 1 gt terminal or an analog input channel APFI lt 0 1 gt Terminals M Series User Manual When you use either APFI lt 0 1 gt terminal as an analog trigger you should drive the terminal with a low impedance signal source less than 1 kQ source impedance If APFI lt 0 1 gt are left unconnected they are susceptible to crosstalk from adjacent terminals which can cause false triggering Note that the APFI lt 0 1 gt terminals also can be used for other functions such as the AO External Reference input as described in the AO Offset and AO Reference Selection section of Chapter 5 Analog Outpu
80. generated by dividing down the Sample Clock Timebase the analog output generation is timed from the output of the UI counter The signal Sample Clock Timebase can be an external signal When the analog output timing engine operates in this mode it is assumed that the source signal for the Sample Clock timebase is a free running clock so the Sync Sample Clock Timebase is the inverted version of Sample Clock Timebase Configuring the analog output timing engine for rising edge operation will cause the external signals to be synchronized on the falling edge of the Sample Clock Timebase which corresponds to the rising edge of Sync Sample Clock Timebase B 26 ni com Appendix B Timing Diagrams sai AE i t Sync Sample Clock Timebase l i A i E KA gt Sample Clock Timebase A Figure B 25 Sample Clock Timebase and the Sync Sample Clock Timebase Timing Diagram Table B 14 Sample Clock Timebase and the Sync Sample Clock Timebase Timing Timing From To Min ns Max ns ty Signal_i Sample Clock 2 4 9 3 Timebase ts Signal_i Sync Sample 2 4 9 3 Clock Timebase START Trigger As an output the START Trigger is routed as an asynchronous pulse The actual signal that gets routed is the Selected START signal so there is no synchronous delay involved Selected Start Signal_i D Q To Internal Logic Sync Sample Clock Timebase
81. generation It is a first in first out FIFO memory buffer between the computer and the DACs It allows you to download the points of a waveform to your M Series device without host computer interaction AO Sample Clock The AO Sample Clock signal reads a sample from the DAC FIFO and generates the AO voltage AO Offset and AO Reference Selection AO Offset and AO Reference Selection signals allow you to change the range of the analog outputs AO Offset and AO Reference Selection AO Offset and AO Reference selection allow you to set the AO range The AO range describes the set of voltages the device can generate The digital codes of the DAC are spread evenly across the AO range So if the range is smaller the AO has better resolution that is the voltage output difference between two consecutive codes is smaller Therefore the AO is more accurate The AO range of a device is all of the voltages between AO Offset AO Reference and AO Offset AO Reference The possible settings for AO Reference depend on the device model For models not described below refer to the specifications for your device NI 622x Only On NI 622x devices the AO Offset is always 0 V AO GND The AO Reference is always 10 V So for NI 622x devices the AO Range 10 V M Series User Manual 5 2 ni com Chapter 5 Analog Output NI 625x Only On NI 625x devices the AO Offset is always 0 V AO GND The AO Reference of each analog output
82. gt gt gt gt AS PO 4 D GND PO 1 P0 6 D GND 5 V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5 V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 CONNECTOR 0 Al 0 15 O TERMINAL 68 TERMINAL 34 TERMINAL 35 TERMINAL 1 e Figure A 1 NI 6220 Pinout Table A 1 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 O National Instruments Corporation M Series User Manual Appendix Device Specific Information Table A 1 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 ik Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6220 Specifications Refer to the NI 622x Specifications for more detailed information about the NI 6220 device NI 6220 Accessory and Cabling Options M Series User Manual This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI 6220
83. high enough the resulting reading of channel 1 can be partially affected by the voltage on channel 0 This effect is referred to as ghosting 4 8 ni com Chapter 4 Analog Input If your source impedance is high you can decrease the scan rate to allow the NI PGIA more time to settle Another option is to use a voltage follower circuit external to your DAQ device to decrease the impedance seen by the DAQ device Refer to the KnowledgeBase document How Do I Create a Buffer to Decrease the Source Impedance of My Analog Input Signal by going to ni com info and entering the info code rdbbis Use Short High Quality Cabling Using short high quality cables can minimize several effects that degrade accuracy including crosstalk transmission line effects and noise The capacitance of the cable also can increase the settling time National Instruments recommends using individually shielded twisted pair wires that are 2 m or less to connect AI signals to the device Refer to the Connecting Analog Input Signals section for more information Carefully Choose the Channel Scanning Order Avoid Switching from a Large to a Small Input Range Switching from a channel with a large input range to a channel with a small input range can greatly increase the settling time Suppose a 4 V signal is connected to channel 0 and a mV signal is connected to channel 1 The input range for channel 0 is 10 V to 10 V and the input range of channel 1 is 200 mV
84. is typically configured so that a low to high leading edge can clock external AI multiplexers indicating when the input signal has been sampled and can be removed Al Start Trigger Signal Use the AI Start Trigger ai StartTrigger signal to begin a measurement acquisition A measurement acquisition consists of one or more samples If you do not use triggers begin a measurement with a software command Once the acquisition begins configure the acquisition to stop e When a certain number of points are sampled in finite mode e After a hardware reference trigger in finite mode e With a software command in continuous mode An acquisition that uses a start trigger but not a reference trigger is sometimes referred to as a posttriggered acquisition Using a Digital Source To use ai StartTrigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt 0 15 gt RTSI lt 0 7 gt National Instruments Corporation 4 35 M Series User Manual Chapter 4 Analog Input e Counter n Internal Output e PXISTAR The source also can be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information You also can specify whether the measurement acquisition begins on the rising edge or falling edge of ai StartTrigger Using an Analog Source When you use an analog trigger source the acquis
85. later supports SCXI in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold National Instruments Corporation A 17 M Series User Manual Appendix M Series User Manual Device Specific Information You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCX7 Advisor available by going to ni com info and entering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single e
86. leads travel through noisy environments e Two analog input channels AI and AI are available for the signal DIFF signal connections reduce noise pickup and increase common mode noise rejection DIFF signal connections also allow input signals to float within the common mode limits of the NI PGIA Refer to the Using Differential Connections for Floating Signal Sources section for more information about differential connections When to Use Non Referenced Single Ended NRSE Connections with Floating Signal Sources Only use NRSE input connections if the input signal meets the following conditions e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the National Instruments Corporation 4 15 M Series User Manual Chapter 4 Analog Input result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential differe
87. on your device internally generates ai SampleClock unless you select some external source ai StartTrigger starts this counter and either software or hardware can stop it once a finite acquisition completes When using an internally generated ai SampleClock you also can specify a configurable delay from ai StartTrigger to the first ai SampleClock pulse By default this delay is set to two ticks of the ai SampleClockTimebase signal When using an externally generated ai SampleClock you must ensure the clock signal is consistent with respect to the timing requirements of ai ConvertClock Failure to do so may result in ai SampleClock pulses that are masked off and acquisitions with erratic sampling intervals Refer to AI Convert Clock Signal for more information about the timing requirements between ai ConvertClock and ai SampleClock Figure 4 16 shows the relationship of ai SampleClock to ai StartTrigger ai SampleClockTimebase JUUUUUL ai StartTrigger AO ai SampleClock i Delay From Start Trigger Figure 4 16 ai SampleClock and ai StartTrigger Al Sample Clock Timebase Signal M Series User Manual You can route any of the following signals to be the AI Sample Clock Timebase ai SampleClockTimebase signal 20 MHz Timebase 100 kHz Timebase e PXICLKIO e RTSI lt 0 7 gt e PFI lt 0 15 gt e PXI STAR e Analog Comparison Event an analog trigger 4 30 ni com Chapter 4 Analog Input ai SampleClockT
88. options for M Series devices with two 68 pin connectors such as the NI 6284 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and later supports SCXI in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold M Series User Manual A 92 ni com Appendix Device Specific Information You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by goin
89. physical process Referenced Single Ended configuration All measurements are made with respect to a common reference measurement system or a ground Also called a grounded measurement system Real Time System Integration Real Time System Integration bus The National Instruments timing bus that connects DAQ devices directly by means of connectors on top of the devices for precise synchronization of functions National Instruments Corporation G 15 M Series User Manual Glossary sample counter scan scan interval scan rate SCC SCXI sensor signal conditioning signal source signals M Series User Manual Seconds Samples The clock that counts the output of the channel clock in other words the number of samples taken On devices with simultaneous sampling this counter counts the output of the scan clock and hence the number of scans One or more analog or digital input samples Typically the number of input samples in a scan is equal to the number of channels in the input group For example one pulse from the scan clock produces one scan which acquires one new sample from every analog input channel in the group Controls how often a scan is initialized is regulated by the AI Sample Clock signal Reciprocal of the scan interval Signal Conditioning Carriers A compact modular form factor for signal conditioning modules Signal Conditioning eXtensions for Instrumentation The National I
90. products PCMCIA cards and devices such as the DAQPad 1200 which connects to your computer parallel port are all examples of DAQ devices SCXI modules are distinct from devices with the exception of the SCXI 1200 which is a hybrid G 6 ni com DIFF differential input digital I O digital signal digital trigger DIO DMA DMA controller chip driver E E Series edge detection EEPROM National Instruments Corporation G 7 Glossary Differential mode An analog input mode consisting of two terminals both of which are isolated from computer ground whose difference is measured An input circuit that actively responds to the difference between two terminals rather than the difference between one terminal and ground Often associated with balanced input circuitry but also may be used with an unbalanced source The capability of an instrument to generate and acquire digital signals Static digital I O refers to signals where the values are set and held or rarely change Dynamic digital I O refers to digital systems where the signals are continuously changing often at multi MHz clock rates A representation of information by a set of discrete values according to a prescribed law These values are represented by numbers A TTL level signal having two discrete levels A high and a low level Digital input output Direct Memory Access A method by which data can be transferred to from computer memory
91. signal conditioning devices cables that connect the various devices to the accessories the M Series device programming software and PC The following sections cover the components of a typical DAQ system ii A 0 ME Signal Cables and DAQ DAQ Personal Conditioning Accessories Hardware Software Computer Sensors and Transducers Figure 2 1 Components of a Typical DAQ System DAQ Hardware DAQ hardware digitizes signals performs D A conversions to generate analog output signals and measures and controls digital 1 O signals Figure 2 2 features components common to all M Series devices National Instruments Corporation 2 1 M Series User Manual Chapter 2 DAQ System Overview a Analog Input Analog Output E Digital 2 Routing Bus LE 8 Digital 1 O and Clock Interface Bus m Generation Counters RTSI ul PFI Figure 2 2 General M Series Block Diagram DAQ STC2 and DAQ 6202 The DAQ STC2 and DAQ 6202 implement a high performance digital engine for M Series data acquisition hardware Some key features of this engine include the following M Series User Manual Flexible AI and AO sample and convert timing Many triggering modes Independent AI AO DI and DO FIFOs Generation and routing of RTSI signals for multi device
92. signal to sample the P0 lt 0 31 gt terminals and store the result in the DI waveform acquisition FIFO M Series devices do not have the ability to divide down a timebase to produce an internal DI Sample Clock for digital waveform acquisition Therefore you must route an external signal or one of many internal signals from another subsystem to be the DI Sample Clock For example you can correlate digital and analog samples in time by sharing your AI Sample Clock or AO Sample Clock as the source of your DI Sample Clock To sample a digital signal independent of an AI AO or DO operation you can configure a counter to generate the desired DI Sample Clock or use an external signal as the source of the clock If the DAQ device receives a di SampleClock when the FIFO is full it reports an overflow error to the host software Using an Internal Source To use di SampleClock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals e AI Sample Clock e AI Convert Clock e AO Sample Clock e Counter n Internal Output e Frequency Output DI Change Detection Output Several other internal signals can be routed to di SampleClock through RTSI Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information Using an External Source You can route any of the following signals as di SampleClock e PFI lt 0 15 gt e RTSI lt 0 7 gt
93. signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors National Instruments Corporation A 55 M Series User Manual Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to c
94. software or in hardware When implemented in software LabVIEW all data is collected transferred into system memory and analyzed for the trigger condition When analog triggering is implemented in hardware no data is transferred to system memory until the trigger condition has occurred Analog output G 2 ni com AO 0 AO 1 AO 2 AO 3 AO GND application arm ASIC asynchronous block diagram BNC buffer National Instruments Corporation G 3 Glossary Analog channel 0 output signal Analog channel output signal Analog channel 2 output signal Analog channel 3 output signal Analog output ground signal A software program that creates an end user function The process of getting an instrument ready to perform a function For example the trigger circuitry of a digitizer is armed meaning that it is ready to start acquiring data when an appropriate trigger condition is met Application specific integrated circuit A proprietary semiconductor component designed and manufactured to perform a set of specific functions for a specific customer 1 Hardware A property of an event that occurs at an arbitrary time without synchronization to a reference clock 2 Software A property of a function that begins an operation and returns prior to the completion or termination of the operation Bit One binary digit either 0 or 1 Byte Eight related bits of data an eight bit binary number Also use
95. synchronization Generation and routing of internal and external timing signals Two flexible 32 bit counter timer modules with hardware gating Digital waveform acquisition and generation Static DIO signals True 5 V high current drive DO DI change detection PLL for clock synchronization Seamless interface to signal conditioning accessories PCI PXI interface Independent scatter gather DMA controllers for all acquisition and generation functions 2 2 ni com Chapter 2 DAQ System Overview Calibration Circuitry The M Series analog inputs and outputs have calibration circuitry to correct gain and offset errors You can calibrate the device to minimize AI and AO errors caused by time and temperature drift at run time No external circuitry is necessary an internal reference ensures high accuracy and stability over time and temperature changes Factory calibration constants are permanently stored in an onboard EEPROM and cannot be modified When you self calibrate the device software stores new constants in a user modifiable section of the EEPROM To return a device to its initial factory calibration settings software can copy the factory calibration constants to the user modifiable section of the EEPROM Refer to the NJ DAQmx Help or the LabVIEW 8 x Help for more information about using calibration constants For a detailed calibration procedure for M Series devices refer to the E S M B Series Calibration Procedure for NI DAQmx by
96. the input signal with the gain for the new input range Settling time refers to the time it takes the NI PGIA to amplify the input signal to the desired accuracy before it is sampled by the ADC The specifications document for your DAQ device lists its settling time M Series devices are designed to have fast settling times However several factors can increase the settling time which decreases the accuracy of your measurements To ensure fast settling times you should do the following in order of importance e Use low impedance sources e Use short high quality cabling e Carefully choose the channel scanning order e Avoid scanning faster than necessary The following sections contain more information about these factors Use Low Impedance Sources M Series User Manual To ensure fast settling times your signal sources should have an impedance of lt 1 KQ Large source impedances increase the settling time of the NI PGIA and so decrease the accuracy at fast scanning rates Settling times increase when scanning high impedance signals due to a phenomenon called charge injection Multiplexers contain switches usually made of switched capacitors When one of the channels for example channel 0 is selected in a multiplexer those capacitors accumulate charge When the next channel for example channel 1 is selected the accumulated charge leaks backward through channel 1 If the output impedance of the source connected to channel 1 is
97. to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices O National Instruments Corporation A 41 M Series User Manual Appendix Device Specific Information RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI PCI Express devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are requi
98. ton te ne ne 8 4 VO Protection ne e Nae tn RE Rent ne Nas RA aetna nu 8 6 Programmable Power Up States 8 6 Chapter 9 Digital Routing and Clock Generation Clock Routing LS in ne te eres M Ae nies aaa et ln te tent 9 1 80 MHZ Timebase sas este nette ms sent 9 2 20 MHZ Timebase cuida tentent ann RS dt ts due 9 2 LOO KAZ Time Das e a en Mr tn Ml R 9 2 External Reference Clock orri nas inienn na EAREN SEA EEEE RE 9 2 10 MHZ Reference Clock evi ii que 9 3 Synchronizing Multiple Devices ss 9 3 Real Time System Integration RTSI ss 9 4 RTSI Connector Pinout camila 9 4 Using RIST as Outputs incas at ii age 9 5 Using RTSI Terminals as Timing Input Signals 9 6 RT SL BU tet S ET Le re ge md adas 9 6 PXI Clock and Trigger Signals ss 9 8 PXI CIRM Es nn A en eee 9 8 PITH GS ers LENS eit lab Aah rte NE nn nn NES ai Ne ates 9 8 PXI STAR TB tidad 9 8 PXESTAR Bilters ui add 9 9 O National Instruments Corporation xiii M Series User Manual Contents Chapter 10 Bus Interface DMA Controllers and USB Signal Streams 10 1 PXI COnsideratiOus pa He ot E Ravens ce Suc aly ee ice vers pwede ms 10 2 PXI Clock and Trigger Signals ss 10 2 PXI and PXTEXPI SS 2 sue tv re hr redemande 10 2 Using PXI with CompactPCI ss 10 3 Data Transfer Mods ide rene eee iia
99. up to 25 ns On the 2 55 ms setting the jitter is up to 10 025 us When a PFI input is routed directly to RTSL or a RTSI input is routed directly to PFI the M Series device does not use the filtered version of the input signal Refer to the KnowledgeBase document Digital Filtering with M Series for more information about digital filters and counters To access this KnowledgeBase go to ni com info and enter the info code rddfms National Instruments Corporation 9 7 M Series User Manual Chapter 9 Digital Routing and Clock Generation PXI Clock and Trigger Signals 3 Note PXI clock and trigger signals are only available on PXI devices PXI_CLK10 PXI Triggers PXI_STAR Trigger M Series User Manual PXI_CLK10 is a common low skew 10 MHz reference clock for synchronization of multiple modules in a PXI measurement or control system The PXI backplane is responsible for generating PXI_CLK10 independently to each peripheral slot in a PXI chassis A PXI chassis provides eight bused trigger lines to each module in a system Triggers may be passed from one module to another allowing precisely timed responses to asynchronous external events that are being monitored or controlled Triggers can be used to synchronize the operation of several different PXI peripheral modules On M Series devices the eight PXI trigger signals are synonymous with RTSI lt 0 7 gt Note that in a PXI chassis with more than eight slots the PXI t
100. used to generate the signal that will actually cause the ADC to do a conversion p_AL Convert This signal can be an internal or external timebase that will be divided by the SI2 counter or can be an external Convert Clock signal Sync Convert Clock Timebase is a signal related to Convert Clock Timebase that is used to synchronize external signals before they are used by circuits running from Convert Clock Timebase Sample Clock Timebase is the source for the SI counter and can be used to generate the sample timing Each Sample Clock in turn triggers the generation of one or more converts This signal can be an internal or external timebase Sync Sample Clock Timebase is a signal related to Sample Clock Timebase that is used to synchronize external signals before they are used by circuits running from Sample Clock Timebase Start is the signal that starts the analog input timing engine This signal can come from external signals a software command or internal sources Selected Start is the signal chosen to be the Start before 1t is synchronized just after the selection mux A Reference Trigger is a trigger that can stop the Al timing engine If the Reference Trigger 1s enabled the Al timing engine will stop acquiring data once it sees a valid event on the Reference Trigger and it has acquired the posttrigger number of samples This signal can come from external signals a software command or internal sources The Selected Refe
101. 0 1 gt to provide the AO Reference You can route the output of one of the AO lt 0 3 gt signals to be the AO Reference for a different AO lt 0 3 gt signal For example AO 0 can be routed to be the AO Reference of AO 1 This route is done on the device no external connections are required You cannot route an AO channel to be its own reference The AO Reference can be a positive or negative voltage If AO Reference is a negative voltage the polarity of the AO output is inverted Minimizing Glitches on the Output Signal When you use a DAC to generate a waveform you may observe glitches on the output signal These glitches are normal when a DAC switches from one voltage to another it produces glitches due to released charges The largest glitches occur when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal Visit ni com support for more information about minimizing glitches Analog Output Data Generation Methods When performing an analog output operation you either can perform software timed or hardware timed generations Hardware timed generations can be non buffered or buffered Software Timed Generations M Series User Manual With a software timed generation software controls the rate at which data is generated Software sends a separate command to the hardware to initiate each
102. 0 as shown in Figure 7 14 Assume this signal to measure has frequency F1 Configure Counter 0 to generate a single pulse that is the width of N periods of the source input signal 7 12 ni com Chapter 7 Counters Signal to SOURCE OUT Measure F1 COUNTER 0 Signal of Known A SOURCE OUT Frequency F2 COUNTER 1 L p GATE 0 1 2 3 N CTR_0_ SOURCE U U U U UI U L Signal to Measure CTR_0_OUT CTR_1_GATE Mierval to Measure CTR_1_SOURCE JUUUUUUUUUUUUUUULN Figure 7 14 Method 3 Then route the Counter 0 Internal Output signal to the Gate input of Counter 1 You can route a signal of known frequency F2 to the Counter 1 Source input F2 can be 80MHzTimebase For signals that might be slower than 0 02 Hz use a slower known timebase Configure Counter 1 to perform a single pulse width measurement Suppose the result is that the pulse width is J periods of the F2 clock From Counter 0 the length of the pulse is N F1 From Counter 1 the length of the same pulse is J F2 Therefore the frequency of F1 is given by F1 F2 N J Choosing a Method for Measuring Frequency The best method to measure frequency depends on several factors including the expected frequency of the signal to measures the desired accuracy how many counters are available and how long the measurement can take e Method 1 uses only one counter It is a good method for many applications However
103. 23 Single Pulse Generation with Start Trigger Retriggerable Single Pulse Generation The counter can output a single pulse in response to each pulse on a hardware Start Trigger signal The pulses appear on the Counter n Internal Output signal of the counter You can route the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the beginning of each pulse You also can specify the pulse width The delay and pulse width are measured in terms of a number of active edges of the Source input The counter ignores the Gate input while a pulse generation is in progress After the pulse generation is finished the counter waits for another Start Trigger signal to begin another pulse generation Figure 7 24 shows a generation of two pulses with a pulse delay of five and a pulse width of three using the rising edge of Source GATE HL Start Trigger SOURCE UUU OUT Figure 7 24 Retriggerable Single Pulse Generation For information about connecting counter signals refer to the Default Counter Timer Pinouts section National Instruments Corporation 7 21 M Series User Manual Chapter 7 Counters Pulse Train Generation M Series User Manual Continuous Pulse Train Generation This function generates a train of pulses with progra
104. 4 2 lowpass filter 4 4 MUX 4 1 range 4 2 sampling channels with AI Sample Clock and AI Convert Clock C 2 timing diagrams B 1 timing signals 4 25 triggering 4 13 troubleshooting C 1 analog input data acquisitions 4 11 analog input range 4 2 analog input signals 4 25 AI Convert Clock 4 31 AI Convert Clock Timebase 4 35 AI Hold Complete Event 4 35 AI Pause Trigger 4 38 AI Reference Trigger 4 36 AI Sample Clock 4 28 AI Sample Clock Timebase 4 30 Al Start Trigger 4 35 analog output 5 1 circuitry 5 1 connecting signals 5 6 data generation methods 5 4 fundamentals 5 1 M Series User Manual getting started with applications in software 5 12 glitches on the output signal 5 4 offset 5 2 reference selection 5 2 timing diagrams B 23 timing signals 5 7 triggering 5 6 troubleshooting C 3 analog output data generation 5 4 analog output signals 5 7 AO Pause Trigger 5 9 AO Sample Clock 5 10 AO Sample Clock Timebase 5 12 AO Start Trigger 5 8 analog output trigger signals 5 6 analog source triggering 11 2 analog to digital converter 4 2 analog trigger 11 2 accuracy 11 7 actions 11 3 improving accuracy 11 7 analog window triggering 11 6 ANSI C documentation xxi AO FIFO 5 2 AO offset 5 2 AO offset and AO reference selection settings 5 2 AO Pause Trigger signal 5 9 AO reference selection 5 2 AO Sample Clock 5 2 Timebase signal 5 12 AO sample clock signal 5 10 AO
105. 5 PFI 10 Al 9 5 I9 P0 4 69 22 Al GND S 86 D GND AI GND 6 19 P0 5 70 K 23 Al6 SI 87 PFI 11 Al 2 7S PO6 71 18 24 Al 14 88 D GND Al 10 8 PO 7 72 25 AI GND 89 PFI 12 AI GND 9 PFIO 73 26 Al7 90 D GND Al 3 10 PFI1 74 S 27 Al15 SI 91 PFI 13 Al 11 11 PFI2 75 K 28 AI GND S 92 D GND AI GND 12 PFI3 76 K 29 APFI0 93 PFI 14 AI SENSE 13 PFI4 77 8 30 Al GND 94 D GND Al GND 14 PFI5 78 31 AO1 95 PFI 15 AO 0 15 AO GND PFI6 79 IX 96 5V AOGND 16 PFI7 80 S S96 z es N Figure A 9 USB 6251 Pinout Table A 9 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 81 PFI 8 CTR 0 GATE 83 PFI 9 CTR 0 AUX 85 PFI 10 CTR 0 OUT 89 PFI 12 National Instruments Corporation A 43 M Series User Manual Appendix Device Specific Information Table A 9 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTRO A 81 PFI 8 CTROZ 83 PFI 9 CTR OB 85 PFI 10 CTR 1 SRC 76 PFI 3 CTR 1 GATE 77 PFI 4 CTR 1 AUX 87 PFI 11 CTR 1 OUT 91 PFI 13 CTR1A 76 PFI 3 CTR1Z 77 PFI 4 CTR 1 B 87 PFI 11 3 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help
106. 51 Mass Termination USB 6251 Mass Termination Pinout Figure A 11 shows the pinout of the USB 6251 Mass Termination device For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 46 ni com Appendix Device Specific Information Fes AI 8 AIO AI 1 AI GND AI GND AI9 AI 10 Al2 Al3 Al GND AI GND Al 11 Al4 AI SENSE Al GND Al 12 Al 13 Al5 Al6 AI GND AI GND Al 14 Al 15 AI7 AO 0 AI GND AO 1 AO GND APFIO AO GND P0 4 D GND D GND P0 0 PO PO 5 P0 6 D GND D GND P0 2 5 V PO 7 D GND P0 3 D GND PFI 11 P2 3 PFI 0 P1 0 PFI 10 P2 2 PFI 1 P1 1 D GND D GND PFI 2 P1 2 5 V PFI 3 P1 3 D GND PFI 4 P1 4 PFI 5 P1 5 PFI 13 P2 5 PFI 6 P1 6 PFI 15 P2 7 D GND PFI 7 P1 7 PFI 9 P2 1 PFI 8 P2 0 PFI 12 P2 4 D GND PFI 14 P2 6 D GND CONNECTOR 0 Al 0 15 TERMINAL 68 TERMINAL 35 cp TERMINAL 34 TERMINAL 1 Figure A 11 USB 6251 Mass Termination Pinout Table A 11 Default NI DAQmx Counter Timer Pins Counter Timer S
107. 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 89 M Series User Manual Appendix Device Specific Information NI 6264 NI 6284 Pinout Figure A 22 shows the pinout of the NI 6284 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 90 ni com Appendix Device Specific Information AIO AI GND AI9 Al2 Al GND Al 11 Al SENSE Al 12 Al5 AI GND Al 14 Al7 Al GND NC NC D GND PO 0 PO 5 D GND P0 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND gt E gt E gt Ba gt E gt Oe gt ES Q Z O0 CONNECTOR 0 Al 0 15 CONNECTOR 1 Al 16 31 15 TERMINAL 68 TERMINAL35 NC TERMINAL 34 TERMINAL 1 APFIO PO 4 D GND PO 1 PO 6 D GND 5 V D GND D GND TERMINAL 35 TERMINAL 68 PFI 0 P1 0 PRIME D GND 5 V D GND PEIISIPIFS PFI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 TERMINAL 1 TERMINAL 34
108. 7 0 National Instruments Corporation B 31 M Series User Manual Appendix B Timing Diagrams Sample Clock The rising edge of the Sample Clock is output synchronous to the Sample Clock Timebase It can be calculated by adding the Sample Clock Timebase insertion to the delay in Table B 21 The exported Sample Clock signal is active low each falling edge representing a conversion Routing Logic m RTSI PFI Internal Logic gt D Sample Clock Timebase gt gt Figure B 34 Sample Clock Path Sample Clock Timebase ha RTSI PFI Terminal Figure B 35 Sample Clock Delay Timing Diagram Table B 21 Sample Clock Delay Timing Timing Description Line From To Min ns Max ns tia AO Sample PFI 9 7 10 7 31 1 34 3 Clock AO Sample RTSI 8 8 9 1 21 3 21 7 Clock Digital 1 0 Timing Diagrams M Series User Manual This section describes the timing delays and requirements of digital waveform acquisitions and digital waveform generations B 32 ni com Appendix B Timing Diagrams Digital Waveform Acquisition Timing To describe digital waveform acquisition timing delays and requirements refer to the circuitry shown in Figure B 36 In the figure PO PFI RTSI and PXI_STAR represent signals at connector pins of the M Series device The other named signals represent internal signals
109. 8 Pause Trigger Setup and Hold Timing Timing Parameter Min ns Max ns to Setup 1 5 2n ti Hold 0 gt Input Timing Verification For external triggers the timing conditions that need to be verified are as follows Tsetup Ext Tinsertion CIK Tpetay Clk Tinsertion Trigger Tpelay Trigger gt DFF getup THotd Ext Tinsertion Trigger Tpelay Trigger a Tinsertion CIK Tpelay Clk gt DFFyo1a For setup calculations use the maximum timing parameters For hold calculations use the minimum timing parameters In order to account for the worst case skew between different input terminals use the range given in the input delay tables in the Input Timing section in a way that provides the most conservative results e For setup calculations use Tinsertion Trigger gt Tinsertion CIK For hold calculations use Tinsertion CIK gt Tinsertion Trigger For an example of calculating setup and hold refer to the Example of the General Case section The analog output timer has three possible trigger outputs START Trigger Pause Trigger and Sample Clock The delays presented in this section assume a 200 pF load on PFI lines and a 50 pF load on RTSI lines Actual delays will vary with the actual load The two numbers given for each condition represent the variation from the best case and worst case terminals M Series User Manual Appendix B Timing Diagrams START Trigger As an output the S
110. 9 66 32 Al GND P0 25 3 37 P0 24 AI 2 65 31 Alto a DGND 4 38 Po 23 AI GND 64 30 AI13 Ca Es PO 22 5 39 Po 31 Al 11 63 29 Al GND 57 5 PO 21 6 40 Po 29 Al SENSE 62 28 Al4 us mE DGND 7 41 P0 20 AI 12 61 27 AI GND a gt gs 5V 8 42 Po 19 Al5 60 26 A113 o 9 DGND 9 43 Po 18 AI GND 59 25 Al6 Po 17 10144 DGND AI 14 58 24 AI GND P0 16 11 45 Po 26 AI7 57123 Al 15 TERMINAL 68 H TERMINAL35 D GND 12 46 Po 27 AI GND 56 22 NC DGND 13 47 P0 11 NC ssT211 NC TERMINAL 34 TERMINAL 1 By 141481 Po15 NC 54 20 APFIO DGND 15 49 Po 10 D GND 53 19 Po 4 Po i4 16 50 DGND P0 0 52 18 DGND PO 9 17 51 P0 13 P0 5 51 17 Po D GND 18 52 Pog D GND 50 16 Po 6 Po 12 19 53 D GND P0 2 49 15 D GND APFI1 20 54 NC PO 7 48 14 SM TERMINAL 1 TERMINAL 34 NC 21 55 NC P0 3 47 13 D GND NC 22 56 AI GND PFI11 P2 3 46 12 D GND TERMINAL 35 F TERMINAL 68 Al31 23 57 A123 PFI 10 P2 2_ 45 11 PFI0 P1 0 AI GND 24 58 A1 30 D GND 44 10 PFI1 P1 1 AI 22 25 59 AI GND PFI 2 P1 2 43 9 DGND AI 29 26 60 A1 21 PFI 3 P1 3 42 8 5V AI GND 27 61 A128 PFI 4 P1 4 41 7 DGND AI 20 28 62 Al SENSE 2 PFI 13 P2 5 40 6 PFI5 P1 5 AI GND 29 63 A1 27 PFI15 P2 7 39 5 PFI6 P1 6 Al 19 30 64 Al GND PFI 7 P1 7 38 4 DGND Al 26 31 65 A118 PFI 8 P2 0 37 3 PFI9 P2 1
111. A to Counter n B 25 0 t20 Delay from Counter n B to Counter n A 25 0 a signal driving a PFI RTSI or PXI_STAR pin when that signal is internally routed to Counter n A The timings in this table are measured at the pin of the M Series device For example t 4 specifies the minimum period of Clock Generation Timing Diagrams Table B 36 shows delays for generating different clocks described in the Clock Routing section of Chapter 9 Digital Routing and Clock Generation from the onboard 80 MHz oscillator Onboard 80 MHz Oscillator 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase N Figure B 51 Generating Different Clocks from the Onboard 80 MHz Oscillator M Series User Manual B 48 ni com Appendix B Timing Diagrams Table B 36 Generating Different Clocks from the Onboard 80 MHz Oscillator Timing From To Min ns Max ns ty Onboard 80 MHz Oscillator 80 MHz Timebase 4 0 9 0 b 80 MHz Timebase 20 MHz Timebase 0 5 2 5 t3 80 MHz Timebase 100 kHz Timebase 1 0 5 0 Table B 37 shows delays for generating different clocks using an External Reference Clock and the PLL RTSI lt 0 7 gt i STAR_TRIG i PXI_CLK10 Reference Clock 80 MHz Timebase PLL 20 MHz Timebase PLL gt lt
112. AQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 3 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6255 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6255 device NI 6255 Accessory and Cabling Options M Series User Manual This section describes some cable and accessory options for the NI 6255 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your NI 6255 device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your NI 6255 device to control SCXI Connector 1 cannot be used to control SCXI SCC SCC provides portable modular signal conditioning to your DAQ system To connect your NI 6255 device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable A 60 ni com Appendix Device Specific Information Use Connector 0 of your NI 6255 device to control an SCC module carrier Connector 1 cannot be used with SCCs R
113. Analog Comparison Event PXI_CLK10 F4 PXI_STAR Analog Comparison Event PFI RTSI i leClock Ctr n Internal Output avoampleciee ai SampleClock SW Pulse Timebase Programmable Clock Divider PFI RTSI ai ConvertClock Ctr n Internal Output Le ai ConvertClock Timebase Programmable hd Clock Divider M Series User Manual Figure 4 12 Analog Input Timing Options M Series devices use ai SampleClock and ai ConvertClock to perform interval sampling As Figure 4 13 shows ai SampleClock controls the sample period which is determined by the following equation 1 Sample Period Sample Rate Channel 0 Channel 1 gt 3 Convert Period Sample Period gt Figure 4 13 Interval Sampling ai ConvertClock controls the Convert Period which is determined by the following equation 1 Convert Period Convert Rate 4 26 ni com Chapter 4 Analog Input NI DAQm x chooses the default convert rate to allow for the maximum settling time between conversions Typically this rate is the sampling rate for the task multiplied by the number of channels in the task ays Note The sampling rate is the fastest you can acquire data on the device and still achieve accurate results For example if an M Series device has a sampling rate of 250 kS s this sampling rate is aggregate one channel at 250 kS s or two channe
114. C 1 ground reference connections checking C 1 ground reference settings 4 2 4 5 analog input 4 5 ground referenced signal sources connecting 4 20 description 4 20 using in differential mode 4 23 using in NRSE mode 4 24 when to use in differential mode 4 21 when to use in NRSE mode 4 21 when to use in RSE mode 4 22 H hardware 1 1 2 1 hardware timed acquisitions 4 11 hardware timed generations 5 5 help technical support E 1 hysteresis analog edge triggering with 11 4 I O connector 3 1 NI 6220 pinout A 2 NI 6250 pinout A 33 NI 6254 pinout A 52 NI 6255 pinout A 58 NI 6221 37 pin pinout A 12 16221 68 pin pinout A 7 NI 6224 pinout A 15 NI 6225 pinout A 21 NI 6229 pinout A 27 NI 6280 pinout A 80 NI 6281 pinout A 85 NI 6284 pinout A 90 NI 6289 pinout A 96 PCI PCle PXI 6251 pinout A 38 Z M Series User Manual Index PCI PCle PXI 6259 pinout A 64 USB 6251 Mass Termination pinout A 46 USB 6251 pinout A 43 USB 6259 Mass Termination pinout A 74 USB 6259 pinout A 70 I O protection 6 7 8 6 improving analog trigger accuracy 11 7 input signals using PFI terminals as 8 2 using RTSI terminals as 9 6 input timing analog input B 4 insertion of grounded channels between signal channels 4 10 installation hardware 1 1 NI DAQ 1 1 other software 1 1 troubleshooting C 3 instrument drivers NI resources E 1 instrumentation amplifier 4 2 interface bus 10 1 int
115. DAQ M Series M Series User Manual NI 622x NI 625x and NI 628x Devices April 2006 7 NATIONAL 371022F 01 INSTRUMENTS Worldwide Technical Support and Product Information ni com National Instruments Corporate Headquarters 11500 North Mopac Expressway Austin Texas 78759 3504 USA Tel 512 683 0100 Worldwide Offices Australia 1800 300 800 Austria 43 0 662 45 79 90 0 Belgium 32 0 2 757 00 20 Brazil 55 11 3262 3599 Canada 800 433 3488 China 86 21 6555 7838 Czech Republic 420 224 235 774 Denmark 45 45 76 26 00 Finland 385 0 9 725 725 11 France 33 0 1 48 14 24 24 Germany 49 0 89 741 31 30 India 91 80 41190000 Israel 972 0 3 6393737 Italy 39 02 413091 Japan 81 3 5472 2970 Korea 82 02 3451 3400 Lebanon 961 0 1 33 28 28 Malaysia 1800 887710 Mexico 01 800 010 0793 Netherlands 31 0 348 433 466 New Zealand 0800 553 322 Norway 47 0 66 90 76 60 Poland 48 22 3390150 Portugal 351 210 311 210 Russia 7 095 783 68 51 Singapore 1800 226 5886 Slovenia 386 3 425 4200 South Africa 27 0 11 805 8197 Spain 34 91 640 0085 Sweden 46 0 8 587 895 00 Switzerland 41 56 200 51 51 Taiwan 886 02 2377 2222 Thailand 662 278 6777 United Kingdom 44 0 1635 523545 For further support information refer to the Technical Support and Professional Services appendix To comment on National Instruments documentation refer to the National Instruments Web site at ni com info and enter the info code feedback 2004 2006 National Instruments Cor
116. DI change detection 6 8 digital waveform generation 6 5 M Series User Manual Index getting started with applications in software 6 10 I O protection 6 7 programmable power up states 6 7 static DIO 6 2 timing diagrams B 32 triggering 11 1 waveform acquisition 6 3 waveform triggering 6 3 digital routing 9 1 digital signals Change Detection Event 6 8 connecting 6 9 DI Sample Clock 6 4 DO Sample Clock 6 5 digital source triggering 11 1 digital waveform acquisition 6 3 generation 6 5 disk drive power PCI Express 3 6 disk drive power connector PCI Express devices 3 6 DMA 10 1 as a transfer method 10 4 changing data transfer methods 10 5 controllers 10 1 DO Sample Clock signal 6 5 do SampleClock 6 5 documentation conventions used in manual xvii NI resources E 1 related documentation xviii double buffered acquisition 4 12 drivers NI resources E 1 duplicate count prevention 7 35 enabling in NI DAQmx 7 38 example 7 35 prevention example 7 36 troubleshooting C 3 M Series User Manual 1 6 E E Series differences from M Series D 1 migrating applications from D 1 pinout comparison versus M Series 3 4 upgrading from D 1 edge counting 7 2 buffered 7 3 non cumulative buffered 7 4 on demand 7 2 sample clock 7 3 single point 7 2 edge separation measurement buffered two signal 7 19 single two signal 7 18 enabling duplicate count prevention in NI DAQmx 7 38 encoders qua
117. FI 6 P1 6 D GND PFI 9 P2 1 PFI 12 P2 4 PFI 14 P2 6 TERMINAL 1 D GND D GND P0 24 P0 23 P0 31 P0 29 P0 20 P0 19 P0 18 D GND P0 26 P0 27 P0 11 P0 15 P0 10 D GND P0 13 P0 8 D GND AO GND AO GND GND 23 30 GND 21 28 SENSE 2 27 GND 18 25 GND 16 TERMINAL 35 TERMINAL 1 TERMINAL 34 TERMINAL 68 DDD Figure A 23 NI 6289 Pinout Table A 23 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 O National Instruments Corporation A 97 M Series User Manual Device Specific Information Table A 23 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6289 Specifications Refer to the NI 628x Specifications for more detailed information about the NI 6289 device NI 6289 Accessory and Cabling Options This section describes some cable and accessory options for M Series
118. Floating Signal Sources M Series User Manual It is important to connect the negative lead of a floating source to AI GND either directly or through a bias resistor Otherwise the source may float 4 16 ni com Chapter 4 Analog Input out of the maximum working voltage range of the NI PGIA and the DAQ device returns erroneous data The easiest way to reference the source to AI GND is to connect the positive side of the signal to AI and connect the negative side of the signal to AI GND as well as to AI without using resistors This connection works well for DC coupled sources with low source impedance less than 100 Q Al Floating Signal Source Al Inpedance lt 100 Q AI SENSE AI GND Figure 4 4 Differential Connections for Floating Signal Sources without Bias Resistors However for larger source impedances this connection leaves the DIFF signal path significantly off balance Noise that couples electrostatically onto the positive line does not couple onto the negative line because it is connected to ground This noise appears as a DIFF mode signal instead of a common mode signal and thus appears in your data In this case instead of directly connecting the negative line to AI GND connect the negative line to AI GND through a resistor that is about 100 times the equivalent source impedance The resistor puts the signal path nearly in balance so that about the same amount of noise couples onto both connect
119. Getting Started with DAQ Includes overview information and a tutorial to learn how to take an NI DAQmx measurement in LabVIEW using the DAQ Assistant VI and Function Reference Measurement I O VIs and Functions Describes the LabVIEW NI DAQmx VIs and properties Taking Measurements Contains the conceptual and how to information you need to acquire and analyze measurement data in LabVIEW including common measurements measurement fundamentals NI DAQmx key concepts and device considerations LabWindows CVI M Series User Manual The Data Acquisition book of the LabWindows CVI Help contains measurement concepts for NI DAQmx This book also contains Taking an NI DAQmx Measurement in LabWindows CVI which includes step by step instructions about creating a measurement task using the DAQ Assistant In LabWindows CVI select Help Contents then select Using LabWindows CVI Data Acquisition The NI DAQm x Library book of the LabWindows CVI Help contains API overviews and function reference for NI DAQmx Select Library Reference NI DAQmx Library in the LabWindows CVI Help XX ni com About This Manual Measurement Studio The NI Measurement Studio Help contains function reference measurement concepts and a walkthrough for using the Measurement Studio NI DAQmx NET and Visual C class libraries This help collection is integrated into the Microsoft Visual Studio NET documentation In Visual Studio NET select Help Co
120. I 28 gt lt AI 21 AI 29 gt lt AI 22 AI 30 gt lt AI 23 AI 31 gt lt AI 32 AI 40 gt lt AI 33 AI 41 gt lt AI 34 AI 42 gt lt AI 35 AI 43 gt lt AI 36 AI 44 gt lt AI 37 AI 45 gt lt AI 38 AI 46 gt lt AI 39 AI 47 gt lt AI 48 AI 56 gt lt AI 49 AI 57 gt lt AI 50 AI 58 gt lt AI 51 AI 59 gt lt AI 52 AI 60 gt lt AI 53 AI 61 gt lt AI 54 AI 62 gt lt AI 55 AI 63 gt lt AI 64 AI 72 gt lt AI 65 AI 73 gt lt AI 66 AI 74 gt lt AI 67 AI 75 gt lt AI 68 AI 76 gt lt AI 69 AI 77 gt lt AI 70 AI 78 gt lt AI 71 AI 79 gt Also refer to the Connecting Ground Referenced Signal Sources section of Chapter 4 Analog Input AI SENSE Input Analog Input Sense In NRSE mode the reference for AI SENSE 2 each AI lt 0 15 gt signal is AI SENSE the reference for each AI lt 16 63 gt and AI lt 64 79 gt signal is AI SENSE 2 Also refer to the Connecting Ground Referenced Signal Sources section of Chapter 4 Analog Input AO lt 0 3 gt AO GND Output Analog Output Channels 0 to 3 These terminals supply the voltage output of AO channels 0 to 3 AO GND Analog Output Ground AO GND is the reference for AO lt 0 3 gt All three ground references AI GND AO GND and D GND are connected on the device M Series User Manual 3 2 ni com Chapter 3 Connector Information Table 3 1 1 0 Connector Signals Continued Signal Name Re
121. I3 P1 3 5 V 8 42 P0 19 D GND 7 41 PFI 4 P1 4 D GND 7 41 P0 20 PFI 5 P1 5 6 40 PFI 13 P2 5 P0 21 6 40 P0 29 PFI 6 P1 6 5 39 PFI 15 P2 7 P0 22 5 39 P0 31 D GND 4 38 PFI 7 P1 7 DGND 4 38 P0 23 PFI 9 P2 1 3 37 PFI 8 P2 0 P0 25 3 37 P0 24 PFI 12 P2 4 2 36 D GND P0 28 2 36 D GND PFI 14 P2 6 1 35 D GND P0 30 1 35 D GND T CONNECTOR 0 CONNECTOR 1 Al 0 15 Al 16 31 TERMINAL 68 TERMINAL 35 TERMINAL 68 TERMINAL 35 a TERMINAL 34 TERMINAL 1 TERMINAL 34 TERMINAL 1 Figure A 18 USB 6259 Mass Termination Pinout Table A 18 Default NI DAQmx Counter Timer Pins Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 National Instruments Corporation A 75 M Series User Manual Appendix Device Specific Information Table A 18 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTRO A 37 PFI 8 CTR OZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR 1 A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 i Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help M Series User Manual USB 6259 Mass Termination Spec
122. Input AI GND is an AI common signal that routes directly to the ground connection point on the devices You can use this signal if you need a general analog ground connection point to the device Refer to the When to Use Differential Connections with Ground Referenced Signal Sources section of Chapter 4 Analog Input for more information How can I use the AI Sample Clock and AI Convert Clock signals on an M Series device to sample the AI channel s M Series devices use ai SampleClock and ai ConvertClock to perform interval sampling As Figure C 1 shows ai SampleClock controls the sample period which is determined by the following equation 1 sample period sample rate Channel 0 Channel 1 l Convert Period Sample Period gt Figure C 1 ai SampleClock and ai ConvertClock ai ConvertClock controls the convert period which is determined by the following equation 1 convert period convert rate This method allows multiple channels to be sampled relatively quickly in relationship to the overall sample rate providing a nearly simultaneous effect with a fixed delay between channels C 2 ni com Appendix C Troubleshooting Analog Output I am seeing glitches on the output signal How can I minimize it When you use a DAC to generate a waveform you may observe glitches on the output signal These glitches are normal when a DAC switches from one voltage to another it produces g
123. NI 6280 A 82 NI 6281 A 87 NI 6284 A 92 NI 6289 A 98 PCI PCle PXI 6251 A 40 PCI 6259 A 66 PCIe 6259 A 66 PXI 6259 A 66 USB 6251 A 44 USB 6251 Mass Termination A 48 USB 6259 A 72 USB 6259 Mass Termination A 76 start analog input internal timing B 11 trigger 7 32 static DIO 6 2 using PFI terminals as 8 3 support technical E 1 switching from a large to a small input range 4 9 synchronization modes 7 38 80 MHz source 7 39 external source 7 39 other internal source 7 39 synchronizing multiple devices 9 3 synchronous counting mode 7 35 T technical support xxii E 1 terminal configuration 4 5 analog input 4 1 terminal name 3 4 terminals connecting counter 7 30 NI DAQmx default counter 7 30 M Series User Manual 1 14 Timebase 100 kHz 9 2 20 MHz 9 2 80 MHz 9 2 timed acquisitions 4 11 timing diagrams AI timing clocks B 6 analog input B 1 analog input internal timing B 6 analog input output timing B 21 analog input pause trigger B 19 analog input reference trigger B 14 analog input sample clock B 16 analog input signal definitions B 1 analog input Start B 11 analog input timing B 4 analog output B 23 analog output input timing B 25 analog output Pause Trigger B 31 analog output pause trigger B 28 analog output signal definitions B 23 analog output START trigger B 27 analog output timing START trigger B 30 clock generation B 48 Convert Clock B 9 count enab
124. O 7 PFI O PFI 1 PFI 2 PFI 3 PFI 4 PFI 5 PFI 6 PFI 7 J O O1 ND Al 4 S NI Gl 18 Al 12 Ae S S SI 19 Al GND END S S Sll 20 Al5 TEE S XI SI 21 Al 13 RTE S S Sll 22 Al GND ALGND S SI 23 Al6 S S 24 Alta AIME AI 26 ISIS 25 AI GND AVGNO lt S Gl 26 AI7 ALAS S S SI 27 Al 15 T7 S S Sl 28 Al GND AGND S I S 29 APFIO Al SENSE 2 S S 30 Al GND ACNE S S GI 31 AO 1 AO 2 S S SI 32 AO GND AO GND S j A y y ST S ex dono pos orris S P0 9 98 K II Gill 83 PFI 9 IS Sil Ses Den BONON IS S Sill Ses PFI 10 P0 11 100 S S SI alles D GND PO 12 101 IS amp Sil Ole pra Po 13 102 Sil S SI ales be P0 14 103 S QU GI 80 PFI 12 PO 15 104 S S ST loo bano pote 10s S S II Soi PFI 13 Po 17 106 Sil S SI Whoo bano PO18 107 ISI g Sil alos Pri 14 Po 19 108 S S Si llos D GND P0 20 109 SI amp N Gl 95 PFI 15 Po 21 110 N S S ll 06 5 v P0 22 111 S S S P0 23 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 Al 20 Al 28 Al GND Al 21 Al 29 Al GND Al 22 Al 30 Al GND Al 23 Al 31 Al GND APFI 1 Al GND AO 3 AO GND P0 24 D GND
125. P gt 3 National Instruments Corporation Figure A 19 USB 6259 Mass Termination Fuse Location Replace the lid and screws M Series User Manual Appendix Device Specific Information NI 6260 NI 6280 Pinout Figure A 20 shows the pinout of the NI 6280 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 80 ni com Appendix Device Specific Information ALO AI 8 Al GND Alt AI AI GND Al2 Al 10 AI GND A13 So Al11 Al GND 5 7 Al SENSE Al4 23 AI 12 AI GND 57 Al5 AI 13 2 AI GND Al 6 Al 14 AI GND Al7 Al15 TERMINAL 68 TERMINAL 34 AI GND NC NC NC NC APFI O D GND P0 4 P0 0 D GND P0 5 PO 1 D GND P0 6 P0 2 D GND P0 7 5V P0 3 D GND PFI 11 P2 3 D GND TERMINAL 35 TERMINAL 1 PFI 10 P2 2 PFI 0 P1 0 D GND PFI 1 P1 1 PFI 2 P1 2 D GND PFI 3 P1 3 5 V PFI 4 P1 4 D GND PFI 13 P2 5 PFI 5 P1 5 PFI 15 P2 7 PFI 6 P1 6 PFI 7 P1 7 D GND PFI 8 P2 0 PFI 9 P2 1 D GND PFI 12 P2 4 D GND PFI 14 P2 6 NC No Connect Figure A 20 NI 6280 Pinout Table A 20 Default NI DAQmx Counter Timer Pins Counter Timer Signal Defau
126. PXI_STAR Counter n Source National Instruments Corporation B 37 Figure B 40 Counter Timer Circuitry M Series User Manual Appendix B Timing Diagrams Pin to Internal Signal Delays Input timing is the timing specification for importing a signal to an internal bus on the M Series device Table B 26 shows the input timing for the counters on all input terminals Signals refer to the signal at the I O connector of the device and signals appended with _i refer to the signal internal to the device after the input buffer PFI RTSI or PXI_STAR PFLi RTSL i or PXI_STAR i o ti et Figure B 41 Pin to Internal Signal Delays Timing Diagram Table B 26 Pin to Internal Signal Delays Timing Timing From To Min ns Max ns t PFI PFI_i 5 2 6 2 18 2 22 0 RTSI RTSLi 2 0 2 5 5 0 6 0 STAR STAR_i 0 9 2 5 The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition maximum or minimum timing This difference can be useful when two external signals will be used together and the relative timing between the signals is important M Series User Manual Selected Gate and Selected Source Delays Tables B 27 and B 28 show the timing for the Selected Source and Selected Gate internal signals Selected Source is used to clock the 32 bit counter Selected Gate dr
127. Pin Device Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Counter Timer Signal Number Name CTR 1 A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 Table 7 5 37 Pin Device Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 13 PFI 0 CTR 0 GATE 32 PFI 1 CTR 0 AUX 33 PFI 2 CTR 0 OUT 17 PFI 6 CTROA 13 PFI 0 CTROZ 32 PFI 1 CTROB 33 PFI 2 CTR 1 SRC 15 PFI 3 CTR 1 GATE 34 PFI 4 CTR 1 AUX 35 PFI 5 CTR 1 OUT 36 PFI 7 CTR 1 A 15 PFI 3 CTR1Z 34 PFI 4 CTR 1B 35 PFI 5 You can use these defaults or select other sources and destinations for the counter timer signals in NI DAQmx Refer to Connecting Counter Signals in the NJ DAQmx Help or the LabVIEW 8 x Help for more information about how to connect your signals for common counter measurements and generations M Series default PFI lines for counter functions are listed in Physical Channels in the NI DAQmx Help or the LabVIEW 8 x Help O National Instruments Corporation 7 31 M Series User Manual Chapter 7 Counters Counter Triggering Arm Start Trigger Start Trigger Pause Trigger M Series User Manual Counters support three different triggering actions arm start start and pause Any counter operation can use the arm start trigger For counter output operations you can use it in addition to t
128. R Analog Comparison Event In addition Counter 1 TC or Counter 1 Gate can be routed to Counter 0 Source Counter 0 TC or Counter 0 Gate can be routed to Counter 1 Source Some of these options may not be available in some driver software 7 26 ni com Chapter 7 Counters Routing Counter n Source to an Output Terminal You can route Counter n Source out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFIs are set to high impedance at startup Counter n Gate Signal The Counter n Gate signal can perform many different operations depending on the application including starting and stopping the counter and saving the counter contents Routing a Signal to Counter n Gate Each counter has independent input selectors for the Counter n Gate signal Any of the following signals can be routed to the Counter n Gate input RTSI lt 0 7 gt e PFI lt 0 15 gt e ai ReferenceTrigger e al StartTrigger e ai SampleClock e ai ConvertClock e ao SampleClock e di SampleClock e do SampleClock e PXI STAR e Change Detection Event e Analog Comparison Event In addition Counter 1 Internal Output or Counter 1 Source can be routed to Counter 0 Gate Counter 0 Internal Output or Counter 0 Source can be routed to Counter 1 Gate Some of these options may not be available in some driver software Routing Counter n Gate to an Output Terminal You can route Counter n Gate out to any PFI lt 0 15 gt or RTSI lt 0
129. Series User Manual NI PXI M Series devices can be installed in any PXI chassis and most slots of PXI Express chassis PXI specifications are developed by the PXI System Alliance www pxisa org Using the terminology of the PXI specifications NI PXI M Series devices are 3U Hybrid Slot Compatible PXI 1 Peripheral Modules 3U designates devices that are 100 mm tall as opposed to the taller 6U modules Hybrid slot compatible defines where the device can be installed PXI M Series devices can be installed in the following chassis and slots e PXI chassis PXI M Series devices can be installed in any peripheral slot of a PXI chassis 10 2 ni com Chapter 10 Bus Interface PXI Express chassis PXI M Series devices can be installed in the following PXI Express chassis slots PXI 1 slots Accepts all PXI modules PXI hybrid slots Accepts PXI or PXI Express modules PXI 1 devices use PCI signaling to communicate to the host controller as opposed to PCI Express signaling Peripheral devices are installed in peripheral slots and are not system controllers Using PXI with CompactPCI Using PXI compatible products with standard CompactPCI products is an important feature provided by the PXI Hardware Specification Revision 2 1 If you use a PXI compatible plug in module in a standard CompactPCI chassis you cannot use PXI specific functions but you can still use the basic plug in device functions For example t
130. Software You can use the M Series device in the following analog input applications e Single point analog input e Finite analog input e Continuous analog input You can perform these applications through DMA interrupt or programmed I O data transfer mechanisms Some of the applications also use start reference and pause triggers 3 Note For more information about programming analog input applications and triggers in software refer to the NI DAQmx Help or the LabVIEW 8 x Help National Instruments Corporation 4 39 M Series User Manual Analog Output Many M Series devices have analog output functionality M Series devices that support analog output have either two or four AO channels that are controlled by a single clock and are capable of waveform generation Refer to Appendix A Device Specific Information for information about the capabilities of your device Figure 5 1 shows the analog output circuitry of M Series devices AO 0 AO 1 AO 2 AO 3 DACO AO FIFO AO Data DAC2 DAC3 ia L AO Sample Clock AO Offset Select AO Reference Select Figure 5 1 M Series Analog Output Circuitry Analog Output Circuitry DACs Digital to analog converters DACs convert digital codes to analog voltages National Instruments Corporation 5 1 M Series User Manual Chapter 5 Analog Output AO FIFO The AO FIFO enables analog output waveform
131. TART Trigger is routed as an asynchronous pulse The actual signal that gets routed is the Selected START signal so there is no synchronous delay involved Routing Logic ob gode RTSI PFI Selected Start p D Q To Internal Logic Sync Sample Clock Timebase _ gt Figure B 30 START Trigger Path t Selected Start 12 PFI RTSI Terminal Figure B 31 START Trigger Output Delay Timing Diagram Table B 19 START Trigger Output Delay Timing Timing Description Line From To Min ns Max ns ty Selected START PFI 8 1 9 1 27 1 30 8 Selected START RTSI 7 5 JA 17 9 18 5 M Series User Manual B 30 ni com Appendix B Timing Diagrams Pause Trigger Pause Trigger is only output asynchronously and only to RTSI The actual signal being routed is Selected Pause The Pause Trigger output timing can be derived by adding the delay in Table B 20 to the total Selected Pause delay Routing Logic Selected Pause To Internal Logic Sync Sample Clock Timebase Figure B 32 Pause Trigger Path Selected Pause CO 1 gt tig RTSI Terminal Figure B 33 Pause Trigger Output Routing Delay Timing Diagram Table B 20 Pause Trigger Output Routing Delay Timing Timing Description Line From To Min ns Max ns t3 Selected Pause RTSI 6 7 7 1 16 3 1
132. Timebase is a delayed version of the external signal This delay is long enough so that external signals can be synchronized with Sync Convert Clock Timebase and used by Convert Clock Timebase For timing diagrams and parameters for this case refer to the Convert Clock section The second level of timing is the sample level Basically converts are grouped in sets called samples and the timing of the samples can be independent from the timing of the converts The M Series device can use a timebase to generate the sample timing This timebase is called Sample Clock Timebase This signal can be internal for example an internal timebase or external Either way the signal gets divided in the SI counter and used to generate Sample Clock signals which in turn signal the start of a sample In order to synchronize external triggers to the Sample Clock Timebase another related signal is created Sync Sample Clock Timebase This is always the inverted signal selected to be Sample Clock Timebase while the Sample Clock Timebase signal is a copy without inversion of the signal The idea is that for each significant edge of the Sample Clock B 6 ni com Appendix B Timing Diagrams Timebase there is a significant edge of the Sync Sample Clock Timebase signal that occurs before Sample Clock Timebase and that can be used to synchronize the input triggers The source for Convert Clock Timebase and Sample Clock Timebase is the internal signal bus _i T
133. XI 6251 Pinout Figure A 8 shows the pinout of the PCI PCIe PXI 6251 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 38 ni com Appendix Device Specific Information AIO AI GND Al9 Al2 Al GND Al 11 Al SENSE Al 12 AI5 AI GND Al 14 Al7 Al GND AO GND AO GND D GND PO 0 PO 5 D GND P0 2 POZ P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND er 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 9 42 41 40 39 38 37 36 35 N O Aa o o o Al 8 Al 1 AI GND Al 10 Al 3 Al GND Al 4 Al GND Al 13 Al 6 Al GND Al 15 AO 0 AO 1 APFI 0 PO 4
134. You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 100 ni com Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information abou
135. affect the voltage in AI 0 To circumvent this problem use a voltage follower that has operational amplifiers op amps with unity gain for each high impedance source before connecting to an M Series device Otherwise you must decrease the sample rate for each channel Another common cause of channel crosstalk is due to sampling among multiple channels at various gains In this situation the settling times can increase For more information about charge injection and sampling channels at different gains refer to the Multichannel Scanning Considerations section of Chapter 4 Analog Input I am using my device in differential analog input ground reference mode and I have connected a differential input signal but my readings are random and drift rapidly What is wrong In DIFF mode if the readings from the DAQ device are random and drift rapidly you should check the ground reference connections The signal can be referenced to a level that is considered floating with reference to the device ground reference Even if you are in DIFF mode you must still reference the signal to the same ground level as the device reference There National Instruments Corporation C 1 M Series User Manual Appendix C Troubleshooting M Series User Manual are various methods of achieving this reference while maintaining a high common mode rejection ratio CMRR These methods are outlined in the Connecting Analog Input Signals section of Chapter 4 Analog
136. ain host memory once the operation is started thereby preventing any problems that may occur due to excessive bus traffic With non regeneration old data will not be repeated New data must be continually written to the buffer If the program does not write new data to the buffer at a fast enough rate to keep up with the generation the buffer will underflow and cause an error Analog Output Triggering Analog output supports two different triggering actions e Start trigger e Pause trigger An analog or digital trigger can initiate these actions All M Series devices support digital triggering but some do not support analog triggering To find your device s triggering options refer to the specifications document for your device Refer to the AO Start Trigger Signal and AO Pause Trigger Signal sections for more information about these triggering actions Connecting Analog Output Signals AO lt 0 3 gt are the voltage output signals for AO channels 0 1 2 and 3 AO GND is the ground reference for AO lt 0 3 gt M Series User Manual 5 6 ni com Chapter 5 Analog Output Figure 5 2 shows how to make AO connections to the device Analog Output Channels Analog Output Channels rt fon lt Channel o Ft ae Channel 2 Bi Load V OUT Load V OUT en V V Load V OUT Load V OUT Ho 1 Chann
137. al analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 68 ni com Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 69 M Series User Manual Appendix Device Specific Information USB 6259 USB 6259 Pinout Figure A 16 shows the pinout of the USB 6259 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information M Series User Manual A 70 ni com Appendix Device Specific Information AIO Al 8 Al GND Al 1 AI9 Al GND Al 2 Al 10 Al GND Al3 Al 11 Al GND Al SENSE Al GND AO 0 AO GND PO 0 PO 1 PO 2 P0 3 P0 4 P0 5 P0 6 P
138. al or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between two edges of the Gate signal You can calculate the semi period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter Single Semi Period Measurement Single semi period measurement is equivalent to single pulse width measurement 7 8 ni com Chapter 7 Counters Buffered Semi Period Measurement In buffered semi period measurement on each edge of the Gate signal the counter stores the count in a hardware save register A DMA controller transfers the stored values to host memory The counter begins counting when it is armed The arm usually occurs between edges on the Gate input So the first value stored in the hardware save register does not reflect a full semi period of the Gate input In most applications this first point should be discarded Figure 7 10 shows an example of a buffered semi period measurement Counter Armed GATE HALLA adas SOURCE A A Counter Value 0 1 2 1 2 3 1 1 2 1 22 32 412 22 Buffer 1 3 3 3 i _ 11 4 2 Figure 7 10 Buffered Semi Period Measurement Note that if you are using an external signal as the Source at least one So
139. alog output applications and triggers in software refer to the NI DAQmx Help or the LabVIEW 8 x Help M Series User Manual 5 12 ni com Digital 1 0 M Series devices contain up to 32 lines of bidirectional DIO signals on Port 0 In addition M Series devices have up to 16 PFI signals that can function as static DIO signals M Series devices support the following DIO features on Port 0 Up to 32 lines of DIO Direction and function of each terminal individually controllable Static digital input and output High speed digital waveform generation High speed digital waveform acquisition DI change detection trigger interrupt Figure 6 1 shows the circuitry of one DIO line Each DIO line is similar The following sections provide information about the various parts of the DIO circuit National Instruments Corporation 6 1 M Series User Manual Chapter 6 Digital I O DO Sample Clock DO x Direction Control DI Sample Clock DO Waveform Generation FIFO Static DO Buffer I O Protection e PO x Static DI Weak Pull Down DI Waveform Measurement FIFO DI Change Detection Static DIO Figure 6 1 M Series Digital 1 0 Circuitry The DIO terminals are named P0 lt 0 31 gt on the M Series device I O connector The voltage input and output levels and the current drive levels of the DIO lines are listed in th
140. annel list within the sample interval The greater the interchannel delay the more time the PGIA is allowed to settle before the next channel is sampled The interchannel delay is regulated by ai ConvertClock Connection between one or more of the following hardware software and the user For example hardware interfaces connect two other pieces of hardware 1 A means for a device to notify another device that an event occurred 2 A computer signal indicating that the CPU should suspend its current task to service a designated activity G 10 ni com kHz kS L LabVIEW LED lowpass filter LSB m M Series measurement measurement device MHz micro u O National Instruments Corporation G 11 Glossary Current output high Current output low See interrupt interrupt request line Kilohertz A unit of frequency 1 kHz 10 1 000 Hz 1 000 samples A graphical programming language Light Emitting Diode A semiconductor light source A filter that passes signals below a cutoff frequency while blocking signals above that frequency Least Significant Bit Meter An architecture for instrumentation class multichannel data acquisition devices based on the earlier E Series architecture with added new features The quantitative determination of a physical characteristic In practice measurement is the conversion of a physical quantity or observation to a domain where a human being or
141. ase all other combinations of signals driving Source and Gate B 42 ni com Appendix B Timing Diagrams Figure B 47 and Table B 32 show the setup and hold requirements at the PFI pins for the first case where a PFI pin drives Counter n Source and a different PFI pin drives Counter n Gate PFI Gate A X x no I PFI Source Figure B 47 Gate to Source Setup and Hold Timing Diagram Table B 32 Gate to Source Setup and Hold Timing Synchronizatio Timing Description Gating Mode n Mode Min ns Max ns tgs Setup time from Edge External Source 12 3 PFI Gate to PFI Source Level External Source 8 3 tsH Hold time from Edge External Source 0 5 PFI Gate to PFI Source Level External Source 2 0 O National Instruments Corporation B 43 Figure B 48 and Table B 33 show the setup and hold requirements of the internal block of the DAQ STC2 Use the table to calculate the setup and hold times for your Source and Gate signals for the general case In the general case you can determine whether the setup and hold requirements are met by adding up the various delays of the appropriate signals through the counter timer circuit Count_Enable A x x Selected_Source Figure B 48 DAQ STC2 Internal Block Setup and Hold Requirements Timing Diagram Table B 33 DAQ STC2 Internal Block Setup and Hold Requirements Timi
142. ater than Less than or equal to Greater than or equal to Per E Degree Q Ohm National Instruments Corporation G 1 M Series User Manual Glossary A A A D AC accuracy ADE AI AI GND AI SENSE analog analog input signal analog output signal analog signal analog trigger AO M Series User Manual Amperes the unit of electric current Analog to Digital Most often used as A D converter Alternating current A measure of the capability of an instrument or sensor to faithfully indicate the value of the measured signal This term is not related to resolution however the accuracy level can never be better than the resolution of the instrument Application development environment 1 Analog input 2 Analog input channel signal Analog input ground signal Analog input sense signal A signal whose amplitude can have a continuous range of values An input signal that varies smoothly over a continuous range of values rather than in discrete steps An output signal that varies smoothly over a continuous range of values rather than in discrete steps A signal representing a variable that can be observed and represented continuously A trigger that occurs at a user selected point on an incoming analog signal Triggering can be set to occur at a specific level on either an increasing or a decreasing signal positive or negative slope Analog triggering can be implemented either in
143. ation 4 37 M Series User Manual Chapter 4 Analog Input Routing Al Reference Trigger Signal to an Output Terminal You can route ai ReferenceTrigger out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFI terminals are configured as inputs by default Al Pause Trigger Signal 3 You can use the AI Pause Trigger ai PauseTrigger signal to pause and resume a measurement acquisition The internal sample clock pauses while the external trigger signal is active and resumes when the signal is inactive You can program the active level of the pause trigger to be high or low Using a Digital Source To use ai SampleClock specify a source and a polarity The source can be any of the following signals e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXISTAR The source also can be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information Using an Analog Source When you use an analog trigger source the internal sample clock pauses when the Analog Comparison Event signal is low and resumes when the signal goes high or vice versa Routing Al Pause Trigger Signal to an Output Terminal You can route ai PauseTrigger out to RTSI lt 0 7 gt Note Pause triggers are only sensitive to the level of the source not the edge M Series User Manual 4 38 ni com Chapter 4 Analog Input Getting Started with AI Applications in
144. ation A 9 M Series User Manual Appendix Device Specific Information M Series User Manual SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connecto
145. ault NI DAQmx Counter Timer Pins Figure A 4 NI 6224 Pinout Default Connector 0 Pin Number Counter Timer Signal Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 A 16 ni com Appendix Device Specific Information Table A 4 Default NI DAQmx Counter Timer Pins Continued Default Connector 0 Pin Number Counter Timer Signal Name CTROZ 3 PFI 9 CTR OB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1 B 46 PFI 11 May Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6224 Specifications Refer to the NI 622x Specifications for more detailed information about the NI 6224 device NI 6224 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with two 68 pin connectors such as the NI 6224 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and
146. ay float out of the valid input range of the NI PGIA and the DAQ device returns erroneous data Figure 4 8 shows a floating source connected to the DAQ device in NRSE mode Al Floating F Signal V o Source Le o Al SENSE R o Al GND Figure 4 8 NRSE Connections for Floating Signal Sources All of the bias resistor configurations discussed in the Using Differential Connections for Floating Signal Sources section apply to the NRSE bias resistors as well Replace AI with AI SENSE in Figures 4 4 4 5 4 6 and 4 7 for configurations with zero to two bias resistors The noise M Series User Manual Chapter 4 Analog Input rejection of NRSE mode is better than RSE mode because the AI SENSE connection is made remotely near the source However the noise rejection of NRSE mode is worse than DIFF mode because the AI SENSE connection is shared with all channels rather than being cabled in a twisted pair with the AI signal Using the DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Using Referenced Single Ended RSE Connections for Floating Signal Sources Figure 4 9 shows how to connect a floating signal source to the M Series device configured for RSE mode Al lt 0 n gt So ol x Programmable Gain Floating Instrumen
147. c text also denotes text that is a placeholder for a word or value that you must supply National Instruments Corporation xvii M Series User Manual About This Manual monospace monospace bold monospace italic Text in this font denotes text or characters that you should enter from the keyboard sections of code programming examples and syntax examples This font is also used for the proper names of disk drives paths directories programs subprograms subroutines device names functions operations variables filenames and extensions Bold text in this font denotes the messages and responses that the computer automatically prints to the screen This font also emphasizes lines of code that are different from the other examples Italic text in this font denotes text that is a placeholder for a word or value that you must supply Related Documentation Each application software package and driver includes information about writing applications for taking measurements and controlling measurement devices The following references to documents assume you have NI DAQ 8 1 or later and where applicable version 7 0 or later of the NI application software NI DAQmx for Windows M Series User Manual The DAQ Getting Started Guide describes how to install your NI DAQmx for Windows software your NI DAQmx supported DAQ device and how to confirm that your device is operating properly Select Start All Programs National Inst
148. cal errors exist National Instruments reserves the right to make changes to subsequent editions of this document without prior notice to holders of this edition The reader should consult National Instruments if errors are suspected In no event shall National Instruments be liable for any damages arising out of or related to this document or the information contained in it EXCEPT AS SPECIFIED HEREIN NATIONAL INSTRUMENTS MAKES NO WARRANTIES EXPRESS OR IMPLIED AND SPECIFICALLY DISCLAIMS ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE CUSTOMER S RIGHT TO RECOVER DAMAGES CAUSED BY FAULT OR NEGLIGENCE ON THE PART OF NATIONAL INSTRUMENTS SHALL BE LIMITED TO THE AMOUNT THERETOFORE PAID BY THE CUSTOMER NATIONAL INSTRUMENTS WILL NOT BE LIABLE FOR DAMAGES RESULTING FROM LOSS OF DATA PROFITS USE OF PRODUCTS OR INCIDENTAL OR CONSEQUENTIAL DAMAGES EVEN IF ADVISED OF THE POSSIBILITY THEREOF This limitation of the liability of National Instruments will apply regardless of the form of action whether in contract or tort including negligence Any action against National Instruments must be brought within one year after the cause of action accrues National Instruments shall not be liable for any delay in performance due to causes beyond its reasonable control The warranty provided herein does not cover damages defects malfunctions or service failures caused by owner s failure to follow the National Instruments installation operation or
149. can be single ended or differential For digital signals you group channels to form ports Ports usually consist of either four or eight digital channels Hardware component that controls timing for reading from or writing to groups Complementary metal oxide semiconductor Common mode rejection ratio A measure of the ability of a differential amplifier to reject interference from a common mode signal usually expressed in decibels dB The ability of an electronic system to cancel any electronic noise pick up that is common to both the positive and negative polarities of the input leads to the instrument front end Common mode rejection is only a relevant specification for systems having a balanced or differential input G 4 ni com common mode signal connector convert rate count counter counter timer D D GND D SUB connector DAC Glossary 1 Any voltage present at the instrumentation amplifier inputs with respect to amplifier ground 2 The signal relative to the instrument chassis or computer s ground of the signals from a differential input This is often a noise signal such as 50 or 60 Hz hum 1 A device that provides electrical connection 2 A fixture either male or female attached to a cable or chassis for quickly making and breaking one or more circuits A symbol that connects points on a flowchart Reciprocal of the interchannel delay The number of events such as zero crossings puls
150. ce Refer to the Connecting Analog Input Signals section for more information Ground reference settings are programmed on a per channel basis For example you might configure the device to scan 12 channels four differentially configured channels and eight single ended channels M Series devices implement the different analog input ground reference settings by routing different signals to the NI PGIA The NI PGIA is a differential amplifier That is the NI PGIA amplifies or attenuates the difference in voltage between its two inputs The NI PGIA drives the ADC National Instruments Corporation 4 5 M Series User Manual Chapter 4 Analog Input with this amplified voltage The amount of amplification the gain is determined by the analog input range as shown in Figure 4 2 Vin o Vin 0 Instrumentation Amplifier Measured Voltage Vm Vin Vin x Gain Figure 4 2 NI PGIA Table 4 5 shows how signals are routed to the NI PGIA Table 4 5 Signals Routed to the NI PGIA AI Ground Reference Signals Routed to the Positive Signals Routed to the Negative Settings Input of the NI PGIA Vin Input of the NI PGIA V j _ RSE AI lt 0 79 gt AI GND NRSE AI lt 0 15 gt AI SENSE AI lt 16 63 gt AI SENSE 2 AI lt 64 79 gt AI SENSE NI 6225 only AI SENSE 2 NI 6255 only DIFF AI lt 0 7 gt AI lt 8 15 gt AI lt 16 23 gt AI lt 24 31 gt AI lt 32 39 gt
151. ce for each Source pulse Normally the counter value and Counter n Internal Output signals change synchronously to the Source signal With duplicate count prevention the counter value and Counter n Internal Output signals change synchronously to the 80 MHz Timebase Note that duplicate count prevention should only be used if the frequency of the Source signal is 20 MHz or less When To Use Duplicate Count Prevention You should use duplicate count prevention if the following conditions are true e You are making a counter measurement e You are using an external signal such as PFI x as the counter Source e The frequency of the external source is 20 MHz or less e You can have the counter value and output to change synchronously with the 80 MHz Timebase In all other cases you should not use duplicate count prevention National Instruments Corporation 7 37 M Series User Manual Chapter 7 Counters Enabling Duplicate Count Prevention in NI DAQmx You can enable duplicate count prevention in NI DAQmx by setting the Enable Duplicate Count Prevention attribute property For specific information about finding the Enable Duplicate Count Prevention attribute property refer to the help file for the API you are using Synchronization Modes The 32 bit counter counts up or down synchronously with the Source signal The Gate signal and other counter inputs are asynchronous to the Source signal So M Series devices synchronize
152. ce in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information A 82 ni com Appendix Device Specific Information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector bloc
153. ce input to the 32 bit general purpose counter timers The 20 MHz Timebase is generated by dividing down the 80 MHz Timebase The 100 kHz Timebase can be used to generate many of the Al and AO timing signals The 100 kHz Timebase also can be used as the Source input to the 32 bit general purpose counter timers The 100 kHz Timebase is generated by dividing down the 20 MHz Timebase by 200 External Reference Clock M Series User Manual The external reference clock can be used as a source for the internal timebases 80 MHz Timebase 20 MHz Timebase and 100 kHz Timebase on an M Series device By using the external reference clock you can synchronize the internal timebases to an external clock The following signals can be routed to drive the external reference clock RTSI lt 0 7 gt e PXICLK10 e PXISTAR The external reference clock is an input to a Phase Lock Loop PLL The PLL generates the internal timebases 9 2 ni com Chapter 9 Digital Routing and Clock Generation 10 MHz Reference Clock The 10 MHz reference clock can be used to synchronize other devices to your M Series device The 10 MHz reference clock can be routed to the RTSI lt 0 7 gt terminals Other devices connected to the RTSI bus can use this signal as a clock input The 10 MHz reference clock is generated by dividing down the onboard oscillator Synchronizing Multiple Devices With the RTSI bus and the routing capabilities of M Series devic
154. ces use an onboard oscillator to generate the filter clock with a 40 MHz frequency ay Note NI DAQmx only supports filters on counter inputs The following is an example of low to high transitions of the input signal High to low transitions work similarly M Series User Manual 8 4 ni com Chapter 8 PFI Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on N consecutive edges the low to high transition is propagated to the rest of the circuit The value of N depends on the filter setting refer to Table 8 1 Table 8 1 Filters Filter Clock 40 MHz PXI_STAR Terminal J ETL Filtered input goes high Filtered Input _ _ _ N Filter Clocks Pulse Width Pulse Width Needed to Pass Guaranteed to Pass Guaranteed to Not Filter Setting Signal Filter Pass Filter 125 ns 5 125 ns 100 ns 6 425 us 257 6 425 us 6 400 us 2 55 ms 101 800 2 55 ms 2 54 ms Disabled The filter setting for each input can be configured independently On power up the filters are disabled Figure 8 3 shows an example of a low to high transition on an input that has its filter set to 125 ns N 5 RTSI PFI or when terminal is sampled high on five consecutive filter clocks 1 1 2 3 4 1 2 3 4 5 National Instruments Corporation 8 5 Figure 8 3 Filt
155. clicking Manual Calibration Procedures at ni com calibration Signal Conditioning Many sensors and transducers require signal conditioning before a measurement system can effectively and accurately acquire the signal The front end signal conditioning system can include functions such as signal amplification attenuation filtering electrical isolation simultaneous sampling and multiplexing In addition many transducers require excitation currents or voltages bridge completion linearization or high amplification for proper and accurate operation Therefore most computer based measurement systems include some form of signal conditioning in addition to plug in data acquisition DAQ devices Sensors and Transducers Sensors can generate electrical signals to measure physical phenomena such as temperature force sound or light Some commonly used sensors are strain gauges thermocouples thermistors angular encoders linear encoders and resistance temperature detectors RTDs To measure signals from these various transducers you must convert them into a form that a DAQ device can accept For example the output voltage of most thermocouples is very small and susceptible to noise Therefore you may need to amplify or filter the thermocouple output before digitizing National Instruments Corporation 2 3 M Series User Manual Chapter 2 DAQ System Overview it The manipulation of signals to prepare them for digitizing is calle
156. considerations 4 8 multiple device synchronization 9 3 MUX 4 1 National Instruments support and services E 1 NET languages documentation xxi NI 6220 accessory options A 4 cabling options A 4 pinout A 2 specifications A 4 NI 6221 A 7 specifications A 9 NI 6221 37 pin A 12 accessory options A 13 cabling options A 13 pinout A 12 specifications A 13 NI 6221 68 pin A 7 accessory options A 9 cabling options A 9 pinout A 7 specifications A 9 NI 6224 accessory options A 17 cabling options A 17 pinout A 15 specifications A 17 NI 6225 accessory options A 23 cabling options A 23 pinout A 21 specifications A 23 National Instruments Corporation Index NI 6229 accessory options A 29 cabling options A 29 pinout A 27 specifications A 29 NI 6250 accessory options A 35 cabling options A 35 pinout A 33 specifications A 35 NI 6251 A 38 specifications A 40 A 48 NI 6254 accessory options A 54 cabling options A 54 pinout A 52 specifications A 54 NI 6255 accessory options A 60 cabling options A 60 pinout A 58 specifications A 60 NI 6259 A 64 specifications A 66 A 76 NI 6280 accessory options A 82 cabling options A 82 pinout A 80 specifications A 82 NI 6281 accessory options A 87 cabling options A 87 pinout A 85 specifications A 87 NI 6284 accessory options A 92 cabling options A 92 pinout A 90 specifications A 92 M Series User Manual
157. cuitry uses FIFOs if present in each sub system to ensure efficient data movement e Routes timing and control signals The acquisition generation sub systems use these signals to manage acquisitions and generations These signals can come from the following sources Your M Series device Other devices in your system through RTSI User input through the PFI terminals User input through the PXI_STAR terminal e Routes and generates the main clock signals for the M Series device Clock Routing Figure 9 1 shows the clock routing circuitry of an M Series device Onboard 10 MHz RefCk To ATSI lt 0 7 gt lo Output Selectors us e 80 MHz Timebase RTSI lt 0 7 gt Clock in PXI_CLK10 4 20 MHz Timebase PXI STAR V4 200 4 100 kHz Timebase Figure 9 1 M Series Clock Routing Circuitry National Instruments Corporation 9 1 M Series User Manual Chapter 9 Digital Routing and Clock Generation 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase The 80 MHz Timebase can be used as the Source input to the 32 bit general purpose counter timers The 80 MHz Timebase is generated from the following sources Onboard oscillator External signal by using the external reference clock The 20 MHz Timebase normally generates many of the Al and AO timing signals The 20 MHz Timebase also can be used as the Sour
158. cutoff frequency of 40 kHz that can be enabled If the programmable filter is not enabled the cutoff frequency is fixed at 750 kHz If the cutoff is programmable choose the lower cutoff to reduce measurement noise However a filter with a lower cutoff frequency increases the settling time of your device as shown in the specifications which reduces its maximum conversion rate Therefore you may have to reduce the rate of your AI Convert and AI Sample Clocks If that reduced sample rate is too slow for your application select the higher cutoff frequency Add additional filters to AI signals using external accessories as described in the Cables and Accessories section of Chapter 2 DAQ System Overview Analog Input Ground Reference Settings M Series devices support the analog input ground reference settings shown in Table 4 4 Table 4 4 Analog Input Ground Reference Settings AI Ground Reference Settings Description DIFF In differential DIFF mode the M Series device measures the difference in voltage between two AI signals RSE In referenced single ended RSE mode the M Series device measures the voltage of an AI signal relative to AI GND NRSE In non referenced single ended NRSE mode the M Series device measures the voltage of an AI signal relative to one of the AI SENSE or AI SENSE 2 inputs The A ground reference setting determines how you should connect your AI signals to the M Series devi
159. d signal conditioning For more information about sensors refer to the following documents e For general information about sensors visit ni com sensors e Ifyou are using LabVIEW refer to the LabVIEW Help by selecting Help Search the LabVIEW Help in LabVIEW and then navigate to the Taking Measurements book on the Contents tab e Ifyou are using other application software refer to Common Sensors in the NI DAQmx Help or the LabVIEW 8 x Help Signal Conditioning Options SCXI SCXI is a front end signal conditioning and switching system for various measurement devices including M Series devices An SCXI system consists of a rugged chassis that houses shielded signal conditioning modules that amplify filter isolate and multiplex analog signals from thermocouples or other transducers SCXI is designed for large measurement systems or systems requiring high speed acquisition System features include the following Modular architecture Choose your measurement technology Expandability Expand your system to 3 072 channels Integration Combine analog input analog output digital I O and switching into a single unified platform High bandwidth Acquire signals at high rates e Connectivity Select from SCXI modules with thermocouple connectors or terminal blocks i Note SCXI is not supported on the NI 6221 37 pin or USB 625x devices M Series User Manual SCC SCC is a front end signal conditioning sys
160. d to denote the amount of memory required to store one byte of data A pictorial description or representation of a program or algorithm Bayonet Neill Concelman A type of coaxial connector used in situations requiring shielded cable for signal connections and or controlled impedance applications 1 Temporary storage for acquired or generated data 2 A memory device that stores intermediate data between two devices M Series User Manual Glossary bus buses C C calibration calibrator cascading CE channel clock CMOS CMRR common mode rejection M Series User Manual The group of electrical conductors that interconnect individual circuitry in a computer Typically a bus is the expansion vehicle to which I O or other devices are connected Examples of PC buses are the PCI AT ISA and EISA bus Celsius The process of determining the accuracy of an instrument In a formal sense calibration establishes the relationship of an instrument s measurement to the value provided by a standard When that relationship is known the instrument may then be adjusted calibrated for best accuracy A precise traceable signal source used to calibrate instruments Process of extending the counting range of a counter chip by connecting to the next higher counter European emissions control standard Pin or wire lead to which you apply or from which you read the analog or digital signal Analog signals
161. d to the Counter n Gate signal input of the counter 7 32 ni com Chapter 7 Counters Other Counter Features Cascading Counters Counter Filters You can internally route the Counter n Internal Output and Counter n TC signals of each counter to the Gate inputs of the other counter By cascading two counters together you can effectively create a 64 bit counter By cascading counters you also can enable other applications For example to improve the accuracy of frequency measurements use reciprocal frequency measurement as described in the Method 3 Measure Large Range of Frequencies Using Two Counters section You can enable a programmable debouncing filter on each PFI RTSL or PXI_STAR signal When the filters are enabled your device samples the input on each rising edge of a filter clock M Series devices use an onboard oscillator to generate the filter clock with a 40 MHZ frequency B Note NI DAQmx only supports filters on counter inputs The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on N consecutive edges the low to high transition is propagated to the rest of the circuit The value of N depends on the filter setting refer to Table 7 6 Table 7 6 Filters
162. dapters are necessary Refer to the SCXT Advisor available by going to ni com info and entering the info code rdscad for more information National Instruments Corporation A 87 M Series User Manual Appendix Device Specific Information M Series User Manual SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector b
163. data acquisition devices A 5B system consists of eight or 16 single channel modules that plug into a backplane for conditioning thermocouples and other analog signals National Instruments offers a complete line of 5B modules carriers backplanes and accessories 3 Note 5B is not supported on the NI 6221 37 pin or USB 625x devices B Note For more information about SCXI SCC and 5B Series products refer to ni com signalconditioning Cables and Accessories NI offers a variety of products to use with M Series devices including cables connector blocks and other accessories as follows National Instruments Corporation Cables and cable assemblies unshielded ribbon and shielded Screw terminal connector blocks shielded and unshielded RTSI bus cables 2 5 M Series User Manual Chapter 2 DAQ System Overview Custom Cabling SCXI modules and accessories for isolating amplifying exciting and multiplexing signals with SCXI you can condition and acquire up to 3 072 channels e Low channel count signal conditioning modules devices and accessories including conditioning for strain gauges and RTDs simultaneous sample and hold circuitry and relays For more specific information about these products refer to ni com Refer to the Custom Cabling section of this chapter the Field Wiring Considerations section of Chapter 4 Analog Input and Appendix A Device Specific Information for information about how to select
164. dge Separation Measurement Buffered Two Signal Edge Separation Measurement Buffered and single two signal edge separation measurements are similar but buffered measurement measures multiple intervals The counter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in a hardware save register On the next active edge of the Gate signal the counter begins another measurement A DMA controller transfers the stored values to host memory Figure 7 21 shows an example of a buffered two signal edge separation measurement AUX As A GATE A A A SOURCE Counter Value 1 2 3 1 2 3 1 2 3 3 3 3 Buffer Figure 7 21 Buffered Two Signal Edge Separation Measurement For information about connecting counter signals refer to the Default Counter Timer Pinouts section National Instruments Corporation 7 19 M Series User Manual Chapter 7 Counters Counter Output Applications Simple Pulse Generation M Series User Manual Single Pulse Generation The counter can output a single pulse The pulse appears on the Counter n Internal Output signal of the counter You can specify a delay from when
165. drature 7 15 encoding X1 7 15 X2 7 16 X4 7 16 equivalent time sampling 7 24 examples NI resources E 1 exporting timing output signals using PFI terminals 8 3 external reference clock 9 2 external source mode 7 39 F features counter 7 33 field wiring considerations 4 25 filters counter 7 33 PFL 8 4 PXI_STAR 9 9 RTSI 9 6 floating signal sources connecting 4 15 ni com description 4 15 using in differential mode 4 16 using in NRSE mode 4 19 using in RSE mode 4 20 when to use in differential mode 4 15 when to use in NRSE mode 4 15 when to use in RSE mode 4 16 FREQ OUT signal 7 30 frequency division 7 24 generation 7 23 generator 7 23 frequency measurement 7 9 Frequency Output signal 7 30 fuse replacement USB 6251 A 45 USB 6251 Mass Termination A 50 USB 6259 A 73 USB 6259 Mass Termination A 79 G generations analog output data 5 4 buffered hardware timed 5 5 clock 9 1 continuous pulse train 7 22 digital waveform 6 5 frequency 7 23 hardware timed 5 5 non buffered hardware timed 5 5 pulse for ETS 7 24 pulse train 7 22 retriggerable single pulse 7 21 simple pulse 7 20 single pulse 7 20 single pulse with start trigger 7 20 software timed 5 4 getting started 1 1 Al applications in software 4 39 AO applications in software 5 12 O National Instruments Corporation 1 7 Index DIO applications in software 6 10 ghost voltages when sampling multiple channels
166. e For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help PCI PCle PXI 6259 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6259 device PCI PCle PXI 6259 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with two 68 pin connectors such as the NI PCI PCIe PXI 6259 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and later supports SCX in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series User Manual A 66 ni com Appendix Device Specific Information M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information SCC
167. e Specific Information for device I O connector pinouts 1 0 Connector Signal Descriptions Table 3 1 describes the signals found on the I O connectors Not all signals are available on all devices National Instruments Corporation 3 1 M Series User Manual Chapter 3 Connector Information Table 3 1 1 0 Connector Signals Signal Name Reference Direction Description AI GND Analog Input Ground These terminals are the reference point for single ended AI measurements in RSE mode and the bias current return point for DIFF measurements All three ground references AI GND AO GND and D GND are connected on the device AI lt 0 79 gt Varies Input Analog Input Channels 0 to 79 For single ended measurements each signal is an analog input voltage channel In RSE mode AI GND is the reference for these signals In NRSE mode the reference for each AI lt 0 15 gt signal is AI SENSE the reference for each AI lt 16 63 gt and AI lt 64 79 gt signal is AI SENSE 2 For differential measurements AI 0 and AI 8 are the positive and negative inputs of differential analog input channel 0 Similarly the following signal pairs also form differential input channels lt AI 1 AI 9 gt lt AI 2 AI 10 gt lt AI 3 AI 11 gt lt AI 4 AI 12 gt lt AI 5 AI 13 gt lt AI 6 AI 14 gt lt AI 7 AI 15 gt lt AI 16 AI 24 gt lt AI 17 AI 25 gt lt AI 18 AI 26 gt lt AI 19 AI 27 gt lt AI 20 A
168. e number of points you average and slow down the scanning rate 4 10 ni com Chapter 4 Analog Input Suppose you want to sample 10 channels over a period of 20 ms and average the results You could acquire 500 points from each channel at a scan rate of 250 kS s Another method would be to acquire 1 000 points from each channel at a scan rate of 500 kS s Both methods take the same amount of time Doubling the number of samples averaged from 500 to 1 000 decreases the effect of noise by a factor of 1 4 the square root of 2 However doubling the number of samples in this example decreases the time the NI PGIA has to settle from 4 us to 2 us In some cases the slower scan rate system returns more accurate results Example 2 If the time relationship between channels is not critical you can sample from the same channel multiple times and scan less frequently For example suppose an application requires averaging 100 points from channel 0 and averaging 100 points from channel 1 You could alternate reading between channels that is read one point from channel 0 then one point from channel 1 and so on You also could read all 100 points from channel 0 then read 100 points from channel 1 The second method switches between channels much less often and is affected much less by settling time Analog Input Data Acquisition Methods When performing analog input measurements you either can perform software timed or hardware timed acqui
169. e specifications of your device M Series User Manual Each of the M Series DIO lines can be used as a static DI or DO line You can use static DIO lines to monitor or control digital signals Each DIO can be individually configured as a digital input DI or digital output DO All samples of static DI lines and updates of DO lines are software timed P0 6 and P0 7 on 68 pin M Series devices also can control the up down input of general purpose counters 0 and 1 respectively However it is recommended that you use PFI signals to control the up down input of the counters The up down control signals Counter 0 Up_Down and Counter 1 Up_Down are input only and do not affect the operation of the DIO lines 6 2 ni com Chapter 6 Digital I O Digital Waveform Triggering M Series devices do not have an independent DI or DO Start Trigger for digital waveform acquisition or generation To trigger a DI or DO operation first select a signal to be the source of DI Sample Clock or DO Sample Clock Then generate a trigger that initiates pulses on the source signal The method for generating this trigger depends on which signal is the source of DI Sample Clock or DO Sample Clock For example consider the case where you are using AI Sample Clock as the source of DI Sample Clock To initiate pulses on AI Sample Clock and therefore on DI Sample Clock you use AI Start Trigger to trigger the start of an AI operation The AI Start Trigger caus
170. e two software selectable output options are pulse on TC and toggle output polarity on TC The output polarity is software selectable for both options National Instruments Corporation 7 29 M Series User Manual Chapter 7 Counters Routing Counter n Internal Output to an Output Terminal You can route Counter n Internal Output to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFIs are set to high impedance at startup Frequency Output Signal The Frequency Output FREQ OUT signal is the output of the frequency output generator Routing Frequency Output to a Terminal You can route Frequency Output to any PFI lt 0 15 gt terminal All PFls are set to high impedance at startup The FREQ OUT signal also can be routed to DO Sample Clock and DI Sample Clock Default Counter Timer Pinouts M Series User Manual By default NI DAQmx routes the counter timer inputs and outputs to the PFI pins shown in Table 7 4 for 68 pin devices and Table 7 5 for 37 pin devices Table 7 4 68 Pin Device Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Connector 0 Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 7 30 ni com Chapter 7 Counters Table 7 4 68
171. e user s program is responsible for transferring data Each read or write call in the program initiates the transfer of data Programmed I O is typically used in software timed on demand operations Refer to the Software Timed Generations section of Chapter 5 Analog Output for more information 10 4 ni com Chapter 10 Bus Interface Changing Data Transfer Methods PCI PCle PXI Devices On PCI PCI Express and PXI M Series devices each measurement and acquisition circuit that is AI AO and so on has a dedicated DMA channel So in most applications all data transfers use DMA However NI DAQmx allows you to disable DMA and use interrupts To change your data transfer mechanism between DMA and interrupts in NI DAQmx use the Data Transfer Mechanism property node USB Devices USB M Series devices have four dedicated USB Signal Stream channels These channels are assigned to the first four measurement acquisition circuits that request one If a USB Signal Stream is not available you must set the data transfer mechanism to programmed I O otherwise the driver returns an error To change your data transfer mechanism between USB Signal Streams and programmed I O use the Data Transfer Mechanism property node function in NI DAQmx National Instruments Corporation 10 5 M Series User Manual Triggering A trigger is a signal that causes an action such as starting or stopping the acquisition of data When you configure a trigge
172. easured 0123 0 1 23 e Properly Matched Sample Clock and Convert Clock Figure 4 21 ai SampleClock and ai ConvertClock Properly Matched It is also possible to use a single external signal to drive both ai SampleClock and ai ConvertClock at the same time In this mode each tick of the external clock will cause a conversion on the ADC Figure 4 22 shows this timing relationship ai SampleClock NA NL ai ConvertClock aaa nan Channel Measured 0 123 01 2 3 01 Sample 1 Sample 2 Sample 3 gt lt gt lt gt e One External Signal Driving Both Clocks Figure 4 22 Single External Signal Driving ai SampleClock and ai ConvertClock Simultaneously 4 34 ni com Chapter 4 Analog Input Al Convert Clock Timebase Signal The AI Convert Clock Timebase ai ConvertClockTimebase signal is divided down to provide on of the possible sources for ai ConvertClock Use one of the following signals as the source of ai ConvertClockTimebase e ail SampleClockTimebase e 20 MHz Timebase ai ConvertClockTimebase is not available as an output on the I O connector Al Hold Complete Event Signal The AI Hold Complete Event ai HoldCompleteEvent signal generates a pulse after each A D conversion begins You can route ai HoldCompleteEvent out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal The polarity of ai HoldCompleteEvent is software selectable but
173. ed acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode generation refers to the generation of a specific predetermined number of data samples Once the specified number of samples has been written out the generation stops Continuous generation refers to the generation of an unspecified number of samples Instead of generating a set number of data samples and stopping a continuous generation continues until you stop the operation There are several different methods of continuous generation that control what data is written These methods are regeneration FIFO regeneration and non regeneration modes National Instruments Corporation 5 5 M Series User Manual Chapter 5 Analog Output Regeneration is the repetition of the data that is already in the buffer Standard regeneration is when data from the PC buffer is continually downloaded to the FIFO to be written out New data can be written to the PC buffer at any time without disrupting the output With FIFO regeneration the entire buffer is downloaded to the FIFO and regenerated from there Once the data is downloaded new data cannot be written to the FIFO To use FIFO regeneration the entire buffer must fit within the FIFO size The advantage of using FIFO regeneration is that it does not require communication with the m
174. ed by M N For information about connecting counter signals refer to the Default Counter Timer Pinouts section 7 22 ni com Chapter 7 Counters Frequency Generation 20 MHz Timebase e You can generate a frequency by using a counter in pulse train generation mode or by using the frequency generator circuit Using the Frequency Generator The frequency generator can output a square wave at many different frequencies The frequency generator is independent of the two general purpose 32 bit counter timer modules on M Series devices Figure 7 26 shows a block diagram of the frequency generator Frequency Output 100 kHz Timebase _____LL 2 Timebase e Frequency Generator o FREQ OUT Divisor 1 16 Figure 7 26 Frequency Generator Block Diagram The frequency generator generates the Frequency Output signal The Frequency Output signal is the Frequency Output Timebase divided by a number you select from 1 to 16 The Frequency Output Timebase can be either the 20 MHz Timebase divided by 2 or the 100 kHz Timebase The duty cycle of Frequency Output is 50 if the divider is either 1 or an even number For an odd divider suppose the divider is set to D In this case Frequency Output is low for D 1 2 cycles and high for D 1 2 cycles of the Frequency Output Timebase Figure 7 27 shows the output waveform of the frequency generator when the divider is set to 5 Frequency
175. ed by this version of NI DAQm x Base Select Start All Programs National Instruments NI DAQmx Base Documentation Readme The NI DAQmx Base VI Reference Help contains VI reference and general information about measurement concepts In LabVIEW select Help NI DAQmx Base VI Reference Help The NI DAQmx Base C Reference Help contains C reference and general information about measurement concepts Select Start All Programs National Instruments NI DAQm x Base Documentation C Function Reference Manual National Instruments Corporation xix M Series User Manual About This Manual LabVIEW If you are a new user use the Getting Started with LabVIEW manual to familiarize yourself with the LabVIEW graphical programming environment and the basic LabVIEW features you use to build data acquisition and instrument control applications Open the Getting Started with LabVIEW manual by selecting Start All Programs National Instruments LabVIEW LabVIEW Manuals or by navigating to the labview manuals directory and opening LV_Getting_Started pdf Use the LabVIEW Help available by selecting Help Search the LabVIEW Help in LabVIEW to access information about LabVIEW programming concepts step by step instructions for using LabVIEW and reference information about LabVIEW VIs functions palettes menus and tools Refer to the following locations on the Contents tab of the LabVIEW Help for information about NI DAQmx e Getting Started
176. efer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC Using a BNC Accessory with Connector 0 Connector 0 of your device is compatible with several BNC accessories e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use the SHC68 68 EPM shielded cable to connect Connector 0 of your DAQ device to BNC accessories Using a BNC Accessory with Connector 1 Connector 1 of your device is compatible with BNC 2115 BNC 2115 provides BNC connectivity to 24 of the differential 48 single ended analog input signals on Connector 1 You can use a SHC68 68 cable to connect to the BNC 2115 Screw Terminal National Instruments offers several styles of screw terminal connector blocks such as e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor make sure the switches are set properly National Instru
177. el 1 Ho AOS lt Channel 3 a Connector O Al 0 15 M Series Device Connector 1 Al 16 31 M Series Device Figure 5 2 Analog Output Connections Analog Output Timing Signals Figure 5 3 summarizes all of the timing options provided by the analog output timing engine PFI RTSI io PXI_STAR PFI RTSI Analog Comparison Event ao SampleClock PXI STAR Ctr n Internal Output Anal ao SampleClock naay cing ee Timebase Programmable o Clock 20 MHz Timebase Divider 100 kHz Timebase PXI_CLK10 ca Figure 5 3 Analog Output Timing Options M Series devices feature the following AO waveform generation timing signals e AO Start Trigger Signal e AO Pause Trigger Signal National Instruments Corporation 5 7 M Series User Manual Chapter 5 Analog Output e AO Sample Clock Signal e AO Sample Clock Timebase Signal AO Start Trigger Signal M Series User Manual Use the AO Start Trigger ao StartTrigger signal to initiate a waveform generation If you do not use triggers you can begin a generation with a software command Using a Digital Source To use ao StartTrigger specify a source and an edge The source can be one of the following signals e A software pulse e PFI lt 0 15 gt e RTSI lt 0 7 gt e ai ReferenceTrigger e ai StartTrigger e PXISTAR The source also can be one of several internal signals on your DAQ device Ref
178. el and amount of hysteresis The high threshold is the trigger level the low threshold is the trigger level minus the hysteresis For the trigger to assert the signal must first be below the low threshold then go above the high threshold The trigger stays asserted until the signal returns below the low threshold The output of the trigger detection circuitry is the internal Analog Comparison Event signal as shown in Figure 11 5 Then signal must go above high threshold before yo Comparison Event asserts ee a ae ee roo High threshold Hysteresis i Eeva O o is e STRESS O a REN Low threshold First signal must a i i i Level Hysteresis below low threshold Analog Comparison Event Figure 11 5 Analog Edge Triggering with Hysteresis Rising Slope Example Analog Edge Trigger with Hysteresis Falling Slope When using hysteresis with a falling slope you specify a trigger level and amount of hysteresis The low threshold is the trigger level the high threshold is the trigger level plus the hysteresis For the trigger to assert the signal must first be above the high threshold then go below the low threshold The trigger stays asserted until the signal returns above the high threshold The output of the trigger detection circuitry is the internal Analog Comparison Event signal as shown in Figure 11 6 National Instruments Corporation 11 5 M Series User Manual Chapter 11 Triggering
179. em To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI dev
180. en samples You also can use the Change Detection Event signal to trigger DO or counter generations Connecting Digital 1 0 Signals The DIO signals PO lt 0 31 gt P1 lt 0 7 gt and P2 lt 0 7 gt are referenced to D GND You can individually program each line as an input or output Figure 6 4 shows P1 lt 0 3 gt configured for digital input and P1 lt 4 7 gt configured for digital output Digital input applications include receiving TTL signals and sensing external device states such as the state of the switch shown in the figure Digital output applications include sending TTL signals and driving external devices such as the LED shown in the figure National Instruments Corporation 6 9 M Series User Manual Chapter 6 Digital I O TTL Signal 5 V MW to gt Switch 1 0 Connector M Series Device Figure 6 4 Digital 1 0 Connections A Caution Exceeding the maximum input voltage ratings which are listed in the specifications document for each M Series device can damage the DAQ device and the computer NI is not liable for any damage resulting from such signal connections Getting Started with DIO Applications in Software You can use the M Series device in the following digital I O applications e Static digital input e Static digital output e Digital waveform generation e Digital waveform acquisition e DI change detection
181. enable multimode scanning in LabVIEW use NI DAQmx Create Virtual Channel vi of the NI DAQmx API You must use a new VI for each channel or group of channels configured in a different input mode In Figure 4 3 channel 0 is configured in differential mode and channel is configured in RSE mode Differential Y DAGmx 4 Devi fail v Suu Al Voltage Al Voltage Figure 4 3 Enabling Multimode Scanning in LabVIEW Fi Dev1fai0 v To configure the input mode of your voltage measurement using the DAQ Assistant use the Terminal Configuration drop down list Refer to the DAQ Assistant Help for more information about the DAQ Assistant To configure the input mode of your voltage measurement using the NI DAQmx C API set the terminalConfig property Refer to the NI DAQmx C Reference Help for more information National Instruments Corporation 4 7 M Series User Manual Chapter 4 Analog Input Multichannel Scanning Considerations M Series devices can scan multiple channels at high rates and digitize the signals accurately However you should consider several issues when designing your measurement system to ensure the high accuracy of your measurements In multichannel scanning applications accuracy is affected by settling time When your M Series device switches from one AI channel to another AI channel the device configures the NI PGIA with the input range of the new channel The NI PGIA then amplifies
182. ence and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SH68 68 EP shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors O National Instruments Corporation A 77 M Series User Manual Appendix Device Specific Information Cables In most applications you can use the following cables SH68 68 EP A high performance cable with individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e R68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and fle
183. ence setting Connect the signal to one of AI lt 0 15 gt and connect the signal local ground reference to AI SENSE You also can connect the signal to one of AI lt 16 79 gt and connect the signal local ground reference to AI SENSE 2 AI SENSE or AI SENSE 2 is internally connected to the negative input of the NI PGIA Therefore the ground point of the signal connects to the negative input of the NI PGIA Any potential difference between the device ground and the signal ground appears as a common mode signal at both the positive and negative inputs of the NI PGIA and this difference is rejected by the amplifier If the input circuitry of a device were referenced to ground as it is in the RSE Refer to the Analog Input Ground Reference Settings section for an alternative NRSE signal routing configuration for NI 6225 devices M Series User Manual 4 24 ni com Chapter 4 Analog Input ground reference setting this difference in ground potentials would appear as an error in the measured voltage Using the DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Field Wiring Considerations Environmental noise can seriously affect the measurement accuracy of the device if you do not take proper care when running signal wires between signal sources and the device The following recommendat
184. endix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable 1 TB 2706 uses Connecto
185. ent AI Reference Trigger AI Sample Clock AI Start Trigger AO Sample Clock AO Start Trigger Counter n Source Counter n Gate Counter n Internal Output Frequency Output PXI_STAR RTSI lt 0 7 gt Analog Comparison Event Change Detection Event DI Sample Clock DO Sample Clock Note Signals with a are inverted before being driven to a terminal Using PFI Terminals as Static Digital I Os Each PFI can be individually configured as a static digital input or a static digital output When a terminal is used as a static digital input or output it is called P1 x or P2 x On the I O connector each terminal is labeled PFI x P1 x or PFI x P2 x In addition M Series devices have up to 32 lines of bidirectional DIO signals National Instruments Corporation 8 3 M Series User Manual Chapter 8 PFI Connecting PFI Input Signals All PFI input connections are referenced to D GND Figure 8 2 shows this reference and how to connect an external PFI 0 source and an external PFI 2 source to two PFI terminals PFIO PFI 2 PFI O PFI 2 Source Source D GND xi 1 0 Connctor M Series Device Figure 8 2 PFI Input Signals Connections PFI Filters You can enable a programmable debouncing filter on each PFI RTSI or PXI_STAR signal When the filters are enabled your device samples the input on each rising edge of a filter clock M Series devi
186. entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors National Instruments Corporation A 99 M Series User Manual Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices
187. er Example Enabling filters introduces jitter on the input signal For the 125 ns and 6 425 us filter settings the jitter is up to 25 ns On the 2 55 ms setting the jitter is up to 10 025 us When a PFI input is routed directly to RTSL or a RTSI input is routed directly to PFI the M Series device does not use the filtered version of the input signal Refer to the KnowledgeBase document Digital Filtering with M Series for more information about digital filters and counters To access this KnowledgeBase go to ni com info and enter the info code rddfms M Series User Manual Chapter 8 PFI 1 0 Protection Each DIO and PFI signal is protected against overvoltage undervoltage and overcurrent conditions as well as ESD events However you should avoid these fault conditions by following these guidelines e If you configure a PFI or DIO line as an output do not connect it to any external signal source ground signal or power supply e Ifyou configure a PFI or DIO line as an output understand the current requirements of the load connected to these signals Do not exceed the specified current output limits of the DAQ device NI has several signal conditioning solutions for digital applications requiring high current drive e If you configure a PFI or DIO line as an input do not drive the line with voltages outside of its normal operating range The PFI or DIO lines have a smaller operating range than the AI signals e Treat t
188. er the trigger The Reference Trigger signals the time when the AI timing engine starts counting the number of posttrigger conversions to take before stopping The Reference Trigger can come from external or internal sources and its source is selected with a multiplexer Its output is called the Selected Reference Trigger M Series User Manual B 14 ni com Appendix B Timing Diagrams Selected Reference Trigger Reference Trigger POUT Terminal Terminal Terminal Le gt Start gt Terminal D Selected Start gt O gt RTSI Terminal S Selected Pause Trigger e Pp Pause Trigger SI Start Terminal gt lt Sl ane Sample Clock Timebase Counter Te Sync Sample Clock Timebase Bie OF D gt Terminal D SI_TC y j p_Al_Convert ec SI2 Convert Clock Timebase Counter 8 2 TC Block T Sync Convert Clock Timebase Start oc 1 Terminal gt 5 Selected Sample Clock Terminal e D Figure B 13 Reference Trigger and the Analog Input Timing Engine t22 Selected Reference Trigger gt 1 ba gt t Sync Convert Clock Timebase 28 tos om Reference Trigger tog gt gt bo POUT Figure B 14 Reference Trigger Timing Diagram National Instruments Corporation B 15 M Series User Manual Appendix B Tim
189. er the reload occurs the counter continues to count as before The figure illustrates channel Z reload with X4 decoding ChA _ ChB 237 ChZ Max Timebase FL Counter Value AG G Y Y2 Xa Y4 A B Z 0 0 1 Figure 7 18 Channel Z Reload with X4 Decoding Measurements Using Two Pulse Encoders The counter supports two pulse encoders that have two channels channels A and B The counter increments on each rising edge of channel A The counter decrements on each rising edge of channel B as shown in Figure 7 19 ChA ChB Counter Value 2 X 3 X 4 X 5 Y 4 X 3 X 4 Figure 7 19 Measurements Using Two Pulse Encoders National Instruments Corporation 7 17 M Series User Manual Chapter 7 Counters For information about connecting counter signals refer to the Default Counter Timer Pinouts section Two Signal Edge Separation Measurement Two signal edge separation measurement is similar to pulse width measurement except that there are two measurement signals Aux and Gate An active edge on the Aux input starts the counting and an active edge on the Gate input stops the counting You must arm a counter to begin a two edge separation measurement After the counter has been armed and an active edge occurs on the Aux input the c
190. er to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information You also can specify whether the waveform generation begins on the rising edge or falling edge of ao StartTrigger Using an Analog Source When you use an analog trigger source the waveform generation begins on the first rising edge of the Analog Comparison Event signal Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing AO Start Trigger Signal to an Output Terminal You can route ao StartTrigger out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal The output is an active high pulse PFI terminals are configured as inputs by default 5 8 ni com Chapter 5 Analog Output AO Pause Trigger Signal Use the AO Pause trigger signal ao PauseTrigger to mask off samples in a DAQ sequence That is when ao PauseTrigger is active no samples occur ao PauseTrigger does not stop a sample that is in progress The pause does not take effect until the beginning of the next sample When you generate analog output signals the generation pauses as soon as the pause trigger is asserted If the source of your sample clock is the onboard clock the generation resumes as soon as the pause trigger is deasserted as shown in Figure 5 4 Pause Trigger LL Sample Clock Figure 5 4 ao PauseTrigger with the Onboard Clock Source If yo
191. er to the SCX7 Advisor available by going to ni com info and entering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors A 30 ni com App
192. ered Pulse Width Measurement 7 5 Period Measurement gt ss ii ono 7 6 Single Period Measurement 7 7 Buffered Period Measurement 7 7 Semi Period Measurement n niron aA aieeaa E KREY 7 8 Single Semi Period Measurement 7 8 Buffered Semi Period Measurement 7 9 Frequency Measurement erered earna e a A Ee E E ne ETTE 7 9 Method 1 Measure Low Frequency with One Counter 7 10 Method 1b Measure Low Frequency with One Counter Averaged ss 7 10 Method 2 Measure High Frequency with Two Counters 7 11 Method 3 Measure Large Range of Frequencies Using TWO Cote cinco dd 7 12 Choosing a Method for Measuring Frequency s src 7 13 Position Measurement tend seen ste er eee 7 15 Measurements Using Quadrature Encoders ooonconocncccnoncnncnnncnncanccnnos 7 15 Measurements Using Two Pulse Encoders cee eeeeseeeeeereeees 7 17 Two Signal Edge Separation Measurement 7 18 Single Two Signal Edge Separation Measurement eee 7 18 Buffered Two Signal Edge Separation Measurement ooconccnncnnncnnnn 7 19 Counter Output Applications sise 7 20 Simple Pulse Generation ss 7 20 Single Pulse G n ration circa trata iia 7 20 Single Pulse Generation with Start Trigger 7 20 National Instruments Corporation xi M Series User Manual Contents Retriggerable Single Pulse Generation 7 21 Pu
193. erential analog input channel on Connector 1 is routed on a twisted pair on the SHC68 68 cable e RC68 68 A highly flexible unshielded ribbon cable TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 62 ni com Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 63 M Series User Manual Appendix Device Specific Information NI 6259 The following sections contain information about the PCI PCle PXI 6259 USB 6259 and USB 6259 Mass Termination devices PCI PCle PXI 6259 PCI PCle PXI 6259 Pinout Figure A 15 shows the pinout of the PCI PCle PXI 6259 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the
194. eries User Manual Device Specific Information NI 6221 37 Pin Pinout Figure A 3 shows the pinout of the PCI 6221 37 pin device For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information AIO Al9 Al GND Al 10 Al3 Al 4 Al 13 Al SENSE Al 14 Al 15 AO GND AO 0 PFI 0 P1 0 D GND PFI 3 P1 3 D GND PFI 6 P1 6 D GND PO 1 NC No Connect Pee 1 2 20 AI 8 Ral 21 Al1 4 22 Al2 rst 23 Al 11 6 24 Al GND 25 AI 12 u 26 AI5 27 Al6 9 28 AI7 10 1 29 NC 30 AO 1 12 31 AO GND 2 32 PFI 1 P1 1 1 33 PFI 2 P1 2 15 34 PFI 4 P1 4 ue 35 PFI 5 P1 5 z 36 PFI 7 P1 7 19 37 P0 0 ue Figure A 3 NI 6221 37 Pin Pinout Table A 3 Default NI DAQmx Counter Timer Pins Counter Timer Signal Default Pin Number Name CTR 0 SRC 13 PFI 0 CTR 0 GATE 32 PFI 1 CTR 0 AUX 33 PFI 2 CTR 0 OUT 17 PFI 6 CTROA 13 PFI 0 CTROZ 32 PFI 1 A 12 ni com Appendix Device Specific Information Table A 3 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTROB 33 PFI 2 CTR 1 SRC 15 PFI 3 CTR 1 GATE 34 PFI 4 CTR 1 AUX 35 PFI 5 CTR 1 OUT 36 PFI 7 CTRIA 15 PFI 3 CTR1Z 34 PFI 4 CTR1B 35
195. ering the info code rdscav for more information A 48 ni com Appendix Device Specific Information BNC You can use the SH68 68 EP shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SH68 68 EP shielded cable to connect an M Series device to a connector block such as the following CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block Cables In most applications you can use the following cables SH68 68 EP A high performance cable with individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually
196. ernal timing analog input B 6 interrupt request as a transfer method 10 4 IRQ as a transfer method 10 4 changing data transfer methods 10 5 K KnowledgeBase E 1 L LabVIEW documentation xx LabWindows CVI documentation xx LED patterns USB 6251 A 44 USB 6251 Mass Termination A 50 M Series User Manual 1 8 USB 6259 A 72 USB 6259 Mass Termination A 78 low impedance sources 4 8 lowpass filter analog input 4 4 M Series and E Series accessories D 1 differences from E Series D 1 information A 1 migrating applications to D 1 pinout comparison versus E Series 3 4 specifications xxi A 1 upgrading to D 1 Measurement Studio documentation xxi measurements buffered period 7 7 buffered pulse width 7 5 buffered semi period 7 9 buffered two signal edge separation 7 19 choosing frequency 7 13 frequency 7 9 period 7 6 position 7 15 pulse width 7 5 semi period 7 8 single period 7 7 single pulse width 7 5 single semi period 7 8 single two signal edge separation 7 18 two signal edge separation 7 18 using quadrature encoders 7 15 using two pulse encoders 7 17 measuring high frequency with two counters 7 11 large range of frequencies using two counters 7 12 low frequency with one counter 7 10 averaged 7 10 methods data transfer 10 4 ni com minimizing glitches on the output signal 5 4 output signal glitches C 3 voltage step between adjacent channels 4 10 multichannel scanning
197. es or cycles 1 Software A memory location used to store a count of certain occurrences 2 Hardware A circuit that counts events When it refers to an instrument it refers to a frequency counter A circuit that counts external pulses or clock pulses timing Digital ground signal A serial connector Digital to Analog Converter An electronic device often an integrated circuit that converts a digital number into a corresponding analog voltage or current In the instrumentation world DACs can be used to generate arbitrary waveform shapes defined by the software algorithm that computes the digital data pattern which is fed to the DAC National Instruments Corporation G 5 M Series User Manual Glossary DAQ DAQ device DAQ STC2 data acquisition data transfer dB DC device M Series User Manual 1 Data acquisition The process of collecting and measuring electrical signals from sensors transducers and test probes or fixtures and inputting them to a computer for processing 2 Data acquisition The process of collecting and measuring the same kinds of electrical signals with A D and or DIO devices plugged into a computer and possibly generating control signals with D A and or DIO devices in the same computer A device that acquires or generates data and can contain multiple channels and conversion devices DAQ devices include plug in devices PCMCIA cards and DAQPad devices which connect to
198. es there are several ways to synchronize multiple devices depending on your application nye Note RTSI is not supported on USB devices To synchronize multiple devices to a common timebase choose one device the initiator to generate the timebase The initiator device routes its 10 MHz reference clock to one of the RTSI lt 0 7 gt signals All devices including the initiator device receive the 10 MHz reference clock from RTSI This signal becomes the external reference clock A PLL on each device generates the internal timebases synchronous to the external reference clock On PXI systems you also can synchronize devices to PXI_CLK10 In this application the PXI chassis acts as the initiator Each PXI module routes PXI_CLK10 to its external reference clock Another option in PXI systems is to use PXI_STAR The Star Trigger controller device acts as the initiator and drives PXI_STAR with a clock signal Each target device routes PXI_STAR to its external reference clock Once all of the devices are using or referencing a common timebase you can synchronize operations across them by sending a common start trigger out across the RTSI bus and setting their sample clock rates to the same value National Instruments Corporation 9 3 M Series User Manual Chapter 9 Digital Routing and Clock Generation Real Time System Integration RTSI Real Time System Integration RTS is set of bused signals among devices that allow you to
199. es devices On M Series devices you 40 CTR 1 OUT PFI 13 P2 5 also can route many other internal timing signals to each GPCTR1_OUT terminal 45 EXT STROBE PFI 10 P2 2 On M Series devices you also can use these terminals as additional PFI inputs to drive internal timing signals 46 AI HOLD COMP PFI 11 P2 3 SCANCLK On M Series devices you also can use these terminals as digital I O signals Also refer to Chapter 8 PFI 3 PFI 9 CTR 0 GATE PFI 9 P2 1 As a PFI input the functionality of E Series and GPCTRO_GATE M Series devices is similar for these terminals 5 PFI 6 AO START PFI 6 P1 6 E Series devices can drive each of these terminals with TRIG WFTRIG one particular internal timing signal 6 PFI 5 AO SAMP CLK PFI 5 P1 5 M Series devices can drive each terminal with the same UPDATE signal as on E Series devices On M Series devices you also can route many other internal timing signals to each 10 PFI 1 AI REF TRIG PFI 1 P1 1 terminal TRIG2 On M Series devices you also can use these terminals as 37 PFI 8 CTR 0 SRC PFI 8 P2 0 digital I O signals GPCTRO_SOURCE A Also refer to Chapter 8 PFI 38 PFI 7 AI SAMP CLK PFI 7 P1 7 STARTSCAN 41 PFI 4 CTR 1 GATE PFI 4 P1 4 GPCTR1_GATE 42 PFI 3 CTR 1 SRC PFI 3 P1 3 GPCTR1_SOURCE 43 PFI 2 AI CONV CLK PFI 2 P1 2 CONVERT M Series User Manual ni com Chapter 3 Connector Information Table 3 2 M Series and E Series Device Pinout Comparison Continued M Series
200. es than non buffered acquisitions because data is moved in large blocks rather than one point at a time One property of buffered I O operations is the sample mode The sample mode can be either finite or continuous Finite sample mode acquisition refers to the acquisition of a specific predetermined number of data samples Once the specified number of samples has been written out the generation stops If you use a reference trigger you must use finite sample mode Continuous acquisition refers to the acquisition of an unspecified number of samples Instead of acquiring a set number of data samples and stopping a continuous acquisition continues until you stop the operation Continuous acquisition is also referred to as double buffered or circular buffered acquisition If data cannot be transferred across the bus fast enough the FIFO becomes full New acquisitions will overwrite data in the FIFO before it can be transferred to host memory The device generates an error in this case With continuous operations if the user program does not read data out of the PC buffer fast enough to keep up with the data transfer the buffer could reach an overflow condition causing an error to be generated Non Buffered In non buffered acquisitions data is read directly from the FIFO on the device Typically hardware timed non buffered operations are used to read single samples with known time increments between them 4 12 ni com Chapter 4 A
201. es the M Series device to begin generating AI Sample clock pulses which in turn generates DI Sample clock pulses as shown in Figure 6 2 PFI 1 Al Start Trigger initiates Al Start Trigger a Al Sample Clock and DI Sample Clock Al Sample Clock N DI Sample Clock Figure 6 2 Digital Waveform Triggering Similarly if you are using AO Sample Clock as the source of DI Sample Clock then AO Start Trigger initiates both AO and DI operations If you are using a Counter output as the source of DI Sample Clock the counter s start trigger enables the counter which drives DI Sample Clock If you are using an external signal such as PFI x as the source for DI Sample Clock or DO Sample Clock you must trigger that external signal Digital Waveform Acquisition You can acquire digital waveforms on the Port 0 DIO lines The DI waveform acquisition FIFO stores the digital samples M Series devices have a DMA controller dedicated to moving data from the DI waveform acquisition FIFO to system memory The DAQ device samples the DIO lines on each rising or falling edge of a clock signal di SampleClock National Instruments Corporation 6 3 M Series User Manual Chapter 6 Digital I O You can configure each DIO line to be an output a static input or a digital waveform acquisition input DI Sample Clock Signal M Series User Manual Use the DI Sample Clock di SampleClock
202. esults in four increments or decrements as shown in Figure 7 17 ChB Counter Value ChA AA E E M Series User Manual Figure 7 17 X4 Encoding Channel Z Behavior Some quadrature encoders have a third channel channel Z which is also referred to as the index channel A high level on channel Z causes the counter to be reloaded with a specified value in a specified phase of the quadrature cycle You can program this reload to occur in any one of the four phases in a quadrature cycle 7 16 ni com Chapter 7 Counters Channel Z behavior when it goes high and how long it stays high differs with quadrature encoder designs You must refer to the documentation for your quadrature encoder to obtain timing of channel Z with respect to channels A and B You must then ensure that channel Z is high during at least a portion of the phase you specify for reload For instance in Figure 7 18 channel Z is never high when channel A is high and channel B is low Thus the reload must occur in some other phase In Figure 7 18 the reload phase is when both channel A and channel B are low The reload occurs when this phase is true and channel Z is high Incrementing and decrementing takes priority over reloading Thus when the channel B goes low to enter the reload phase the increment occurs first The reload occurs within one maximum timebase period after the reload phase becomes true Aft
203. example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on N consecutive edges the low to high transition is propagated to the rest of the circuit The value of N depends on the filter setting refer to Table 9 3 Table 9 3 Filters N Filter Clocks Pulse Width Pulse Width Needed to Pass Guaranteed to Pass Guaranteed to Not Filter Setting Signal Filter Pass Filter 125 ns 5 125 ns 100 ns 6 425 us 257 6 425 us 6 400 us 2 55 ms 101 800 2 55 ms 2 54 ms Disabled National Instruments Corporation 9 9 M Series User Manual Chapter 9 Digital Routing and Clock Generation The filter setting for each input can be configured independently On power up the filters are disabled Figure 9 4 shows an example of a low to high transition on an input that has its filter set to 125 ns N 5 RTSI PFI or PXI_STAR Terminal Filter Clock 40 MHz Filtered Input Filtered input goes high when terminal is sampled 1 1 2 3 4 1 2 3 4 5 high on five consecutive filter clocks M Series User Manual Figure 9 4 Filter Example Enabling filters introduces jit
204. fault Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 A 86 ni com Appendix Device Specific Information Table A 21 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTR OB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR1B 46 PFI 11 B Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6281 Specifications Refer to the NI 628x Specifications for more detailed information about the NI 6281 device NI 6281 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI 6281 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or a
205. fer to the specifications for your device Note that this terminal is a no connect on some E Series and M Series devices 39 D GND PFI 15 P2 7 OnE Series devices this is one of the D GND terminals On M Series devices this is the PFI 15 P2 7 terminal In NI DAQmx National Instruments has revised terminal names so they are easier to understand and more consistent among National Instruments hardware and software products This column shows the NI DAQmx terminal names Traditional NI DAQ Legacy terminal names are shown in parentheses Refer to Appendix D Upgrading from E Series to M Series for more information about the differences between these two device families National Instruments Corporation 3 5 M Series User Manual Chapter 3 Connector Information 5 V Power Source The 5 V terminals on the I O connector supply 5 V referenced to D GND Use these terminals to power external circuitry A self resetting fuse protects the supply from overcurrent conditions The fuse resets automatically within a few seconds after the overcurrent condition is removed The power rating on most devices is 4 65 to 5 25 VDC at 1 A Refer to the specifications document for your device to obtain the device power rating 3 Note The NI 6221 37 pin device does not have a 5 V terminal 3 Note PCI Express Devices The PCIe 6251 and PCIe 6259 devices supply less than 1 A of 5 V power unless you use the disk dr
206. ference Direction Description D GND Digital Ground D GND supplies the reference for P0 lt 0 31 gt PFI lt 0 15 gt P1 P2 and 5 V All three ground references AI GND AO GND and D GND are connected on the device P0 lt 0 31 gt DGND Input or Port 0 Digital VO Channels 0 to 31 You can Output individually configure each signal as an input or output APFI lt 0 1 gt AO GND AIGND Input Analog Programmable Function Interface Channels 0 to 1 Each APFI signal can be used as AO External Reference inputs for AO lt 0 3 gt AO External Offset input or as an analog trigger input APFI lt 0 1 gt are referenced to AI GND when they are used as analog trigger inputs APFI lt 0 1 gt are referenced to AO GND when they are used as AO External Offset or Reference inputs These functions are not available on all devices Refer to the specifications for your device 5 V D GND Input or 5 V Power Source These terminals provide a fused Output 5 V power source PFI lt 0 7 gt P1 lt 0 7 gt D GND Input or Programmable Function Interface or Digital I O PFI lt 8 15 gt P2 lt 0 7 gt Output Channels 0 to 7 and Channels 8 to 15 Each of these terminals can be individually configured as a PFI terminal or a digital I O terminal As an input each PFI terminal can be used to supply an external source for AI AO DI and DO timing signals or counter timer inputs As a PFI output you can route man
207. fic Information NI 6255 NI 6255 Pinout Figure A 14 shows the pinout of the NI 6255 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 58 ni com Appendix Device Specific Information de ALO 68 34 Als Al71 1 35 Al79 AI GND 67 33 Al1 AI 78 2 36 A170 AI19 66 32 AI GND AI 69 3 37 A177 AI 2 65 31 A110 aa Al 68 4 38 A176 AI GND 64 30 A13 E e AL 75 5 39 A167 AI 11 63 29 AI GND ee ee Al 66 6 40 A174 Al SENSE 62 28 A14 H ur Al 65 7 4 A173 Al 12 61 27 AI GND 3 Zs AI 72 8 42 A164 Al5 60 26 A113 o 0 AIGND 9 43 Al GND AI GND 59 25 Al6 Al 55 10144 ales AI 14 58 24 AI GND Al 54 11 45 A162 AI7 57 23 Al15 TERMINAL 68 fi Si TERMINAL 35 Al61 12 46 Al53 AI GND 56 22 AOO AI 52 13 47 160 AO GND 55 21 AO 1 TERMINAL 34
208. formation or they might contain different signals See MIO To assign more than one signal to a channel See also mux Multiplexer A set of semiconductor or electromechanical switches arranged to select one of many inputs to a single output The majority of DAQ cards have a multiplexer on the input which permits the selection of one of many channels at a time A switching device with multiple inputs that sequentially connects each of its inputs to its output typically at high speeds in order to measure several signals with a single analog input channel National Instruments The driver software needed to use National Instruments DAQ devices and SCXI components Some devices use Traditional NI DAQ Legacy others use NI DAQmx G 12 ni com NI DAQmx NI PGIA non referenced signal sources NRSE 0 offset P PCI PCI Express PCIe Glossary The latest NI DAQ driver with new VIs functions and development tools for controlling measurement devices The advantages of NI DAQmx over earlier versions of NI DAQ include the DAQ Assistant for configuring channels and measurement tasks for your device for use in LabVIEW LabWindows CVI and Measurement Studio increased performance such as faster single point analog I O and a simpler API for creating DAQ applications using fewer functions and VIs than earlier versions of NI DAQ See instrumentation amplifier Signal sources with voltage signals that are not connec
209. from to a device or memory on the bus while the processor does something else DMA is the fastest method of transferring data to from computer memory Performs the transfers between memory and I O devices independently of the CPU Software unique to the device or type of device and includes the set of commands the device accepts A standard architecture for instrumentation class multichannel data acquisition devices A technique that locates an edge of an analog signal such as the edge of a square wave Electrically Erasable Programmable Read Only Memory ROM that can be erased with an electrical signal and reprogrammed Some SCXI modules contain an EEPROM to store measurement correction coefficients M Series User Manual Glossary encoder EXTCLK external trigger EXTREF FIFO filter filtering M Series User Manual A device that converts linear or rotary displacement into digital or pulse signals The most popular type of encoder is the optical encoder which uses a rotating disk with alternating opaque areas a light source and a photodetector External clock signal A voltage pulse from an external source that causes a DAQ operation to begin External reference signal First In First Out memory buffer A data buffering technique that functions like a shift register where the oldest values first in come out first Many DAQ products and instruments use FIFOs to buffer digital data from an A D conve
210. g Circuitry Figure B 39 and Tables B 24 and B 25 describe the digital waveform generation timing delays and requirements Your inputs must meet the requirements to ensure proper behavior i ho e a ti i ty lt gt a gt PFI RTSI A AO ES or PXILSTAR i ho he gt gt PFI_i RTSL i a E or PXI_STAR i tig tig lt gt lt gt DO Sample Clock i tia gt PO X i ts te A gt PFI Output Figure B 39 Digital Waveform Acquisition Timing Delays National Instruments Corporation B 35 M Series User Manual Appendix B Timing Diagrams Table B 24 DO Timing Delays Timing Delay From To Min ns Max ns ty PFI PFI_i 5 2 6 2 18 2 22 0 RTSI RTSLi 2 0 2 5 5 0 6 0 PXI_STAR PXI_STAR_i 1 5 3 5 13 PFI_i RTSI_i PXI_STAR_i DO Sample 3 5 9 5 or other internal signal Clock ti4 DO Sample Clock PO 75 27 5 tus DO Sample Clock PFI output 8 0 29 8 tie PFI output high PFI output Two periods of 80 MHz Three periods of 80 MHz low Timebase Timebase The delay ranges given for PFI and RTSI represent the fastest and slowest terminal routing within the trigger group for a given condition maximum or minimum timing This difference can be useful when two external signals will be used together and the relative timing between the signals is important When DO Sample Clock is routed to a PFI output pin the pulse width of
211. g Input ai StartTrigger ai ReferenceTrigger n a ai SampleClock sooner FU IT j Ir Scan Counter 3 Figure 4 15 Pretriggered Data Acquisition Example If an ai ReferenceTrigger pulse occurs before the specified number of pretrigger samples are acquired the trigger pulse is ignored Otherwise when the ai ReferenceTrigger pulse occurs the sample counter value decrements until the specified number of posttrigger samples have been acquired M Series devices feature the following analog input timing signals e AI Sample Clock Signal e AI Sample Clock Timebase Signal e Al Convert Clock Signal e AI Convert Clock Timebase Signal e AI Hold Complete Event Signal e AI Start Trigger Signal e AIl Reference Trigger Signal e AT Pause Trigger Signal Al Sample Clock Signal M Series User Manual Use the AI Sample Clock ai SampleClock signal to initiate a set of measurements Your M Series device samples the AI signals of every channel in the task once for every ai SampleClock A measurement acquisition consists of one or more samples You can specify an internal or external source for ai SampleClock You also can specify whether the measurement sample begins on the rising edge or falling edge of ai SampleClock 4 28 ni com Chapter 4 Analog Input Using an Internal Source One of the following internal signals can dr
212. g to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector e BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors National Instruments Corporation A 93 M Series User Manual Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI
213. ge instead of APFI lt 0 1 gt as your trigger source The DAQ device does not amplify the APFI lt 0 1 gt signals When using an AI channel the NI PGIA amplifies the AI channel signal before driving the analog trigger circuitry If you configure the AI channel to have a small input range you can trigger on very small voltage changes in the input signal Software calibrate the analog trigger circuitry The propagation delay from when a valid trigger condition is met to when the analog trigger circuitry emits the Analog Comparison Event may have an impact on your measurements if the trigger signal has a high slew rate If you find these conditions have a noticeable impact on your measurements you can perform software calibration on the analog trigger circuitry by configuring your task as normal and applying a known signal for your analog trigger Comparing the observed results against the expected results you can calculate the necessary offsets to apply in software to fine tune the desired triggering behavior 11 7 M Series User Manual Device Specific Information This appendix contains device pinouts specifications cable and accessory choices and other information for the following M Series devices e NI6220 e NI6221 e NI6224 e NI6225 e NI6229 e NI6250 e NI6251 e NI6254 e NI6255 e NI6259 e NI6280 e NI6281 e NI6284 e NI6289 To obtain documentation for devices not listed here refer to ni com manuals Nationa
214. gger e ai ConvertClock e ai SampleClock e ai PauseTrigger e ao SampleClock e a0 StartTrigger e ao PauseTrigger e 10 MHz Reference Clock e Counter n Source Gate Z Internal Output e Change Detection Event e Analog Comparison Event e FREQ OUT e PFI lt 0 5 gt National Instruments Corporation 9 5 M Series User Manual Chapter 9 Digital Routing and Clock Generation B Note Signals with a are inverted before being driven on the RTSI terminals Using RTSI Terminals as Timing Input Signals RTSI Filters You can use RTSI terminals to route external timing signals to many different M Series functions Each RTSI terminal can be routed to any of the following signals e AI Convert Clock e ATI Sample Clock e AI Start Trigger e AI Reference Trigger AI Pause Trigger e AI Sample Clock Timebase e AO Start Trigger e AO Sample Clock e AO Sample Clock Timebase e AO Pause Trigger e Counter input signals for either counter Source Gate Aux HW_Arm A B or Z e DI Sample Clock DO Sample Clock Most functions allow you to configure the polarity of PFI inputs and whether the input is edge or level sensitive You can enable a programmable debouncing filter on each PFI RTSI or PXI_STAR signal When the filters are enabled your device samples the input on each rising edge of a filter clock M Series devices use an onboard oscillator to generate the filter clock with a 40 MHz frequency 8 Note NI DAQ
215. he DAQ device as you would treat any static sensitive device Always properly ground yourself and the equipment when handling the DAQ device or connecting to it Programmable Power Up States At system startup and reset the hardware sets all PFI and DIO lines to high impedance inputs by default The DAQ device does not drive the signal high or low Each line has a weak pull down resistor connected to it as described in the specifications document for your device NI DAQmx 7 4 and later supports programmable power up states for PFI and DIO lines Software can program any value at power up to the PO P1 or P2 lines The PFI and DIO lines can be set as e A high impedance input with a weak pull down resistor default e An output driving a 0 e An output driving a 1 Refer to the NI DAQmx Help or the LabVIEW 8 x Help for more information about setting power up states in NI DAQmx or MAX 3 Note When using your M Series device to control an SCXI chassis DIO lines 0 1 2 and 4 are used as communication lines and must be left to power up in the default high impedance state to avoid potential damage to these signals M Series User Manual 8 6 ni com Digital Routing and Clock Generation The digital routing circuitry has the following main functions e Manages the flow of data between the bus interface and the acquisition generation sub systems analog input analog output digital I O and the counters The digital routing cir
216. he RTSI bus on a PXI M Series device is available in a PXI chassis but not in a CompactPCI chassis The CompactPCI specification permits vendors to develop sub buses that coexist with the basic PCI interface on the CompactPCI bus Compatible operation is not guaranteed between CompactPCI devices with different sub buses nor between CompactPCI devices with sub buses and PXI The standard implementation for CompactPCI does not include these sub buses The PXI M Series device works in any standard CompactPCI chassis adhering to the PICMG CompactPCI 2 0 R3 0 core specification PXI specific features are implemented on the J2 connector of the CompactPCI bus The PXI device is compatible with any CompactPCI chassis with a sub bus that does not drive the lines used by that device Even if the sub bus is capable of driving these lines the PXI device is still compatible as long as those terminals on the sub bus are disabled by default and never enabled A Caution Damage can result if these lines are driven by the sub bus NI is not liable for any damage resulting from improper signal connections 1 For some PXI M Series devices there are two variants one that will work in PXI hybrid slots and one that supports local bus for SCXI control when the device is in the right most slot Refer to the device specifications for more information National Instruments Corporation 10 3 M Series User Manual Chapter 10 Bus Interface Data Transfer Methods
217. he device is configured but there is no activity over the bus On On The device is configured and there is activity over the bus Blinking On USB 6259 Fuse Replacement USB 6259 devices have a replaceable 2A 250V 5 x 20 mm fuse To remove the fuse from the USB 6251 complete the following steps 1 Loosen the four flathead Phillips screws that attach the back lid to the enclosure and remove the lid 2 Replace the fuse while referring to Figure A 17 for the fuse location Fuse National Instruments Corporation Figure A 17 USB 6259 Fuse Location 3 Replace the lid and screws A 73 M Series User Manual Appendix Device Specific Information USB 6259 Mass Termination USB 6259 Mass Termination Pinout Figure A 18 shows the pinout of the USB 6259 Mass Termination device For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 74 ni com Appendix Device Specific Information
218. he start and pause triggers For counter input operations you can use the arm start trigger to have start trigger like behavior The arm start trigger can be used for synchronizing multiple counter input and output tasks When using an arm start trigger the arm start trigger source is routed to the Counter n HW Arm signal For counter output operations a start trigger can be configured to begin a finite or continuous pulse generation Once a continuous generation has triggered the pulses continue to generate until you stop the operation in software For finite generations the specified number of pulses is generated and the generation stops unless you use the retriggerable attribute When you use this attribute subsequent start triggers cause the generation to restart When using a start trigger the start trigger source is routed to the Counter n Gate signal input of the counter Counter input operations can use the arm start trigger to have start trigger like behavior You can use pause triggers in edge counting and continuous pulse generation applications For edge counting acquisitions the counter stops counting edges while the external trigger signal is low and resumes when the signal goes high or vice versa For continuous pulse generations the counter stops generating pulses while the external trigger signal is low and resumes when the signal goes high or vice versa When using a pause trigger the pause trigger source is route
219. he timing of this signal is described in relation to this common point The Convert Clock Timebase and Sample Clock Timebase can be asynchronous from each other Selected Reference Trigger Reference Trigger Terminal gt lt E 99 De Terminal Start Terminal D e Terminal Selected Start gt gt RTSI Terminal Y Pause Trigger SI Start Terminal Counter Block gt e gt Terminal gt SI_TC p_Al_Convert SZ s2 TC Block Sync Convert Clock Timebase 1 Start Terminal Selected Sample Clock eT Terminal Figure B 4 Al Timing Clocks and the Analog Input Timing Engine National Instruments Corporation B 7 M Series User Manual Appendix B Timing Diagrams ty ty t3 i PLILILILILILJ gt Sample i Clock Timebase 1 gt eb Sync Sample Clock Timebase te ie Convert Clock Timebase l ty 4 Sync Convert i Clock Timebase Figure B 5 Al Timing Clocks Timing Diagram Table B 2 Al Timing Clocks Timing Timing Description Line Min ns Max ns ty Minimum Pulse Width 12 5 t3 Minimum Period 50 0 t4 Delay t
220. hielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 6 ni com Appendix Device Specific Information NI 6221 The following sections contain information about the NI 6221 68 pin and NI 6221 37 pin devices NI 6221 68 Pin NI 6221 68 Pin Pinout Figure A 2 shows the pinout of the PCI PXI 6221 68 pin device For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information B Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 7 M Series User Manual Appendix Device Specific Information M Series User Manual AIO AI GND AI9 Al2 Al GND Al 11 Al SENSE Al 12 AI5 Al GND Al 14
221. i ys sri e ddl ed deb ae 4 1 Analog Input Rangement tentes 4 2 Analog Input Lowpass Filtra naaa 4 4 Analog Input Ground Reference Settings ss 4 5 Configuring AI Ground Reference Settings in Software 4 7 Multichannel Scanning Considerations oooconocnncconnnoncnnccnncnn cnn cono nnnonnnonncnn nono nn con ncncnnno 4 8 Use Low Impedance Sources 4 8 Use Short High Quality Cabling ss 4 9 Carefully Choose the Channel Scanning Order 4 9 Avoid Switching from a Large to a Small Input Range o o 4 9 Insert Grounded Channel between Signal Channels 0 0 4 10 Minimize Voltage Step between Adjacent Channels 0 4 10 Avoid Scanning Faster Than Necessary oooococnnonconnonnnoncnnncnnconccononnnonncnnncnncrnnos 4 10 Example lui 4 10 Example Lui it rela 4 11 Analog Input Data Acquisition Methods 4 11 Software Timed Acquisitions ss 4 11 Hardware Timed Acquisitions s 4 11 Buffered EE RE TRE SN AN M LE HAE 4 12 Non Butlered 212 si ns iii eee ab nr an i aed 4 12 Analog Input Tri S Seri ste sce tied een ev caved sla ne PE serein 4 13 Connecting Analog Input Signals ss 4 13 Connecting Floating Signal Sources ss 4 15 What Are Floating Signal Sources oo cece cece eseeeeeeseeseeesecseeeseeseeeaeeaeenaes 4 15 When to Use Differential Connectio
222. ications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable Use Connector 0 of your M Series device to control SCXI NI DAQ 7 4 and later supports SCXI in parallel mode on Connector 1 Note When using Connector 1 in parallel mode with SCXI modules that support track and hold you must programmatically disable track and hold M Series User Manual A 54 ni com Appendix Device Specific Information You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog
223. ices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required A 36 ni com Appendix Device Specific Information Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 37 M Series User Manual Appendix Device Specific Information NI 6251 The following sections contain information about the PCI PCIe PXI 6251 USB 6251 and USB 6251 Mass Termination devices PCI PCle PXI 6251 PCI PCle P
224. ies D 1 accuracy analog triggers 11 7 National Instruments Corporation acquisition circular buffered 4 12 double buffered 4 12 acquisitions digital waveform 6 3 hardware timed 4 11 on demand 4 11 software timed 4 11 AI channels sampling with AI Sample Clock and AI Convert Clock C 2 AI Convert Clock signal 4 31 AI Convert Clock Timebase signal 4 35 Al data acquisition methods 4 11 AI FIFO 4 2 AI Hold Complete Event signal 4 35 AI Pause Trigger signal 4 38 AI Reference Trigger signal 4 36 AI Sample Clock signal 4 28 AI Sample Clock Timebase signal 4 30 AI Start Trigger signal 4 35 AI timing signals 4 25 ai ConvertClock 4 31 ai ConvertClockTimebase 4 35 ai HoldCompleteEvent 4 35 ai PauseTrigger 4 38 ai ReferenceTrigger 4 36 ai SampleClock 4 28 ai SampleClockTimebase 4 30 ai StartTrigger 4 35 analog trigger actions 11 3 trigger types 11 3 triggering 11 2 analog comparison event routing 11 3 analog comparison event signal 11 3 analog edge triggering 11 4 M Series User Manual Index with hysteresis 11 4 analog input 4 1 channels 11 3 charge injection C 1 circuitry 4 1 connecting signals 4 13 connecting through I O connector 4 1 crosstalk when sampling multiple channels C 1 data acquisition methods 4 11 differential troubleshooting C 1 getting started with applications in software 4 39 ghost voltages when sampling multiple channels C 1 ground reference settings
225. ifications Refer to the NI 625x Specifications for more detailed information about the NI 6259 device USB 6259 Mass Termination Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with two 68 pin connectors such as the NI USB 6259 Mass Termination device Refer to ni com for other accessory options including new devices SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SH68 68 EP shielded cable A 76 ni com Appendix Device Specific Information Use Connector 0 of your M Series device to control an SCC module carrier SCC carriers can be used with Connector 1 with NI DAQ 7 4 and later Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SH68 68 EP shielded cable to connect your DAQ device to BNC accessories such as the following e BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals e BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature refer
226. ignal Default Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 O National Instruments Corporation A 47 M Series User Manual Appendix Device Specific Information Table A 11 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTRIA 42 PFI 3 CTR 1Z 41 PFI 4 CTR 1B 46 PFI 11 3 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help M Series User Manual USB 6251 Mass Termination Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6251 device USB 6251 Mass Termination Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI USB 6251 Mass Termination device Refer to ni com for other accessory options including new devices SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SH68 68 EP shielded cable Refer to the SCC Advisor available by going to ni com info and ent
227. ime relative to a trigger signal M Series User Manual Glossary hysteresis VO impedance in instrument driver instrumentation amplifier interchannel delay interface interrupt interrupt request line M Series User Manual 1 Hertz The SI unit for measurement of frequency One hertz Hz equals one cycle per second 2 The number of scans read or updates written per second Lag between making a change and the effect of the change Input Output The transfer of data to from a computer system involving communications channels operator interface devices and or data acquisition and control interfaces 1 The electrical characteristic of a circuit expressed in ohms and or capacitance inductance 2 Resistance Inch or inches A set of high level software functions that controls a specific GPIB VXI or RS232 programmable instrument or a specific plug in DAQ device Instrument drivers are available in several forms ranging from a function callable language to a virtual instrument VD in LabVIEW A circuit whose output voltage with respect to ground is proportional to the difference between the voltages at its two inputs An instrumentation amplifier normally has high impedance differential inputs and high common mode rejection Amount of time that passes between sampling consecutive channels in an Al scan list The interchannel delay must be short enough to allow sampling of all the channels in the ch
228. imebase is not available as an output on the I O connector ai SampleClockTimebase is divided down to provide one of the possible sources for ai SampleClock You can configure the polarity selection for ai SampleClockTimebase as either rising or falling edge Al Convert Clock Signal Use the AI Convert Clock ai ConvertClock signal to initiate a single A D conversion on a single channel A sample controlled by the AI Sample Clock consists of one or more conversions You can specify either an internal or external signal as the source of ai ConvertClock You also can specify whether the measurement sample begins on the rising edge or falling edge of ai ConvertClock With NI DAQm x 7 4 or later the driver chooses the fastest conversion rate possible based on the speed of the A D converter and adds 10 us of padding between each channel to allow for adequate settling time This scheme enables the channels to approximate simultaneous sampling and still allow for adequate settling time If the AI Sample Clock rate is too fast to allow for this 10 us of padding NI DAQmx chooses the conversion rate so that the AI Convert Clock pulses are evenly spaced throughout the sample With NI DAQmx 7 3 the driver chooses a conversion rate so the AI Convert Clock pulses are evenly spaced throughout the sample This allows for the maximum settling time between conversions To approximate simultaneous sampling manually increase the conversion rate To explic
229. iming Diagram B 18 ni com Table B 9 Al_Sample_In_Progress Timing Appendix B Timing Diagrams Timing Description Line Min ns Max ns t32 Sample Clock to POUT as leading edge of PFI 3 4 8 0 AI_Sample_In_Progress RTSI 4 2 9 2 t33 Convert Clock to POUT as trailing edge of PFI 5 4 12 4 AI_Sample_In_Progress RTSI 6 2 13 6 Pause Trigger The Pause Trigger signal can be used to pause the acquisition any time the signal deasserts It is generated from internal or external sources A multiplexer selects a signal from the _i bus its output is called Selected Pause Trigger National Instruments Corporation B 19 M Series User Manual Appendix B Timing Diagrams Selected Reference Trigger Reference Trigger Terminal Le gt Terminal e D Terminal gt lt SE gt e gt Terminal La Selected Start RTSI Pause Trigger SI Start Terminal gt e lt SI Sample Clock Timebase Counter he Sync Sample Clock Timebase B ck OH gt e gt Terminal gt SI_TC p_Al_Convert 12 nii Convert Clock Timebase oe SI2_TC 1 Sync Convert Clock Timebase toa gt Terminal Selected Sample Clock Terminal Figure B 18 Pause Trigger and the Analog Input Timing Engine tos Lo Selected Pause Trigger i i ts o 1 ms d
230. ing Diagrams M Series User Manual Table B 7 Reference Trigger Timing Timing Description Line Min ns Max ns too Delay to the PFI 3 6 8 9 Selected Reference RTSI 34 84 Trigger STAR 29 5 6 bz Selected Reference Trigger Setup 1 5 to Sync Convert Clock Timebase ba Selected Reference Trigger Hold 0 to Sync Convert Clock Timebase bs Sync Convert Clock Timebase to 0 9 2 2 Reference Trigger b Reference PFI 0 8 2 3 Trigger to POUT RTSI 0 8 1 9 Sample Clock Sample Clock signals the start of a sample which in turn is a set of converts Sample Clock is generated from external or internal sources The main internal source is the terminal count TC of the SI counter that runs on the Sample Clock Timebase signal All the sources for Sample Clock are at the _i level and are selected using a multiplexer The output of this multiplexer is called Selected Sample Clock B 16 ni com Appendix B Timing Diagrams a Selected Reference Trigger Reference Trigger Terminal Le gt Terminal La Terminal 4 gt Start De Terminal e D Selected Start gt S gt RTSI Trnina yl ys Selected Pause Trigger Es e A Pause Trigger SI Start Terminal gt SI Sample Clock Timebase Counter Sync Sample Clock Timebase Block O gt e gt
231. input signals on Connector 1 You can use a SHC68 68 cable to connect to the BNC 2115 A 24 ni com Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks such as e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor make sure the switches are set properly TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your NI 6225 device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables The NI 6225 has two connectors that require different cables Choosing a Cable for Connector 0 In most applications you can use the following cables with Connector 0 e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individual
232. input terminal and ground See also differential input A circuit whose output signal is present between one output terminal and ground The programs that run on your computer and perform a specific user oriented function such as accounting program development measurement or data acquisition In contrast operating system functions basically perform the generic housekeeping of the machine which is independent of any specific application Operating system functions include the saving of data file system handling of multiple programs at the same time multi tasking network interconnection printing and keyboard user interface interaction A method of triggering in which you simulate an analog trigger using software Also called conditional retrieval A parameter of signal sources that reflects current driving ability of voltage sources lower is better and the voltage driving ability of current sources higher is better 1 Hardware A property of an event that is synchronized to a reference clock 2 Software A property of a function that begins an operation and returns only when the operation is complete A synchronous process is therefore locked and no other processes can run during this time In NI DAQnx a collection of one or more channels timing and triggering and other properties that apply to the task itself Conceptually a task represents a measurement or generation you want to perform See termina
233. ion of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 21 M Series User Manual Appendix Device Specific Information gt PA PA gt ee gt ES gt gt ao m Zz n m GND gt O Z AO GND D GND PO 0 PO 5 D GND poz PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND 68 w 67 oO oO 66 oO D 65 wo 64 oO 63 nN 62 D 61 m NI 60 D o 59 D a 58 N R 57 N w 56 N N 55 N 54 m o 53 52 51 er 50 o 49 a 48 i P 47 w 45 N 46 44 o 43 o 41 14218 40 39 37 38 36 35 N O ajuo o 0 AI 8 Al 1 Al GND Al 10 Al3 Al GND Al 4 Al GND Al 13 Al6 Al GND Al 15 AO 0 AO 1 NC PO 4 D GND PO 1 P0 6 D GND 5 V D GND D GND PFI 0 P1 0 PFI 1 P1 1 D GND 5 V D GND PFI 5 P1 5 PFI 6 P1 6 D GND PFI 9 P2
234. ional Instruments and have no agency partnership or joint venture relationship with National Instruments Patents For patents covering National Instruments products refer to the appropriate location Help Patents in your software the patents txt file on your CD or ni com patents WARNING REGARDING USE OF NATIONAL INSTRUMENTS PRODUCTS 1 NATIONAL INSTRUMENTS PRODUCTS ARE NOT DESIGNED WITH COMPONENTS AND TESTING FOR A LEVEL OF RELIABILITY SUITABLE FOR USE IN OR IN CONNECTION WITH SURGICAL IMPLANTS OR AS CRITICAL COMPONENTS IN ANY LIFE SUPPORT SYSTEMS WHOSE FAILURE TO PERFORM CAN REASONABLY BE EXPECTED TO CAUSE SIGNIFICANT INJURY TO A HUMAN 2 IN ANY APPLICATION INCLUDING THE ABOVE RELIABILITY OF OPERATION OF THE SOFTWARE PRODUCTS CAN BE IMPAIRED BY ADVERSE FACTORS INCLUDING BUT NOT LIMITED TO FLUCTUATIONS IN ELECTRICAL POWER SUPPLY COMPUTER HARDWARE MALFUNCTIONS COMPUTER OPERATING SYSTEM SOFTWARE FITNESS FITNESS OF COMPILERS AND DEVELOPMENT SOFTWARE USED TO DEVELOP AN APPLICATION INSTALLATION ERRORS SOFTWARE AND HARDWARE COMPATIBILITY PROBLEMS MALFUNCTIONS OR FAILURES OF ELECTRONIC MONITORING OR CONTROL DEVICES TRANSIENT FAILURES OF ELECTRONIC SYSTEMS HARDWARE AND OR SOFTWARE UNANTICIPATED USES OR MISUSES OR ERRORS ON THE PART OF THE USER OR APPLICATIONS DESIGNER ADVERSE FACTORS SUCH AS THESE ARE HEREAFTER COLLECTIVELY TERMED SYSTEM FAILURES ANY APPLICATION WHERE A SYSTEM FAILURE WOULD CREATE A RISK OF HARM TO PROPERTY
235. ions M Series User Manual A 14 ni com Appendix Device Specific Information NI 6224 NI 6224 Pinout Figure A 4 shows the pinout of the NI 6224 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 15 M Series User Manual Appendix Device Specific Information AIO AI GND AI9 2 N GND 111 SENSE 1 12 GND gt gt gt gt gt gt gt gt a NC NC D GND PO 0 PO 5 D GND P0 2 PO 7 PO 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 o 42 41 40 39 38 37 36 35 Nj
236. ions yielding better rejection of electrostatically coupled noise This configuration does not load down the source other than the very high input impedance of the NI PGIA o Al Floating Signal Source A ot Al R is about R gt 100 times e AL SENSE source o Al GND impedance of sensor Figure 4 5 Differential Connections for Floating Signal Sources with Single Bias Resistor National Instruments Corporation 4 17 M Series User Manual Chapter 4 Analog Input You can fully balance the signal path by connecting another resistor of the same value between the positive input and AI GND as shown in Figure 4 6 This fully balanced configuration offers slightly better noise rejection but has the disadvantage of loading the source down with the series combination sum of the two resistors If for example the source impedance is 2 kQ and each of the two resistors is 100 kQ the resistors load down the source with 200 KQ and produce a 1 gain error Floating s Instrumentation Signal Vs s Amplifier Source sa Al 9 O O O Bias Resistors o4 SC o e see text 9 PGIA Al jj ol oo Measured SK PTAISENSE 1 0 Connector Bias Current SF so Return oe Paths qa m Voltage oF Sr op So Input Multiplexers Al GND M Series Device
237. ions apply mainly to AI signal routing to the device although they also apply to signal routing in general Minimize noise pickup and maximize measurement accuracy by taking the following precautions Use DIFF AI connections to reject common mode noise e Use individually shielded twisted pair wires to connect Al signals to the device With this type of wire the signals attached to the positive and negative input channels are twisted together and then covered with a shield You then connect this shield only at one point to the signal source ground This kind of connection is required for signals traveling through areas with large magnetic fields or high electromagnetic interference Refer to the NI Developer Zone document Field Wiring and Noise Considerations for Analog Signals for more information To access this document go to ni com info and enter the info code rdfwn3 Analog Input Timing Signals In order to provide all of the timing functionality described throughout this section M Series devices have a flexible timing engine Figure 4 12 summarizes all of the timing options provided by the analog input timing engine Also refer to the Clock Routing section of Chapter 9 Digital Routing and Clock Generation National Instruments Corporation 4 25 M Series User Manual Chapter 4 Analog Input PXI_STAR Analog Comparison Event 20 MHz Timebase 100 kHz Timebase PXI_STAR PFI RTSI PS
238. ition begins on the first rising edge of the Analog Comparison Event signal Routing Al Start Trigger to an Output Terminal You can route ai StartTrigger out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal The output is an active high pulse All PFI terminals are configured as inputs by default The device also uses ai StartTrigger to initiate pretriggered DAQ operations In most pretriggered applications a software trigger generates ai StartTrigger Refer to the AJ Reference Trigger Signal section for a complete description of the use of ai StartTrigger and ai ReferenceTrigger in a pretriggered DAQ operation Al Reference Trigger Signal M Series User Manual Use a reference trigger ai ReferenceTrigger signal to stop a measurement acquisition To use a reference trigger specify a buffer of finite size and a number of pretrigger samples samples that occur before the reference trigger The number of posttrigger samples samples that occur after the reference trigger desired is the buffer size minus the number of pretrigger samples Once the acquisition begins the DAQ device writes samples to the buffer After the DAQ device captures the specified number of pretrigger samples the DAQ device begins to look for the reference trigger condition If the reference trigger condition occurs before the DAQ device captures the specified number of pretrigger samples the DAQ device ignores the condition 4 36 ni com Chapter 4 A
239. itly specify the conversion rate use AI Convert Clock Rate DAQmx Timing property node or function A Caution Setting the conversion rate higher than the maximum rate specified for your device will result in errors Using an Internal Source One of the following internal signals can drive ai ConvertClock e AT Convert Clock Timebase divided down e Counter n Internal Output A programmable internal counter divides down the AI Convert Clock Timebase to generate ai ConvertClock The counter is started by ai SampleClock and continues to count down to zero produces an ai ConvertClock reloads itself and repeats the process until the sample is National Instruments Corporation 4 31 M Series User Manual Chapter 4 Analog Input finished It then reloads itself in preparation for the next ai SampleClock pulse Using an External Source Use one of the following external signals as the source of ai ConvertClock e PFI lt 0 15 gt e RTSI lt 0 7 gt e PXI STAR e Analog Comparison Event an analog trigger Routing Al Convert Clock Signal to an Output Terminal You can route ai ConvertClock as an active low signal out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal All PFI terminals are configured as inputs by default Using a Delay from Sample Clock to Convert Clock When using an internally generated ai ConvertClock you also can specify a configurable delay from ai SampleClock to the first ai ConvertClock pul
240. ive ai SampleClock e Counter n Internal Output e AI Sample Clock Timebase divided down e A software pulse A programmable internal counter divides down the sample clock timebase Several other internal signals can be routed to ai SampleClock through RTSI Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information Using an External Source Use one of the following external signals as the source of ai SampleClock e PFI lt 0 15 gt RTSI lt 0 7 gt e PXI STAR e Analog Comparison Event an analog trigger Routing Al Sample Clock Signal to an Output Terminal You can route ai SampleClock out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal This pulse is always active high You can specify the output to have one of two behaviors With the pulse behavior your DAQ device briefly pulses the PFI terminal once for every occurrence of ai SampleClock With level behavior your DAQ device drives the PFI terminal high during the entire sample All PFI terminals are configured as inputs by default Other Timing Requirements Your DAQ device only acquires data during an acquisition The device ignores ai SampleClock when a measurement acquisition is not in progress During a measurement acquisition you can cause your DAQ device to ignore ai SampleClock using the ai PauseTrigger signal National Instruments Corporation 4 29 M Series User Manual Chapter 4 Analog Input A counter
241. ive power connector A Caution Never connect the 5 V power terminals to analog or digital ground or to any other voltage source on the M Series device or any other device Doing so can damage the device and the computer NI is not liable for damage resulting from such a connection Disk Drive Power Connector The disk drive power connector is a four pin hard drive connector on PCI Express devices that when connected increases the current the device can supply on the 5 V terminal When to Use the Disk Drive Power Connector M Series User Manual M Series PCI Express devices without the disk drive power connector installed perform identically to other M Series devices for most applications and with most accessories For most applications it is not necessary to install the disk drive power connector However you should install the disk drive power connector in either of the following situations e You need more power than listed in the device specifications e You are using an SCC accessory without an external power supply such as the SC 2345 3 6 ni com Chapter 3 Connector Information Refer to the specifications document for your device for more information about PCI Express power requirements and power limits Disk Drive Power Connector Installation Before installing the disk drive power connector you must install and set up the M Series PCI Express device as described in the DAQ Getting Started Guide Complete the foll
242. ives the Gate Logic which generates the Counter Enable signal B 38 ni com Appendix B Timing Diagrams All internal counter timing is referenced to these two signals Any internal signal refers to signals with _i from the previous table or signals coming from another subsystem inside the M Series device It does not include internal timebases or the PXI_CLK10 PFI_i RTSL_i or PXI_STAR_i Selected_Gate Figure B 42 Selected Gate Delays Timing Diagram Table B 27 Selected Gate Delays Timing Timing From To Min ns Max ns to PFI_i RTSI_i Selected Gate 1 0 6 0 PXI_ STAR i or any internal signal PFI_i RTSL_i or PXI_STAR_i D Selected_Source lt gt tz lt gt t Figure B 43 Selected Source Delays Timing Diagram National Instruments Corporation B 39 M Series User Manual Appendix B Timing Diagrams Table B 28 Selected Source Delays Timing Timing From To Min ns Max ns t3 PFI_i RTSL i Selected Source 8 0 21 0 PXI_STAR i or any internal signal 20 MHz Timebase Selected Source 1 5 4 0 100 kHz Timebase Selected Source 1 5 4 0 80 MHz Timebase Selected Source 1 0 2 5 PXI_CLK10 Selected Source 1 0 3 5 Count Enable Delay Table B 29 shows
243. k such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required National Instruments Corporation A 83 M Series User Manual Appendix Device Specific Information Cables In most applications you can use the following cables SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions
244. k and ai ConvertClock 0123 0123 0123 Sample 1 ai SampleClock ai ConvertClock Channel Measured Sample 2 e Sample Clock Too Fast for Convert Clock e Sample Clock Pulses are Gated Off Figure 4 18 ai SampleClock Too Fast ai SampleClock ai ConvertClock 012 3 Sample 2 012 3 Sample 1 gt Sample 3 Channel Measured 0123 4 i 1 lt pi e Convert Clock Too Fast for Sample Clock e Convert Clock Pulses are Gated Off Figure 4 19 ai ConvertClock Too Fast National Instruments Corporation 4 33 M Series User Manual Chapter 4 Analog Input ai SampleClock ai ConvertClock Channel Measured M Series User Manual e Improperly Matched Sample Clock and Convert Clock e Leads to Aperiodic Sampling 0 1 2 3 Sample 2 0 1 2 3 Sample 1 0 Sample 3 4 pid gt Figure 4 20 ai SampleClock and ai ConvertClock Improperly Matched ai SampleClock ai ConvertClock 012 3 Sample 3 gt Sample 1 Sample 2 lt q gt q gt q Channel M
245. l The period of a signal most often measured from one zero crossing to the next zero crossing of the same slope The period of a signal is the reciprocal of its frequency in Hz Period is designated by the symbol T The number of periods of a signal Programmable Function Interface Programmable Gain Instrumentation Amplifier See channel Devices that do not require DIP switches or jumpers to configure resources on the devices Also called switchless devices port 1 A communications connection on a computer or a remote controller 2 A digital port consisting of four or eight lines of digital input and or output The technique used on a DAQ device to acquire a programmed number of samples after trigger conditions are met An instrument that provides one or more sources of AC or DC power Also known as power supply Parts per million The technique used on a DAQ device to keep a continuous buffer filled with data so that when the trigger conditions are met the sample includes the data leading up to the trigger condition A signal whose amplitude deviates from zero for a short period of time The time from the rising to the falling slope of a pulse at 50 amplitude A rugged open system for modular instrumentation based on CompactPCI with special mechanical electrical and software features The PXIbus standard was originally developed by National Instruments in 1997 and is now managed by the PXIbus Systems Alliance
246. l This is the timing that controls when the analog to digital conversions take place The SC DIV and SI2 counters run on this timing level The signal that clocks this timing level is called Convert Clock Timebase This signal can come from an internal source for example an internal timebase or an external signal It can be divided down using the SI2 counter or it can be used directly in external convert mode In order to synchronize triggers to the Convert Clock Timebase signal another related signal is generated called Sync Convert Clock Timebase Sync Convert Clock Timebase is generated differently depending on the mode the AI timing engine is operating on e When Convert Clock Timebase is a signal that will be divided down using the SI2 counter either internal or external it is considered to be a free running clock In this case the Sync Convert Clock Timebase is the inverted version of the Convert Clock Timebase signal The idea is to use the falling edge of the original signal to synchronize external signals before the rising edge of the Convert Clock Timebase occurs after polarity selection This case is the one described in this section e When Convert Clock Timebase is not going to be divided by the SI2 counter in the case of an external convert signal this signal is assumed to be not free running and highly irregular In this case Sync Convert Clock Timebase is selected to be the actual external signal and Convert Clock
247. l gt lt gt SI Start Pause Trigger Terminal D O gt l Sl Sample Clock Timebase Counter Block Sync Sample Clock Timebase oO gt e gt Terminal gt SI_TC y p_Al_Convert e E See SI2 Convert Clock Timebase Counter SI2_TC U S Sync Convert Clock Timebase Blook 1 Start Selected Sample Clock gt Terminal Le gt p lt gt gt Terminal gt Figure B 9 Convert Clock Timebase Timing and the Analog Input Timing Engine o Selected Start i oa tis lt gt it Sync Convert Clock Timebase pag t 146 gt Start POUT Figure B 10 Convert Clock Timebase Timing Diagram M Series User Manual B 12 ni com Appendix B Timing Diagrams Table B 5 Convert Clock Timebase Timing Timing Description Line Min ns Max ns t3 Delay to PFI 3 4 8 8 Selected Start RTSI 3 3 8 5 STAR 2 1 9 4 tia Selected Start Setup Time to 1 5 Sync Convert Clock Timebase tis Selected Start Hold Time to 0 Sync Convert Clock Timebase tie Sync Convert Clock Timebase to 0 9 24 Start to Start to POUT PFI 1 1 3 1 RTSI 1 1 2 1 Selected Reference Trigger Reference
248. l Instruments Corporation A 1 M Series User Manual Appendix Device Specific Information NI 6220 NI 6220 Pinout Figure A 1 shows the pinout of the NI 6220 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 2 ni com Appendix Device Specific Information GND GND 11 SENSE gt gt gt gt gt gt gt gt gt gt gt gt D GND PO 0 PO 5 D GND Ore PO 7 P0 3 FI 11 P2 3 110 P2 2 GND 12 P1 2 3 P1 3 14 P1 4 13 P2 5 115 P2 7 Fl 7 P1 7 PFI 8 P2 0 DGND D GND m 7 7 TU al UEN UEN Al U 7 TI A 68 34 67 33 66 32 65 31 64 30 63 29 62 28 61 27 60 26 59 25 58 24 57 23 56 22 55 21 54 20 53 19 52 18 51 17 50 16 49 15 48 14 47 13 46 12 45 11 44 10 43 9 42 41 40 39 38 37 36 35 N O Aa OI O 0 le NC No Connect gt gt gt gt
249. l count An object or region on a node through which data passes M Series User Manual Glossary terminal count toh gsu tow Timebase tout Traditional NI DAQ Legacy transducer trigger M Series User Manual The highest value of a counter Gate hold time Gate setup time Gate pulse width The reference signals for controlling the basic accuracy of time or frequency based measurements For instruments timebase refers to the accuracy of the internal clock Output delay time An upgrade to the earlier version of NI DAQ Traditional NI DAQ Legacy has the same VIs and functions and works the same way as NI DAQ 6 9 x You can use both Traditional NI DAQ Legacy and NI DAQmx on the same computer which is not possible with NI DAQ 6 9 x A device that responds to a physical stimulus heat light sound pressure motion flow and so on and produces a corresponding electrical signal See also sensor 1 Any event that causes or starts some form of data capture 2 An external stimulus that initiates one or more instrument functions Trigger stimuli include a front panel button an external input voltage pulse or a bus trigger command The trigger may also be derived from attributes of the actual signal to be acquired such as the level and slope of the signal Source clock period Source pulse width Transistor Transistor Logic A digital circuit composed of bipolar transistors wired in a certain
250. le delays B 40 counter gating modes B 47 counter input requirements B 41 counter output delays B 46 counter pin to internal signal delays B 38 counters B 37 digital 1 O B 32 digital waveform acquisition B 33 digital waveform generation B 35 gate pulse width input requirements B 42 gate to source setup and hold B 42 input timing verification B 29 internal analog output timing B 25 output timing B 29 pulse width input requirements B 41 ni com quadrature encoder B 47 selected gate to count enable delays B 40 selected gate to selected source delays B 38 source period input requirements B 41 two pulse encoder B 47 timing output signals exporting using PFI terminals 8 3 training xxii training and certification NI resources E 1 transducers 2 3 trigger 11 1 analog actions 11 3 arm start 7 32 pause 7 32 PXI 9 8 PXI_STAR 9 8 Star Trigger 9 8 start 7 32 triggering 11 1 analog accuracy 11 7 analog actions 11 3 analog edge 11 4 analog edge with hysteresis 11 4 analog input 4 13 analog input channels 11 3 analog types 11 3 analog window 11 6 APFI terminals 11 2 counter 7 32 digital waveform 6 3 with a digital source 11 1 with an analog source 11 2 troubleshooting analog input C 1 analog output C 3 counters C 3 installation C 3 troubleshooting NI resources E 1 two signal edge separation measurement 7 18 National Instruments Corporation Index buffered 7 19 single
251. litches due to released charges The largest glitches occur when the most significant bit of the DAC code changes You can build a lowpass deglitching filter to remove some of these glitches depending on the frequency and nature of the output signal Visit ni com support for more information about minimizing glitches Counters When multiple sample clocks on my buffered counter measurement occur before consecutive edges on my source I see weird behavior Why Duplicate count prevention ensures that the counter returns correct data for counter measurement in some applications where a slow or non periodic external source is used Refer to the Duplicate Count Prevention section of Chapter 7 Counters for more information How do I connect counter signals to my M Series device The Default Counter Timer Pinouts section of Chapter 7 Counters has information about counter signal connections M Series Installation Issues My M Series device is not detected by Measurement amp Automation Explorer MAX or the Windows 2000 NT XP operating system When using other devices such as E Series devices on the same PC they work fine What is the problem Appendix D Upgrading from E Series to M Series lists some issues encountered when upgrading from E Series to M Series devices Customers also can refer to NI s KnowledgeBase at ni com kb and Developer Zone at ni com devzone for more updated troubleshooting tips and answers to fre
252. lock such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor e TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required A 88 ni com Appendix Device Specific Information Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions NI recommends that you use the SHC68
253. ls e Counter n Source e Counter n Gate e Counter n Aux e Countern A Counter n B Counter n Z e Counter n Up_Down e Counter n HW Arm e Counter n Internal Output e Counter n TC e Frequency Output In this section n refers to either Counter 0 or 1 For example Counter n Source refers to two signals Counter 0 Source the source input to Counter 0 and Counter 1 Source the source input to Counter 1 National Instruments Corporation 7 25 M Series User Manual Chapter 7 Counters Counter n Source Signal The selected edge of the Counter n Source signal increments and decrements the counter value depending on the application the counter is performing Table 7 3 lists how this terminal is used in various applications M Series User Manual Table 7 3 Counter Applications and Counter n Source Application Purpose of Source Terminal Pulse Generation Counter Timebase One Counter Time Measurements Counter Timebase Two Counter Time Measurements Input Terminal Non Buffered Edge Counting Input Terminal Buffered Edge Counting Input Terminal Two Edge Separation Counter Timebase Routing a Signal to Counter n Source Each counter has independent input selectors for the Counter n Source signal Any of the following signals can be routed to the Counter n Source input 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase RTSI lt 0 7 gt PFI lt 0 15 gt PXI_CLK10 PXI_STA
254. ls at 125 kS s per channel illustrates the relationship Posttriggered data acquisition allows you to view only data that is acquired after a trigger event is received A typical posttriggered DAQ sequence is shown in Figure 4 14 The sample counter is loaded with the specified number of posttrigger samples in this example five The value decrements with each pulse on ai SampleClock until the value reaches zero and all desired samples have been acquired ai StartTrigger ai SampleClock ai ConvertClock j Sample Counter Figure 4 14 Posttriggered Data Acquisition Example Pretriggered data acquisition allows you to view data that is acquired before the trigger of interest in addition to data acquired after the trigger Figure 4 15 shows a typical pretriggered DAQ sequence ai StartTrigger can be either a hardware or software signal If ai StartTrigger is set up to be a software start trigger an output pulse appears on the ai StartTrigger line when the acquisition begins When the ai StartTrigger pulse occurs the sample counter is loaded with the number of pretriggered samples in this example four The value decrements with each pulse on ai SampleClock until the value reaches zero The sample counter is then loaded with the number of posttriggered samples in this example three Mational Instruments Corporation 4 27 M Series User Manual Chapter 4 Analo
255. lse Train Gen rati n sssr sid cesdessscesaseatazes etapa saved sages dependent teen 7 22 Continuous Pulse Train Generation 7 22 Frequency Generations csccsesseciscescsassettseestesticaessacacbeceasbassstess RETAKE ai 7 23 Using the Frequency Generator 7 23 Fr quency DIVISION ices ics sees cine is dvsdeca sass yes Din sot iatesavctagaisvas cavastuniessuattsmeeicts 7 24 Pulse Generation for ETS sense cyses ninio TE AEE 7 24 Counter Timing Signals cnni nt seas va stbeeve aasckg a aa aa 7 25 Counter n Source Sigmal ses Sees alan sd hack ceci teta ladies 7 26 Routing a Signal to Counter n Source coooococcncccoconononncnnnonncancnnncnnnnnnono 7 26 Routing Counter n Source to an Output Terminal 7 27 Counter Gate Signal 48 nara e aa a a 7 27 Routing a Signal to Counter n Gate 7 27 Routing Counter n Gate to an Output Terminal 0 ee 7 27 Counterin Aux Signal insien cies ai os cons dete deh dead nent 7 28 Routing a Signal to Counter n AUX c ocooccnncconanoncononnncnnonnncononnnonnnnnnon 7 28 Counter n A Counter n B and Counter n Z Signals cooncccnncccoccconcncnnnconncnnnos 7 28 Routing Signals to A B and Z Counter Inputs 0 0 eee 7 28 Routing Counter n Z Signal to an Output Terminal 0 7 28 Counter n Up_Down Signal 7 29 Counter n HW Arm Signal 7 29 Routing Signals to Counter n HW Arm Input 7 29 Counter n Internal Output and Counter n TC Signals 7 29 Routing Counter n Inter
256. lt Pin Number Name CTR 0 SRC 37 PFI 8 CTR 0 GATE 3 PFI 9 CTR 0 AUX 45 PFI 10 CTR 0 OUT 2 PFI 12 CTROA 37 PFI 8 CTROZ 3 PFI 9 National Instruments Corporation A 81 M Series User Manual Appendix Device Specific Information Table A 20 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTR1A 42 PFI 3 CTR1Z 41 PFI 4 CTR 1B 46 PFI 11 3 Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6280 Specifications Refer to the NI 628x Specifications for more detailed information about the NI 6280 device NI 6280 Accessory and Cabling Options M Series User Manual This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI 6280 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series devi
257. ly shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable 1 TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 25 M Series User Manual Appendix Device Specific Information Choosing a Cable for Connector 1 In most applications you can use the following cables with Connector 1 SHC68 68 A shielded cable with 34 twisted pairs of wire Each differential analog input channel on Connector 1 is routed on a twisted pair on the SHC68 68 cable e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions M Series User Manual A 26 ni com Appendix Device Specific Information NI 6229 NI 6229 Pinout Figure A 6 shows the pinout of the NI 6229 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Infor
258. maintenance instructions owner s modification of the product owner s abuse misuse or negligent acts and power failure or surges fire flood accident actions of third parties or other events outside reasonable control Copyright Under the copyright laws this publication may not be reproduced or transmitted in any form electronic or mechanical including photocopying recording storing in an information retrieval system or translating in whole or in part without the prior written consent of National Instruments Corporation National Instruments respects the intellectual property of others and we ask our users to do the same NI software is protected by copyright and other intellectual property laws Where NI software may be used to reproduce software or other materials belonging to others you may use NI software only to reproduce materials that you may reproduce in accordance with the terms of any applicable license or other legal restriction Trademarks National Instruments NI ni com and LabVIEW are trademarks of National Instruments Corporation Refer to the Terms of Use section on ni com legal for more information about National Instruments trademarks FireWire is the registered trademark of Apple Computer Inc Other product and company names mentioned herein are trademarks or trade names of their respective companies Members of the National Instruments Alliance Partner Program are business entities independent from Nat
259. manner A typical medium speed digital technology Nominal TTL logic levels are 0 and 5 V G 18 ni com USB Vox VoL V out V S virtual channel W waveform Glossary Universal Serial Bus A 480 Mbit s serial bus with up to 12 Mbps bandwidth for connecting computers to keyboards printers and other peripheral devices USB 2 0 retains compatibility with the original USB specification Volts Common mode voltage Ground loop voltage Volts input high Volts input low Volts in Measured voltage Volts output high Volts output low Volts out Signal source voltage See channel 1 The plot of the instantaneous amplitude of a signal as a function of time 2 Multiple voltage readings taken at a specific sampling rate National Instruments Corporation G 19 M Series User Manual Index Symbols 5 V power source 3 6 Numerics 10 MHz reference clock 9 3 100 kHz Timebase 9 2 20 MHz Timebase 9 2 5B Series 2 5 80 MHz source mode 7 39 80 MHz Timebase 9 2 A A D converter 4 2 accessories 2 5 choosing for your device 1 2 NI 6220 A 4 NI 6221 37 pin A 13 NI 6221 68 pin A 9 NI 6224 A 17 NI 6225 A 23 NI 6229 A 29 NI 6280 A 82 NI 6281 A 87 NI 6284 A 92 NI 6289 A 98 NI 6250 A 35 NI 6254 A 54 NI 6255 A 60 PCI PCle PXI 6251 A 40 PCI PCle PXI 6259 A 66 USB 6251 Mass Termination A 48 USB 6259 Mass Termination A 76 used with M Ser
260. mation 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 27 M Series User Manual Appendix Device Specific Information 14 17 GND AO GND AO GND D GND PO 0 PO 5 D GND P0 2 PO 7 PO 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND gt gt gt gt gt gt gt gt gt gt gt gt ao m Zz ao m 68 w 67 oO oO 66 0 D 65 wo 64 oO 63 N 62 De 61 m Y 60 to o 59 D a 58 N x 57 N oO 56 N N 55 D 54 m o 53 o 52 51 er 50 o 49 a 48 mn P 47 w 46 D 45 44 o 43 o 42 41 40 39 38 37 36 35 NjoO a oajo 0 Als P0 30 Al 1 P0 28 AI GND P0 25 Al 10 m D GND Al 3 E P0 22 AI GND ego 25 P0 21 04 Oo Al4 uo E D GND AI GND 9 2 45 V Al 13 6 6 D GND Al6 O O P0 17 AI GND P0 16 AIS TERMINAL 68 fl EE TERMINAL 35
261. mation Table A 2 Default NI DAQmx Counter Timer Pins Continued Counter Timer Signal Default Pin Number Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTRIA 42 PFI 3 CTR1Z 41 PFI 4 CTR1B 46 PFI 11 B Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6221 68 Pin Specifications Refer to the MI 622x Specifications for more detailed information about the NI 6221 68 pin device NI 6221 68 Pin Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI 6221 68 pin Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXI Advisor available by going to ni com info and entering the info code rdscad for more information National Instruments Corpor
262. maximum or minimum timing This difference can be useful when two external signals will be used together and the relative timing between the signals is important When DI Sample Clock is routed to a PFI output pin the pulse width of the output is independent of the pulse width of the input The pulse width is specified in a number of periods of the 80 MHz Timebase Table B 23 DI Timing Requirements Timing Requirement Condition Min ns Max ns t PFI RTSI or PXI_STAR When used as DI Sample Clock NI 622x devices 1000 0 Minimum Period NI 625x 628x devices 100 0 to PFI RTSI or PXI_STAR When used as DI Sample Clock 12 0 Minimum Pulse Width ts Setup time From P0_i to DI 1 5 Sample Clock te Hold time From DI Sample 0 Clock to PO _i M Series User Manual B 34 ni com Appendix B Timing Diagrams Digital Waveform Generation Timing To describe digital waveform generation timing delays and requirements we model the circuitry as shown in Figure B 38 In the figure PO PFI RTSL and PXI_STAR represent signals at connector pins of the M Series device The other named signals represent internal signals PFI_i RTSI_i PO or PXI_STAR_i DO Waveform PFI RTSI ES sie ae Generation FIFO or PXI_STAR Other Internal gt PFI Output Signals Figure B 38 Digital Waveform Generation Timin
263. ments Corporation A 61 M Series User Manual Appendix Device Specific Information TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your NI 6255 device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables The NI 6255 has two connectors that require different cables Choosing a Cable for Connector 0 In most applications you can use the following cables with Connector 0 e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Choosing a Cable for Connector 1 In most applications you can use the following cables with Connector 1 e SHC68 68 A shielded cable with 34 twisted pairs of wire Each diff
264. mmable frequency and duty cycle The pulses appear on the Counter n Internal Output signal of the counter You can specify a delay from when the counter is armed to the beginning of the pulse train The delay is measured in terms of a number of active edges of the Source input You specify the high and low pulse widths of the output signal The pulse widths are also measured in terms of a number of active edges of the Source input You also can specify the active edge of the Source input rising or falling The counter can begin the pulse train generation as soon as the counter is armed or in response to a hardware Start Trigger You can route the Start Trigger to the Gate input of the counter You also can use the Gate input of the counter as a Pause Trigger if it is not used as a Start Trigger The counter pauses pulse generation when the Pause Trigger is active Figure 7 25 shows a continuous pulse train generation using the rising edge of Source SOURCE OUT Counter Armed Figure 7 25 Continuous Pulse Train Generation Continuous pulse train generation is sometimes called frequency division If the high and low pulse widths of the output signal are M and N periods then the frequency of the Counter n Internal Output signal is equal to the frequency of the Source input divid
265. more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 95 M Series User Manual Appendix Device Specific Information NI 6289 NI 6289 Pinout Figure A 23 shows the pinout of the NI 6284 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 96 ni com Appendix Device Specific Information GND 14 77 GND AO GND AO GND D GND PO 0 PO 5 D GND P0 2 PO 7 P0 3 PFI 11 P2 3 PFI 10 P2 2 D GND PFI 2 P1 2 PFI 3 P1 3 PFI 4 P1 4 PFI 13 P2 5 PFI 15 P2 7 PFI 7 P1 7 PFI 8 P2 0 D GND D GND gt gt gt gt gt gt gt gt gt gt gt gt ao m Zz n m gt GND CONNECTOR 0 Al 0 15 CONNECTOR 1 Al 16 31 gt gt gt gt gt gt gt gt gt gt gt A 15 TERMINAL 68 AO 0 01 TERMINAL 34 APFI 0 P0 4 D GND P0 1 P0 6 D GND 5V D GND D GND TERMINAL 35 PFI 0 P1 0 PFI 1 P1 1 D GND 5 V D GND PFI 5 P1 5 P
266. mparison Event out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal Analog Trigger Types Configure the analog trigger circuitry to different triggering modes analog edge triggering analog edge triggering with hysteresis or analog window triggering National Instruments Corporation 11 3 M Series User Manual Chapter 11 Triggering Analog Edge Triggering Configure the analog trigger circuitry to detect when the analog signal is below or above a level you specify In below level analog triggering mode shown in Figure 11 3 the trigger is generated when the signal value is less than Level Analog Comparison Event Figure 11 3 Below Level Analog Triggering Mode In above level analog triggering mode shown in Figure 11 4 the trigger is generated when the signal value is greater than Level Analog Comparison Event Figure 11 4 Above Level Analog Triggering Mode Analog Edge Triggering with Hysteresis Hysteresis adds a programmable voltage region above or below the trigger level that an input signal must pass through before the DAQ device recognizes a trigger connection and is often used to reduce false triggering due to noise or jitter in the signal M Series User Manual 11 4 ni com Chapter 11 Triggering Analog Edge Trigger with Hysteresis Rising Slope When using hysteresis with a rising slope you specify a trigger lev
267. mx only supports filters on counter inputs M Series User Manual The following is an example of low to high transitions of the input signal High to low transitions work similarly Assume that an input terminal has been low for a long time The input terminal then changes from low to high but glitches several times When the filter clock has sampled the signal high on N consecutive edges the low 9 6 ni com Chapter 9 Digital Routing and Clock Generation to high transition is propagated to the rest of the circuit The value of N depends on the filter setting refer to Table 9 2 Table 9 2 Filters N Filter Clocks Pulse Width Pulse Width Needed to Pass Guaranteed to Pass Guaranteed to Not Filter Setting Signal Filter Pass Filter 125 ns 5 125 ns 100 ns 6 425 us 257 6 425 us 6 400 us 2 55 ms 101 800 2 55 ms 2 54 ms Disabled The filter setting for each input can be configured independently On power up the filters are disabled Figure 9 3 shows an example of a low to high transition on an input that has its filter set to 125 ns N 5 RTSI PFI or PXI_ STAR Terminal Filtered input goes high when terminal is sampled high on five consecutive filter clocks Filter Clock 1 1 2 3 4 1 2 345 40 MHz Filtered Input po Figure 9 3 Filter Example Enabling filters introduces jitter on the input signal For the 125 ns and 6 425 us filter settings the jitter is
268. n T to the Gate of a counter You can generate the pulse using a second counter You also can generate the pulse externally and connect it to a PFI or RTSI terminal You only need to use one counter if you generate the pulse externally Route the signal to measure F1 to the Source of the counter Configure the counter for a single pulse width measurement Suppose you measure the width of pulse T to be N periods of Fl Then the frequency of Fl is N T Figure 7 13 illustrates this method Another option would be to measure the width of a known period instead of a known pulse O National Instruments Corporation 7 11 M Series User Manual Chapter 7 Counters Width of Pulse T gt Pulse _ Pulse Gate 1 2 zi N F1 Source m FLIA Pulse Width Width of y _N Measurement Pulse F1 Frequency of F1 oo M Series User Manual Figure 7 13 Method 2 Method 3 Measure Large Range of Frequencies Using Two Counters By using two counters you can accurately measure a signal that might be high or low frequency This technique is called reciprocal frequency measurement In this method you generate a long pulse using the signal to measure You then measure the long pulse with a known timebase The M Series device can measure this long pulse more accurately than the faster input signal You can route the signal to measure to the Source input of Counter
269. n Number Name CTROB 45 PFI 10 CTR 1 SRC 42 PFI 3 CTR 1 GATE 41 PFI 4 CTR 1 AUX 46 PFI 11 CTR 1 OUT 40 PFI 13 CTRIA 42 PFI 3 CTR1Z 41 PFI 4 CTR1B 46 PFI 11 B Note For more information about default NI DAQmx counter inputs refer to Connecting Counter Signals in the NI DAQmx Help or the LabVIEW 8 x Help NI 6250 Specifications Refer to the NI 625x Specifications for more detailed information about the NI 6250 device NI 6250 Accessory and Cabling Options This section describes some cable and accessory options for M Series devices with one 68 pin connector such as the NI 6250 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXT Advisor available by going to ni com info and entering the info code rdscad for more information National Instruments Corporation A 35 M Series User Manual Appendix Device Specific Information M Series User Manual SCC SCC provides portable modular signal conditioning to your DAQ syst
270. n exactly the counter synchronizes the Gate signal vary depending on the synchronization mode Synchronization modes are described in the Synchronization Modes section Example Application That Works Incorrectly Duplicate Counting In Figure 7 32 after the first rising edge of Gate no Source pulses occur so the counter does not write the correct data to the buffer No Source edge so no value written to buffer Gate oOo moo Source Counter Value 6 X 7 X 1 Buffer 7 Figure 7 32 Duplicate Count Example Example Application That Prevents Duplicate Count With duplicate count prevention enabled the counter synchronizes both the Source and Gate signals to the 80 MHz Timebase By synchronizing to the timebase the counter detects edges on the Gate even if the Source does not pulse This enables the correct current count to be stored in the buffer even if no Source edges occur between Gate signals as shown in Figure 7 33 M Series User Manual 7 36 ni com Chapter 7 Counters Gate Source Counter detects rising Gate edge Counter value increments only one time for each Source pulse 80 MHz Timebase Counter Value Buffer 6 Cae Xt ne E 7 Figure 7 33 Duplicate Count Prevention Example Even if the Source pulses are long the counter increments only on
271. nal Output to an Output Terminal 7 30 Frequency Output Signal sise 7 30 Routing Frequency Output to a Terminal 7 30 Default Counter Timer Pinouts ss 7 30 Counter Triggering tonic anita iii rinde 7 32 Arm Start Tauste lia 7 32 Start TIS Ger E rt niet 7 32 Pause Turrillas 7 32 Other Counter Features uses tenais ententes 7 33 Cascading Cotice 7 33 Counter Filters sis fassent dde 7 33 Pr scaling cia in th anti Me eect nas 7 34 Duplicate Count Prevention 7 35 Example Application That Works Correctly No Duplicate Counting RL 7 35 Example Application That Works Incorrectly Duplicate Counting Jsir aiiin 7 36 Example Application That Prevents Duplicate Count 7 36 When To Use Duplicate Count Prevention oooconccnncninnnoncnnnnonconannonn 7 37 Enabling Duplicate Count Prevention in NI DAQmx 7 38 M Series User Manual xii ni com Contents Synchronization Modes 7 38 80 MHz Source Modessa onar naici ste tir tubes sigeacevcsses 7 39 Other Internal Source Mode 7 39 External Source Mode sssstissnsnrshenssinenene 7 39 Chapter 8 PFI Using PFI Terminals as Timing Input Signals 8 2 Exporting Timing Output Signals Using PFI Terminals 8 3 Using PFI Terminals as Static Digital MOS oooninnicncnncnnoninanicananncnnrancnnonnrnnnnnnncnncnncnnos 8 3 Connecting PFI Input Signals ss 8 4 PPD Filters is Sienne cate sated
272. nalog Input Analog Input Triggering Analog input supports three different triggering actions e Start trigger e Reference trigger e Pause trigger Refer to the AI Start Trigger Signal AI Reference Trigger Signal and AI Pause Trigger Signal sections for information about these triggers An analog or digital trigger can initiate these actions All M Series devices support digital triggering but some do not support analog triggering To find your device triggering options refer to the specifications document for your device Connecting Analog Input Signals Table 4 6 summarizes the recommended input configuration for both types of signal sources National Instruments Corporation 4 13 M Series User Manual Chapter 4 Analog Input Table 4 6 Analog Input Configuration Floating Signal Sources Not Ground Referenced Connected to Building Ground Signal Sources Examples Example e Ungrounded thermocouples e Plug in instruments with a ninni PRE non isolated outputs e Signal conditioning with isolated P Al outputs Ground Reference P Setting Battery devices Differential Signal Source DAQ Device Signal Source DAQ Device Al Al C Al Al Al GND Al GND Single Ended Non Referenced Signal Source
273. nalog Input If the buffer becomes full the DAQ device continuously discards the oldest samples in the buffer to make space for the next sample This data can be accessed with some limitations before the DAQ device discards it Refer to the KnowledgeBase document Can a Pretriggered Acquisition be Continuous for more information To access this KnowledgeBase go to ni com info and enter the info code rdcanq When the reference trigger occurs the DAQ device continues to write samples to the buffer until the buffer contains the number of posttrigger samples desired Figure 4 23 shows the final buffer Reference Trigger Pretrigger Samples Posttrigger Samples T Complete Buffer Figure 4 23 Reference Trigger Final Buffer Using a Digital Source To use ai ReferenceTrigger with a digital source specify a source and an edge The source can be any of the following signals e PFI lt O0 15 gt RTSI lt 0 7 gt e PXI STAR The source also can be one of several internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information You also can specify whether the measurement acquisition stops on the rising edge or falling edge of ai ReferenceTrigger Using an Analog Source When you use an analog trigger source the acquisition stops on the first rising edge of the Analog Comparison Event signal National Instruments Corpor
274. nce between the signal source and the device ground Refer to the Using Non Referenced Single Ended NRSE Connections for Floating Signal Sources section for more information about NRSE connections When to Use Referenced Single Ended RSE Connections with Floating Signal Sources Only use RSE input connections if the input signal meets the following conditions e The input signal can share a common reference point AI GND with other signals that use RSE e The input signal is high level greater than 1 V e The leads connecting the signal to the device are less than 3 m 10 ft DIFF input connections are recommended for greater signal integrity for any input signal that does not meet the preceding conditions In the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground Refer to the Using Referenced Single Ended RSE Connections for Floating Signal Sources section for more information about RSE connections Using Differential Connections for
275. nded analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors A 18 ni com Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals
276. ng Timing Parameter Min ns Max ns tos Setup 1 5 toy Hold 0 M Series User Manual Appendix B 3 Timing Diagrams Example of the General Case Calculate the setup and hold time requirements when the Gate and Source come from PFI lines and the Gate is used in level mode Note This example shows how we determine the setup and hold times for the PFI to PFI example above first case using level gating Setup To calculate the setup time subtract the Source delay from the Gate delay Use maximum delays Gate Delay PFI to PFI_i PFI_i to Selected Gate Selected Gate to Count Enable Level Count Enable Setup Time Source Delay PFI to PFI_i PFI_i to Selected Source Tsetup gt 47 5 ns 39 2 ns 8 3 ns Hold 22 0 ns 6 0 ns 18 0 ns 1 5ns 47 5 ns 18 2 ns 21 0 ns 39 2 ns To calculate the hold time subtract the Gate delay from the Source delay Use minimum delays Gate Delay PFI to PFI_i PFI_i to Selected Gate Selected Gate to Count Enable Level Count Enable Hold Time Source Delay PFI to PFI_i PFI_i to Selected Source Thoi gt 14 2 ns 12 2 ns 2 0 ns M Series User Manual B 44 5 2 ns 1 0 ns 6 0 ns 0 0ns 12 2 ns 6 2 ns 8 0ns 14 2 ns ni com Appendix B Timing Diagrams For external triggers the timing conditions that need to be verified are as follows Tsetup Ext Tinsertion Clk Tpetay Clk
277. nnector 3 6 PCI 6220 A 2 PCI 6221 37 pin A 12 PCI 6221 68 pin A 7 PCI 6224 A 15 PCI 6225 A 21 PCI 6229 A 27 PCI 6250 A 33 PCI 6251 accessory options A 40 cabling options A 40 pinout A 38 specifications A 40 PCI 6254 A 52 PCI 6255 A 58 PCI 6259 accessory options A 66 cabling options A 66 pinout A 64 specifications A 66 PCI 6280 A 80 PCI 6281 A 85 ni com PCI 6284 A 90 PCI 6289 A 96 PCle 6251 accessory options A 40 cabling options A 40 pinout A 38 specifications A 40 PCIe 6259 accessory options A 66 cabling options A 66 pinout A 64 specifications A 66 period measurement 7 6 buffered 7 7 single 7 7 PFI 8 1 connecting input signals 8 4 exporting timing output signals using PFI terminals 8 3 filters 8 4 I O protection 8 6 programmable power up states 8 6 using terminals as static digital I Os 8 3 using terminals as timing input signals 8 2 PFI terminals as static digital I Os 8 3 pin assignments See pinouts pinouts comparison 3 4 counter default 7 30 device 1 1 NI 6220 A 2 NI 6250 A 33 NI 6254 A 52 NI 6255 A 58 NI 6221 37 pin A 12 NI 6221 68 pin A 7 NI 6224 A 15 NI 6225 A 21 NI 6229 A 27 NI 6280 A 80 National Instruments Corporation 1 11 Index NI 6281 A 85 NI 6284 A 90 NI 6289 A 96 PCI PCle PXI 6251 A 38 PCI PCle PXI 6259 A 64 RTSI connector 3 8 9 4 USB 6251 A 43 USB 6251 Mass Termination A 46 USB 6259 A 70 USB 6259 Mas
278. ns with Floating Signal Sources 4 15 When to Use Non Referenced Single Ended NRSE Connections with Floating Signal Sources ss 4 15 When to Use Referenced Single Ended RSE Connections with Floating Signal Sources ss 4 16 Using Differential Connections for Floating Signal Sources 4 16 M Series User Manual viii ni com Contents Using Non Referenced Single Ended NRSE Connections for Floating Signal SourceS iriiri ians atinira isie iiir 4 19 Using Referenced Single Ended RSE Connections for Floating SipmalSOULCES cintia estriado 4 20 Connecting Ground Referenced Signal Sources ss 4 20 What Are Ground Referenced Signal Sources 4 20 When to Use Differential Connections with Ground Referenced Signal SOULCES si sert sn nie era emilie 4 21 When to Use Non Referenced Single Ended NRSE Connections with Ground Referenced Signal Sources 4 21 When to Use Referenced Single Ended RSE Connections with Ground Referenced Signal Sources 4 22 Using Differential Connections for Ground Referenced Signal Sources 4 23 Using Non Referenced Single Ended NRSE Connections for Ground Referenced Signal Sources 4 24 Field Wiring Considerations 2 8snss nissan nn 4 25 Analog Input Timing Signals conc cnn nrnno na nonncnncrnos 4 25 Al Sample Clock Signal ss tinte sine hist tente 4 28 Using an Internal Source 4 29 Using an External Source stunt tintin nn 4 29 Routing AI
279. nstruments M Series data acquisition DAQ devices with NI DAQ 8 1 and later M Series devices feature up to 80 analog input AT channels and up to four analog output AO channels up to 48 lines of digital input output DIO and two counters lt gt gt amp e bold italic The following conventions appear in this manual Angle brackets that contain numbers separated by an ellipsis represent a range of values associated with a bit or signal name for example AO lt 3 0 gt The symbol leads you through nested menu items and dialog box options to a final action The sequence File Page Setup Options directs you to pull down the File menu select the Page Setup item and select Options from the last dialog box This icon denotes a tip which alerts you to advisory information This icon denotes a note which alerts you to important information This icon denotes a caution which advises you of precautions to take to avoid injury data loss or a system crash When this symbol is marked on a product refer to the Read Me First Safety and Radio Frequency Interference document which can be found at ni com manuals for information about precautions to take Bold text denotes items that you must select or click in the software such as menu items and dialog box options Bold text also denotes parameter names Italic text denotes variables emphasis a cross reference or an introduction to a key concept Itali
280. nstruments product line for conditioning low level signals within an external chassis near sensors so that only high level signals are sent to DAQ devices in the noisy PC environment A device that responds to a physical stimulus heat light sound pressure motion flow and so on and produces a corresponding electrical signal Primary characteristics of sensors are sensitivity frequency range and linearity 1 Electronic equipment that makes transducer or other signals suitable in level and range to be transmitted over a distance or to interface with voltage input instruments 2 The manipulation of signals to prepare them for digitizing A generic term for any instrument in the family of signal generators Signals are waveforms containing information Although physical signals can be in the form of mechanical electromagnetic or other forms they are most often converted to electronic form for measurement G 16 ni com single trigger mode single buffered single ended input single ended output software applications software triggering source impedance synchronous task TC terminal National Instruments Corporation G 17 Glossary When the arbitrary waveform generator goes through the staging list only once Describes a device that acquires a specified number of samples from one or more channels and returns the data when the acquisition is complete A circuit that responds to the voltage on one
281. ntents Note You must have Visual Studio NET installed to view the NJ Measurement Studio Help ANSI C without NI Application Software The NI DAQmx Help contains API overviews and general information about measurement concepts Select Start All Programs National Instruments NI DAQm x Help NET Languages without NI Application Software The NI Measurement Studio Help contains function reference and measurement concepts for using the Measurement Studio NI DAQmx NET and Visual C class libraries This help collection is integrated into the Visual Studio NET documentation In Visual Studio NET select Help Contents Note You must have Visual Studio NET installed to view the NJ Measurement Studio Help Device Documentation and Specifications The NI 622x Specifications contains all specifications for the NI 6220 NI 6221 NI 6224 NI 6225 and NI 6229 M Series devices The NI 625x Specifications contains all specifications for the NI 6250 NI 6251 NI 6254 NI 6255 and NI 6259 M Series devices The NI 628x Specifications contains all specifications for the NI 6280 NI 6281 NI 6284 and NI 6289 M Series devices NI DAQ 7 0 and later includes the Device Document Browser which contains online documentation for supported DAQ SCXI and switch devices such as help files describing device pinouts features and operation and PDF files of the printed device documents You can find view and or print the documents for each
282. ntering the info code rdscad for more information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your NI 6225 device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable Use Connector 0 of your NI 6225 device to control an SCC module carrier Connector 1 cannot be used with SCCs Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC Using a BNC Accessory with Connector 0 Connector 0 of your device is compatible with several BNC accessories BNC 2110 Provides BNC connectivity to all analog signals some digital signals and spring terminals for other digital signals BNC 2111 Provides BNC connectivity to 16 single ended analog input signals two analog output signals five DIO PFI signals and the external reference voltage for analog output e BNC 2120 Similar to the BNC 2110 and also has a built in function generator quadrature encoder temperature reference and thermocouple connector BNC 2090 Rack mountable device with 22 BNCs for connecting analog digital and timing signals You can use the SHC68 68 EPM shielded cable to connect Connector 0 of your DAQ device to BNC accessories Using a BNC Accessory with Connector 1 Connector 1 of your device is compatible with BNC 2115 BNC 2115 provides BNC connectivity to 24 of the differential 48 single ended analog
283. o PFI 3 8 9 3 Sample Clock Timebase RTSI 3 5 9 0 STAR 3 0 6 4 ts Delay to Sync PFI 3 4 8 5 Sample Clock Timebase RTSI 3 2 8 3 STAR 2T 5 6 te Delay to PFI 4 1 10 2 Convert Clock Timebase RTSI 3 9 9 9 STAR 3 4 7 3 t Delay to Sync PFI 3 6 8 9 Convert Clock Timebase RTSI 33 8 6 STAR 2 9 6 0 M Series User Manual B 8 ni com Appendix B Timing Diagrams Convert Clock Convert Clock is the signal that determines when an analog to digital conversion is started The signal going to the ADC is called p_AT Convert Convert Clock also can be routed to several external I O terminals for external use Convert Clock is always generated from the Convert Clock Timebase signal either directly or indirectly by dividing it down using the SI2 counter If the SI2 counter is used it is assumed that a reliable free running clock is being used Refer to the A7 Timing Clocks section for the timing relationship between Convert Clock Timebase and Sync Convert Clock Timebase If the SI2 counter is not being used external convert case the Convert Clock Timebase is assumed to be not free running and the relationship between the Convert Clock Timebase and the Sync Convert Clock Timebase is an asynchronous delay This relationship is described in this section Whether the SI2 counter is used or not the timing parameters in the generation of Convert Clock are the same starting at the Convert Clock Timebase signal Selected Reference
284. ock for digital waveform generation Therefore you must route an external signal or one of many internal signals from another subsystem to be the DO Sample Clock For example you can correlate digital and analog samples in time by sharing your AI Sample Clock or AO Sample Clock as the source of your DO Sample Clock To generate digital data independent of an AI AO or DI operation you can configure a counter to generate the desired DO Sample Clock or use an external signal as the source of the clock If the DAQ device receives a do SampleClock when the FIFO is empty the DAQ device reports an underflow error to the host software National Instruments Corporation 6 5 M Series User Manual Chapter 6 Digital 1 0 M Series User Manual Using an Internal Source To use do SampleClock with an internal source specify the signal source and the polarity of the signal The source can be any of the following signals e AI Sample Clock e AI Convert Clock e AO Sample Clock e Counter n Internal Output e Frequency Output DI Change Detection Output Several other internal signals can be routed to do SampleClock through RTSI Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information Using an External Source You can route any of the following signals as do SampleClock e PFI lt 0 15 gt e RTSI lt 0 7 gt PXI STAR e Analog Comparison Event an analog trigger You can generate sample
285. om info and enter the info code rddfms Prescaling allows the counter to count a signal that is faster than the maximum timebase of the counter M Series devices offer 8X and 2X prescaling on each counter prescaling can be disabled Each prescaler consists of a small simple counter that counts to eight or two and rolls over This counter can run faster than the larger counters which simply count the rollovers of this smaller counter Thus the prescaler acts as a frequency divider on the Source and puts out a frequency that is one eighth or one half of what it is accepting External Signal Prescaler Rollover Used as Source by Counter Counter Value 0 X 1 Figure 7 30 Prescaling 7 34 ni com Chapter 7 Counters Prescaling is intended to be used for frequency measurement where the measurement is made on a continuous repetitive signal The prescaling counter cannot be read therefore you cannot determine how many edges have occurred since the previous rollover Prescaling can be used for event counting provided it is acceptable to have an error of up to seven or one Prescaling can be used when the counter Source is an external signal Prescaling is not available if the counter Source is one of the internal timebases 80MH7Timebase 20MHzTimebase or 100kHzTimebase Duplicate Count Prevention Duplicate c
286. on 7 2 conventions used in the manual xvii count enable delay B 40 counter input and output 7 30 Counter n A signal 7 28 Counter n Aux signal 7 28 M Series User Manual 1 4 Counter n B signal 7 28 Counter n Gate signal 7 27 Counter n HW Arm signal 7 29 Counter n Internal Output signal 7 29 Counter n Source signal 7 26 Counter n TC signal 7 29 Counter n Up_Down signal 7 29 Counter n Z signal 7 28 counter output applications 7 20 counter signals Counter n A 7 28 Counter n Aux 7 28 Counter n B 7 28 Counter n Gate 7 27 Counter n HW Arm 7 29 Counter n Internal Output 7 29 Counter n Source 7 26 Counter n TC 7 29 Counter n Up_Down 7 29 FREQ OUT 7 30 Frequency Output 7 30 counter terminals default 7 30 counters 7 1 cascading 7 33 connecting terminals 7 30 duplicate count prevention 7 35 edge counting 7 2 filters 7 33 generation 7 20 input applications 7 2 other features 7 33 output applications 7 20 prescaling 7 34 pulse train generation 7 22 retriggerable single pulse generation 7 21 simple pulse generation 7 20 single pulse generation 7 20 single pulse generation with start trigger 7 20 synchronization modes 7 38 ni com timing diagrams B 37 timing signals 7 25 triggering 7 32 troubleshooting C 3 counters timing diagrams counter input delays B 37 counting edges 7 2 crosstalk when sampling multiple channels C 1 custom cabling 2 6 D DACs 5 1 DAQ hardware 2 1
287. on Another disadvantage of Method 2 is that it requires two counters if you cannot provide an external signal of known width An advantage of Method 2 is that the measurement completes in a known amount of time e Method 3 measures high and low frequency signals accurately However it requires two counters Table 7 2 summarizes some of the differences in methods of measuring frequency 7 14 ni com Table 7 2 Frequency Measurement Method Comparison Chapter 7 Counters Measures High Measures Low Number of Frequency Frequency Number of Measurements Signals Signals Method Counters Used Returned Accurately Accurately 1 1 1 Poor Good 1b 1 Many Fair Good 2 1 or2 1 Good Poor 3 2 1 Good Good For information about connecting counter signals refer to the Default Counter Timer Pinouts section Position Measurement National Instruments Corporation 7 15 You can use the counters to perform position measurements with quadrature encoders or two pulse encoders You can measure angular position with X1 X2 and X4 angular encoders Linear position can be measured with two pulse encoders You can choose to do either a single point on demand position measurement or a buffered sample clock position measurement You must arm a counter to begin position measurements Measurements Using Quadrature Encoders The counters can perform measurements of quadrature encoders that use X1 X2 or X4 encoding
288. on the following rising edge of the source as shown in Figure 7 35 Source A A Synchronize Count Figure 7 35 Other Internal Source Mode External Source Mode In external source mode the device generates a delayed Source signal by delaying the Source signal by several nanoseconds The device synchronizes signals on the rising edge of the delayed Source signal and counts on the following rising edge of the source as shown in Figure 7 36 A Source Synchronize Delayed Source Count Figure 7 36 External Source Mode National Instruments Corporation 7 39 M Series User Manual PFI M Series devices have up to 16 Programmable Function Interface PFI signals In addition M Series devices have up to 32 lines of bidirectional DIO signals Each PFI can be individually configured as the following e A Static digital input e A Static digital output e A timing input signal for AI AO DI DO or counter timer functions e A timing output signal from AI AO DI DO or counter timer functions Each PFI input also has a programmable debouncing filter Figure 8 1 shows the circuitry of one PFI line Each PFI line is similar Timing Signals Static DO Buffer LA To Input Timing Signal Selectors Direction Control 1 O Protection e PFI x P1 P2 Static DI Weak Pull Down A PFI Filters
289. onal NI DAQ Legacy and NI DAQmx M Series devices use the NI DAQm x driver Each driver has its own API hardware configuration and software configuration Refer to the DAQ Getting Started Guide for more information about the two drivers NI DAQmx includes a collection of programming examples to help you get started developing an application You can modify example code and save it in an application You can use examples to develop a new application or add example code to an existing application To locate LabVIEW and LabWindows CVI examples open the National Instruments Example Finder In LabVIEW select Help Find Examples e In LabWindows CVI select Help NI Example Finder Measurement Studio Visual Basic and ANSI C examples are located in the following directories e NI DAQmx examples for Measurement Studio supported languages are in the following directories Measurement Studio VCNET Examples NIDaq Measurement Studio DotNET Examples NIDaqg NI DAQmx examples for ANSI C are in the NI DAQ Examples DAQmx ANSI C Dev directory For additional examples refer to zone ni com National Instruments Corporation 2 7 M Series User Manual Connector Information The V O Connector Signal Descriptions M Series and E Series Pinout Comparison 5 V Power Source Disk Drive Power Connector and RTSI Connector Pinout sections contain information about M Series connectors Refer to Appendix A Devic
290. onnect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable TB 2706 uses Connector 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 56 ni com Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 57 M Series User Manual Appendix Device Speci
291. or a PFI lt gt Selected STAR_TRIG_i START gt 6 E or gt gt gt gt Re START Trigger i gt Selected Pause gt UT Pause Trigger La RTSI B a gt gt gt O National Instruments Corporation Figure B 22 M Series Analog Output Timing B 23 M Series User Manual Appendix B Timing Diagrams The signals used in this diagram and in the following sections are Sample Clock Sample Clock Timebase Sync Sample Clock Timebase START Trigger Selected START Pause Trigger Selected Pause M Series User Manual B 24 This signal multiplied by the digital to analog conversions This signal is routed to the DAC and in every pulse the DAC will perform a data conversion This signal can come directly from an external signal or can be the result of dividing down the Sample Clock Timebase using the UI counter This signal can be used to generate the Sample Clock This signal acts as the clock for the UI counter and a Sample Clock can be generated every N periods of the Sample Clock Timebase by programming the UI counter accordingly This signal can come from an internal source such as the board oscillator or an external source The Sync Sample Clock Timebase is a signal that is generated internally and is related to the Sample Clock Timebase How it is generated and the relationship between the two signals depends on the mode of operation In general
292. or an input range of 10 V to 10 V the voltage of each code of a 16 bit ADC is OV 10V 305 uV 216 M Series devices use a calibration method that requires some codes typically about 5 of the codes to lie outside of the specified range This calibration method improves absolute accuracy but it increases the nominal resolution of input ranges by about 5 over what the formula shown above would indicate Choose an input range that matches the expected input range of your signal A large input range can accommodate a large signal variation but reduces the voltage resolution Choosing a smaller input range improves the voltage resolution but may result in the input signal going out of range For more information about setting ranges refer to the NI DAQmx Help or the LabVIEW 8 x Help Tables 4 1 4 2 and 4 3 show the input ranges and resolutions supported by each M Series device family Table 4 1 Input Ranges for NI 622x Nominal Resolution Assuming Input Range 5 Over Range 10 V to 10 V 320 uV 5 V to5 V 160 uV 1Vto1V 32 uV 200 mV to 200 mV 6 4 uV Table 4 2 Input Ranges for NI 625x Nominal Resolution Assuming Input Range 5 Over Range 10 V to 10 V 320 uV 5 Vto5 V 160 uV 2 V to2 V 64 uV National Instruments Corporation 4 3 M Series User Manual Chapter 4 Analog Input Table 4 2 Input Ranges for NI 625x Continued Nominal Resol
293. os Sync Convert Clock Timebase bo t37 t37 Pause Trigger zE i t 138 t37 ia gt POUT A e Figure B 19 Pause Trigger Timing Diagram M Series User Manual B 20 ni com Output Timing Appendix B Table B 10 Pause Trigger Timing Timing Diagrams Timing Description Line Min ns Max ns t34 _i to Selected PFI 3 2 7 8 Gate RTSI 3 0 7 5 STAR 2 5 4 9 tas Selected Pause Trigger Setup 1 5 Time to Sync Convert Clock Timebase t36 Hold Sync Convert Clock 0 Timebase t37 Sync Convert Clock Timebase to 0 6 2 6 Pause Trigger og Pause Trigger RTSI 1 1 3 1 Source in _i to POUT Output timing refers to the delays involved in exporting internal signals to external terminals so they can be used to trigger or time external devices These timing parameters include the selection multiplexer in each terminal plus the delay of the output driver Figures B 20 and B 21 and Table B 11 describe output timing The delays presented in this section assume a 200 pF load on PFI lines and a 50 pF load on RTSI lines Actual delays will vary with the actual load National Instruments Corporation B 21 M Series User Manual Appendix B Timing Diagrams Terminal e be Selected Reference Trigger Reference Trigger S Terminal Y Selected Pau
294. ount prevention or synchronous counting mode ensures that a counter returns correct data in applications that use a slow or non periodic external source Duplicate count prevention applies only to buffered counter applications such as measuring frequency or period In such buffered applications the counter should store the number of times an external Source pulses between rising edges on the Gate signal Example Application That Works Correctly No Duplicate Counting Figure 7 31 shows an external buffered signal as the period measurement Source Gate Source Counter Value Buffer Rising Edge of Gate Counter detects rising edge of Gate on the next rising edge of Source 6 X7 X2 Xa 7 D Figure 7 31 Duplicate Count Prevention Example On the first rising edge of the Gate the current count of 7 is stored On the next rising edge of the Gate the counter stores a 2 since two Source pulses occurred after the previous rising edge of Gate National Instruments Corporation 7 35 M Series User Manual Chapter 7 Counters The counter synchronizes or samples the Gate signal with the Source signal so the counter does not detect a rising edge in the Gate until the next Source pulse In this example the counter stores the values in the buffer on the first rising Source edge after the rising edge of Gate The details of whe
295. ounter 1 e Digital waveform generation digital output e Digital waveform acquisition digital input Each DMA controller channel contains a FIFO and independent processes for filling and emptying the FIFO This allows the buses involved in the transfer to operate independently for maximum performance Data is National Instruments Corporation 10 1 M Series User Manual Chapter 10 Bus Interface transferred simultaneously between the ports The DMA controller supports burst transfers to and from the FIFO Each DMA controller acts as a PCI Master device The DMA controllers support scatter gather operations to and from host memory Memory buffers may be used in linear or circular fashion Each DMA controller supports packing and unpacking of data through the FIFOs to connect different size devices and optimize PCI bus utilization and automatically handles unaligned memory buffers M Series USB devices have four fully independent USB Signal Streams for high performance transfers of data blocks These channels are assigned to the first four measurement acquisition circuits that request one PXI Considerations 3 Note PXI clock and trigger signals are only available on PXI devices PXI Clock and Trigger Signals Refer to the PXI_CLK10 PXI Triggers PXI_STAR Trigger PXI_ STAR Filters sections of Chapter 9 Digital Routing and Clock Generation for more information about PXI clock and trigger signals PXI and PXI Express M
296. ounter counts the number of rising or falling edges on the Source The counter ignores additional edges on the Aux input The counter stops counting upon receiving an active edge on the Gate input The counter stores the count in a hardware save register You can configure the rising or falling edge of the Aux input to be the active edge You can configure the rising or falling edge of the Gate input to be the active edge Use this type of measurement to count events or measure the time that occurs between edges on two signals This type of measurement is sometimes referred to as start stop trigger measurement second gate measurement or A to B measurement Single Two Signal Edge Separation Measurement With single two signal edge separation measurement the counter counts the number of rising or falling edges on the Source input occurring between an active edge of the Gate signal and an active edge of the Aux signal The counter then stores the count in a hardware save register and ignores other edges on its inputs Software then reads the stored count M Series User Manual 7 18 ni com Chapter 7 Counters Figure 7 20 shows an example of a single two signal edge separation measurement Counter Armed i t Measured Interval AUX GATE y source ILI UU UUUUUUUUU UI Counter Value 00001 2 3 4 5 6 7 8 8 8 HW Save Register 8 Figure 7 20 Single Two Signal E
297. out eee eeeeeeeeeeneeeneeeens Figure A 3 NI 6221 37 Pin Pinout ee eeeeeeeneeeneeeens Figure A 4 NI 6224 Pinout oonccnnncnnnconononcnnnonnnononnnonnnonccnnccnncnnos Figure A 5 YNI 6225 PinOut sense Figure A 6 NI 6229 Pinout conccnncnnnnconononconnnnnnnnconnnonconcnnnccnncnnos Figure A 7 NI 6250 Pinout oonconnccnnnconononconnnnncnnnonnconcnnncnnccnncnnos Figure A 8 PCI PCIe PXI 6251 Pinout n Figure A 9 USB 6251 Pinout 0 eee eee eeeeseeseeeeeneeeaes Figure A 11 USB 6251 Mass Termination Pinout 0 00 0 Figure A 13 NI 6254 Pinout Figure A 14 NI 6255 Pinout oooonnccnnnnonononcnnnnnncnnnonnnannonnnnncrnncnnos Figure A 15 PCI PCIe PXI 6259 Pinout 0 00 eeeeee Figure A 16 USB 6259 Pinout eee ese eseeseeseeneeneeeaes National Instruments Corporation XV Contents M Series User Manual Contents Figure A 18 USB 6259 Mass Termination Pinout A 75 Figure A 20 NI 6280 Pinout cicc3s scc eissaisisdecesssscosescadseogsensigagcascssdbeadescesaseidancesvenaiaes A 81 Figure A 21 NT 6281 Pinolt ccoo incite dista A 86 Figure A222 NT 6284 Pinouts c2s c2 ccscescssacescasesscaqaeevcassgesbeenebatasoneceseaedsgeeeetcdyebtesetsdss A 91 Figure A 23 NL 6289 Pinout s ste menti einen A 97 M Series User Manual xvi ni com About This Manual Conventions The M Series User Manual contains information about using the National I
298. owing steps to install the disk drive power connector 1 Power off and unplug the computer 2 Remove the computer cover 3 Attach the PC disk drive power connector to the disk drive power connector on the device as shown in Figure 3 1 3 Note The power available on the disk drive power connectors in a computer can vary For example consider using a disk drive power connector that is not in the same power chain as the hard drive 1 Device Disk Drive Power Connector 2 PC Disk Drive Power Connector Figure 3 1 Connecting to the Disk Drive Power Connector 4 Replace the computer cover and plug in and power on the computer Self calibrate the PCI Express DAQ device in MAX by following the instructions in Calibrating DAQ Devices in the Measurement amp Automation Explorer Help 3 Note Connecting or disconnecting the disk drive power connector can affect the analog performance of your device To compensate for this NI recommends that you self calibrate after connecting or disconnecting the disk drive power connector National Instruments Corporation 3 7 M Series User Manual Chapter 3 Connector Information RTSI Connector Pinout Refer to the RTSI Connector Pinout section of Chapter 9 Digital Routing and Clock Generation for information about the RTSI connector M Series User Manual 3 8 ni com Analog Input Figure 4 1 shows the analog input circuitry of M Series devices
299. pin connector such as the NI PCI PCIe PXI 6251 Refer to ni com for other accessory options including new devices SCXI SCXI is a programmable signal conditioning system designed for measurement and automation applications To connect your M Series device to an SCXI chassis use the SCXI 1349 adapter and an SHC68 68 EPM cable You also can use an M Series device to control the SCXI section of a PXI SCXI combination chassis such as the PXI 1010 or PXI 1011 The M Series device in the rightmost PXI slot controls the SCXI devices No cables or adapters are necessary Refer to the SCXT Advisor available by going to ni com info and entering the info code rdscad for more information A 40 ni com Appendix Device Specific Information SCC SCC provides portable modular signal conditioning to your DAQ system To connect your M Series device to an SCC module carrier such as the SC 2345 or SC 2350 use an SHC68 68 EPM shielded cable 3 Note PCI Express users should consider the power limits on certain SCC modules without an external power supply Refer to the NI 625x Specifications and the Disk Drive Power Connector section of Chapter 3 Connector Information for information about power limits and increasing the current the device can supply on the 5 V terminal Refer to the SCC Advisor available by going to ni com info and entering the info code rdscav for more information BNC You can use the SHC68 68 EPM shielded cable
300. pling with AI Sample Clock and AI Convert Clock C 2 charge injection C 1 choosing frequency measurement 7 13 circular buffered acquisition 4 12 clock 10 MHz reference 9 3 external reference 9 2 generation 9 1 PXI and trigger signals 9 8 routing 9 1 clock generation timing diagrams B 48 CompactPCI using with PXI 10 3 configuring AI ground reference settings in software 4 7 connecting analog input signals 4 13 analog output signals 5 6 counter signals C 3 digital I O signals 6 9 floating signal sources 4 15 ground referenced signal sources 4 20 PFI input signals 8 4 M Series User Manual Index connections for floating signal sources 4 20 single ended for floating signal sources 4 20 single ended RSE configuration 4 20 connector information 3 1 NI 6220 pinout A 2 NI 6250 pinout A 33 NI 6254 pinout A 52 NI 6255 pinout A 58 NI 6221 37 pin pinout A 12 NI 6221 68 pin pinout A 7 NI 6224 pinout A 15 NI 6225 pinout A 21 NI 6229 pinout A 27 NI 6280 pinout A 80 NI 6281 pinout A 85 NI 6284 pinout A 90 NI 6289 pinout A 96 PCI PCle PXI 6251 pinout A 38 PCI PCle PXI 6259 pinout A 64 RTSI 3 8 USB 6251 Mass Termination pinout A 46 USB 6251 pinout A 43 USB 6259 Mass Termination pinout A 74 USB 6259 pinout A 70 considerations for field wiring 4 25 for multichannel scanning 4 8 for PXI 10 2 continuous pulse train generation 7 22 controller DMA 10 1 controlling counting directi
301. poration All rights reserved Important Information Warranty M Series devices are warranted against defects in materials and workmanship for a period of three years from the date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace equipment that proves to be defective during the warranty period This warranty includes parts and labor The media on which you receive National Instruments software are warranted not to fail to execute programming instructions due to defects in materials and workmanship for a period of 90 days from date of shipment as evidenced by receipts or other documentation National Instruments will at its option repair or replace software media that do not execute programming instructions if National Instruments receives notice of such defects during the warranty period National Instruments does not warrant that the operation of the software shall be uninterrupted or error free A Return Material Authorization RMA number must be obtained from the factory and clearly marked on the outside of the package before any equipment will be accepted for warranty work National Instruments will pay the shipping costs of returning to the owner parts which are covered by warranty National Instruments believes that the information in this document is accurate The document has been carefully reviewed for technical accuracy In the event that technical or typographi
302. pulse on its Gate input signal You can configure the counter to measure the width of high pulses or low pulses on the Gate signal You can route an internal or external periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges on the Source signal while the pulse on the Gate signal is active You can calculate the pulse width by multiplying the period of the Source signal by the number of edges returned by the counter A pulse width measurement will be accurate even if the counter is armed while a pulse train is in progress If a counter is armed while the pulse is in the active state it will wait for the next transition to the active state to begin the measurement Single Pulse Width Measurement With single pulse width measurement the counter counts the number of edges on the Source input while the Gate input remains active When the Gate input goes inactive the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs Software then reads the stored count Figure 7 6 shows an example of a single pulse width measurement GATE ae Oo MAA source 1 414 ry Counter Value 0 1 2 HW Save Register 2 Figure 7 6 Single Pulse Width Measurement Buffered Pulse Width Measurement Buffered pulse width measurement is similar to single pul
303. quently asked questions about M Series devices National Instruments Corporation C 3 M Series User Manual Upgrading from E Series to M Series The following KnowledgeBase and Developer Zone documents will help you overcome typical hurdles in upgrading from E Series to M Series devices National Instruments Corporation Major Differences Between E Series and M Series DAQ Devices KnowledgeBase lists the advantages of M Series over E Series and the functional differences and other differences between the two DAQ device families To access this KnowledgeBase go to ni com info and enter the info code rdmess Migrating an Application from E Series to M Series Developer Zone document highlights the main differences to remember when moving an application from E Series to M Series devices To access this document go to ni com info and enter the info code rde2m1 Using E Series Accessories with M Series Devices KnowledgeBase describes how to use 68 pin E Series accessories with M Series devices To access this KnowledgeBase go to ni com info and enter the info code rdea2m M Series or S Series Devices Are Not Detected During Installation on Some Computers KnowledgeBase describes the difference between M Series and E Series power rails and the PCI specification for the PCI bus and power rails and contains an up to date list of computers with power rails that do not support M Series devices To access this KnowledgeBase go to ni
304. r you must decide how you want to produce the trigger and the action you want the trigger to cause All M Series devices support internal software triggering as well as external digital triggering Some devices also support analog triggering For information about the different actions triggers can perform for each sub system of the device refer to the following sections e The Analog Input Triggering section of Chapter 4 Analog Input e The Analog Output Triggering section of Chapter 5 Analog Output e The Counter Triggering section of Chapter 7 Counters My Note Not all M Series devices support analog triggering For more information about triggering compatibility refer to the specifications document for your device Triggering with a Digital Source Your DAQ device can generate a trigger on a digital signal You must specify a source and an edge The digital source can be any of the PFI RTSI or PXI_STAR signals The edge can be either the rising edge or falling edge of the digital signal A rising edge is a transition from a low logic level to a high logic level A falling edge is a high to low transition Figure 11 1 shows a falling edge trigger 5V Digital Trigger OV Falling Edge Initiates Acquisition Figure 11 1 Falling Edge Trigger National Instruments Corporation 11 1 M Series User Manual Chapter 11 Triggering You also can program your DAQ device to perform an action in response to a trigger
305. r 0 of your PXI device After a TB 2706 is installed Connector 1 cannot be used 2 NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 31 M Series User Manual Appendix Device Specific Information Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions M Series User Manual A 32 ni com Appendix Device Specific Information NI 6250 NI 6250 Pinout Figure A 7 shows the pinout of the NI 6250 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information 3 Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information National Instruments Corporation A 33 M Series User Manual Appendix Device Specific Information M Series User Manual AIO Al GND AI9 Al2 Al GND Al 11 Al SENSE Al 12 AI5 AI GND Al 14 Al7 Al GND NC NC D GND PO 0 PO 5 D GND P0 2 PO 7
306. r Manual In edge counting applications the counter counts edges on its Source after the counter is armed You can configure the counter to count rising or falling edges on its Source input You also can control the direction of counting up or down The counter values can be read on demand or with a sample clock Single Point On Demand Edge Counting With single point on demand edge counting the counter counts the number of edges on the Source input after the counter is armed On demand refers to the fact that software can read the counter contents at any time without disturbing the counting process Figure 7 2 shows an example of single point edge counting Counter Armed SOURCE __ 414 EII Counter Value 0 1 2 3 4 5 Figure 7 2 Single Point On Demand Edge Counting You also can use a pause trigger to pause or gate the counter When the pause trigger is active the counter ignores edges on its Source input When the pause trigger is inactive the counter counts edges normally You can route the pause trigger to the Gate input of the counter You can configure the counter to pause counting when the pause trigger is high or when it is low Figure 7 3 shows an example of on demand edge counting with a pause trigger 7 2 ni com Chapter 7 Counters Counter Armed Pause Trigger Pause When Low ____t L DAA 0 1 2 3 4 5 SOURCE Counter
307. r block e TB 2706 front panel mounted terminal block for PXI M Series devices RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required A 10 ni com Appendix Device Specific Information Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices National Instruments Corporation A 11 M Series User Manual Appendix NI 6221 37 Pin M S
308. r project challenges National Instruments Alliance Partner members can help To learn more call your local NI office or visit ni com alliance Declaration of Conformity DoC A DoC is our claim of compliance with the Council of the European Communities using the manufacturer s declaration of conformity This system affords the user protection for electronic compatibility EMC and product safety You can obtain the DoC for your product by visiting ni com certification E 1 M Series User Manual Appendix E Technical Support and Professional Services e Calibration Certificate If your product supports calibration you can obtain the calibration certificate for your product at ni com calibration If you searched ni com and could not find the answers you need contact your local office or NI corporate headquarters Phone numbers for our worldwide offices are listed at the front of this manual You also can visit the Worldwide Offices section of ni com niglobal to access the branch office Web sites which provide up to date contact information support phone numbers email addresses and current events M Series User Manual E 2 ni com Glossary Symbol Prefix Value p pico 10712 n nano 1072 u micro 1076 m milli 1073 k kilo 103 M mega 10 G giga 10 T tera 192 Symbols Percent Positive of or plus Negative of or minus Plus or minus lt Less than gt Gre
309. r you can use the internal ground signal refer to Internal Channels in the NI DAQmx Help Set the input range of channel 2 to 200 mV to 200 mV to match channel 1 Then scan channels in the order 0 2 1 Inserting a grounded channel between signal channels improves settling time because the NI PGIA adjusts to the new input range setting faster when the input is grounded Minimize Voltage Step between Adjacent Channels When scanning between channels that have the same input range the settling time increases with the voltage step between the channels If you know the expected input range of your signals you can group signals with similar expected ranges together in your scan list For example suppose all channels in a system use a 5 to 5 V input range The signals on channels 0 2 and 4 vary between 4 3 V and 5 V The signals on channels 1 3 and 5 vary between 4 V and 0 V Scanning channels in the order 0 2 4 1 3 5 produces more accurate results than scanning channels in the order 0 1 2 3 4 5 Avoid Scanning Faster Than Necessary M Series User Manual Designing your system to scan at slower speeds gives the NI PGIA more time to settle to a more accurate level Here are two examples to consider Example 1 Averaging many Al samples can increase the accuracy of the reading by decreasing noise effects In general the more points you average the more accurate the final result However you may choose to decrease th
310. rated in a commercial environment This equipment generates uses and can radiate radio frequency energy and if not installed and used in accordance with the instruction manual may cause harmful interference to radio communications Operation of this equipment in a residential area is likely to cause harmful interference in which case the user is required to correct the interference at their own expense Canadian Department of Communications This Class A digital apparatus meets all requirements of the Canadian Interference Causing Equipment Regulations Cet appareil num rique de la classe A respecte toutes les exigences du R glement sur le mat riel brouilleur du Canada Compliance with EU Directives Users in the European Union EU should refer to the Declaration of Conformity DoC for information pertaining to the CE marking Refer to the Declaration of Conformity DoC for this product for any additional regulatory compliance information To obtain the DoC for this product visit ni com certification search by model number or product line and click the appropriate link in the Certification column The CE marking Declaration of Conformity contains important supplementary information and instructions for the user or installer Contents About This Manual CONVENTIONS melitas elements Related Documentation NI DAQmx for Windows NI DAQmx for Linux NI DAQmx Base LaDVIE Wicca nec tre Mana as LabWindows CVE
311. red Cables In most applications you can use the following cables SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differential analog input channel is routed on an individually shielded twisted pair of wires Analog outputs are also individually shielded e SHC68 68 A lower cost shielded cable with 34 twisted pairs of wire e RC68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions NI recommends that you use the SHC68 68 EPM cable however an SHC68 68 EP cable will work with M Series devices M Series User Manual A 42 ni com Appendix Device Specific Information USB 6251 Pinout Figure A 9 shows the pinout of the USB 6251 For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ALO is 17 Al4 EOG GS ST SI 81 PFI8 18 Al 12 Gj 82 D GND AI 8 2 IS PO 1 66 I 19 AI GND SI 83 PFI9 Al GND 3189 P02 67 8 20 Al5 S 84 D GND AI 1 418 P0 3 68 S 21 Al13 SI 8
312. remove the lid 2 Replace the fuse while referring to Figure A 12 for the fuse location A 50 ni com National Instruments Corporation Appendix Device Specific Information A os aye er TK o O 0 O a ES y 3 A 51 Figure A 12 USB 6251 Mass Termination Fuse Location Replace the lid and screws M Series User Manual Appendix Device Specific Information NI 6254 NI 6254 Pinout Figure A 13 shows the pinout of the NI 6254 The I O signals appear on two 68 pin connectors For a detailed description of each signal refer to the 7 0 Connector Signal Descriptions section of Chapter 3 Connector Information ik Note M Series devices may be used with most E Series accessories However some E Series accessories use different terminal names Refer to the M Series and E Series Pinout Comparison section of Chapter 3 Connector Information for more information M Series User Manual A 52 ni com Appendix Device Specific Information ALO 68 34 Als P0 30 1 35 D GND Al GND 67 33 Alt P0 28 2 36 D GND Al
313. rence Trigger is the signal chosen to be the Reference Trigger before itis synchronized just after the selection mux M Series User Manual Timing Diagrams Appendix B Timing Diagrams Selected Sample The Sample Clock marks the beginning of a Clock and Sample new sample This signal can be an external or Clock internal signal When an internal signal it can be generated with the SI counter dividing the Sample Clock Timebase signal It also can come from an external terminal or from a signal from another internal resource inside the M Series device Selected Sample Clock is the signal selected to become Sample Clock before after any synchronization just after the selection mux Selected Pause The Pause Trigger can be used to pause the Trigger and Pause acquisition for a certain period of time Trigger Selected Pause Trigger is the signal that becomes the Pause Trigger signal before synchronization p_AL Convert The signal that starts the conversions of data at the ADC component This signal goes directly to the ADC but copies can be routed to output terminals Input Timing Input timing refers to the delays involved in importing external signals to be used as triggers or clocks in the Al timing engine Figures B 2 and B 3 and Table B 1 describe the insertion delays for external signals M Series User Manual B 4 ni com Appendix B Timing Diagrams Selected Reference Trigger Reference Trigger Terminal e
314. rigger 5 9 AO Sample Clock 5 10 AO Sample Clock Timebase 5 12 AO Start Trigger 5 8 Change Detection Event 6 8 connecting analog input 4 13 connecting analog output 5 6 connecting counter C 3 connecting digital I O 6 9 connecting PFI input 8 4 Counter n A 7 28 Counter n Aux 7 28 Counter n B 7 28 Counter n Gate 7 27 Counter n HW Arm 7 29 Counter n Internal Output 7 29 Counter n Source 7 26 Counter n TC 7 29 National Instruments Corporation 1 13 Index Counter n Up_Down 7 29 Counter n Z 7 28 counters 7 25 DI Sample Clock 6 4 DO Sample Clock 6 5 exporting timing output using PFI terminals 8 3 FREQ OUT 7 30 Frequency Output 7 30 minimizing output glitches C 3 output minimizing glitches on 5 4 simple pulse generation 7 20 single period measurement 7 7 point edge counting 7 2 pulse generation 7 20 retriggerable 7 21 with start trigger 7 20 pulse width measurement 7 5 semi period measurement 7 8 two signal edge separation measurement 7 18 single ended connections RSE configuration 4 20 single ended connections for floating signal sources 4 20 software configuring AI ground reference settings 4 7 programming devices 2 6 software NI resources E 1 software timed acquisitions 4 11 generations 5 4 specifications A 1 device 1 2 NI 6220 A 4 NI 6221 A 9 NI 6224 A 17 NI 6225 A 23 NI 6229 A 29 M Series User Manual Index NI 6250 A 35 NI 6254 A 54 NI 6255 A 60
315. rigger lines may be divided into multiple independent buses Refer to the documentation for your chassis for details In a PXI system the Star Trigger bus implements a dedicated trigger line between the first peripheral slot adjacent to the system slot and the other peripheral slots The Star Trigger can be used to synchronize multiple devices or to share a common trigger signal among devices A Star Trigger controller can be installed in this first peripheral slot to provide trigger signals to other peripheral modules Systems that do not require this functionality can install any standard peripheral module in this first peripheral slot An M Series device receives the Star Trigger signal PXI_STAR from a Star Trigger controller PXI_STAR can be used as an external source for many AI AO and counter signals 9 8 ni com PXI_STAR Filters Chapter 9 Digital Routing and Clock Generation An M Series device is not a Star Trigger controller An M Series device may be used in the first peripheral slot of a PXI system but the system will not be able to use the Star Trigger feature You can enable a programmable debouncing filter on each PFI RTSL or PXI_STAR signal When the filters are enabled your device samples the input on each rising edge of a filter clock M Series devices use an onboard oscillator to generate the filter clock with a 40 MHZ frequency 3 Note NI DAQmx only supports filters on counter inputs The following is an
316. rter or to buffer the data before or after bus transmission The first data stored is the first data sent to the acceptor FIFOs are often used on DAQ devices to temporarily store incoming or outgoing data until that data can be retrieved or output For example an analog input FIFO stores the results of A D conversions until the data can be retrieved into system memory a process that requires the servicing of interrupts and often the programming of the DMA controller This process can take several milliseconds in some cases During this time data accumulates in the FIFO for future retrieval With a larger FIFO longer latencies can be tolerated In the case of analog output a FIFO permits faster update rates because the waveform data can be stored on the FIFO ahead of time This again reduces the effect of latencies associated with getting the data from system memory to the DAQ device A physical device or digital algorithm that selectively removes noise from a signal or emphasizes certain frequency ranges and de emphasizes others Electronic filters include lowpass band pass and highpass types Digital filters can operate on numeric data to perform equivalent operations on digitized analog data or to enhance video images A type of signal conditioning that allows you to filter unwanted frequency components from the signal you are trying to measure G 8 ni com floating floating signal sources FREQ OUT frequency ft function
317. ruments NI DAQ DAQ Getting Started Guide The NI DAQ Readme lists which devices are supported by this version of NI DAQ Select Start All Programs National Instruments NI DAQ NI DAQ Readme The NI DAQmx Help contains general information about measurement concepts key NI DAQmx concepts and common applications that are applicable to all programming environments Select Start All Programs National Instruments NI DAQ NI DAQmx Help xviii ni com About This Manual NI DAQmx for Linux The DAQ Getting Started Guide describes how to install your NI DAQmx supported DAQ device and confirm that your device is operating properly The NI DAQ Readme for Linux lists supported devices and includes software installation instructions frequently asked questions and known issues The C Function Reference Help describes functions and attributes The NI DAQmx for Linux Configuration Guide provides configuration instructions templates and instructions for using test panels Sy Note All NI DAQmx documentation for Linux is installed at usr local natinst nidagmx docs NI DAQmx Base The NI DAQmx Base Getting Started Guide describes how to install your NI DAQmx Base software your NI DAQmx Base supported DAQ device and how to confirm that your device is operating properly Select Start All Programs National Instruments NI DAQmx Base Documentation Getting Started Guide The NI DAQmx Base Readme lists which devices are support
318. s Termination A 74 pins default 7 30 position measurement 7 15 power connector PCI Express disk drive 3 6 power rail D 1 power 5 V 3 6 power up states 6 7 8 6 prescaling 7 34 programmable function interface 8 1 programmable power up states 6 7 8 6 programmed I O 10 4 changing data transfer methods 10 5 programming devices in software 2 6 programming examples NI resources E 1 pulse encoders 7 17 pulse generation for ETS 7 24 pulse train generation 7 22 continuous 7 22 pulse width measurement 7 5 buffered 7 5 single 7 5 PXI and PXI Express 10 2 clock 10 2 clock and trigger signals 9 8 considerations 10 2 trigger signals 10 2 triggers 9 8 using with CompactPCI 10 3 PXI Express chassis compatibility 10 2 M Series User Manual Index PXI_CLK10 9 8 PXI_STAR filters 9 9 trigger 9 8 PXI 6220 A 2 PXI 6221 68 pin A 7 PXI 6224 A 15 PXI 6225 A 21 PXI 6229 A 27 PXI 6250 A 33 PXI 6251 accessory options A 40 cabling options A 40 pinout A 38 specifications A 40 PXI 6254 A 52 PXI 6255 A 58 PXI 6259 accessory options A 66 cabling options A 66 pinout A 64 specifications A 66 PXI 6280 A 80 PXI 6281 A 85 PXI 6284 A 90 PXI 6289 A 96 Q quadrature encoders 7 15 R range analog input 4 2 real time system integration bus 9 4 reciprocal frequency measurement 7 12 reference clock 10 MHz 9 3 external 9 2 reference trigger analog input internal
319. s depend on the gating mode Depending on the application the counter timers either level gating mode or edge gating mode In NI DAQm x the counter timers use level gating mode for the following measurements Edge counting Pulse width measurements e Two signal edge separation measurements All other measurements use edge gating mode Quadrature and Two Pulse Encoder Timing Counter n A Counter n B and Counter n Z described in the Counter n A Counter n B and Counter n Z Signals section of Chapter 7 Counters are used in position measurements using quadrature encoder or two pulse encoder counting modes Table B 35 shows the timing requirements for these signals tia i i oD 1 1 ots io ts 3 bo ma Counter nA sieve i i tie i poto i 7 on 1 E AA 1 1 Counter nB 1 Ho E Counter n Z p tig tig gt gt Figure B 50 Quadrature and Two Pulse Encoder Timing Diagrams National Instruments Corporation B 47 M Series User Manual Appendix B Timing Diagrams Table B 35 Quadrature and Two Pulse Encoder Timing Timing Description Min ns Max ns tia Counter n A Period 50 0 tis Counter n A Pulse Width 25 0 tie Counter n B Period 50 0 ti7 Counter n B Pulse Width 25 0 tig Counter n Z Pulse Width 25 0 tio Delay from Counter n
320. s on the rising or falling edge of do SampleClock You must ensure that the time between two active edges of do SampleClock is not too short If the time is too short the DO waveform generation FIFO is not able to read the next sample fast enough The DAQ device reports an overrun error to the host software Routing DO Sample Clock to an Output Terminal You can route do SampleClock out to any PFI terminal The PFI circuitry inverts the polarity of do SampleClock before driving the PFI terminal 6 6 ni com Chapter 6 Digital I O 1 0 Protection Each DIO and PFI signal is protected against overvoltage undervoltage and overcurrent conditions as well as ESD events However you should avoid these fault conditions by following these guidelines e Ifyou configure a PFI or DIO line as an output do not connect it to any external signal source ground signal or power supply e If you configure a PFI or DIO line as an output understand the current requirements of the load connected to these signals Do not exceed the specified current output limits of the DAQ device NI has several signal conditioning solutions for digital applications requiring high current drive e Ifyou configure a PFI or DIO line as an input do not drive the line with voltages outside of its normal operating range The PFI or DIO lines have a smaller operating range than the AI signals e Treat the DAQ device as you would treat any static sensitive device Alwa
321. se Trigger D Pause Trigger SI Start Terminal Le SI Sample Clock Timebase Counter pe Sync Sample Clock Timebase Block O gt SLICy j lt 12 Convert Clock Timebase Pio SI2_TC lt Block Sync Convert Clock Timebase 1 Start A Y Terminal gt Selected Sample Clock 7 e Terminal so e Selected Start Figure B 20 Output Timing and the Analog Input Timing Engine Terminal Figure B 21 Output Timing Diagram Table B 11 Output Timing Edge Line Min ns Max ns Rising Edge PFI 7 2 25 7 RTSI 5 6 14 0 Falling Edge PFI 135 25 9 RTSI 6 0 13 9 M Series User Manual B 22 ni com Appendix B Timing Diagrams Analog Output Timing Diagrams The analog output timing can be broken into the following three sections Signal Definitions Input Timing The timing for external signals to enter the M Series device and be available on the internal signal buses Internal Analog Output Timing The timing specifications of the analog output unit itself to and from internal signals Output Timing The timing of exported signals going to the M Series device external terminals Figure B 22 gives an overview of analog output timing Other Internal Internal Sources Sources Sample Ps Clock gt Timebase AO TIMER Sample Clock STAR_TRIG gt RTSI
322. se width measurement but buffered pulse width measurement takes measurements over multiple pulses National Instruments Corporation 7 5 M Series User Manual Chapter 7 Counters The counter counts the number of edges on the Source input while the Gate input remains active On each trailing edge of the Gate signal the counter stores the count in a hardware save register A DMA controller transfers the stored values to host memory Figure 7 7 shows an example of a buffered pulse width measurement GATE source LAL ALIAS Counter Value Buffer 3 2 Figure 7 7 Buffered Pulse Width Measurement Note that if you are using an external signal as the Source at least one Source pulse should occur between each active edge of the Gate signal This condition ensures that correct values are returned by the counter If this condition is not met consider using duplicate count prevention described in the Duplicate Count Prevention section For information about connecting counter signals refer to the Default Counter Timer Pinouts section Period Measurement M Series User Manual In period measurements the counter measures a period on its Gate input signal after the counter is armed You can configure the counter to measure the period between two rising edges or two falling edges of the Gate input signal You can route an internal or ex
323. se within the sample By default this delay is three ticks of ai ConvertClockTimebase Figure 4 17 shows the relationship of ai SampleClock to ai ConvertClock ai ConvertClockTimebase ai SampleClock ai ConvertClock 4 Pit gt Delay Convert From Period Sample Clock M Series User Manual Figure 4 17 ai SampleClock and ai ConvertClock 4 32 ni com Chapter 4 Analog Input Other Timing Requirements The sample and conversion level timing of M Series devices work such that clock signals are gated off unless the proper timing requirements are met For example the device ignores both ai SampleClock and ai ConvertClock until it receives a valid ai StartTrigger signal Once the device recognizes an ai SampleClock pulse it ignores subsequent ai SampleClock pulses until it receives the correct number of ai ConvertClock pulses Similarly the device ignores all ai ConvertClock pulses until it recognizes an ai SampleClock pulse Once the device receives the correct number of ai ConvertClock pulses it ignores subsequent ai ConvertClock pulses until it receives another ai SampleClock Figures 4 18 4 19 4 20 and 4 21 show timing sequences for a four channel acquisition using AI channels 0 1 2 and 3 and demonstrate proper and improper sequencing of ai SampleCloc
324. shielded R68 68 A highly flexible unshielded ribbon cable Custom Cabling and Connectivity The CA 1000 is a configurable enclosure that gives user defined connectivity and flexibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 49 M Series User Manual Appendix Device Specific Information USB 6251 Mass Termination LED Patterns The USB 6251 Mass Termination device has two LEDs labeled ACTIVE and READY The ACTIVE LED indicates activity over the bus The READY LED indicates whether or not the device is configured Table A 12 shows the behavior of the LEDs Table A 12 USB 6251 Mass Termination LED Patterns ACTIVE LED READY LED USB 6251 State Off Off The device is either not connected to the host computer or not powered Off On The device is configured but there is no activity over the bus On On The device is configured and there is activity over the bus Blinking On M Series User Manual USB 6251 Mass Termination Fuse Replacement USB 6251 Mass Termination devices have a replaceable 2A 250V 5 x 20 mm fuse To remove the fuse from the USB 6251 Mass Termination device complete the following steps 1 Loosen the four flathead Phillips screws that attach the lid to the enclosure and
325. sitions Hardware timed acquisitions can be buffered or non buffered Software Timed Acquisitions With a software timed acquisition software controls the rate of the acquisition Software sends a separate command to the hardware to initiate each ADC conversion In NI DAQmx software timed acquisitions are referred to as having on demand timing Software timed acquisitions are also referred to as immediate or static acquisitions and are typically used for reading a single sample of data Hardware Timed Acquisitions With hardware timed acquisitions a digital hardware signal ai SampleClock controls the rate of the acquisition This signal can be generated internally on your device or provided externally National Instruments Corporation 4 11 M Series User Manual Chapter 4 Analog Input M Series User Manual Hardware timed acquisitions have several advantages over software timed acquisitions e The time between samples can be much shorter The timing between samples is deterministic e Hardware timed acquisitions can use hardware triggering Hardware timed operations can be buffered or non buffered A buffer is a temporary storage in computer memory for to be generated samples Buffered In a buffered acquisition data is moved from the DAQ device s onboard FIFO memory to a PC buffer using DMA or interrupts before it is transferred to application memory Buffered acquisitions typically allow for much faster transfer rat
326. t 11 2 ni com Chapter 11 Triggering Analog Input Channels Select any analog input channel to drive the NI PGIA The NI PGIA amplifies the signal as determined by the input ground reference setting and the input range The output of the NI PGIA then drives the analog trigger detection circuit By using the NI PGIA you can trigger on very small voltage changes in the input signal When the DAQ device is waiting for an analog trigger with a AI channel as the source the AI muxes should not route different AI channels to the NI PGIA If a different channel is routed to the NI PGIA the trigger condition on the desired channel could be missed The other channels also could generate false triggers This behavior places some restrictions on using AI channels as trigger sources When you use an analog start trigger the trigger channel must be the first channel in the channel list When you use an analog reference or pause trigger and the analog channel is the source of the trigger there can be only one channel in the channel list Analog Trigger Actions The output of the analog trigger detection circuit is the Analog Comparison Event signal You can program your DAQ device to perform an action in response to the Analog Comparison Event signal The action can affect the following e Analog input acquisition e Analog output generation Counter behavior Routing Analog Comparison Event to an Output Terminal You can route Analog Co
327. t is operated this Class A product could be subject to restrictions in the FCC rules In Canada the Department of Communications DOC of Industry Canada regulates wireless interference in much the same way Digital electronics emit weak signals during normal operation that can affect radio television or other wireless products All Class A products display a simple warning statement of one paragraph in length regarding interference and undesired operation The FCC rules have restrictions regarding the locations where FCC Class A products can be operated Consult the FCC Web site at www fcc gov for more information FCC DOC Warnings This equipment generates and uses radio frequency energy and if not installed and used in strict accordance with the instructions in this manual and the CE marking Declaration of Conformity may cause interference to radio and television reception Classification requirements are the same for the Federal Communications Commission FCC and the Canadian Department of Communications DOC Changes or modifications not expressly approved by NI could void the user s authority to operate the equipment under the FCC Rules Class A Federal Communications Commission This equipment has been tested and found to comply with the limits for a Class A digital device pursuant to part 15 of the FCC Rules These limits are designed to provide reasonable protection against harmful interference when the equipment is ope
328. t the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions National Instruments Corporation A 101 M Series User Manual Timing Diagrams Analog Input Timing Diagrams The following sections describe the timing specifications and timing of the triggers and clock signals related to the analog input timing engine e Input Timing Input timing relates to any signal external to the M Series device that will be used as a clock or a trigger This timing describes the delays involved with importing the external signal into the device e Internal Timing Internal timing describes the relationship between internal signals In general how the input and other internal signals get used to generate output signals such as the convert signal e Output Timing Output timing refers to the timing parameters related to exporting signals internal to the device to a terminal for external use Signal Definitions Figure B 1 is a simplified model of the M Series analog input timing engine National Instruments Corporation B 1 M Series User Manual Appendix B Timing Diagrams POUT ai Terminal Y Selected Reference Trigger Reference Trigger Terminal e E 2 Sia POUT Terminal gt e lt gt ar gt e gt Terminal
329. tal and timing signals You can use one BNC accessory with the signals on either connector of your M Series device You can use two BNC accessories with one M Series device by using both connectors National Instruments Corporation A 67 M Series User Manual Appendix Device Specific Information Screw Terminal National Instruments offers several styles of screw terminal connector blocks Use an SHC68 68 EPM shielded cable to connect an M Series device to a connector block such as the following e CB 68LP and CB 68LPR unshielded connector blocks e SCB 68 shielded connector block with temperature sensor TBX 68 DIN rail mountable connector block e TB 2706 front panel mounted terminal block for PXI M Series devices You can use one screw terminal accessory with the signals on either connector of your M Series device You can use two screw terminal accessories with one M Series device by using both connectors RTSI Use RTSI bus cables to connect timing and synchronization signals among PCI PCI Express devices such as M Series E Series CAN and other measurement vision and motion devices Since PXI devices use PXI backplane signals for timing and synchronization no cables are required Cables In most applications you can use the following cables e SHC68 68 EPM A high performance cable designed specifically for M Series devices It has individual bundles separating analog and digital signals Each differenti
330. tation Signal vs Amplifier Source Input Multiplexers Al SENSE A T AI GND 4 1 0 Connector Measured Voltage Q Selected Channel in RSE Configuration Figure 4 9 RSE Connections for Floating Signal Sources Using the DAQ Assistant you can configure the channels for RSE or NRSE input modes Refer to the Configuring AI Ground Reference Settings in Software section for more information about the DAQ Assistant Connecting Ground Referenced Signal Sources What Are Ground Referenced Signal Sources A ground referenced signal source is a signal source connected to the building system ground It is already connected to a common ground point with respect to the device assuming that the computer is plugged into the M Series User Manual 4 20 ni com Chapter 4 Analog Input same power system as the source Non isolated outputs of instruments and devices that plug into the building power system fall into this category The difference in ground potential between two instruments connected to the same building power system is typically between and 100 mV but the difference can be much higher if power distribution circuits are improperly connected If a grounded signal source is incorrectly measured this difference can appear as measurement error Follow the connection instructions for grounded signal sources to eliminate this ground potential difference from the measured signal
331. ted to an absolute reference or system ground Also called floating signal sources Some common example of non referenced signal sources are batteries transformers or thermocouples Non Referenced Single Ended mode All measurements are made with respect to a common NRSE measurement system reference but the voltage at this reference can vary with respect to the measurement system ground The unwanted DC voltage due to amplifier offset voltages added to a signal Peripheral Component Interconnect A high performance expansion bus architecture originally developed by Intel to replace ISA and EISA It offers a theoretical maximum transfer rate of 132 MB s A high performance expansion bus architecture originally developed by Intel to replace PCI PCI Express offers a theoretical maximum transfer rate that is dependent upon lane width A x1 link theoretically provides 250 MB s in each direction to and from the device Once overhead is accounted for a x1 link can provide approximately 200 MB s of input capability and 200 MB s of output capability Increasing the number of lanes in a link increases maximum throughput by approximately the same factor See PCI Express National Instruments Corporation G 13 M Series User Manual Glossary period periods PFI PGIA physical channel Plug and Play devices posttriggering power source ppm pretriggering pulse pulse width PXI PXI Express M Series User Manua
332. tem for M Series plug in data acquisition devices An SCC system consists of a shielded carrier that holds up to 20 single or dual channel SCC modules for conditioning thermocouples and other transducers SCC is designed for small measurement systems where you need only a few channels of each signal type or for portable applications SCC systems also offer the most comprehensive and flexible signal connectivity options 2 4 ni com Chapter 2 DAQ System Overview System features include the following Modular architecture Select your measurement technology on a per channel basis Small channel systems Condition up to 16 analog input and eight digital I O lines Low profile portable Integrates well with other laptop computer measurement technologies High bandwidth Acquire signals at rates up to 1 25 MHz Connectivity Incorporates panelette technology to offer custom connectivity to thermocouple BNC LEMO B Series and MIL Spec connectors Sy Note PCI Express users should consider the power limits on certain SCC modules without an external power supply Refer to the specifications for your device and the Disk Drive Power Connector section of Chapter 3 Connector Information for information about power limits and increasing the current the device can supply on the 5 V terminal 3 Note SCC is not supported on the NI 6221 37 pin or USB 625x devices 5B Series 5B is a front end signal conditioning system for plug in
333. ter on the input signal For the 125 ns and 6 425 us filter settings the jitter is up to 25 ns On the 2 55 ms setting the jitter is up to 10 025 us When a PFI input is routed directly to RTSL or a RTSI input is routed directly to PFI the M Series device does not use the filtered version of the input signal Refer to the KnowledgeBase document Digital Filtering with M Series for more information about digital filters and counters To access this KnowledgeBase go to ni com info and enter the info code rddfms 9 10 ni com Bus Interface The bus interface circuitry of M Series devices efficiently moves data between host memory and the measurement and acquisition circuits M Series devices are available for the following platforms e PCI e PCI Express e PXI e USB All M Series devices are jumperless for complete plug and play operation The operating system automatically assigns the base address interrupt levels and other resources M Series PCI PCIe PXI devices incorporate PCI MITE technology to implement a high performance PCI interface M Series USB devices incorporate USB STC2 technology to implement a Hi Speed USB interface DMA Controllers and USB Signal Streams M Series PCI PCIe PXI devices have six fully independent DMA controllers for high performance transfers of data blocks One DMA controller is available for each measurement and acquisition block e Analog input e Analog output e Counter 0 e C
334. ternal periodic clock signal with a known period to the Source input of the counter The counter counts the number of rising or falling edges occurring on the Source input between the two active edges of the Gate signal You can calculate the period of the Gate input by multiplying the period of the Source signal by the number of edges returned by the counter 7 6 ni com Chapter 7 Counters Single Period Measurement With single period measurement the counter counts the number of rising or falling edges on the Source input occurring between two active edges of the Gate input On the second active edge of the Gate input the counter stores the count in a hardware save register and ignores other edges on the Gate and Source inputs Software then reads the stored count Figure 7 8 shows an example of a single period measurement GATE 7 LL source FTL LAL AL AL ELIS 1 2 3 4 5 Counter Value 0 HW Save Register 5 Figure 7 8 Single Period Measurement Buffered Period Measurement Buffered period measurement is similar to single period measurement but buffered period measurement measures multiple periods The counter counts the number of rising or falling edges on the Source input between each pair of active edges on the Gate input At the end of each period on the Gate signal the counter stores the count in a hardware save register A DMA controller transfers the stored val
335. the DACs You can specify an internal or external source for ao SampleClock You also can specify whether the DAC update begins on the rising edge or falling edge of ao SampleClock Using an Internal Source One of the following internal signals can drive ao SampleClock e AO Sample Clock Timebase divided down e Counter n Internal Output A programmable internal counter divides down the AO Sample Clock Timebase signal 5 10 ni com Chapter 5 Analog Output Using an External Source Use one of the following external signals as the source of ao SampleClock e PFI lt 0 15 gt RTSI lt 0 7 gt e PXI STAR e Analog Comparison Event an analog trigger Routing AO Sample Clock Signal to an Output Terminal You can route ao SampleClock as an active low signal out to any PFI lt 0 15 gt or RTSI lt 0 7 gt terminal Other Timing Requirements A counter on your device internally generates ao SampleClock unless you select some external source ao StartTrigger starts the counter and either the software or hardware can stop it once a finite generation completes When using an internally generated ao SampleClock you also can specify a configurable delay from ao StartTrigger to the first ao SampleClock pulse By default this delay is two ticks of ao SampleClockTimebase Figure 5 6 shows the relationship of ao SampleClock to ao StartTrigger ao SampleClockTimebase ao StartTrigger
336. the Sync Sample Clock Timebase is used to synchronize the input signals to the analog output timing engine before they are used by the Sample Clock Timebase The START Trigger determines when a timed analog output operation will start This signal can come from a software command or an external pulse Selected START is the output of the selection block for the START Trigger source The waveform generation can be paused using the pause trigger When enabled the waveform generation will occur as long as the gate is enabled The generation will be paused if the gate is disabled This signal can come from a software command or an external signal The Selected Pause is the output of the selection block for the Pause Trigger source ni com Appendix B Timing Diagrams Start_Trig RTSL or These terminals are the I O interface for the PFI device All external triggers are input on these terminals Internal signals can be exported to these terminals as well _i Signals All signals marked with _i are external signals that have been through the I O buffers and are ready for internal use Input Timing Input timing refers to the delays of importing signals from the external terminals so that the analog output timing engine can use them as sources for different triggers or clocks Figure B 23 and Table B 12 describe the insertion delays for external signals Terminal ty Hoty i i Figure B 23
337. the counter is armed to the beginning of the pulse The delay is measured in terms of a number of active edges of the Source input You can specify a pulse width The pulse width is also measured in terms of a number of active edges of the Source input You also can specify the active edge of the Source input rising or falling Figure 7 22 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source Counter Armed SOURCE L L LIL Es Figure 7 22 Single Pulse Generation Single Pulse Generation with Start Trigger The counter can output a single pulse in response to one pulse on a hardware Start Trigger signal The pulse appears on the Counter n Internal Output signal of the counter You can route the Start Trigger signal to the Gate input of the counter You can specify a delay from the Start Trigger to the beginning of the pulse You also can specify the pulse width The delay and pulse width are measured in terms of a number of active edges of the Source input After the Start Trigger signal pulses once the counter ignores the Gate input 7 20 ni com Chapter 7 Counters Figure 7 23 shows a generation of a pulse with a pulse delay of four and a pulse width of three using the rising edge of Source GATE i Start Trigger SOURCE __ OUT Figure 7
338. the output is independent of the pulse width of the input The pulse width is specified in a number of periods of the 80 MHz Timebase Table B 25 DO Timing Requirements Timing Requirement Condition Min ns Max ns tio PFI RTSI or When used as DO NI 622x devices PXI_STAR Sample Clock 1000 0 Minimum Period NI 625x NI 628x devices 100 0 ty PFI RTSI or When used as DO 12 0 PXI_STAR Sample Clock Minimum Pulse Width M Series User Manual B 36 ni com Counters Timing Diagrams Appendix B Timing Diagrams Input Delays This section describes input delays input requirements output delays gating modes and quadrature and two pulse encoder timing This section describes some of the timing delays of the counter timer circuit To describe delays of the counter timer we model the circuitry as shown in Figure B 40 In the figure PFI RTSL and PXI_STAR represent signals at connectors pins of the M Series device The other named signals represent internal signals PFI RTSI gt e or PXI_STAR Other Internal Signals 80 MHz Timebase 20 MHz Timebase 100 kHz Timebase PXICLK10 PFI_i RTSL_i or PXI_STAR_i PFI RTSI Selected_Gate Gate Logic Count_Enable Selected_Source pL 32 Bit Counter Out_o PFI RTSI gt or PXI_STAR or PXI_STAR Counter n Gate Counter n Internal Output PFI RTSI or
339. the single ended modes more electrostatic and magnetic noise couples into the signal connections than in DIFF configurations The coupling is the result of differences in the signal path Magnetic coupling is proportional to the area between the two signal conductors Electrical coupling is a function of how much the electric field differs between the two conductors With this type of connection the NI PGIA rejects both the common mode noise in the signal and the ground potential difference between the signal source and the device ground Refer to the Using Non Referenced Single Ended NRSE Connections for Ground Referenced Signal Sources section for more information about NRSE connections When to Use Referenced Single Ended RSE Connections with Ground Referenced Signal Sources M Series User Manual Do not use RSE connections with ground referenced signal sources Use NRSE or DIFF connections instead As shown in the bottom rightmost cell of Table 4 6 there can be a potential difference between AI GND and the ground of the sensor In RSE mode this ground loop causes measurement errors 4 22 ni com Chapter 4 Analog Input Using Differential Connections for Ground Referenced Signal Sources Figure 4 10 shows how to connect a ground referenced signal source to the M Series device configured in DIFF mode Ground Referenced Signal Source Common Mode Noise and Ground Potential Q Co 477
340. these signals before presenting them to the internal counter M Series devices use one of three synchronization methods 80 MHz source mode Other internal source mode External source mode In DAQmx the device uses 80 MHz source mode if you perform the following e Perform a position measurement e Select duplicate count prevention Otherwise the mode depends on the signal that drives Counter n Source Table 7 7 describes the conditions for each mode Table 7 7 Synchronization Mode Conditions Duplicate Count Type of Signal Driving Synchronization Prevention Enabled Measurement Counter n Source Mode Yes Any Any 80 MHz Source No Position Measurement Any 80 MHz Source No Any 80 MHz Timebase 80 MHz Source No All Except Position 20 MHz Timebase Other Internal Source Measurement 100 kHz Timebase or PXI_CLK10 No All Except Position Any Other Signal External Source Measurement such as PFI or RTSI M Series User Manual 7 38 ni com Chapter 7 Counters 80 MHz Source Mode In 80 MHz source mode the device synchronizes signals on the rising edge of the source and counts on the following rising edge of the source as shown in Figure 7 34 Source A A Synchronize Count Figure 7 34 80 MHz Source Mode Other Internal Source Mode In other internal source mode the device synchronizes signals on the falling edge of the source and counts
341. timing B 14 M Series User Manual 1 12 referenced single ended connections using with floating signal sources 4 20 when to use with floating signal sources 4 16 when to use with ground referenced signal sources 4 22 related documentation xviii retriggerable single pulse generation 7 21 routing analog comparison event to an output terminal 11 3 clock 9 1 digital 9 1 RSE configuration 4 20 RSE connections using with floating signal sources 4 20 when to use with floating signal sources 4 16 when to use with ground referenced signal sources 4 22 RTSI 9 4 connector pinout 3 8 9 4 filters 9 6 using as outputs 9 5 using terminals as timing input signals 9 6 S sample clock analog input internal timing B 16 edge counting 7 3 scanning speed 4 10 SCC 2 4 SCXI 2 4 semi period measurement 7 8 buffered 7 9 single 7 8 sensors 2 3 settings analog input ground reference 4 5 ni com AO offset 5 2 AO reference selection 5 2 short high quality cabling 4 9 signal conditioning 2 3 options 2 4 signal descriptions 3 1 signal routing RTSI bus 9 4 signal sources floating 4 15 ground referenced 4 20 Signal Stream USB 10 1 signals AI Convert Clock 4 31 AI Convert Clock Timebase 4 35 AI Hold Complete Event 4 35 AI Pause Trigger 4 38 AI Reference Trigger 4 36 AI Sample Clock 4 28 AI Sample Clock Timebase 4 30 AI Start Trigger 4 35 analog input 4 25 analog output 5 7 AO Pause T
342. timing for the internal Count Enable signal as shown in Figure B 40 Count Enable enables the 32 bit counter to count on the rising edge of the Selected Source signal The delays depend on both the synchronization mode and gating mode for the application Selected_Gate y y lt gt gt Count_Enable Figure B 44 Count Enable Delays Table B 29 Selected Gate to Count Enable Delays Synchronization Timing Mode Gating Mode Min ns Max ns ty 80 MHz Source Edge 0 5 5 0 Level 1 0 0 5 Other Internal Edge 1 2 Source Period 1 ns 1 2 Source Period 3 ns Source Level 1 2 Source Period 2 5 ns 1 2 Source Period 1 ns External Source Edge 7 5 22 0 Level 6 0 18 0 M Series User Manual B 40 ni com Appendix B Timing Diagrams Input Requirements Refer to the Figure B 40 for the M Series counter timer circuitry Source Period and Pulse Width Figure B 45 and Table B 30 show the timing requirements for Counter n Source The requirements depend on the synchronization mode e Counter n Source te Figure B 45 Counter n Source Timing Requirements Table B 30 Counter n Source Timing Synchronization Timing Description Mode Min ns Max ns ts Counter n Source 80 MHz Source 12 5 Period Other Internal Source 25 0 External Source 50 0 te Counter n Source 80 MHz Source 6 2 Pulse Width Other Internal Source 12 5 External Source 16 0
343. tions document for your device on ni com manuals Before installing your DAQ device you must install the software you plan to use with the device Installing NI DAQmx The DAQ Getting Started Guide which you can download at ni com manuals offers NI DAQmx users step by step instructions for installing software and hardware configuring channels and tasks and getting started developing an application Installing Other Software If you are using other software refer to the installation instructions that accompany your software Installing the Hardware The DAQ Getting Started Guide contains non software specific information about how to install PCI PCI Express PXI and USB devices as well as accessories and cables Device Pinouts Refer to Appendix A Device Specific Information for M Series device pinouts National Instruments Corporation 1 1 M Series User Manual Chapter 1 Getting Started Device Specifications Refer to the specifications for your device available on the NI DAQ Device Document Browser or ni com manuals for more detailed information about M Series devices Device Accessories and Cables NI offers a variety of accessories and cables to use with your DAQ device Refer to Appendix A Device Specific Information or ni com for more information M Series User Manual 1 2 ni com DAQ System Overview Figure 2 1 shows a typical DAQ system which includes sensors transducers
344. to 200 mV When the multiplexer switches from channel 0 to channel 1 the input to the NI PGIA switches from 4 V to 1 mV The approximately 4 V step from 4 V to 1 mV is 1 000 of the new full scale range For a 16 bit device to settle within 0 0015 15 ppm or 1 LSB of the 200 mV full scale range on channel 1 the input circuitry must settle to within 0 00003 1 0 31 ppm or 1 50 LSB of the 10 V range Some devices can take many microseconds for the circuitry to settle this much To avoid this effect you should arrange your channel scanning order so that transitions from large to small input ranges are infrequent In general you do not need this extra settling time when the NI PGIA is switching from a small input range to a larger input range National Instruments Corporation 4 9 M Series User Manual Chapter 4 Analog Input Insert Grounded Channel between Signal Channels Another technique to improve settling time is to connect an input channel to ground Then insert this channel in the scan list between two of your signal channels The input range of the grounded channel should match the input range of the signal after the grounded channel in the scan list Consider again the example above where a 4 V signal is connected to channel 0 and a mV signal is connected to channel 1 Suppose the input range for channel 0 is 10 V to 10 V and the input range of channel is 200 mV to 200 mV You can connect channel 2 to AI GND o
345. u are using any signal other than the onboard clock as the source of your sample clock the generation resumes as soon as the pause trigger is deasserted and another edge of the sample clock is received as shown in Figure 5 5 Pause Trigger Sample Clock Figure 5 5 ao PauseTrigger with Other Signal Source National Instruments Corporation 5 9 M Series User Manual Chapter 5 Analog Output Using a Digital Source To use ao PauseTrigger specify a source and a polarity The source can be one of the following signals e PFI lt 0 15 gt RTSI lt 0 7 gt e PXISTAR The source also can be one of several other internal signals on your DAQ device Refer to Device Routing in MAX in the NI DAQmx Help or the LabVIEW 8 x Help for more information You also can specify whether the samples are paused when ao PauseTrigger is at a logic high or low level Using an Analog Source When you use an analog trigger source the samples are paused when the Analog Comparison Event signal is at a high level Refer to the Triggering with an Analog Source section of Chapter 11 Triggering for more information Routing AO Pause Trigger Signal to an Output Terminal You can route ao PauseTrigger out to RTSI lt 0 7 gt AO Sample Clock Signal M Series User Manual Use the AO Sample Clock ao SampleClock signal to initiate AO samples Each sample updates the outputs of all of
346. ues to host memory The counter begins when it is armed The arm usually occurs in the middle of a period of the Gate input So the first value stored in the hardware save register does not reflect a full period of the Gate input In most applications this first point should be discarded Figure 7 9 shows an example of a buffered period measurement National Instruments Corporation 7 7 M Series User Manual Chapter 7 Counters SOURCE Counter Value Buffer GATE Counter Armed CLA LALA LEAL LEAL 1 a 1 2 3 l 1 2 3 1 O 2 2 Discard 3 2 Discard 3 2 Discard 3 Figure 7 9 Buffered Period Measurement Note that 1f you are using an external signal as the Source at least one Source pulse should occur between each active edge of the Gate signal This condition ensures that correct values are returned by the counter If this condition is not met consider using duplicate count prevention described in the Duplicate Count Prevention section For information about connecting counter signals refer to the Default Counter Timer Pinouts section Semi Period Measurement M Series User Manual In semi period measurements the counter measures a semi period on its Gate input signal after the counter is armed A semi period is the time between any two consecutive edges on the Gate input You can route an intern
347. urce pulse should occur between each active edge of the Gate signal This condition ensures that correct values are returned by the counter If this condition is not met consider using duplicate count prevention described in the Duplicate Count Prevention section For information about connecting counter signals refer to the Default Counter Timer Pinouts section Frequency Measurement You can use the counters to measure frequency in several different ways You can choose one of the following methods depending on your application National Instruments Corporation 7 9 M Series User Manual Chapter 7 Counters Method 1 Measure Low Frequency with One Counter In this method you measure one period of your signal using a known timebase This method is good for low frequency signals You can route the signal to measure F1 to the Gate of a counter You can route a known timebase Ft to the Source of the counter The known timebase can be 80MHzTimebase For signals that might be slower than 0 02 Hz use a slower known timebase You can configure the counter to measure one period of the gate signal The frequency of F1 is the inverse of the period Figure 7 11 illustrates this method F1 Gate 1 2 3 ne Ur N Ft Source Ft 4 A Single Period Period of F1 N Measurement Ft E a Interval Measured Frequency of F1 gt M Series User Manual
348. ut Terminal You can route Counter n Z out to RTSI lt 0 7 gt 7 28 ni com Chapter 7 Counters Counter n Up_Down Signal Counter n Up_Down is another name for the Counter n B signal Counter n HW Arm Signal The Counter n HW Arm signal enables a counter to begin an input or output function To begin any counter input or output function you must first enable or arm the counter In some applications such as buffered semi period measurement the counter begins counting when it is armed In other applications such as single pulse width measurement the counter begins waiting for the Gate signal when itis armed Counter output operations can use the arm signal in addition to a start trigger Software can arm counters or configure counters to be armed on the assertion of the Counter n HW Arm signal Routing Signals to Counter 7 HW Arm Input Any of the following signals can be routed to the Counter n HW Arm input RTSI lt 0 7 gt e PFI lt 0 15 gt e ai ReferenceTrigger e al StartTrigger e PXI STAR e Analog Comparison Event Counter 1 Internal Output can be routed to Counter 0 HW Arm Counter 0 Internal Output can be routed to Counter 1 HW Arm Some of these options may not be available in some driver software Counter n Internal Output and Counter n TC Signals Counter n TC is an internal signal that asserts when the counter value is 0 The Counter n Internal Output signal changes in response to Counter n TC Th
349. ution Assuming Input Range 5 Over Range 1Vto1V 32 uV 500 mV to 500 mV 16 uV 200 mV to 200 mV 6 4 uV 100 mV to 100 mV 3 2 uV Table 4 3 Input Ranges for NI 628x Nominal Resolution Assuming Input Range 5 Over Range 10 V to 10 V 80 1 uV 5 V to5 V 40 1 uV 2 V to2 V 16 0 uV 1Vto1V 8 01 uV 500 mV to 500 mV 4 01 uV 200 mV to 200 mV 1 60 uV 100 mV to 100 mV 0 80 uV Analog Input Lowpass Filter M Series User Manual A lowpass filter attenuates signals with frequencies above the cutoff frequency while passing with minimal attenuation signals below the cutoff frequency The cutoff frequency is defined as the frequency at which the output amplitude has decreased by 3 dB Lowpass filters attenuate noise and reduce aliasing of signals beyond the Nyquist frequency For example if the signal of interest does not have frequency components beyond 40 kHz then using a filter with a cutoff frequency at 40 kHz will attenuate noise beyond the cutoff that is not of interest The cutoff frequency of the lowpass filter is also called the small signal bandwidth The specifications document for your DAQ device lists the small signal bandwidth On some devices the filter cutoff is fixed On other devices this filter is programmable and can be enabled for a lower frequency For example the 4 4 ni com Chapter 4 Analog Input NI 628x devices have a programmable filter with a
350. value can be between 0 and 255 For instance if you specify the increment to be 10 the delay between the active Gate edge and the pulse on the output will increase by 10 every time a new pulse is generated Suppose you program your counter to generate pulses with a delay of 100 and pulse width of 200 each time it receives a trigger Furthermore suppose you specify the delay increment to be 10 On the first trigger your pulse delay will be 100 on the second it will be 110 on the third it will be 120 the process will repeat in this manner until the counter is disarmed The counter ignores any Gate edge that is received while the pulse triggered by the previous Gate edge is in progress The waveform thus produced at the counter s output can be used to provide timing for undersampling applications where a digitizing system can sample repetitive waveforms that are higher in frequency than the Nyquist 7 24 ni com Chapter 7 Counters frequency of the system Figure 7 28 shows an example of pulse generation for ETS the delay from the trigger to the pulse increases after each subsequent Gate active edge GATE l l l n D1 D2 D1 AD D3 D1 2AD OUT Figure 7 28 Pulse Generation for ETS For information about connecting counter signals refer to the Default Counter Timer Pinouts section Counter Timing Signals M Series devices feature the following counter timing signa
351. vices use the NI PGIA to deliver high accuracy even when sampling multiple channels with small input ranges at fast rates M Series devices can sample channels in any order at the maximum conversion rate and you can individually program each channel in a sample with a different input range A D Converter The analog to digital converter ADC digitizes the AI signal by converting the analog voltage into a digital number Al FIFO M Series devices can perform both single and multiple A D conversions of a fixed or infinite number of samples A large first in first out FIFO buffer holds data during AI acquisitions to ensure that no data is lost M Series devices can handle multiple A D conversion operations with DMA interrupts or programmed I O Analog Input Range M Series User Manual Input range refers to the set of input voltages that an analog input channel can digitize with the specified accuracy The NI PGIA amplifies or attenuates the AI signal depending on the input range You can individually program the input range of each AI channel on your M Series device The input range affects the resolution of the M Series device for an AI channel Resolution refers to the voltage of one ADC code For example a 16 bit ADC converts analog inputs into one of 65 536 216 codes that is one of 65 536 possible digital values These values are spread fairly 4 2 ni com Chapter 4 Analog Input evenly across the input range So f
352. xibility through customized panelettes Visit ni com for more information about the CA 1000 Refer to the Custom Cabling section of Chapter 2 DAQ System Overview for more information about custom cabling solutions USB 6259 Mass Termination LED Patterns The USB 6259 Mass Termination device has two LEDs labeled ACTIVE and READY The ACTIVE LED indicates activity over the bus The READY LED indicates whether or not the device is configured Table A 19 shows the behavior of the LEDs Table A 19 USB 6259 Mass Termination LED Patterns ACTIVE LED READY LED USB 6251 State Off Off The device is either not connected to the host computer or not powered Off On The device is configured but there is no activity over the bus On On The device is configured and there is activity over the bus Blinking On M Series User Manual A 78 ni com Appendix Device Specific Information USB 6259 Mass Termination Fuse Replacement USB 6259 Mass Termination devices have a replaceable 2A 250V 5 x 20 mm fuse To remove the fuse from the USB 6259 Mass Termination device complete the following steps 1 Loosen the four flathead Phillips screws that attach the lid to the enclosure and remove the lid 2 Replace the fuse while referring to Figure A 19 for the fuse location Bol Fuse e se Ag IN Cee
353. y different internal AI AO DI or DO timing signals to each PFI terminal You also can route the counter timer outputs to each PFI terminal As a Port 1 or Port 2 Digital I O signal you can individually configure each signal as an input or output NC No connect Do not connect signals to these terminals NI 6255 devices only For NI 6255 devices in NRSE mode the reference for each AI lt 64 79 gt signal is AI SENSE by default For more information about routing NI 6225 signals in NRSE mode refer to the KnowledgeBase document NI 6225 Using Channels 64 Through 79 in NRSE Mode by going to ni com info and entering the info code 6225NRSE National Instruments Corporation 3 3 M Series User Manual Chapter 3 Connector Information M Series and E Series Pinout Comparison The pinout of Connector 0 of 68 pin M Series devices is similar to the pinout of 68 pin E Series devices On M Series devices some terminals have enhanced functionality or other slight differences Table 3 2 compares the two pinouts Table 3 2 M Series and E Series Device Pinout Comparison M Series Terminal E Series Terminal Terminal Differences 1 FREQ OUT PFI 14 P2 6 E Series devices drive each of these terminals with one particular internal timing signal 2 CTR 0 OUT PFI 12 P2 4 GPCTRO_OUT M Series devices can drive each terminal with the same signal as on E Seri
354. ys properly ground yourself and the equipment when handling the DAQ device or connecting to it Programmable Power Up States At system startup and reset the hardware sets all PFI and DIO lines to high impedance inputs by default The DAQ device does not drive the signal high or low Each line has a weak pull down resistor connected to it as described in the specifications document for your device NI DAQmx 7 4 and later supports programmable power up states for PFI and DIO lines Software can program any value at power up to the PO P1 or P2 lines The PFI and DIO lines can be set as e A high impedance input with a weak pull down resistor default e An output driving a 0 e An output driving a 1 Refer to the NI DAQmx Help or the LabVIEW 8 x Help for more information about setting power up states in NI DAQmx or MAX iy Note When using your M Series device to control an SCXI chassis DIO lines 0 1 2 and 4 are used as communication lines and must be left to power up in the default high impedance state to avoid potential damage to these signals National Instruments Corporation 6 7 M Series User Manual Chapter 6 Digital I O DI Change Detection You can configure the DAQ device to detect changes in the DIO signals Figure 6 3 shows a block diagram of the DIO change detection circuitry Enable P0 0 Synch las Change Detection Event

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