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Microwind & Dsch User's Manual Version 2

1. Save in CAD sch 2 0 X cores Pree Fig 6 4 Create a symbol from the schematic diagram In order to build hierarchical designs using the adder we detail the procedure to generate the symbol of the full adder from its schematic diagram In DSCH2 click the above icon the screen of figure 6 4 appears Simply click OK The symbol of the full adder is created with the name Fadd sym in the current directory Use the command Insert gt Symbol to include this symbol into a new circuit 47 18 05 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics 6 4 Full Adder Layout MRNA i L NE CN ga E S EZ GG TOR ARE A T db s Gc um m T E 134 7 Z7 Hg IN x E Th E r ay Ze E jam A CE APERTE E Figi MM RUIN 6 beet l l E M HTC M HAN 4 1b lr A Be spk Hinh gla Ell i A Ce a fee c rn Sere HE E E ES E us H pi m UE WZ TEE ea HERS AENA EA aed ENG jou v a ee elt mE He JIPE RT Lr Mu LL Eae A T LT Hu Ven eum RT ET mas feel Hi Hu mo d la Es HU RS Heh ME LIE m 19 E BE x 777777 ERENT IZ il E Fig 6 5 The full custom implementation of the full adder and its simulation FullADD MSK You may create the layout of the full adder by hand in order to create a compact design Notice that the AND OR combination of cells may be replaced by a complex gate An example of full custom layout of the full adder i
2. National Institute of Applied Sciences Toulouse FRANCE Department of Electrical amp Computer Engineering o INSA TOULOUSE Microwind amp Dsch User s Manual Version 2 Microwind 2 C microwind2 Book on CHOSXEeprom x4 MSK 3 Nmos Width 4 000 Lenath 0 200 ym 40x2 lambda E File View Edi ii Compile Analysis Help E Palette ids va its va odas va Threshold votage Capacitance ets Levelt Leve ESME wn We4 000um L 0 doou simul ane rss 4 LL 4x0 2um 0 18um kr oo a 2500 0 pio 2000 0 pyri oss pen 559 af NFACT 1 690 Pscaer 320 000 vo feos a ua eo lt UC oo a s ER a 2250 0 1750 0 1500 0 1250 0 1000 0 750 Pel nt In zan Tempe 27 00 E i Va 250 04 p 0 0 0 00 0 50 EN Dsch2 C Dsch2 Book on CMOS Clock24H_sch Ez Doe di Mis Bile Edt Inset View Simulate Help PEO Fa fs oo A 4 hie WAAL SD Diy_60es F s HH Enable clk1 MEE Div 24es a Lm Re ud Raz Enable ud Simulation Control elk1 ut E z ua Sugd23 Lin mem 1 vo amp aj AD ALY m terns r oieotiesinios M nose mos az May 2002 Etienne Sicard http intrage insa tlse fr etienne 1 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction About the author ETIENNE SICARD was born in Paris France in June 1961 He received a B S degree in 1984 and a PhD in Electr
3. la nh Generate Device X cancel Fig 3 10 Analog simulation of the MOS device The MOS Model 1 For the evaluation of the current Ids between the drain and the source as a function of Vd Vg and Vs you may use the old but nevertheless simple MODEL 1 described below Mone CUT OFF W Vds2 LINEAR Vds lt V gs Ids KP Vgs Vt Vds gt Vt SATURAT Vds gt Vgs Ids KP 2 T Ves Wt 2 ED Vt With vt ZVTO GAMMA PHI vb PHI MOS MODEL 1 PARAMETERS PARAMETE DEFINITION TYPICAL VALUE 0 25um R NMOS pMOS Theshold voltage Transconductance coefficient 30014 A V 120uA V HI L P Surface potential at strong 0 3V 0 3V inversion Bulk threshold parameter MOS channel width 0 5 20um 0 5 40um L MOS channel length 0 25um 0 25um 18 05 02 3 10 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Let us compare the simulation and the measurement for a 10x10um device O Click Simulate gt Mos characteristics Or the icon O Click Add Measure Select the data file Nb10x0 25 MES The N means an n channel MOS device The b corresponds to a chip called BETA fabricated in 0 25um technology The values 10x0 25 means W 10um L 0 25um O Select Level 1 in the parameter list to compare LEVEL1 simulated characteristics with the measurements ASMA 11 0 0004m L 0 250um simul Model 1 predicts 25mA maximum 25 2 008 100 25 um Beta 20 1
4. module Hadd B A sum carry LIU BA OULPUC SUM Carry xor xorlqsumpb 2 and andl carry AB endmodule Click on Compile When the compiling is complete the resulting layout appears shown below The XOR gate is routed on the left and the AND gate is routed on the right Now click on Simulate gt Start Simulation The timing diagrams of figure 6 2 appear and you should verify the truth table of the half adder Click on Close to return to the editor Fig 6 2 Compiling and simulation of the half adder gate Hadd MSK Full Adder Gate The truth table and schematic diagram for the full adder are shown in Figure 6 3 The SUM is made with two XOR gates and the CARRY is a combination of NAND gates as shown below The most straightforward implementation of the CARRY cell is AB BC AC The weakness of such a circuit is the use of positive logic gates leading to multiple stages A more efficient circuit consists in the same function but with inverting gates 46 18 05 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics FULL ADDER B SUM CARRY 0 A 0 0 0 0 l l l l O DOD m e m O O Oo Or Onm OW 0 1 0 l 0 0 l l 0 0 l 0 l 1 l Fig 6 3 The truth table and schematic diagram of a full adder FADD SCH 6 3 Full Adder Symbol in DSCH t Schema to Symbol x Symbol preview gt Symbol Properties Name fadd sym ncreasing orde f Decreasing order Tile fadd
5. nmm Fig 7 16 An array of 4x4 dynamic cells Dram4x4 SCH Dynamic RAM Embedded dynamic RAM Parasitic junction capacitance Specific embedded capacitance usedtostem org gt usedto store 1 or 0 Fig 7 19 The dynamic ram cell may be a single MOS device with enlarged source region or an embedded capacitance In figure 7 19 two layout implementation are proposed In the left part the source area of the MOS is significantly enlarged to increase artificially the parasitic junction capacitance A typical target capacitance value C for large DRAM arrays is 3fF In this layout C is 0 2fF In the layout of figure 7 19 right a specific option layer is added with a property of embedded capacitance with a very high value 67 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories Fig 7 20 Compared to the regular MOS left the embedded DRAM uses poly2 and a second specific layer violet to create an efficient capacitor Thanks to a specific option layer available in embedded RAM process Ceen is increased to 3fF while reducing the cell area Figure 7 21 right Three 8x8 DRAM arrays have been created by duplicating Command Edit Duplicate XY in Microwind the basic DRAM cell See the impact of embedded capacitor on the reduction of silicon area Also notice that joining two cells at the common contact saves silicon area The fixed voltage of the embedded capacitor is driven by the 2 layer of polysi
6. A A A A AAA A A E 5 metal layer technology zi em i eum E me scillate2 Fig 2 6 A three inverter ring oscillator routed with 2 metal layers and 5 metal layers technologies As can be noticed the number of metal layers used for interconnects has been continuously increasing in the course of the past ten years More layers for routing means a more efficient use of the silicon surface as for printed circuit boards Active areas 1 6 MOS devices can be placed closer from each other if many routing layers are provided Figure 2 6 HOW TO SIMULATE D Start Microwind2 By default the software is configured with 0 25um technology Click File gt Open Select INV3 Click Simulate Process section in 2D Draw a line representing the location for 2D process view The 2D view appears Click OK Click Simulate gt Start Simulation Observe the oscillator frequency Click File Select Foundry Select ams08 rul 0 8um technology Ask again for the 2D view Observe the change in the process aspect 2 Ask again for analog simulation Observe the change in frequency and voltage supply 10 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 3 The MOS device 3 1 This chapter presents the CMOS transistor its layout static characteristics and dynamic characteristics The vertical aspect of the device and the three dimensional sketch of the fabrication are also describ
7. Flat bandvoltage 09 09 KI b4k1 First order body bias coefficient 045 VI2_ 045VI2 K2 b4k2 Second order body bias coefficient 0 1 Joi b4d0vt First coefficient of short channel effect on 22 2 2 threshold voltage 5adlwt Second coefficient of short channel effect 0 53 0 53 on Vth 1 Drain induced barrier lowering coefficient NFACTOR B4nf Sub threshold turn on swing factor 1 und dl Controls the exponential increase of current ME with Vgs degradation due to vertical field body bias effect V V WINT Channel width offset parameter 0 01 6um 0 01 6um Channel length offset parameter 0 01 6um 0 01 6um mobility reduction effect mobility reduction voltage mobility UO Offset voltage in subthreshold region 0 08V 0 08V Parameter for channel length modulation Junction depth For MOS2 MOS3 and MOS4 only the threshold voltage mobility ant oxides thickness are user accessible All other parameters are identical to MOSI 104 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 12 TEC file for DSCH2 The logic simulator includes a current evaluator To run this evaluation the following parameters are proposed in a TEC file example cmos012 TEC DSCH 2 0 technology file NAME CMOS 0 12um VERSION 14 12 2001 Time unit for simulation TEMEUNTET 0 Supply voltage VDD le eZ Typical gate delay in ns TDelay 0 02 Typical wire delay in ns TWireD
8. The CMOS inverter design is detailed in the figure below Here the p channel MOS and the n channel MOS transistors function as switches When the input signal is logic O Fig 4 2 left the nMOS is switched off while PMOS passes VDD through the output When the input signal is logic 1 Fig 4 3 right the pMOS is switched off while the nMOS passes VSS to the output ind Source WES Fig 4 3 The MOS Inverter File Cmoslnv sch The inverter consumes power during transitions due to two separate effects The first is short circuit power arising from momentary short circuit current that flow from VDD to VSS when the transistor functions in the incomplete on off state This state occurs briefly during transitions of the output either from 0 to 1 or from 1 to O Fig 4 4 int i aut1 Y 1 anout Load Capa l Charge Discharge Fig 4 4 Short circuit current in CMOS inverters The second is the charging discharging power which depends on the output wire capacitance With small loading the short circuit current is dominant But as the number of gates connected to the inverter increase the load capacity increases Consequently the charging and discharging current starts to dominate the short circuit current 31 18 05 02 4 3 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fanout effect The fanout corresponds to the number of gates connected to the inverter output Physically a large fanout means a large number o
9. 3 3V 1 2V I Os at high voltage Core logic operating at low voltage Fig 3 16 Interfacing low voltage logic signals with high voltage I Os requires specific circuits operating in high voltage mode For I Os operating at high voltage specific MOS devices called High voltage MOS are used We cannot use high speed or low leakage devices as their oxide is too small A 2 5V voltage would damage the gate oxide of a high speed MOS in 0 12um technology The high voltage MOS is built using a thick oxide two to three times thicker than the low voltage MOS to handle high voltages as required by the I O interfaces 24 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 5 lambda 0 300pm j 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 3 0 high speed MOS 12V in 0 12um lowleakage MOS 12V inO 12um high voltage MOS Up to 3 34 thin gate oxide 3nm thin gate oxide 3nm thick gate oxide Fnm Fig 3 17 High speed low leakage and high voltage MOS The high voltage MOS has a minimum length longer than for the other MOS The gate oxide is also thicker to handle high voltage operation 3 14 Temperature effects on the MOS The MOS device 1s sensitive to temperature Two main parameters are concerned the threshold voltage VTO and the transconductance coefficient KP that decrease with temperature increase The physical background is the degradation of mobility of
10. Operating and Modeling of the MOS transistor McGraw Hill 1987 ISBN 0 07 065381 X 5 S M Sze Physics of Semiconductor devices John Wiley 1981 ISBN 0 471 05661 8 6 Y Cheng C Hu MOSFET Modeling amp BSIMG user s guide Kluwer Academic Publishers 1999 7 A Hastings The Art of Analog Layout Prentice Hall 2001 ISBN 0 13 087061 7 8 N Weste K Eshraghian Principles of CMOS VLSI design Addison Wesley ISBN 0 201 53376 6 1993 9 K Lee M Shur T A Fjeldly T Ytterdal Semiconductor Device Modeling for VLIS Prentice Hall 1993 ISBN 0 13 805656 0 10 W Liu Mosfet Models for SPICE simulation including Bsim3v3 and BSIM4 Wiley amp Sons 2001 ISBN 0 471 39697 4 11 C Motchenbacher J A Connely Low Noise Electronic System Design Wiley amp sons 1993 ISBN 0 471 57742 1 12 A K Sharma Semiconductor Memories IEEE Press 1996 ISBN 0 7803 1000 4 110 18 05 02
11. b4ua le 15 b4uc 0 047e 15 b4vsat 60e3 b4 pscbel 230e6 b4ute 1 8 b4kt1 0 1 b4lint 0 01e 6 b4wint 0 02e 6 b4xj 1 5e 7 b4ndep 1 7e17 b4pclm 0 7 NEGAR Speed b4v2to 0 3 b4t2ox 3e 9 lt hrgh voltage b4v3to 0 7 b4t3ox 7e 9 CIF Layers MicroWind layer CIF layer overetch cif nwell 1 0 0 cif diffp 17 0 5 CIE diff dos 945 cif aarea 2 0 5 cift p ly 253 NEU Gar contact 19 07025 cif metal 23 0 0125 cif via 25 0 0125 cif metal2 27 0 0125 cif via2 32 0 0125 cif metal3 34 0 0125 cif via3 35 0 0125 cif metal4 36 0 0125 cif via4 52 0 0125 cif metal5 53 0 0 Gif viaj 54 0s 0 cif metal6 55 O cif passiv 31 0 0 0 cif text 56 0 MicroWind simulation parameters 18 05 02 DSCH amp MICROWIND USER S MANUAL deltaT 0 30e 12 Minimum simulation interval dT vdd 1 2 hvdd 3 3 temperature 27 riseTime 0 05 End CMOS 0 12um 109 13 Design Rules File for 0 12um 18 05 02 DSCH amp MICROWIND USER S MANUAL 13 References 14 References 1 R J Bakcer H W Li D E Boyce CMOS design layout and simulation IEEE Press 1998 www ieee org 2 M John S Smidth Application Specific Integrated Circuits Addison Wesley 1997 ISBN 0 201 50022 1 www awl com cseng 3 B Razavi Design of Analog CMOS integrated circuits McGraw Hill ISBN 0 07 238032 2 2001 www mhhe com 4 Y P Tsividis
12. equation or modify the items proposed in the list of examples In the one line equation the first parameter is the output name In the present case that name is s The sign is obligatory The sign corresponds to the operation NOT and can be used only right after the sign The parenthesis are used to build the function where amp is the AND operator l is the OR operator and is the XOR operator a ill Fig 5 12 A compiled complex gate dnd its es se eee ComplexABCD MSK Multiplexor Multiplexing means transmitting a large amount of information through a smaller number of connections A digital multiplexer is a circuit that selects binary information from one of many input logic signals and directs it to a single input line The main component of the multiplexer is a basic cell called the transmission gate The transmission gate let a signal flow if Enable is asserted Remember that the n channel MOS is only good for low signals and the p channel MOS is only good for high signals To pass logic signals well both a n channel device and a p channel device must be used as shown in figure 5 13 The main drawback is the need for two control signals Enable and Enable thus an inverter 1s required Enable signalln signalOut signalln Signalcut Fig 5 13 The transmission gate used as a multiplexor 43 18 05 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates In DSCH2 a transmission gate sy
13. sA e OS AAA A A dae ure about O A 14 2 91 static Mos marce nO Sereno aaa eo e da tats M SMS ine E 14 DO My Mami MOS DEA Os i n 15 327 ANIOS SMA A A A A A A ected 16 Dad Layout COASTISTAONS A A dias 17 29 Ee MOS Model laa id T 18 310 The MOS iles ES TP 19 SX Whe EB SIMA MOS MOdeLl 2 itt ida 21 Sol MOM akire NIC rm 23 A PAT ONY Ole MOS A set ac TELE IE ac bite ae 24 314 Temperature eects On the MOS ui oi 25 o TCPhePNIOS TPEInstslOE aout ca etd alates be ot ac ma delectu ded oe D d 26 316 The Eransaissi n Gauss TEE 28 LS E RR 30 dl TAS TOG IG AVE acid 30 42 THE EMOS UN VERTER oi SE A A aa 31 43 Janotebleob custode t nte col Catala 32 dd MANUALE LAYOUT OFTHE INVERTER suas arado II NO 33 45 Analog smi lation or the IN VER TER iia ran ci loess 34 20 2 Dt View OP ANC PL NI O cede a Set dues S Et 35 AT SID View OPThoeDEOSeSS ou isa a 35 To OSLATEINVERLDER 5 euet hu debo A da 36 S ABASTO GATEN AS A 37 SEM a TAN Eo TO Gae APO UNES 37 I2 NA A A a ae iaten sens 39 Du de AAA AA aaa a dclantacmndams ate edo bita Led uan aa aaa 39 AAA UU TUTUP NER EN 40 SEXE EA DT t m m m t er 42 E ANB IIIS CS ea TIU TT m T E 43 dl 2101 Mpx add 44 3 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction o Koy Hodi MODEX O eissa erate rey Ma n uM eet amet wren Tne Cena oe M t da ARM A D M entree 44 6 DUANE 45 6T HaleAdder Gate ir vet Uim MEME EDI MUN LOI CU MM IM A DELLI D pt 45 0 2 ue Aer Grate NITE HE 46 6 3 Fulle Adder S
14. 102 WIDDINV SS Floorplan ts tal 86 I0 LO A rH a a teesaant me iatancens 87 OA VOPI e aa a aa a a ACE LLL DIM CILLUM Ls DE 87 TOS ESDIPTOTECHONS a ds ces A ANN 88 TOG VO Pad deseripuon usine Ia ico 89 Jl PERUS td ias 92 Li Selecta Desist Rule Ele secas dide A isa 92 11 2 Start Microwind with a specitic deston Rule Pile ai ada Me gere tee ian 92 LS IN Well MDGS OTM IR les TE 92 IDE Difusion SSH TRO T c 93 DLS Polysilicon Desten Rules acsi te e ES EFI A E 93 11 6 2 Polysilicon Design Rule aid 94 LE Dj AAA A 94 lis Contact Deston Ruleta dde Sedona E Dist coi ead sates 94 4 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction Oe Meta Ya De RUIE S reorientar 95 LE Metals Will Oe SPO RES cat dica 95 Li bL Metals V tas Dese ERU Sierra Saeed ate es alan oce ons edicts eae eae aan 95 11 12 Metalt Vat Desrom Roles ani teed al ra nes aeo ode Mte una ms el eet M n asd aM ande 96 11 15 MetalS ve Vias Deston Rules sieut trn aco paste cil 96 ETA Metalo Deston RES A LU ven 96 Ls Fad Desion Rules a EU T Uc 97 12 Electrical AOS Ae 98 Ml Electrical Ctrcut Extra AS AS 98 IEEE A a e nn e o TTE 98 Pa Murla as RET TETUR 99 124 Tae ayere pac aN E a a 99 123 Crossilk Capacitance socra a r a a a 99 2407 RESISTANCE 100 127 Vertical Aspect of the LechtiolO8y ii A A A AA a 100 1 DIE E a E E E E NE A A E E A E E E 101 1239 STM ALO MP ALAIN CIS na a S 102 12 10 Models Levell and Level3 for analog simulation nsyi iinn aa a
15. 3 Sample and Hold circuit 18 05 02 6 The transmission gate used to sample analog signals SampleHold MSK Fig 9 84 MICROWIND amp DSCH USER S MANUAL 9 Converters The effect of sample and hold is illustrated in figure 9 7 When sampling the transmission gate is turned on so that the sampled data DataOut reaches the value of the sinusoidal wave DataIn When the gate is off the value of the sampled data remains constant This is mainly due to the parasitic capacitance of the node which is the order of several fF 2 51 l I I I I A e scc ndo A bee NR ON IA I I I I I l I I l l I l l A SE AA j eS er zEun ELx NN Fig 9 7 Effect of sampling on a sinusoidal wave SampleHold MSK 85 18 05 02 10 10 1 10 2 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing Input Output Interfacing Create a Pad Ring Click on the chip library icon and click on Pads Enable the pad ring option A pad ring with 3 pads in X and 3 pads in Y is generated by a click on Generate Pad In that case a set of pads is added to your circuit The VSS pad is situated at the bottom and the VDD pad at the top with the associated power rings VDD VSS Floor planning The supply network of a typical integrated circuit is shown in figure 10 1 Bars of metal wires cross the circuit to supply the active parts of the circuit The metal wires are designed very large to enabl
16. For most values of Vload N2 produces the same current as NI except when Vload is lower than 0 5V 8 4 Single Stage Amplifier The single stage amplifier is described in figure 8 7 It consists of a MOS device we choose here a n channel MOS and a load resistance The resistance can be made from polysilicon or diffusion As the gain of this amplifier is proportional to the load resistance a MOS device with gate and drain connected as shown in figure 8 7 could replace the resistance This 1s called an active resistance Using a small silicon area high resistance can be obtained meaning high amplifier gains Vds for Source pMOS Load resistance sinus Out eI sinus In nan Daly Sinus In 5 sinus Out Vds for nMOS a b Figure 8 7 Single stage amplifier with passive resistance a and active resistance b Single stage amplifier Active load pMOS Input MOS Figure 8 6 Single Stage amplifier layout AmpliSingle MSK 74 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells In the simulation window click Voltage vs voltage and More to compute the static response of the amplifier Figure 8 9 The range of voltage input that exhibits a constant gain appears clearly For Vps higher than 0 6V and lower than 0 8V the output gain is around 5 Therefore an optimum offset value is 0 7V Change the parameter Offset of the input sinusoidal wave to place the input voltage in t
17. and B3 B2 B1 B0 Insert the user defined Fadd sym symbol using the command Insert gt User Symbol In DSCH2 the A and B numbers are generated by keyboard symbols as reported below Also notice the hexadecimal display with a ground connected to the K input to activate the display A n iul CARRY iT rie nom Lcd ELE TAE SUMO Hee THe l E Br LI C Full amp dder Sm La Fig 6 6 Schematic diagram of the four bit adder ADD4 SCH 49 18 05 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Figure 6 7 details the four bit adder layout based on the full custom cell design with the corresponding simulation In Microwind2 the command Edit gt Duplicate X Y has been used to duplicate the full adder layout vertically An E AE AAA VERA LES CM TEE eR CP HH Silo AE TL Tl ie TE ue o E dv i de Ed bL e S oe n Lg mui rg ead El AA Pe arcs mmn RED Amalie x uc E Fa Gres Wr mer BE E 2 ET EFA dli m pe Hi xw BE FF Ein H UE fats TE pes ESA SD ME ER 5 i ae E Tm ese BLA 7 nme T E E 7 rn mh RIT n rr Er LL HF x Br ral ea a BFI ta Nicaea sity ET ix T CI E LLLI Le c EIE liim HET TE tne coe eee raat ett tt m peed j ES Inm WC ER E CINES E E Cx ee it jo ti IE pnr ABE ad Ni ici oA ppm Ey pretii 7 qi ELTE GE aca LE SE DM mm s TE 25 LE EZE pe ees C BETIS me E im bil Fe E E T
18. gates NAND NOR INV are faster and simpler than the non negative gates AND OR Buffer The cell delay observed in the figure 5 5 are significantly higher than for the NAND2 gate alone due to the inverter stage delay Fig 5 5 Layout and simulation of the AND gate The 3 Input OR Gate The truth table and the schematic diagram of the three input OR gate are shown in Figure 5 6 You may use the DSCH2 logic editor to design a schematic diagram based on the OR gate generate a Verilog description and compile the text file in Microwind2 As can be seen again in the final layout the OR gate is the sum of a NOR3 gate and an inverter 39 18 05 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates OR 3 Inputs A B C Or3 0 0 0 0 0 0 1 0 0 0 1 0 0 1 0 1 0 1 1 1 1 Fig 5 6 The truth table and symbol of the OR3 gate S lambda 1 525 rri E Fa Cas E E F Er PT L e e Se g Un 3 IRR om Fig 5 7 Layout and simulation of the OR3 gate OR3 MSK 5 4 The XOR Gate Et XOR 2 inputs A B OUT 00 0 01 l 10 l 11 0 The truth table and the schematic diagram of the CMOS XOR gate are shown above There exist many possibilities for implementing the XOR function into CMOS The least efficient design but the most forward consists in building the XOR logic circuit from its Boolean equation 40 18 05 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Ga
19. non homogeneous oxide structure homogeneous oxide structure Fig 12 4 Illustration of the use of LOWK HIGHK dielectric constants left figure or detailed permittivity for each layer right figure 4 4 3 3 3 3 3 101 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 9 Simulation Parameters The following list of parameters 1s used in Microwind2 to configure the simulation CODE DESCRIPTION TYPICAL VALUE Supply voltage of the chip High voltage supply DELTAT Simulator minimum time step to ensure 0 5e 12 s convergence You may increase this value to speed up the simulation but instability problems may rise TEMPERATURE _ Operating temperature of the chip RISETIME Typical rise and fall time of clocks 12 10 Models Level1 and Level3 for analog simulation Four types of MOS devices may be described as detailed in figure 12 4 Data from SIA 0 12um CMOS technology In the rule file the keyword MOSI MOS2 MOS and MOS4 are used to declare the device names appearing in menus In 0 12um technology three types of MOS devices are declared as follows Also NMOS amp PMOS keywords are used to select n channel Mos or p channel Mos device parameters MOS MOS2 MOS3 CET Speed T Leakage DIE voltage Vt nmos Vt pmos KPammo ho ho bo KP pmos MOS definition MOS1 low leakage MOS2 high speed MOS3 high voltage Figure 12 5 Description of MOS options in 0
20. passivation v s metals rp05 5um Between pad and unrelated active rp01 area 20 um 97 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 Electrical Rules 12 1 12 2 Electrical Circuit Extraction MICROWIND2 includes a built in extractor from layout to electrical circuit Worth of interest are the MOS devices capacitance and resistance The flow is described in figure 12 1 Layout Skip in case of big circuits Clean layout P d A Extract MOS width Esteact devices Eo Extract MOS length Extract MOS option Eae e i Extract all electrical nets L A Extract net capacitance Extract coupling capacitance between nets A Extract net resistance Create SPICE netlist Figure 12 1 Extraction of the electrical circuit from layout The first step consists in cleaning the layout Mainly redundant boxes are removed overlapping boxes are transformed into non overlapping boxes In the case of complex circuits MICROWIND2 may skip this cleaning step as it required a significant amount of computational time Capacitance Each deposited layer is separated from the substrate by a S102 oxide and generated by a parasitic capacitor The unit is the aF um2 atto 10 18 Basically all layers generate parasitic capacitors Diffused layers generate junction capacitors N P P N The list of capacitance handled by MICROWINDJ2 is given below The name corresponds to the code
21. th s Sr eg E ge m eel R ri 1 A 1 T p ER a eee 7 V uti iO E Ilt Yo a EE TAL be ee XU Li ge Ret MS NETT o RUF AR Bow teat ee etr ot Wi Frequency GHiz ae _ A A A p j 7 10 00 8 00 BOO pere em MICROWIND amp DSCH USER S MANUAL i et ee o A 18 05 02 A SS E DO ap E gay Ae ane dupe e eo enisi ins cii uu oe ale es i scusa cumin es ipu AA AAN we use the specific mode Frequency and Voltages to plot the gt 18 frequency variation with Vc The VCO output is a frequency varying square wave Its 0 00 Fig 8 18 Simulation of the voltage controlled oscillator dependence with Vc is not linear In the simulation of figure 8 80 MICROWIND amp DSCH USER S MANUAL 9 Converters 9 Converters 9 1 Analog Digital Converter The analog digital converter converts an analog value Vin into a two bit digital value called A0 A1 The flash converter uses three converters and a coding logic to produce AO and AI Figure 9 1 A very complex logic circuit and 255 comparators would be used for an ADC eight bit flash The polysilicon has a high resistance 50 per square and can be used as a resistor network Left of Figure 9 2 which generates intermediate voltage references used by the voltage comparators located in the middle The
22. 102 1211 BSIM4 Model tor analop sim lation said tai 104 2 12 REC tile tor DS CW cad 105 ES DESTE Rule Pile Jor DA atasesesutssesecteasivesstssase otevesesstesesecdinns 106 I4 ROI erelt RCA CORE RE Ms aT ECR E ld 109 5 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction 1 Introduction amp Installation The present manual introduces the design and simulation of CMOS integrated circuits in an attractive way thanks to user friendly PC tools Dsch2 and Microwind2 About Dsch2 The DSCH2 program is a logic editor and simulator DSCH2 is EA Dsch2 C Dsch 2 0 Manual uw2 Add4 sch A ES File Edt Inset View Simulate Help used to validate the architecture of the logic circuit before the c H Dlx yo F cf BBA La wWaQgk D bu e ae d al microelectronics design is started DSCH2 provides a user friendly environment for hierarchical logic design and auTO simulation with delay analysis which allows the design and validation of complex logic structures A key innovative d feature is the possibility to estimate the power consumption of the circuit Some techniques for low power design are Fast Slow described in the manual initialCarry C v Wirestate Pinvalue Reg stae NI Keyboard X1 at 64 94 About Microwind2 The MICROWIND2 program allows the student to design and gt Microwind 2 C microwind2 Manual mw2 inv3 MSK File View Edit Simulate Compile Analysis Help DET pu
23. 12 The differential pair is built from n channel MOS devices Their size must be identical and drawn with the same orientation to minimize the offset generated by transistor mismatch In the simulation it can be seen that a small voltage difference between V and V induces the saturation of the output either near VSS and VDD ul ERES urrent mirror S S gt BS e We Mau Many unu EE UU ue AULA yy poppe 4 Im AA a ULT 772 75 2222 NA opcre ul cw cupere oct rw d iddmaxz 678mA Ed MI i i issMax 0 690mA 0 80 ae rd ee SSS SS A an ee er rry Ps I 1 l out 1 1 i i 1 1 l 1 00 ft iy High power i A consumption 0 40 J4 1 MI 1 D 1 e um 0 20 E SOR LU V varies from the difference Power 4 39 mw 1 L O 0 00 1 8 to 2 0V Se ae anaes novum 3 e ara a de ss a asa qe Ped V is constant 1 9V 5 Figure 8 12 Layout and transient simulation of the differential amplifier AmpliDiff MSK 76 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells MEASURE THE GAIN 1 Click Voltage vs Voltage to select static characteristics mode 2 Select Slope in the Evaluate menu 3 Click More to compute the static characteristics of the differential amplifier The value of the gain is added on the simulation window MEASURE THE INPUT RANGE The best way to measure the input range 1s to connect the differential amplifier as a follower that is Vou
24. 12um technology cmos012 RUL The list of parameters for level 1 and level 3 is given below PARAMETER KEYWORD DEFINITION TYPICAL VALUE 0 251 m NMOS pMOS VTO i3vto Threshold voltage wo mo Low field mobility 0 06 mV s 0 025 mis TSpha Surface potential at strong 0 3V 0 3V inversion 102 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules rotad Lateral diffusion into 0 0lum 0 0lum channel GAMMA Bulk threshold parameter KAPPA Saturation field factor 0 01 V 0 01 V VMAX Maximum drift velocity 150Km s 100Km s THETA 13theta Mobility degradation 0 3 V 0 3 V factor Substhreshold factor 0 07 V 0 07 V Gate oxide thickness For MOS2 MOS3 and MOSA only the threshold voltage mobility ant oxides thickness are user accessible All other parameters are identical to MOSI NMOS pMOS MOS2 MOS3 U0 Mos2 Mobility for MOS2 000 U0 Mos3 Mobility for MOS3 000 MOS2 MOS3 Nmos Model parameters NMOS LSVEO 04 Lou O 06 LSCOX 36 9 l3vmax 170e3 l3gamma 0 4 DOLI eU S Du l3kappa 0 06 pham 2 131d 8e 9 bones usse high speed Lovato 043 Lua 19 4 36 13t2ox 3e 9 high voltage 13v3to 0 7 T DS SO 6 13t30x 7e 9 103 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules 12 11 BSIM4 Model for analog simulation The list of parameters for BSIM4 is given below Parameter Keyword Description VEB b4vfb
25. 50 o SON R HEEE L The measured ERE maximum current is S Mi 0 00 a a Hi a vos Fig 3 11 The model 1 predict a current 4 times higher than the measurement When dealing with sub micron technology the model 1 is more than 4 times too optimistic regarding current prediction compared to real case measurements as shown above for a 10x0 25um n channel MOS The MOS Model 3 For the evaluation of the current Ids as a function of Vd Vg and Vs between Drain and Source we commonly use the following equations close from the SPICE model 3 formulations The formulations are derived from the model 1 and take into account a set of physical limitations in a semi empirical way CUT OFF MODE Ves lt 0 Ids 0 NORMAL MODE Vgs gt Von Ids Keff bal 1 KAPPA vds Vde Vgs vth ve LEFF 2 with von 1 2 vth vth VTO GAMMA A PHI vb 4 PHI vde min vds vdsat vdsat vc vsat 4 vc vsat vsat vgs vth 19 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter ve VMAX 0 06 LEFF L 2LD Repo EP __ 1 THETA ves vth SUB THRESHOLD MODE Ves lt Von Vds 1s replaced by von in the above equations Ids Ids von vds e aves atom nkT TEMPERATURE EFFECTS un uno T 300 e up upo T 300 e vt vto 0 002 T 300 Mos MODEL 3 PARAMETERS PARAMETE DEFINITION TYPICAL VALUE 0 25um R p Theshold voltage Transconductance coefficient 3 ic PHI Surfac
26. A Helg T PA M Pa Fi rH pos icri a i a sch NS BEIM TE a aru ME a i F En Er pii 1 am io x 03 EIF ES Wem BH EUER E d ii UNO ON SU M 1 AH F Lu HH maA E P pe T T i fe AE E trea EE UEM EAS GE E BON EET FALL dli i m FE IF un a ri ire D E Qm as k aeh x E A O E a HEIC E E i A EAN id zm ar HE LER Ur Teen Ws Fig 6 7 Design and simulation of the four bit adder ADD4 MSK 90 18 05 02 6 6 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Comparator The truth table and the schematic diagram of the comparator are given below The A B equality represents an XNOR gate and A gt B A lt B are operators obtained by using inverters and AND gates Comparator A B A gt B _A lt B__A B 0 0 0 0 0 0 0 0 0 0 0 Fig 6 8 The truth table and schematic diagram of the comparator COMP SCH Using DSCH2 the logic circuit of the comparator is designed and verified at logic level Then the conversion into Verilog is invoked File gt Make verilog File Microwind2 compiles the verilog text into layout The simulation of the comparator is given in Figure 6 9 The XNOR gate is located at the left side of the design The inverter and NOR gates are at the right side After the initialization A B rises to 1 The clocks A and B produce the combinations 00 01 10 and 11 Fig 6 9 Simulation of a comparator COMP
27. Aspect of the Technology The vertical aspect of the layers for a given technology is described in the RUL file after the design rules using coed HE height and TH thickness for all layers The figure 12 3 below illustrates the altitude 0 which corresponds to the channel of the MOS The height of diffused layers can be negative for P EPI layer for example Layer altitude in um 2 0 1 0 Altitude 0 0 contro el pg STI height is negative EPI height is negative 100 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules Figure 12 3 Description of the 2D aspect of the CMOS technology DESCRIPTION PARAMETERS Buried layer made of P used to create a HEEPI for height negative in good ground reference underneath the active respect to the origin area THEPI for thickness active areas THSTI for thickness layer THPASS for thickness Final oxide on the top of the passivation HENIT for height usually Si3N4 THNIT for thickness NISO Buried N layer to isolate the Pwell HENBURRIED for height underneath the nMOS devices to enable THNBURRIED for thickness forward bias and back bias 12 8 Dielectrics Some options are built in Microwind to enable specific features of ultra deep submicron technology Details are provided in the table below HVTOX Substrate Metal 4 LOWK HIGHK HIGHK HIGHK Metal 1 LOWK HIGHK Substrate Substrate Using LOWK HIGHK with Using Lkii LKij with
28. MOS pass transistors The cell has been designed to be duplicated in X and Y in order to create a large array of cells Usual sizes for Megabit SRAM memories are 256 x 256 cells or higher An arrangement of 4x4 RAM cells is also shown in figure 6 14 The selection line Sel concerns all the cells of one row The lines Data and nData concern all the cells of one column Memory Cell Fig 7 11 The schematic diagram of the static RAM cell RAM I SCH The RAM layout is given in Figure 7 12 Click on File gt Open RAM MSK to read it The Data and nData signals are made with metal2 and cross the cell from top to bottom The supply lines are horizontal made with metal3 This allows easy matrix style duplication of the RAM cell The cross section shows the nMOS devices and the connection to VSS using metal3 situated on the middle of the cell The Data and nData lines in metal2 are on both sides 62 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories E Ed Hayaa3p o 2333 FFFFF ooo Fig 7 12 The layout of the static RAM cell RAM I MSK WRITE CYCLE Values 1 or 0 must be placed on Data and the data inverted value on nData Then the line Sel goes to 1 The two inverter latch takes the Data value When the line Sel returns to O the RAM is in a memory state See figure 7 13 for the analog simulation of the WRITE cycle READ CYCLE In order to read the cell the line Sel must be asserted The RAM
29. MSK file 91 18 05 02 6 7 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Arithmetic and logic Units ALU The digital function that implements the micro operations on the information stored in registers is commonly called an arithmetic logic unit ALU The ALU receives the information from the registers and performs a given operation as specified by the control A very simple ALU design is proposed to illustrate its principle The control unit is made up of a 4 1 multiplexor The operation part consists of four kinds of operations listed as follows and or addition and subtraction The and and or operation are realized by using the basic logic gates The addition and subtraction are realized using the ADDER user symbols A digital multiplexer made from MOS devices selects one of the 4 operations results and directs it to a single output line Result L H Carry Sump Borrow Res Alu Fig 6 10 The 1 bit ALU operates the and or addition and substraction ALU Ibit SCH 52 18 05 02 6 8 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics Critical Path In DSCH2 a specific command computes the critical path that is the path between one input and one output with the longest switching delay In the example reported in figure 6 11 the critical path between inputs inl in2 in3 and the outputs is marked using dot lines The estimated maximum delay is 0 38ns bottom output while the other branch e
30. S zc IE BHH ES A t Tett F tH E m E iw pa E bi n F Ei Ili E a E An ERE idiei uM EPA EJE ELE e d tle y m NON EIE AG 4 4 G ee pe rE ERE Brey eae ZEEE EERE E ru EI HH El H Er EHHH Ela Se Fig 7 14 Duplicating the RAM Cell in X and Y 64 18 05 02 7 Latches and Memories MICROWIND amp DSCH USER S MANUAL 7 7 RAM Line decoder The line decoder is based on the following schematic diagram One line is asserted while all the are at zero In this circuit one line was picked out from a choice of four lines Using other lines AND gates would be an easy solution but in order to save the inverter we choose NOR gates with inverted inputs Fig 7 15 A line selection circuit L 0 0 9 1 ET I I I I a ee is 5 00 Line Adress lee Does Line Anressi p 4 L5 00 ns 2 0 4 0 6 0 8 0 10 0 2420 14 0 16 0 18 0 0 0 Fig 7 16 A line selection layout and its corresponding simulation RamLineSelect MSK 18 05 02 65 7 8 7 9 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories The NOR gate height should be adjusted to that of the RAM cell height When making the final assembly between blocks the command Edit gt Move Area is very important This command helps to move a selected block with a lambda step RAM Column Selection The column selection circuit is based on the same principles as those of the line de
31. The erasure involves the transfer of electrons from the floating gate back to the source Fig 7 22 The double poly MOS device used as a non volative memory The programming operation is performed using a very high gate voltage on poly2 usually around 10V The mechanism for electron transfer from the grounded source to the floating polysilicon gate is called tunneling With a sufficiently positive voltage on the poly2 gate the voltage difference between poly and source is high enough to enable electrons to pass through the thin oxide The electron transfer mechanism is called hot electron injection Fig 7 23 Erase operation to remove electrons For the erase operation Figure 7 23 the poly2 gate is grounded and a high voltage Around 10V is applied to the source Electrons are pulled off the floating gate thanks to the high electrical field between the source and the floating gate This charge transfer 1s called Fowler Nordheim electron tunneling 69 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories From an operational point of view the double poly MOS device works as a normal MOS when the floating gate is discharged a VDD gate voltage is high enough to turn the device on Consequently a Ids current flows between the drain and grounded source If the floating gate 1s charged with electrons the threshold voltage is very high and a VDD gate voltage is not sufficient to turn the MOS on Almost no Ids curr
32. Vs 0 0 The MOS parameters correspond to SPICE Level 3 A tutorial on MOS model parameters is proposed later in this chapter 3 6 Dynamic MOS behavior This paragraph concerns the dynamic simulation of the MOS to exhibit its switching properties The most convenient way to operate the MOS is to apply a clock to the gate another to the source and to observe the drain The summary of available properties that can be added to the layout is reported below VDD property VSS property Clock property IL Vv 4 Node visible Sinusoidal wave Pulse property O Apply a clock to the gate Click on the Clock icon and then click on the polysilicon gate The clock menu appears again Change the name into Vgate and click on OK to apply a clock with 2 1ns period Ins at 0 50ps rise Ins at 1 SOps fall 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Add a Clock Label name VOD v55 Clock Puise Sinus Variable Parameter Low level V9 0 00 High Level vj 2 50 Tinie low Risetme Timehiah Falltime ns ion oos 1 00 0 05 TU Stower AR Faster x Invert LiH a Assign X amp cancel Iv visible in simulation Fig 3 7 The clock menu O Apply a clck to the drain Click on the Clock icon click on the left diffusion The Clock menu appears Change the name into Vdrain and click on OK A default clock with 4 2ns period 1s generated The Clock property is sent to th
33. c level using the logic editor and simulator DSCH2 and at layout level using the tool MICROWIND2 The LOGIC Inverter In this section an inverter circuit 1s loaded and simulated O Click on the icon above to activate the Dsch2 software O Click File gt Open in the main menu Select INV SCH in the list In this circuit are on button situated on the left side of the design namely A an inverter and a led Click Simulate gt Start simulation in the main menu Fig 4 1 The schematic diagram including one single inverter Inverter SCH Now click inside the buttons situated on the left part of the diagram The result is displayed on the lamps The red value indicates logic 1 the black value means a logic 0 Click the button Stop simulation shown in the above picture You are back to the editor Click the above icon to get access to the chronograms of the simulation Double click on the INV symbol the symbol properties window is activated In this window appears the VERILOG description left side and the list of pins right side A set of drawing options is also reported in the same window Notice the gate delay 0 06ns in the default technology the fanout that represents the number of cells connected to the output pin 1 cell connected and the wire delay due to this cell connection An extra 0 1ns delay 30 18 05 02 4 2 MICROWIND amp DSCH USER S MANUAL 4 The Inverter THE CMOS INVERTER
34. coder The major modification is that the data flows both ways that is firstly from the cell to the read circuit Read cycle and secondly from the write circuit to the cell Write cycle Fig 7 17 proposes an architecture for this The n channel MOS device is used as a switch controlled by the column selection When the n channel MOS is on and Write is asserted the data issued from DatalIn is amplified by the buffer flows from the bottom to the top and reaches the memory If Write is off the 3 state inverter is in high impedance which allows one to read the information Circuit principles for one column selection Dataln is amplified validated and sent to vertical data bus TTT oo e e e e e e e 1 o o 1 e 1 e e o Ou o g ColumnSelect n goo BF ta i Todata TonData ee rar o o ee o o JHo 4 Fig 7 17 Row selection and Read Write circuit RamColumn SCH Dynamic RAM Memory The dynamic RAM memory uses a single MOS device with a parasitic junction capacitance as a storage element In figure 7 18 a set of 4x4 dynamic RAM cells are reported The gates are connected horizontally while the drains are connected vertically Furthermore the sources are connected to a polarization node 66 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories m i m nummum
35. connected from the drain When the gate is on the source copies the drain It can be observed that the nMOS device drives well at zero but poorly at the high voltage The highest value of s1 is around 2 0V that is VDD minus the threshold voltage This means that the n channel MOS device do not drives well logic signal 1 as summarized in figure 3 9 Click on More in order to perform more simulations Click on Close to return to the editor 0 m ap no Ma i 1 0 AN Good 0 1 J Poor 1 VDD Vt Fig 3 9 The nMOS device behavior summary Layout considerations The safest way to create a MOS device is to use the MOS generator In the palette click the MOS generator icon A window appears as reported below The programmable parameters are the MOS width length the number of gates in parallel and the type of device n channel or p channel By default metal interconnects and contacts are added to the drain and source of the MOS You may add a supplementary metal2 interconnect on the top of metal 1 for drain and source 17 18 05 02 3 9 MICROWIND amp DSCH USER S MANUAL 4 The Inverter I 5 Layout Generator A ES hoy Palette Pads Inductor Contacts Bus MOS Path Logo Access to MOS Li E E Mos Parameters generator N4 d X X Width mos 5250 um L Se Length MOS 0 250 pm m PHILA LM a A ne ou raat MbrofGates fl m T Add metal to drain and source Channel C p Channal
36. cron l technology 1 0 Industry Research 0 1 82 85 89 92 95 98 01 04 Year Fig 2 3 Evolution of lithography 8 18 05 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 2 Frequency Improvements 0 5 um 0 25 um 0 12um MOS Devices 4995 1998 Hi 2001 Sayer 5 layers 7 layers n mmea m JH dd frequency JA 120MHz 350MHz 800 MHz Fig 2 4 Reduced device features and increased interconnect layers Figure 2 4 illustrates the main improvements in terms of feature size reduction for MOS devices increased number of metal interconnects to link MOS together within the chip Consequently the clock frequency of the chip has never stopped increasing with an expected 800MHz in 2001 An illustration is given below Figure 5 with a ring oscillator made from 3 inverters simulated with MICROWIND2 using 0 8um and 0 25um technologies Although the supply voltage has been cut by half VDD is 5V in 0 8um 2 5 in 0 25um the E mn ie a is close from a factor of five 0 8 um f i 7 N O 845ns i 0 915ns 2 67 d 1853GHz l i if 1 093GHI i i l 0 0 0 2 04 DE D8 10 12 14 18 18 ns d 5 2 353 2 356 2 355 2 356 2 356 12 354 pls 2 356 _ ug 2 355 2 355 0 25 um l Gortie i 0 224ns 0 228ns 224ns 0 224ns J 228ns 0 224ns D 224ns i 1 228ns i i 2d AEN S 4 PIE ae ib n 4 386GHZ i i ids 0 0 0 2 0 4 0 6 0 8 1 0 12 14 1 6 1 8 ns Fig 2 5 Improve
37. ction of the Inverter circuit near the nMOS device 3D View of the Process T q m mae eed a z f I ib ee Click Simulate gt Process steps in 3D or the icon above The simulation of the CMOS fabrication process is performed step by step On figure 4 10 the picture represents the nMOS device pMOS device common polysilicon gate and contacts together with the metal layers stacked on the top of the active devices Fig 4 10 The step by step fabrication of the Inverter circuit 35 18 05 02 4 8 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 3 STATE INVERTER Until now all the symbols produced the value logic 0 and logic 1 However if two outputs are connected together as the left circuit shown below it will provoke a circuit error In order to avoid such conflicts specific symbols are used featuring the possibility to remain in a high impedance state The 3 state symbol used below is Bufif and it consists of the logic buffer and an enable control There also exists a 3 state inverter NotifT The output remains in high impedance as long as the enable En is set to level The truth table of the 3 state inverter is reported below Fig 4 11 Truth table of the three state inverter 36 18 05 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates 5 Basic Gates 9 1 The Nand Gate The truth table and logic symbol of the NAND gate with 2 inputs ar
38. diffusion boxes are represented in green The intersection between diffusion and polysilicon creates the channel of the nMOS device Fig 3 4 Creating the N channel MOS transistor Vertical aspect of the MOS z y Click on this icon to access process simulation Command Simulate gt Process section in 2D The cross section is given by a click of the mouse at the first point and the release of the mouse at the second point 13 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Interlayer oxide Field oxide B Lateral drain diffusion Thin gate oxide Fig 3 5 The cross section of the nMOS devices In the example of Figure 3 5 three nodes appear in the cross section of the n channel MOS device the gate red the left diffusion called source green and the right diffusion called drain green over a substrate gray A thin oxide called the gate oxide 1solates the gate Various steps of oxidation have lead to stacked oxides on the top of the gate The physical properties of the source and of the drain are exactly the same Theoretically the source is the origin of channel impurities In the case of this nMOS device the channel impurities are the electrons Therefore the source is the diffusion area with the lowest voltage The polysilicon gate floats over the channel and splits the diffusion into 2 zones the source and the drain The gate controls the current flow from the drain to the source bo
39. e node and appears at the right hand side of the desired location with the name Vdrain O Watch the output Click on the Visible icon and then click on the right diffusion Click OK The Visible property is then sent to the node The associated text s1 is in italic meaning that the waveform of this node will appear at the next simulation Always save BEFORE any simulation The analog simulation algorithm may cause run time errors leading to a loss of layout information Click on File gt Save as A new window appears into which you enter the design name Type for example myMos Then click on Save The design is saved under that filename 3 Analog Simulation Click on Simulate Start Simulation The timing diagrams of the nMOS device appear as shown in Figure 3 8 16 18 05 02 4 The Inverter MICROWIND amp DSCH USER S MANUAL 3 8 5 Simulation of C microwind2 M anual mw2 nM0S_MSK Detay between VOrain and 51 v vDrain Time Scale 10ns Pewee Evaluate MiniMax Frequency s1 Step psi 15 2 50 eco f ik OOK cos 7 0 8 0 9 0 ns 0 0 1 0 2 0 3 0 4 0 5 0 6 0 Voltage vs time voltages and currents f and currents A Voltage vs voltage Fig 3 6 Analog simulation of the MOS device 8 p 5 1070ps Stop When the gate is at zero no channel exists so the node sl is dis
40. e number of parameters specified in the official release of BSIM4 is as high as 300 A significant portion of these parameters is unused in our implementation We concentrate on the most significant parameters for educational purpose The set of parameters is reduced to around 20 5 MOS Viewer for Nmos Width 10 020 Length 0 120 pm Id vs Vd 1d vs va logtid vs Va Threshold voltage Mobility Debug T Elmo 400 6 0 ee eee 1 20 Toxe 5500 lt 5 5 A acacia ovs o al LATA HAT l doma ARA 3 0 o EE Quem ILL o y HZI 2 oo rara A eee H E Fi Y ad 2 st ttt AAA ttt tt tt if l n ua Vac 0 00 0 20 0 40 0 60 0 80 1 00 1 21 vas le ads Add measure E E v temote i20 Fervatomoi 20 step Va o20 elf AAA d JL Nmos Pmos w OK ra Draw LE Fit W 10um L 0 1 20yr low leakage A Nmos a Fig 3 13 Implementation of BSIM4 within Microwind2 The general equation of the threshold voltage is presented below vth VTHO KIN P Vbs 4 K2Vbs AVtcz AVtyurp FAVE 51 21 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter where VTHO is the long channel threshold voltage at Vbs 0 Around 0 5V K1 is the first order body bias coefficient 0 5 V bs is the surface potential Vbs is the bulk source voltage K2 is the second order body bias coefficient AVtsck is the short channel effect on Vt AVtuyp is the non uniform la
41. e potential at strong 0 3V ae NR LD NSS LD Lateral diffusion into channel O0lum 0 100Km s 03 V The curve shown in Figure 3 12 is used to fit VTO KP and GAMMA Act on VTO cursors in order to shift the curves right or left KP to adjust the slope and GAMMA to fit the spacing between curves 10x10 um Beta 155 12 1n AAS MEN VTO zs je A E See Se le ee ee ee ld a See yi 0 00 0 50 1 00 1 50 2 1 2 Fig 3 12 The Id Vg curves used to fit KP VTO and GAMMA Nb10x10 MES 20 18 05 02 3 11 MICROWIND amp DSCH USER S MANUAL 4 The Inverter The BSIM4 MOS Model A family of models has been developed at the University of Berkeley for the accurate simulation of sub micron technology The Berkeley Short channel IGFET Model BSIM exist in several version BSIMI BSIM2 BSIM3 The BSIM3v3 version promoted by the Electronic Industries Alliance EIA is an industry standard for deep submicron device simulation A new MOS model called BSIM4 has been introduced in 2000 A simplified version of this model is supported by Microwind2 and recommended for ultra deep submicron technology simulation BSIM4 still considers the operating regions described in MOS level 3 linear for low Vds saturated for high Vds subthreshold for Vgs lt Vt but provides a perfect continuity between these regions BSIM4 introduces a new region where the impact ionization effect 1s dominant Th
42. e shown below In DSCH select the NAND symbol in the palette add two buttons and one lamp as shown above Add interconnects if necessary to link the button and lamps to the cell pins Verify the logic behavior of the cell p A B Out 00 1 01 1 10 1 11 0 Fig 5 1 The truth table and symbol of the NAND gate In CMOS design the NAND gate consists of two nMOS in series connected to two pMOS in parallel The schematic diagram of the NAND cell is reported below The nMOS in series tie the output to the ground for one single combination A 1 B 1 For the three other combinations the nMOS path is cut but a least one pMOS ties the output to the supply VDD Notice that both nMOS and pMOS devices are used in their best regime the nMOS devices pass 0 the pMOS pass 1 0m 0 751m Fig 5 2 The truth table and schematic diagram of the CMOS NAND gate design 3 18 05 02 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates You may load the NAND gate design using the command File gt Read gt NAND MSK You may also draw the NAND gate manually as for the inverter gate An alternative solution is to compile directly the NAND gate into layout with Microwind2 In this case complete the following procedure EMOS Cell Compiler 22200200 In Microwind2 click on Compile gt Compile One Line Select the line corresponding to the 2 input NAND description as shown above The input and output names can be by the user mod
43. e strong currents to flow within the supply interconnects Basic cells VDD Pad gi HL LL LLL we Fig 10 1 Supply of an integrated circuit 86 18 05 02 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing VO pad with its ESD protections E 6 z z VSS supply d i UAE ng fcr rss A VDD ring Fig 10 2 Supply network in a real case circuit 10 3 High Voltage MOS For interfacing with input output specific high voltage MOS are introduced These MOS devices are called high voltage MOS They use a thick gate oxide to handle the high voltage of the I Os An example of high voltage MOS device is reported below N I MOS High Voltage orma MOS 3 3V Fig 10 3 The High voltage MOS device is used in 3 3V I Os The high voltage MOS uses a gate width which 1s slightly larger than the one of the regular MOS As the high voltage MOS device is generally used in I O structures the MOS width is usually large even sometimes very large 100 500um 10 4 1 0 Pad We give here some details about input output pad structure The basic bonding pad size 1s 100x100um The pad consists of a sandwich of metal layers For advanced technologies all metal layers are stacked on the top of each other The passivation oxide has been removed from over the pad so that a gold connection can be fixed upon it 67 18 05 02 10 5 MICROWIND amp DSCH USER S MANUAL 10 Input Output Int
44. ed The MOS as a switch The MOS transistor is basically a switch When used in logic cell design 1t can be on or off When on a current can flow between drain and source When off no current flow between drain and source The MOS is turned on or off depending on the gate voltage In CMOS technology both n channel or nMOS and p channel MOS or pMOS devices exist The nMOS and pMOS symbols are reported below The n channel MOS is built using polysilicon as the gate material and N diffusion to build the source and drain The p channel MOS is built using polysilicon as the gate material and P diffusion to build the source and drain The symbols for the ground voltage source 0 or VSS and the supply 1 or VDD are also reported in figure 3 1 drain source gate gate nrpos pros source drain n channel MOS p channel MOS Ground for 55 supply for DD 0 1 nMOS VV gt 0 1 pMOS Y Y Fig 3 1 the MOS symbol and switch The n channel MOS device requires a logic value 1 or a supply VDD to be on In contrary the p channel MOS device requires a logic value O to be on When the MSO device 1s on the link between the source and drain is equivalent to a resistance The order of range of this on resistance is 100Q 5KQ The off resistance 1s considered infinite at first order as its value 1s several MQ 11 18 05 02 3 2 3 3 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Logic Simulation of the MOS At logic
45. ed to half of the minimum available lithography of the technology The default technology is a CMOS 6 metal layers 0 25um technology consequently lambda is 0 125 um Microwind 2 example ioj xi File View Edit Simulate Compie Analysis Help eB YFY S89 atin wea BAe Ee 5 lambda E EE J 0 625um B Metal 2 n Via M1 M2 Iv Metal 1 gll IV Contact s Polysilicium ll Iv P Diffusion E F iIST0 250m B 7 Welcome to Microwind 2a 04 11 1999 No Error 12 18 05 02 3 4 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 3 The MICROWIND2 window as it appears at the initialization stage The palette 1s located in the lower right corner of the screen A red color indicates the current layer Initially the selected layer in the palette is polysilicon By using the following procedure you can create a manual design of the n channel MOS O Fix the first corner of the box with the mouse While keeping the mouse button pressed move the mouse to the opposite corner of the box Release the button This creates a box in polysilicon layer as shown in Figure 3 4 The box width should not be inferior to 2 A which is the minimum width of the polysilicon box O Change the current layer into N diffusion by a click on the palette of the Diffusion N button Make sure that the red layer is now the N Diffusion Draw a n diffusion box at the bottom of the drawing as in Figure 3 4 N
46. el is created for a logic O on the gate Load the file pmos msk and click the icon MOS characteristics The p channel MOS simulation appears as shown in Figure 3 19 Note that the pMOS gives approximately half of the maximum current given by the nMOS with the same device size The highest current is obtained with the lowest possible gate voltage that is 0 VDrain 1 i i F 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 n Fig 3 19 Layout and simulation of the p channel MOS pMOS MSK 26 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 20 Summary of the performances of a pMOS device From the simulation of figure 3 19 we see that the pMOS device is able to pass well the logic level 1 But the logic level O is transformed into a positive voltage equal to the threshold voltage of the MOS device The summary of the p channel MOS performances is reported in figure 3 20 27 18 05 02 3 16 MICROWIND amp DSCH USER S MANUAL 4 The Inverter The Transmission Gate Both NMOS devices and PMOS devices exhibit poor performances when transmitting one particular logic information The nMOS degrades the logic level 1 the pMOS the logic level 0 Thus a perfect pass gate can be constructed from the combination of nMOS and pMOS devices leading to improved performances Enable signalln signalOut Signalut Fig 3 21 The transmission gate The transmission gate let a signal flow if Enable is a
47. elay 0 07 TypoLceal current in mA TCurrent 0 5 Default MOS length and width MI TOU LAU MNW 1 0u MPW 2 0u 105 18 05 02 DSCH amp MICROWIND USER S MANUAL 13 Design Rules File for 0 12um 13 Design Rule File for 0 1 2um MICROWIND 2 0 Rule File for CMOS 0 12um Date 27 Apr 99 created by Etienne Sicard 04 Jan 00 smaller dt Q3 Avr 01 2d cross section x 17 Apr 01 update params add high voltage tox level3 20 Apr 01 various lowK 4 types of MOS 10 Dec O1 Bsim4 model gatek NAME CMOS 0 12um 6 Metal lambda 0 06 Lambda is set to half the gate size metalLayers 6 Number of metal layers Dielectrics lowK 3 2 inter metal oxide permittivity gateK 5 0 HighK gate dielectric Design rules associated to each layer Well riol 10 well width r102 11 well spacing Diffusion r201 4 diffusion width r202 4 diffusion spacing r203 6 border of nwell on diffp r204 6 nwell to next diffn Poly r301 2 poly width r302 2 gate length r303 4 high voltage gate length r304 3 poly spacing r305 1 spacing poly and unrelated diff r306 4 width of drain and source diff r307 2 extra gate poly Poly 2 poll lieu poly2 width 106 r312 2 poly2 spacing x Contact r401 2 contact width r402 3 contact spacing r403 2 metal border for con
48. electrons and holes when the temperature increase due to a higher atomic volume of the crystal underneath the gate and consequently less space for the current carriers The modeling of the temperature effect 1s as follows KP T KP To T To e VTO T VTO T9 0 002 T To With To 300 K generally Ids tpe Lo 75 a pe ed E EE mE pepe E EE GENE NE MC ON E A AAA A 25 EA ET ee is ho Ue IM nt E AAA A n jo dE AA An AA 0 EA E vb 0 00 E bo O n pe o ue E E AE 0 00 0 50 1 00 1 50 2 01 25 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter Fig 3 18 Effect of temperature on the MOS device characteristics To obtain this curve proceed as follows E 0 Click the icon MOS characteristics o Select one MOS in the design or click anywhere e Select the curve Id Vg el Enable the screen memory mode by a click on this icon Tempe 100 00 E Change the temperature The change in the slope 1s shown You may reduce the number of Id curves by putting a 0 0 in the field For Vb from 0 to In Microwind2 you can get access to temperature using the command Simulate gt Simulation Parameters The screen below appears The temperature is given in C 3 15 The PMOS Transistor The p channel transistor simulation features the same functions as the n channel device but with opposite voltage control of the gate For the nMOS the channel is created with a logic 1 on the gate For the pMOS the chann
49. endors and end customers a format has been proposed by the IBIS group www eia org ibis The intention of the IBIS to specify a consistent format that can be parsed by software allowing simulation vendors to derive models compatible with their own products The version 3 2 of IBIS was finalized by an industry wide group of experts representing various companies and interests Regular EIA IBIS Open Forum meetings were held to accomplish this task See www eia org ibis for the complete backup of slides and meeting notes for the latest IBIS open forum gize Labels Routing Routing startegy Metal 123 y i Add Vertical bus E IO Floorplan Free placement Fixed Os IBIS Load lw Limitrow width ta bonn ym Fig 10 6 Controlling the I O pin assignment by an IBIS description file Microwind2 uses IBIS to pilot the generation of the I O pads when compiling a Verilog file Click the button Load in front of the check box Fixed I Os in the Verilog menu The default IBIS file is default IBS The following screen appears 89 18 05 02 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing 7s Import ibis file default ibs IBIS Input File i Floorplarr LIBIS wer ik ee BENCHON I File name default ibs ii L I File Few 03 722 702 0322 70 Microwindz This file describes the IBIS Pin number 22 t
50. ent is flowing Vdd Vdd Control gate poly2 Charged Floating gate ERES poly Discharged Floating gate poly a Discharged gate low Vt small current b Charged gate high Vt no current Fig 7 24 Read operation with a double poly MOS device 70 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells 8 Analog Cells 8 1 Diode connected MOS The schematic diagram of the diode connected MOS is proposed in figure 8 1 The question rises is this device a capacitance a diode or a resistance The answer is a capacitance for Vk Vt a diode with an interesting high resistance when Vk Vt where Vt is the threshold voltage of the device The main application of this circuit 1s the design of a big resistance in a very small silicon area Source vk drain qate nmus Source Figure 8 1 MOS connected as a diode uy ES Figure 8 2 Layout and simulation of the MOS connected as a diode O In the palette click the icon MOS generator O Enter a large length and a small width For example enter W 0 5um L 5um This sizing corresponds to a long and narrow channel featuring a very high resistance channel with poor current performances 71 18 05 02 8 2 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells Add a poly metal contact and connect the gate to one diffusion Add a clock on that node Add a VSS property to the other diffusion O Click Simulation on Layou
51. erfacing The input output pad contains one input stage with a polysilicon resistor and two protection diodes The output stage contains a chain of inverters The last stage is a 3 state inverter so that the buffer can be turned off Data Out eee rererererererererererecercrerece nece c o o ke f JHBZEGUHHIIHHHIHHHDHHIBEHIBDEHIH E T t Input Resistor E Fig 10 4 Design of an input output pad PAD MSK ESD Protections The input pad includes some voltage boosting and under voltage protections linked with problems of electrostatic discharge ESD Such protections are required as the oxide of the gate connected to the input could be destroyed by over voltage One of the most simple ESD protection 1s made up of a set of two diodes and a resistance Fig 10 5 One diode handles the negative voltage flowing inside the circuit N P substrate the other diode P N well handles the positive voltage ESD protection Resistance To internal logic Fig 10 5 Diodes for electrostatic discharge protection 88 18 05 02 10 6 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing I O Pad description using Ibis IBIS is a standard for electronic behavioral specifications of integrated circuit input output analog characteristics In order to enable an industry standard method to electronically transport IBIS Modeling Data between semiconductor vendors simulation v
52. f connections that is a large load capacitance An inverter circuit is simulated using different clock fanout and supply conditions The initial configuration is a 1OOMHz clock one output connected to the inverter and a supply voltage 2 5V To investigate the fanout effect on the consumption we simulate first the inverter with one single output In the simulation chronograms we observe that 0 018 mW with a fanout The corresponding file is FANOUT1 SCH Now we add other lights to the output node thus increasing the charge capacitance In the simulation chronograms both the inverter delay and the power consumption have increased 0 059 mW with a fanout of 4 The power consumption linearly increases with the load capacitance This is mainly due to the current needed to charge and discharge that capacitance The corresponding file is FANOUT4 SCH 0 Smsidi LILI 0 0 5 0 10 0 15 0 20 0 25 0 30 0 35 0 40 0 45 0 ns div unu du b n b n n n i b n i a n n d n a CIk100M clock1 0 EREA SRR ERA TETEE eo E RN n fight ce ecc ERA ec RUNS comes PERRA ree RRE sme ID Idd m L L L J L J Laos darnos Lum da A honnn edere gt dee caen 000708 FANOUTI SCH 3 00 L 1 4 NS 4 TEEN en Power dissip 0 018m w Sn en 0 0 50 100 150 200 250 300 350 400 450 hun n b n n n n n b n n n P n E n n n n n b n n n E n CIk100M clock1 Qut2 light Qut3 light2 out4 fl
53. h Build the interconnections and run the Design Rule Checker Assign a clock to CLK and a clock to DATA An example of such an implementation can be found in the file DLatchLevel MSK Its layout an corresponding simulation are illustrated in figure 7 5 EL r de eps E RFE i Ta FUR INN gt a Fa A DR eie F A La FF me ns E ke I a A OO O E gt i E Th Th T dex EEE dm PEE M rs E e rarer ere wm mi ME E Ti Y E OST Re Be ba DE 3635 3 E ETEIE Turis Ex t x z Tig o4 F d sE E cpu Ae y LE ye EF 1 Hl Es ty UE EN ENEE dE ay FE E E EE i hi dee LE SE dE uu EEE EF e T EU o einer AAN EE x dz En 1 RekeRokeR ES drid Er deem z itid Hirt FEL a aat a d bti xL 4 Rh idis hl ay B H d d ElllliE p illlill HHH I eee eee d c Es UH SEHH NS UE E dris A 123 EP CREE A HIRE per dE ded TaT Gi Er Ee OM 1 bel TH IM iint uu SN APRA OT ara E Gaus Ji a E al dum trii AP CACAO I LAA HW a 00 10 20 30 40 50 60 70 80 80ns Fig 7 5 Implementation and simulation of the D Latch File DLatchLevel MSK Edit the schematic diagram called DLATCH SCH using DSCH2 Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file DLATCH txt Click on Compile 57 18 05 02 7 3 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memo
54. he correct polarization a S UT CERE SE TOS zx es Mee CUM ODIN DQO 9 MR eb I sinus ri offset 03V E de 3 pp Linear behavior 1 50 ponini es ee E P ssp 1 L Eo i i P Offset 0 IN A we 2 Valid fap TR A o X voltage range n i enan i T r 3inus i D00 39 040 BD 080 100 120 140 181 180 220 230 240 Figure 8 9 Single Stage amplifier static response We change the sinusoidal input offset and start again the simulation A gain of 5 1s observed as predicted from the static simulation when the offset is 0 8V input 100mV peak to peak output 482mV peak to peak volt Figure 8 10 Single Stage amplifier with high gain 8 5 Simple Differential Amplifier The goal of the differential amplifier is to compare two analog signals and to amplify their difference The differential amplifier formulation is reported below Usually the gain K is high ranging from 10 to 1000 The consequence is that the differential amplifier output saturates very rapidly because of the supply voltage limits Vout K Vp Vm 19 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells Differential Amplifier pMOS current mirror nmos nmos nMOS differential pair Equivalent symbol Vp Vout vm Figure 8 11 Schematic diagram of the differential amplifier The differential amplifier layout is reported in figure 8
55. he timing diagrams of figure 7 2 appear Click on Close to return to the editor LLE 52 i o Fi z eae ee pe ee ee Fig 7 2 Layout of the RS latch made RSNor MSK In the simulation of Figure 7 3 a positive pulse on SET turns Q to a stable high state Notice that when SET goes to 0 Q remains at 1 which is called the memory state When a positive OO 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories pulse occurs on RESET Q goes low nQ goes high In this type of simulation the combination Reset Set 1 is not present 0 0 40 5 0 6 0 1 0 2 0 3 0 Fig 7 3 Simulation of the RSNOR latch RSNor MSK 7 2 D Latch The truth table and schematic diagram of the static D latch also called Static D Flip Flop are shown in Figure 7 4 The data input D is transferred to the output 1f the clock input is at level 1 When the clock returns to level O the latch keeps its last value D Latch NOR D Clock Q nQ 0 l 0 l Fig 7 4 The truth table and schematic diagram of a D Latch File DLATCH SCH 56 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories MANUAL DESIGN Note that the NOR2 AND combination can be implemented in a complex gate style You may find useful to invoke the one line compiler to create successively one inverter nd d and two complex gates which include the AND NOR cells using the syntax Q nQ nd amp h and nQ Q d amp
56. ical Engineering in 1987 both from the University of Toulouse He was granted a Monbusho scholarship and stayed 18 months at the University of Osaka Japan Previously a professor of electronics in the department of physics at the University of Balearic Islands Spain E Sicard is currently an associate professor at the INSA Electronic Engineering School of Toulouse His research interests include several aspects of design of integrated circuits including crosstalk fault tolerance and electromagnetic compatibility of integrated circuits Etienne SICARD is the author of several educational software in the field of microelectronics and sound processing Copyright Copyright 1997 2002 Etienne Sicard Address Etienne Sicard INSA DGEI 135 Av de Rangueil 31077 TOULOUSE Cedex 4 FRANCE Tel 33 561 55 98 42 Fax 33 561 55 98 00 e mail etienne sicard insa tlse fr Web information http intrage insa tlse fr etienne 2 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction Table of Contents MEE LOT amp Insiallati oh risa 6 INSTALA LION pai DIM tM EM C MM UEM MU I Inu fU 7 2 Technoloey Scale DI OWI aea et eon a otn shi d Sado ets o fie oe recu sS 8 2 41 Evolution oF Microprocessors and Memories 3 5 9 1 A A Remedies 8 2 2 Frequency Improvement ida 9 29 METE ASC Ay CUS saben E pm 10 3 The MOSUVO inei alado Il SNNT USES WU ii 11 OIC Similation OF tne MO Sisa a AS A coda estende 12 2 MOS AO ta tt 12
57. ient of short channel effect on threshold 2 2 2 2 voltage 1 DVTI Second coefficient of short channel effect on Vth 0 53 0 53 ETAO Drain induced barrier lowering coefficient 0 08 NFACTOR Sub threshold turn on swing factor Controls the exponential increase of current with Vgs Low field mobility 0 060 m2 Vs 0 025 m2 Vs UA Coefficient of first order mobility degradation due to 11 0e 15 m V 11 0e 15 m V vertical field Coefficient of mobility degradation due to body bias 0 04650e 15 0 04650e 15 V 1 effect V VSAT 8 0e4 m s 8 004 m s 1 22 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter WINT Channel width offset parameter 0 01 6um 0 01 6um Channel length offset parameter 0 01 6um 0 01 64m reduction reduction KTI Temperature coefficient of the threshold voltage 01V 0V 15 vor offer voltage in subthreshold region 00V 99 3 12 Low leakage MOS A new kind of MOS device has been introduced in deep submicron technologies starting the 0 18um CMOS process generation The new MOS called low leakage or High Vt MOS device is available as well as the normal one recalled high speed MOS The main objective is to reduce significantly the loff current that is the small current that flows from between drain and source with a gate voltage 0 Supposed to be no current in first order approximation On the figure below the low leakage MOS device right side has an Ioff current red
58. ified 4 lambda ere Click Compile The result is reported above a i ul E 7 The compiler has fixed the position of VDD power supply at Si and the ground VSS The texts A B and S have also been M E ou fixed to the layout Default clocks are assigned to inputs A n ae dal OOO and B T7071 E TII Fig 5 3 A NAND cell created by the CMOS compiler The 2D process viewer is a useful tool to display the two nMOS in series and the two pMOS in parallel Select the corresponding icon and draw an horizontal line in the layout in the middle of the nMOS channels The figure below appears In fig 5 4 the output 1s connected to the VSS supply only if A 1 and B 1 E i H E EN gt Fig 5 4 The nMOS devices in serial in the NAND gate 38 18 05 02 9 2 9 3 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates The cell architecture has been optimized for easy supply and input output routing The supply bars have the property to connect naturally to the neighboring cells so that specific effort for supply routing is not required The input output nodes are routed on the top and the bottom of the active parts with a regular spacing to ease automatic channel routing between cells The AND gate As can be seen in the schematic diagram and in the compiled results the AND gate is the sum of a NAND2 gate and an inverter The layout ready to simulate can be found in the file AND2 MSK In CMOS the negative
59. ight3 Out light4 FANOUTA SCH Fig 4 5 Power consumption increase with the fanout Fanoutl SCH and Fanout4 SCH 32 18 05 02 4 4 MICROWIND amp DSCH USER S MANUAL 4 The Inverter In summary three factors contribute to the power consumption the load capacitance C the supply voltage VDD and the clock frequency f For a CMOS inverter this relation is represented by the equation below The equation remains valid for more complex gates although some extra considerations have to be taken into account pou VYDD E Where k technological factor close from 1 C Output load capacitance Farad VDD supply voltage V f Clock frequency Hz MANUAL LAYOUT OF THE INVERTER In this paragraph the procedure to create manually the layout of a CMOS inverter is described Click the icon MOS generator on the palette The following window appears The proposes size is 1 25um for the width 0 25um for the length Simply click Generate Device and click on the middle of the screen to fix the MOS device Click again the icon MOS generator on the palette Change the type of device by a tick on p chamnel and click Generate Device Click on the top of the nMOS to fix the pMOS device The result is displayed in figure 3 7 5 Layout Generator Pads Inductor Contacts Bus MOS Path Logo Mas Parameters width MOS fi 250 ium L source Length MOS 0 250 prm Nhrot Gates Add metal to drai
60. isation thme 0 heme thm2 hem2 thm3 hem3 thm4 hem4 thms hem5 thm6 hemo thpass hepass thnit 0 6 henit 8 4 al OY OC O10 i OwWON op JO ann ABPNA N ON ON OI P2 Oo Ol Resistances Copper Unit is ohm squafe repo 4 rep2 4 reme 0 06 rem2 0 06 rem3 0 06 rem4 0 06 rem 0 05 remo 0 05 x Resistances vias unit is ohm vria reco 20 revi 2 rev2 2 rev3 2 rev4 1 rev5 1 Parasitic capacitances cpoOxyde 4600 Surface capacitance Poly Thin oxyde aF yum2 107 13 Design Rules File for 0 12um cpobody 400 No lineic capa cp2body 400 cmebody upper and lower capa emZ body 550 to metal grid i e 2 Cg cm3body 550 cm4body 550 cmSbody 450 cm6body 450 cgsn 500 Gate source capa of nMOS cgsp 500 550 Strong value due to cmelineic cm2lineic cm3lineic cm4lineic cm5lineic oO OO Co CO cmolineic Vertical crosstalk cmepoly 60 cm2me 50 cm3m2 50 cm4m3 50 cm5m4 50 cmom5 50 Lateral Crosstalk cmextk 70 Lineic capacitance for crosstalk coupling in aF um cm2xtk 100 C is computed using Cx cmextk 1 spacing cm3xtk 100 cm4xtk 100 cm5xtk 100 cmoxtk 100 Junction capacitances cdnpwell 350 n psub cdpnwell 300 p nwell cnwell 250 nwell psub cpwell 100 pwell nsub cldn 100 Lineic capacitance N P aF
61. l2 over via2 2 r805 Extra metal3 over via2 2 11 11 Metal3 amp Via3 Design Rules 1901 Metal3 width 4 A 1902 Between two metal3 4 1910 Minimum surface 32 7 95 11 Design Rules r501 gt metal r502 metal r604 Zo 1j r602 via Stacked via over gt lt contact r601 when r603 is O r603 contact r804 Zo r802 F via2 r901 metal 3 18 05 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules ra01 Via3 width 2 A ra04 ra02 Between two Via3 5 A T ra04 Extra metal3 over via3 2 A Ss ra05 Extra metal4 over via3 2 S via3 Meal raOl 11 12 Metal4 8 Via4 Design Rules rb01 Metal4 width 4 rb02 Between two metal4 4 A rb10 Minimum surface 32 7 rc01 Via4 width 2 rc02 Between two Via4 5 rc04 Extra metal4 over via2 3 A rc05 Extra metal5 over via2 3 A 11 13Metal5 amp Via5 Design Rules rd01 Metal5 width 8 A rd02 Between two metal5 8 rd10 Minimum surface 100 A re01 Via5 width 4 re02 Between two Via5 6 re04 Extra metal5 over via5 3 A re05 Extra metal6 over via5 3 A M etal 5 6 11 14 Metal6 Design Rules rf0l Metal6 width 8 A rf02 Between two metal6 15 eta rf10 Minimum surface 300 24 dius 96 18 05 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 15 Pad Design Rules rpOl Pad width 100 um rp02 Between two pads 100 um rp03 Opening in passivation v s via 5um E rp04 Opening in
62. layout is shown in Figure 8 14 The output stage 1s not strong enough to be able to drive large loads such as output pads 18 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells 8 6 Voltage Controlled Oscillator The voltage controlled oscillator is able to produce a square wave with a frequency varying depending on an analog control Vc Ideally the frequency dependence with Vc should be linear One example of voltage controlled oscillator is given in figure 8 16 It consists of a ring oscillator with three stages Vc acts on the resistance of the supply path which acts on the speed response of the inverters rill zs a as I Voltage Ctr Osc C Fig 8 16 Schematic diagram of a voltage controlled oscillator Voltage Contraled Oscillator EPA TT PT Ana ur pa p m d MIC ui iw L vt HE at ol E E LENT Eten rp oap a 1 a LERLE i PR ES 3 gt l HH i VANS Ca a Ca Ca Ca Ca Ca a et at a UP at at a Ca Ca aat na aat na Hel aat na mr aan TEE L3 Ji an L3 m m HE H3 ES BRL IEEE IST E Ere Roues bese an E eS Ul Fig 8 17 Implementation of a voltage controlled oscillator based on a 5 stage ring oscillator 19 18 05 02 EA I m 8 Analog Cells ee ee E SAS LU i I i HEP TT RED IEA i Lu i 7 03 6 27 CEST a os ete E uio 7 en oe E AI 4 E ag wo em tote
63. level the MOS is considered as a simple switch Moreover the logic switch is unidirectional meaning that the logic signal always flows from the source to the drain This major restriction has no physical background In reality the current may flow both ways The reason why the logic MOS device enables the signal to propagate only from source to drain is purely a software implementation problem In the logic simulator of DSCH2 an arrow indicates whether or not the current flows and its direction Figure 3 2 When the device is OFF the drain keeps its last logic value thus acting as an elementary memory Notice that you cannot pass any logic information from the drain to the source Such a circuit would fail The arrow indicates that the channel is ON Gate gate l l l nmos Ben NE 7 EIS source drain nMOS Out source dran pMOS Out L pmo NS bon bM me ee e Data goes to pMos out keeps its previous value gate Fig 3 2 the logic simulation of the MOS device MosExplain SCH MOS layout We use MICROWIND 2 to draw the MOS layout and simulate its behavior Go to the directory in which the software has been copied By default MICROWIND2 Double click on the MicroWind2 icon The MICROWIND2 display window includes four main windows the main menu the layout display window the icon menu and the layer palette The layout window features a grid scaled in lambda A units The lambda unit is fix
64. licon Lig ial b Be el BE Liu Er BEI Bi Sod UR Soe E nE afi laf A gt Be BE Gelb et ETS TE NES En AA RUE EE pui pui HE Bun ZEN e 1t E te ET EP a Lig lid JE al lLla anheg MEN D EE SH dep peH BEN dd ERE B ease ease ease ese REESE IN Esa EL a E rab rab rab rab E ETE Me CATER E a te M Ema 3 aei GH wH RN T E n a etarra d RE TE nae UE D EE Sae U D EEE See o cp pepe cp pepe EE Bas CARE ee noes OR STO PRI TE UE m H heal fea pui p E EEE p E H vel fas LL Ea kaj PA da dila tia ila 1L Lin ia ra imj mj imj i m an A EE EEI SEn PIM E ERU EIA eee E ES EE a Rao EE eS A Ta B E al TE del Jia ll dol JE lal Ea een ER TEER i8 Jl RJE NM br erm PONES RN Hai B E HET o HEE SERE RG PEE A l E iol Ein ls E Lin Ein im AAA x WE AT TEA TARTA pyra Ke Rt RH Rit gH S gii dl Ka Fa El aL ll Fm Fm m ml m 83 m 801 a p p p E E Embedded DRAM array 8x8 Same with folded cells 8x8 Large diffusion DRAM array 8x8 Fig 7 21 Impact of embedded capacitor on silicon area on a 8x8 array 68 18 05 02 7 10 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories EEPROM The EEPROM memory includes 2 poly gates with the bottom polysilicon floating isolated by oxide Figure 7 22 The programming of a double poly transistor involves the transfer of electrons from the source to the floating gate through the thin oxide
65. ly Then the comparator multiplier and the arithmetic and logic unit are also discussed This chapter also includes details on a student project concerning the design of binary to decimal addition and display Half Adder Gate The Half Adder gate truth table and schematic diagram are shown in Figure 6 1 The SUM function is made with an XOR gate the Carry function is a simple AND gate HALF ADDER A B SUM CARRY 0 0 0 0 0 1 1 0 1 0 1 0 1 1 0 1 Fig 6 1 Truth table and schematic diagram of the half adder gate HADD MSK FULL CUSTOM You may create the layout of the half adder fully by hand in order to create a compact design Use the polysilicon and metall layers for short connections only because of the high resistance of these materials Use Poly Metal Diff Metal contact macros situated in the upper part of the Palette menu to link the layers together LAYOUT Load the layout design of the Half Adder through the File gt Open and LIBRARY HADD MSK sequence 45 18 05 02 6 2 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics VERILOG COMPILING Use DSCH2 to create the schematic diagram of the half adder Verify the circuit with buttons and lamps Save the design under the name hadd sch using the command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file hadd txt
66. ly rataa mal a la y y MEM x g 8g simulate an integrated circuit at physical description level 5 lambda The package contains a library of common logic and analog 0 500um ICs to view and simulate MICROWIND2 includes all the Options iv Meta amp EJ Metal 5 Bj commands for a mask editor as well as original tools never LEELEE gathered before in a single module 2D and 3D process view Metal2 iv Metal 1 HEIN Contact Local Interc Polysiionum m Ie 2 bi biffusion Xi N Diffusion Il v N Well mil VERILOG compiler tutorial on MOS devices You can gain ERA FEE Whit M ES 6s AAN P ES DR CRPEPTLEER deve PS Bes UTSBSSRIIIIIIIII FE 1 1 ti access to Circuit Simulation by pressing one single key The xi E ELELE ti EAD Re al 6 PATRE DP eT E 1 Sees VS ss Og tn MALAS L d n electric extraction of your circuit is automatically performed Redraw Cmicrowind2Wanual miw2 invS MSK 105 boxes and the analog simulator produces voltage and current curves immediately The chapters of this manual have been summarized below Chapter 2 describes the technology scale down and the major improvements given by deep sub micron technologies Chapter 3 is dedicated to the presentation of the single MOS device with details on the device modeling simulation at logic and layout levels Chapter 4 presents the CMOS Inverter the 2D and 3D views the comparative design in mic
67. mbol exists It includes the nMOS pMOS and inverter cells Concerning the layout the channel length is usually the minimum length available in the technology and the width is set large in order to reduce the parasitic on resistance of the gate 5 7 4to 1 Multiplexer The multiplexer is a very useful function and has a multitude of application The selection of a particular input line is controlled by a set of selection lines Normally there are 2 input lines and n selection lines whose bit combinations determine which input is selected Figure 5 14 shows the transmission gate implementation of the 4 to 1 multiplexer In the configuration S1 1 S2 0 the input C is connected to the output E gt O 51 e Li H m Fig 5 14 4 to I multiplexing based on transmission gates Mux4tol sch 5 8 Keyboard multiplexor Figure 5 15 gives an example of 2 multiplexed hexadecimal keyboards sharing the same hexadecimal display using transmission gates We use a clock to generate an alternative selection of the keyboard information E HER EIU E e NC s B HIE BIS M d Fig 5 15 Keyboard multiplexing based on transmission gates Mux2Kbd sch 44 18 05 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics 6 Arithmetics 6 1 This chapter introduces basic concepts concerning the design of arithmetic gates The adder circuit is presented with its corresponding layout created manually and automatical
68. ment in speed thanks to deep submicron technology HOW TO SIMULATE D Start Microwind2 By default the software is configured with 0 25um technology Click File gt Open Select INV3 Click Simulate gt Start Simulation The oscillation figure 2 5 appears Click Close Click File gt Select Foundry Click cmos08 rul Run again the simulation Observe the change of VDD and the slow down of the oscillating frequency 9 18 05 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 3 Increased Layers The table below lists a set of key parameters and their evolution with the technology Worth of interest is the increased number of metal interconnects the reduction of the power supply VDD and the reduction of the gate oxide down to atomic scale values Notice also the slow decrease of the threshold voltage of the MOS device and the increasing number of input output pads available on a single die Lithography Year Metal Oxide Threshold Input output Microwind2 rule layers dest V mu voltage V pads file 12m 1986 2 50 08 250 Cmosi2rall Omm 198 2 so 20 07 350 Cmos08rall Osum mo s 33 rm fos foo Cmo06mi 025um 196 6 25 6 Joss i000 Cm s025 rul OI8um 198 6 20 S 040 1590 Cmos0i8rul_ O 10um 20 8 10 3 X 020 290 Cmos010 rul
69. n and source rOntians ae fa L ij le EA par A C n channel e stapa Pida enibvonturn A E Aa lesa p Channetb piunt ET Le al ea pac ee t Sia adr Wt tj B r In lambda Se Generate Device x Cancel Fig 4 6 nMOS and pMOS devices placed on the layout 33 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 4 lambda Lp L A D 625um UB EN HET THE eae VDD supply ERTS SEP UU D c ka PMOS device Poly Gate s NMOS device LLL Ap LL Fig 4 7 The circuit Inverter compiled into layout 4 5 Analog simulation of the INVERTER Click Simulate gt Start Simulation or the icon above The simulation of the circuit is performed You may verify the correct behavior of the inverter cell Fig 4 8 The analog simulation of the circuit Inverter MSK using Microwind2 34 18 05 02 4 6 4 7 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 2D View of the Process The Process Simulator shows the vertical aspect of the layout as when fabrication has been completed This feature 1s a significant aid to understand the fabrication principles A click of the mouse at the first point and the release of the mouse at the second point give the cross section NMOS gate Polysilicon Thick oxide S102 40 Drain N diffusion i Insulator oxides S102 Source N diffusion YP substrate Fig 4 9 The 2D process se
70. n two MOS devices as presented in figure 8 5 A current I1 flowing through the nMOS device Master is copied to the MOS device Slave If the size of Master and Slave are identical in most operating conditions the currents are the same The remarkable point is that the current is almost independent of the drain voltage of the slave V2 If the ration W L of the Slave is 10 times the ratio of the Master the current on the right branch is 10 times the current on the left branch V2 l i2 V I1 mos i prgos nms Argos Master Slave jJ 1 2 Dp Figure 8 5 Current mirror principles in nMOS and pMOS versions The illustration of the current mirror behavior is performed on the layout of figure 8 6 The circuit includes a voltage reference using N1 and P1 as described above a device N2 which has an identical size as N1 and a device N3 with L 0 5um leading to a ratio equal to 10 W L of NI What we expect is a current I2 equal to I1 in most operating conditions and a current I3 10xI1 W 0 50 L 5u 5u L 5u I 5u L 0 5u M27 Figure 6 6 Illustration of the current mirror principles Mirror MSK 13 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells You may observe each MOS characteristics by using the command Simulate Simulate on Layout During the transient simulation the functional point of the select MOS device appears in the characteristics which provides a valuable aid to understand the current mirror behavior
71. name used in CMOS025 RUL CMOS 0 25um Surface capacitance refers to the body Vertical crosstalk capacitance refer to inter layer coupling capacitance while lateral crosstalk capacitance refer to adjacent interconnects 98 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules Inter layer Frindging Surface capacitance To body Adjacent layers SUBSTRATE BODY Figure 12 2 Capacitances 12 3 Surface Capacitance aF um aF um capacitance CpoBody Polysilicon to substrate n c demi FO m CM4Body Metaldonbody 30 J6 CMSBody Metal5 on body CM6Body Metal6 on body 12 4 Interlayer Capacitance 12 5 Crosstalk Capacitance NAME DESCRIPTION VALUE aF um Metal to metal at 4A distance 4A width CM2M2 Metal to metal 2 99 18 05 02 MICROWIND amp DSCH USER S MANUAL 12 Electrical Rules s The crosstalk capacitance value per unit length is H H Metal 3 given in the design rule file for a predefined interconnect width w 4A and spacing d 4A CM2M2 nm H In Microwind2 The computed crosstalk capacitance 1s not CMeMe dependant on the interconnect width w H H Meral The computed crosstalk capacitance value is COM proportional to 1 d where d is the distance between SUBSTRATE BODY 12 6 Resistance NAME DESCRIPTION VALUE Resistance per square for polysilicon Resistance per square for polysilicon2 0 05 12 7 Vertical
72. nces in terms of spacing and speed than conventional logic circuits To illustrate the concept of complex gates let us take the example of the following Boolean equation F A B C The logic circuit corresponding to this equation 1s reported below The circuit 1s built using a 2 input NOR and a 2 input AND cell that is 10 transistors and three delay stages F AHB 10 transistors Fig 5 10 The conventional schematic diagram of the function F A B C A much more compact exists in this case Figure 5 11 consisting in the following steps 1 For the nMOS network translate the AND operator into nMOS in series and the OR operator in nMOS in parallel 2 For the pMOS network translate the AND operator into pMOS in parallel and the OR operator in pMOS in series 3 If the function is non inverting as for F A B C an inverter is mandatory pmos 0 25um 2 A pmas 0 25um 2 um pinos a 2Ssum 2 Cum a 7 F rimo nmos 0 25um 0 75 ic 25um Sum imas 0 25uMm 0 Sum F i 4 8 0 6 transistors 1 stage Fig 5 11 The complex gate implementation of the function F A B C 42 18 05 02 9 6 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates Microwind2 is able to generate the CMOS layout corresponding to any description based on the operators AND and OR using the command Compile gt Compile one line Using the keyboard enter the cell
73. o control the Hicrovind Copyright Etienne SICARD Component BENCHO1 Manuftacturer INSA power 551 gnd Clk E lo ini nand2 aut 4 VDDi power nore nut 5 V5OSl gnd uu le Elk ini i VOD Power 7 D ini jl 8 nand outi El w Back to Verilog file compiler Fig 10 6 The IBIS description file loaded for controlling the pin assignment It can be seen that IBIS is a text file with a simple structure based on keywords We only use a very reduced set of the available keywords IBIS Ver Specifies the IBIS template version This keyword informs electronic parsers of the kinds of data types that are present in the file Tracks the revision level of a particular ibs file Revision level is set at the discretion of the engineer defining the file Marks the beginning of the IBIS description of the integrated circuit named after the keyword Manufacturer Specifies the manufacturer s name of the component Each manufacturer must use a consistent name 1n all ibs files Package Defines a range of values for the default packaging resistance inductance and capacitance of the component pins Sub Parameters are named R_pkg L_pkg C_pkg Pin Associates the component s I O models to its various external pin names and signal names Each line must contain either three or six columns A pin line with three columns only associates the pin s signal and model Six columns can be used to override
74. of the clock 99 18 05 02 7 Latches and Memories MICROWIND amp DSCH USER S MANUAL 7 17 r cc Ds sse Fig 7 8 Simulation of the DREG cell DREG MSK 18 05 02 60 7 4 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories Counter The one bit counter is able to produce a signal featuring half the frequency of a clock The most simple implementation consists of a D flip flop where the output nQ is connected to D as shown in figure 7 9 In the logic simulation shown in figure 7 9 the clock Clock1 changes the state of Clock_Div_2 at each fall edge The RESET is active high and stuck the output to 0 Clock_Div_2 1H clock Clock1 Fig 7 9 Schematic diagram of the 2 bit counter DivFreq MSK UTZ ILELLL LLL LD n LIH NU ili E Due Bernd le halal FIFE Hi il ali EE x la il fork A a PPP PPLE LL CTS ZAR LLL ELLE LLL ZE RE ZZZ ER ZZZ AN A fy 4 Fag ZZZZIZZZZZZZIZIZIZZTZIZIZIZITTA ABV OZ ZZ LLL LLL LLL 2 ZZZARZZ ZAS Ea pa a 77777777 Clock 0 701ns 0 701ns 1 0 698ns 0 700ns 0 700n 1428GHz 1428GHZ 1431GHZ 1 428GHZ 1 4286 Fig 7 10 Layout and analog simulation of the divider by two ClockDiv2 MSK 61 18 05 02 7 5 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RAM Memory The schematic diagram of the static memory cell used in High Capacity Static RAMs is given in figure 7 11 The circuit consists of 2 cross coupled inverters and two n
75. ons and lamps Save the design under the name RS sch using the command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File gt Select the text file 54 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RS txt Click on Compile When the compiling is complete the resulting layout appears as shown below The NOR implementation of the RS gate is completed module RSNor Reset Set Q nQ input Reset Set Suk put Ono nor norl Q nQ Reset nor Hor noraa endmodule With the Reset and Set signals behaving like clocks the memory effect is not easy to illustrate A much better approach consists in declaring pulse signals with an active pulse on RESET followed by an active pulse on SET Consequently you must change the CLOCK property into a PULSE property For NOR implementation the pulse is positive 1 Select the PULSE icon Click on the RESET node 2 Click the brush to clear the existing pulse properties of the pulse 3 Enter the desired sequence for example 01000 An click INSERT A piece wise linear sequence is generated in the table describing the 01000 waveform in an analog way 4 Repeat the same procedure to change the clock into a pulse for node SET This time the sequence must be 000100 to delay the pulse 5 Click on Simulate gt Start Simulation T
76. pm cldp 100 Idem for P N SOMOS ek tit Eon MOS1 low leakage MOS2 high speed MOS3 high voltage Nmos Model 3 parameters NMOS l3vto 0 4 1300 0 06 LSCOX 26 9 l3vmax 170e3 l3gamma 0 4 l3theta 0 3 l3kappa 0 06 13phi 0 2 18 05 02 DSCH amp MICROWIND USER S MANUAL 131d 8e 9 l3nss 0 06 high speed l3v2to 0 3 l3u2 0 06 l3t20x 3e 9 high voltage 13v3to 0 7 l3u3 0 06 13t30x 7e 9 PMOS Model 9 PMOS 13vto 0 4 13u9 0 02 13tox 3e 9 l3vmax 120e3 l3gamma 0 4 l3theta 0 3 l3kappa 0 06 l3phi 0 2 131d 8e 9 l3nss 0 06 o high speed l3v2to 0 3 l3u2 0 02 13t20x 3e 9 high voltage l3v3to 0 7 jo 0 02 13t30x 7e 9 BSIM4 parameters Nmos NMOS b4vtho 0 4 b4k1 0 45 b4k2 0 1 b4xj 1 7e 7 b4toxe 3 5e 9 b4ndep 1 8e17 b4d0vt 2 3 b4dlvt 0 54 b4vfb 0 9 b4u0 0 068 b4ua le 15 b4uc 0 047e 15 b4vsat 100e3 b4pscbel 230e6 b4ute 1 8 b4ktl 0 1 b4lint 0 01e 6 b4wint 0 02e 6 b4xj 1 5e 7 b4ndep 1 7e17 b4pclm 1 1 high speed b4v2to 0 3 108 13 Design Rules File for 0 12um b4t2ox 3e 9 high voltage b4v3to 0 7 b4t30x 7e 9 Pmos BSIM4 PMOS b4vtho 0 4 b4k1 0 45 b4k2 0 1 b4xj 1 7e 7 b4toxe 3 5e 9 b4ndep 1 8el7 b4d0vt 2 3 b4divt 0 54 b4vfb 0 9 b4u0 0 028
77. r high voltage MOS 4 A r304 Between two polysilicon boxes 3 A r305 Polysilicon vs other diffusion 2 r306 Diffusion after polysilicon 4 A r307 Extra gate after polysilicium 3 A 1310 Minimum surface 8 A r301 H igh voltage MOS 93 18 05 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 6 2 Polysilicon Design Rules 1311 Polysilicon2 width 2 A r311 1312 Polysilicon2 gate on diffusion 2 A Poly2 r312 11 7 Option Design Rules rOpt Border of option layer over diff N and diff P 11 8 Contact Design Rules r401 Contact width 2 A a r402 Between two contacts 5 ion r403 Extra diffusion over contact 2 A MA r404 Extra poly over contact 2 A i r405 Extra metal over contact 2 r406 Distance between contact and poly gate 3 r405 e 7 ti hr diffusio metal gate 94 18 05 02 MICROWIND amp DSCH USER S MANUAL 11 9 Metal amp Via Design Rules r501 Metal width 4 2 r502 Between two metals 4 r510 Minimum surface 32 7 r601 Via width 2 A r602 Between two Via 5 A r603 Between Via and contact 0 r604 Extra metal over via 2 r605 Extra metal2 over via 2 When r603 0 stacked via over contact is allowed 11 10 Metal2 amp Via2 Design Rules r701 Metal width 4 r702 Between two metal2 4 r710 Minimum surface 32 7 r801 Via2 width 2 r802 Between two Via2 5 r804 Extra meta
78. real switch where the signal can flow both ways Use the Verilog compiler to generate the edge trigged latch using the following text dreg txt or by creating a schematic diagram including the D register symbol in the symbol palette of DSCH2 As can be seen the register is built up from one single call to the primitive dreg For simulation 98 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories RESET is active on a level 1 RESET 1s activated twice at the beginning and later using a piece wise linear description included in the pulse property CLK is a clock with 10ns at O and 10ns at 1 JD is the data chosen here not synchronized with CLK in order to observe various behaviors of the register To compile the DREG file use the command Compile Compile Verilog Text The corresponding layout is reported below The piece wise linear data is transferred to the text rst automatically Ec te Um E SERE HERY a izi gt l col roe rum m EMI 4 VITIUM IIIA AZZZZZZZZHA Fig 7 7 Compiled version of the Edge trigged D Flip Flop The simulation of the edge trigged latch 1s reported in figure 7 8 The signals Q and nQ always act in opposite When RESET is asserted the output Q is 0 nQ is 1 When RESET is not active Q takes the value of D at a fall edge of the clock For all other cases Q and nQ remain in memory state The latch is thus sensitive to the fall edge
79. resistance symbol is inserted in the layout to indicate to the simulator that an equivalent resistance must be taken into account for the analog simulation Open loop amplifiers are used as voltage comparators The comparisons address the decoding logic situated to the right and that provides correct AO and Al coding Analog Input Vin C Vimd2sV fo Vin gt 3 75 Poly resistor Fig 9 1 Node description and schematic diagram of the analog digital converter ADC MSK 81 18 05 02 MICROWIND amp DSCH USER S MANUAL 9 Converters Lal d A ETT TUNI EB a O da AI ARES RES EE eet diaz E E EB HE Ed FE EY EI r1 ae R x HE E 3 EE E T1 qe to LE eB d ul EET ERU eire Lum B re m F n B o Dh HIE pan coe PM S SEI aE E E FEl arn rea E Sab EEE Fig 9 3 Simulation of the analog digital converter ADC MSK In the simulation shown in Figure 9 3 the comparators CO and C1 work well but the comparator C2 is used in the upper limit of the voltage input range The generation of combinations 00 01 and 10 is correct 82 18 05 02 MICROWIND amp DSCH USER S MANUAL 9 Converters Digital Analog Converter The digital analog converter converts a digital three bit input AO A1 A2 into an analog value Vout The polysilicon resistive net gives intermediate voltage references which flow to the output via a transmission gate net The resistance symbol is inserted in the layout to indicate to
80. ries Edge Trigged Latch The most common example of an edge trigged flip flop is the JK latch Anyhow the JK is rarely used a more simple version that features the same function with one single input D 1s preferred This simple type of edge trigged latch is one of the most widely used cells in microelectronics circuit design The cell structure comprises two master slave basic memory stages The most compact implementation of the edge trigged latch 1s reported below The schematic diagram is based on inverters and pass transistors On the left side the two chained inverter are in memory state when the pMOS pass transistor P1 is on that is when CLK 0 The two chained inverters on the right side act in an opposite way The reset function is obtained by a direct ground connection of the master and slave memories using nMOS devices The logic siganl flows from source to drain Chess tpe e td one A a D source drain mynot inat mynot outsource drain mynot out mynot out a nms Lomos P Ou L 0 25u tj gate drain source gate drain source mos Inmos drain O drain source source O nmos nmos reset gate gate gate E gate ck LC Figure 7 6 The edge trigged latch and its logic simulation Dreg MSK Notice that the logic model of the MOS device is not working the same way as for the real MOS switch In the case of the logic implementation the logic signal flows only from the source to the drain This is not the case of the
81. ron and deep submicron technologies Chapter 5 concerns the basic logic gates AND OR XOR complex gates Chapter 6 the arithmetic functions Adder comparator multiplier ALU The latches and memories are detailed in Chapter 7 6 18 05 02 MICROWIND amp DSCH USER S MANUAL 1 Introduction As for Chapter 8 analog cells are presented including voltage references current mirrors operational amplifiers and phase lock loops Chapter 9 concerns analog to digital and digital to analog converter principles The input output interfacing principles are illustrated in Chapter 10 The detailed explanation of the design rules is in Chapter 11 Electrical rules are described in chapter 12 The program operation and the details of all commands are given in the help files of the programs INSTALLATION From The web From The CD ROM Connect to page http intrage insa Double click index html tlse fr etienne Click Introduction to microelectronics Click Download MICROWIND2 ZIP file In your PC create manually a directory Suggested c program files microwind2 Store the mw ZIP file in this directory Extract all files with WinZIP in c program files microwind2 Test double click MICROWIND2 EXE Click File gt Load select CMOS msk Click Simulate Click Download DSCH2 ZIP file In your PC create manually a directory Suggested c program files dsch2 Store the dsch2 ZIP file in this directory Extrac
82. s proposed in Figure 6 5 Notice that the carry propagates vertically within the cell to ease multiple addition The typical delay is less than 100ps in 0 25um technology module fulladd sum carry a b c LHput a cs output sum carry wire suml xor xorl suml a D xor xorz sum suml cG and and el a b and and2 c2 b c and and3 c3 a c ar orl carry cl c2 03 3 endmodule Alternatively you may use DSCH2 to create the schematic diagram of the full adder and compile it directly into layout Verify the circuit with buttons and lamps Save the deign under the name fadd sch using the 48 18 05 02 MICROWIND amp DSCH USER S MANUAL 6 Arithmetics command File gt Save As Generate the Verilog text by using the command File gt Make Verilog File In Microwind2 click on the command Compile gt Compile Verilog File Select the text file fadd txt Click on Compile When the compiling is complete the resulting layout appears shown below The XOR gate is routed on the left and the AND gate is routed on the right Click on Simulate gt Start Simulation The timing diagrams appear Figure J A e Fig 6 5 Simulation of a full adder File FADD MSK 6 5 Four Bit Adder The four bit adder circuit includes adders in serial to perform the arithmetic addition The result of each stage propagates to the next one from the top to the bottom The circuit allows a four bit addition between two numbers A3 A2 A1 A0
83. specific foundry as the default foundry click Files gt Properties Set as Default Technology Start Microwind with a specific design Rule File To start Microwind with a specific design rule file click with the right button of the mouse on the Microwind icon select the Properties item then the target The default target may be C microwind2 Microwind2 exe The command line may include two more parameters The First parameter is the default mask file loaded at initialization The Second parameter is the design rule file loaded at initialization The following command executes MICROWIND2 with a default mask file test MSK gt and the rule file cmos018 RUL C microwind2 Microwind2 exe test cmos018 rul Nwell Design Rules rl101 Minimum well size 12 r102 Between wells 12 r110 Minimum surface 144 X p substrate 92 18 05 02 MICROWIND amp DSCH USER S MANUAL 11 Design Rules 11 4 Diffusion Design Rules 1201 Minimum N and P diffusion width 4 A ies polarization r205 1202 Between two P and N diffusions 4 1203 Extra nwell after P diffusion 6 A 1204 Between N diffusion and nwell 6 A 1205 Border of well after N polarization 2 A 1206 Distance between Nwell and P polarization 6 1210 Minimum surface 24 27 P polarization 11 5 Polysilicon Design Rules 1301 Polysilicon width 2 1302 Polysilicon gate on diffusion 2 A 1303 Polysilicon gate on diffusion fo
84. sserted To pass logic signals well both a n channel device and a p channel device are used as shown in figure 3 21 The main drawback is the need for two control signals Enable and Enable thus an inverter is usually required en Good 1 1 en bow Transmission gate 0 0 0 Good 0 1 A Fig 3 22 The transmission gate used to pass logic signals escrros Mercere n tettetett vesecolooo RERET 224 ntaQut m T h TIME Fig 3 23 Layout of the transmission gate TGATE MSK 28 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter The layout of the transmission gate is reported in figure 3 23 The n channel MOS is situated on the bottom the p channel MOS on the top Notice that the gate controls are not connected as nEnable is the opposite of Enable The operation of the transmission gate is illustrated in figure 3 24 A sinusoidal wave with a frequency of 2GHz is assigned to Dataln With a zero on Enable And a 1 on nEnable the switch is off and no signal is transferred When Enable is asserted the sinusoidal wave appears nearly identical to the output al a NM A A EE SN 12 80 fed o pt pg T echo gin JN EB ar hy y A A A A A ah oo 05 10 165 20 25 Fig 3 24 Simulation of the transmission gate TGATE MSK 29 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter 4 The Inverter 4 1 This chapter describes the CMOS inverter at logi
85. t In a small window the MOS characteristics are drawn with the functional point drawn as a color dot Figure 7 2 It can be seen that the I V characteristics correspond to a diode The resistance varies with Vk but can be estimated around 30KQ The resistance obtained using such a circuit can reach easily 100KQ in a very small silicon area The same resistance can be drawn in poly but would require a much larger area Voltage Reference The voltage reference is usually derived from a voltage divider made from resistance The main problem is that the value of the resistance must be high to keep the short cut current low to avoid wasted power consumption A key idea is to use MOS devices rather than polysilicon or diffusion resistance to keep silicon area very small HRP ref ref Small W amem large L i Figure 8 3 Voltage reference using PMOS and NMOS devices as large resistance i 1 Vref i 1 I Figure 6 4 Voltage reference of IV Vref MSK 72 18 05 02 8 3 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells In the layout of figure 8 5 the PMOS and NMOS have the same size Due to lower PMOS mobility the resulting Vref is not VDD 2 but 1V You may change the temperature Simulate gt Simulate Options and see how the voltage reference is altered by temperature Current Mirror The current mirror is one of the most useful basic blocs in analog design In its most simple configuration it consists i
86. t all files with WinZIP in c program filesidsch2 Test double click in DSCH2 EXE Load base sch Click Simulate C Program Files Executable EXE Executable EXE Examples MSK FE les SCH Rule files RUL HTML IS pus E IM IR IMS mim P 7 18 05 02 MICROWIND amp DSCH USER S MANUAL 2 Technology Scale Down 2 Technology Scale Down The evolution of integrated circuit IC fabrication techniques is a unique fact in the history of modern industry The improvements in terms of speed density and cost have keep constant for more than 30 years By the end of 2000 System on Chips with about 100 000 000 transistors will be fabricated on a single piece of silicon no larger than 2x2 cm In this chapter we present some information illustrating the technology scale down 2 1 Evolution of Microprocessors and Memories Figure 2 1 describes the evolution of Intel microprocessors figure 2 2 describes the evolution of memory size during the last decades In figure 3 it is shown that industry has started to produce ICs in deep submicron technology starting 1995 Research has always kept around 5 years ahead mass production Nbr of device Memory size bi 1 GIGA 10 GIGA 100 MEG 1 GIGA 10 MEG 100 MEG 1 MEG 10 MEG 100 K 1 MEG 10K 100K 82 85 89 92 95 98 01 04 82 85 89 92 95 98 01 04 Year Year Fig 2 1 Evolution of microprocessors Fig 2 2 Evolution of memories Cnannel um 2 0 _ Deep submi
87. t connect to V In this case a slow ramp is applied on the input V and the result is observed on the output The valid input range 0 5 1 9V is the value of V for which the output copies the same voltage in a reasonable time Wide Range Amplifier The wide range amplifier is built using a voltage comparator and a power output stage Its schematic diagram is reported in Fig 8 13 The difference between V and V is amplified and it produces a result codified Vout The gain near 2 5V is very high more than 100 Use the Voltage vs Voltage simulator mode to get the transfer characteristics Vout V 4 Current Mirror pu Vout Output V V B Vbias HERR V Amplifier Symbol me we i Differential pair Output stage Wide Range Amplifier Fig 58 13 Node description and schematic diagram of the analog amplifier AMPLI2 MSK 77 18 05 02 MICROWIND amp DSCH USER S MANUAL 8 Analog Cells HHRHH HFH e EEN ye EH A ee a r A rra ye O o e E rr e ee ID eee n n n n ET E1 RB EEE EEE E O EE Er T EE EET dg TT nl D ee et Ce kai tt E eE eiai Tro A AA Fig 8 14 Design of the analog amplifier AMPLI2 MSK r Un c I I I I V I eaters out E eset hed Lat 0 0 2 0 40 6 0 8 0 10 0 12 0 14 0 16 0 19 0 ns Fig 8 15 Transient simulation of the analog amplifier AMPLI2 MSK connected as a follower You can easily build a follower by designing an extra connection from Vout to V This
88. tact r404 2 poly border for contact r405 2 diff border for contact r406 3 contact to gate r407 2 poly2 border for contact metal r501 3 metal width r502 4 metal spacing via r601 2 Via width r602 4 Spacing r604 2 border of metal amp metal2 metal 2 r701 3 Metal 2 width r702 4 via 2 r801 2 Via width r802 4 Spacing r804 2 border of metal2 amp metal3 metal 3 r901 3 width r902 4 spacing via 3 ra01l 2 Via width ra02 4 Spacing ra04 2 border of metal3 amp metal4 metal 4 rb01 3 width rb02 4 spacing via 4 EC Od 2 Via width rc02 4 Spacing rc04 2 border of metal4 amp metal 5 metal 5 rag 8 width rd02 8 spacing yie 5 re01 5 Via width re02 5 Spacing re04 2 border of metalb5 amp metalo metal 6 rd01 8 width rd02 15 spacing Pad rules rp01 800 Pad width rp02 800 Pad spacing rp03 40 Border of Vias rp04 40 Border of metals rp05 200 to unrelated active areas Thickness of conductors for process aspect 18 05 02 DSCH amp MICROWIND USER S MANUAL All in pm P epitaxial thepi 1 0 Keep 2 0 Shallow tretch isolation thsti 0 8 hesti 048 POLY thpoly 0 20 hepoly 0 01 Poly2 thp2 0 2 hep2 0 22 Diffusions thdn 0 4 thdp 0 4 thnw 1 0 Metall
89. teral doping effect and AVtpjp _ is the drain induced barrier lowering effect of short channel on Vt Concerning the formulations for mobility of channel carriers he generic parameter 1s UO the mobility of electrons and holes The effective mobility Uey1s reduced due to several effects the bulk polarization and the gate voltage The equation implemented in Microwind2 is the most recent mobility model proposed in BSIM4 reported in 3 xxx UO Nastere t 2 VTHO Vep 9 v TOXE Mor 1 UA UCV o Al where UA is the low field mobility in m V s Its default value is around 0 06 for n channel MOS and 0 025 for p channel MOS UA is the first order mobility degradation coefficient in m V Its default value is around 10 P UC is the body effect coefficient of mobility degradation in m V Its default value is 0 045x10 VFB is the flat band voltage in V TOXE is the oxide thickness in m A typical value for TOXE in 0 12um is 3nm 3 10 m EU is a coefficient equal to 1 67 for n channel MOS and 1 0 for p channel MOS The current Ids is computed using one single equation as described below Weff Ids0 V 1 Leff ueff TOXE este AbulkV asefr V aseff 2V ser t 4 vt V 1 dseff d sat Leff Parameter Description NMOS value NMOS value in in 0 12um 0 12um O 03V 03V Long channel threshold voltage at Vbs OV 0 3V 0 3V VFB Flat bandvoltage OD DVTO First coeffic
90. tes The proposed solution consists of a transmission gate implementation of the XOR operator The truth table of the XOR can be read as follow IF B 0 OUT A IF B 1 OUT Inv A The principle of the circuit presented below is to enable the A signal to flow to node N1 if B 1 and to enable the Inv A signal to flow to node N1 if B 0 The node OUT inverts N1 so that we can find the XOR operator Notice that the nMOS and pMOS devices situated in the middle of the gate serve as pass transistors ys pmas D 25um 2 Dum prnos a D z5um 2 um AOR amog D z5um rn Sum amog o 25umt0 Sum 0 ur Suni Fig 5 8 The schematic diagram of the XOR gate XORCmos SCH You may use DSCH2 to create the cell generate the Verilog description and compile the resulting text In Microwind2 the Verilog compiler is able to construct the XOR cell as reported in Figure 5 9 You may add a visible property to the intermediate node which serves as an input of the second inverter See how the signal called internal is altered by Vtn when the nMOS is ON and Vtp when the pMOS is ON Fortunately the inverter regenerates the signal Fig 5 9 Layout and simulation of the XOR gate XOR MSK 41 18 05 02 5 5 MICROWIND amp DSCH USER S MANUAL 5 Basic Gates Complex Gates The complex gate design technique applies for any combination of operators AND and OR The technique produces compact cells with higher performa
91. th ways A high voltage on the gate attracts electrons below the gate creates an electron channel and enables current to flow A low voltage disables the channel 3 5 Static Mos Characteristics Click on the MOS characteristics icon The screen shown in Figure 2 6 appears It represents the Id Vd static characteristics of the nMOS device 14 18 05 02 MICROWIND amp DSCH USER S MANUAL MOS Viewer for Nmos Width 3 250 Length 0 250 um ldws Vd id ws va logdidy vs Va ads vs Ya Ids pA 2000 YTO 0 50 a 1500 1000 Va 2 50 500 ES P UL VEA ES O T ix En 0 00 1 00 2 00 vds L Vd from 0td5 50 Fora from Oto sg Step Vg 0 50 1 50 1 00 0 50 LD 0 05 a KP 300 00 PH pro X Gamma foso 4 kappa ooi THETA o0 Y VMAX fraooo lt Nes oor lt Ss OK rs Draw DE Fit W 3 250um L 0 251 5 Fig 3 6 N Channel MOS characteristics 4 The Inverter orante eres Temp 27 00 a E Add Measure 4 Nmos 4n Pras The MOS size width and length of the channel situated at the intersection of the polysilicon gate and the diffusion has a strong influence on the value of the current In Figure 3 6 the MOS width is 3 25um and the length is 0 25um A high gate voltage Vg 2 5V corresponds to the highest Id Vd curve For Vg 0 no current flows A maximum current around 1 5mA is obtained for Vg 2 5V Vd 2 5V with
92. the default package values In that case headers R_pin L_pin and C_pin appear 90 18 05 02 MICROWIND amp DSCH USER S MANUAL 10 Input Output Interfacing darte FREE EET ir Fig 10 7 The I O pad generation constructed using the IBIS file default IBS Furthermore Dsch2 uses IBIS to ease the generation of user symbols You may load an IBIS file using the command File gt Open select the IBIS format IBS and click Open If you click Generate Symbol the following screen appears Schema to Symbol ES ls Verlag symbol preview VS Ssuncancarsortabut ENLAU Carr 1 B nord E ors RA DD1 A 55 DOS pkp paroi Dis 5 i Refresh ala Symbol Properties Marne BENCHOT Title BENCHO1_ Save in C Dsch norz Clk ol ee cee se Al rl mi ri 3 ls increasing order of Decreasing T Fig 10 8 User symbol generated from the IBIS description 9 18 05 02 11 11 1 11 2 11 3 MICROWIND amp DSCH USER S MANUAL 11 Design Rules Design Rules Select a Design Rule File The software can handle various technologies The process parameters are stored in files with the appendix RUL The default technology corresponds to a generic 6 metal 0 25um CMOS process The default file is CMOS025 RUL To select a new foundry click on File gt Select Foundry and choose the appropriate technology in the list To set a
93. the simulator that an equivalent resistance must be taken into account for the analog simulation The schematic diagram and layout of the digital analog converter are shown in Figure 9 4 Analog output Vout V ojo o jo fh oes o ro Jo os oo ho h qus Palv E C d 1 fugis RAE X pz ri REE any Tt HE de E le ae el iae Slee H eee e diem Eee i l MEEL E od ms ae tal M s INMITTEN ru pS FHE BH Fej Farrag OS i EET O ad A2 nA2 VH e H om HFH mud WEE PEERS r5 CROCI ESSE Te ote ee Al nAl AO nAO Fig 9 4 Schematic diagram and implementation of the digital analog converter DAC MSK 83 18 05 02 9 Converters MICROWIND amp DSCH USER S MANUAL ns 18 0 analog converter DAC MSK 16 0 BAD 14 0 A nae oe 12 0 shows a regular increase of the output voltage Vout with sat MESS 5 the input combinations from 000 OV to 111 4 375 V Each input change provokes a VEMM EX i VERAM UU 8S Transmission gate Used as sample Hol D Fig 9 5 Simulation of the digital During the conversion from analog to digital the input signal must be kept constant This operation is called sample and hold The transmission gate can be used as a sample and hold circuit The layout of the transmission gate is reported below capacitance network charge and discharge The simulation of the DAC Fig 9 9
94. uced by a factor 50 thanks to a higher threshold voltage 0 45V rather than 0 35 V Small lon reduction pepe AAA cea rM DIEM AAA A TEENE RS p 2 2 2 2 2 2 2 2 dy 2 2 2 2 2 2 2 2 j Fig 3 14 Low leakage MOS for lower loff current The main drawback of the Low leakage MOS device is a 30 reduction of the Ion current leading to a slower switching High speed MOS devices should be used in the case of fast operation linked to critical nodes while low leakage MOS should be placed whenever possible for all nodes where a maximum switching speed is not required 23 18 05 02 MICROWIND amp DSCH USER S MANUAL 4 The Inverter high speed MOS 1 24 n0 12um low1eakage MOS 1 2v In 0 1 thin gate oxide nm thin gate oxide 3rim Fig 3 15 High speed and Low leakage MOS layout The only difference is the option layer configured for the low leakage option 3 13 High voltage MOS Integrated circuits with low voltage internal supply and high voltage I O interface are getting common in deep sub micron technology The internal logic of the integrated circuit operates at very low voltage Typically 1 0V in 0 12um while the I O devices operate in standard voltages 2 5 3 3 or 5V The input output structures work at high voltage thanks to specific MOS devices with thick oxide while the internal devices work at low voltage with optimum performances
95. value propagates to Data and its inverted value propagates to nData SIMULATION The simulation parameters correspond to the write cycle in the RAM The simulation steps describe din figure 6 16 are as follows Mem reaches 1 after an unstable period unpredicatable value Data gets to value O and nData to value 1 Sel is asserted The memory cell Mem goes down to O Data gets to a value of 1 and nData gets to a value of O Sel is still asserted The memory cell fights against Data 1 and surrenders Mem 1 000 Selis inactive The RAM is in a memory state 63 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories 2 50 Fig 7 13 Write cycle for the static RAM cell RAM I MSK 7 6 RAM Array You can duplicate the RAM cell into a 4x4 bit array using the command Edit gt Duplicate XY Select the whole RAM cell and a new window appears Enter the value 4 for X and 4 for Y into the menu Click on Generate The result is shown below D peg meee Bp pe VORNE OL BE E EE if LE m ERBE Eros et a z AER ENTE hes H EE i Kcu HE MEL T 35 REPE ed Peak a EL E E Rz mam plc m ERE x Hm JS NUNT ne DEL Es EJER rif Petr mss DOE ll DE 2 tic x js Lenis n M RENS E 2211 21 15 s gene inn SER SE ii EHE SE NEC d EE eae re ET ih mibi E E ae der ae Hti E ETHE uc kt Ine E el SEDE p n HE ita E z EE E a dubi bs dia aoo l dan Em jki Pr wr Wiz m E
96. xhibits a delay of 0 30ns Fig 6 11 Displaying the critical path between one input and one output 99 18 05 02 MICROWIND amp DSCH USER S MANUAL 7 Latches and Memories 7 Latches Memories 7 1 This chapter details the structure and behavior of latches and memory circuits The RS Latch the D Latch and the edge sensitive register are presenter Then the concepts of ROM static RAM and dynamic RAM memories are introduced together with simulations RS Latch The RS Latch also called Set Reset Flip Flop SR FF transforms a pulse into a continuous state The RS latch can be made up of two interconnected NAND gates In that case the Reset and Set inputs are active low The memory state corresponds to Reset Set 1 The combination Reset Set 0 should not be used as Q nQ 1 Furthermore the simultaneous change from Reset Set 0 to Reset Set 1 provokes what is called the metastable state that corresponds to a parasitic ring effect that may jeopardize the behavior of the whole circuit RS Latch NAND Fig 7 1 The truth table and schematic diagram of a RS latch made RSNor SCH FULL CUSTOM LAYOUT You may create the layout of RS latch manually The two NAND gates may share the VDD and VSS supply achieving continuous diffusions The internal routing may also save routing area leading to the layout shown in Figure 6 2 VERILOG COMPILING Use DSCH2 to create the schematic diagram of the RS latch Verify the circuit with butt
97. yimbol am DICHO M uo qd QM S den 47 0 4 EUA dct Lay 48 Go 1 G10 AE UT NU T DE 49 0 0 Gordo P 51 6 7 Jxnthmctic and Josie Units CAD Uds A btc te pP Eoi rub edat onibus tats faeces 52 Geer Cea at RERO TNR RETE 53 7 Latches e MOHIOFIOS eiii uidisse ibit a EI dor atte EA e EN octet 54 FAR MEA A AO 54 TR TUE 56 Sa A UR E TL E 58 FA AOU SONT uc m 61 TS RAM Meno q OCA O PU EUN LN 62 KORAM A A A A O II A A 64 der RAM Eme decido 65 Lo RAM Column Sec aa 66 TI Dynami cR AM MenO Gor ERE RE POPE PP T na Uae aye aiaedaise Ee Ct ME ed 66 O EEPROM A A LC IM M ALIM EOS EE LAU 69 Oe AMA COS A Rae ENIM CM ee EI 71 dul JIuodeseconiected MONS an os c C o AS 71 9 2 Voltage IRE Cher rice t eesti ete neces T OT cm 72 0 9 RINE NT OE Sra ar Rt Sie EL Au Ea Nate SO eae Eh ELLE DL DAE 73 SA mele MACS MA ae ion A AS dean beau Ged A bn rd etuer 74 8 5 imple Ditictemlal Aiur iibi Ebr dE Sure tenses iaa 75 5 6 Voltage Controlled Oscillator s desino ecussnslecendualtiuestarecGaeohesuisnsdeimtduaddivastasatGeneetasucsasdasued o iier b beret 79 9 ACONMVEN Oo eene l Ah Amalos Brbal ci CON VEO dls I TTE 81 2 2 ADO Male malos CONVE Mer tai aia 83 9 sample and Hold Cri rai n 84 10 Input Output Inter ACME oret ERE ep UE ER elastase Ud mM 6 TO b Create Pad RIDE it Lead e iau 86

Microwind & Dsch User's Manual Version 2

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Microwind &amp; Dsch User's Manual Version 2

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Microwind & Dsch User's Manual Version 2