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UM10204 I2C-bus specification and user manual

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2. VDD 1 4 HCT4066 5V 10 1 3 KQ Rp2 1 7 K2 Rp1 7 E s I SDA or SCL bus line lt 100 9 Rs lt 100 Q Rg l l O O Cp T 400 pF e En max N N Vss FAST MODE C BUS DEVICES mbc620 Fig 44 Switched pull up circuit UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 57 of 64 NXP Semiconductors U M1 0204 7 3 UM10204 I2C bus specification and user manual The switched pull up circuit in Figure 44 is for a supply voltage of Vpp 5 V 10 anda maximum capacitive load of 400 pF Since it is controlled by the bus levels it needs no additional switching control signals During the rising falling edges the bilateral switch in the HCT4066 switches pull up resistor Rp2 on off at bus levels between 0 8 V and 2 0 V Combined resistors Rp and Rp2 can pull up the bus line within the maximum specified rise time t of 300 ns Series resistors Rs are optional They protect the I O stages of the I2C bus devices from high voltage spikes on the bus lines and minimize crosstalk and undershoot of the bus line signals The maximum value of R is determined by the maximum permitted voltage drop across this resistor when the bus line is switched to the LOW level in order to switch Off Rp2 Additionally some bus buffers contain integral rise time accelerators Stand
3. Fig 16 General call address format There are two cases to consider e When the least significant bit B is a zero e When the least significant bit B is a one When bit B is a zero the second byte has the following definition e 0000 0110 06h Reset and write programmable part of slave address by hardware On receiving this 2 byte sequence all devices designed to respond to the general call address reset and take in the programmable part of their address Precautions must be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage since these low levels would block the bus e 0000 0100 04h Write programmable part of slave address by hardware Behaves as above but the device does not reset e 0000 0000 00h This code is not allowed to be used as the second byte Sequences of programming procedure are published in the appropriate device data sheets The remaining codes have not been fixed and devices must ignore them When bit B is a one the 2 byte sequence is a hardware general call This means that the sequence is transmitted by a hardware master device such as a keyboard scanner which can be programmed to transmit a desired slave address Since a hardware master does not know in advance to which device the message has to be transferred it can only generate this hardware general call and its
4. UM10204 I2C bus specification and user manual Rev 5 9 October 2012 User manual Document information Info Content Keywords 12C l2C bus Standard mode Fast mode Fast mode Plus Fm Ultra Fast mode UFm High Speed Hs inter IC SDA SCL USDA USCL Abstract Philips Semiconductors now NXP Semiconductors developed a simple bidirectional 2 wire bus for efficient inter IC control This bus is called the Inter IC or I C bus Only two bus lines are required a serial data line SDA and a serial clock line SCL Serial 8 bit oriented bidirectional data transfers can be made at up to 100 kbit s in the Standard mode up to 400 kbit s in the Fast mode up to 1 Mbit s in the Fast mode Plus Fm or up to 3 4 Mbit s in the High speed mode The Ultra Fast mode is a uni directional mode with data transfers of up to 5 Mbit s NXP Semiconductors U M1 0204 I2C bus specification and user manual Revision history Rev Date Description v 5 20121009 User manual fifth release Modifications e Section 3 1 7 Clock synchronization first paragraph first sentence changed from idle bus to free bus e Section 3 1 8 Arbitration third paragraph second sentence changed from the bus is idle to the bus is free e Section 3 1 12 Reserved addresses Table 3 Reserved addresses slave address 1111 1XX R W bit changed from X to 1 descripti
5. Fig 8 Arbitration procedure of two masters Since control of the 1 C bus is decided solely on the address and data sent by competing masters there is no central master nor any order of priority on the bus There is an undefined condition if the arbitration procedure is still in progress at the moment when one master sends a repeated START or a STOP condition while the other master is still sending data In other words the following combinations result in an undefined condition e Master 1 sends a repeated START condition and master 2 sends a data bit e Master 1 sends a STOP condition and master 2 sends a data bit e Master 1 sends a repeated START condition and master 2 sends a STOP condition UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 12 of 64 NXP Semiconductors U M1 0204 I2C bus specification and user manual 3 1 9 Clock stretching Clock stretching pauses a transaction by holding the SCL line LOW The transaction cannot continue until the line is released HIGH again Clock stretching is optional and in fact most slave devices do not include an SCL driver so they are unable to stretch the clock On the byte level a device may be able to receive bytes of data at a fast rate but needs more time to store a received byte or prepare another byte to be transmitted Slaves can then hold the SCL lin
6. a Configuring master sends dump address to hardware master DUMP ADDR FROM H W MASTER R W A DATA A DATA A A P write a e n bytes ack 002aac886 b Hardware master dumps data to selected slave Fig 18 Data transfer by a hardware transmitter capable of dumping data directly to slave devices 3 1 14 Software reset Following a General Call 0000 0000 sending 0000 0110 06h as the second byte causes a software reset This feature is optional and not all devices respond to this command On receiving this 2 byte sequence all devices designed to respond to the general call address reset and take in the programmable part of their address Precautions must be taken to ensure that a device is not pulling down the SDA or SCL line after applying the supply voltage since these low levels would block the bus 3 1 15 START byte Microcontrollers can be connected to the I C bus in two ways A microcontroller with an on chip hardware C bus interface can be programmed to be only interrupted by requests from the bus When the device does not have such an interface it must constantly monitor the bus via software Obviously the more times the microcontroller monitors or polls the bus the less time it can spend carrying out its intended function There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on sof
7. kHz ns ns ns ns ns ns ns ns ns ns ns 1 tvp pat minimum time for USDA data out to be valid following USCL LOW 2 Typical rise time or fall time for UFm signals is 25 ns measured from the 30 level to the 70 level rise time or from the 70 level to the 30 level fall time USDA USCL eee USCL tr tsu DAT oe eo eet it 9th clock Fig 40 Definition of timing for Ultra Fast mode devices on the I2C bus 9th clock eee cont cont 002aag826 UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 54 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual 7 Electrical connections of I2C bus devices to the bus lines 7 1 Pull up resistor sizing The bus capacitance is the total capacitance of wire connections and pins This capacitance limits the maximum value of Rp due to the specified rise time Figure 41 shows Rp max as a function of bus capacitance Consider the Vpp related input threshold of Vi 0 7Vpp and V 0 3Vpp for the purposes of RC time constant calculation Then V t Vpp 1 et RC where tis the time since the charging started and RC is the time constant V t1 0 3 x Vpp Vpop 1 et RC then t1 0 3566749 x RC V t2 0 7 x Vpp Vpp 1 e 2 RC then t2 1 2039729 x RC T
8. ____ mbc608 Fig 10 The first byte after the START procedure UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 13 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual Possible data transfer formats are Master transmitter transmits to slave receiver The transfer direction is not changed see Figure 11 The slave receiver acknowledges each byte Master reads slave immediately after first byte see Figure 12 At the moment of the first acknowledge the master transmitter becomes a master receiver and the slave receiver becomes a slave transmitter This first acknowledge is still generated by the slave The master generates subsequent acknowledges The STOP condition is generated by the master which sends a not acknowledge A just before the STOP condition Combined format see Figure 13 During a change of direction within a transfer the START condition and the slave address are both repeated but with the R W bit reversed If a master receiver sends a repeated START condition it sends a not acknowledge A just before the repeated START condition Notes 1 UM10204 Combined formats can be used for example to control a serial memory The internal memory location must be written during the first data byte After the START condition and slave address is repe
9. e SU DAT tsu sTO lt __ tHigH tLow MCS current source pull up f Rp resistor pull up CL lt M tlow HIGH 1 First rising edge of the SCLH signal after Sr and after each acknowledge bit Fig 39 Definition of timing for Hs mode devices on the I2C bus 002aag825 0 7 x VDD 0 3 x VDD 6 3 Ultra Fast mode devices The I O levels I O current spike suppression output slope control and pin capacitance are given in Table 13 The UFm I C bus timing characteristics are given in Table 14 Figure 40 shows the timing definitions for the 1 C bus The minimum HIGH and LOW periods of the SCL clock specified in Table 14 determine the maximum bit transfer rates of 5000 kbit s for Ultra Fast mode Devices must be able to follow transfers at their own maximum bit rates either by being able to transmit or receive at that speed Table 13 Characteristics of the USDA and USCL I O stages n a not applicable Symbol Parameter Vib LOW level input voltage Vin HIGH level input voltage Vhys hysteresis of Schmitt trigger inputs VoL LOW level output voltage Vou HIGH level output voltage IL leakage current Ci input capacitance tsp pulse width of spikes that must be suppressed by the input filter Conditions at 4 mA sink current Vpp gt 2 V at 4 mA source current Vpp gt 2 V Vpp 3 6 V Vpp 5 5 V Is Ultra Fast mode Min 0 5 0
10. MASTER SLAVE MASTER SLAVE msc612 SDA and SCL are not used here but may be used for other functions To input filter Only the active master can enable its current source pull up circuit Dotted transistors are optional open drain outputs which can stretch the serial clock signal SCLH Fig 32 1 C bus configuration with Hs mode devices only 5 3 2 Serial data format in Hs mode Serial data transfer format in Hs mode meets the Standard mode C bus specification Hs mode can only commence after the following conditions all of which are in F S mode 1 START condition S 2 8 bit master code 0000 1XXX 3 Not acknowledge bit A Figure 33 and Figure 34 show this in more detail This master code has two main functions e It allows arbitration and synchronization between competing masters at F S mode speeds resulting in one winning master e lt indicates the beginning of an Hs mode transfer Hs mode master codes are reserved 8 bit codes which are not used for slave addressing or other purposes Furthermore as each master has its own unique master code up to eight Hs mode masters can be present on the one I2C bus system although master code 0000 1000 should be reserved for test and diagnostic purposes The master code for an Hs mode master device is software programmable and is chosen by the System Designer UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All
11. UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 40 of 64 NXP Semiconductors U M1 0204 UM10204 5 3 4 I2C bus specification and user manual The non active or losing masters 1 Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hs mode 2 Wait fora STOP condition to detect when the bus is free again All slaves 1 Adapt their SDAH and SCLH input filters according to the spike suppression requirement in Hs mode 2 Adapt the set up and hold times according to the Hs mode requirements This requirement may already be fulfilled by the adaptation of the input filters 3 Adapt the slope control of their SDAH output stages if necessary For slave devices slope control is applicable for the SDAH output stage only and depending on circuit tolerances both the Fast mode and Hs mode requirements may be fulfilled without switching its internal circuit At time tps in Figure 34 each connected device must recognize the STOP condition P and switch its internal circuit from the Hs mode setting back to the Fast mode setting as present before time t4 This must be completed within the minimum bus free time as specified in Table 10 according to the Fast mode specification Hs mode devices at lower speed modes Hs mode devices are fully downwards compatible and can be connected
12. Ultra Fast mode UFm devices offer an increase in I C bus transfer speeds UFm devices can transfer information at bit rates of up to 5 Mbit s UFm devices offer push pull drivers eliminating the pull up resistors allowing higher transfer rates The same serial bus protocol and data format is maintained as with the Sm Fm or Fm system UFm bus devices are not compatible with bidirectional I2 C bus devices 6 Electrical specifications and timing for I O stages and bus lines UM10204 6 1 Standard Fast and Fast mode Plus devices The I O levels I O current spike suppression output slope control and pin capacitance are given in Table 9 The I C bus timing characteristics bus line capacitance and noise margin are given in Table 10 Figure 38 shows the timing definitions for the 1 C bus The minimum HIGH and LOW periods of the SCL clock specified in Table 10 determine the maximum bit transfer rates of 100 kbit s for Standard mode devices 400 kbit s for Fast mode devices and 1000 kbit s for Fast mode Plus Devices must be able to follow transfers at their own maximum bit rates either by being able to transmit or receive at that speed or by applying the clock synchronization procedure described in Section 3 1 7 which forces the master into a wait state and stretch the LOW period of the SCL signal In the latter case the bit transfer rate is reduced All information provided in this document is subject to legal disclaimers
13. Input reference levels are set as 30 and 70 of Vpp Vit is 0 3Vpp and Vip is 0 7Vpp See Figure 38 timing diagram Some legacy device input levels were fixed at Vi_ 1 5 V and V p 3 0 V but all new devices require this 30 70 specification See Section 6 for electrical specifications Data validity The data on the SDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the SCL line is LOW see Figure 4 One clock pulse is generated for each data bit transferred SDA SCL data line change stable of data data valid allowed mba607 Fig 4 Bit transfer on the I2C bus START and STOP conditions All transactions begin with a START S and are terminated by a STOP P see Figure 5 A HIGH to LOW transition on the SDA line while SCL is HIGH defines a START condition A LOW to HIGH transition on the SDA line while SCL is HIGH defines a STOP condition START condition STOP condition mba608 Fig 5 START and STOP conditions START and STOP conditions are always generated by the master The bus is considered to be busy after the START condition The bus is considered to be free again a certain time after the STOP condition This bus free situation is specified in Section 6 The bus stays busy if a repeated START Sr is generated instead of a STOP condition In this respect the START S and repeated START Sr condit
14. 0 1Vpp V including hysteresis VhH noise margin at the HIGH level for each connected device 0 2Vpp 0 2Vpp 0 2Vpp V including hysteresis SJOJONPUODIWIIS dXN 1 All values referred to ViH min 0 3Vpp and Vit max 0 7Vpp levels see Table 9 2 tup pat is the data hold time that is measured from the falling edge of SCL applies to data in transmission and the acknowledge 3 A device must internally provide a hold time of at least 300 ns for the SDA signal with respect to the ViH min of the SCL signal to bridge the undefined region of the falling edge of SCL 4 The maximum typ pat could be 3 45 us and 0 9 us for Standard mode and Fast mode but must be less than the maximum of typ pat OF tvp ack by a transition time This maximum must only be met if the device does not stretch the LOW period tLow of the SCL signal If the clock stretches the SCL the data must be valid by the set up time before it releases the clock jenuew Jasn pue uoneoyisads snq 2zl vozo LINN jenuew sn ZLO 14990390 6 S 34 sJaWure Osip je 0 JOalgns s zjuawnoop Siu u PaplAOsd UOHEWOYU jiy v9 0 6t v0zOlLWN pamasa syfu Ily ZLOZ A dXN 5 6 7 8 9 10 11 12 A Fast mode I C bus device can be used in a Standard mode 2C bus system but the requirement tgy pat 250 ns must then be met This will automatically be the case if the device does not stretch the LOW period of the
15. 2012 35 of 64 NXP Semiconductors U M1 0204 UM10204 5 1 5 2 l2C bus specification and user manual Fast mode Fast mode devices can receive and transmit at up to 400 kbit s The minimum requirement is that they can synchronize with a 400 kbit s transfer they can then prolong the LOW period of the SCL signal to slow down the transfer The protocol format logic levels and maximum capacitive load for the SDA and SCL lines are the same as the Standard mode C bus specification Fast mode devices are downward compatible and can communicate with Standard mode devices in a 0 to 100 kbit s 1 C bus system As Standard mode devices however are not upward compatible they should not be incorporated in a Fast mode I2C bus system as they cannot follow the higher transfer rate and unpredictable states would occur The Fast mode C bus specification has the following additional features compared with the Standard mode e The maximum bit rate is increased to 400 kbit s e Timing of the serial data SDA and serial clock SCL signals has been adapted There is no need for compatibility with other bus systems such as CBUS because they cannot operate at the increased bit rate e The inputs of Fast mode devices incorporate spike suppression and a Schmitt trigger at the SDA and SCL inputs e The output buffers of Fast mode devices incorporate slope control of the falling edges of the SDA and SCL signals e If the power supply to a Fast
16. 7 During Hs mode transfer however the bridge All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 42 of 64 UM10204 l2C bus specification and user manual NXP Semiconductors opens to separate the two bus sections and allows Hs mode devices to communicate with each other at 3 4 Mbit s Arbitration between Hs mode devices and F S mode devices is only performed during the master code 0000 1XXX and normally won by one Hs mode master as no slave address has four leading zeros Other masters can win the arbitration only if they send a reserved 8 bit code 0000 0XXX In such cases the bridge remains closed and the transfer proceeds in F S mode Table 8 gives the possible communication speeds in such a system Vpp1 Vpp2 Rp Rp BRIDGE Rp Rp SDAH Rs SDAH SDA lt gt SCLH Rs SCLH SCL 4 p A s Je Rs Rs Rs Rs Rs Rs Rs Rs Rs Rs M 0 F S mode F S mode MASTER SLAVE Hs mode MASTER SLAVE Hs mode MASTER SLAVE Hs mode SLAVE Hs mode SLAVE SLAVE msc614 Bridge not used SDA and SCL may have an alternative function 2 T
17. 7Vppt 0 05Vpp 0 Vpp 0 4 1 10 Max 0 3Vpp 2 0 4 1 10 10 10 Unit lt lt lt lt lt uA uA pF ns 1 Refer to component data sheets for actual switching points 2 Maximum Viq Vppimax 0 5 V or 5 5 V whichever is lower See component data sheets 3 Special purpose devices such as multiplexers and switches may exceed this capacitance because they connect multiple paths together 4 Input filters on the USDA and USCL slave inputs suppress noise spikes of less than 10 ns UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 53 of 64 NXP Semiconductors UM10204 I2C bus specification and user manual Table 14 UFm I2C bus frequency and timing specifications Symbol fuscL tBUF tHD STA tsu STA tsu sTo tHD DAT tvD DAT tsu DAT tLow tHIGH tf tr Parameter Conditions USCL clock frequency bus free time between a STOP and START condition hold time repeated START condition set up time for a repeated START condition set up time for STOP condition data hold time data valid time 0 data set up time LOW period of the USCL clock HIGH period of the USCL clock fall time of both USDA and USCL signals rise time of both USDA and USCL signals Ultra Fast mode Unit Min 0 80 50 50 50 10 10 30 50 50 2 2 Max 5000 50 50
18. All rights reserved User manual Rev 5 9 October 2012 56 of 64 NXP Semiconductors U M1 0204 7 2 4 l2C bus specification and user manual capacitance Keep in mind that adding a buffer always adds delays a buffer delay plus an additional transition time to each edge which reduces the maximum operating frequency and may also introduce special Vj and Vo considerations Refer to application notes AN255 C SMBus Repeaters Hubs and Expanders and AN262 PCA954x Family of C SMBus Multiplexers and Switches for more details on this subject and the devices available from NXP Semiconductors Vpp1 Vpp2 ei on eee ee Oooo slaves and masters slaves and masters 002aac882 Remark Some buffers allow Vpp and Vpp 2 to be different levels Fig 43 Using a buffer to divide bus capacitance Switched pull up circuit The supply voltage Vpp and the maximum output LOW level determine the minimum value of pull up resistor Rp see Section 7 1 For example with a supply voltage of Vpp 5V 10 and VoL max 0 4Vat3 mA Rp min 5 5 0 4 0 003 1 7 KQ As shown in Figure 42 this value of Rp limits the maximum bus capacitance to about 200 pF to meet the maximum t requirement of 300 ns If the bus has a higher capacitance than this a switched pull up circuit as shown in Figure 44 can be used
19. HIGH thus preventing spikes on the bus lines TR1 and TR2 must be closed within the minimum bus free time according to the Fast mode specification see tgyr in Table 10 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 44 of 64 UM10204 l2C bus specification and user manual NXP Semiconductors 8 bit Master code 00001 xxx Ss tH e ee Y ae ee ee SCLH SDA SCL SDAH SCLH ft f pews 6 7 Js J9 1 210 5 Je 7 a Jo P SDA a to SCL IfP then Hs mode a F S mode If Sr dotted lines then Hs mode gee tH tFs mes611 S MCS current source pull up Rp resistor pull up Fig 37 A complete Hs mode transfer in a mixed speed bus system 5 3 8 Timing requirements for the bridge in a mixed speed bus system It can be seen from Figure 37 that the actions of the bridge at t4 ty and tes must be so fast that it does not affect the SDAH and SCLH lines Furthermore the bridge must meet the related timing requirements of the Fast mode specification for the SDA and SCL lines All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved UM10204 User manual Rev 5 9 October 2012 45 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual 5 4 Ultra Fast mode
20. SCL signal If such a device does stretch the LOW period of the SCL signal it must output the next data bit to the SDA line trmax tsu pat 1000 250 1250 ns according to the Standard mode l2C bus specification before the SCL line is released Also the acknowledge timing must meet this set up time If mixed with Hs mode devices faster fall times according to Table 10 are allowed The maximum t for the SDA and SCL bus lines is specified at 300 ns The maximum fall time for the SDA output stage t is specified at 250 ns This allows series protection resistors to be connected in between the SDA and the SCL pins and the SDA SCL bus lines without exceeding the maximum specified ty In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing Necessary to be backwards compatible to Fast mode The maximum bus capacitance allowable may vary from this value depending on the actual operating voltage and frequency of the application Section 7 2 discusses techniques for coping with higher bus capacitances tvp pat time for data signal from SCL LOW to SDA output HIGH or LOW depending on which one is worse tvp ack time for Acknowledgement signal from SCL LOW to SDA output HIGH or LOW depending on which one is worse jenuew Jasn pue uoneoyiseds snq 2zl vozo LINN SJOJONPUODIWIIS dXN NXP Semiconductors U M1 0204 l
21. a PCB with a Vss and or Vpp layer is used the Vss and Vpp lines can be omitted If the bus lines are twisted pairs each bus line must be twisted with a Vss return Alternatively the SCL line can be twisted with a Vgs return and the SDA line twisted with a Vpp return In the latter case capacitors must be used to decouple the Vpp line to the Vss line at both ends of the twisted pairs If the bus lines are shielded shield connected to Vss interference is minimized However the shielded cable must have low capacitive coupling between the SDA and SCL lines to minimize crosstalk All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 60 of 64 NXP Semiconductors UM10204 8 Abbreviations I2C bus specification and user manual Table 15 Abbreviations Acronym A D ATCA BMC CMOS cPCl D A DIP EEPROM HW 0 12C bus IC IPMI LCD LED LSB MCU MSB NMOS PCB PCI PMBus RAM ROM SMBus SPI UART USB Description Analog to Digital Advanced Telecom Computing Architecture Baseboard Management Controller Complementary Metal Oxide Semiconductor compact Peripheral Component Interconnect Digital to Analog Dual In line Package Electrically Erasable Programmable Read Only Memory Hardware Input Output Inter Integrated Circuit bus Integrated Circuit Intelligent Platform Management Interface Liquid Crystal
22. alone rise time accelerators are also available Series protection resistors As shown in Figure 45 series resistors Rs of for example 300 Q can be used for protection against high voltage spikes on the SDA and SCL lines resulting from the flash over of a TV picture tube for example If series resistors are used designers must add the additional resistance into their calculations for Rp and allowable bus capacitance VDD VDD 12C 12C DEVICE DEVICE Rp Rp Rs Rs Rs Rs SDA ai SCL mbc627 Fig 45 Series resistors R for protection against high voltage spikes The required noise margin of 0 1Vpp for the LOW level limits the maximum value of Rg Rg max as a function of Rp is shown in Figure 46 Note that series resistors affect the output fall time All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 58 of 64 NXP Semiconductors UM10204 UM10204 l2C bus specification and user manual 10 mbc629 Rp k9 8 6 4 2 0 0 400 800 1200 1600 maximum value Rg Q Fig 46 Maximum value of Rs as a function of the value of Rp with supply voltage as a parameter 7 4 Input leakage The maximum HIGH level input current of each input output connection
23. between 100 pF and 400 pf the rise and fall time values must be linearly interpolated 4 If their supply voltage has been switched off SDAH and SCLH I O stages of Hs mode slave devices must have floating outputs Due to the current source output circuit which normally has a clipping diode to Vpp this requirement is not mandatory for the SCLH or the SDAH I O stage of Hs mode master devices This means that the supply voltage of Hs mode master devices cannot be switched off without affecting the SDAH and SCLH lines 5 Special purpose devices such as multiplexers and switches may exceed this capacitance because they connect multiple paths together UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 51 of 64 NXP Semiconductors UM10204 I2C bus specification and user manual Table 12 Characteristics of the SDAH SCLH SDA and SCL bus lines for Hs mode I C bus devices Symbol Parameter Conditions C 100 pF max Cp 400 pF Unit Min Max Min Max fgcLH SCLH clock frequency 0 3 4 0 1 7 MHz tsu STA set up time for a repeated 160 160 ns START condition tHD sTA hold time repeated START 160 160 ns condition tlow LOW period of the SCL clock 160 320 ns tHIGH HIGH period of the SCL clock 60 120 ns tsu DAT data set up time 10 10 ns tup pat data hold time ols 70 ols 150 ns trot rise time of
24. electrical characteristics than SMBus 1 0 The main difference is the current sink capability with Vor 0 4 V e SMBus low power 350 uA e SMBus high power 4 mA e I C bus 3 mA SMBus high power devices and 2C bus devices will work together if the pull up resistor is sized for 3 mA For more information refer to www nxp com redirect smbus org UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 33 of 64 NXP Semiconductors U M1 0204 4 3 4 4 UM10204 I2C bus specification and user manual PMBus Power Management Bus PMBus is a standard way to communicate between power converters and a system host over the SMBus to provide more intelligent control of the power converters The PMBus specification defines a standard set of device commands so that devices from multiple sources function identically PMBus devices use the SMBus Version 1 1 plus extensions for transport For more information refer to www nxp com redirect pmbus org Intelligent Platform Management Interface IPMl Intelligent Platform Management Interface IPMI defines a standardized abstracted message based interface for intelligent platform management hardware IPMI also defines standardized records for describing platform management devices and their characteristics IPMI increases reliability of systems by monitoring paramet
25. environmental UM10204 All information provided in this document is subject to legal disclaimers damage NXP Semiconductors and its suppliers accept no liability for inclusion and or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and or use is at the customer s own risk Applications Applications that are described herein for any of these products are for illustrative purposes only NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification Customers are responsible for the design and operation of their applications and products using NXP Semiconductors products and NXP Semiconductors accepts no liability for any assistance with applications or customer product design It is customer s sole responsibility to determine whether the NXP Semiconductors product is suitable and fit for the customer s applications and products planned as well as for the planned application and use of customer s third party customer s Customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products NXP Semiconductors does not accept any liability related to any default damage costs or problem which is based on any weakness or default in the customer s applications or products or the application or use by customer s third
26. has a specified maximum value of 10 uA Due to the required noise margin of 0 2Vpp for the HIGH level this input current limits the maximum value of Rp This limit depends on Vpp The total HIGH level input current is shown as a function of Remax in Figure 47 mbc630 20 maximum value Rp kQ 0 40 80 120 160 200 total high level input current uA Fig 47 Total HIGH level input current as a function of the maximum value of Rp with supply voltage as a parameter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 59 of 64 NXP Semiconductors U M1 0204 UM10204 l2C bus specification and user manual 7 5 Wiring pattern of the bus lines In general the wiring must be chosen so that crosstalk and interference to from the bus lines is minimized The bus lines are most susceptible to crosstalk and interference at the HIGH level because of the relatively high impedance of the pull up devices If the length of the bus lines on a PCB or ribbon cable exceeds 10 cm and includes the Vpp and Vss lines the wiring pattern should be SDA Vpp Vss SCL If only the Vss line is included the wiring pattern should be SDA Vss SCL These wiring patterns also result in identical capacitive loads for the SDA and SCL lines If
27. in over 1000 different ICs and licensed to more than 50 companies Many of today s applications however require higher bus speeds and lower supply voltages This updated version of the 2C bus specification meets those requirements v1 0 1992 Version 1 0 of the I2C bus specification Original 1982 first release Contact information For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 2 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual 1 Introduction The C bus is a de facto world standard that is now implemented in over 1000 different ICs manufactured by more than 50 companies Additionally the versatile 1 C bus is used in various control architectures such as System Management Bus SMBus Power Management Bus PMBus Intelligent Platform Management Interface IPMI Display Data Channel DDC and Advanced Telecom Computing Architecture ATCA This document assists device and system designers to understand how the 2C bus works and implement a working application Various operating modes are described It contains a comprehensive introduction to the 1 C bus data transfer handshaking and bus arbitration schemes Detailed sections cover the timing a
28. manual The START byte 0000 0001 01h can precede the 10 bit addressing in the same way as for 7 bit addressing see Section 3 1 15 Reserved addresses Two groups of eight addresses 0000 XXX and 1111 XXX are reserved for the purposes shown in Table 3 Table 3 Reserved addresses X don t care 1 HIGH 0 LOW Slave address R W bit Description 0000 000 0 general call address 0000 000 1 START bytel2 0000 001 X CBUS address 0000 010 X reserved for different bus format 0000 011 X reserved for future purposes 0000 1XX X Hs mode master code 1111 1XX 1 device ID 1111 OXX X 10 bit slave addressing 1 The general call address is used for several functions including software reset 2 No device is allowed to acknowledge at the reception of the START byte 3 The CBUS address has been reserved to enable the inter mixing of CBUS compatible and 1 C bus compatible devices in the same system I2C bus compatible devices are not allowed to respond on reception of this address 4 The address reserved for a different bus format is included to enable 12C and other protocols to be mixed Only C bus compatible devices that can work with such formats and protocols are allowed to respond to this address Assignment of addresses within a local system is up to the system architect who must take into account the devices being used on the bus and any future interaction with other conventional I2C buses For example a device wi
29. protocols 6 SDA and SCL signals 4 8 SDA and SCL logic levels 9 Data validity 0 cee eee eee eee 9 START and STOP conditions 9 Byte TOrmMatsnce enc ae eae eee sarees eee 10 Acknowledge ACK and Not Acknowledge NACK esaera a8 scott EEEN DEV Enpa iE 10 Clock synchronization 11 Arbitrate ai ensia Ohne Aots ananernd wees 11 Clock stretching siete byte athe ney 13 The slave address and R W bit 13 10 bit addressing 4 15 Reserved addresses 5 17 General call address 0 17 Software reset 0000 cece eee 19 START Dyt sc diester ek doa cate sane tE ii 19 BUS Cleali cic cceevinedeadeceeav aed bed 20 Device ID aie Fickle pera nmani aeg does 20 Ultra Fast mode I2C bus protocol 23 USDA and USCL signals 25 USDA and USCL logic levels 25 Data validity 0 eee eee eee 25 START and STOP conditions 25 Byte format iseda iana e mis thE ne tiha 26 Acknowledge ACK and Not Acknowledge NACK 2 005 al Soe apn as Sate 27 The slave address and R W bit 27 10 bit addressing 0 28 Reserved addresses in UFm 29 General call address 0 30 Software reset 20000 eee 30 START byte eich vase esas ended 30 Unresponsive slave reset 31 Dev
30. rights reserved User manual Rev 5 9 October 2012 38 of 64 NXP Semiconductors U M1 0204 UM10204 I2C bus specification and user manual Arbitration and clock synchronization only take place during the transmission of the master code and not acknowledge bit A after which one winning master remains active The master code indicates to other devices that an Hs mode transfer is to begin and the connected devices must meet the Hs mode specification As no device is allowed to acknowledge the master code the master code is followed by a not acknowledge A After the not acknowledge bit A and the SCLH line has been pulled up to a HIGH level the active master switches to Hs mode and enables at time ty see Figure 34 the current source pull up circuit for the SCLH signal As other devices can delay the serial transfer before ty by stretching the LOW period of the SCLH signal the active master enables its current source pull up circuit when all devices have released the SCLH line and the SCLH signal has reached a HIGH level thus speeding up the last part of the rise time of the SCLH signal The active master then sends a repeated START condition Sr followed by a 7 bit slave address or 10 bit slave address see Section 3 1 11 with a R W bit address and receives an acknowledge bit A from the selected slave After a repeated START condition and after each acknowledge bit A or not acknowledge bit A the active master di
31. 2C bus specification and user manual tr tsu DAT gth clock 1 fsci 18t clock cycle eee SDA tSU STA eee SCL gth clock 002aac938 Vit 0 3Vpp Vin 0 7Vpp Fig 38 Definition of timing for F S mode devices on the I C bus 6 2 Hs mode devices The I O levels I O current spike suppression output slope control and pin capacitance for I2 C bus Hs mode devices are given in Table 11 The noise margin for HIGH and LOW levels on the bus lines are the same as specified for F S mode C bus devices Figure 39 shows all timing parameters for the Hs mode timing The normal START condition S does not exist in Hs mode Timing parameters for Address bits R W bit Acknowledge bit and DATA bits are all the same Only the rising edge of the first SCLH clock signal after an acknowledge bit has a larger value because the external Rp has to pull up SCLH without the help of the internal current source The Hs mode timing parameters for the bus lines are specified in Table 12 The minimum HIGH and LOW periods and the maximum rise and fall times of the SCLH clock signal determine the highest bit rate With an internally generated SCLH signal with LOW and HIGH level periods of 200 ns and 100 ns respectively an Hs mode master fulfills the timing requirements for the external SCLH clock pulses taking the rise and fall times into account for the maximum bit rate of 3 4 Mbit s So a basic frequency of 10 MHz or a mult
32. Data Channel DDC The Display Data Channel DDC allows a monitor or display to inform the host about its identity and capabilities The specification for DDC version 2 calls for compliance with the l2C bus standard mode specification It allows bidirectional communication between the display and the host enabling control of monitor functions such as how images are displayed and communication with other devices attached to the I C bus For more information refer to www nxp com redirect vesa org 5 Bus speeds UM10204 Originally the 1 C bus was limited to 100 kbit s operation Over time there have been several additions to the specification so that there are now five operating speed categories Standard mode Fast mode Fm Fast mode Plus Fm and High speed mode Hs mode devices are downward compatible any device may be operated at a lower bus speed Ultra Fast mode devices are not compatible with previous versions since the bus is unidirectional e Bidirectional bus Standard mode Sm with a bit rate up to 100 kbit s Fast mode Fm with a bit rate up to 400 kbit s Fast mode Plus Fm with a bit rate up to 1 Mbit s High speed mode Hs mode with a bit rate up to 3 4 Mbit s e Unidirectional bus Ultra Fast mode UFm with a bit rate up to 5 Mbit s All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October
33. Display Light Emitting Diode Least Significant Bit Microcontroller Most Significant Bit Negative channel Metal Oxide Semiconductor Printed Circuit Board Peripheral Component Interconnect Power Management Bus Random Access Memory Read Only Memory System Management Bus Serial Peripheral Interface Universal Asynchronous Receiver Transmitter Universal Serial Bus UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 61 of 64 NXP Semiconductors UM10204 9 Legal information l2C bus specification and user manual 9 1 Definitions Draft The document is a draft version only The content is still under internal review and subject to formal approval which may result in modifications or additions NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information 9 2 Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable However NXP Semiconductors does not give any representations or warranties expressed or implied as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information NXP Semiconductors takes no responsibility for the
34. M10204 2 2 I2C bus specification and user manual e Integrated addressing and data transfer protocol allow systems to be completely software defined e The same IC types can often be used in many different applications e Design time reduces as designers quickly become familiar with the frequently used functional blocks represented by 2C bus compatible ICs e ICs can be added to or removed from a system without affecting any other circuits on the bus e Fault diagnosis and debugging are simple malfunctions can be immediately traced e Software development time can be reduced by assembling a library of reusable software modules In addition to these advantages the CMOS ICs in the I2C bus compatible range offer designers special features which are particularly attractive for portable equipment and battery backed systems They all have e Extremely low current consumption e High noise immunity e Wide supply voltage range e Wide operating temperature range Manufacturer benefits I2C bus compatible ICs not only assist designers they also give a wide range of benefits to equipment manufacturers because e The simple 2 wire serial I C bus minimizes interconnections so ICs have fewer pins and there are not so many PCB tracks result smaller and less expensive PCBs e The completely integrated I C bus protocol eliminates the need for address decoders and other glue logic e The multi master capability of the 1 C bu
35. NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 46 of 64 jenuew sn ZLOZ 4990390 6 S 34 sa wrejos p ea 0 JOalgns s zjuawnoop Siu u PaplAosd UOHEWOJU jiy t9 JO Lh YOZOLNN pamasa syfu Ily ZLOZ A dXN Table 9 Characteristics of the SDA and SCL I O stages ma not applicable Symbol Parameter Conditions Standard mode Fast mode Fast mode Plus Unit Min Max Min Max Min Max VIL LOW level input voltage 0 5 0 3Vpp 0 5 0 3Vpp 0 5 0 3Vpp V Vin HIGH level input voltagel 0 7Vpp 2 0 7Vpp 2 0 7Vpp 2 V Vhys hysteresis of Schmitt trigger inputs 0 05Vpp 0 05Vpp V Vou LOW level output voltage 1 open drain or open collector 0 0 4 0 0 4 0 04 V at 3 mA sink current Vpop gt 2V VoLe2 LOW level output voltage 2 open drain or open collector 0 0 2Vpp 0 0 2Vpp V at 2 mA sink currentl Vpp lt 2 V lot LOW level output current VoL 0 4 V 3 3 20 mA VoL 0 6 vil a J 6 mA tof output fall time from ViHmin 250151 20 x 25015 20 x 1207 ns to Vitmax Voo 5 5 VE Voo 5 5 V tsp pulse width of spikes that must be 0 50 8 0 508 ns suppressed by the input filter li input current each I O pin 0 1Vpp lt Vi lt 0 9Vppmax 10 10 10 1019 10 9 1019 uA Ci capacitance for each I O pin t0 10 10 10 pF 1 2 3 4 5 6 7 8 9 10 Some legacy Standard mode devices had fixed input levels o
36. Plus COVICES 2 95 8 dae Ni a e Betas wed bed Hs mode deviceS 2 0 200005 Ultra Fast mode devices Electrical connections of I2C bus devices to the bus lines 0 0c eee eee eee Pull up resistor sizing 4 Operating above the maximum allowable bus capacitance 200 Reduced fgcl 000 eee ee Higher drive outputs 2 4 Bus buffers multiplexers and switches Switched pull up circuit Series protection resistors Input leakage eee eee eee Wiring pattern of the bus lines Abbreviations 0000ee eens continued gt gt NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 63 of 64 NXP Semiconductors UM10204 9 Legal information 00eee eens 62 9 1 Definitions 0 00 eee 62 9 2 Disclaimers snese crassana Ae wk Sk 62 9 3 Trademarks 0 ees 62 10 Contents a eceec ee nuita toe ee neneiia 63 l2C bus specification and user manual Please be aware that important notices concerning this document and the product s described herein have been included in section Legal information NXP B V 2012 For more information please visit http www nxp com For sales office addresses please send an email to salesaddresses nxp com Date of release 9 October 2012 Document identifier UM10204 All rights reserved
37. SCLH signal 10 40 20 80 ns trout rise time of SCLH signal after a 10 80 20 160 ns repeated START condition and after an acknowledge bit tic fall time of SCLH signal 10 40 20 80 ns trDA rise time of SDAH signal 10 80 20 160 ns tioa fall time of SDAH signal 10 80 20 160 ns tsu sTo set up time for STOP condition 160 160 ns C 21 capacitive load for each bus line SDAH and SCLH lines 100 400 pF SDAH SDA line and i 400 400 pF SCLH SCL line VaL noise margin at the LOW level for each connected device 0 1Vpp 0 1Vpp V including hysteresis VhH noise margin at the HIGH level for each connected device 0 2Vpp 0 2Vpp V including hysteresis 1 All values referred to ViH min and ViL max levels see Table 11 2 For bus line loads Cp between 100 pF and 400 pF the timing parameters must be linearly interpolated 3 A device must internally provide a data hold time to bridge the undefined part between Vi and Vj of the falling edge of the SCLH signal An input circuit with a threshold as low as possible for the falling edge of the SCLH signal minimizes this hold time UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 52 of 64 NXP Semiconductors UM10204 l2C bus specification and user manual SDAH SCLH UDA gt pe DA tHD DAT gt I tsu STA M e HD STA
38. a wWrejos p e a 0 2 fqns s zjuawnoop siy u PaplAosd UOHEWOJU Jy pamasa syybu Iy ZLOZ A dXN Y9 JO 8p Table 10 Characteristics of the SDA and SCL bus lines for Standard Fast and Fast mode Plus I C bus devices Symbol Parameter Conditions Standard mode Fast mode Fast mode Plus Unit Min Max Min Max Min Max fscL SCL clock frequency 0 100 0 400 0 1000 kHz tHD STA hold time repeated START condition After this period the first 4 0 0 6 0 26 us clock pulse is generated tLow LOW period of the SCL clock 4 7 1 3 0 5 us THIGH HIGH period of the SCL clock 4 0 0 6 0 26 us tsu sTA set up time for a repeated START 4 7 0 6 0 26 us condition tuD DAT data hold timel2 CBUS compatible masters 5 0 us see Remark in Section 4 1 I2C bus devices ols 4 ols 4 0 us SU DAT data set up time 250 10005 50 ns tr rise time of both SDA and SCL signals 1000 20 300 120 ns ti fall time of both SDA and SCL 300 20 x 300 20 x 120 81 ns signals SIl6171 8 Vpp 5 5 V Vpp 5 5 V tsu sTo set up time for STOP condition 4 0 0 6 0 26 us BUF bus free time between a STOP and 4 7 1 3 0 5 us START condition Cy capacitive load for each bus linell 400 400 550 pF tvp DAT data valid time 3 4514 0 941 0 454 us tvp ack data valid acknowledge timel 2 3 45 41 0 9141 0 4514 us VaL noise margin at the LOW level for each connected device 0 1Vpp 0 1Vpp
39. a HIGH wait state during this time start counting wait HIGH period state counter as reset SCL mbc632 Fig 7 Clock synchronization during the arbitration procedure When all masters concerned have counted off their LOW period the clock line is released and goes HIGH There is then no difference between the master clocks and the state of the SCL line and all the masters start counting their HIGH periods The first master to complete its HIGH period pulls the SCL line LOW again In this way a synchronized SCL clock is generated with its LOW period determined by the master with the longest clock LOW period and its HIGH period determined by the one with the shortest clock HIGH period Arbitration Arbitration like synchronization refers to a portion of the protocol required only if more than one master is used in the system Slaves are not involved in the arbitration procedure A master may start a transfer only if the bus is free Two masters may generate a START condition within the minimum hold time typ sta of the START condition which results in a valid START condition on the bus Arbitration is then required to determine which master will complete its transmission Arbitration proceeds bit by bit During every bit while SCL is HIGH each master checks to see if the SDA level matches what it has sent This process may take many bits Two masters can actually complete an entire transaction without er
40. address is for addressing every device connected to the C bus at the same time However if a device does not need any of the data supplied within the general call structure it can ignore this address If a device does require data from a general call address it behaves as a slave receiver The master does not actually know how many devices are responsive to the general call The second and following bytes are received by every slave receiver capable of handling this data A slave that cannot process one of these bytes must ignore it The meaning of the general call address is always specified in the second byte see Figure 30 LSB o ofo o o olololalx x x x x x x ala first byte second byte general call address 002aag662 Fig 30 General call address format There are two cases to consider e When the least significant bit B is a zero e When the least significant bit B is a one When bit B is a zero the second byte has the following definition 0000 0110 06h Reset and write programmable part of slave address by hardware On receiving this 2 byte sequence all devices designed to respond to the general call address reset and take in the programmable part of their address 0000 0100 04h Write programmable part of slave address by hardware Behaves as above but the device does not reset 0000 0000 00h This code is
41. any devices however are designed to operate properly under this condition 6 Each device connected to the bus is addressable by a unique address A simple master slave relationship exists but it is possible to have multiple identical slaves that can receive and respond simultaneously for example in a group broadcast where all identical devices are configured at the same time understanding that it is impossible to determine that each slave is responsive Refer to individual component data sheets 3 2 8 10 bit addressing 10 bit addressing expands the number of possible addresses Devices with 7 bit and 10 bit addresses can be connected to the same 2C bus and both 7 bit and 10 bit addressing can be used in all bus speed modes The 10 bit slave address is formed from the first two bytes following a START condition S or a repeated START condition Sr The first seven bits of the first byte are the combination 1111 OXX of which the last two bits XX are the two Most Significant Bits MSBs of the 10 bit address the eighth bit of the first byte is the R W bit that determines the direction of the message Although there are eight possible combinations of the reserved address bits 1111 XXX only the four combinations 1111 OXX are used for 10 bit addressing The remaining four combinations 1111 1XX are reserved for future 1 C bus enhancements All information provided in this document is subject to legal disclaimers NXP B V 2012 All rig
42. ated data can be transferred All decisions on auto increment or decrement of previously accessed memory locations etc are taken by the designer of the device Each byte is followed by an acknowledgment bit as indicated by the A or A blocks in the sequence I C bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address even if these START conditions are not positioned according to the proper format ASTART condition immediately followed by a STOP condition void message is an illegal format Many devices however are designed to operate properly under this condition Each device connected to the bus is addressable by a unique address Normally a simple master slave relationship exists but it is possible to have multiple identical slaves that can receive and respond simultaneously for example in a group broadcast This technique works best when using bus switching devices like the PCA9546A where all four channels are on and identical devices are configured at the same time understanding that it is impossible to determine that each slave acknowledges and then turn on one channel at a time to read back each individual device s configuration to confirm the programming Refer to individual component data sheets All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights res
43. be terminated by a STOP P see Figure 24 A HIGH to LOW transition on the USDA line while USCL is HIGH defines a START condition A LOW to HIGH transition on the USDA line while USCL is HIGH defines a STOP condition All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 25 of 64 NXP Semiconductors U M1 0204 3 2 5 l2C bus specification and user manual START condition STOP condition 002aaf145 Fig 24 Definition of START and STOP conditions for UFm I2C bus START and STOP conditions are always generated by the master The bus is considered to be busy after the START condition The bus is considered to be free again a certain time after the STOP condition This bus free situation is specified in Section 6 The bus stays busy if a repeated START Sr is generated instead of a STOP condition In this respect the START S and repeated START Sr conditions are functionally identical For the remainder of this document therefore the S symbol is used as a generic term to represent both the START and repeated START conditions unless Sr is particularly relevant Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware However microcontrollers with no such interface have to sample the USDA line at least twice per clock period to sense the transiti
44. content in this document if provided by an information source outside of NXP Semiconductors In no event shall NXP Semiconductors be liable for any indirect incidental punitive special or consequential damages including without limitation lost profits lost savings business interruption costs related to the removal or replacement of any products or rework charges whether or not such damages are based on tort including negligence warranty breach of contract or any other legal theory Notwithstanding any damages that customer might incur for any reason whatsoever NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document including without limitation specifications and product descriptions at any time and without notice This document supersedes and replaces all information supplied prior to the publication hereof Suitability for use NXP Semiconductors products are not designed authorized or warranted to be suitable for use in life support life critical or safety critical systems or equipment nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury death or severe property or
45. d to a positive supply voltage via a current source or pull up resistor see Figure 3 When the bus is free both lines are HIGH The output stages of devices connected to the bus must have an open drain or open collector to perform the wired AND function Data on the 1 C bus can be transferred at rates of up to 100 kbit s in the Standard mode up to 400 kbit s in the Fast mode up to 1 Mbit s in Fast mode Plus or up to 3 4 Mbit s in the High speed mode The bus capacitance limits the number of interfaces connected to the bus For a single master application the master s SCL output can be a push pull driver design if there are no devices on the bus which would stretch the clock Vpp1 5V 10 Vpp2 VDD3 CMOS CMOS NMOS BIPOLAR Rp Rp SDA J SCL L 002aac860 Vpp2 Vpp3 are device dependent for example 12 V Fig 3 Devices with various supply voltages sharing the same bus All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 8 of 64 NXP Semiconductors U M1 0204 UM10204 3 1 2 3 1 4 I2C bus specification and user manual SDA and SCL logic levels Due to the variety of different technology devices CMOS NMOS bipolar that can be connected to the 2C bus the levels of the logical 0 LOW and 1 HIGH are not fixed and depend on the associated level of Vpp
46. device is allowed to acknowledge the START byte 3 1 16 Bus clear In the unlikely event where the clock SCL is stuck LOW the preferential procedure is to reset the bus using the HW reset signal if your 12C devices have HW reset inputs If the 12C devices do not have HW reset inputs cycle power to the devices to activate the mandatory internal Power On Reset POR circuit If the data line SDA is stuck LOW the master should send nine clock pulses The device that held the bus LOW should release it sometime within those nine clocks If not then use the HW reset or cycle power to clear the bus 3 1 17 Device ID The Device ID field see Figure 20 is an optional 3 byte read only 24 bits word giving the following information e Twelve bits with the manufacturer name unique per manufacturer for example NXP e Nine bits with the part identification assigned by manufacturer for example PCA9698 e Three bits with the die revision assigned by manufacturer for example RevX UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 20 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual wese D ES ES ES ESE mews EEEE erse Bao 002aab942 Fig 20 Device ID field The Device ID is read only hard wired in the device and can be accessed as follows 1 START condition 2 The maste
47. e LOW after reception and acknowledgment of a byte to force the master into a wait state until the slave is ready for the next byte transfer in a type of handshake procedure see Figure 7 On the bit level a device such as a microcontroller with or without limited hardware for the 1 C bus can slow down the bus clock by extending each clock LOW period The speed of any master is adapted to the internal operating rate of this device In Hs mode this handshake feature can only be used on byte level see Section 5 3 2 3 1 10 The slave address and R W bit Data transfers follow the format shown in Figure 9 After the START condition S a slave address is sent This address is seven bits long followed by an eighth bit which is a data direction bit R W a zero indicates a transmission WRITE a one indicates a request for data READ refer to Figure 10 A data transfer is always terminated by a STOP condition P generated by the master However if a master still wishes to communicate on the bus it can generate a repeated START condition Sr and address another slave without first generating a STOP condition Various combinations of read write formats are then possible within such a transfer 1 Si Pi food cet START ADDRESS RW ACK DATA ACK DATA ACK STOP condition condition mbc604 Fig 9 A complete data transfer MSB LSB T T T T T T R W Lo slave address
48. e eighth R W bit However none of them will be addressed because R W 1 for 10 bit devices or the 1111 OXX slave address for 7 bit devices does not match Fig 14 A master transmitter addresses a slave receiver with a 10 bit address 11110XX 0 SLAVE ADDRESS SLAVE ADDRESS an S ist 7BiTs PRWIA1 ong Byte A2 DATA A ee A A write mbc613 11110XX 0 11110XX 1 SLAVE ADDRESS SLAVE ADDRESS SLAVE ADDRESS x S ist 7 BITS R W A1 2nd BYTE A2 Sr ist 7 BITS R W A3 DATA A DATAJA P write read mbc614 Fig 15 A master receiver addresses a slave transmitter with a 10 bit address UM10204 Slave devices with 10 bit addressing react to a general call in the same way as slave devices with 7 bit addressing Hardware masters can transmit their 10 bit address after a general call In this case the general call address byte is followed by two successive bytes containing the 10 bit address of the master transmitter The format is as shown in Figure 15 where the first DATA byte contains the eight least significant bits of the master address All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 16 of 64 NXP Semiconductors U M1 0204 UM10204 3 1 12 3 1 13 I2C bus specification and user
49. eded by a start procedure which is much longer than normal see Figure 31 The start procedure consists of e A START condition S e A START byte 0000 0001 e A Not Acknowledge clock pulse NACK e A repeated START condition Sr aici ey USDA dummy acknowledge HIGH usc T A AAAA 7 8 9 s 7 NACK Sr START byte 0000 0001 gt 002aag663 Fig 31 START byte procedure After the START condition S has been transmitted by a master which requires bus access the START byte 0000 0001 is transmitted Another microcontroller can therefore sample the USDA line at a low sampling rate until one of the seven zeros in the START byte is detected After detection of this LOW level on the USDA line the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization A hardware receiver resets upon receipt of the repeated START condition Sr and therefore ignores the START byte An acknowledge related clock pulse is generated after the START byte This is present only to conform with the byte handling format used on the bus No device is allowed to acknowledge the START byte 3 2 13 Unresponsive slave reset In the unlikely event where the slave becomes unresponsive for example determined through external feedback not through UFm I C bus the preferential procedure is to reset the slave by using the software reset c
50. ence until a NACK has been detected UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 21 of 64 NXP Semiconductors UM10204 UM10204 Table 4 l2C bus specification and user manual Assigned manufacturer IDs Manufacturer bits Company 11 10 0 oo E e E E E m E L E IE I E mI E I E Il E I oo O GrG O O G D a a Ora ooo oo0ooo 0 000 00 0 aeee 0 0 o0 NXP Semiconductors NXP Semiconductors reserved NXP Semiconductors reserved NXP Semiconductors reserved Ramtron International Analog Devices STMicroelectronics ON Semiconductor Sprintek Corporation ESPROS Photonics AG Fujitsu Semiconductor Flir O gt Micro Atmel oooooo O O O O O O O oo0oo0oo0oo0oo0oo0oo0oo0oo0oo0oo0o oO STOO OOOO OOD OO WO Oo FP O0OO OOOO OO IO oO PTO OOOO OOOO OO oO 3 9 32 tH ODDO OOO Ow 000 0A R74 4H DOO ON POF olol olola A Oo a ol o ol o o 0 200 oO oO Designers of new 12C devices who want to implement the device ID feature should contact NXP at i2c support nxp com to have a unique manufacturer ID assigned All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 22 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user ma
51. equipment SMBus also has a High Power version 2 0 that includes a 4 mA sink current that cannot be driven by 12C chips unless the pull up resistor is sized to 1 C bus levels I2C SMBus compliancy SMBus and I C protocols are basically the same A SMBus master is able to control 12C devices and vice versa at the protocol level The SMBus clock is defined from 10 kHz to 100 kHz while I2C can be 0 Hz to 100 kHz 0 Hz to 400 kHz 0 Hz to 1 MHz and 0 Hz to 3 4 MHz depending on the mode This means that an C bus running at less than 10 kHz is not SMBus compliant since the SMBus devices may time out All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 32 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual Logic levels are slightly different also TTL for SMBus LOW 0 8 V and HIGH 2 1 V versus the 30 70 Vpp CMOS level for 12C This is not a problem if Vpp gt 3 0 V If the 12C device is below 3 0 V then there could be a problem if the logic HIGH LOW levels are not properly recognized 4 2 2 Time out feature SMBus has a time out feature which resets devices if a communication takes too long This explains the minimum clock frequency of 10 kHz to prevent locking up the bus 12C can be a DC bus meaning that a slave device stretches the master clock when performing some routine while the maste
52. ers of Hs mode devices incorporate slope control of the falling edges of the SDAH and SCLH signals Figure 32 shows the physical I2C bus configuration in a system with only Hs mode devices Pins SDA and SCL on the master devices are only used in mixed speed bus systems and are not connected in an Hs mode only system In such cases these pins can be used for other functions Optional series resistors Rg protect the I O stages of the 1 C bus devices from high voltage spikes on the bus lines and minimize ringing and interference Pull up resistors Rp maintain the SDAH and SCLH lines at a HIGH level when the bus is free and ensure that the signals are pulled up from a LOW to a HIGH level within the required rise time For higher capacitive bus line loads gt 100 pF the resistor Rp can be replaced by external current source pull ups to meet the rise time requirements Unless All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 37 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual proceeded by an acknowledge bit the rise time of the SCLH clock pulses in Hs mode transfers is shortened by the internal current source pull up circuit MCS of the active master VDD Rp Rp SDAH lt gt
53. ers such as temperatures voltages fans and chassis intrusion IPMI provides general system management functions such as automatic alerting automatic system shutdown and restart remote restart and power control The standardized interface to intelligent platform management hardware aids in prediction and early monitoring of hardware failures as well as diagnosis of hardware problems This standardized bus and protocol for extending management control monitoring and event delivery within the chassis e I2C based e Multi master e Simple Request Response Protocol e Uses IPMI Command sets e Supports non IPMI devices e Physically 12C but write only master capable devices hot swap not required e Enables the Baseboard Management Controller BMC to accept IPMI request messages from other management controllers in the system e Allows non intelligent devices as well as management controllers on the bus e BMC serves as a controller to give system software access to IPMB Hardware implementation is isolated from software implementation so that new sensors and events can then be added without any software changes For more information refer to www nxp com redirect intel com design servers ipmi All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 34 of 64 NXP Semiconductors U M1 0204 4 5 4 6 I2C bus specificatio
54. erved User manual Rev 5 9 October 2012 14 of 64 NXP Semiconductors U M1 0204 UM10204 3 1 11 I2C bus specification and user manual S SLAVE ADDRESS R W A DATA A DATA A A p data transferred 0 write n bytes acknowledge from master to slave A acknowledge SDA LOW A not acknowledge SDA HIGH from slave to master S START condition P STOP condition mbc605 Fig 11 A master transmitter addressing a slave receiver with a 7 bit address the transfer direction is not changed 1 S SLAVE ADDRESS RW A DATA A DATA A P data transferred __ read n bytes acknowledge mbc606 Fig 12 A master reads a slave immediately after the first byte S SLAVE ADDRESS RAW A DATA A A Sr SLAVE ADDRESS R W A DATA A A P nbytes nbytes read or write ack RACK read or write direction of transfer may change at this point Sr repeated START condition not shaded because p k transfer direction of data and acknowledge bits depends on R W bits mbc607 Fig 13 Combined format 10 bit addressing 10 bit addressing expands the number of possible addresses Devices with 7 bit and 10 bit addresses can be connected to the same 12C bus and both 7 bit and 10 bit addressing can be used i
55. esigning digital control circuits Here are some of the features of the I C bus e Only two bus lines are required a serial data line SDA and a serial clock line SCL e Each device connected to the bus is software addressable by a unique address and simple master slave relationships exist at all times masters can operate as master transmitters or as master receivers e Itis atrue multi master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer e Serial 8 bit oriented bidirectional data transfers can be made at up to 100 kbit s in the Standard mode up to 400 kbit s in the Fast mode up to 1 Mbit s in Fast mode Plus or up to 3 4 Mbit s in the High speed mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 3 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual e Serial 8 bit oriented unidirectional data transfers up to 5 Mbit s in Ultra Fast mode e On chip filtering rejects spikes on the bus data line to preserve data integrity The number of ICs that can be connected to the same bus is limited only by a maximum bus capacitance More capacitance may be allowed under some conditions Refer to Section 7 2 Figure 1 shows an example of I2C bus applications 12C 12C A D or D A General Purpose Conve
56. f Vi 1 5 V and Viy 3 0 V Refer to component data sheets Maximum Vy Vppimax 0 5 V or 5 5 V which ever is lower See component data sheets The same resistor value to drive 3 mA at 3 0 V Vpp provides the same RC time constant when using lt 2 V Vpp with a smaller current draw In order to drive full bus load at 400 kHz 6 mA Io is required at 0 6 V VoL Parts not meeting this specification can still function but not at 400 kHz and 400 pF The maximum t for the SDA and SCL bus lines quoted in Table 10 300 ns is longer than the specified maximum tot for the output stages 250 ns This allows series protection resistors Rg to be connected between the SDA SCL pins and the SDA SCL bus lines as shown in Figure 45 without exceeding the maximum specified ty Necessary to be backwards compatible with Fast mode In Fast mode Plus fall time is specified the same for both output stage and bus timing If series resistors are used designers should allow for this when considering bus timing Input filters on the SDA and SCL inputs suppress noise spikes of less than 50 ns If Vpp is switched off I O pins of Fast mode and Fast mode Plus devices must not obstruct the SDA and SCL lines Special purpose devices such as multiplexers and switches may exceed this capacitance because they connect multiple paths together jenuew Jasn pue uoneoyiseds snq dzI vozo LINN SJOJONPUODIWIIS dXN v0zZOlLWN jenuew sn ZLOZ 4990390 6 S 34 s
57. h and tolerance for slow rise and fall times allow the use of larger bus capacitance as long as set up minimum LOW time and minimum HIGH time for Fast mode Plus are all satisfied and the fall time and rise time do not exceed the 300 ns t and 1 us t specifications of Standard mode Bus speed can be traded against load capacitance to increase the maximum capacitance by about a factor of ten All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 36 of 64 NXP Semiconductors U M1 0204 UM10204 l2C bus specification and user manual 5 3 Hs mode 5 3 1 High speed mode Hs mode devices offer a quantum leap in I C bus transfer speeds Hs mode devices can transfer information at bit rates of up to 3 4 Mbit s yet they remain fully downward compatible with Fast mode Plus Fast or Standard mode F S devices for bidirectional communication in a mixed speed bus system With the exception that arbitration and clock synchronization is not performed during the Hs mode transfer the same serial bus protocol and data format is maintained as with the F S mode system High speed transfer To achieve a bit transfer of up to 3 4 Mbit s the following improvements have been made to the regular 1 C bus specification e Hs mode master devices have an open drain output buffer for the SDAH signal and a combination of an open drain pull down and current
58. he ninth clock pulse The ninth data bit is always driven HIGH 1 Slave devices are not allowed to drive the SDA line at any time 3 2 7 The slave address and R W bit Data transfers follow the format shown in Figure 26 After the START condition S a slave address is sent This address is seven bits long followed by an eighth bit which is a data direction bit W a zero indicates a transmission WRITE a one indicates a request for data READ and is not supported by UFm except for the START byte Section 3 2 12 since the communication is unidirectional refer to Figure 27 A data transfer is always terminated by a STOP condition P generated by the master However if a master still wishes to communicate on the bus it can generate a repeated START condition Sr and address another slave without first generating a STOP condition e O LY Fig 26 A complete UFm data transfer I S 1 P 1 I 1 I START ADDRESS WwW NACK DATA NACK DATA NACK STOP condition condition 002aag658 UM10204 MSB LSB T T T T T T _ W j i i L i i C slave address 002aag659 Fig 27 The first byte after the START procedure The UFm data transfer format is e Master transmitter transmits to slave receiver The transfer direction is not changed see Figure 28 The master never acknowledges because it never receives any data but generates the 1 on the
59. hts reserved User manual Rev 5 9 October 2012 28 of 64 NXP Semiconductors U M1 0204 UM10204 3 2 9 l2C bus specification and user manual Only the write format previously described for 7 bit addressing is possible with 10 bit addressing Detailed here e Master transmitter transmits to slave receiver with a 10 bit slave address The transfer direction is not changed see Figure 29 When a 10 bit address follows a START condition each slave compares the first seven bits of the first byte of the slave address 1111 OXX with its own address and tests if the eighth bit R W direction bit is 0 W All slaves that found a match compare the eight bits of the second byte of the slave address XXXX XXXX with their own addresses but only one slave finds a match The matching slave remains addressed by the master until it receives a STOP condition P or a repeated START condition Sr followed by a different slave address 11110XX 0 SLAVE ADDRESS SLAVE ADDRESS S ia BITS WIA ond BYTE A DATA A DATA NA P write 002aag661 Fig 29 A master transmitter addresses a slave receiver with a 10 bit address The START byte 0000 0001 01h can precede the 10 bit addressing in the same way as for 7 bit addressing see Section 3 2 12 Reserved addresses in UFm The UFm C bus has a different physical layer than the other I2C bus modes Therefore the available slave add
60. ication with the master 3 During the transfer the receiver gets data or commands that it does not understand 4 During the transfer the receiver cannot receive any more data bytes 5 A master receiver must signal the end of the transfer to the slave transmitter All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 10 of 64 NXP Semiconductors U M1 0204 UM10204 3 1 7 l2C bus specification and user manual Clock synchronization Two masters can begin transmitting on a free bus at the same time and there must be a method for deciding which takes control of the bus and complete its transmission This is done by clock synchronization and arbitration In single master systems clock synchronization and arbitration are not needed Clock synchronization is performed using the wired AND connection of I C interfaces to the SCL line This means that a HIGH to LOW transition on the SCL line causes the masters concerned to start counting off their LOW period and once a master clock has gone LOW it holds the SCL line in that state until the clock HIGH state is reached see Figure 7 However if another clock is still within its LOW period the LOW to HIGH transition of this clock may not change the state of the SCL line The SCL line is therefore held LOW by the master with the longest LOW period Masters with shorter LOW periods enter
61. ice ID 4c oho s eh BBS oe 31 Other uses of the I2C bus communications protocol occ ieee 32 CBUS compatibility 32 SMBus System Management Bus 32 I2C SMBus compliancy 005 32 All information provided in this document is subject to legal disclaimers 4 2 2 4 2 3 4 3 4 4 4 5 Time out feature 0000 Differences between SMBus 1 0 and PMBus Power Management Bus Intelligent Platform Management Interface IPMD 2 5 4 4 t 22 Ge cd pohaeeact ead ae de wad Advanced Telecom Computing Architecture ATCA ecrire cress rodeo ieee ba Display Data Channel DDC Bus speeds 2 00 cece eee eee ene Fast mode 000 000 eee a E Fast mode Plus 220005 HS MO06 2 2 ce2kehesoneau tend ee nee High speed transfer 0 4 Serial data format in Hs mode Switching from F S mode to Hs mode and DACK a4 cette aeea chuamae wae ca lne tare Hs mode devices at lower speed modes Mixed speed modes on one serial bus SYSTEM acosa oh eoa anp E a ane ened dew Standard Fast mode and Fast mode Plus transfer in a mixed speed bus system Hs mode transfer in a mixed speed bus SYSTEM eee ee eee Timing requirements for the bridge in a mixed speed bus system Ultra Fast mode 2 0005 Electrical specifications and timing for I O stages and bus lines 4 Standard Fast and Fast mode
62. igure 36 interconnects corresponding serial bus lines forming one serial bus system As no master code 0000 1XXX is transmitted the current source pull up circuits stay disabled and all output stages are open drain All devices including Hs mode devices communicate with each other according to the protocol format and speed of the F S mode C bus specification Hs mode transfer in a mixed speed bus system Figure 37 shows the timing diagram of a complete Hs mode transfer which is invoked by a START condition a master code and a not acknowledge A at F S mode speed Although this timing diagram is split in two parts it should be viewed as one timing diagram were time point ty is a common point for both parts The master code is recognized by the bridge in the active or non active master see Figure 36 The bridge performs the following actions 1 Between t and ty see Figure 37 transistor TR1 opens to separate the SDAH and SDA lines after which transistor TR3 closes to pull down the SDA line to Vss 2 When both SCLH and SCL become HIGH ty in Figure 37 transistor TR2 opens to separate the SCLH and SCL lines TR2 must be opened before SCLH goes LOW after Sr Hs mode transfer starts after ty with a repeated START condition Sr During Hs mode transfer the SCL line stays at a HIGH and the SDA line at a LOW steady state level and so is prepared for the transfer of a STOP condition P After each acknowledge A or not ackno
63. ions are functionally identical For the remainder of this document therefore the S symbol is used as a generic term to represent both the START and repeated START conditions unless Sr is particularly relevant All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 9 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual Detection of START and STOP conditions by devices connected to the bus is easy if they incorporate the necessary interfacing hardware However microcontrollers with no such interface have to sample the SDA line at least twice per clock period to sense the transition Byte format Every byte put on the SDA line must be eight bits long The number of bytes that can be transmitted per transfer is unrestricted Each byte must be followed by an Acknowledge bit Data is transferred with the Most Significant Bit MSB first see Figure 6 If a slave cannot receive or transmit another complete byte of data until it has performed some other function for example servicing an internal interrupt it can hold the clock line SCL LOW to force the master into a wait state Data transfer then continues when the slave is ready for another byte of data and releases clock line SCL Fig 6 sa NL ZX OX XX A S AXX am Gam Gi Sor Sr START or repeated START condition Data transfer on the I2C bu
64. ip enable signals Additionally a microcontroller that includes an 12C interface is more successful in the marketplace due to the wide variety of existing peripheral devices available 3 The I2C bus protocol 3 1 Standard mode Fast mode and Fast mode Plus I C bus protocols Two wires serial data SDA and serial clock SCL carry information between the devices connected to the bus Each device is recognized by a unique address whether it is a microcontroller LCD driver memory or keyboard interface and can operate as either a transmitter or receiver depending on the function of the device An LCD driver may be only a receiver whereas a memory can both receive and transmit data In addition to transmitters and receivers devices can also be considered as masters or slaves when performing data transfers see Table 1 A master is the device which initiates a data transfer on the bus and generates the clock signals to permit that transfer At that time any device addressed is considered a slave Table 1 Definition of I C bus terminology Term Description Transmitter the device which sends data to the bus Receiver the device which receives data from the bus Master the device which initiates a transfer generates clock signals and terminates a transfer Slave the device addressed by a master Multi master more than one master can attempt to control the bus at the same time without corrupting the message Arbitration procedu
65. iple of 10 MHz can be used by an Hs mode master to generate the SCLH signal There are no limits for maximum HIGH and LOW periods of the SCLH clock and there is no limit for a lowest bit rate Timing parameters are independent for capacitive load up to 100 pF for each bus line allowing the maximum possible bit rate of 3 4 Mbit s At a higher capacitive load on the bus lines the bit rate decreases gradually The timing parameters for a capacitive bus load of 400 pF are specified in Table 12 allowing a maximum bit rate of 1 7 Mbit s For UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 50 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual capacitive bus loads between 100 pF and 400 pF the timing parameters must be interpolated linearly Rise and fall times are in accordance with the maximum propagation time of the transmission lines SDAH and SCLH to prevent reflections of the open ends Table 11 Characteristics of the SDAH SCLH SDA and SCL I O stages for Hs mode I2C bus devices Symbol Parameter Conditions Hs mode Unit Min Max Vib LOW level input voltage 0 5 0 3Vpplt V Vin HIGH level input voltage 0 7Vpp Vpp 0 521 V Vhys hysteresis of Schmitt trigger inputs 0 1Vppl V VoL LOW level output voltage open drain at 3 mA sink current at SDAH SDA and SCLH Vpop gt 2V 0 0 4 V Vpo
66. mode device is switched off the SDA and SCL I O pins must be floating so that they do not obstruct the bus lines The external pull up devices connected to the bus lines must be adapted to accommodate the shorter maximum permissible rise time for the Fast mode I C bus For bus loads up to 200 pF the pull up device for each bus line can be a resistor for bus loads between 200 pF and 400 pF the pull up device can be a current source 3 mA max or a switched resistor circuit see Section 7 2 4 Fast mode Plus Fast mode Plus Fm devices offer an increase in 2C bus transfer speeds and total bus capacitance Fm devices can transfer information at bit rates of up to 1 Mbit s yet they remain fully downward compatible with Fast or Standard mode devices for bidirectional communication in a mixed speed bus system The same serial bus protocol and data format is maintained as with the Fast or Standard mode system Fm devices also offer increased drive current over Fast or Standard mode devices allowing them to drive longer and or more heavily loaded buses so that bus buffers do not need to be used The drivers in Fast mode Plus parts are strong enough to satisfy the Fast mode Plus timing specification with the same 400 pF load as Standard mode parts To be backward compatible with Standard mode they are also tolerant of the 1 us rise time of Standard mode parts In applications where only Fast mode Plus parts are present the high drive strengt
67. more than one UFm master to the UFm C bus is not allowed due to bus contention on the push pull outputs If an additional master is required in the system it must be fully isolated from the other master that is with a true one hot MUX as only one master is allowed on the bus at a time Generation of clock signals on the UFm I C bus is always the responsibility of the master device that is the master generates the clock signals when transferring data on the bus Bus clock signals from a master cannot be altered by a slave device with clock stretching and the process of arbitration and clock synchronization does not exist within the UFm 12C bus Table 6 summarizes the use of mandatory and optional portions of the UFm C bus specification Table 6 Applicability of I2 C bus features to UFm M mandatory O optional n p not possible Feature Configuration Single master START condition M STOP condition M Acknowledge n p Synchronization n p Arbitration n p Clock stretching n p 7 bit slave address M 10 bit slave address O General Call address O Software Reset O START byte O Device ID n p All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 24 of 64 NXP Semiconductors U M1 0204 UM10204 3 2 1 3 2 2 3 2 3 3 2 4 l2C bus specification and user manual USDA and USCL signals B
68. n all bus speed modes Currently 10 bit addressing is not being widely used The 10 bit slave address is formed from the first two bytes following a START condition S or a repeated START condition Sr The first seven bits of the first byte are the combination 1111 0XX of which the last two bits XX are the two Most Significant Bits MSB of the 10 bit address the eighth bit of the first byte is the R W bit that determines the direction of the message Although there are eight possible combinations of the reserved address bits 1111 XXX only the four combinations 1111 0XX are used for 10 bit addressing The remaining four combinations 1111 1XX are reserved for future 1 C bus enhancements All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 15 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual All combinations of read write formats previously described for 7 bit addressing are possible with 10 bit addressing Two are detailed here e Master transmitter transmits to slave receiver with a 10 bit slave address The transfer direction is not changed see Figure 14 When a 10 bit address follows a START condition each slave compares the first seven bits of the first byte of the slave address 1111 OXX with its own address and tests if the eighth bit R W direction bit is 0 It is possible that more than
69. n and user manual Advanced Telecom Computing Architecture ATCA Advanced Telecom Computing Architecture ATCA is a follow on to Compact PCI cPCl providing a standardized form factor with larger card area larger pitch and larger power supply for use in advanced rack mounted telecom hardware It includes a fault tolerant scheme for thermal management that uses I2C bus communications between boards Advanced Telecom Computing Architecture ATCA is backed by more than 100 companies including many of the large players such as Intel Lucent and Motorola There are two general compliant approaches to an ATCA compliant fan control the first is an Intelligent FRU Field Replaceable Unit which means that the fan control would be directly connected to the IPMB Intelligent Platform Management Bus the second is a Managed or Non intelligent FRU One requirement is the inclusion of hardware and software to manage the dual C buses This requires an on board isolated supply to power the circuitry a buffered dual I2C bus with rise time accelerators and 3 state capability The 12C controller must be able to support a multi master C dual bus and handle the standard set of fan commands outlined in the protocol In addition on board temperature reporting tray capability reporting fan turn off capabilities and non volatile storage are required For more information refer to www nxp com redirect picmg org v2internal newinitiative Display
70. nd electrical specifications for the I2C bus in each of its operating modes Designers of I2 C compatible chips should use this document as a reference and ensure that new devices meet all limits specified in this document Designers of systems that include 2C devices should review this document and also refer to individual component data sheets 2 1I C bus features UM10204 In consumer electronics telecommunications and industrial electronics there are often many similarities between seemingly unrelated designs For example nearly every system includes e Some intelligent control usually a single chip microcontroller e General purpose circuits like LCD and LED drivers remote I O ports RAM EEPROM real time clocks or A D and D A converters e Application oriented circuits such as digital tuning and signal processing circuits for radio and video systems temperature sensors and smart cards To exploit these similarities to the benefit of both systems designers and equipment manufacturers as well as to maximize hardware efficiency and circuit simplicity Philips Semiconductors now NXP Semiconductors developed a simple bidirectional 2 wire bus for efficient inter IC control This bus is called the Inter IC or I C bus All 1 C bus compatible devices incorporate an on chip interface which allows them to communicate directly with each other via the I2C bus This design concept solves the many interfacing problems encountered when d
71. ng specification Portable designs with sensitivity to supply current consumption can use a value toward the higher end of the range in order to limit Ipp Operating above the maximum allowable bus capacitance Bus capacitance limit is specified to limit rise time reductions and allow operating at the rated frequency While most designs can easily stay within this limit some applications may exceed it There are several strategies available to system designers to cope with excess bus capacitance e Reduced fsc Section 7 2 1 The bus may be operated at a lower speed lower fsc e Higher drive outputs Section 7 2 2 Devices with higher drive current such as those rated for Fast mode Plus can be used PCAQ6xx e Bus buffers Section 7 2 3 There are a number of bus buffer devices available that can divide the bus into segments so that each segment has a capacitance below the allowable limit such as the PCA9517 bus buffer or the PCA9546A switch e Switched pull up circuit Section 7 2 4 A switched pull up circuit can be used to accelerate rising edges by switching a low value pull up alternately in and out when needed Reduced fsc To determine a lower allowable bus operating frequency begin by finding the tLow and tuicH of the most limiting device on the bus Refer to individual component data sheets for these values Actual rise time t depends on the RC time constant The most limiting fall time t depends on the lowest outpu
72. ninth bit for the slave to conform to the 1 C bus protocol All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 27 of 64 NXP Semiconductors U M1 0204 UM10204 l2C bus specification and user manual S SLAVE ADDRESS W A DATA A DATA A P data transferred 0 write n bytes not acknowledge from master to slave A not acknowledge USDA HIGH S START condition P STOP condition 002aag660 Fig 28 A master transmitter addressing a slave receiver with a 7 bit address Notes 1 Individual transaction or repeated START formats addressing multiple slaves in one transaction can be used After the START condition and slave address is repeated data can be transferred 2 All decisions on auto increment or decrement of previously accessed memory locations etc are taken by the designer of the device 3 Each byte is followed by a Not Acknowledgment bit as indicated by the A blocks in the sequence 4 l2C bus compatible devices must reset their bus logic on receipt of a START or repeated START condition such that they all anticipate the sending of a slave address even if these START conditions are not positioned according to the proper format 5 A START condition immediately followed by a STOP condition void message is an illegal format M
73. not allowed to be used as the second byte Sequences of programming procedure are published in the appropriate device data sheets The remaining codes have not been fixed and devices must ignore them When bit B is a one the 2 byte sequence is ignored Software reset Following a General Call 0000 0000 sending 0000 0110 06h as the second byte causes a software reset This feature is optional and not all devices respond to this command On receiving this 2 byte sequence all devices designed to respond to the general call address reset and take in the programmable part of their address START byte Microcontrollers can be connected to the I2C bus in two ways A microcontroller with an on chip hardware 2C bus interface can be programmed to be only interrupted by requests from the bus When the device does not have such an interface it must constantly monitor the bus via software Obviously the more times the microcontroller monitors or polls the bus the less time it can spend carrying out its intended function There is therefore a speed difference between fast hardware devices and a relatively slow microcontroller which relies on software polling All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 30 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual In this case data transfer can be prec
74. nual 3 2 Ultra Fast mode I2C bus protocol The UFm C bus is a 2 wire push pull serial bus that operates from DC to 5 MHz transmitting data in one direction It is most useful for speeds greater than 1 MHz to drive LED controllers and other devices that do not need feedback The UFm 2C bus protocol is based on the standard I C bus protocol that consists of a START slave address command bit ninth clock and a STOP bit The command bit is a write only and the data bit on the ninth clock is driven HIGH ignoring the ACK cycle due to the unidirectional nature of the bus The 2 wire push pull driver consists of a UFm serial clock USCL and serial data USDA Slave devices contain a unique address whether it is a microcontroller LCD driver LED controller GPO and operate only as receivers An LED driver may be only a receiver and can be supported by UFm whereas a memory can both receive and transmit data and is not supported by UFm Since UFm C bus uses push pull drivers it does not have the multi master capability of the wired AND open drain Sm Fm and Fm C buses In UFm a master is the only device that initiates a data transfer on the bus and generates the clock signals to permit that transfer All other devices addressed are considered slaves Table 5 Definition of UFm I2C bus terminology Term Description Transmitter the device that sends data to the bus Receiver the device that receives data from the bus Master
75. o input filter Only the active master can enable its current source pull up circuit 4 Dotted transistors are optional open drain outputs which can stretch the serial clock signal SCL or SCLH Fig 36 Bus system with transfer at Hs mode and F S mode speeds Communication bit rates in a mixed speed bus system Serial bus system configuration Hs Fast Table 8 Transfer between Fast Standard UM10204 Hs lt Hs Hs Fast Hs Standard Fast lt Standard Fast lt gt Fast Standard 0 to 3 4 Mbit s 0 to 100 kbit s 0 to 100 kbit s 0 to 100 kbit s 0 to 100 kbit s Standard gt Standard 0 to 100 kbit s Hs Fast 0 to 3 4 Mbit s 0 to 400 kbit s 0 to 400 kbit s Hs Standard 0 to 3 4 Mbit s 0 to 100 kbit s 0 to 100 kbit s 0 to 100 kbit s 0 to 100 kbit s 0 to 100 kbit s Remark Table 8 assumes that the Hs devices are isolated from the Fm and Sm devices when operating at 3 4 Mbit s The bus speed is always constrained to the maximum communication rate of the slowest device attached to the bus All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 43 of 64 NXP Semiconductors U M1 0204 UM10204 5 3 6 5 3 7 1 C bus specification and user manual Standard Fast mode and Fast mode Plus transfer in a mixed speed bus system The bridge shown in F
76. ommand or the hardware reset signal If the slaves do not support these features then cycle power to the devices to activate the mandatory internal Power On Reset POR circuit 3 2 14 Device ID The Device ID field is not supported in UFm UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 31 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual 4 Other uses of the I2C bus communications protocol UM10204 4 1 4 2 4 2 1 The C bus is used as the communications protocol for several system architectures These architectures have added command sets and application specific extensions in addition to the base IC specification In general simple 1 C bus devices such as I O extenders could be used in any one of these architectures since the protocol and physical interfaces are the same CBUS compatibility CBUS receivers can be connected to the Standard mode I C bus However a third bus line called DLEN must then be connected and the acknowledge bit omitted Normally 12C transmissions are sequences of 8 bit bytes CBUS compatible devices have different formats In a mixed bus structure 1 C bus devices must not respond to the CBUS message For this reason a special CBUS address 0000 001X to which no I2C bus compatible device responds has been reserved After transmission of the CBUS addres
77. on Byte format Every byte put on the USDA line must be eight bits long The number of bytes that can be transmitted per transfer is unrestricted The master drives the USDA HIGH after each byte during the Acknowledge cycle Data is transferred with the Most Significant Bit MSB first see Figure 25 A slave is not allowed to hold the clock LOW if it cannot receive another complete byte of data or while it is performing some other function for example servicing an internal interrupt wT LZ XOXOXO OOD OD USCL Sor Sr VJ INVA 2X LLL 8 9 1 2 3t07 8 9 Sr or P Master drives the line HIGH on 9th clock cycle Slave never drives the USDA line SETATI NACK NACK BESTER START or STOP or repeated START byte complete repeated START condition interrupt within slave condition 002aag657 Fig 25 Data transfer on the UFm I C bus UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 26 of 64 NXP Semiconductors U M1 0204 I2C bus specification and user manual 3 2 6 Acknowledge ACK and Not Acknowledge NACK Since the slaves are not able to respond the ninth clock cycle the ACK and NACK are not required However the clock cycle is preserved in the UFm to be compatible with the l2C bus protocol The ACK and NACK are also referred to as the ninth clock cycle The master generates all clock pulses including t
78. on changed from reserved for future purposes to device ID deleted old third paragraph e Section 3 1 17 Device ID in numbered list following second paragraph START command changed to START condition in numbered list following second paragraph STOP command changed to STOP condition in Remark paragraph NACK command changed to NACK Table 4 Assigned manufacturer IDs updated e Section 3 2 8 10 bit addressing fifth paragraph bullet item NA1 changed to W in third sentence deleted NA2 from fourth sentence Figure 29 A master transmitter addresses a slave receiver with a 10 bit address modified e Section 3 2 9 Reserved addresses in UFm deleted old third paragraph e Section 7 2 1 Reduced fsc third paragraph corrected from 30 to 30 or 70 to 70 to 30 to 70 or 70 to 30 v 4 20120213 User manual Rev 4 v 3 20070619 Many of today s applications require longer buses and or faster speeds Fast mode Plus was introduced to meet this need by increasing drive strength by as much as 10x and increasing the data rate to 1 Mbit s while maintaining downward compatibility to Fast mode and Standard mode speeds and software commands v2 1 2000 Version 2 1 of the 1 C bus specification v2 0 1998 The I2C bus has become a de facto world standard that is now implemented
79. one device finds a match and generate an acknowledge A1 All slaves that found a match compare the eight bits of the second byte of the slave address XXXX XXXX with their own addresses but only one slave finds a match and generates an acknowledge A2 The matching slave remains addressed by the master until it receives a STOP condition P or a repeated START condition Sr followed by a different slave address Master receiver reads slave transmitter with a 10 bit slave address The transfer direction is changed after the second R W bit Figure 15 Up to and including acknowledge bit A2 the procedure is the same as that described for a master transmitter addressing a slave receiver After the repeated START condition Sr a matching slave remembers that it was addressed before This slave then checks if the first seven bits of the first byte of the slave address following Sr are the same as they were after the START condition S and tests if the eighth R W bit is 1 If there is a match the slave considers that it has been addressed as a transmitter and generates acknowledge A3 The slave transmitter remains addressed until it receives a STOP condition P or until it receives another repeated START condition Sr followed by a different slave address After a repeated START condition Sr all the other slave devices will also compare the first seven bits of the first byte of the slave address 1111 OXX with their own addresses and test th
80. ontroller A master addresses microcontroller B slave microcontroller A master transmitter sends data to microcontroller B slave receiver microcontroller A terminates the transfer 2 lf microcontroller A wants to receive information from microcontroller B microcontroller A master addresses microcontroller B slave microcontroller A master receiver receives data from microcontroller B slave transmitter microcontroller A terminates the transfer Even in this case the master microcontroller A generates the timing and terminates the transfer The possibility of connecting more than one microcontroller to the I2C bus means that more than one master could try to initiate a data transfer at the same time To avoid the chaos that might ensue from such an event an arbitration procedure has been developed This procedure relies on the wired AND connection of all 12C interfaces to the I C bus If two or more masters try to put information onto the bus the first to produce a one when the other produces a zero loses the arbitration The clock signals during arbitration are a synchronized combination of the clocks generated by the masters using the wired AND connection to the SCL line for more detailed information concerning arbitration see Section 3 1 8 Generation of clock signals on the I C bus is always the responsibility of master devices each master generates its own clock signals when tran
81. oth USDA and USCL are unidirectional lines with push pull outputs When the bus is free both lines are pulled HIGH by the upper transistor of the output stage Data on the I2C bus can be transferred at rates of up to 5000 kbit s in the Ultra Fast mode The number of interfaces connected to the bus is limited by the bus loading reflections from cable ends connectors and stubs VpD IO USCL or USDA pin 002aag655 Fig 22 Simplified schematic of USCL USDA outputs USDA and USCL logic levels Due to the variety of different technology devices CMOS NMOS bipolar that can be connected to the 1 C bus the levels of the logical 0 LOW and 1 HIGH are not fixed and depend on the associated level of Vpp Input reference levels are set as 30 and 70 of Vpp Vit is 0 3Vpp and V is 0 7Vpp See Figure 40 timing diagram See Section 6 for electrical specifications Data validity The data on the USDA line must be stable during the HIGH period of the clock The HIGH or LOW state of the data line can only change when the clock signal on the USCL line is LOW see Figure 23 One clock pulse is generated for each data bit transferred USDA USCL data line change stable of data data valid allowed 002aaf113 Fig 23 Bit transfer on the UFm I2C bus START and STOP conditions Both data and clock lines remain HIGH when the bus is not busy All transactions begin with a START S and can
82. own address identifying itself to the system see Figure 17 S 00000000 A MASTER ADDRESS 1 A DATA A DATA A P B ak lt a gt eg SS general second n bytes ack call address byte mbc624 Fig 17 Data transfer from a hardware master transmitter The seven bits remaining in the second byte contain the address of the hardware master This address is recognized by an intelligent device for example a microcontroller connected to the bus which then accepts the information from the hardware master If the hardware master can also act as a slave the slave address is identical to the master address All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 18 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual In some systems an alternative could be that the hardware master transmitter is set in the slave receiver mode after the system reset In this way a system configuring master can tell the hardware master transmitter which is now in slave receiver mode to which address data must be sent see Figure 18 After this programming procedure the hardware master remains in the master transmitter mode SLAVE ADDR H W MASTER R W A DUMP ADDR FOR H W MASTER X write 002aac885 n gt v
83. p lt 2 V 0 0 2Vpp V Ront transfer gate on resistance for Vor level lop 3 mA 50 Q currents between SDA and SDAH or SCL and SCLH Ronn transfer gate on resistance between both signals SDA and SDAH or SCL 50 kQ SDA and SDAH or SCL and SCLH and SCLH at Vpp level los pull up current of the SCLH SCLH output levels between 0 3Vpp and 3 12 mA current source 0 7Vpp tre rise time of SCLH signal output rise time current source enabled with an external pull up current source of 3 mA capacitive load from 10 pF to 100 pF 10 40 ns capacitive load of 400 pFIS 20 80 ns tic fall time of SCLH signal output fall time current source enabled with an external pull up current source of 3 mA capacitive load from 10 pF to 100 pF 10 40 ns capacitive load of 400 pF 8 20 80 ns DA fall time of SDAH signal capacitive load from 10 pF to 100 pF 10 80 ns capacitive load of 400 pF 8 20 160 ns tsp pulse width of spikes that must be SDAH and SCLH 0 10 ns suppressed by the input filter 41 input current each I O pin input voltage between 0 1Vpp and 10 uA 0 9Vpp Ci capacitance for each I O pinl5l 10 pF 1 Devices that use non standard supply voltages which do not conform to the intended I2C bus system levels must relate their input levels to the Vpp voltage to which the pull up resistors Rp are connected 2 Devices that offer the level shift function must tolerate a maximum input voltage of 5 5 V at SDA and SCL 3 For capacitive bus loads
84. party customer s Customer is responsible for doing all necessary testing for the customer s applications and products using NXP Semiconductors products in order to avoid a default of the applications and the products or of the application or use by customer s third party customer s NXP does not accept any liability in this respect Export control This document as well as the item s described herein may be subject to export control regulations Export might require a prior authorization from competent authorities Translations A non English translated version of a document is for reference only The English version shall prevail in case of any discrepancy between the translated and English versions 9 3 Trademarks Notice All referenced brands product names service names and trademarks are the property of their respective owners 2C bus logo is a trademark of NXP B V NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 62 of 64 NXP Semiconductors UM10204 10 Contents I2C bus specification and user manual 1 2 2 1 4 1 4 2 4 2 1 UM10204 Introduction 200 e eee eee eee 3 I2C bus featureS 00 ccc eee eee eee 3 Designer benefits 255 4 Manufacturer benefits 5 IC designer benefits 6 The I C bus protocol 020000ee0e 6 Standard mode Fast mode and Fast mode Plus 2C bus
85. r is accessing it This notifies the master that the slave is busy but does not want to lose the communication The slave device will allow continuation after its task is complete There is no limit in the 1 C bus protocol as to how long this delay can be whereas for a SMBus system it would be limited to 35 ms SMBus protocol just assumes that if something takes too long then it means that there is a problem on the bus and that all devices must reset in order to clear this mode Slave devices are not then allowed to hold the clock LOW too long 4 2 3 Differences between SMBus 1 0 and SMBus 2 0 The SMBus specification defines two classes of electrical characteristics low power and high power The first class originally defined in the SMBus 1 0 and 1 1 specifications was designed primarily with Smart Batteries in mind but could be used with other low power devices The 2 0 version introduces an alternative higher power set of electrical characteristics This class is appropriate for use when higher drive capability is required for example with SMBus devices on PCI add in cards and for connecting such cards across the PCI connector between each other and to SMBus devices on the system board Devices may be powered by the bus Vpp or by another power source Vays as with for example Smart Batteries and will inter operate as long as they adhere to the SMBus electrical specifications for their class NXP devices have a higher power set of
86. r sends the Reserved Device ID C bus address followed by the R W bit set to 0 write 1111 1000 3 The master sends the I2C bus slave address of the slave device it must identify The LSB is a Don t care value Only one device must acknowledge this byte the one that has the C bus slave address 4 The master sends a Re START condition Remark A STOP condition followed by a START condition resets the slave state machine and the Device ID Read cannot be performed Also a STOP condition or a Re START condition followed by an access to another slave device resets the slave state machine and the Device ID Read cannot be performed 5 The master sends the Reserved Device ID 1 C bus address followed by the R W bit set to 1 read 1111 1001 6 The Device ID Read can be done starting with the 12 manufacturer bits first byte four MSBs of the second byte followed by the nine part identification bits four LSBs of the second byte five MSBs of the third byte and then the three die revision bits three LSBs of the third byte 7 The master ends the reading sequence by NACKing the last byte thus resetting the slave device state machine and allowing the master to send the STOP condition Remark The reading of the Device ID can be stopped anytime by sending a NACK If the master continues to ACK the bytes after the third byte the slave rolls back to the first byte and keeps sending the Device ID sequ
87. re to ensure that if more than one master simultaneously tries to control the bus only one is allowed to do so and the winning message is not corrupted Synchronization procedure to synchronize the clock signals of two or more devices The 2C bus is a multi master bus This means that more than one device capable of controlling the bus can be connected to it As masters are usually microcontrollers let us consider the case of a data transfer between two microcontrollers connected to the I2C bus see Figure 2 UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 6 of 64 NXP Semiconductors U M1 0204 UM10204 I2C bus specification and user manual MICRO LCD STATIC CONTROLLER DRIVER RAM OR A EEPROM SDA SCL C T C T T MICRO GATE CONTROLLER ARRAY ADC B mbc645 Fig 2 Example of an I C bus configuration using two microcontrollers This example highlights the master slave and receiver transmitter relationships found on the 1 C bus Note that these relationships are not permanent but only depend on the direction of data transfer at that time The transfer of data would proceed as follows 1 Suppose microcontroller A wants to send information to microcontroller B microc
88. ress range is different Two groups of eight addresses 0000 XXX and 1111 XXX are reserved for the purposes shown in Table 7 Table 7 Reserved addresses X don t care 1 HIGH 0 LOW Slave address R W bit Description 0000 000 0 general call address 0000 000 1 START bytel2 0000 001 X reserved for future purposes 0000 010 xX reserved for future purposes 0000 011 X reserved for future purposes 0000 1XX X reserved for future purposes 1111 1XX X reserved for future purposes 1111 OXX X 10 bit slave addressing 1 The general call address is used for several functions including software reset 2 No UFm device is allowed to acknowledge at the reception of the START byte Assignment of addresses within a local system is up to the system architect who must take into account the devices being used on the bus and any future interaction with reserved addresses For example a device with seven user assignable address pins allows all 128 addresses to be assigned If it is known that the reserved address is never going to be used for its intended purpose then a reserved address can be used for a slave address All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 29 of 64 NXP Semiconductors U M1 0204 UM10204 3 2 10 3 2 11 3 2 12 l2C bus specification and user manual General call address The general call
89. ror as long as the All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 11 of 64 NXP Semiconductors U M1 0204 I2C bus specification and user manual transmissions are identical The first time a master tries to send a HIGH but detects that the SDA level is LOW the master knows that it has lost the arbitration and turns off its SDA output driver The other master goes on to complete its transaction No information is lost during the arbitration process A master that loses the arbitration can generate clock pulses until the end of the byte in which it loses the arbitration and must restart its transaction when the bus is free If a master also incorporates a slave function and it loses arbitration during the addressing stage it is possible that the winning master is trying to address it The losing master must therefore switch over immediately to its slave mode Figure 8 shows the arbitration procedure for two masters More may be involved depending on how many masters are connected to the bus The moment there is a difference between the internal data level of the master generating DATA1 and the actual level on the SDA line the DATA1 output is switched off This does not affect the data transfer initiated by the winning master master 1 loses arbitration x DATA 1 SDA DATA 1 DATA 2 SDA S msc609
90. rters I O Expanders VDD4 I 2c Eo E n 12C Port VDD2 via HW or MCUs ae PCAQ541 Bit Banging 12C Master Selector Demux Multiplexers and Switches 2 2 12C LCD Drivers Pe PC Real Time Clock Temperature Serial EEPROMs with 12C ealendare Sensors v pbs SPI gt Bridges OD 4 l with 12C USB 002aac858 Fig 1 Example of I C bus applications 2 1 Designer benefits I2C bus compatible ICs allow a system design to progress rapidly directly from a functional block diagram to a prototype Moreover since they clip directly onto the I2C bus without any additional external interfacing they allow a prototype system to be modified or upgraded simply by clipping or unclipping ICs to or from the bus Here are some of the features of I C bus compatible ICs that are particularly attractive to designers e Functional blocks on the block diagram correspond with the actual ICs designs proceed rapidly from block diagram to final schematic e No need to design bus interfaces because the C bus interface is already integrated on chip UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 4 of 64 NXP Semiconductors U M1 0204 U
91. s acknowledgement acknowledgement signal from slave signal from receiver NSN SNS NS VYN s VA rere CK ACK EI STOP or byte complete clock line held LOW repeated START interrupt within slave while interrupts are serviced condition 002aac861 UM10204 3 1 6 Acknowledge ACK and Not Acknowledge NACK The acknowledge takes place after every byte The acknowledge bit allows the receiver to signal the transmitter that the byte was successfully received and another byte may be sent The master generates all clock pulses including the acknowledge ninth clock pulse The Acknowledge signal is defined as follows the transmitter releases the SDA line during the acknowledge clock pulse so the receiver can pull the SDA line LOW and it remains stable LOW during the HIGH period of this clock pulse see Figure 4 Set up and hold times specified in Section 6 must also be taken into account When SDA remains HIGH during this ninth clock pulse this is defined as the Not Acknowledge signal The master can then generate either a STOP condition to abort the transfer or a repeated START condition to start a new transfer There are five conditions that lead to the generation of a NACK 1 No receiver is present on the bus with the transmitted address so there is no device to respond with an acknowledge 2 The receiver is unable to receive or transmit because it is performing some real time function and is not ready to start commun
92. s J9 1 2tos Je 7 a gt f I 1 I TTH P then Hs mode _F S mode If Sr dotted lines then Hs mode aj eR tes Master current source pull up f Resistor pull up Fig 34 A complete Hs mode transfer msc618 5 3 3 Switching from F S mode to Hs mode and back After reset and initialization Hs mode devices must be in Fast mode which is in effect F S mode as Fast mode is downward compatible with Standard mode Each Hs mode device can switch from Fast mode to Hs mode and back and is controlled by the serial transfer on the I2C bus Before time t in Figure 34 each connected device operates in Fast mode Between times t and ty this time interval can be stretched by any device each connected device must recognize the S 00001 XXX A sequence and has to switch its internal circuit from the Fast mode setting to the Hs mode setting Between times t4 and ty the connected master and slave devices perform this switching by the following actions The active winning master 1 Adapts its SDAH and SCLH input filters according to the spike suppression requirement in Hs mode 2 Adapts the set up and hold times according to the Hs mode requirements 3 Adapts the slope control of its SDAH and SCLH output stages according to the Hs mode requirement 4 Switches to the Hs mode bit rate which is required after time ty 5 Enables the current source pull up circuit of its SCLH output stage at time ty
93. s the DLEN line can be made active and a CBUS format transmission sent After the STOP condition all devices are again ready to accept data Master transmitters can send CBUS formats after sending the CBUS address The transmission is ended by a STOP condition recognized by all devices Remark If the CBUS configuration is known and expansion with CBUS compatible devices is not foreseen the designer is allowed to adapt the hold time to the specific requirements of the device s used SMBus System Management Bus The SMBus uses 12C hardware and 12C hardware addressing but adds second level software for building special systems In particular its specifications include an Address Resolution Protocol that can make dynamic address allocations Dynamic reconfiguration of the hardware and software allow bus devices to be hot plugged and used immediately without restarting the system The devices are recognized automatically and assigned unique addresses This advantage results in a plug and play user interface In both those protocols there is a very useful distinction made between a System Host and all the other devices in the system that can have the names and functions of masters or slaves SMBus is used today as a system management bus in most PCs Developed by Intel and others in 1995 it modified some 12C electrical and software characteristics for better compatibility with the quickly decreasing power supply budget of portable
94. s allows rapid testing and alignment of end user equipment via external connections to an assembly line e The availability of I2C bus compatible ICs in various leadless packages reduces space requirements even more These are just some of the benefits In addition I C bus compatible ICs increase system design flexibility by allowing simple construction of equipment variants and easy upgrading to keep designs up to date In this way an entire family of equipment can be developed around a basic model Upgrades for new equipment or enhanced feature models that is extended memory remote control etc can then be produced simply by clipping the appropriate ICs onto the bus If a larger ROM is needed it is simply a matter of selecting a microcontroller with a larger ROM from our comprehensive range As new ICs supersede older ones it is easy to add new features to equipment or to increase its performance by simply unclipping the outdated IC from the bus and clipping on its successor All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 5 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual 2 3 IC designer benefits Designers of microcontrollers are frequently under pressure to conserve output pins The 12C protocol allows connection of a wide variety of peripherals without the need for separate addressing or ch
95. sables its current source pull up circuit This enables other devices to delay the serial transfer by stretching the LOW period of the SCLH signal The active master re enables its current source pull up circuit again when all devices have released and the SCLH signal reaches a HIGH level and so speeds up the last part of the SCLH signal s rise time Data transfer continues in Hs mode after the next repeated START Sr and only switches back to F S mode after a STOP condition P To reduce the overhead of the master code it is possible that a master links a number of Hs mode transfers separated by repeated START conditions Sr F S mode Hs mode current source for SCLH enabled F S mode 4 q S MASTER CODE A Sr SLAVE ADD RW A DATA aa P 1 n bytes ack Hs mode continues a WH ro l 1 Sr SLAVE ADD CONDEK AA msc616 Fig 33 Data transfer format in Hs mode All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 39 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual r 8 bit master code 0000 1xxx Au a TE E S G SCLH TIENE 2t05 6 7 8 9 Lo Z F S mode M ee a 7 it 1 gt gt 4 L i i l l i z zon SDAH A IK i e Uy as os ea 1 ot i l 1 l 1 pig iag I SCLH A NAs 6 J 7 J
96. sferring data on the bus Bus clock signals from a master can only be altered when they are stretched by a slow slave device holding down the clock line or by another master when arbitration occurs Table 2 summarizes the use of mandatory and optional portions of the I C bus specification and which system configurations use them All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 7 of 64 NXP Semiconductors U M1 0204 UM10204 3 1 1 I2C bus specification and user manual Table 2 Applicability of I2 C bus protocol features M mandatory O optional n a not applicable Feature Configuration Single master Multi master Slavel START condition M M M STOP condition M M M Acknowledge M M M Synchronization n a M n a Arbitration n a M n a Clock stretching oll oll O 7 bit slave address M M M 10 bit slave address O O O General Call address O O O Software Reset O O O START byte n a oB n a Device ID n a n a O 1 Also refers to a master acting as a slave 2 Clock stretching is a feature of some slaves If no slaves in a system can stretch the clock hold SCL LOW the master need not be designed to handle this procedure 3 Bit banging software emulation multi master systems should consider a START byte See Section 3 1 15 SDA and SCL signals Both SDA and SCL are bidirectional lines connecte
97. source pull up circuit on the SCLH output This current source circuit shortens the rise time of the SCLH signal Only the current source of one master is enabled at any one time and only during Hs mode e No arbitration or clock synchronization is performed during Hs mode transfer in multi master systems which speeds up bit handling capabilities The arbitration procedure always finishes after a preceding master code transmission in F S mode e Hs mode master devices generate a serial clock signal with a HIGH to LOW ratio of 1 to 2 This relieves the timing requirements for set up and hold times e As an option Hs mode master devices can have a built in bridge During Hs mode transfer the high speed data SDAH and high speed serial clock SCLH lines of Hs mode devices are separated by this bridge from the SDA and SCL lines of F S mode devices This reduces the capacitive load of the SDAH and SCLH lines resulting in faster rise and fall times e The only difference between Hs mode slave devices and F S mode slave devices is the speed at which they operate Hs mode slaves have open drain output buffers on the SCLH and SDAH outputs Optional pull down transistors on the SCLH pin can be used to stretch the LOW level of the SCLH signal although this is only allowed after the acknowledge bit in Hs mode transfers e The inputs of Hs mode devices incorporate spike suppression and a Schmitt trigger at the SDAH and SCLH inputs e The output buff
98. t drive on the bus Be sure to allow for any devices that have a minimum t or t Refer to Equation 3 for the resulting fmax oe TLoW min HIGH min tr actual Y actual I ites 3 Remark Very long buses must also account for time of flight of signals Actual results are slower as real parts do not tend to control tLow and tyigy to the minimum from 30 to 70 or 70 to 30 respectively Higher drive outputs If higher drive devices like the PCA96xx Fast mode Plus or the P82B bus buffers are used the higher strength output drivers sink more current which results in considerably faster edge rates or looked at another way allows a higher bus capacitance Refer to individual component data sheets for actual output drive capability Repeat the calculation above using the new values of Cp Rp tr and t to determine maximum frequency Bear in mind that the maximum rating for fsc as specified in Table 10 100 kHz 400 kHz and 1000 kHz may become limiting Bus buffers multiplexers and switches Another approach to coping with excess bus capacitance is to divide the bus into smaller segments using bus buffers multiplexers or switches Figure 43 shows an example of a bus that uses a PCA9515 buffer to deal with high bus capacitance Each segment is then allowed to have the maximum capacitance so the total bus can have twice the maximum All information provided in this document is subject to legal disclaimers NXP B V 2012
99. t2 t1 0 8473 x RC Figure 41 and Equation 1 shows maximum Rp as a function of bus capacitance for Standard Fast and Fast mode Plus For each mode the Rp max is a function of the rise time maximum t from Table 10 and the estimated bus capacitance Cp t R _ pmax 0 8473 x C 1 20 7 002aac883 4 002aac884 Rp max Rp mi min kQ i 16 kQ 3 12 2 8 2 1 1 4 3 2 0 0 0 200 400 600 0 5 10 15 20 Cp pF Vpop V 1 Standard mode 1 Fast mode and Standard mode 2 Fast mode 2 Fast mode Plus 3 Fast mode Plus Fig 41 Rp max as a function of bus capacitance Fig 42 Rp min as a function of Vpp The supply voltage limits the minimum value of resistor Rp due to the specified minimum sink current of 3 mA for Standard mode and Fast mode or 20 mA for Fast mode Plus Rp min as a function of Vpp is shown in Figure 42 The traces are calculated using Equation 2 R E Vop VoL max 2 p min 7 I OL UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 55 of 64 NXP Semiconductors U M1 0204 UM10204 7 2 7 2 1 7 2 2 7 2 3 l2C bus specification and user manual The designer now has the minimum and maximum value of Ry that is required to meet the timi
100. th seven user assignable address pins allows all 128 addresses to be assigned If it is known that the reserved address is never going to be used for its intended purpose a reserved address can be used for a slave address General call address The general call address is for addressing every device connected to the I2C bus at the same time However if a device does not need any of the data supplied within the general call structure it can ignore this address by not issuing an acknowledgment If a device does require data from a general call address it acknowledges this address and behave as a slave receiver The master does not actually know how many devices acknowledged if one or more devices respond The second and following bytes are acknowledged by every slave receiver capable of handling this data A slave who cannot process one of these bytes must ignore it by not acknowledging Again if one or more slaves acknowledge the not acknowledge will not be seen by the master The meaning of the general call address is always specified in the second byte see Figure 16 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 17 of 64 NXP Semiconductors U M1 0204 UM10204 l2C bus specification and user manual LSB ofofo o o olololalx x x x x x x afa Oo first byte second byte general call address mbc623
101. the device that initiates a transfer generates clock signals and terminates a transfer Slave the device addressed by a master Let us consider the case of a data transfer between a master and multiple slaves connected to the UFm 1 C bus see Figure 21 Master ASIC LCD LED DRIVER controller 3 USDA USCL Ti Ti LT LED LED controller 1 controller 2 GPO 002aag654 Fig 21 Example of UFm I C bus configuration UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 23 of 64 NXP Semiconductors U M1 0204 UM10204 l2C bus specification and user manual This highlights the master transmitter slave receiver relationship found on the UFm I2C bus Note that these relationships are permanent as data transfer is only permitted in one direction The transfer of data would proceed as follows Suppose that the master ASIC wants to send information to the LED controller 2 e ASIC A master transmitter addresses LED controller 2 slave receiver by sending the address on the USDA and generating the clock on USCL e ASIC A master transmitter sends data to LED controller 2 slave receiver on the USDA and generates the clock on USCL e ASIC A terminates the transfer The possibility of connecting
102. to an F S mode I2C bus system see Figure 35 As no master code is transmitted in such a configuration all Hs mode master devices stay in F S mode and communicate at F S mode speeds with their current source disabled The SDAH and SCLH pins are used to connect to the F S mode bus system allowing the SDA and SCL pins if present on the Hs mode master device to be used for other functions All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 41 of 64 NXP Semiconductors U M1 0204 l2C bus specification and user manual VDD SDA Rp Rp Hs mode SLAVE 2 To input filter Bridge not used The current source pull up circuit stays disabled 4 Dotted transistors are optional open drain outputs which can stretch the serial clock signal SCL Fig 35 Hs mode devices at F S mode speed Hs mode Hs mode F S mode F S mode SLAVE MASTER SLAVE MASTER SLAVE SLAVE msc613 SDA and SCL may have an alternative function 5 3 5 UM10204 Mixed speed modes on one serial bus system If a system has a combination of Hs mode Fast mode and or Standard mode devices it is possible by using an interconnection bridge to have different bit rates between different devices see Figure 36 and Fig
103. tware polling In this case data transfer can be preceded by a start procedure which is much longer than normal see Figure 19 The start procedure consists of e A START condition S e A START byte 0000 0001 e An acknowledge clock pulse ACK e A repeated START condition Sr UM10204 All information provided in this document is subject to legal disclaimers NXP B V 2012 All rights reserved User manual Rev 5 9 October 2012 19 of 64 NXP Semiconductors U M1 0204 I2C bus specification and user manual SDA dummy acknowledge HIGH SCL tN ee Pe 7 8 9 s 7 NACK Sr _ _ START byte 0000 0001 002aac997 Fig 19 START byte procedure After the START condition S has been transmitted by a master which requires bus access the START byte 0000 0001 is transmitted Another microcontroller can therefore sample the SDA line at a low sampling rate until one of the seven zeros in the START byte is detected After detection of this LOW level on the SDA line the microcontroller can switch to a higher sampling rate to find the repeated START condition Sr which is then used for synchronization A hardware receiver resets upon receipt of the repeated START condition Sr and therefore ignores the START byte An acknowledge related clock pulse is generated after the START byte This is present only to conform with the byte handling format used on the bus No
104. ure 37 One bridge is required to connect disconnect an Hs mode section to from an F S mode section at the appropriate time This bridge includes a level shift function that allows devices with different supply voltages to be connected For example F S mode devices with a Vpp2 of 5 V can be connected to Hs mode devices with a Vpp1 of 3 V or less that is where Vpp2 Vpp1 provided SDA and SCL pins are 5 V tolerant This bridge is incorporated in Hs mode master devices and is completely controlled by the serial signals SDAH SCLH SDA and SCL Such a bridge can be implemented in any IC as an autonomous circuit TR1 TR2 and TR3 are N channel transistors TR1 and TR2 have a transfer gate function and TR3 is an open drain pull down stage If TR1 or TR2 are switched on they transfer a LOW level in both directions otherwise when both the drain and source rise to a HIGH level there is a high impedance between the drain and source of each switched on transistor In the latter case the transistors act as a level shifter as SDAH and SCLH are pulled up to Vpp1 and SDA and SCL are pulled up to Vpp2 During F S mode speed a bridge on one of the Hs mode masters connects the SDAH and SCLH lines to the corresponding SDA and SCL lines thus permitting Hs mode devices to communicate with F S mode devices at slower speeds Arbitration and synchronization are possible during the total F S mode transfer between all connected devices as described in Section 3 1
105. wledge bit A the active master disables its current source pull up circuit This enables other devices to delay the serial transfer by stretching the LOW period of the SCLH signal The active master re enables its current source pull up circuit again when all devices are released and the SCLH signal reaches a HIGH level and so speeds up the last part of the SCLH signal rise time In irregular situations F S mode devices can close the bridge TR1 and TR2 closed TR3 open at any time by pulling down the SCL line for at least 1 us for example to recover from a bus hang up Hs mode finishes with a STOP condition and brings the bus system back into the F S mode The active master disables its current source MCS when the STOP condition P at SDAH is detected tes in Figure 37 The bridge also recognizes this STOP condition and takes the following actions 1 Transistor TR2 closes after tes to connect SCLH with SCL both of which are HIGH at this time Transistor TR3 opens after tes which releases the SDA line and allows it to be pulled HIGH by the pull up resistor Rp This is the STOP condition for the F S mode devices TR3 must open fast enough to ensure the bus free time between the STOP condition and the earliest next START condition is according to the Fast mode specification see tgur in Table 10 2 When SDA reaches a HIGH ts in Figure 37 transistor TR1 closes to connect SDAH with SDA Note interconnections are made when all lines are

UM10204 I2C-bus specification and user manual

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