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Xilinx ISim User Guide (UG660)

1. into ID Specifies the object ID of the group into which the divider should be added color color Sets the divider color to the specified color The value of is defined in RGB format For example 0000FF is blue FF0000 is red and 00FF00 is green You can also specify the textual name of color can for some of the popular colors The following color names are accepted black red darkred green darkgreen blue darkblue cyan darkcyan magenta darkmagenta darkyellow gray darkgray lightgray The RGB values for these colors are defined in the RGB table divider add Command Examples Add a divider with name Inputs to the current wave configuration divider add Inputs Add red divider with name Outputs divider add Outputs color red Add dividers into a group set test group id group add test group wave add dcm clk s tb data2 into test group id divider add data color blue into test group id wave add addrl1 tb UUT addr2 into test group id divider add address color red into test group id group add The group add command adds a new group group add Command Syntax group add into lt ID gt Where into ID Specifies the object ID of an already existing group into which to add a newly created group group add Command Examples Add a group with name Inputs to the current wave configuration group add Inputs ISim User Guide UG660 v14 3
2. am Instances and Processes Ea Memory ILS Source Files Figure 2 2 Instances and Processes Panel 14 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Design Hierarchy Buttons Table 2 4 describes the design hierarchy buttons in the Instances and Processes panel Table 2 4 Instance and Processes Panel Buttons Icon Represents T VHDL Entity VHDL Package VHDL Block y VHDL Process va g Verilog Module F x A toggle for filtering Verilog tasks A toggle for filtering Verilog blocks G A toggle for filtering Verilog Processes With Hierarchy buttons you can take the following actions e To expand a hierarchy to display its components click the arrows or use the Expand context menu commands see Expanding and Collapsing a Hierarchy page 16 e To sort the information in this panel according to the data in one of the columns click the column title such as Design Unit e To hide or restore the panel select View gt Panel gt Instances and Processes ISim User Guide www xilinx com 15 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX Expanding and Collapsing a Hierarchy You can expand and collapse a hierarchy in any window or panel with objects in nested groups using one of the following methods Clicking the arrows e Click the expand arrow to expand the hierarchy O
3. Selects the wave configuration file to be displayed in the active window Using Object Names with Special Characters in Tcl Some commands such as wave add can take arguments that contain characters that have special meaning to Tcl Those arguments must be surrounded with curly braces to avoid unintended processing by Tcl The most common cases are as follows Bus Indexes Because square brackets have special meaning to Tcl an indexed bit or part selected bus using square bracket notation must be surrounded with curly braces For example when adding element 4 of bus to the Wave window using square bracket notation you must write the command as wave add bus 4 Parentheses can also be used for indexing a bus and because parentheses have no special meaning to Tcl the command can be written without curly braces For example wave add bus 4 ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback 101 Chapter 9 ISim Tcl Commands XILINX Verilog Escaped Identifiers Verilog identifiers containing characters that are special to Verilog need to be escaped both in Verilog source code and on the ISim command line by prefixing the identifier with a backslash and appending a space Additionally on the Tcl command line the escaped identifier must be surrounded with curly braces For example to add wire my wire to the Wave window you must write the command as wave add my
4. XILINX Board Support e Pin is the clock pin location For differential clock sources provide both Positive and Negative clock pin locations e BoundaryScanPosition is the position of the FPGA on the JTAG boundary scan chain beginning with 1 This information can be determined by running the Xilinx iMPACT tool Note For P2P Ethernet HWCoSim additional fields must be specified See the setup for the ml605 ppethernet entry in the SXILINX sysgen hwcosim data hwcosim bsp file as an example Board Support File Xilinx boards are supported by default The default board support file is installed under the following directory of an ISE 14 x installation SXILINX sysgen hwcosim data hwcosim bsp Boards with default support are as follows ISim User Guide ml401 jtag Xilinx Virtex 4 ML401 Evaluation Platform m1402 jtag Xilinx ML402 Evaluation Platform m1403 jtag Xilinx ML403 Evaluation Platform m1405 jtag Xilinx ML405 Evaluation Platform m1410 jtag Xilinx ML410 Evaluation Platform m1501 jtag Xilinx Virtex 5 ML501 Evaluation Platform m1505 jtag Xilinx ML505 Evaluation Platform m1506 jtag ML506 ppethernet Xilinx ML506 Evaluation Platform m1507 jtag Xilinx ML507 Evaluation Platform xupv5 jtag Xilinx University Program XUPV5 LX110T Development System m1510 jtag Xilinx ML510 Evaluation Platform m1605 jtag ML605 ppethernet Xilinx Virtex 6 ML605 Evaluation Platform kc705 jtag Xilinx Kintex
5. db ff fed inv we o Loge CQ Cort 89 1 d mtd i tex Ch Aways 91 2 4H AS fon inse 00001111100110 Array C4 Neays 94 3 fft busy o Loge C Meays 101 4 up ft edone o Loge Qm 195 g ip fft done o Loge gt o preise aes rennin tei x lt gt lt Ov X fftok nde 00000000000000 Anay oL S veteres I Source lt fp fft tb wfo E Corea Ox Pedi D8x c Opx wen HU P of bounds Sam Iwecosim set ethernetinterfacelD 00 19 59 75 5 95 PRERE Rasika WMEENGM S m bwecosin get ethernetinterfacelD cunis 0 19 09 7S 5 95 1007 Sim run 10us MOSON vertoolacdc Figure 8 6 HWCoSim Process in GUI Console Frequently Asked Questions In the following description design under test DUT refers to the portion of design that is co simulated in FPGA General 1 Q Does HWCoSim support any kind of designs A Certain limitations described in Limitations page 84 apply 2 Q Is IHWCoSim a functional simulation or a timing simulation A It is a functional simulation assisted with hardware which is bit and cycle accurate with respect to the pure tool simulation 3 Q How do I use my own board A You can add your own board in the board support file as described in Board Support page 92 ISim User Guide www xilinx com 95 UG660 v14 3 October 16 2012 Send Feedback Chapter 8 Using Hardware Co Simulation XILINX Compilation 1 Simulation 1 Q Can I co si
6. E options can be specified with the Other Command Line Line Options Compilation eo Options property Specify define Macro Name and Value Incremental Compilation N A Compile for HDL Debugging Miscellaneous Settings Use Configuration Name N A Configuration Name N A Log All Signals In N A Simulation Other VSIM Command Specify Top Level Line Options Instance Name ISim User Guide www xilinx com UG660 v14 3 October 16 2012 Send Feedback 155 Appendix C Migrating from ModelSim XE to ISim XILINX 156 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Xilinx Resources Appendix D Additional Resources Xilinx Resources ISim Tutorials ISim User Guide Device User Guides http www xilinx com support documentation user guides htm Xilinx Glossary http www xilinx com company terms htm Xilinx Design Tools Installation and Licensing Guide UG798 http www xilinx com support documentation sw manuals xilinx14 3 iil pdf Xilinx Design Tools Release Notes Guide UG631 http www xilinx com support documentation sw manuals xilinx14 3 irn pdf Product Support and Documentation http www xilinx com support Synthesis and Simulation Design Guide UG626 http www xilinx com support documentation sw manuals xilinx14 3 sim pdf PlanAhead User Guide UG632 http www xilinx com support documentation sw manuals xilinx14 3 PlanAhe
7. Select Window Next or Window Previous to navigate through open wave configurations ISim User Guide www xilinx com 21 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX Adding Signals to the Wave Configuration You can populate the Wave window with the signals from your design using menu commands or drag and drop capabilities in the GUI or using Tcl commands in the Console panel Note Changes to the wave configuration including creating the wave configuration or adding signals do not become permanent until you save the WCFG file For more information see Wave Configurations and WCFG Files In the GUI 1 Inthe Instances and Processes panel expand the design hierarchy and select an item The objects that correspond to the selected instance or process displays in the Objects panel 2 Inthe Objects panel select one or more objects 3 Useone ofthe following methods to add objects to the wave configuration e Right click and select Add to Wave Window from the context menu e Drag and drop the objects from the Objects panel to the Name column of the Wave window e Inthe Console panel use wave add command Using Tcl e Optionally you can first identify the objects you want to add by exploring the design hierarchy in the Instances and Processes panel and the Objects panel or by entering the scope command in the Console panel e Inthe Console panel enter the wave add com
8. 1 Buffer and linkage ports of VHDL are not supported 2 Connection to bidirectional pass switches in Verilog are not supported Unnamed Verilog ports are not allowed on mixed design boundary Table 3 2 shows the supported VHDL and Verilog data types for ports on the mixed language design boundary Table 3 2 Supported VHDL an d Verilog data types VHDL Port Verilog Port bit net std_ulogic net std_logic net bit_vector vector net std_ulogic_vector vector net std_logic_vector vector net Note Verilog output port of type reg is supported on the mixed language boundary On the boundary an output reg port is treated as if it were an output net wire port Note Any other type found on mixed language boundary is considered an error Generics Parameters Mapping ISim supports the following VHDL generic types and their Verilog equivalents integer e real e string e boolean Note Any other generic type found on mixed language boundary is considered an error ISim User Guide www xilinx com 47 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX VHDL and Verilog Values Mapping Table 3 3 lists the Verilog states mappings to std_logic and bit Table 3 3 Verilog States mapped to std logic and bit Verilog std logic bit Z 0 0 0 0 1 1 1 X X 0 Note Verilog strength is ignored There is no corresponding mapping to stre
9. Allowed values are 0 and 1 Default 0 i include path Verilog only Specifies that if fuse calls vlogcomp it should use the specified path for Verilog include directives Each i can be used for only one include path More than one i can be specified Place quotes around paths with spaces incremental Compiles only the files that have changed since last compile initfile sim init file Specifies a user defined simulator initialization file to add to or to override the logical to physical mappings of libraries provided by the default xilinxsim ini file intstyle ise xflow silent default Use one of the specified styles for printing messages e ise formats messages for the ISE Console e xflow formats messages for XFLOW silent suppress all messages e default is the specified default message style ise lt file gt Lets you specify an ISE file L lib search lib lib path Specifies other libraries and optionally the physical path name for those libraries You can use multiple L switches that are treated as resource libraries The physical path provided through L overrides mappings provided by the xilinxsim ini file The search lib is the logical name of the specified library optionally followed by the 1ib path the path to the physical library Note Ensure that there is no space between the and the value the space would be interpret
10. 7 FPGA KC705 Evaluation Kit zc702 jtag Zyng 7000 EPP board vc707 jtag Xilinx Virtex 7 FPGA VC707 Evaluation Kit s3e sk jtag Xilinx Spartan 3E Starter Kit s3e mb jtag Xilinx Spartan 3E MicroBlaze Development Kit s3a sk jtag Xilinx Spartan 3A Starter Kit s3an sk jtag Xilinx Spartan 3AN Starter Kit s3adsp1800a jtag Xilinx Spartan 3A DSP 1800A Starter Platform s3adsp3400a jtag Xilinx Spartan 3A DSP 3400A Development Platform sp601 jtag sp601 ppethernet Xilinx Spartan 6 SP601 Evaluation Platform sp605 jtag sp605 ppethernet Xilinx Spartan 6 SP605 Evaluation Platform www xilinx com 93 UG660 v14 3 October 16 2012 us s Chapter 8 Using Hardware Co Simulation XILINX Determining the Ethernet To run an Ethernet based Hardware Co Simulation when multiple Ethernet interfaces are present you must select the Ethernet interface that you want to co simulate If you ran a previous hardware co simulation using the Point to Point interface option you see the following error message ERROR In process wrapper AHIL INITIALIZE Failed to open hardware co simulation instance Error in Point to point Ethernet Hardware Co simulation There are multiple Ethernet interfaces available Please select an interface Use the following steps to determine the Ethernet port set and verify the Ethernet address and verify that the simulation runs 1 Determine the Ethernet port to which the co simulation boar
11. Lockstep Emulated Clack M ISim Test bench HW Co Sim Interface Figure 8 4 Determining Lockstep and Free running Design Portions 2 Copy the original design constraints file and use it as the basis for the custom constraints file 3 Modify the custom constraints file to comment out the LOC constraints for those pins that are controlled by ISim Other pins with LOC constraints are assumed to be external 4 Asan example for a FIFO design that you want to single step the write side and free run the read side such as module FIFO WCLK WDATA WE RCLK RDATA RI Lj The isim hwcosim ucf would be The following pin LOCs commented out as they are driven by ISim NET WCLK PERIOD 5 ns HIGH 50 NET WCLK LOC Al lt this becomes single step clock NET WDATA LOC A2 lt these are accessible from ISim testbench NET WE LOC A3 NET RCLK PERIOD 10 ns HIGH 50 NET RCLK LOC B1 lt this becomes free running clock NET RDATA LOC B2 lt these go to external IOBs NET RE LOC B3 ISim User Guide www xilinx com 89 UG660 v14 3 October 16 2012 Send Feedback Chapter 8 Using Hardware Co Simulation XILINX Hardware Board Usage The following procedure describes how to install and set up the hardware to run hardware co simulation 1 Ensure the hardware board is powered off 2 If
12. Opening a Wave Configuration from a Command Prompt Because a wave configuration is not open by default when you launch the GUI you can include the view switch to open an existing one Run the simulation executable with the following syntax sim exe exe gui wdb lt wdb gt wdb view lt wcfg gt wcfg Where e gui launches the GUI e wdb lt wdb gt wdb specifies the filename where the simulation data is stored e view lt wcfg gt wcfg opens the specified waveform file in the GUI www xilinx com 73 UG660 v14 3 October 16 2012 send Feedback Chapter 5 Viewing Simulation Results XILINX The GUI opens with a new database a live simulation If simulation objects from the WCEG correspond to those in the database the wave configuration is pre populated with data from the database For information about creating a new wave configuration see Working with the Wave Configuration in Chapter 4 Opening a Static Simulation A static read only simulation consists of a e Wave configuration WCFG file which contains the order and settings associated with objects the display in the wave configuration and e WDB file which contains the simulation data from a previously run live simulation A wave configuration file references the waveform database for which it was created A simulation cannot be performed in the static simulator For information about opening a live simulation see Simulating the Design in Chapter 3
13. signal name vhdl process name process variable name element reference value Description signal name is the name of the signal or bus to be compared This can also be the name of an array of signals or buses an array of records containing signals and buses or a record of arrays of buses signals vhdl process name process variable name is the name of the process and process variable to be compared To compare the value of a process variable you must also supply the name of the process that contains the variable The process name and process variable names must be separated by a forward slash element reference are the different ways in which the sub elements of the signal name can be referenced when used with the test command This provides the ability to further refine the signals by referencing the individual sub elements of a signal value is the supplied value to compare with actual value on net or bus object value radix radix type Compares the specified value with the specified radix to object value object specifies the signals buses or objects to test value is the value to add to the object The supported radix types are default dec bin oct hex unsigned and ascii When no radix type is specified the global radix type set with the isim set radix command is used or if none is set default is used test Command Examples
14. isim condition add top asig 8 stop label label0 radix hex Adding a VHDL specific signal condition that states that when the signal asig is equal to 1 a stop occurs and the condition is called 1abe11 isim condition add top asig 1 stop label label1 Adding a condition that states that for any change on the asig signal a stop occurs and the condition is called 1abe12 isim condition add top asig stop label label2 Adding a Verilog specific signal condition that states that when clk is equal to St 1 a stop occurs and the condition is called 1abe13 isim condition add clk St1 stop label label3 Adding a condition that states that when asig 3 0 is equal to 0001 and reset is equal to 1 a stop occurs isim condition add asig 3 0 0001 amp amp reset 1 stop isim condition remove Examples Remove all conditions in the current simulation isim condition remove or isim condition remove all Remove the conditions label0 labeli and label2 isim condition remove label label0 label1 label2 108 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Remove a single statement isim condition remove index 2 or isim condition remove label label3 ISim condition list Examples Listing all ISim conditions added to the design at the current time isim condition list isim force The isim force command forces a VHDL
15. restart the simulation Use the Restart command to reset time to the beginning of the test bench See Running Simulation in Chapter 3 2 Select Window gt Tile Horizontally or Window gt Tile Vertically to simultaneously see the waveform and the HDL code 3 Repeat the Step action until debugging is complete www xilinx com 77 UG660 v14 3 October 16 2012 send Feedback Chapter 6 Debugging at the Source Level XILINX As each line is executed you can see the yellow arrow moving down the code If the simulator is executing lines in another file the new file opens and the yellow arrow steps through the code It is common in most simulations for multiple files to be opened when running the Step command The Console panel also indicates how far along the HDL code the step command has progressed Using Breakpoints A breakpoint is a user determined stopping point in the source code used for debugging the design Breakpoints are particularly helpful when debugging larger designs for which debugging with the Step command stopping the simulation for every line of code might be too cumbersome and time consuming You can set breakpoints in executable lines in your HDL file so you can run your code continuously until the source code line with the breakpoint is reached Note You can set breakpoints on lines with executable code only If you place a breakpoint on a line of code that is not executable the breakpoint is not added
16. sync and array not supported sync nand array not supported sync nor array not supported sync or array not supported async and plane not supported async nand plane not supported async nor plane not supported async or plane not supported sync and plane not supported sync nand plane not supported sync nor plane not supported sync or plane not supported Value Change Dump VCD Files dumpportson not supported dumpports dumpportsoff dumpportsflush dumpportslimit vcdplus www xilinx com UG660 v14 3 October 16 2012 Send Feedback 1 Appendix B Exceptions to VHDL and Verilog Language Support XILINX 146 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX About ModelSim XE Appendix C Migrating from ModelSim XE to ISim Retargeting from a ModelSim XE simulation environment to a Xilinx ISim simulation environment can be accomplished without significantly modifying the existing environment This overview identifies and details the appropriate migration guidelines and other considerations for making the switch from ModelSim XE to ISim To get the best use of the underlying innovations of ISim a video demonstration and tutorials are also available e Tutorials http www xilinx com support documentation dt ise htm e Sim Video Demos http www xilinx com products design resources design tool resources index htm e Sim Product Page ht
17. ISim User Guide www xilinx com 9 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX To close ISim select File gt Exit ISim prompts you to save your waveform configuration before closing Table 2 1 lists the ISim GUI components as idenfied in Figure 2 1 page 9 and links to the GUI part description Note n your PDF reader turn on Previous View and Next View Buttons to navigate back and forth to linked information Table 2 1 Sim GUI Components GUI Part by Description 1 Menus and Toolbar Provides access to most operations available in the tool Some Commands and operations are available in context menu only Shortcuts 2 ISim Menu and Provides access to frequently used commands Toolbar 3 Instances and Displays the block instance and process hierarchy associated Processes Panel with the current simulation 4 Source Files Panel Displays the list of all the files associated with the design 5 Console Panel Displays messages generated by the simulator You can enter simulation Tcl commands at the prompt 6 Breakpoints Panel Displays a list of all breakpoints currently set in the design 7 Findin Files Results Displays the results that match a text string in a set of files Panel 8 Search Results Panel Displays the results that match the criteria from a search 9 Objects Panel Displays the simulation objects associated with the block sele
18. Note Running the restart command cancels all the effective isim force commands e Value Radix Displays the current radix setting of the selected signal You can choose one of the supported radix types from the dropdown box Binary Hexadecimal Unsigned Decimal Signed Decimal Octal and ASCII e Leading Edge Value Specify the first edge of the clock pattern The Leading Edge Value uses the radix defined in Value Radix Trailing Edge Value Specify the second edge of the clock pattern The Trailing Edge Value uses the radix defined in the Value Radix field e Starting at Time Offset Start the force command after the specified time from the current simulation The default starting time is 0 Time can be a string such as 10 or 10 ns If you enter a number without a unit ISim uses the default user unit as returned by the isim get userunit Tcl command e Cancel after Time Offset Cancel the force command after the specified time from the current simulation time Time can be a string such as 10 or 10 ns When you enter a number without a unit ISim uses the default simulation time unit e Duty Cycle Specify the percentage of time that the clock pulse is in an active state The acceptable value ranges from 0 to 100 e Period Specify the length of the clock pulse defined as a time value Time can be a string such as 10 or 10 ns ISim User Guide www xilinx com 31 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the
19. Opening a Wave Configuration and Waveform Database If you have a waveform configuration WCFG file from a previous simulation run and you want to open the WCFG and its associated simulation data WDB use one of the following methods to open the WCFG and WDB To open a wave configuration and the waveform database do the following 1 Run isimgui exe to open the static simulator 2 Select File gt Open select the wefg file type from the file filter list and select the wave configuration WCFG file from a previous simulation Alternatively you can type isimgui exe open wcfg file wcfg Where e isimgui exe is the application executable e open instructs the that the tool open the specified file e view lt wcfg gt wcfg opens the specified waveform file in the GUI The static simulator displays the wave configuration with all signals previously traced and the associated waveform database Opening an Existing WCFG and Non Associated Waveform Database You can load simulation data WDB and view a WCFG that is not associated with the database This way of opening a static simulation is useful for cases when different views as captured in a WCFG file of the same simulation result the transitions stored in the WDB file need to be seen by different engineers in a team ISim issues a warning for any object name that is present in the WCFG but not found in the WDB file and displays only those objects that match 74 www
20. Some asynchronous buffer or additional synchronization logic is expected to properly handle clock domain crossing between the two portions Q Can I run the DUT at a particular clock frequency A You can supply external clocks for the free running portion of the DUT in hybrid co simulation However the clock in the lockstep portion is controlled by ISim and is synchronous to the tool simulation and thus not fixed to a particular clock frequency The effective clock rate of the lockstep portion is slow regardless of its input clock frequency Driving the DUT with a faster clock does not improve the simulation performance as the major bottleneck is the communication between tool and hardware The DUT is constrained with a lower clock frequency to make the compilation process such as map and place and route faster Q Can I connect some ports of the DUT to external I Os such as DDR memory modules A External I Os and clocks are supported in the hybrid co simulation mode through the use of a custom constraints file as described in Hybrid Co Simulation Flow page 88 www xilinx com 97 UG660 v14 3 October 16 2012 Send Feedback Chapter 8 Using Hardware Co Simulation 98 Send Feedback www xilinx com XILINX ISim User Guide UG660 v14 3 October 16 2012 XILINX Chapter 9 ISim Tcl Commands Simulation commands let you run an interactive simulation at a command prompt Note All commands are case sensitiv
21. The test command can be used as follows Compare a bit values of 1 to a signal called count 6 in the module u1 that is instantiated under your current scope test ul count 6 1 Compare the value of signal A to FF test A FF radix hex Compare value with c1k value test clk U Returns 1 Compare value with clk value test clk 0 Returns 0 128 Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX Tcl Commands Stop simulation if top rst is 0 if test top rst 0 stop else For the signal Reset in Block UUT the command test Reset 1 displays the following message test failed Command failed test Reset 1 1 Net Reset has value 0 not 1 as expected For the bus Lsbcnt in UUT the command test Lsbcnt 1001 displays the following message test passed 0 For a standard logic vector called sigx that is declared as follows signal sigx std logic vector 0 to 5 Compare bit 0 of sigx to 1 test sigx 0 1 Compare slice 1 to 2 of sigx to 11 test sigx 1 2 11 Compare all of sigx to 101010 test sigx 101010 For an array of standard logic vectors that is declared as follows signal sigarray vectorarray 0 to 5 1 to 4 2 to 6 Compare every bit of a vector array element of sigarray to 1 test sigarray 0 1 2 1111 Compare the first two bits of each array element of sigarray to 10 test sigarray 0 1 2 1 2 10 Compare bits three of eac
22. and the Instances and Processes panel Working with the Wave Configuration You can add signals and buses to the wave configuration file then save that configuration to a WDB file See Opening a Wave Configuration and Waveform Database in Chapter 5 Adding Signals to the Wave Configuration ISim User Guide You can populate the Wave window with the signals from your design using menu commands or drag and drop capabilities in the GUI or using Tools Command Language Tcl commands in the Console panel Note Changes to the wave configuration including creating the wave configuration or adding signals do not become permanent until you save the WCFG file For more information see Saving the Results Adding Signals in the GUI 1 In the Instances and Processes panel expand the design hierarchy and select an item The objects that correspond to the selected instance or process displays in the Objects panel In the Objects panel select one or more objects Use one of the following methods to add objects to the wave configuration Right click and select Add to Wave Window from the context menu Drag and drop the objects from the Objects panel to the Name column of the Wave window In the Console panel use the wave add command www xilinx com 59 UG660 v14 3 October 16 2012 Seno Fee aek Chapter 4 Waveform Analysis XILINX Adding Signals Using Tcl 1 Optionally you can first identify the objects you want t
23. float and dock the panel Table 2 5 lists the buttons and description 16 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Table 2 5 Panel Control Buttons Icon Description Toggle Slide Out Minimizes the panel Also used to restore the pane by hovering over the name of the panel at the edge of the window and clicking the minimize button Toggle Maximized Maximizes the panel Click again to restore the panel size Toggle Floating Floats the panel Re click to restore to its former location Close Closes the panel from view To restore the panel select View Panels and select the pane to restore to view Wave Window ISim User Guide The Wave window displays signals buses and their waveforms Each tab in the Wave window shows a wave configuration that contains a list of signals and buses their properties and any added wave objects such as dividers cursors and markers In the GUI the signals and buses in the wave configuration are traced during simulation and you use the wave configuration to examine the simulation results The design hierarchy and the signal transitions are not part of the wave configuration and are stored in a separate database wdb file Wave Configuration File wcfg A wave configuration comprises a list of signals their properties such as color and radix value and other wave objects such as dividers
24. hwcosim incremental optional specifies whether fuse reuses the last generated hardware co simulation bitstream and skips the implementation flow e hwcosim instance specifies the full hierarchical path of the instance to co simulate in hardware e hwcosim no combinatorial path speeds up simulation if the design run on FPGA does not have a purely combinatorial path from any input to any output Tools Flow 1 Ensure you have ISim selected as the simulator for the project Switch to the Simulation view 2 Fromthe Hierarchy pane select the instance to co simulate in hardware and right click to show the context menu 3 Fromthe context menu select Source Properties to open the Source Properties dialog box 4 Inthe Source Properties dialog box select Hardware Co Simulation from the category list ISim User Guide www xilinx com 85 UG660 v14 3 October 16 2012 Send Feedback 86 Chapter 8 Using Hardware Co Simulation XILINX 5 Setthe following properties for hardware co simulation Check the Enable Hardware Co Simulation check box Because only one instance can be enabled for hardware co simulation enabling a instance for hardware co simulation disables any other instance that has been previously enabled for hardware co simulation In the Clock Port field specify the name of the clock port on the instance For an instance with multiple clocks specify the name of the fastest clock port From the Target Board f
25. mylib1 lib cde v 4 Where test prj contains verilog work test v The fuse command uses files from the sourcelibfile options for modules used in test vasitanalyzes the modules and elaborates the test design For every unresolved module with name module name instantiated in file test v the compiler looks up files with name modulename v inside the directories mylib1 and mylib2 in that order Use the fuse command with the work g151 option fuse work testbench work glbl prj design prj L simprims ver o isim exe Note Using g1b1 as top name is necessary in fuse during timing simulation The o switch is optional Without o the default name for the simulation executable is x exe For example fuse topunit work glbl prj mydesign prj o my sim exe Note To exclude certain lines in a PRJ file use the option Verilog Search Order The fuse command uses the following search order to search and bind instantiated Verilog design units 1 A library specified by the uselib directive in the Verilog code For example module full adder c in c out a b sum input c in a b output c out sum wire carryl carry2 sum1 uselib lib adder lib half adder adderl a a b b c carryl s sum1 half adder adderl a sum1 b c in c carry2 s sum c out carryl carry2 endmodule Libraries specified on the command line with 1ib L switch A library of the parent design unit The w
26. 2001 Verilog standard generate block begin generate block identifier generate item end Production supported by Simulator generate block begin generate block identifier generate item end Source Text Constructs Library Source Text library text not supported library descriptions not supported library declaration not supported include statement This refers to include statements within library map files See IEEE 1364 2001 section 13 2 This does not refer to the include compiler directive Configuration Source Text config declaration not supported design statement not supported config rule statement not supported default clause not supported System Timing Check Commands skew timing check not supported timeskew timing check not supported fullskew timing check not supported nochange timing check not supported System Timing Check Command Argument checktime condition not supported PLA Modeling Tasks async nand array not supported async nor array not supported async or array not supported Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX ISim User Guide Verilog Language Support Exceptions Table B 2 Verilog Language Support Exceptions Cont d Verilog Construct Exception
27. Assigns a value to a specified bit slice or all of a variable or signal quit Exits either the simulation or the tool depending on the command options restart Restarts simulation setting the simulation time back to 0 100 Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX Table 9 1 Simulation Command Summary Cont d Command Description resume With the onerror command continues executing commands after an error is encountered run Starts simulation saif Creates a Switching Activity Interchange Format SAIF file and records estimated power usage scope Navigates the design hierarchy sdfanno Back annotates delays from an SDF file to the HDL design show Displays selected aspects of the design in the Simulation Console panel step Executes simulation through your HDL design line by line to assist with debug test Compares the actual value of a net or bus with a supplied value vcd Generates simulation results in VCD format virtualbus add Adds a new virtual bus wave add Adds simulation objects or blocks to the specified wave configuration in the ISim graphical user interface wave log Logs simulation output of HDL objects to a waveform database wcfg new Creates a new wave configuration wcfg open Opens a wave configuration from a file wcfg save Saves a wave configuration wcfg select
28. File New and File Open Wave Configuration Signal and Bus Buttons The signals and buses in the Wave window can be one of the following design objects with the corresponding icon Table 2 6 lists the ISim signal buttons Table 2 7 page 19 lists the Bus signal buttons Table 2 6 Sim Signal Buttons Icon Description iB Input Port Output Port InOut Bidirectional Port Internal Signal Constants parameters and generics Variable E e EP F Linkage Signal VHDL only i lu Buffer Signal www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Table 2 7 lists the ISim Bus buttons Table 2 7 Sim Bus Buttons Button Description P Input Bus Output Bus InOut Bidirectional Bus Internal Bus Constants Parameters and Generics Bus Variable Bus amp d EE E Linkage Bus EN rs Buffer Bus Objects in the Wave Configuration Cursors The main cursor and secondary cursor in the wave configuration are used to pinpoint a time main cursor and to measure time main and secondary cursors together The cursors form the focal point for various navigation activities e Main Cursor The main cursor is a solid line that intersects the waveform and the value at that intersection is displayed in the Value column for each waveform The cursor is the current simulation
29. HDL source code for debugging purposes describe Displays information about the given HDL data or block object divider add Adds a new divider dump Displays a list of variables generics parameters and nets along with their values for the current scope of the design hierarchy group add Adds a new group help Displays a description with usage and syntax of the specified ISim command isim condition Enables the execution of a set of commands based on a specified condition on one or more nets or Verilog regs isim force Forces or removes a value on a VHDL signal Verilog wire or Verilog reg isim set arraydisplaylength Displays the limit of numbers of elements for an array type HDL object isim get radix Gets the global radix being used isim get userunit Displays the current unit of measurement for all time values where unit is unspecified isim ltrace Turns on and off line tracing isim ptrace Turns on and off tracing of execution of processes isim set arraydisplaylength Sets the limit on the number of elements for an array type HDL object isim set radix Sets the global radix to use isim set userunit Sets the default unit of measurement for all time values where unit is unspecified marker add Adds a new marker onerror For batch mode controls the behavior immediately following a failed Tcl simulation command put
30. INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF DATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION Copyright 2012 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners PCI PCle and PCI Express are trademarks of PCI SIG and used under license Revision History The following table shows the revision history for this document Date Version Revision 01 19 2011 13 4 Date and Revision change only 04 24 2012 14 1 Updated Feature Support page 3 Consolidated the Simulation chapters into Chapter 3 Compilation and Simulation Consolidated fuse vhpcomp and vlogcomp Command Options page 51 into a single table and created a top level command cross reference e Added uselib Verilog Directive in Chapter 3 Added hil zynq ps Hardware Co Simulation command to fuse command option in both Chapter 3 Compilation and Simulation and Chapter 8 Using Hardware Co Simulation e Consolidated VHDL Language Support Exceptions and Verilog Language Support Exceptions in Appendix B into two exceptions only tables 07 25 2012 142 Revised one sentence in Chapter 3 to clarify uselib directive Minor grammatical edits Updated links in Appendix D Additional Resources 10 16 2012 14 3 Added a note to functi
31. ISim GUI XILINX Define Clock Settings Examples To assign a permanent clock to a signal 100 MHz clock set the following fields e Leading Edge Value 1 e Trailing Edge Value 0 e Starting at Time Offset 0 e Cancel after Time Offset lt blank gt e Duty Cycle 50 e Period 10 ns To assign a clock to a signal for a specific period of time start toggling at 100 ns stop toggling after 1 ms set the following fields e Leading Edge Value 1 e Trailing Edge Value 0 e Starting at Time Offset 100 ns e Cancel after Time Offset 1 ms e Duty Cycle 50 e Period specify clock period To assign a toggling value for a signal toggle between hex F and hex A every 50 ns for 1us set the following fields e Value Radix Hexadecimal e Leading Edge Value F e Trailing Edge Value A e Starting at Time Offset 0 e Cancel After Time Offset lus e Duty Cycle 50 e Period 50 ns Setting ISim Preferences 32 The preference settings let you view and change the settings for ISim To set preferences 1 Select Edit gt Preferences 2 In the left pane of the Preferences dialog box click a category to view e ISE Text Editor Preferences e Sim Simulator Preferences 3 Make the necessary setting changes 4 Clickthe Apply button and then click OK The Preference settings are saved and are effective immediately in your ISim session ISE Text Editor Preferences The preference setting associated with ISE
32. ISim HDL compile programs vhpcomp vlogcomp and fuse use the xilinxisim ini configuration file to find the definitions and physical locations of VHDL and Verilog logical libraries The compilers attempt to read xilinxisim ini from these locations in the following order 1 S SXILINX vhdl hdp platform 2 User file specified through the initfile switch If initfile is not specified the program searches for xilinxisim ini in the current working directory The xilinxisim ini file has the following syntax logical libraryl1 physical dir pathi1 logical library2 physical dir path2 logical libraryn physical dir pathn The following is an example xilinxisim ini file VHDL std C libs vhdl hdp stdieee C libs vhdl hdp ieee work C workVerilog unisims ver XILINX rtf verilog hdp nt unisims ver xilinxcorelib ver C libs verilog hdp nt xilinxcorelib ver mylib mylib work C work The xilinxisim ini file has the following features and limitations e There must be no more than one library path per line inside the xilinxisim ini file e If the directory corresponding to the physical path does not exist vhpcomp or vlogcomp creates it when the compiler first tries to write to it e You can describe the physical path in terms of environment variables The environment variable must start with the character e The default physical directory for a logical library is isim logical libra
33. JTAG boundary scan chain information After you enter the board information into a board support file you can use that board for HWCoSim There is no GUI option to generate the board support file To support additional boards you can either modify the default board support file or provide your own board support file named hwcosim bsp in the directory where fuse is invoked The board support file contains board specifications in a specific format In the following example m1402 j tag is the board identifier that is provided to the fuse command to compile the design for the given board ml402 jtag gt Description gt ML402 JTAG Vendor gt Xilinx Type gt jtag Part gt xc4vsx35 10ff668 Clock gt Period gt 10 Pin gt AE14 Fo BoundaryScanPosition gt 3 Where the board identifier includes the following list of properties e Description is the description of the board e vendor is the the board vendor e Type is the type of co simulation interface to be used Allowed values are as follows jtag ppethernet for Point To Point Ethernet based HWCoSim e Part is the part name of the FPGA on the board e Clock is the system clock information where Period and VariablePeriods specifies the supported clock period s in nanoseconds 92 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012
34. October 16 2012 www xilinx com Send Feedback 135 Chapter 9 ISim Tcl Commands XILINX Create a group that adds a simulation object dcm c1k s to the group set test group id group add test group wave add dcm clk s into test group id Create groups within a group set group id group add test group set group id 1 group add group 1 into group id set group id 2 group add group 2 into group id wave add clk read ok into group id 1 wave add data w into group id 2 virtualbus add The virtualbus add command adds a new virtual bus to the currently active waveform configuration The bus is empty when it is created Subsequently HDL objects can be added to populate the virtual bus as desired virtualbus add Command Syntax virtualbus add name into lt ID gt reverse radix lt radix gt color lt color gt virtualbus add Command Options Option Description lt name gt Name of the virtual bus into lt ID gt Specifies the object ID of an existing virtual bus into which to add the new virtual bus reverse Reverses the bus order radix radix Uses the specified radix when displaying signal values The value of radix is one ofbin oct hex signed dec or ascii color color Sets the virtual bus color as specified The value of is defined in RGB format For example 0000FF is blue FF0000 is red and 00FF00 is green You can also specify the textual
35. Setting a Breakpoint To set a breakpoint do the following 1 Select View gt Breakpoint gt Toggle Breakpoint or click the Toggle Breakpoint shy button 2 In the HDL file click a line of code just to the right of the line number The breakpoint icon displays next to the line Note Alternatively you can right click a line of code and select Toggle Breakpoint After the procedure completes a simulation breakpoint icon opens next to the line of code and a list of breakpoints is available in the Breakpoints panel Debugging Your Design Using Breakpoints 1 Open the HDL source file See Opening HDL Source Files page 23 2 Set breakpoints on executable lines in the HDL source file as described in Setting a Breakpoint page 78 Repeat steps 1 and 2 until all breakpoints are set Click the Wave window to return to the waveform e Torun from the beginning use the Simulation gt Restart command e Use the Simulation gt Run All or Simulation gt Run for Specified Time command The simulation runs until a breakpoint is reached then stops The HDL source gt file displays and the breakpoint stopping point is indicated with a yellow arrow 5 Click the Wave window again to return to the waveform to determine if the design behavior such as the signal value change is as expected at the breakpoint 6 Repeat the steps to advance the simulation breakpoint by breakpoint until you are satisfied with the results A c
36. Step Runs simulation for one executable HDL instruction at a time See Stepping Through a Simulation in Chapter 6 and the step Tcl command In addition you can run simulation until a specific point in your HDL source code is reached To do so use breakpoints and the run a11 command See Chapter 6 Debugging at the Source Level Note The current simulation time displays on the status bar in the lower right corner Mixed Language Simulation ISim supports mixed language project files and mixed language simulation This lets you include Verilog modules in a VHDL design and vice versa Restrictions on Mixed Language in Simulation ISim User Guide Mixing VHDL and Verilog is restricted to the module instance or component only A VHDL design can instantiate Verilog modules and a Verilog design can instantiate VHDL components Any other mix use of VHDL and Verilog is not supported A Verilog hierarchical reference cannot refer to a VHDL unit nor can a VHDL expanded selected name refer to a Verilog unit Only a small subset of VHDL types generics and ports are allowed on the boundary to a Verilog module Similarly a small subset of Verilog types parameters and ports are allowed on the boundary to VHDL design unit Component instantiation based default binding is used for binding a Verilog module to a VHDL design unit Specifically configuration specification direct instantiation and component configurations are not supported for a
37. The object name option displays a description about either an HDL object or an HDL block in the current simulation scope describe Command Example The describe command can be used as follows describe param Returns Verilog Instance param Path parameter8_hn param Location home test5 v 42 Instantiation home test5 v 37 dump The dump command displays values for all VHDL signals and generics and Verilog wires non subprogram regs and parameters in the current scope To navigate the design hierarchy use the scope command The dump command uses the default radix set using the isim set radix command dump Command Syntax dump dump Command Example This example displays a list of all the signal names and their values at the current scope of the design hierarchy dump help The help command displays a description with usage and syntax of the specified ISim Tcl command With no command specified the help command displays descriptions usage and syntax for ISim Tcl commands Help Command Syntax help command_name help Command Options help displays a description for the specified command help Command Examples The help command can be used as follows For a description of all of ISim commands 106 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands help For a description of the bp command help bp isim condition The isim condition c
38. Turns error messages into warning messages This lets you continue simulation even though there are errors in SDF back annotation root root path Specifies the place in the design to apply annotation The paths specified in the SDF file are relative to the place in the design hierarchy specified by root path By default the root is at the top level of the design sdfanno Command Examples sdfanno typ Examples Annotate the submodule called subdesign with the typical delay values from mysubdesign sdf sdfanno typ mysubdesign sdf root subdesign Annotate the current top level design with the typical delay values from design sdf and ignore all errors or warnings sdfanno typ design sdf noerror nowarn sdfanno min Example Annotate the submodule subdesign with the minimum delay values from mysubdesign sdf sdfanno min mysydesign sdf root subdesign sdfanno max Example Annotate the current top level design with the maximum delay values found in design sdf and ignore warnings sdfanno max design sdf nowarn 122 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands show The show command displays selected aspects of the design show Command Syntax show child child r constant driver signal name load lt signal_name gt port scope signal time value lt generic_name gt lt parameter_name gt lt
39. VHDL only option Specifies the time precision unit of accuracy for all VHDL design units The time precision is entered as number 1 10 100 followed by unit s ps ns us ms s Default is 1ps timescale time unit time precision Verilog only option Specifies the default timescale for Verilog modules that do not have an effective timescale e time unit is the unit of measurement of delays e time precision is the unit of accuracy Both time unit and time precision are entered as number 1 10 100 followed by unit s ps ns us ms s Default is 1ns 1ps typdelay Verilog only option Specifies that if fuse calls vlogcomp it should use typical delays timeprecision vhdl time precision VHDL only option Specifies the time precision unit of accuracy for all VHDL design units The time precision is entered as number 1 10 100 followed by unit s ps ns us ms s Default is 1ps 54 Send Feedback ISim User Guide UG660 v14 3 October 16 2012 www xilinx com XILINX ISim Executable Command Table 3 7 fuse vhpcomp and vlogcomp Command Options Cont d Option v verbose value Description Specifies the verbosity level for printing messages Values are 0 1 2 Default is 0 For example fuse v 1 prints useful debugging information which can help to identify problems in ISim compilers Th
40. Verilog module instantiated inside a VHDL design unit www xilinx com 45 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX Key Steps in a Mixed Language Simulation 1 Optionally specify the search order for VHDL entity or Verilog modules in the design libraries of a mixed language project 2 Usefuse Lto specify the binding order of a VHDL entity or a Verilog module in the design libraries of a mixed language project Note The library search order specified by L is used for binding Verilog modules to other Verilog modules as well Mixed Language Binding and Searching When you instantiate a VHDL component or a Verilog module the fuse command e First searches for a unit of the same language as that of the instantiating design unit e Ifa unit of the same language is not found fuse searches for a cross language design unit in the libraries specified by the 1ib option The search order is the same as the order of appearance of libraries on the fuse command line See Verilog Search Order page 40 for more information Note When using the ISE Design Suite the library search order is specified automatically No user intervention is necessary or possible Instantiating Mixed Language Components In a mixed language design you can instantiate a Verilog module in a VHDL design unit or a VHDL module in a Verilog design unit as described in the following subsections Mixed Language B
41. below that signal 2 From the context menu select Edit gt New Divider or right click and select New Divider The change is visual and nothing is added to the HDL code The new divider is saved with the wave configuration file when you save the file Changing Dividers ISim User Guide The following changes can be made to a divider e Dividers can be renamed See Renaming Objects page 65 e Dividers can be moved to another location in the waveform by dragging and dropping the divider name www xilinx com 63 UG660 v14 3 October 16 2012 usc Chapter 4 Waveform Analysis XILINX Deleting Dividers To delete a divider highlight the divider and click the Delete key or right click and select Delete from the context menu Groups A Group is a collection of expandable and collapsible categories to which signals and buses can be added in the wave configuration to organize related sets of signals The group itself displays no waveform data but can be expanded to show its contents or collapsed to hide them Adding a Group To add a Group 1 Ina wave configuration select one or more signals or buses to add to a group Note A group can also comprise dividers virtual buses and other groups 2 Select Edit gt New Group or right click and select New Group from the context menu A group that contains the selected signal or bus is added to the wave configuration A group is represented with the group icon Th
42. can be accomplished at the same time When simulation ends close the SAIF or VCD file by issuing the saif or vcd command Examples are saif close ved dumpoff Retrieve the SAIF or VCD file from the working directory for use in another tool www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Prerequisites Chapter 6 Using Hardware Co Simulation Hardware Co Simulation HWCoSim is a complementary flow to the tool based HDL simulation This feature lets you simulate a design or a portion of the design and offload that simulation to hardware It can accelerate the simulation of a complex design and verify that the design works in hardware Prerequisites Hardware co simulation has the following requirements Use Models Xilinx ISE Design Suite 14 x any edition 32 bit or 64 bit Windows or Linux An FPGA board with a JTAG header Supported FPGA devices are e Virtex amp 4 Virtex 5 Virtex 6 Virtex 7 e Spartan 3 Spartan 3E Spartan 3A Spartan 3AN Spartan 3A DSP Spartan 6 e Artix 7 and Kintex 7 A Xilinx Parallel Cable IV or Platform Cable USB HWCoSim supports two use models one for pure logic based designs and another for hybrid designs Pure Logic based Designs Pure logic based designs are co simulated in a lockstep fashion with ISim The modules under co simulation typically have the following characteristics Composed of LUTs FFs block RAMs and DSP
43. declared as a signal in your Hardware Description Language HDL source code You cannot use the put command to assign a value to a VHDL variable a VHDL generic or a Verilog parameter You can assign values to the whole signal a bit of a signal or a slice of a signal You can also access the signal hierarchically This command can be overridden 114 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands The stimulus from your design can override the put command consequently the command is temporary put Command Syntax put signal name vhdl process name process variable name element reference value object value radix radix type put Command Options Table 9 6 put Command Options Option Description signal name signal name is the name of the signal or bus to vhdl process name which you want to assign a value This can also be the name of an array of signals or buses an array of records containing signals and buses or a record of arrays of element reference buses signals process variable name value e vhdl process name process variable name is the name of the process and process variable to assign a value To assign a value to a process variable you must also supply the name of the process that contains the variable The process name and process variable names must be separated by a
44. design source code ISim User Guide www xilinx com 65 UG660 v14 3 October 16 2012 Send Feedback Chapter 4 Waveform Analysis XILINX Display Names You can display the full hierarchical name long name the simple signal or bus name short name or a custom name for each signal The signal or bus name displays in the Name column of the wave configuration If the name is hidden e Expand the Name column until you see the entire signal name e Use the scroll bar in the Name column to view the name Changing Display Names To change the display name 1 Select one or more signal or bus names Use Shift click or Ctrl click to select many signal names 2 Right click and select Name gt e Long to display the full hierarchical name e Short to display the name of the signal or bus only e Custom to display the custom name given to the signal when renamed See Renaming Objects page 65 The name changes immediately according to your selection Radixes The default radix controls the bus radix displayed in the wave configuration the Objects panel and the Console panel Changing the Default Radix The default radix is binary To change the radix do the following Select Edit Preferences In the Preferences dialog box click ISim Simulator in the left pane From the Default Radix drop down list select a radix Click Apply and click OK p Oo Jr oqo Changing an Individual Radix You can change the rad
45. following fields e Units Lets you set the units for time values The default settings for the Other GUI elements is Default for the Waveform Window the default is Auto e Decimal Places Lets you set the number of decimal places to be used in displaying time values The default setting for all categories that have a setting is Maximum e Reset To Defaults Resets the values to the original default settings www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Chapter 3 Compilation and Simulation You can run simulation for VHDL Verilog or Mixed Language components e Functional Simulation can be run early in the design process e Timing Simulation must be run post Place and Route PAR In addition to the two types of simulation you have the options of running simulation as follows e From a Tools Command Language Tcl batch file or from the command line using Tcl commands e From the GUI which can be invoked from either the ISE Design Suite or the PlanAhead tools Running a simulation from the command line for either a Functional or a Timing simulation requires the following steps 1 Parsing design files 2 Generating a simulation executable 3 Simulating the design There are additional requirements for a Timing simulation which is described in Timing Simulation Gate Level Simulation page 49 The following subsections describe these steps ISim User Guide www xilinx
46. in the specified sourcelibdir directory If such a file exists vlogcomp analyzes that file While processing the sourcelibdir switch vlogcomp ignores any files with extensions such as v or h unless sourcelibext is also used Note sourcelibext provides functionality that is similar to the 1ibext switch in Verilog XL You can use this command line argument in conjunction with sourcelibdir when the source library files have extensions Examples vlogcomp sourcelibdir project mysources tb v fft v vlogcomp sourcelibdir project mysources tb v fft v sourcelibext v You can also provide a source Verilog library file that contains definitions of all the unresolved modules Example sourcelibfile library lib abc v ISim User Guide www xilinx com 37 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX vhpcomp Command The vhpcomp command parses VHDL source files and stores a binary representation of the HDL files The binary representation generated by vhpcomp is used by the use command to create a simulation executable Specify either a project file or one or more VHDL files If neither project file nor VHDL file are specified vhpcomp issues an error See Project File Syntax page 43 for information about the project file vhpcomp Syntax To go to the command option click the option link Note n your PDF reader turn on Previous View and Next View Buttons to na
47. interface of the DUT can be accessed from ISim through the hardware co simulation interface To debug an internal signal you need to route the signal to a port of the DUT Clocking and I Os 1 96 Q Which clock is supplied to the DUT How is the clocking of the DUT being handled during co simulation A The clock pin of the hardware board specified in the board support file is the master clock source but is not used directly to drive the DUT This clock source is scaled to a particular clock frequency typically around 25 to 100 MHz through a DCM PLL The scaled clock further goes through a gated clock buffer BUFGCTRL before driving the clock port of the DUT The gated clock buffer generates a clock pulse to the DUT per simulation cycle to synchronize the tool simulation and the DUT execution Q Can I et the DUT clock be free running A In hybrid co simulation you can let a portion of the DUT be free running by mapping one or multiple clock ports to external I Os However at least one clock of the DUT must be clocked in a lockstep fashion synchronous to the tool simulation That effectively partitions the DUT into two portions one running in lockstep and the other free running Also note that ISim hardware co simulation does not insert any clock domain crossing between the two portions www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide Frequently Asked Questions
48. name of a color for some of the popular colors The following color names are accepted black red darkred green darkgreen blue darkblue cyan darkcyan magenta darkmagenta darkyellow gray darkgray lightgray The RGB values for these colors are defined in the RGB table virtualbus add Command Examples Add a virtual bus with name mybus having radix as hexadecimal to the current wave configuration virtualbus add mybus radix hex 136 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Create a virtual bus that adds two simulation objects sigA and sigB to the virtual bus set vbusId virtualbus add mybus radix hex wave add sigA into vbusId wave add sigB into vbusId marker add The marker add command adds a new marker marker add Command Syntax marker add time The time option lets you specify the time location at which to add the new marker If you do not specify the time unit you can get the default user time unit by running the isimget userunit command marker add Command Examples Add a marker at 10 ns to the current wave configuration marker add 10 ns ISim User Guide www xilinx com 137 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX 138 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Appendix A Library Mapping File xilinxisim ini The
49. on VHDL assignments This option does not affect index range checking for arrays ISim always checks an index into an array for being within the allowed range For example e Jfa signalis declared as positive fuse checks that the signal is not assigned a negative number e Ifasignal is declared as std_logic vhpcomp generates output to check that the signal is assigned only valid std logic values U X 0 1 Z W L H Note This option does not affect the checking of index ranges The simulator always checks the index ranges By default rangecheck is turned off sdfnoerror Treats SDF errors as warnings sdfnowarn Blocks the display of SDF warnings sdfmin sdftyp sdfmax root file Specifies the type of delays to use e sdfmin nnotates ile at root with minimum delay e sdftyp Annotates lt file gt at root with standard delay e sdfmax Annotates lt file gt at root with maximum delay sdfroot root path Sets the default location in the design hierarchy in which to apply the SDF annotation sourcelibdir directory name Specifies the source directory for library modules sourcelibext file extension Specifies the file extension for source files for modules The sourcelibdir option provides the location for these files sourcelibfile file name Specifies the filename for library modules timeprecision vhdl time precision
50. operations Measuring with Markers and Cursors Measuring with markers and cursors is different between ModelSim XE and ISim ModelSim XE provides cursors to measure between two points of interest You can add cursors as needed and each new cursor gets added under the existing cursors The waveform viewer automatically shows the distance between the cursors Figure C 2 shows the ModelSim XE waveform with cursors Messages Itestbench ONES itestbench TENS Jtestbench CLK Jtestbench RESET testbench STRTS jtestbench GSR ftestbench TENTH a ees eee Se See ERE 1000000 ps 300000 ps 700000 ps Cursor 3 800000 ps Figure C 2 ModelSim XE Waveform View with Cursor ISim has a different approach to measuring ISim uses both cursors and markers While in ModelSim XE a cursor is a permanent measuring stick Sim cursors are treated as temporary ISim has a primary and a secondary cursor that together can be used to measure between two points ISim markers let you measure between multiple points including the primary cursor Figure C 3 shows the ISim measure in use ISim User Guide www xilinx com 151 UG660 v14 3 October 16 2012 Send Feedback Appendix C Migrating from ModelSim XE to ISim XILINX 200 ns 400 ns 600 ns 800 ns 1111111110 Figure C 3 Sim Measure in Use ISim also provides a ruler for frame of reference The selected marker or cursor is always the 0 location against which all other mar
51. primitives only Port controlled by ISim and accessible from the tool test bench no external I Os Functionality of the module is irrelevant of the clock frequency at which it operates there is no need to run on a continuous clock or a clock at a specific frequency The pure logic lockstep based HWCoSim provides the following advantages ISim User Guide Simulation acceleration for computational intensive designs In hardware functional verification Bit and cycle accurate with respect to pure tool simulation www xilinx com 83 UG660 v14 3 October 16 2012 usc Chapter 8 Using Hardware Co Simulation XILINX Hybrid Designs The pure logic based design use model is simple and trivial to set up but is not suitable for designs that require hard IPs external I Os and specific clock frequencies ISim HWCoSim provides a hybrid co simulation flow that supports designs with the following characteristics e Composed of hard IP blocks DCMs PLLs and MGTs e Some clocks are in lockstep with the tool simulation using emulated clock sources and other clocks are free running using external clock sources e Some ports can be mapped to external I Os which are neither controlled by ISim nor accessible from tool test bench The hybrid co simulation flow offers the following advantages e Accelerates simulation e Verifies functionality in hardware e Allows customized or complicated software and hardware interactions beyond a typica
52. process_name gt lt process_variable_name gt element references show Command Options object signal name radix radix type variable Table 9 11 show Command Options Option child child r Description The child displays the children blocks one level only from the current block The child r option recursively lists all children blocks including the child processes from the current block constant Lists constants generics and parameters within the current block driver signal name Displays the processes that are driving the signal specified by signal name If possible it prints the line numbers of the HDL code that is contributing to the driver load signal name Displays all of the load for the signal specified by gignal name port Displays the port signals within the current block This command identifies signals as inputs or outputs scope Displays the current scope in the design hierarchy You can view but not alter the hierarchy location This command is identical to the scope command without the lt path_name gt option signal Displays signals within the current module including port signals time Displays the simulator current time value lt generic_name gt lt parameter_name gt lt process_name gt lt process_variable_name gt generic name is the name of the VHDL generic to be
53. signal Verilog wire or Verilog reg to a constant value or a repeating pattern over time The value applied by the isim force command overrides any value assigned from within the HDL code or any value applied by a previous force The force remains active until cancel time if a cancel time is specified or until an explicit isim force remove command is issued e Fora VHDL signal or a Verilog wire removal of a force restores the value of the signal or the wire to the current driven value e Fora Verilog reg the forced value is retained even after the applied force has been removed until the time one of the HDL processes that write into the Verilog reg gets to assign a new value to the reg isim force Command Syntax isim force add remove lt object_name gt value lt value gt radix lt radix_type gt time lt time gt cancel lt time gt repeat lt time gt isim force Command Options Table 9 5 sim force Command Options Option Description add remove Specifies whether you wish to assign or remove a value from a bus or signal lt object_name gt Specifies name of the VHDL signal Verilog wire or Verilog reg to be forced value lt value gt Specifies one or more values to add radix lt radix_type gt This option specifies the radix The supported radix types are default dec bin oct hex unsigned and ascii When no radix type is specified the global radix type set with the isim set
54. signal You can choose one of the supported radix types Binary Hexadecimal Unsigned Decimal Signed Decimal Octal and ASCII e Force to Value Specifies a force constant value using the defined radix value e Starting at Time Offset Starts after the specified time The default starting time is 0 Time can be a string such as 10 or 10 ns When you enter a number without a unit ISim uses the default e Cancel after Time Offset Cancels after the specified time Time can be a string such as 10 or 10 ns When a number entered without a unit the default simulation time unit is used Applying Clock Stimulus When you right click Force Clock you can use the Define Clock dialog box to enter parameters to force a VHDL signal Verilog wire or a Verilog reg to an alternating pattern clock The newly applied clock pattern overrides assignments made from within HDL code or any previously applied constant or clock force Click Apply to apply changes 30 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Define Clock Dialog Box Right click Force Clock to open the Define Clock dialog box The options in the dialog box are e Signal Name Displays the default signal name which is the full path name of the item selected in the Objects panel or waveform You can change the signal name in the edit box When you enter an invalid signal name in the edit box the edit box turns red
55. signals that are traced when you launch the GUI The simulator runs for the time specified under the ISE simulation process property Simulation Run Time See Simulation Properties in ISE Help for details To run for an additional time use one of the run simulation commands described in Simulating the Design page 44 Interactive Command Line Mode Run the simulation executable for example my sim exe When the Tcl prompt displays type the run command Optionally you can also invoke the simulation executable with a Tcl file by leveraging the tclbatch option for example my sim exe tclbatch my sim tcl Ensure that this step was run successfully If not see Examining Error Messages and Examining Log Files in Step 5 Debugging the Design 6 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Simulation Steps Overview Step 4 Examining the Design After the design is simulated you debug the design to ensure that it meets the design specification You can examine the simulation results by e Viewing the signal interactions in the Wave window e Viewing or querying the results in the Console panel or the Tcl prompt In the debug phase you can do the following e Save the results see Saving Simulation Results page 56 e View and examine simulation results in a read only static simulator see Opening a Static Simulation in Chapter 5 Step 5 Debugging the Design If yo
56. slash symbol e The optional lt element reference refers to the different ways in which the sub elements of the signal name can be referenced when used with the put command You can use it to further refine the signals by referencing the individual sub elements of a signal See the following examples for more information The accepted lt value gt depends upon the signal type as follows Integer type can be a positive or negative integer e A bit vector can be or 1 ora series of 0s and 1s e For VHDL std_logic values can be U X 0 1 e For Verilog bit values can be U X O 1 Strength values are not supported object value Takes a value with the specified radix converts the value to radix radix type the data type of the object and writes the value to the 7 object lt object gt specifies the signals buses or objects to modify lt value gt refers to the value you wish to add to the object Supported radix types radix radix types default dec bin oct hex unsigned and ascii When no radix type is specified the global radix type set with the isim set radix command is used or if none is set there default is used as radix ISim User Guide www xilinx com 115 UG660 v14 3 October 16 2012 send Feedback Chapter 9 ISim Tcl Commands XILINX put Command Examples Assign a Value To a Bus or Signal Assign a value to a signal called c1k put clk 1 O
57. the simulation launches in command line mode For example type x exe The ISim gt Tcl prompt opens and you can interactively type simulation Tcl commands that let you run simulation and debug the design You can use the tclbatch option to contain commands within a file and execute those command as simulation starts For example you can have a file named run tcl that contains the following run 20ns show time quit Then launch simulation as follows x exe tclbatch run tcl 44 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Mixed Language Simulation Using the GUI The following example shows command options for running the simulation executable and opening the GUI executable name exe gui You can use the following GUI menu commands to run simulation Simulation Restart Stops simulation and sets simulation time back to 0 Use the Run All Run for or Step command to run the simulation over again without reloading the design Alternatively you can type the restart Tcl command in the Console panel Simulation gt Run All Runs simulation until all events are executed Alternatively you can type the run a11 Tcl command in the Console Simulation Run Runs simulation for 100ns or for the specified amount of time Type the Time and time unit in the Value box Alternatively you can use the run Tcl command with a specified length and unit Simulation
58. the panel click the Clear All button To open the file that contains the find result in the Workspace select a find 5 result and click the Show Current Result button Alternatively you can double click the find result to open the file l To view the next find result click the Show Next Result button To view the previous find result click the Show Previous Result button o To stop the currently running Find in Files search click the Stop Job button To save your Find in Files search results to a Comma Separated Value H CSV file click the Save Results as a Text File button Re launching Simulation a modification in an Hardware Description Language HDL file to fix an The Re launch button lets you re launch the ISim simulation after making L3 ReJaunch identified issue You also can recompile from the ISim GUI Recompile and Re launch are fully automated features The dialog box messages specify where an issue is located Re launch keeps all the options as set at compile time and automatically runs simulation to the specified runtime when the flow was launched from either the Project Navigator or the PlanAhead tool e When you successfully re launch a simulation your simulation completes without errors e When you re launch an unsuccessful simulation a dialog box opens with the syntax error failure to the compiled source code The links go to the source code with errors in the source window It is recommended that
59. the selected marker The floating ruler button and the floating ruler itself are visible only when the secondary cursor or selected marker is present 1 Doeither of the following to display or hide a floating ruler e Place the secondary cursor e Select a marker 2 Select View gt Floating Ruler or click the Floating Ruler button You only need to follow this procedure the first time The floating ruler displays each time the secondary cursor is placed or marker is selected Select the command again to hide the floating ruler Displaying Waveform Values With Markers Markers which are lines that intersect the waveform at a particular time can be used to navigate through the wave configuration and to display the signal and bus values in the Value column for each marker Follow this procedure to jump the main cursor from marker to marker to display waveform values 1 Inthe wave configuration in the Wave window add one or more markers as described in Adding a Marker page 62 For a single marker if the main cursor and marker occupy the same location the Value column displays the signal and bus values No further action is required For multiple markers continue 2 Select Edit gt Markers gt Next Marker or click the Next Marker button The cursor advances through markers in the wave configuration 3 Observe the values in the Value column at each marker 68 www xilinx com ISim User Guide Send Feedback UG660 v1
60. to print Pe Ce Select Close to close the Print Preview dialog box Print preview displays the wave configuration in black and white or color as determined by your default printer You can select another printer if available just prior to printing ISim User Guide www xilinx com 71 UG660 v14 3 October 16 2012 Send Feedback Printing Chapter 4 Waveform Analysis XILINX 1 Select File Print 2 Inthe Print Setup dialog box specify the Page Orientation Time Range Fit Time Range To and other display settings Note Time Range is populated with the time range of the main and secondary cursor if both are placed in the wave configuration 3 Click OK 4 Inthe Print dialog box select a printer and click Print The wave configuration prints according to the print settings Using Custom Colors 72 You can change the color for individual signals or buses to make them stand out for comparison purposes General color settings are part of the color scheme specified in the Colors Preferences page See ISim Color Preferences in Chapter 2 You can use pre defined color schemes or create your own color scheme Changing an individual signal or bus color overrides the general color setting for signal or bus waveforms 1 Right click on a signal or bus 2 Select Signal Color and a color The signal or bus waveform displays the new color selection Note When using custom colors all logic values including specia
61. true This command is surrounded by braces The command can include standard Tcl commands and simulation Tcl commands except run restart init and step Tcl variables used in the condition expression are surrounded by quotes instead of Refer to the syntax examples below ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback 197 Chapter 9 ISim Tcl Commands XILINX Table 9 4 isim condition Command Options Cont d Option Description radix radix type Anoptional argument used to read the value in the condition expression The supported radix types are default dec bin oct hex unsigned and ascii When no radix type is specified the global radix type set with the isim set radix command is used or if none is set there default is used as radix label label name An optional argument that specifies the name of a condition For isim condition add when no label is specified the simulator generates an index used to identify the condition index lt index_name gt An optional argument that identifies a condition Can be used with isim condition remove only all An optional argument that is used to remove all conditions in the current simulation isim condition Command Examples isim condition add Examples Adding a condition that states that when the signal asig is equal to 8 a stop occurs and the condition is called 1abe10
62. two Verilog files specify a source library directory and specify a Verilog file extension vlogcomp tb v fft v sourcelibdir mylib sourcelibext v Specify a Verilog file and the source library file vlogcomp dff v sourcelibfile mylib dff lowest v Specify the work directory and a Verilog file vlogcomp work my lib tb v Use two files vlogcomp top testbench v top timesim v 36 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Parsing Design Files Search for unresolved cells inside directory mydir cells vlogcomp work mywork1 filel v sourcelibdir mydir cells For example if file1 v instantiates DFF and DMUX which are unresolved the command then searches for files with names DFF and DMUX inside the mydir cells directory The DFF and DMUX files define the DFF and DMUX modules Supporting Source Libraries The following command arguments provide equivalent support to the de facto Verilog XL standard Pass the following command options to the vlogcomp command vlogcomp sourcelibdir library location Note sourcelibdir provides the same functionality as the y switch in Verilog XL After the source files on the command line are parsed if there are any unresolved references to modules the command searches the source libraries for resolution During this search v1ogcomp attempts to match the name of any unresolved instantiated design unit with a file of the same name
63. up and down Left Previous Transition Right Next Transition Pause Break Instances and Processes Panel The Instances and Processes panel displays the block instance and process hierarchy associated with a wave configuration that is open in the Wave window Instantiated and elaborated entities and modules display in a tree structure components being entities processes tasks and blocks The columns in this panel are e Instance and Process Name Shows the instance process and static tasks or functions buttons in a tree structure showing the block hierarchy of the design Design Unit Displays the names of the design units Verilog module or VHDL entity architecture corresponding to the instance static task or function or process from the first column e Block Type Displays the type of the instance static task or function or process for example Verilog Module The Instances and Processes tabs are e Instance Displays the instance process and static tasks or functions buttons in a tree structure showing the block hierarchy of the design e Memory Displays the memory of the design object See Using the Memory Editor page 26 e Source Files Lists the source files of the design Figure 2 2 page 14 shows the Instances and Processes panel Instances and Processes epneax 8 ce lota SG Instance and Process Name Design Unit Block Type EH testbench testbench Verilog Module iJ gibi gibi Verilog Module
64. values in the vector specified by signal name Forexample show value 3 0 Oneor more integers separated by commas and enclosed by parenthesis displays the values of elements in a multidimensional array specified by lt signal_name gt For example show value 2 3 lt object gt radix lt radix_type gt lt object gt radix lt radix_type gt displays values with the specified radix For lt object gt set the HDL object data type Supported radix type are default dec bin oct hex unsigned and ascii When no radix type is specified the global radix type set with the isim set radix command is used or if none is set with that command default is used show variable variable Displays all of the variables within the current block To see variables within a VHDL process use the scope command to navigate to the VHDL process and then run show Command Examples show child If you are located at the top level of the hierarchy in a design called fifo_controller and type show child the following hierarchy information displays Block Name fifo controller Type show child r for the same level of the design and the current and recursive hierarchy information displays Sand Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX show driver Tcl Commands If you are located at the top level of the hierarchy in a design called ifo count and t
65. view Used in combination with the gui switch to open the specified waveform file in the waveform file wcfg ISim GUI wdb Saves simulation data to the specified WBD file waveform file wbd For example x exe wdb my wdb saves the simulation data to my wdb instead of the default isimgui wdb ISim Executable Command Examples lt executable_name gt exe tclbatch lt tcl_file_name gt sdfmin lt instance gt lt sdf_file name gt Where e lt executable_name gt exe is the simulation executable called x exe unless otherwise specified with the fuse o switch e tclbatch is an optional switch to use when you want to run additional Tcl commands e sdfmin is the type of delay minimum to use e lt instance gt is the hierarchical path name of the instance at which the Standard Delay File SDF back annotation needs to be done e lt sdf_file_name gt is the filename of the SDF file to annotate fuse vhpcomp and vlogcomp Command Options Table 3 7 lists the use vhpcomp and v1ogcomp command options Table 3 7 fuse vhpcomp and vlogcomp Command Options Option Description d Verilog only option Define the macros used in Verilog files and any macro definition value value required values You can specify more than one d option Note Ensure that there is no space between the and the value the space would be interpreted as part of the value Double quote any path that contai
66. xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Opening a Static Simulation In a command prompt run isimgui exe open lt wdb gt wdb view wcfg wcfg Where e isimgui exe is the application executable e open lt wdb gt wdb opens the specified waveform database file in the ISim graphic user interface e view lt wcfg gt wcfg opens the specified waveform file in the ISim graphical user interface Opening a Waveform Database and a New Default WCFG If you have simulation data WDB that you wish to analyze and you do not want to open a previous WCFG use the following method to open the Waveform Database and a new default WCFG In a command prompt type isimgui exe view lt wdb_file gt wdb Where e isimgui exe is the application executable e view lt wdb gt wdb opens the specified waveform database file in the ISim graphical user interface The static viewer displays the data from the previous simulation and a new wave configuration file named as Default wcfg that displays up to a maximum of 1000 objects from the WDB file in the Wave window You can remove or add signals to the default WCIG file and save the WCFG for future viewing Opening a Waveform Database Only ISim User Guide If you would like to open a WDB from a previous simulation and no WCFG use this method 1 Ina command prompt type isimgui exe This opens the static simulator 2 Select File gt O
67. 4 3 October 16 2012 XILINX 4 5 Navigating the Wave Configuration Select Edit Markers Previous Marker or click the Previous Marker button ix The cursor moves backward through markers in the wave configuration i Observe the values in the Value column at each marker Displaying Waveform Values at Signal Transitions You can view signal values at each transition of a signal in your waveform using the Next Transition or Previous Transition commands The starting point is the main cursor Using Next and Previous Transition Commands 1 7 Select a signal The starting point is the location of the cursor in the waveform To advance to the next transition select View Cursors Next Transition or click the Next Transition button i The marker advances to the next transition for the selected signal The values for all signals at that time are displayed in the Value column Repeat step 2 as necessary To go back to the previous transition select View gt Cursors gt Previous Transition or click the Previous Transition i button The marker moves back to the previous transition for the selected signal The values for all signals at that time display in the Value column Repeat step 4 as necessary The cursor advances or moves back and the signal values are updated Measuring Time with Cursors Together the main and secondary cursors in the wave configuration measure a range of time In add
68. AD Notice that you must constrain the extended identifiers CLK and PAD with a backslash at the beginning and at the end sdfanno The sdfanno command back annotates VITAL delays from a Verilog Standard Delay Format SDF file to a VHDL design that is made of VITAL compliant VHDL models The sdfanno command also back annotates to the timing specified in specify blocks of Verilog modules sdfanno Command Syntax sdfanno min typ max lt file_name gt file name nowarn noerror root lt root_path gt Where min typ max and ile name are required The options are any options listed in Table 9 10 page 122 ISim User Guide www xilinx com 121 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX sdfanno Command Options Table 9 10 sdfanno Command Options Option Description min typ max A delay switch type min typ or max must be specified in the sdfanno command e min Annotates VHDL Verilog file with fastest possible delay values and gives you a Hold Time timing simulation e typ Annotates VHDL Verilog file with typical delay values max Annotates VHDL Verilog file with longest possible delay values and gives you a Setup Time timing simulation file name Name of the SDF file that contains the delay information A filename must be specified in the sd anno command nowarn Turns off warning messages noerror
69. Additional Resources provides links to these documents 8 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Chapter 2 Using the ISim GUI The ISim Graphical User Interface GUI consists of the main window which contains panels the Workspace toolbars and the status bar In the main window you can e View the parts of the design that can be simulated e Add and view signals in the wave configuration e Use commands to run simulation e Examine the design and debug as necessary ISim GUI Overview The ISim GUI launches when you run the simulation executable from the ISE tool the command line or the PlanAhead tool Figure 2 1 shows the ISim GUI 72 ISH D efault v rcfg Oe Instances and Processes TOBEE I C stimulus std logic 1164 attributes std log misc numeric std 34 textio vital timing vital primitives std logic arith std logic textio std logic unsigned vcomponents 3 vpkg d prims constants v8 0 n lt Y 31 ieu 51 1 Instances and Proces Source Fi K i Default wcfg 3 stopwatch_tb vhd Console rinisnea creut nmalzaoon process e ns File C Documents and Settngs chantal watchwhd stopwatch tb vhd Line 49 299589 i Documents and Rag dodi ede pde vind Line 49 Console Breakpoits Find n Files Results Search Results 23 995 895 000 ps Figure 2 1 ISim GUI
70. Compilation and Simulation Simulation Steps Overview The steps for simulating a design in ISim are Step 1 Gathering Files and Mapping Libraries Step 2 Parsing and Elaborating the Design Step 3 Simulating the Design Step 4 Examining the Design Step 5 Debugging the Design Step 1 Gathering Files and Mapping Libraries The required files to run a simulation in ISim are as follows Design files including stimulus file User libraries Miscellaneous data files www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Simulation Steps Overview Stimulus File Include an HDL based test bench as the stimulus file You can create or edit your test bench using any of the following e Text Editor Create or edit an HDL test bench in any text editor Language Templates Use a template to populate the file correctly such as those available with the ISE tool For more information see Using the Language Templates in ISE Help e Third party tool Create or edit an HDL test bench in any vendor provided tool User Libraries Depending upon how you launch ISim there are different methods available to add user libraries e When launching Project Navigator define the user libraries in the ISE tool See Working with VHDL Libraries in ISE Help for details e When using ISim standalone interactive command mode or non interactive mode set the library mapping file see Appendix A Library
71. Ctrl V The signal or bus is now copied to the wave configuration You can move the signal or bus using drag and drop as needed 60 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Customizing the Wave Configuration Customizing the Wave Configuration You can customize the Wave configuration using the features that are listed and briefly described in Table 4 1 the feature name links to the subsection that fully describes the Cursors Placing the Main Cursor ISim User Guide feature Note n your PDF reader turn on Previous View and Next View Buttons to navigate back and forth Table 4 1 Feature Description Cursors The main cursor and secondary cursor in the Wave window let you display and measure time and they form the focal point for various navigation activities Markers You can add markers to navigate through the waveform and to display the waveform value at a particular time Dividers You can add a divider to create a visual separator of signals Groups You can add a group that is a collection to which signals and buses can be added in the wave configuration as a means of organizing a set of related signals Virtual Buses You can add a virtual bus to your wave configuration to which you can add logic scalars and arrays Renaming Objects You can rename objects signals buses and groups Display Names You can display the full hierarch
72. File Other Compiler Options Value Range Check g Library for Verilog Sources Specify Search Directories for Include Specify define Macro Name and value Specify Top Level Instance Names Other Simulator Commands 1000 ns Wawveform Database Filename C Documents and Settings lammers watchver testbench isim beh wdb zd work testbench Property display level Advanced w Display switch names Figure C 4 Project Navigator Project Settings Dialog Box with ISim Selected Default ISim User Guide www xilinx com UG660 v14 3 October 16 2012 Send Feedback 153 Appendix C Migrating from ModelSim XE to ISim XILINX The simulation properties are similar between ModelSim XE and ISim the following table lists the differences Table C 2 Simulation Properties in Project Navigator ModelSim XE Property Name Library Compilation ISim Property Name Comments Compiled Library Directory Pre compiled libraries delivered with ISE Design Suite BR installation for ISim Ignore Pre compiled Library Warning Check Tn Generate Verbose Library Compilation Messages N A Custom User Commands Use Custom Do File Use Custom Simulation Command File Use Custom Wave Configuration File Custom Do File Custom Simulation Command File Custom Wave Configuration File ISim supports Tcl commands to control engine operation as well as to control most common GUI operation
73. For example uselib dir file f v lib newlib Is illegal Multiple libraries can be specified in one uselib directive The order in which libraries are specified determine the search order For example uselib lib mylib lib yourlib Specifies that the search for an instantiated module is made in my1ib first followed by yourlib Like uselib dir uselib file and uselib libext directives the uselib lib persists across HDL files in a given invocation of parse analyze such as in a given invocation of parse unless another uselib is encountered any previously encountered uselib including any Verilog XL uselib directive in the HDL source remains in effect A uselib without any argument removes the effect of any currently active uselib lib file dir libext The following module search mechanism is used for resolving an instantiated module or UDP by the Verific Verilog elaboration algorithm First search for the instantiated module in the ordered list of logical libraries of the currently active uselib lib if any e f not found search for the instantiated module in the ordered list of libraries provided as search libraries in fuse command line e Ifnot found search for the instantiated module in the library of the parent module For example if module A in library work instantiated module B of library mylib and B instantiated module C then search for module C in library mylib which is the library of C s pa
74. G660 v14 3 October 16 2012 Send Feedback 125 Chapter 9 ISim Tcl Commands XILINX show value of Array of Objects The following examples refer to an array of standard logic vectors that is declared as follows signal sigarray vectorarray 0 to 5 1 to 4 2 to 6 Query every bit of a vector array element of sigarray show value sigarray 0 1 2 Query the first two bits of each array element of sigarray show value sigarray 0 1 2 1 2 Query bits three of each array element of sigarray show value sigarray 0 1 2 3 An array of records which in turn contains an array of standard logic vectors is declared as follows type ram 3d vector is array 0 to 10 7 downto 0 0 to 2 of std logic vector 1 to 4 type rectype is record a integer b string 1 to 7 c std logic vector 0 to 3 d ram 3d vector end record type recarray is array 0 to 3 4 downto 1 of rectype signal recarrsig recarray signal recsig rectype Query the second element b of the record recsig show value recsig b 2 4 Query the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig show value recsig d 2 3 1 Query the first two bits of the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig show value recsig d 2 3 1 1 2 Query the four bit wide vector represented by the coordinates 2 3 1 in the three dim
75. ISim User Guide UG660 v14 3 October 16 2012 This document applies to the following software versions ISE Design Suite 14 3 through 14 7 XILINX XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL
76. Mapping File xilinxisim ini to point to your logical or physical libraries e When launching ISim from the PlanAhead tool define the user libraries in that tool See the PlanAhead User Guide UG632 for more information Appendix D Additional Resources contains a link to the document Step 2 Parsing and Elaborating the Design Before running a simulation ISim must parse the code into one or more libraries and then elaborate the design components upon which the design depends The simulation executable is generated during this step GUI Mode When you invoke ISim from either the ISE or the PlanAhead tool the ISim GUI is launched the design is parsed and design components are elaborated For details see Simulation from ISE in Step 3 Simulating the Design or the PlanAhead User Guide UG632 The design is parsed and elaborated manually at the command line as described in the next section Then you can invoke the generated simulation executable with the gui mode to launch the GUI Interactive Command Line Mode The steps in the interactive command line mode 1 Creating a project file See Project File Syntax page 43 2 Using the fuse command See Running fuse page 38 ISim User Guide www xilinx com 5 UG660 v14 3 October 16 2012 Send Feedback Chapter 1 Introduction to ISim XILINX Step 3 Simulating the Design After design compilation and elaboration the next step is to run the simulation executable an
77. Sim Executable Command ii cue en pr een e Gen Gen RC pee e Ri Red 49 Pausing a Simulation susessessssssss eee 56 Saving Simulation Results 122 Ea Le ERE RA TRIER RERXUEE RR KE RE E Ke EA IE 56 Closing Simulation 5 14 i 4 12559 Er rep pet CE HC HR EHCESCR SACER E CIE A Ced ud 57 Chapter 4 Waveform Analysis Working with the Wave Configuration susssesssseeseeeeeeen 59 Customizing the Wave Configuration 0 0 0 cece eee eee eee 61 Navigating the Wave Configuration 00 0 c cece eee eee 67 Printing Wave Configurations 000 0 cece eee 71 Using Custom Colts ereen reb Rada kd ee Rr er bp dtd e dde ded 72 Chapter 5 Viewing Simulation Results Waveform Databases and Configuration Files 0005 73 Opening a Static Simulation 0 ccc cece eee eee een ees 74 UG660 v14 3 October 16 2012 www xilinx com ISim User Guide Chapter 6 Debugging at the Source Level Stepping Through a Simulation esee a e e 77 Using Breakp ints r i coca uo oaths CE Pe HEC C EERE Con AERA EEE eines 78 Chapter 7 Writing Activity Data for Power Consumption Chapter 8 Using Hardware Co Simulation PE requisile eis Lec gd dpa oe pL QUE R dct oe dura Foul Rdbtedorpal ee Gali Mast keen 83 Use Models oneri El ded ertUpen beste a Rd ede deen aaed 83 Limitations ose er exero e EET PDC d whee xe 84 Usage or Compilation sooo added e
78. Text Editor controls the behavior of Hardware Description Language HDL files open in ISim only For more information about the preference settings see the ISE Text Editor Help www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Setting ISim Preferences ISim Simulator Preferences ISim User Guide Use the ISim Simulator page in the Preferences dialog box Select Edit gt Preferences gt ISim Simulator in the left pane Draw Waveform Shadow Shows or hides the shadow background for signals in the Wave window Limit the maximum number of elements display to Sets limit for number of children elements to display for objects in the Object window See Showing Display Elements Default Radix Sets the default radix value displayed in the wave configuration the Objects panel and the Console panel See Changing the Default Radix Console text font The window to the right of the field shows example text for the specified font Click the Change button to open a dialog box in which you can specify the font used in the Console ISim Color Preferences Use the Colors page to set your color preferences for displaying the waveform Click Apply to apply changes The color preference options are e Current Color Scheme Displays the default color scheme and any custom schemes you have created e New Creates a new scheme Enter the new name in the Current Color Scheme field and edit the colors in the sc
79. ad_UserGuide pdf Command Line Tools User Guide UG628 http www xilinx com support documentation sw_manuals xilinx14_3 devref pdf ChipScope Pro Software and Cores User Guide UG029 http www xilinx com support documentation sw manuals xilinx14 3 chipscope pro sw cores ug029 pdf ISE Help http www xilinx com support documentation sw manuals xilinx14 3 isehelp start htm XPower Help http www xilinx com support documentation sw manuals xilinx14 3 isehelp start htmfxpa c overview htm ISim In Depth Tutorial UG682 http www xilinx com support documentation sw manuals xilinx14 3 ug682 pdf ISE Hardware Co Simulation Tutorial Accelerating Floating Point FFT Simulation UG817 http www xilinx com support documentation sw manuals xilinx14 1 ug817 fft sim tutorial pdf www xilinx com 157 UG660 v14 3 October 16 2012 Send Feedback Appendix D Additional Resources XILINX 158 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012
80. akpoints that are set in the design See Using Breakpoints in Chapter 6 For each breakpoint set in your source files the list in the Breakpoints panel identifies the file location filename and line number You can delete a selection delete all breakpoints and go to the source code from either the Breakpoint panel toolbar buttons or the context menu To set a breakpoint use one of the following options e Select View gt Breakpoint gt Toggle Breakpoint e Click the Toggle Breakpoint button 4m e Inthe HDL file click a line of code just to the right of the line number e Type bp option in the Tcl console Alternatively you can right click a line of code and select Toggle Breakpoint After the procedure completes a simulation breakpoint icon appears next to the line of code A list of breakpoints is available in the Breakpoints panel If you place a breakpoint on a line of code that is not executable the breakpoint is not added To remove the breakpoint click the breakpoint www xilinx com 27 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX Breakpoint Toolbar Buttons Table 2 10 describes the Breakpoint buttons Table 2 10 Breakpoint Buttons Button Description Deletes the selected line from the Breakpoint panel and deletes the x breakpoint from the HDL source file x Deletes all breakpoints from the HDL source files Opens the HDL source file in the text editor wit
81. als on and off E E E g Toggles the constants parameters and generics on and off www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide ISim GUI Overview Table 2 9 Object Panel Toolbar Buttons Cont d Button Description 1 Toggles the variables on and off Toggles the Sync Time feature on and off Ee 793 e When on Objects panel values are based on the main cursor in the Wave window e When off values are the values at the Sim Time in the Status Bar at simulation end time Using Show Drivers You can use the Show Driver command to display the driver for a change in signal or object value This command is used to determine the cause of a value change which helps determine if circuit connections are correct ISim displays the signal or object and its one or more drivers in the Console panel The Show Driver command is available for probing objects in the following areas e Objects panel e Wave window e Console panel using the show driver command To show drivers 1 Select an object or signal 2 Select Edit Wave Objects Show Drivers The Console panel lists the drivers for the object or signal When there is no driver a message indicates that there is no driver Note Running this command is the same as running show driver at the Console panel prompt Showing Display Elements In the Objects panel y
82. alternative to using menu commands Console commands do not display the dialog boxes that menu commands invoke Table 9 2 provides a summary of the syntax used for the simulation commands Table 9 2 Simulation Command Syntax Syntax Description Indicates an optional command option Note The can be used in Tcl for nesting commands A command put inside is executed and result of that is returned as a value to be used in another Tcl command For example set var show time sets var to the current time Indicates a choice of possible parameters If one term is divided into a subset of parameters that can be entered separately or together each sub parameter occurs between square brackets Indicates that one or more occurrences of the option separated by space is accepted Encloses variables for which you must supply values ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback 1 Chapter 9 ISim Tcl Commands XILINX Tcl Commands Engine Commands bp The bp command controls the setting and removal of breakpoints in the HDL source code that you are simulating A breakpoint is used to interrupt the simulation during debugging bp Command Syntax bp add file name line number clear del index lt index gt list remove file name line number bp Command Options Table 9 3 bp Command Options Option Description add file name A
83. as isim wdb by default and can be changed using the wdb switch with the simulation executable The wave configuration displays in the Wave window The equivalent GUI command is to right click in the wave window for the context menu and select the Add to Wave Window option wave add Command Syntax wave add into lt ID gt reverse radix radix color color name lt custom_name gt r lt object_name gt wave add Command Options Table 9 14 Wave add Command Options Option Description into lt ID gt Specifies object ID of the group or virtual bus into which the object should be added reverse Reverses the bus order MSB to LSB or vice versa radix radix Uses the specified radix when displaying signal values The value of radix isoneofdefault bin oct hex dec unsigned or ascii www xilinx com 133 UG660 v14 3 October 16 2012 us Chapter 9 ISim Tcl Commands XILINX Table 9 14 Wave add Command Options Cont d Option color color Description Sets the simulation object s to the specified color The value of is defined in RGB format For example 0000FF is blue FF0000 is red and 00FF00 is green You can also specify the textual name of color can for some of the popular colors The following color names are accepted black red darkred green darkgreen blue darkblue cyan darkcyan magenta darkmagenta darkyellow gray darkgra
84. ble during the simulation step This file does not disclose any design data and is safe to share with Xilinx Technical Support if you report a problem isimcrash log Log file generated when the tool encounters an unexpected error or condition This is generated inside the isim simulation executable sim directory www xilinx com Send Feedback Chapter 1 Introduction to ISim XILINX Provide this file to Xilinx Technical Support for further assistance This file also does not disclose any design data and is safe to share with Xilinx Technical Support if you report a problem Using Tcl Simulation Commands Several simulation commands are available to assist you with debugging The following commands are linked to the full command description and can be run at the command line Tcl prompt or in the Console panel e isim ptraceon isim ltraceon e dump e show afin force bp bd ODnerror For debug strategies see Chapter 6 Debugging at the Source Level For more commands see Chapter 9 ISim Tcl Commands ISim Tutorials See the following tutorials for more information e ISE Simulator ISim In Depth Tutorial UG682 Demonstrates how to use ISim for design simulation and debugging e ISE Hardware Co Simulation Tutorial Accelerating Floating Point FFT Simulation UG817 Shows how to use the ISim Hardware Co Simulation HW CoSim feature to accelerate Floating Point FFT simulation Appendix D
85. change the selected design unit s Hardware Co Simulation properties Target Board for Hardware Co Simulatic Re Use Last Bitstream File Figure 8 2 Steps 4 and 5 www xilinx com Send Feedback i Chapter 8 Using Hardware Co Simulation IM DUT eroe eee peer structura 2 parsistantdff J inst xipersistenit E w wimax duc cfr v5 v1 x0 wimax duc cfr E x wimax_duc_cfr_692a51409f wimax d bwsel driver xitbsource behavior bwselen driver xitbsource behavior ck driver xick behavior off gt Simulate Behavioral Model xt Stop n With Current Data Figure 8 3 Steps 6 7 and 8 Hybrid Co Simulation Flow To use external pins and free running clocks you need to provide a custom constraints file in UCF format The flow currently reads in a constraints file specified through the hwcosim constraints option to determine which pins are mapped to FPGA IOBs 88 XILINX 1 Decide which portion of your design to run in lockstep with ISim simulation and which to be free running Figure 8 4 page 89 outlines the concept Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX Hybrid Co Simulation Flow External Parts routed to external OBs Peripherls Free running External Clock Dual port BlackRAM or asynchronous FIF O for cross clock domain Asynchronous communication poate lene ose Buffers
86. cludes a text string and or an object type filter To search for objects do the following 1 Place the cursor in the Objects panel or the Instances and Processes panel 2 Right click and select Search from the context menu 3 In the Search dialog box enter a text string You can use an asterisk as a wildcard symbol 4 Select the object type for which you are searching Click Match case if applicable 5 Click OK Objects that match the search criteria display in the Search Results Panel Opening HDL Source Files You can open Hardware Description Language HDL source file in the ISim Text Editor To view an HDL source file do the following 1 Inthe Instances and Processes panel the Objects panel or the Source Files panel select a file 2 Double click the file or right click and select Go To Source from the context menu The HDL source file associated with that object opens in the Text Editor When you open a file using the File Open menu command the file is in write mode In the Open dialog box change Files of type file to Verilog or VHDL select the file and click Open See Modifying Source Files page 26 ISim User Guide www xilinx com 23 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX 24 Source Files Panel The Source Files panel displays as a tab in the Instances and Processes panel When you select the tab it displays list of files associated with the d
87. com 35 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX Parsing Design Files The vhpcomp and vlogcomp commands parse VHDL and Verilog files respectively vlogcomp Command The vlogcomp command parses Verilog source files and generates a binary representation of the Verilog files The binary representation generated by vlogcomp is used by the fuse command to create a simulation executable You must specify either a project file or one or more Verilog source files to compile If neither the project file nor the Verilog file is specified vlogcomp issues an error See Project File Syntax page 43 for information about the project file vlogcomp Command Syntax To go to the command description click the option link Note n your PDF reader turn on Previous View and Next View buttons to navigate back and forth vlogcomp d macro definition value value f cmd file h i include path intstyle ise xflow silent default initfile sim init file gt L lib search lib lib path prj prj files prj sourcelibdir directory name sourcelibext file extension sourcelibfile file name v verbose lt value gt version verilog files work work library library path lt filenames gt The option descriptions are in the fuse vhpcomp and vlogcomp Command Options section vlogcomp Command Examples Use
88. cope debugging analyzer Refer to the iMPACT help and the ChipScope Pro Software and Cores User Guide LIG029 for details on specifying cable plug in parameters Appendix D Additional Resources has a link to this document shareCable Default is 0 This property is only available for JTAG based co simulation interfaces Set to 1 if the JTAG cable is to be shared with the Xilinx Microprocessor Debugger XMD or the ChipScope debugging analyzer for concurrent access Share the JTAG cable only when necessary as this could decrease the hardware co simulation performance substantially www xilinx com 91 UG660 v14 3 October 16 2012 Send Feedback Chapter 8 Using Hardware Co Simulation XILINX e ethernetInterfaceID Default is an empty string This property is only available for Ethernet based co simulation interfaces If you have multiple Ethernet cards available on your host machine you need to select the Ethernet card that is connected to your FPGA board You can select an Ethernet card by setting the value of this property to the MAC address in the format of XX XX XX XX XX XX of the Ethernet card For more information see Determining the Ethernet page 94 Board Support To support a new FPGA board for hardware co simulation in ISim the board must have a JTAG header Provide a board support file that records the following information of the board e FPGA part information e Period and pin location of the system clock e
89. cted in the Instances and Processes panel 10 Wave Window Displays the wave configuration which consists of a list of signals and buses their waveforms and any wave objects such as dividers cursor or markers The Wave window can display more than one wave configuration 11 Text Editor Window Displays read only Hardware Description Language HDL files 12 Status Bar Displays a brief description for a menu command or toolbar button that your cursor is placed over and the simulation time The following subsections describe each ISim GUI component Menus and Toolbar Commands and Shortcuts The ISim main window consists of functionally different toolbars that reflect the most commonly used Main menu options The Main menu provides extended options within the option categories The main window toolbar buttons are below the Main menu at the top of the user interface To show or hide toolbars select View Toolbars toolbar name 10 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview File Menu and Standard Toolbar The Standard toolbar provides access to frequently used File menu commands 8 Hi The File menu and the Standard toolbar provide access to the following options New Use the New dialog box and to select the type of file you want to create You can open a new text file schematic or symbol Open Use this option to brows
90. d Button Description 9o Go To Latest Time moves the cursor and focus to the end of simulation gt r Go To Next Transition moves the main cursor to next transition 16 Go To Previous Transition moves the main cursor to the previous transition H Adds a marker at the position of the main cursor to the Waveform area Moves the main cursor to the nearest marker to the left of the current position Ud Moves the main cursor to the nearest marker to the right of the current position Uni Swaps the main and secondary cursors if both are set yl Snap to Transition Mode moves the cursor to a transition when you place the cursor close to the transition This mode can be switched on or off Displays and hides the floating ruler that can be moved to the desired location Ej in the Wave window Working With Wave Configurations You can create any number of Wave Configurations in the current session The Wave Configuration stores the list of signals their properties and any wave objects that were added To create a wave configuration 1 Select File gt New The New dialog box opens Select Wave Configuration from the list Click OK A new untitled wave configuration opens The new wave configuration is empty until you add signals see Adding Signals to the Wave Configuration If more than one wave configuration is open either e Use the wave configuration tab to locate a particular wave configuration
91. d be interpreted as part of the value Double quote any path that contains white spaces ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback Chapter 3 Compilation and Simulation XILINX Pausing a Simulation While running a simulation for any length of time you can pause a simulation using the Break command which leaves the simulation session open To pause a running simulation do one of the following Select Simulation Break e Click the Break button e Type Ctrl C at the command line only The simulator stops at the next executable HDL line The line at which the simulation stopped is displayed in the text editor Note This behavior applies to designs that are not compiled with the nodebug switch The simulation can be resumed at any time by using the Run AIL Run or Step commands See Stepping Through a Simulation page 77 Saving Simulation Results ISim saves the simulation results of the objects VHDL signals or Verilog reg or wire being traced to the Waveform Database WDB file lt filename gt wdb in the working directory If you add objects to the Wave window and run the simulation the design hierarchy for the complete design and the transitions for the added objects are automatically saved to the WDB file The wave configuration settings which include the signal order name style radix and color among others are saved to the wave configuration WCFG file upo
92. d is connected a On your system command prompt open a command terminal window cmd b Inthe command window type ipconfig a11 to list all Ethernet ports and connections Figure 8 5 shows the command in the cmd window M ILLUS IU 3 7 cond exe Figure 8 5 ipconfig all in cmd exe c Locate the physical address of the Ethernet port connected to the co simulation board d Convert the physical address delimiter from a dash to a colon For example 00 19 B9 75 E5 95 2 Set and verify the correct Ethernet port as follows a Open the GUI b Select the Design under Test DUT Go to the Tcl Console panel aop In the Tcl Console panel type the following commands i Setthe Ethernet address hwcosim set ethernetInterfaceID lt LH LH gt physical address gt ii Verify the Ethernet address hwcosim get ethernetInterfaceID iii Verify that the simulation runs run 10us 94 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 g XILINX Frequently Asked Questions Figure 8 6 outlines the process within the GUI IntarcesandPr 8 X Odets nsex als g Fiatin Objects for dut aJ Iv Instance and Process Name Mi Ga S 2 w O fost Object Name Value Data Ho reverse vector d o Loge Gow f o5 du ap fft_start i Log Ax load fft n dat BG ffton r 31 0 0011111010111111 Array n fft n m 31 0 0000000000000000 Array EETXEENNE inm m iex
93. d simulate the design For information about running simulation in read only mode see Opening a Static Simulation in Chapter 5 GUI Mode Simulation at the Command Line After you generate a simulation executable x exe default or a user specified name you can run the simulation executable with the gui switch on the command line for example my sim exe gui This command launches the GUI The simulation executable command does not start the simulation To start the simulation use one of the run simulation commands described in Simulating the Design page 44 You can then add signals to the Wave configuration See Working with the Wave Configuration page 59 for details Optionally you can also invoke the simulation executable launch the GUI and run simulation with a Tcl file by leveraging the tclbatch option for example my sim exe gui tclbatch my sim tcl You can use the wave add command to add all signals at top level of your my sim tc1 file to automatically trace the signals and display the signals in the GUI upon launch Simulation from ISE Parsing elaboration and running the simulation executable command is run in the background when you run one of the following processes in the ISE or the PlanAhead tool e Simulate Behavioral Model e Simulate Post Place amp Route Model These processes launch the GUI with the top level signals being traced by default Optionally you can specify custom Tcl files to control the
94. dds a breakpoint at the given line in the HDL file line number The ile name is the name of the HDL source file that you are simulating where you want to put a breakpoint line number is the number of the line of HDL code where you want the simulation to stop clear Deletes all breakpoints for all loaded HDL files If you have breakpoints in multiple files all breakpoints are deleted del index Deletes individual breakpoints from your HDL code Before lt index gt using this command run the bp 1ist command to obtain the index numbers for your breakpoints See the 1ist option for details index is the index number assigned to the breakpoint you want to delete Each breakpoint in your design is assigned a unique index number Note This index is notthe line number of the breakpoint in the source file 104 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Table 9 3 bp Command Options Cont d Option Description list Lists all of the breakpoints in your design and shows their index number to be used with the bp del command If you have set breakpoints in multiple files all breakpoints are listed bp 1ist returns the following index directory path file name line number Where e index is the index number to use with the bp del command e directory path is the fully qualified path to your so
95. e Simulation Command Entry Methods Simulation commands can be entered as follows e ISim GUI Type simulation commands in the ISim Console panel e Command Line Type simulation commands at the command line Tcl prompt e Telbatch Type simulation commands in a Tcl file and reference the Tcl file with the tclbatch option of the simulation executable You can enter individual commands or create simulation scripts For examples of simulation Tcl scripts see the Simulation Constructs folder available in the Language Templates To access these examples 1 Click Edit gt Language Templates 2 Inthe Language Templates expand the Tcl gt Tools gt ISim folder You can set a variable to represent a simulation command to quickly run frequently used simulation commands For more information see Aliasing Simulation Commands page 102 Note For information on using Tcl see documentation at http www tcl tk ISim User Guide www xilinx com 99 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX Simulation Command Summary Table 9 1 lists the available simulation Tcl commands with a brief description and links to a more complete description of the command syntax options and examples In your PDF reader turn on Previous View and Next View buttons to navigate back and forth Table 9 1 Simulation Command Summary Command Description bp Sets and deletes breakpoints in your
96. e The radix type option sets the global radix for the current simulation The simulator uses radix type for other commands show value put test dump isim force and isim condition The supported radix types are default dec bin oct hex unsigned and ascii isim set radix Examples Set a radix of hex and see a count value isim set radix hex show value count Returns a Set a radix of dec and see a count value isim set radix dec show value count count is defined as reg 3 0 count Returns 4 Set a radix of unsigned and see a count value isim set radix unsigned show value count Returns 10 isim set userunit Ihe isim set userunit command let you set the default unit of measurement for all time values where unit is unspecified The default time unit is the same as the time unit of the engine as setin the fuse command timescaleor override timeunit options In the absence of these use options the timescale is determined by e The default time unit which is 1ps e As defined by the timescale simulator directive in Verilog ISim User Guide www xilinx com 113 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX isim set userunit Command Syntax isim set userunit lt 1 10 100 gt lt fs ps ns us ms s gt Example Set the simulator timescale to 1 ps isim set userunit 1 ps onerror put The onerror command lets you control the behavior immediat
97. e change is visual and nothing is added to the HDL code You can move other signals or buses to the group by dragging and dropping the signal or bus name The new group and its nested signals or buses is saved when you save the wave configuration file Changing Groups You can change groups as follows e You can rename Groups See Renaming Objects page 65 e You can move Groups to another location in the Name column by dragging and dropping the group name Removing a Group To remove a group highlight it and select Edit Wave Objects Ungroup or right click and select Ungroup from the context menu Signals or buses formerly in the group are placed at the top level hierarchy in the wave configuration Caution Pressing the Delete key removes the group and its nested signals and buses from the wave configuration 64 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Customizing the Wave Configuration Virtual Buses You can add a virtual bus to your wave configuration which is a grouping to which you can add logic scalars and arrays The virtual bus displays a bus waveform which shows the signal waveforms in the vertical order that they appear under the virtual bus flattened to a one dimensional array Adding Virtual Buses To add a virtual bus 1 Inawave configuration select one or more signals or buses you to add to a virtual bus 2 Select Edit New Virtual Bus or r
98. e changes EE Setting Breakpoints You can set breakpoints in executable lines in your HDL file so you can run your code continuously until the source code line with the breakpoint is reached as described in Using Breakpoints in Chapter 6 Note You can set breakpoints on lines with executable code only Using the Memory Editor The Memory Editor lets you find and change contents of two dimensional memory arrays ina design during simulation without recompiling or re elaborating the design There are three places that show memory objects the Memory tab the Object panel and the Search Result tab To open the Memory Editor follow one of these methods e On the Memory tab which contains all the two dimensional arrays of logic types in a design double click a displayed memory object e Inthe Objects panel right click a two dimensional array of logic type and select Memory Editor from the context menu e Inthe Instance and Processes panel run a search on a memory name When the searched memory displays in the Search Results panel you can right click the memory and select Memory Editor from the context menu Note For objects that are not two dimensional array of a logic type the Memory Editor choice in the Context Menu is grayed out The Memory Editor displays the following fields e Address Go to a particular location in the displayed memory e Columns Controls the display of the number of elements per row The auto column d
99. e configuration open 1 Select the Go To Time 0 button to move the cursor to time 0 in the wave configuration 2 Select the Go To Latest Time button to move the cursor to the latest time in the wave configuration o Using Show Drivers You can use the Show Driver command to display the driver for a change in signal or object value This command is used to determine the cause of a value change which helps determine if circuit connections are correct ISim displays the signal or object and its one or more drivers in the Console panel The Show Driver command is available for probing objects in the following areas e Objects panel e Wave window e Console panel To show drivers 1 Select an object or signal 2 Select Edit gt Wave Objects gt Show Drivers or select Show Drivers from the right click menu The Console panel lists the drivers for the object or signal When there is no driver a Console message indicates that there is no driver Note Running this command is the same as running show driver at the Console prompt Printing Wave Configurations You can print one wave configuration at a time using the setting specified during print setup The wave configuration always prints with a white background Printing Preview Select File gt Print Preview In the Print Preview dialog box make sure the wave configuration looks as expected Select Print or Setup to further customize the print options and layout and
100. e drivers when prompted For more information about Ethernet see Determining the Ethernet page 94 Hardware Co Simulation Unlike the executable for tool simulation the executable for HWCoSim communicates with a hardware board and offloads the simulation of the selected portion of a design into the hardware It is invoked in the same way as in the tool simulation flow e Invoking the executable launches a Tcl shell interface for controlling the simulation e Invoking the executable with the gui option launches the GUI front end with waveform display Before the simulation starts and each time the simulation is restarted the executable configures the FPGA with the hardware co simulation bitstream The configuration process can take a few seconds or longer depending on the speed of the JTAG cable ISim prints a message to the Console panel when the configuration is complete 90 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim Hardware Co Simulation Tcl Commands ISim Hardware Co Simulation Tcl Commands ISim provides the following Tool Command Language Tcl commands to access a given property of an instance in the design hierarchy under hardware co simulation These commands are scope sensitive you must first use the scope command to select an instance that is marked enabled ISim User Guide hwcosim get property Get a property of the hardware co simulation instance in the curre
101. e through your directories and select a file to open The file displays in the appropriate application or editor Save Use this option to save the active file to disk and overwrites the previously saved version If a file is not saved previously the Save As dialog box opens and lets you save the active file to disk e Save All Use this option to save all files that require saving e Print Use the Print dialog box to print an active file Edit Menu and Toolbar The Edit toolbar provides access to frequently used Edit menu commands 05xX o o Ob em e Cut Copy Paste Delete are available as well as Undo Redo Find and Find in File View Menu and Toolbar The View toolbar provides access to frequently used View menu commands 2 P BPB View toolbar options are as follows e Zoom In and Zoom Out Set View for all content to be visible and Zoom to Cursors The Refresh button cleans up the display of the file in focus In the View menu additional options are e Panel Opens a dialog box with the following check box options Search Results Find in Files Results Breakpoints Compilation Log Source Files Memory Objects Instances and Processes Console e Toolbars Turn the toolbars on and off e A check box controls the use of the Status Bar ISim User Guide www xilinx com 11 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX ISim Menu and Toolbar The ISim toolbar provide
102. e verbosity level 1 Dumps the library mapping as seen by the compiler after reading all available library mapping files xilinxsim ini Gets verbose messages from design elaborator Gets the dumps of current values of environment variables that affect the behavior of the compiler Gets the list of loaded shared objects by the compiler Dumps operating system information including version number and processor Dumps path to the GCC compiler being used to compile the generated code verilog files Specifies the Verilog file to be compiled vhdl files Specifies one or more VHDL source files to be compiled version Prints the compiler version wdb waveform file wbd Saves simulation data to the specified WBD file For example x exe wdb my wdb saves the simulation data to my wdb instead of the default isimgui wdb work work library lt library_path gt lt filenames gt Specifies the work library and optionally the physical path for the work library The physical path overrides the mappings provided by the xilinxsim ini file The default work library is the logical library work The lt work_library gt is the logical name of the specified work library optionally followed by lt library_path gt the path to the physical library For example mywork C home worklib Note Ensure that there is no space between the and the value the space woul
103. ed as part of the value Double quote any path that contains white spaces 52 Send Feedback ISim User Guide UG660 v14 3 October 16 2012 www xilinx com XILINX ISim Executable Command Table 3 7 fuse vhpcomp and vlogcomp Command Options Cont d Option log file name Description Generates a log file with the specified ile name maxdeltaid number Specifies the maximum delta number in an integer maxdelay Verilog only option Specifies that if fuse calls vlogcomp it should use worst case delays maxdesigndepth depth Overrides maximum design depth allowed by the fuse elaborator If a design exceeds the depth use errors out This option lets you increase the depth in case fuse has inaccurately determined that a design has infinite recursive instantiation mindelay Verilog only option Specifies that if fuse calls vlogcomp it should use fastest possible delays mt value Specifies the number of sub compilation jobs which can be run in parallel Values are on off or an integer greater than 1 Default is on where the compiler automatically chooses a number based upon the number of cores in the system nodebug Generates output that has no information for debugging your HDL code during simulation Output with no debug information results in a faster simulation runtime The default is to generate HDL debug units nolog Blocks l
104. ely following a failed Tcl simulation command See examples for various applications such as printing the error and resuming the next command This command can be used to debug simulation command errors and is particularly useful when running a Tcl script in which an error is encountered Note This command is not intended for users who type one Tcl command at a time at the Tcl prompt onerror Command Syntax onerror list of Tcl commands lt source Tcl script Where e list of Tcl commands Isa list of simulation Tcl commands to control behavior upon encountering a simulation command error e lt source Tcl script Is the sourced Tel script file that contains listed Tcl commands onerror Command Examples Print the that an error occurred and all values in the current scope then exit onerror showtime dump quit f Continue reading the next command in the Tcl script after showing the time the error occurred and all values in the current scope onerror show time dump resume Read the sourced Tcl file and executes its command upon encountering an error onerror source myerror tcl The put command lets you modify values of signals or buses during simulation The put command can be used to assign e Aspecified signal or bus e An array of signals or buses e A record or array of records containing signals or buses Avalue with the specified radix is put to an object To use the put command the signal or bus must be
105. ensional array d in the record recsig represented by the coordinates 2 2 in the two dimensional array recarrsig show value recarrsig 2 2 d 2 3 1 step After you run an initial simulation you can step through your HDL design one line of source code at a time to verify that the design is working as expected 126 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide Tcl Commands The step command advances to the next line of executable code in the Verilog or VHDL file The equivalent GUI command is Simulation Step step Command Syntax step where no options are available step Command Example Step through one line of HDL source code step The test command compares the actual value of a VHDL signal Verilog wire Verilog reg VHDL generic Verilog parameter or VHDL process variable in the current scope with a supplied value If the two values match nothing is displayed Otherwise the current correct value is displayed and ISim reports an error You can test one bit a slice of a vector element or a whole value test Command Syntax test signal name vhdl process name process variable name element reference value object value radix radix type www xilinx com 127 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX test Command Options Table 9 12 test Command Options Option
106. er 7 Writing Activity Data for Power Consumption ISim writes out files with switching activity data of the design which is useful for two tasks e Estimating the power consumption with a power analysis tool such as XPower Analyzer Implementing the design for optimal power consumption with Map and Place amp Route PAR tools The switching activity data can be written out from the simulation of the design either at the RTL level or after full PAR Map PAR and XPower Analyzer all work with switching activity data generated from both RTL and post PAR simulation For better accuracy in power analysis and power optimized implementation it is recommended to use switching activity data generated from a post PAR simulation The data then matches the design internal nodes that result from the placement and routing It is also possible to use switching activity data generated from a RTL simulation quicker than the post PAR simulation for both power analysis and power driven implementation However only activities for the inputs and outputs of the design are taken into account The tools use their vector less analysis algorithms to estimate activities of the internal nodes of the design For more information about how these tools use the switching activity data see the Command Line Tools User Guide for implementation tools Map and PAR and XPower Analyzer Help for power analysis Appendix D Additional Resources contains links t
107. esign The list of files is provided by the use command during design parsing and elaboration which is run in the background for GUI users To open a source code file do the following 1 Select a file in the list 2 Clickthe Go To Source Code button You can also use the Go To Source Code command from the context menu or double click a file Bm Objects Panel The Objects panel displays all simulation objects ports signals variables constants parameters and generics associated with the selected instances and processes in the Instances and Processes panel The top of the panel displays which instance or process is selected in the Instances and Processes panel those objects and their values are listed in the Objects panel The table columns are defined as follows e Object Name Displays the name of the simulation object accompanied by the symbol which represents the type of object e Value The value of the simulation object at the current simulation time or at the main cursor as determined by the Sync Time button e Data Type Displays the data type of the corresponding simulation object logic or an array Toggle buttons are available in the Objects panel as described in Table 2 9 Table 2 9 Object Panel Toolbar Buttons Button Description IH Toggles the input ports on and off Toggles the output ports on and off Toggles the inout bidirectional ports on and off Toggles the internal sign
108. ewing and debugging memory elements e Single click simulation re compile and re launch e Easy to use one click compilation and simulation e Built in Xilinx simulation libraries ISim User Guide www xilinx com 3 UG660 v14 3 October 16 2012 Send Feedback Chapter 1 Introduction to ISim XILINX Operating System Support See the Xilinx Design Tools Installation and Licensing Guide UG798 for operating systems support The Xilinx Design Tools Release Notes Guide UG631 provides information about the most recent release changes Links to these document are also available in Appendix D Additional Resources ISim Modes of Operation ISim has two modes of operation Graphical User Interface GUI Provides a graphical view of simulation data Menu commands context commands and toolbar buttons run simulation and examine and debug data For information about working with the GUI see Chapter 2 Using the ISim GUI Command line mode Has no interaction with the GUI and you run commands at the command prompt After the simulation executable runs a Tool Command Language Icl prompt opens in which you can enter simulation Tcl commands to examine and debug data You can specify tclbatch file name option to the simulation executable to run a set of Tcl commands after simulation has been loaded You must have quit as the last Tcl command if you want the simulation to quit upon completion For more information see Chapter 3
109. groups markers and cursors You can completely customize a wave configuration you can add or remove signals and other wave objects at any time when the simulation is not actively running The initial file Default wcfg is not saved until you save the file The wave configuration file stores the list of signals their properties and wave objects You can create and simulate multiple wave configurations and the wave configurations can be saved separately For information about saving the Wave Configuration see Saving Wave Configurations page 23 When you invoke the simulator from any mode it creates the De ault wcfg file You must supply a filename to save a wave configuration file to the disk as a wcfg file e In GUI mode when ISim exits it prompts you to type a filename in the Save As dialog box e In batch mode type wcfg save to save the contents of the Default wcfg before exiting the ISim tool www xilinx com 17 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX 18 Active Window When you invoke the simulator the first active window is Default wcfg You can change the active window by clicking the window tab or using the wave add command e Inthe GUI select File gt New or File gt Open to change the active window to the newly created waveform configuration window e InTc the wcfg newand wcfg open commands change the active window to the newly created window just like
110. h array element of sigarray to 1 test sigarray 0 1 2 3 1 For an array of records that contains an array of standard logic vectors and is declared as follows type ram 3d vector is array 0 to 10 7 downto 0 0 to 2 of std logic vector 1 to 4 type rectype is record a integer b string 1 to 7 c std logic vector 0 to 3 d ram 3d vector end record type recarray is array 0 to 3 4 downto 1 of rectype Signal recarrsig recarray signal recsig rectype Compare the second element b of the record recsig to the string abc test recsig b 2 4 abc ISim User Guide www xilinx com 129 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX vcd Compare the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig to 0110 test recsig d 2 3 1 0110 Compare the first two bits of the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig to 01 test recsig d 2 3 1 1 2 01 Compare the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig represented by the coordinates 2 2 in the two dimensional array recarrsig to 0011 test recarrsig 2 2 d 2 3 1 0011 The vcd command generates simulation results in Value Change Dump VCD format This command lets you e Dump specified instances to a VCD file e Na
111. h the breakpoint in focus Search Results Panel The Search Results panel displays the results that match the search criteria from the Search command The results display the icon for the object type being displayed and the location of the object in the design Search Results Toolbar Command Buttons Table 2 11 shows and describes the buttons available in the Search Results panel Table 2 11 Search Results Toolbar Buttons Button Description Clears the contents of the Search Results panel Adds the signal associated with the selected search result to the wave lp configuration in the Wave window Opens the HDL source file in the text editor at the line where the design unit Bm is defined Opens the HDL source file in the text editor at the line where the design unit EH is instantiated o Stops the search 28 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Find in Files Results Panel You can find a text string in a set of files as follows To use the Find in Files options Table 2 12 Find in File Buttons and Actions Button Action Select Edit Find in Files or click the Find Text in Files button D In the Find in Files dialog box specify the text to find set the parameters for your search and click Find In the Find in Files Results panel do any of the following N To clear all results from
112. he Wave Configuration Moving a Marker After you add a marker you can move the marker to another location in the waveform using the drag and drop method 1 Click the marker label at the top of the marker and drag it to the location e The drag symbol indicates that the marker can be moved As you drag the marker in the Wave window you see a hollow or filled in circle ifthe Snap to Transition button is selected which is the default behavior e A filled in circle indicates that you are hovering over a transition of the E waveform for the selected signal or over another marker e For markers the filled in circle is white e A hollow circle indicates that you between transitions in the waveform of O the selected signal 2 Release the mouse key to drop the marker to the new location Deleting a Marker Dividers You can delete one or all markers with one command 1 Right click over a marker 2 Perform one of the following functions Select Delete Marker from the context menu to delete a single marker e Select Delete All Markers from the context menu to delete all markers Note You can also use the Delete key to delete a selected marker Use Edit Undo to reverse a marker deletion Dividers create a visual separator between signals Adding Dividers You can add a divider to your wave configuration to create a visual separator of signals 1 Ina Name column of the Wave window click a signal to add a divider
113. heme table e Delete Deletes the custom scheme that you have selected You can edit the color of this scheme See Setting ISim Preferences page 32 Time Format Preferences You can customize the appearance of displayed time values using the Time Format Preferences Select Edit gt Preferences Time Format in the left pane The following subsections describe the two categories of time formats Waveform Window Time format options apply to the GUI elements inside the waveform viewer window The time format options are e Link All Waveform Time Units To Ruler Is on by default and keeps the Units setting of the Cursors Markers and Measure Bubble categories in sync with changes to the Ruler category e Rulers Applies to the main ruler at the top of the waveform window as well as to the floating ruler e Cursors Markers Applies to the time values displayed for the all cursors and markers e Measure Bubbles Applies to the cursor value bubbles displayed at the bottom of the waveform window www xilinx com 33 UG660 v14 3 October 16 2012 usc Chapter 2 Using the ISim GUI XILINX 34 Other GUI Elements The time format options apply to the GUI elements outside the Waveform window as follows All Time Values Applies to the current simulation time shown at the bottom right of the main window and time values shown in the Objects panel Time formats allow setting of time units and precision of display of values using
114. hy You can expand and collapse a hierarchy in any window or with objects in nested groups using one of the following methods Using the Arrows Click the expand arrow to expand the hierarchy One level can be expanded at a time Click the collapse arrow to collapse the hierarchy Using the Menu 1 2 ISim User Guide Select an object Select Edit gt Wave Objects gt e Expand Expands the hierarchy object that is selected One level can be expanded at a time e Collapse Collapses the hierarchy of the object selected www xilinx com 67 UG660 v14 3 October 16 2012 send Feedback Chapter 4 Waveform Analysis XILINX Using the Context Menu 1 Select an object 2 Right click and select the applicable command from the context menu e Expand Expands the hierarchy object that is selected One level can be expanded at a time e Collapse Collapses the hierarchy of the selected object Zooming In and Out Use the zoom functions to view your wave configuration in the Wave window as needed See the View Menu and Toolbar page 11 Using the Floating Ruler The floating ruler assists with time measurements using a time base other than the absolute simulation time shown on the standard ruler at the top of the Wave window You can display or hide a floating ruler and move it to a location in the Wave window The time base time 0 of the floating ruler is the secondary cursor or if there is no secondary cursor
115. ical name long name the simple signal or bus name short name or a custom name for each signal Radixes The default radix controls the bus radix that displays in the wave configuration Objects panel and the Console panel Bus Bit Order You can change the Bus bit order from Most Significant Bit MSB to Least Significant Bit LSB and vice versa Cursors are used primarily for temporary indicators of time and are expected to be moved frequently as in the case when you are measuring the time between two waveform edges For more permanent indicators used in situations such as establishing a time base for multiple measurements add markers to the Wave window instead See Markers page 62 for more information You can place the main cursor with a single click in the Wave window UG660 v14 3 October 16 2012 www xilinx com Send Feedback 61 Chapter 4 Waveform Analysis XILINX 62 Placing the Secondary Cursor Place the secondary cursor as follows 1 Click and hold the waveform and drag either left or right This sets the secondary cursor with the initial click and the main cursor when you finish dragging 2 Press Shift and click the mouse in the waveform If the secondary cursor is not already on this action sets the secondary cursor to the present location of the main cursor and places the main cursor at the location of the mouse click Note To preserve the location of the secondary cursor while p
116. ich case the command points out the exact process where the simulator is stuck isim ptrace Command Syntax isim ptrace on off isim ptrace Command Options The options are on off The default is off isim ptrace Command Example See which process is currently executing isim ptrace on isim set arraydisplaylength Theisim set arraydisplaylength command sets the limit on the number of elements for an array type HDL object The default is 64 The following are affected by the limit set e The display of values in the GUI Objects e The response to the show value command isim set arraydisplaylength Syntax isim set arraydisplaylength size The available option is size Type a number of elements of an array type HDL object to display Use 0 for unlimited length The default is 64 isim set arraydisplaylength Command Examples Enter isim set arraydisplaylength 2 show value xcountout Returns 00 00 112 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Examine the Value column for arrays in the Objects isim set arraydisplaylength 64 show value xcountout Returns 0001000000 0001000000 isim set radix The isim set radix command enables you to set the global radix for the current simulation This radix type is used for other commands show value put test dump isim force and isim condition isim set radix Syntax isim set radix radix type Wher
117. ied hierarchy into the SAIF file and so forth saif Command Examples The saif command can be used as follows Write all ports of a design starting at the current scope recursively to a file called xpower saif saif open Write the ports and internal nets of a design starting at the current scope recursively to a file called xpower saif saif open allnets Write ports and internal nets of a design starting at the UUT recursively to a file called uut backward saif saif open scope uut file uut backward saif allnets 120 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Scope The scope command lets you navigate the design hierarchy With no options the scope command displays the current module information scope Command Syntax Scope path name Where m Moves the current scope to the hierarchy directly above the current one e path name is the path to the module for which you want to display the module information You can use a relative or an absolute path scope Command Examples The scope command can be used as follows Move up one level in the design hierarchy scope Move to the module UUT that is instantiated in the current module scope UUT Use the scope command on child instances in a post route netlist X_IPAD CLK PAD PAD CLK Where NCLK PAD is an extended identifier scope testbench UUT CLK P
118. if The saif command lets you create a Switching Activity Interchange format SAIF file and record port and signal switching rates See Chapter 7 Writing Activity Data for Power Consumption saif Command Syntax saif open scope path name file file name allnets close level number of levels saif Command Options Table 9 9 saif Command Options Option Description open open creates a file for SAIF power estimation scope path name scope path name creates power estimation data l file efile names starting at specified scope and recursively You can use a relative or an absolute path If no path is specified the allnets current scope is used e file file name creates a new SAIF file The default name of the SAIF file is xpower sai f Only one SAIF file can be opened during one run of simulation allnets includes internal nets and port signals in the power estimation Without this switch only port signal changes are monitored close Stops monitoring and flushes the SAIF file level You can have as many levels as you have in your design lt number_of_levels gt hierarchy as follows level 0 tracks and dumps all levels of signal transitions below the specified hierarchy into the SAIF file level 1 tracks and dumps only the signal transitions in the specified hierarchy into the SAIF file e level 2 tracks and dumps two levels of signal transitions in the specif
119. ight click and select New Virtual Bus from the context menu The virtual bus is represented with the Virtual Bus button The change is visual and nothing is added to the HDL code You can move other signals or buses to the virtual bus by dragging and dropping the signal or bus name The new virtual bus and its nested signals or buses are saved when you save the wave configuration file Changing Virtual Buses The following changes can be made to a virtual bus e You can rename them See Renaming Objects page 65 e You can move it to another location in the waveform by dragging and dropping the virtual bus name Removing Virtual Buses To remove a virtual bus and ungroup its contents highlight the virtual bus and select Edit Wave Objects Ungroup or right click and select Ungroup from the context menu Caution The Delete key removes the virtual bus and its nested signals and buses from the wave configuration Renaming Objects You can rename any object in the Wave window such as signals dividers groups and virtual buses 1 Select the object name in the Name column 2 Right click and select Rename from the context menu 3 Replace the name with a new one 4 Press Enter or click outside the name to make the name change take effect You can also double click the object name and then type a new name The change is effective immediately Object name changes in the wave configuration do not affect those in the
120. ine In a timing simulation of a Verilog design the following rules apply e Compile XILINX verilog src glbl v to the work library e Specify work glblasoneofthe library name top name in the fuse command e Specify L simprims ver in the fuse command ISim Executable Co mmand Note Commands are case sensitive The following subsections provide an overview of the ISim executable compilation and elaboration commands as well as the command syntax and command options The ISim executable file is user defined Running the file at the command line invokes a simulation You can set the executable name using the fuse command o option If not user defined the default executable nameis x exe ISim Executable Syntax The syntax for this command is executable name exe options Where exe opt ISim User Guide UG660 v14 3 October 16 2012 cutable name exe is user defined or by default x exe ions are the options specified in Table 3 6 www xilinx com Send Feedback ii Chapter 3 Compilation and Simulation XILINX ISim Executable Command Options Table 3 6 lists the command options used by ISim executable Table 3 6 ISim Command Options Option f cmd file Description Lets you save command options in a text file for future use This option reads and executes the saved options that are specified in cmd ile gui Launche
121. is For more information see Stepping Through a Simulation e Set breakpoints on the specific lines of HDL code and run the simulation until a breakpoint is reached In larger designs it can be cumbersome to stop after each line of HDL source code is run Breakpoints can be set at any predetermined points in your HDL source code and the simulation is run either from the beginning of the test bench or from where you currently are in the design and stops are made at each breakpoint You can use the Step Run All or Run For command to advance the simulation after a stop For more information see Using Breakpoints page 78 Stepping Through a Simulation ISim User Guide You can use the Step command at any point in the simulation to debug your HDL gt source code The Step command executes your HDL source code one line of source code at a time to verify that the design is working as expected A yellow arrow points to the line of code currently being executed You can also create breakpoints for additional stops while stepping through your simulation For more information on debugging strategies in ISim see Using Breakpoints page 78 1 To step through a simulation e From the current running time do one of the following Select Simulation gt Step Click the Step button Ge Type the step command at the Console prompt The HDL associated with the top design unit opens as a new tab in the Wave window e From the start 0 ns
122. isplays the maximum of 2 to power N of elements 26 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview e Address Radix Controls the radix of the address displayed in the Memory Editor e Value Radix Controls the radix of the display value in the Memory Editor You can float the Memory Editor window and the Memory Editor retains the previous state after the float operation You can navigate inside Memory Editor with the arrow keys the current position of a selected item displays on the status bar based on the current address radix Console Panel The Console panel lets you view a log of commands generated by ISim and enter standard and ISim specific Tcl commands at the command prompt The Console panel shows Messages Generated messages include errors warnings and informational messages The Console panel also echoes simulator commands that were invoked from the graphical controls in the ISim GUI Simulation commands The command prompt lets you enter simulation Tcl commands and to view the command dump or print out in the Console panel See Simulating the Design in Chapter 3 A number of right click menu commands are available to help manage the contents of the Console panel Breakpoints Panel ISim User Guide A breakpoint is a user determined stopping point in the source code used for debugging a design with ISim The Breakpoints panel displays a list of bre
123. ition to measuring time the time range also forms the focal point for zooming to cursors and printing a range A quick time measurement between one transition and another possibly between two different signal waveforms can be done with the following procedure Note The Snap to Transition button is on by default This feature assists with placing the cursor more precisely on a signal transition because the cursor snaps to the transition when in close proximity 1 Place the mouse on the first transition and press and hold the left mouse button 2 Dragthe mouse to the second transition 3 Release the mouse button ISim User Guide These actions place the secondary cursor on the first transition and the main cursor on the second transition www xilinx com 69 UG660 v14 3 October 16 2012 usc Chapter 4 Waveform Analysis XILINX 4 Examine the values at the bottom of the wave configuration e X1 represents the time of the main cursor e X2 represents the time of the secondary cursor e Delta X represents the time range between the cursors If the floating ruler is displayed the time values of the cursors display just above the floating ruler 5 Optional You can switch the cursors using the Swap Cursors button li 6 Thetime range displays until you click in the wave configuration to place a new main cursor If you move the secondary cursor as described in Placing the Secondary Cursor the time range updates automa
124. ix of an individual signal HDL object in the Objects panel as follows 1 Right click a bus in the Objects panel 2 Select Radix and the format you want from the drop down menu e Binary e Hexadecimal e Unsigned Decimal e Signed Decimal e Octal e ASCII Note Changes to the radix of an item in the Objects panel do not apply to values in the Wave window or the Console panel 66 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Navigating the Wave Configuration To change the radix of an individual signal HDL object in the Wave window use the Wave window context menu To change the radix in the Console panel use the Tcl command isim set radix Bus Bit Order You can reverse the bus bit order in the wave configuration in order to switch between MSB first and LSB first signal representation To reverse the bit order 1 2 Select a bus Right click and select Reverse Bit Order The bus bit order is reversed The Reverse Bit Order command is marked to show that this is the current behavior Navigating the Wave Configuration You can navigate the wave configuration using a variety of options which include Expanding and Collapsing a Hierarchy Zooming In and Out Using the Floating Ruler Displaying Waveform Values With Markers Displaying Waveform Values at Signal Transitions Measuring Time with Cursors Using Go To Time Using Show Drivers Expanding and Collapsing a Hierarc
125. kers are measured Figure C 3 shows how to measure between the edges of interest in ISim Note You cannot rename markers in ISim Analog Waveforms Contact Xilinx Technical Support for more information on availability Single Click Compile and Reload ModelSim XE has a true text editor built into the standalone GUI which lets you make changes to HDL code recompile and re simulate The ISim GUI has a text viewer only for HDL files When you make edits to the file you cannot recompile and re simulate You must shut down the existing simulation make HDL modifications in the ISE tool or PlanAhead tool text editor then re launch the simulation in ISim 152 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Simulation Process Project Navigator Integration The ISE Project Navigator notifies you when ModelSim XE is not a valid simulator choice and that you should select one of the other integrated simulators The following figure shows the ISim selection in Project Navigator 8 Process Properties ISim Properties Switch Name incremental nodebug prj rangecheck Property Name Use Custom Simulation Command File g Custom Simulation Command File Incremental Compilation Compile For HDL Debugging Use Custom Project File Custom Project Filename Run for Specified Time v Simulation Run Time Use Custom Waveform Configuration File Custom Waveform Configuration
126. l based command prompt You can then use the variable to execute the command many times without having to type it in each time Setting a variable to represent one or more commands is called aliasing Setting a Variable at the Simulation Console Panel In the Console panel GUI mode or Tcl prompt command line mode type in a variable as follows set svc show value count Where e set indicates that you are creating a variable e svc is the variable name e show value count is the simulation command represented by the variable name The Tcl variable svc is set to show value count To then run the variable and thereby execute the simulation command type eval svc www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim Wave Viewer Tcl Commands Overview ISim Wave Viewer Tcl Commands Overview The ISim Wave Viewer Tcl commands operate on the active window When ISim starts the first active window is Default wcfg You can change the active window by e Clicking the window tab or using the wcfg select command e Inthe GUI select File gt New and File gt Open to change the active window to the newly created waveform configuration window e InTc you can use the wc g newand wcfg open commands to change the active window to the newly created window Command Line Conventions You can enter console commands at the command line of the ISim Console panel as an
127. l co simulation setup Limitations HWCoSim has the following limitations Only one instance in a design can be selected for hardware co simulation and it cannot be the top level test bench itself e The selected instance for hardware co simulation must be able to be synthesized using XST and must be able to be implemented on the target FPGA device of the selected board The lockstep hardware co simulation has additional restrictions on clocking and I Os e The co simulation instance in hardware is clocked with an emulated clock source that ISim controls and is asynchronous to the simulation Thus the co simulation does not exactly model the design scenario running in hardware or serve as a timing simulation e The instance under co simulation cannot have access to external I Os or Multi Gigabit Transceivers MGTs nor can it instantiate primitives such as DCMs PLLs that require a continuous clock or a clock at a specific frequency e All ports of the instance under co simulation must be routable to a slice register or LUT Certain resources on the FPGA require dedicated routes such as to an IOB or to certain port of a primitive and thus cannot be wired to any port of the instance under co simulation Usage for Compilation As with tool based HDL simulation you first compile a design into a simulation executable before performing HWCoSim Invoke the fuse command for compilation using the command line or through the ISE t
128. l values such as X and Z display in the same color www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Waveform Databases and Configuration Files Chapter 5 Viewing Simulation Results A live simulation consists of the following e A waveform database file WDB which contains all simulation data Awave configuration file WCFG which contains the order and settings associated with objects in the wave configuration Waveform Databases and Configuration Files ISim User Guide A WDB opens automatically when you run a simulation For more information about running a simulation see Running Simulation in Chapter 3 When you run a simulation from the ISE tool or the PlanAhead tool a default wave configuration opens automatically You can open additional wave configurations When running a simulation from the command prompt or using a batch script a wave configuration is not opened by default when the GUI is launched and you must open or create one See the following subsections and Running Simulation in Chapter 3 for more information Open a Wave Configuration in the GUI 1 Select File Open 2 Select wcfg from the file type list 3 Select the file to open and click OK The wave configuration opens in the Wave window Multiple wave configurations can be opened during one simulation session Click the corresponding wave configuration tab to view the wave configuration
129. le select File gt Save and specify a file name for the WCFCG file 56 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Closing Simulation Closing Simulation You can terminate a simulation with one of the following commands e Select File gt Exit Type the quit command in the Console at the prompt Click the X at the top right corner of the main window ISim User Guide www xilinx com 57 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation 58 Send Feedback www xilinx com XILINX ISim User Guide UG660 v14 3 October 16 2012 XILINX Working with the Wave Configuration Chapter 4 Waveform Analysis Before starting the waveform analysis you need to open the ISim GUI using one of the following methods In read only mode to view or analyze the data from a previous simulation see Opening a Static Simulation page 74 From the ISE or the PlanAhead tools a wave configuration with top level signals displays You can then proceed to add additional signals or run the simulation See Running Simulation in Chapter 3 From the command line run the simulation executable with the gui switch and an empty wave configuration displays You must add signals to the wave configuration before you run simulation See Running Simulation in Chapter 3 ISim populates design data in other areas of the GUI such as the Objects
130. loading static wave databases using File Open to open a WDB file The switch has no effect at the command line www xilinx com 117 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX quit Command Examples Exit ISim and leave the Tcl prompt quit Exit ISim and save your waveform quit f Quit the current simulation quit s restart The restart command stops simulation and sets simulation time back to 0 This lets you start simulation over again within the same simulation run without reloading the design The equivalent GUI command is Simulation Restart restart Command Syntax restart onerror scope saif vcd isim force put restart Command Options Table 9 7 restart Command Options Option Description onerror Removes the onerror script scope Resets scope to top saif Closes file ved Closes file isim force Removes force put Returns to initial value restart Command Example To set simulation time back to 0 and start simulation restart resume The resume command is used with the onerror command to continue executing commands after an error is encountered Note This command has no effect when entered alone resume Command Syntax resume There no available options to this command resume Command Example To continue reading the next command in the Tcl script after showing the time the error occurred and all values in the cu
131. log wire and Verilog reg type HDL objects can be logged Logging of VHDL variables is not supported wave log Command Syntax wave log r lt object_name gt Where e r Recursively adds all child modules of the specified block e lt object_name gt HDL object whose simulation output is to be logged to the waveform database The lt object_name gt can also be a hierarchical instance name UG660 v14 3 October 16 2012 ISim User Guide www xilinx com Send Feedback 131 Chapter 9 ISim Tcl Commands XILINX for example tb UUT of a block in which case all HDL objects within the given block are logged Wild characters such as are not supported in the object name To add all HDL objects inside instance of a block the instance name of the block can be used for example wave add UUT is the same as wave add UUT if were supported wave log Command Examples Log the signals associated with the module instances tb UUT and tb child gt to the waveform database wave log tb UUT tb child gt Log all signals in the design wave log r Waveform Window Commands wcfg new The wcfg new command creates a new wave configuration and opens it in a new window wcfg new Command Syntax wcfg new wcfg new Command Example Create a new wave configuration wcfg new wcfg open The wcfg open command opens a wave configuration from a file into a new window wcfg open Command Syntax wcfg open file
132. mand to enter an individual object or a group of objects Wave Configurations and WCFG Files Although both a wave configuration and a WCFG file refer to the customization of lists of waveforms there is a conceptual difference between them e The wave configuration is an object that is loaded into memory with which you can work e You can name a wave configuration or leave it untitled The name appears on the tab of the wave configuration window e When saving a wave configuration to a WCFG file using a GUI Tcl command the WCFG file takes the name supplied as a command argument e When loading a wave configuration from a WCFG file the wave configuration displays the name of the file e The WCFCG file is the saved form of a wave configuration on disk 22 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Saving Wave Configurations You can save the current wave configuration and if you have multiple wave configurations open each can be saved to a unique name for later viewing To save a wave configuration do one of the following e Select File gt Save e Press Crtl S e Click the Save button a Note Use File gt Save As to assign a different name to the wave configuration Searching For Objects You can search for objects in the design using the Search command which is available in the Instances and Processes panel and in the Objects panel Search criteria in
133. me the VCD file e Start and stop the dump process and other functions See Chapter 7 Writing Activity Data for Power Consumption vcd Command Syntax vcd dumpfile file name dumpvars m module name 1 lt level gt dumpoff dumpon dumpall dumplimit file size dumpflush vcd Command Options Table 9 13 vcd Command Options Option Description dumpfile file name Givesaname to VCD file The default file name is dump vcd Invokes the Verilog dumpfile directive dumpvars m Dumps the specified variables and their values to the VCD lt module_name gt file 1 lt levyel gt m module name dumps the module of that name l level 0 1 e Ocauses a dump of all variables in the specified module and in all module instances below the specified module The argument 0 applies only to subsequent arguments which specify module instances and not to individual variables e 1dumps all variable within the module specified by m it does not dump variables in any of the modules instantiated by the module specified by m Invokes the Verilog dumpfile directive dumpoff Temporarily suspends the dumping process and dumps all selected variables as an X value Invokes the Verilog dumpof f directive 130 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands Table 9 13 vcd Command Options Cont d Option Description dum
134. mulate multiple instances in the design in hardware A No Only one instance can be selected for hardware co simulation You can co simulate the parent instance of the multiple instances or group the multiple instances into one instance Q What happens if the DUT already instantiates a BSCAN primitive such as the ChipScope debugging tool ICON A The hardware co simulation interface uses a BSCAN primitive at location 1 which could result in an error in MAP if the DUT also instantiates another BSCAN primitive at location 1 You might need to change the ChipScope ICON to use a different location for the BSCAN primitive Some device families such as Spartan 3 have only one BSCAN primitive where the hardware co simulation interface cannot coexist with a ChipScope ICON module To share the JTAG cable with ChipScope Analyzer or the XMD run the Tcl command hwcosim set shareCable 1 Q Can I skip the FPGA configuration and reuse the last downloaded bitstream for multiple co simulation runs A There is no command line or GUI option for that however you can run this Tcl command hwcosim set skipConfig 1 Beaware that by skipping the bitstream configuration the design running in the FPGA maintains its previous states across simulation runs You might need to appropriately reset the design in the test bench when a new simulation run starts Q Can I probe a signal inside the DUT that is co simulated in hardware A No Only the port
135. mulation Process This section describes the different modes of simulation and the steps involved in simulation Each sub section explains the differences between the two simulators Figure C 1 shows the different steps in simulation and the process for each step ModelSim XE ISE Libraries pre compiled and pre mapped in ISE Separate downlod of latest libraries gt from lounge Gathering files amp mapping libraries vcom vlog Parsing amp UP elaborating y ogcomp and fuse x exe or x exe gui vsim Simulating EXE can be renamed in fuse Tcl console Tcl console waveform viewer e minua Examining amp wave configuration list window h debugging memory viewer memory viewer d objects window objects window Not all viewers are listed FERA Figure C 1 Simulation Steps Step 1 Gathering Files and Mapping Libraries ModelSim XE Flow The ModelSim XE libraries are downloaded from http www xilinx com support download index htm Each time a new release of the ISE Design Suite is available you must go to this area and download the libraries separately These libraries are marked and must be used to ensure that the Xilinx libraries are not counted against the line count limits The modelsim ini file delivered with ModelSim XE is pre mapped with the correct Xilinx libraries ISim User Guide www xilinx com 149 UG660 v14 3 October 16 2012 Send Feedback 150 Appendix C Mig
136. n demand See Chapter 4 Waveform Analysis for more information Saving a Database to a WDB File When ISim is launched from the e ISE tool or the PlanAhead tool the WDB file is named according what is specified in the ISim Properties dialog box Command line use the wdb switch to specify a filename When a simulation is run results of the objects VHDL signals Verilog reg or wire being traced are automatically saved to the WDB no additional action is required If another simulation is run on the same design in the same working directory as a currently running simulation the WDB filename for the new simulation is the name of the first simulation appended with an integer The results of the first simulation are not overwritten For a WDB file called isim wdb subsequent invocations of simulation results in WDB files isim1 wdb isim2 wdb and so forth Note The name of the database file cannot be changed while running simulation Saving a Wave Configuration to a WCFG File When you save the wave configuration WCFG file ISim automatically adds a reference in the file to the associated waveform database WDB file There can be multiple WCFG files for a single WDB file The WCFG stores the order and inclusion of simulation objects their properties and any added wave objects such as dividers and markers found in the Wave window For more information see Working with the Wave Configuration in Chapter 4 When saving a WCFCG fi
137. n time 50 ns e Set data_in back to 1 at current simulation time 75 ns e Repeat this 101 pattern every 100 ns for a duration of 5000 ns force add data in 1 value 0 time 50 ns value 1 time 75 ns repeat 100 ns cancel 5000 ns Removing a Value Remove the values on signals s s1 and s2 isim force remove s sl s2 get arraydisplaylength The isim getarraydisplaylength command lets you display the limit of numbers of elements for array type HDL object The limit can be set with the isim set arraydisplaylength command ism get arraydisplaylength Command Syntax isim get arraydisplaylength where no options are available www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide isim isim isim Tcl Commands isim get arraydisplaylength Command Example Type the following command to determine the array display length and the array is 64 bit isim get arraydisplaylength Returns 64 get radix The isim get radix command lets you display the default radix as a string The radix is set with the isim set radix command isim get radix Command Syntax isim get radix No options are available isim get radix Command Example Return the radix isim get radix Returns the current global radix get userunit Theisim get userunit command displays the current unit of measurement for all time values where unit is unspecified The unit of measurement can be set with the isim set
138. name The filename command option specifies the name of the WCFG file to open wcfg open Command Example Open a WCFG file of the name toplevel wcfg wcfg open toplevel wcfg wcfg save The wcfg save command saves the active wave configuration to a file wcfg save Command Syntax wcfg save filename 132 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide wcfg wave Tcl Commands wcfg save Command Option The wcfg save command option lt filename gt specifies the name of the WCFG file to save wcfg save Command Example Save the active wave configuration to a WCFG file named toplevel wcfg wcfg save toplevel wcfg select The wcfg select command makes the specified wave configuration the active window wcfg select Command Syntax wcfg select wave config name wcfg select Command Option The wcfg select command option wave config name specifies the wave configuration to activate The wave config name must be the name of an open existing wave configuration otherwise the command reports an error wcfg select Command Example Activate the wave configuration named design wcfg select design add The wave add command adds HDL object s to the currently active wave configuration in the ISim graphical user interface and logs simulation output of the HDL object s to a waveform database wdb file The waveform database file is named
139. ne level can be expanded ata time e Click the collapse arrow to collapse the hierarchy e Using the menu command 1 Select an object 2 Select Edit gt Wave Objects gt Expand Expands the hierarchy object that is selected One level can be expanded at a time Collapse Collapses the hierarchy of the object selected e Using the context menu 1 Select an object 2 Right click and select the applicable command from the context menu Arranging the Main Window You can move windows panels and the toolbar around in the interface using one of the following techniques e Using Window Commands The Window menu commands are available for the Wave window and Text Editor window only e Using Drag and Drop For other parts of the interface like panels and the main window toolbar drag and drop lets you move the object to a new location To do so 1 Click and hold the header for the panel to move 2 Move the panel to a new location A gray box indicates where the panel is placed 3 Release the mouse button to place the panel to the new location Hiding and Restoring Windows Many of the parts of the main window can be hidden from view and restored again Note To restore windows to their default locations select View Restore Default Layout Standard minimize maximize and close commands apply to the Wave window and Text Editor window using the upper right hand buttons With these commands you can hide restore
140. ng indication Binding indication without use of entity aspect is not supported bit string literal m Empty bit string literal is not supported block statement Guard expression is not supported for example guarded blocks guarded signals guarded targets and guarded assignments are not supported ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback m Appendix B Exceptions to VHDL and Verilog Language Support XILINX Table B 1 VHDL Language Support Exceptions Cont d Supported VHDL Construct choice Exceptions Aggregate used as choice in case statement is not supported concurrent assertion statement Postponed is not supported concurrent signal assignment s tatement Postponed is not supported concurrent statement Concurrent procedure call containing wait statement is not supported conditional signal assignment Keyword guarded as part of options is not supported as there is no supported for guarded signal assignment configuration declaration Non locally static for generate index used in configuration is not supported entity class Literals unit file and group as entity class are not supported entity class entry Optional intended for use with group templates is not supported file logical name Although file logical name is allowed to be any wild expression evaluating to a st
141. ngth in VHDL Table 3 4 lists the VHDL type bit mapping to Verilog states Table 3 4 VHDL bit Mapping to Verilog States bit Verilog 0 0 1 1 Table 3 5 lists the VHDL type std_logic mappings to Verilog states Table 3 5 VHDL std logic mapping to Verilog States std logic Verilog X X o xa TIo zz N oO XN m X Because Verilog is case sensitive named associations and the local port names that you use in the component declaration must match the case of the corresponding Verilog port names ISim User Guide UG660 v14 3 October 16 2012 www xilinx com 48 Send Feedback XILINX Timing Simulation Gate Level Simulation Instantiating a VHDL Module in a Verilog Design Unit To instantiate a VHDL module in a Verilog design unit instantiate the VHDL entity as if it were a Verilog module For example module testbench wire wire FD F Q Q C CI in clk out D1 OUT LK D A Timing Simulation Gate Level Simulation Before launching a timing simulation you must have a timing simulation model and a Standard Delay File SDF for back annotation Use the NetGen tool to generate these files See Generating Gate Level Netlist Running NetGen in the Synthesis and Simulation Design Guide LIG626 Appendix D Additional Resources contains a link to this document Timing Simulation of a Verilog Design on the Command L
142. ns white spaces f cmd file Lets you save command options in a text file for future use This option reads and executes the saved options that are specified in cmd file generic top lt parameter gt lt value gt Overrides generic or parameter of a top level design unit with the specified value For example generic top P 10 applies the value of 10 on the top level parameter before elaboration ISim User Guide www xilinx com 51 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX Table 3 7 fuse vhpcomp and vlogcomp Command Options Cont d Option Description gui Launches the ISim GUI h Displays all command line options and usage hil zynq ps Use this to enable Zynq Processor System PS Hardware In Loop HIL simulation hwcosim board arg Hardware Co Simulation HWCoSim option specifies the board name hwcosim clock arg Specifies the clock port name on the HWCoSim instance hwcosim instance arg HWCoSim option specifies the hierarchical name of the instance to be run on the FPGA For example testbench UUT hwcosim no combinatorial path HWCoSim option to speed up simulation if the design run on FPGA does not have a purely combinatorial path from any input to any output hwcosim incremental arg HWCoSim option skips the implementation phase and reuses the previously created bit file
143. nt scope For example the following Tcl commands get the cableParameters property of the hardware co simulation instance under mytestbench top hwcosim inst scope mytestbench top hwcosim inst hwcosim get cableParameters hwcosim set property value Set a property of the hardware co simulation instance in the current scope The effect ofthe hwcosim set command is only taken after the initialization finishes after the init restart command and before the simulation runs before the run command Also the effect is not preserved between simulation runs you might need to call the hwcosim set command each time after calling the init or restart command For example the following Tcl commands set the skipConfig property of the hardware co simulation instance under mytestbench top hwcosim inst in two simulation runs init scope mytestbench top hwcosim inst hwcosim set skipConfig 1 run 1000 ns restart scope mytestbench top hwcosim inst hwcosim set skipConfig 1 run 1000 ns The following hardware co simulation properties can be changed before a simulation runs skipConfig Default is 0 Set to 1 if the FPGA configuration should be skipped To skip the configuration the FPGA should have been configured with a valid hardware co simulation bitstream Otherwise unexpected behavior can occur cableParameters Default is an empty string This property is used to specify a third party JTAG cable supported by iMPACT or the ChipS
144. o these documents Creating Activity Files ISim User Guide You can write out two types of stimulus files e SAIF The Switching Activity Interchange format SATF file contains toggle counts number of changes on the signals of the design It also contains the timing attributes which specify time durations for signals at level 0 1 X or Z The SAIF file is recommended for power related tasks such as power analysis or power driven implementation because it is smaller than the VCD file e VCD The Value Change Dump VCD file is an ASCII file containing header information variable definitions and value change details for each step of the simulation The file can be used to estimate the power consumption of the design The computation time of this file can be very long and the resulting file size is larger than the SAIF file www xilinx com 81 UG660 v14 3 October 16 2012 send Feedback 82 Chapter 7 Writing Activity Data for Power Consumption XILINX To write out a switching activity file 1 Create the activity file to gather the signals transition during simulation for power estimation e SAIF Use the saif command at a Tcl prompt e VCD Use the vcd command at a Tcl prompt or set the ved ile optionin your simulation executable at the command line Run simulation For example run 1000 ns If you are running your simulation using the simulation executable at the command line the first and second steps
145. o 3 d ram 3d vector end record type recarray is array 0 to 3 4 downto 1 of rectype signal recarrsig recarray signal recsig rectype Set the second element b of the record recsig to the string abc put recsig b 2 4 abc Set the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig to 0110 put recsig d 2 3 1 0110 Set the first two bits of the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig to 01 put recsig d 2 3 1 1 2 01 Set the four bit wide vector represented by the coordinates 2 3 1 in the three dimensional array d in the record recsig represented by the coordinates 2 2 in the two dimensional array recarrsig to 0011 put recarrsig 2 2 d 2 3 1 0011 The quit command exits either the simulation or the tool depending on the command options With no options the quit command closes the ISim tool after being prompted to do so for graphic user interface GUI mode or simply closes ISim in command line mode quit Command Syntax quit f s Where e f Quits the current simulation and quits the ISim tool You are not prompted to save the wave configuration even when changes have been made to wave configurations The switch has no effect at the command line Li S Quits the current simulation while keeping the graphical user interface open At this point ISim can only be used for
146. o add by exploring the design hierarchy in the Instances and Processes panel and the Objects panel as described above or type scope in the Console panel 2 Inthe Console panel type wave add to and an individual object or a group of objects Wave Configurations and WCFG Files Though both a wave configuration and a WCFG file refer to customizing lists of waveforms there is a conceptual difference between them e The wave configuration is an object with which you can work that is loaded into memory e The WCFCG file is the saved form of a wave configuration on disk Wave Configuration Names and WCFG File Names A wave configuration can have a name or be untitled The name shows on the tab of the wave configuration window e When saving a wave configuration to a WCFG file using a GUI Tcl command the WCEFG file takes the supplied name as a command argument e When loading a wave configuration from a WCFG file the wave configuration uses the name of the WCFG file Adding Copies of Signals or Buses You can add copies of the same signal or bus in a wave configuration for comparing waveforms You can place copies of the same signal or bus anywhere in the wave configuration such as in groups or virtual buses Adding a Copy of a Signal or Bus 1 Selecta signal or bus in the wave configuration in the Wave window 2 Select Edit gt Copy or type Ctrl C The signal name is copied to the clipboard 3 Select Paste command or type
147. o derate the performance of the simulator for that invocation ISim Full The full version of ISE Simulator Feature Comparison Table C 1 ModelSim and ISim Feature Comparison Feature ModelSim XE Starter ModelSim XE Full ISim Lite ISim Full Line Limit Statements 10 000 40 000 50 000 None Performance 30 of ModelSim PE 40 of ModelSim PE Same as Same as or ModelSim DE or ModelSim DE ModelSim XE ModelSim XE Mixed Language No No Yes Yes VHDL Yes Yes Yes Yes Verilog Yes Yes Yes Yes System Verilog for No No No No Design Sas Venlo foe No No No No Verification Debugging Yes Yes Yes Yes Environment Standalone Waveform Yes Yes Yes Yes Viewer Memory Viewer Editor Yes Yes Yes Yes Verilog PLI VPI Yes Yes No No VHDL FLI VHPI No No No No Code Coverage No No No No SecureIP HardIP No No Yes Yes Support EDK Support No No Yes Yes System Generator No No Yes Yes Support CORE Generator Yes Yes Yes Yes Support MIG Support No No Yes Yes 148 Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX Simulation Process Table C 1 ModelSim and ISim Feature Comparison Cont d Feature ModelSim XE Starter ModelSim XE Full ISim Lite ISim Full Floating License No No Yes Yes 32 bit OS Support Windows Windows Windows Linux Windows Linux Pic peuve Oe No No Windows Linux Windows Linux Support Si
148. og file generation nospecify Verilog only option Disables specify block functionality notimingchecks Verilog only option Disables the timing checks o gim exe Specifies the name of the simulation executable output file The name of the file is sim exe If you do not use this option the default executable name is work library mod name platform x exe where e work library is the work library e module name is the first specified top module e platform is the operating system override timeprecision Verilog only option Overrides the time precision unit of accuracy of Verilog modules in the design with the time precision specified in the timescale option override timeunit Overrides the time unit unit of measurement of delays of all Verilog modules in the design with the time unit specified in the timescale option prj prj file prj Specifies a project file to use for input A project file contains a list of all the files associated with a design It is the main source file used by the ISE tool A prj file must havea prj extension ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback Chapter 3 Compilation and Simulation XILINX Table 3 7 fuse vhpcomp and vlogcomp Command Options Cont d Option rangecheck Description VHDL only option Specifies value range check to be performed
149. ommand adds removes or generates a list of conditional actions A conditional action is equivalent to a VHDL process or a Verilog always block When added it starts monitoring signals those that appear in the isim condition expression continually during simulation The condition expression is evaluated anytime a signal change is detected When a specified condition expression is met the specified command runs e isim condition remove stops monitoring signals e isim condition list lists all active conditional actions added and their labels and IDs isim condition Command Syntax isim condition add remove list condition expression command radix radix type label label name index index name all isim condition Command Options Table 9 4 isim condition Command Options Option add remove list Specifies to add a condition remove one or more conditions or Description list all active conditions lt condition expression gt lt command gt The lt condition expression gt is associated with the add function and it determines when to run the specified lt command gt Operators used in the condition expression include not equal equal amp amp and and or A space is required between words in the expression and the operator such as clk Stl The command is a Tcl command or script that is executed when the condition expression is
150. on call that states In named parameter association in a function call slicing indexing or selection of formals is not supported ISim User Guide www xilinx com UG660 v14 3 October 16 2012 Table of Contents Revision History 2o reiris Corre HERR LEE Re dr aas 2 Chapter 1 Introduction to ISim Simulation Libraries 145 eek uussa neck dele EUH sada e eoe eel 3 Language Support eic ce ve PEPPER EORR ERROR ERROR AP d ds 3 Peat r Support s cce PFERDE RETE KU CRI e RS CUN RU PUR ER EO RIA d MORIR RU AE 3 Operating System Support ioo REIR eras 4 ISim Modes of Operation i ciscacvsduiupia t es er RE er bb poe be p oe oae 4 Simulation Steps Overview 4 5 scesccpden pae der o e e ace a lee Rie Ro e e RR ted 4 I51m Tutorials 26 3 petite dishes edn edie Ene He be Een tidy inde 8 Chapter 2 Using the ISim GUI I5im GUI Overview 65008 EEN hhh en EA Ca eR OEE SCR RR 9 Setting Sim Preferences 3 3 0 cereo re Rr epERr REX Ee EIU REY Ee due e reda 32 Chapter 3 Compilation and Simulation Parsing Design PIGs iiio pha rodea ore de ER DR CR a dr ed d 36 Project File Syntax 22s mina y Klos Cer Ctr CHR e rd o ee CC Ie FCU on de a EAS 43 Predefined XILINX ISIM Macro for Verilog Simulation 44 Simulating the Design auod wpe dor edes da Rt a e Rap teo pale Moo ue ee Re 44 Mixed Language Simulation uos eese 45 Timing Simulation Gate Level Simulation 0005 49 I
151. ontrolled simulation runs stopping at each breakpoint set in your HDL source files During design debugging you can also run the Simulation gt Step command to advance the simulation line by line to debug the design at a more detailed level 78 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Using Breakpoints Deleting Breakpoints You can delete a single breakpoint or all breakpoints from your HDL source code Deleting a Single Breakpoint Delete a single breakpoint using one of the following methods e Click the Breakpoint button e e At the Tcl prompt Type bp list to list all breakpoints in your design and shows each breakpoint index number and line number Type bp del or bp remove followed by the breakpoint index number of the breakpoint to remove See bp page 104 Note You can also remove a breakpoint in the Breakpoints by selecting a breakpoint and using the Delete context menu command or the Delete button Removing All Breakpoints Use one of the following methods to remove all breakpoints e Select View gt Breakpoint gt Delete All Breakpoints Click the Delete All Breakpoints button W e Type bp clear at the Tcl prompt ISim User Guide www xilinx com 79 UG660 v14 3 October 16 2012 Send Feedback Chapter 6 Debugging at the Source Level 80 Send Feedback www xilinx com XILINX ISim User Guide UG660 v14 3 October 16 2012 XILINX Chapt
152. ool or the PlanAhead tool to produce the co simulation executable a HWCoSim bitstream and a co simulation project file 84 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX fuse Command Line Flow fuse Command Line Flow The fuse command provides some additional compiler options to compile a design for hardware co simulation Usage fuse prj project file top level modules hil zynq ps hwcosim board board hwcosim clock clock hwcosim constraints constraints file hwcosim incremental 0 1 hwcosim instance instance hwcosim no combinatorial path Where e hil zynq ps enables Zynq Processor System PS Hardware In Loop HIL simulation e hwcosim board specifies the identifier of the hardware board to use for co simulation See Board Support page 92 for a list of supported boards e hwcosim clock specifies the port name of the clock input for the instance For a design with multiple clocks specify the fastest clock using this option so that ISim can optimize the simulation Other clock ports are treated as regular data ports e hwcosim constraints optional specifies the custom constraints file that provides additional constraints for implementing the instance for hardware co simulation A custom constraints file is also used in the hybrid co simulation flow to specify which ports of the instance are mapped to external I Os or clocks e
153. or Hardware Co Simulation drop down list select a board The list shows only the boards with an FPGA of same project device family If a previous hardware co simulation bitstream is available and the instance under co simulation remains unchanged check the Reuse Last Bitstream File check box to skip the implementation flow for hardware co simulation Click OK Notice that the instance enabled for hardware co simulation is now marked with a special icon e Select the test bench module in the hierarchy pane to the start the simulation Hardware Co Simulation must be started at a level above the instance that is selected for co simulation 6 Inthe Instances and Processes panel of the test bench double click Simulate Behavior Model to start the compilation and simulation process 7 Open the Process Properties for the Simulate Behavior Model to specify any additional options for ISim before starting the compilation and simulation process Figure 8 1 through Figure 8 3 page 88 display steps 1 through 8 Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX ISim User Guide UG660 v14 3 October 16 2012 j i l amp l a a u a V Tools Flow wimax duc cfr vS v1 cw xcSvlxSOt 1ff1136 wimax duc cfr vS v1 tb structural B dh Setas Top Module SmartGuide Figure 8 1 Steps 1 2 and 3 8 Source Properties Hardware Co Simulation Properties XI Use this to
154. or Verilog d lt macro gt optionally lets you define one or more macros For Verilog i lt include_path gt optionally lets you define one or more include path directories ISim User Guide www xilinx com 43 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX Predefined XILINX ISIM Macro for Verilog Simulation XILINX ISIMis a Verilog predefined macro The value of this macro is 1 Predefined macros perform tool specific functions or identify which tool to use in a design flow module isim predefined macro integer fp initial begin ifdef XILINX ISIM display XILINX ISIM defined fp fopen ISIM dat else Sdisplay XILINX_ISIM not defined fp fopen other dat endif Sfdisplay fp results end endmodule Simulating the Design Simulation is the process of verifying the logic and timing of a design and can be run from ISim using functions in the GUI in a Tcl batch file or at the command line After you parse the design files and create a simulation executable using fuse you can run a functional or a timing simulation Running Simulation You can run simulation using any of the following methods e Using the Command Line e Using the GUI Using the Command Line You can run the executable generated by the fuse command to launch simulation in a command shell If you do not specify the gui switch to the simulation executable
155. ork library 40 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Parsing Design Files Verilog Instantiation Unit When a Verilog design instantiates a component the fuse command treats the component name as a Verilog unit and searches for a Verilog module in the user specified list of unified logical libraries in the user specified order e If found fuse binds the unit and the search stops e If fuse cannot find a Verilog unit it treats the name of the instantiated module as a VHDL entity name and continues a case insensitive search The fuse command searches for an entity with the same name as the instantiated module name in the user specified list and order of unified logical libraries searches for and selects the first one matching name then stops the search e If the case sensitive search is not successful fuse performs a case sensitive search for a VHDL design unit name constructed as an extended identifier in the user specified list and order of unified logical libraries e If fuse finds a unique binding for any one library it selects that name and stops the search Note For a mixed language design the port names used in a named association to a VHDL entity instantiated by a Verilog module are always treated as case insensitive Also note that you cannot use a defparam statement to modify a VHDL generic VHDL Instantiation Unit When a VHDL design instantiates a componen
156. ositioning the main cursor hold the Shift key while clicking Note When placing the secondary cursor by dragging you must drag a minimum distance before the secondary cursor appears Moving a Cursor Markers To move a cursor hover over the cursor until you see the grab symbol and click and drag the cursor to the new location As you drag the cursor in the Wave window you see a hollow or filled in circle if the Snap to Transition button is selected which is the default behavior e A hollow circle indicates that you are between transitions in the waveform of the O selected signal e A filled in circle indicates that you are hovering over the waveform transition of e the selected signal A secondary cursor can be hidden by clicking anywhere in the Wave window where there is no cursor marker or floating ruler You can add move and delete markers Adding a Marker You add markers to the wave configuration at the location of the main cursor 1 Place the main cursor at the time where you want to add the marker by clicking in the Wave window at the time or on the transition 2 Select Edit Markers Add Marker or click the Add Marker button A marker is placed at the cursor or slightly offset if a marker already exists at the location of the cursor The time of the marker displays at the top of the line mg www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Customizing t
157. ou can control whether or not to limit a preset maximum number of child elements displayed for every composite object You can change the preset maximum number using the Preferences dialog box To display all child elements 1 Right click anywhere in the object list in the Objects panel 2 Right click and select Show All Elements The number of children in the object hierarchy display To limit the display of child elements right click anywhere in the object list in the Objects panel and select Limit Elements To change the preset maximum number of child elements set the preference settings as follows 1 Select Edit gt Preferences 2 Inthe Preferences dialog box select ISim Simulator 3 Select Limit the maximum number of elements displayed to and enter a number 4 Click Apply and OK www xilinx com 25 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX Selecting an Object in the Wave Window To highlight signals for an object in the Objects panel 1 Select an object in the Objects panel 2 Right click and choose Select in Wave Window Text Editor Window The Text Editor window is available for access to the underlying HDL source files Modifying Source Files To modify source files 1 Open the source file in the ISim Text Editor 2 Make the appropriate edits and run Re Launch to re simulate the design C9 Relaunch The ISE project automatically saves the source fil
158. oundary and Mapping Rules The following restrictions apply to the boundaries between VHDL and Verilog design units modules e The boundary between VHDL and Verilog is enforced at design unit level e A VHDL design is allowed to instantiate one or more Verilog modules e nstantiation of a Verilog UDP inside a VHDL design is not supported e A Verilog design can instantiate a VHDL component corresponding to a VHDL entity only e Instantiation of a VHDL configuration in a Verilog design is not supported Instantiating a Verilog Module in a VHDL Design Unit 1 Declare a VHDL component with the same name as the Verilog module respecting case sensitivity that you want to instantiate For example COMPONENT MY VHDL UNIT PORT Q out STD ULOGIC D in STD ULOGIC G s in STD ULOGIC END COMPONENT 2 Use named association to instantiate the Verilog module For example UUT MY VHDL UNIT PORT MAP Q gt 0 D gt I C gt CLK To ensure that you are correctly matching port types review the Port Mapping page 47 46 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Mixed Language Simulation Port Mapping The following rules and limitations for port mapping are used in mixed language projects Supported Port Types Table 3 1 lists the supported port types Table 3 1 Supported Port Types VHDL Verilog IN INPUT OUT OUTPUT INOUT INOUT
159. over compilation and elaboration Step 3 Simulating the Design ModelSim XE Flow Running VSIM elaborates the design and runs the simulation By default running vsim launches the GUI To run in command line mode use the c switch ISim Flow Running fuse creates a named executable You must run this executable to launch the simulation By default this executable is named x exe but you can change the name By default running the executable runs the simulation in command line mode To launch the GUI use the gui switch www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Simulation Process Step 4 Examining and Debugging the Design Customizing Wave Operations ModelSim XE and ISim provide the same capabilities for customizing the waveform window but perform the customization differently ModelSim XE uses standard Tools Command Language Tcl commands for all waveform operations ISim uses a subset of Tcl commands but the majority of the customizing is through the GUI with results saved in the waveform configuration file The waveform configuration file for ISim is an XML based file that you cannot edit while the waveform Tcl commands in ModelSim XE can be modified The load time for the wave configuration through the ISim implementation is faster because loading an XML file is faster than executing multiple Tcl commands Note Sim does not have Tcl support for all wave configuration
160. pen select the wdb file type from the file filter list and select the wave database WDB file from a previous simulation Alternatively you can type isimgui exe open lt wdb_file gt wdb Where e isimgui exe is the application executable e open lt wdb_name gt wdb opens the specified waveform database file in the GUI The static viewer displays the data from the previous simulation in the Objects panel and the Instances and Processes panel There is no waveform data open in the Wave window You can open an existing wave configuration using File Open or create a new wave configuration using File New www xilinx com 75 UG660 v14 3 October 16 2012 Send Feedback Chapter 5 Viewing Simulation Results v Send Feedback www xilinx com XILINX ISim User Guide UG660 v14 3 October 16 2012 XILINX Stepping Through a Simulation Chapter 6 Debugging at the Source Level You can debug your HDL source code to verify that the design is running as expected Debugging is accomplished through controlled execution of the source code to determine where issues might be occurring Available strategies for debugging are e Step through the code line by line For any design at any point in development you can use the Step command to debug your HDL source code one line at a time to verify that the design is working as expected After each line of code run the Step command again to continue the analys
161. ph e den ir wun adem ee n del Miche ween ied 84 fuse Command Line Flow uses 85 Tools FloW 91st s aces ba EP iube he ee Oe ea ect ve ie eek 85 Hybrid Co Simulation Flow sss 88 Hardware Board Usage civic stib hA FERREA ERES EREDLER UE dri 90 Hardware Co Simulation sssssseseeee ee 90 ISim Hardware Co Simulation Tcl Commands Luuuuuuuus 91 Board SUpport decree Ra EORR OR Rep CRF RC Endo KO ee Elta ee eras 92 Frequently Asked Questions sese 95 Chapter 9 ISim Tcl Commands Aliasing Simulation Commands sess 102 ISim Wave Viewer Tcl Commands Overview uuuussss 103 Command Line Conventions uuussseeeee e 103 Tcl Commands oin Debet eet adr dou EROR Gre RE 104 Appendix A Library Mapping File xilinxisim ini Appendix B Exceptions to VHDL and Verilog Language Support VHDL Language Support Exceptions 0 0 0 e cece eee eee ees 141 Verilog Language Support Exceptions 0 0 000 e cece eee eee 143 Appendix C Migrating from ModelSim XE to ISim About ModelSim XE usssseseeseee e n 147 About ISI nos ooo ib Rin eb ta nade dice Rew ee eas E Ue UE 148 Pearle Comparison coge da RR Ao OUR een hie Oe d cen dp Ie i eR in 148 Simulation Process 000 000 c cette nee e 149 Appendix D Additional Resources Xilinx Resources suse e a 157 ISim Tutorials
162. pon Resumes the dumping process after the dumpof option is invoked and dumps all selected values at the time dumpon is invoked Invokes the Verilog dumpon directive dumpall Creates a checkpoint in the VCD file that dumps the current value of all selected variables Invokes the Verilog dumpa11 directive dumplimit file size Limits the size of the VCD file ile size specifies the maximum size of the VCD file in bytes When the size of VCD file reaches the limit the dump process stops and a comment is inserted in the VCD file indicating that the dump limit was reached Invokes Verilog dumplimit directive dumpflush Empties the operating system VCD file buffer to ensure that all the data in that buffer is stored in the VCD file After executing dump process resumes as before so no value changes are lost Invokes Verilog dumpf1ush directive vcd Command Examples The vcd command can be used as follows Following are the commands you would use to write the VCD simulation values of the module UUT to a VCD file after running simulation for 1000 ns Specify which file to write vcd dumpfile adder vcd Specify which module net activities to write vcd dumpvars m UUT Run simulation for given time run 1000 ns Dump the activity data to the VCD file vcd dumpflush wave log The wave log command logs simulation output of HDL object s to a waveform database wdb file VHDL signal Veri
163. ported Verilog language support Table B 2 Verilog Language Support Exceptions Verilog Construct Exception Compiler Directive Constructs celldefine not supported endcelldefine not supported undefs Supports parameterized define macros unconnected drive not supported nounconnected drive not supported Attributes attribute instance not supported attr spec not supported attr name not supported Primitive Gate and Switch Types cmos switchtype not supported mos switchtype not supported pass en switchtype not supported Generated Instantiation generated instantiation The module or generate item alternative is not supported Production from 1364 2001 Verilog standard generate item or null generate conditonal statement generate case statement generate loop statement generate block module or generate item Production supported by Simulator generate item or null generate conditional statement generate case statement generate loop statement generate blockgenerate condition www xilinx com UG660 v14 3 October 16 2012 Send Feedback 143 Appendix B Exceptions to VHDL and Verilog Language Support 144 XILINX Table B 2 Verilog Language Support Exceptions Cont d Verilog Construct genvar assignment Exception Partially supported All generate blocks must be named Production from 1364
164. queried e parameter name is the name of the VHDL parameter to be queried e process name process variable name is the name of the process and process variable to be queried To query the value of a process variable you must also supply the name of the process that contains the variable The process name and process variable names must be separated by a forward slash ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback 123 Chapter 9 ISim Tcl Commands XILINX Table 9 11 show Command Options Cont d Option signal name element references e signal name is the name of the signal or bus to be Description queried This can also be the name of an array of signals or buses an array of records containing signals and buses or a record of arrays of buses signals e Usea dot to separate the record hierarchy as in show value recsig c Use a forward slash to delimit the hierarchical name of the signal to query a value to a signal on a lower level of hierarchy as in show value mymod mysig element reference refers to the different ways in which the sub elements of the signal name can be referenced when used with the show command This allows further refinement to the signals by referencing the individual sub elements of a signal See the following examples Two integers separated by a colon and enclosed in parenthesis displays a range of
165. r put clk 1 radix bin or put clk 1 radix bin Assign a value to a 4 bit bus called busx put busx 0101 Assign a value FF to signal A put A FF radix hex Assign a bit value of 1 to a signal called count 6 in the module u1 that is instantiated under your current scope put ul count 6 1 Assign a Value To a Standard Logic Vector For a standard logic vector called sigx thatis declared as follows signal sigx std logic vector 0 to 5 Set bit 0 of sigx to 1 put sigx 0 1 Set slice 1 to 2 of sigx to 11 put sigx 1 2 11 Set all of sigx to 101010 put sigx 101010 Assign a Value To an Array of Objects To assign a value to an array of standard logic vectors that is declared as follows signal sigarray 0 to 3 vectorarray 0 to 5 1 to 4 2 to 6 Set every bit of the array element of sigarray to 1 put sigarray 0 1 2 1111 Set the first two bits of the array element of sigarray to 10 put sigarray 0 1 2 1 2 10 Set bits three of the array element of sigarray to 1 put sigarray 0 1 2 3 1 116 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim User Guide Tcl Commands Assign a value to an array of records which in turn contain an array of standard logic vectors that is declared as follows type ram 3d vector is array 0 to 10 7 downto 0 0 to 2 of std logic vector 1 to 4 type rectype is record a integer b string 1 to 7 c std logic vector 0 t
166. radix command is used or if none is set default is used ISim User Guide www xilinx com 109 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX isim 110 Table 9 5 sim force Command Options Cont d Option Description time time Time can be a string such as 10 10 ns 10 ns When a number entered without a unit the simulator resolution unit is used which is ps Time is relative to the time of execution of the command cancel lt time gt Cancels the force command after the specified time repeat lt time gt Repeats the cycle after the specified time isim force Examples The isim force command can be used as follows Assigning a Value Force signal rst to 0 starting at the current simulation time isim force rst 0 Forcesignal rst to 1 starting at 10 ns from the current simulation time and cancel forcing after 50 ns from the current simulation time isim force rst 1 time 10 ns cancel 50 ns Apply a clock to the signal clk such that clk goes to 1 at current simulation time goes back to 0 at 20 ns later and then repeats this every 40 ns until 1us from the current simulation time for example to generate a clock with 50 duty cycle and 40 ns period for a duration of 1 us isim force clk 1 value 0 time 20 ns repeat 40 ns cancel 1 us To e Force signal data in to 1 at current simulation time e Set data_in to 0 at current simulatio
167. rating from ModelSim XE to ISim XILINX ISim Flow Libraries for ISim are updated as part of the standard Xilinx installation No additional steps are needed Mapping is also handled automatically by Xilinx You do not need to know where to download from or how to map the Xilinx libraries to start simulating Step 2 Parsing and Elaborating the Design ModelSim XE Flow ModelSim XE uses the following commands for compilation and elaboration VCOM options VHDL Compiler runs the VHDL compiler and compiles VHDL files to a specified directory VLOG options Verilog Compiler runs the Verilog compiler and compiles Verilog files to a specified directory VSIM options VSIM simulator elaborates the load for the simulation For each of these commands multiple options give you additional control over compilation and elaboration For a complete list of equivalent ModelSim XE commands see Appendix B Exceptions to VHDL and Verilog Language Support ISim Flow ISim uses the following commands for compilation and elaboration e vhpcomp VHDL Compiler runs the VHDL compiler and compiles VHDL files to a specified directory e vlogcomp Verilog Compiler runs the Verilog compiler and compiles Verilog files to a specified directory e fuse VSIM simulator elaborates the load for the simulation and creates an executable that needs to be launched to run the simulation For each of these commands multiple options give you additional control
168. rent B e Ifnot found search for the instantiated module in the work library which is one of the following e The library into which HDL source is being compiled e The library explicitly set as work library e The default work lib is named as work 42 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 g XILINX Project File Syntax uselib Examples File half adder v compiled into File full adder v compiled into logical library logical library named adder lib named work module module half adder a b c s full adder c in c out a b sum input a b input c in a b Oontput C S output c out sum S a lb wire carryl carry2 sum1 c a amp b uselib lib adder lib endmodule half adder adderl1 a a b b c carryl s sum1 half adder adderl a suml1 b c in c carry2 s sum c out carryl carry2 endmodule Project File Syntax To parse design files using a project file create a file called lt proj_name gt prj and use the following syntax inside the project file verilog work library file names d lt macro gt i include path vhdl work library file name Where work library is the library into which the HDL files on the given line should be compiled file names are Verilog source files You can specify multiple Verilog files per line file name is a VHDL source file specify only one VHDL file per line F
169. ring value only string literal and identifier is acceptable as file name function call In named parameter association in a function call slicing indexing or selection of formals is not supported instantiated unit Direct configuration instantiation is not supported mode Linkage and Buffer ports are not supported completely options Guarded is not supported primary At places where primary is used allocator is expanded there procedure call In named parameter association in a procedure call slicing indexing or selection of formals is not supported process statement Postponed processes are not supported selected signal assignment The guarded keyword as part of options is not supported as there is no support for guarded signal assignment signal declaration Signal kind is not supported Signal kind is used for declaring guarded signals which are not supported subtype indicationd Resolved subtype of composites arrays and records is not supported waveform Unaffected is not supported waveform element Null waveform element is not supported as it only has relevance in the context of guarded signals ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Lue Send Feedback XILINX Verilog Language Support Exceptions ISim User Guide Verilog Language Support Exceptions The following table lists the exceptions to sup
170. ro definition value value f cmd file generic top parameter value h hil zynq ps hwcosim board arg hwcosim clock lt arg gt hwcosim instance lt arg gt hwcosim no combinatorial path hwcosim incremental lt arg gt i include path incremental initfile sim init file intstyle ise xflow silent default L lib search lib lib path log file name maxdeltaid lt number gt maxdelay maxdesigndepth lt depth gt mindelay mt lt value gt nodebug nolog nospecify notimingchecks o gim exe override timeprecision override timeunit pry prj Frle prJj rangecheck sdfnoerror sdfnowarn sdfmin sdftyp sdfmax lt root file gt sdfroot lt root_path gt sourcelibdir lt directory_name gt sourcelibext lt file_extension gt sourcelibfile lt file_name gt timeprecision_vhdl lt time_precision gt timescale lt time_unit time_precision gt typdelay v verbose lt value gt version The option descriptions are in the fuse vhpcomp and vlogcomp Command Options section ISim User Guide www xilinx com 39 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX fuse Command Examples Use the fuse command with a project file and source library fuse prj test prj test sourcelibfile mylib1 lib abc v sourcelibfile
171. rrent scope onerror show time dump resume 118 www xilinx com ISim User Guide send Feedback UG660 v14 3 October 16 2012 XILINX Tcl Commands run The run command starts simulation With no options the run command runs simulation for 100 ns The equivalent GUI commands are e Simulation gt Run All e Simulation gt Run run Command Syntax run all continue time unit run Command Options Table 9 8 run Command Options all Option Runs simulation until there are no more events or until ISim encounters Description a breakpoint See bp Command for information about setting and removing breakpoints continue Resumes simulation after ISim has stopped at a breakpoint This option is the same as running run all time unit e time is the length of time you want simulation to run It can be any positive integer or decimal lt unit gt isthe unit of time Possible values are s ps ns us ms and sec Default is ps run Command Examples The run command can be used as follows Run simulation until there are no more events or until ISim reaches a breakpoint run all Run simulation for 2000 nanoseconds run 2000 ns Run simulation for 1 2 nanoseconds run 1 2 ns Run simulation for 100 ns run ISim User Guide UG660 v14 3 October 16 2012 www xilinx com Send Feedback 119 Chapter 9 ISim Tcl Commands XILINX sa
172. ry name e File comments must start with ISim User Guide www xilinx com 139 UG660 v14 3 October 16 2012 Send Feedback Appendix A Library Mapping File xilinxisim ini XILINX 140 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 g XILINX VHDL Language Support Exceptions Appendix B Exceptions to VHDL and Verilog Language Support VHDL Language Support Exceptions ISim supports e VHDL IEEE STD 1076 1993 e Verilog IEEE STD 1364 2001 with exceptions as noted in the Exceptions Column in the following tables Table B 1 VHDL Language Support Exceptions Supported VHDL Construct abstract_literal Exceptions Floating point expressed as based literals are not supported aggregate Mixing choice directions in an aggregate is not supported alias_declaration Alias to non objects are in general not supported particularly the following Alias of an alias Alias declaration without subtype indication Signature on alias declarations Operator symbol as alias designator Alias of an operator symbol Character literals as alias designators alias designator Operator symbolas alias designator Character literal as alias designator association element Globally locally static range is acceptable for taking slice of an actual in an association element attribute name Signature after prefix is not supported bindi
173. s In addition it allows a faster way to set waveform window using wave configuration file Use Automatic Do File N A You cannot prevent Project Navigator from creating the ISim script Custom Compile File List Use Custom Project File Custom Project Filename Lets you change the compile order of the file N A Waveform Database Filename Lets you specify a different database for the simulation Custom Compiler Commands Other VSIM Command Other Compiler ISim splits the VSIM commands into fuse commands and Line Options Options executable commands Other Simulator Commands 154 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Table C 2 Simulation Properties in Project Navigator Cont d Simulation Process ModelSim XE Property Name Other VLOG Command Line Options Other VCOM Command Line Options ISim Property Name Other Compiler Options Comments Passes the options to the fuse command in ISim Runtime Settings Simulation Run Time Simulation Run Time Simulation Resolution N A ISim defaults to 1ps Language Settings VHDL Syntax N A The default in ISim is 93 Use Explicit Declarations N A Only Value Range Check Specify Search Directories for include Other VCOM Command Incremental ModelSim XE does not have specific options for this but
174. s access to frequentlyused ISim commands wer 689 ios z 6 il GG Relaunch Table 2 2 describes the Simulation toolbar options Table 2 2 Simulation Toolbar Options Button Description Po Moves the main cursor to the nearest marker to the left of the current m position of the marker br Moves the main cursor to the nearest marker to the right of the main current position of the marker 4 Adds a marker at the position of the main cursor to the Waveform area a Resets the simulation time to zero b Runs simulation until there are no more events a stop command is issued or a break point is encountered p Runs simulation for the amount of time specified Run For 1 00us w Specifies the amount of time the simulation runs Qz Steps through the simulation to the next line of HDL code Forces a running simulation to stop immediately Simulation can be Il restarted using one of the run commands F Ends the current simulation leaving the simulation data open C9 Re taunch Relaunch Simulation Window Menu and Toolbar The Window toolbar provides access to frequently used Window menu commands 257757 The Window toolbar options are the standard options to cascade tile show side by side and bring to front Help Toolbar The Help toolbar provides access to frequently used Help menu commands Support and Services displays the Xilinx Support page in the default web browser 12 ww
175. s the ISim GUI h Displays all command line options and usage intstyle Use one of the specified styles for printing messages ise xflow silent default e ise formats messages for the ISE Console e xflowformats messages for XFLOW silent suppress all messages e default is the specified default message setting log file name Generates a log file with the specified ile name maxdeltaid number Specifies the maximum delta number in an integer nolog Blocks log file generation sdfnowarn Blocks the display of SDF warnings sdfnoerror Treats SDF errors as warnings sdfmin sdftyp sdfmax root file Specifies the type of delays for ISim to use e sdfmin Annotates lt file gt at lt root gt with minimum delay e sdftyp Annotates lt file gt at root with standard delay e sdfmax Annotates lt file gt at root with maximum delay sdfroot root path Sets default place in the design hierarchy where SDF annotation is applied tclbatch file name Specify a Tcl script file to be run after simulation is loaded The ile name specifies the name of file containing Tcl commands To quit simulation after executing the Tcl commands in ile name you must include the quit Tcl command as the last command in the ile name testplusarg string string value When the simulator matches this command line argument string wi
176. t the fuse command treats the component name as a VHDL unit and searches for it in the logical work library e Ifa VHDL unit is found the fuse command binds it and the search stops e If fuse does not find a VHDL unit it treats the case preserved component name as a Verilog module name and continues a case sensitive search in the user specified list and order of unified logical libraries The command selects the first matching the name then stops the search e If case sensitive search is not successful fuse performs a case insensitive search for a Verilog module in the user specified list and order of unified logical libraries If a unique binding is found for any one library the search stops uselib Verilog Directive The Verilog uselib directive is supported in ISim and by the library search order uselib Syntax uselib compiler directive uselib Verilog XL uselib directives gt lt lib directive gt Verilog XL uselib directives dir library directory file library file libext lt file_extension gt lt lib directive gt lt library reference gt lt library reference gt lt library reference gt lib lt logical library name gt ISim User Guide www xilinx com 41 UG660 v14 3 October 16 2012 Send Feedback Chapter 3 Compilation and Simulation XILINX uselib Lib Semantics The useliblib directive can not be used with any of the Verilog XL uselib directives
177. te sve oe eee DM It e LLL ie es 157 UG660 v14 3 October 16 2012 www xilinx com ISim User Guide XILINX Simulation Libraries Chapter 1 Introduction to ISim Xilinx ISim is a Hardware Description Language HDL simulator that lets you perform behavioral and timing simulations for VHDL Verilog and mixed VHDL Verilog language designs This document describes the ISim tool features lists the HDL languages that ISim supports and explains the methods of interfacing with the tool For easier navigation through this document in your PDF reader turn on Previous View and Next View buttons to navigate back and forth to linked information Simulation Libraries ISim uses precompiled simulation device libraries and updates those libraries automatically when updates are installed Note Do not run the Simulation Library Compilation Wizard Compx1ib to compile libraries for use with ISim Language Support ISim supports the following languages e VHDL IEEE STD 1076 1993 e Verilog IEEE STD 1364 2001 e Standard Delay Format SDF version 2 1 e VITAL 2000 Feature Support The following features are supported e Incremental compilation Source code debugging e SDF Annotation e VCD Generation e Power analysis and optimization using SAIF e Native support for HardIP blocks such as MGT PPC andPCle e Multi threaded compilation e Hardware Co Simulation HWCoSim e Mixed VHDL Verilog e Memory Editor for vi
178. th the test plusarg or value plusarg system function of a Verilog design file the test or design behavior change associated with the system function is run where lt string gt is any string For example testplusarg HELLO ifa Verilog file uses test plusargs HE the function returns true string value is an appropriate string for the Verilog format specifiers It provides a value to the variable in the value plusargs system function call For example testplusarg FINISH 10000 if a Verilog file uses value plusargs FINISH d stop clock and when Verilog format specifier d matches 10000 and stop clock gets values 10000 the function returns true The same string or string and value need to be set both in this command line switch and in the system function for the action specified in the Verilog file such as a value display to occur 50 Send Feedback www xilinx com UG660 v14 3 October 16 2012 ISim User Guide XILINX ISim Executable Command Table 3 6 ISim Command Options Cont d Option Description transport int delays Use transport model for interconnect delays No pulse rejection on interconnect delays vcdfile vcd file Verilog only option Specifies the VCD output file for Verilog projects The default filename is dump vcd vcdunit unit Verilog only option Specifies the VCD output time unit Unit values are fs ps ns us ms and sec The default is ps
179. tically Measuring Time with Markers When the floating ruler is displayed you can view the time measurement between the floating ruler time base at the selected marker and the main cursor and markers in the waveform 1 Display the floating ruler using a selected marker as the time base 2 Add additional markers 3 Move markers to a location in the waveform The marker label above the floating ruler shows the time intervals between the selected marker and each of the new markers The time base can be switched quickly from one marker to another by clicking and thus selecting another marker You can also use a combination of cursors and markers for measuring time To do so use the secondary cursor as the time base and the floating ruler displays the time measurement of the markers and main cursor against the secondary cursor Using Go To Time The Go To Time function lets you jump the main cursor to a particular time in the wave configuration Going To a User Specified Time With a wave configuration open 1 Select Edit Go To The Go To Time dialog box opens in the Wave window below the wave configuration 2 Typethe time and time unit to which to jump the cursor or select a time time unit from the drop down list if available 3 Press Enter 70 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Printing Wave Configurations Going to Time O or Latest Time With a wav
180. time while simulation is running with the time displayed directly above the cursor See Cursors in Chapter 4 e Secondary Cursor The secondary cursor is a dotted line used with the main cursor to identify a time range The time range can be used with zoom and print to focus on the area ISim User Guide www xilinx com 19 UG660 v14 3 October 16 2012 Send Feedback 20 Chapter 2 Using the ISim GUI XILINX Markers A marker is used to mark a particular time for future reference A marker is a vertical line intersecting the waveform A marker lets you display the signal value where the marker intersects the waveform The time of the marker displays at the top of the line In addition a series of markers can be used to jump the cursor forward or back for quick analysis of value change See Markers in Chapter 4 Adding Markers and Displaying Waveform Values With Markers Hollow Filled in Circle When placing or moving cursors and markers you can use the Snap to Transition button to assist with placing the cursor marker more precisely on a signal transition e When placing or moving a cursor or marker the mouse displays a hollow circle e When hovering over the signal transition the mouse displays a filled in circle e when hovering over a transition of a signal Dividers A divider is a visual separator of signals in the wave configuration Groups A group is a virtual collection to which you can add signals and buses in the
181. tp www xilinx com tools isim htm About ModelSim XE ModelSim XE stands for ModelSim Xilinx Edition which is an OEM product from Mentor Graphics ModelSim XE provides a complete HDL simulation environment that lets you verify the functional and timing models of your design and your HDL source code ModelSim XE was discontinued in the Xilinx ISE Design Suite 12 4 tool release See the Product Discontinuance Notice at http www xilinx com support documentation customer notices xcn10028 pdf ModelSim XE was shipped with each major Xilinx ISE Design Suite release through version 12 3 There were two versions e ModelSim XE Starter a free version that can be downloaded from the Xilinx website A starter license is required for using this product e ModelSim XE Full an OEM version from Mentor Graphics based on their PE product line ISim User Guide www xilinx com 147 UG660 v14 3 October 16 2012 Send Feedback Appendix C Migrating from ModelSim XE to ISim About ISim XILINX ISim is a Xilinx simulation product that provides a complete full featured HDL simulator integrated within the ISE tool and the PlanAhead tool Embedded Development Kit EDK and System Generator ISim is available with all major Xilinx tools releases and comes in two versions ISim Lite A limited version of the ISE Simulator In this version when your design plus test bench exceeds 50 000 lines of HDL code the simulator begins t
182. u encounter issues you must debug the design to identify the root cause and the resolution of the issues ISim provides a variety of ways to debug the design To debug your design examine the error messages and log files Examining Error Messages First look at the error messages to see if there are any errors in the design Error messages appear in the ISE tool Console GUI mode and the log files discussed in the next section Look for messages with one of the following prefixes HDL Compiler Indicates an error during the parsing or static elaboration step If an error occurs during parsing and elaboration and this step was not run successfully the problem can be an HDL compiler issue Type fuse v 1 to dump information that might help identify the problem A fuse 1og file that contains a list of error messages and errors appears in the ISE tool Console in ISE Integration Mode Simulator Indicates an error during executable code generation or simulation See Step 3 Simulating the Design page 6 Use the file name and line number in the message to locate the issue Examining Log Files Examining the available log files can provide helpful clues about design errors The following log files are available ISim User Guide UG660 v14 3 October 16 2012 fuse log Log file containing output produced by the fuse command during the parsing and elaboration step isim log Log file containing output produced by simulation executa
183. urce files file name isthe name of the source file in which there is a breakpoint line number is the line number in the source file of the breakpoint remove file name Deletes a breakpoint at the 1ine number in the line number file name e The file name is the name of the HDL source file that you are simulating and where you want to remove a breakpoint e The line number is the number of the line of HDL code where the breakpoint has been set bp Command Examples Set a breakpoint at line 2 for the file statmach vhd bp add statmach vhd 2 List all Breakpoints List all breakpoints in all files in your simulation and give them a unique index number bp list Delete all breakpoints in your simulation bp clear To delete a breakpoint by index number 1 First use the bp list command to get the breakpoint indexes bp list The simulator returns the following 1 C examples watchvhd stopwatch tb vhd 46 2 C examples watchvhd stopwatch tb vhd 55 2 Then delete the breakpoint at line number 46 in stopwatch tb vhd bp del 1 Delete a breakpoint at line 2 in statmach vhd bp remove statmach vhd 2 ISim User Guide www xilinx com 105 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX describe The describe command displays information about the given HDL data or block object describe Command Syntax describe object name
184. userunit command isim get userunit Command Syntax isim get userunit where no options are available isim get userunit Example isim get userunit Returns 1 ps ltrace The isim 1trace command lets you turn line tracing on or off When line tracing is turned on you can do a line by line analysis for debugging Executed HDL lines print to the screen with the following information simulation time filepath filename and line number Note isim ltrace on can slow the simulation isim Itrace Command Syntax isim ltrace on off isim Itrace Command Options The isim ltrace command options are on off The default is off isim Itrace Command Example To see which line is currently executing www xilinx com 111 UG660 v14 3 October 16 2012 Send Feedback Chapter 9 ISim Tcl Commands XILINX isim ltrace on run The output lists the simulation time filename line number as follows 1005 ns C Data ISE Projects freqm watchver stopwatch tb v 261005 ns C Data ISE Projects freqm watchver stopwatch tb v 271005 ns 3 C Data ISE Projects freqm watchver statmach v 631005 ns 3 C Data ISE Projects freqm watchver statmach v 64 isim ptrace The isim ptrace command lets you turn process tracing on or off When turned on the command also displays the name of the currently executing VHDL or Verilog process in the Simulation Console panel This is useful if the simulator is stuck in an infinite loop in wh
185. vigate back and forth The vhpcomp command syntax is vhpcomp f cmd file h i include path intstyle ise xflow silent default initfile sim init file L lib search lib lib path prj prj file prjl rangecheck v verbose value version vhdl files work work library library path lt filenames gt The options descriptions are in the fuse vhpcomp and vlogcomp Command Options section vhpcomp Command Example vhpcomp using two files vhpcomp suba vhd subb vhd Running fuse The fuse command e Performs static elaboration of a design in terms of parsed nodes e Generates object code for each unique module instance e Links the generated object codes with the simulation engine library to create a simulation executable The fuse command generates object code and data files for each design unit comprising the design and puts them in the isim lt simulation_executable gt sim directory Note Do not remove the isim simulation executable sim directory otherwise the design cannot be simulated 38 www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX Parsing Design Files fuse Command Syntax Click the link to go to the command option descriptions Note n your PDF reader turn on Previous View and Next View Buttons to navigate back and forth The fuse command syntax is Fuse d mac
186. w xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview What s This activates tooltips After clicking this button you can hover over a menu item or button and get a brief description of its functionality Keyboard Shortcuts Table 2 3 lists the ISim keyboard shortcuts Table 2 3 Keyboard Shortcuts Shortcut Menu Command F1 Help Topics Help menu F3 Find Next Edit menu F5 Run All View menu F6 Zoom Full View View menu F7 Zoom Out View menu F8 Zoom In View menu F11 Step Delete Delete Edit menu Ctrl N New File menu Ctrl O Open File menu Ctrl S Save File menu Ctrl P Print File menu Ctrl Z Undo Edit menu Ctrl Y Redo Edit menu Ctrl X Cut Edit menu Ctrl C Copy Edit menu Ctrl V Paste Edit menu Ctrl F Find Edit menu Ctrl G Go To Edit menu Ctrl A Select All Edit menu Ctrl W Add To Wave Configuration Ctrl F4 Close Window menu Ctrl Tab Next Window menu Ctrl Shift Tab Previous Window menu Ctrl Home Go To Time 0 Ctrl End Go To Latest Time Ctrl Shift F5 Restart Ctrl Mouse Wheel Zooms in and out Shift Mouse Wheel Zooms left and right ISim User Guide www xilinx com 13 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI XILINX Table 2 3 Keyboard Shortcuts Cont d Shortcut Menu Command Mouse Wheel Scrolls
187. wave a configuration as a means of organizing a set of related signals A group displays the m group icon and group name The group itself displays no waveform data but can be expanded to show its contents or collapsed to hide them See Adding a Group in Chapter 4 Virtual Buses A virtual bus is a grouping to which logic scalars and arrays can be added A virtual Xi bus displays the icon and virtual bus name The virtual bus displays a bus waveform which is comprised of the signal waveforms in the vertical order that they appear under the virtual bus flattened to a one dimensional array See Adding Virtual Buses in Chapter 4 Wave Window Toolbar Buttons Table 2 8 shows and describes the wave window toolbar buttons Table 2 8 Wave Window Toolbar Buttons Button Description 2 Zoom Out decreases the size of the viewed objects C P Zoom In increases the size of the viewed objects B Zoom to Full View zooms out to display the entire view in the active window Zoom to Cursors displays the waveforms such that the two cursors are at the Pp left and right edge of the display If the secondary is off the command centers the display around the main cursor without changing the magnification level Q Go To Time 0 moves the cursor and focus to O time www xilinx com ISim User Guide Send Feedback UG660 v14 3 October 16 2012 XILINX ISim GUI Overview Table 2 8 Wave Window Toolbar Buttons Cont
188. wire taking care to supply a space between the final character and the closing curly brace Note Verilog allows any identifier to be escaped On the ISim command line do not escape Verilog identifiers that are not required to be escaped For example to add wire w to the Wave window ISim would not accept wave add w as a valid command Instead the command must be written as wave add w or optionally wave add w If the escaped identifier contains a curly brace then the technique of surrounding the identifier with curly braces does not work because Tcl interprets curly braces as special characters even within curly braces Instead you must use the technique demonstrated in VHDL Extended Identifiers below VHDL Extended Identifiers VHDL extended identifiers contain backslashes which are special characters to Tcl Because Tcl interprets a backslash next to a close curly brace as being a close curly brace character VHDL extended identifiers cannot be written with curly braces Instead the curly braces must be absent and each special character to Tcl must be prefixed with a backslash For example to add the signal my sig to the Wave window you must write the command as wave add my sig Both the backslashes that are part of the extended identifier and the space inside the identifier are prefixed with a backslash Aliasing Simulation Commands 102 You can set a variable to represent a simulation command using a Tc
189. y lightgray The RGB values for these colors are defined in the RGB table name custom name Names the wave object with a custom name r Adds objects associated with each block to the waveform down to the lowest level of hierarchy Without r the first level objects of the block s entered as object name are added object name Specifies HDL object whose simulation output is to be logged to the waveform database The object name can also be a hierarchical instance name for example b UUT of a block in which case all HDL objects within the given block are logged This option does not support the use of wild card characters To add all HDL objects inside instance of a block use the block instance name wave add Command Examples The wave add command can be used as follows Add the signals associated with object UUT to the current wave configuration wave add tb UUT Add all top level signals wave add Add all signals in the design in color whose RGB value is 00FF10 wave add r color 00FF10 Add specific signals with radix hex and in color red wave add tb clk tb UUT data radix hex color red 134 Send Feedback www xilinx com ISim User Guide UG660 v14 3 October 16 2012 XILINX Tcl Commands divider add The divider add command adds a new divider divider add Command Syntax divider add into ID color lt color gt Where
190. you address the linked errors sequentially to correct the issues and then recompile using the Re launch button to verify the fix ISim User Guide www xilinx com 29 UG660 v14 3 October 16 2012 Send Feedback Chapter 2 Using the ISim GUI g XILINX Applying Stimulus Use the Force Selected Signal dialog box to enter parameters to force a VHDL signal Verilog wire or a Verilog reg to a constant value This dialog box opens when you select a signal then right click the Force Constant option After you assign a new constant force those values override the assignments made from within HDL code or any previously applied constant or clock force Click Apply to apply all changes Figure 2 3 shows the Force Selected Signal dialog box Enter parameters below to force the signal to a constant value Assignments made from within HDL code or any previously applied constant or clock force will be overridden Signal Name drp_demo drp_start Value Radix Binary Force to Value Starting at Time Offset 0 Cancel after Time Offset Figure 2 3 Force Selected Signal Dialog Box The Force Selected Signal options are e Signal Name Displays the default signal name The default signal name is the full path name of the selected item You can change the signal name in the edit box When you enter an invalid signal name in the edit box the edit box turns red e Value Radix Displays the current radix setting of the selected
191. you are using a Xilinx Parallel Cable IV follow steps 2a through 2d a Connectthe DB25 Plug Connector on the Xilinx Parallel Cable IV to the IEEE 1284 compliant PC Parallel Printer Port Connector b Usingthenarrow 14 pin 6 High Performance Ribbon cable connect the pod end of the Xilinx Parallel Cable IV to the FPGA JTAG header on the board c Connect the attached Power Jack cable to the Keyboard Mouse connector on the PC d Ifnecessary connect the male end of the Keyboard Mouse cable to the associated female connector on the Xilinx Power Jack cable splitter cable 3 Ifyouare using a Xilinx Platform Cable USB follow steps 3a and 3b a Connectthe Xilinx Platform Cable USB to a USB port on the PC b Usingthenarrow 14 pin 6 High Performance Ribbon cable connect the pod end of the Xilinx Platform Cable USB to the FPGA JTAG header on the board 4 Ifyour board supports Point to Point P2P Ethernet co simulation and you want to use Ethernet P2P for faster co simulation then in addition to the above steps use an Ethernet cable to connect the Ethernet port of your PC to the Ethernet port of your board If your computer has more than one Ethernet card port note the MAC address of the port that you connected to the board Specify that address to the ISim engine using the ISim Tcl command hwcosim set ethernetInterfaceID 5 Power the board on and check to ensure the LED on the cable is green 6 Install the Xilinx cabl
192. ype show driver fifocount the following information displays for the signal ifocount Driver for fifocount gt fifoctlr cc v2 v 221 The number 221 at the end of the lines refers to the code line in the source file show load If you are located at the top level of the hierarchy in a design called ifo count and type show load fifocount the following information displays for the signal fi focount Load for fifocount gt Signal Hex 0 Block Signal Hex 1 Block Signal Hex 2 Block Signal Hex 3 Block show scope fifo count Lsbled fifo count Lsbled fifo count Lsbled fifo count Lsbled If you are located at the top level of the hierarchy in a design called ifo count and type show scope the following information displays Block tb cc func show value Signal Query a value to a signal called c1k show value clk Query a value to a 4 bit bus called busx show value busx Query the value of addr show value addr e Displays 0111010101011101 show value addr radix hex e Displays 755D show value addr radix dec e Displays 30045 show value Object The following examples refer to a standard logic vector called sigx that is declared as follows signal sigx std logic vector 0 to 5 Query bit 0 of sig show value sigx 0 Query slice 1 to 2 of sigx show value sigx 1 2 Query all of sigx show value sigx ISim User Guide www xilinx com U

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