Home

Xilinx Partial Reconfiguration User Guide

1. Flow Placement Routing Standard No limitations beyond device No limitations beyond device restrictions restrictions Partitions Imported logic is placed first Imported logic is routed first Implemented logic is placed Implemented logic is routed second second No Area Group requirements Partial Only reconfigurable logic can Routing resources that extend Reconfiguration be placed in RP Area Groups outside the RP Area Groups are unless explicitly forced witha not available for reconfigurable LOC constraint logic Routing restrictions considered Imported logic is routed first during placement phase Implemented logic is routed second Due to these flow differences designs which implement successfully in the standard or partition flows might not always implement or achieve the same timing or density metrics in the Partial Reconfiguration flow The amount of degradation varies from design to design www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 4 PlanAhead Support This chapter describes the Xilinx Plan Ahead software support for Partial Reconfiguration and includes e About PlanAhead Support e Creating a Partial Reconfiguration Project e Setting the Project as a PR Project e Opening the Netlist Design e Defining the Reconfigurable Instances e Adding Reconfigurable Modules to the Project
2. Partial Not Specified 4 4 Default setting The report for the partial bit file indicates that it is a partial bit file and which Partition and Reconfigurable Module to which it is associated Summary of Bitgen Options 4 4 ActiveReconfig Yes Partial reconfig_red Creating bit stream for Partition top reconfig_red Reconfigurable Module red_fast Creating bit map Saving bit stream in fff_reconfig_red_red_fast_partial bit www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX pr_verify pr_verify For Partial Reconfigurable designs to work in hardware static logic s placement and routing must be consistent between all configurations In addition proxy logic must be placed in the same locations and clock spine routing must match The pr_verify utility is used to compare routed ncd files from two or more configurations created for a Partial Reconfiguration design to validate that all imported resources match These resources include e Global Clock Spines Each global clock must have clock spines routed within the same clock regions in all configurations e Regional Clock Spines For architectures except for Virtex 5 each regional clock m
3. Partial Reconfiguration User Guide www xilinx com 55 UG702 v 12 1 May 3 2010 XILINX Chapter 3 Software Tools Flow pr_verify Log File The sample command line above would output this pr_verify Log File Command Line build xfndry M 53d rtf bin lin unwrapped pr verify BlankConfig BlankConfig ncd FastConfig FastConfig ncd FSFConfig FSFConfig ncd SlowConfig SlowConfig ncd Loading Loading Loading Loading BlankConfig BlankConfig ncd FastConfig FastConfig ncd FSFConfig FSFConfig ncd SlowConfig SlowConfig ncd Wed Sep 16 14 53 16 2009 Wed Sep 16 14 35 32 2009 Wed Sep 16 14 47 54 2009 Wed Sep 16 14 40 58 2009 Analyzing Designs BlankConfig BlankConfig ncd FastConfig FastConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 33 Number of matched global clock nets 4 Number of matched Reconfigurable Partitions 0 SUCCESS Analyzing Designs FastConfig FastConfig ncd FSFConfig FSFConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 399 Number of matched global clock nets ew Number of matched Reconfigurable Partitions 2 SUCCESS Analyzing Designs FSFConfig FSFConfig ncd BlankConfig BlankConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 2393 Number of matched global clock nets 4 Number of matched Reconfigurable Partitions 0 SUCCESS Analyzing Designs FSFConf
4. Updating Netlist Files If there are changes to the source files the new netlists must be brought into PlanAhead For static netlists use the Project Manager or open the Sources pane of the Netlist Design Select the netlist to be updated right click and select Update File to bring in a new top level netlist To modify a Reconfigurable Module netlist select the Reconfigurable Partition and choose the Update Reconfigurable Module option This will allow you to reload a new version of the active RM Both of these solutions assume that the interfaces between static and reconfigurable logic has not changed If the port lists have changed in any way it is recommended to create a new project with the new netlists Adding Black Box Modules You can also define Black box modules 1 Use the same Add Reconfigurable Module command but select the black box option No netlist is associated with this module O Add Reconfigurable Module x Reconfigurable Module Name Enter a name for the new reconfigurable module For instance reconfig blue de Reconfigurable Module Name blue bb Netlist already available For this Reconfigurable Module v Add this Reconfigurable module as a black box without a netlist lt Back Cancel Figure 4 11 Adding a Black Box as a Reconfigurable Module The RMs are added to the Reconfigurable Modules folder under the RP in the netlist view A check mark indicates the active Reconfigurable Mod
5. g XILINX Example Project File Structure ccee eee 28 Synthesis ocd nies oa o a o alia RMT aa a Ea e pl n i ol ip nul 29 Config ratians ceia a n dea ee ee et 31 Constralnts 222 See eo phe ana eee ede he ee eee 32 Area Group Constraints esre ciesa eiee ae 32 Partition PINS esset base ec aaa an gates wane sacs it an eaten vad ached ne Rus 35 Timing Constraints for the ICAP ceea 38 Extracting Partition Pin information 38 Constraints Editor sira cm i Ses eo biel ie ws a ek ea nw ee Rew ae 39 RM Constraints in PlanAhead 0 0 0 0 cece eee nn 40 PlanAhead UCF Recommendations cece eee eee e 40 PlanAhead UCF Known Issues 0 0 e 40 Partitions and Import 11235 civdanvig 9C OEC p en e e Pea eta 41 The Role of PXML EFiles pepsi ae otet e ee e a e Oe EEE E E Ea 41 First Configuration PXML File ee 42 Second Configuration PXML File lt eee 42 Third Configuration PXML File ee 43 Implementation ied Pee et de o EE ORE a o a E Rd EORR e ed 43 Debugging Placement and Routing Problems eese 43 Generating Bit Files eo REOR HA ADR RERO E onn 45 Report Files n s dees bd ea kde eau ER bed ad YAN Xd aa REA Ra ete a RU adc 46 Negdbuild Report 2 22 he tme ago bre pa Cera Op a kd e edid 47 Map Report sve pr Uer aaa Re a Pa a a HI Ee bEda dee uie ed 47 PAR RED OP bi cad eo UR dries cea a Soak ta ieee pa a 49 Tree NepOEFt proe estende ee Seb neepilata Rd coo oe ette ds 49 Bitpen Report P
6. AREA GROUP pblock reconfig red RANGE SLICE X20Y76 SLICE X25Y79 INST reconfig blue AREA GROUP pblock reconfig blue AREA GROUP pblock reconfig blue RANGE SLICE X28Y64 SLICE X33Y67 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Constraints INST reconfig green AREA GROUP pblock reconfig green AREA GROUP pblock reconfig green RANGE SLICE X20Y50 SLICE X25Y53 Most logic types can be in a Reconfigurable Partition such as Slices Block RAM DSP48 IOB and MGT The global clocking logic including clock modifying logic like the DCM PLL or PMCD must be in a static module For more information on Reconfigurable Partition regulations see Chapter 7 Design Considerations The Slice range must be on a CLB boundary not split a CLB Following this rule ensures that any AREA GROUP RANGE constraint fully encapsulates CLBs for Virtex9 5 devices AREA GROUP Slice range horizontal coordinates minX is always EVEN AREA GROUP Slice range horizontal coordinates maxX is always ODD This rule ensures that a Reconfigurable Partition s RANGE falls on CLB boundaries in a Virtex 5 device It does not ensure that any reconfigurable frame rules are followed Be sure to follow the frame rules described in Chapter 7 Design Considerations The AREA GROUP RANGE for block RAM has coordinates minX minY and maxX maxY which can be
7. Compatible Designs for Migration Any EA design that targets Virtex 4 or newer can be migrated to the ISE 12 solution Users will need to create anew PlanAhead project in ISE 12 To create this project simply follow the instructions found in Chapter 4 PlanAhead Support Bus Macro instantiations no longer required Bus Macros BMs are no longer needed Partition Pins are automatically managed and this automation replaces some of the aspects of Bus Macro functionality Both Synchronous and Asynchronous Bus Macros were available in the EA solution To follow good hierarchical design practices in registering boundaries and to decouple the reconfigurable logic you can add registers in HDL to replace the functionality of the output registers delivered within Synchronous Bus Macros It is very important to register the partition boundaries and to use enables with these registers During reconfiguration the activity in these regions is indeterminate and could lead to design corruption if the output of the reconfiguring logic is used Therefore you should register boundaries with enables to disable the reconfigurable region during reconfiguration Partial Reconfiguration User Guide www xilinx com 121 UG702 v 12 1 May 3 2010 Chapter 122 XILINX PR Specific Environment Variables Deprecated The EA solution required several different environment variables to be set These are no longer required for the ISE 12 solution
8. Configurations in the order they were promoted In Configuration FSF shown in Figure 4 30 Static reconfig_green and reconfig_red are imported from FFFand RM reconfig blue is imported from SSS as it was not implemented in the FFF Configuration EJA Static Logic reconfig blue 54 reconfig areen 54 reconfig red 4 555 4 Be Static Logic reconfig blue reconfig green reconfig red FSF 4 Je Static Logic 54 reconfig blue v reconfig areen e reconfig red Be BB 4 Ne Sources Timing Co blue fast green fast red fast blue slow green slow red slow blue fast green slow red fast iil Physical Ce i Promoted Promoted Promoted Promoted Promoted Promoted Imported Promoted Promoted Promoted Not started Import Import Import Import Not started QO Netlist Figure 4 30 Multiple Configurations Promoted Configurations cannot be promoted if the Static Logic and all the RMs have been imported from other Configurations In this example there is no need to promote the FSF Configuration since it is built entirely from pieces from FFF and SSS www xilinx com 77 Chapter 4 PlanAhead Support g XILINX Because RMs can be implemented or imported experimentation can be done on any individual RM This flexibility can help find the optimal Configurations to promote This is done through the Configuration Module State Properties shown in Figure 4 31 Im
9. Partial Reconfiguration User Guide www xilinx com 63 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX Undefined Modules Found x While importing this netlist 3 undefined instances were Found and converted to black A boxes Make sure you have loaded all intended module definitions before proceeding Black boxes can be populated later by using the Update Netlist operation Module names rm_green rm_blue rm_red Figure 4 5 This Warning is Expected In the example design shown in Figure 4 4 the three black box instances reconfig_blue reconfig_green and reconfig_red have black box icons in the netlist pane because there are currently no netlists associated with them For a complete list of icons for the netlist pane see UG632 PlanAhead User Guide The Reconfigurable Module netlists that are linked to them are the Fast and Slow variations of blue green and red respectively Defining the Reconfigurable Instances You can define a Reconfigurable Partition by selecting a lower level instance and using the Set Partition dialog menu command 1 Select the Set Partition option as shown in Figure 4 6 H Nets 105 H Primitives 26 t E reconfig 3 Instance Properties Ctrl E E reconfig pa Export Statistics H a static D TET CENT 3 a static D PEE aid static II ri Assign gf Unassign E Draw Pbloc
10. Select All Clear All con Figure 4 17 Run DRC Dialog Box for Partial Reconfiguration The DRC Results view displays all warnings and errors Selecting a violation displays the details in the Violation Properties view as shown in Figure 4 18 Partial Reconfiguration User Guide www xilinx com 71 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX Violation Properties Od x e gt Pale 5 p PRSC 3 Reconfigurable instance reconfiqd qreen module qgreen slow is not implemented by any configuration Please define a configuration that contains this module to ensure that the module will be implemented Figure 4 18 Results of a DRC check Objects that violate certain PR DRCs can be located by selecting the links in the Violation Properties view Creating Configurations Once all modules have been defined you can define and implement Configurations The first Configuration has been automatically generated for you Click on the Design Runs tab at the bottom of the PlanAhead GUI to select config_1 The Partitions tab at the bottom of the Implementation Run Properties dialog box shows the Reconfigurable Modules that have been chosen for this Configuration see Figure 4 19 The first RM for each Reconfigurable Partition has been selected but these can be modified if needed The name of the Configuration found in the General tab can also
11. Sl SSize 0 lt S1 SSize pr 0 and busmacro enable Sl SSize 1 lt S1 SSize pr 1 and busmacro enable Sl wait lt S1 wait pr and busmacro enable Redefine Bus Macros The BMs can be replaced with a newly created netlist that matches the BMs old name This method is recommended for Synchronous Bus Macros as they can be used directly for logic decoupling needs The task of re validating the PR solution is greatly simplified as the logic design will remain equivalent Create a netlist with the same interface as a BM from HDL with the internal assignments defined as desired During synthesis ensure that IO buffer insertion is disabled for example in XST the option is named Add I O Buffers iobuf Note These logic modules will exist in static logic regardless of whether or not the replaced BM was an input or an output of a Reconfigurable Partition Example VHDL Bus Macro Redefined for busmacro_xc5v_async library IEEE use IEEE STD LOGIC 1164 ALL entity busmacro xcb5v async is Port inputO in STD LOGIC inputl in STD_LOGIC input2 in STD_LOGIC input3 in STD_LOGIC outputO0 out STD LOGIC outputl out STD LOGIC output2 out STD LOGIC output3 out STD LOGIC end busmacro xcb5v async architecture Behavioral of busmacro xcb5v async is begin output0 lt input0 outputil lt input1 output lt input2 output3 lt input3 end Behavioral
12. e Running Partial Reconfiguration Design Rule Checks e Creating Configurations e Controlling Configurations e Verifying Configurations e Generating Bit Files e PlanAhead Project Directory Structure About PlanAhead Support This section describes the design steps involved when using the PlanAhead software for Partial Reconfiguration designs This flow description starts post synthesis and assumes that the design has been coded in RTL and synthesized according to the instructions in Chapter 3 Software Tools Flow This Guide assumes basic knowledge of the PlanAhead software If you are unfamiliar with PlanAhead see UG632 PlanAhead User Guide and the PlanAhead Quick Front to Back Tutorial which are both shipped with the PlanAhead software Partial Reconfiguration User Guide www xilinx com 59 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX Creating a Partial Reconfiguration Project 60 To create a Partial Recofiguration project 1 Launch the New Project Wizard and after specifying a project name and location Import a synthesized EDIF or NGC netlist PR projects cannot start at the RTL level in the PlanAhead software Figure 4 1 shows the New Project Wizard B New Project xj Design Source Specify the type of sources for your design You can start with RTL or a synthesized EDIF de Specify RTL Sources You will be able to run RTL analysis synthesis post s
13. e JTAG A good interface for quick testing or debug Can be driven via iMPACT or ChipScope Analyzer using a Xilinx configuration cable that supports JTAG e Slave SelectMAP or Slave Serial Good choice to perform full configuration and Partial Reconfiguration over the same interface Master modes are not directly supported due to IPROG housecleaning that will clear the configuration memory 94 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 g XILINX Downloading a Full Bit File Downloading a Full Bit File The FPGA device in a digital system is configured after power on reset by downloading a full bit file either directly from a PROM or from a general purpose memory space by a microprocessor A full bit file contains all the information necessary to reset the FPGA device configure it with a complete design and verify that the bit file is not corrupt Figure 6 1 illustrates this process Partial Configuration Bit File Check Sum Config Data FPGA ee Start Vcc Power on Download Full DONE Vcc Rise Stable Reset Bit File Asserted X12031 Figure 6 1 Configuring With a Full Bit File After the initial configuration is completed and verified the FPGA device enters user mode and the downloaded design begins functioning If a corrupt bit file is detected the DONE signal is never asserted the FPGA device never enters user mode and the corrupt design never starts functioning Downloading
14. 28 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Synthesis Synthesis Color2 name of the overall project Docs readme txt Source HDL source files Static collection of all HDL for static logic Top top level static module DVI_IF lower level static module TEGAN dec 56H VGA Qo o x ox s g T red fast Reconfigurable Module for Red red slow blue fast Reconfigurable Module for Blue blue slow green fast Reconfigurable Module for Green green slow UCF constraint files Synth synthesized netlists static top DVI IF IIC init and VGA red fast red slow blue fast blue slow green fast green slow Implementation implementation results from scripted runs FastConfig contains implementation results and bit files SlowConfig ESECOonf1g s 2 a s T BlankConfig contains black boxes for the three colors PlanAhead implementation results from PlanAhead runs FFF contains implementation results and bit files Boo cde Ue cde le ll oe OP ESE a dw x scc e 7 BB contains black boxes for the three colors Tools Tcl scripts or any other user scripts Each Reconfigurable Module is synthesized independently from the others in a bottom up fashion This can be done through the use of independent projects either thr
15. Im Tcl Console CA Compilation Log Compilation Messages 3 Reports Design Runs Export to Spreadsheet Figure 4 34 Creating Bit Files This action generates a full Configuration bit file as well as partial bit files for each RM in a selected Configuration In this example design for the FFF Configuration the bit files generated are e fff bit e fff reconfig blue blue fast partial bit e fff reconfig red red fast partial bit e fff reconfig green green fast partial bit You can select multiple Configurations at once to create all the full and partial bit files for an entire project The full and partial bit files are placed in the same Configuration specific results directories For more information see Controlling Configurations 80 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX PlanAhead Project Directory Structure PlanAhead Project Directory Structure To manage the files Configurations and implementations Plan Ahead manages and stores all design data in a simple and structured fashion as shown in Figure 4 34 Folders El C3 Color2 Ce Docs O Implementation O PlanAhead O PlanAhead data O constrs_1 O runs El O sources 1 pr modules El O reconfig blue blue bb blue fast O blue slow O reconfig green O reconfig_red ie O wt O Plan4head promot
16. Please make sure to unset all environment variables that were set specifically for the EA solution MODE Constraint Deprecated With the EA solution the tools had to be explicitly told which area groups were reconfigurable This was handled by specific constraints added to the UCF MODE RECONFIG These constraints are no longer required This functionality has been replaced by using the Set Reconfigurable option in PlanAhead which in turn adds the Reconfigurable TRUE information to the xpartition pxml NGDBuild modular switch deprecated It is no longer necessary to specifically tell NGDBuild that you are running a PR design This concept is now handled by an xpartition pxml file See the following section for more details Partition Information is Stored in the xpartition pxml File In the ISE 12 solution a PXML file manages partition specific information This file is named xpartition pxml and this name cannot be changed This file is ASCII XML and is created for each implementation Most of the PR specific information everything save for Area Group Range constraints is contained in the xpartition pxml file The tools will automatically check for the xpartition pxml file Any design with reconfigurable partitions requires that the xpartition pxml file be present and have at least one partition defined If it is not found the design is treated as a flat design The xpartition pxml file is generated by PlanAhead and should
17. UG702 v 12 1 May 3 2010 38 Chapter 3 Software Tools Flow g XILINX This correctly takes the Partition Pin delay into account A global OFFSET OUT that could apply OFFSET OUT 5 ns AFTER clk Optionally a Partition Pin can be physically locked to a site within the area group range of the RP This is not required as they are placed automatically by the PR software but can be done to gain an additional level of control in the implementation results This methodology should be used as a last resort and only after automatic placement with timing constraints has been explored The following UCF command physically locks the Partition Pin to a site PIN RP A 1 LOC SLICE X4Y4 Timing Constraints for the ICAP If the Internal Configuration Access Port ICAP is used as the configuration port for partially reconfiguring the FPGA timing constraints can be very useful to understand the potential performance of this interface It is important to understand that the paths to the ICAP and from the ICAP are not covered by PERIOD constraints The ICAP inputs and outputs are not considered synchronous by TRCE This is also true for the BUSY CE and WRITE signals This means that the inputs to and the outputs from the ICAP must be constrained using the exception constraint NET MAXDELAY Using NET MAXDELAY constraints the syntax looks like this NET to icap MAXDELAY 15 ns NE
18. of relying on a predefined library of partial bit files O Partially Reconfigurable Co processor Packet Processor PBF Partial Bit Flle X12005 Figure 2 4 Dynamically Reconfigurable Packet Processor 22 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Asymmetric Key Encryption Asymmetric Key Encryption There are some new applications that are not possible without Partial Reconfiguration A very secure method for protecting the FPGA configuration file can be architected when Partial Reconfiguration and asymmetric cryptography are combined See Public key cryptography for asymmetric cryptography details In Figure 2 5 all of the functions in the blue box can be implemented within the physical package of the FPGA The cleartext information and the private key never leave a well protected container cleartext Key Co generation A ciphertext Private Key cleartext 4 X12022 Figure 2 5 Asymmetric Key Encryption In a real implementation of this design the initial bit file is an unencrypted design that does not contain any proprietary information The initial design only contains the algorithm to generate the public private key pair and the interface connections between the host FPGA and ICAP After the initial bit file is loaded the FPGA device generates the public private key pair The public key is sent to the host which uses it to encrypt a partial b
19. red VGA in7 PROXY red VGA in7 SLICE X25Y76 D5 net fanout 1 0 164 red VGA out7 SLICE X25Y76 D Tilo 0 080 red VGA out7 PROXY red VGA out7 PROXY red VGA out7 OLOGIC X2Y39 D1 net fanout 1 24192 VGA R 7 OLOGIC X2Y39 CLK Todck 0 297 DVI LCD DATA11 c Static DVI IF ODDR DVI DATA11 Total 3 387ns 0 783ns logic 2 604ns rte 23 1 logic 76 9 rte Figure 3 10 illustrates the path from FF to FF through partition pins Partial Reconfiguration User Guide www xilinx com 53 UG702 v 12 1 May 3 2010 54 Chapter 3 Software Tools Flow g XILINX Path Analyzed Partition pin red Partition pin red VGA_in7 partition red VGA_out7 VGA_in7_PROXY VGA_out7_PROXY static_VGA static_DVI_IF VGA_R_1 0 ODDR_DVI_DATA11 X12030 Figure 3 10 Path from FF to FF through Partition Pins Bitgen Report The Bitgen executable creates a report file for the full bit file in addition to each partial bit file The full bit file report lists all of the Reconfigurable Modules included in the full bit file and indicates that it is not a partial bit file with the ActiveReconfig No setting Partition top reconfig_red Reconfigurable Module red_fast Partition top reconfig_blue Reconfigurable Module blue_fast Partition top reconfig_green Reconfigurable Module green_fast Summary of Bitgen Options ActiveReconfig No 4 4
20. were implemented and which were preserved In this example the top level static Partition was preserved and the three Reconfigurable Partitions were implemented Partition Implementation Status Preserved Partitions Partition top Implemented Partitions Partition top reconfig_red Reconfigurable Module red_fast Attribute STATE set to IMPLEMENT Partition top reconfig_blue Reconfigurable Module blue_fast Attribute STATE set to IMPLEMENT Partition top reconfig_green Reconfigurable Module green_fast Attribute STATE set to IMPLEMENT Map Report Similar to the Ngdbuild report the MAP report mrp shows that all Partitions were implemented except the top level static Partition Section 9 Area Group and Partition Summary Preserved Partitions Partition top Implemented Partitions Partition top reconfig_red Reconfigurable Module red_fast Attribute STATE set to IMPLEMENT Partition top reconfig_blue Reconfigurable Module blue_fast Attribute STATE set to IMPLEMENT Partition top reconfig_green Reconfigurable Module green_fast Attribute STATE set to IMPLEMENT The Partition Resource Summary reports the number of resources used by each partition in the design It also reports which area group is associated with each Reconfigurable Partition Partial Reconfiguration User Guide www xilinx com 47 UG702 v 12 1 May
21. 3 2010 Chapter 3 Software Tools Flow g XILINX In the example below the AREA GROUP pblock_reconfig_red is associated with Reconfigurable Partition top reconfig_red Partition Resource Summary Resources are reported for each Partition followed in parenthesis by resources for the Partition plus all of its descendants Partition top State implement Slice Logic Utilization Number of Slice Registers 113 188 Number of Slice LUTs 148 274 Number used as logic 146 272 Number used as Memory 2 2 Slice Logic Distribution Number of occupied Slices 60 105 Number of LUT Flip Flop pairs used 157 288 Number with an unused Flip Flop 44 out of 157 28 Number with an unused LUT 7 out of 157 4 Number of fully used LUT FF pairs 106 out of L57 67 IO Utilization Number of bonded IOBs 26 26 Number of MMCM_ADV 1 1 Number of OLOGICE1 17 17 Number of STARTUP ib a t Partition top reconfig_blue Reconfigurable Module Blue_Fast Area Group AG reconfig blue State implement Slice Logic Utilization Number of Slice Registers 25 25 Number of Slice LUTs 42 42 Number used as logic 42 42 Slice Logic Distribution Number of occupied Slices 15 15 Number of LUT Flip Flop pairs used 44 44 Number with an unused Flip Flop 19 out of 44 43 Number with an unused LUT 1 out of 44 2 Number of fully used LUT FF pairs 24 out of 44 54 The section of the following MAP report provides percent
22. A Reconfigurable Frame is the smallest size physical region that can be reconfigured and it cannot contain logic from more than one Reconfigurable Partition If it were to contain logic from more than one Reconfigurable Partition it would be very easy to reconfigure the region with information from an incorrect Reconfigurable Module thus creating contention The software tools are designed to avoid that potentially dangerous occurrence Partition Pins are defined as the interface between static and reconfigurable logic No special logic or tags are required to accommodate this definition The software handles these points automatically In most cases a LUTI is inserted at this interface point to represent this node Since this LUT exists in the hierarchical level of the static logic it exists in the same logical and physical location for every Configuration Since the physical location itself is within the Reconfigurable Partition to which it connects reconfiguration accommodates connecting logic internal to the RM to this known interface point As noted in Constraints in Chapter 3 proxy logic can be constrained in the UCF The pr2ucf utility generates constraints for all the proxy logic from a Configuration that has been implemented Providing location constraints for proxy logic is not required This section also includes information for setting timing constraints to and from individual and grouped Partition Pins Controlled Routes C
23. A design can have multiple Reconfigurable Partitions You must run the Set Partition command for each RP in a design In this example design modules with the ast variants are loaded for each RP red green and blue Adding Reconfigurable Modules to the Project You can add additional Reconfigurable Modules for each Reconfigurable Partition using the Add Reconfigurable Module command as shown in Figure 4 10 Netlist A gsx H Nets 105 H Primitives 26 3 mmem_clocks clocks E3 gt Reconfigurabli Instance Properties Ctrl E blue fast pa Export Statistics I c5 Nets 109 n _ EH ES Primitives 99 Unplace CtrhU E reconfig green r gf Assign a reconfig red rm Unassign T static DVI dvi gt ached E static_DVI_IF dvi Draw Pbloc H 2 static_IIC_INIT ii New Pblock Set Partition Clear Partition Unset Reconfigurable Partition 4 Add Reconfigurable Module amp Update Reconfigurable Module Figure 4 10 Adding a Reconfigurable Module to a Reconfigurable Partition 66 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Adding Reconfigurable Modules to the Project Use this command to add all Reconfigurable Modules to all Reconfigurable Partitions in the design In the example design slow variants of red green and blue are added
24. Be It Pp GEM PE PE 126 8 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Preface About This Guide Partial Reconfiguration is the modification of an operating FPGA design by loading a par tial configuration file This Guide describes how to create and implement an FPGA design that is partially reconfigurable using a modular design technique called Partitioning Module instances in the design are translated into partial bit files which define the new hardware function Other techniques such as the differencing method described in XAPP290 are not covered in this Guide For supplemental material see Additional Resources page 10 This Guide Guide Contents Is intended for designers who want to create a Partially Reconfigurable FPGA design Assumes familiarity with FPGA design software particularly Xilinx ISE Design Suite and the PlanAhead software Has been written specifically for ISE Design Suite Release 12 1 This release supports Partial Reconfiguration for Virtex 4 Virtex 5 and Virtex 6 devices only This Guide contains the following Chapter 1 Introduction provides a general introduction to Partial Reconfiguration PR and the terminology that is specific to this feature Chapter 2 Common Applications describes typical applications that can be optimized with Partial Reconfiguration and the FPGA architectural features that enable Partial Reconfi
25. Blank 9 List of configurations in order of implementation finally build the list of all the configuration data This list will drive the implementation of all configurations in the order they are listed set ALL CFGS list CONFIG FastConfig CONFIG SlowConfig CONFIG FSFConfig SCONFIG BlankConfig set ALL CFGS list CONFIG BlankConfig ouk 8 Configuration information This section defines each Configuration including What RMs it contains Whether they are imported or implemented Where they are imported from The format is set CONFIG config name ConfigName config name Settings partition name State lt implement import gt gt ImportLocation directory to import from NetlistDir directory where RM netlist is located ModName name of netlist file The ImportLocation is required only if the State for that partition is set to import The NetlistDir differs from the ModName only if Synthesis is run outside of the Tcl scripts Partial Reconfiguration User Guide www xilinx com 87 UG702 v 12 1 May 3 2010 Chapter 5 Command Line Scripting g XILINX For the first Configuration all Partitions are implemented because there is no promoted image from which to import All Configurations are exported to X lt config_name gt after the implementation is complete and this can be used for the import location for other Configurations 9 A11 c
26. Ctrl M Unmark Ctrl Shift Figure 4 13 Changing the Active Reconfigurable Module Once all the Reconfigurable Module variants of all Reconfigurable Partitions have been defined in the PlanAhead software the next step is to define the physical layout of the design 68 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Adding Reconfigurable Modules to the Project Defining a PR Region Pblock rectangles must be created to define the reconfigurable regions of the device The Set Pblock Size command is used to draw a rectangle area in the Device view 1 Select the Pblock to be defined in the Physical Hierarchy pane to enable this command as shown in Figure 4 14 e PlanAhead Netlist Design C PRdesigns Color2 PlanAhead PlanAhead ppr PlanAhead 12 1 MRO EI x File Edit View Flow Tools Window Select Layout Help gocomBuoexdiXexseorb a ORG iu Ready Project Manager e Desig e Design Planner O Pla gi CUP Netlist B Lo Xx etlist Design 2 UE I Resource Estimation Nt Run prc E E Nets 105 H 5 Primitives 2 EE Run Noise Analysis v Report Timing ll Slack Histogram blue fast blue slow 3 Set up Chipscope 4 blue bb H 75 Nets E C Primitives 99 S E reconfig green rm areer Implement Reconfigurable Modules Q green fast green slow 4 green bb H 5 Nets 10 E E Primitives 9 E reconfig red rr S r5
27. Figure 4 32 Verifying Configurations 2 The dialog box prompts for two or more Configurations and you define the output file All Configurations must be verified to ensure success in hardware GB verify Configuration xj i This runs pr verify program to validate the implementation of two or more configurations Verification Output File C PRdesigns Color2 Plandhead Plandhead runs pr_verify log l verbose output Select Configurations to verify Figure 4 33 Selecting Configurations to Verify Partial Reconfiguration User Guide www xilinx com 79 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX The log file also appears in the workspace If there are no errors found during pr_verify the next step is to create bit files Generating Bit Files Once Configurations have been implemented satisfactorily and pr verify has validated all Configurations bit files can be generated In the popup menu in the Design Runs view select Run Bitgen Implementation Run Properties Ctrl E Delete Delete x Make lt Set Program Options ave As Strateg Edit Strategies Launch Runs Reset Runs x Open Implemented Design F t gt Create Multiple Runs Promote Partitions 9 58 v2E Complete Complete Run Bitgen Complete nch ChipScope Analyzer i i Launch impact e Launch FPGA Editor
28. High Speed Transceivers Interaction with Other Xilinx Tools About Design Considerations To take advantage of the Partial Reconfiguration capability of Xilinx FPGA devices you must analyze the design specification thoroughly and consider the requirements characteristics and limitations associated with PR designs This simplifies both the design and debug processes and avoids potential future risks of malfunction in the design Partial Reconfiguration User Guide www xilinx com 105 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX Design Hierarchy 106 This section discusses Design Hierarchy and includes e About Design Hierarchy e Design Elements Inside Reconfigurable Modules e Packing Logic e TO in Reconfigurable Modules e Packing Input Output Registers in the IOB e Design Instance Hierarchy e Submodules in Reconfigurable Modules e Global Clocking e Regional Clocking e Controlled Routes e ChipScope Pro e EDK System Generator for DSP and CORE Generator About Design Hierarchy Good hierarchical design practices resolve many complexities and difficulties when implementing a Partially Reconfigurable FPGA design A clear design instance hierarchy simplifies physical and timing constraints Registering signals at the boundary between static and reconfigurable logic eases timing closure Grouping logic that is packed to
29. No configuration error O 6 DALIGN Sync word received active High 0 No sync word received 1 Sync word received by interface logic O 5 RIP Readback in progress active High 0 No readback in progress 1 A readback is in progress O 4 IN ABORT B ABORT in progress active Low 0 Abort is in progress 1 No abort in progress O 3 0 1 Reserved The most significant nibble of this byte reports the status These Status bits indicate whether the Sync word been received and whether a configuration error has occurred The following table displays the values for these conditions Table 6 3 ICAP Sync Bits O 7 0 Sync Word CFGERR 9F No Sync No CFGERR DF Sync No CFGERR 5F Sync CFGERR 1F No Sync CFGERR Figure 6 6 below shows a completed full configuration followed by a Partial Reconfiguration with a CRC error and finally a successful Partial Reconfiguration Using the table above and the description below you can see how the O port of the ICAP can be used to monitor the configuration process If a CRC error occurs these signals can be used by a configuration state machine to recover from the error These signals can also be used by ChipScope to capture a configuration failure for debug purposes With this information ChipScope can also be used to capture the various points of a Partial Reconfiguration 102 www xilinx com Partial Reconfiguration User Gui
30. PAR Complete By Static Logic Implemented reconfig blue blue fast Implemented reconfig green green fast Implemented 45v reconfig red red fast Implemented gt 555 4 Not started E Static Logic Implement reconfig blue blue slow Implement reconfig green green slow Implement 4 reconfig red red slow Implement Hm FSF 4 Not started BB 4 Not started _ amp Sources amp Timing Co A Physical C Configu 5 Netlist Figure 4 28 Before Promotion of Configuration FFF 76 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 Controlling Configurations Configuration Module Variant Status FFF 4 E2 Static Logic 54 reconfig blue reconfig areen reconfig_red S55 4 Be static Logic reconfig blue reconfig green O reconfig red o gt FSF 4 Ec BB 4 d Sources Timing Co blue fast green fast red fast blue slow green slow red slow fl Physical C Promoted Promoted Promoted Promoted Promoted Not started Import Implement Implement Implement Not started Not started OO Netlist Figure 4 29 After Promotion of Configuration FFF Multiple Configurations can be promoted at once The modules are imported from
31. Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 2 Common Applications This chapter discusses common applications and includes e Basic Premise of Partial Reconfiguration e Networked Multiport Interface e Configuration by Means of PCIe Interface e Dynamically Reconfigurable Packet Processor e Asymmetric Key Encryption e Summary Basic Premise of Partial Reconfiguration The basic premise of Partial Reconfiguration is that the FPGA hardware resources can be time multiplexed similar to the ability of a microprocessor to switch tasks Because the FPGA device is switching tasks in hardware it has the benefit of both flexibility of a software implementation and the performance of a hardware implementation A number of different scenarios are presented here to illustrate the power of this technology Networked Multiport Interface Partial Reconfiguration optimizes traditional FPGA applications by reducing size weight power and cost Time independent functions can be identified isolated and implemented as Reconfigurable Modules and swapped in an out of a single device as needed A typical example is a network switch The ports of the switch might support multiple interface protocols however it is not possible for the system to predict which protocol will be used before the FPGA device is configured To ensure that the FPGA device does not have to be reconfigur
32. Partition Before creating timing constraints the nets must be grouped by input to or output from the RM with a PIN TPSYNC constraint The pin name syntax is lt Partition_name gt lt port_name gt The following code snippet is an example PIN RP A 1 TPSYNC group RP A input PIN RP A 2 TPSYNC group RP A output Using the TPSYNC constraint on Partition Pins is more comprehensive than just using a PERIOD constraint to cover these paths By using a TPSYNC initial budgeting can be done to minimize the delay from the static region to the Partition Pin This provides more of the timing budget to the RMs and ultimately makes it easier for the implementation tools to meet the RMs timing requirements www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Constraints The PIN TPSYNC grouping constraint supports standard UCE wildcard conventions For example if there was a data bus input to RP_A it could be added to the input group in the previous example with this constraint PIN RP A data TPSYNC group RP A input To create timing constraints for all static nets going to Partition Pin RP A 1 and all reconfigurable nets going from Partition Pin RP A 1 paths A amp B above use this convention TIMESPEC TS from static to PP input TO group RP A input 4 5 ns TIMESPEC TS from PP input to RM FROM group RP A input 4 5 ns To create
33. Partition is imported then its implementation including placement and routing is identical to the design from which it was imported For example the first Configuration implements the static logic and the user exports promotes this result All subsequent implementations import the static Partition from the promoted Configuration If the static logic is modified and re exported then the subsequent Configurations must be updated by importing the new static logic and re implementing those Configurations The Role of PXML Files The Partition information is stored in the xpartition pxml file located in the implementation directory Each Configuration has its own PXML file stored in its design directory The xpartition pxml file e Isa text file using XML format e Is generated automatically by the PlanAhead software or the provided gen_xp tcl script For more information on gen xp tc1 see Chapter 5 Command Line Scripting e Can be user created or modified e Is treated by the implementation tools such as MAP and PAR as an input e Can be considered a source for revision control needs Xilinx software such as ngdbuild MAP and PAR looks automatically for and uses the xpartition pxml file in the implementation directory The XML file with the Partition information must be named xpartition pxmland must reside in the implementation directory Otherwise the Reconfigurable Partitions are not recognized When the xpartition pxml file
34. Sources amp Timing Co E Physical C Configu 3 Netlist Figure 4 26 Promoting a Configuration Partial Reconfiguration User Guide www xilinx com 75 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support XILINX There are interdependencies between Configurations e Static Logic as well as each Reconfigurable Module must be identical for each Configuration that uses it e Every Configuration must use the same Static Logic implementation and some Configurations might share the same RMs e When a Configuration is Promoted those implementations are set as the golden result for all modules in that Configuration e Other Configurations could be affected by promoting or resetting a Configuration The PlanAhead software displays an alert if this occurs 3 Reset out of date run xj 2 Promoting 555 configuration will result in the following runs going out of date BB FFF Out of date runs will be reset Click OK to continue v Delete files on disk when resetting runs i Cancel Figure 4 27 Resetting Out of Date Configurations Once a run is promoted the status of RMs in other Configurations is updated where appropriate Figure 4 28 and Figure 4 29 show that because Configuration FFF has been promoted the status of the Static Logic in Configuration SSS is set to Import Configurations n a Z Em Pe E e B ___ Configuration Module variant status zw FFF 4
35. While this may seem like more work up front if a design has hundreds of BMs throughout this will make the conversion much easier and quicker as each of those instances do not have to be changed As you begin to redefine these bus macros any problems with the module can be fixed and the change will be consistent with all BMs of that type throughout the design Below is another asynchronous example but with control logic Partial Reconfiguration User Guide www xilinx com 125 UG702 v 12 1 May 3 2010 Chapter XILINX Example VHDL Bus Macro with Enable Redefined for busmacro_xc5v_async_enable library IEEE use IEEE STD LOGIC 1164 ALL entity busmacro xc5v async enable is Port inputO in STD LOGIC inputl in STD_LOGIC input2 in STD_LOGIC input3 in STD_LOGIC enableO in STD_LOGIC enablel in STD_LOGIC enable2 in STD_LOGIC enable3 in STD_LOGIC outputO out STD LOGIC outputl out STD LOGIC output2 out STD LOGIC output3 out STD LOGIC end busmacro xcb5v async enable architecture Behavioral of busmacro xcbv async enable is begin outputO lt input0 and enabled outputl lt inputl and enablel output2 lt input2 and enable2 output3 lt input3 and enable3 end Behavioral OO O Verilog Bus Macro Removal The flow is exactly the same as the VHDL flow except the Verilog flow does not have module declarations Follow the VHDL flow
36. a Partial Bit File A partially reconfigured FPGA device is in user mode while the partial bit file is loaded This allows the portion of the FPGA logic not being reconfigured to continue functioning while the reconfigurable portion is modified Figure 6 2 illustrates this process Partial Reconfiguration User Guide www xilinx com 95 UG702 v 12 1 May 3 2010 Chapter 6 Configuring the FPGA Device g XILINX Partial Configuration Bit File Config Data FPGA nee Start Initial Configuration Done Download Vcc Rise Asserted Partial Bit File X12032 Figure 6 2 Configuring With a Partial Bit File The partial bit file has no header nor is there a startup sequence that brings the FPGA device into user mode The bit file contains essentially only frame address and configuration data plus a final checksum value When all the information in a partial bit file is sent to the FPGA device by means of dedicated modes or through the ICAP no external DONE signal is raised to indicate completion You must monitor the data being sent to know when configuration has completed The end of a partial bit file has a DESYNCH word 0000000D that informs the configuration engine that the bit file has been completely delivered This word is given after a series of padding NO OP commands ensuring that once the DESYNCH has been reached all the configuration data has already been sent to the target frames throughout the device As soon as the c
37. already in user mode when the partial bit file is loaded Because the configuration circuitry supports error detection only after a bit file has been loaded a corrupt partial bit file can become active potentially damaging the FPGA device if left operating for an extended period of time If a corrupt partial bit file is loaded it can be detected through the ICAP TheStatus Register STAT indicates that the partial bit file has a CRC error by asserting the CRC ERROR flag bit 0 in Virtex 5 devices If the CRC ERROR flag is asserted the FPGA design attempts to fix the corruption Partial Reconfiguration User Guide www xilinx com 97 UG702 v 12 1 May 3 2010 Chapter 6 Configuring the FPGA Device g XILINX There are two types of partial bit file errors to consider data errors and address errors the partial bit file is essentially address and data information If the error is in the data portion then recovery is relatively simple Load a new partial bit file or even a blank partial bit file and the corruption is resolved If the error occurs in the address portion of the partial bit file recovery is more invasive The corruption could have modified the static portion of the FPGA design In this case the only method for safe recovery is to download a new full bit file to ensure the state of the static logic which requires the entire FPGA device to be reset Many systems do not need a complex recovery mechanism because r
38. cost Partial Reconfiguration enables new types of FPGA designs that would otherwise be impossible to implement 24 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 3 Software Tools Flow This chapter discusses the Software tools flow and includes e About the Software Tools Flow e Example Design Structure e Example Project File Structure e Synthesis e Configurations e Constraints e Partitions and Import e Implementation e Generating Bit Files e Report Files e pr verify e Flow Differences About the Software Tools Flow Implementing a partially reconfigurable FPGA design is similar to implementing multiple non PR designs that share common logic Partitions are used to ensure that the common logic between the multiple designs is identical Figure 3 1 illustrates this concept Partial Reconfiguration User Guide www xilinx com 25 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX Static Module Netlists EDIF or NGC Design 1 Module Constraints Static Constraints Design 2 ES fs Module RMB bit Constraints Implement Static Constraints Design N Module Constraints Static Constraints X12024 Figure 3 1 Overview of the Partial Reconfiguration Software Flow The top gray box represents the synthesis of HDL source to netlists for each
39. driven by regional clocking correspond to clock region boundaries whenever possible In addition Xilinx recommends that the BUFRs be constrained to specific BUFR locations See the Clock Resources chapter in the Virtex 4 FPGA User Guide for more information on the restrictions of regional clocking Virtex 5 Proxy logic is inserted on regional clocks which pass between static and RPs The proxy logic adds delay to the regional clock which can have detrimental effects on timing To prevent timing degradation Xilinx recommends that BUFRs and all their loads be fully contained within the same Partition whether static or reconfigurable This provides minimal skew between regional clock loads and results in the greatest chance for meeting timing In addition Xilinx recommends that the BUFRs be constrained to specific BUFR locations All other limitations of regional clocking still apply See the Clock Resources chapter in the Virtex 5 FPGA User Guide for more information on the restrictions of regional clocking Virtex 6 No proxy logic is inserted on regional clocks and regional clock spines are prerouted The spines will be prerouted to each clock region which may need that clock spine For example if a regional clock drives a port on an RP which covers portions of two clock regions regional clock spines will be reserved for that regional clock in both of the clock regions Virtex 6 is the first architecture which has had multiple colu
40. e Partial Bitstream CRC Checking e Configuration Frames e Configuration Time e Configuration Debugging About Configuring the FPGA Device This section describes the system design considerations when configuring the FPGA device with a partial bit file as well as architectural features in the FPGA that facilitate Partial Reconfiguration Because most aspects of Partial Reconfiguration are no different than standard full configuration this section concentrates on the details that are unique to PR Any of the following configuration ports can be used to load the partial bitstream SelectMAP Serial JTAG or ICAP Internal Configuration Access Port To use SelectMAP or Serial modes for loading a partial bit file these pins must be reserved for use after the initial device configuration This is achieved by using the UCF constraint CONFIG MODE only needed to select a width of 16 or 32 and the Bitgen g persist option Partial bitstreams contain all the configuration commands and data necessary for Partial Reconfiguration The task of loading a partial bitstream into an FPGA does not require knowledge of the physical location of the RM because configuration frame addressing information is included in the partial bitstream A partial bitstream cannot be sent to the wrong part of the FPGA device A Partial Reconfiguration controller retrieves the partial bitstream from nonvolatile memory then delivers it t
41. either odd or even The AREA GROUP block RAM range can be determined by looking in the PlanAhead or the FPGA Editor An AREA GROUP RANGE example is illustrated in Figure 3 4 Partial Reconfiguration User Guide www xilinx com 33 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow 7 M Te lt c 2 Oo o CC O lt LY WT 71 N N N N N N XILINX X12026 Figure 3 4 Slice Range and BRAM Range for a PR Region The following code snippet is an AREA_GROUP RANGE constraint example with Slices and BRAM AREA GROUP AG PRregionA RANGE AREA GROUP AG PRregionA RANGE SLICI E X2YO SLICE X43Y157 RAMB16 X0YO RAMB16 X3Y18 The PlanAhead software estimates the size of each RM and displays the resources used which is useful in determining if an AREA GROUP RANGI IO 34 www xilinx com E is necessary for Block RAM or Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Constraints However the tools cannot make recommendations as to the shape or placement of the Reconfigurable Partition The AREA_GROUP RANGE must be large enough to accommodate the largest RM for each resource type that is the RM using the most Slices might not be the RM using the most BRAM and it must be shaped and placed in a way that allows the design to meet timing Partition Pins PR designs contain special components named Par
42. for these two configurations This number should be the same for all analyses Number of matched external nets This reflects the number of ports input or output on the RMs for these two configurations This number should be the same for all analyses Number of matched global clock nets This reflects the number of Global Clock nets in the design that were consistently routed between these two configurations This number should be the same for all analyses Number of matched Reconfigurable Partitions This reflects the number of RMs that were used in both these configurations and have consistent implementation This will not necessarily be the same for all analyses For example BlankConfig and FastConfig only have static in common so the analysis for those configurations shows 0 matched reconfigurable partitions However FSFConfig and FastConfig have static Red Fast and Green Fast in common so they have two matched reconfigurable partitions Partial Reconfiguration User Guide www xilinx com 57 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow Flow Differences The flow for Partial Reconfiguration is very similar to the standard flow through the implementation tools but to create a safe result for the silicon restrictions must be imposed on placement and routing These limitations impact the performance packing density and implementation flexibility of a design 58 Table 3 1 Flow Differences XILINX
43. not be edited If you are using the Xilinx HD Tcl scripting method to implement the design the file will be created when the implementation script is run Tcl Flow is the only Command Line Option In the EA solution the tools could be run directly from command line While the tools can also be run in 12 1 from command line the difference is that the PXML file needs to exist before the ISE 12 tools will treat the design as a PR design This requires the user to script the flow in Tcl to generate the PXML file Note To help get started with the Xilinx HD Tcl scripting method some basic flat flow scripts can be generated using the Generate Scripts Only option when creating runs To write Xilinx HD Tcl scripts that leverage the Reconfigurable Partition promoting implementing and importing functionality see Chapter 5 Command Line Scripting UCF is only required in NGDBuild There was also a requirement that the UCF be available for post Translate implementation processes MAP and PAR in the EA solution This is no longer the case and all information that is required for downstream implementation processes is embedded in the design database files www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Migrating a Design Manage full design timing constraints As ISE 12 implements complete designs in context timing constraints and timing budgets should be established Review the recommend
44. not contain dynamic elements such as Block RAM Distributed LUT RAM or SRLs When static logic is placed in a reconfigured frame the exact functionality of the static logic is rewritten and is guaranteed not to glitch Irregular shaped Partitions such as a T or L shapes are permitted but discouraged Placement and routing in such regions can become challenging because routing resources must be entirely contained within these regions Boundaries of Partitions can touch but this is not recommended as some separation helps mitigate potential routing restriction issues Nested or overlapping Reconfigurable Partitions Partitions within Partitions are not permitted Design rule checks Tools gt Run DRC validate the Partitions and settings in a PR project The partial bit files that are created are based upon the AREA_GROUP RANGE constraints set by the user To generate the smallest bit files possible and to avoid complications or errors only define AREA_GROUP RANGE constraints for the elements that exist in the full set of Reconfigurable Modules for a Reconfigurable Partition If you are using PlanAhead this Partial Reconfiguration User Guide www xilinx com 113 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX Proxy Logic means unchecking any unnecessary element type in the Pblock Properties gt General option Finally only one Reconfigurable Partition can exist per physical Reconfigurable Frame
45. the fast and slow variants for each color module Static Modules Reconfigurable Partitions X12025 Figure 3 2 Color2 Design Hierarchy The following is a code snippet of the design source hierarchy and Reconfigurable Module variants for the overall PR Project named Color2 Design source hierarchy and Reconfigurable Module variants for overall PR project named Color2 TOp V top module which is static red instantiation of a Reconfigurable Module red fast v Reconfigurable Module red slow v blue instantiation of a Reconfigurable Module blue fast v Reconfigurable Module blue slow v green instantiation of a Reconfigurable Module green fast v Reconfigurable Module green slow v DVI IF v Static module TIC INIG 2 xm Ro ow UU VGA 2 4 ow xoxo wow M Red Green and Blue are partially reconfigurable instances All other logic in the design is static Partial Reconfiguration User Guide www xilinx com 27 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX The instances Red Green and Blue do not contain any logic they are simply instantiation statements the module definitions such as red_fast and blue_slow contain the logic to be implemented Example Project File Structure A partially reconfigurable FPGA design project is more complex than an av
46. to static and reconfigurable parts of the net Therefore the PERIOD constraint should be used in combination with FROM TO and FROM TO constraints to accurately budget the entire path Connecting input pads directly into a Partition or outputs from a Partition directly to an output pad could result in suboptimal timing performance The Partition Pins are made of combinatorial logic and add path delay The Partition Pins also prevent IOB packing which could lead to timing failures for the inputs and outputs if that packing were required Xilinx strongly recommends that all signals except global clocks passing through the Reconfigurable Partition boundary are registered to simplify timing constraints and to increase the likelihood that timing constraints are met However if pads are connected directly to a synchronous component in a Reconfigurable Partition then OFFSET constraints can be used to correctly constrain the path If an input pad drives a synchronous component inside of a Partition an OFFSET IN constraint can be applied to constrain the input This correctly takes the Partition Pin delay into account A global OFFSET IN that could apply OFFSET IN 3 ns VALID 8 ns BEFORE clk If a synchronous component drives the output of a Partition and the Partition output drives an output pad an OFFSET OUT constraint can be applied to constrain that output Partial Reconfiguration User Guide www xilinx com 37
47. to maintain placement from one Configuration to the next Even though Partition Pins are physically located within the reconfigurable regions they are logically part of the static logic and any constraints placed upon them must reside in www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Constraints the top level UCE Partition Pins can be viewed within FPGA Editor to see their placement in relation to other logic in the design Partition Pins can also be referenced by using the Partition Pins predefined group PPS Use this keyword in the same way as any other predefined groups such as FFS RAMS or PADS would be used This example uses this predefined group to specify timing through a Partition or from one Partition to another TIMESPEC TS01 FROM PPS TO PPS 5 ns Constraints Editor The Constraints Editor can be used to create the Partition Pin groups and timing constraints after an initial implementation has been run on at least one Configuration When prompted for design files select any NGD file in an up to date Configuration however the UCF must be a new file created before the Constraints Editor is opened not the name of the UCE file that has already been imported into the Plan Ahead software or one that currently exists with a Configuration Within Constraints Editor there is a Group Constraints category in the Constraint Type window Select By Combinatoria
48. tools to see when a register is connected to IO logic When a partition boundary exists between the register and the associated buffer the tools cannot see across the partition boundary to correctly place the register in the IO logic When this is not possible the implementation tools do have the ability to handle this situation if the following rules are followed e The register must have an IOB FORCE UCF constraint This will allow the tools to see through the partition boundary and see the register is connected to an IO buffer thus allowing the tools to place the register in the IO logic ILOGIC OLOGIC Using the OB FORCE will cause an error in the implementation tools if the register cannot be placed in the IO logic This is the desired behavior for situations that require that a register is placed in the IO logic for example if a register is clocked by a BUFIO or when an interface timing requires a fixed delay In this case using the map pr b option will not place a register in the IO logic like it could in a flat flow or when the buffer and register are in the same partition e The IOB FORCE constraint must be the instance name of the register INST rp module outl ff IOB FORCE Do not put this constraint on the register s output or input net e The RP s AREA GROUP constraint must contain the IO logic where the input output register will be placed For instance there must be a RANGE value that
49. usage global signals design constraints and other requirements To implement all Reconfigurable Modules you must choose a subset of all possible Reconfigurable Module combinations and implement them as unique designs Each unique implementation is called a Configuration Each Reconfigurable Partition can be optionally set as a black box leaving a blanking bitstream as a Reconfigurable Module Therefore in the Color design the full set of Reconfigurable Modules and therefore partial bit files that can be implemented are Red red fast red slow black box Blue blue fast blue slow black box Green green fast green slow black box With three choices for each Reconfigurable Partition and three RPs in this design there are twenty seven unique combinations that can define a Configuration However it is not necessary to create a Configuration for each combination It is sufficient to implement only the Configurations that contain each module once since the partial bit file for a module is independent of the other Reconfigurable Modules In the Color2 design one minimal set is as shown in Figure 3 3 Minimum number of FPGA designs Configurations required to implement the PR project Color2 First Configuration Second Configuration Third Configuration Top Top Top Red Red Red red fast red slow black box Blue Blue Blue blue fast blue slow black box Green Green Green green fast green slow black box DVI IF DVI IF DV
50. utilization with respect to the resources contained in the physical area group ranges defined in the UCF file In this example the pblock_reconfig_blue area group has one range associated with it for slices LUTs and FFs The AG_RP_green area group has ranges for block RAM and slices Area Group Information Area Group AG_reconfig_blue No COMPRESSION specified for Area Group AG_reconfig_blue RANGE SLICE_X74Y0 SLICE_X83Y79 Slice Logic Utilization Number of Slice Registers 25 out of 6 400 1 Number of Slice LUTs 42 out of 3 200 1 Number used as logic 42 Slice Logic Distribution Number of occupied Slices 15 out of 800 1 48 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Report Files Number of LUT Flip Flop pairs used 44 Number with an unused Flip Flop 19 out of 44 43 Number with an unused LUT 1 out of 44 2 Number of fully used LUT FF pairs 24 out of 44 54 PAR Report Similar to the Ngdbuild report and the MAP report the following PAR report also shows which Partitions were implemented Partition Implementation Status Preserved Partitions Partition top Implemented Partitions Partition top reconfig_red Reconfigurable Module red fast Attribute STATE set to IMPLEMENT Partition top reconfig blue Reconfigurable Module blue fast Attribute STATE set to IMPLEMENT Partition top reconfig green Reconfigurable Module
51. verify see Verifying Configurations in Chapter 4 Partial Reconfiguration User Guide www xilinx com 89 UG702 v 12 1 May 3 2010 Chapter 5 Command Line Scripting XILINX Required Files and Directory Structure 90 The Tcl scripts require a unique directory for each RM and each Configuration These must all be contained under a single top level directory For the example used throughout this Guide the scripts run from the Implementation directory The data tcl file is stored in the Tools directory Figure 5 1 shows an example directory structure 3 PR C3 PRdesians C3 Color2 Common C3 Does i C3 Implementation BlankConfig Blue Blank blue fast Cj blue slow C3 FastConfig C3 FsFConfig Green Blank C3 green fast C3 green slow Red Blank 3 red fast C3 red slow SlowConfig C3 static C3 PlanAhead C3 Source C3 Synth C Tools Figure 5 1 Required Directory Structure for Sample Scripts If any of these directories are missing regardless of whether their contents have been generated the scripts fail to process As the scripts run they move into the Configuration directories to run implementation Report files are required for debugging RM Directories If the option RUN_RM_SYNTH is set to YES the directory for each RM in the list must contain the synthesis input files xst and prj The XST file contains the command l
52. vlde 106 About Design Hierarchy 6 666 en 106 Design Elements Inside Reconfigurable Modules 06 6 00 c cee neue 106 Packing Logic cics ir a inec d e REF se cede REG a ies eae Hea a dee ed 107 IO in Reconfigurable Modules 06 0 eee eens 107 Packing Input Output Registers in the IOB 0 000008 110 Design Instance Hierarchy sss scssi ce 110 Submodules in Reconfigurable Modules anunua cece eee eens 110 Clocking Rules cen sie OIRO ete e Ya EERE KI A ORO RN HEA 111 Global ClOCKIN 8 00 one oe ote Dat GP hunk e Pe a dat a tie ll 111 Regional Clocking sii c tati bua tiie ee Fue ere Hig we LG we Lalas the 112 Decoupling Functionality lt lt ce re ce shop ah e Re Ee RR a 113 Defining Reconfigurable Partition Boundaries 05 113 Proxy LOGIC 35410502 tota tense al it a Rd d a eta lada de kd iati 114 Controlled Routes ce 114 Black BOXES incerce re e ee pct de ded ed et d dada 115 Module Level Constraint Files uuusuuiusslllsssssls esses 115 Implementation Strategies 0 116 Partial Reconfiguration User Guide www xilinx com UG702 v 12 1 May 3 2010 Chapter g XILINX Simulation and Verification 0 00 00 0000 en 116 Using High Speed Transceivers sies r tee pee n a iata ae la ep aie 116 Interaction with Other Xilinx Tools ccn eese 116 GHP SCOP Os PrO zoe see eet a data i aula tea aul i i aaa al tag el 1
53. 16 EDK System Generator for DSP and CORE Generator cc 117 Appendix A Known Issues and Known Limitations Known Iss es etta bed at Sees a e ut ee ease tie 1 119 Known Limitations e ceea ndo e rey os bee eb een bbe ea Ea bad aaa 119 Appendix B Partial Reconfiguration Migration Guide OVERVIEW 600245054 a te d a e d ata ota a a Aa sae deas 8 HERR A al d a 121 Differences Between the Early Access and Production Solutions 121 Compatible Designs for Migration lt nenea 121 Bus Macro instantiations no longer required cn 121 PR Specific Environment Variables Deprecated 0 000 nnna rnrn 122 MODE Constraint Deprecated 6 ceea 122 NGDBuild modular switch deprecated 00 eee eens 122 Partition Information is Stored in the xpartition pxml File 0 122 Tcl Flow is the only Command Line Option cc 122 UCF is only required in NGDBuild ssseee e 122 Manage full design timing constraints 123 BUFRs require Partition Pins in Virtex 5 2 6 eee ee 123 Migrating a Desiphi v c coe tit tier dl tae HERR ERR ER OR FERES ERE d ee deis 123 Bus Macro Removal sseeeeeeeeeeee er n 123 VHDL Bus Macro Removal ceea 123 Redetine Bus Macros d eu eee ed ce Rhe eR a Fe FR ane patit BR n adu 125 Verilog Bus Macro Removal sees nn 126 Create a PlanAhead Project in 12 1 2 6 eee 126 SUMMATY coii dee tit set a ad Al o e E
54. 2010 XILINX Black Boxes Black Boxes The Partial Reconfiguration software allows black boxes to be implemented as Reconfigurable Modules This is an effective way to reduce the size of full configuration bit file and therefore reduce the initial configuration time To create a black box Partition create a Reconfigurable Module with no associated netlist file The source shown in PlanAhead is listed as Blackbox module Even though a black box has no user logic contained in the logical representation of the design the physical region is not entirely empty As noted in the Proxy Logic section above a LUT1 is inserted for each Partition Pin as the interface to the Reconfigurable Partition Because these proxy LUTs must exist within the reconfigurable region they appear in the black box along with their connections outside the region The bitgen compression g compress feature may be enabled to reduce the size of bit files This option looks for repeated configuration frame structures to reduce the amount of configuration data that must be stored in the bit file This savings is seen in reduced configuration and reconfiguration time When the compression option is applied to a routed PR design all of the bit files full and partial are created as compressed bit files This option is especially useful when coupled with the technique of building a PR design with black box RMs Module Level Constraint Files In order to adequat
55. A Device g XILINX It is important to note that a Partial Reconfiguration does not perform a CRC check until the entire partial bit file has been loaded so corrupted data will have already been loaded into the FPGA If the corruption occurred on an address bit the static logic could potentially be corrupted and that status is indicated at the INIT_B configuration register bit In a system requiring high reliability it is important to do a CRC check on the partial bitstream prior to sending it to the configuration interface Information on performing a CRC check on partial bitstreams prior to loading is given in the Partial Bitstream CRC Checking section of this chapter If a CRC error occurs by default the configuration interface will try to issue a full reconfiguration of the device This is usually not the desired behavior To prevent this from happening follow the recommendations given in Generating Bit Files in Chapter 3 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 7 Design Considerations This section discusses design considerations and includes About Design Considerations Design Hierarchy Clocking Rules Decoupling Functionality Defining Reconfigurable Partition Boundaries Proxy Logic Black Boxes Module Level Constraint Files Implementation Strategies Simulation and Verification Using
56. ARTUP and USR_ACCESS www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Design Hierarchy Packing Logic Any logic that must be packed together must be placed in the same group whether it is static or reconfigurable For example IO registers must remain with the IO port Partition boundaries are barriers to optimization Choose the hierarchical boundaries wisely since the insertion of proxy logic may result in suboptimal results or routes that are impossible to achieve IO in Reconfigurable Modules Device pins can be placed in RMs and therefore can be reconfigured RMs must include the IO circuitry such as IBUF and OBUF that is required to connect internal logic to package pins and the ports must connect to the static logic by name only In other words the IO features must be completely contained within the module but the port list for the complete design remains at the top level design description Other requirements of submodule IO include e HDL Each Reconfigurable Module for a Reconfigurable Partition must have the same set of module ports All external port declarations should be made at the top level Automatic IOB insertion should be enabled for the top level synthesis and disabled for module level synthesis Synthesis tools handle declarations of submodule pins differently Examples for XST and Synplify are provided in the following subsec
57. ATA OR LOST PROFITS ARISING FROM YOUR USE OF THE DOCUMENTATION 2007 2010 Xilinx Inc XILINX the Xilinx logo Virtex Spartan ISE and other designated brands included herein are trademarks of Xilinx in the United States and other countries All other trademarks are the property of their respective owners Partial Reconfiguration User Guide www xilinx com UG702 v 12 1 May 3 2010 Revision History The following table shows the revision history for this document Date 05 03 10 Version 12 1 Initial release for ISE 12 1 Revision UG702 v 12 1 May 3 2010 www xilinx com Partial Reconfiguration User Guide Partial Reconfiguration User Guide www xilinx com UG702 v 12 1 May 3 2010 Table of Contents Beviston ASI OEI asp ln iei ina aci ede Deta i ae ee ee ee a ee dard 3 Preface About This Guide Guide Contents uses e es 9 Additional Resources sese e 10 Conventions orbe E RERFIQW on ae Gu qu RERPPCLE PR IVA E 10 Iypographical eiie titre dedo dde leto eden dele a an 10 Online Document ce ccc RR Re 11 Revision History eM 11 Chapter 1 Introduction Partial Reconfiguration Overview 0 00 esee 13 Terminology ceserer epe bae EHE a e E a OE PER REE ae Era t 14 Bottom Up Synthesis iis ee ee anii nti rer ee acc a 14 Config raton sss anea sni ede rte d RITE PR IU RR HER EY ho aa Pew 14 Configuration Frame cessas sek e ERRE
58. E HE TE HE HE HE HE E E HE H Create the per partition attributes list This list must be called PartitionAttrsList The format is set PartitionAttrsList lt partitionlist gt where lt partitionlist gt partitionattrs lt partitionattrs gt lt partitionName gt lt attrslist gt lt attrslist gt lt namevalpair gt lt namevalpair gt lt attrName gt lt attrValue gt HEE HE FE HE HE HH FE E HE E FE HH HE HEH HE HE HE HE FE FE FE FE HE FE FE HE HHH HEH EE HE HE HE HE HEHE HE set PartitionAttrsList top Reconfigurable false top reconfig_red Reconfigurable true top reconfig_green Reconfigurable true top reconfig_blue Reconfigurable true 6 RM list Each RM in the list is synthesized with bottom up synthesis You must create a directory for each of the RMs in the list Specify the RMs that must be run through bottom up synthesis Synthesis is run in the order specified The required directory structure is discussed in a later section 4 7 Partition Attributes List This allows you to specify whether Partitions are reconfigurable The three RPs have Reconfigurable set to true while top has no setting as the default is False Partial Reconfiguration User Guide www xilinx com 85 UG702 v 12 1 May 3 2010 Chapter 5 Command Line Scripting XILINX Section 3 Define Configurations Section 3 Define Configurations defines th
59. I IF IIC init IIC init IIC init VGA VGA VGA Figure 3 3 Minimum Number of FPGA designs Configurations Required to Implement PR Project Color2 There are three different modules each for Red Green and Blue Accordingly a minimum of just three Configurations is necessary to implement all Reconfigurable Modules If desired further Configurations can be created to achieve unique full bit files For example a Fourth Configuration containing modules red fast blue slow and green fast can be created All three Reconfigurable Modules are re used in this Configuration The implementation results and partial bit files for these modules are identical between the multiple Configurations Once a partial bitstream is created it can be loaded in the FPGA device in any combination of full or partial bitstreams created within that PR project however to validate that a particular combination works as expected it might be necessary to create a Configuration for that combination of modules Full design level simulation and verification flows for Partial Reconfiguration designs are no different than for standard designs Partial Reconfiguration User Guide www xilinx com 31 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX Constraints Constraints for the static logic are usually stored in the UCF file and are shared among all Configurations By using the ngdbuild uc option one common UCF file can be shared among all Con
60. MMCM No bidirectional interfaces are permitted between static and reconfigurable regions No dedicated encryption support is available until ISE 12 2 at that release it will be available natively for Virtex 6 and via an IP core for Virtex 5 Users are free to build their own software encryption engine to modify partial bit files and a hardware decryption engine within the FPGA fabric to handle encryption needs While Virtex devices do have dedicated CRC functionality at the end of a Partial Reconfiguration validation of the integrity of partial bit files can be checked via an IP core inserted as part of a bit file delivery mechanism While a specific IP solution will be available users are again welcome to develop their own solution for CRC checking within their design Partial Reconfiguration is a powerful capability within Xilinx FPGAs and understanding the capabilities of the silicon and software is instrumental to success with this technology While trade offs must be recognized and considered during the development process the overall result will be a more flexible implementation of your FPGA design Partial Reconfiguration is fully supported by the Xilinx Support Design Services and Titanium Engineering teams These expert resources are available to help meet any design needs Partial Reconfiguration User Guide www xilinx com 17 UG702 v 12 1 May 3 2010 Chapter 1 Introduction 18 www xilinx com XILINX
61. O which is required if Slave SelectMAP or Slave Serial modes are to be used for Partial Reconfiguration This option should be used in conjunction with the CONFIG_MODE constraint to select the proper set of configuration pins to be reserved for post configuration use Consult the Constraints Guide for the complete set of values for CONFIG_MODE examples S_SELECTMAP S SERIAL g RetainConfigStatus No Use this option to prevent the configuration status bit from being sticky used to detect errors during PR Use this option for Virtex 5 and newer architectures Do not use the BitGen r option with the Partition based Partial Reconfiguration flow The r switch supports the difference based flow where minor edits are made to a routed design and this option compares the changes in order to build a partial bit file For more information on these and other BitGen Options see the chapter titled BitGen in the Command Line Tools User Guide The report files for ngdbuild MAP PAR trce and bitgen contain specific information for Reconfigurable Partitions The report files are Ngdbuild Report Map Report PAR Report Tree Report Bitgen Report The following sample reports are in a simplified format www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Report Files Ngdbuild Report The Ngdbuild report indicates which Partitions including the top level static Partition
62. Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX amp XILINX Xilinx is disclosing this user guide manual release note and or specification the Documentation to you solely for use in the development of designs to operate with Xilinx hardware devices You may not reproduce distribute republish download display post or transmit the Documentation in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Xilinx expressly disclaims any liability arising out of your use of the Documentation Xilinx reserves the right at its sole discretion to change the Documentation without notice at any time Xilinx assumes no obligation to correct any errors contained in the Documentation or to advise you of any corrections or updates Xilinx expressly disclaims any liability in connection with technical support or assistance that may be provided to you in connection with the Information THE DOCUMENTATION IS DISCLOSED TO YOU AS IS WITH NO WARRANTY OF ANY KIND XILINX MAKES NO OTHER WARRANTIES WHETHER EXPRESS IMPLIED OR STATUTORY REGARDING THE DOCUMENTATION INCLUDING ANY WARRANTIES OF MERCHANTABILITY FITNESS FOR A PARTICULAR PURPOSE OR NONINFRINGEMENT OF THIRD PARTY RIGHTS IN NO EVENT WILL XILINX BE LIABLE FOR ANY CONSEQUENTIAL INDIRECT EXEMPLARY SPECIAL OR INCIDENTAL DAMAGES INCLUDING ANY LOSS OF D
63. Partial Reconfiguration design timing analysis needs to be run for each Configuration of the design Partial Reconfiguration User Guide www xilinx com 49 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX Following is an example of the TRCE command line For more information on the switches used in this example see the TRCE section of UG628 the Command Line Tools User Guide trce v 10 u 10 tsi top tsi o top twr xml top twx top top pcf The timing report can be used to examine the paths to from and through Partition Pins To find this logic search for the keyword PROXY A LUT name concatenated with the name PROXY identifies that the LUT is used as proxy logic and this also means that the Partition Pin exists on this proxy logic In the following example a TPSYNC constraint was applied to the red addr bus with these constraints PIN red addr TPSYNC group_RP_red_input TIMESPEC TS_from_static_to_PP_input TO group_RP_red_input 4 5 ns The source of this path is in the static region The destination is the LUT that has been inserted as proxy logic The destination name for this specific path is red addr 11 This indicates that the Partition name is red and that the port name is addr 11 This analysis shows that the clock to out time of the register and the net delay are taken into consideration up to the partition pin The delay through the partition pin is not conside
64. PlanAhead software to be applied to the design Select File gt Import Constraint and import constraints from the UCE updated by the Constraints Editor RM Constraints in PlanAhead PlanAhead provides an effective way to manage a Partial Reconfiguration design Constraining a PR design can be complex and managing those constraints through PlanAhead requires some planning There are three main methods for getting RM constraints into a Plan Ahead PR design Top UCF Method In this method the constraints exist prior to the PlanAhead project in one or more top level UCF files These constraints include full hierarchical paths to the RM logic and will apply to all RMs that contain the specified instances The constraints relating to RM logic will be pulled out of the top UCF and will be added to a PlanAhead generated partition UCF This method is not recommended for constraining RM logic RM UCF Method In this method the constraints exist prior to the PlanAhead project in an RM level UCF The hierarchy for these constraints is specific to the RM hierarchy not full hierarchical paths from Top If multiple RMs require the same constraint the constraint will need to be duplicated in each RM UCF This is the recommend way to add RM specific constraints GUI Method In this method the constraints are created after the PlanAhead project has been created with the PlanAhead GUI or a TCL command RM specific constraints will only apply to the RM a
65. Pm 54 pd T 55 pi verify Usage ses ce er exer REC PR C RR I RES ERE CER d eR d 55 Command Line Syntax 224a tele e ex obey Pee E pe wee Mw gg Es va 55 PE Verity bog Elea rreri debes E exer pedir dua een tae dee dre sea 56 Flow Differences e a os ia ra Rd RR i A RA RR d us 58 Chapter 4 PlanAhead Support About PlanAhead Support 0 00 00 59 Creating a Partial Reconfiguration Project 0c eee eee 60 Setting the Project as a PR Project 0 eens 62 Opening the Netlist Design 1 deesset ERRORES eee betes 63 Defining the Reconfigurable Instances 0 0 ee eese 64 Adding Reconfigurable Modules to the Project 0005 66 Updating Netlist Files eer E a EB ot ul duce da la a drea 67 Adding Black Box Modules sssss en 67 Defining a PR Region inscenat ten terr eren e Rd e feme a i bte Ren 69 Running Partial Reconfiguration Design Rule Checks 7 Creating Configurations s siia s ebd cies e Roc bb pp e e b ledio Yo 72 Controlling Configurations 4240 iere e i n la i ae ete e RE A 74 Verifying Configurations ccm eee 79 Generating Bit Flag sn parai are re ba te rela d e Poe abe da dana a ea aa 80 PlanAhead Project Directory Structure eee 81 6 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 5 Command Line Scripting About Comm
66. Reconfigurable Modules Q red fast d 7 red slow O red bb 5 Nets a led Fast inst le E static DVI dvi E static DVI IF dvi 3 static IC INIT cl Pblock Properties LEER e xn blue 3 pblock reconfig l Physical Resource Estimates Site Type Available Required Util LUT 1600 23 2 FD_LD 3200 25 1 SLICEL 280 5 2 X General Statistics Instances Rectangles Attributes Device x X Project Summary x pere Tcl Console Au 00X a INFO HD UCFReader 1 Finished Parsing UCF File PlanAhead srcs constrs_l imports top_m1605 ucf INFO HD LIB 0 Reading timing library C Xilinx 12 1 ISE DS Plan head parts xilinx virtex6 virtex6 lib is aw INFO HD LIB 1 Done reading timing library C Xilinx 12 1 ISE DS PlanAhead parts xilinx virtex6 virtex6 lib A resize pblock pblock reconfig blue add SLICE X92Y147 SLICE X101Y154 locs keep all replace imi resize pblock pblock reconfig blue add SLICE X92Y155 5LICE X101Y159 locs keep all pl ra la inaia ES p EEEE x Be a u EJ Tel Console 5 Reports r Design Runs Partial Reconfiguration Flow Figure 4 14 Drawing a Pblock for a Reconfigurable Partition The Clock Region boundaries in the device view can be used as a guide when shaping the reconfigurable region For more recommendations for floorplanning reconfigurable regions see Con
67. T from icap MAXDELAY 15 ns NET busy from icap MAXDELAY 15 ns NET write to icap MAXDELAY 15 ns NET ce to icap MAXDELAY 15 ns In this example the to icap and rom icap networks are buses of any width The asterisk represents the entire bus that is 0 1 2 The NET MAXDELAY constraint constrains only the net delay It does not take the setup time or clock to out time into consideration The ICAP component cannot be added to time groups because it is not considered a synchronous element Therefore the ICAP cannot be made a synchronous component by use of a TPSYNC constraint The ICAP component is a special type of component and must given special consideration for timing when it is used in a design Extracting Partition Pin information Partition Pins are added by the implementation tools and do not exist in the logical source design Partition Pins are named in a predictable fashion but to be absolutely sure that the correct names are used the design must be run through implementation The Partition Pin placement can then be extracted from an implemented design using the pr2ucf utility Run the utility on the placed and routed NCD file within the Configuration directory pr2ucf design routed ncd o Partition pins ucf The PIN location constraints can be back annotated to the design UCF file by copying them from the partition pins ucf file to the design ucf file though this is not necessary
68. UR RE RE E rd dE Rd 14 Frane 2 ve VERS WERE eek ee bk Ok Be let ali A pd RE E 14 Internal Configuration Access Port ICAP ne 14 Partial Reconfiguration PR eee eras serius 15 Partition mi pi caca ke eere a aa pai Ree ae a REGN RP Ra ee Rad fa 15 Partition Pili ke cer RR PROPRES gg pa aid aia p MR a E 15 Proxy LOGIC C EE 15 Reconfigurable Logic n a sine meme ne e E Ser er bag ce eus 15 Reconfigurable Module RM II 15 Reconfigurable Partition RP eee 15 Static LOGIC 0 C 15 Partial Reconfiguration Design Criteria for ISE12 1 16 Design Requirements and Guidelines 0 0 ee 16 Design Pertormandce ni ies i ati nn Pd ea ee eee eee ai 16 Design Considerations ms nica civ cae e De aaa da ati Sd ta ae d 17 Chapter 2 Common Applications Basic Premise of Partial Reconfiguration ccmc 0c eee eee 19 Networked Multiport Interface ce eee 19 Configuration by Means of PCIe Interface 0 00 eee eee 21 Dynamically Reconfigurable Packet Processor 0 0 02000 22 Asymmetric Key Encryption 0 0 6 0 cece ee 23 SD RA 1097 odo ceia de ieee ceeded di aa dd DER A cd ea Ree eeu ua 24 Chapter 3 Software Tools Flow About the Software Tools Flow sees 25 Example Design Structure cecidere a d ECCE REX E e a 27 Partial Reconfiguration User Guide www xilinx com UG702 v 12 1 May 3 2010 Chapter
69. analyzed path from partition pin to static PAD Path Analyzed red partition Partition pin red d out 5 d out 5 PROXY out bram 5 PAD X12029 Figure 3 9 Path from Partition Pin to static PAD In the following example a PERIOD constraint was applied to the static VGA vgaclk2 i clock signal and a related PERIOD constraint was applied to the VGA_CLK clock signal both of which are in the static region of the design The source and destination of this path are FFs in the static region however the path between the source and the destination passes through proxy logic into a Reconfigurable Partition back through more proxy logic leaving the Reconfigurable Partition and finally to a FF in the static region The name of the first Partition Pin for this specific path is www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Report Files red VGA_in7 indicating that the Partition name is red and the port name is VGA_in7 The name in the second Partition Pin for this specific path is red VGA_out7 indicating that the Partition name is red and the port name is VGA out7 The analysis in the following file snippet shows the entire path being taken into consideration including the propagation delay in the Partition Pins There is a violation on this path and this violation could be resolved by adding registers inside the Partition A fully combinatoria
70. and Line Scripting eee 83 TCE Scripts 1 apt n e e od to EE E e i A Ra d 83 Data tcl Format ecce t a ta HER RR Eee gre a 84 Section 1 Set Project Options mean 84 Section 2 Specify Modules for Synthesis and Define Partition Attributes 85 Section 3 Define Configurations ssssssss eh 86 Section 4 Implementation Options eee eee 88 Recommended Flow usssssse RR ene ees 89 Required Files and Directory Structure 0 000 0 cee eee 90 RM Directories NER ETE T TET T NU TM 90 Configuration Directories nenea 91 Export Directories i23 s e in acer ge ke aa a e e dc e ce Med der rcm a ea 92 Chapter 6 Configuring the FPGA Device About Configuring the FPGA Device ccm eee 93 Configuration Modes 1 1 55 iad seceta et i een CLE EC H4 Ca Edi CA RE E a 94 Downloading a Full Bit File 95 Downloading a Partial Bit File ccme sese eese 95 System Design for Configuring an FPGA Device Luuutuuuuuusse 96 Partial Bit File Integrity iiia odds bed retard da rar Ra oe ber dd iod 97 Partial Bitstream CRC Checking cei n te iei euin rp ot E NOCERE AIR RU Re 99 Configuration Frames sisse en 100 Configuration EHE osi de poe oa e e ee E er ua x e do edi 100 Configuration Debugging 0 101 Chapter 7 Design Considerations About Design Considerations 0 00 ee 105 Design EDerameby sepi cepa ap i re ete bie a d ia ee oe ea
71. ast Implement 4 reconfig red red fast Implement 555 4 Not started gt FSF 4 Not started gt BB 4 Not started _ amp Sources Timing Co E Physical C Configu 3 Netlist Figure 4 23 Initial Configurations Controlling Configurations Traditional Plan Ahead software analysis capabilities such as timing analysis and design exploration with the schematic can be used to explore the various Configurations 1 Use the Load Configuration command in the popup menu in the Configurations pane to load the netlist for analysis as shown in Figure 4 24 This makes the RMs for that Configuration active in the Netlist window 74 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Controlling Configurations Configurations Not started Not started Static Logic Promote Partitions reconfig_blue reconfig_green reconfig_red verify Configuration gt FSF 4 Load Configuration gt BB 4 Unpromote Configuration Export to Spreadsheet _ Sources Timing Co E Physical C Configu j Netlist Figure 4 24 Loading an Existing Configuration Once implementation and constraint settings have been settled upon Configurations can be implemented 2 Right click the Configurations in the Design Runs tab and choose the Launch Runs command You can also launch the Active design run by c
72. ations for timing management in Chapter 3 Software Tools Flow BUFRs require Partition Pins in Virtex 5 In the EA solution BUFRs had several restrictions but the network did not require Bus Macros In the ISE 12 solution Partition Pins are added to the BUFR networks to meet clock region pre routing requirements This is only true for Virtex 5 Migrating a Design EA designs can easily be migrated to the ISE 12 solution The first step is to remove or replace the Bus Macros in the HDL and regenerate resynthesize the appropriate netlists Once the netlists are correctly set up a new PlanAhead project must be created in the ISE 12 solution Do not attempt to directly migrate a 9 2 04i PlanAhead project to 12 1 PlanAhead Bus Macro Removal The first step in design migration is removal of the Bus Macros and this is done in HDL There are two general ways to remove BMs e Remove Bus Macro Instantiations PRO Leaves cleaner HDL CON This is time consuming and must be done for all instances e Redefine Bus Macros PRO This is the fastest way to replace large numbers of BMs CON This leaves BM instantiations littered throughout a design If you fail to make any attempt to remove the BMs and remove the BM NMC files then you will receive the following error in Translate NGDBuild ERROR NgdBuild 604 logical block my RP my BM GENERATE 7 my BM with type busmacro xc5v async enable could not be resolved A pin
73. be modified Implementation Run Properties Og x amp 9 RI gt config 1 Static Logic Implement reconfig blue blue fast Ea Implement reconfig green green fast Implement reconfig red red fast Implement General Options Monitor Reports Messages Partitions Figure 4 19 Defining the Reconfigurable Modules in a Configuration Implementation run properties can be modified by selecting them in the Options tab or by selecting the Implementation Settings selection in the Flow Manager See Figure 4 20 72 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Creating Configurations fe Implementation Settings x i Change implementation options and launch the run Options Part xc6vlx240tff 1156 2 active l Constraint Set i constrs 1 active Options 1s Defaults ISE 12 l Launch Options Launch on local host tsunami l Specify Partitions reconfig_blue blue_Fast reconfig_green green_Fast reconfig_red red_fast l i Save Cancel Figure 4 20 Setting the Properties of an Implementation The Configurations View shows the Configuration and the RMs that it contains as well as their status as shown in Figure 4 21 Configurations ELLE PT pe a SEE B Configuration Module variant status config 1 4 Mot started Static Logic Implement reconfig blue blue fast Implement reco
74. be used to differentiate instances 3 Provide the path to the NGC file The Reconfigurable Module appears underneath the Reconfigurable Partition in the Netlist pane as shown in the following figure set Partition EU xj Specify Top Netlist File Specify the EDIF or NGC netlist that contains the Reconfigurable Module s Top Netlist File C PRdesigns Color2 Implementation Blue_Fast rm_blue nagc Netlist directories optional Add Directories Remove Down v Copy Sources into Project lt Back Next gt Cancel Figure 4 8 Partition Defined as Reconfigurable with a Single Reconfigurable Module Added Partial Reconfiguration User Guide www xilinx com 65 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX If additional netlists that exist in other directories must be specified enter those search paths here Also constraint files that contain physical constraints for this particular Reconfigurable Module may be specified in the next dialog box After the Reconfigurable Partition has been defined the PlanAhead software creates a Pblock for the RP if one does not already exist as shown in Figure 4 9 Physical Constraints og x TA netlist 1 EJ ROOT pblock reconfig blue _ amp Sources j Netlist El Physical Constr Timing Constraints Figure 4 9 Pblock Defined Automatically for a Reconfigurable Partition
75. but use Verilog syntax Create a PlanAhead Project in 12 1 Summary To create this project follow the instructions in Creating a Partial Reconfiguration Project in Chapter 4 If the Redefine Bus Macro process was used then the BM replacement netlists need to be included as static logic source files for PlanAhead when the project is created Designs created and implemented with the Modular Design Early Access Partial Reconfiguration tools can be easily converted to the Partition based ISE 12 solution Bus macros must be removed or replaced decoupling logic should be considered and Modular Design specific options can be removed In no time at all you will be implementing designs with the latest Partial Reconfiguration software 126 Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 www xilinx com
76. configurable Software tools such as Ngdbuild Map and Par detect the Reconfigurable Partition attribute on the instance and process it correctly The term Reconfigurable Partition is often used interchangeably with instance if the instance is a Reconfigurable Partition Static Logic Static Logic is any logical element that is not part of a Reconfigurable Partition The logical element is never partially reconfigured and is always active when Reconfigurable Partitions are being reconfigured Static Logic is also known as Top level Logic Partial Reconfiguration User Guide www xilinx com 15 UG702 v 12 1 May 3 2010 Chapter 1 Introduction XILINX Partial Reconfiguration Design Criteria for ISE 12 1 Partial Reconfiguration PR is an expert flow within the ISE Design Suite While many significant advances have been made within this software prospective customers must understand the following requirements and expectations before embarking on a PR project 16 Each of the topics below is covered in greater detail in later sections of this User Guide Design Requirements and Guidelines Partial Reconfiguration requires the use of ISE 12 1 or newer Device support Virtex 4 Virtex 5 Virtex 6 Virtex 6 support is for LXT CXT devices only in 12 1 Virtex 6 HXT and Virtex 6 SXT support will be added in later releases Spartan class support will be introduced for the next generation of Xilinx FPGAs PR is support
77. ctive at the time the constraints were created and will be added to PlanAhead Generated RM UCF they will not show up in the top level target UCF Instead it is recommend to manually add these constraints to each user defined RM UCF and then update the RM using the Update Reconfigurable Module command PlanAhead UCF Recommendations There are rules regarding UCF constraints that should be followed when using the PlanAhead flow Note that these rules will likely change as the constraint management system is modified in future releases of PlanAhead However for the 12 1ISE software these rules should be followed Use the Copy into Project option when specifying UCFs for a PlanAhead project PlanAhead does some manipulation of RM constraints that are read into the tools Following this rule will ensure that any changes done by PlanAhead only affect a local copy of the UCE Put all RM constraints into RM specific UCF files Putting RM constraints into the top level UCF or using the GUI to create RM UCFs can lead to undesirable behavior PlanAhead UCF Known Issues If the top level UCF contains RM specific constraints they will not be loaded properly until the RMs have been defined for appropriate RPs If this occurs the Netlist Design will need to be closed and reopened after the RM netlists have been added This is a known issue that will be fixed in a future release but can be avoided by following the recommendations above The Netlis
78. d from the Implementation folder of a PR project as described in Chapter 3 Software Tools Flow tclsh84 Tools xpartition tcl Tools data tcl Data tcl Format The data tcl file is divided into three main sections The data tcl uses to mark comments outside of list or array declarations Members of lists and arrays must be deleted or commented outside of the list or array to have them be ignored Section 1 Set Project Options Section 1 Set Project Options lets you set variables including environment variables part constraints file Partitions and Reconfigurable Modules 1 environment variables for all configurations set env XIL TIMING ALLOW IMPOSSIBLE 1 2 part definition set PART xc5vl1x50t 3 ff1136 3 constraints file set UCF Source UCF top_m1505 ucf 4 Partition names These names must match the actual instance names in the design set TOP_PART top set RED_PART TOP_PART reconfig_red set GREEN PART TOP_PART reconfig_green set BLUE PART S TOP PART reconfig blue 5 RM names set RED FAST Red Fast set RED SLOW Red Slow set RED BB Red Blank set GREEN FAST Green Fast set GREEN SLOW Green Slow set GREEN BB Green Blank E FAST Blue Fast set BLU set BLUE SLOW Blue Slow set BLUE BB Blue Blank set STATIC Static 1 environment variables for all configurations Define any environment variables that are required for implementation here using the forma
79. d must be done for each Reconfigurable Module This strategy is supported for the CORE Generator flow only The ChipScope Core Inserter software modifies the design at the netlist itself rather than the HDL source This flow is supported in PlanAhead but probe points are limited to signals that exist in the static logic If an attempt to probe logic in a Reconfigurable Module is made the tool reports that this modification changes the Partition interface and is therefore not allowed EDK System Generator for DSP and CORE Generator When using advanced tools and IP from Xilinx or third party sources rules similar to those for ChipScope Pro software must be followed Because these tools build and modify designs at the HDL or netlist level they work smoothly with a bottom up synthesis approach required by the Partial Reconfiguration flow Considerations must be made for the definition of the reconfigurable regions to ensure the proper elements are contained within and for timing in and out of the Reconfigurable Partition but other than these general requirements these tools will work well with Partial Reconfiguration One significant consideration for use of Partial Reconfiguration with advanced tools and IP is the contents of these design blocks No global clocks or clock modifying logic BUFG DCM PLL etc may exist in any module to be reconfigured Like the ChipScope ICON core certain blocks will be required to remain in static logic i
80. de UG702 v 12 1 May 3 2010 XILINX Configuration Debugging MAI Es d ad ee Ei 2 78 ijlEE cep TT EE Figure 6 6 ChipScope Display for Partial Reconfiguration The markers in the ChipScope display indicate the following 1st done This marker indicates the completion of the initial full bitstream configuration The DONE pin done pad in this waveform goes High cfgerr This marker indicates a CRC error is detected while loading partial bitstream The status can be observed through O 31 0 icap_o_top 31 0 in the waveform Icap o top 31 0 starts at Ox9F After seen SYNC word Icap o top 31 0 change to 0xDF After detect CRC error Icap o top 31 0 change to 0x5F for one cycle and then switches to 0x1F RCRC This marker indicates when the partial bitstream is loaded again The RCRC command resets the c gerr status and removes the pull down on the INIT B pin init pad in this waveform Icap o top 31 0 change from Ox1E to Ox5F when the SYNC word is seen Icap o top 31 0 change from 0x5F to OxDF when RCRC command is received pr done This marker indicates a successful Partial Reconfiguration Icap o top 31 0 change from OxDF to 0x9F when the DESYNC command is received and no configuration error is detected Partial Reconfiguration User Guide www xilinx com 103 UG702 v 12 1 May 3 2010 104 Chapter 6 Configuring the FPG
81. e and the XILINX variable does not point to an installation area of an older release of ISE tools To set the project as a PR Project e Select File gt Set PR Project Once a project is set as a PR project it must not be used for flat ISE implementation The interface and options are intended to work with the PR software features and may impose unnecessary restrictions on flat designs Selecting the option modifies the PlanAhead interface specifically for a PR design Additional commands are available in the Netlist view popup menu to set instances as Reconfigurable Partitions and to add additional Reconfigurable Modules for an instance When this option is selected the bottom right status bar changes from Post Synthesis Flow to Partial Reconfiguration Flow as shown in Figure 4 4 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Opening the Netlist Design GJ Planahead Netlist Design C PRdesigns Color2 PlanAhead PlanAhead ppr PlanAhead 12 1 MRO ioj xj Fie Edit View Flow Tools Window Select Layout Help go di amp 6 Z D E OFA GG Wu Ready Design Planner 1 0 Planner Project Manager 2 Netlist Design E Resource Estimation Run prc 7 Primitives 26 3 mmem clocks clock E reconfig blue l E reconfig_green r E reconfig_red 6 E static DVI a static_DVI_IF il a static IIC INIT c ini
82. e EI XFFF E xsss C3 PlanAhead runs 5 Plandhead sres FH O constrs_1 O sources 1 H Source O Tools Figure 4 35 PlanAhead PR directory structure This structure is very similar to the PlanAhead software project directory with some extensions The netlists for all static logic are found in the sources directory and the netlists for all reconfigurable modules are kept in the sources_1 directory The netlists for RMs are in the pr modules subdirectory where each RP has its own subdirectory The implementation runs including bit files are found in the PlanAhead runs directory under the appropriate floorplan and Configuration Promoted configurations are placed in the PlanAhead promote directory and prepended with the letter X Partial Reconfiguration User Guide www xilinx com 81 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support 82 www xilinx com XILINX Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 5 Command Line Scripting This chapter discusses Command Line Scripting and includes About Command Line Scripting TCL Scripts Data tcl Format Recommended Flow Required Files and Directory Structure About Command Line Scripting Xilinx provides a set of example TCL scripts to define and implement a Partition based Partial Reconfiguration Design These scripts work for a general
83. e details of each Configuration and the order in which they must be implemented 8 Configuration Information FEFE EAE HE HE E FE E HE HE HE E FE HE FE FE FE HEHE HE HE FE HE FE HE AE E FE HE FE FE HE HE AE HE AE FE HE FE FE AE HE AE FE HE FE HE FE HE AE FE HE TE HE FE HE FE HE AE HE EEE EEE EEE EE Create the per configuration variables The format is set CONFIG1DATA lt ConfigList gt set CONFIG2DATA lt ConfigList gt set ALL CFGS list CONFIG1DATA CONFIG2DATA where lt ConfigList gt lt ConfigNamePair gt lt Settings gt lt ConfigNamePair gt ConfigName lt Name gt lt Settings gt Settings lt SettingsList gt ii lt SettingsList gt lt PartSettingsList gt lt PartSettingsList gt lt partitionName gt lt namevalpair gt EE E HE HE FE E TE HERE HE FE HE TEE HERE HE FE HE FE HE FE RETE HE HE HE FE HE HE HE E FE HE FE E FE HE FE HE FE HE HE HE HE HE HE HE HE FE HE FE FE FE HE HE HE HERE RETE HE FE HE FE HE FE HEH EHH HHH Configuration FastConfig settings Everything is implemented there is no import location set CONFIG_FastConfig ConfigName FastConfig Settings top State implement top reconfig_red State implement NetlistDir Red_Fast ModName Red_Fast top reconfig green State implement NetlistDir Green_Fast ModName Green_Fast top reconfig_blue State implement NetlistDir Blue_Fast ModName Blue_Fast Configuration SlowConf
84. e examples of XST Verilog and XST VHDL XST Verilog example top level HDL module top clk reset data in data out port in port out input clk reset data in buffer type none input port in output data out buffer type none output port out XST VHDL example top level HDL entity top is port clk in std_logic reset in std_logic data in in std logic data out out std logic port in in std logic port out out std logic attribute buffer type string attribute buffer type of port in signal is none attribute buffer type of port out signal is none end my rm e Synplicity Synplicity supports this capability through the syn black box and black box pad pin directives The approach here is different all of the ports are still listed at the top level but Synplicity is informed at the black box module definition that the IO buffer is found in the submodule still in the top level HDL As with XST any reconfigurable IO logic must be instantiated in each Reconfigurable Module variant The following code snippets are an example Synplicity Verilog file and a Synpilicity VHDL respectively 108 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Design Hierarchy Synplicity Verilog example reconfigurable module declaration within Top level HDL module my_rm clk reset data_in data_out port_in port_out synthesis s
85. e needs of all Reconfigurable Modules For a description of how to solve placement and routing problems during implementation see Debugging Placement and Routing Problems in Chapter 3 Simulation and Verification Configurations of Partial Reconfiguration designs are complete designs in and of themselves All standard simulation timing analysis and verification techniques are supported for PR designs Partial reconfiguration itself cannot be simulated Using High Speed Transceivers Xilinx high speed transceivers GT11 GTP GTX have dedicated connections to many of their pins These dedicated connections require that the IO connected to these pins be handled differently than general purpose IO For the tools to recognize the direct connection the transceivers and all associated IO logic must be contained within the same Partition This includes all the pads and buffers as well as all transceiver logic Interaction with Other Xilinx Tools 116 This section discusses Interaction with Other Xilinx Tools and includes e ChipScope Pro e EDK System Generator for DSP and CORE Generator ChipScope Pro ChipScope Pro analyzer inserts logic analyzer bus analyzer and virtual IO low profile software cores directly into a design allowing you to view any internal signal or node including embedded hard or soft processors Instrumentation of designs can be done by means of two methods the Xilinx CORE Generator soft
86. ed and thus disable all ports every possible interface protocol is implemented for every port as illustrated in Figure 2 1 Partial Reconfiguration User Guide www xilinx com 19 UG702 v 12 1 May 3 2010 Chapter 2 Common Applications g XILINX 10 GigE tx rx OC48 trx Pori 10 GigE tx rx Port 2 OCA48 tx rx Switch Fibre bun Fabric 10 GigE tx rx Port 3 OC48 tx rx a 10 GigE tx rx Port 4 OC48 tx rx X12002 Figure 2 1 Network Switch Without Partial Reconfiguration This is an inefficient design because only one of the standards for each port is in use Partial Reconfiguration enables a more efficient design by making each of the port interfaces a Reconfigurable Module as shown in Figure 2 2 page 20 This also eliminates the MUX elements required to connect multiple protocol engines to one port Config Memory Storage 10GigE tx rx OC48 tx rx Fabric Port 3 X12003 Figure 2 2 Network Switch With Partial Reconfiguration A wide variety of designs can benefit from this basic premise Software Defined Radio SDR for example is one of many applications that has mutually exclusive functionality 20 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Configuration by Means of PCle Interface and which sees a dramatic improvement in flexibility and resource usage when this functionality is multiplexed There are additional advantages with a partially reconfigurable d
87. ed via PlanAhead or command line only there is no Project Navigator support Floorplanning is required to define reconfigurable regions per element type For greatest efficiency align to frame clock region boundaries when possible Bottom up synthesis to create multiple netlist files and management of reconfigurable module netlist files is the responsibility of the user Synthesis done outside of PlanAhead any synthesis tool may be used Decoupling Logic is highly recommended to disconnect the reconfigurable region from the static portion of the design during the act of Partial Reconfiguration Ifthe reconfigurable element is an output of the FPGA the decoupling should be performed off chip Standard timing constraints are supported and additional timing budgeting capabilities are available if needed A unique set of Design Rule Checks has been established to guide users on a successful path to design completion A PR design must consider the initiation of Partial Reconfiguration as well as the delivery of partial bit files either within the FPGA or as part of the system design Not all implementation options are available to the PR flow The g1obal opt option to the MAP command and its child options the power option to the MAP command and SmartGuide cannot be used with Partitions or PR since these techniques perform optimization across the entire design Design Performance Performance metrics will vary
88. ely constrain the entire design you must supply constraints for both the static and reconfigurable portions of the design This can be done in a number of ways The static logic is controlled by any constraints in the top level netlists and the main UCFs supplied to the PlanAhead software or the Tcl scripts Constraints such as IO location constraints to be shared across all variants of the Reconfigurable Partitions must be included in the top level UCFs If constraints apply only to specific Reconfigurable Modules they may be supplied in one of three different methods e As part of the netlist itself Because synthesis tools can embed constraints within the design netlist these constraints are read in with the rest of the contents of that file e Ina UCF placed alongside the RM netlist After a run has been defined it resides below the PlanAhead project in this location lt project gt lt project data gt netlists netlist_1 pr_modules lt RP gt lt RM gt Place the UCF file in this folder with the same name as the EDF file that exists there and it is used automatically when that RM is used in a Configuration The constraints in this UCF must be scoped to the top level references to instances within the RM must have the full hierarchical path to the instance e Ina UCF to be merged with the RM netlist using ngcbuild Ngcbuild can be run on the command line to merge netlists and constraints For more information see Design Hie
89. eneral Statistics Instances Rectangles Attributes Figure 4 16 Applicable Targets for Range Constraints in a Reconfigurable Partition 70 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Running Partial Reconfiguration Design Rule Checks Running Partial Reconfiguration Design Rule Checks A set of developed Design Rule Checks catch violations of the rules for a PR design 1 From Tools gt Run DRC enable or disable the DRCs in any category 2 Run these checks periodically to ensure that the design work does not violate any basic premises of Partial Reconfiguration Figure 4 17 shows a list DRCs for Partial Reconfiguration or Partitions xi Results Name resuts 1 Output File l Rules to Check 13 of 69 1 E Partition 9 iv Partial Reconfig 13 Mi Reconfigurable instances must have a Slice range iv At least one reconfigurable region PRPR iv Reconfigurable modules exist For each reconfigur iv Overlapping reconfigurable regions PROL MI Glitching logic LOC above and below PR GL MI Glitching logic block above and below PR GE iv IO LOCs PRIL Mi Reconfigurable instances must have a valid regio iv Global clock inside reconfigurable module PREC iv Illegal logic inside reconfigurable module PRLO Mi Regional clock inside Reconfigurable Module PRF iv All reconfigurable modules implemented PRSC MI PR static logic illegally placed PRLL gt
90. er designs If a name is misspelled or otherwise incorrect no error messaging is returned to communicate that mistake back to the user Closely examine the report files to ensure all the correct files and settings have been applied during the synthesis and implementation runs Known Limitations Following are known limitations Support for Virtex 6 devices in the 12 1 software release is for the LXT family only No Spartan device families are supported by Partial Reconfiguration software Encrypted partial bitfiles by means of Bitgen g encrypt are not supported Bi directional Partition Pins are not supported the interface between static and reconfigurable logic must use unidirectional pins only Partial Reconfiguration User Guide www xilinx com 119 UG702 v 12 1 May 3 2010 Chapter XILINX 120 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Appendix B Partial Reconfiguration Migration Guide Overview This appendix includes e Overview e Differences Between the Early Access and Production Solutions e Migrating a Design e Summary This Partial Reconfiguration PR Migration Guide provides step by step instructions to migrate designs created with the 9 2 04i Modular Design Early Access PR EA solution to the Partition based ISE 12 solution described in this User Guide Differences Between the Early Access and Production Solutions
91. erage FPGA design project A clearly defined file and directory structure eases the task of project management There are multiple Reconfigurable Modules for each Reconfigurable Partition in the overall project The modules are synthesized in a bottom up fashion resulting in many netlists associated with each Reconfigurable Partition The implementation is then done top down which defines a specific set of netlists called a Configuration To eliminate confusion between sources constraints synthesis results and implementation results separate directories are recommended for each step in the design implementation A commonly used though not required directory structure for a PR design is shown in the following file snippet project name name of the overall project Docs user or design documents Implementation Xilinx software implementation results modules static or Reconfig Module netlists configurations Configuration implementation results Source source files modules HDL source files for static and Reconfig Modules UCF a constraint files Synth synthesis results modules netlists for each static and Reconfig Module Tools Tcl scripts or any other user scripts Given the Color2 design described in the file a directory structure that is flow based could be as shown in the following file snippet
92. ertain connections require specific routing resources from one design element to another If a Partition boundary crosses this connection a failure occurs once the proxy logic has been inserted on that path For these situations the implementation tools must be instructed to skip the proxy logic insertion This is done by applying the PARTITION_PIN_DIRECT_ROUTE UCF constraint to the Partition Pin of the route in question Following is an example of the error message and UCF syntax ERROR NgdBuild 1319 Detected a controlled route on Partition Pin aurora 201 i TX CLK OUT The connection between GTP DUAL pin aurora 201 i aurora mod i GTP DUAL INST TXOUTCLKO0 in Partition fpga chip top aurora 201 i and DCM ADV pin aurora 201 clk mod i clock divider i CLKIN in Partition fpga chip top should reside within the same Partition If this is not possible create the following constraint and run pr verify to validate that this route is the same in each configuration PIN aurora 201 i TX CLK OUT PARTITION PIN DIRECT ROUTE TRUE As noted in the message the complete controlled route and therefore the same pair of source and destination elements must exist in each Reconfigurable Module to ensure that no dangling wire is created Because of this detail controlled routes are not allowed for black box Reconfigurable Modules 114 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3
93. es which Slices are part of the PR region The Slice contains the basic LUT and FF logical elements If the RMs also contain block RAM IO or other types of logical components then additional range constraints must be created for them There are a few requirements when setting AREA GROUP RANGE constraints e AREA GROUP RANGE constraints are required for each Reconfigurable Partition as they define the size and shape of those regions e All device resources such as Slices IO BRAM DSP blocks and Multi Gigabit Transceivers MGTs that are part of any Reconfigurable Module that are placed in that Reconfigurable Partition must each have corresponding AREA GROUP RANGE constraints Even single site resources must have an associated RANGE constraint e Do NOT create AREA GROUP RANGE constraints for elements that should not be or are not allowed to be reconfigured For example do not create AREA GROUP RANGE constraints for DCM PLL or BUFG elements e Ifa single Reconfigurable Partition is defined by multiple AREA GROUP RANGI constraints they must be contiguous Lj e The AREA GROUP RANGE constraints of a given Reconfigurable Partition must not overlap the AREA GROUP RANGE constraints of any other Reconfigurable Partition e PR Slice regions should be defined from the lower left corner minX minY to the upper right corner maxX maxY For example INST reconfig red AREA GROUP pblock reconfig red
94. esetting the entire FPGA device is not critical or the partial bit file is stored locally In that case the chance of bit file corruption is not appreciable Systems where the bit files have a risk of becoming corrupted such as sending the partial bit file over a radio link should contain design circuitry to mitigate the problem One possibility is to process the partial bit file locally in the FPGA fabric immediately before it is loaded into the ICAP to partially reconfigure the device The static logic of the FPGA design could contain a circuit that analyzes the partial bit file before it is sent to the ICAP If an error is detected the Partial Reconfiguration is stopped and retried or a known good partial bit file is loaded instead Figure 6 4 illustrates this process Buffer CRC Verify Host Bit Files ICAP X12034 Figure 6 4 Partial Bit File Error Detection The partial bit file contains CRC information that can be used to check integrity or you may generate custom CRC information and send it with the partial bit file This scheme is similar to the Asymmetric Key Encryption application described in Chapter 2 Common Applications 98 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Partial Bitstream CRC Checking Partial Bitstream CRC Checking Because a partial bitstream is being loaded into an active design and because the built in CRC check does not occ
95. esign other than efficiency In the Figure 2 2 example a new protocol can be supported at any time without affecting the static logic the switch fabric in this example When a new standard is loaded for any port the other existing ports are not affected in any way Additional standards can be created and added to the configuration memory library without requiring a complete redesign This allows greater flexibility and reliability with less down time for the switch fabric and the ports A debug module could be created so that if a port was experiencing errors an unused port could be loaded with analysis correction logic to handle the problem real time In the Figure 2 2 example a unique partial bit file must be generated for each unique physical location that could be targeted by each protocol Partial bit files are associated with an explicit region on the device In this example sixteen unique partial bit files to accommodate four protocols for four locations A possible future enhancement of Partial Reconfiguration could allow bit files to be relocatable to different physical locations Configuration by Means of PCle Interface Partial Reconfiguration can create a new configuration port utilizing an interface standard more compatible with the system architecture For example the FPGA device could be a peripheral on a PCIe bus and the system host could configure the FPGA through the PCIe connection After power on reset the FPGA device must be co
96. f they contain non reconfigurable design elements Partial Reconfiguration User Guide www xilinx com 117 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations XILINX 118 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Appendix A Known Issues and Known Limitations This appendix includes Known Issues Known Issues Known Limitations For a complete listing of Partial Reconfiguration Known Issues see Answer Record 35019 Known Issues are Reconfiguration of Virtex 6 BlockRAM not properly inserted into partial bit files When partial bitstreams are generated incorrect data is written for the Block Rams within a Reconfigurable Module There is a patch available for the 12 1 software This issue is documented in Answer Record 35399 PlanAhead frame statistics not shown for Virtex 6 In PlanAhead details for a Reconfigurable Partition are shown in the Pblock Properties window the Statistics tab shows the number of frames regions covered by that Pblock and the estimated bitstream size for the Reconfigurable Partition This information is missing for Virtex 6 devices but does exist for Virtex 4 and Virtex 5 devices Typos in Tcl scripts might be silently ignored When using the sample Tcl scripts supplied with the Color2 design names of instances such as Configurations Reconfigurable Modules and paths must be modified to accommodate us
97. figurations to ensure that all static constraints are identical There may be module specific constraints that cannot be included in the static logic constraints For example if a timing constraint is set on a path that only exists in red fast then the constraint can only be applied to the First Configuration above This can be accomplished by using PlanAhead to manage the constraint files or by embedding the constraint within the specific module netlist The ngdbuild uc switch can be used multiple times per command line invocation so more than one UCF can be specified per run Area Group Constraints 32 An AREA GROUP is a grouping constraint that associates logical design elements with a particular label or group AREA GROUP constraints and Partition definitions are necessary to delineate the static non reconfigurable logic from the reconfigurable logic preventing logic in the static design from merging with logic in the RMs and vice versa The AREA GROUP constraints must be defined for each Reconfigurable Partition The following example shows an AREA GROUP constraint called pblock_reconfig_red fora Reconfigurable Partition named reconfig red INST reconfig red AREA GROUP pblock reconfig red At least one and possibly more AREA GROUP RANGE constraints must be defined for each reconfigurable region to set the shape and placement of the PR region The primary range constraint is usually a Slice range that defin
98. file Partition A Partition is a logical section of the design defined by the user at a hierarchical boundary to be considered for design reuse A Partition is either implemented as new or preserved from a previous implementation A Partition that is preserved maintains not only identical functionality but also identical implementation Partition Pin Partition Pins are the logical and physical connection between static logic and reconfigurable logic Partition Pins are automatically created for all Reconfigurable Partition ports Proxy Logic Proxy Logic is a single LUT1 element automatically inserted by the software for each Partition Pin except for dedicated routes Proxy Logic is required to be a fixed known point as an interface between static and reconfigurable logic Reconfigurable Logic Reconfigurable Logic is any logical element that is part of a Reconfigurable Module These logical elements are modified when a partial bit file is loaded Most types of logical components may be reconfigured such as LUTs Flops BRAM DSP blocks and IO Reconfigurable Module RM A Reconfigurable Module RM is the netlist or HDL description that is implemented when instantiated by an instance that is a Reconfigurable Partition There may be multiple Reconfigurable Modules for one Reconfigurable Partition Reconfigurable Partition RP Reconfigurable Partition RP is an attribute set on an instantiation that defines the instance as re
99. flow and provide a template that can be modified for custom flows A TCL shell must be available to run these scripts Many Linux distributions have TCL installed in the usr bin directory which is found by default If a TCL shell is not installed you can download one for free from http www activestate com activetcl The scripts in this Guide have been tested with TCL 8 4 TCL Scripts xpartition tcl Defines and implements a Partition based Partial Reconfiguration Design It calls three other TCL scripts to perform these functions Xilinx recommends that this script be used to run the complete flow gen xp tcl Creates and or modifies the necessary Partition files for each project Itis called by the xpartition tcl script implement tcl Implements a Partition based PR Configuration It is called from the xpartition tcl script export tcl Exports the necessary files to import a Partition into future runs It is called from the xpartition tcl script The xpartition tcl file takes a data tc1 file as an argument The data tc1 file contains Partition definitions Configurations and options for implementation This file allows for modification of the design and its options without changing the TCL scripts Partial Reconfiguration User Guide www xilinx com 83 UG702 v 12 1 May 3 2010 Chapter 5 Command Line Scripting XILINX Following is a sample command line calling the TCL scripts This is launche
100. for all Configurations To customize the command line tools use the following three variables The default for all three variables is to use the default implementation options For more information on available command line options see UG628 the Command Line Tools User Guide e NGDBUILD OPTS ngdbuild options Optional NGDBuild command line options e MAP OPTS map options Optional MAP command line options e PAR OPTS par options Optional PAR command line options These options apply to implementation of all Configurations To specify different command line options for a specific Configuration use the f option to select a command file in each directory For example MAP OPTS lt f map opt gt Looks fora map opt file in the directory for each implementation and uses the options in it For more information on the f option see UG628 the Command Line Tools User Guide Recommended Flow Currently these scripts do not run pr verify although this is being investigated for a future release You must still run pr verify prior to configuring the device with the generated bitstreams The recommended method to incorporate this step into the flow is 1 Run the complete flow including bitgen using the TCL scripts 2 Runthepr verify command line prior to configuring the device If the log reports PASS you are safe to use the generated bitstreams For more information on running pr
101. from design to design and negative effects will be minimized by following the Hierarchical Design techniques documented in UG748 Hierarchical Design Methodology Guide and WP362 Repeatable Results with Design Preservation However the additional restrictions that are required for silicon isolation are expected to have an impact on most designs In general Expect 10 degradation in Clock Frequency www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Partial Reconfiguration Design Criteria for ISE 12 1 Expect to not exceed 80 slices in Packing Density Longer Design Runtimes are expected in most cases as these additional requirements are factored into the overall solution Map will display the greatest impact but NGDBuild and Par could also show the effects of processing a PR design Routing challenges may occur if the reconfigurable region is too small or is constructed of non rectangular shapes Design Considerations Most but not all component types can be reconfigured Global Clocks and Clock Modifying Logic must reside in the Static region Includes BUFG MMCM PLL DCM and similar Individual architecture feature components such as BSCAN STARTUP etc should remain in the static region of the design IP restrictions may occur due to components used to implement the IP Examples include ChipScope ICON BUFG EDK blocks with global buffers MIG controller
102. ftware reads the target device from the netlist 3 Confirm that it is correct or adjust it if necessary then click Next to accept the device Add the top level constraints files which should include IO and Timing constraints More than one UCF can be used The PlanAhead software concatenates all top level UCF files along with module level UCF files before launching implementation runs Figure 4 3 displays the New Project gt Constraint Files dialog box B New Project i xj Constraint Files optional Specify LICF File For physical and timing constraints IF there are multiple files then please choose de the target UCF file which is where all of the constraints produced by Plan head will be saved Constraint files optional 83 C PRdesigns Color2 Source UCFitop_ml605 ucF Down Add Files Create File v Copy Sources into Project Cancel Figure 4 3 Constraints Files Dialog Box 5 Click the rest of the way through the Wizard to generate the project Partial Reconfiguration User Guide www xilinx com 61 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support XILINX Setting the Project as a PR Project 62 If you haven t already defined the project as a PR project when the project was created a menu option is used to define the project as a PR project and to enable the PR related commands This option is visible only if a valid Partial Reconfiguration license is availabl
103. gModuleName red_fast gt lt Partition Name top blue Version 2 0 State import ImportLocation XSSS Reconfigurable true ReconfigModuleName blue_slow gt lt Partition Name top green Version 2 0 State import ImportLocation XFFF Reconfigurable true ReconfigModuleName green_fast gt lt Partition gt lt Partition gt lt Project gt The static logic along with the Red and Green modules is imported from the first configuration The Blue module is imported from the second Configuration Implementation To implement the FPGA design run ngdbuild MAP and PAR ina similar fashion to a non PR design Most of the PR specific information is contained in the xpartition pxmlfile and the UCF file There are no PR specific command line switches The following example shows the commands to implement a PR design ngdbuild sd red fast sd blue fast sd green fast uc UCF design ucf Static top edf FFF ngd map w o FFF map ncd FFF ngd FFF pcf par w FFF map ncd FFF ncd FFF pcf Not all Implementation options are available for Partial Reconfiguration Options not available are the g1obal opt option to the MAP command and its child options the power option to the MAP command and SmartGuide Debugging Placement and Routing Problems When a Partial Reconfiguration design is placed and routed see Figure 3 1 e Static routes can route through Reconfigurable Partitions e Routes with
104. gether in the same hierarchical level is necessary These are all well known design practices that are often not followed in general FPGA designs Following these design rules is not strictly required in a partially reconfigurable design but the potential negative effects of not following them are more pronounced The benefits of Partial Reconfiguration are great but the extra complexity in design could be more challenging to debug especially in hardware For additional information about design hierarchy see WP362 Repeatable Results with Design Preservation and UG748 Hierarchical Design Methodology Guide Design Elements Inside Reconfigurable Modules Not all logic is permitted to be actively reconfigured Global logic and clocking resources must be placed in the static region to not only remain operational during reconfiguration but to benefit from the initialization sequence that occurs at the end of a full device configuration Logic that must remain in static logic includes e Clock modifying blocks PLL PMCD DCM e Certain clock buffers BUFG BUFR is permitted in an RM with restrictions as noted in the Clocking Rules section of this chapter e Xilinx recommends that device feature blocks remain in static logic It is possible these elements will function properly after reconfiguration but extensive silicon testing has not been performed These elements include BSCAN CAPTURE DCIRESET FRAME_ECC ICAP KEY_CLEAR ST
105. green fast Attribute STATE set to IMPLEMENT Trce Report The TRCE tool is used to perform static timing analysis on FPGA designs This tool is used for both timing verification and reporting For more information on TRCE usage see the TRCE section of UG628 the Command Line Tools User Guide The Partial Reconfiguration design flow always works with a full design This allows timing analysis to leverage constraints applied to the static region for analysis of an RM that is a PERIOD constraint applied to a clock in the static region performs analysis on the applicable paths in an RM for the current combination The static logic is always analyzed TRCE can generate several output files The following three are of particular interest for examining how well a design meets user defined constraints e TWR an ASCII Timing Report e TWX an XML Timing Report e TSI an ASCII Constraint Interaction Report TWR and TWX timing reports are created with each Configuration run through implementation If additional reports are needed with different options then TRCE can be run from the command line or the options can be changed for that implementation in the PlanAhead software and the implementation can be re run Running static timing analysis on a design that contains Reconfigurable Partitions is the same as running static timing analysis on a regular design However there is a difference in methodology For a
106. gt Promoted runs reside in another folder in the PlanAhead project directory at lt project_name gt promote lt promoted_configuration_name gt In this design example directories XFFF XSSS and XBB can be created for FFF SSS FSF and BB Promotion of FSF is not required or allowed because all of the modules that are used were implemented from other Configurations 78 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Verifying Configurations Verifying Configurations PR verify is a tool that must be called on any combination of implemented Configurations to validate the implementation of the Configurations of the design 1 From the Configurations pane using the popup menu launch PR verify This is an important step in a Partial Reconfiguration design to ensure that all design rules have been met Configurations Og x a SPs S 3 o gt FFF 4 Promoted 3 Static Logic Promoted 454 reconfig blue blue fast Promoted 454 reconfig green green fast Promoted 454 reconfig red red fast Promoted e Static Logic 4 Promote Partitions reconfig blue b Unpromote Configuration 154 reconfig green g 54 reconfig red re _ Verify Configuration zw FSF 4 Load Configuration V BB 4 Export to Spreadsheet gt Sources Timing Co E Physical C 9 Configu Q Netlist
107. guration Chapter 3 Software Tools Flow explains the underlying software tools flow how to build a system that supports a partially reconfigurable FPGA and structure a partially reconfigurable design and the application of constraints Chapter 4 PlanAhead Support details the features and flows within the graphical environment from setting up a PR project and building the variations of a design to final validation of a reconfigurable design Chapter 5 Command Line Scripting gives instructions and recommendations on how to automate the flow through the toolset without the use of a GUI Chapter 6 Configuring the FPGA Device explains the unique requirements for the act of partially reconfiguring an FPGA device Chapter 7 Design Considerations explains design requirements that are unique to Partial Reconfiguration and covers specific PR features within the Xilinx FPGA design software tools Partial Reconfiguration User Guide www xilinx com 9 UG702 v 12 1 May 3 2010 Chapter XILINX Appendix A Known Issues and Known Limitations lists the known issues limitations and resolved issues Appendix B Partial Reconfiguration Migration Guide provides step by step instructions to migrate designs created with the 9 2 04i Modular Design Early Access PR EA solution to the Partition based ISE 12 solution described in this User Guide Additional Resources To find additional documentat
108. he different configuration ports in Virtex architectures have the maximum bandwidths shown in Table 6 1 Table 6 1 Maximum Bandwidths for Configuration Ports in Virtex Architectures Configuration Mode Max Clock Rate Data Width Maximum Bandwidth ICAP 100 MHz 32 bit 3 2 Gbps SelectMAP 100 MHz 32 bit 3 2 Gbps Serial Mode 100 MHz 1 bit 100 Mbps JTAG 66 MHz 1 bit 66 Mbps 100 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Configuration Debugging The Bitstream size as reported in the PlanAhead PR Statistics tab for a Reconfigurable Partition is an accurate estimate of the size of the partial bit file to be created Because this number is given in bytes you must multiply it by 8 to find the bitstream size in bits Example A small partial bit file for a Virtex 5 device contains a region spanning 200 Slices drawn in such a way that it covers 5 Reconfigurable Frames 100 CLBs 5 CLBs wide by 20 CLBs high Before the rawbits xbt file is generated the configuration time can be estimated by using the bitstream size provided by the PlanAhead software which is listed as 29 520 bytes or 236 160 bits Using Select MAP mode or the ICAP this partial bit file could be loaded in about 236 160 bits 3 200 000 000 bps 0 0000738 seconds or about 73 8 microseconds The configuration time scales fairly linearly as the partial bit file size grows with the number of frames w
109. he output of a Reconfigurable Partition The destination is a PAD in the static region The source name for this specific path is red d_out 5 indicating that the Partition name is red and the port name is d out 5 The following analysis shows that the propagation time through the proxy logic is taken into consideration along with the net delay to the output buffer followed by the propagation delay through the output buffer to the PAD Partial Reconfiguration User Guide www xilinx com 51 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow XILINX Timing constraint TS from PP output to static MAXDELAY FROM TIMEGRP Bram output PPs 5 0 ns 8 paths analyzed 8 endpoints analyzed 0 failing endpoints 0 timing errors detected 0 setup errors 0 hold errors Maximum delay is 4 770ns Slack 0 230ns requirement data path Source red d out 5 PROXY LUT red d out 5 Destination out bram 5 PAD Requirement 5 000ns Data Path Delay 4 770ns Levels of Logic 2 Maximum Data Path U1 RP Bram d out 5 PROXY to out bram 5 Location Delay type Delay ns Physical Resource Logical Resource s Partition Pin SLICE X33Y38 B Tilo 0 080 red d_out 5 _PROXY red d out 5 PROXY red d out 5 G15 0 net fanout 1 2 514 out bram 5 OBUF G15 PAD Tioop 2 176 out bram 5 out bram 5 OBUF out bram 5 Total 4 770ns 2 256ns logic 2 514ns rte 47 3 logic 52 7 route Figure 3 9 illustrates the
110. iable is used and STATIC is removed from the RM list the Static directory is not required If the option RUN RM SYNTH is set to NO the directory for each RM must contain the netlist for each module Configuration Directories These directories do not require any specific content but must be created for implementation to run In the example above they are the FastConfig SlowConfig FSFConfig and BlankConfig directories Partial Reconfiguration User Guide www xilinx com 91 UG702 v 12 1 May 3 2010 Chapter 5 Command Line Scripting XILINX Export Directories Export directories are created by the script to hold Configurations which have completed implementation The names are based on the Configuration name X lt config_name gt and in the example are XFastConfig XSlowConfig XFSFConfig and XBlankConfig The files in these directories are overwritten each time the scripts are run To save runs for analysis or comparison save copies in a new location 92 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 6 Configuring the FPGA Device This chapter describes how to configure the FPGA device and includes e About Configuring the FPGA Device e Configuration Modes e Downloading a Full Bit File e Downloading a Partial Bit File e System Design for Configuring an FPGA Device e Partial Bit File Integrity
111. ig FSFConfig ncd SlowConfig SlowConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 33 Number of matched global clock nets 4 Number of matched Reconfigurable Partitions 1 SUCCESS www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX pr_verify Analyzing Designs SlowConfig SlowConfig ncd BlankConfig BlankConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 33 Number of matched global clock nets sd Number of matched Reconfigurable Partitions 0 SUCCESS Analyzing Designs SlowConfig SlowConfig ncd FastConfig FastConfig ncd Number of matched proxy logic bels 54 Number of matched external nets 33 Number of matched global clock nets 4 Number of matched Reconfigurable Partitions 0 SUCCESS build xfndry M 53d rtf bin lin unwrapped pr verify BlankConfig BlankConfig ncd FastConfig FastConfig ncd FSFConfig FSFConfig ncd SlowConfig SlowConfig ncd PASS As you can see from the Log File the ncd files are compared two at a time so that specific information on the configurations and resources that are inconsistent can be discovered The last line contains the overall PASS FAIL for the run The Log File shows the following resource comparisons Number of matched proxy logic bels This reflects the number of LUT1s used as proxy logic that are the same in both existence and location
112. ig settings Static is imported from the FastConfig set CONFIG_SlowConfig ConfigName SlowConfig Settings top State import ImportLocation XFastConfig top reconfig_red State implement NetlistDir Red Slow ModName Red Slow top reconfig green State implement NetlistDir Green Slow ModName Green Slow top reconfig blue State implement NetlistDir Blue Slow ModName Blue Slow j 86 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Data tcl Format Configuration FSFConfig settings All 4 partitions are imported set CONFIG_FSFConfig ConfigName FSFConfig Settings top State import ImportLocation XFastConfig top reconfig red State import ImportLocation XFastConfig NetlistDir Red Fast ModName Red Fast top reconfig green State import Importlocation XFastConfig NetlistDir Green Fast ModName Green Fastj top reconfig blue State import ImportLocation XSlowConfig NetlistDir Blue Slow ModName Blue Slow Configuration BlankConfig settings set CONFIG_BlankConfig ConfigName BlankConfig Settings top State import ImportLocation XFastConfig top reconfig red State implement NetlistDir Red Blank ModName Red Blank top reconfig green State implement NetlistDir Green Blank ModName Green Blankj top reconfig blue State implement NetlistDir Blue Blank ModName Blue
113. in Reconfigurable Modules cannot route outside the Area Group associated with that Reconfigurable Partition e Imported routes will have precedence over implemented routes Partial Reconfiguration User Guide www xilinx com 43 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow XILINX may FoI Figure 3 7 Routing Restriction in Partial Reconfiguration What does this mean for debugging placement and routing problems e RP area groups will need to be larger than the same Area Group would be for a flat design e The placer considers these routing restrictions so placement failures may be caused by unavailability of routing resources If your design fails to place test with non reconfigurable partitions by modifying your xpartition pxml file to remove the reconfigurable true statement Before the modification the file will look like this lt Project FileVersion 1 2 Name FastConfig ProjectVersion z 0 s Partition Name top State implement lt Partition Name top reconfig red Reconfigurable true State implement ReconfigMHoduleName Red Fast lt Partition gt Partition Names topi reconfig green Reconfigurable true State implement ReconfigModuleName Green Fast gt lt Partition gt lt Partition Name top reconfig blue Reconfigurable true State implement ReconfigModuleName Blue Fast gt x Partition lt Partition gt lt Project gt After the modificati
114. includes the ILOGIC OLOGIC associated with the IO buffer connected to the register If the IO logic site does not belong to the RP s AREA GROUP the tools are not allowed to utilize that site nor would the site be included in the partial bitstream e The output port of the RP must have the PARTITION PIN DIRECT ROUTE constraint to prevent the tools from inserting proxy logic between the buffer and the register which would prevent the register from being packed in the IO logic Also this forces all RMs variants associated with this RP to have the same IOB FORCE constraint and disables the ability to generate a black box RM for this RP Design Instance Hierarchy The simplest method is to instantiate the Reconfigurable Partitions in the top level module Each Reconfigurable Partition must correspond to exactly one instance The instance has multiple modules with which it is associated Submodules in Reconfigurable Modules All the logic for a Reconfigurable Module must exist in the same directory If an RM requires submodule netlist files the PlanAhead software loads them only if they exist in the same local folder as the root RM netlist PlanAhead needs the full contents of each Reconfigurable Module to both constrain and implement each Configuration If other netlists IP core netlists for example must be merged in from other directories the ngcbuild utility can be used to pre assemble an RM in
115. ine options for the synthesis run For information on XST command line options see UG627 the XST User Guide The following code is an example XST file www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Required Files and Directory Structure run ifn red prj ifmt mixed ofn red ofmt NGC p xc5vlx50t 3 f 1136 top red opt_mode Speed opt_level 1 power NO iuc NO keep hierarchy NO netlist hierarchy as optimized rtlview Yes glob opt AllClockNets read cores YES write timing constraints NO hierarchy separator bus delimiter lt gt case maintain slice utilization ratio 100 bram utilization ratio 100 dsp utilization ratio 100 reduce control sets off verilog2001 YES fsm extract YES fsm encoding Auto safe implementation No fsm style lut The XST file specifies the appropriate PRJ file as the input file The PRJ file contains all the HDL files for an RM as well as the language and library to into which to compile the source For example verilog work Source red fast led fast v verilog work Source red fast red fast v Examples of both the xst and prj files can also be seen in UG627 the XST User Guide or generated from ISE Design Suite In the example the required directories are Red Fast Red Slow Red Blank Green Fast Green Slow Green Blank Blue Fast Blue Slow Blue Blank and Static If the NGDBUILD TOP var
116. ion see the User Guide for your target device at http www xilinx com support documentation Partial Reconfiguration User Guide www xilinx com 111 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX Regional Clocking The BUFRs in static logic that drive Partition Pins have proxy logic inserted This is required to guarantee a stationary point between different configurations just as for all other nets that cross from static logic into Reconfigurable Partitions The proxy logic adds delay to the regional clock which can have detrimental effects on timing To prevent timing degradation Xilinx recommends that BUFRs and all their loads be fully contained within the same Partition whether static or reconfigurable This provides minimal skew between regional clock loads and results in the greatest chance for meeting timing Regional Clocks have different restrictions in the three supported Virtex architectures 112 Virtex 4 No proxy logic is inserted on regional clocks and regional clock spines are prerouted The spines will be prerouted to each clock region which may need that clock spine For example if a regional clock drives a port on an RP which covers portions of two clock regions regional clock spines will be reserved for that regional clock in both of the clock regions Since there are only two regional clock spines available per clock region Xilinx recommends that regions for RPs which are
117. ion see the Xilinx website at http www xilinx com literature To search the Answer Database of silicon software and IP questions and answers or to create a technical support WebCase see the Xilinx website at http www xilinx com support For additional information to help build Partial Reconfiguration designs see Conventions 10 UG360 Virtex 6 FPGA Configuration User Guide UG191 Virtex 5 FPGA Configuration User Guide UG071 Virtex 4 FPGA Configuration User Guide UG632 PlanAhead User Guide installed with software UG627 XST User Guide UG687 XST User Guide for Virtex 6 and Spartan 6 Devices UG628 Command Line Tools User Guide UG748 Hierarchical Design Methodology Guide WP362 Repeatable Results with Design Preservation XAPP290 Differencing Method for Partial Reconfiguration This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Courier bold Literal commands that you enter ngdbuild lt desi gt in a syntactical statement abia pesce Commands that you select from File Open Helvetica bold PUER Keyboard shortcuts Ctrl C www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Re
118. ion of the hardware solution required Xilinx is working on a Reference Design IP Core for a future software release that will work with the BitGen software solution If a CRC error is detected using a solution similar to this it is the user s responsibility to figure out how to resend data and correct the situation Since the data corruption will be determined prior to the corrupt data being loaded it is not necessary to reconfigure the static logic Partial Reconfiguration User Guide www xilinx com 99 UG702 v 12 1 May 3 2010 Chapter 6 Configuring the FPGA Device g XILINX Configuration Frames All user programmable features inside Virtex devices are controlled by volatile memory cells that must be configured at power up These memory cells are collectively known as configuration memory They define the LUT equations signal routing IOB voltage standards and all other aspects of the design Virtex architectures have configuration memory arranged in frames that are tiled about the device These frames are the smallest addressable segments of the device configuration memory space and all operations must therefore act upon whole configuration frames The numbers of configuration frames per device are shown in the FPGA device family specific Configuration User Guides table 7 1 for Virtex 4 table 6 1 for Virtex 5 table 6 22 for Virtex 6 Reconfigurable Frames are built upon these configuration frames and these are the minimum b
119. is modified portions of the flow must be rerun If the STATE attribute is changed then MAP or PAR can be re run If you re run both MAP and PAR placement and routing takes the STATE from the xpartition pxml file If you re run just PAR placement keeps the STATE from the previous run and the routing takes the STATE from the current xpartition pxml If the Import Location or Reconfigurable attributes are changed ngdbuild MAP and PAR must all be re run The following subsections show first second and third Configuration PXML files Partial Reconfiguration User Guide www xilinx com 41 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow XILINX First Configuration PXML File The First Configuration PXML file simplified is as shown in the following file snippet First Configuration s xpartition pxml file Project FileVersion 1 0 Name FFF ProjectVersion 2 0 gt Partition Name top Version 2 0 State implement ImportLocation NONE gt Partition Name top red Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName red fast Partition Name top blue Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName blue_fast gt lt Partition Name top green Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName green_fast gt lt Partition gt lt Part
120. it file The encrypted partial bit file is downloaded to the FPGA device where it is decrypted and sent to the ICAP to partially reconfigure the FPGA device as shown in Figure 2 6 Partial Reconfiguration User Guide www xilinx com 23 UG702 v 12 1 May 3 2010 Chapter 2 Common Applications g XILINX me Config 1 7 i Algorithm EOS External Decrypt X12023 Figure 2 6 Loading an Encrypted Partial Bit File The partial bit file could be the vast majority of the FPGA design with the logic in the static design consuming a very small percentage of the overall FPGA resources This scheme has several advantages e The public private key pair can be regenerated at any time If a new configuration is downloaded from the host it can be encrypted with a different public key If the FPGA device is configured with the same partial bit file such as after a power on reset a different public key pair is used even though it is the same bit file e The private key is stored in SRAM If the FPGA device ever loses power the private key no longer exists e Even if the system is stolen and the FPGA device remains powered it is extremely difficult to find the private key because it is stored in the general purpose FPGA fabric It is not stored in a special register The designer could manually locate each register bit that stores the private key in physically remote and unrelated regions Summary In addition to reducing size weight power and
121. ith small variances depending on the location and contents of the frames There is also a small amount of overhead after the last frame is loaded The exact bitstream length is available in the created rbt file by using the b option with Bitgen Use this number along with the bandwidth to calculate the total configuration time In the example above the header of the bitstream that is created is shown in the following file snippet of an rbt header The actual configuration time is about 75 6 microseconds Xilinx ASCII Bitstream Created by Bitstream L 46 Design name FFF routed ncd UserID O0xFFFFFFFF Architecture virtex5 Part 5vlx50tff1136 Date Tue Jun 09 14 00 59 2009 Bits 242016 11111111111111111111111111111111 Configuration Debugging The ICAP interface can be use used to monitor the configuration process even if other configuration means are used JTAG or Slave SelectMAD In fact the status of the configuration is automatically pushed out to the O port of the ICAP without having to issue a read The O port of the ICAP block is a 32 bit bus but only the lowest byte is used The mapping of the lower byte is as follows Partial Reconfiguration User Guide www xilinx com 101 UG702 v 12 1 May 3 2010 Chapter 6 Configuring the FPGA Device XILINX Table 6 2 ICAP O Port Bits Bit Number Status Bit Meaning O 7 CFGERR_B Configuration error active Low 0 A configuration error has occurred 1
122. ition gt lt Project gt Second Configuration PXML File The second Configuration that imports the static logic is shown in the following simplified file snippet Second Configuration s xpartition pxml file Project FileVersion 1 0 Name SSS ProjectVersion 2 0 gt Partition Name top Version 2 0 State import ImportLocation XFFF gt lt Partition Name top red Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName red_slow gt lt Partition Name top blue Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName blue_slow gt lt Partition Name top green Version 2 0 State implement ImportLocation NONE Reconfigurable true ReconfigModuleName green_slow gt lt Partition gt lt Partition gt lt Project gt 42 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Implementation Third Configuration PXML File The third Configuration which imports both static and all three Reconfigurable Modules is shown in the following simplified file snippet Third Configuration s xpartition pxml file lt Project FileVersion 1 0 Name FSF ProjectVersion 2 0 gt lt Partition Name top Version 2 0 State import ImportLocation XFFF gt lt Partition Name top red Version 2 0 State import ImportLocation XFFF Reconfigurable true Reconfi
123. k New Pblock Set Partition Clear Partition Unset Reconfigurable Partition Add Reconfigurable Module Update Reconfigurable Module Select Primitives Select Primitive Parents g Highlight Primitives gt Unhighlight Primitives Figure 4 6 Setting a Partition as Reconfigurable 64 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Defining the Reconfigurable Instances Partitions can be Reconfigurable or standard Since no netlist has been associated with this module it can only be defined as Reconfigurable The Reconfigurable Partition can have netlists for a Reconfigurable Module loaded and it can also be defined optionally as a black box module 2 Enter a unique name for the Reconfigurable Module that corresponds to the module variant to be selected as shown in Figure 4 7 set Partition EU xl Reconfigurable Module Name Enter a name for the new reconfigurable module For instance reconfig blue de Reconfigurable Module Name blue fast fe Netlist already available For this Reconfigurable Module dd this Reconfigurable module as a black box without a netlist lt Back Cancel Figure 4 7 Naming the Reconfigurable Module If the first option netlist exists is selected the wizard prompts for the netlist for this module Because all variants of one RP must have the same netlist name the directory structure must
124. l Pins to create TPSYNC constraints based on Partition Pins In the dialog that opens the Design element type field can be set to Partition Pins to find the instances easily within the design Use groups created here to define timing specifications Figure 3 6 shows the Group Constraints by Combinatorial Pins dialog box v Group Constraints by Combinatorial Pins TPSYNC P x Tpsync name group blue VGA in Design element type Partition Pins Filter e Use the pattern in the Filter as the targets Available partition pins Pin targets reconfig blue out reconfig blue vGA out3 reconfig_blue GA_out4 reconfig_blue V GA_outS reconfig_blue V GA_out6 reconfig_blue V GA_out reconfig_green out reconfig_green rst_n reconfig_green V GA_in2 reconfig_green VGA_in3 gt gt lt lt lt reconfig_green GA_in gt OK reconfig blue vGA in2 reconfig blue rst n reconfig blue vGA in3 reconfig blue vGA out reconfig blue vGA in4 reconfig_blue GA_out1 reconfig_blue V GA_inS reconfig_blue V GA_out2 reconfig_blue V GA_in6 gt reconfig blue VGA in7 vaconfia araen Wh inc Close Create Help Figure 3 6 Grouping Partition Pins in Constraints Editor Partial Reconfiguration User Guide www xilinx com 39 UG702 v 12 1 May 3 2010 40 Chapter 3 Software Tools Flow g XILINX The new constraints generated by the Constraints Editor must be imported into the
125. l netlist If the static logic has already been synthesized you can use this variable to point to the path rather than running synthesis with the RMs This variable must be set if RUN RM SYNTH is set to NO or if Static is not in your RM list e NGDBUILD SEARCH search directories for NGDBUILD Sets the macro search path for NGDBuild to point to directories where core netlists are located This can reference more than one directory separated by spaces and enclosed in curly braces UNIX type forward slashes must be used on both Windows and Linux due to Tcl conventions e GENERATE RUNFILES YES NO Sets whether or not to run implementation or only generate the script files The default is NO which will run the processes Also you can also specify whether to run each 88 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Recommended Flow particular process with the following variables This is for all Configurations The default for all three variables is YES RUN MAP YES NO Controls whether or not MAP is run on all implementations RUN PAR YES NO Controls whether or not PAR is run on all implementations RUN BITGEN YES NO Controls whether or not bitgen is run on all implementations Each implementation process may also have customized command line options In the current software customized options are set
126. l path through a Reconfigurable Partition is strongly discouraged not only due to the two additional LUT delays incurred but also due to the lack of logic decoupling as described in Decoupling Functionality in Chapter 7 Timing constraint TS static VGA vgaclk2 i PERIOD TIMEGRP Static VGA vgaclk2 i TS static VGA pixel clock i PHASE 3 167 ns HIGH 50 126 paths analyzed 36 endpoints analyzed 10 failing endpoints 10 timing errors detected 10 setup errors 0 hold errors 0 component switching limit errors Minimum period is 15 401ns Slack 0 451ns req data path clock path skew uncer ty Source static VGA VGA R 1 0 FF Destination Static DVI IF ODDR DVI DATA11 FF Requirement 3 167ns Data Path Delay 3 387ns Levels of Logic 2 Clock Path Skew 0 084ns 1 427 1 343 Source Clock static VGA pixel clock rising at 0 000ns Destination Clock VGA CLK rising at 3 167ns Clock Uncertainty 0 315ns Clock Uncertainty 0 315ns TSJ 2 TIJ 2 1 2 DJ 2 PE Total System Jitter TSJ 0 070ns Total Input Jitter TIJ 0 000ns Discrete Jitter DJ 0 458ns Phase Error PE 0 050ns Maximum Data Path static_VGA VGA_R_1 0 to static_DVI_IF ODDR_DVI_DATA11 Location Delay type Delay ns Physical Resource Logical Resource s Partition Pin SLICE_X25Y75 DQ Tcko 0 326 VGA_R_bus_out 1 static_VGA VGA_R_1 0 SLICE_X25Y76 C6 net fanout 8 0 248 VGA_R_bus_out 1 SLICE X25Y76 C Tilo 0 080 red VGA out7 PROXY
127. licking the Implement button in the Flow Manager Design Runs Ogx a Sum prea rit Fmax et ina Score rates c gt FFF active xc6ylx240tff1 156 2 constrs_1 ISE Defaults ISE 12 Running MAP 20 4 5 10 11 45 AM 00 00 14 ISE Defaults including packing rec c 555 xc6vlx240tff1156 2 constrs 1 ISE Defaults ISE 12 Not started LL 0 ISE Defaults including packing registers m c FSF xc vlx240tff1156 2 constrs 1 ISE Defaults ISE 12 Not started 0 ISE Defaults including packing registers gt c BB xc6vlx240tff1156 2 constrs 1 ISE Defaults ISE 12 Not started o 938 ISE Defaults including packing registers e 4 E Tel Console Compilation Log Compilation Messages amp Reports 2 Design Runs E Figure 4 25 Implementing a Configuration Once a Configuration has been successfully implemented it can be promoted to allow future implementations and Configurations to import the results 3 From the popup menu in the Configurations view select Promote Configuration Configurations Configuration Module Variant Status FFF 4 PAR Complete lv Static Logic 4 Promote Partitions 45 reconfig blue reconfig greer _ reconfig red Verify Configuration Unpromote Configuration 555 4 Load Configuration e FSF 4 lt gt BB 4 Export to Spreadsheet _ amp
128. list name for each Red must be identical to allow the instantiation of the module in the static logic to call any of the Reconfigurable Modules In addition the ports of each Reconfigurable Module must be identical so the assembly of the design can succeed Each instantiation of a reconfigurable module must have a unique module name In this sample design Red can be instantiated only once This allows the implementation tools to determine which Reconfigurable Modules are associated with which Reconfigurable Partition In practice the netlist name of each Reconfigurable Module is identical requiring that each netlist be in its own directory Netlist directory for the PR project named Color2 Static Top ngc contains logic for all static logic including DVI_IF IIC_init and VGA Netlists for the reconfigurable instance Red red_fast red ngc red_slow red ngc Netlists for the reconfigurable instance Blue blue fast blue ngc blue slow blue ngc Netlists for the reconfigurable instance Green green fast green ngc green slow green ngc 30 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Configurations Configurations The Partial Reconfiguration software implements a full design containing static logic and one Reconfigurable Module for each Reconfigurable Partition Each implementation is done in context This gives the tools a complete set of information for resource
129. mns of BUFRs within the same clock region Partial Reconfiguration requires that all BUFRs used within one clock region be contained in the same partition For example if an outside BUFR is used in the same clock region as an inside BUFR both would either have to be in the static or the same RP See the Virtex 6 FPGA Clocking Resources User Guide for more information on the restrictions of regional clocking www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Decoupling Functionality Decoupling Functionality Because the reconfigurable logic is modified while the FPGA device is operating the static logic connected to outputs of Reconfigurable Modules must ignore data from Reconfigurable Modules during Partial Reconfiguration The Reconfigurable Modules will not output valid data until Partial Reconfiguration is complete and the reconfigured logic is reset A common design practice to mitigate this issue is to register all output signals on the static side of the interface from the Reconfigurable Module An enable signal can be used to isolate the logic until it is completely reconfigured The static portion should include the logic required for the data and interface management It can implement mechanisms such as handshaking or disabling interfaces which might be required for bus structures to avoid invalid transactions It is also useful to consider the down time performance effect of a PR module tha
130. module The appropriate netlists are implemented in each design to generate the full and partial bit files for that Configuration The static logic from the first implementation is shared among all subsequent design implementations 26 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Example Design Structure Example Design Structure Throughout this Guide the Color2 sample design is used to illustrate design flow and techniques This design displays on a DVI support monitor color bars of primary color red blue and non primary green as well as the different shades of mixing the primary colors The partial Reconfigurable Modules are the red blue and green modules The variants of each of the modules are fast and slow for each red blue and green The speed of the color represents how fast the LEDs are blinking on the demo board this design targets the Virtex 6 ML 605 Evaluation Platform Design files for the referenced design can be downloaded from http www xilinx com tools partial reconfiguration Figure 3 2 is a diagram of the hierarchical netlist Top IIC init DVI_IF and VGA are modules in the static region of the design meaning this logic maintains normal operation while the other modules can be reconfigured red blue and green are the instantiations of Reconfigurable Module for the Red Blue and Green functionality The modules that are interchanged are
131. name misspelling can cause this a missing edif or ngc file case mismatch between the block name and the edif or ngc file name or the misspelling of a type name Symbol busmacro xcb5v async enable is not supported in target virtex5 VHDL Bus Macro Removal Remove Only Bus Macros Instantiations In the following example an asynchronous BM is used To simplify the BM removal process in this example the BM inputs are connected directly to the BM outputs However this is not necessary and a single network could replace the BM inputs and BM outputs Conversely several BMs have associated control logic and these BM types would require both input and output signals to be preserved as the control logic will interface the two signals In a later section the Redefine Bus Macro process is explained Partial Reconfiguration User Guide www xilinx com 123 UG702 v 12 1 May 3 2010 Chapter XILINX Step 1 Remove the component declarations for all bus macros Example VHDL Bus Macro Declaration to be removed component busmacro_xc5v_async is port inputO0 in std logic inputi in std logic input2 in std logic input3 in std logic outputO0 out std logic outputi out std_logic output2 out std_logic output3 out std_logic E end component Step 2 Replace Bus Macro Instantiations with a 1 1 signal mapping assignment Example Old VHDL Bus Macro Instantiation Control1_0_BM busmacro_xc5v_async
132. nfig_green green_Fast Implement reconfig_red red_fast Implement N Sources Timing Co E Physical C 9 Configu G9 Netlist Figure 4 21 Details of Each Configuration are Reported Multiple Configurations can be created by selecting Tools gt Create Multiple Runs see Figure 4 23 Any combination of Reconfigurable Modules and black boxes can be used to create a Configuration Configurations can be created at any time while working with a Partial Reconfiguration design Partial Reconfiguration User Guide www xilinx com 73 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX e Create Multiple Runs x Choose Implementation Strategies and Reconfigurable Modules Create and configure runs using various strategies and Module Variants for de Reconfigurable Modules j Create Implementation Runs 555 ISE Defaults ISE12 a reconfig FSF ISE Defauts I5E 12 C reconfig BB ise Defaults ISE 12 C reconfig More Fewer Runs to create 3 lt Back Next gt Cancel Figure 4 22 Creating Multiple Runs In this example design four unique Configurations are created as shown in Figure 4 23 Configurations Q zm PR EI 4 B Configuration Module variant status z FFF 4 Not started B Static Logic Implement amp reconfig blue blue fast Implement reconfig green green f
133. nfigured with a full bit file However the full bit file might only contain the PCle interface and connection to the Internal Configuration Access Port ICAP The system host could then configure the majority of the FPGA functionality with a partial bit file downloaded through the PCle port as shown in Figure 2 3 Full Bit File Partial Bit File X12021 Figure 2 3 Configuration by Means of PCle Interface The PCIe standard requires the peripheral the FPGA device in this case to acknowledge any requests even if it cannot service the request Reconfiguring the entire FPGA device would violate this requirement Because the PCIe interface is part of the static logic it is Partial Reconfiguration User Guide www xilinx com 21 UG702 v 12 1 May 3 2010 Chapter 2 Common Applications g XILINX always active during the Partial Reconfiguration process thus ensuring that the FPGA device can respond to PCle commands even during reconfiguration Dynamically Reconfigurable Packet Processor A packet processor can use Partial Reconfiguration to change its processing functions quickly based on the packet types received In Figure 2 4 a packet has a header that contains the partial bit file or a special packet contains the partial bit file After the partial bit file is processed it is used to reconfigure a coprocessor in the FPGA device This is an example of the FPGA device reconfiguring itself based on the data packet received instead
134. o a configuration port The Partial Reconfiguration control logic can either reside in an external device for example a processor or in the fabric of the FPGA device to be reconfigured A user designed internal PR controller loads partial bitstreams through the ICAP interface As with any other logic in the static design the Partial Reconfiguration User Guide www xilinx com 93 UG702 v 12 1 May 3 2010 Chapter 6 Configuring the FPGA Device g XILINX internal Partial Reconfiguration control circuitry operates without interruption throughout the Partial Reconfiguration process Internal configuration can consist of either a custom state machine or an embedded processor such as MicroBlaze processor or PowerPC 405 processor PPC405 As an aid in debugging Partial Reconfiguration designs and PR control logic the Xilinx iMPACT tool can be used to load full and partial bitstreams into an FPGA device by means of the JTAG port For more information on loading a bitstream into the configuration ports see the Configuration Interfaces chapter in UGO71 Virtex 4 FPGA Configuration Guide UG191 Virtex 5 FPGA Configuration User Guide or UG360 Virtex 6 FPGA Configuration User Guide Configuration Modes Partial Reconfiguration is supported via the following configuration modes e ICAP A good choice for user configuration solutions Requires the instantiation of an ICAP controller as well as logic to drive the ICAP interface
135. o optimizations are done across these boundaries ensuring that each portion of the design is synthesized independently Top level logic must be synthesized with black boxes for Partitions Configuration A Configuration is a complete design that has one Reconfigurable Module for each Reconfigurable Partition There may be many Configurations in a Partial Reconfiguration FPGA project Each Configuration generates one full bit file as well as one partial bit file for each Reconfigurable Module Configuration Frame Frame Configuration frames are the smallest addressable segments of the FPGA configuration memory space Reconfigurable frames are built from discrete numbers of these lowest level elements Frames in all references other than configuration frames in this Guide represent the smallest reconfigurable region within an FPGA device Bitstream sizes of reconfigurable frames vary depending on the types of logic contained within the frame Internal Configuration Access Port ICAP 14 The Internal Configuration Access Port ICAP is essentially an internal version of the SelectMAP interface For more information see the family specific Configuration User Guides www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Terminology Partial Reconfiguration PR Partial Reconfiguration PR is modifying a subset of logic in an operating FPGA design by downloading a partial configuration
136. omplete partial bitfile has been sent to the configuration port it is safe to release the reconfiguration region for active use System Design for Configuring an FPGA Device 96 A partial bit file can be downloaded to the FPGA device in the same manner as a full bit file An external microprocessor determines which partial bit file should be downloaded where it exists in an external memory space and directs the partial bit file to a standard FPGA configuration port such as JTAG SelectMAP or serial interface The FPGA device processes the partial bit file correctly without any special instruction that it is receiving a partial bit file It is common to assert the INIT or PROG signals on the FPGA configuration interface before downloading a full bit file This must not be done before downloading a partial bit file as that would indicate the delivery of a full bit file not a partial one Any indication to the working design that a partial bit file will be sent such as holding enable signals and disabling clocks must be done in the design and not by means of dedicated FPGA configuration pins Figure 6 3 shows the process of configuring through a microprocessor www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Partial Bit File Integrity full RM A1 RM A2 RM A3 configuration config config config Off chip memory or System ACE Self reconfiguring FPGA X12033 Fig
137. on the file will look like this 44 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Generating Bit Files Project FileVersion 1 2 Name FastConfig ProjectVersion z lt Partition Name top State implement lt Partition Name top reconfig red State implement lt Partition gt lt Partition Name top reconfig green State implement lt Partition gt lt Partition Name top reconfig blue State implement gt lt Partition gt lt f Partition gt ky Project gt Since non reconfigurable partitions don t have the same routing restrictions if the RP places and routes successfully with this change the area groups will need to be made larger for the Reconfigurable Partitions to place and route NGDBuild Map and PAR will need to be rerun after this change Generating Bit Files Run bitgen on the NCD file to generate both the full and partial bit files No special options are required to generate partial bit files but options specific to Partial Reconfiguration capabilities are listed later in this section bitgen w FFF ncd If the design contains Reconfigurable Partitions partial bit files are generated automatically for each of them The full bit file includes the partial modules used in the Configuration For example the first Configuration in the example design generates the files fff bit static logic and modules red fast blue fas
138. onfigurations with implementation order This list drives the implementation of all configurations in the order they are listed The order of this list is of great importance Partitions cannot be imported until after the first implementation Section 4 Implementation Options Section 4 Implementation Options lets you set variables that change the implementation options 10 Implementation options set the optional implementation data flags The format of the optional data is RUN RM SYNTH NO if the design has no modules to be synthesized bottom up NGDBUILD TOP top path is path to pre existing top module for Ngdbuild NGDBUILD SEARCH search path a string containing search path directories NGDBUILD OPTS ngdbuild command line options optional cmd line options for Ngdbuild RUN MAP NO if you do not want to run Map MAP OPTS map command line options optional command line options for Map RUN PAR NO if you do not want to run PAR PAR OPTS par command line options optional command line options for Par RUN BITGEN NO if you do not want to generate bitstreams array set IMPLEMENTATION DATA RUN RM SYNTH NO THE cR HR HR d H The variables are e RUN RM SYNTH YES NO Sets whether or not to run bottom up synthesis on all modules in RM list This should be set to YES for the first implementation then changed to NO until HDL changes occur The default is YES e NGDBUILD TOP path to top leve
139. ough a graphical interface or on the command line For each module be sure to disable IO insertion as the ports of these modules in most cases do not connect to package pins but to the static logic above it IO ports may be included to be reconfigured For more information see IO in Reconfigurable Modules in Chapter 7 The static modules can be synthesized together to generate one netlist or individually to generate multiple static netlists The ngdbuild utility merges the static and reconfigurable modules and the Reconfigurable Partition definitions denote the interfaces between the static and reconfigurable logic Different options can be used for any of the static or reconfigurable module synthesis The minimum generated netlists for the example design Color2 are shown in the following code snippet Partial Reconfiguration User Guide www xilinx com 29 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX Netlists generated for the PR project named Color2 Netlist for Top which contains DVI_IF IIC_init and VGA modules Netlists for the reconfigurable instance Red Netlist for red_fast Netlist for red_slow Netlists for the reconfigurable instance Blue Netlist for blue_fast Netlist for blue_slow Netlists for the reconfigurable instance Green Netlist for green_fast Netlist for green_slow Caution The netlist names are related to the module name not the HDL file name The module net
140. plementation Run Properties Og x e 9 5 gt sss Static Logic 4 reconfig blue blue slow 4 reconfig green green slow Implement reconfig red red slow General Options Monitor Reports Messages Partitions Figure 4 31 Selecting the Action Implement vs Import The following is a summary of the Status fields shown in Figure 4 30 for Static and Reconfigurable logic e Implement or Not Started for the Configuration Module has been defined but has not been implemented When implementation is run place and route are done from scratch with the netlist options and constraints provided for that module e Import Module has been defined and results are copied from another Configuration When implementation is run place and route copies the results from a Promoted location for this module preserving the exact results e Implemented or PAR Complete for the Configuration Module has successfully completed place and route in the selected Configuration e Imported Module has successfully been copied and pasted from a Promoted run e Promoted Module has been elevated to golden status and duplicate modules in other Configurations marked for Import are imported from this master result The results for these implementation runs are found in the PlanAhead project directory at lt project_name gt runs lt configuration_name
141. port map input0 gt MY_ADDR_SPACE input1 gt PLB SAValid input2 gt PLB_rdPrim input3 gt PLB_wrPrim outputO gt MY ADDR SPACE pr outputil gt PLB SAValid pr output2 PLB rdPrim pr output3 PLB wrPrim pr Jos Example New VHDL Replacement for Bus Macro a 1 1 Assignment MY ADDR SPACE pr MY ADDR SPACE PLB SAValid pr PLB SAValid PLB rdPrim pr PLB rdPrim PLB wrPrim pr PLB wrPrim This is a very simple asynchronous BM but it does convey the idea of how to replace the BMs There are BMs with control logic and synchronous types of BMs These BMs need to be replaced with register inferences and any desired control logic enables clock enables etc as necessary Below is another asynchronous example but with control logic Example Old VHDL Bus Macro Instantiation with Enable Control2 0 BM busmacro xc5v async enable port map inputo gt Sl addrAck pr inputl gt Sl SSize pr 0 input2 gt Sl SSize pr 1 input3 gt Sl wait pr enable0 gt busmacro enable enablel gt busmacro enable enable2 busmacro enable enable3 busmacro enable outputO0 gt S1 addrAck outputi gt Sl SSize 0 output2 gt Sl SSize 1 output3 gt Sl wait Viz 124 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Migrating a Design Example New VHDL Replacement for Bus Macro with Enable Sl_addrAck lt Sl addrAck pr and busmacro_enable
142. rable logic and static logic The gray area of the FPGA block represents static logic and the block portion labeled Reconfig Block A represents reconfigurable logic The static logic remains functioning and is completely unaffected by the loading of a partial bit file The reconfigurable logic is replaced by the contents of the partial bit file There are many reasons why the ability to time multiplex hardware dynamically on a single FPGA device is advantageous Partial Reconfiguration User Guide www xilinx com 13 UG702 v 12 1 May 3 2010 Chapter 1 Introduction g XILINX Terminology These include e Reducing the size of an FPGA device required for implementing a given function with consequent reductions in cost and power consumption e Providing flexibility in the choices of algorithms or protocols available to an application e Enabling new techniques in design security e Improving FPGA fault tolerance e Accelerating configurable computing In addition to reducing size weight power and cost Partial Reconfiguration enables new types of FPGA designs that are impossible to implement without it The following terminology is specific to the Partial Reconfiguration feature and is used throughout this document Bottom Up Synthesis Bottom Up Synthesis is synthesis of the design by modules whether in one project or multiple projects Bottom Up Synthesis requires that a separate netlist is written for each Partition and n
143. rarchy page 106 This technique can be used for single netlists to incorporate the information from a UCF into the netlist itself The constraints in this UCF must be scoped to the module level references to instances within the RM must NOT have the full hierarchical path to the instance Partial Reconfiguration User Guide www xilinx com 115 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX Implementation Strategies There are trade offs associated with optimizing any FPGA design Partial Reconfiguration is no different Partitions are barriers to optimization and reconfigurable frames require specific layout constraints These are the additional costs to building a reconfigurable design The additional overhead for timing and area needs vary from design to design To minimize the impact follow the design considerations stated in this Guide When building Configurations of a reconfigurable design the first Configuration to be chosen for implementation should be the most challenging one Be sure that the physical region selected has adequate resources especially elements such as block RAM DSP48 and IO for each Reconfigurable Module in each Reconfigurable Partition then select the most demanding in terms of either timing or area RM for each RP If all of the RMs in the subsequent Configurations are smaller or slower meeting their demands will prove to be easier Timing budgets should be established to meet th
144. red in this path analysis Timing constraint TS from static to PP input MAXDELAY TO TIMEGRP group RP red input 4 5 ns 12 paths analyzed 12 endpoints analyzed 0 failing endpoints 0 timing errors detected 0 setup errors 0 hold errors Maximum delay is 1 111ns Slack 3 389ns requirement data path Source count 34 FF Destination red addr 11 PROXY LUT red addr 11 Requirement 4 500ns Data Path Delay 1 111ns Levels of Logic 0 Source Clock gclk rising at 0 000ns Maximum Data Path count 34 to RP red addr 11 PROXY Location Delay type Delay ns Physical Resource Logical Resource s SLICE X47Y39 CQ Tcko 0 326 count 34 count 34 SLICE X45Y37 A1 net fanout 2 0 785 count 34 Total 1 111ns 0 326ns logic 0 785ns route 29 3 logic 70 7 route Figure 3 8 shows the path from static FF to the Partitioned Pin 50 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Report Files Path Analyzed Partition pin red red addr 11 gt partition N addr 11 _ PROXY count_34 X12028 Figure 3 8 Path from static FF to Partition Pin For the following example a TPSYNC constraint was applied to the red d_out bus with these constraints PIN red d_out TPSYNC Bram_output_PPs TIMESPEC TS_from_PP_output_to_static FROM Bram_output_PPs 5 0 ns The source of this path is the proxy logic on t
145. straints in Chapter 3 and Defining Reconfigurable Partition Boundaries in Chapter 7 When a Pblock is defined the PlanAhead software prompts you to select the resources to be constrained in that region as shown in Figure 4 15 Partial Reconfiguration User Guide www xilinx com 69 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX GB Set Pblock x 2 Which resources do you wish pblock_reconfig_blue to constrain Grids v SLICE RAMBI8 RAMB36 Figure 4 15 Defining Ranges with a Pblock This selection produces a series of AREA GROUP RANGE constraints for the Reconfigurable Partition 2 Uncheck the selections for elements that do not exist in any variant of the Reconfigurable Modules Because partial bit files are created based upon the constraints selected here any extraneous elements make the bit files unnecessarily large The General tab of the Pblock Properties pane shows the different resources available for inclusion and can be enabled or disabled based on the design 3 Define the Range defined for each type of logic that exists in any of the corresponding RMs Each reconfigurable region must have Ranges for the logic types contained within the modules to be placed there Pblack Properties Rog x amp e 5 9 pblock reconfig red Name pblock reconfig red Parent Roor v Grid Range GLOCKREGION v SLICE X52Y40 x59Y79 BSCAN G
146. t E Run Noise Analysis Report Timing hui Slack Histogram Set up ChipScope NE Implement v Promote Partitions amp Sources j Netlist El Physical Constr Timing Constr Properties Rog X e 5 Device X E Project Summary x Tcl Console e zi A INFO HD UCFReader 0 Parsing UCF File C PRdesigns Color2 PlanAhead PlanAhead srces constrs_l imports top_ml605 ucf a INFO HD UCFReader 1 Finished Parsing UCF File C PRdesigns Color2 Plandhead Plandhead srces constrs_l imports top_ml605 ucf INFO HD LIB 0 Reading timing library C Xilinx 12 1 ISE DS Plan head parts xilinx virtex6 virtex6 lib E INFO HD LIB 1 Done reading timing library C Xilinx 12 1 ISE DS PlanAhead parts xilinx virtex6 virtex6 lib amp Tcl Console Design Runs Reports Partial Reconfiguration Flow Figure 4 4 PlanAhead Partial Reconfiguration Project Opening the Netlist Design PlanAhead opens to the Project Manager pane To begin working with your design you must first load the netlist into memory Click on the Netlist Design option in the Flow Manager After the netlist is loaded in a warning displays that explains there are Undefined Modules as expected This message indicates that the netlists that have been imported do not describe the entire design Verify that the modules listed are the modules that are to be reconfigured
147. t Design view should be opened for before launching a run This will ensure that all constraints are properly applied to RM logic before the run files are written www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Partitions and Import e If you make changes to constraints in the PlanAhead GUI save the project and then close and reopen the Netlist Design view before launching a run Partitions and Import Partitions guarantee that shared modules such as static logic are identical among all Configurations A Partition is an attribute set on an instance or top level module which directs the Xilinx software to implement the logic in a particular way The Partition itself has attributes such as RECONFIGURABLE and STATE that further direct the Xilinx software regarding how the Partition logic should be implemented The RECONFIGURABLE attribute determines whether the instance or module is implemented in a way that ultimately results in a partial bit file Because a reconfigurable module has many physical requirements that are not necessary for a non reconfigurable module the RECONFIGURABLE attribute must be set prior to running the implementation tool flow This has a significant impact on the final implementation of the module The STATE attribute determines whether the module is implemented or imported preserved from a previously implemented design If the
148. t and green fast fff reconfig red red fast partial bit only logic in the range defined for the red Reconfigurable Partition fff reconfig blue blue fast partial bit only logic in the range defined for the blue Reconfigurable Partition fff reconfig green green fast partial bit only logic in the range defined for the green Reconfigurable Partition The following BitGen options should be set for Partial Reconfiguration designs where applicable e g ActiveReconfig Yes The ActiveReconfig option is typically used in PR to prevent shutting down the FPGA prevents GHIGH and GSR assertion e g Binary Yes This will generate a binary configuration with configuration data only same as bit file minus header information Because the BIT file has header information of varying length does not always fall on a Word boundary a BIN file is often a preferred format to use for custom configuration interfaces Partial Reconfiguration User Guide www xilinx com 45 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX Report Files 46 g ConfigFallback Disable Use this option to prevent triggering a full device configuration after a configuration error CRC error on a partial bitstream Use this option for Virtex 5 and newer architectures g CRC enable This is the default and disabling the CRC is not recommended g Persist Yes Prohibits the use of the dual purpose configuration pins as user I
149. t below These variables are used for all Configurations set env VARIABLE value 4 2 part definition Define the part that is targeted for implementation 84 www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Data tcl Format 3 constraints file Specify the constraints file This is used for all Configurations 4 4 Partition names These names must match the actual instance names in the design All Partitions in the design must be defined here regardless of whether they are reconfigurable The names must match the instance name in the HDL 5 RM names Declare all Reconfigurable Modules They are used to run bottom up synthesis and to define the Configurations Static is not required to be declared Section 2 Specify Modules for Synthesis and Define Partition Attributes Section 2 Specify Modules for Synthesis and Define Partition Attributes defines modules to be synthesized and declares Partitions as reconfigurable 6 RM list Each RM in the list is synthesized with bottom up synthesis You must create a directory for each of the RMs in the list set RMs list S RED FAST RED SLOW SGREEN FAST S GREEN SLOW SBLUE FAST S BLUE SLOW STATIC I 7 Partition Attributes List FE HE HE E HE AE e FE HE E HE FE E E HE HE FE HE FE HE FE HE TEE HE FE FE FE FE HE FE E FE HE FE FE AERE HE AE FE E FE HE FE TE AE HE HE FE HE FE HE FE FE AE E FE FE TE FE E H
150. t is the unavailability of any shared resources included in a PR module during or after reconfiguration You should assert local reset in the reconfigured logic after reconfiguration has completed to ensure a known good starting state Unlike a full device configuration there are no dedicated functions such as GSR global set reset or GTS global tri state to force logic to an initial state Because the logic surrounding a reconfiguring frame is operating during the reconfiguration it is impossible to predict the state or activity of the new logic when it is released for use This is true for IO logic as well as general fabric logic Defining Reconfigurable Partition Boundaries Partial reconfiguration is done on a frame by frame basis As such when partial bit files are created they are built with a discrete number of configuration frames When the physical region for a Partition is defined the PlanAhead software reports the number of reconfigurable regions that are consumed as well as an estimate for the corresponding bitstream size The estimates from PlanAhead are accurate within 2 3 Partition boundaries do not have to align to reconfigurable frame boundaries but the most efficient place and route results are achieved when this is done Static logic is permitted to exist in a frame that will be reconfigured as long as e Itis outside the area group defined by the Pblock unless forced inside with a LOC constraint and e It does
151. timing constraints for all reconfigurable nets going to Partition Pin RP A 2 and all static nets going from Partition Pin RP A 2 paths C amp D above use this convention TIMESPEC TS from RM to PP output TO group RP A output 4 5 ns TIMESPEC TS from PP output to static FROM group RP A output 4 5 ns Because these constraints might cover asynchronous paths Xilinx recommends that all paths to and from Reconfigurable Partitions be synchronous During an initial implementation only one of the RMs is considered for timing purposes The tool generated timing budget might not provide enough timing margin for all of the other RMs to meet timing when they are implemented later The TPSYNC option allows you to constrain the static portion of the design separately from each RM This helps ensure that an adequate timing budget is allocated to the static region and to each RM For more information on a TPSYNC limitation see Appendix A Known Issues and Known Limitations A standard period timing constraint is used for register to register paths that contain Partition Pins Nets X Y amp Z above would be constrained by the following NET clk TNM NET clk group TIMESPEC TS clk period PERIOD clk group 10 ns This constraint ensures that the register to register path including Partition Pin delay meets the timing constraint It does not specify what portion of the net delay is allocated
152. tions e UCF Location constraints are required for all IO placed in Reconfigurable Modules These constraints should be placed in the top level UCF to ensure consistency among the different module variants but can be placed in a submodule UCF if necessary Thereconfigurable region must include AREA GROUP RANGE constraints that include IOB sites along with other types such as ILOGIC or OLOGIC as needed In the following code examples ports port inand port out are connected from the top level to IO logic in the RM and ports clk reset data_in and data_out connect to IO logic at the top level The instantiation of a submodule from static must include references to port_inand port out and the submodule must include instantiations of IO logic on the appropriate ports iport_ini and iport_outi in this case e XST XST can be directed to insert or not insert IO buffers by means of the BUFFER_TYPE attribute The recommended flow using XST is to let the synthesis tool insert IO at the top level by default and use this attribute to denote the IO that should NOT receive IO buffers at the top level This attribute is applied to the ports at the top level port definition The IO components such as IBUF and OBUF must be instantiated in the submodule HDL Partial Reconfiguration User Guide www xilinx com 107 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX The following code snippets ar
153. tition Pins at the port boundary between static logic and reconfigurable logic Partition Pins are necessary to guarantee that the circuit connections between the static logic and the different RMs for each RP are identical The Partition Pin is also a convenient component for creating timing constraints on nets that pass to from or through the RP boundary Partition Pins are inserted automatically by the implementation software No special instantiations or other considerations are required of the designer with the exception of controlled routes which is described in Chapter 7 Design Considerations Note Partition Pins can be input or output connections to a reconfigurable region Partition Pins cannot be bidirectional Partition Pin timing constraints take one of several forms depending on path structure as illustrated in Figure 3 5 The yellow RM bounding box represents the logical boundary not necessarily a physical range or floorplan Path A Static net input to a Partition Pin Path B Reconfigurable net output of a Partition Pin Path C Reconfigurable net input to a Partition Pin Path D Static net output of a Partition Pin Paths X Y and Z Register to register paths that contain a Partition Pin in the path Partial Reconfiguration User Guide www xilinx com 35 UG702 v 12 1 May 3 2010 Chapter 3 Software Tools Flow g XILINX 36 Top static X12027 Figure 3 5 Timing Paths to and from a Reconfigurable
154. to a single netlist that is easily referenced in a Partial Reconfiguration project NGCBuild takes EDIF and or NGC sources along with the full set of options that are valid for ngdbuild including sd and uc and produces a single constraint annotated NGC file www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 K XILINX Clocking Rules Clocking Rules This section discusses clocking rules and includes e Global Clocking e Regional Clocking Global Clocking Because the clocking information for every Reconfigurable Module for a particular Reconfigurable Partition is not known at the time of the first implementation the PR tools pre route each BUFG output driving a Partition Pin on that RP to all clock regions that the AREA GROUP encompasses This means that clock spines in those clock regions might not be available for static logic to use regardless of whether the RP has loads in that region In the example shown in Figure 7 1 icap_c1lk is routed to clock regions X0Y1 X0Y2 and X0Y3 prior to any placement and static logic is able to use the other clock spines in that region Figure 7 1 Pre routing Global Clock to Reconfigurable Partition If there are a large number of global clocks driving an RP Xilinx recommends that area groups that encompass complete clock regions be created to ease placement and routing of static logic For more information on the number of clocks spines per reg
155. uilding blocks for performing Partial Reconfiguration e Base regions in Virtex 6 are 40 CLBs high by 1 CLB wide e Base regions in Virtex 5 are 20 CLBs high by 1 CLB wide e Base regions in Virtex 4 are 16 CLBs high by 1 CLB wide Similar base regions exist for different element types such as block RAM IOB IO elements such as ILOGIC OLOGIC IODELAY and DSP48 Use the PlanAhead software floorplanning capabilities to examine the sizes of these base regions The Frames referenced in the PlanAhead documentation and Reconfigurable Frames in the paragraph above are not the same as the configuration frames as described in the Configuration User Guides Frames as shown in the PR Statistics tab refer to the minimum reconfigurable building blocks and cannot be broken any smaller Even if an area group that is smaller than a single reconfigurable frame is selected the entire frame is reconfigured After a Pblock has been drawn corresponding to a Reconfigurable Partition details for that Partition are shown in the Pblock Properties window The Statistics tab shows the number of frames regions covered by that Pblock and the estimated bitstream size for the Reconfigurable Partition As the size of the Pblock changes the information shown here changes accordingly Configuration Time The speed of configuration is directly related to the size of the partial bit file and the bandwidth of the configuration port T
156. ule for a Reconfigurable Partition Figure 4 12 shows that blue bbis the active RM for the RP reconfig blue The figure also shows the icon for reconfig_blue asa grey square with a gold diamond indicating that the current module is a Reconfigurable Module that is currently a black box Partial Reconfiguration User Guide www xilinx com 67 UG702 v 12 1 May 3 2010 Chapter 4 PlanAhead Support g XILINX H 0 Nets 105 Primitives 26 3 mmcm clocks clocks 3 reconfig blue rm blue E 3 Reconfigurable Modules 3 49 blue Fast 4 blue slow 4y blue bb HB reconfig_green rm areen H reconfig red rm red H 31 static DVI dvi a static DVI IF dvi if E E static IC INIT iic init Figure 4 12 Reconfigurable Partition with All Reconfigurable Modules Added 2 Using the Set as Active Reconfigurable Module command from the popup menu you can change the active module for a RP at any time This loads the netlist for the selected module into the active workspace H 6 Nets 105 H E Primitives 26 B 8 mmem clocks clocks B E reconfig blue rm blue B Reconfigurable Modules 3 E d O blue Reconfigurable Module Properties Ctrl E blue x Delete Delete HI reconfig are fi reconfig rec Setas Active Reconfigurable Module E static DVI d Show Connectivity Ctrl T u static DVL I x show Hierarchy F6 ii static IC If S Highlight Unhighlight Mark
157. ur until the end of the bitstream it is recommended that you implement a CRC checker that can check the bitstream data prior to loading it into the FPGA A complete solution to this problem requires both a software and a hardware solution The software solution will calculate CRC values on blocks or frames of data and insert the CRC value into the bitstream The hardware solution will recalculate a CRC value and compare it to the software value embedded in the bitstream This solution should be necessary only for scenarios where there is a potential risk to the integrity of the stored bit files These situations would include remote uploads of partial bit files to systems in the field or space applications subject to radiation upsets A high level schematic of such a solution would look like the following E gS E Original Partial mu File split CRC generated Partial Bit File Bit File into Sections for each Section reassembled w CRC Hardware Solution Tu ERROR e ee DUX lt gt n e BRAM ICAP Packets enter Config Data CRC calculated from Shift Data FPGA stored wo CRC BRAM check vs Packet to ICAP X12035 Figure 6 5 CRC Checking for a Partial Reconfiguration Design The top half this figure shows a high level description of the software solution This could be implemented using a script Xilinx also has a solution planned for BitGen in a future software release The lower half of the figure shows a high level descript
158. ure 6 3 Configuring by Means of a Microprocessor In addition to the standard configuration interfaces Partial Reconfiguration supports configuration by means of the Internal Configuration Access Port ICAP The ICAP protocol is identical to SelectMAP and is described in the Configuration User Guide for the FPGA device The ICAP library primitive can be instantiated in the HDL description of the FPGA design thus enabling analysis and control of the partial bit file before it is sent to the configuration port The partial bit file can be downloaded to the FPGA device through general purpose IO or gigabit transceivers and then routed to the ICAP in the FPGA fabric Partial Bit File Integrity Error detection and recovery of partial bit files have unique requirements compared to loading a full bit file If an error is detected in a full bit file when it is being loaded into an FPGA device the FPGA device never enters user mode The error is detected after the corrupt design has been loaded into configuration memory and specific signals are asserted to indicate an error condition Because the FPGA device never enters user mode the corrupt design never becomes active The designer determines the system behavior for recovering from a configuration error such as downloading a different bit file if the error condition is detected Downloading partial bit files cannot use this methodology for error detection and recovery The FPGA device is by definition
159. ust have clock spines routed within the same clock regions in all configurations See Regional Clocking in Chapter 7 for more information e Proxy logic Proxy logic although logically part of the static design must be placed at the same locations within the Area Groups allocated for the Reconfigurable Partitions e Imported Partitions All partitions that are imported must have identical placement and routing between configurations Both the static partition and any Reconfigurable Modules that are used in multiple configurations will be validated e Partition Interfaces Each RP must have the same ports in and out of the RM in each configuration pr verify Usage pr verify can be run either in PlanAhead or on the command line For information on running it within PlanAhead see Verifying Configurations in Chapter 4 Command Line Syntax pr verify verbose lt designi ncd gt design2 ncd design ncd o lt outfile gt verbose Report all messages o outfile Specify the output file name including extension If this option is not used the default file pr_verify 1log is created design ncd Entera list of at least two ncd files to be compared For the example design appearing in this User Guide the pr verify command line would be as follows pr verify verbose FastConfig FastConfig ncd SlowConfig SlowConfig ncd FSFConfig FSFConfig ncd BlankConfig BlankConfig ncd
160. vision History Convention Italic font Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design name References to other manuals See the Development System Reference Guide for more information Emphasis in text If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected Square brackets An optional entry or parameter However in bus specifications such as bus 7 0 they are required ngdbuild option_name lt design_name gt A list of items from which you Repetitive material that has been omitted B 1 ff races must choose one or more owpwr on off i in a list of Verticalbar Sep arates caii lowpwr on off choices 2 AM IOB 1 Name QOUT Vertical ellipsis ee Nane S NU ENU Horizontal ellipsis Repetitive material that has been omitted allow block block name loci loc2 locn Online Document The following conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files Revision History Date 3 Ma
161. ware or the ChipScope Core Inserter Both methods can be used in conjunction with Partial Reconfiguration but limitations do exist When using the Xilinx CORE Generator software you create netlist based cores to be instantiated in the design As long as the boundaries of the Reconfigurable Partitions are not modified these cores can be instantiated easily to debug the portion of the design in question This is easy to manage when all the ChipScope cores are placed within the static www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Interaction with Other Xilinx Tools portion of the design The ICON core must remain in the static logic due to the fact that it contains both BUFG and BSCAN elements If ILA or VLO cores are instantiated in a Reconfigurable Partition additional measures must be taken The bounding region in the floorplan must include all the necessary elements to implement the ChipScope cores specifically enough block RAM to build the requested functionality Given the size and physical location of this requirement this could have a significant impact on the Reconfigurable Partition If there is a need to debug signals in multiple regions static and reconfigurable this can be done but the appropriate signals data trigger and or control bus must be threaded up from the individual Reconfigurable Partitions to the top level This requires modifications to the Partition interface an
162. y 2010 Version 12 1 Initial release for ISE 12 1 Revision Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 www xilinx com 11 Chapter 12 www xilinx com XILINX Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Chapter 1 Introduction This chapter discusses Partial Reconfiguration and includes e Partial Reconfiguration Overview e Terminology Partial Reconfiguration Overview FPGA technology provides the flexibility of on site programming and re programming without going through re fabrication with a modified design Partial Reconfiguration PR takes this flexibility one step further allowing the modification of an operating FPGA design by loading a partial configuration file usually a partial bit file After a full bit file configures the FPGA partial bit files can be downloaded to modify reconfigurable regions in the FPGA without compromising the integrity of the applications running on those parts of the device that are not being reconfigured Figure 1 1 illustrates the premise behind Partial Reconfiguration Reconfig Block A X12001 Figure 1 1 Basic Premise of Partial Reconfiguration As shown the function implemented in Reconfig Block A is modified by downloading one of several partial bit files A1 bit A2 bit A3 bit or A4 bit The logic in the FPGA design is divided into two different types reconfigu
163. yn_black_box black_box_pad_pin port_in port_out input clk reset data_in input port_in output data_out output port_out endmodule Synplicity VHDL example reconfigurable module entity declaration within Top level HDL entity my_rm is port clk in std_logic reset in std_logic data in in std logic data out out std logic port in in std logic port out out std logic Ju attribute syn black box boolean attribute syn black box of my rm component is true attribute black box pad pin string attribute black box pad pin of my rm component is port in port out end my rm Synplicity VHDL example reconfigurable module entity declaration within Top level HDL entity my rm is port clk in std logic reset in std logic data in in std logic data out out std logic port in in std logic port out out std logic E attribute syn_black_box boolean attribute syn_black_box of my_rm component is true attribute black_box_pad_pin string attribute black_box_pad_pin of my_rm component is port_in port_out end my_rm Partial Reconfiguration User Guide www xilinx com 109 UG702 v 12 1 May 3 2010 Chapter 7 Design Considerations g XILINX 110 Packing Input Output Registers in the IOB Whenever possible it is recommended that input and output registers belong to the same partition as the associated input or output buffer This will allow the implementation
164. ynthesis design analysis planning and implementation fe Specify synthesized EDIF or NGC netlist You will be able to run post synthesis design analysis planning and implementation JV Set PR Project Create an I O Planning Project Do not specify design sources You will be able to do port assignment and verification Import ISE Place amp Route results You will be able to do post implementation analysis of your design Cancel Figure 4 1 New Project Wizard 2 Specify the top level netlist Netlist directories should be set to point to locations where other modules for static logic exist In this example all the static logic is included in top ngc The lower level reconfigurable modules will be imported later Figure 4 2 shows the New Project gt Specify Top Netlist File dialog box www xilinx com Partial Reconfiguration User Guide UG702 v 12 1 May 3 2010 XILINX Creating a Partial Reconfiguration Project B New Project x Specify Top Netlist File Specify the top level EDIF or NGC netlist file that contains the top module and optionally a list of de directories to be used as a search path Top Netlist File C PRdesigns Color2 Implementation Static top ngc Netlist directories optional Add Directories Remove Down v Copy Sources into Project lt Back Next gt Cancel Figure 4 2 Import Netlists for Static Logic Only The PlanAhead so

Xilinx Partial Reconfiguration User Guide

Contents

Download Pdf Manuals

Related Search

Related Contents