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Cortex-M3 Instruction Set Technical User's Manual

1. UXTextend cond Rd Rm ROR n where extend Is one of B Extends an 8 bit value to a 32 bit value Extends a 16 bit value to a 32 bit value cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rm Is the register holding the value to extend ROR n Is one of ROR 8 Value from Rm is rotated right 8 bits ROR 16 Value from Rm is rotated right 16 bits ROR 24 Value from Rm is rotated right 24 bits If ROR nis omitted no rotation is performed Operation These instructions do the following 1 Rotate the value from Rm right by 0 8 16 or 24 bits 2 Extract bits from the resulting value SXTB extracts bits 7 0 and sign extends to 32 bits UXTB extracts bits 7 0 and zero extends to 32 bits SXTH extracts bits 15 0 and sign extends to 32 bits UXTH extracts bits 15 0 and zero extends to 32 bits September 07 2010 71 Texas Instruments Incorporated Bitfield Instructions 6 3 3 Restrictions Do not use SP and do not use PC 6 3 4 Condition Flags These instructions do not affect the flags 6 3 5 Examples SXTH R4 R6 ROR 16 Rotate R6 right by 16 bits then obtain the lower halfword of the result and then sign extend to 32 bits and write the result to R4 UXTB R3 R10 Extract lowest byte of the value in R10 and zero extend it and write the result to R3 72 Sept
2. September 07 2010 83 Texas Instruments Incorporated Miscellaneous Instructions 8 2 8 2 1 8 2 2 8 2 3 8 2 4 8 2 5 84 CPS Change Processor State Syntax CPSeffect iflags where effect Is one of IE Clears the special purpose register Sets the special purpose register iflags Is a sequence of one or more flags i Set or clear the Priority Mask Register PRIMASK Set or clear the Fault Mask Register FAULTMASK Operation CPS changes the PRIMASK and FAULTMASK special register values See the Stellaris Data Sheet for more information about these registers Restrictions The restrictions are m Use CPS only from privileged software it has no effect if used in unprivileged software m CPS cannot be conditional and so must not be used inside an IT block Condition Flags This instruction does not change the flags Examples CPSID 1 Disable interrupts and configurable fault handlers set PRIMASK CPSID f Disable interrupts and all fault handlers set FAULTMASK CPSIE 1 Enable interrupts and configurable fault handlers clear PRIMASK CPSIE f Enable interrupts and fault handlers clear FAULTMASK September 07 2010 Texas Instruments Incorporated 8 3 8 3 1 8 3 2 8 3 3 8 3 4 Cortex M3 Instruction Set DMB Data Memory Barrier Syntax DMB cond where cond Is an optional condition code See Table 1 2 on page
3. Restrictions Rd must not be SP and must not be PC Condition Flags This instruction does not change the flags Examples MOVT R3 0xF123 Write 0xF123 to upper halfword of R3 lower halfword and APSR are unchanged September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 3 8 REV REV16 REVSH and RBIT Reverse bytes and Reverse bits 3 8 1 Syntax op cond Rd Rn where op IS any of REV Reverse byte order in a word REV16 Reverse byte order in each halfword independently REVSH Reverse byte order in the bottom halfword and sign extend to 32 bits RBIT Reverse the bit order in a 32 bit word cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rn Is the register holding the operand 3 8 2 Operation Use these instructions to change endianness of data REV Converts 32 bit big endian data into little endian data or 32 bit little endian data into big endian data REV16 Converts 16 bit big endian data into little endian data or 16 bit little endian data into big endian data REVSH Converts either m 16 bit signed big endian data into 32 bit signed little endian data m 16 bit signed little endian data into 32 bit signed big endian data 3 8 3 Restrictions Do not use SP and do not use PC September 07 2010 55 Texas Instruments Incorporated General Data Processing Instructions 3 8 4 Condition Flags These instructions do not change th
4. STREX cond Rd Rt Rn offset LDREXB cond Rt Rn STREXB cond Rd Rt Rn LDREXH cond Rt Rn STREXH cond Rd Rt Rn where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register for the returned status Rt Is the register to load or store Rn Is the register on which the memory address is based offset Is an optional offset applied to the value in Rn If offset is omitted the address is the value in Rn Operation LDREX LDREXB and LDREXH load a word byte and halfword respectively from a memory address STREX STREXB and STREXH attempt to store a word byte and halfword respectively to a memory address The address used in any Store Exclusive instruction must be the same as the address in the most recently executed Load exclusive instruction The value stored by the Store Exclusive instruction must also have the same data size as the value loaded by the preceding Load exclusive instruction This means software must always use a Load exclusive instruction and a matching Store Exclusive instruction to perform a synchronization operation see Synchronization Primitives in the Stellaris Data Sheet If a Store Exclusive instruction performs the store it writes 0 to its destination register If it does not perform the store it writes 1 to its destination register If the Store Exclusive instruction writes 0 to the destination r
5. Note Though it is possible to use MOV as a branch instruction Texas Instruments strongly recommends the use of a BX or BLX instruction to branch for software portability to the ARM Cortex M3 instruction set Condition Flags If s is specified these instructions m Update the N and z flags according to the result m Can update the C flag during the calculation of Operana2 See Flexible Second Operand on page 15 Do not affect the v flag Example MOVS R11 0x000B Write value of 0x000B to R11 flags get updated MOV R1 0xFA05 Write value of 0xFA05 to R1 flags are not updated MOVS R10 R12 Write value in R12 to R10 flags get updated MOV R3 23 Write value of 23 to R3 MOV R8 SP Write value of stack pointer to R8 MVNS R2 0xF Write value of OxFFFFFFFO bitwise inverse of OxF to R2 and update flags September 07 2010 53 Texas Instruments Incorporated General Data Processing Instructions 3 7 3 7 1 3 7 2 3 7 3 3 7 4 3 7 5 54 MOVT Move Top Syntax MOVT cond Rd imm16 where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register immi Is a 16 bit immediate constant Operation MOVT writes a 16 bit immediate value imm1 6 to the top halfword Rd 31 16 of its destination register The write does not affect Rd 15 01 The MOV MOVT instruction pair enables you to generate any 32 bit constant
6. Signed R5 R4 R5 R4 R3 x R8 September 07 2010 63 Texas Instruments Incorporated Multiply and Divide Instructions 4 3 4 3 1 4 3 2 4 3 3 4 3 4 4 3 5 64 SDIV and UDIV Signed Divide and Unsigned Divide Syntax SDIV cond Rd Rn Rm UDIV cond Rd Rn Rm where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register If Rd is omitted the destination register is Rn Rn Is the register holding the value to be divided Rm Is a register holding the divisor Operation SDIV performs a signed integer division of the value in Rn by the value in Rm UDIV performs an unsigned integer division of the value in Rn by the value in Rm For both instructions if the value in Rn is not divisible by the value in Rm the result is rounded towards zero Restrictions Do not use SP and do not use PC Condition Flags These instructions do not change the flags Examples SDIV RO R2 R4 Signed divide RO R2 R4 UDIV R8 R8 R1 Unsigned divide R8 R8 R1 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 5 Saturating Instructions Table 5 1 on page 65 shows the saturating instructions Table 5 1 Saturating Instructions Mnemonic Brief Description See Page SSAT Signed saturate 66 USAT Unsigned saturate 66 September 07 2010 65 Texas Instruments Incorporated Saturating Instructions 5 1 5 1 2
7. MOV Instruction Preferred Syntax using Shift Instruction MOV S cond Rd Rm ASR n ASR S cond Rd Rm n MOV S cond Rd Rm LSL din ifn 0 LSL S cond Rd Rm n MOV S cond Rd Rm LSR n LSR S cond Rd Rm n MOV S cond Rd Rm ROR n ROR S cond Rd Rm n MOV S cond Rd Rm RRX RRX S cond Rd Rm Also the Mov instruction permits additional forms of Operand2 as synonyms for shift instructions See ASR LSL LSR ROR and RRX on page 48 Shift Instruction MOV Instruction Synonym ASR S cond Rd Rm Rs MOV S cond Rd Rm ASR Rs LSL S cond Rd Rm Rs MOV S cond Rd Rm LSL Rs LSR S cond Rd Rm Rs MOV S cond Rd Rm LSR Rs ROR S cond Rd Rm Rs MOV S cond Rd Rm ROR Rs September 07 2010 Texas Instruments Incorporated 3 6 3 3 6 4 3 6 5 Cortex M3 Instruction Set The MVN instruction takes the value of Operand2 performs a bitwise logical NOT operation on the value and places the result into Rd Note The Movw instruction provides the same function as MOV but is restricted to using the imm1 6 operand Restrictions You can use SP and PC only in the Mov instruction with the following restrictions m The second operand must be a register without shift You must not specify the S suffix When Ra is PC in a MOV instruction m Bit 0 of the value written to the PC is ignored m A branch occurs to the address created by forcing bit 0 of that value to 0
8. Use the TEQ instruction to test if two values are equal without affecting the V or C flags TEQ is also useful for testing the sign of a value After the comparison the N flag is the logical Exclusive OR of the sign bits of the two operands 3 9 3 Restrictions Do not use SP and do not use PC 3 9 4 Condition Flags These instructions m Update the N and z flags according to the result m Can update the c flag during the calculation of Operana2 See Flexible Second Operand on page 15 Do not affect the V flag September 07 2010 57 Texas Instruments Incorporated General Data Processing Instructions 3 9 5 Examples TST RO 0x3F8 Perform bitwise AND of RO value to 0x3F8 APSR is updated but result is discarded TEQEQ R10 R9 Conditionally test if value in R10 is equal to value in R9 APSR is updated but result is discarded 58 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 4 Multiply and Divide Instructions Table 4 1 on page 59 shows the multiply and divide instructions Table 4 1 Multiply and Divide Instructions Mnemonic Brief Description See Page MLA Multiply with accumulate 32 bit result 60 MLS Multiply and subtract 32 bit result 60 MUL Multiply 32 bit result 60 SDIV Signed divide 64 SMLAL Signed multiply with accumulate 32x32 64 64 bit result 62 SMULL Signed multiply 32x32 64 bit result 62 UDIV Unsigned divide 64
9. any LDM LDR or POP instruction that writes to the PC TBB and TBH m Do not branch to any instruction inside an IT block except when returning from an exception handler m All conditional instructions except Bcond must be inside an IT block Bcond can be either outside or inside an IT block but has a larger branch range if it is inside one m Each instruction inside the IT block must specify a condition code suffix that is either the same or the logical inverse Note Your assembler might place extra restrictions on the use of IT blocks such as prohibiting the use of assembler directives within them Condition Flags This instruction does not change the flags Example ITTE NE Next 3 instructions are conditional ANDNE RO RO R1 ANDNE does not update condition flags ADDSNE R2 R2 1 ADDSNE updates condition flags MOVEQ R2 R3 Conditional move CMP RO 9 Convert RO hex value 0 to 15 into ASCII gt OMS TO BASE ITE G Next 2 instructions are conditional ADDGT R1 RO 55 Convert OxA gt A ADDLE R1 RO 48 Convert 0x0 gt O IT GT IT block with only one conditional instruction ADDGT R1 Rl 1 Increment R1 conditionally September 07 2010 Texas Instruments Incorporated ITTEE MOVEQ ADDEQ ANDNE BNE W IT ADD September 07 2010 EQ RO R1 R2 R2 10 R3 R3 1 dloop NE RO RO R1 Cortex M3 Instr
10. For store instructions m Rt can be SP for word stores only m Rt must not be PC m Rn must not be PC m Rn must be different from Rt and Rt 2 in the pre indexed or post indexed forms 2 2 4 Condition Flags These instructions do not change the flags 2 2 5 Examples LDR R8 R10 DRNE R2 R5 960 i STR R2 R9 const struc E STRH R3 R4 4 A LDRD R8 R9 R3 0x20 STRD RO R1 R8 16 28 Loa Loads R8 from the address in R10 ds conditionally R2 from a word 960 bytes above the address in R5 and inc const struc is an to Sto R4 Loa add byt Sto a constant ress in R3 in rements R5 by 960 expression rd 32 bytes and load R9 f a word 4 bytes above the add then decrement R8 by 16 and Texas Instruments Incorporated evaluating the range 0 4095 re R3 as halfword data in then increment R4 by 4 d R8 from a wo to address in above the rom a word 36 es above the address in R3 re RO to address in R8 and store R1 to ress in R8 September 07 2010 Cortex M3 Instruction Set 2 3 LDR and STR Register Offset Load and Store with register offset 2 3 1 Syntax op type cond Rt Rn Rm LSL n where op Is one of LDR Load Register STR Store Register type Is one of B Unsigned byte zero extend to 32 bits on loads SB Signed byte sign extend to 32 bits LDR only H Unsigned
11. 66 SSAT and USAT Signed Saturate and Unsigned Saturate to any bit position with optional shift before saturating Syntax op cond Rd n Rm shift s where Op Is one of SSAT Saturates a signed value to a signed range USAT Saturates a signed value to an unsigned range cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Specifies the bit position to saturate to m nranges from 1 to 32 for SSAT m nranges from 0 to 31 for USAT Rm Is the register containing the value to saturate shift s Is an optional shift applied to Rm before saturating It must be one of the following ASR s Where s is in the range 1 to 31 LSL s Where s is in the range 0 to 31 Operation These instructions saturate to a signed or unsigned n bit value The SSAT instruction applies the specified shift then saturates to the signed range 2 1 lt x lt 27 1 1 The USAT instruction applies the specified shift then saturates to the unsigned range O lt x lt 2 1 For signed n bit saturation using SSAT this means that m Ifthe value to be saturated is less than 2 7 the result returned is 2 7 m If the value to be saturated is greater than 2 1_1 the result returned is 2 7 1 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set m Otherwise the result returned is the same as the value to be saturated For unsigned
12. 73 B BL BX and BLX saisis bereeden deed 74 YAR NR NN 74 Operation re ane A AE Te te eo te en Arte tee ap 74 RESINGUONS En aan ee ET 75 Condition FIAGS tics DEE AER ASA 75 EXaMples iia d gege geneet deg Mn aires sea tee Cu 75 CBZ and CBNZ Hunt Rte E 76 NN 76 IN O O En Te 76 ee 76 Condito Fags ci en attente tir nette 76 EX Me E E E A E E a te 76 RE 77 SO EL Re sade teeceet AE AEEA 77 OPIO ER dE Re Ee Ee EE 77 Ee 78 Condition Flags EE EE 78 Etape een tr A Rabie A AS an eden dia TT eel 78 PBB and TBA EE 80 EVT 80 Operation 1 E dees 80 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set TAS E ele ET 80 1 44 Conditor Flags Gui a EE A SE 80 Z r EXampleSi rf inch titres al i liye in eee ee Aen 80 8 Miscellaneous Instructions omromoirrarr itinere 82 8 1 E NEE 83 BETA En CN 83 8 1 2 Operations tite ant Men N Re ane cesse antenne entente ne tn ete et 83 8 1 3 Condition Ee ET 83 8 14 EXamples ti AT CA aae a a IAE Ad 83 8 2 OPS at I TETE T I A a ln Me end et de A tte 84 NC EE 84 8 2 2 Op ration en Ae aes eens A ds Sie adn ean eatin eee 84 8 2 3 Restrictions Ahsa ao nadae tt AA RA 84 824 Condition Fags ranirea a eeka a ica 84 3 20 Examples Aen ner Ee Bee pd ete a A at tine ook Ee aa foes Deena An 84 8 3 DMB SA E A EE A A A A OO as Us e 85 ET SAR oar a Aaaa AAAA deg degen dag en dan na 85 Ie O e Ee 85 8 3 3 Condition Flags E 85 8 34 EE Een tat A dee ee Zeg 85 8 4 DS heet en
13. Instructions 8 8 8 8 1 8 8 2 8 8 3 8 8 4 90 NOP No Operation Syntax NOP cond where cond IS an optional condition code See Table 1 2 on page 22 Operation NOP does nothing NOP is not necessarily a time consuming NOP The processor might remove it from the pipeline before it reaches the execution stage Use NOP for padding for example to place the following instruction on a 64 bit boundary Condition Flags This instruction does not change the flags Examples NOP No Operation Texas Instruments Incorporated September 07 2010 Cortex M3 Instruction Set 8 9 SEV Send Event 8 9 1 Syntax SEV cond where cond Is an optional condition code See Table 1 2 on page 22 8 9 2 Operation SEV is a hint instruction that causes an event to be signaled to all processors within a multiprocessor system lt also sets the one bit event register to 1 See Power Management in the Stellaris Data Sheet 8 9 3 Condition Flags This instruction does not change the flags 8 9 4 Examples SEV Send Event September 07 2010 91 Texas Instruments Incorporated Miscellaneous Instructions 8 10 8 10 1 8 10 2 8 10 3 8 10 4 92 SVC Supervisor Call Syntax SVC cond imm where cond Is an optional condition code See Table 1 2 on page 22 imm Is an expression evaluating to an integer in the range 0 255 8 bit value Operation T
14. LookUpTable LDRSB R7 localdata Load a byte value from an address labeled as localdata sign extend it to a word value and put it in R7 September 07 2010 Texas Instruments Incorporated 2 6 2 6 1 LDM and STM Load and Store Multiple registers Syntax op addr_mode cond Rn reglist where Op Is one of LDM Load Multiple registers STM Store Multiple registers addr_mode Is any one of the following IA Increment address After each access This is the default DB Decrement address Before each access cond Is an optional condition code See Table 1 2 on page 22 Rn Is the register on which the memory addresses are based Cortex M3 Instruction Set Is an optional writeback suffix If is present then the final address that is loaded from or stored to is written back into Rn reglist Is a list of one or more registers to be loaded or stored enclosed in braces It can contain register ranges It must be comma separated if it contains more than one register or register range See Examples on page 36 Descending stacks Ascending stacks September 07 2010 Texas Instruments Incorporated LDM and LDMFD are synonyms for LDMIA LDMFD refers to its use for popping data from Full DMEA is a synonym for LDMDB and refers to its use for popping data from Empty Ascending stacks STM and STMEA are synonyms for STMIA STMEA refers to its use for p
15. Unsigned multiply 32x 2 64 bit result 62 USAT Rd n Rm shift s Unsigned saturate Q 66 UXTB Rd Rm ROR n Zero extend a byte 71 UXTH Rd Rm ROR n Zero extend a halfword 71 WFE Wait for event 93 WFI Wait for interrupt 94 1 2 About The Instruction Descriptions The following sections give more information about using the instructions m Operands on page 15 m Restrictions When Using the PC or SP on page 15 m Flexible Second Operand on page 15 m Shift Operations on page 17 m Address Alignment on page 20 m PC Relative Expressions on page 20 m Conditional Execution on page 20 m Instruction Width Selection on page 22 1 2 1 Operands An instruction operand can be an ARM Cortex M3 register a constant or another instruction specific parameter Instructions act on the operands and often store the result in a destination register When there is a destination register in the instruction it is usually specified before the operands Operands in some instructions are flexible in that they can either be a register or a constant See Flexible Second Operand on page 15 See the Stellaris Data Sheet for more information on the ARM Cortex M3 registers 1 2 2 Restrictions When Using the PC or SP Many instructions have restrictions on whether you can use the Program Counter PC or Stack Pointer SP for the operands or destination register See the instruction des
16. and R1 setting flags ITT GT IT instruction for the two GT conditions CMPGT R2 R3 If greater than compare R2 and R3 setting flags MOVGT R4 R5 If still greater than do R4 R5 Instruction Width Selection There are many instructions that can generate either a 16 bit encoding or a 32 bit encoding depending on the operands and destination register specified For some of these instructions you can force a specific instruction size by using an instruction width suffix The w suffix forces a 32 bit instruction encoding The N suffix forces a 16 bit instruction encoding If you specify an instruction width suffix and the assembler cannot generate an instruction encoding of the requested width it generates an error Note In some cases it might be necessary to specify the w suffix for example if the operand is the label of an instruction or literal data as in the case of branch instructions This is because the assembler might not automatically generate the right size encoding September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set To use an instruction width suffix place it immediately after the instruction mnemonic and condition code if any Example 1 3 Instruction Width Selection on page 23 shows instructions with the instruction width suffix Example 1 3 Instruction Width Selection BCS W label creates a 32 bit instruction even for a short branch ADDS W RO RO R1 creates a 32 b
17. and if the carry flag is updated it is updated to bit 31 of Rm m ROR with shift length n more than 32 is the same as ROR with shift length n1132 Figure 1 4 ROR 3 Carry Flag Br eehh I LEE LH RRX A rotate right with extend RRX moves the bits of the register Rm to the right by one bit And it copies the carry flag into bit 31 of the result See Figure 1 5 on page 19 When the instruction is RRXS or when RRX is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to bit 0 of the register Rm Figure 1 5 RRX Carry Flag e NEID NR D RER September 07 2010 19 Texas Instruments Incorporated Introduction 1 2 5 1 2 6 1 2 7 20 Address Alignment An aligned access is an operation where a word aligned address is used for a word dual word or multiple word access or where a halfword aligned address is used for a halfword access Byte accesses are always aligned The Cortex M3 processor supports unaligned access only for the following instructions LDR LDRT LDRE LDRHT LDRSH LDRSHT STR STRT STRH STRH All other load and store instructions generate a usage fault exception if they perform an unaligned access and therefore their accesses must be address aligned For more information about usage faults see Fault Handling in the Stellaris Data Sheet Unaligned accesses are usua
18. cond Is an optional condition code See Table 1 2 on page 22 Operation Use CLREX to make the next STREX STREXB or STREXH instruction write 1 to its destination register and fail to perform the store It is useful in exception handler code to force the failure of the store exclusive if the exception occurs between a load exclusive instruction and the matching store exclusive instruction in a synchronization operation see Synchronization Primitives in the Stellaris Data Sheet Condition Flags These instructions do not change the flags Examples CLREX September 07 2010 41 Texas Instruments Incorporated General Data Processing Instructions 3 General Data Processing Instructions Table 3 1 on page 42 shows the data processing instructions Table 3 1 General Data Processing Instructions Mnemonic Brief Description See Page ADC Add with carry 43 ADD Add 43 ADDW Add 43 AND Logical AND 46 ASR Arithmetic shift right 48 BIC Bit clear 46 CLZ Count leading zeros 50 CMN Compare negative 51 CMP Compare 51 EOR Exclusive OR 46 LSL Logical shift left 48 Logical shift right 48 Move Move top Move 16 bit constant Move NOT Logical OR NOT Logical OR Reverse bits Reverse byte order in a word Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend Rotate right Rotate right w
19. determines the address by adding an immediate value to the PC and writes the result to the destination register ADR produces position independent code because the address is PC relative If you use ADR to generate a target address for a BX or BLX instruction you must ensure that bit 0 of the address you generate is set to 1 for correct execution Values of 1abe1 must be within the range of 4095 to 4095 from the address in the PC Note You might have to use the w suffix to get the maximum offset range or to generate addresses that are not word aligned See Instruction Width Selection on page 22 2 1 3 Restrictions Rd must not be SP and must not be PC 2 1 4 Condition Flags This instruction does not change the flags 2 1 5 Examples ADR R1 TextMessage Write address value of a location labeled as TextMessage to R1 September 07 2010 25 Texas Instruments Incorporated Memory Access Instructions 2 2 LDR and STR Immediate Offset Load and Store with immediate offset pre indexed immediate offset or post indexed immediate offset 2 2 1 Syntax op type cond Rt Rn offset immediate offset op type cond Rt Rn offset pre indexed op type cond Rt Rn offset post indexed opD cond Rt Rt2 Rn offset immediate offset two words opD cond Rt Rt2 Rn offset pre indexed two words opD cond Rt Rt2 Rn offset p
20. eege Gebeier Leed deeg 86 A EE met DS Rene nn de Ca ee 86 8 42 Op raton ss vat T en En A tine Ret ake Ge wiles d AY 86 9 43 Condition GET EE 86 9 44 AEXAMPIES casey iris dod Ae emmener ann pane dede sente Ca Cee a ma Qi mnt peda ge due ren re tada 86 8 5 ETC NEE 87 B A internet ee hate ner AE ee detain 87 e e Ee NEE 87 8 5 3 Condition Flags reier iniedi iit eda ead es NENNEN Red A le annee net 87 Nk East nt A ATEN an ft Mt da nt an r de it Al ane 87 8 6 MR Sarea eA TEA OE A Ee EE 88 SIGE MEDIEN e e Ee Re M A en AA 88 E e Ee EE 88 8 6 3 sIRESUICHONS sta ri ta lid ata ile tedetal 88 8 6 4 Al artnet menant costae re ua tirant TRO 88 8 6 51 Examples tia ea eed een ele eed adele ment vee eee en 88 8 7 MORE ARR he Se anh haha section ek ona ht eae ees eaten hades este deren eee 89 AS TAN 89 Nee te 89 SI Restrictions 1d deet an tra ne none ed eege 89 8 7 4 Condition Flag vit nd 89 8 7 94 WEXAMPpPIES ebe ee EE e Taie dns Tarn ae eg 89 8 8 NOP occitano con stiateest abies Madsaeadadioend A EA Mtkatdeauasausedzeituneed AEAEE 90 BOs SVM aKa este Ee E dee Rae nest tee ad edad ch ere teen 90 8 8 2 Operation Awe ce ie Ate eh ee PE Ge dt a ta al atte 90 8 8 3 Condition Te 90 8 84 A ts O dt nt te B bee Pots ebe 90 8 9 SEVA gege ee ee Ee 91 September 07 2010 7 Texas Instruments Incorporated Table of Contents 8 9 1 8 9 2 8 9 3 8 9 4 8 10 8 10 1 8 10 2 8 10 3 8 10 4 8 11 8 11 1 8 11 2 8 11 3 8 11 4 8 12
21. halfword zero extend to 32 bits on loads SH Signed halfword sign extend to 32 bits LDR only Omit for word cond Is an optional condition code See Table 1 2 on page 22 Rt Is the register to load or store Rn Is the register on which the memory address is based Rm Is a register containing a value to be used as the offset LSL n Is an optional shift with n in the range 0 to 3 2 3 2 Operation LDR instructions load a register with a value from memory September 07 2010 29 Texas Instruments Incorporated Memory Access Instructions 2 3 3 2 3 4 2 3 5 30 STR instructions store a register value into memory The memory address to load from or store to is at an offset from the register Rn The offset is specified by the register Rm and can be shifted left by up to 3 bits using LSL The value to load or store can be a byte halfword or word For load instructions bytes and halfwords can either be signed or unsigned See Address Alignment on page 20 Restrictions In these instructions Rn must not be PC Rm must not be SP and must not be PC m Rt can be SP only for word loads and word stores m Rt can be PC only for word loads When Rt is PC in a word load instruction m Bit 0 of the loaded value must be 1 for correct execution and a branch occurs to this halfword aligned address m Ifthe instruction is conditional it must be the last instruction in the IT block Condition Flags These inst
22. its AE A ge es AE A eee tt eae 64 A ER dif gash en ET 64 4 3 4 Condition EISE isorine salad dededetdade DE NEE relate telle et 64 4 39 59 EXAMPpIGS Zeng red dense tata a a Tu ere da Re dh a 64 September 07 2010 5 Texas Instruments Incorporated Table of Contents 5 1 5 1 1 5 1 2 5 1 3 5 1 4 5 1 5 6 1 6 1 1 6 1 2 6 1 3 6 1 4 6 1 5 6 2 6 2 1 6 2 2 6 2 3 6 2 4 6 2 5 6 3 6 3 1 6 3 2 6 3 3 6 3 4 6 3 5 7 1 7 1 1 7 1 2 7 1 3 7 1 4 7 1 5 7 2 7 2 1 7 2 2 7 2 3 7 2 4 7 2 5 7 3 7 3 1 7 3 2 7 3 3 7 3 4 7 3 5 7 4 7 4 1 7 4 2 Saturating RE ten CET 65 SSAr aNd RE 66 SM a tne lined eit te T eee 66 Operation sects xcs ne chest Se hee chs PAL tags bre a ack Mad Sha ince de MR BEE mee ai aces 66 ReESINIGUONS EE 67 Condition Fags iii dd 67 Examples rio Men tt nt an ete ARR Eeer 67 Bitheld instr ctiOns iessen de gedet gege deg EEGENEN ENEE 68 BG and Bl nn Ee EE see dE Hokie EA EE 69 O een M A E rt en ee ele Pet nat eee sien tar 69 Operations maani tte obtained 69 Ee e 69 Condition ElagS imstande lt dit 69 Examples geeiert ata asi tn dees 69 SBEXANd UBEX in Pr ne nan ee SR Mine A PUR EE 70 EM 70 Operation ida 70 RESITICLONS EE E EE EE 70 Condition Le EE 70 LE TA EC eege E aa 70 Sad UXT iaa 71 VII 71 Op ration A Te A ee St Lance ee ne on 71 Eder 72 Condition Flags EE 72 EXAMPICS orita TT nn tree ed Eeselen eh danse tdi 72 Branch and Control Instructions ss
23. not change the flags Examples MRS RO PRIMASK Read PRIMASK value and write it to RO September 07 2010 Texas Instruments Incorporated 8 7 8 7 1 8 7 2 8 7 3 8 7 4 8 7 5 Cortex M3 Instruction Set MSR Move the contents of a general purpose register to a special register Syntax MSR cond spec reg Rn where cond IS an optional condition code See Table 1 2 on page 22 Rn Is the source register spec_reg Can be any of APSR IPSR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK BASEPRI BASEPRI_MAX FAULTMASK or CONTROL Operation The register access operation in MSR depends on the privilege level Unprivileged software can only access the Application Program Status Register APSR see APSR in the Sfellaris Data Sheet Privileged software can access all special registers In unprivileged software writes to unallocated or execution state bits in the PSR are ignored Note When you write to BASEPRI_ MAX the instruction writes to BASEPRI only if either m Rnis non zero and the current BASEPRI value is 0 m Rn is non zero and less than the current BASEPRI value See also MRS on page 88 Restrictions Rn must not be SP and must not be PC Condition Flags This instruction updates the flags explicitly based on the value in Rn Examples MSR CONTROL R1 Read R1 value and write it to the CONTROL register September 07 2010 89 Texas Instruments Incorporated Miscellaneous
24. subtract a 96 bit integer contained in R9 R1 and R11 from another contained in R6 R2 and R8 The example stores the result in R6 R9 and R2 Example 3 2 96 Bit Subtraction SUBS R6 R6 R9 Subtract the least significant words SBCS R9 R27 RI Subtract the middle words with carry SBC R2 R8 R11 Subtract the most significant words with carry September 07 2010 45 Texas Instruments Incorporated General Data Processing Instructions 3 2 3 2 1 3 2 2 46 AND ORR EOR BIC and ORN Logical AND OR Exclusive OR Bit Clear and OR NOT Syntax op S cond Rd Rn Operand2 where Op Is one of AND Logical AND ORR Logical OR or bit set EOR Logical Exclusive OR BIC Logical AND NOT or bit clear ORN Logical OR NOT Is an optional suffix If S is specified the condition code flags are updated on the result of the operation See Conditional Execution on page 20 cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rn Is the register holding the first operand Operand2 Is a flexible second operand See Flexible Second Operand on page 15 for details of the options Operation The AND EOR and ORR instructions perform bitwise AND Exclusive OR and OR operations on the values in Rn and Operand2 The BIC instruction performs an AND operation on the bits in Rn with the complements of the corresponding bits in the valu
25. the processor so that all instructions following the ISB are fetched from cache or memory again after the ISB instruction has been completed Condition Flags This instruction does not change the flags Examples ISB Instruction Synchronization Barrier September 07 2010 87 Texas Instruments Incorporated Miscellaneous Instructions 8 6 8 6 1 8 6 2 8 6 3 8 6 4 8 6 5 88 MRS Move the contents of a special register to a general purpose register Syntax MRS cond Rd spec reg where cond Is an optional condition code See Table 1 2 on page 22 Rd IS the destination register spec_reg Can be any of the following special registers APSR IPSR EPSR IEPSR IAPSR EAPSR PSR MSP PSP PRIMASK BASEPRI BASEPRI_MAX FAULTMASK or CONTROL Operation Use MRS in combination with MSR as part of a read modify write sequence for updating a PSR for example to clear the Q flag In process swap code the programmers model state of the process being swapped out must be saved including relevant PSR contents Similarly the state of the process being swapped in must also be restored These operations use MRS in the state saving instruction sequence and MSR in the state restoring instruction sequence Note BASEPRI_MAX is an alias of BASEPRI when used with the MRS instruction See also MSR on page 89 Restrictions Rd must not be SP and must not be PC Condition Flags This instruction does
26. 22 Operation DMB acts as a data memory barrier It ensures that all explicit memory accesses that appear before the DMB instruction in program order are completed before any explicit memory accesses that appear after the DMB instruction in program order DMB does not affect the ordering or execution of instructions that do not access memory Condition Flags This instruction does not change the flags Examples DMB Data Memory Barrier September 07 2010 85 Texas Instruments Incorporated Miscellaneous Instructions 8 4 8 4 1 8 4 2 8 4 3 8 4 4 86 DSB Data Synchronization Barrier Syntax DSB cond where con d Is an optional condition code See Table 1 2 on page 22 Operation DSB acts as a special data synchronization memory barrier Instructions that come after DSB in program order do not execute until the DSB instruction completes The DSB instruction completes when all explicit memory accesses before it complete Condition Flags This instruction does not change the flags Examples DSB r Data Synchronization Barrier Texas Instruments Incorporated September 07 2010 Cortex M3 Instruction Set 8 5 8 5 1 8 5 2 8 5 3 8 5 4 ISB Instruction Synchronization Barrier Syntax ISB cond where cond IS an optional condition code See Table 1 2 on page 22 Operation ISB acts as an instruction synchronization barrier It flushes the pipeline of
27. 30 bytes after the instruction m These instructions must not be used inside an IT block Condition Flags These instructions do not change the flags Examples CBZ R5 target Forward branch if R5 is zero CBNZ RO target Forward branch if RO is not zero September 07 2010 Texas Instruments Incorporated 7 3 7 3 1 7 3 2 Cortex M3 Instruction Set IT If Then Syntax IT x y z cond Where X Specifies the condition switch for the second instruction in the IT block Yy Specifies the condition switch for the third instruction in the IT block zZ Specifies the condition switch for the fourth instruction in the IT block cond Specifies the condition for the first instruction in the IT block The condition switch for the second third and fourth instruction in the IT block can be either p Then Applies the condition cond to the instruction Else Applies the inverse condition of cond to the instruction Note Itis possible to use AL the always condition for cond in an IT instruction If this is done all of the instructions in the IT block must be unconditional and each of x y and z must be T or omitted but not E Operation The IT instruction makes up to four following instructions conditional The conditions can be all the same or some of them can be the logical inverse of the others The conditional instructions following the IT instruction form the T block The instructions in the IT blo
28. 6 Logical shift right by 6 bits ROR R4 R5 R6 Rotate right by the value in the bottom byte of R6 RRX R4 R5 Rotate right with extend September 07 2010 49 Texas Instruments Incorporated General Data Processing Instructions 3 4 3 4 1 3 4 2 3 4 3 3 4 4 3 4 5 50 CLZ Count Leading Zeros Syntax CLZ cond Rd Rm where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rm Is the operand register Operation The CLZ instruction counts the number of leading zeros in the value in Rm and returns the result in Rd The result value is 32 if no bits are set in the source register and zero if bit 31 is set Restrictions Do not use SP and do not use PC Condition Flags This instruction does not change the flags Examples CLZ R4 R9 CLZNE R2 R3 Texas Instruments Incorporated September 07 2010 Cortex M3 Instruction Set 3 5 CMP and CMN Compare and Compare Negative 3 5 1 Syntax CMP cond Rn Operand2 CMN cond Rn Operand2 where cond Is an optional condition code See Table 1 2 on page 22 Rn Is the register holding the first operand Operand2 Is a flexible second operand See Flexible Second Operand on page 15 for details of the options 3 5 2 Operation These instructions compare the value in a register with Operand2 They update the condition flags on the result but do not write the result to
29. 8 12 1 8 12 2 8 12 3 8 12 4 SO ER A sebheeeezeda A AE A ATEN 91 Op ration BEE 91 Condition Flags eet s t dali aie A ARET 91 E le 91 SNE ee 92 A re dans a nee cul wate cash ae Ay dale de ar ee cat nat Ne dant 92 Operation k ieren Eenheet mettant a e ee die 92 Condition Flag nn ida ar Me be onde ee cia 92 Eeler tase a Rd Ee eege 92 US GETT 93 DIM EEE RS e EET E 93 Op ration Rene tetas hart engl as tall ae 93 Condition Plaga e ee a a 93 Ex mMpl eS A e TS 24 93 VU WE 94 SNE re ent ge caida deeg ee ti dant unten Ae 94 IER 94 Condition FAQS si eege A ete te ideas tied age e eee 94 EXA MPICS ege Ladies rade tes La swag eee rare diese nant se nan EE eg 94 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set List of Figures Fig re Ta To ASR AS sie TR ee aa EE 17 Figure T A LOR Fo set iis in adds sade aati a A te 18 Figure 1 3 JESL EE 19 Figure TA SIRORAS TTT 19 Figure 155 IRRA EE 19 September 07 2010 9 Texas Instruments Incorporated Table of Contents List of Tables 10 Table 1 1 Table 1 2 Table 2 1 Table 2 2 Table 2 3 Table 3 1 Table 4 1 Table 5 1 Table 6 1 Table 7 1 Table 7 2 Table 8 1 Cortex M3 Instructions ated Me ad 12 Condition Code Suffixes Herrera a 22 Memory Access INStructions correran a EA AA 24 Offset Ranges eerta a a tt tt 27 TT 34 General Data Processing Instructions oocccooonncccnnoncccnnnnnaccnnnnnnccnnnnnnccnnnnnncrnnnnnnon 42 Mu
30. BNZ instructions to compare the value of a register against zero and branch on the result 1 2 7 1 Condition Flags The Application Program Status Register APSR contains the following condition flags m N Set to 1 when the result of the operation was negative cleared to 0 otherwise m Z Set to 1 when the result of the operation was zero cleared to 0 otherwise m C Set to 1 when the operation resulted in a carry cleared to 0 otherwise m V Set to 1 when the operation caused overflow cleared to O otherwise For more information about APSR see the Stellaris Data Sheet A carry occurs m If the result of an addition is greater than or equal to 23 m lf the result of a subtraction is positive or zero m As the result of an inline barrel shifter operation in a move or logical instruction Overflow occurs if the result of an add subtract or compare is greater than or equal to 231 or less than 221 Note Most instructions update the status flags only if the S suffix is specified See the instruction descriptions for more information 1 2 7 2 Condition Code Suffixes The instructions that can be conditional have an optional condition code shown in syntax descriptions as cond Conditional execution requires a preceding IT instruction An instruction with a condition code is only executed if the condition code flags in APSR meet the specified condition Table 1 2 on page 22 shows the condition codes to use You can use conditional execution with th
31. Flags These instructions do not change the flags 7 1 5 Examples B loopA BLE ng B W target BEQ target BEQ W target BL func S H BX LR S BXNE RO BLX RO September 07 2010 Branch to lo Conditionall Branch to ta Conditionall Conditional Branch with stored in LR Return from Conditionall Branch with in RO OPA y branch to label ng rget within 16MB range y branch to target ly branch to target within 1MB link Call to function funC return address function call y branch to address stored in RO link and exchange Call to a address stored 75 Texas Instruments Incorporated Branch and Control Instructions 7 2 7 2 1 7 2 2 7 2 3 7 2 4 7 2 5 76 CBZ and CBNZ Compare and Branch if Zero Compare and Branch if Non Zero Syntax CBZ Rn label CBNZ Rn label where Rn Is the register holding the operand label Is the branch destination Operation Use the CBZ or CBNZ instructions to avoid changing the condition code flags and to reduce the number of instructions CBZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BEQ label CBNZ Rn label does not change condition flags but is otherwise equivalent to CMP Rn 0 BNE label Restrictions The restrictions are m Rn must be in the range of RO to R7 m The branch destination must be within 4 to 1
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33. Restrictions The restrictions are m Rn must not be SP Rmmust not be SP and must not be PC m When any of these instructions is used inside an IT block it must be the last instruction of the IT block Condition Flags These instructions do not change the flags Examples ADR W RO BranchTable_Byte TBB RO R1 R1 is the index RO is the base address of the branch table Casel an instruction sequence follows Case2 an instruction sequence follows September 07 2010 Texas Instruments Incorporated Case3 an instruction BranchTable Byte sequence follows Cortex M3 Instruction Set DCB 0 Casel offset calculation DCB Case2 Casel 2 Case2 offset calculation DCB Case3 Casel 2 Case3 offset calculation TBH PC R1 LSL 1 R1 is the index PC is used as base of the BranchTable_H DCI CaseA DCI CaseB DCI CaseC CaseA an instruction CaseB an instruction CaseC an instruction September 07 2010 branch table BranchTable H 2 CaseA offset calculation BranchTable H 2 CaseB offset calculation BranchTable H 2 CaseC offset calculation sequence follows sequence follows sequence follows Texas Instruments Incorporated 81 Miscellaneous Instructions 8 Miscellaneous Instructions Table 8 1 on page 82 shows the remaining Cortex M3 instructions Table 8 1 Miscell
34. S ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to the last bit shifted out bit n 1 of the register Rm Note m If nis 32 or more then all the bits in the result are set to the value of bit 31 of Rm m If nis 32 or more and the carry flag is updated it is updated to the value of bit 31 of Rm Figure 1 1 ASR 3 September 07 2010 17 Texas Instruments Incorporated Introduction 1 2 4 2 LSR A logical shift right LSR by n bits moves the left hand 320 n bits of the register Rm to the right by n places into the right hand 32 in bits of the result And it sets the left hand n bits of the result to 0 See Figure 1 2 on page 18 You can use the LSR n operation to divide the value in the register Rm by 2 if the value is regarded as an unsigned integer When the instruction is LSRS or when LSR n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to the last bit shifted out bit n 1 of the register Rm Note am If nis 32 or more then all the bits in the result are cleared to 0 m If nis 33 or more and the carry flag is updated it is updated to 0 Figure 1 2 LSR 3 1 243 LSL A logical shift left LSL by n bits moves the right hand 320 n bits of the register Rm to the left by n places into the left hand 320 n bits of the result And it sets the right hand n bits of the result to 0 S
35. TEXAS INSTRUMENTS INCORPORATED 14 Texas INSTRUMENTS Cortex M3 Instruction Set TECHNICAL USER S MANUAL UM COREISM 7703 Copyright 2010 Texas Instruments Inc Copyright Copyright 2010 Texas Instruments Inc All rights reserved Stellaris and Stellaris Ware are registered trademarks of Texas Instruments ARM and Thumb are registered trademarks and Cortex is a trademark of ARM Limited Other names and brands may be claimed as the property of others Texas Instruments Incorporated on nu oe 108 Wild Basin Suite 350 13 TEXAS g Co te Austin TX 78746 INSTRUMENTS ARM Intelligent Processors by ARM http www ti com stellaris http www k ext ti com sc technical support product information centers htm 2 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Table of Contents 1 1 1 2 1 2 1 1 2 2 1 2 3 1 2 4 1 2 5 1 2 6 1 2 7 1 2 8 2 1 2 1 1 2 1 2 2 1 3 2 1 4 2 1 5 2 2 2 2 1 2 2 2 2 2 3 2 2 4 2 2 5 2 3 2 3 1 2 3 2 2 3 3 2 3 4 2 3 5 2 4 2 4 1 2 4 2 2 4 3 2 4 4 2 4 5 2 5 2 5 1 2 5 2 2 5 3 2 5 4 2 5 5 2 6 2 6 1 2 6 2 ld ge e d EE Instruction Set SUMMANY arrete nr di About The Instruction Descriptions ooooooocccccncccocccnoncccnnnnnnnnonnoncnnnncnnnoncncnnnnnonannnnnencnnnnns Operands eaei teisena aa aao aia raa dai nn nl An ins Restrictions When Using the PC or SP sienne Flexible Second Operand sise Shift Ee te EE Address Alignment ege ana vas
36. UMLAL Unsigned multiply with accumulate 32x32 64 64 bit result 62 UMULL Unsigned multiply 32x32 64 bit result 62 September 07 2010 59 Texas Instruments Incorporated Multiply and Divide Instructions 4 1 4 1 1 60 MUL MLA and MLS Multiply Multiply with Accumulate and Multiply with Subtract using 32 bit operands and producing a 32 bit result Syntax MUL S cond Rd Rn Rm Multiply MLA cond Rd Rn Rm Ra Multiply with accumulate MLS cond Rd Rn Rm Ra Multiply with subtract where cond Is an optional condition code See Table 1 2 on page 22 Is an optional suffix If S is specified the condition code flags are updated on the result of the operation See Conditional Execution on page 20 Rd Is the destination register If Rd is omitted the destination register is Rn Rn Rm Are registers holding the values to be multiplied Ra Is a register holding the value to be added or subtracted from Operation The MUL instruction multiplies the values from Rn and Rm and places the least significant 32 bits of the result in Ra The MLA instruction multiplies the values from Rn and Rm adds the value from Ra and places the least significant 32 bits of the result in Rd The MLS instruction multiplies the values from Rn and Rm subtracts the product from Ra and places the least significant 32 bits of the result in Ra The results of these instructions do not depend on wheth
37. a register The CMP instruction subtracts the value of Operand2 from the value in Rn This is the same as a SUBS instruction except that the result is discarded The CMN instruction adds the value of Operand to the value in Rn This is the same as an ADDS instruction except that the result is discarded 3 5 3 Restrictions In these instructions Do not use PC m Operand2 must not be SP 3 5 4 Condition Flags These instructions update the N Z C and v flags according to the result 3 5 5 Examples CMP R2 R9 CMN RO 6400 CMPGT SP R7 LSL 2 September 07 2010 51 Texas Instruments Incorporated General Data Processing Instructions 3 6 3 6 1 3 6 2 52 MOV and MVN Move and Move NOT Syntax MOV S cond Rd Operand2 MOV cond Rd imml6 MVN S cond Rd Operand2 where S Is an optional suffix If S is specified the condition code flags are updated on the result of the operation See Conditional Execution on page 20 cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Operand2 Is a flexible second operand See Flexible Second Operand on page 15 for details of the options imm16 Is any value in the range 0 65535 Operation The Mov instruction copies the value of Operana2 into Rd When Operana2 in a MOV instruction is a register with a shift other than LSL 0 the preferred syntax is the corresponding shift instruction
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39. aneous Instructions Mnemonic Brief Description See Page BKPT Breakpoint 83 CPSID Change processor state disable interrupts 84 CPSIE Change processor state enable interrupts 84 DMB Data memory barrier 85 DSB Data synchronization barrier 86 ISB Instruction synchronization barrier 87 MRS Move from special register to register 88 MSR Move from register to special register 89 NOP No operation 90 SEV Send event 91 SVC Supervisor call 92 WFE Wait for event 93 WFI Wait for interrupt 94 82 September 07 2010 Texas Instruments Incorporated 8 1 8 1 1 8 1 2 8 1 4 Cortex M3 Instruction Set BKPT Breakpoint Syntax BKPT imm where imm Is an expression evaluating to an integer in the range 0 255 8 bit value Operation The BKPT instruction causes the processor to enter Debug state Debug tools can use this to investigate system state when the instruction at a particular address is reached imm is ignored by the processor If required a debugger can use it to store additional information about the breakpoint The BKPT instruction can be placed inside an IT block but it executes unconditionally unaffected by the condition specified by the IT instruction Condition Flags This instruction does not change the flags Examples BKPT OxAB Breakpoint with immediate value set to OxAB debugger can extract the immediate value by locating it using the PC
40. ck including any branches must specify the condition in the cond part of their syntax Note Your assembler might be able to generate the required IT instructions for conditional instructions automatically so that you do not need to write them yourself See your assembler documentation for details A BKPT instruction in an IT block is always executed even if its condition fails Exceptions can be taken between an IT instruction and the corresponding IT block or within an IT block Such an exception results in entry to the appropriate exception handler with suitable return information in LR and stacked PSR See the PSR register in the Stellaris Data Sheet for more information Instructions designed for use for exception returns can be used as normal to return from the exception and execution of the IT block resumes correctly This is the only way that a PC modifying instruction is permitted to branch to an instruction in an IT block September 07 2010 77 Texas Instruments Incorporated Branch and Control Instructions 7 3 3 7 3 4 7 3 5 78 Restrictions The following instructions are not permitted in an IT block a IT m CBZ and CBNZ m CPSID and CPSI GI Other restrictions when using an IT block are m branch or any instruction that modifies the PC must either be outside an IT block or must be the last instruction inside the IT block These are ADD PC PC Rm MOV PC Rm B BL BX BLX
41. cou bees EE de nn E eege Ale ua 37 Operation sles eee a ie eee ee ie ree be le eee 37 FRESIICUONS EEE salle chante an a Pen anes sees nt net ce sake neuen weld cava senc fe dares pale hy 37 Condon Flade TEE TEE 37 EXaMples gt testa heal he E re met Et eebe ed mn At de nn ts 38 LDREX andi AR EE 39 LEE 39 IEN 39 Ener e 40 Condition ElagS EE 40 Example Srne aea a aE a A EN te en A eet 40 OR RE EE 41 E D OR E AE A E A TE E ET 41 Operation ca da 41 Condition Flags atm a 41 A a ei et et 41 General Data Processing Instructions ooomnnnnncccnnnnnnnnancnnnnnnnnnnnnnnannnn cnn nn nn 42 ADD ADC SUB SBC and RSB gt rege al A a A Ed 43 VULLE EE 43 Op ration nn Rue in nie E a TN uh tu Mises ee Mate das a Te 43 ee 44 Condition Flags cia teh laden ee a ln d in 44 E le 45 Multiword Arithmetic Examples 0 cccccceeceeeeece cece ee eeeeeeee ae eeeeeeeeeaeeeeeaeeesaeeesaeeeeaeeeea 45 AND ORR EOR BIC and ORN 0000 46 Eu 46 le e RE 46 Ee e rt EE 47 Condition FIAQGS tics 47 Eelere acen 47 ASR ESL ESR ROR and RRX ui Seed EENS EENS NN AEN 48 DMA A a taa 48 OPSration iii EE 49 ee 49 Condition Fags EE 49 E le 49 CU coat A ee ee eebe 50 LTE 50 Operation rss ee A em tn dt remet ens 50 Ee 50 Condition Flag TEE 50 EXamples 2 201242 mines te it ae E eee Pal Ru shit den di Pt nt nt se 50 GMP And OMNr egene ege seed date Manet a ee sd eg eege 51 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Se
42. criptions for more information Important Bit 0 of any address you write to the PC with a BX BLX LDM LDR or POP instruction must be 1 for correct execution because this bit indicates the required instruction set and the Cortex M3 processor only supports Thumb instructions 1 2 3 Flexible Second Operand Many general data processing instructions have a flexible second operand This is shown as Operana2 in the descriptions of the syntax of each instruction Operand2 can be a constant or a register with optional shift September 07 2010 15 Texas Instruments Incorporated Introduction 1 2 3 1 1 2 3 2 16 Constant You specify an Operand2 constant in the form constant where constant can be X and Y are hexadecimal digits m Any constant that can be produced by shifting an 8 bit value left by any number of bits within a 32 bit word m Any constant of the form 0x00XY00XY m Any constant of the form 0xXY00XY00 m Any constant of the form OxXYXYXYXY In addition in a small number of instructions constant can take a wider range of values These are described in the individual instruction descriptions When an Operana2 constant is used with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to bit 31 of the constant if the constant is greater than 255 and can be produced by shifting an 8 bit value These instructions do not affect the carry flag if Operana2
43. e TT instruction to reduce the number of branch instructions in code Table 1 2 on page 22 also shows the relationship between condition code suffixes and the N Z C and v flags September 07 2010 21 Texas Instruments Incorporated Introduction 1 2 8 22 Table 1 2 Condition Code Suffixes Suffix Flags Meaning EQ Z Equal NE 0 Not equal CS or HS c 1 Higher or same unsigned gt CC or LO c 0 Lower unsigned lt MI N Negative PL N 0 Positive or zero vs v Overflow VC v 0 No overflow HI c 1andz 0 Higher unsigned gt LS C 0orz 1 Lower or same unsigned lt GE N V Greater than or equal signed gt LT NIFV Less than signed lt GT Z 0andN v Greater than signed gt LE Z 1andN l v Less than or equal signed lt AL Can have any value Always This is the default when no suffix is specified Example 1 1 Absolute Value on page 22 shows the use of a conditional instruction to find the absolute value of a number RO ABS R1 Example 1 1 Absolute Value MOVS RO R1 RO R1 setting flags IT MI IT instruction for the negative condition RSBMI RO Rly 0 If negative RO R1 Example 1 2 Compare and Update Value on page 22 shows the use of conditional instructions to update the value of R4 if the signed value RO is greater than R1 and R2 is greater than R3 Example 1 2 Compare and Update Value CMP RO R1 Compare RO
44. e calculation word aligned Ifyou want to generate the address of an instruction you have to adjust the constant based on the value of the PC ARM recommends that you use the ADR instruction instead of ADD or SUB with Rn equal to the PC because your assembler automatically calculates the correct constant for the ADR instruction When Rd is PC in the ADD cond PC PC Rm instruction m Bit 0 of the value written to the PC is ignored m A branch occurs to the address created by forcing bit 0 of that value to 0 Condition Flags If Sis specified these instructions update the N Zz C and v flags according to the result September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 3 1 5 Examples ADD R2 R1 R3 SUBS R8 R6 240 Sets the flags on the result RSB R4 R4 1280 Subtracts contents of R4 from 1280 ADCHI R11 RO R3 Only executed if C flag set and Z flag clear 3 1 6 Multiword Arithmetic Examples Example 3 1 64 Bit Addition on page 45 shows two instructions that add a 64 bit integer contained in R2 and R3 to another 64 bit integer contained in RO and R1 and place the result in R4 and R5 Example 3 1 64 Bit Addition ADDS R4 RO R2 Add the least significant words ADC R5 Rl R3 Add the most significant words with carry Multiword values do not have to use consecutive registers Example 3 2 96 Bit Subtraction on page 45 shows instructions that
45. e flags 3 8 5 Examples REV R3 R7 Reverse byte order of value in R7 and write it to R3 REV16 RO RO Reverse byte order of each 16 bit halfword in RO REVSH RO R5 Reverse Signed Halfword REVHS R3 R7 Reverse with Higher or Same condition RBIT R7 R8 Reverse bit order of value in R8 and write the result to R7 56 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 3 9 TST and TEQ Test bits and Test Equivalence 3 9 1 Syntax TST cond Rn Operand2 EQ cond Rn Operand2 where cond Is an optional condition code See Table 1 2 on page 22 Rn Is the register holding the first operand Operand2 Is a flexible second operand See Flexible Second Operand on page 15 for details of the options 3 9 2 Operation These instructions test the value in a register against Ope rand2 They update the condition flags based on the result but do not write the result to a register The TST instruction performs a bitwise AND operation on the value in Rn and the value of Operand2 This is the same as the ANDS instruction except that it discards the result To test whether a bit of Rn is O or 1 use the TST instruction with an Operand2 constant that has that bit set to 1 and all other bits cleared to 0 The TEQ instruction performs a bitwise Exclusive OR operation on the value in Rn and the value of Operand2 This is the same as the EORS instruction except that it discards the result
46. e of Operand2 The ORN instruction performs an OR operation on the bits in Rn with the complements of the corresponding bits in the value of Operand2 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 3 2 3 Restrictions Do not use SP and do not use PC 3 2 4 Condition Flags If s is specified these instructions m Update the N and z flags according to the result m Can update the c flag during the calculation of Operana2 See Flexible Second Operand on page 15 Do not affect the v flag 3 2 5 Examples AND R9 R2 OxFFOO ORREQ R2 RO R5 ANDS R9 R8 0x19 EORS R7 R11 0x18181818 BIC RO BI Oxab ORN R7 R11 R14 ROR 4 ORNS R7 R11 R14 ASR 32 September 07 2010 47 Texas Instruments Incorporated General Data Processing Instructions 3 3 3 3 1 48 ASR LSL LSR ROR and RRX Arithmetic Shift Right Logical Shift Left Logical Shift Right Rotate Right and Rotate Right with Extend Syntax op S cond Rd Rm Rs op S cond Rd Rm n RRX S cond Rd Rm where Op Is one of ASR Arithmetic Shift Right LSL Logical Shift Left LSR Logical Shift Right ROR Rotate Right Is an optional suffix If S is specified the condition code flags are updated on the result of the operation See Conditional Execution on page 20 Rd Is the destination register Is the
47. ee Figure 1 3 on page 19 You can use the LSL n operation to multiply the value in the register Rm by 2 if the value is regarded as an unsigned integer or a two s complement signed integer Overflow can occur without warning When the instruction is LSLS or when LSL n with non zero n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to the last bit shifted out bit 32 0n of the register Rm These instructions do not affect the carry flag when used with LSL 0 Note am If nis 32 or more then all the bits in the result are cleared to 0 m f nis 33 or more and the carry flag is updated it is updated to 0 18 September 07 2010 Texas Instruments Incorporated 1 2 4 4 1 2 4 5 Cortex M3 Instruction Set Figure 1 3 LSL 3 ROR A rotate right ROR by n bits moves the left hand 320 n bits of the register Rm to the right by n places into the right hand 320 n bits of the result And it moves the right hand n bits of the register into the left hand n bits of the result See Figure 1 4 on page 19 When the instruction is RORS or when ROR n is used in Operand2 with the instructions MOVS MVNS ANDS ORRS ORNS EORS BICS TEQ or TST the carry flag is updated to the last bit rotation bit n 1 of the register Rm Note m If nis 32 then the value of the result is the same as the value in Rm
48. eet Some instructions update all flags and some only update a subset If a flag is not updated the original value is preserved See the instruction descriptions for the flags they affect You can execute an instruction conditionally based on the condition flags set in another instruction either immediately after the instruction that updated the flags or after any number of intervening instructions that have not updated the flags Conditional execution is available by using conditional branches or by adding condition code suffixes to instructions See Table 1 2 on page 22 for a list of the suffixes to add to instructions to make them conditional instructions The condition code suffix enables the processor to test a condition based on the flags If the condition test of a conditional instruction fails the instruction September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Does not execute Does not write any value to its destination register Does not affect any of the flags m Does not generate any exception Conditional instructions except for conditional branches must be inside an If Then instruction block See IT on page 77 for more information and restrictions when using the IT instruction Depending on the vendor the assembler might automatically insert an IT instruction if you have conditional instructions outside the IT block See IT on page 77 for more on the IT block Use the CBZ and C
49. egister it is guaranteed that no other process in the system has accessed the memory location between the Load exclusive and Store Exclusive instructions For reasons of performance keep the number of instructions between corresponding Load Exclusive and Store Exclusive instruction to a minimum September 07 2010 39 Texas Instruments Incorporated Memory Access Instructions 2 8 3 2 8 4 2 8 5 40 Important The result of executing a Store Exclusive instruction to an address that is different from that used in the preceding Load Exclusive instruction is unpredictable Restrictions In these instructions Donotuse PC Donotuse SP for Rdand Rt m For STRI EX Rd must be different from both Rt and Rn m The value of offset must be a multiple of four in the range 0 1020 Condition Flags These instructions do not change the flags Examples MOV R1 try LDREX RO CMP RO ETT EQ STREXEQ RO CMPEQ RO BNE try 0x1 LockAddr 0 R1 LockAddr 0 Initialize the lock taken value Load the lock value Is the lock free IT instruction for STREXEQ and CMPEQ Try and claim the lock Did this succeed No try again Yes we have the lock September 07 2010 Texas Instruments Incorporated 2 9 2 9 1 2 9 2 2 9 3 2 9 4 Cortex M3 Instruction Set CLREX Clear Exclusive Syntax CLREX cond where
50. ember 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 7 Branch and Control Instructions Table 7 1 on page 73 shows the branch and control instructions Table 7 1 Branch and Control Instructions Mnemonic Brief Description See Page B Branch 74 BL Branch with link 74 BLX Branch indirect with link 74 BX Branch indirect 74 CBNZ Compare and branch if non zero 76 CBZ Compare and branch if zero 76 IT f Then 77 TBB Table branch byte 80 TBH Table branch halfword 80 September 07 2010 73 Texas Instruments Incorporated Branch and Control Instructions 7 1 74 B BL BX and BLX Branch instructions Syntax B cond label BL cond label BX cond Rm BLX cond Rm where B Is branch immediate BL Is branch with link immediate BX Is branch indirect register BLX Is branch indirect with link register cond Is an optional condition code See Table 1 2 on page 22 label Is a PC relative expression See PC Relative Expressions on page 20 Rm Is a register that indicates an address to branch to Bit 0 of the value in Rm must be 1 but the address to branch to is created by changing bit 0 to 0 Operation All these instructions cause a branch to 1abe1 or to the address indicated in Rm In addition m The BL and BLX instructions write the address of the next instruction to the Link Register LR register R14 See the Stellaris Data Sheet for mo
51. er the operands are signed or unsigned Restrictions In these instructions do not use SP and do not use PC If you use the S suffix with the MUL instruction m Rd Rn and Rm must all be in the range RO to R7 Rdmust be the same as Rm m You must not use the cond suffix September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 4 1 4 Condition Flags If sis specified the MUL instruction m Updates the N and z flags according to the result Does not affect the c and v flags 4 1 5 Examples MUL R10 R2 R5 Multiply R10 R2 x R5 MLA R10 R2 R1 R5 Multiply with accumulate R10 R2 x R1 R5 MULS RO R2 R2 Multiply with flag update RO R2 x R2 MULLT R2 R3 R2 Conditionally multiply R2 R3 x R2 MLS R4 R5 R6 R7 Multiply with subtract R4 R7 R5 x R6 September 07 2010 61 Texas Instruments Incorporated Multiply and Divide Instructions 4 2 4 2 1 4 2 2 4 2 3 62 UMULL UMLAL SMULL and SMLAL Signed and Unsigned Long Multiply with optional Accumulate using 32 bit operands and producing a 64 bit result Syntax op cond RdLo RdHi Rn Rm where op IS one of UMULL Unsigned Long Multiply UMLAL Unsigned Long Multiply with Accumulate SMULL Signed Long Multiply SMLAL Signed Long Multiply with Accumulate cond Is an optional condition code See Table 1 2 on page 22 RdHi RdLo Are the de
52. he Svc instruction causes the Svc exception immis ignored by the processor If required it can be retrieved by the exception handler to determine what service is being requested Condition Flags This instruction does not change the flags Examples SVC 0x32 Supervisor Call SVC handler can extract the immediate valu by locating it via the stacked PC September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 8 11 WFE Wait For Event 8 111 Syntax WFE cond where cond Is an optional condition code See Table 1 2 on page 22 8 11 2 Operation WFE is a hint instruction If the one bit event register is O WFE suspends execution until one of the following events occurs m An exception unless masked by the exception mask registers PRIMASK FAULTMASK and BASEPRI or the current priority level m An exception enters the Pending state if SEVONPEND in the System Control Register SCR is set m A Debug Entry request if Debug is enabled m An event signaled by a peripheral or another processor in a multiprocessor system using the SEV instruction If the event register is 1 WFE clears it to O and returns immediately For more information see Power Management in the Stellaris Data Sheet 8 113 Condition Flags This instruction does not change the flags 8 11 4 Examples WFE Wait for Event September 07 2010 93 Texas Instruments Inco
53. hese instructions have only unprivileged access even when used in privileged software September 07 2010 31 Texas Instruments Incorporated Memory Access Instructions 2 4 3 2 4 4 2 4 5 32 When used in unprivileged software these instructions behave in exactly the same way as normal memory access instructions with immediate offset Restrictions In these instructions m Rn must not be PC m Rt must not be SP and must not be PC Condition Flags These instructions do not change the flags Examples STRBTEQ R4 R7 Conditionally store least significant byte in R4 to an address in R7 with unprivileged access LDRHT R2 R2 8 Load halfword value from an address equal to sum of R2 and 8 into R2 Texas Instruments Incorporated with unprivileged access September 07 2010 2 5 2 5 1 2 5 2 Cortex M3 Instruction Set LDR PC Relative Load register from memory Syntax LDR type cond Rt label LDRD cond Rt Rt2 label Load two words where type Is one of B Unsigned byte zero extend to 32 bits SB Signed byte sign extend to 32 bits H Unsigned halfword zero extend to 32 bits SH Signed halfword sign extend to 32 bits Omit for word cond Is an optional condition code See Table 1 2 on page 22 Rt Is the register to load or store Rt2 Is the second register to load or store label Is a PC relative expression See PC Relative Expres
54. ils Restrictions In these instructions Rn must not be PC m reglist must not contain SP m Inany STM instruction reglist must not contain PC m Inany LDM instruction reg1ist must not contain PC if it contains LR m reglist must not contain Rn if you specify the writeback suffix When PC is in reglist in an LDM instruction m Bit 0 of the value loaded to the PC must be 1 for correct execution and a branch occurs to this halfword aligned address m Ifthe instruction is conditional it must be the last instruction in the IT block Condition Flags These instructions do not change the flags Examples LDM R8 RO R2 R9 LDMIA is a synonym for LDM STMDB R1 R3 R6 R11 R12 Incorrect Examples STM R5 R5 R4 R9 Value stored for R5 is unpredictable LDM R2 There must be at least one register in the list September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 2 7 PUSH and POP Push registers on and pop registers off a full descending stack 2 7 1 Syntax PUSH cond reglist POP cond reglist where cond Is an optional condition code See Table 1 2 on page 22 reglist Is a non empty list of registers enclosed in braces It can contain register ranges It must be comma separated if it contains more than one register or register range PUSH and POP are synonyms for STMDB and LDM or LDMIA with the memory addresses for the access based on SP and with the final address for the access writ
55. is any other constant Your assembler might be able to produce an equivalent instruction in cases where you specify a constant that is not permitted For example an assembler might assemble the instruction CMP Ra OxFFFFFFFE as the equivalent instruction CMN Rd 0x2 Register With Optional Shift You specify an Operand2 register in the form Rm shift where Rm Is the register holding the data for the second operand shift Is an optional shift to be applied to Rm It can be one of ASR n Arithmetic shift right n bits 1 lt n lt 32 LSL n Logical shift left n bits 1 lt n lt 31 LSR n Logical shift right n bits 1 lt n lt 32 ROR n Rotate right n bits 1 lt n lt 31 RRX Rotate right one bit with extend September 07 2010 Texas Instruments Incorporated 1 2 4 1 2 4 1 Cortex M3 Instruction Set If omitted no shift occurs equivalent to LSL 0 If you omit the shift or specify LSL 0 the instruction uses the value in Rm If you specify a shift the shift is applied to the value in Rm and the resulting 32 bit value is used by the instruction However the contents in the register Rm remain unchanged Specifying a register with shift also updates the carry flag when used with certain instructions For information on the shift operations and how they affect the carry flag see Shift Operations on page 17 Shift Operations Register shift operations move the bits in a regis
56. it field insert 69 SBFX Signed bit field extract 70 SXTB Sign extend a byte 71 SXTH Sign extend a halfword 71 UBFX Unsigned bit field extract 70 UXTB Zero extend a byte 71 UXTH Zero extend a halfword 71 Texas Instruments Incorporated September 07 2010 Cortex M3 Instruction Set 6 1 BFC and BFI Bit Field Clear and Bit Field Insert 6 1 1 Syntax BFC cond Rd 1sb width BFI cond Rd Rn lsb width where cond IS an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rn Is the source register 1sb Is the position of the least significant bit of the bitfield 1sb must be in the range 0 to 31 width Is the width of the bitfield and must be in the range 1 to 320 1 sb 6 1 2 Operation BFC clears a bitfield in a register It clears width bits in Ra starting at the low bit position 1 sb Other bits in Rd are unchanged BFI copies a bitfield into one register from another register It replaces width bits in Rd starting at the low bit position 1sb with width bits from Rn starting at bit 0 Other bits in Rd are unchanged 6 1 3 Restrictions Do not use SP and do not use PC 6 1 4 Condition Flags These instructions do not affect the flags 6 1 5 Examples BFC R4 8 12 Clear bit 8 Je bit 19 412 bits ot RA ECO BFI R9 R2 8 12 Replace bit 8 to bit 19 12 bits of R9 with bit 0 to bit 11 from R2 September 07 2010 69 Texas Instruments Incorpo
57. it instruction even though the same Operation can be done by a 16 bit instruction September 07 2010 23 Texas Instruments Incorporated Memory Access Instructions 24 Memory Access Instructions Table 2 1 on page 24 shows the memory access instructions Table 2 1 Memory Access Instructions Mnemonic Brief Description See Page ADR Load PC relative address 25 CLREX Clear exclusive 41 LDM mode Load multiple registers 35 LDR type Load register using immediate offset 26 LDR type Load register using register offset 29 LDR type T Load register with unprivileged access 31 LDR type Load register using PC relative address 33 LDRD Load register using PC relative address two words 33 LDREX type Load register exclusive 39 POP Pop registers from stack 37 PUSH Push registers onto stack 37 STM mode Store multiple registers 35 STR type Store register using immediate offset 26 STR type Store register using register offset 35 STR type T Store register with unprivileged access 31 STREX type Store register exclusive 39 Texas Instruments Incorporated September 07 2010 Cortex M3 Instruction Set 2 1 ADR Load PC relative address 2 1 1 Syntax ADR cond Rd label where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register label Is a PC relative expression See PC Relative Expressions on page 20 2 1 2 Operation ADR
58. ith extend Reverse subtract Subtract with carry Subtract Subtract TEQ Test equivalence 57 TST Test 57 42 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set 3 1 ADD ADC SUB SBC and RSB Add Add with carry Subtract Subtract with carry and Reverse Subtract 3 1 1 Syntax op S cond Rd Rn Operand2 op cond Rd Rn imm12 ADD and SUB only where Op Is one of ADD Add ADC Add with Carry SUB Subtract SBC Subtract with Carry RSB Reverse Subtract Is an optional suffix If S is specified the condition code flags are updated on the result of the operation See Conditional Execution on page 20 cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register If Rd is omitted the destination register is Rn Rn Is the register holding the first operand Operand2 Is a flexible second operand See Flexible Second Operand on page 15 for details of the options imm12 Is any value in the range 0 4095 3 1 2 Operation The ADD instruction adds the value of Operand2 or imm12 to the value in Rn The ADC instruction adds the values in Rn and Operand2 together with the carry flag September 07 2010 43 Texas Instruments Incorporated General Data Processing Instructions 3 1 4 44 The SUB instruction subtracts the value of Operand2 or imm12 from the value in Rn The SBC i
59. itten back into the register Rn The assembly language syntax for this mode is Rn offset Post indexed addressing The address obtained from the register Rn is used as the address for the memory access The offset value is added to or subtracted from the address and written back into the register Rn The assembly language syntax for this mode is Rn offset The value to load or store can be a byte halfword word or two words Bytes and halfwords can either be signed or unsigned See Address Alignment on page 20 Table 2 2 on page 27 shows the ranges of offset for immediate pre indexed and post indexed forms Table 2 2 Offset Ranges Word halfword signed halfword 255 to 4095 255 to 255 255 to 255 byte or signed byte Two words Multiple of 4 in the range Multiple of 4 in the range Multiple of 4 in the range 1020 to 1020 1020 to 1020 1020 to 1020 2 2 3 Restrictions For load instructions m Rt can be SP or PC for word loads only September 07 2010 27 Texas Instruments Incorporated Memory Access Instructions m Rt must be different from Rt2 for two word loads m Rn must be different from Rt and Rt2 in the pre indexed or post indexed forms When Rt is PC in a word load instruction m Bit 0 of the loaded value must be 1 for correct execution m A branch occurs to the address created by changing bit 0 of the loaded value to 0 m Ifthe instruction is conditional it must be the last instruction in the IT block
60. lly slower than aligned accesses In addition some memory regions might not support unaligned accesses Therefore ARM recommends that programmers ensure that accesses are aligned To avoid accidental generation of unaligned accesses use the UNALIGNED bit in the Configuration and Control CFGCTRL register to trap all unaligned accesses see CFGCTRL in the Stellaris Data Sheet PC Relative Expressions A PC relative expression or label is a symbol that represents the address of an instruction or literal data It is represented in the instruction as the PC value plus or minus a numeric offset The assembler calculates the required offset from the label and the address of the current instruction If the offset is too big the assembler produces an error Note m Forp BL CBNZ and CBZ instructions the value of the PC is the address of the current instruction plus 4 bytes m Forall other instructions that use labels the value of the PC is the address of the current instruction plus 4 bytes with bit 1 of the result cleared to 0 to make it word aligned m Your assembler might permit other syntaxes for PC relative expressions such as a label plus or minus a number or an expression of the form PC number Conditional Execution Most data processing instructions can optionally update the condition flags in the Application Program Status Register APSR register according to the result of the operation see APSR in the Stellaris Data Sh
61. ltiply and Divide Instructions sisaria randina and aaa A AAA R 59 SZ MCL 65 Bitfeld InStr ctions ergeet rege fn de sree ee fn ee 68 Branch and Control Instructions 2 000 220 ccceeeeceeeeeeeeeeeeeee eee eter ee aaeeeeeeaaeeeeeeaaeeeeeeaaeeees 73 Branch Ranges sister A reese ened ant 75 Miscellaneous Instructions eri aain Ennai E ERE EEEE 82 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set List of Examples Example 1 1 Absolute Value sise 22 Example 1 2 Compare and Update Value 0ccccccceeeeeeeeeeeee cece ae eeeeeeeeeceeeeeaeeesaeeeeaeeeeseeeeaaes 22 Example 1 3 Instruction Width Selection cccccceeceeeeeee eee ceeeee ee eeeeeeeesaeeeeeaeesaeeesaeeeeseeesaaees 23 Example 3 1 G4 Bit Addition nt sets tante nn dti es te a a a a dt ns uns 45 E ie e e e RE A5 September 07 2010 11 Texas Instruments Incorporated Introduction 1 1 Introduction Each of the following chapters describes a functional group of Cortex M3 instructions Together they describe all the instructions supported by the Cortex M3 processor Memory Access Instructions on page 24 General Data Processing Instructions on page 42 Multiply and Divide Instructions on page 59 Saturating Instructions on page 65 Bitfield Instructions on page 68 Branch and Control Instructions on page 73 Miscellaneous Instructions on page 82 Instruction Set Summary The processo
62. n bit saturation using USAT this means that m Ifthe value to be saturated is less than 0 the result returned is 0 m Ifthe value to be saturated is greater than 2 1 the result returned is 2 1 m Otherwise the result returned is the same as the value to be saturated If the returned result is different from the value to be saturated it is called saturation If saturation occurs the instruction sets the flag to 1 in the APSR Otherwise it leaves the flag unchanged To clear the Q flag to 0 you must use the MSR instruction See MSR on page 89 To read the state of the o flag use the MRS instruction See MRS on page 88 5 1 3 Restrictions Do not use SP and do not use PC 5 1 4 Condition Flags These instructions do not affect the condition code flags If saturation occurs these instructions set the Q flag to 1 5 1 5 Examples SSAT R7 16 R7 LSL 4 Logical shift left value in R7 by 4 then Saturate it as a signed 16 bit value and write it back to R7 USATNE RO 7 R5 Conditionally saturate value in R5 as an unsigned 7 bit value and write it to RO September 07 2010 67 Texas Instruments Incorporated Bitfield Instructions 68 Bitfield Instructions Table 6 1 on page 68 shows the instructions that operate on adjacent sets of bits in registers or bitfields Table 6 1 Bitfield Instructions Mnemonic Brief Description See Page BFC Bit field clear 69 BFI B
63. nstruction subtracts the value of Operand2 from the value in Rn If the carry flag is clear the result is reduced by one The RSB instruction subtracts the value in Rn from the value of Operana2 This is useful because of the wide range of options for Operand2 Use ADC and SBC to synthesize multiword arithmetic See Multiword Arithmetic Examples on page 45 See also 25 Note ADDW is equivalent to the ADD syntax that uses the imm12 operand SUBW is equivalent to the SUB syntax that uses the imm12 operand Restrictions In these instructions m Operand2 must not be SP and must not be PC m Rd can be SP only in ADD and SUB and only with the additional restrictions Rnmustalso be SP any shift in Operand2 must be limited to a maximum of 3 bits using LSL m Rn can be SP only in ADD and SUB m Rdcan be PC only inthe ADD cond PC PC Rminstruction where You must not specify the S suffix Rm must not be PC and must not be SP Ifthe instruction is conditional it must be the last instruction in the IT block m With the exception ofthe ADD cond PC PC Rminstruction Rn can be PC only in ADD and SUB and only with the additional restrictions You must not specify the S suffix The second operand must be a constant in the range 0 to 4095 Note When using the PC for an addition or a subtraction bits 1 0 of the PC are rounded to b00 before performing the calculation making the base address for th
64. ost indexed two words where OP IS one of LDR Load Register STR Store Register type Is one of B Unsigned byte zero extend to 32 bits on loads SB Signed byte sign extend to 32 bits LDR only H Unsigned halfword zero extend to 32 bits on loads SH Signed halfword sign extend to 32 bits LDR only Omit for word cond Is an optional condition code See Table 1 2 on page 22 Rt Is the register to load or store 26 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Rn Is the register on which the memory address is based offset Is an offset from Rn If offset is omitted the address is the contents of Rn Rt2 Is the additional register to load or store for two word operations 2 2 2 Operation LDR instructions load one or two registers with a value from memory STR instructions store one or two register values to memory Load and store instructions with immediate offset can use the following addressing modes Offset addressing The offset value is added to or subtracted from the address obtained from the register Rn The result is used as the address for the memory access The register Rn is unaltered The assembly language syntax for this mode is Rn offset Pre indexed addressing The offset value is added to or subtracted from the address obtained from the register Rn The result is used as the address for the memory access and wr
65. p 54 MRS Rd spec_reg Move from special register to general 88 register MSR spec_reg Rn Move from general register to special N Z C V 89 register MUL MULS Rd Rn Rm Multiply 32 bit result N Z 60 MVN MVNS Rd Op2 Move NOT N Z C 52 NOP No operation 90 ORN ORNS Rd Rn Op2 Logical OR NOT N Z C 43 September07 2010 S 13 Texas Instruments Incorporated Introduction Table 1 1 Cortex M3 Instructions continued Mnemonic Operands Brief Description Flags See Page ORR ORRS Rd Rn Op2 Logical OR N Z C 43 POP reglist Pop registers from stack 37 Push registers onto stack Reverse bits Reverse byte order in a word Reverse byte order in each halfword Reverse byte order in bottom halfword and sign extend Rm lt Rs n gt Rotate right Rd Rm Rotate right with extend Rd Rn Rd Rn Op2 Op2 Reverse subtract Subtract with carry Rd Rn lsb width Signed bit field extract Rd Rn Rm Signed divide Send event RdLo RdHi Rn Rm Signed multiply with accumulate 32x32 64 64 bit result RdLo RdHi Rn Rm Signed multiply 32x32 64 bit result Rd n Rm shift s Signed saturate STMDB STMEA STMFD STMIA 1 reglist 1 reglist Store multiple registers increment after Store multiple registers decrement before Store multiple registers increment after STR Rn off
66. r applications assistance or customer product design Customers are responsible for their products and applications using TI components To minimize the risks associated with customer products and applications customers should provide adequate design and operating safeguards TI does not warrant or represent that any license either express or implied is granted under any TI patent right copyright mask work right or other TI intellectual property right relating to any combination machine or process in which TI products or services are used Information published by TI regarding third party products or services does not constitute a license from TI to use such products or services or a warranty or endorsement thereof Use of such information may require a license from a third party under the patents or other intellectual property of the third party or a license from TI under the patents or other intellectual property of TI Reproduction of TI information in TI data books or data sheets is permissible only if reproduction is without alteration and is accompanied by all associated warranties conditions limitations and notices Reproduction of this information with alteration is an unfair and deceptive business practice TI is not responsible or liable for such altered documentation Information of third parties may be subject to additional restrictions Resale of TI products or services with statements different from or beyond the parameters stated b
67. r implements a version of the Thumb instruction set Table 1 1 on page 12 lists the supported instructions In Table 1 1 on page 12 m Angle brackets lt gt enclose alternative forms of the operand m Braces enclose optional operands m The Operands column is not exhaustive m Op2 is a flexible second operand that can be either a register or a constant Most instructions can use an optional condition code suffix For more information on the instructions and operands see the instruction descriptions Table 1 1 Cortex M3 Instructions Mnemonic Operands Brief Description Flags See Page ADC ADCS Rd Rn Op2 Add with carry N Z C V 43 ADD ADDS Rd Rn Op2 Add N Z C V 43 ADD ADDW Rd Rn imml2 Add N Z C V 43 ADR Rd label Load PC relative address 25 AND ANDS Rd Rn Op2 Logical AND N Z C 46 ASR ASRS Rd Rm lt Rs n gt Arithmetic shift right N Z C 48 B label Branch 74 BFC Rd lsb width Bit field clear 69 BFI Rd Rn lsb width Bit field insert 69 BIC BTCS Rd Rn Op2 Bit clear N Z C 43 BKPT imm Breakpoint 83 BL label Branch with link 74 BLX Rm Branch indirect with link 74 BX Rm Branch indirect 74 CBNZ Rn label Compare and branch if non zero 76 12 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Table 1 1 Cortex M3 Instructions continued Mnemonic Operands Brief Description Flag
68. rated Bitfield Instructions 6 2 6 2 1 6 2 2 6 2 3 6 2 4 6 2 5 70 SBFX and UBFX Signed Bit Field Extract and Unsigned Bit Field Extract Syntax SBFX cond Rd Rn 1sb width UBFX cond Rd Rn lsb width where cond Is an optional condition code See Table 1 2 on page 22 Rd Is the destination register Rn Is the source register 1sb Is the position of the least significant bit of the bitfield 1sb must be in the range 0 to 31 width Is the width of the bitfield and must be in the range 1 to 320 1 sb Operation SBFX extracts a bitfield from one register sign extends it to 32 bits and writes the result to the destination register UBFX extracts a bitfield from one register zero extends it to 32 bits and writes the result to the destination register Restrictions Do not use SP and do not use PC Condition Flags These instructions do not affect the flags Examples SBFX RO R1 20 4 Extract bit 20 to bit 23 4 bits from R1 and sign extend to 32 bits and then write the result to RO UBFX R8 R11 9 10 Extract bit 9 to bit 18 10 bits from R11 and zero extend to 32 bits and then write the result to R8 September 07 2010 Texas Instruments Incorporated 6 3 6 3 1 6 3 2 Cortex M3 Instruction Set SXT and UXT Sign extend and Zero extend Syntax SXTextend cond Rd Rm ROR n
69. re on LR m The BX and BLX instructions cause a UsageFault exception if bit 0 of Rmis 0 B cond label is the only conditional instruction that can be either inside or outside an IT block All other branch instructions must be conditional inside an IT block and must be unconditional outside the IT block See IT on page 77 Table 7 2 on page 75 shows the ranges for the various branch instructions September 07 2010 Texas Instruments Incorporated Table 7 2 Branch Ranges Cortex M3 Instruction Set Instruction Branch Range B label 16 MB to 16 MB Bcond label outside IT block 1 MB to 1 MB Bcond label inside IT block 16 MB to 16 MB BL cond label 16 MB to 16 MB BX cond Rm Any value in register BLX cond Rm Any value in register a You might have to use the w suffix to get the maximum branch range See Instruction Width Selection on page 22 7 1 3 Restrictions The restrictions are Donotuse PC in the BLX instruction m For BX and BLX bit 0 of Rm must be 1 for correct execution but a branch occurs to the target address created by changing bit 0 to 0 m When any of these instructions is inside an IT block it must be the last instruction of the IT block Note B condis the only conditional instruction that is not required to be inside an IT block However it has a longer branch range when it is inside an IT block 7 1 4 Condition
70. register holding the value to be shifted Is the register holding the shift length to apply to the value in Rm Only the least significant byte is used and can be in the range 0 to 255 Is the shift length The range of shift length depends on the instruction ASR Shift length from 1 to 32 LSL Shift length from 0 to 31 LSR Shift length from 1 to 32 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set ROR Shift length from 1 to 31 Note MOV S cond Rd Rmisthe preferred syntax for LSL S cond Rd Rm 0 3 3 2 Operation ASR LSL LSR and ROR move the bits in the register Rm to the left or right by the number of places specified by constant n or register Rs RRX moves the bits in register Rm to the right by 1 In all these instructions the result is written to Rd but the value in register Rm remains unchanged For details on what result is generated by the different instructions see Shift Operations on page 17 3 3 3 Restrictions Do not use SP and do not use PC 3 3 4 Condition Flags If Sis specified m These instructions update the N and z flags according to the result m The flag is updated to the last bit shifted out except when the shift length is O See Shift Operations on page 17 3 3 5 Examples ASR R7 R87 9 Arithmetic shift right by 9 bits LSLS R1 R2 3 Logical shift left by 3 bits with flag update LSR R4 R5
71. rporated Miscellaneous Instructions 8 12 WEI Wait for Interrupt 8 12 1 Syntax WFI cond where cond Is an optional condition code See Table 1 2 on page 22 8 12 2 Operation WF I is a hint instruction that suspends execution until one of the following events occurs m An exception m Debug Entry request regardless of whether Debug is enabled 8 123 Condition Flags This instruction does not change the flags 8 124 Examples WEI Wait for Interrupt 94 September 07 2010 Texas Instruments Incorporated IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries Tl reserve the right to make corrections modifications enhancements improvements and other changes to its products and services at any time and to discontinue any product or service without notice Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete All products are sold subject to Tl s terms and conditions of sale supplied at the time of order acknowledgment TI warrants performance of its hardware products to the specifications applicable at the time of sale in accordance with Tl s standard warranty Testing and other quality control techniques are used to the extent TI deems necessary to support this warranty Except where mandated by government requirements testing of all parameters of each product is not necessarily performed TI assumes no liability fo
72. ructions do not change the flags Examples STR RO R5 R1 Store value of RO into an address equal to sum of R5 and RI LDRSB RO R5 R1 LSL 1 Read byte value from an address equal to sum of R5 and two times R1 sign extend it to a word value and put it in RO STR RO R1 R2 LSL 2 Store RO to an address equal to sum of R1 and four times R2 September 07 2010 Texas Instruments Incorporated 2 4 2 4 1 2 4 2 Cortex M3 Instruction Set LDR and STR Unprivileged Access Load and Store with unprivileged access Syntax op type T cond Rt Rn offset immediate offset where Op Is one of LDR Load Register STR Store Register type Is one of B Unsigned byte zero extend to 32 bits on loads SB Signed byte sign extend to 32 bits LDR only H Unsigned halfword zero extend to 32 bits on loads SH Signed halfword sign extend to 32 bits LDR only Omit for word cond Is an optional condition code See Table 1 2 on page 22 Rt Is the register to load or store Rn Is the register on which the memory address is based offset Is an offset from Rn and can be 0 to 255 If offset is omitted the address is the value in Rn Operation These load and store instructions perform the same function as the memory access instructions with immediate offset see LDR and STR Immediate Offset on page 26 The difference is that t
73. s See Page CBZ Rn label Compare and branch if zero 76 CLREX Clear exclusive 41 Count leading zeros Compare negative Compare Change processor state disable interrupts Change processor state enable interrupts Data memory barrier Data synchronization barrier Rd Rn Op2 Exclusive OR Instruction synchronization barrier If Then condition block Rn reglist Load multiple registers increment after DMDB LDMEA Rn reglist Load multiple registers decrement before DMFD LDMIA Rn reglist Load multiple registers increment after DR Rn offset Load register with word DRB LDRBT Rn offset Load register with byte DRD Rn offset Load register with two words DREX Rn offset Load register exclusive DREXB Rn Load register exclusive with byte DREXH Rn Load register exclusive with halfword DRH LDRHT Rn offset Load register with halfword DRSB LDRSBT Rn offset Load register with signed byte DRSH LDRSHT Rn offset Load register with signed halfword Rn offset Load register with word Rm lt Rs n gt Logical shift left Rm Logical shift right MLA Rd Rn Rm Ra Multiply with accumulate 32 bit result 60 MLS Rd Rn Rm Ra Multiply and subtract 32 bit result 60 MOV MOVS Rd Op2 Move N Z C 52 MOV MOVW Rd imml6 Move 16 bit constant N Z C 52 MOVT Rd imm16 Move to
74. sal a aA EN EAA DEES PC Relative Expressions eieren nd aa aa ENEE NEE EN Conditional Execution leioar eee ea lb el ee Instruction Width Selection ss Memory Access Instructions sis REH NS Op ration sas ee a A ee ee ea Pee ea Ces ces Sep nt a eae ea Kee Condition Flags EE East Eege A A a EE a e dida LDR and STR Immediate Offset LTE OL TELLE RE EE RESIIGUONS EE Condition FIAGS EE LD Lu 0 PR TR airada inalterada LDR and STR Register Offset oae taa EEn ir o des AO A A PE ae EE ds ene IEN EE Condition Flag Sariaren ATARA dd di Examples ica aa MT et eege LDR and STR Unprivileged Access SM o a at aa Op ration sise sense E ant Ra fan Ans dan ts ELE Condition Le ET Examples eege aaa LDR ee E E ET A done ads dede ra T deed EE Operation EE RESTICUONS EE Condition Flags EE Examples oogarts degen deen dE enden DM and TM aa ad DIM ias Operation era iia tada September 07 2010 Texas Instruments Incorporated Table of Contents 2 6 3 2 6 4 2 6 5 2 6 6 2 7 2 7 1 2 7 2 2 7 3 2 7 4 2 7 5 2 8 2 8 1 2 8 2 2 8 3 2 8 4 2 8 5 2 9 2 9 1 2 9 2 2 9 3 2 9 4 3 1 3 1 1 3 1 2 3 1 3 3 1 4 3 1 5 3 1 6 3 2 3 2 1 3 2 2 3 2 3 3 2 4 3 2 5 3 3 3 3 1 3 3 2 3 3 3 3 3 4 3 3 5 3 4 3 4 1 3 4 2 3 4 3 3 4 4 3 4 5 3 5 Bee 36 Condition FlagS EE 36 Examples israel os 36 leegen 36 PUSH and POP fish ccs echo A A A 37 SVIMAK ee cb eat ee dene ce eae
75. set Store register word STRB STRBT Rn offset Store register byte STRD Rt2 Rn offset Store register two words STREX Rt Rn offset Store register exclusive STREXB Rt Rn Store register exclusive byte STREXH Rt Rn Store register exclusive halfword STRH STRHT Rn offset Store register halfword STRSB STRSBT Rn offset Store register signed byte STRSH STRSHT Rn offset Store register signed halfword STRT Rn offset Store register word SUB SUBS Rd Rn Op2 Subtract SUB SUBW Rd Rn imm12 Subtract 12 bit constant SVC imm Supervisor call SXTB Rd Rm ROR n Sign extend a byte Rd Rm ROR n Sign extend a halfword TBB Rn Rm Table branch byte 80 TBH Rn Rm LSL 1 Table branch halfword 80 TEQ Rn Op2 Test equivalence N Z C 57 TST Rn Op2 Test N Z C 57 14 September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Table 1 1 Cortex M3 Instructions continued Mnemonic Operands Brief Description Flags See Page UBFX Rd Rn lsb width Unsigned bit field extract 70 UDIV Rd Rn Rm Unsigned divide 64 UMLAL RdLo RdHi Rn Rm Unsigned multiply with accumulate 62 32x32 64 64 bit result UMULL RdLo RdHi Rn Rm
76. sions on page 20 Operation LDR loads a register with a value from a PC relative memory address The memory address is specified by a label or by an offset from the PC The value to load or store can be a byte halfword or word For load instructions bytes and halfwords can either be signed or unsigned See Address Alignment on page 20 label must be within a limited range of the current instruction Table 2 3 on page 34 shows the possible offsets between label and the PC September 07 2010 Texas Instruments Incorporated 33 Memory Access Instructions 2 5 3 2 5 4 2 5 5 34 Table 2 3 Offset Ranges Instruction Type Offset Range Word halfword signed halfword byte signed byte 4095 to 4095 Two words 1020 to 1020 a You might have to use the 1 suffix to get the maximum offset range See Instruction Width Selection on page 22 Restrictions In these instructions m Rt can be SP or PC only for word loads m Rt2 must not be SP and must not be PC m Rt must be different from Rt2 When Rt is PC in a word load instruction m Bit 0 of the loaded value must be 1 for correct execution and a branch occurs to this halfword aligned address m Ifthe instruction is conditional it must be the last instruction in the IT block Condition Flags These instructions do not change the flags Examples LDR RO LookUpTable Load RO with a word of data from an address labeled as
77. stination registers For UMLAL and SMLAL they also hold the accumulating value Rn Rm Are registers holding the operands Operation The UMULL instruction interprets the values from Rn and Rmas unsigned integers It multiplies these integers and places the least significant 32 bits of the result in RdLo and the most significant 32 bits of the result in RdHi The UMLAL instruction interprets the values from Rn and Rmas unsigned integers It multiplies these integers adds the 64 bit result to the 64 bit unsigned integer contained in RdHi and RdLo and writes the result back to RdHi and RdLo The SMULL instruction interprets the values from Rn and Rm as two s complement signed integers It multiplies these integers and places the least significant 32 bits of the result in RdLo and the most significant 32 bits of the result in RdHi The SMLAL instruction interprets the values from Rn and Rm as two s complement signed integers It multiplies these integers adds the 64 bit result to the 64 bit signed integer contained in RdHi and RdLo and writes the result back to RdHi and RdLo Restrictions In these instructions September 07 2010 Texas Instruments Incorporated Cortex M3 Instruction Set Donotuse SP and do not use PC m RdHi and RdLo must be different registers 4 2 4 Condition Flags These instructions do not affect the flags 4 2 5 Examples UMULL RO R4 R5 R6 Unsigned R4 R0 R5 x R6 SMLAL R4 R5 R3 R
78. t SE EMU 51 3 0 22 D e11 1118 EE 51 3 59 37 E ee EE EE 51 3 54 Condition Flags see dee pane ee A oe ask Bd EE eee ee de en EE 51 3 5 5 Examples sen A E nan ent ENEE LARA 51 3 6 MOV and MVN WEE 52 KONNEN 52 3 0 2 e Ce TEE 52 3 60 32 RESIIICUONS sn sm enr EE 53 3 6 4 Condition FlagS TE 53 30 29 TN 53 3 7 MONT int BE nn EEEE TE te th ee ane alias eda ate Ae ea 54 SL SN O eebe ge dee beet 54 3 72 E e Ee TEE 54 E E ee EE 54 3 14 Condition Flag rue ii range Seen dee eh ee deed Seed en 54 327 0 JEXAMPplES EE 54 3 8 REV REV16 REVSH and RIIT 55 3 68 1 ENEE nn engen E des a nd E ea nn dant 55 KE Ee e Ee EE 55 SE See EE 55 3 9 4 Condition Flags 35 rinda ten 56 3 8 2 C A O EEEE aient lirica 56 3 9 TS RL RE e EEN 57 BOT OMIR hr nas ease ten AR EE 57 3 9 2 Operator art tao bio dal aan 57 E EN ele E 57 3 94 Condition Ge 57 3 9 5 Examples menti ee Seege Ole ane in al sateen 58 4 Multiply and Divide Instructions nes 59 4 1 MULE MLA and MES en seess SEA nue tsa dete Ee EE dee AE dus stade ten 60 We E DEEL LE kde Arete ee Ad a eh e 60 41 20 Operation E 60 E E GE Ee de sien ft nt RAT AR Lt en SR nn A Sn Li a 60 41 4 Condition Elie ii de EE chats 61 E SN Tue 61 4 2 UMULL UMLAL SMULL and SMLAL iii 62 IS O A A 62 4 2 2 Op ration it dad dd ita bli tias 62 42 3 erte 62 4 24 Condition Fleece a An ee aes tae M RE 63 4 2 5 Tue EE 63 4 3 AUN A IN 64 o e A VE 64 43 2 Operation Actes
79. ten back to the SP PUSH and POP are the preferred mnemonics in these cases 2 7 2 Operation PUSH stores registers on the stack in order of decreasing register numbers with the highest numbered register using the highest memory address and the lowest numbered register using the lowest memory address POP loads registers from the stack in order of increasing register numbers with the lowest numbered register using the lowest memory address and the highest numbered register using the highest memory address See LDM and STM on page 35 for more information 2 7 3 Restrictions In these instructions m reglist must not contain SP m For the PUSH instruction reg1ist must not contain PC m For the POP instruction reg1ist must not contain PC if it contains LR When PC is in reglist in a POP instruction m Bit 0 of the value loaded to the PC must be 1 for correct execution and a branch occurs to this halfword aligned address m If the instruction is conditional it must be the last instruction in the IT block 2 7 4 Condition Flags These instructions do not change the flags September 07 2010 37 Texas Instruments Incorporated Memory Access Instructions 2 7 5 Examples PUSH RO R4 R7 PUSH R2 LR POP RO R10 PC 38 September 07 2010 Texas Instruments Incorporated 2 8 2 8 1 2 8 2 Cortex M3 Instruction Set LDREX and STREX Load and Store Register Exclusive Syntax LDREX cond Rt Rn offset
80. ter left or right by a specified number of bits the shift length Register shift can be performed m Directly by the instructions ASR LSR LSL ROR and RRX and the result is written to a destination register m During the calculation of Operana2 by the instructions that specify the second operand as a register with shift see Flexible Second Operand on page 15 The result is used by the instruction The permitted shift lengths depend on the shift type and the instruction see the individual instruction description or see Flexible Second Operand on page 15 If the shift length is 0 no shift occurs Register shift operations update the carry flag except when the specified shift length is 0 The following sub sections describe the various shift operations and how they affect the carry flag In these descriptions Rm is the register containing the value to be shifted and n is the shift length ASR An arithmetic shift right ASR by n bits moves the left hand 320 n bits of the register Rm to the right by n places into the right hand 32 n bits of the result And it copies the original bit 31 of the register into the left hand n bits of the result See Figure 1 1 on page 17 You can use the ASR n operation to divide the value in the register Rm by 2 with the result being rounded towards negative infinity When the instruction is ASRS or when ASR n is used in Operand2 With the instructions MOVS MVN
81. uction Set Next 4 instructions are conditional Conditional move Conditional add Conditional AND Branch instruction can only be used in the last instruction of an IT block Next instruction is conditional Syntax error no condition code used in IT block 79 Texas Instruments Incorporated Branch and Control Instructions 7 4 7 4 1 7 4 2 7 4 3 7 4 4 7 4 5 80 TBB and TBH Table Branch Byte and Table Branch Halfword Syntax TBB Rn Rm TBH Rn Rm LSL 1 where Rn Is the register containing the address of the table of branch lengths If Rn is the Program Counter PC register R15 then the address of the table is the address of the byte immediately following the TBB or TBH instruction Rm Is the index register This contains an index into the table For halfword tables LSL 1 doubles the value in Rm to form the right offset into the table Operation These instructions cause a PC relative forward branch using a table of single byte offsets for TBB or halfword offsets for TBH Rn provides a pointer to the table and Rm supplies an index into the table For TBB the branch offset is twice the unsigned value of the byte returned from the table For TBH the branch offset is twice the unsigned value of the halfword returned from the table The branch occurs to the address at that offset from the address of the byte immediately after the TBB or TBH instruction
82. ushing data onto Empty STMED is s synonym for STMDB and refers to its use for pushing data onto Full Descending stacks 35 Memory Access Instructions 2 6 2 2 6 3 2 6 4 2 6 5 2 6 6 36 Operation LDM instructions load the registers in reg1ist with word values from memory addresses based on Rn STM instructions store the word values in the registers in reglist to memory addresses based on Rn For LDM LDMIA LDMFD STM STMIA and STMEA the memory addresses used for the accesses are at 4 byte intervals ranging from Rn to Rn 4 n 1 where n is the number of registers in reglist The accesses happen in order of increasing register numbers with the lowest numbered register using the lowest memory address and the highest number register using the highest memory address If the writeback suffix is specified the value of Rn 4 n 1 is written back to Rn For LDMDB LDMEA STMDB and STMED the memory addresses used for the accesses are at 4 byte intervals ranging from Rn to Rn 4 n 1 where n is the number of registers in reglist The accesses happen in order of decreasing register numbers with the highest numbered register using the highest memory address and the lowest number register using the lowest memory address If the writeback suffix is specified the value of Rn 4 n 1 is written back to Rn The PUSH and POP instructions can be expressed in this form See PUSH and POP on page 37 for deta
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