5648 User's Manual - CSL-EP
Contents
1. JA Vo 08 los Vec Supply Cure Cela IccsB Vcc Supply Current Standby 5 5V Vin or GND Port Conditions Open High O P Open Only With Data Bus High Low CS High Reset Low Pure Inputs Low High NOTES 1 Pins A4 CS WA AD Reset 2 Data Bus Ports B C 3 Outputs open 4 Limit output current to 4 0 mA INTEL CORPORATION 1992 18 Appendix A 43 intel 82C55A CAPACITANCE 25 C GND OV Parameter Min Max Unite TestConditione Input Capaotance 10 F unmeasuredphs returned to GND e o Taer fe 1 MHz 5 NOTE 5 Sampled not 100 iested CHARACTERISTICS 0 to 70 C 5V 110 GND OV 40 C to 85 for Extended Temperature BUS PARAMETERS READ CYCLE EEE EO E ww Time Af RDT 9 ET Test Conditions WRITE CYCLE Symbol Parameter we Address Stable Balore WR o m Address Holi Time After WRT 20 ms 10 me Cate Seip Timo Sie WT we __ me Deta Hoa Time After WR T 5 ns ras ne lwp INTEL CORPORATION 1992 18 Appendix A 44 OTHER THINGS Symbol ia Unks Test n PerpheralDataBeforer o Ws FebmaDmMweRD 02. aai 1 Conventions Used In This Manual Ne 1 Symbols and Terminology tt 2 Technical S pport Sissi nien xm ertt cine er erede 3 CHAPTER 1 nnn 5 DESC DU QR 5 Major Features E 6 CHAPTER 2 INSTALLATION 7 QUIPMEN m L 7 Installation EM 7 Base Address ipso trea ee deep id rn bs 9 Port PIROUES erp aT 11 CHAPTER 3 CONTROLLING I O LINES 13 Descriptiob ea 13 Pott Addresses sss ral cla 14 Configuring I O Elles iret rtc ree d 15 EXxatmpl6e6 reiner ien 16 Pulling the 1 O Lines High or LOW eene 17 Access Indicator LEDS 2 orn e N nna wan aka ERE 17 Driving OPTO Module Racks ient tne 17 G4 Opto isolated Modules pe 17 G5 Analog i Modules xen mand taie a 18 TOUDLESHOOE AG nou iaia 20 Power Module lia 20 Jumper Configuration sissies ita ia 20 CHAPTER 4 TECHNICAL DATA 21 Technical Specifications cite ee dei rers 21 I O A 22 Jiumper Configurations nior creme aad 22 Connector PINGUS ens ala 24 APPENDIX A INTEL 82C55 DATA SHEET 25 WARRANTY PREFACE This manual is a guide to the proper configuration and operation of your 5648 Analog Digital Interface Card Install
3. 20 Common Installation 12 Chapter 3 CONTROLLING I O LINES DESCRIPTION The 48 digital 1 0 lines the 5648 are supplied by two 82C55 chips The 82C55 located in U13 is connected toJ 1 and the 82C55 located in U12 is connected toJ 2 On power up and software or hardware reset all the digital 1 0 lines in J 1 and J 2 are configured as inputs All lines are TTL logic level compatible 0 5V and have 22K pull up down resistors to the 5V supply The 24 digital 1 0 lines at J 1 and J 2 can be used to interface to switches turn on low current LEDs and other devices that have TTL input or output for examples printers and scales The STB 26 terminal board provides a convenient way of interfacing switches or other digital 1 0 devices to the J 1 and J 2 A CMA 26 cable is used to interface the STB terminal board to the 5648 Digital O devices are then connected to the screw terminals on the STB 26 You can also connect opto module racks and drive G4 opto isolated and G5 analog modules Figure 3 1 shows a typical terminal board and or opto rack configuration 13 9 4 557353 RENEE g eooeeoeoepoeenosedqdq MPB Opto Rack DigitalAnalog igital Analog Interface Card Y 26 Ribbon Cable Ns N CMA 26 Ribbon Cable STB 26 Terminal Board Figure 3 1 Typical Terminal Board and Opto Rack Configuration Controlli
4. 5648 Analog Digital Interface Card Micro PC Motherboard Card Edge Pins A1 amp BI Figure 2 3 E dge Connector Orientation Installation 10 1 Verify the base address settings are correct for your applica tion 2 Make sure power to the card cage is OFF 3 Slide the 5648 into the card cage The components the card should face to the left or up depending on the type of card cage 4 The amber LEDs will light briefly whenever the card is accessed input or output at J 1 or J 2 PORT PINOUTS The pinouts are identical for connectors J 1 and J 2 Each connector has 24 1 0 lines 3 ports 5 volts and ground The individual ports are designated A B and C Port A has the lowest address each half of port C is controllable upper and lower C Each port pin has a 22K pull up down resistor Installation 11 Digital UO amp J2 Position Function Port A line 0 Port A line 1 9 Port A line 2 10 Port A line 3 11 Port A line 4 12 22 PortA lines 13 13 20 14 14 18 Port line 7 15 15 10 Port B line 0 16 16 8 Port B line 1 17 17 4 Port B line 2 18 18 6 Port B line 3 19 19 1 Port B line 4 20 20 3 Port B line 5 21 21 5 pPorB line6 22 22 7 Port B line 7 23 23 16 Port C line 1 1 1 15 Port C line 2 2 2 17 Port C line 3 3 3 14 Port C line 4 4 4 11 Port C line 5 3 3 12 Port C line 6 6 6 7
5. Controlling 1 0 Lines 20 Chapter 4 TECHNICAL DATA TECHNICAL SPECIFICATIONS The 5648 accepts switch dosures and logic inputs drives displays and LEDs and interfaces with opto mounting racks Each 1 0 line has a 22K pull up down resistor external resistors are not required when using switch contacts The 5648 will interface with most parallel devices induding LCD and DP vacuum fluorescent series displays printers and single LEDs The 1 0 levels are 0 5 volts and are compatible with standard TTL logic levels DC Characteristics Input Low 0 3V to 0 8V Input High 2V to Vcc Output Low 0 45V maximum Output High 2 4V minimum Connectors Two male 26 position straight 1 0 connectors Ansley 609 1007 Mates with Octagon CMA 26 cable Opto Rack Interface Directly drives Octagon MPB series opto racks using CMA 26 cable Drives G4 opto isolated and G5 analog modules Software Support Software drivers are provided on the 5648 utility disk A README DOC text file explains the driver usages Bus Compatibility Electrically compatible with the PC bus designed to be used in the Micro PC card cage with Octagon s Micro PC Control Cards May be used with AT sized PC s if used in conjunction with adapter bracket Power Requirements 5V 5 at 270 mA typical 300 mA maximum Environmental 40 to 70 C operating temperature 50 to 85 C nonoperating 5 to 9596 RH noncondensing Size 4 5 in x 4 9 in
6. Ips Per Data Before STB High 2 ns er Wer wo AC o Ouput w e wos WR 1w0er o ir STE 1toINTR 1 150 n fart ACK 1to INTR 1 150 ns wit WR Oto INTR 0 200 ns see note 1 1RES Reset Pulse Width so ns seenote2 NOTE 1 INTR may occur as early as WA 2 Pulse width of initial Reset pulse after power on must be at least 50 Subsequent Reset pulses may be 500 ns minimum INTEL CORPORATION 1982 20 Appendix A 45 intel B2C55A WAVEFORMS MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT sa an 231256 23 INTEL CORPORATION 1962 21 Appendix A 46 intel 82C55A WAVEFORMS Continued MODE 1 STROBED INPUT 231256 24 INTEL CORPORATION 1982 22 Appendix A 47 WAVEFORMS Continued MODE 2 BIDIRECTIONAL DATA FROM 8258 TO 8080 Note Any sequence where WR occurs before ACK AND STE occurs before RD is permissible INTR IBF MASK STE AD MASK ACK WA WRITE TIMING READ TIMING A C TESTING LOAD CIRCUIT 28 24 gt rowre lt t n due se es 231256 29 Testing inputs Are Driven At 2 4V For A Logic 1 And 45V For A Logic O Timing Measurements Ars Made At 2 0V For Logic 1 And 0 8 For A Logic D 17 ES UNDER 231256 30 Vex Is Set Al Various Voltages During Testing To Guarantee The Specification C Includes
7. CONTROL WORD 12 D Oe D D D D O Dy CONTROL WORD 13 By Da s Dy D Dy Dp Operating Modes MODE 1 Strobed Input Output This functional configuration provides a means for transferring MO data to or from specilied port in conjunction with strobes or handshaking signals In mode 1 Port A and Port B use the lines on Port C to generate or accept these handshaking signals INTEL CORPORATION 1992 CONTROL WORD 18 Dj Dy D Dy Oy 0 D Mode 1 Basic functional Definitions Two Groups Group A and Group B Each group contains one 8 bit data port and one 4 bit control data port The 8 bit data port can be either input or output Both inputs and outputs are latched The 4 bit port is used for control and status of the 8 bit data port Appendix A 35 intel Input Control Signal Definition STB Strobe input low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output indicates that the data has been loaded into the input latch in essence an ac knowledgemeni IBF is set by STB input being low and is reset by the rising edge of the input INTR Interrupt Request A high on this output can be used to interrupt the CPU when an input device is requesting service INTR is set by the STB is a one IBF is a one and INTE is a one It is reset by the falling edge of RD This procedure all
8. are used WI NOTE PC SmartLINK Reset TTL Compatible H Denotes a jumper block and the pins to connect Information under this heading presents helpful tips for using the 5648 Information under this heading warns you of situations which might cause catastrophic or irreversible damage A serial communications software package designed by Octagon It provides communica tions between a PC and other equipment and may be used with any PC software package induding CAMBASIC IV Refers to all versions of PC SmartLINK Resetting the system hardware and software by pushing the reset switch Has the same results as disconnecting power to the system without the potential side effects of a cold reset 0 5V logic levels The suffix H denotes a hexadecimal number For example 1000H in hexadecimal equals 4096 in decimal Preface 2 TECHNICAL SUPPORT If you have a question about the 5648 Analog Digital Interface Card and can t find the answer in this manual call Technical Support They will be ready to give you the assistance you need When you call please have the following at hand Your 5648 Analog Digital Interface Card User s Manual A description of your problem The direct line to the Technical Support is 303 426 4521 Preface 3 This page intentionally left blank Preface 4 Chapter 1 OVERVIEW DESCRIPTION The Micro 5648 Analog Digital Interface Card accepts switch dosures and lo
9. Technical Data 21 Port Address Functions Function Port Address Port A Base 00H Port B Base 01H Port C Base 02H Control Register Base 03H J2 Port Base 04H J2 Port B Base 05H J2 Port C Base 06H J2 Control Register Base 07H J2 GS input start conversion D7 1 write Counter Data Low read Base OSH Reset Counter write Counter Data High read Fees Channel Select Mux 1 of 24 write Channel Select Mux read back read Base DAB Status Register Interrupt Bit 7 1 State Code Bits Base 0BH 0 3 Value of 8FH overflow JUMPER CONFIGURATIONS Base Address Select W1 Pins J umpered Base Address 1 2 3 4 5 6 100H 3 4 5 6 110H 1 2 5 6 120H 5 6 130H 1 2 3 4 140H 3 4 150H 1 2 160H Not jumpered 170H default Technical Data 22 Interrupt Select W1 ET 7 8 3 9 10 4 11 12 5 13 14 6 15 16 7 8 10 Nointerrupts default W2 amp W3 Digital 1 0 Pull up Pull down Resistors J umpered 1 2 1 0 lines pulled high 2 3 1 0 lines pulled low default Description Technical Data 23 CONNECTOR PINOUTS Digital amp J2 Position Function Port line 0 Port line 1 9 Port line 2 10 25 Pora lines 24 PortA line4 12 22 Port line 5 13 13
10. one of the most common failures of expansion cards Using desktop PC power supplies Occasionally a cus tomer will use a regular desktop PC power supply when bringing up a system Most of these are rated at 5V at 20A or more Switching supplies usually require a 2096 load to operate properly This means 4A or more Since a typical Micro PC system takes less than 2A the supply does not regulate properly Customers have reported that the output can drift up to 7V and or with 7 8V voltage spikes Unless a scope is connected you may not see these transients Terminated backplanes Some customers try to use Micro PC cards in backplanes that have resistor capacitor termina tion networks CMOS cards cannot be used with termination networks Generally the cards will function erratically or the bus drivers may fail due to excessive output currents Excessive signal lead lengths Another source of failure that was identified years ago at Octagon was excessive lead lengths on digital inputs Long leads act as an antenna to pick up noise They can also act as unterminated transmission lines When 5V is switch onto a line it creates a transient waveform Octagon has seen submicrosecond pulses of 8V or more The solution is to place a capacitor for example 0 1 uF across the switch contact This will also eliminate radio frequency and other high frequency pickup Using CMOS 4 TABLE OF CONTENTS ldizz iel
11. 20 Port line 6 14 14 18 Port line 7 15 15 10 Port B line 0 16 16 8 Port B line 1 17 17 4 Port B line 2 18 18 6 19 19 1 Port B line 4 20 20 3 Port B line 5 21 21 5 Port B line 6 22 22 7 Port B line 7 23 23 13 Port C line 0 0 16 PortC linel 1 15 PortC line2 2 17 Port C line 3 3 14 Port C line 4 4 11 Port C line 5 5 12 Port line 6 6 7 9 Port line 7 Technical Data 24 Appendix A Intel 82C55 Data Sheet INTEL 82C55A DATA SHEET The material in this appendix is Copyright 1992 Intel Corporation Appendix 25 intel 82C55A CHMOS PROGRAMMABLE PERIPHERAL INTERFACE w Compatible with ali intel and Most m Control Word Read Back Capability Other Microprocessors u Direct Bit Set Reset Capability High Speed Zero Wait State Operation with 8 MHz 8086 88 and soa Capability on all 1 0 SEI Available in in DIP and 44 Pi CC m 24 Programmable 1 0 Pins Aa vallable in EXPRE m Low Power CHMOS Standard Temperature Range m Completely TTL Compatible Extended Temperature Range The Intel 82C55A is a high performance CHMOS version of the industry standard 8255 general purpose programmable device which is designed for use with all Intel and most other microprocessors It provides 24 pins which may be individually programmed in 2 groups of 12 and used in 3 major modes of operation The 82 55 is pin compatible w
12. J1 8 ri o 0 o Address gt _ o a 5 gt dj les Control W3 5 ti a 5 o gt 9 o seg 2 O 5 8 E 5 o o 8 EE o o o L gt x 8 O A o o 8 gl Interrupt 8 5 Select oa o o o a lt gt o o 8 o o 9 Mux ID o o o o Figure 2 2 5648 Functional diagram Base Address The 5648 is configured at the factory to operate in most systems without any jumper changes J umper block W1 defines the base address As shipped the base address is 100H which is jumper configuration W1 1 2 3 4 5 6 If thereis another card in your system with a base address of 100H you must use a different base address for the 5648 or the other expansion card To change the base address change the jumper connections in block W1 Installation 9 Base Address Select W1 Pins J umpered Base Address 1 2 3 4 5 6 100H 3 4 5 6 110H 1 2 5 6 120H 5 6 130H 1 2 3 4 140H 3 4 150H 1 2 160H Not jumpered 170H default To install the 5648 in the card cage Take care to correctly position the 5648 in the cage The V and ground signals must match those on the backplane Figure 2 3 shows the relative position of the 5648 as it is installed in the card cage A31 Card Edge Pins A31 amp B31
13. Jig Capacitance 9 INTEL CORPORATION 1982 23 Appendix A 48 WARRANTY Octagon Systems Corporation Octagon warrants that its stan dard hardware products will be free from defects in materials and workmanship under normal use and service for the current established warranty period Octagon s obligation under this warranty shall not arise until Buyer returns the defective product freight prepaid to Octagon s facility or another specified location Octagon s only responsibility under this warranty is at its option to replace or repair free of charge any defective component part of such products LIMITATIONS ON WARRANTY The warranty set forth above does not extend to and shall not apply to 1 Products including software which have been repaired or altered by other than Octagon personnel unless Buyer has properly altered or repaired the products in accordance with procedures previously approved in writing by Octagon 2 Products which have been subject to power supply reversal misuse neglect accident or improper installation 3 The design capability capacity or suitability for use of the Software Software is licensed on an AS IS basis without warranty The warranty and remedies set forth above are in lieu of all other warranties expressed or implied oral or written either in fact or by operation of law statutory or otherwise including warranties of merchantability and fitness for a particular purpose
14. the 82 55 to respond to FD and WA signals AD and WR are ignored otherwise rr si GND 7 8 System Ground A1 0 8 9 9 10 I ADDRESS These input signals in conjunction RD and WR control the selection of one of the three ports or the control word registers CS Input Operation Read Port Data Bus Port B Data Bus Port C Data Bus Control Word Data Bus Output Operation Write Data Bus Port A Data Bus Port o o DataBus PorC la o DataBus Control Disable Function x x 1 bataBus 3 Siate x x 1 1 0 Det Bus 3 State PC7 4 10 13 MD POAT C PINS 4 7 Upper nibble of an 8 51 date output latch buffer and 8 bit data input buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains 4 bit latch and it can be used for the control Signal outputs and status signal inputs in conjunction with ports and B PCo 3 14 17 PORT PINS 0 3 Lower nibble of Port C PBo 7 18 25 I O PORT PINS 0 7 An 8 bit data output latch buffer and an 8 bit data input buffer 26 SYSTEM POWER 5V Power Supply 07 0 27 34 I O DATA BUS Bi diractional tri state data bus lines connected to system bus RESET 35 A high on this input clears the control register and all ports are sel to the inp
15. the conversion e Wait until the conversion is completed Read the counter data e Convert the counter data to 12 bit count The following is a sample program written in QuickBASIC V4 5 This program reads a G5 input module connected to an off opto rack If you run this program without a video card substitute the PRINT statement with the PRINTS funcion included on the 5648 utility disk The 5648 is mapped to 100H DEFINT A Z use integers where possible ZC4 250000 9 zero offset factor G5BASE amp H108 base address of counter OUT amp H107 amp H9B config 8255 port C as inputs FOR X 1 TO 1000 take 1000 samples OUT G5BASE 1 0 reset freq counter OUT G5BASE 2 8 select G5 channel 8 OUT G5BASE amp H80 start conversion WHILE INP G5BASE 3 lt amp H7F poll until conv done WEND LSB amp INP G5BASE read count Isb MSB amp INP G5BASE 1 read count msb WORD amp LSB amp MSB amp 256 form the word VALUE INT ZC WORD amp WORD amp 1024 5 scale value PRINT VALUE NEXT X END The conversion time will be less than 1 mS maximum The End of Conversion may be determined either by using an interrupt or by polling the status register In the event that a conversion is started on a channel that is not connected to a G5 module the counting circuit will time out with a count value of 7FFFH The data that is read is contained in 1
16. which Octagon specifically disdaims Octagon neither assumes nor authorizes any other liability in connection with the sale installa tion or use of its products Octagon shall have no liability for incidental or consequential damages of any kind arising out of the sale delay in delivery installation or use of its products SERVICE POLICY 1 Octagon s goal is to ship your product within 5 working days of receipt 2 Ifa product should fail during the warranty period it will be repaired free of charge For out of warranty repairs the customer will be invoiced for repair charges at current stan dard labor and materials rates 3 Customers that return products for repairs within the warranty period and the product is found to be free of defect may be liable for the minimum current repair charge RETURNING A PRODUCT FOR REPAIR Upon determining that repair services are required the customer must 1 Obtain an RMA Return Material Authorization number from the Customer Service Department 303 430 1500 2 If the request is for an out of warranty repair purchase order number or other acceptable information must be sup plied by the customer 3 Indude a list of problems encountered along with your name address telephone and RMA number 4 Carefully package the product in an antistatic bag Failure to package in antistatic material will VOID all warranties Then package in a safe container for shipping Write RMA nu
17. work with the 508x Microcontrollers The software utility disk does not apply WARNING The 5648 contains static sensitive CMOS compo nents The greatest danger occurs when the card is plugged into a card cage The 5648 becomes charged by the user and the static discharges to the backplane from the pin dosest to the card connector If that pin happens to be an input pin even TTL inputs may be damaged To avoid damaging your card and its components e Ground yourself before handling the 5648 Digital 1 0 Card e Disconnect power before removing or insert ing the 5648 Card EQUIPMENT You will need the following equipment or equivalent 5648 Analog Digital Interface Card e Micro PC Control Card e Micro PC Card Cage e Power Supply or Module e PC SmartLINK or other communications software INSTALLATION Before installing the 5648 Analog Digital Interface Card refer to Figure 2 1 for the location of various connectors and jumpers and Figure 2 2 for a functional diagram of the card Installation 7 Digital MO Base Pull up Down Address Interrupt Resistors Select Indicator Digital MO J2 Access Indicator Digital MO B Pin 1 Figure 2 1 5648 Component Diagram Installation 8 W2 5 F 0 gt T o lt 6 Data 5 4 Data 4 a m E Zad E 18 a a 8
18. 5 bits The most significant bit of the high data byte will always be a zero The data that is read must be converted to a numeric value in the range of 0 to 4095 as per the above program example NOTE The utility disk also includes software drivers that can be used to read G5 input modules Descriptions of the drivers are induded in the README DOC file Controlling 1 0 Lines 19 You may optionally configure the 5648 to generate an interrupt at the end of each conversion versus polling Use the W1 jumper block to define the interrupt number Interrupt Select W1 Interrupt 7 8 3 9 10 4 11 12 5 13 14 6 15 16 7 8 10 Nointerrupts default TROUBLESHOOTING If you have difficulty getting your system to work properly remove all expansion cards except the 5648 Digital Analog Interface Card from your system and check the power module and jumper configu rations Power Module The power module voltage should be 5V 0 25V when measured at the connector pins The power module ripple should be less than 50 mv Jumper Configuration The 5648 is shipped with jumper connections in place for Base 1 0 Address 100H J umper changes are usually not needed to get the system running If you changed the jumpers and the system is not working properly return the system to the original jumper posi tions If you still encounter difficulties please contact Technical Support at 303 426 4521
19. 5648 Users Manual Doc 03764 Rev 0194 OCTAGON SYSTEMS CORPORATION 6510 W 91st Ave Westminster CO 80030 Tech Support 303 426 4521 COPYRIGHT Copyright 1994 Octagon Systems Corporation rights re served However any part of this document may be reproduced provided that Octagon Systems Corporation is cited as the source The contents of this manual and the specifications herein may change without notice TRADEMARKS Micro PCM SmartLink Octagon Systems Corporation the Octagon logo and the Micro PC logo are trademarks of Octagon Systems Corporation NOTICE TO USER The information contained in this manual is believed to be correct However Octagon assumes no responsibility for any of the circuits described herein conveys no license under any patent or other right and makes no representations that the circuits are free from patent infringement Octagon makes no representation or war ranty that such applications will be suitable for the use specified without further testing or modification Octagon Systems Corporation general policy does not recommend the use of its products in life support applications where the failure or malfunction of a component may directly threaten life or injury It is a Condition of Sale that the user of Octagon products in life support applications assumes all the risk of such use and indemnifies Octagon against all damage IMPORTANT Please read before installing you
20. 92 13 Output Operations OBF Output Buffer Full The OBF output will go low to indicate that the CPU has written data oul 1o port A ACK Acknowledge A low on this input enables the tri state output buffer of to send out the data Otherwise the output buffer will be in the high impedance state INTE 1 The INTE Flip Fiop Associated with Controlled by bit set resel of PCs Input Operations STB Strobe Input A low on this input loads data into the input latch IBF Input Buffer Full F F A high on this output Indicates that data has been loaded into the input latch INTE 2 The INTE Flip Flop Associated with IBF Controlled by bit set reset of PCy Appendix A 38 intel 82C55A Figure 13 MODE Control Word 231256 19 Figure 14 MODE 2 Figure 15 MODE 2 Bidirectional NOTE Any sequence where WF occurs before ACK and STB occurs before RD is permissible INTR IBF MASK STB AD UBF MASK WR INTEL CORPORATION 1992 14 Appendix A 39 intel 82 55 MODE 2 AND MODE 0 INPUTS MODE 2 AND MODE 0 OUTPUT CONTROL WORO D Dy My Dy Dy D D Pe 2 1 e CONTROL WORD D D Oy Da Oy Dy D Dy 1 ut 0 OUTPUT MODE 2 AND MODE 1 INPUT MODE 2 AND MODE 1 IOUTPUT CONTROL WORD 9 Ds Di D Da DI Os ET Teh zi 231256 21 Figure 16 MOD
21. CK Output Mode 1 or Mode 2 Figure 18 interrupt Enable Flags in Modes 1 and 2 INTEL CORPORATION 1992 ar Appendix A 42 intel 82C55A ABSOLUTE MAXIMUM RATINGS NOTICE This is a production data sh 8 subject to change without noti Ambient Temperature Under Bias 0 C to 70 WARNING Stressing the device beyond the Absolute Storage Temperature 65 C to 150 C Maximum Ratings may cause permanent damage Supply Voltage 0 5 to 8 0V These are stress ratings only Operation beyond the E ting Conditions is not recommended and ex Operating Vollage 4V to 7V tended exposure beyond the Operating Conditions Voltage on any Input GND 2V to 6 5V may affect device reliability Voltage on any Output GND 0 5V to 0 5V Power Dissipation 1 Watt D C CHARACTERISTICS Ta C lo 70 C 5V GND OV Ta 40 C to 85 C for Extended Temperture LM NN zn TAT Ga ian e Vor put Low Votage os en Output High Voltage lou 2 5 mA Voc 04 lon 100 uA liL Input Leakage Current Vin to OV Note 1 IOFL Output Float Leakage Current 10 pA Vin Voc to OV Note 2 mmm lou Port Hold Low Leakage Current 50 300 Vour 1 0V Port A only IPHH Porl Hold High Leakage Curreni pA Vout 3 0V Ports
22. E 14 Combinations INTEL CORPORATION 1992 15 Appendix A 40 Special Mode Combination Considerations There are several combinations of modes possible For any combination some or all of the C lines are used for control or status The remaining bils are either inputs or outputs as defined by a Set Mode command During a read of Port C the state of all the Port C lines except the and STE lines will be placed on the data bus In place of the ACK and STE line states flag status will appear on the data bus in the PC2 PC4 and PC6 bit positions as illustrated by Figure 18 Through a Write Port C command only the Port C pins programmed as outputs in Mode 0 group can be written No other pins can be affected by a Write Port C command nor can the interrupt enable flags be accessed To write to any Port C output pro grammed as an output in Mode 1 group or to INTEL CORPORATION 1992 16 82C55A MODE 0 OR MODE 1 ONLY change an interrupt enable flag the Set Reset Port C Bit command must be used With a Sot Resel Port C Bit command any Port C line programmed as an output including INTR IBF and can be written or an interrupt enable flag can be either set or reset Port C lines programmed as inputs including and STE lines associated with Port C are not affected by a Set Reset Port C Bit command Writing to the corresponding Port C bit positions of the ACK a
23. INTEL CORPORATION 1982 12 Appendix A 37 231256 16 Combinations of MODE 1 82C55A Port and Port B can be individually defined as input or output in Mode 1 to support a wide variety ol strobed YO applications CONTROL WORD 9 D By D Dy Dy DI BORE Coo Pay Ge INPUT 0 OUTPUT FORT STROGED INPUTI PORT B STROBED OUTPUT By n D B b 0 Oy CIE er T Ee Pas 1 FORT A FTROBED OUTPUT PORT B STRODED INPUT Figure 12 Combinations of MODE 1 Operating Modes MODE 2 Strobed Bidirectional Bus 1 0 This functional configuration provides means for com municating with a peripheral device or structure on a single 8 bit bus tor both transmitting and receiving dala bidirectional bus 1 0 Handshaking signals are provided to maintain proper bus flow discipline in a similar manner to MODE 1 Interrupt generation and enable disable functions are also available MODE 2 Basic Functional Definitions Used in Group only One 8 bit bi directional bus port Port A and a 5 bit control port Port Both inputs and outputs are latched The 5 bit control port Port C is used for control and status for the 8 bit bi directional bus port Port A Bidireclional Bus 1 0 Control Signal Definition INTR interrupt Request A high on this output can be used to interrupt the CPU for input or output oper ations INTEL CORPORATION 19
24. UT amp H103 amp H80 The following statement configures Ports A and C as input ports and B as an output port OUT amp H103 amp H99 Controlling 1 0 Lines 16 PULLING THE I O LINES HIGH OR LOW J umper block W2 pulls all of the 24 1 0 lines of the J 1 high or low while W3 affects the 24 1 0 lines of J 2 The factory default pulls all of the 1 0 lines high W2 amp W3 Digital 1 0 Pull up Pull down Resistors J umpered 1 2 1 lines pulled high 2 3 1 0 lines pulled low default Description ACCESS INDICATOR LEDS Two access indicators are on the 5648 one for each connector When the lower 24 1 0 lines of J 1 are accessed the J 1 LED will flash When the upper 24 1 0 lines or the G5 input module hardware is accessed the J 2 LED will flash DRIVING OPTO MODULE RACKS The 5648 can drive two MPB 8 16 or 24 series opto module racks via a CMA 26 cable interface To drive opto module racks plug one end of a CMA 26 cable into one of the connectors that you want to use and the other end into the MPB opto mounting rack Run ground and 45V to the opto mounting rack G4 Opto isolated Modules You can use G4 opto isolated modules when driving or receiving signals from high voltage and or high current devices Opto isolation also eliminates ground loops and significantly reduces the chance that noise will invade the system Use the following table to determine the corresponding opto channe
25. a testing charge from Octagon m Of the remaining 80 of the cards 90 of these cards fail due to customer misuse and accident Customers often cannot pinpoint the cause of the misuse W Therefore 7296 of the returned cards are damaged through some type of misuse Of the remaining 896 Octagon is unable to determine the cause of the failure and repairs these cards at no charge if they are under warranty The most common failures on CPU cards are over voltage of the power supply static discharge and damage to the serial and parallel ports On expansion cards the most common failures are static discharge over voltage of inputs over current of outputs and misuse of the CMOS circuitry with regards to power supply sequencing In the case of the video cards the most common failure is to miswire the card to the flat panel display Miswiring can damage both the card and an expensive display m Multiple component failures The chance of a random component failure is very rare since the average MTBF of an Octagon card is greater than 11 years In a 7 year study Using CMOS Circuitry 2 Octagon has never found single case where multiple 1C failures were not caused by misuse or accident It is very probable that multiple component failures indicate that they were user induced Testing dead cards For a card that is completely nonfunctional there is a simple test to determine accidental over voltage reverse voltage or othe
26. ation instructions card mapping information and jumpering options are described in the main body of the manual technical specifications are induded in the appendices The 5648 card is designed to be used with any Octagon Micro PC Control Card This combination provides a modular system which is easy to set up modify and use Y ou can also use your 5648 in conjunction with other Micro PC expansion cards allowing you to tailor your system for a wide variety of applications CONVENTIONS USED IN THIS MANUAL 1 Information which appears on your screen output from your system or commands or data that you key in is shown in a different type face Example 1 Octagon 5648 ROM BIOS Vers X XX Copyright c 1993 Octagon Systems Corp All rights reserved Example 2 Press the lt E SC gt key 2 ltalidzed refers to information that is specific to your particu lar system or program for example Enter filename means enter the name of your file Names of other sections or manuals are also italicized 3 Warnings always appear in this format WARNING The warning message appears Preface 1 4 Paired angle brackets are used to indicate a specific key your keyboard for example lt E SC gt means the escape key CTRL gt means the control key lt 1 means the F1 function key 5 All addresses are given in hexadecimal SYMBOLS AND TERMINOLOGY Throughout this manual the following symbols and terminology
27. buffer no latch for input This port can be divided into two 4 bit ports under the mode control Each 4 bit port contains a 4 bit latch and it can be used for the control signal outputs and status signal inputs in conjunction with ports A and B Only pull up bus hold devices are present on Port C See Figure 4 for the bus hold circuit configuration for Port B and C Appendix A 28 231258 4 Port pins loaded with more than 20 pF capacitance may not have their logic level guaranteed following hardware reset Figure 4 Port A B C Bus hold Configuration INTEL CORPORATION 1992 4 Appendix A 29 intel 82C55A OP amp RATIONAL DESCRIPTION Mode Selection There are three basic modes of operation that can be selacted by the system software Mode 0 Basic input output Mode 1 Strobed Input output Mode 2 Bi directional Bus When the reset input goes high all ports will be set to the input mode with all 24 port lines held at a logic one tevel by the internal bus hold devices see Figure 4 Note After the reset is removed the 82C55A can remain in the input mode with no addi tional initialization required This eliminates the need for pullup or pulldown devices in all CMOS de signs During the execution of the system program any of ihe other modes may be selected by using single output instruction This allows single 82C55A to service a variety of peripheral dev
28. gic inputs drives displays and LEDs and interfaces with opto module racks It also allows analog input and output modules to be mixed with digital 1 0 modules in the same opto isolator rack Twenty four of the 48 lines can be used for either analog or digital 1 0 while the remaining 24 lines are digital 1 0 only Each 1 0 line has a 22K pull up resistor so that external resistors are not required when reading switch contacts The measures 4 5 x 4 9 inches and uses one slot of the Micro PC card cage It is compatible with all Micro PC Control Cards and is elecrically compatible with standard sized CPU cards It requires 5 volts at 270 mA typical The 5648 interfaces with most types of parallel devices including LCD and VF displays printers and single LEDs 1 0 levels are 0 5V and are compatible with standard TTL logic levels If the field wiring requires termination use the STB 26 with a CMA 26 cable MPB OPTO RACKS 5648 Analog Digital DP IFB or LDC IFB Interface Card STB 26 TERMINAL BOARD TBD 100 TERMINAL BOARD OR ITB TERMINAL BOARDS Figure 1 1 Typical 5648 system configuration Overview 5 MAJOR FEATURES Driving Opto Racks The 5648 can drive up to two of the MPB xx opto module racks The isolator modules are required when driving or receiving signals from high voltage and or high current devices Opto isolation also elimi
29. gister Base 07H J2 GS input start conversion D7 1 write Counter Data Low read MAKALE Counter Data High ead adipi Status Register Interrupt Bit 7 1 State Code Bits Base 0BH 0 3 Value of 8FH overflow For a complete description of the capabilities of the 82C55 please refer to the information in Appendix A in the Intel Peripheral Databook Some of the chip s capabilities are described below CONFIGURING I O LINES On power up or reset all three ports are in the input state You can alter which ports are inputs or outputs by writing a control command to the control register in the 82C55 The examples below assume the base address is 100H Controlling 1 0 Lines 15 82C55 Control Register Commands OUT T T T 89H 137 OUT OUT IN IN 8AH 138 OUT IN IN OUT 8 139 OUT IN IN IN 90H 144 IN OUT OUT OUT 91H 145 IN OUT OUT IN 92 146 IN IN OUT OUT 93H 147 IN IN OUT IN 98 152 IN OUT IN OUT 99H 153 IN OUT IN IN 9AH 154 IN IN IN OUT 9BH 155 IN IN IN IN Ports A and must be either all inputs of all outputs Each half of Port C is controllable Upper C UC includes bits 4 through 7 and Lower C LC includes bits 0 through 3 Examples The following example shows how to configure all three ports as outputs when the base address is set at 100H O
30. ices with a simple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port A and Port B definitions All of the output registers including the status flip flops will be reset whenever the mode is changed Modes may be combined so that thelr functional definition can be tailored to almost any 1 0 structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display computa tional results Group could be programmed in Mode 1 to monitor keyboard or tape reader on an interrupt driven basis Figure 5 Basic Mode Definitions and Bus Interface INTEL CORPORATION 1992 MODE SET FLAG 3 ACTIVE Figure 6 Mode Definition Format The mode definitions and possible mode combina tions may seem confusing at first but alter a cursory review of tha complete device operation a simple logical I O approach will surface The design of the 82 55 has taken into account things such as effi cient PC board layout control signal definition vs PC layout and complete functional flexibility to support almost any peripheral device with no external logic Such design represents the maximum use of the available pins Single Bit Set Reset Feature Any of the eight bits of Port C can be Set or Heset using a single OUTput instruction This feature re duces software requirements in Cont
31. ith the NMOS 8255A and 8255 5 In MODE 0 each group of 12 1 0 pins may be programmed in sets of 4 and 8 to be inputs or outputs In MODE 1 each group may ba programmed to have 8 lines of input or output 3 of the remaining 4 pins are used for handshaking and interrupt control signals MODE 2 is a strobed bi direclional bus configuration The 82C55A is fabricated on Intel s advanced CHMOS IH technology which provides low power consumption with performance equal to or greater than the equivalent NMOS produci The 82C55A is available in 40 pin DIP and 44 pin plastic leaded chip carrier PLCC packages Figure 1 82C55A Block Diagram 231256 2 Figure 2 82C55A Pinout Diagrams are for pin refsrenca only Package sizes ara noi lo scale Intel Corporation assumes no responsibility for the use of any circuitry other Ihan circuitry embodied in an Intel product No other patent licenses are implied Information contained herein supersedes previously published specifications on these devices kom Intel September 1987 INTELCORPORATION 1992 Order Number 231256 004 Appendix 26 intel 82C55A Table 1 Pin Description Symbol rec Type Name and Function 0 1 4 2 5 PORT A PINS 0 3 Lower nibble of an 8 bit data output latch butter and an 8 bit data input latch READ CONTROL This input is low during CPU read operations CS 6 7 I CHIP SELECT A low on this input enables
32. l for a particular 82C55 port Remember to add the base address of the card Controlling 1 0 Lines 17 Opto Channels 82C55 J 1 Offset Port Address 2 47 2 6 8 15 A 0 4 16 23 B 1 5 For example if the base address of the 5648 is 110H the following would be entered into the program A INP amp H116 reads opto rack on J 2 channels 0 7 G5 Analog Modules OuTPUT Ports A B or may be used on either J 1 or J 2 for G5 analog output These ports must be configured as an output by writing to the control word register of the 82C55 Refer to the programming examples in the G5 directory on the 5648 utility disk for informa tion on using G5 output modules A file called README DOC describes the demo programs and functions that are available in QuickBASIC and C Octagon s G5 analog output driver routines momentarily disables all interrupts while in use NOTE Because of strict timing requirements when updating the G5 output module this feature is only available when the 5648 is used with the following Micro PC Control Cards 5012 5012A 5025 5025 486 6012 and 6024 INPUT Only 2 may be used for G5 analog inputs The frequency counter circuit used to read the G5 analog inputs is addressed at BASE 8 through BASE amp HB The steps for reading inputs are as follows e Reset frequency counter circuit e Write multiplexer channel 0 23 Controlling 1 0 Lines 18 Start
33. mber on the outside of the box For products under warranty the customer pays for shipping to Octagon Octagon pays for shipping back to customer 7 Other conditions and limitations may apply to international shipments NOTE PRODUCTS RETURNED TO OCTAGON FREIGHT COLLECT OR WITHOUT AN RMA NUMBER CANNOT BE ACCEPTED AND WILL BE RETURNED FREIGHT COLLECT RETURNS There will be 15 restocking charge on returned product that is unopened and unused if Octagon accepts such return Returns will not be accepted 30 days after purchase Opened and or used products non standard products software and printed materials are not returnable without prior written agreement GOVERNING LAW This agreement is made in governed by and shall be construed in accordance with the laws of the State of Colorado The information in this manual is provided for reference only Octagon does not assume any liability arising out of the application or use of the information or products described in this manual This manual may contain or reference information and products protected by copyrights or patents No license is conveyed under the rights of Octagon or others
34. nates ground loops and significantly reduces the chance that noise will invade the system The MPB xx racks interface to the 5648 via CMA 26 cables Driving Analog 1 0 Modules In addition to the standard digital 1 0 modules the 5648 is compatible with Grayhill G5 modules The G5 input modules produce a frequency output that is directly proportional to the input A custom ASIC on the 5648 converts the frequency to a 0 4095 count The commands from the CPU card select the channel and start the conversion The ASIC generates an interrupt on the completion of the conversion The maximum conversion time is 625 uS The analog modules accept thermocouples current loop RTD and voltage inputs Output modules indude voltage and current outputs The ASIC measures the frequency eliminating processor overhead The system will detect incorrect polarity out of range signal and missing or defective module conditions Driving Parallel Displays Adapter cables are available for driving VF and LCD series displays Software drivers are available You can also drive almost any parallel display Access Indication The 5648 has two LED indicators that flash briefly when each connector group of 24 is accessed This is useful when debugging software Overview 6 Chapter 2 INSTALLATION The 5648 Analog Digital Interface Card uses one slot of the Micro PC card cage It may be used with any Micro PC Control Card NOTE The G5 analog outputs will not
35. nd STB with the Sel Reset Port C Bit command will affect the Group A and Group B interrupt enable flags as illus trated in Figure 18 Current Drive Capability Any output on Pori A B or C can sink or source 2 5 mA This feature allows the 82C55A to directly drive Darlington type drivers and high voltage displays that require such sink or source current Appendix A 41 intel 82C55A Reading Port C Stetus INPUT CONFIGURATION D Da Ds De Da pz Di Do In Mode 0 Port transfers data to or from the pe ripheral device When the 82C55A is programmed to INTEA lBFa MM function in Modes 1 or 2 Port C generates or cepts hand sheking signals with the peripheral de GROUPA GROUPS vice Reading the contents of Port C allows the pro OUTPUT CONFIGURATIONS grammer to test or verify the status of each pe D De Ds D Ds Da Di Do a eee vo vo rra INTRE There is no special instruction to read the status in SROUFA GROUPA formation from Port C A normal read operation af Figure 17a MODE 1 Status Word Format Port C is executed to perform this function O7 Ds Ds D Da D Do armejerlwrelwrnl __ _ I GROUP A GROUP B Defined By Mode D or Mode 1 Selection Figure 17b MODE 2 Status Word Format Interrupt Enable Flag Alternate Port C Pin Signal Mode INTEB Output Mode 1 or STBg Input Mode 1 INTE A2 STB input Mode 1 or Moda 2 INTE A1 A
36. ng 1 0 Lines 13 PORT ADDRESSES Each 82C55 has three ports with eight parallel 1 0 lines bits port Each port has a unique I O address Port and Port can be programmed as all inputs or all outputs Port C can be pro grammed in one group of eight lines all inputs or all outputs or as two groups of four lines upper and lower C The four lines in upper or lower C can each be programmed as all inputs or all outputs 5648 Digital 1 0 Port J 1and J 2 Description 8lines which can be programmed as all inputs or all outputs 8lines which can be programmed as all inputs or all outputs 8 lines interfaceto a high current driver 8lines which can be programmed as one group of 8 lines or two groups of 4 lines as all inputs or all outputs Control Register 1x3H 1x7H NOTE xis the value 0 7 depending on the base address selection at W1 When a line is configured as an output it can sink a maximum of 2 5 mA at 0 4V and can source over 2 5 mA at 2 4V When driving opto modules the output can sink 15 mA at 1 0V The 5648 uses a block of 16 addresses Refer to the following table for the function of the associated address Controlling 1 0 Lines 14 Port Address Functions Function Port Address Port Base 00H Port 01 J1 Port C 02 Control Register Base 03H J2 Port A Base 04H J2 Port B Base 05H J2 Port C Base 06H J2 Control Re
37. ows an input device to re quest service from the CPU by simply strobing its data into the port INTE Controlled by bit set resel of PC4 INTEB Controlled by bit set resel of PCa 82C55A MODE 1 PORT AE Dy Dy Oy 0 Ds O Dy O 09002554 uu Te UT Ge QUTPUT MODE 1 PORT B 281256 13 Figure 8 MODE 1 input Figure 9 MODE 1 Strobad Input INTEL CORPORATION 1982 Appendix A 36 intel 82C55A Output Control Signa Definition Output Butter Full F F The output will go low to indicate that the CPU has written data out lo the specified port The OBF F F will be set the rising edge of the WR input and reset by Input being iow Acknowledge Input low on this input informs the 82 55 that the data from Port A or Port B has been accepted In essence response from the peripheral device Indicating thal it has received the data output by the CPU INTR interrupt Request A high on this output can be used to interrupt the CPU when an output device has accepted data transmitted by the CPU INTR is set when ACK is is one and INTE is a one It is reset by the falling edge of INTE Controlled by bit set reset af PCs INTE B Controlled by bit set reset of PC CONTROL WORD 0 Dy Dy D D De Dy D P 9090054 Pas ret Figure 10 MODE 1 Output Figure 11 MODE 1 Strobed Output
38. ports and two 4 bil ports Any port can be input or output Outputs are lalched Inputs are not latched 16 different Input Output configurations are pos sible in this Mode 231256 8 Appendix 32 intel 82C55A PORTC s Ls ouor _ gt oureur 2 meu OUTPUT 5 wur wer eur s OUTPUT mew s meur EN Ea L3 4 as INPUT INP OUTPUT INPUT OUTPUT N 1 7 INPUT INPUT 11 INPUT 1 INPUT 15 MODE 0 Configurations CONTROL WORD 0 CONTROL WORD 4 Os D Dy 0 D Dp Dp 06 Os Da D DI Oy BCE sso fe e CONTROL WORD 4 CONTROL WORD 3 Dr De Dy Os D Po Dy D Os D D D tee loys ll Bangggggu INTEL CORPORATION 1992 8 Appendix A 33 intel 82C55A MODE 0 Configurations Continued CONTROL WORD SE 0 De D Da Dy Dy 0 CONTROL WORD 4 Dr D Ps 0 D A mer a 4 CONTROL WORD Ds Ds D D D Plebe CONTROL NORD D Dy Dy D D D D 0 CONTROL WORD 10 Dy O Os D D D 5 CONTROL WORD 6 D De De Ds Dy Dy CONTROL WORD 11 D Ds 0 D D D Da CONTROL WORD 4 D D Dy Dy D 334 INTEL CORPORATION 1992 9 Appendix A 34 intel 82C55A MODE 0 Configurations Continued
39. r forced current situations Unplug the card from the bus and remove all cables Using an ordinary digital ohmmeter on the 2 000 ohm scale measure the resistance between power and ground Record this number Reverse the ohmmeter leads and measure the resistance again If the ratio of the resistances is 2 1 or greater fault conditions most likely have occurred A common cause is miswiring the power supply Improper power causes catastrophic failure f a card has had reverse polarity or high voltage applied replacing a failed component is not an adequate fix Other components probably have been partially damaged or a failure mechanism has been induced Therefore a failure will probably occur in the future For such cards Octagon highly recommends that these cards be replaced Other over voltage symptoms In over voltage situations the programmable logic devices EPROMs and CPU chips usually fail in this order The failed device may be hot to the touch It is usually the case that only one IC will be overheated at a time Power sequencing The major failure of 1 0 chips is caused by the external application of input voltage while the Micro PC power is off If you apply 5V to the input of a TTL chip with the power off nothing will happen Applying a 5V input toa CMOS card will cause the current to flow through the input and out the 5V power pin This current attempts to power up the card Most inputs are rated at 25 mA maximum When
40. r product Octagon s products are designed to be high in performance while consuming very little power In order to maintain this advantage CMOS circuitry is used CMOS chips have specific needs and some special requirements that the user must be aware of Read the following to help avoid damage to your card from the use of CMOS chips Using CMOS Circuitry 1 Using CMOS Circuitry in Industrial Control Industrial computers originally used LSTTL circuits Because many PC components are used in laptop computers 1C manufac turers are exclusively using CMOS technology Both TTL and CMOS have failure mechanisms but they are different This section describes some of the common failures which are common to all manufacturers of CM OS equipment However much of the information has been put in the context of the Micro PC Octagon has developed a reliable database of customer induced field failures The average MTBF of Micro PC cards exceeds 11 years yet there are failures Most failures have been identified as customer induced but there is a small percentage that cannot be identified As expected virtually all the failures occur when bringing up the first system On subsequent systems the failure rate drops dramatically Mm Approximately 20 of the returned cards are problem free These cards typically have the wrong jumper settings or the customer has problems with the software This causes frustration for the customer and incurs
41. rol based appli cations When Port C is being used as status control for Port A or B these bite can be set or reset by using the Bit Set Reset operation just as if they were data output ports Appendix A 30 intel 82C55A Interrupt Control Functions When the 82C55A is programmed to operate mode 1 or mode 2 control signals are provided that can bo used as Interrupt request inputs to the CPU The Interrupt request signals generated from port C be inhibited or enabled by setting or resetting the associated INTE flip flop using the bit set reset function of port This function allows the Programmer to disallow ar allow a specific 1 0 device to interrupt the CPU with out affecting any other device in the interrupt struc ture INTE flip flop definition BIT SET INTE is SET Interrupt enable BIT RESET INTE is RESET interrupt disable Figure 7 Bit Set Reset Format Note All Mask flip flops are automaticaliy reset during mode selection and device Reset INTEL CORPORATION 1992 6 Appendix A 31 intel 82C55A Operating Modes Moda 0 Basic Input Output This functional con figuration provides simple input and output opera lions for each of the three ports No handshaking is required dala is simply written to or read from a specified port MODE 0 BASIC INPUT MODE 0 BASIC OUTPUT INTEL CORPORATION 1992 Mode 0 Basic Functional Definitions Two 8 bit
42. this is exceeded the chip may be damaged Failure on power up Even when there is not enough current to destroy an input described above the chip may be destroyed when the power to the card is applied This is due to the fact that the input current biases the so that it acts as a forward biased diode on power up This type of failure is typical on serial interface chips Using CMOS Circuitry 3 Serial and parallel Customers sometimes connect the serial and printer devices to the Micro PC while the power is off This can cause the failure mentioned in the above section Failure upon power up Even if they are connected with the Micro PC on there can be another failure mechanism Some serial and printer devices do not share the same power AC grounding The leakage can cause the serial or parallel signals to be 20 40V above the Micro PC ground thus damaging the ports as they are plugged in This would not be a problem if the ground pin is connected first but there is no guarantee of this Damage to the printer port chip will cause the serial ports to fail as they share the same chip Hot insertion Plugging cards into the card cage with the power on will usually not cause a problem Octagon urges that you do not do this However the card may be dam aged if the right sequence of pins contacts as the card is pushed into the socket This usually damages bus driver chips and they may become hot when the power is applied This is
43. ts a control word ta the 82C55A The control word contains information such as mode bit set bit reset etc that initializes the func tional configuration of the B2C55A INTELCORPORATION 1992 Each of the Control blocks Group A and Group accepts commands from the Read Write Control Logic receives control words from the Internal data bus and issues the proper commanda to its as sociated ports Control Group A A and upper C7 C4 Control Group Port B and Port C lower C3 C0 The control word register can be both writlen and read as shown in the address decode table in the pin descriptions Figure 6 shows the control word format for both Read and Write operations When the control word is read bit D7 will aways be a logic 1 as this implies control word mode information Ports A B and C The 82 55 contains three 8 bit ports A B and C All can be configured in a wide variety of functional characteristics by the system softwere but each has its own special features or personality to further enhance the power and flexibility of the 82C55A Port A One 8 bit data output latch buffer and one 8 bit input latch buffer Both pull up and down bus hold devices are present on Port A Port B One B bit data input output latch buffer Only pull up bus hold devices are present on Port B Port One 8 bit data output latch bulfer and one 8 bit data input
44. ut made WA 36 WRITE CONTROL This input is low during CPU write operations PA7 4 37 40 MO PORT A PINS 4 7 Upper nibble ol an 8 bit data output latch buffer and an 8 bit data input latch NC No Canneci 9 INTEL CORPORATION 1992 2 Appendix A 27 intel 82C55A 82C55A FUNCTIONAL DESCRIPTION General The 82C55A is a programmable peripheral interface device designed for use in Intel microcomputer sys tems lis function is that of a general purpose I O component to interface peripheral equipment to the microcomputer system bus The functional configu ration of the 82C55A is programmed by the system software so that normally no external logic is neces sary to interface peripheral devices or structures Data Bus Buffer This 3 state bidirectional 8 bit buffer is used to Inter face the 82C55A to the system data bus Data is transmitted or received by the butter upon execution of or output instructions by the CPU Control words and status information are also transferred through the data bus buffer Read Write and Control Logic The function of this block is to manage all of the internal and external transfers of both Data and Control or Status words it accepts inputs from the CPU Address and Control busses and in turn issues commands to both of the Control Groups Group A and Group B Controls The functional configuration of each port is pro grammed by the systems software In essence the CPU outpu
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