Goldstar FC200 service manual
Contents
1. appo ALTE ae Um IC REGULATOR STR 9005 IC REGULATOR 51 51223 IC REGULATOR L 7912 DIODE PRIDGE 6 401 DIOD amp BRIDGE DBA 208 DIODE RECTIFIER 144001 4700MF 160 4 100MF 16 4 100MF 25l 04 1000MF 259 04 470MF 259 4 CARBON FILM 4 27 1 1 4W WIRE COPPER TIN COATED COMM AY POWER TO MAIN FC 200 COMM AY REMOTE FC 200 FUSE 250 20 ere ee ee ee ee ee ee ge em wy mink ee i et idtm i Rm MEE am urs Peral ici muni Miri C CT tO Ji US USA 21 34 44 Was 3 32 40 36 3 J35 42 01052 41 22 RELAY D2 CPU 2 80 ZILOG 6 5 8910 G I ROM2. mi 24 mom omo ch ome oco m 42 VALID ONLY PORT B BIT 6 IS L x2 VALID ONLY WHILE 8 81 6 1 H 53 SET FF NOT USED AS AN OUTPUT OPEN CLLECTOR OUTPUT OTHER PINS ON J2 14 J3 5 474 5 0 43 9 344 9 GND iS not supplied in the minimum configuration EXPANSION MSX BASIC 7 inous area memory ron WIFI to Ehe lower mnemotty area txpausi un should be Located just under Che existing Lo make continuous available lo BASIC When Cte memory system configuration contains Hk RAM from 1000 1111 memory must stilt be incremented LOK as the SLOT SELECT SIGNAL works on a 16k unit basis lh this case the originali Bk of HAM are not used and the expansion of results iu a total of 16k memory nol 24k There are two Kinds Of 16k RAM cartridges available Oone s for the Bk RAM minimum system and the other for those machine which comes with 16k RAM While both cartridges contain i6k of RAM they must not be confused with one another and care must be Laken that they are installed properly Computers with RAM to start with use RAM from FFFF to 00 0 Computers with 16k RAM to start with use 16k RAM Expansion C
3. FUNCTION SOF TOR rial sLOV TD FOR ADDO 7ELT ib Fk Bono BENE SLOT SLOT 1D FOR FFFF KEYBOARD RETURN E P CASSETTE MOTOR ON L ON CASSETTE WRITE SIGNAL DRIVES CAPS INDICATER ONE BIT OUTPUT FOR EXTRA 4 4 PSG O BEC ASSIGNMENT PORT BET JO JOYSTICK DI JA 1 u 1 oa BACK JA os BACKZ Y 1 1 12 3 J3 A RIGHT 4 x2 RIGHT2 4 6 x TRGAI JAG 012 ommo eee ees i i ic oe len ca P y I db 5 37 TRGBL OJA 7 TROB2 Si ni mm 6 KEY MATRIX SELECTOR AAA AM RR Ee a 7 1 CSAR CASSETTE READ SIGNAL p m 11 kS 2 2 5 23 S2 G u a unc moo c omo ax 44 p T om oe om mm e SS 5 E HED CE 2 5 2E oto PORT A INPUT SELECT
4. 14 rarattet tine of PORT A is connected to 8 10 2 ENCODER 27 85155 and CSDL 514 CSOH 014 15 selected 8 310 2 ENCODER 74151539 This stanalt is wired to dual 2 10 4 DECODER 2405153 In DECODER ly 0 neaatived sjanal 5 active SLOT 18 selected Therefore the content of OOOOH address in system COM is read b the CPU 6 4 UYDEO DISPLAY PPOCESSOR THS93129WML SPECIFICATION UDP IS DESIGHED INTERFACE DIRECTLY WITH THE TMg4415 15 16k 4BIT D RAM IT IS H CHh HMHEL MOS LSI DEVICE USED IM UIDEO SYSTEMS WHERE DATA DISPLAY OM RASTER SCAHHED HOME COLOR T U OR COLOR MONITOR IS DESIRED THIS DEVICE GENERATES ALL NECESSARY VIDEO COHTROL AND SYHCHROHIZATION SIGNALS AND ALGO CONTROLS THE STORAGE RETRIEVAL AND REFRESH OF DISPLAY DATA IN THE DYNAMIC SCREEH REFRESH MEMORY 3122 HAS A 625 LINE FORMAT FOR USE WITH THE EUROPEAN PAL SYSTEM AMD OPERATES ONLY IN A MODE THE HAS FOUR VIDEO DISPLAY MODE TEXT MODE GRAPHIC ONE MODE GRAPHIC TWO MODE MULTICOLOR MODE RESOLUTION PATTERI PATTERH coLog SPRITE DISPLAY SIZE HO 8 8 2555 16 I24LINE DOT 2 COL 1924256 8 8 768 16 24 LINE PIXEL DOT 32 COL MULTICOLOR 48 64 44 15 24 LINE BLOCK 2 COL 192 256 256 16 HO 24 LINE PIXEL 40 COL GRAPHIC 1 1 24256 PIXEL BRAPHIT 2 f 7 f RAM ROM DATA BUS RGB ENCODER MATRIX VIDEO RGB MONITOR MONITOR
5. 2 SL Inm Ee 3 z 11223122 DOD i m 1 T oo EEE E 1816 ur um ret 5 rt nn 2220 5 owas sooo Mn NOH 482530 ON 1Uvd 21 7 um n 3 vl EN 818151 2330 81010 TWNOISNAWIG oag 8 329012 Td ed Ld Peek h ma wa 55 244 am Gr Vv 2 wy civ edes ign an vn LN ov Gv TV gv 29 OW LW ev 3 zy ev Qx rogy WH pY LY 5 t 16 ON 16 SI 5102 B 02614621 wi 91312385 351 8 3810 55 T 29 OD 270 org 03 033 10 awas B Sr ocu Ch WAY AIMINVDO 6 mae W 65 2406 0075 i PORU TUY 1 ura Ou NOLL 9109530 80103 317 t 7 8 i A 07 917 MEE DASH 13533 t t 1 7 SE em d lt 59 ho RS2
6. 9 S 300H ov t 5 0 4 1 2 3 A 6 t da 1 1 g 2 5 a 4 592 994 eda 1 4 T 3 NEN T m c ono 5 0 V ON 0 G E el E 1 at r 4 331345 359 940 7 z AL V QI Odd Lo 11145 dite ru 5 JDISPIOD R UT p db n cafe or fo ttu mam TT eee oaz pb rz fabu da uil Wis n 111 2 ote Ot 40 01 2 HSINI4 80102 ALLLNWAQ 3 8 1 3 011414 25 30 ON ON 3 01 lt x it Of Op X115 gt N uL Insti 32v43alN n veisaudlea r 22 3 HSINI 3 40102 1 3
7. to its A Port proper commands Control Group Control Group B Port Word Of The Control Regist read operation the c Ports A B and The 255A contains 011 i fo DATA BUS 3 STATE input clears the the H255A Thoe de bit set three 5 CONDIT ON the input mode trols essence the CPU bit ctional blocksCGroup A dnd Group ernal data bus and associated ports input thie significant control reset configuration of signals ba registers T bits configuration of each port is programmed outuputs control word contains issues the and Port C uppertC7 Ca B and Port C lower C3 Co er can only be writtleen ongtol bit port sCA n word register 15 and C ALL set bout Tor of register ete the 82554 accepts into No allowed con of ho and by all D 1 6 1 11113111 1 teristics by the syslog soltware but each bhas its own special Peatupres of personalitv to the power and tlexibiltity of the Port A One B bit data output lateh buffer and S8 bDit data input Port B One S hil data input eutput latch buffer and one S bit data input buffer Port C One data output latch buffer and one 8 bit data input buffer ino latch for input This port cad be divided into tw
8. z TEER AM 59120 5011088888000006 0 5 EE EEE be 3000 0 gt PRINTER INTERFACE STANDARD 1 parallel LEVEL TTL CONNECTOR 14 PIN SIGNAL TABLE TERMINAL NOISIGNAL PMN CONNECTION 7 4 PDD2 7654321 7000 6 PDB amp 08 8 PDB6 14 13 121110 9 8 9 PDB7 10 NC i 11 BUSY pin arrangement toward the system i 12 NC 13 NC Cis GND 2 10 THE LIST OF CONNECTOR TERMINAL NAME SPEC STANDARD i VIDEO OUTPUT COMPOSITE SIGNAL RCA 2 PIN CONNECTOR RF SIGNAL 2 PIN CONNECTOR CASSETTE 21 DIN 8 PIN CONNECTOR GENERAL 1 0 PORT h AMP 9 PIN CONNECTOR PRINTER AMPHENOL 14 PIN CONNECTOR CARTRIDGE BUS 2 54 PITCH 50 PIN CONNECTOR AUDIO OUTPUT 2 3 1 BLOCK DIAGRAM CPU 2 80 COMPA TABLES KEY BOARD CASSETTE o 8255 INTERFACE CMTIN _ REM CMTOUT 9129 16 VIDEO OUTPUT 4 RF OUTPUT ROM 32KB RAM 64KB PRINTER 9 INTERFACE PRINTER CONNECTOR AY 3 8910 AUDIO OUTPUT JOYSTICK ROM PACK EXPASION CONNECTOR CONNECTOR 50 PIN 50 pin FOR ROM CARTRIOGE LIGHT PEN E LIGHT PEN 5 2 CARTRIDGE SI
9. BLOCK DIAGRAM OF 9 ADDRESS BUS CPU VDP 16 CONTROL INT VDP 4 9129 VIDEO ENCODER MOD D P interr urt The VDP interrurt autrut rin is used to senerate Interrupt at the end of each actitte di srlayv scan which is about every 1750 second far the 129 The interrurt output is active when the Interrurt Enable in the UDP reetster 1 ts a Ii and the F bit of the status resister a i Interrupts are cleared when the status realster is read amp CpPli upmp IHHTERFEnCE The VDP communicates with the CPL via an g bit bidlrectlanal data bus Three control tines decoded from the CPU address and enable Lines determines interpretation of the bus Thrauah the bus CPU can write to U RAM read from write to VDP resisters and read the DP status reaister The VDP also generates interrupt sianat after every refresh of the TU disrlar If the interrurt is enabted FUDP UpnhH INTERFACE The VDP can use either Th i 54116 15 16k 1 ar 1154416 152 20 16k44 dynamic RAMs ADO Is used for the eishth address bit in the 1 54416 15 20 RAMs but not for the 17154115 Since the early write cycle is used br the UDP G an the TH24416 must be tled to ground The UD accesses ur to 16 584kb te of PNM usina a 14 61 address The MDP fetches data from the VRAM In order to Process the video Image T
10. M ROM BASIC D RAM HM4864 2DC 64 1 DECODER 24 15 DECODER 74151559 DECODER 7445138 D F F 741 324 OR 744532 AND 748 INVERT 74HCU04P OPEN COLL 741 309 D F F 7419374 HYBRID RELAY 031 0654 DIODE SWITCHING 144149 CERAMIC 5 ELECTRO CAP 4 7MF 164 CERAMIC 0 1 R ARRAY LOKed 174W RS 12 15 RESISTOR LOK J 1 41 R13 47 48 RESISTOR LOK J 1 4W 2 18 RESISTOR 2 2K J 1 4W 13 16 RESISTER 10 7 1 44 Pei RES STOR 10 7 1 4w P42 R44 RESISTOR 470 7 1 4W P11 RESISTOR 120 J 1 4W PCB COMM COMM 50 920 050 059 PRT COMM CONN 14 57L 40140 770B KBD COMM COMM 11 MLX 5267 1160 PWR COMM CONN 4P PLY 5289 046 JACK RCA 1P 5 1558 R45 RESISTOR 8 26 7 1 4W U2 UDP 9121 PAL UDP 4 1 182556 INTEL D RAM TMS4416 15 T I U26 33 48 24917 249 QUAD MJX 5157 U2 DUAL MPN 7415153 2 31 HEX BUFFER 74L5367 43 HEX BUFFER 37 WAS NOR 74202 3 MAND 0 U47 50 INVERT 74204 U28 2 0 4559 MEC U24 QUAD BUFFER 74LS125 C53 TRIMMER CAP 66 01 03 TR 11 Di DIODE ZENER GIBS 1 B T56 CERAMIC 470PF SOY C58 ELECTRO CAP 220MF 161 5 0 59 ARRAY 2 2K 10 1 4 R2S5 R40 ARRAY 10 8 124 R4 10 RESISTOR 4 7K 2J 174W RESISTOR 220 J 1 4 R14 PESISTER 6 2K J 174W F20 RESISTOR 5 PK J 1244 RS RESISTOR
11. a H end mamme mmm aum uma cu UR 1 MEMORY Tho following diagram fs the memory _ C000 A000 48000 8000 32K8 4000 SYSTEM ROM MSX BASIC 0000 0000 CPU SLOT 40 SLOT 1 SLOT 2 SLOT 3 MEMORY SYSTEM CARTRIDGE RAM EXPANSIN SLOT SLOT SLOT SLOT DU CO 110 AG AG 48 90 G0 00 DEV ECL ADRS ao n ee mm ee ee MM ac ee ee PRINTER RS 232C 1198 81199 RIAU SALA I 18 amp H91 eee c sn iw IR IW COMMAND ADDRESS SET IR STATUS READ mi i re en 77 umor ada VRAM DATA WRITE DATA READ ADDRESS LATCH DATA WRITE iR DATA READ DATA WRITE READ PORT B DATA WRITE read PORT C DATA WRITE READ MODE SET iw STROBE OUTPUT bO IR STATUS 1 0 1 DATA LINDEX i9129 3 8910 BUSY 1 LATCH OUT BET ASS EGONMENT 4 PPI ESIH z Za h fF oe uk CASON CASW TCAPS _ SOUND lt M m ee
12. vs as LE lt lt oz 60 La amp O Gg 5 3 Gr 5 PLE S E TL 9 9 v A FTE TE 1 9109115 ON W205 Ef 3180802 5009 1452 Ev Loc 27 Tos ww t z B 5 3 10 IDASPK gt 9 0 IRONY Er Tete srol wer 1 Er vt 10 6 0 0 06 16 01 8 Z iios mm WHMIS PELLO Tui 069 XiMLVA OB 905 24 992530 oy r el md 43 16 OM 18 4 uos r Fi H ne ut 3 5 Lil v E ias PSMA dea 1 ES m JO3SDIODU T UT BSS o l 200382 AST 5207 ex 2 LU aT ee T 77240 2 6 2 2 OR Md LM zn m p RR lI 1 6 40102
13. 3 3 NOI 2530 ON 1i4 JN 2 et 4 8 ASEN MD 5 q een je 7 409 NM a OL 219 45 LL LEO ser Lya FE AG ovala f 3 ENG AM 7 N i 109116 ON 42015 B 029 62 Ev 5 JDJSPIOD E 03423H2 C i 7 5 lu CC 2 d H v NMWHG an _ Siano Ceg 2025 3 01 TYNOISNWIO enl sapan gt CLTS 0 1075 1772 Lu LH OC 2 0 22 i 263 0009 WOLINOW 79 do f oO 23 vany w 0301 3 3 HE me 19 33000N3 Av 0 bare 31 203009 3 79 H 3 1 Z 5 5 pani t z abet Ma TLE ada AAA Ton ALA Ae Ore 4t z 050 i 1 I LOL Len 4 3 1 TU 0 T gen T T orn 2 Lot 853 83 Cle 4 een 56 6 o 6 5 T Gs M gen M 144 60 M 01 ttn on AA
14. 5 IK J 124 PS0 RESISTOR 226 7 1 44 R49 RESISTOR 550 7 1 4 EXP CONN CONN SOP 6201 050 258 1 2 COMM 22 5045 024 KBD CONN CONN 12 MLM 5262 1258 JOY COMM COMM SP SUB D TYPE SOCKET DIN TCS 4480 01 1 EMI FILTER 1 2 MOM anb un Hu m Miis rm imr sur ipm ana em PR mim m 2 iD Lyme PD Cro k po hd Ld Cad Legg ur 16 Te Pe De a 55 TU i C uineis ey Uo P AB Mord E O LCL bo i I DA 3 gt d in G 1 3h 5 uv ut JD fi Lb CV ivi tv gt rid T5V gt 2 15V lt Q 0 RE j 15 ns 35 j c PA 4150 w d ONIS i5 9 ty 9 35156 Y 3 IN UN FE Gals 3o 10 89 PS 4 0 17 27 REMARK COLOR FINISH FC 200 CIRCUITS 1 MATERIAL
15. A low on this input pin enables the CPU to write data or control words into the 8255 CAO Port select a and port junct bon with the RD and one of the three are normally connected t tus cAQ AT 8255A BASIC OPERATION on al mL Al AO 10 INPUT or 0 1 1 T 0 1 o I do lilo 1 POR 7 DORT B PORT C i TOUTE OPERATION WRITE 0011 10 HUS PORT A i TT TO TO TOATA 1 O 1 O io 1 1 li 10 d IDISABLH poris DATA BUS PORT B MS DATA BIS CONTROL x x Ix x 1 DATA daus 3 STATE 1 WR i nputs contrioal the control word o dite beast ay RAT TON CRE AD ee BUS RMS 00 rt eee 6 0 DA BUS DATA umr PORT C MM FNCTION 1 1 10 1 10 ILLEGAL RESET Reset A high on this gre sot ta coil ports A B C Group A and Group The functional the systems software In a control word to information such as mo that initialize the fun Fach of th Control commands from the int
16. DESCRIPTION APPROVED PART NO KA Goldstar A3 297 11 VY apak pe peers 1 3 24 D js pu 0 2 a ta En zu Elo hs Lise 2 w n e 2 elzisic HE z z 21225 e je 3 5 11 21 joie 212 5 2 elg X 143 Stock No 91180143 5 420 SASH 49109116 ON 019 5 0 62 tv F s 3 1 2345 10 533280 SDISPIOD e ESI 8187 c GS M i if 5 a 0 1 NN ANE 3 3 i 1 9 E CMM j 4 IZ SLA 002 241 LNA 308 j curs 303 CET NEC SES v1 TC 01 310 HSINI4 80109 5 0 ee e a On 31 1 E 109116 ON 42615 3 Ob 762 tv 1 5 j 2 d 2 9 131554 12345 3510 80110 5 JD31SPIOD wt um 5 7U ur mob j 5 AXONSW 3 Pd ace t 3
17. SLOT H34 DDRESS 4000 2 should write a datatACHEX ta the PORT A resister in eel ee ee ee eee GRE ARR ee ici ree ici a Ss So m em mart aum ricum ee dd Mum nem ium dt M P n MEN Rui ee If vou input AChex data to PORT of chir e755 it allows access of MSM BASIC INTERPRETER in SLOT Internat D RAM in SLOT H2 and external cartridge POM in SLOT 3 for evamrle assembly OUT POREN is inserted 6 5 POWER OF RESET Qs vou turn on the raver switch PROGRA COULTER s Content 5 set tn OOOOH This realster s content set to the system ROM the address 15 and PORT h in is set
18. oO 23 vany w 0301 3 3 HE me 19 33000N3 Av 0 bare 31 203009 3 79 H 3 1 Z 5 5 pani t z 3015 18 380 3 OT 191 TD pr y f V yD 2 Rt z 6 1 8 2 z L AA HELM 3 2 3 Gold Star MSX 611 1348
19. 20 120 170 1 0 I O I O 0 CARTRIDGE BUS SIGHAL FUNCTION 0 9 E lo HO HAME CONTENTS 1 ITS GE RGM 4000H 7FFFH ADDR SELECTION SIGHAL 2 i82 QU ROM amp 800DH BFFFi4 ADDR SELECTION SIGNAL 512 HY ROM 4000H BFFFH ADDR SELECTION SIGNAL 4 SLISL ch SLOT SELECTION SIGHAL EACH SLOT 5 Reserved S RFSH CMD REFRESH CYCLE SIGNAL 7 WATT ND WAIT REGUEST SIGHAL TO CPU 8 THT INTERRUPT REQUEST SIGHAL CPU 11 4 MACHINE LANGUAGE FETCH CYCLE 10 BUSDIR DATA BUS DIRECTION SIGNAL 11 IORG HD INPUT OUTPUT REQUEST SIGHAL 12 MERG CD MEMORY REGUEST SIGNAL 13 WR CD WRITE CYCLE SIGNAL 14 RD READ CYCLE SIGMAL 15 RESET CPU RESET SIGMAL 16 COMP VIDEO COMPOSITE VIDEO SIGHAL 17 32 0 15 ADDRESS BUS SIGNAL 55 40 100 77 DATA BUS SIGNAL 41 435 1 GND SIGHAL GROUND 42 CLOCK CPU CLOCK 5 S8MHz 44 46 541 SWZ FOR SYSTEM PROTECTION amp AUTO RESET 45 47 50 50 POWER 48 21 24 120 POWER 43 SUMBIM EXTERNAL SOUND Sdbm 50 2 0 12U POWER umm M ile
20. 31 yl hls 93423HJ 1290 orgena aah SS 41592530 ON SR m Om cm a Aus GN WOES EFI Try 9 1 ions JO3SDIOD A ft lt a 0 0 D 1 0 A 229212 2 8 I gt gt gt 1 n Teens 00 20016114 51440011 wi EY RE 111 HYH 3101 1 0151 1 ESIMHY TLO SS 3101 CN 1 N 58 lt aw Ser 4 Biz 9 e oc e 27 v 5 Z Gun 42015 EPL 23029152 Ev L 27 35 3010 5 ND 7 3 A 0304 scri m i 00 2174 ME 1 E m Win gt a vc d t sd i pen m up ou ti we 0 1 ON 141 2530 ON 4 43101 TYNOISN WI M 3 HE 4 1 22 Gent oh 266 122 4v 5 Ai 05 EMEN sa
21. A 1 SEN Cl 3 7 ik 11015 1015 hat 4 14 1 0 4 5 dk 14 CS sr 3014 TN os a4 j 7 174 a4 4 12 t 2 A 1 1 id UT mM 3 T Low n oon a0 a EC l Cue CA ocn 7 gn Ha _ 13 ELLA s t L TC Bin Si 4 i o SiL St T T a3 gun vein M 5 5 J 1 T 53 i GSO i T n 1 T L 523 501 in K Tull T sn T AANT pri e YYY Sra t 33 x i eo a T 2 t i TT 9 oe 23 4 T AZI C3 24 422 6 4 7 Lo Zn MXJCOON3 oa QN 2 109116 ON 42015 B 029 62 Ev 5 JDJSPIOD E 03423H2 C i 7 5 lu CC 2 d H v NMWHG an _ Siano Ceg 2025 3 01 TYNOISNWIO enl sapan gt CLTS 0 1075 1772 Lu LH OC 2 0 22 i 263 0009 WOLINOW 79 do f
22. GNAL ee MEL inem Gba je Homer Weg e nm r toe SEF ee iHe gt m r Die acm gt wey UT Od IER inque numb aam ee ee Ems ues egy EP dn md Fy s ty ARAM HR um ee ee el CS Lari 25124143 Reserved 41 WATT 42 P11 thd LORG Ch WR OH AD ALL Als 14 1 AS AS SUNDIN I OO I O T70 Reserved means that 9 collector state this Pin is prohibited tg C het 524 LTEL NO RF EH 14 IRIT tH BUSDIR CD A FD 7 COMP VIDEO 15 A1 AS Ag ALS AD AZ A DO Dz D4 DE CLOCK 1 2 1
23. Goldstar FC200 service manual CHAPTER CHAPTER CHAPTER CHAPTER CHAPTER Scanned and converted to PDF by HansO 2001 NDEX 1 HARDWARE CONFIGURATION 2 BASIC FUNCTION SPECIFICATION CARTRIDGE 4 ADDRESS MAP 5 CONCEPTION OF THE SLOT 6 EXPLANATION OF MAIN CIRCUIT 7 S8 8 PARTS LOCATION 14 18 23 28 41 53 1 General Specification CEI Z SOA Equivalence MEMORY ROM 42KBCMSX BASIC RAM CRT DISPLAY TEXT MODE amp Ochr 241ine GRAPHIC MODE 256 192dots COLOR ibcolor CMT FSK METHOD 2200 2400 baud rate SOUND FUNCTION 8 octave 3 tones output KEYBOARD Alphanumeric graphic symbol code symbols FLOPPY DISK 5 amp supporting MSX DOS formatting 34 t PRINTER 8 bit paralleitCentronics ROM Cartridge 1 0 bus Game cartridge expansion bus cartridge Joystick ior 2 2 SYSTEM COMFIGURAT TON MINIMUM SOUND OUTPUT VIDEO OUTPUT CARTRIDGE SLOT JOYSTICK 2804 32KB PSG RAM 64KB VDP KEYBOARD CASSETTE SOFTWARE SUPPORT AREA VIDEO OUTPUT CARTRIDGE SLOT EXPANSION CARTRIDGE PRINTER OUTPUT ROM 32KB JOYSTICK 64KB 2 PPI KEYBOARD xThe number of the slot is maxinum 16 containing system 1 SUEC 19 CPU ZBHOA CLOCK 8 57 9940474 1 WAIT SIGNAL 1 inserted after each Mi e
24. RA ODN UE RT ACE 4119 GENERAR The 82554 is a peripheral inbkertfaececppltodevice esd peg For usein oF SUSI OMS LS Funcion s that o general purpose TSO component to interface peripheral euulpment themicrocomputer bus The functional configuration of the 8255 is programmed by the system software so that normally no external logic is necessarv to interface peripheral devices or structures DATA BUS BUFFER This 3 state bidirectional S8 bit is used to interface the 32554 to tho Svsteum data bus Dato is transmitted or received by the bufrer upon execution of input or output instructions bv the CPU Control words and status infor mation are also transterred through the data bus buffer Read Write and Control logic The function of this block is to manage all of th internal and external transfers of both data and contro or status words It accepts inputs from the CPU Address and cont rol busses in turn issues commands to both of the control groups CS Chip select A low on this input pin enables the communi cation between the 3255 and the CPU ORD PEAD A low on this input pin enables the 2554 to send the data or statusinformation to the CPU on the data bus In essence it allows the CPu to read from the B2554 WR NRITE
25. SLOT WHAT 18 SLOT phe word slot 15 used with a special meaning tt does uot refer to the cartridge connector slot familiar to Apple 2 users Slot here is somewhat similar to blank it is a block of 6 k of memory It is also similar to hard wore slot because the CPU names each slot and telects a slot ou the cartridge bus is called the Slot Select Signal Note that we are discussing the slot fram the of view of software and the number of physical cartridge slots will bo discussed in another section 7415139 8255 7415153 OD SUTSLo CSOL 2 CSIL 0 7 _ 13 102 PAS SE __tace PAS 103 PAT 203 2Y D 517512 D 50913 CS3H e L B255 _ Chip Select RFSH 2 4 EXPANSION SEO CIRCUIT EXAMEN JE CARTRIDGE SLOT EXPANSION ROX TO EACH EXPANSION SLOT B SDIR DATA BUS 0 0 88 ADDRESS BUS DECODER CIRCUIT O 1 0 CARTRIDGE EXPANSION SLOT SLOT SELECT WHY EHE SI OTS On a system with an ordinary 1 memory seup every device receives Lhe same select signals This makes it impossible to put two or more devices au the same operation or even unies it Using slots makes it possible ta put several edvices in the game address Dut in dif ercel slots C stso makes i
26. artridges with RAM Frou to 8000 BASIC OCCUPIES THE RAM from 8000 to FFF and cannot use RAM from 0000 to 5 2 ILOT EXPANSION The four slots which come with rhe minimum system called the BASIC SLOTS and from each of these BASIC SLOTS other siots can be added to expand the System TO select an expanded slot the BASIC SLOT to which is belong must First be selected this is not necessary in systems iu which Chere is a Function which can inhibit the BASIC SLOT Up to four stots be connected to each BASIC SLOT without using a buffer five or more slots can be connected using the buffer For the cartridge bus Siuce the CPU cannot distinguish whether a cartridge Es before or after the butter a circuit which accepts a signal from tte cartridge to distiuguish the derection of fhe buffer is installed The signal from the cartridge is called BUSDIR In some cases however this signal is not necessary and the circuit can pe simplified using Fn cases this 1 gat necessary Che eaviridge cipeuit be simplified using RC A cart idge which aceepts 11 Hever sends dita 1 IN this case buftep aiways waks outward and never inward 29 A tremors eartridge in this case the bus dorection cau be distinguished from the signals availablecSiot Select Memory Request Read Write Thus ROM cartridges can be made inexpeustvelv d
27. ctive Lou the outruts B bits on 000 2747 to the CSW and CSR should never be simultaneously Low at the same time If beth are tow the YDP outputs data on 00 007 and Latches invalid data Mode determines the source or destination of 8 read or data transfer Made is normally tled ta a CPU Low address AO AC PU UDP DATA TRANSFERS mami UNA um HAC DATA BIT OPERATION 0 1 2 5 4 5 6 SW CSR MODE WRITE TO DP PEG BYTE 1 DATA WRITE pa Di 02 05 D4 BS 06 0 1 BYTE 2 PEG SELECT 1 0 0 0 0 PSO RSL 0 1 WRITE TO UPAM BYTE 1 ADDF SETUP ne as AS ALO All 612 0 1 1 BYTE 2 ADDR SETUP 0 1 Al A2 0 1 1 BYTE 3 DATA WRITE pi D2 05 D4 DS neo 0 1 0 PEAD FROM 5 PEG BYTE 1 DATA READ D0 Di D2 DS D4 DS D6 1 0 1 PEAD LBOM BYTE 1 ADDR SETUP A7 AB AD A10 11 4812 0 1 1 BYTE 2 ADDR SETUP 0 1 AQ Al n2 424 0 1 1 BYTE 5 DATA READ DO Di D2 D3 DS D6 1 0 g icum od muss uerum do mois wee m m OY A iniu GN Rr et duin nur i E PERRETE
28. erence for the TONE NOISE and ENVELOPE GENERATORS BDIR BC2 BC1 Cinput Bus Direction Bus control 2 1 BDIRIBC2 BCi PSG FUNCTION 2 0 1 O INACTIVE 2 011111 READ FROM PSG 1 1 0 WRITE TO PSG 12111111 LATCH ADDRESS 7 ANALOG CHANNEL A B CCoutput Each of these signals is the output of its corresponding D A converter and complex sound waveshape generated by the PSG 10A7 10AOcinput output IOB7 IOBO CInput ont put Puput Output A7 AO BF BO Lach of these two parailel input output ports provides bits of paral data to from tbe PSG CPU bus from to devices to the OM 1 pius Each pin is provided whith an on chip pulJ up resistor so that when in the input mode all pins will read normally high Therefore the recommended method for scan ning external switches would be to ground the input bit ilum amp ee nn GNE te le hp C CT NO pamm UNA n mam UM Rog mu Ce C3 C4 7 R1 31 24 1 F1 200 POWER 1 151444 en 5 pe apos mam LLL qd HU aueh He
29. he also stores data In ar read out data from the YRAN durins a CPU URAM data transfer The UDP automaticatty refreshes the THE VDP URAM INTERFACE CONSISTS OF A BIDIRECTIONAL S BIT DATA BUS AHD THREE CONTROL LINES EAS CAS RAW THE VDP READS FROM AND WRITES DATA TO THE V RAaM ON THE RAM DATA BUS THE VDE OUTPUTS THE ADDRESS TO THE VRAM OF THE ADDRESS BUS THE UPAH LOW ADDRESS IS OUTRIUT WHE Pas IS ACTIVE LOW THE COLUM ADDRESS 15 OUTPUT WHER CAS IS ACTIVE LOW DATA IS OUTPUT TO THE WPAM WHEN P W IS ACTIVE CLOW CPU CLOCK GENERATION 33 The senerates CPU clock 3 SertHz fundamental freauencyr raraliel mode TAL is used as the freauency reference for the internal clock osciltatatr which is the master time base for all system orerations This master clock 15 divided by twa to generate the pixel clock 5 SMHz and br three to provide the CPUCLK CS 598127 INTERFACE The UDP Interface to the CPU usina an bit bidirectional data bus three control Lines and an Interrurt lowrite data brtes to VRAM 2 yead data bytes from SRAM S write to one af the S UDP write ontz resisters 4 read the VDP status register The tyre and direction of data transfers are control by the CSW CSR and mode Inputs SW the CPU to VDP write select When it is acti verlos2 the bits on 600 07 are strobed inta the DPF SR is the CPU from read select When it is a
30. o 4 bit ports under the mod control Each 4 bit port contains a 4 bit latch and it can be used for the contro signal outputs and status sianal inputs in conjunction with ports A and B 82554 OPERATIONAL DESCRIPTION MODE SELECTION There are three basic modes of operation that cab be sele cted by the system software Mode O Basic Input Output Mode 1 Strobed Input Output Mode 2 Bi Directional bus When the reset input goes high all ports will be set to the input mode i e all 24 lines will be in the high im pedence state After the reset is removed the 8255 can remain in the input mode with no additional initialization required During the execution of the system program any of the other modes may be selected using a single output instruc tion This allows a single 8255A to service a variety of peripheral devices with asimple software maintenance routine The modes for Port A and Port B can be separately defined while Port C is divided into two portions as required by the Port 4 and Port B definitions All of the output registers in cluding the status flip flops will be reset whenever the mode is changed Modes nay be combined so that their functional derinitton can be tailored to almost any I O Structure For instance Group B can be programmed in Mode 0 to monitor simple switch closings or display compu tational results Group could be programmed in mode i to monitor a kevbouid reader on 71 inter
31. rupt cp iven pasis The mode definitions and possi bile comubinatious may seem confusing at tirst but after review of the complete device operation a simple 1 0 ap proach will surface design of the 2955A kas taken into account things such efficient pc and complete functional flexibility to support almos peripheral device with no external logic Such design represents the maximum use of the available pins E pSGOPpogqammable Sound Generators x EATURES software control of sound gener stile TACOS to most 8 bit microppocessors independent lv Programmed Analog Output B bit General purpose 1 0 Ports xSinglie 5 volt supply Data Address 7 0 These 8 lines comprise the 8 bit bidirectional bus used bv the microprocessor to send both data and addresses to the PSG and to receive data from the PSG IN the data mode DA7 DAO correspond to Register Array bits B7 BO In the address mode DA3 DAO select the register number 0 17 and a DA7 DA4 in conjunction with address inputs A9 and for the high order address chip select RESET input initialization power on purposes applying a logic O Cground to the RESET pin will reset ail registers to O The reset pin is provided with an on chip pull up resistor CLOCK input This TTL compatible input supplies the timing ref
32. t possitle Lo pul programs in the same atea AS result the slot makes for a more Flexible environment and adds more expandability to the syst eu cxx EXPANSION CARTRIDGE SELECT SIGNAL CIRCUIT ei ACCESS OF ADRSO MREO RD SLTSEL 00 ACCESS OF ADRS MREQ WR SUTSET DATA BUS Riser ZZ MREQ m m eee os in or RESI CACCESS OF ADRS 1 CEV SLOT CIRCUIT Cpirz2 BO0r p clock 16 derived from the video disrlay rrocessor 11 Usina the GS425C1815 in main reset circuit turnina the rower switch on made nesative pulse set CPU and other rrocessor resetted system has four stats b the SLOT SELECTION method Each slot consists of BFR SLOT BASIC IHMTERPPETER ROM VERSION S2KB SLOT Hl lt EXTERHAL CARTRIDGE SLOT SLOT H2 MSX SYSTEM INTERNAL D RAN BAKE tSLOT HS lt EXTERNAL EMPAMSICH SLOT the evransion and cartridge stot slanals S0 rins CPU address and control sianals are connected thraush the HEX BUFFER 74LS3674 4 but not the DATA BUSOD D 6 2 SLOT SELECTION CIRCUIT Slot selection get through PORT of the P P I INTEL 2255A b the DATA BUSDO0 D7 The PORT A in the LSI ts wired to 8 10 2 ENCODER 74151535 b the BG bit raraltet Line SLOT SELECTION 15 derendins on the content of PORT register tn As evamrle if you want to select the
33. velle 3 8910 PPI INTEL B255A 9 3 MEMORY gt ROM BASIC INTERPRIETER 32kKD 9 USER 64KU VIDEO RAM 16K x There is basic slot in system and the system can access 256KD ROM And it can have maximum 1M tuemors area Basic ROM exists form OOOOH to 7FFFFH and RAM exists from to lower address Refer Lo Chapter 4 for details 2 INTERRUPT NWi Not use MSX BASIC has RAM HOOK INT VDP or cartridge bus can input external inter rupt signal VDP inputs interrupt signi to CPU on every 1 50 sec then CPU restarts From OO38H INTERRUPT CIRCUIT EXAMPLE VDP NT amp DISPLAY MODE m isi TMSOISONLO Character sul pharumer le graph i C symbols RS dots Color 16 colors x Sprite possible x Displuv mode table L ee PP ar e 5 m Ca m i e MODE RESOLUTION SIZE NO COLORj3PRITEIDIPLAY GRAPHIC 1 1240 192 8 8 256 16 20x24 GRAPHIC 2 240 192 18 8 7651 16 O 29 24 16 29 24 MULTICOLOR 64 48bIK 454 240x192 8 6 256 2 616 x 39 24 x NO THE NUMBER OF PATTERN 2 5 DISPLAY CODI ug p tower 4B fois 2 3 fe 2 quce opere
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