PPP Packet Processor 622 Mbps Megacore Function (PP622)
Contents
1. Encrypted gate level netlist Place and route constraints where necessary Secure RTL simulation model Demo testbench Access to problem reporting system Downloading the MegaCore Function If you have Internet access you can download the PPP Packet Processor 622 Mbps MegaCore function from the Altera web site Follow the instructions below to obtain the core via the Internet If you do not have Internet access you can obtain the core from your local Altera representative 1 Point your web browser at http www altera com IPmegastore 2 Inthe IP MegaSearch keyword field type PPP 3 Click the link for the PPP Packet Processor 622 Mbps MegaCore function 4 On the product page click the Free Test Drive icon 5 Follow the on line instructions to download the function and save it to your hard disk Installing the MegaCore Files Use the MegaWizard Plug In to generate the files and install them on your PC The following instructions describe this process For UNIX systems you must have Java runtime environment version 1 3 before you can use the MegaWizard Plug In You can download this file from the Java web site at http www java sun com For Windows follow the instructions below 1 Click Run Start menu Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Getting Started 2 Type lt path name gt lt filename gt exe where lt path name gt is the locati2. oocccnnnnccccnnnncccnnnnincccnonos 21 RX_PM_FCS Receive FCS Error Count HOS sccscsiaccccccs asec ivavecicisessessiacisiaciers 21 RX_PM_ABORT Receive Abort Count HOA occooocccnncnicccconinincccnnnnocccnnnnncccnnnos 21 RX_PM_RUNT Receive Runt Frame Count h0C oooncccncnnncccnnnnccncnnnnniccnnnns 22 TAS easter DON TIPON aia ld paa TA CTRL Transmit Control Register NIO vaciar idos 22 TAXAS Transmit Interrupt Reg Ste lA screens 23 TAE Transmit Interrupt Enable Register Aduna 23 TX_PM_GOOD Transmit Good Packet Count h16 wee cece e eee 23 TX_PM_ERR Transmit Error Packet Count h 18 oooccccnnnnccccncnincccnononicnnnnnos 24 Care VTC AON UTI AAN 24 lea io 2 arene aor N Creer o tye ne E A A re erry tr tt 24 Compaubiity Tests EOvIONME E ans pio 25 Getting Started POSSE VY d a E E re 27 Obtamines Installing the EPO22 rca is 28 Downloading the Wes aC Ore PICO secc isis 28 Installing tne Mesa Core Piles praia naa 28 GoNSIAHALA LLO ao 29 Memento eta SECA 30 mukan TOUR DER TE naaoR 30 teme tie Mene Domno TeDe aaa E Ea apis 30 w A Eo E E 31 Sy Min sis Compuation Hace NOUS aaa 31 Using Third Party EDA Tools tor SOUDESIS errante nadaa 31 Using the Quartus II development tool for compilation and place and route 31 Ejeensine for Coni 2 UTAUONL sii 32 Perorming Tost Routing SiO asirieni aiian aaia aiee 32 viii Altera Corporation NOTESYA Specifications O General Description Altera Corp
3. E MegaCore PPP Packet Processor 622 Mbps MegaCore Function PP622 August 2001 User Guide JA DTE RYA o nnovation Drive San Jose CA 95134 408 544 7000 http www altera com PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Copyright O 2001 Altera Corporation Altera The Programmable Solutions Company the stylized Altera logo specific device designations and all other words and logos that are identified as trademarks and or service marks are unless noted otherwise the trademarks and service marks of Altera Corporation in the U S and other countries All other product or service names are the property of their respective holders Altera products are protected under numerous U S and foreign patents and pending applications maskwork rights and copyrights Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Corporation Altera customers are advised to obtain the latest version of device specifications before relying on any published NSAI information and before placing orders for products or services All rights reserved I S EN
4. ERR 1 RW1C_ Set if a packet is aborted atxerr asserted simultaneously with atxeop This is set if atxerr is asserted Software writes a 1 to this bit to clear it UNDERFLOW RW1C_ Set if the FIFO has underflowed This bit is set if the Atlantic interface does not supply data when required i e atxval 0 in the middle of a packet If atxval is negated after sending a complete packet and before starting a new packet no underflow is reported An underflow aborts the current packet and discards the remainder Subsequent packets are transmitted normally Software writes a 1 to this bit to clear it TX_IE Transmit Interrupt Enable Register h14 DOI O tt GOOD a RW __ Enabies the transit good imerupt saus o ERR 1 RW Enabies the transit err interrupt tato lo JUNDERFLOW o RW Enabies the transmit undertow interrupt status o TX_PM_G00D Transmit Good Packet Count h16 Count of correctly transmitted packets Each correctly transmitted packet no underflow not aborted causes this count to increment by one The counter saturates at OxFFFF it does not wrap to 0 Reading this register clears the count 16 bit values may be written to this register for testing Altera Corporation 23 STAT BED ES Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide TX_PM_ERR Transmit Error Packet Count h18 CNT 15 0 RTCW _ Count of transmitted packets terminated with ABORT Packets
5. Project menu Select Custom EDIF in the Design entry synthesis tool list Click Settings In the EDA Tool Input Settings dialog box make sure that the relevant tool name or option is selected in the Design Entry Synthesis Tool list 5 Add your third party EDA tool generated netlist file to your project 6 Add any tdf vhd or v files not synthesized in the third party tool 7 Add the pre synthesized and encrypted e vqm v file from your working directory created by the MegaWizard Plug In Manager 8 Constrain your design as needed 9 Compile your design The Quartus II Compiler synthesizes and performs place and route on your design Refer to Quartus II Help for further instructions on performing compilation After you have compiled and analyzed your design you are ready to configure your targeted Altera semiconductor device If you are evaluating the PP622 with the OpenCore feature you must license the function before you can generate programming files To obtain licenses contact your local Altera sales representative Ls All current PP622 variants use a single license with ordering code PLSM PP622 After you have licensed the PP622 you can generate EDIF VHDL Verilog HDL and Standard Delay Output Files from the Quartus II software and use them with your existing EDA tools to perform functional modeling and post routing simulation of your design 1 Open your existing Quartus II project 2 Depending on the typ
6. Atlantic interface Users may set this bit to improve the performance of the Atlantic interface or to simplify downstream processing of the packet This function requires that the crclen bit be set properly ENABLE O Disable packet reception 1 Enable packet reception Clearing this bit to zero places the internal state variables in the idle condition clears the status register and all receive performance monitor counts good FCS runt abort Setting it enables all functions GOOD RW1C_ Set if a good packet is received This is set if a legal correct packet is received UNALIGNED RW1C_ Set if receiver is unaligned This is set when the receive aligner is not in the aligned state To determine when the aligner has regained alignment software should read and clear this bit periodically until it stays cleared Clearing align in the control register prevents this bit from being set but does not clear the bit FCS 2 RW1C Setif an FCS error occurs This is set if a packet with an incorrect FCS is received ABORT 1 RW1C_ Set if a receive packet is aborted This is set if a packet terminated with an abort sequence is received RW1C_ Set if a runt packet is received This is set if an illegally short packet is received 20 Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications RX_IE Receive Interrupt Enable Register h04 O nea oe ees O O tt cooo a aw Enables t
7. detecting the start of frame and end of frame indicated by flags and removing the stuff octets control escape characters Aborted frames are also detected FCS 16 32 The FCS 16 32 blocks check for errors by calculating a syndrome and by using either the CRC 16 Care ae 1 or CRC 32 x7O4 x79 x x164 x124 xT e x44 x24 x 1 generator polynomial as an FCS All packets good packets packets with CRC errors aborted packets and runt packets are counted in statistics registers FCS Deletion FCS Deletion removes the FCS from the frame Removal of the FCS is enabled or disabled via the Receive Control Register The frame is then passed to the Atlantic interface The PP622 takes in packets from the Atlantic interface and passes them to the TXHDLC block for processing TXHDLG The TXHDLC block frames the data in the incoming transmit stream The following descriptions explain the principle functions of the TXHLDC block 13 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Interfaces amp Protocols 14 Processing The TXHDLC block inserts the FCS into the data stream for stuffing at the end of a normal packet The TXHDLC also inserts the abort sequence as needed into the data stream for aborted packets and inserts flags between frames It also stuffs the data and FCS octets for transparency Stuffing is performed 8 bits at a time byte oriented for high performance and low gat
8. for the PP622 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Features Receive Features Extraction of octet synchronous PPP packets from a single STS 12 SPE Arbitrary packet length one or more octets Packet delineation and destuffing of all stuffed octets Byte realignment software programmable Descrambling software programmable Error detection by CRC 32 and CRC CCITT FCS Flag sequence deletion FCS deletion software programmable RFC1662 and RFC 2615 compliant HDLC type framing some sections are not implemented Performance monitoring by counting Good frames Bad FCS Aborted frames Runt frames Error detection FCS Runt Optional removal of FCS Transmit Features 10 RFC1662 and RFC 2615 compliant HDLC type framing some sections are not implemented Flag octets and control escape octets stuffing in message and FCS for transparency 16 or 32 bit FCS appended to packet Flag sequence insertion between packets for under utilized paths Flag sharing single flag between frames Scrambling software programmable Automatic abortion in case of transmit underflow or by host command from Atlantic interface Arbitrary packet length one or more octets Automatic appending of FCS to transmitted frames Performance monitoring by counting Good frames Underflows Aborted packets Altera Corporation PPP Packet Processor 622 Mbps Meg
9. signal indicate the location and type of access within the block The rdata buses and dtack signals can be merged from multiple blocks using a simple OR function The dtack signal is sustained until the block sel is removed four way handshaking meaning the AIRbus can cross clock domain boundaries The PP622 is an AIRbus slave with a data width of 16 bits Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications Altera Corporation Atlantic Interface to The Atlantic interface is a full duplex synchronous bus protocol N supporting both packets and cells The PP622 is an Atlantic interface E master using an 8 bit wide data path clocked at 77 76 MHz to deliver packets to the slave a Ls The arxdav atxdiv and atxsop signals are provided but are a not used More detailed information on the Midbus AIRbus and Atlantic is available from the Altera web site at http www altera com Data Ordering Data is transferred in parallel 8 bits at a time in the same order it was received internally between the PP622 and the interfaces but it is ultimately transmitted received MSB first through external bit serial mediums such as SONET and SDH optical fibre in keeping with telephony convention This convention of MSB first is not followed in doing CRC FCS syndrome calculations which use data communications LSB first conventions In CRC calculations the LSB of each octe
10. testbench are located on your hard drive the paths are sim_lib lt variant gt modelsim_verilog sim_lib lt variant gt modelsim_vhdl sim_lib lt variant gt visual_ip sim_lib lt variant gt test Ls lt variant gt is a unique code aotXXXX_ _pp622 assigned to the specific configuration requested through the MegaWizard Plug In Using the Verilog Demo Testbench The demo testbench includes some simple stimulus to control the user interfaces of the PP622 Each PP622 variant includes scripts to compile and run the demo testbench using a variety of simulators and models 30 Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Getting Started Using the Visual IP Software The Visual IP software facilitates the use of Visual IP simulation models with third party simulation tools To view a simulation model you must have the Visual IP software installed on your system To download the software or for instructions on how to use the software refer to the Altera web site at http www altera com and search for Visual IP For examples of how to use the provided Visual IP model refer to the sample scripts included with the demo testbench Synth esis After you have verified that your design is functionally correct you are TT ready to perform synthesis and place and route Synthesis can be Comp ilation amp performed by the Quartus II development tool or by a third party Place amp Route synthe
11. which are not runts but which are terminated by an abort sequence increment this count The counter saturates at OxFFFF it does not wrap to 0 Reading this register clears the count Core The PP622 was the object of very thorough verification for operation Te according to industry standards The PP622 was tested by simulation and Verification in circuit for third party compatibility Both test environments are S umma ry eee iia briefly including the number of test programs and their results Simulation Environment The PP622 was simulated using behavioral utilities with multiple simulators including but not limited to ModelSim SE The behavioral utilities consist of generic flow control generators and monitors Midbus generators and monitors Atlantic generators and monitors an AIRbus master model and clock generators A test suite using the utilities and the RTL model of the PP622 was used to verify the proper operation of all the features listed on page 10 Table 4 lists the results of the simulation for the PP622 Table 4 Results Number of test programs 7 Number of test programs passing Number of test programs failing Number of test cases 7 Number of test cases passing Number of test cases failing Note 1 Each test program contains at least one test case 24 Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications Altera Corporation Compatibility Testi
12. ISO 9001 il Altera Corporation NOTE SYA About this User Guide How to Find Information Altera Corporation This user guide provides comprehensive information about the Altera PPP Packet Processor 622 Mbps MegaCore Function PP622 Table 1 shows the user guide revision history Go to the following sources for more information m See Features on page 10 for a complete list of the core features including new features in this release mM Refer to the PP622 readme file for late breaking information that is not available in this user guide Table 1 User Guide Revision History ee tn December 2000 First version of user guide August 2001 First revision Added Core Verification Summary section Revised the Getting Started chapter The Adobe Acrobat Find feature allows you to search the contents of a PDF file Click on the binoculars icon in the top toolbar to open the Find dialog box or click the right mouse button for a pull down menu m Bookmarks serve as an additional table of contents m Thumbnail icons which provide miniature previews of each page provide a link to the pages E Numerous links shown in green text allow you to jump to related information About this User Guide PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide How to Conta cl For the most up to date information about Altera products go to the Altera world wide web site at http www alt
13. RC 32 mode If set the receiver computes syndromes for received packets using the CRC 32 polynomial if cleared the CRC CCITT 16 bit polynomial The syndrome is always computed and checked Packets with bad syndromes i e with errors are not discarded but are counted in the Receive FCS Error Count register and marked as erroneous when sent to the Atlantic interface SCRAMEN 2 RW Enable descrambling of transmit frame and descrambling of the receive frame This causes the received data stream to be descrambled using the x43 1 scrambling polynomial The bits are descrambled using the most significant higher numbered bit first All bits including flags the body of the packet and the FCS are scrambled The descrambling process is self synchronizing The descrambler is not reset by the enable bit and will therefore synchronize the state with the received data stream while the enable is cleared It should therefore be set to its desired value and at least 43 bits of data should be received before turning on the enable bit Altera Corporation 19 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide RX_CTRL Receive Control Register h00 Part 2 of 2 DELFCS RW 0 Store FCS with received packet 1 Delete FCS from received frame If cleared the packet is delivered to the Atlantic interface with the FCS appended Setting this bit causes the receiver to remove the FCS before sending the packet to the
14. aCore Function PP622 User Guide Specifications Functional The PP622 is a fully static reusable easy to replicate single channel 1 ae processor no interleaving which operates in octet synchronous mode Descri pti on and offers full duplex processing capability Figure 1 shows a complete block diagram of the PP622 including the three interfaces that support it See Interfaces amp Protocols on page 14 for more information N D T 5 y r 7 Figure 1 Block Diagram rxclk arxena 4 RXHDLC rxreset_n arxdav Midbus J mrxdat 7 0 arxdiv Interface mrxena arxdat 7 0 arxsop arxeop arxerr Atlantic atxena Interface txclk atxdiv txreset_n atxdav atxval Midbus mtxdat 7 0 e atxdat 7 0 l nterface mtxena atxeop lt 4 atxsop atxerr o UU Z 0 F e 0 5b Bb 2 B y 3 gt oO qu oO pe O LL AlRbus Interface Rece iver The PP622 receives data from the Midbus interface and forwards it to the _ RXHLDC block for processing Description RXHDLC The RXHDLC block processes the data in the incoming PPP packet The following descriptions explain the principle functions of the RXHLDC block Altera Corporation 11 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide 12 byte Alignment Byte alignment aligns the boundaries of the PPP bytes flags CRC etc with the boundaries of the packet processor This function is necessary if the t
15. e Flag Sequence 0x7d is encoded as 0x7d Ox5d Control Escape RFC1662 also defines an ACCM for the convenience of software and hardware designed for transferring text files This allows other special characters to be stuffed as directed by the user The PP155 does not implement the ACCM thus the TXHDLC does not stuff anything other than the flag and control escape patterns However in accordance with RFC1662 the RXHDLC destuffs any stuffed octets On reception Each Control Escape octet is also removed and the following octet is exclusive or d with hexadecimal 0x20 unless it is the Flag Sequence which aborts a frame 0 Si g na Is Table 2 describes the input output signals used by the PP622 Table 2 1 0 Signals Part 1 of 2 O eon orei egtn Receive Interface Signals Midbus Receive Interface Signals Atlantic Receive Interface Signals Atlantic Receive Interface Signals arxerr Output Error indication 16 Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications Table 2 1 0 Signals Part 2 of 2 on ot Jon Transmit Interface Signals Midbus Transmit Interface Signals Atlantic Transmit Interface Signals AlRbus Interface Signals AlRbus Interface Signals S a o oupa mermar request Performance Table 3 shows the required speed and estimated gate count of PP622 in an APEX 20KE device Table 3 Performance Note 1 Note 1 The nu
16. e count When enabled it delivers octets to the Midbus interface FCS 16 32 The FCS is calculated using the CRC 16 or CRC 32 generating polynomial Scrambling The transmit data stream is scrambled using the rege polynomial Scrambling can be enabled or disabled via the Transmit Control Register The packet is sent to the Midbus interface for transmission Midbus Interface The Midbus interface is a simple synchronous full duplex data path bus The PP622 Midbus runs at 77 76 MHz over a single byte lane in each direction In the receive direction RX data is transferred from the Midbus master to the slave PP622 In the transmit direction TX data is transferred from the slave PP622 to the master In each direction the Midbus can carry 8 bits per clock cycle It includes Midbus receive data mrxdat 7 0 and Midbus receive enable mrxena lines to indicate valid data transfers in the RX direction and Midbus transmit data mtxdat 7 0 and Midbus transmit enable mt xena lines to indicate valid data requests in the TX direction Since the PP622 is a slave to the Midbus it can work with any Midbus master AlRbus Interface The AIRbus interface provides access to internal registers using a simple synchronous internal bus protocol This consists of separate read data rdata 15 0 and write data wdata 15 0 buses a data transfer acknowledge dtack signal and a select se1 signal An address addr 4 11 bus and read read
17. e of output file you want specify Verilog HDL output settings or VHDL output settings in the General Settings dialog box Project menu 3 Compile your design with the Quartus II software refer to the Using the Quartus II development tool for compilation and place and route section The Quartus II software generates output and programing files Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Getting Started 4 You can now import your Quartus II software generated output files edo vho vo or sdo into your third party EDA tool for post route device level and system level simulation lt P cD e cc WM mp pa Lm 92 a Altera Corporation 33 Notes
18. era com Altera For additional information about Altera products consult the sources shown in Table 2 Table 2 How to Contact Altera Information Type Recess USA amp Canada All Other Locations Altera Literature Electronic mail lit_req altera com 1 lit_req O altera com 1 Services Non technical Telephone hotline 800 SOS EPLD 408 544 7000 customer service 7 30 a m to 5 30 p m Pacific Time 408 544 7606 408 544 7606 Technical support Telephone hotline 800 800 EPLD 408 544 7000 1 7 00 a m to 5 00 p m 7 30 a m to 5 30 p m Pacific Time Pacific Time 08 544 2401 T General product 408 544 7104 1 information World wide web site http www altera com Note 1 You can also contact your local Altera sales office or sales representative iv Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide About this User Guide Typog rap h j C The PPP Packet Processor 622 Mbps MegaCore Function PP622 User a Guide uses the typographic conventions shown in Table 3 Conventions Table 3 Conventions Bold Type with Initial Command names dialog box titles checkbox options and dialog box options are Capital Letters shown in bold initial capital letters Example Save As dialog box bold type External timing parameters directory names project names disk drive names filenames filename extensions and software utility names are shown in bold type Examples fmax ma
19. he receive good imeruptsas o JUNALIGNED a faw Enables the receive unaligned interrupt satus Jo Fos e RW enables he receive FCS interrupt sets Jo ABORT mw enables the receve abon ineruptstatus Jo RUNT 0 RW Enables the receive runt interrupt status Jo RX_PM_GOOD Receive Good Packet Count h06 ma ats acess romo oe CNT 15 0 Count of correctly received packets Each correctly received packet good FCS not aborted not a runt causes this count to increment by one The counter saturates at OxFFFF it will not wrap to O Reading this register clears the count 16 bit values may be written to this register for testing RX_PM_FCS Receive FCS Error Count h08 Count of received packets with bad FCS Packets that are not runts and are not aborted but which have bad CRC syndromes increment this count The counter saturates at OxFFFF and does not wrap to 0 Reading this register clears the count RX_PM_ ABORT Receive Abort Count h0A ia mis access natin pt RTCW _ Count of received packets terminated with ABORT o Altera Corporation 21 STAT BED ES Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide RX_PM_RUNT Receive Runt Frame Count hoc CNT 15 0 RTCW Count of runt frames Runt packets are packets received with frames shorter than 3 or 5 octets depending on the setting of crclen not including stuff octets and flags Individual runt packets increment
20. mbers for the LEs and ESBs are approximate as of August 2001 77 76 a to support 622 08 Mbps Altera Corporation 17 Le D T 5 y 7 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Software Interface 18 Memory Map All addresses access 16 bit registers and are shown as hexadecimal values The value is the byte address thus bit 0 is not used All addresses are even Transmit Error Packet Count Registers The following is a list of access codes used to describe the type of register bits e IA Ro faeson S Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications RX Register Description The following tables describe the registers for the receiver section of the PP622 RX_CTRL Receive Control Register h00 Part 1 of 2 REALIGN 5 RWSC 1 Forces aligner to try new alignment Writing a 1 to this bit note that it always reads as 0 forces the byte aligner to try a new alignment This bit is ignored if align is O ALIGN 4 RW O Byte alignment disabled 1 Byte alignment enabled If set the aligner monitors the error rate to determine if the PPP bytes are aligned to mrxdat If data are not aligned it shifts the data on mrxdat to attempt to align the data If cleared the PPP bytes are assumed to be aligned to mrxdat Le D T 5 y r 7 CRCLEN 3 RW 0 CRC CCITT mode 1 C
21. n You can test drive a PP622 using the Altera OpenCore feature within the Quartus II software to instantiate it to perform place and route to perform static timing analysis and to simulate it using a third party simulator within your custom logic You only need licenses when you are ready to generate programming files This design walkthrough involves the following steps 1 Obtaining and installing the PP622 MegaCore Function 2 Generating a PP622 for your system using the MegaWizard Plug In 3 Implementing the rest of your system using AHDL VHDL or Verilog HDL 4 Simulating the PP622 within your design 5 Synthesis compilation and place and route 6 Licensing the PP622 to configure the device 7 Performing post routing simulation The instructions assume that m You are using a PC E You are familiar with the Quartus II software m The Quartus II software the newest version is installed in the default location m You are using the OpenCore feature to test drive a PP622 or you have licensed it 27 lt P cD e cc N mp fay Lm mp cD a Getting Started PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Obtaining amp Installing the PP622 28 To start using the PP622 you need to obtain the MegaCore package which includes the following Data sheet User guide AIRbus Midbus and Atlantic interface functional specifications MegaWizard Plug In
22. n Language Very High Speed Integrated Circuit Altera Corporation Contents NOTE RYA About this User Guide Porto nal norna ON ns sou detustiiaatatianeseunstnanstonuliies 111 a POP o A E E yeuors exes eoeupuetencasnechsuasaeqeneaie iv pO erm On SONS escasas oie means vV een seen orer sneer e ree ete vi Specifications Genera DESC axdinnumonnnuaicun adnan One RmE 9 O a o cans E A ia saensiabetoneetauaearnens 10 RETCINE PEAIUIES N E ee PP Per te tne er are ere ester et fer Pena E T Coreen reer ate 10 Trans PATEAR 10 a e A neato vesaaeinpearnoamutets 11 Receiver DiescrplOl ss 11 164 10 PP EA A A cones PCE E a 11 oa a e E E A E E 12 Pe MN E E A A E E E A E A 13 PEOC EOE ai E 13 PEA iia 15 E A e arctan A E AEA R 13 Transnutier Desc puOn mv A ia 13 P PEC aero aaa 13 TOTES pita Anas 14 PESTO da it a 14 e o E A AT 14 et Aces a a iia E 14 A PP A A EE AATA 14 o A eta trey cesta Tre ence E etter terry 14 AE METAS ra o topan 15 DATE eae veneer ee ee 15 CARS ACI ida 15 PLEET A AEEA AA IA E rere A A 16 Pe E E A T E AEE TOE AE tener 17 a A A A 18 Mentor Diap urraca EE tere nia rane etree EEE ERE 18 a e o ert ee 18 Ie LOS UO raices EEE 19 RAX IRL Receive Control Register OU src 19 RA I Revere mMierropit Reer Wea 20 EA IE Receive Interrupt Enable Register MUA pao 2l Altera Corporation vii Contents PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide RX_PM_GOOD Receive Good Packet Count h06
23. ng Environment The PP622 was evaluated within an APEX EP20K1000EFC672 device against a commercial third party packet processor with similar features as required by industry standards For testing purposes the PP622 was interconnected with the Altera STS12CFRM MegaCore function and the Altera PCI MegaCore function was used to interface to the AIRbus and to the third party packet processor Figure 2 shows the test board used Software from a host PC was used to set registers on the PP622 and the third party packet processor The effects of setting these registers and any corresponding registers were observed to determine functionality Tests were run for extended periods of time thereby testing millions of packets Figure 2 Test Board Third Party ASSP APEX EP20K1000EFC672 Table 5 lists the results of the hardware verification for the PP622 Table 5 Results Number of test programs passing Number of test programs failing NS Number of test cases passing 2 Number of test cases failing Note 1 Each test program contains at least one test case 25 N D T 5 y r 7 Notes NOTE YA Getting Started O Design Walkthrough Altera Corporation This section describes how to obtain a variant from the PPP Packet Processor 622 Mbps MegaCore Function PP622 It explains how to install the PP622 on your PC and walks you through the process of implementing the variant in a desig
24. ocedure Bullets are used in a ist of items when the sequence of the items is not important Y The checkmark indicates a procedure that consists of one step only Se O The feet direct you to more information on a particular topic Altera Corporation V About this User Guide PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Abbreviations and Acronyms vi ACCM AHDL CPU CRC 16 32 CRC CCITT EDA EDIF ESB FCS FIFO HDL HDLC I O IP LE LSB LSByte Mbps MSB MSByte PC POS PHY PPP RX RXHLDC SDH SONET SPE STS 3 TX TXHLDC VHDL VHSIC Asynchronous Control Character Map Altera Hardware Description Language Central processing unit Cyclic Redundancy Check 16 or 32 bit Cyclic Redundancy Check Electronic Design Automation Electronic Design Interchange Format Embedded System Block Frame Check Sequence First In First Out Hardware Description Language High Level Data Link Control Input Output Intellectual Property Logic Element Least Significant Bit Least Significant Byte Megabits per second Most Significant Bit Most Significant Byte Personal computer Packet Over SONET Physical layer Point to Point Protocol Receive Receive High Level Data Link Control sub block Synchronous Digital Hierarchy Synchronous Optical Network Synchronous Payload Envelope System Transport Signal level 3 Transmit Transmit High Level Data Link Control sub block VHSIC Hardware Descriptio
25. on of the downloaded PP622 and lt filename gt is the filename of the PP622 Click OK 3 The MegaCore Installer dialog box appears Follow the MegaWizard Plug In instructions to finish the installation 4 Disregard this step if you are using Quartus II version 1 1 or higher Otherwise after you have finished installing the files you must specify the directory in which you installed them as a user library in the Quartus II software Search for User Libraries in Quartus II Help for instructions on how to add these libraries In Manager used within the Quartus II software allows you to create or modify design files to meet the needs of your application You can then instantiate the PP622 in your design file G cD Generatin ga This section describes the design flow using the PPP Packet Processor 622 Mbps MegaCore function and the Quartus II development system A PP622 MegaWizard Plug In is provided with the PP622 The MegaWizard Plug 2 D E To create a PP622 using the MegaWizard Plug In follow these steps 1 Start the MegaWizard Plug In by choosing the MegaWizard Plug In Manager command Tools menu in the Quartus II software The MegaWizard Plug In Manager dialog box is displayed Ls Refer to Quartus II Help for detailed instructions on how to use the MegaWizard Plug In Manager 2 Specify that you want to create a new custom variant and click Next 3 On the second page of the MegaWizard Plug In
26. open the Communications folder and select the PP622 from the PPP folder 4 Choose the type of output files language specify the folder and name for the files the MegaWizard Plug In creates and click Next 5 The final screen lists the design files created by the MegaWizard Plug In and indicates the location of the simulation models for the PP622 Click Finish Altera Corporation 29 Getting Started PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Imp lementin g Once you have created your PP622 you are ready to implement it You can use the files generated by the MegaWizard Plug In and use the the System Quartus II software or other EDA tools to create your design Table 1 lists the generated files Table 1 MegaWizard Plug In Files Design File Wrapper ns E Sample Tnstantiation insta insta na Black Box Module DA E EE Symbol files for the Quartus II software used to instantiate the PP622 into a schematic design An encrypted HDL netlist file S imulati ng Altera provides three models to be used for functional verification of the PP622 within your design A Verilog demo testbench including scripts to Your Des l g n run it is also provided This demo testbench used with the ModelSim AE simulator demonstrates how to instantiate a model in a design To find the simulation models for your selected variant refer to the last page of the MegaWizard Plug In Manager These models and the demo
27. oration The PP622 encapsulates user data packets using HDLC type framing in compliance with the Internet Request For Comment RFC 1622 and RFC 2615 documents For a link to these documents please visit the Internet Engineering Task Force web site at http www ietf org rfc Y The following functions are not supported by the PP622 2 RFC1662 ACCM Bit stuffing Non flag inter frame fill Transparent mode FCS not appended to transmit frame Maximum length frame check For the purpose of this user guide receive indicates data flowing into the PP622 from the Midbus interface for transmission through the Atlantic interface transmit indicates data received from the Atlantic interface for transmission through the Midbus interface Thus the Atlantic interface is the source for transmit packets and the sink for received packets The PPP Packet Processor 622 Mbps MegaCore Function PP622 uses the MegaWizard Plug In within the Quartus II software to generate variants in VHDL AHDL or Verilog HDL which you can instantiate into your design Table 1 shows the optional features available to generate the PP622 Ls Only the basic configuration of PP622 is available Table 1 Optional Features Note 1 Basic Configuration Note 1 The numbers for the LEs and ESBs are approximate as of August 2001 Users are strongly advised to run the MegaWizard Plug In and the Quartus II software to see exact numbers
28. ransmission facility does not preserve byte boundaries If the byte boundaries are preserved as in SONET this function should be disabled Assume the following packet If the data becomes misaligned by 2 bits the bytes on the Midbus are as follows k ME ble k Symptoms of misalignment are m Extremely long packets They typically occur during line idle when the bus is normally carrying flags The flags no longer look like flags but like packet data In the above example the flags are converted into 10011111 E Excessive error rate Random data patterns may when shifted masquerade as flags and hence mark the start and stop of packets This is likely to cause FCS errors and less likely runts or aborts Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications Transmitter Description Altera Corporation If it detects a misalignment the aligner rearranges the data to compensate This function is enabled via the Receive Control Register Descrambling The receive frame and between frame flags are descrambled using a self synchronizing descrambler The generator polynomial used is the standard x 1 Descrambling can be enabled or disabled via the Receive Control Register The inter frame fill is then discarded and the frame is forwarded for processing Le D T 5 y r 7 Processing Processing involves taking the descrambled frame
29. sis tool The Quartus II software works seamlessly with tools from many EDA vendors including Cadence Exemplar Logic Mentor Graphics Synopsys Synplicity and Viewlogic lt P cD e cc WM mp pa Lm 92 a Using Third Party EDA Tools for Synthesis To synthesize your design in a third party EDA tool follow these steps 1 Create your custom design instantiating a PP622 2 Synthesize the design using your third party EDA tool Your EDA tool should treat the PP622 instantiation as a black box by either setting attributes or ignoring the instantiation 3 After compilation generate a netlist file in your third party EDA tool Using the Quartus Il development tool for compilation and place and route To use the Quartus II software to compile and place and route your design follow these steps 1 Select Compile mode Processing menu 2 Specify the Compiler settings in the Compiler Settings dialog box Processing menu or use the Compiler Settings wizard 3 Disregard this step if you are using Quartus II version 1 1 or higher Otherwise specify the user libraries for the project and the order in which the Compiler searches the libraries Altera Corporation 31 Getting Started PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Licensing for Configuration Performing Post Routing Simulation 32 4 Specify the input settings for the project Choose EDA Tool Settings
30. t is nominally processed first CRC calculations are actually done in parallel though the calculation simulates a bit serial LSB first calculation The order that octets go into the CRC calculation is the same as the transmission order The difference in ordering has no practical effect as long as both ends follow the same convention ic It is important to specify the nominal order within the bits on the Atlantic and Midbus interfaces Transparency Special flag characters delimit the start and end of a PPP frame These special characters are known as a Flag Sequence which is the binary sequence 01111110 hexadecimal 0x7e There is no length field loss of carrier or other delimiter of packet boundaries Since the data in the packet is unrestricted all data patterns are valid Transparency is achieved when the framing protocol stuffs flag and escape characters as explained in RFC1662 An octet stuffing procedure is used The Control Escape octet is defined as binary 01111101 hexadecimal 0x7d most significant bit first 15 Specifications PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide After FCS computation the transmitter examines the entire frame between the two Flag Sequences Each Flag Sequence Control Escape octet is replaced by a two octet sequence consisting of the Control Escape octet followed by the original octet exclusive or d with hexadecimal 0x20 Ox7e is encoded as 0x7d Ox5
31. the count The counter saturates at OxFFFF and does not wrap to 0 Reading this register clears the count 32 bit values may be written to this register for testing TX Register Description The following tables describe the registers for the transmitter section of the PP622 TX_CTRL Transmit Control Register h10 CRCLEN RW Set to 1 for CRC 32 32 bits O for CRC CCITT 16 bits If set the transmit section computes FCSs for transmit packets using the CRC 32 polynomial if cleared the CRC CCITT 16 bit polynomial is used The FCS is always generated and appended SCRAMEN Enables scrambling of the transmit frame This causes the transmitted data stream to be scrambled using the x43 1 scrambling polynomial The bits are scrambled using the most significant higher numbered bit first All bits including flags the body of the packet and the FCS are scrambled ENABLE RW O Disable packet transmission 1 Enable packet transmission Clearing this bit to zero places the internal state variables in the idle condition clears the status registers and all transmit performance monitor counts good error Setting it enables all functions 22 Altera Corporation PPP Packet Processor 622 Mbps MegaCore Function PP622 User Guide Specifications TX_IS Transmit Interrupt Register h12 Fd ICC A GOOD 2 RW1C_ Set if a packet is transmitted correctly This bit is set by the transmission of a complete packet with no errors
32. xplus2 directory d drive chiptrip gdf file Bold italic type Book titles are shown in bold italic type with initial capital letters Example 1999 Device Data Book Italic Type with Initial Document titles are shown in italic type with initial capital letters Example AN 75 Capital Letters High Speed Board Design Italic type Internal timing parameters and variables are shown in italic type Examples tp y N 1 Variable names are enclosed in angle brackets lt gt and shown in italic type Example lt file name gt lt project name gt pof file Initial Capital Letters Keyboard keys and menu names are shown with initial capital letters Examples Delete key the Options menu Subheading Title References to sections within a document and titles of Quartus Il and MAX PLUS II Help topics are shown in quotation marks Example Configuring a FLEX 10K or FLEX 8000 Device with the BitBlaster Download Cable Courier type Signal and port names are shown in lowercase Courier type Examples data1 tdi input Active low signals are denoted by suffix _n e g reset_n Anything that must be typed exactly as it appears is shown in Courier type For example c max2work tutorial chiptrip gdf Also sections of an actual file such as a Report File references to parts of files e g the AHDL keyword SUBDESIGN as well as logic function names e g TRI are shown in Courier important such as the steps listed in a pr
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