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Cyclone V SoC Development Kit User Guide

1. This tab requires that a bts ini file with QTS ON specified at the 1st line reside in the same directory as BoardTestSystem exe Removing or renaming this file will run an older version of this tab which is grayed out by default See the readme txt in that same directory for more information Figure 5 7 The HSMC Tab Board Test System zu xj Configure Help About System info eero rac poses HSM SD Video HEMC XCVR 3 Data rate 1250 00MBps Start Stop Freq 2500 03MHz bits 8 243995e 10 _Insert rror cear Inserted errors 0 E PMA Setting Detected errors 0 cmm m Pattern sync Yes pRes7 rLVDS Data rate 1699 97MBps Start Stop Freq 800 00MHz bits 1 124133e 11 Insert Error Clear Inserted errors 0 Detected errors 0 Pattern s Yes BER ync PRBS7 CMOS Datarate 18 75MBps Start Stop Freq 50 00MHz bits 1 323948e 10 Insert Error Gear Status Inserted errors 0 PMA Setting Detected HSMC Project PLLlock Yes Detected errors 0 Pattern sync Yes BER pRes7 start stop 5 You must have the loopback HSMC installed on the HSMC Port A connector for this test to work correctly The following sections describe the controls on the HSMC tab Start Stop The Start and Stop controls at the bottom right of this tab allow you to start and stop testing for all three ports September 2015 Alte
2. F vco 2500 0000 Pr E LE Hsec GU Disable all CLkO 156 2500 CLKO 100 00 DisablectKO CLK1 25 0000 CGKi 100 00 Disable CLK1 CLk2 25 0000 CLK2 100 00 Disable CLK2 ak3 100 0000 CLK3 100 00 Disable CLK3 Default Set New Frequency USB BlasterII on localhost USB 1 5M 1270ZF324 E 122102 EPM221062 The following sections describe the Clock Control controls Serial Port Registers The Serial port registers control shows the current values from the Si570 registers For more information about the Si570 registers refer to the Si570 Si571 data sheet available on the Silicon Labs website ww w silabs com fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values For more information about the fyrar value and how it is calculated refer to the Si570 Si571 data sheet available on the Silicon Labs website www silabs com Target Frequency The Target frequency control allows you to specify the frequency of the clock Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possible within 100 parts per million ppm The Target frequency control works in conjunction with the Set New Frequency control Default This control sets the frequency for the oscillator associated with the active tab back to its default value This can
3. The User LEDs control displays the current state of the user LEDs Click the graphical representation of the LEDs to turn the board LEDs on and off You can click ALL to turn on and off all of the user LEDs at once Push Button Switches The read only Push Button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The 12C Tab The I2C tab allows you to read and write 1 kilobit Kb to an PDC EEPROM located at U28 on the development board Figure 5 4 shows the I2C tab Figure 5 4 The 12C Tab Board Test System E p lal xl Configure Help About System info cero I2c DDR3 esc ot Video EEPROM Start address Range 0x0000 0000 0x0000 0FFF 0000 0000 Red Address 6C637943 20656E6F 6F532056 65442043 0000 0010 6F6C6576 BE656D70 6F422074 00647261 0000 0020 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0030 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0040 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0050 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0060 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF 0000 0070 FFFFFFFF FFFFFFFF FFFFFFFF FFFFFFFF i RTC RTC time 2013 03 26 10 37 14 System time 2013 03 26 10 37 17 Write System time to RTC Detected the GPIO Project The following sections describe the controls on the I
4. Total Power 967 61mW Total Power 1376 27mW Messages Controls 3 Stop Update Speed M r zi MAX Ver 8 Connected to the target The following sections describe the Power Monitor controls U34 and U26 The U34 and U26 groups show the power rail graphs They display the mA power consumption of your board over time The green line indicates the current value The red line indicates the maximum value read since the last reset You can enlarge a graph by clicking on it Click it again to restore the original size Temp on 2978 The temperature controls display only the temperature from the power supply manager not the FPGA Total Power These controls display the sum of all four rails for each group U34 and for U26 Controls This group contains the following controls m Start Starts the communication with the board to monitor power September 2015 Altera Corporation Chapter 5 Board Test System 5 17 The Clock Control m Stop Stops the communication with the board to monitor power m Update speed Specifies how often to refresh the graph m Log Results Specifies that a log file is saved to lt install dir NkitsNcycloneVSX 5csxfc6df31 socNexamplesNboard test system m MAX V version Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir NkitsNcycloneVSX 5csxfc6df31 socMfactory recovery and install dir gt kits cycloneVSX_5csxfc6df3
5. Bars Color RGB Values White Grey 180 180 180 Yellow 180 180 16 Cyan 16 180 180 Green 16 180 16 Magenta 180 16 180 Red 180 16 16 Blue 16 16 180 Black 16 16 16 m Pathological Specifies a video color bar pattern with two horizontal color bars that stresses the receive PLL m PRBS Specifies a pseudo random bit sequence useful for electrical testing of the interface for data integrity Intensity Specifies the color intensity of the transmitted color bar pattern The following choices are available m 75 Specifies 75 intensity m 100 Specifies 100 intensity SDI Standard Specifies the video standard used by the pattern generator on the SDI video stream The following choices are available m SD Specifies a 270 Mbps data rate m HD Specifies a 1 485 Gbps data rate m 3G HD Specifies a 2 97 Gbps data rate Clock Source Specifies the clock used by the SDI PLL to lock onto The following choices are available m Lock to host Locks the SDI PLL to the local reference on the Cyclone V SoC Development board m Lock to input Locks the SDI PLL to the SDI video data input September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 12 Chapter 5 Board Test System Using the Board Test System Data Test This group displays information about the SDI interface test when running in PRBS mode in the patter generator m Data rate Displays the current SDI data rate in me
6. Chapter 4 Board Update Portal Connecting to the Board Update Portal Web Page 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser Ka You can click Cyclone V SoC Development Kit on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs Te You can also navigate directly to the Cyclone V SoC Development Kit page of the Altera website to determine if you have the latest kit software Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide AA OTE RYA 5 Board Test System e The development kit includes an application called the Board Test System BTS and related design examples The BTS provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters observe performance and measure power usage While using the BTS you reconfigure the FPGA several times with test designs specific to the functionality you are testing To install the BTS follow the steps in Installing the Development Kit on page 2 2 The Board Test System GUI communicates over the JTAG bus to a test design running in the Cyclone V device Figure 5 1 shows the initial GUI for a board that is in the factory configuration Look for yellow
7. File and select the path to the desired sof Turn on the Program Configure option for the added file m e SP N Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 I gt Using the Quartus II Programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 20 Chapter 5 Board Test System Configuring the FPGA Using the Quartus Il Programmer Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide N DTE RYN A Programming Flash Memory This appendix describes programming information for the following memory devices m Common flash interface CFI flash memory m Quad serial peripheral interface quad SPI flash memory m SD card flash memory The Cyclone V development board s flash memory ships preconfigured with the parallel flash loader PFL option bits to support FPGA designs to be written to any of the three locations as shown in Table A 1 The PFL is disabled by default Set SW2 3 to ON to enable FPGA programming from CFI flash memory on power up There are several other factory software files written to flash memory to support the Board Update Portal These software files were created using the Nio
8. N DTE RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01135 1 2 Cyclone V SoC Development Kit User Guide PX Feedback Subscribe 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks eb Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide NBD rs SYN Contents Chapter 1 About This Kit Kit Features iore d bte EP rae a a hb P Rabe doe Ra deq id pleted e Vd opido is 1 1 Detore XOU Beg lb dcs athe ane ant ate ay
9. also be accomplished by power cycling the board Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 19 Configuring the FPGA Using the Quartus II Programmer Set New Frequency The Set New Frequency control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the 51570 X1 and Si571 X3 Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with your SRAM Object File sof file Before Configuring Ensure the following m The Quartus II Programmer and the USB Blaster II driver are installed on the host computer m The USB cable is connected to the development board m Power to the board is on and no other applications that use the JTAG chain are running If the Quartus II Programmer window is already open and you power cycle the board to detect the JTAG chain do the following m Click Hardware Setup in the Quartus II Programmer window m Reselect USB Blaster II in order to properly detect the JTAG chain Configuring the FPGA Perform these steps 1 Start the Quartus II Programmer Click Auto Detect to display the devices in the JTAG chain Click Add
10. een cetero a yd HE y Er V EXE re a XE amare A 3 guad SEI Flasi Memory o iere cerdrckett as etary t avete desastres eee ae petes A 3 Programming quad SPI Flash Using the Quartus II Programmer ssseeseees A 3 SD Card Memory isis kb gee ER EEEY PEE GT E rH RECIPE CORERP CHR C RED ECKE E EE A 4 Programming the SD Card Boot Image 6 6 6 nen nee eee A 4 Additional Information Document Revision History sssssssss nnne Info 1 How to Contact Altera ees fice bd ereti ceia eed pe tene POUR P d ee duree quee ae does Info 1 Typographic Conventions scs veetk essen ene er epe rie beer eb aeeoe Ren gedai Roga Reed Info 1 Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide N DTE SYN 1 About This Kit The Altera Cyclone V system on a chip SoC Development Kit is a complete design environment that includes both the hardware and software you need to develop Cyclone V SoC designs Kit Features This section briefly describes the kit contents Te For a complete list of this kit s contents and capabilities refer to the Cyclone V SoC Development Kit page The Cyclone V SoC Development Kit includes the following hardware m Cyclone V development board A development platform that allows you to develop and prototype hardware designs running on the Cyclone V SoC T For detailed information about the board components and interfaces refer to the Cyclone V SoC Development Board Refere
11. the FPGA logic via the AXI Bridge interfaces Cyclone V SoC Development Board Reference Manual Complete information about the development board Development Board Daughtercards Additional daughter cards available for purchase Documentation Cyclone V Devices Cyclone V device documentation Devices Purchase devices from the eStore Capture CIS Symbols Cyclone V OrCAD symbols Embedded Processing Nios Il 32 bit embedded processor solutions Cyclone V SoC Development Kit User Guide September 2015 Altera Corporation ANB TE SYAN 2 Software Installation This chapter explains how to install the following software m Quartus II Web Edition Software optional m Altera SoC Embedded Development Suite EDS m Cyclone V SoC Development Kit software m On Board USB Blaster II driver If you do not need to develop FPGA designs you do not need to download the Quartus II software For example when you only want to write software for the SoC HPS Installing the SoC EDS software along with USB II Blaster drivers can provide your development kit JTAG programming environment Installing the Quartus Il Web Edition Software Perform these steps 1 Download the Quartus II Web Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera we
12. the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 Ensure that the CSEL and BSEL jumpers Table 3 4 on page 3 4 and the DIP switch SW2 3 Table 3 1 on page 3 2 are in the factory default positions 2 Attach an Ethernet cable to the HPS Ethernet connector J2 on the upper left of the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address and displays it to the LCD If no IP address is obtained the LCD displays No IP obtained If the system booted the LCD displays Hello Tim If the LCD displays No IP obtained your system partially booted but without Ethernet access If you receive the No IP obtained message Altera recommends that you install the USB virtual COM port drivers to access the Linux system through a terminal window St For more information refer to the Configuring Serial Connection section of the Linux Getting Started page on RocketBoards org L gt There are several reasons why your board may fail to get and IP address in this step m Your port is not active or the cable is not plugged in You do not have a DHCP server a Your DHCP server ran out of addresses a Your DHCP server was not allowed to respond to the board due to security filters such as MAC address filtering September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 4 2
13. up Do not Include HPS in the JTAG chain OFF down Include HPS in the JTAG chain Default Position OFF FPGA HSMC ON up Do not Include the FPGA in the JTAG chain OFF down Include the FPGA in the JTAG chain m ON up Do not include the HSMC connector in the JTAG chain OFF down Include the HSMC connector in the JTAG chain OFF ON MAX ON up Do not include the MAX V system controller in the JTAG chain OFF down Include the MAX V system controller in the JTAG chain 4 Setthe following jumper blocks to match Table 3 4 and Figure 3 1 Table 3 4 Default Jumper Settings J5 Board Reference Board Label 9V Description m SHORT Powers the CFI flash memory device using a 9 V supply for fast write in manufacturing m OPEN Powers CFI flash memory from the default 3 V supply OFF Default Position OPEN J6 JTAG HPS SEL m SHORT Controls the HPS from On Board USB Blaster JTAG master m OPEN Controls the HPS from MICTOR based JTAG master such as DSTREAM or Lauterbach programming cables Also set SW4 1 to ON to remove the On Board USB Blaster II from driving the HPS JTAG input port in this mode SHORT J7 JTAG SEL m SHORT The USB Blaster Il is the source of the JTAG chain m OPEN The Mictor is the source of the JTAG chain SHORT J13 OSC1 CLK SEL m SHORT Selects the on board 25MHz clock m O
14. 1_soc examples max5 directories Ia Newer revisions of this code might be available on the Cyclone V SoC Development Kit page of the Altera website A table with the power rail information is available in the Cyclone V SoC Development Board Reference Manual The Clock Control The Clock Control application sets the 51570 X1 or Si571 X3 programmable oscillators to any frequency between 10 MHz and 810 MHz The frequencies support eight digits of precision to the right of the decimal point The Clock Control application runs as a stand alone application ClockControl exe resides in the install dir NkitsNcycloneVSX 5csxfc6df31 socNexamplesNboard test system directory To start the application click Start gt All Programs gt Altera gt Cyclone V SoC Development Kit lt version gt gt Clock Control For more information about the Si570 Si571 and the Cyclone V development board s 2 clocking circuitry and clock input pins refer to the Cyclone V SoC Development Board Reference Manual September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 18 Chapter 5 Board Test System The Clock Control The Clock Control communicates with the MAX V device on the board through the JTAG bus The 1570 and Si571 programmable oscillators are connected to the MAX V device through a 2 wire serial bus Figure 5 9 shows the Clock Control Si570 tab Figure 5 9 The Clock Control zi xg ANU S RA si570 sisz1 U29
15. 2 4 Chapter 2 Software Installation Installing the USB Blaster Il Driver Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide N DTE RYN l 3 Development Board Setup This chapter explains how to set up the Cyclone V SoC development board and restore default settings Setting Up the Board To prepare the board perform these steps 1 The development board ships with its board switches preconfigured to support the design examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch and Jumper Settings on page 3 1 to return the board to its factory settings before proceeding The development board ships with the Golden System Reference Design binaries stored in the microSD card The microSD card also includes the following m Hardware reference design FPGA image Raw Binary File rbf file m HPS image preloader U Boot and Linux images m File system and software examples 2 Power up the development board by using the included laptop power supply plugged into J22 on the board A Use only the supplied power supply Power regulation circuitry on the board can be damaged by power supplies with greater voltage and a lower rated power supply may not be able to provide enough power for the board Alternatively you can use the an ATX power from a PC by plugging a 4 pin output from that supply to J20 on the develo
16. 2C tab Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 7 Using the Board Test System EEPROM The serial DC EEPROM is 32 Kilobits m Start Address O0x0 m Range 0x1000 m Read Reads data from the 2C EEPROM St For more information on the EEPROM refer to the Cyclone V SoC Development Board Reference Manual RTC Real time clock m Current Time Displays current time stored in RTC memory when you click Read It is not updated automatically m System Time Displays current time from PC and is updated automatically m Read Reads the time from the RTC device on the board m Write System Time to RTC Writes the time to the RTC device on the board September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 8 Chapter 5 Board Test System Using the Board Test System The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board Figure 5 5 shows the DDR3 tab Figure 5 5 The DDR3 Tab Board Test System Write MBps 1228 03 Read MBps 1500 38 Total MBps 2728 41 or control Detected errors 0 Inserted errors 0 Insert Error cear Number of addresses to write and read Detected DDR3 Project The following sections describe the controls on the DDR3 tab Start The Start control initiates DDR3 memory transaction performance analysis Stop The Stop control t
17. 3 September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide iv Contents XCVR LVDS CMOS nune hm er kh eTERS RENE TEEREReLEPquera Ed erp redes 5 14 The Power Monitor 22 e eer d ek E Geeks Qed RR E ER RA ERA ee RR CX G ed 5 15 U34and U26 utes E rir bier Uer eter be Mee he a ber Aden 5 16 Conttols iere e REGERE EERED I A pet bre A A RC ber Y R4 d ONERE ER Td e eS 5 16 The Clock Cotritrol sn beer ere IRI REdeu eu Pp pbpIqGua Ad bide RETE EAD nse nere 5 17 Serial Port Registers eere re Gahan ee EE RE ce tg eles E eK RE 5 18 EXT Ale venue ae olay OS uice Pepe Bene Uti vns VER Vete Valde e SR ee 5 18 Target Frequency 3 4 sta dox aca decisa abeo dv iau ilta dh AEN baute tut a peptides 5 18 Default 222a Eres ee ek ennduaa sera pRu Ed exp e A oed 5 18 Set New Frequency 5 a c5 tan th dee E TI et Ee E duke b gea icit dU ced dos esa gp anes 5 19 Configuring the FPGA Using the Quartus II Programmer 0 000 e eee eee eee ee 5 19 before Configuring esc cocco steer ay eee aon eee ee wa ee eee 5 19 Configuring the FPGA e200 sicscsved eR eee Res px RE I PE creek ni un ere he ipu ka Rue Eger 5 19 Appendix A Programming Flash Memory CET Blasb MemoEy ire cede eet PR etie PR rit ep e einn ede eue edes ep ttem eios A 1 CFI Hash Memory Map 5 eh y Ru hh narod ERES eC REPE HORA ROS angie eq A 1 Programming CFI Flash Using the Quartus II Programmer sssssssssseeeeeeee A 1 Converting sof Piles to apof 2 sods
18. PEN Selects SMA SHORT Cyclone V SoC Development Kit User Guide September 2015 Altera Corporation Chapter 3 Development Board Setup 3 5 Restoring the MAX V CPLD to the Factory Settings Table 3 4 Default Jumper Settings Continued Board Default Reference Board Label Description Position m SHORT JTAG TRST input to HPS driven from the JTAG chain J16 JTAG MIC SEL OPEN m OPEN JTAG TRST input to HPS driven from the MICTOR J26 CLKSELO Selects the HPS clock settings 1 ui pins J27 CLKSEL1 Selects the HPS clock settings 2 pins J28 BOOTSELO Selects the boot mode and source for the HPS 1 SHORT pins J29 BOOTSEL1 Selects the boot mode and source for the HPS 1 p pins J30 BOOTSEL2 Selects the boot mode and source for the HPS 1 SHORT pins m SHORT Select SPI bus access from HPS to Linear Tech daughter card interface through J31 SPI 12C J32 OPEN m OPEN Select 12C bus access from HPS to Linear Tech daughter card interface through J32 2 m SHORT External Mictor 38 pin connector s pin 14 is powered by 3 3V rail J39 SHORT m OPEN External Mictor 38 pin connector s pin 14 is floating Note to Table 3 4 1 For more information refer to the Cyclone V Device Handbook 2 This connection can be software controlled from the HPS GPIO pin F16 on rev D and later boards For more information about the FPGA board settings refer to the Cyclone V SoC Development Bo
19. ammer window click Auto Detect La If you do not see USB Blaster or the board s embedded USB Blaster II listed next to Hardware Setup refer to the Installing the USB Blaster II Driver on page 2 3 Click Add File and open install dir gt kits cycloneVSX_5csxfc6df31_soc factory_recovery max2_PFL_writer po f Turn on the Program Configure option for the pof file Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 Click Auto Detect and a flash device should show up attached to the MAX V in the main window Double click the graphic of the flash device in the device chain pane to display the Device s Properties dialog box Select the flash image pof file install dir NkitsNcycloneVSX 5csxfc6df31 socMfactory recovery output file pof Once the flash image pof is attached in the Quartus II Programmer turn on Page 1 and Option Bits Page 0 is reserved for the GSRD factory design Click Start After the flash writing process has completed power cycle the board and look for the MAX CONF DONE LED to turn ON if successful Altera recommends that you return to the Max V System Controller factory design after completing the flash writing To do so program the Max V with install dir NkitsNcycloneVSX 5csxfc6df31 socMfactory recoveryNmax version pof For more information refer to Restoring the MAX V CPLD to the Factory Settings on
20. ard Reference Manual Restoring the MAX V CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX V CPLD on the development board Make sure you have the Quartus II software installed and then perform these steps 1 Setthe board switches to the factory default settings described in Factory Default Switch and Jumper Settings on page 3 1 5 DIP switch SW4 includes the MAX V device in the JTAG chain 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click Add File and select install dir NkitsNcycloneVSX 5csxfc6df31 socMfactory recovery max lt no_ver gt pof September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 3 6 5 6 Chapter 3 Development Board Setup Restoring the CFI Flash Device to the Factory Defaults Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 Ta Toensure that you have the most up to date factory restore files and product information refer to the Cyclone V SoC Development Kit page of the Altera website Restoring the CFI Flash Device to the Factory Defaults To program the factory image to the flash device in the Quartus II Programmer do the following steps 1 2 10 11 12 On the Tools menu in the Quartus II software click Programmer In the Progr
21. bsite 2 Run the Quartus II Web Edition Software installer 3 Follow the on screen instructions to complete the installation process For a list of the Web Edition capabilities and features refer to the Detailed Comparison sheet If you have difficulty installing the Quartus II software refer to the Altera Software Installation and Licensing Manual Licensing Considerations The Quartus II Web Edition Software is license free and supports Cyclone V devices without any additional licensing requirement This kit also works in conjunction with the Quartus II Subscription Edition Software once you obtain the proper license file To purchase a subscription contact your Altera sales representative Installing the Altera SoC EDS The Altera SoC EDS is a comprehensive tool suite for embedded software development on Altera SoC devices The Altera SoC EDS contains the following m Development tools m Utility programs m Run time software September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 2 2 Chapter 2 Software Installation Installing the Development Kit m Application examples that enable firmware and application software development The SoC EDS includes an exclusive offering of the ARM Development Studio 5 DS 5 Altera Edition Toolkit The ARM DS 5 combines advanced multicore debugging capabilities with FPGA adaptivity With Altera s SignalTap II Logic Analyzer embedded software developers have
22. cate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key 1 2 3 and Numbered steps indicate a list of items when the sequence of the items is important a b C and so on such as the steps listed in a procedure Bea Bullets indicate a list of items when the sequence of the items is not important l The hand points to information that requires special attention The question mark directs you to a software help system with related information Adi The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situat
23. ce Manual For USB Blaster II configuration details refer to the On Board USB Blaster II page Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 5 Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 5 3 shows the GPIO tab Figure 5 3 The GPIO Tab Board Test System E Configure Help About System info GPIO 2c 0022 esc sot Video Character LCD Enter text i Cyclone V Soc Development Kit Detected the GPIO Project The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display La Ifyou exceed the 16 character display limit on either line a warning message appears User DIP Switch The read only User DIP switch control displays the current positions of the switches in the user DIP switch bank Change the switches on the board to see the graphical display change accordingly September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 6 Chapter 5 Board Test System Using the Board Test System User LEDs
24. ched to the MAX V in the main window Double click the graphic of the flash device in the device chain pane to display the Device s Properties dialog box Select the flash image pof file generated from the Quartus II Convert Programming Files dialog box The default file name is output_file pof After the flash image pof is attached in the Quartus II Programmer turn on Page 1 and Option Bits Page 0 is reserved for the GSRD factory design 10 Click Start September 2015 Altera Corporation Appendix A Programming Flash Memory A 3 quad SPI Flash Memory 11 After the flash writing process has completed power cycle the board and look for the MAX CONF DONE LED to turn ON if the writing process is successful 12 Altera recommends that you return to the Max V System Controller factory design after completing the flash writing To do so program the Max V with install dir NkitsNcycloneVSX 5csxfc6df31 socMfactory recovery max lt version gt pof For more information refer to Restoring the MAX V CPLD to the Factory Settings on page 3 5 a For more information on programming flash memory refer to the Parallel Flash Loader Megafunction User Guide and Using FPGA Based Parallel Flash Loader with the Quartus II Software Converting sof Files to a pof To generate a flash programming file you must open the Quartus II software and convert the sof files to pof To convert the files follow these steps 1 Onthe File menu
25. click Convert Programming Files 2 For Programming file type specify Programmer Object File pof and name the file 3 For Configuration device select CFI 512Mb for this kit s CFI device 4 To add the configuration data under Input files to convert select SOF Data 5 Click Add File and browse to the sof files you want to add If you want to store the data from other sof files in a different page click Add SOF page Add the sof files to the new page 6 Select SOF Data and click Properties to set the page number and name 7 Under Address mode for selected pages choose the User Hardware 1 offset as listed in the memory map in Appendix Table A 1 as 0x006E 0000 quad SPI Flash Memory Programming quad SPI Flash Using the Quartus Il Programmer Although the quad SPI flash is not programmed by factory default you can program this device using quartus hps exe that resides in the quartus bin directory To use this tool open a command window and change directories to your 13 0 or later installation e g c altera 13 0 quartus bin To program an entire file to quad SPI flash starting at address 0 type quartus hps exe c programming cable index o P flash boot image bin For a typical setup where the Cyclone V SoC board is the only board connected to the PC you can detect the quad SPI flash by running the following command quartus hps exe o 1 cl enter September 2015 Altera Corporation Cyclone V SoC Developm
26. consumption and thermal modeling to determine whether your application requires additional cooling For information about measuring board and FPGA power in real time refer to The Power Monitor on page 5 15 For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs Use the following links in Table 1 1 to check the Altera website for other related information Table 1 1 Related Links and Documents Altera Website Link Cyclone V SoC Development Kit page Information Latest board design files reference designs kit installation for Windows and Linux RocketBoards org ARM Cortex A SoC Open source community website supporting SoC development including Altera and Partner SoC development kit targets and related designs and documentation On the dual core ARM Cortex A9 MPCore processor Getting Started for Software Developers Cyclone V SoC Development Kit Hardware Developer Resource Center Developing software for the Cyclone V SoC Developing SoC Hardware designs on the development kit Altera SoC Embedded Design Suite User Guide Installing the SoC EDS and ARM DS 5 Preloader user guide Hard Processor System HPS Flash programmer Bare Metal and Linux Compiler Yocto plugin Debugging GSRD User Manual page The Golden System Reference Design GSRD demonstrates the HPS features and the ability to communicate between HPS to
27. d writes September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 10 Chapter 5 Board Test System Using the Board Test System The SDI Video Tab The SDI Video tab allows you to test the SDI video interface on your board Figure 5 6 shows the SDI Video tab Figure 5 6 The SDI Video Tab Board Test System E i 215 xl Configure Help About System info ieero zc poss Rsc sor Wied Pattern generator Pattern Intensity SDI standard Color bar C 75 C SD HD C Pathological 100 c 7 Clock source Lock to host Lock to input r Data test Data rate 311 15MBps Start Stop Freq 2970 32MHz bits 2 396522e 11 Insert Error Clear Status Inserted errors 0 PMA Setting PLL lock Yes Detected errors 0 Pattern s Yes BER L4 pres7 v Detected SDI Video Project The following sections describe the controls on the SDI Video tab Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 11 Using the Board Test System Pattern Generator This control specifies the test pattern to output to the monitor The following choices are available Pattern m Color bar Specifies a video color bar pattern with eight vertical color bars as shown in table Table 5 1 Table 5 1 HDMI Color Bar Test Pattern Color
28. ent Kit User Guide A 4 Appendix A Programming Flash Memory SD Card Memory Using this tool requires that the board be placed into quad SPI boot mode by setting BOOTSEL1 J29 shunt to the 1 2 position The default position is 2 3 SD card The board must be power cycled after changing this jumper for the settings to take effect For help and more options type quartus hps exe help Te For more information refer to the SoC Board QSPI Boot page on RocketBoards org SD Card Memory Programming the SD Card Boot Image The SD card is the default boot source for the HPS as selected by the BSEL jumpers The socket is designed to accept microSD cards The SoC development kit comes with a microSD card micro to standard SD card adapter and a USB programming adapter To program the SD card do the following steps 1 9o OW OX UH Cyclone V SoC Development Kit User Guide Insert the SD card into the USB programming adapter and insert the programming adapter into a USB port on your PC In Windows you should see a pop up window asking what you d like to do with the flash device Click Cancel but note the drive letter it is mounted as You cannot drag and drop files onto the SD card because the file system is different You need to use a disk imaging program such as Win32DiskImager for Windows or the dd command in Linux You can also use a Cygwin installation such as the NIOS II Embedded Development System Nios II EDS Sta
29. erminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last clicked Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 9 Using the Board Test System m Write MBps Read MBps and Total MBps Show the number of bytes of data analyzed per second The data bus is 72 bits wide and the frequency is 400 MHz double data rate 800 Mbps per pin equating to a theoretical maximum bandwidth of 3200 Megabits per second or 400 MBps Error Control The Error control control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transaction stream m Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads an
30. full chip visibility and control T Forthe steps to install the SoC EDS Design Suite refer to the Altera SoC Embedded Design Suite User Guide Installing the Development Kit Perform these steps 1 Download the Cyclone V SoC Development Kit installer from the Cyclone V SoC Development Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website 2 Start the Cyclone V SoC Development Kit installer 3 Choose an installation directory that is relative to the Quartus II software installation directory Follow the on screen instructions to complete the installation process 4 For the latest issues and release notes Altera recommends that you review the readme txt located in the root directory of the kit installation The installation program creates the Cyclone V SoC Development Kit directory structure shown in Figure 2 1 Figure 2 1 Cyclone V SoC Development Kit Installed Directory Structure install dir The default Windows installation directory is C altera lt version gt kits cycloneVGX 5cgxfc7df31 fpga board design files fes demos fii documents examples fig factory recovery Note to Figure 2 1 1 Early release versions might have slightly different directory names Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 2 Software Installation 2 3 Installi
31. gabytes per second MBps m Freq Displays the data rate frequency in MHz which is equivalent to Mbps m Bits Displays the number of bits transmitted since clicking Start Inserted errors Displays the number of errors inserted by clicking Insert Error button Detected errors Displays the number of bit errors detected by the error checking circuitry BER Displays the bit error rate of the interface PLL lock Displays Yes if the SDI PLL is locked Pattern Sync Displays Yes if the receiver has detected the input data pattern Start Starts the PRBS data test and begins to monitor and update screen with live test results Stop Stops the PRBS data test m Insert Error Inserts an error into an SDI data stream that is detected by the receiver when in loopback using the included video cable m Clear Clears the Detected errors counter m PMA Setting Opens the PMA settings window that allows for adjusting the analog transceiver settings such as output voltage loopback settings and equalization m PRBS list 5elects the transmit pattern and sets the receive error detection circuitry to expect the same pattern for use in loopback testing Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 13 Using the Board Test System The HSMC Tab The HSMC tab allows you to perform loopback tests on the XCVR LVDS and CMOS ports Figure 5 7 shows the HSMC tab
32. highlights in the board picture around the corresponding components for each tab Figure 5 1 Board Test System Graphical User Interface zig Configure Help About Detected the GPIO Project System info cero rc 0022 esc SDI Video r Board information Board Name Cyclone V SoC Development Board Board P N 6XX 44104R Serial number 5SGXAS000000 18 Factory test version 1 MAC1 00 11 22 33 44 55 MAC2 66 77 88 99 aa bb HPS MAC cc dd ee 00 11 MAX V ver USB BlasterII on localhost USB 2 1 SOCVHPS 1 2 SCS EBA6ES XFC6C6ES G2 3 5M 1270ZF324 2210Z EPM2210 3 September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 2 Chapter 5 Board Test System Preparing the Board for the Board Test System Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab After successful FPGA configuration the appropriate tab appears that allows you to exercise the related board features The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the JTAG bus to the MAX II device you can measure the power of any design in the FPGA including your own designs The Boa
33. ion that can damage or destroy the product or your work A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document A Electromagnetic interference caused by modification of the kit contents is the sole responsibility of the user CAUTION This equipment is designated for use only in an industrial research environment Cyclone V SoC Development Kit User Guide CE September 2015 Altera Corporation
34. nce Manual microSD flash memory card Debug header breakout board high speed mezzanine card HSMC Loopback daughtercard HSMC Power supply and cables The kit includes the following items m Power supply and AC adapters for North America Japan Europe and the United Kingdom m USB cable m Ethernet cable m SMBcable Before You Begin Before using the kit or installing the software check the kit contents and inspect the boards to verify that you received all of the items listed in Quick Start Guide printout in the box If any of the items are missing contact Altera before you proceed Inspect the Boards To inspect each board perform these steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment A Without proper anti static handling you can damage the board CAUTION September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide Chapter 1 About This Kit References 2 Verify that all components on the boards appear in place and intact Ia Intypical applications with the Cyclone V development board a heat sink is not References necessary However under extreme conditions or for engineering sample silicon the board might require additional cooling to stay within operating temperature guidelines The board has two holes near the FPGA that accommodate many different heat sinks including the Dynatron V31G You can perform power
35. ng Flash Memory CFI Flash Memory m Program the CFI flash memory devices connected to the CPLD I O pins Figure A 1 shows an Altera CPLD configured as a bridge to program the CFI flash memory device through the JTAG interface Figure A 1 Programming the CFI Flash Memory With the JTAG Interface MAX II CPLD Altera i Quartus II Configuration Data FPGA Sofware t s rF 7 7 gt via JTAG epee ae E Common Altera FPGA Not Used Flash for Flash Programming Interface CFI Flash Memory Perform the following steps to program a user design to the flash device in the Quartus II Programmer The following flash writing procedure blinks the SEL 2 1 and 0 LEDs and does not support the Power Monitor Clock Control or other logic functions 1 2 On the Tools menu in the Quartus II software click Programmer In the Programmer window click Auto Detect La If you do not see USB Blaster or the board s embedded USB Blaster II listed next to Hardware Setup refer to the Installing the USB Blaster II Driver on page 2 3 Click Add File and open lt install dir gt kits cycloneVSX_5csxfc6df31_soc factory_recovery max2_PFL_writer po f Turn on the Program Configure option for the pof file Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 Click Auto Detect and a flash device should show up atta
36. ng the USB Blaster II Driver Table 2 1 lists the file directory names and a description of their contents Table 2 1 Installed Directory Contents Directory Name board design files Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a starting point for a new prototype board design demos Contains demonstration applications if available documents Contains the kit documentation examples Contains the sample design files for the Cyclone V SoC Development Kit factory recovery Contains the original data programmed onto the board before shipment Use this data to restore the board with its original factory contents Installing the USB Blaster Il Driver The Cyclone V development board includes integrated USB Blaster circuitry for FPGA programming However for the host computer and board to communicate you must install the On Board USB Blaster II driver on the host computer Installation instructions for the On Board USB Blaster II driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions For USB Blaster II configuration details refer to the On Board USB Blaster II page September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide
37. or exe resides in the install dir NKkitsNcycloneVSX 5csxfc6df31 socNexamplesNboard test system directory In Windows click Start gt All Programs gt Altera gt Cyclone V SoC Development Kit version Power Monitor to start the application The Power Monitor communicates with the MAX V device on the board through the JTAG bus A power monitor circuit attached to the MAX V device allows you to measure the power that the Cyclone V FPGA is consuming The Power Monitor measures power over an I C bus with multiple masters You might see some glitches in the measurements if the HPS is booted The GSRD and other Linux images access the IC bus periodically and cause inaccurate measurements for a cycle or two These should go away and likely return to an accurate steady state measurement for most designs September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 5 16 Cyclone V SoC Development Kit User Guide Chapter 5 Board Test System The Power Monitor Figure 5 8 shows the Power Monitor Figure 5 8 The Power Monitor A LTC2978 Monitor Ac xl ANU S RA U34 0x5C U26 0x5E 400mA 400mA 1 1V_HPS 197 998mA 2 5V FPGA 253 906mA 1100 10mV 100mA 2499 88mV 100mA 1 5V HPS 53 385mA 1 5V FPGA 1 602mA 1499 88mV 1499 88mV 400mA 800mA 2 5V HPS 233 643mA 1 1V VCC 671 875mA 2500 00mV 1100 10mV 100mA 100mA 3 3V HPS 25 940mA 3300 42mV Temp on 2978 38 75C Temp on 2978 39 31C
38. ormation sesoses ens rev depu rA de E bee da prd c V dA Ea REG eg 5 3 JT AG Chatn oe a kem bed pU E REG hee eae ee GUERRERO ER AR ER PNE REOR ded 5 4 The GPIO Tab 2 buon uus USER p sou eat xa bate eire VE peti va tes 5 5 Character LCD zi eeretceraex pte Ph Rie Fiestas RAS 4 bera d Racer eaim 5 5 User DIP Switch uero RHERE EHE EE RE Na abr ge ER ae FACH RU doe sis 5 5 User LEDS i2 i EH eU EE REP C E Seeds CCP ICH C eRRE RE CHRPEN RR I RR e RA 5 6 Push Button Switches uid chee tat keds Yee eee Ove ee d 0a se be Riad eu re puces 5 6 The RC Tabs cision es aces oh ee bh ck he RARER BRAS Pho PG X Pie ee E te A add ett RS 5 6 EEPROM zv doce bebes boas dy avete gu bate dede dde tts deve And can ek a des dea o re eee ad 5 7 d a T 5 7 The DDR3 Tab gv vui REEL UPS IVa ers UESTRE RCM VE ES V eit va YR euis 5 8 OLarb acces acta hse PS ERT bI EUR EDCCEPPICUPTEIGGng ad rbreRrQeua qu rdbaudu AA E eR 5 8 SOP m 5 8 Performance Indicators lleeeeeeeeeeeee eR m a 5 8 Error Control 44 ede tRIRI Eben pes kx REX ORENSE Sh eRe a v EE HA Puds 5 9 Number of Addresses to Write and Read 0 ccc ununun nnana 5 9 The SDI Video Tab ERR Rx eR bee pee en neue nrGucert eer44xc bunk eder 5 10 Pattern Generators iiss bates e ELIO Gd PEG Ge Ed b G KELLER GG EX REG DYEOCYG d E e XE 5 11 The HSMC Tab uve hb eux hei eevee bends koe ee eels RR EV aate be vade s 5 13 po et EE 5 1
39. ors counter m PMA Setting Opens the PMA settings window that allows for adjusting the analog transceiver settings such as output voltage loopback settings and equalization The following settings are available for analysis m Serial Loopback Routes the selected TX output signal back to the RX input signal on chip to verify operation without using an external loopback board m VOD Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m Pre Specifies the amount of pre emphasis on the pre tap of the transmitter buffer m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Second post Specifies the amount of pre emphasis on the second post tap of the transmitter buffer September 2015 Altera Corporation Chapter 5 Board Test System 5 15 The Power Monitor Ia Support for this tap is device and software version dependent m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer m PRBS Selects the transmit pattern and sets the receive error detection circuitry to expect the same pattern for use in loopback testing The Power Monitor The Power Monitor measures and reports current power information To start the application click Power Monitor in the Board Test System application You can also run the Power Monitor as a stand alone application PowerMonit
40. page 3 5 The flash writer version blinks the SEL 2 1 and 0 LEDs and does not support the Power Monitor Clock Control or other logic functions Use the flash writer only for flash programming Cyclone V SoC Development Kit User Guide September 2015 Altera Corporation Chapter 3 Development Board Setup 3 7 Restoring the CFI Flash Device to the Factory Defaults Ta Toensure that you have the most up to date factory restore files and information about this product refer to the Cyclone V SoC Development Kit page of the Altera website September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 3 8 Cyclone V SoC Development Kit User Guide Chapter 3 Development Board Setup Restoring the CFI Flash Device to the Factory Defaults September 2015 Altera Corporation N DTE RYN 4 Board Update Portal The Board Update Portal web page provides links to useful information on the Altera website You can use this web page to interact with your board m Blinking LEDs m Writing text messages to the LCD m Mouse over the board photo to view features The Board Update Portal web page is served by the web server application running on the HPS on your board Connecting to the Board Update Portal Web Page Ensure that you have the following setup or installed m APC with a connection to a working Ethernet port on a DHCP enabled network m A separate working Ethernet port connected to the same network for
41. pment board Make sure that the ATX supply is off when connecting to the board Hot swap is not supported and may damage the board s power supplies and other downstream devices CAUTION When configuration is complete the Config Done LED D38 illuminates signaling that the Cyclone V device configured successfully Factory Default Switch and Jumper Settings This section shows the factory settings Figure 3 1 for the Cyclone V SoC development board These settings ensure that the Board Update Portal and Golden System Reference design function properly September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 3 2 Chapter 3 Development Board Setup Factory Default Switch and Jumper Settings 5 The SD card Max V system controller and common flash interface CFI flash are already programmed with the factory default files For more information refer to Appendix A Programming Flash Memory Figure 3 1 Switch Locations and Default Settings w SECURITY 01234 m 3210 3210 Ime F o SW1 RzssveErY pex sws HAAN PP MSEL p ae HWA Ir go mm a o 528 J5 J39 p Fr JTAG jm J6 HPS SEL JTAG qm J7 SEL OSC1 CLK SEL LE J13 JTAG MIC SEL mm J16 9 J26 J27 J28 J29 J30 nmm mmm mmu mmu mum CLKSELO CLKSEL BOOTSELO BOOTSEL1 BOOTSEL2 cb 12C J81 To restore the swi
42. ra Corporation Cyclone V SoC Development Kit User Guide 5 14 Cyclone V SoC Development Kit User Guide Chapter 5 Board Test System Using the Board Test System XCVR LVDS CMOS These groups displays the following XCVR LVDS CMOS status information during the loopback test m Data rate Displays the current XCVR data rate in megabytes per second MBps m Freq Displays the data rate frequency in MHz which is equivalent to Mbps m Bits Displays the number of bits transmitted since clicking Start m Inserted errors Displays the number of errors inserted by clicking Insert Error button m Detected errors Displays the number of bit errors detected by the error checking circuitry m BER Displays the bit error rate of the interface m PLL lock Displays Yes if the SDI PLL is locked m Pattern Sync Displays Yes if the receiver has detected the input data pattern m Start Starts the PRBS data test and begins to monitor and update screen with live test results m Stop Stops the PRBS data test m Insert Error Inserts an error into a data stream that is detected by the receiver when in loopback using the included video cable With the Insert Error there are differences among the three ports XCVR inserts 4 errors at 1 click due to 4 test control blocks in the design LVDS inserts 3 errors at 1 click due to 3 test control block in the design CMOS inserts 1 error at 1 click m Clear Clears the Detected err
43. rd Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board for the Board Test System With the power to the board off follow these steps 1 Plug the included USB cable from J37 USB Blaster II interface to the host computer s USB port 2 Ensure that the development board switches and jumpers are set to the default positions as shown in the Factory Default Switch and Jumper Settings section starting on page 3 1 Te For more information about the board s DIP switch and jumper settings refer to the Cyclone V SoC Development Board Reference Manual To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System Navigate to the lt install dir NkitsNcycloneVSX 5csxfc6df31 socNexamplesNboard test system directory and run the BoardTestSystem exe application To run the BTS in Windows you can also click Start gt All Programs gt Altera gt Cyclone V SoC Development Kit lt ve
44. rsion gt gt Board Test System A GUI appears displaying the application tab that corresponds to the design running in the FPGA Typically the board will not be pre programmed with a BTS design One must be loaded using the Configure menu as described in the next section Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 5 Board Test System 5 3 Using the Board Test System Using the Board Test System This section describes each control in the BTS The Configure Menu Use the Configure menu to select the design you want to use Each design example on this menu tests different board features that corresponds to one or more application tabs For example if you select Configure with GPIO Design the System Info GPIO and I2C tabs become active Figure 5 2 The Configure Menu Help About Configure with GPIO Design Configure with DDR3 Design Configure with Transceiver Design Configure with Video Design Exit Ctrl Q The System Info Tab The System Info tab shows board s current configuration Figure 5 1 on page 5 1 shows the System Info tab The tab displays the contents of the MAX V registers the JTAG chain the board s MAC address the flash memory map and other details stored on the board The following sections describe the controls on the System Info tab Board Information The Board information controls display static information about your board m Board Name Indicates
45. rt the Nios II Command Shell by clicking Start All Programs Altera version Nios II EDS Nios II Command Shell At this shell type the command 1s dev enter The SD card will generally be mounted as sda sdb or sdc etc depending on other devices that may be present To be sure which is correct remove the card and type 1s dev enter Look for what changed since you type the command the first time Re insert the SD card and verify the name once more Type dd if boot image filename img of dev sd card name enter Linux users use the same dd commands a Be careful using this programming command as it will overwrite whatever is found on the device pointed to in the of command For more information refer to the SoC EDS User Guide and RocketBoards org September 2015 Altera Corporation N DTE BAAN Additional Information This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes September 2015 1 2 Updates for Rev E PCB using Enpirion EN23x2 power products November 2013 1 1 Updates for production silicon and rev D PCB using Enperion power products May 2013 1 0 Initial release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Con
46. s II EDS just as the hardware design was created using the Quartus II software CFI Flash Memory CFI Flash Memory Map A CAUTION Table A 1 shows the default memory contents of the 512 Mb CFI flash device Table A 1 Byte Address Flash Memory Map Block Description KB Size Address Range Unused 44711 0x0145 635C O3FF FFFF User hardware 2 6872 0x00DA 0000 0145 635B User hardware 1 6872 0x006E 0000 00D9 635B Factory hardware 6872 0x0002 0000 006D 635B PFL option bits 32 0x0001 8000 0001 8080 Altera recommends that you do not overwrite the factory hardware images unless you are an expert with Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the CFI Flash Device to the Factory Defaults on page 3 6 Programming CFI Flash Using the Quartus Il Programmer You can use the JTAG interface in Altera CPLDs to indirectly program the flash memory device The Altera CPLD JTAG block interfaces directly with the logic array in a special JTAG mode This mode brings the JTAG chain through the logic array instead of the Altera CPLD boundary scan cells BSC The PFL megafunction provides JTAG interface logic to do the following m Convert the JTAG stream provided by the Quartus II software September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide A 2 Cyclone V SoC Development Kit User Guide Appendix A Programmi
47. sition of the switch with the board orientation as shown in Figure 3 1 Important The default MSEL pin settings are set to all zeroes ON to select the fast passive parallel x16 mode For power up configuration from MAX V and CFI flash ensure that the MAX V design uses this same mode as does in the design in the install dir NkitsNcycloneVSX 5csxfc6df31 socNexamples max5 directory Table 3 2 SW3 DIP Switch Settings Default Position Board Lahel Function Switch Switch 1 has the following options 1 MSELO m ON up MSELO is 0 ON m OFF down MSELO is 1 Switch 2 has the following options 2 MSEL1 m ON up MSEL1 is 0 ON m OFF down MSEL1 is 1 Switch 3 has the following options 3 MSEL2 m ON up MSEL2 is 0 ON m OFF down MSEL2 is 1 Switch 4 has the following options 4 MSEL3 m ON up MSEL3 is 0 ON m OFF down MSEL3 is 1 Switch 5 has the following options 5 MSEL4 m ON up MSEL4 is 0 ON m OFF down MSEL4 is 1 September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 3 4 Chapter 3 Development Board Setup Factory Default Switch and Jumper Settings 3 Set the DIP switch bank SW4 to match Table 3 3 and Figure 3 1 In the following table up and down indicates the position of the switch with the board orientation as shown in Figure 3 1 Table 3 3 SW4 JTAG DIP Switch Settings Switch Board Label HPS Function ON
48. tact Contact Method Address Technical support Website www altera com support f 2 Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Initial Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility names and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets gt For example file name and lt project name gt poft file September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Initial Capital Letters Indi
49. tated upitaueest scum True edes 1 1 Inspect the Boards i cese perep web hi eet tae ted OU Pe Veen peak wee pas e 1 1 References cas ded de er e EenrRE ASR ER DCCERETaa E a Re sh EL eee rers 1 2 Chapter 2 Software Installation Installing the Quartus II Web Edition Software ssssseessseeeee eene 2 1 Licensing Considerations esee eee eer pter die ascend eem edad tee aede dus geod den edunt 2 1 Installing the Altera SOC EDS 2 1 oc e n 2 1 Installing the Development Kit coe eps cc pereen erkese ka kee III 2 2 Installing the USB Blaster II Driver sricrceretid eiir pr hi eee 2 3 Chapter 3 Development Board Setup Setting Up the Board ecce eee gerne tte eedem i Ree dece ee qe E h 3 1 Factory Default Switch and Jumper Settings 0 6 66 eee eens 3 1 Restoring the MAX V CPLD to the Factory Settings ssssssseeeeeeeeeee eee 3 5 Restoring the CFI Flash Device to the Factory Defaults 6 0c ccc en eee 3 6 Chapter 4 Board Update Portal Connecting to the Board Update Portal Web Page 0 00 4 1 Chapter 5 Board Test System Preparing the Board for the Board Test System sse 5 2 Running the Board Test System sssssssssssssellee eee nnn 5 2 Using the Board Test System 0 26 cee ee eene hee 5 3 The Configure Menu vex seo RI y dees yon eee UR Pes eee bea due ale Bee we vae aa ep 5 3 The System mio Ta Duosi i ec acta aes sess tud eU opc ees aie vue 5 3 Board Inf
50. tches to their factory default settings perform these steps 1 Set the DIP switch bank SW2 to match Table 3 1 and Figure 3 1 In the following table ON indicates the switch is to the left according to the board orientation as shown in Figure 3 1 Table 3 1 SW2 DIP Switch Settings Part 1 of 2 F Board 2 Default Switch Label Function Position Switch 1 has the following options 1 CLK125A m ON 0 On board oscillator is disabled OFF m OFF 1 On board oscillator is enabled Switch 2 has the following options m ON 0 On board programmable oscillator is 2 Si570 enabled ON m OFF 1 On board programmable oscillator is disabled Cyclone V SoC Development Kit September 2015 Altera Corporation User Guide Chapter 3 Development Board Setup 3 3 Factory Default Switch and Jumper Settings Table 3 1 SW2 DIP Switch Settings Part 2 of 2 Board Default Switch Lahel Function Position Switch 3 has the following options 3 FACT LOAD m ON 0 Load the factory design starting at OFF 0x20000 at power up m OFF 1 Parallel flash loader PFL disabled Switch 4 has the following options m ON 0 On Board USB Blaster I sends 4 Security FACTORY command at power up OFF m OFF 1 On Board USB Blaster II does not send FACTORY command at power up 2 Set the DIP switch bank SW3 to match Table 3 2 and Figure 3 1 In the following table up and down indicates the po
51. the official name of the board m Part number Indicates the part number of the board m Serial number Indicates the serial number of the board Factory test version Indicates the version of the Board Test System currently running on the board m MAC1 Indicates the MAC address of the board s ENET1 10 100 port m MAC2 Indicates the MAC address of the board s ENET2 10 100 port m HPS MAC1 Indicates the MAC address of the board s HPS 10 100 1000 Ethernet port m MAX V ver Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir NkitsNcycloneVSX 5csxfc6df31 socNexamples directory Newer revisions of this code might be available on the Cyclone V SoC Development Kit page of the Altera website September 2015 Altera Corporation Cyclone V SoC Development Kit User Guide 9 4 Chapter 5 Board Test System Using the Board Test System JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Cyclone V device is always the first device in the chain The JTAG chain is normally mastered by the On board USB Blaster II IL If you plug in an external USB Blaster cable to the JTAG header J23 the On Board USB Blaster II is disabled La JTAG DIP switch bank SW4 selects which interfaces are in the chain Refer to Table 3 3 on page 3 4 for detailed settings a For details on the JTAG chain refer to the Cyclone V SoC Development Board Referen

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