SCFIFO and DCFIFO IP Cores User Guide
Contents
1. lpm_type String Identifies the library of parameterized modules LPM entity name The values are SCFIFO and DCFIFO maximize_speed Integer Specifies whether or not to optimize for area or speed The values are 0 through 10 The values 0 1 2 3 4 and 5 result in area optimization while the values 6 7 8 9 and 10 result in speed optimization This parameter is applicable for Cyclone II and Stratix II devices only overflow_checking String Specifies whether or not to enable the protection circuitry for overflow checking that disables the wrreq port when the FIFO IP core is full The values are ON or OFF If omitted the default is ON underflow_checking String Specifies whether or not to enable the protection circuitry for underflow checking that disables the rdreq port when the FIFO IP core is empty The values are ON or OFF If omitted the default is ON Note that reading from an empty SCFIFO gives unpredictable results Only applicable for the DCFIFO IP core SCFIFO and DCFIFO IP Cores User Guide J send Feedback Altera Corporation SCFIFO and DCFIFO Parameters UG MFNALT_FIFO 2014 12 17 To delay_ rdusedw delay_wrusedw String Specify the number of register stages that you want to internally add to the rdusedw or wrusedw port using the respective parameter The default value of 1 adds a single register stage to the output to improve its perf2. Nai wielk weg data OO 6 A F A 8 A 9S A A A B ee eee wrfull tdelk tdreq tdempty q po KT a 4 The required functional timing for the DCFIFO as described previously is also applied to the SCFIFO The difference between the two modes is that for the SCFIFO the wrreq signal must meet the functional timing requirement based on the fu11 signal and the rdreg signal must meet the functional timing requirement based on the empty signal SCFIFO and DCFIFO Output Status Flag and Latency The main concern in most FIFO design is the output latency of the read and write status signals SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback UG MFNALT_FIFO 12 SCFIFO and DCFIFO Output Status Flag and Latency 2014 12 17 Table 4 Output Latency of the Status Flags for SCFIFO This table shows the output latency of the write signal wrreq and read signal rdreq for the SCFIFO according to the different output modes and optimization options Output Mode Optimization Option Output Latency in number of clock cycles wrreq rdreqto full 1 wrreg to empty 2 Speed rdreq to empty 1 wrreq rdreq to usedw 1 Normal rdreq to q 1 wrreq rdreq to full 1 wrreq rdreqto empty 1 Area wrreq rdreq to usedw 1 rdreq to q 1 wrreq rdreq to full 1 wrreg to empty 3 rdreq to empty 1 Speed wrreq rdreq to usedw 1 wrreq tog 3
3. wrregq to q lwrclk following l rdclk 5 rdreg to rdempty 1 rdclk rdreq to wrempty 1 rdclk following nwrelk 5 rdreq to rfull 1 rdclk rdreq to wrfull l rdclk following n wrelk 5 rdreq to rdusedw 2 rdclk rdreq to wrusedw 1 rdclk following n 1 wrelk rdreq to q 1 rdclk SCFIFO and DCFIFO Metastability Protection and Related Options The FIFO parameter editor provides the total latency clock synchronization metastability protection area and fmax options as a group setting for the DCFIFO Table 7 DCFIFO Group Setting for Latency and Related Options This table shows the available group setting Lowest latency but requires synchronized clocks This option uses one synchronization stage with no metastability protection It uses the smallest size and provides good fmax Select this option if the read and write clocks are related clocks 3 The output latency information is only applicable for Arria GX Stratix and Cyclone series except for Stratix Stratix GX Hardcopy Stratix and Cyclone devices It might not be applicable for legacy devices such as APEX and FLEX series of devices 4 The number of n cycles for rdc1k and wrclk is equivalent to the number of synchronization stages and are related to the wRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters For more information about how the actual synchronization stage n is related to the parameters se
4. Show ahead rdreqto q 1 wrreq rdreq to full 1 wrreg to empty 2 rdreq to empty 1 Area wrreq rdreq to usedw 1 wrreg to g 2 rdreqto q 1 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON Setting the parameter to oFF is equivalent to area optimization The information of the output latency is applicable for Stratix and Cyclone series only It may not be applicable for legacy devices such as the APEX and FLEX series For the Quartus II software versions earlier than 9 0 the normal output mode is called legacy output mode Normal output mode is equivalent to setting the LpM_SHOWAHEAD parameter to orr For Show ahead mode the parameter is set to on Altera Corporation SCFIFO and DCFIFO IP Cores User Guide GJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Output Status Flag and Latency 13 Table 5 LE Implemented RAM Mode for SCFIFO and DCFIFO Output Mode Optimization Option Output Latency in number of clock cycles wrreq rdreq to full 1 wrreg to empty 2 Speed rdreq to empty 1 wrreg rdreq to usedw 1 Normal rdreqto q 1 wrreq rdreq to full 1 wrreg rdreq to empty 1 Area wrreq rdreq to usedw 1 rdreqto q 1 ch head wrreq rdreq to full 1 ow ahea wrreg to empty 3 rdreq to empty 1 Speed w
5. You can set the parameter to ON or OFF for the SCFIFO or the DCFIFO that do not target Stratix II Cyclone II and new devices This parameter does not apply to these devices because the q output must be registered in normal mode and unregistered in show ahead mode for the DCFIFO almost_full_value Integer No Sets the threshold value for the almost_fu11 port When the number of words stored in the FIFO IP core is greater than or equal to this value the almost_full port is asserted almost_empty_value Integer No __ Sets the threshold value for the almost_empty port When the number of words stored in the FIFO IP core is less than this value the almost_empty port is asserted allow_wrcycle_when_full String No _ Allows you to combine read and write cycles to an already full SCFIFO so that it remains full The values are ON and OFF If omitted the default is orr Use only this parameter when the OVERFLOW_CHECKING parameter is set to ON intended_device_family String No Specifies the intended device that matches the device set in your Quartus II project Use only this parameter for functional simulation SCFIFO and DCFIFO Functional Timing Requirements The wrreq signal is ignored when FIFO is full if you enable the overflow protection circuitry in the FIFO parameter editor or set the ovERFLOW_CHECKING parameter to on The rdreg signal is ignored when FIFO is empty if you ena
6. E module declaration module dcfifo8x32 aclr data m wfull Module s port declarations input aclr input 31 0 data output wrfull Module s data type declarations and assignments wire rdempty_w wire wrfull wrfull_w wire 31 0 q q_w Instantiates dcfifo megafunction Must declare all the ports available from the megafunction and define the connection to the module s ports Refer to the ports specification from the user guide for more information about the megafunction s ports syntax lt megafunction s name gt lt given an instance name gt dcfifo instl syntax lt dcfifo s megafunction s port gt lt module s port wire gt wrclk wrclk rdclk rdreq wrusedw left the output open if it s not used Start with the keyword defparam defines the parameters and value assignments Refer to parameters specifications from the user guide for more information about the megafunc tion s parameters defparam syntax lt instance name gt lt parameter gt lt value gt instl intended_device_family Stratix Iri instl lpm_numwords 8 instl wrsync_delaypipe 4 endmodule Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 Design Example 21 Design Example In this design example the data from the ROM is required to be transferred to the RAM Assuming the ROM and RAM are driven b
7. bits can corrupt the counter sequence Taking a counter width with 3 bit wide and assuming it is transferred from write clock domain to read clock domain Assume all the counter bits have 0 delay relative to the destina tion clock excluding the bit 0 that has delay of 1 clock period of source clock That is the skew of the counter bits will be 1 clock period of the source clock when they arrived at the destination registers The following shows the correct gray code counter sequence 000 001 011 010 Lles which then transfers the data to the read domain and on to the destination bus registers Because of the skew for bit 0 the destination bus registers receive the following sequence 000 000 01t 01l Lirras Because of the skew a 2 bit transition occurs This sequence is acceptable if the timing is met If the 2 bit transition occurs and both bits violate timing it may result in the counter bus settled at a future or previous counter value which will corrupt the DCFIFO Therefore the skew must be within a certain skew to ensure that the sequence is not corrupted Related Information skew_report tcl Use the skew_report tcl to analyze the actual skew and required skew in your design Document Revision History This table lists the document revision history for this user guide Altera Corporation SCFIFO and DCFIFO IP Cores User Guide GJ Send Feedback UG MFNALT_FIFO gt gt 2014 12 17 Document Revision Hi
8. ensure whether or not a valid write request operation can be performed regardless of the target device empty Owrempty 2 4 rdrempty o 4 Output When asserted the FIFO IP core is considered empty Do not perform read request operation when the FIFO IP core is empty In general the wrempty signal is a delayed version of the rdempty signal However for Stratix III devices and later the wrempty signal function as a combinational output instead of a derived version of the rdempty signal Therefore you must always refer to the rdempty port to ensure whether or not a valid read request operation can be performed regardless of the target device almost_full o almost_empty Output Output Asserted when the usedw signal is greater than or equal to the almost_full_value parameter It is used as an early indication of the fu11 signal Asserted when the usedw signal is less than the almost_ empt y_value parameter It is used as an early indication of the empty signal SCFIFO and DCFIFO IP Cores User Guide Send Feedback Altera Corporation 6 SCFIFO and DCFIFO Parameters UG MFNALT_FIFO 2014 12 17 a a S a usedaw wrusedw 4 rdusedw 4 Output Show the number of words stored in the FIFO Ensure that the port width is equal to the 1pm_widthu parameter if you manually instantiate the SCFIFO IP core or the DCFIFO IP core For the DCFIFO_MIXED_ WIDTH IP c
9. In the IDLE state the ram_addr ff to accommodate the increment of the RAM address in the INCADR state so that the first data read is stored at ram_addr 00 in the wRITE state INCADR The read controller transitions from the IDLE state to the INCADR state if the fifo_ rdempty signal is low In the 1ncanpr state the read controller drives the fi fo_rdreq signal to high and requests for read operation from the DCFIFO The ram_adar signal is increased by one ff to 00 so that the read data can be written into the RAM at ram_ addr 00 WRITE From the INCADR state the read controller always transition to the wRITE state at the next rising clock edge In the wRITE state it drives the ram_wren signal to high and enables the data writing into the RAM at ram_addr 00 At the same time the read controller drives the ram_rden signal to high so that the newly written data is output at q at the next rising clock edge Also it increases the word_count signal to 1 to indicate the number of words successfully read from the DCFIFO The same state transition continues as stated in INCADR and WRITE states if the fifo_ rdempty signal is low SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback UG MFNALT_FIFO 24 Design Example 2014 12 17 Figure 9 Write Operation when DCFIFO is FULL Trasmitting Domain J 1 Da X vy X X vy Na s
10. KJ 2 2 2 2 5 d 7500 ps 63 75 ns Table 14 Write Operation when DCFIFO is FULL Waveform Description E Description INCADR When the write controller is in the INCADR state and the fifo_wrfu11 signal is asserted the write controller transitions to the wart state in the next rising clock edge WAIT In the wart state the write controller holds the rom_addr signal 08 so that the respective data is written into the DCFIFO when the write controller transitions to the WRITE State The write controller stays in wart state if the fifo_wrfu11 signal is still high When the fifo_wrful1 is low the write controller always transitions from the warrt state to the WRITE state at the next rising clock edge WRITE In the wRITE state then only the write controller drives the fifo_wrreq signal to high and requests for write operation to write the data from the previously held address 08 into the DCFIFO It always transitions to the INcApR state in the next rising clock edge if the rom_addr signal has not yet increased to ff The same state transition continues as stated in INCADR WAIT and WRITE states if the fifo_wrfull1 signal is high Figure 10 Completion of Data Transfer from ROM to DCFIFO Trasmitting Domain 1 i l 4 Eg vy vy vy 4 v Ee DDD 3 2 2500 ps 15000 ps 5018 75 ns Altera Corporation SCFIFO and DCFIFO IP Cores U
11. changes Altera Corporation SCFIFO and DCFIFO IP Cores User Guide G send Feedback
12. separate simulation waveforms to describe how the write and read control logics generate the control signal with respect to the signal received from the DCFIFO Note For better understanding refer to the signal names in Figure 6 on page 25 when you go through the descriptions for the simulation waveforms SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback UG MFNALT_FIFO 22 Design Example 2014 12 17 Figure 7 Initial Write Operation to the DCFIFO IP Core Trasmitting Domain S3 s 3 v a 1 i Yy 4 2500 ps 2500 ps 16 25 ns Table 12 Initial Write Operation to the DCFIFO IP Core Waveform Description SS SSS SSS SSS SSS IDLE Before reaching 10 ns the reset signal is high and causes the write controller to be in the IDLE state In the IDLE state the write controller drives the ifo_wrreq signal to low and requests the data to be read from rom_addr 00 The ROM is configured to have an unregistered output so that the rom_out signal immediately shows the data from the rom_addr signal regardless of the reset This shortens the latency because the rom_out signal is connected directly to the fifo_in signal which is a registered input port in the DCFIFO In this case the data 00000001 is always stable and pending to be written into the DCFIFO when the fifo_wrreq signal is high during the wRITE state WRITE The write controller transi
13. 4 11 X 12 X 13 gt wrusedw UD Ci a gt gt ee ee ee mi wrempty wrfull rdelk tdreq q 0403 tdusedw RO eK a D 00 tdempty rdfull In this example the read port is operating at half the frequency of the write port Writing four 8 bit words to the FIFO buffer increases the wrusedw flag to four and the rusedw flag to two Two 16 bit read operations empty the FIFO The first and second 8 bit word written are equivalent to the LSB and MSB of the 16 bit output words respectively The rdempty signal stays asserted until enough words are written on the narrow write port to fill an entire word on the wide read port Constraint Settings When using the Quartus II TimeQuest timing analyzer with a design that contains a DCFIFO block apply the following false paths to avoid timing failures in the synchronization registers e For paths crossing from the write into the read domain apply a false path assignment between the delayed_wrptr_g and rs_dgwp registers set_false_path from get_registers dcfifo delayed_wrptr_g to get_registers dcfifo rs_dgwp e For paths crossing from the read into the write domain apply a false path assignment between the rdptr_g and ws_dgrp registers set_false_path from get_registers dcfifo rdptr_g to get_registers dcfifo ws_dgrp The false path assignments are automatically added through the HDL embedded Synopsis design constraint SDC commands when you compile your design The r
14. O_MIXED_WIDTHS IP core supports different write input data and read output data widths if the width ratio is valid The FIFO parameter editor prompts an error message if the combinations of the input and the output data widths produce an invalid ratio The supported width ratio in a power of 2 and depends on the RAM The IP core supports a wide write port with a narrow read port and vice versa Figure 4 Writing 16 bit Words and Reading 8 bit Words This figure shows an example of a wide write port 16 bit input and a narrow read port 8 bit output wrelk wireq data 0006 wrusedw Se a AM o0 wrempty wrfull tdelk tdreq q ee ee C dd ed 00 tdusedw o o 0 Ae ee ae ee acd ae a oo tdempty tdfull In this example the read port is operating at twice the frequency of the write port Writing two 16 bit words to the FIFO buffer increases the wrusedw flag to two and the ruseaw flag to four Four 8 bit read operations empty the FIFO buffer The read begins with the least significant 8 bits from the 16 bit word written followed by the most significant 8 bits Altera Corporation SCFIFO and DCFIFO IP Cores User Guide GJ Send Feedback UG MFNALT_FIFO 2014 12 17 Constraint Settings 19 Figure 5 Writing 8 Bit Words and Reading 16 Bit Words This figure shows an example of a narrow write port 8 bit input with a wide read port 16 bit output wrelk wreg data OTF 02 X 03 X04 x 05 x 06 X OF X 08 X 09 X 0A KOB X OC X OD X OE X OF X10
15. SCFIFO and DCFIFO IP Cores User Guide 2014 12 17 UG MFNALT_FIFO ES subscribe GJ Send Feedback Altera provides FIFO functions through the parameterizable single clock FIFO SCFIFO and dual clock FIFO DCFIFO megafunction IP cores The FIFO functions are mostly applied in data buffering applications that comply with the first in first out data flow in synchronous or asynchronous clock domains The specific names of the IP cores are as follows e SCFIFO single clock FIFO e DCFIFO dual clock FIFO supports same port widths for input and output data e DCFIFO_MIXED_WIDTHS dual clock FIFO supports different port widths for input and output data Note The term DCFIFO refers to both the DCFIFO and DCFIFO_MIXED_WIDTHS IP cores unless specified Configuration Methods You can configure and build the FIFO IP cores with the following methods Table 1 Configuration Methods Using the FIFO parameter editor Altera recommends using this method to build your FIFO IP cores It is an efficient way to configure and build the FIFO IP cores The FIFO parameter editor provides options that you can easily use to configure the FIFO IP cores Manually instantiating the FIFO IP cores Use this method only if you are an expert user This method requires that you know the detailed specifi cations of the IP cores You must ensure that the input and output ports used and the parameter values assigned are valid for the FIFO IP cores you in
16. ahead mode with unregistered output in the FIFO parameter editor The corresponding parameter settings for the low latency version are ADD_RAM_OUTPUT_ 17 R only applicable to Stratix Stratix GX and Cyclone devices EGISTER OFF LPM_SHOWAHEAD ON and CLOCKS_ARE_SYNCHRONIZED FALSE These parameter settings are The values assigned to WRSYNC_DELAYPIPE and RDSYNC_DELAYPIPE parameters are internally reduced by 2 to represent the actual synchronization stage implemented Thus the default value 3 for these parameters corresponds to a single synchronization pipe stage a value of 4 results in 2 synchronization stages and so on For these devices choose 4 2 synchronization stages for metastability protection SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback 16 SCFIFO and DCFIFO Synchronous Clear and Asynchronous Clear Effect UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Synchronous Clear and Asynchronous Clear Effect The FIFO IP cores support the synchronous clear sc1r and asynchronous clear acir signals depending on the FIFO modes The effects of these signals are varied for different FIFO configurations The SCFIFO supports both synchronous and asynchronous clear signals while the DCFIFO support asynchronous clear signal and asynchronous clear signal that synchronized with the write and read clocks Table 9 Synchronous Clear and Asynchronous Clear in
17. aled down by two to reflect the actual synchronization stage Table 8 Relationship between the Actual Synchronization Stage and the Pipeline Parameters for Different Target Devices This table shows the relationship between the actual synchronization stage and the pipeline parameters Stratix Il Cyclone Il and later Stratix and Cyclone Other Devices Devices in Low Latency Version 9 Actual synchronization stage value of pipeline parameter 2 Actual synchronization stage value of pipeline parameter The TimeQuest timing analyzer includes the capability to estimate the robustness of asynchronous transfers in your design and to generate a report that details the mean time between failures MTBF for all detected synchronization register chains This report includes the MTBF analysis on the synchroniza tion pipeline you applied between the asynchronous clock domains in your DCFIFO You can then decide the number of synchronization stages to use in order to meet the range of the MTBF specification you require Related Information e Area and Timing Optimization Provides information about enabling metastability analysis and reporting http www altera com literature hb qts qts_qii53018 pdf Provides information about enabling metastability analysis and reporting 18 You can obtain the low latency of the DCFIFO for Stratix Stratix GX and Cyclone devices when the clocks are not set to synchronized in Show
18. ation stages and so on For these devices choose at least 4 two synchroniza tion stages for metastability protection use_eab String No Specifies whether or not the FIFO IP core is constructed using the RAM blocks The values are ON or OFF Setting this parameter value to OFF yields the FIFO IP core implemented in logic elements regardless of the type of the TriMatrix memory block type assigned to the ram_block_type parameter Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Parameters To write_aclr synch String Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the wrc1k clock Adding the circuit prevents the race condition between the wrreg and acir ports that could corrupt the FIFO IP core The values are ON or OFF If omitted the default value is orF This parameter is only applicable for Stratix and Cyclone series except for Stratix Stratix GX and Cyclone devices read_aclr_synch String No Specifies whether or not to add a circuit that causes the aclr port to be internally synchronized by the rdc1k clock Adding the circuit prevents the race condition between the rdreq and acir ports that could corrupt the FIFO IP core The values are ON or OFF If omitted the default value is OFF This parameter is only applicable for families beginning from S
19. ble the underflow protection circuitry in the FIFO MegaWizard interface or set the UNDERFLOW_CHECKING parameter to ON If the protection circuitry is not enabled you must meet the following functional timing requirements Table 3 Functional Timing Requirements Deassert the wrreq signal in the same clock cycle Deassert the wrreq signal in the same clock cycle when the wrfu11 signal is asserted when the full signal is asserted Deassert the rdregq signal in the same clock cycle Deassert the rdreq signal in the same clock cycle when the rdempty signal is asserted You must when the empty signal is asserted observe these requirements regardless of expected behavior based on wrc1k and rac1k frequencies Only applicable for the SCFIFO IP core Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Output Status Flag and Latency 11 Figure 2 Functional Timing for the wrreq Signal and the wrfull Signal This figure shows the behavior for the wrreq and the wrful1 signals D ps 5 0 ns 10 0 ns 15 0 ns 20 0 ns 25 0 ns 30 0 ns 35 Nai 0 ps wrelk wire data a ee Gee es ee ee Ge ee ee ee ee ee ee ee wrfull tdelk tdreq tdempty Figure 3 Functional Timing for the rdreq Signal and the rdempty Signal This shows the behavior for the rdreg the rdempty signals bo 0ns 35 0ns 40 0 ns 45 0 ns 50 0 ns 55 0 ns 60 0 ns 65
20. bruary 2012 7 0 e Updated the notes for Table 4 on page 16 e Added the DCFIFO Clock Domain Crossing Timing Violation section September 2010 6 2 Added prototype and component declarations SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback 28 Document Revision History UG MFNALT_FIFO 2014 12 17 oe ves chang January 2010 September 2009 6 1 6 0 Updated Functional Timing Requirements section Minor changes to the text Replaced FIFO Megafunction Features section with Configuration Methods Updated Input and Output Ports Added Parameter Specifications Output Status Flags and Latency Metastability Protection and Related Options Constraint Settings Coding Example for Manual Instantiation and Design Example February 2009 5 1 Minor update in Table 8 on page 17 January 2009 5 0 Complete re write of the user guide May 2007 4 0 Added support for Arria GX devices Updated for new GUI Added six design examples in place of functional description Reorganized and updated Chapter 3 to have separate tables for the SCFIFO and DCFIFO megafunctions Added Referenced Documents section March 2007 3 3 Minor content changes including adding Stratix III and Cyclone III information Re took screenshots for software version 7 0 September 2005 3 2 Minor content
21. dth of the q port for the DCFIFO_ MIXED_WIDTHS IP core lpm_widthu lpm_widthu_r 4 Integer Integer Yes Yes Specifies the width of the usedw port for the SCFIFO IP core or the width of the rdusedw and wrusedw ports for the DCFIFO IP core For the DCFIFO_MIXED_ WIDTHS IP core it only represents the width of the wrusedw port Specifies the width of the rdusedw port for the DCFIFO_MIXED_WIDTHS IP core Only applicable for the DCFIFO_MIXED_WIDTHS IP core Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Parameters To lpm_numwords Integer Specifies the depths of the FIFO you require The value must be at least 4 The value assigned must comply with this equation 2LPM_WIDTHU lpm_showahead String Yes Specifies whether the FIFO is in normal mode oFF or show ahead mode on For normal mode the FIFO IP core treats the rdreq port as a normal read request that only performs read operation when the port is asserted For show ahead mode the FIFO IP core treats the rdreg port as a read acknowledge that automatically outputs the first word of valid data in the FIFO IP core when the empty or rdempty port is low without asserting the rdreq signal Asserting the rdreq signal causes the FIFO IP core to output the next data word if available If you set the parameter to ON you may reduce performance
22. elated message is shown under the TimeQuest timing analyzer report Note The constraints are internally applied but are not written to the Synopsis Design Constraint File sdc To view the embedded false path type report_sdc in the console pane of the TimeQuest timing analyzer GUI If you use the Quartus II Classic timing analyzer the false paths are applied automatically for the DCFIFO Note If the DCFIFO is implemented in logic elements LEs you can ignore the cross domain timing violations from the data path of the DFFE array that makes up the memory block to the g output SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback one UG MFNALT_FIFO 20 Coding Example for Manual Instantiation 2014 12 17 register To ensure the q output is valid sample the output only after the rdempty signal is deasserted Related Information Quartus II TimeQuest Timing Analyzer Provides information about setting the timing constraint Coding Example for Manual Instantiation This section provides a Verilog HDL coding example to instantiate the DCFIFO IP core It is not a complete coding for you to compile but it provides a guideline and some comments for the required structure of the instantiation You can use the same structure to instantiate other IP cores but only with the ports and parameters that are applicable to the IP cores you instantiated Table 11 Verilog HDL Coding Example to Instantiate the DCFIFO IP Core
23. flow_ checking parameter to ON so that the FIFO IP core can automatically disable the wrreq signal when it is full e The wrreq signal must meet the functional timing requirement based on the full or wrfull signal Do notassert the wrreg signal during the deassertion of the acir signal Violating this requirement creates a race condition between the falling edge of the acir signal and the rising edge of the write clock if the wrreq port is set to high For both the DCFIFO IP cores that target Stratix and Cyclone series except Stratix Stratix GX and Cyclone devices you have the option to automatically add a circuit to synchronize the ac1r signal with the wrc1k clock or set the write_ aclr_synch parameter to ON Use this option to ensure that the restriction is obeyed rdreq Input Yes Assert this signal to request for a read operation The rdreq signal acts differently in normal mode and show ahead mode Ensure that the following conditions are met e Do not assert the rdreg signal when the empty for SCFIFO or rdempt y for DCFIFO port is high Enable the underflow protection circuitry or set the underflow_checking parameter to ON so that the FIFO IP core can automatically disable the rareq signal when it is empty e The rdreq signal must meet the functional timing requirement based on the empty or rdempty signal sclr aclr Input Assert this signal to clear all the output status port
24. he lt Quartus II installation directory gt eda synthesis directory VHDL Component Declaration The VHDL component declaration is located in the lt Quartus II installation directory gt libraries vhdl altera_mf altera_mf_components vhd VHDL LIBRARY USE Declaration The VHDL LIBRARY USE declaration is not required if you use the VHDL Component Declaration LIBRARY altera_mf USE altera_mf_altera_mf_components all SCFIFO and DCFIFO Signals This section provides diagrams of the SCFIFO and DCFIFO blocks to help in visualizing their input and output ports This section also describes each port in detail to help in understanding their usages functionality or any restrictions For better illustrations some descriptions might refer you to a specific section in this user guide Figure 1 SCFIFO and DCFIFO IP Cores Input and Output Signals ql7 0 wrfull full wrempty almost_full wrusedw 8 0 empty ql7 0 almost_empty usedw 7 0 rdfull rdempty rdusedw 8 0 For the SCFIFO block the read and write signals are synchronized to the same clock for the DCFIFO block the read and write signals are synchronized to the rdc1k and wrc1k clocks respectively The prefixes wr and rd represent the signals that are synchronized by the wrc1k and rac1k clocks respectively SCFIFO and DCFIFO IP Cores User Guide GJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Signals 3 Table 2 Input and Output Ports Descrip
25. he q output Note To verify the results compare the q outputs with the data in rom_initdata hex file provided in the design example Open the file in the Quartus II software and select the word size as 32 bit The q output must display the same data as in the file Related Information DCFIFO Design Example Provides all the design files including the testbench The zip file also includes the do script dcfifo_de_top do that automates functional simulation that you can use to run the simulation using the ModelSim Altera software SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback UG MFNALT_FIFO 26 Gray Code Counter Transfer at the Clock Domain Crossing 2014 12 17 Gray Code Counter Transfer at the Clock Domain Crossing This section describes the effect of the large skew between Gray code counter bits transfers at the clock domain crossing CDC with recommended solution The gray code counter is 1 bit transition occurs while other bits remain stable when transferring data from the write domain to the read domain and vice versa If the destination domain latches on the data within the metastable range violating setup or hold time only 1 bit is uncertain and destination domain reads the counter value as either an old counter or a new counter In this case the DCFIFO still works as long as the counter sequence is not corrupted The following section shows an example of how large skew between GNU C compiler GCC
26. how ahead data It reflects the data where the read pointer is pointing to because the q output is not registered To obtain a valid Show ahead data perform a valid write after the reset Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 Tab This table shows the asynchronous clear supported by the DCFIFO SCFIFO and DCFIFO Synchronous Clear and Asynchronous Clear Effect 17 le 10 Asynchronous Clear in DCFIFO Asynchronous Clear aclr synchronize aclr synchronize with read clock EYA with write clock 2 wa e 7p Deasserts the wrfull The wrfu11 signal is The rdempty signal is signal asserted while the asserted while the read write domain is domain is clearing which clearing which nominally takes three cycles nominally takes of the read clock after the three cycles of the asynchronous release of the write clock after the aclr input asynchronous release of the ac1r input Effects on status ports Deasserts the rafu11 signal Asserts the wrempty and rdempty signals Resets the wrusedw and rdusedw flags Commencement of effects Immediate upon assertion Effects on the q output for The output remains unchanged if it is not registered If the port is normal output modes 4 registered it is cleared Effect on the q output for The output shows X if it is not registered If the port is registered it is show ahead
27. mal mode and unregistered q output in Show ahead mode For other devices you have an option to register or unregister the q output regardless of the Normal mode or Show ahead mode in the FIFO parameter editor or set through the ADD_RAM_OUTPUT_REGISTER parameter SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback rer g ai UG MFNALT_FIFO 18 Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO IP Core 2014 12 17 Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO IP Core During compilation of a design that contains a DCFIFO IP core the Quartus II software may issue recovery and removal timing violation warnings You may safely ignore warnings that represent transfers from acir to the read side clock domain To ensure that the design meets timing enable the ACLR synchronizer for both read and write domains To enable the ACLR synchronizer for both read and write domains on the DCFIFO 2 tab of the FIFO MegaWizard Plug In Manager turn on Asynchronous clear Add circuit to synchronize aclr input with wrclk and Add circuit to synchronize aclr input with rdclk Note For correct timing analysis Altera recommends enabling the Removal and Recovery Analysis option in the TimeQuest timing analyzer tool when you use the ac1r signal The analysis is turned on by default in the TimeQuest timing analyzer tool Different Input and Output Width The DCFIF
28. ore the width of the wrusedw and rdusedw ports must be equal to the LpM_WIDTHU and 1lpm_widthu_ r parameters respectively For Stratix Stratix GX and Cyclone devices the FIFO IP core shows full even before the number of words stored reaches its maximum value Therefore you must always refer to the full or wrfull1 port for valid write request operation and the empty or rdempty port for valid read request operation regardless of the target device The DCFIFO IP core rdempty output may momentarily glitch when the acir input is asserted To prevent an external register from capturing this glitch incorrectly ensure that one of the following is true e The external register must use the same reset which is connected to the acir input of the DCFIFO IP core Or e The reset connected to the acir input of the DCFIFO IP core must be asserted synchronous to the clock which drives the external register The output latency information of the FIFO IP cores is important especially for the q output port because there is no output flag to indicate when the output is valid to be sampled SCFIFO and DCFIFO Parameters This table lists the parameters for the SCFIFO and DCFIFO IP cores ed lpm_width Integer Specifies the width of the data and q ports for the SCFIFO IP core and DCFIFO IP core For the DCFIFO_MIXED_WIDTHS IP core this parameter specifies only the width of the data port lpm_width_r Integer Yes Specifies the wi
29. ormance Increasing the value of the parameter does not increase the maximum system speed It only adds additional latency to the respective output port add_usedw_msb_bit String Increases the width of the rdusedw and wrusedw ports by one bit By increasing the width it prevents the FIFO IP core from rolling over to zero when it is full The values are ON or OFF If omitted the default value is OFF This parameter is only applicable for Stratix and Cyclone series except for Stratix Stratix GX and Cyclone devices rdsync_delaypipe wrsync_delaypipe 5 5 Integer Specify the number of synchronization stages in the cross clock domain The value of the rdsync_ delaypipe parameter relates the synchronization stages from the write control logic to the read control logic the wrsync_delaypipe parameter relates the synchronization stages from the read control logic to the write control logic Use these parameters to set the number of synchronization stages if the clocks are not synchronized and set the clocks_are_synchronized parameter to FALSE The actual synchronization stage implemented relates variously to the parameter value assigned depends on the target device For Cyclone II and Stratix II devices and later the values of these parameters are internally reduced by two Thus the default value of 3 for these parameters corresponds to a single synchronization stage a value of 4 results in two synchroniz
30. output cleared modes 20 21 22 23 24 The wrreq signal must be low when the DCFIFO comes out of reset the instant when the acir signal is deasserted at the rising edge of the write clock to avoid a race condition between write and reset If this condition cannot be guaranteed in your design the acir signal needs to be synchronized with the write clock This can be done by setting the Add circuit to synchronize aclr input with wrclk option from the FIFO parameter editor or setting the WwRITE_ACLR_SYNCH parameter to ON Even though the ac1r signal is synchronized with the write clock asserting the acir signal still affects all the status flags asynchronously The rdreq signal must be low when the DCFIFO comes out of reset the instant when the ac1r signal is deasserted at the rising edge of the read clock to avoid a race condition between read and reset If this condition cannot be guaranteed in your design the aclr signal needs to be synchronized with the read clock This can be done by setting the Add circuit to synchronize aclr input with rdclk option from the FIFO parameter editor or setting the READ_ACLR_SYNCH parameter to ON Even though the ac1r signal is synchronized with the read clock asserting the acir signal affects all the status flags asynchronously For Stratix and Cyclone series except Stratix Stratix GX and Cyclone devices the DCFIFO only supports registered q output in Nor
31. rreg rdreq to usedw 1 wrregtog 1l rdreqto q 1 wrreq rdreq to full 1 wrreq to empty 2 rdreq to empty 1 Area wrreq rdreq to usedw 1 wrreqtoq 1 rdreq to q 1 10 Speed optimization is equivalent to setting the ADD_RAM_OUTPUT_REGISTER parameter to ON Setting the parameter to or F is equivalent to area optimization 0D The information of the output latency is applicable for Stratix and Cyclone series only It may not be applicable for legacy devices such as the APEX and FLEX series 2 For the Quartus II software versions earlier than 9 0 the normal output mode is called legacy output mode Normal output mode is equivalent to setting the LpM_SHOWAHEAD parameter to oFF For Show ahead mode the parameter is set to on SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback UG MFNALT_FIFO 14 SCFIFO and DCFIFO Metastability Protection and Related Options 2014 12 17 Table 6 Output Latency of the Status Flag for the DCFIFO This table shows the output latency of the write signal wrreq and read signal rdreq for the DCFIFO Output Latency in number of clock cycles wrreq to wrfull l wrclk wrreq to rdfull 2 wrclk cycles following n rdclk wrreg to wrempty l wrclk wrreg to rdempty 2 wrelk following n rdclk 15 wrreg to wrusedw 2 wrclk wrreg to rdusedw 2 wrclk following n l rdclk
32. s but the effect on the q output may vary for different FIFO configurations There are no minimum number of clock cycles for aclr signals that must remain active Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Signals 5 SE EE Output Shows the data read from the read request operation For the SCFIFO IP core and DCFIFO IP core the width of the q port must be equal to the width of the data port If you manually instantiate the IP cores ensure that the port width is equal to the 1pm_width parameter For the DCFIFO_MIXED_WIDTHS IP core the width of the q port can be different from the width of the data port If you manually instantiate the IP core ensure that the width of the q port is equal to the 1pm_width_r parameter The IP core supports a wide write port with a narrow read port and vice versa However the width ratio is restricted by the type of RAM block and in general are in the power of 2 full wrfull B 4 rdfull 4 Output When asserted the FIFO IP core is considered full Do not perform write request operation when the FIFO IP core is full In general the rafu11 signal is a delayed version of the wrfull signal However for Stratix III devices and later the rafu11 signal function as a combinational output instead of a derived version of the wrfu11 signal Therefore you must always refer to the wrfu11 port to
33. ser Guide GJ Send Feedback UG MFNALT_FIFO 2014 12 17 Design Example 25 Table 15 Completion of Data Transfer from ROM to DCFIFO Waveform Description e WRITE When the write controller is in the wRITE state and rom_addr ff the write controller drives the ifo_wrreq signal to high to request for last write operation to DCFIFO The data 100 is the last data stored in the ROM to be written into the DCFIFO In the next rising clock edge the write controller transitions to the Don state DONE In the Done state the write controller drives the ifo_wrreg signal to low The fifo_wrfu11 signal is deasserted because the read controller in the receiving domain continuously performs the read operation However the fi fo_wrful1 signal is only deasserted sometime after the read request from the receiving domain This is due to the latency in the DCFIFO rdreq signal to wrfull signal Figure 11 Completion of Data Transfer from DCFIFO to RAM l l ene ee oe 1 1 1 i 10000 ps 2 5165 ns OO Od The fifo_rdempty signal is asserted to indicate that the DCFIFO is empty The read controller drives the fifo_rdreq signal to low and enables the write of the last data 100 at ram_addr ff The word_count signal is increased to 256 in decimal to indicate that all the 256 words of data from the ROM are success fully transferred to the RAM The last data written into the RAM is shown at t
34. stantiate for your target device Related Information Introduction to Altera IP Cores Provides general information about the Quartus II Parameter Editor 2015 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE ENPIRION MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks of Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance ISO of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any 9001 2008 products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information Registered product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services JAN DTE RYA 101 Innovation Drive San Jose CA 95134 Altera Corporation o cot UG MFNALT_FIFO 2 Specifications 2014 12 17 Specifications Verilog HDL Prototype You can locate the Verilog HDL prototype in the Verilog Design File v altera_mf v in t
35. story 27 Table 16 Document Revision History oe version chan December 2014 2014 12 17 Clarified that there are no minimum number of clock cycles for acir signals that must remain active e Added Recovery and Removal Timing Violation Warnings when Compiling a DCFIFO Megafunc tion section e Removed a note about ignoring any recovery and removal violation reported in the TimeQuest timing analyzer that represent transfers from the aclr to the read side clock domain in Synchronous Clear and Asynchronous Clear Effect section May 2013 8 2 e Updated Table 8 on page 20 to state that both the read and write pointers reset to zero upon assertion of either the sclr or acir signal e Updated Table 1 on page 7 to note that the wrusedw rdusedw wrfull rdfull wrempty and rdempty values are subject to the latencies listed in Table 5 on page 18 August 2012 8 1 e Included a link to skew_report tel Gray Code Counter Transfer at the Clock Domain Crossing on page 29 August 2012 8 0 e Updated DCFIFO on page 3 Ports Specifica tions on page 6 Functional Timing Require ments on page 14 Synchronous Clear and Asynchronous Clear Effect on page 20 e Updated Table 1 on page 7 Table 2 on page 10 Table 9 on page 21 e Added Table 4 on page 16 e Renamed and updated DCFIFO Clock Domain Crossing Timing Violation to Gray Code Counter Transfer at the Clock Domain Crossing on page 29 Fe
36. t for different target device refer to 5 This is applied only to Show ahead output modes Show ahead output mode is equivalent to setting the LPM_SHOWAHEAD parameter to ON Altera Corporation SCFIFO and DCFIFO IP Cores User Guide CJ Send Feedback UG MFNALT_FIFO 2014 12 17 SCFIFO and DCFIFO Metastability Protection and Related Options 15 Minimal setting for unsynchronized clocks This option uses two synchronization stages with good metastability protection It uses the medium size and provides good fmax Best metastability protection best fmax and This option uses three or more synchronization unsynchronized clocks stages with the best metastability protection It uses the largest size but gives the best fmax The group setting for latency and related options is available through the FIFO parameter editor The setting mainly determines the number of synchronization stages depending on the group setting you select You can also set the number of synchronization stages you desire through the wRsYNC_DELAYP IPE and RDSYNC_DELAYPIPE parameters but you must understand how the actual number of synchronization stages relates to the parameter values set in different target devices The number of synchronization stages set is related to the value of the wrsyNC_DELAYPIPE and RDSYNC_DELAYP IPE pipeline parameters For some cases these pipeline parameters are internally sc
37. the SCFIFO This table shows the synchronous clear and asynchronous clear signals supported in the SCFIFO Effects on status ports Synchronous Clear sclr Asynchronous Clear aclr Deasserts the fu11 and almost_ful1 signals Asserts the empty and almost_empty signals Resets the usedw flag Commencement of effects upon assertion At the rising edge of the clock Immediate except for the q output Effects on the q output for normal output modes The read pointer is reset The q output remains at its previous and points to the first data value location If the q output is not registered the output shows the first data word of the SCFIFO otherwise the q output remains at its previous value Effects on the q output for show ahead output modes The read pointer is reset _ If the q output is not registered the and points to the first data output shows the first data word of location If the q output is the SCFIFO starting at the first rising not registered the output clock edge ee Pe Otherwise the q output remains its value for only one clock i OER cycle and shows the first PFEV1OUS Value data word of the SCFIFO at the next rising clock edge 9 Otherwise the q output remains at its previous value 18 The read and write pointers reset to zero upon assertion of either the sc1r or ac1r signal 9 The first data word shown after the reset is not a valid S
38. tion This table lists the signals of the IP cores The term series refers to all the device families of a particular device For example Stratix series refers to the Stratix Stratix GX Stratix II Stratix II GX Stratix III and new devices unless specified otherwise clock Input Yes __ Positive edge triggered clock wrelk Input Yes _ Positive edge triggered clock Use to synchronize the following ports e data e wrreq e wrfull e wrempty e wrusedw rdclk Input Yes Positive edge triggered clock Use to synchronize the following ports lt gq e rdreq e rdfull e rdempty e rdusedw data Input Yes Holds the data to be written in the FIFO IP core when the wrreg signal is asserted If you manually instantiate the FIFO IP core ensure the port width is equal to the 1pm_ width parameter Only applicable for the SCFIFO IP core Applicable for both of the DCFIFO IP cores Applicable for the SCFIFO DCFIFO and DCFIFO_MIXED_WIDTH IP cores SCFIFO and DCFIFO IP Cores User Guide Altera Corporation Send Feedback 4 SCFIFO and DCFIFO Signals UG MFNALT_FIFO 2014 12 17 a a S l e e wrreg Input Assert this signal to request for a write operation Ensure that the following conditions are met e Do not assert the wrreg signal when the full for SCFIFO or wrfu11 for DCFIFO port is high Enable the overflow protection circuitry or set the over
39. tions from the IDLE state to the WRITE state ifthe fifo_ wrfull signal is low after the reset signal is deasserted In the WRITE state the write controller drives the ifo_wrreg signal to high and requests for write operation to the DCFIFO The rom_adar signal is unchanged 00 so the data is stable for at least one clock cycle before the DCFIFO actually writes in the data at the next rising clock edge INCADR The write controller transitions from the WRITE state to the INCADR state if the rom_ addr signal has not yet increased to ff that is the last data from the ROM has not been read out In the 1NDADR state the write controller drives the fifo_wrreq signal to low and increases the rom_adar signal by 1 00 to 01 The same state transition continues as stated in IDLE and WRITE states if the fifo_ wrfull signal is low and the rom_adar signal not yet increased to ff Altera Corporation SCFIFO and DCFIFO IP Cores User Guide GJ Send Feedback UG MFNALT_FIFO 2014 12 17 Design Example 23 Figure 8 Initial Read Operation from the DCFIFO IP Core 1 NCADR 1 B B l Na ed s 000d D 10000 ps 10000 ps 4 65ns Table 13 Initial Read Operation from the DCFIFO IP Core Waveform Description A IDLE Before reaching 35 ns the read controller is in the IDLE state because the ifo_rdempty signal is high even when the reset signal is low not shown in the waveform
40. tratix III series clocks_are_synchron ized String Specifies whether or not the write and read clocks are synchronized which in turn determines the number of internal synchronization stages added for stable operation of the FIFO The values are TRUE and FALSE If omitted the default value is FALSE You must only set the parameter to TRUE if the write clock and the read clock are always synchronized and they are multiples of each other Otherwise set this to FALSE to avoid metastability problems If the clocks are not synchronized set the parameter to FALSE and use the rdsync_delaypipe and wrsync_ delaypipe parameters to determine the number of synchronization stages required ram_block_type String Specifies the target device s Trimatrix Memory Block to be used To get the proper implementation based on the RAM configuration that you set allow the Quartus II software to automatically choose the memory type by ignoring this parameter and set the use_eab parameter to ON This gives the compiler the flexibility to place the memory function in any available memory resource based on the FIFO depth required SCFIFO and DCFIFO IP Cores User Guide Send Feedback Altera Corporation UG MFNALT_FIFO SCFIFO and DCFIFO Functional Timing Requirements 2014 12 17 ed add_ram_output_register String Specifies whether to register the q output The values are ON and OFF If omitted the default value is OFF
41. y non related clocks you can use the DCFIFO to transfer the data between the asynchronous clock domains effectively Figure 6 Component Blocks and Signal Interaction This figure shows the component blocks and their signal interactions Note Note ROM Write 2 DCFIFO Read RAM 256x32 Control Logic i ifo Control Logic 256x32 32 32 ram_in 8 ram_wren ram_rden word_count Both the DCFIFO IP cores are only capable of handling asynchronous data transferring issues metastable effects You must have a controller to govern and monitor the data buffering process between the ROM DCFIFO and RAM This design example provides you the write control logic write_control_logic v and the read control logic read_control_logic v which are compiled with the DCFIFO specifications that control the valid write or read request to or from the DCFIFO This design example is validated with its functional behavior but without timing analysis and gate level simulation The design coding such as the state machine for the write and read controllers may not be optimized The intention of this design example is to show the use the IP core particu larly on its control signal in data buffering application rather than the design coding and verifica tion processes To obtain the DCFIFO settings in this design example refer to the parameter settings from the design file dcfifo8x32 v The following sections include
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