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CY9266 HOTLink™ Evaluation Board User's Guide

1. Pin Pin No JP3 JP2 JP4 No JP3 JP2 JP4 1 SYNC_POL SYNC_POL REC_9 31 RCV CLK1 RCV CLK1 VCC 2 CD_POL CD_POL GND 32 GND GND XMIT_6 3 DIP_FOTO DIP_FOTO REC_6 33 RCV_CLK0 RCV_CLK0 XMIT_3 4 DIP_RCVA B DIP_RCVA B REC_4 34 VCC VCC XMIT_0 5 RCV_MODE RCV_MODE VCC 35 XMIT_8 XMIT_8 GND 6 SWRCVBISTEN SWRCVBISTEN REC_0 36 GND GND LOOP_BACK 7 REC_9 REC_9 RCV_CLK1 37 ENBYTESYNC ENBYTESYNC BYTE_SYNC 8 XMIT_ENA XMIT_ENA VCG 38 RESET RESET LINK_STATUS 9 REC_6 REC_6 XMIT_4 39 XMIT_7 XMIT_7 GND 10 XMIT_MODE XMIT_MODE XMIT_1 40 GND GND GND 11 REC_8 REC_8 GND 41 XMIT_6 XMIT_6 GND 12 XMIT_ENN XMIT_ENN XMITCLOCK 42 VCC VCC XMIT_9 13 REC 5 REC 5 REC 8 43 XMIT 3 XMIT 3 XMIT 8 14 XMIT BISTEN XMIT BISTEN REC 5 44 GND GND XMIT 7 15 REC 2 REC 2 VCC 45 XMIT_4 XMIT_4 N C 16 GND GND REC 3 46 RDY RDY XMIT_5 17 REC_7 REC_7 REC_1 47 XMIT 0 XMIT 0 LINK CONTROL 18 GND GND GND 48 VCC VCC VCC 19 LINK STATUS LINK STATUS RCV CLKO 49 XMIT 5 XMIT 5 20 BYTE SYNC BYTE SYNC ENBYTESYNC 50 GND GND 21 REC_4 REC_4 GND 51 XMIT_2 XMIT_2 22 VCC VCC XMIT_2 52 GND GND 23 REC_3 REC_3 N C 53 XMIT_1 XMIT_1 24 EXTREFCLK EXTREFCLK VCC 54 RP RP 25 REC_0 REC_0 REC_7 55 GND GND 26 GND GND GND 56 XMITCLOCK XMITCLOCK 27 REC_1 REC_1 REC_2 57 LINK_CONTROL LINK_CONTROL 28 VCC VCC N C 58 LOOP_BACK LOOP_BACK 29 XMIT_9 XMIT_9 GND 59 GND 30 GND GND RESET 60 GND Signal Naming Conventions There are three types of sign
2. 37 E F s CY9266 HOTLink Evaluation Board User s Guide ses CYPRESS Appendix B CY9266 C T Schematic Sheet 5 of 5 38 SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Appendix B CY9266 C T Parts List Instance Part Number Description U1 Cypress CY7B923 JC HOTLink Transmitter U2 Cypress CY7B933 JC HOTLink Receiver U3 74F86 Quad XOR Gate SOIC Package U5 CTS CTX126 or Equivalent 25 MHz TTL Clock Oscillator U6 U7 TI TIL311 Hex Display With Logic U8 Cypress CY7C344 15HC 32 Macrocell MAX EPLD U9 U10 74F174 Hex D register SOIC Package U11 Maxim MAX707CSA or Equivalent Vol
3. 81 asi Figure 13 HOTLink Receiver Parallel Interface that were received and framed The letter form Qa Qj as illustrated in Figure 13 of the bit identifiers is followed for this setting These designators specify which encoded data bit is connected to a specific REC Oto REC 9 signal In this mode the user must decode the data from the 10 bit patterns used to send the data across the serial interface While it is not necessary to use the 8B 10B code described in the HOTLink datasheet it is advised that this code be used for simplicity If another code is used it is the user s respon sibility to insure that sufficient transitions are present in the data stream to allow the HOTLink Receiver to properly phase lock to the serial data stream For the HOTLink Receiver to maintain byte framing and syn chronization the K28 5 pattern must also be used for framing initialization For those systems that perform their own fram ing SONET etc the HOTLink Receiver will phase lock to a serial data stream without a K28 5 code present and clock out a character every 10 bit clocks These systems must operate in Bypass mode as the HOTLink Receiver decoder requires operation with the 8B 10B code and must acquire byte sync to recover valid data These systems must provide external byte framing When the HOTLink Receiver MODE input is LOW the internal 108 88 decoder is enabled this mode the ten output bits
4. Az ee SR we S S Sr ww wu a HM ue 0 00000000 0 ee 000 00 00000 00900 009 09 e 8 ETETE araa ra ra ra rare ree rare 000 00 0 0 0 0 0060 0000000 rr 9149 LAYER2 GND 46 _ FP CY9266 HOTLink Evaluation Board User s Guide ZcypREss_ C9266 HOTLink Evaluation Board User s Guide DE CY9266 HOTLink Evaluation Board User s Guide CYPRESS CY9266 HOTLink Evaluation Board User s Guide Appendix D CY9266 F Artwork Bottom Silkscreen CC O E ASA il etA ESA 2 SSH p E ISA L O co TT1145 05 26 93 al Is Cleo a L ero E ata E eta P A cA Bro oro 0 E SILKSCREEN BOT 48 f s CY9266 HOTLink Evaluation Board User s Guide MI cypress___ 8266 HOTLInk Evaluation Board User s Guide Appendix D CY9266 F Artwork Drill Chart YY YY T Y Y Y Y Fat Y Y Y Y Y Y Y Y opa Y Y Y Y YYYY q Y Y Y Y Y Y Y Y H Y Y Y Y YYYY 4 Y Y m gu iE NY Y Y Y Y Y Y Y Y YI YY Y Y Y Y Y Y Y Y Y x x T X X XXX x X X X X X X X X lt x XXXXX x XXXXX T x z t XXXXXXXXXX 180 DRILLM AP 111145 05 26 93 rs oo e2_ free owe x ue rs so v vs
5. CY9266 HOTLink Evaluation Board User s Guide Appendix E CY9266 C T Artwork Drill Chart T H t XX lt lt lt lt lt lt lt lt lt lt lt lt lt gt 4 4 4 4 4 4 Y Y Y Y Y Y Y Y Y Y Y Y Y puro YYYYYYYYYY YYYYYYYYYY T 2 750 3 00 x X X X Xx x x X X X X X X X X lt KKK KKK KKK KKK KX x KKK KK KK KX X X X X X X X X X Xx DRILLMAP TT1132 04 28 93 53 fos se 5303 56 SESJ CYPRESS 01 9266 HOTLink Evaluation Board User s Guide Appendix F CY9266 Configuration Guide Switch SW1 Settings 0 on 1 off Function JP1 Jumper Settings 1 2 3 4 5 6 7 8 9 10 Xmtr BIST Enable 0 Xmtr BIST External 1 Xmtr Encode Mode 0 Xmtr Bypass Mode 1 Xmtr ENA Active 0 Xmtr ENA External 1 Xmtr ENN Active 0 Xmtr ENN External 1 Rcvr BIST Enable 0 Rcvr BIST External 1 Rcvr Decode Mode 0 Rcvr Bypass Mode 1 Rcvr Port A Selected 1 Rcvr Port B Selected A 0 Xmtr Enabled FOTO Off 0 Xmtr External Ens 1 Active High Carrier Det
6. Appendix D CY9266 F Artwork Top Silkscreen 4 PWR C15 D ON o 2 q e D CAR i DET amp BIST E WAIT S dBisT OVFL F UB CY7C344 XMTR RESET E co e e m qi m gt gt O O QN Si m o A B 6 D E F U10 G Lr J R20 U11 5 0 LU LLI CC O w JP3 Guide 01 9266 HOTLink Evaluation Board User s CYPRESS Appendix D CY9266 F Artwork Top Layer Copper 6 92 60 GPLLLL O Ko rot 0 n a HOLONGNODINAS SSIHA O o 6 NT ON FES Aw NINE SE 3t QQ 0 daloaaloao Q O goo 0 0 ololla p gt OJ O O O O O O O IO O OJO OJO O O O ojojojojo o 2 01 1 11 111111 1110111223234 dOL 3 V 1 019 9266 HOTLink Evaluation Board User s Guide YPRESS jik Lue Appendix D CY9266 F Artwork Power Layer 26 92 40 SpLLIL e q 900000000 e e e e 2 00 10000 du e 00 000 fu Ph F 9 en e 0004 HAAd 8 H3AVTI La a ee af 45 Tis DE CY9266 HOTLink Evaluation Board User s Guide CYP PES ii ee Appendix D CY9266 F Artwork Ground Layer M RETAS Neue eues m M e FREE e FS P T ae T ah T ee PN P TT1145 05 26 93 00000 e furs en e 0 00 00 e e e ee e L4 e FS ES PS ex
7. r at xe we e 2 mo ula 200 X 100 OVAL HOLE 49 019 9266 HOTLink Evaluation Board User s Guide YPRESS aa 1 Lue w Top Silkscreen Appendix E CY9266 C T Artwork 6 8Z P0 ZELLLL gt LA dOl N334254 115 JP3 50 CY9266 HOTLink Evaluation Board User s Guide ZcypREss_ CY9266 HOTLink Evaluation Board User s Guide Appendix E CY9266 C T Artwork Top Layer Copper 7 PERES SoG 9 SSE ONA 00 fa n 0 5 H2 AN D o o Sa pi 019 9266 HOTLink Evaluation Board User s Guide YPRESS ng 1 ha Pa Appendix E CY9266 C T Artwork Power Layer 6 8zivO cELLLL e e o e 0 Wa we ve pei e d gt 27 gt 00600606 ey tt HAAd H3AVI 52 019 9266 HOTLink Evaluation Board User s Guide YPRESS Tae Lue Appendix E CY9266 C T Artwork Ground Layer as e eoo e D ae 6 8zivO cELLLL FA 4 eo ray P co as aa rn en COO e 0 ey ey 2 NS d3AV1 53 Tis i WE RESS CY9266 HOTLink Evaluation Board User s Guide Appendix E CY9266 C T Artwork Bottom Silkscreen 4 TT1132 04 28 93 SILKSCREEN BOT ASSEMBLY BOTTOM 55 bay M CY9266 HOTLink Evaluation Board User s Guide SE
8. A B to control which serial input is fed to the shifter and PLL When the A B input is HIGH the differential INA pair is con nected to the shifter and PLL When the A B input is LOW the INB input is fed to the shifter and PLL Because the INB input is directly connected to the OUTC output from the HOTLink Transmitter this LOW setting is used for a local loop back and allows the transmitter and receiver to communicate without using an optical module The A B input is a PECL input and normal TTL or CMOS logic swings will not work to control it This input uses PECL or larger signal swings These can still be achieved in a TTL environment through use of a resistive divider network Using this network a TTL LOW level on the input to the divid er creates a PECL LOW at the A B input to the receiver With a TTL or CMOS HIGH into the divider the A B input is placed at or above a PECL HIGH While standard 100K ECL inputs should never be taken above Vcc 700 mV the ECL inputs on the HOTLink Receiver may be connected directly to Voc Without degradation or damage The divider network on this evaluation board may be config ured to be controlled from either the JP4 connector LOOP BACK or from S1 7 DIP RCVA B To avoid possi ble signal contention from these sources the signal is first run through jumper block JP1 Placing a shorting jumper across the X and Y pins of JP1 B allows the receiver port selection to be controlled fro
9. C2 6 022 AS Cl 6 022 gt C13 6 100 C18 LOuF Tant A gt 3514 VCC 35 E f err CY9266 HOTLink Evaluation Board User s Guide ZcypREss_ CY8266 HOTLink Evaluation Board User s Guide Appendix B CY9266 C T Schematic Sheet 3 of 5 SEE S seo ge Sp eee ee x x BS x eRe zB SEEE SE oH E SABAN aigada a s E E o eii Bh 3 5 EE 5 36 _ F p CY9266 HOTLink Evaluation Board User s Guide SES CYPRESS 219266 HOTLInk Evaluation Board User s Guide Appendix B CY9266 C T Schematic Sheet 4 of 5 R20 vec RPACKIS SK RRRRRR 5 RRRRRRRRRITIITI M 123456789012345 1 AAN 6 filefalals efalalololi 23 fals mo 91
10. Once U9 and U10 are removed it is necessary to short elev en adjacent pad pairs on U9 and U10 to allow the receiver yy CYPRESS CY9266 HOTLink Evaluation Board User s Guide data bus to connect to the output connectors The pairs that must be shorted are listed in Table 7 Table 7 OLC Compatibility Register Bypass Connections Register Pin Connections Part Pins Signal Name U10 14 15 RCVR 0 U10 12 13 RCVR_1 U10 10 11 RCVR 2 U10 6 7 RCVR 3 U10 4 5 RCVR 4 U10 2 3 RCVR 5 U9 10 11 RCVR 6 U9 12 13 RCVR 7 U9 14 15 RCVR 8 U9 6 7 RCVR 9 U9 4 5 RDY Copper Cable Connectors The CY9266 C and CY9266 T are assembled on the same substrate and may be configured for use with either coaxial or shielded pair cables Changing from coax to shielded pair requires the removal of the J1 BNC and J2 TNC connectors and replacing them with a female 9 pin D sub connector at location P1 see Appendix B for manufacturer part numbers HOTLink is a trademark of Cypress Semiconductor IBM is a registered trademark of International Business Machines 27 Also the foil traces that connect pins 6 and 9 of P1 to the shield of J1 and J2 located on the bottom of the board must be cut Because the cable impedance used for shielded pair cable is different from that of coax cable the line termination resistors R40 and R41 must be replaced with 750 resistors and coupling transformer T1 must also change to
11. gt wait0 define operational vectors 5 wait0 1 x gt waitl waitl T x gt wait2 wait2 1 x gt enabled enabled Ls 1 gt enabled enabled T7 0 gt locked1 locked1 1 1 gt enabled lockedl Ty 0 gt locked2 locked2 d 1 gt lockedl 15 0 gt locked2 locked2 END TABLE GI 7 41 E poem CY9266 HOTLink Evaluation Board User s Guide S87 CYPRESS CY9266 HOTLink Evaluation Board User s Guide Appendix C BIST PLD Logic Schematic 5 S e E 4 E 3 CMT A 2 E NE E e cs E 5 2 lt lt w a ale Zoos cS E z s ge B 2 eas E aoe ME 2 AA 2 OD MEE seo i lt E Tr E a z i 2 la 8 al A 5 oe a se E 8 8 elo S 2 fs ale cla ka o z 3 4 p a 4 5 4 b 4 b i 4 er EP iis 8 5 z zy 2 w PAY 71 TI lt 3 E 3 u l ESSA 4 E a gt gt 5 z 8 ah lis See ES ol sb zl LANG wl off 5g x o bed o 3 s T e o Easy ers TEN GED yet 5 2135 RESET BISTE 42 Tp ER CY9266 HOTLink Evaluation Board User s Guide SS CYPRESS CY9266 HOTLink Evaluation Board User s Guide
12. 10W 1 0805 Chip Resistor R44 4640 1 10W 1 0805 Chip Resistor 39 SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Appendix B CY9266 C T Parts List continued Instance Part Number Description R42 1 5 kO 1 10W 1 0805 Chip Resistor R56 2 2 kO 1 10W 5 0805 Chip Resistor R63 5100 1 2W Axial Lead Resistor R20 CTS 766 161 R512 or Equivalent 5 1 kO R Pack 15 S016 R38 R39 CTS 766 143 R220 or Equivalent 220 R Pack 7 SO14 AMP 645955 2 or Equivalent 4 Low Profile Socket Pin 3M 929955 06 or Equivalent 4 0 1 Centerline Shorting Jumper Used only for supervisory functions Not needed for communications 40 T _ CY9266 HOTLink Evaluation Board Users Guide IM nii He ni rato Board ners puki Appendix C BIST PLD State Machine Source Code SUBDESIGN bist_sm ready bisten clock INPUT enable OUTPUT VARIABLE ss MACHINE OF BITS enable_q state outputs WITH STATES wait0 0 waitl 0 wait2 0 enabled 0 lockedl T locked2 1 BEGIN ss clk clock Sassign machine clock nable enable_q assign output of machine TABLE present present next 5 5 state inputs states ss bisten ready ss define reset vectors wait0 0 x gt waito waitl 0 x gt wait0 wait2 0 x gt wait0 enabled 0 x gt waito locked1 0 x gt wait0 locked2 0 x
13. 51 8 DIP FOTO is used to enable the OUTA and OUTB differential output drivers of the HOTLink Transmitter When this switch is on closed the differential outputs are allowed to follow the pattern of the data serialized by the transmitter see Figures 8 and 9 When this switch is off open the OUTA and OUTB differential outputs of the transmitter are driven to a logic zero state output is logic LOW output is logic HIGH This places an attached optical transmitter in a state where no light is output or presents no transitions on a copper cable Carrier Detect Polarity Switch S1 9 is used to control the active level of the carri er detect output signal LINK STATUS When this switch is on closed LINK STATUS is driven HIGH when a carrier is present and LOW when one is not When this switch is off open these levels are reversed see Figure 13 13 The carrier detect status is also displayed on one of the dec imal point indicators of the two digit BIST display When the indicator is on a carrier is present The state of S1 9 has no affect on the operation of this indicator Byte Sync Polarity Switch S1 10 is used to control the active level of the BYTE SYNC output signal This level is also affected by the operating mode of the HOTLink Receiver S1 6 see Figure 13 With the HOTLink Receiver in Bypass mode the BYTE SYNC signal is used as a K28 5 SYNC character in dicator With SYNC POL LOW BYTE SYNC is LOW wh
14. Fibre Channel standard Allow full data rate testing of the serial link without expen sive test equipment Allow the user to exercise all modes of operation of the receiver and transmitter Offer various parallel attachment methods for simplified system interfacing Offer various media types for evaluation Allow simple interfacing to existing OLC compatible test platforms Because of the flexibility inherent in the HOTLink parts these goals were easily achieved Three electrical connection methods are provided a 60 pin board edge connector a 58 pin 2x29 0 025 square pin header and a 48 pin 4 x 12 0 025 square pin header These different connectors allow the user to select the con nector form that best suits their desired mode of attachment The HOTLink Transmitter and Receiver contain a BIST capa bility This capability was designed into the HOTLink parts to allow high speed serial testing without expensive test equip ment All hardware necessary to exercise and monitor the BIST function is present on the CY9266 board This hardware allows a bit error rate BER test to be performed without ad ditional equipment The BIST capability of the HOTLink Transmitter and Receiver allows offline testing of the transmitter receiver and serial link by performing a byte by byte comparison of the data while a 511 byte pseudo random byte stream is repeatedly sent received and checked Through use of either JP2 or J
15. Option Select Switch is used for configuring those options of the CY9266 that may be changed on a regular basis or are used to operate the board in a standalone mode These functions are Transmitter BIST Enable Encoder Mode Select Enable Next Parallel Transmitter Data Enable Parallel Transmitter Data Receiver BIST Enable Receiver Mode Select Receiver A B Port Select Transmitter FOTO Enable Carrier Detect Polarity Byte Sync Polarity S1 exists as a 10 position DIP switch The switch positions numbered 1 through 10 are identified on the top of the switch When a switch is on closed the signal connected to that switch is tied directly to ground When a switch is off open the signal on that switch is pulled up through a 5 kQ resistor in R pack R20 These signals are also connected to pins on JP2 and JP3 to allow external logic to control these functions A drawing of the S1 option select switch is shown in Figure 6 Transmitter BIST Enable Switch S1 1 XMIT BISTEN is used to enable the HOTLink Transmitter BIST function When this switch is on closed the BISTEN input to the transmitter is pulled LOW placing the 12 L XMIT BISTEN XMIT MODE XMIT ENN XMIT ENA SWRCVRBISTEN ROV MODE DIP RCV A B DIP FOTO CD POL SYNC POL O JO O JO JO JOP IO JO O JO OJ IOJ jo IO IO 1O IO IO O IO 0168 29 G
16. accessed two ways on the board The eas iest is to cut the foil on the bottom of the board that shorts the X and Y pins of JP1 D together Once cut it will be necessary to place a shorting jumper across these pins to allow JP2 JP3 or S1 to place the transmitter into one of its normal data modes The other method of accessing this mode is to actively bias the XMIT MODE pin on JP2 or JP3 to Vcc 2 When doing so keep in mind that this input also has a 5 kQ pull up resistor attached to this signal The ENN enable next parallel data and ENA enable parallel data inputs are normally used to specify when valid data is present on the transmit data bus Both of these inputs are sampled on the rising edge of CKW at the same time as the 10 bit transmit data bus If ENA is LOW and ENN is HIGH at the rising edge of CKW the data present on the transmit data bus is loaded pro cessed and sent to the shifter If both ENA and ENN are HIGH at the rising edge of CKW the latched data is ignored and a K28 5 SYNC code is sent in its place If ENN is LOW and ENA is HIGH at the rising edge of CKW the data present on the transmit data bus at the next rising edge of CKW is loaded processed and sent to the shifter If both ENN and ENA are HIGH at the rising edge of CKW the data latched on the next rising edge of CKW is ignored and a K28 5 SYNC code is sent in its place These two enable control signals are used to allow different hardware interfaces
17. data bus is composed of the ten signals named XMIT O through XMIT 9 This bus may be driven from any of three possible sources JP2 JP3 or JP4 The data present on this bus is sampled by the HOTLink Transmitter U1 CY7B923 at the rising edge of CKW The information present on the transmit data bus is interpret ed by the HOTLink Transmitter in one of two ways based on the setting of the MODE input to the transmitter When MODE is HIGH Bypass mode all ten signals are accepted as the actual data to be transmitted and are fed directly to the shifter The letter form Da Dj as illustrated in Figure 7 of the bit identifiers is followed for this setting These designators spec ify which encoded data bit is connected to a specific XMIT O to XMIT 9 signal In this mode the user must encode the data into the 10 bit patterns used to send data across the serial interface While it is not necessary to use the 8B 10B code described in the HOTLink datasheet it is advised that this code be used for simplicity If another code is used its is the user s responsibility to insure that sufficient transitions are present in the serial data stream to allow the receiver to prop erly phase lock to the serial data stream For the HOTLink Receiver to provide byte framing and synchronization the K28 5 pattern must be used for framing initialization When the MODE input is LOW Encode mode the internal 8B 10B encoder is enabled In this mode the ten input b
18. from the actual received signal through 10042 resistors to prevent this additional load from distorting the received signal The input signal amplitude necessary to detect either a 1 or a Ois set by the resistor divider shown in Figure 11 To prevent the 10H116 gate from oscillating it is recommended that this threshold be set to a minimum of 50 mV above the termina tion reference voltage The outputs of these two gates are then wire ORed together to charge a capacitor Because of the low on resistance of the emitter follower output transistors of the 10H116 gates the capacitor can be charged quite quickly In the absence of 1 or 0 transitions above the set threshold level this capacitor is discharged both by a bleeder resistor to Veg and through the input of the third gate The third gate is configured as a comparator with feedback to form a Schmitt trigger This feedback is necessary because of the slow transition rate of the input signal to this gate If feedback was not used this gate would oscillate as the input signal slowly passes through the threshold region of the gate The output of this Schmitt trigger is then connected to the HOTLink Receiver INB input which is configured as a PECL to TTL translator Receiver Parallel Interface The receiver parallel interface is used to move the character framed in the HOTLink Receiver to the external world where it can be used This portion of the design consists of five sec tions re
19. from the shifter are sent to the decode register once every ten bit clocks as determined by the framer The 8 bit output from this decoder is then placed on the receiver output data bus bits 00 07 along with the two data status bits SC D and RVS When receiving normal data patterns both the RVS and SC D pins are LOW In this setting the 8 bit data character present on Q0 Q7 is latched at the rising edge of CKR into the exter nal register and presented to the output of the board The two status bits SC D special character data select and RVS received violation symbol are used to indicate recep tion of characters other than those used to represent data When the SC D output is HIGH special control codes see listing in the CY7B923 CY7B933 datasheet have been de coded These control codes are used to indicate framing control status and other supervisory functions across the interface 19 The RVS pin is used for diagnostic purposes When this out put is HIGH the HOTLink Receiver decoder has detected a 10 bit pattern that is not a valid 8B 10B transmission charac ter or sequence When the receiver detects this encoding vi olation it asserts RVS and places information on the 00 7 outputs to represent the type of error detected Because all of these errors are represented with special codes C0 7 C1 7 C2 7 and C4 7 the SC D output is always HIGH when ever RVS is HIGH These possible error type codes are listed in the HO
20. lection of the clock source can only be done through jumper block JP1 The on board oscillator is used primarily for standalone oper ation and testing using the BIST capabilities of the HOTLink parts This clock is selected by placing a shorting jumper across pins X and Y of JP1 20 The XMITCLOCK input is used for normal data transmit re ceive functions and for OLC compatibility mode This clock is selected by placing a shorting jumper across pins JP1 HX and JP1 IX The EXTREFCLK input is used for those instances when the transmitter and receiver are to be clocked with different fre quency clocks This is expected to be used only to test for PLL capture lock range testing of the receiver or when the HOT Link Receiver is connected to a transmitter operating at a different frequency from the local HOTLink Transmitter This clock is selected by placing a shorting jumper across pins JP1 JX and JP1 IX The CKR output clock is generated in the HOTLink Receiver and is based directly on the internal PLL frequency This out put is synchronous with the receiver output data bus and may be used to clock the data into an associated register as is done on this board or into synchronous FIFOs The period and duty cycle of the CKR output clock are fixed by the logic in the receiver To achieve compatibility with OLC type systems the CKR signal is used to generate two new clock signals RCV_CLKO and RCV CLK1 that are true and complement co
21. level enable pin called FOTO fiber optic transmitter off This control input is used to disable all light output from the optical module While not specifically neces sary for LED based optical modules the ability to disable all light output is a safety requirement for all laser based links ANSI 2136 1 and 2136 2 FD A regulation 21 CFR sub chapter J and IEC 825 When FOTO is HIGH the OUTA and OUTB differential pairs are forced to a logic O state OUT is LOW and OUT is HIGH When FOTO is LOW the OUTA and OUTB differential outputs are allowed to follow the serial data pattern from the shifter SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide The FOTO pin on the HOTLink Transmitter may be configured to be controlled from either the JP2 JP3 or JP4 connectors LINK_CONTROL or from S1 8 DIP_FOTO To avoid pos sible signal contention from these sources this signal is first run through jumper block JP1 Placing a shorting jumper across the X and Y pins of JP1 F allows the transmitter FOTO pin to be controlled from the LINK CONTROL signal Moving this jumper to JP1 E allows this selection to be made through S1 8 or through the DIP FOTO signal on JP2 and JP3 If the jumper is omitted from the board the OUTA and OUTB outputs are placed in the disabled state The OUTCz differential output is not controlled by FOTO This output continues to follow the serial shifter data at all times Because it is never d
22. package form of the optical module does provide both and forms of the carrier detect signal only the form is available on the endfire package To allow the same circuitry to be used with either module type only the Carrier detect signal is used Receiver Data Inputs The HOTLink Receiver differential INA and INB inputs are similar but not identical While the INA inputs must always operate as a differential pair the INB signals do not This allows the INB inputs to be split into two separate ECL in puts INB which feeds the shifter and PLL and INB which feeds an ECL to TTL translator The configuration of the INB inputs is controlled by the SO output of the translator While technically an output the SO pin on the HOTLink Receiver also contains sense circuits that monitor the voltage level on the pin during power up If the SO output is connected to Vcc the INB input becomes part of the INB differential serial input If the SO output is normally loaded no resistive pull up to Voc the INB input becomes a single ended serial data receiver and the INB input be comes part of a PECL to TTL translator 17 This split mode is used on the CY9266 Evaluation Board It allows the INB input to be used to convert the PECL carri er detect output of the optical module SIGO to the TTL level signal needed on the receiver parallel interface Receiver Port Select The HOTLink Receiver uses a single ended PECL input
23. selective attenuation to the received sig nal that brings the amplitude and phase of the frequency components in that signal into the same amplitude and phase Because signals transmitted over copper cables are effectively run through a high frequency attenuator the equalizer used for copper cables is a form of low frequency attenuator high pass filter The equalizer used is implemented in a bridged H configura tion that is designed for balanced line operation It is shown on Sheet 4 of the CY9266 C schematic in Appendix B and is constructed using R64 R65 R66 R67 R68 R69 R70 R71 C29 C30 and L1 To implement this equalizer it is necessary to remove the foil shorts across R64 and H71 Copper Carrier Detect The carrier detect circuit used on the CY9266 C and CY9266 T boards is shown in Figure 12 This circuit uses two ECL differential receivers as level comparators to detect the presence of 1 and O level pulses on the incoming signal The gate connected to the top side of the transformer shown in Figure 11 detects the presence of received 1 pulses while the gate connected to the bottom of this transformer detects 18 YAN 150 FROM 100 16 10H116 TO XFMRO VW ao skoi 270 270 RESISTOR gt 150 DIVIDER 348 270 FROM 100 10H116 xFuR gt WV i 0 022uF Figure 12 Copper Interface Carrier Detect the presence of received 0 pulses The input capacitance of these comparators is isolated
24. signals on the board are left open to conserve power Pads are present on the bottom of the board labeled R1 R2 R3 and R4 for bias termination resistors for these outputs While these re sistors are present on the board schematic they are not part of the delivered assembly If the B outputs are used for prob 26 ing or test purposes resistors must be added in these loca tions to enable the output drivers Oscillator The on board oscillator U5 is used primarily for exercising the BIST capability of the board in a standalone mode If the board is only used with an external clock the oscillator does not need to be present This part is socketed to allow the user to select the operating frequency When selecting an oscillator care must be taken to insure the frequency stability and jitter characteristics of the oscillator are within the specifications of the HOTLink Receiver and Transmitter and the intended system application The hole pattern on the board supports direct soldering of the oscillator to the board This should not be attempted on a board that is already equipped with a socket for the oscillator as removal of the socket pins may damage the board BIST Support Hardware The BIST support hardware does not interact with the func tionality of the HOTLink Transmitter or Receiver and is not part of the communications link If there is no requirement for BIST and display hardware the following components may be r
25. the higher inductance type Changing from shielded pair to coax requires removal of the P1 D sub connector and the addition of connectors J1 and J2 It is necessary to connect pin 6 of the P1 pad set to the shield pin of J1 and pin 9 of P1 to the shield pin of J2 Because the cable impedance used for coax cable is different from that of shielded pair cable the line termination resistors R40 and R41 must be replaced with 37 442 resistors and coupling transformer T1 must also change to the lower inductance type Redesign Capability The CY9266 F CY9266 C and CY9266 T boards were de signed strictly as a demonstration vehicle for the Cypress Semiconductor HOTLink family of communications parts The designs shown here may not be optimal for most appli cations as these are expected to be more specialized and may not require all the configuration and BIST demonstration hardware contained on these boards Examination of the evaluation boards will show that the com ponents necessary for creating a serial link are all on one half of the board while the components used for configuration and BIST support are located on the other half of the board This placement of parts was intentional and shows that two com plete channels may be placed on a board of the same size as the CY9266 without placing active components on both sides of the board rac 33 01 9266 HOTLink Evaluation Board User s Guide Appendix A CY9266 F Schemat
26. the optical receiver output This signal is also routed through jumper block JP1 In order for this signal to control the port selection of the receiver itis necessary to have a shorting jumper across the X and Y pins of JP1 C To allow the LOOP_BACK signal on the I O connectors JP2 JP3 and JP4 to control the A B port selection this jumper should be moved to JP1 B DIP Switch Controlled FOTO S1 8 This signal is used to enable the A and B differential output drivers of the HOTLink Transmitter When this signal is LOW the differential outputs are allowed to follow the pattern of the data serialized by the transmitter When this signal is HIGH the A and B differential outputs of the trans mitter are driven to a logic zero state output is logic HIGH output is logic LOW This places an attached optical transmitter in a state where no light is output This signal is also routed through jumper block JP1 In order for this signal to control the FOTO fiber optic transmitter off enable on the transmitter it is necessary to have a shorting jumper across the X and Y pins of JP1 E To allow the LINK_CONTROL signal on the I O connectors JP2 JP3 and JP4 to control the FOTO enable this jumper should be moved to JP1 F CD_POL Input Switched Control Carrier Detect Polarity Select S1 9 This input selects the output polarity of the LINK_STATUS signal When LOW the LINK_STATUS signal is HIGH when a valid carrier is presen
27. 44 CKR3 o RDY gt BIST PLD so ix 99 OO RCVR_9 RVS jS 4 LW SWRCVBISTEN 51 5 MAX707 i 9 RCV_BISTEN S2 RESET Sm The MAX707 is used to monitor the power supply voltage and remove the RESET signal when Vcc is above 4 65V This is a close approximation to the 4 75V RESET threshold speci fied for the OLC card This part also supports an external mechanical switch input that also controls the RESET output This input is controlled by the BIST reset push button switch S2 When this switch is depressed the RESET output is driven LOW until 200 ms after the switch is released This RESET signal is used to clear the BIST error counter located RESET Figure 16 BIST Support Hardware SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide in the BIST PLD U8 The PWR ON indicator is extinguished as long as RESET is active The BIST PLD is a Cypress CY7C344 MAX EPLD pro grammed with the counters and state machines necessary to monitor the status of the receiver outputs and count when BIST compare errors are detected This PLD also drives the decimal points on the attached displays to indicate four status signals These status signals are lt PWR ON Litwhen power is present and above the 4 65V sense threshold lt CAR DET Lit when a valid carrier is present lt BIST WAIT Lit when BIST is enabled but the recei
28. 7 fax id 5100 ol YPRESS 019266 HOTLink Evaluation Board User s Guide Overview This document describes the construction interfaces and operation of the CY9266 F optical fiber CY9266 T shield ed twisted pair twinax and CY9266 C coaxial cable HOTLink Evaluation Boards These boards implement a complete bidirectional parallel to serial and serial to parallel communications link capable of operation at serial rates of 160 to 330 Mbits second 16 to 33 Mbytes second The sup ported rate of communication may be limited by the specific type and speed grade of optical module or copper cable type used The CY9266 Evaluation Boards are optically electrically and mechanically compatible with the ANSI X3T11 Fibre Channel Interface as documented in the ANSI standard ANS X3 230 1994 It provides three different methods of access for the TTL parallel interface and supervisor functions for testing or exercising the serial data link Block Diagram The block diagram in Figure 1 illustrates the major functional blocks contained in the CY9266 These include 10 bit TTL parallel transmit data input 10 bit TTL parallel receive data output Selectable Encoded or Bypass operation modes On board oscillator Selectable internal external clocking Selectable carrier detect polarity Selectable local loopback CY7B923 XMTR CY7B933 lt Power supply voltage monitor Built in self test B
29. 9 HOTLink Transmitter to Copper Serial Interface The copper based CY9266 C and CY9266 T boards use a transformer coupled interface Transformer coupling is called out in the ANSI Fibre Channel standard for copper based in terfaces Its primary advantages are excellent common mode rejection balanced to unbalanced conversion for coaxial ca bles and DC isolation 2 kV hi pot tested The CY9266 C and CY9266 T boards are designed to allow other modes of line biasing and coupling to be used for pre senting a signal into the cable Pads are present on the board to allow a Th venin bias to be used on OUTA These resis tors are identified as R72 and R73 on Sheet 4 of the CY9266 C T schematic see Appendix B The CY9266 C and CY9266 T are designed to operate with cable systems providing a reflection coefficient of zero This means that the receiving end of the cable should be terminat ed in the characteristic impedance of the cable Pads are also present to allow both source termination and AC coupling to the transformer These components are iden tified as R54 R55 C25 and C26 on Sheet 4 of the CY9266 C T schematic see Appendix B To use parts in these locations it is necessary to remove the foil shorts across these component pads on the circuit board The control signal inputs for copper based interfaces operate identically to those of the optical interface The difference in operation is that when the OUTA outputs are disabled
30. 9 VCC 28 27 REC 1 GND 26 I 25 REC O EXTREFCLK 24 23 REC 3 VCC 22 21 REC 4 BYTE SYNC 20 19 LINK ST ATUS GND 18 17 REC 7 GND 16 15 REC 2 XMIT BISTEN 14 13 REC 5 XMIT ENN 12 11 REC 8 XMIT MODE 10 9 REC 6 XMIT ENA 8 7 REC 9 SWRCVBISTEN 6 IL 5 RCV MODE DIP RCWB 4 fh 3 DIP FOTO CD POL 2 1 SYNC POL Figure 3 JP3 Pin Numbering Edge of Board LOOP BACK 36 24 VCC VCC 48 6 6 12 XMITCL OCK GND 35 23 N C LINK_CONTROL 47 11 GND XMIT_0 34 22 XMIT 2 XMIT 5 46 O O O QO 10xMIT XMIT 3 33 21 GND Nc 45 O O O Qexwr 4 XMIT 6 32 20 ENB YTESYNC XMIT 7 4 O O 8 VCC VCC 31 19 RCV_CLK0 E Z XMIT 842 O O Q 7RCV CLKI RESET 30 18 GND XMIT 942 O O 6 REC_0 GND 29 17 REC_1 N Vom GND 41 O O Os5vcc N C 28 16 REC 3 TEN Tax GND 40 O O 4REC 14 REC_2 27 15 VCC YA GND 39 O O 3 886 6 GND 26 14 REC_5 LINK_STATUS 38 2 GND REC 7 25 18 REC 8 BYTE_SYNC 37 O 1 REC 9 Figure 4 JP4 Pin Numbering Top Side of Board View Pins Are On the Bottom SESJ CYPRESS 01 9266 HOTLink Evaluation Board User s Guide Connector Pinouts The CY9266 provides three interface connectors to the user Table 1 1 0 Connector Pinouts JP2 JP3 and JP4 Table 1 shows which signal is present on each connector pin
31. Block Diagram Cypress Semiconductor Corporation 3901 North First Street gt San Jose CA 95134 408 943 2600 October 1993 Revised May 10 1995 yy CYPRESS 01 9266 HOTLink Evaluation Board User s Guide An additional jumper block JP1 is used to configure three of the operating characteristics of the board clock sourcing se rial output enable FOTO and local loopback control Optical Modules The CY9266 F Evaluation Board is designed to operate with industry standard footprint optical modules The evaluation board contains low profile socket pins so the user may select and test optical modules from different vendors This board accepts both the four row DIP and the single row endfire types of modules These modules are available from multiple vendors with ei ther ST or SC type optical fiber connectors Because these modules are all LED based they are not required to meet many of the safety standards ANSI 2136 1 and Z136 2 F D A regulation 21 CFR subchapter J and IEC 825 neces sary for laser based modules These modules should be used with 62 5 125 mm multimode graded index fiber Coaxial Cables The CY9266 C Evaluation Board is configured to support 750 coaxial cables that attach through BNC TNC connectors Other cable impedances may be used with the board by changing the value of the termination and driver bias resistors on the board Shielded Pair Cables The CY9266 T Evaluation Board is conf
32. CY9266 F Schematic Sheet 4 of 5 vee 31 E F s CY9266 HOTLink Evaluation Board User s Guide ses CYPRESS Appendix A CY9266 F Schematic Sheet 5 of 5 32 SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Append
33. CY9266 that are primarily either to protect the board from signal contention or for those signals having multiple sources and destinations These functions are lt Receiver Mode Select lt Receiver Loopback Source Select Transmitter Mode Select Transmitter FOTO Source Select Transmitter Clock CKW Source Select Receiver Reference Clock REFCLK Source Select JP1 exists as a 2 x 10 matrix of 0 025 square pins on the top of the board The rows in this matrix are identified on the top silk screen as A through J The columns are identified as X and Y A drawing of the JP1 jumper block is shown in Figure 5 Oo m RCVMODE Aja a RCV_MODE RCV_AB B L OOPBACK ROV AB C DIP RCV A B XMITMODE D XMIT MODE ENLFOTO E DIP FOTO ENLFOTO LINK CONTROL XMITCIOCK G CK W XMITCIOCK H LCLCLK REFCLK LCLCLK EXTREFCLK J o o LCLCLK KY Figure 5 JP1 Top Side View Receiver Mode Select This jumper ties pins X and Y of JP1 A together It is used to connect the receiver s MODE select pin to the option select switch S1 6 and to allow the HOTLink Receiver mode to be set to the clock Test mode see Figure 13 The three modes of receiver operation are 11 lt Decode Mode S1 6 ON closed Bypass Mode S1 6 OFF open Test Mode JP1 A X and Y open Because this clock Test mode is not normal
34. IST pattern generation and checking hardware with error status display Board Connectors This board offers three primary methods of TTL level access JP2 A 58 position 2 x 29 set of holes capable of ac cepting a 0 025 sq pin header on the top or bottom of the board lt JP3 A 60 position 2 x 30 0 1 spaced board edge finger stock lt JP4 A 48 position 4 x 12 matrix 0 025 sq pin header mounted on the bottom of the board Connectors JP2 and JP3 provided access to all data input and output buses as well as all BIST control and clocking signals for the HOTLink Transmitter and Receiver These con nectors may be used individually or together since all signals present on JP2 are also present on JP3 Power for the board is also brought in through these same connectors Connector JP4 is positioned and pinned to match up with the connector and signals present on other industry standard Fi bre Channel modules Unlike these other modules which may contain two full duplex channels this evaluation board only provides a single full duplex channel While sufficient room exists to build a board with two channels other function ality was added on board oscillator BIST PLD and display etc in this space to allow better testing and demonstration of the enhanced capabilities present in the Cypress HOTLink parts Optical or Copper XMTR Optical or Copper RCVR RCVR BIST Display Figure 1 HOTLink Evaluation Board
35. P3 users may exercise all modes of operation of the parts JP4 is configured as a func tional system interface and thus does not include all the mode clock and special control signals present on JP2 and JP3 all of which may be selected or controlled in JP1 or S1 Connector Pin Numbering JP2 58 Position Pin Header The 58 position pin header JP2 holes are located next to the board edge connector Pin 1 of this connector area is identified on the board by a square solder pad The remaining pin locations use a round solder pad The connector hole pattern is made to accept 58 0 025 square pins soldered into the board The numbering for this connector is shown in Figure 2 Note The numbering of this connector is specified to match up with standard 0 050 centerline flat cable connectors Be cause of the location of pin 1 of this hole pattern the mating pins for this connector should normally be on the bottom of the board If a connector is instead attached to the top side of the board the even and odd numbered pins of the connector are effectively swapped This means that conductor 1 of a cable attached to the top side of the board is in reality con nected to the signal listed for pin 2 in Table 1 JP3 60 Position Board Edge The 60 position board edge connector JP3 is a section of gold plated 0 062 board finger stock that connects to the same signals as JP2 Contact centerline for this connector is 0 1 with even and od
36. RCV CLKi X y JA f o RF Figure 14 Receiver Data Timing Bypass Mode RF HIGH When RF is LOW the RDY and BYTE SYNC outputs operate the same as that shown in Figure 14 The difference is that the clocks are not allowed to change phase or width upon detection of a K28 5 SYNC character The functionality of the RDY and thus BYTE SYNC signal changes when the receiver is in Decode mode receiver MODE is LOW Here the RDY signal pulses LOW for every character received including the K28 5 SYNC character When multiple consecutive SYNC characters are received SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide RDY is inhibited except for the last K28 5 character received This is done to prevent overfilling a receiver FIFO with non data information Figure 15 shows the relative timing re lationships for this type of operation RECEIVER ATA YX K28 5 Y K28 5 DATA ODATA 1 DATA PIPELINE DATA KIDATA Y K28 5 K28 5 DATA OYDATA 1 ag s ap eo 2 BYTE_SYNC JS WAN oes Sese pestes ee e revei V X Naja cA S RF Figure 15 Receiver Data Timing Decode Mode RF LOW Because RF is LOW in Figure 15 the CKR clock and thus RCV_CLKO and RCV CLK1 is not allowed to reframe on new K28 5 SYNC characters detected When RF is HIGH in Decode mode the HOTLink Receiver RDY output ceases pulsing until the first K28 5 SYNC code is detected after which the behavior
37. Receive Clock 1 This is the byte rate recovered clock used for received data The period of this clock is determined by the serial data rate entering the HOTLink Receiver The duty cycle of this signal is determined by the receiver and is fixed at 5096 This clock may experience a large phase jump when reframing to a serial data stream The phasing on this clock is such that the rising edge of the clock occurs near the center of each interval where a character is present on the output received data bus This signal is a buffered and inverted form of the HOTLink Receiver CKR clock RDY Output Clock RDY Ready This signal is used both as a HOTLink Receiver data output clock and a status indicator for the receiver when in BIST mode This is an unbuffered output from the receiver It is normally used to clock valid data from the receiver data bus into asynchronous FIFOs Because of the additional pipeline register in the data bus added for OLC compatibility this signal will operate one byte prior to the data being available at the I O connectors yy CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Table 4 1 0 Signal Descriptions continued Signal Name Group Description BYTE SYNC Output Data Byte Sync Detected This signal is a pipelined form of the receiver RDY output This additional pipeline stage for the RDY signal and the rest of the receiver data bus was added to match the spec
38. S1 1 XMIT MODE S1 2 XMIT ENN S1 3 XMIT ENA S1 4 SWRCVBISTEN S1 5 lt RCV_MODE S1 6 DIP_RCVA B S1 7 lt DIP FOTO S1 8 CD POL S1 9 SYNC_POL S1 10 To allow these signals to be controlled through the ekternal connectors JP2 and JP3 the corresponding 51 switch must be in the off open position Care should be taken when driv ing these signals as any switch inadvertently left in the closed position will present a direct short to ground for an attached driver Control Signals In addition to the Switched Control signals that are only present on JP2 and JP3 three additional control inputs are present that connect to JP2 JP3 and JP4 These control signals are LOOP_BACK lt ENBYTSYNC LINK CONTROL These control inputs are connected directly to the HOTLink Transmitter or Receiver Because the HOTLink parts contain internal pull up resistors on their TTL compatible inputs 10 Signal Name Group Description XMIT_2 Input Data D1 Dc This signal is the D1 Dc input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN XMIT_1 Input Data DO Db This signal is the DO Db input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN XMIT_O Input Data SC D Da This signal is the SC D Da input to the HOTLink Transmitter It is latched into the transmitter i
39. Sheet 5 contains the parallel interface connectors the voltage monitor reset generator and the OLC compatibility registers Theory of Operation The CY9266 Evaluation Board operation is broken down into five functional sections Transmitter Parallel Interface Transmitter to Optical Module or Copper Serial Interface Optical Module or Copper to Receiver Serial Interface Receiver Parallel Interface BIST and Support Hardware Transmitter Parallel Interface The purpose of the transmitter parallel interface is to load parallel data from an external source and move that data to the shifter inside the transmitter This portion of the design consists of three parts the transmit data bus transmitter con 019 9266 HOTLink Evaluation Board User s Guide SESJ CYPRESS _U1 CY7B923 XMIT_0 Sc D Da XMIT_1 DO Db XMIT_2 D1 De XMIT_3 D2 Dd XMIT_4 D3 De XMIT_5 D4 Di XMIT_6 D5 Df XMIT 7 D6 Dg XMIT 8 D7 Dh XMIT_9 SVS Dj 321 Y p XMIT_MODE gt MODE XMIT_BISTEN gt N BISTEN XMIT_ENN N ENN XMIT_ENA JPi ENA X Y XMITCLOCK gt 2 G O CEU A cxw RP H O RP lt O O O O i Y Y Y LCLCLK UI 1 21 3 4 osc Ls 4 4 Figure 7 Transmitter Parallel Interface trol signals and transmitter clocks A simplified schematic of this interface is shown in Figure 7 Transmit Data Bus The transmit
40. TLink datasheet OLC Compatibility Registers In order for this evaluation board to operate in an OLC 266 compatible system the timing of the RDY signal had to be modified This signal from the receiver is used for four func tions to indicate when a K28 5 SYNC character has been received to indicate that valid data has been received to clock valid data into an external asynchronous FIFO and to indicate the end of a BIST loop To support these different functions from a single pin requires the addition of a single register to convert the waveform gen erated by the RDY signal into the BYTE_SYNC status signal the OLC card generates Additional registers were then add ed to the data bits to keep them in the same byte phase rela tionship as the BYTE_SYNC signal which is now delayed one clock The 22Q series termination present on these signals should not be necessary for most systems but are added here to allow a flat cable type attachment to this card Figure 14 shows the relative timing relationships between the HOTLink Receiver data the RDY signal the BYTE_SYNC signal and the output clocks For RDY to operate in this fash ion the RF Reframe enable control input must be HIGH and the receiver must be in Bypass mode receiver MODE is HIGH RECEIVER X mm Y K28 5 YDATA DYDATA 1XDATA 2 PIPELINE 2 X 22 K28 5 YDATA O DATA iy RDY BYTE_SYNC ro T y EA FA NY
41. a FIFO read operation it is only generated in response to the ENA input being pulled LOW Transmitter to Optical Module Serial Interface The transmitter has three differential output pairs that each output the same serial data stream from the shifter Because of the switching speeds used for these serial outputs and for compatibility with optical interface modules they are all im plemented using positive referenced 100K ECL compatible drivers A simplified schematic of the interface present on the CY9266 F is shown in Figure 8 A g 9 82 330 2 LED U1 CY7B923 825 SEIEN OUTA DX a gt FOTO oura h DXN OUTB 130 OUTB P S130 OUTC o Sei OUTC X Y OEO 270 O F O 0 LINK_CONTROL gt si DIP_FOTO 8 TO RECEIVER INB gt 270 SZ lt 7 Figure 8 HOTLink Transmitter to Optical Serial Interface The normal mode of ECL operation is for all signaling to be done at voltages below ground Because the ground point for ECL is only a reference the same signaling can also be im plemented above ground When this is done the reference point changes from ground to Vcc When operated in this mode ECL is often referred to as PECL positive ECL This is the mode of operation for the serial outputs on the transmit ter Two of the differential outputs OUTA and OUTB are also controlled by a TTL
42. a transmitter to another transmitter or a receiver to another receiver When connecting cables to 24 E Transmit Receive Connector Connector Pano J1 BNC Figure 21 J1 and J2 Coaxial Board Connectors a CY9266 C board the cable BNC connector always attach es to a transmit port J1 and the cable TNC connector always attaches to a receiver port J2 TNC BNC dual female barrel connectors e g Amphenol 76400 are available to allow splicing of cables to evaluate multiple lengths of cable Figure 22 illustrates typical TNC and BNC connectors Threaded Neil Councilman Connector TNC Bayonet Neil Councilman Connector BNC Figure 22 TNC BNC Cable Connectors CY9266 T Serial Interface Connections The CY9266 T HOTLink Evaluation Board implements a copper based serial interface This interface uses 02 shielded twisted pair STP cables with 9 pin male D submin iature type connectors STP Board Connectors The CY9266 T HOTLink Evaluation Board has a right angle female 9 pin D subminiature connector Unlike the coaxial ca ble version of the CY9266 which uses separate connectors for transmit and receive the CY9266 T uses only a single connector P1 for both This connector and its location on the board is shown in Figure 23 STP Cable Connector There are presently two STP cable types identified by ANSI for use with Fibre Channel both specify 1500 differential characteristic impedance These cable types are
43. al names used throughout this document I O connector pin names on board signal names and HOTLink Transmitter and Receiver pin names Except for the transmit and receive data buses these names are unique The names used for the transmit and receive data bus pins on connectors JP2 JP3 and JP4 are different from the signal names present on the HOTLink Transmitter and Receiver The functional names for these signals also change depend ing on the current operating mode of the HOTLink Transmitter or Receiver Table 2 lists the transmit data bus signals and the names mapped to them in each transmitter mode The output data bus from the HOTLink Receiver is pipelined with a single register stage between the receiver outputs and the board output pins Table 3 lists the receive data bus sig nals and the names mapped to them in each receiver mode Sn Ss cy PRESS CY9266 HOTLink Evaluation Board User s Guide Table 2 Transmit Bus Signal Name Map Table 3 Receive Bus Signal Name Map a a HOTLink Transmitter Pin Name Receive Bus HOTLink Receiver Pin Name Input Pin Name Encoded Mode Bypass Mode Output Pin Name Decode Mode Bypass Mode XMIT O SCD Da XMIT_1 DO Db XMIT_2 D1 Dc XMIT 3 D2 Dd XMIT 4 D3 De XMIT_5 D4 Di XMIT_6 D5 Df XMIT_7 D6 Dg XMIT_8 D7 Dh XMIT_9 5 5 Dj REC 9 RVS Qj Signal Descriptions The I O signals listed in Table 1 fall into six groups power switched contro
44. ass mode on both the transmitter and receiver The transmitter and receiver are both clocked by the XMITCLOCK signal on JP4 and the receiver A B selection is controlled by the LOOP_BACK signal on JP4 JP1 Settings The CY9266 jumper block JP1 controls many of the options on the board For the CY9266 to operate in an OLC socket jumper block JP1 must be configured with shorting jumpers as shown in Figure 26 The shorting jumper across pins X and Y of JP1 B allows the LOOP_BACK signal in the JP4 connector to control the A B input selection on the HOTLink Receiver The jumper across JP1 A aa RCV_AB B L OOPBACK Coo Doo E oo ENLFOTO c LINK_CONTROL XMITCLOCK G CK W XMITCIOCK H 0 REFCLK 0 J oo X Y Figure 26 JP1 OLC Compatibility Settings SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide pins X and Y of JP1 F allows the LINK CONTROL signal to control the FOTO enable of the HOTLink Transmitter The jumper connecting pins X and Y of JP1 G connects the XMIT CLOCK input to the HOTLink Transmitter CKW clock The jumper connecting pins JP1 HX to JP1 IX connects the XMITCLOCK input to the HOTLink Receiver REFCLK input Note The active signal level of the LOOPBACK signal as implemented on the CY9266 is opposite that of an actual OLC 266 card If this signal is under software control it should be programmed to allow signal loopback when the signal is active LOW For hardware controlled system
45. ation character D0 0 This signal also enables the BIST PLD CY7C344 U8 which is used to monitor the progress and status of the BIST loop through the receiver RDY and RVS outputs When the receiver detects the initialization character itbegins comparing received data with a built in data sequence that can be used to verify the proper functionality of the transmitter receiver and the serial link connecting them The receiver BIST enable is kept separate from the transmitter BIST enable on this board to allow each component to be tested with external patterns that are not part of the BIST sequence RCV_MODE DIP_RCVA B DIP_FOTO Input Switched Control Input Switched Control Input Switched Control Receiver Mode Select S1 6 This signal is used to select whether encoded 10 bit or non encoded 8 bit data is output from the receiver When LOW De code mode this input enables the internal 10B 8B decoder and outputs 8 bit par allel data Q0 Q7 as listed in Table 3 When HIGH Bypass mode the decoder is bypassed and a 10 bit pattern is output Qa Qj as listed in Table 3 DIP Switch Controlled Receiver A B Port Select S1 7 This signal is used to determine which port INA or INB the receiver uses for the input serial data stream When LOW this signal selects the receiver B port that is directly connected to the C port on the transmitter When HIGH this signal selects the receiver A port that is connected to
46. ceiver parallel data output OLC compatibility regis ters receiver clocks receiver control inputs and receiver sta tus outputs A simplified schematic of this interface is shown in Figure 13 Receiver Parallel Data Output The receiver data bus is composed of ten signals named REC 0 through REC 9 This bus drives all three I O connec tors JP2 JP3 and JP4 Due to the external register in the data path these outputs change coincidental with the rising edge of RCV CLKO CKR The information placed on the receiver data bus is deter mined by the HOTLink Receiver MODE select pin When MODE is HIGH Bypass mode allten outputs are the ten bits yy CYPRESS CY9266 HOTLink Evaluation Board User s Guide U2 CY7B933 22 Sc D Qa AWv nzEc_0 Q0 Qb AM REC 1 Q1 Qc AW gt REC 2 osc Q2 Qd AW REC_3 Q3 Qe AWv nzc_4 rt Q4 Qi MN REC_5 XMITCLOCK gt _O HO 05 0 AN REC 6 OIC 06 0g v REC_7 EXTREFCLK gt O JO Q7 oh ANy gt REC 8 RVS Qj MN REC_9 AM BYTE SYNC JPL Y x S RCV_MODE gt A MODE RDY t x gt RDY ENBYTESYNC RF CKRI 4 AN 9 RCV_CLKO RBFCLK L 22 SWRCVBISTEN gt O AM RCV_CLK1 22 so 1 JDM LINK STATUS CD POL t SYNC POL I U8 CY7C344 BIST PLD
47. d User s Guide m 0 500 E yw Ww 4 4 lt Z xz E Elm alu n ui Ole Ole 0625 x DUPLEX X 0 075 SC RECEPTACLE 1 olo 170 32 0 032 ob 180 E ol4 190 030 1540 04 013 200 029 05 oD 210 o28 0 8 06 oll 220 027 07 010 230 026 4 os o9 240 025 33 34 35 36 37 38 39 40 4 Y 0100 0 400 gt 0 600 ye 1000 gt Figure 18 Optical Module Top View Dimensions tect output differentially while the endfire package only pro vides the active HIGH output Table 5 lists the pinouts for this standard footprint optical module The active signals listed in Table 5 are lt SD Signal Detect TD Transmit Data lt RD Receive Data e Case Outer Case of Module e Vcc Positive Supply Voltage Veg Negative Supply Voltage Pins marked Case are not necessarily isolated pins Be cause the optical module is used in the CY9266 F in a PECL mode these Case pins are connected to the VEE ground supply When selecting an optical module care should be taken to insure that the pins marked Case are either floating or are attached to the appropriate power supply rail To allow evaluation of different types of optical modules the CY9266 F Evaluation Board is built using low profile socket pins for the optical module This allows the modules to be easily replaced In addition two slotted holes are provided for a cable tie to
48. d numbered signals on opposing sides of the board To prevent the evaluation board from being plugged into a mating connector backwards and possibly damaging it a 01 9266 HOTLink Evaluation Board User s Guide SESJ CYPRESS LINK CONTROL 57 58 1 OOP BACK GND 55 56 XMITCL OCK XMIT_1 53 54 RP XMIT_2 51 52 GND XMIT_5 49 50 GND XMIT_0 47 48 VCC XMIT_4 45 46 RD Y XMIT_3 43 44 GND XMIT_6 41 42 VCC XMIT_7 39 40 GND ENBYTESYNC 37 38 RESET XMIT_8 35 36 GND RCV CLKO 33 34 VCC RCV_CLK1 31 32 GND XMIT_9 29 30 GND REC_1 27 o 28 VCC REC 0 25 o 26 GND REC 3 23 24 EXTREFCLK REC 4 21 22 VCC LINK STATUS 19 20 8 YTE SYNC REC 7 17 6 6 18 GND REC 2 15 o o 16 GND REC 5 13 14 XMIT BISTEN REC 8 11 12 XMIT ENN REC 6 9 10 XMIT MODE REC 9 7 8 XMIT ENA RCV MODE 5 6 SWRCVBISTEN DIP_FOTO 3 4 DIP RCVA B SYNC POL 1 e 2 CD POL Figure 2 JP2 Pin Numbering Top Side of Board View 0 040 x 0 450 keying slot is present between contacts 3 4 and 5 6 The pin numbering for this connector is shown in Figure 3 Note The numbering of this connector is specified to match up with standard 0 050 centerline flat cable connectors Be cause of the location of pin 1 of this board edge connector the mating connector would normally be a mass terminate board edge to flat cable type connector If a standard board edg
49. e connector is used instead the even and odd numbered pins of the connector are effectively swapped This means that pin 1 of a standard board edge connector is in reality connected to the signal listed for pin 2 in Table 1 JP4 OLC Compatibility Connector The JP4 OLC compatibility connector is located on the bot tom passive component side of the board Pin 1 of this con nector is identified on the board by a square solder pad The remaining pins use a round solder pad Forthe CY9266 Evaluation Board pins of sufficient length are present so that analysis equipment may be attached to these signal pins on the top active component side of the board while it is plugged into a mating connector The numbering sequence for the JP4 connector pins is shown in Figure 4 The connector is made from 48 0 025 square pins soldered into the board To allow full mating with an OLC compatible connector these pins must extend at least 0 250 beyond the bottom surface of the board GND 60 If 59 GND LOOP BACK 58 57 LINK CONTROL XMITCLOCK 56 55 GND RP 54 53 XMIT 1 GND 52 51 XMIT 2 GND 50 49 XMIT 5 VCC 48 47 XMIT 0 RDY 46 I 45 XMIT 4 GND 44 I 43 XMIT 3 VCC 42 D 41 XMIT 6 GND 40 i 39 XMIT 7 RESET 38 37 ENB YTESYNC GND 36 I 35 XMIT 8 VCC 34 33 RCV CLKO GND 32 31 RCV CLK1 GND 30 29 XMIT
50. e present is to allow for the single pulse on RDY that indicates the end of a BIST loop If RDY is ever HIGH for more than one clock the HOTLink Receiver has determined that it is no longer in sync with the transmitter and it starts looking for the start of loop character again Other BIST PLD Functions The complete schematic for the BIST PLD is shown in Appen dix C Other than the BIST state machine the other main logic functions present in the part are for driving the four status indicators and the actual error counter Error Display The error display is made from two hexadecimal LED displays TIL311 These displays are each capable of showing the entire hexadecimal character set 0 9 A F as well as having two independent decimal points These decimal points are used as individual status indicators for the board External Serial Interface Connections The primary difference between the CY9266 card types is in the external high speed serial interface Each of the card types operates with not only a different media type optical coaxial shielded twisted pair but also different connectors and cable types CY9266 F Serial Interface Connections The CY9266 F HOTLink Evaluation Board implements a fi ber optic based serial interface This interface uses indus try standard LED based fiber optic modules that accept SC type fiber optic connectors Optical Modules The CY9266 F HOTLink Evaluation Board is designed to op e
51. eceiver Mode Select Switch S1 6 RCV_MODE is used to select the data decod ing mode of the HOTLink Receiver see Figure 13 When this switch is on closed the internal 10B 8B decoder is enabled and the received 10 bit transmission characters are decoded into 8 bit data characters When this switch is off open the decoder is bypassed and the receiver outputs 10 bit trans mission characters directly to the output data and status pins Receiver A B Port Select Switch S1 7 DIP_RCVA B is used to select which input port A or B the HOTLink Receiver should use for receiving serial data see Figures 10 and 11 While the A B input of the re ceiver is a 100K ECL emitter coupled logic compatible in put itis connected here to allow control from a switch or TTL driver This requires use of an external resistor network con nected between that input and the select switch to allow full rail to rail swings to be used When this switch is on closed the INB input to the HOT Link Receiver is selected This input is directly connected to the OUTC output from the HOTLink Transmitter This is the Local Loopback mode for the CY9266 evaluation board that allows the transmitter and receiver to be tested without an external serial data cable or optical module When this switch is off open the INA differential input of the receiver is enabled to accept data from the optical module U4 or copper cable Transmitter FOTO Enable Switch
52. ect 0 Active Low Carrier Detect 1 Active High Byte Sync 1 1 0 0 Active Low Byte Sync 1 0 0 1 Revr Port Select DIP CX CY Revr Port Select External BX BY FOTO Select DIP EX EY FOTO Select External FX FY Xmtr Clock Local Oscillator GY HY Xmtr Clock XMITCLOCK Gx GY Rcvr Clock Local Oscillator IX lY Revr Clock XMITCLOCK HX IX Revr Clock EXTREFCLK IX JX OLC 266 Mode BX BY FX FY GX GY HX IX 111 110 1 1 1 1 1 BIST Mode w Cable Standalone CX CY EX EY GY HY IX lY 0 0 1 0 1 0 BIST Mode wo Cable Standalone CX CY EX EY GY HY IX lY 0 0 1 O 0 0 These SW1 controlled signals have a 5 1 kW pull up resistor on the CY9266 card and may be controlled externally when the SW1 switch is in the off position With no attached external driver these signals go to a logic 1 state when the SW1 switch position is off Cypress Semiconductor Corporation 1995 The information contained herein is subject to change without notice Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product Nor does it convey or imply any license under patent or other rights Cypress Semiconductor does not authorize its products for use as critical components in life support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user The inclusion of Cypress Semiconductor produc
53. emoved from the board U6 and U7 TIL311 Hex Displays U8 CY7C344 EPLD S2 Reset Switch R21 R22 R23 and R24 1 kQ C13 0 022 uF e C18 100 pF Voltage Monitor The voltage monitor U11 is used as part of the BIST function and also drives the RESET signal on JP2 JP3 and JP4 If monitoring of the specific voltage is not necessary and BIST capability is not used this part may be removed If U11 is removed it may be necessary to bias the RESET line to allow an external system controller to properly sense a high on the RESET output This may be done by soldering a jumper wire from pin 7 of U11 to pin 2 of R20 JP2 The area of the board labeled as JP2 provides a hole pattern designed to accept multiple types of headers and connectors These connectors allow access to all the same signals present on JP4 and JP3 The current pin 1 designation for JP2 assumes a pin header connector designed for flat cable is attached to bottom of the board If this type of connector is instead attached to the top of the board the even and odd pins are effectively swapped in the connector and cable from those listed in Table 1 OLC Compatibility Registers The 74F174 hex D registers U9 and U10 are used to pro vide compatibility with OLC 266 sockets For those users not requiring this capability or for those who wish to use the re ceiver RDY signal to clock received data into asynchronous FIFOs these registers can be removed
54. en a K28 5 SYNC character is present on the receive data bus With SYNC POL HIGH BYTE SYNC is HIGH when a K28 5 SYNC character is present on the receive data bus With the receiver in Decode mode the BYTE SYNC signal is used as a valid data indicator With SYNC POL LOW BYTE SYNC is LOW whenever a usable data byte is present on the receive data bus With SYNC POL HIGH BYTE SYNC is HIGH whenever a usable data byte is present on the receive data bus CY9266 Schematic The complete schematic for the CY9266 F Evaluation Board is shown in Appendix A and the schematic for the CY9266 C and CY9266 T Evaluation Boards is shown in Appendix B Sheet 1 of the top level schematic contains four functional blocks which are detailed on the remaining pages of the schematic Sheet 2 contains the power supply filtering and bypass ca pacitors It also contains a sacrificial Zener diode that is used to protect the components on the board in case of over volt age or incorrect connection of the power supply Sheet 3 contains the BIST PLD and the error status displays Sheet 4 of Appendix A contains the HOTLink Transmitter and Receiver as well as the optical interface module It also con tains the on board oscillator and option select DIP switch Sheet 4 of Appendix B contains the HOTLink Transmitter and Receiver as well as the copper interface and carrier detect circuit It also contains the on board oscillator and option se lect DIP switch
55. ent 5 1 kQ R Pack 15 6 R38 R39 CTS 766 143 R220 or Equivalent 220 R Pack 7 SO14 AMP 645955 2 or Equivalent 41 Low Profile Socket Pin 3M 929955 06 or Equivalent 4 0 1 Centerline Shorting Jumper Used only for supervisory functions Not needed for communications 33 E F a CY9266 HOTLink Evaluation Board User s Guide SS Cyprrss__C 9266 HOTLink Evaluation Board User s Guide Appendix B CY9266 C T Schematic Sheet 1 of 5 RCWR O 9 RCV BISTEN SU RDY RCVR 9 TKR 50 RDY e RCVR 9 CKR e RCV BISTEN RESET XMITRCVR SCH rror Detection SURCVB STEN ERRORDET SCH A SA AN SURCVBISTEN RESET RCVR 10 9 XMIT IO 9 BYPASS SCH f INTLDGIC SCH Byp 34 T CY9266 HOTLink Evaluation Board User s Guide SBP cypress __0 928 HOTLink Evaluation Board Users Guide Appendix B CY9266 C T Schematic Sheet 2 of 5 IN725 01 100pF p C12 O22uF Cll 6 100 CLO 6 022 C8 100pF pT C8 6 022 0 100pF 4 O22uF p C3 100pf
56. er and one output from the HOTLink Receiver The input data bus consists of ten parallel transmit data sig nals that are sampled at the rising edge of the HOTLink Trans mitter CKW clock In addition to these ten signals ENN and ENA while part of the Switched Control signals may also be considered part of the data bus as they are also sampled at this same time While the XMIT BISTEN input is also sam pled at this same time it is not normally used to transfer data and is therefore not considered part of the input data bus yy CYPRESS CY9266 HOTLink Evaluation Board User s Guide The output data bus is comprised of ten parallel received data signals that are synchronous to the HOTLink Receiver CKR clock To meet specific timing requirements for OLC compat ibility there is also an external pipeline register between the HOTLink Receiver data bus output and the received data bus connected to JP2 JP3 and JP4 One other signal BYTE_SYNC is also clocked through this pipeline register and is thus considered part of the data bus All signals on this output bus are series terminated with a 220 inline resistor to minimize transmission line ringing Configuration Settings The CY9266 board may be user configured to allow many modes of operation This configuration is performed through the jumper block JP1 and the option select switch S1 JP1 Jumper Block The JP1 jumper block is used for configuring those options of the
57. f light INA 0 INA 1 the AC coupled inter face used for copper connections does not When the signal 019 9266 HOTLink Evaluation Board User s Guide SESJ CYPRESS gt TO CARRIER DETECT gt TO CARRIER DETECT CARRIER DETECT THRESHOLD U2 CY7B933 INA N INA INB INB SI FROM TRANSMITTER OUTC gt J A B FROM CARRIER DETECT JP1 Y LOOPBACK2 B DIP_RCVA B gt M O C 0 51 7 Figure 11 Copper to HOTLink Receiver Serial Interface is removed the INA and INA inputs to the HOTLink Receiv er are set to the same voltage Because of the high gain present in the HOTLink Receiver to allow use with long cables low amplitude received data the HOTLink Receiver will probably oscillate This oscillation under a no signal condition can be corrected by forcing an offset between the INA and INA inputs but this offset will induce more jitter into the data stream and limit the usable length of a copper based serial link Rather than compromise operational length a carrier de tection circuit can be added to validate the received data in addition to the validation mechanisms present in the data it self The CY9266 C and CY9266 T boards also contain the pads and routing necessary for implementing an equalizer to allow longer cables to be used The function of an equalizer is to present a frequency
58. gnal on JP2 and JP3 If a jumper is not present in either position the transmitter OUTA and OUTB differential drivers are placed in a mode where a differential logic 0 is driven Transmitter Clock Source Select The HOTLink Transmitter CKW clock can be sourced from two different signals LCLCLK from the on board oscillator and XMITCLOCK from JP2 JP3 and JP4 see Figure 7 To select the on board oscillator a shorting jumper should be placed across pins JP1 GY and JP1 HY To select the XMIT CLOCK signal this shorting jumper should be moved to con nect pins X and Y of JP1 G To allow the transmitter to oper ate it is necessary for a jumper to be in one and only one of these two positions Receiver Reference Clock Source Select The HOTLink Receiver REFCLK signal can be sourced from three different signals LCLCLK from the on board oscillator XMITCLOCK from JP2 JP3 and JP4 and EXTREFCLK from JP2 and JP3 see Figure 13 To select the on board oscillator a shorting jumper should be placed across the X and Y pins of JP1 l To select the XMIT CLOCK signal this shorting jumper should be moved to con nect pin X of JP1 l to pin X of JP1 H To select the EXTREF CLK signal used for PLL range testing the shorting jumper should be placed across pin X of JP1 l and pin X of JP1 J To allow the receiver to operate it is necessary for a jumper to be in one and only one of these three positions S1 Option Select Switch The S1
59. he HOTLink Receiver Q5 Qf signal Q4 Qi This signal is a series terminated pipelined form of the HOTLink Receiver Q4 Qi signal REC 4 Output Data Q3 Qe This signal is a series terminated pipelined form of the HOTLink Receiver Q3 Qe signal REC 3 REC 2 Output Data Output Data Q2 Qd This signal is a series terminated pipelined form of the HOTLink Receiver Q2 Qd signal Q1 Qc This signal is a series terminated pipelined form of the HOTLink Receiver Q1 Qc signal REC 1 Output Data QO Qb This signalis a series terminated pipelined form of the HOTLink Receiver QO Qb signal REC 0 XMIT 9 Output Data Input Data SC D Qa This signal is a series terminated pipelined form of the HOTLink Re ceiver SC D Qa signal SVS Dj This signal is the SVS Dj input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN XMIT 8 Input Data D7 Dh This signal is the D7 Dh input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN XMIT 7 XMIT 6 Input Data Input Data D6 Dg This signal is the D6 Dg input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN D5 Df This signal is the D5 Df input to the HOTLink Transmitter It is latched into the transmitter in the r
60. hold the module in place 23 Table 5 Optical Module Pinout DIP Pin Assignments Pin Signal Pin Signal 1 Case 2 No Pin 3 Case 4 VEE 5 VEE 6 SD 7 SD 8 Case 9 Case 10 RD 11 RD 12 Vcc 13 Vcc 14 Vcc 15 Case 16 Case 17 Case 18 Case 19 Vcc 20 Vcc 21 Case 22 TD 23 TD 24 Case 25 Case 26 VBB 27 Case 28 Case 29 VEE 30 VEE 31 No Pin 32 Case Endfire Pin Assignments Pin Signal Pin Signal 33 VEE 34 RD 35 RD 36 SD 37 Vec 38 Vec 39 TD 40 TD 41 VEE Fiber Optic Connector The optical modules specified for use on the CY9266 F HOT Link Evaluation Board listed in Appendix A item U4 are de signed to accept SC type fiber optic connectors These con nectors are available in both simplex single fiber and duplex dual fiber versions Figure 19 shows a simplex SC fiber op tic connector A duplex connector is formed either by joining two simplex connectors together with a clip sometimes re ferred to as a Z clip or by using a connector that supports two fibers in the same form factor The standard optical fiber type used with these connectors and LED based optical mod ules is 62 5 125 mm multimode graded index fiber When using duplex connector cables the cable construction controls which fiber is connected to the transmit LED and which is connected to the receive photodetector When using simplex cables this polarization control is left to the user The t
61. ic Sheet 1 of 5 E B E o eb BeB BE al SB Bee BE TAA WI wW s 898 Sa E amp E g 3 E 5 5 3 5 2 E a m g 3 Bu 2 E 5 2 Hi E A SA CO 5 A 8 ak a E z 8 z 3 E 8 5 8 28 E SESJ CYPRESS CY9266 HOTLink Evaluation Board User s Guide Appendix A CY9266 F Schematic Sheet 2 of 5 NUS NA 615 VCC 29 yy CYPRESS CY9266 HOTLink Evaluation Board User s Guide Appendix A CY9266 F Schematic Sheet 3 of 5 Elo Haa pia a Hag bad x lt x x x 5222 E 5 SE Rasa stella 9 EBRE g SBS g Er 8 ESSE 3 alse SBR 5556 5 Sesssss x IE Sig 5 25 5 25 zb sis g g z jo m leo zb sh g gt Sb 2B Sp 3 ale E a e N 2 ec sil g ES S B 9 30 E SESJ CYPRESS CY9266 HOTLink Evaluation Board User s Guide Appendix A
62. ific timing of the OLC Byte Sync signal The active level of this output is determined both by the operating mode of the HOTLink Receiver and by the state of the SYNC POL input With the HOTLink Receiver in Bypass mode the BYTE SYNC signal is used as a K28 5 SYNC character indicator With SYNC POL LOW BYTE SYNC is LOW when a K28 5 SYNC character is present on the receive data bus With SYNC POL HIGH BYTE SYNC is HIGH when a K28 5 SYNC character is present on the receive data bus With the receiver in Decode mode the BYTE SYNC signal is used as a valid data indicator With SYNC POL LOW BYTE SYNC is LOW whenever a usable data byte is present on the receive data bus With SYNC POL HIGH BYTE SYNC is HIGH whenever a usable data byte is present on the receive data bus REC 9 REC 8 Output Data Output Data RVS Qj This signal is a series terminated pipelined form of the HOTLink Receiv er RVS GQj signal This termination and additional pipeline stage for the RVS Qj signal and the rest of the receive data bus was added to match the specific timing and signal characteristics of the OLC card Q7 Qh This signal is a series terminated pipelined form of the HOTLink Receiver Q7 Qh signal REC 7 Output Data Q6 Qg This signalis a series terminated pipelined form of the HOTLink Receiver Q6 Qg signal REC 6 REC 5 Output Data Output Data Q5 Qf This signal is a series terminated pipelined form of t
63. igured to support 1500 shielded twisted pair or twinaxial cable that attaches through a 9 pin D sub connector Other cable impedances may be used with the board by changing the value of the termination and driver bias resistors on the board BIST Support The CY9266 contains an on board control PLD and a two digit error count display that are used in conjunction with the BIST built in self test capability of tne Cypress Semicon ductor HOTLink Transmitter and Receiver This capability al lows the parts and any serial link to be exercised and mon itored at their full data rate without the use of expensive external test equipment The BIST PLD CY7C344 contains a simple state machine that monitors the HOTLink Receiver BIST state and an er ror counter that drives an external display The complete con tents of this PLD are documented in Appendix C This BIST PLD also drives the four decimal point LEDs on the displays These indicators are used to present additional sta tus information about the state of the board the BIST state machine and the serial link Design Criteria The CY9266 Evaluation Board was designed as a low cost demonstration vehicle for the Cypress Semiconductor HOT Link family of data communications parts The goals of this board are to Present a Fibre Channel interface board that is fully com pliant with the mechanical electrical optical coding and protocol specifications in levels 0 and 1 of the ANSI
64. illustrated in Figure 15 is resumed Receiver Clocks The HOTLink Receiver parallel interface see Figure 13 op erates with a single input clock REFCLK and two output clocks CKR and RDY The REFCLK input clock does not directly clock anything in the receiver but is used as a reference for the receiver PLL This clock is required to be both stable and reasonably accu rate It must match the byte rate frequency of the received data within 0 1 Unlike an OLC card which requires a spe cial sequencing of the LOCK_TO_REF signal to allow the re ceiver to track to a reference clock the HOTLink Receiver PLL continuously operates in a mode that compares its fre quency to that of the reference clock even when valid data is being received If the frequency of the received data varies outside of specific fixed limits the HOTLink Receiver stops locking to the serial data and reverts to the REFCLK Once the received serial data stream returns to an acceptable frequency the PLL again locks to the received data Since it is likely that byte sync has been lost a reframe cycle should be performed to allow the framer to lock up again Detection of this and the recovery process is normally handled automatically by high er level functions in the communications system The REFCLK input to the receiver can be sourced from three different signals on the evaluation board the on board oscil lator the XMITCLOCK input or the EXTREFCLK input Se
65. isabled this signal is used for the local loopback While this signal is available differentially it is con nected to the receiver single ended This allows the INB in put on the receiver to be used as an ECL to TTL translator for the receive optical module s carrier detect signal Because ECL signals are only active in one direction it is necessary to provide a bias load network of some type for the signals to properly switch The typically specified load for ECL signals is 5042 connected to Veg 2V i e 3V for PECL This type of load can be created in many ways For large ECL Systems a separate power supply is usually present to gen erate this bias voltage This provides the lowest power dissi pation For small systems like this one a simpler method is to use two resistors to create a network whose Th venin equivalent is this same 500 connected to Voc 2V This is used for the OUTA differential pair The capacitor present across the Th venin pair is necessary to produce an AC short between the power and ground planes The OUTB output pair is not used on this evaluation board While normal ECL drivers left in this mode would still dissipate a significant amount of power the HOTLink ECL outputs con tain additional internal structures to sense if an output is used or left open and disables the internal current sources of un used output drivers This results in a current savings of ap proximately 5 mA 25 mW for each
66. ising edge of CKW when enabled by ENA or ENN XMIT 5 Input Data DA Di This signal is the D4 Di input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN XMIT 4 XMIT 3 Input Data Input Data D3 De This signal is the D3 De input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN D2 Dd This signal is the D2 Dd input to the HOTLink Transmitter It is latched into the transmitter in the rising edge of CKW when enabled by ENA or ENN SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Table 4 1 0 Signal Descriptions continued Power Signals The CY9266 Evaluation Board is designed to operate from a single 5V 10 DC supply capable of delivering 1 0A typi cal All Voc and GND pins on JP2 JP3 and JP4 are respec tively common to each other There are no distinctions made for separate supplies pins for the different logic sections Switched Control Signals The CY9266 Evaluation Board contains a 10 position DIP switch S1 This switch is connected in parallel with a number of control signals on JP2 and JP3 Each of these control sig nals is pulled up by a 5 kQ resistor through R pack R20 None of these Switched Control signals are available at the JP4 connector The signals present in this group are XMIT_BISTEN
67. its are partitioned into eight data bits D0 D7 and two data modifier bits SC D and SVS For transmitting normal data patterns both the SVS and SC D pins must be LOW In this setting the 8 bit data character present on D0 D7 is latched at the rising edge of CKW and presented to the encoder The encoder then converts the data character into the appropriate 10 bit transmission character Following conversion the transmis sion character is loaded into the shifter 14 The two data modifier bits SC D Special Character Data Se lect and SVS Send Violation Symbol are used to send transmission characters other than those used to represent data When the SC D input is HIGH the normal 8B 10B en coding of the data characters present on D0 D7 is changed Now special control codes are generated see listing in the CY7B923 CY7B933 datasheet These control codes are used to send framing control status and other supervisory functions across the interface The SVS pin is used for diagnostic purposes When this input is HIGH the HOTLink Transmitter shifter is loaded with a 10 bit pattern that is nota valid 8B 10B transmission charac ter When the HOTLink Receiver detects this encoding viola tion it responds with its RVS Received Violation Symbol out put Note The SVS input is intended for diagnostic purposes only If used within normal message traffic it may cause unexpect ed receive errors Transmitter Control Signals I
68. itter mode to be set to the clock Test mode see Figure 7 The three modes of transmitter operation are lt Encode Mode S1 2 ON closed e Bypass Mode S1 2 OFF open lt Test Mode JP1 D X and Y open Because this clock Test mode is not expected to be used for normal data communications testing the jumper JP1 D is permanently wired in place with a foil trace on the bottom of the board For those users who wish to actually place the transmitter in Test mode it may be necessary to cut this foil on the back of the board Once this foil has been cut it will be necessary to use a jump er across JP1 D to allow the two data modes of the transmit ter to be set by the option select switch S1 2 and the XMIT_MODE signal on JP2 and JP3 Transmitter FOTO Source Select This function uses two positions JP1 E and JP1 F of the jumper block to select the source of the HOTLink Transmitter FOTO signal Because this jumper is used to select from one of two sources only one of these two positions E or F may contain a jumper at any one time see Figures 8 and 9 By placing a shorting jumper across pins X and Y of JP1 F the HOTLink Transmitter FOTO signal is then controlled by the LINK_CONTROL signal on JP2 JP3 and JP4 If this shorting jumper is moved to JP1 E then the transmitter FOTO signal is controlled by the option select switch S1 8 SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide and the DIP FOTO si
69. ix A CY9266 F Parts List Instance Part Number Description U1 Cypress CY7B923 JC HOTLink Transmitter U2 Cypress CY7B933 JC HOTLink Receiver U3 74F86 Quad XOR Gate SOIC Package U4 AMP Lytel 269063 1 266 MB s 1300 nm LED Transceiver Hewlett Packard HFBR 5302 Module Siemens TC 266C2EP CTS 1408N or Equivalent U5 CTS CTX126 or Equivalent 25 MHz TTL Clock Oscillator U6 U7 TI TIL311 Hex Display With Logic U8 Cypress CY7C344 15HC 32 Macrocell MAX EPLD U9 U10 74F174 Hex D Register SOIC Package U11 Maxim MAX707CSA or Equivalent Voltage Monitor D1 1N4735A 1W 6 2V Zener Diode 51 AMP 3 435668 0 or Eguivalent 10 position DIP Switch 52 ECG 520 01 3 or Eguivalent Momentary Pushbutton Switch JP1 Sullins PZC10DAAN or Equivalent 2 x 10 Position 0 25 Sq Pin Header JP4 Sullins PZC12DFBN or Equivalent 2 2 x 12 Position 0 25 Sq Pin Header C1 C8 C7 C9 C11 C18 C17 0 022 uF MLC X7R 0805 Chip Cap C2 C4 C8 C10 C12 C18 100 pF MLC NPO 0805 Chip Cap C14 C15 10 uF 16V Tantalum Electrolytic Cap C16 C21 0 1 uF MLC 8 1206 Chip Cap C19 C20 330 pF MLC NPO 0805 Chip Cap R5 R6 R16 R17 820 1 8W 1206 Chip Resistor R7 R8 R18 R19 1300 1 8W 1206 Chip Resistor R9 R12 R13 R14 2700 1 8W 1206 Chip Resistor R15 R21 R22 R28 R24 1 kQ 1 8W 5 1206 Chip Resistor R74 510Q 1 8W 5 1206 Chip Resistor R20 CTS 766 161 R512 or Equival
70. k As a status output its information is valid at the rising edge of CKR This means that the RDY signal must be regis tered to present its status information For normal data trans fer modes the registered form of RDY is used to identify the presence of multiple K28 5 SYNC characters HIGH at rising edge of CKR and of data or control characters LOW at the rising edge of CKR This registered form of RDY generates the BYTE_SYNC signal The RDY signal is also used to identify what phase the HOT Link Receiver BIST mode is in When HIGH for two or more CKR clocks the receiver is looking for the start character of the BIST loop When LOW the receiver is in the BIST loop When HIGH for a single clock the receiver has completed another BIST loop The SO output is used as part of an ECL to TTL translator to specify the current state of the carrier on the serial interface and is used to drive the LINK_STATUS signal When a valid carrier is present and S1 9 CD_POL is off open LINK_STATUS is LOW This polarity is reversed by turning 51 9 on closed or pulling SYNC_POL LOW BIST and Support Hardware The CY9266 Evaluation Board contains not only those com ponents necessary to form a serial link but also a few support components to enhance OLC compatibility and to support the BIST capability in the HOTLink Transmitter and Receiver A simplified schematic of these additional components is shown in Figure 16 U8 CY7C3
71. known as either EIA TIA568 Type 1 and Type 2 or more generically as SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Pins 5 and 9 Receive Data Pins 1 and 6 Transmit Data Figure 23 STP P1 Board Connector IBM Type 1 or Type 2 Both of these cable types contain two individually shielded pairs of solid conductors The Type 2 ca ble also contains four non shielded conductors that are often used for either low speed signaling or voice grade communi cations For installations where the cables may see more flexing a stranded conductor cable is available that meets the 1500 impedance This cable type is commonly known as IBM Type 6 Other cable types may also be used with the CY9266 T HOTLink Evaluation Board The only require ments for the cable are 1500 differential characteristic imped ance and a properly wired see Figure 25 9 pin male D sub miniature connector at each end of the cable Other cable impedances may also be used however the termination R40 and R41 and bias R61 and R62 resistors on the board must then be changed for correct operation Figure 24 shows an example of a compatible STP cable con nector and how the pins in the connector are numbered This is a 9 pin male D subminiature connector While connectors of this type are available with a plastic housing proper oper ation with STP cables requires using connectors having a metal or conductive shell When properly connected as sho
72. l control status clock and data These sig nals are described in Table 4 Table 4 1 0 Signal Descriptions Signal Name Group Description Vcc Power 5 VDC 1 0A typical GND Power Ground XMIT_BISTEN Input Switched Transmitter BIST Enable S1 1 When this signal is LOW the HOTLink Transmit Control ter is placed into its BIST mode Exact operation of the transmitter is also deter mined by the settings of the ENA S1 4 and ENN S1 3 signals With both ENA and ENN HIGH the transmitter outputs an alternating 0 1 pattern D10 2 or D21 5 If either ENA or ENN is LOW the transmitter sends a repeating 511 char acter test sequence The receiver contains a matching mode that allows this trans mitter BIST mode to be used to test the entire serial link without external hardware The transmitter BIST enable is kept separate from the receiver BIST enable on this board to allow each component to be tested with external patterns that are not part of the BIST sequence XMIT_MODE Input Switched Encoder Mode Select S1 2 This signal is used to select whether pre encoded Control 10 bit or non encoded 8 bit data is clocked into the HOTLink Transmitter When LOW Encoded mode this input enables the internal 8B 10B encoder and accepts 8 bit parallel data from the transmitter data bus D0 D7 as listed in Table 2 When HIGH Bypass mode the encoder is bypassed and a 10 bit pattern is accepted Da Dj as listed in Table 2 XMIT_ENN Inp
73. ly used for com munications testing the jumper JP1 A is permanently wired in place with a foil trace on the bottom of the board For those users who wish to actually place the receiver in Test mode it may be necessary to cut this foil on the back of the board Once this foil has been cut it will be necessary to use a short ing jumper across pins X and Y of JP1 A to allow the two data modes of the receiver to be set by the option select switch S1 6 and the RCV MODE signal on JP2 and JP3 Receiver Source Loopback Select This function uses two positions JP1 B and JP1 C of the jumper block to select the source of the HOTLink Receiver loopback signal Because this jumper is used to select be tween one of two sources only one of these two positions JP1 B or JP1 C may contain a shorting jumper at any one time see Figures 10 and 11 By placing a shorting jumper across pins X and Y of JP1 B the receiver loopback A B input is then controlled by the LOOP BACK signal on JP2 JP3 and JP4 If this shorting jumper is moved to JP1 C then the receiver loopback input is controlled by the option select switch S1 7 and the RCV MODE signal on JP2 and JP3 If a jumper is not present in either position the INA path is selected external serial data Transmitter Mode Select This jumper ties pins X and Y of JP1 D together It is used to connect the transmitter MODE select pin to the option select switch and to allow the HOTLink Transm
74. m the LOOP BACK signal Moving this jumper to JP1 C allows this selection to be made through 51 7 or through the DIP RCVA B signal on JP2 and JP3 If the jumper is left off the board the A pair is selected Copper to Receiver Serial Interface The CY9266 C and CY9266 T Evaluation Boards replace the optical module with a transformer coupled electrical inter face The transformer used here provides the same function ality as the one used at the transmit end of the cable A sim plified schematic of the copper cable to receiver serial interface on the CY9266 C T is shown in Figure 1 1 The output side of the transformer connects to two resistors These resistors provide the line termination for the transmis sion line connected to the transformer Two resistors are used for the termination network to allow a reference voltage to be set for the center of the received signal This reference point is set by an external 3 resistor divider and is set in this circuit to Voc 1 3V This is near the center of the common mode range of the MC10H116 ECL receiver that is used to build a carrier detection circuit If this carrier detect circuit is not used it would be better to bias this point at Vcc 1 5V the center of the HOTLink Receiver s common mode range Both of these reference points must be bypassed to allow them to remain stable under dynamic signal conditions Unlike the optical receiver which outputs a logic zero in the absence o
75. n addition to the transmit data bus four other signals are used to control the serial data stream generated by the HOT Link Transmitter Two of these signals BISTEN and MODE control operating modes of the transmitter The other two sig nals ENN and ENA are used to specify when valid data is present on the transmit data bus Unlike the transmit data bus these control signals are not connected to JP4 but are instead connected to JP2 JP3 and separate switches of S1 These switches allow the control inputs to be set LOW or HIGH when an external controller is not present These switches are used both to control BIST mode for standalone applications and to set the proper oper ating characteristics for systems which only connect to JP4 The BISTEN and MODE inputs are used to control which transmission characters are generated by the HOTLink Transmitter Setting BISTEN LOW places the HOTLink Trans mitter into one of two auto pattern generation modes When BISTEN is LOW and both ENN and ENA are HIGH the HOTLink Transmitter sends an alternating 1 0 pattern D10 2 or D21 5 This pattern provides the highest baseband output frequency that the transmitter can generate and is equal to 5x the frequency of CKW This pattern may be useful to test or characterize various serial link components i e fiber optic modules jitter tests etc When BISTEN is LOW and either ENN or ENA is also LOW the HOTLink Transmitter begins a repeating test
76. n the rising edge of CKW when enabled by ENA or ENN these signals may be driven with either open collector buff ers CMOS or TTL drive levels Status Signals Two status output signals RESET and LINK_STATUS are provided at all three I O connectors The RESET signal is a slow speed signal and does not require the series termination used with LINK_STATUS Clock Signals Six signals are available at the I O connectors that are used as clocks in some form Two of these XMITCLOCK and EX TREFCLK are input output clocks that are routed through the JP1 jumper block and three are output clocks These clock signals are XMITCLOCK EXTREFCLK lt RP lt RDY ROV CLKO ROV CLK1 Of the output clocks the RP and RDY signals are only avail able at JP2 and JP3 The RP signal is generated in the HOT Link Transmitter and is used for reading data from asynchro nous FIFOs while the RDY signal is generated in the HOTLink Receiver and is used for writing data into asynchro nous FIFOs When interfacing to clocked FIFOs CY7C44X CY7C45X the RP signal is not normally used Because these signals are not present in JP4 they are not series ter minated The other two output clocks RCV CLKO and RCV CLK1 are a buffered form of the recovered CKR clock from the re ceiver The RCV CLK1 signal is an inverted form of RCV CLKO Data Signals The CY9266 Evaluation Board has two data buses one input to the HOTLink Transmitt
77. ng bit location of each received character Any re ceived K28 5 SYNC code is treated as normal data and is clocked out with the CKR and RDY clocks If this SYNC code is received across two character boundaries the framer does not reframe If the HOTLink Receiver is operating in Decode mode the existence of such a non aligned pattern may gen erate one or more characters in error When RF rises the RDY output is inhibited With RF held HIGH the framer continuously monitors the serial data stream for either disparity form of the K28 5 SYNC character When this character is detected the bit counter used to count yy CYPRESS 019 9266 HOTLink Evaluation Board User s Guide off serial data bits and specify received characier boundaries is asynchronously reset to properly frame the subsequently received bits on character boundaries If the receiver is set to Decode mode the RDY output as sumes its normal function of pulsing LOW for each byte after the first K28 5 SYNC code is detected If the receiver is in stead set to Bypass mode the RDY signal pulses LOW only for the SYNC K28 5 characters while RF is HIGH or LOW Because of characteristics of the 8B 10B code it is possible to transmit legal character sequences that can cause incor rect framing this requires sending control codes other than K28 5 These codes should be avoided while RF is HIGH Once the framer is disabled RF LOW these sequences may be used to pass cont
78. nk Re ceiver REFCLK from an external source other than XMITCLOCK This input may be used to test the tracking and capture range of the receiver PLL It may also be used to operate the receiver at a different data rate from the transmitter To allow the receiver PLL to properly lock to the received serial stream this clock must be within 0 196 of the clock used to generate the received serial data To drive the receiver REFCLK from this clock source a shorting jumper should be placed across pins JP1 IX and JP1 JX The on board oscillator may also be selected to drive the EXTREFCLK line by placing a shorting jumper across pins X and Y of JP1 J With this jumper in place it is still possible to drive the receiver REFCLK input from the on board oscillator by placing a shorting jumper across the X and Y pins of JP1 RCV CLKO RCV CLK1 Output Clock Output Clock Receive Clock 0 This is the byte rate recovered clock used for received data The period of this clock is determined by the serial data rate entering the HOTLink Receiver The duty cycle of this signal is determined by the receiver and is fixed at 5096 This clock may experience a large phase jump when reframing to a serial data stream The phasing on this clock is such that the rising edge of the clock occurs coincident with the start of each interval where a character is present on the output received data bus This signal is a buffered form of the HOTLink Receiver CKR clock
79. nsmitter When this signal is HIGH the A and B differential outputs of the transmitter are driven to a logic zero state output is logic HIGH output is logic LOW This places an attached optical transmitter in a state where no light is output This signal is also routed through jumper block JP1 In order for this signal to control the FOTO enable on the transmitter it is necessary to have a shorting jumper across the X and Y pins of JP1 F To allow the DIP FOTO signal on the I O connectors JP2 and JP3 to control the FOTO enable this jumper should be moved to JP1 E RESET LINK_STATUS Output Status Output Status Reset Power OK This output is used to emulate the voltage monitor function present on the OLC card It remains active LOW until the Vcc input to the board is above 4 65 VDC This output also becomes active when the BIST RESET switch S2 is pressed Link Status This signal operates as a carrier detect status for the serial interface The polarity of this signal is determined by the CD_POL input S1 9 When CD_POL is LOW LINK_STATUS drives HIGH when a carrier is present When CD_POL is HIGH LINK_STATUS drives LOW when a carrier is present RP Output Clock Read Pulse This is a 60 LOW duty cycle pulse train suitable for clocking data out of Cypress s CY7C42X family of asynchronous FIFOs This pulse is generated by the HOT Link Transmitter in response to the XMIT_ENA input being active at the
80. o select which data patterns are sent by the HOTLink Transmitter during BIST operations see Figure 7 If BIST is enabled S1 1 on and S1 3 off setting S1 4 off open causes the transmitter to send an alternating 1 0 pat tern D10 2 or D21 5 When turned on closed it enables an internal pattern generator in the transmitter that produces a repeating sequence of 511 10 bit patterns For normal data transfer operations this switch should remain off with the XMIT ENA signal controlled externally through JP2 and JP3 When operated from the JP4 system connector this switch should be turned on closed because the system hardware yy CYPRESS 019 9266 HOTLink Evaluation Board User s Guide is reguired to provide a valid 10 bit transmission character or data byte for each CKW clock Receiver BIST Enable Switch 51 5 SWRCVBISTEN is used to enable the HOTLink Receiver BIST function see Figure 13 When this switch is on closed the receiver awaits a D0 0 transmission charac ter sent once per BIST loop When this character is detected the BIST state machine in the receiver begins matching the following received transmission characters with its internal pattern generator This pattern generator follows the same sequence of patterns as those sent by the HOTLink Transmit ter when sending its BIST sequence When this switch is off open the HOTLink Receiver oper ates in one of its two data modes Decode or Bypass R
81. pies of the CKR clock To keep matched delays and to minimize the number of additional logic pack ages on the board these two clocks are generated using XOR gates When framing occurs the CKR clock can experience large phase changes These changes are exhibited by a lengthen ing of either the HIGH or LOW portion of the CKR waveform This can be seen in the waveforms shown in Figure 14 While this functionality is not required by the ANSI Fibre Channel Standard it is included in the HOTLink Receiver to protect downstream clocked logic from the narrow pulses or glitches that can occur otherwise The RDY output signal is used both as a status output and as a clock Its use as a clock is primarily for clocking data present on the receiver data bus outputs into asynchronous FIFOs The duty cycle of the RDY pulse and its position relative to the output data is such that it may be directly connected to the W write input on CY7C42X FIFOs Receiver Control Inputs The receiver parallel interface is controlled by three input sig nals RF Reframe MODE Receiver Mode select and BIS TEN BIST Enable The RF input is used to select when the HOTLink Receiver is allowed to reframe acquire byte sync to the incoming serial data stream This input is present to prevent the receiver from mis framing on aliased K28 5 SYNC codes which would cause long running decode errors When RF is LOW the framer is disabled it does not change the starti
82. ransmit and receive connectors on the fiber optic module are shown in Figure 20 SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide e que Figure 19 SC Simplex Fiber Optic Connector P dl Transmit Connector dert Receive Connector Figure 20 U4 Fiber Optic Module Connectors CY9266 C Serial Interface Connections The CY9266 C HOTLink Evaluation Board implements a copper based serial interface This interface uses 750 coax ial cables having BNC and TNC type connectors Coaxial Board Connectors The CY9266 C HOTLink Evaluation Board has two right an gle female coaxial cable connectors a BNC Bayonet Neil Councilman for the J1 transmit connector and a TNC Threaded Neil Councilman as the J2 receive connector These connectors and their location on the board are shown in Figure 21 Coaxial Cable Connectors Many different coaxial cables may be used with the CY9266 C HOTLink Evaluation Board The only require ments for the cable are 75Q characteristic impedance and BNC TNC connectors at each end to attach to the board Oth er cable impedances may also be used however the termi nation R40 and R41 and bias R61 and R62 resistors on the board must then be changed for correct operation Coaxial cables for the CY9266 C should have a BNC con nector on one end and a TNC connector on the other This dual connector mechanism is specified by ANSI to prevent the inadvertent cabling of
83. rate using a de facto standard footprint optical module Any optical module meeting the pinout and dimensions of this de facto standard established originally for FDDI should oper ate with the CY9266 F Note These standard footprint optical modules are available in a wide range of operating data rates Because the operat ing data rate for some of these modules may be outside the 160 to 330 Mbit second operating range of the HOTLink Transmitter and Receiver care should be exercised when se lecting an optical module This footprint supports two types of optical modules those with four rows of vertical pins and those with a single row of pins along the bottom edge In vendor literature these are referred to as DIP and endfire type packages While specified originally for FDDI modules meeting this foot print are also available for Fibre Channel and ATM data rates and meet all optical and mechanical specifications of the Fi bre Channel Standard Figure 18 shows the mechanical foot print dimensions of this de facto standard package Both package types operate from a 5V supply and interface directly with 100K ECL PECL The biggest mechanical differ ence between them is that the endfire type packages have two oversized pins 1 and 32 that are used only to hold the package in place The main electrical difference between the packages types is that the DIP package drives the Signal De yy CYPRESS CY9266 HOTLink Evaluation Boar
84. rising edge of CKW For repeated pulses the RP period is the same as CKW yet is totally independent of the duty cycle of CKW When the transmitter is in BIST mode the RP signal remains HIGH for all but the last byte of the BIST loop where it pulses LOW yy CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Table 4 1 0 Signal Descriptions continued Signal Name Group Description XMITCLOCK Input Output Clock Transmitter External Clock This is the external byte rate clock input This clock is used to drive the transmitter CKW input To allow for operation using the on board oscillator the XMITCLOCK signal is run through jumper block JP1 To operate using an external HOTLink Transmitter clock source a shorting jumper should be placed across pins X and Y of JP1 G To use the on board oscillator instead this shorting jumper should be moved to connect pin JP1 GY to JP1 HY When oper ated from XMITCLOCK the receiver REFCLK may also be set to use this same clock This is done by placing a shorting jumper across pins JP1 GX and JP1 HX To allow the receiver REFCLK to operate from the on board oscillator this jumper should be moved to connect the X and Y pins of JP1 The on board oscillator may also be driven out on the XMITCLOCK line by placing a shorting jumper across pins X and Y of JP1 H EXTREFCLK Input Output Clock External Reference Clock This byte rate clock is used to drive the HOTLi
85. rol information across the interface with out causing the receiver to incorrectly frame the data that follows The MODE input pin on the HOTLink Receiver is used to select both how the received serial data is to be presented on the data bus encoded 10 bit character or decoded 8 bit char acter and to place the receiver into a clock Test mode This input is capable of selecting one of these three possible modes from a single pin through use of an internal three level comparator When the MODE input is LOW the internal 10B 8B decoder is enabled Decode mode This allows the receiver output data bus to be interpreted as an 8 bit data bus Q0 Q7 with two status bits SC D and RVS When the MODE input is HIGH the internal decoder is bypassed Bypass mode This allows the data bus to be interpreted as a 10 bit bus Qa Q Either of these modes may be set from JP2 JP3 or S1 6 The clock Test mode is accessed by allowing the MODE input pin to float Through use of an internal bias network in the receiver the MODE input pin is placed at Vcc 2 This clock Test mode can be accessed two ways on the board The eas iest is to cut the foil on the bottom of the board that shorts the X and Y pins of JP1 A together Following this it will be nec essary to place a shorting jumper across these pins to allow JP2 JP3 or S1 6 to place the receiver into one of its normal data modes The other method of accessing this mode is to actively bias
86. s an ex ternal signal inversion is necessary or the signal may be jum pered at JP1 for operation from the S1 7 DIP switch S1 Settings The S1 DIP switch is also used to configure many of the HOT Link Transmitter and Receiver options The settings for these switches are listed in Table 6 The setting of switches S1 7 and S1 8 are not applicable when jumpers JP1 B and JP1 F are in place Table 6 51 OLC Compatibility Settings DIP Switch Settings Sw State Controlled Signal 1 Off Transmitter BIST Enable 2 Off Transmitter Mode Select 3 Off Enable Next Parallel Xmit Data 4 On Enable Parallel Xmit Data 5 Off Receiver BIST Enable 6 Off Receiver Mode Select 7 N A Switch Controlled Loopback 8 N A Switch Controlled FOTO 9 Off Carrier Detect Polarity Select 10 Off BYTE SYNC Polarity Select Assembly and Options The design of the CY9266 F and CY9266 C T Evaluation Boards offer many different assembly options for those users interested in making modifications for their own evaluation Optical Module Optical module U4 on the CY9266 F is socketed for user evaluation of different optical modules The hole pattern on the board supports direct soldering of the optical module to the board This should not be attempted on a board that is already equipped with a socket for the module because re moval of the socket pins may damage the board Transmitter The HOTLink Transmitter B differential output
87. s the receiver A port that is connected to the optical receiver out put This signal is also routed through jumper block JP1 In order for this signal to control the port selection of the receiver it is necessary to have a shorting jumper across the X and Y pins of JP1 B To allow the DIP RCVA B signal S1 7 also present on JP2 and JP3 to control the A B port selection this jumper should be moved to JP1 C Enable Byte Sync Detect This signal controls when the HOTLink Receiver is allowed to reframe to the incoming serial data e g acquire byte sync When this signal is HIGH each K28 5 SYNC character received in the shifter will frame the data that follows When this signal is LOW the framing logic in the receiver is disabled Because the CKR output of the receiver must line up with the reframed data it is possible to generate significant phase jumps in the CKR clock To prevent the generation of very short high or low pulses on the CKR output which could cause timing violations in downstream logic the Cypress HOTLink Receiver uses look ahead hardware to prevent these short pulses Instead a portion of the clock period for the character preceding the reframed data is lengthened LINK CONTROL Input Control Link Control This signal is used to enable the A and B differential output drivers of the HOTLink Transmitter When this signal is LOW the differential outputs are allowed to follow the pattern of the data serialized by the tra
88. sequence that allows the transmitter and receiver to work together to test the functionality of the entire serial link The repeating sequence is 511 characters in length and includes all stan dard codes as well as patterns that are normally considered code violations This sequence may also be useful for per forming serial link margin tests The MODE input pin is used to select both how the data on the transmit data bus is interpreted encoded or non encod ed and to place the HOTLink Transmitter into a clock Test mode This input is capable of selecting one of these three possible modes from a single pin by use of an internal three level comparator These modes are lt Encode Mode S1 2 ON closed e Bypass Mode S1 2 OFF open Test Mode JP1 D X and Y open SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide When the MODE input is LOW Encode mode the internal 8B 10B encoder is enabled This allows the transmit data bus to be interpreted as an 8 bit data bus D0 D7 with two con trol bits SC D and SVS When the MODE input is HIGH Bypass mode the internal encoder is bypassed This allows the data bus to be interpreted as a 10 bit bus Da Dj Either of these modes may be set from JP2 JP3 or S1 2 The clock Test mode is accessed by allowing the MODE input pin to float Through use of an internal bias network in the transmitter the MODE input pin is placed at Vc c 2 This clock Test mode can be
89. t When HIGH the LINK_STATUS signal is LOW when a valid carrier is present S37 CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Table 4 1 0 Signal Descriptions continued Signal Name Group Description SYNC_POL LOOP BACK ENBYTESYNC Input Switched Control Input Control Input Control Byte Sync Polarity Select S1 10 This input in conjunction with the HOTLink Receiver MODE input selecis the active level of the BYTE_SYNC signal When LOW with the receiver in Bypass mode the BYTE_SYNC signal is LOW when a K28 5 SYNC character is present on the receive data bus When HIGH with the receiver in Bypass mode the BYTE_SYNC signal is HIGH when a K28 5 SYNC character is present on the receive data bus When LOW with the receiver in Decode mode the BYTE_SYNC output remains HIGH for strings of K28 5 SYNC characters or while awaiting the first K28 5 SYNC character after being placed into Reframe mode RF is set HIGH When HIGH with the receiver in Decode mode the BYTE_SYNC output remains LOW for strings of K28 5 SYNC characters or while awaiting the first K28 5 SYNC character after being placed into Reframe mode RF is set HIGH Loopback Control This signal is used to determine which port A or B the HOT Link Receiver uses for the input serial data stream When LOW this signal selects the receiver B port that is connected directly to the transmitter C port When HIGH this signal select
90. tage Monitor U12 Motorola MC10H116FN ECL Tripple Line Receiver D1 1N4735A 1W 6 2V Zener Diode Si AMP 3 435668 0 or Eguivalent 10 position DIP Switch 52 ECG 520 01 3 or Equivalent Momentary Pushbutton Switch or Equivalent RA Female BNC Connector 227161 3 J2 227818 1 or Equivalent RA Female TNC Connector JP1 Sullins PZC10DAAN or Equivalent 2 x 10 Position 0 25 Sq Pin Header JP4 Sullins PZC12DFBN or Equivalent 2 2 x 12 Position 0 25 Sq Pin Header P1 747844 6 or Equivalent RA Female 9 Pin D Sub Connector C14 10 uF 16V Tantalum Electrolytic Cap C1 C3 C7 C9 C11 0 022 uF MLC 8 0805 Chip Cap C13 C27 C2 C4 C8 C10 C12 100 pF MLC NPO 0805 Chip Cap C18 C21 C24 C20 C23 0 01 uF MLC 8 0805 Chip Cap C28 1000 pF 1 kV Y5P Disc Cap T1 Pulse Engineering PE 65507 for STP Dual Wideband Pulse Transformer Pulse Engineering PE 65508 for coax R12 R13 R14 R15 2700 1 8W 5 1206 Chip Resistor R74 5100 1 8W 5 1206 Chip Resistor R21 R22 R28 R24 1 kO 1 8W 5 1206 Chip Resistor R40 R41 37 40 1 10W 196 for Coax 0805 Chip Resistor 75 00 1 10W 1 for STP R43 40 20 1 10W 1 0805 Chip Resistor R49 R50 1000 1 10W 596 0805 Chip Resistor R51 R57 1500 1 10W 1 0805 Chip Resistor R47 R48 R58 R59 27042 1 10W 5 for 15042 cable 0805 Chip Resistor R61 R62 2000 1 10W 5 of 750 cable 0805 Chip Resistor R52 34842 1
91. the RCV_MODE pin on JP2 or JP3 to Vcc 2 When doing so keep in mind that this input also has a 5 kQ pull up resistor attached to the signal The BISTEN input pin is used to place the HOTLink Receiver in a special pattern verification mode This mode is designed to work in conjunction with a matching pattern generation mode in the transmitter While not shown on the schematic in Figure 13 the BISTEN input is actually run through the BIST PLD U8 CY7C344 This is not necessary but is done here to allow other conditioning of the BISTEN signal if desired When the HOTLink Receiver BISTEN input is set LOW the receivers BIST state machine is enabled and enters its self test mode At this point it sets RDY HIGH and begins looking for the BIST start of loop character D0 0 in the serial data stream Once this character is detected the RDY output is driven LOW where it remains until the end of the 511 char acter BIST loop At this point RDY pulses HIGH for one char acter and starts the next 511 byte loop While BIST mode is enabled the RVS output is used to indi cate that a pattern mismatch has occurred This means that 21 the 10 bit pattern received did not exactly match the 10 bit pattern that was expected expected code violations are not errors Receiver Status Outputs The HOTLink Receiver parallel interface generates two status output signals RDY and SO The RDY output is used both for status information and as a cloc
92. through the use of the FOTO signal instead of disabling all light all output transitions are disabled Optical Module to Receiver Serial Interface The HOTLink Receiver has two differential input pairs INA and INB that can both be used to receive the high speed serial data streams generated directly by the transmitter or as output from an optical receiver These serial inputs are also PECL and are directly compatible with the HOTLink Transmit ter ECL was chosen for these signals for the same reasons speed low noise compatibility with optical modules it was used for the transmitter SESJ CYPRESS 019 9266 HOTLink Evaluation Board User s Guide A separate PECL input signal A B is used to select which input pair INA or INB is actually fed to the receiver shifter and PLL A simplified schematic of the optical module to re ceiver serial interface on the CY9266 F is shown in Figure 10 ZN 330pf PIN s2 U2 CY7B933 RECEIVER EE RO INA gt NRO NINA SIGO 130 FROM TRANSMITTER INB OUTC 6 INB SI e ZN 270 mE YZ A B JP1 2705 Y x LOOPBACK gt OBO DIP RCVA B T O 51 7 Figure 10 Optical to HOTLink Receiver Serial Interface Optical Module Signals The optical receiver generates two signals a 100K PECL dif ferential received data signal and a single ended carrier de tect signal While the DIP
93. to be implemented with the least amount usually none of additional data pipelining hardware When one of these enable inputs is used for enable control the other is usually tied HIGH but may be used in conjunction with BISTEN for link testing without affecting the data path controller Transmitter Clocks The transmitter interface operates with both an input clock CKW and an output clock RP The input clock is used to generate both the internal shifter clock and the output clock The CKW input clock can be sourced from either the on board oscillator or from the XMITCLOCK signal This selection is made through jumper block JP1 All internal operations of the HOTLink Transmitter are based on the rising edge of the CKW clock The CKW clock must be generated from a crystal based source While the duty cycle of the CKW clock source is relatively unimportant it must still meet certain minimum pulsewidth times as listed in the CY7B923 CY7B933 datasheet The RP output clock pulse is a modified duty cycle pulse whose HIGH and LOW components are set for operation with asynchronous FIFOs CY7C42X family The phase relation ship of this clock pulse to CKW and its duty cycle both set 15 by the internal PLL are positioned to have valid data on the transmit data bus at the rising edge of CKW This RP clock pulse may be directly connected to the read control pin R of an attached FIFO Because the presence of this pulse signifies
94. ts in life support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges
95. unused output pair The OUTC output pair is biased to Voc 5V ground through 2709 resistors This bias arrangement is used here to reduce the overall component count This type of load may be used for short connections because it provides a similar current load to a Th venin termination but due to asymmetric rise and fall times it induces more jitter into the data This type of biasing should not be considered as a type of line termination If the switching speeds and length of circuit trac es dictate that the line should be terminated a Th venin bias network should be used to match the line impedance Even in those cases where the connection to the optical mod ules is short and a 270 resistor to Vcc 5V may seem to be usable it should not be used While this type of connection may work for very short optical cable lengths the jitter intro duced by the bias network reduces the overall system jitter margin Transmitter to Copper Cable Serial Interface On the CY9266 C and CY9266 T boards the transmitter output is configured to drive either a coaxial or shielded pair cable A simplified schematic of this interface is shown in Fig ure 9 16 U1 CY7B923 E m OUTA T FOTO outa S OUTB4 270 270 OUTB S OUTC outc JP1 X Y ORO 20 OFO o SZ LINK CONTROL gt si 4 DIP FOTO 8 TO RECEIVER INB lt 270 NZ Figure
96. ut Switched Enable Next Parallel Transmitter Data S1 3 This signal is used to control when Control data is loaded into the HOTLink Transmitter When this signal is LOW at the rising edge of CKW the data present on the transmitter inputs at the next rising edge of CKW is loaded processed and sent When this signal is HIGH the transmitter ignores the data present on its inputs at the next rising edge of CKW and instead inserts a SYNC character K28 5 to fill in the data stream When ENA is used for data control the ENN signal should be tied HIGH but may be used to enable BIST mode yy CYPRESS 019 9266 HOTLink Evaluation Board User s Guide Table 4 1 0 Signal Descriptions continued Signal Name Group Description XMIT_ENA SWRCVBISTEN Input Switched Control Input Switched Control Enable Parallel Transmitter Data S1 4 This signal is used to control when data is loaded into the HOTLink Transmitter When LOW at the rising edge of CKW the data present on the transmitter inputs is loaded processed and sent When this signal is HIGH the transmitter ignores the data present on its inputs and instead inserts a SYNC character K28 5 to fill in the data stream When ENN is used for data control the ENA signal should be tied HIGH but may be used to enable BIST mode Receiver BIST Enable S1 5 When this signal is LOW the HOTLink Receiver monitors the data stream for the BIST loop initializ
97. v 2 Figure 6 S1 Option Select Switch transmitter into its BIST loop The exact patterns transmitted are determined by the levels on the XMIT ENN and XMIT_ENA signals located on 51 3 and 51 4 respectively see Figure 7 Encoder Mode Select Switch S1 2 XMIT MODE is used to select the data encod ing mode of the HOTLink Transmitter When this switch is on closed the internal 8B 10B encoder is enabled and the 8 bit data characters are encoded into 10 bit transmission charac ters When this switch is off open the encoder is bypassed and the transmitter accepts 10 bit patterns for direct serializa tion see Figure 7 Enable Next Parallel Transmitter Data Switch 51 3 XMIT_ENN is used along with S1 1 transmit ter BIST enable and 51 4 XMIT_ENA to select which data patterns are sent during HOTLink Transmitter BIST opera tions see Figure 7 If BIST is enabled S1 1 on and S1 4 off setting this switch off open causes the transmitter to send an alternating 1 0 pattern D10 2 or D21 5 When turned on closed it enables an internal pattern generator in the transmitter that generates a repeating sequence of 511 10 bit patterns For normal data transfer operations this switch should remain off with the XMIT ENN signal controlled externally through JP2 and JP3 Enable Parallel Transmitter Data Switch S1 4 XMIT ENA is used along with S1 1 transmit ter BIST enable and 51 3 XMIT ENN t
98. ver has not detected the start of the BIST loop BIST OVFL Lit when the BIST error count exceeds 9 BIST State Machine The BIST state machine has six states that control when a counter is enabled to count pattern match errors A bubble diagram of this state machine is shown in Figure 17 while the MAX PLUS source file for this state machine is listed in Ap pendix C This state machine controls when the error counter is enabled to count It operates off of two input signals BISTEN and RDY Whenever BISTEN is not present the machine is returned to the WAITO state while all state transition arrows are shown for these transitions not all of them are labeled ENABLED D 0 BISTEN RDY RDY B RDY Figure 17 BIST State Machine Bubble Diagram Once BISTEN becomes active the machine goes through two secondary wait states WAIT1 and WAIT2 before start ing to look for RDY being active These wait states are nec essary to allow the receiver time to recognize the BISTEN signal and bring RDY high When the ENABLED state is reached the machine remains in this state until RDY goes LOW causing the machine to move to the first of the two LOCKED states This signifies that the receiver has received the start of loop character D0 0 22 and is now performing matching of the received data bits to its internal pattern generator In the LOCKED states the external counter is enabled to count errors The reason two LOCKED states ar
99. wn in Figure 25 the shield of each pair in the cable is attached to the conductive front shell of the connector To maintain shielding effectiveness it is recommended that the connector backshell strain relief also be metallic or conduc tive Figure 24 STP Cable Connector and Connector Pinout 25 The STP cable is wired in a crossover fashion where the transmit connections at one end of the cable are connected to the receive connections at the other end of the cable as illustrated in Figure 25 The cable shields for both pairs are tied together and connected to the D sub shell at each end XMIT 1 gt lt 1 4XMIT XMIT6 gt O W NANA gt 6 XMIT RCVR 5 gt gt 5 4RCVR RCVR9 gt OOW NANA lt 9 RCVR Le e SHELL gt 4 Cable Shield lt SHELL Figure 25 STP Cable Connectors OLC Mode Configuration The CY9266 Evaluation Board may be configured to operate in an OLC 266 compatible system This emulation is strictly at the TTL parallel interface level the optical and electrical serial interfaces are not compatible In addition the CY9266 is only a single channel board while the OLC 266 is available in either single or dual channel versions The TTL parallel interface attachment is provided through the JP4 connector This connector is pinned and positioned to mate with host systems designed for the OLC 266 board The following configuration sets the CY9266 for 10 bit data and Byp

CY9266 HOTLink™ Evaluation Board User's Guide

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CY9266 HOTLink&trade; Evaluation Board User's Guide

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CY9266 HOTLink™ Evaluation Board User's Guide