Arria V GX Starter Kit User Guide
Contents
1. Figure 6 11 The Clock Control X1 Tab A Clock Control avis JA DTE RYN U4 X1 Serial port registers HS_DIV 9 Target fri z E 5 get frequency MHz 100 00 MHz I RFREQ O2ec6d48b7 Valid frequency range values are ATAL 114 2877 MHz 10 00000000 to 810 00000000 MHz i M Messages USB BlasterII on localhost USB 2 5M 1270ZF324 122102 EPM2210 2 Ls L November 2014 Altera Corporation Chapter 6 Board Test System 6 21 Configuring the FPGA Using the Quartus II Programmer The following sections describe the Clock Control controls Serial Port Registers The Serial port registers control shows the current values from the Si571 registers For more information about the Si571 registers refer to the Si570 Si571 data sheet available on the Silicon Labs website www silabs com fXTAL The fXTAL control shows the calculated internal fixed frequency crystal based on the serial port register values For more information about the fxra value and how it is calculated refer to the Si570 Si571 data sheet available on the Silicon Labs website ww w silabs com Target Frequency The Target frequency control allows you to specify the frequency of the clock Legal values are between 10 and 810 MHz with eight digits of precision to the right of the decimal point For example 421 31259873 is possible within 100 parts per million ppm The2. This chapter provides additional information about the document and Altera Document Revision History The following table shows the revision history for this document Date Version Changes November 2014 1 3 Updated SW1 PCle default switch settings February 2013 1 2 Updates for CE compliance October 2012 1 1 Update for production silicon July 2014 1 0 Preliminary release How to Contact Altera To locate the most up to date information about Altera products refer to the following table Contact Contact Method Address Technical support Website www altera com support Website www altera com training Technical training Email custrain altera com Product literature Website www altera com literature Nontechnical support general Email nacomp altera com software licensing Email authorization altera com Note to Table 1 You can also contact your local Altera sales office or sales representative Typographic Conventions The following table shows the typographic conventions this document uses Visual Cue Meaning Indicate command names dialog box titles dialog box options and other GUI Bold Type with Initial Capital labels For example Save As dialog box For GUI elements capitalization matches Letters the GUI Indicates directory names project names disk drive names file names file name bold type extensions software utility name
3. 11 Set the DIP switch FAC LOAD SW4 3 to the user on 0 position position and power cycle the board The Config Done LED D12 illuminates indicating that the flash device is ready for programming November 2014 Altera Corporation Arria V GX Starter Kit User Guide A 4 Appendix A Programming the Flash Memory Device Restoring the Flash Device to the Factory Settings Programming the board is now complete For more information about the nios2 flash programmer utility refer to the Nios II Flash Programmer User Guide Restoring the Flash Device to the Factory Settings This section describes how to restore the original factory contents to the flash memory device on the starter board Make sure you have the Nios II EDS installed and perform the following instructions Arria V GX Starter Kit User Guide 1 10 11 12 13 Set the board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 21 for more information Click Add File and select lt install dir gt kits arriaV GX_5agxfb3hf35_start factory_recovery a5gx_starter_fpga_bu p_top sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is compl
4. Appendix A Programming the Flash Memory Device CFI Flash Memory Map een a Bein en RE a A 1 Preparing Design Files for Flash Programming 2222eeeeeeeeeeeneneeeeennnen A 2 Creating Flash Files Using the Nios IT EDS 6 ccc cee eens A 2 Programming Flash Memory Using the Board Update Portal 0 000 000 0200 0000 A 3 Programming Flash Memory Using the Nios TI EDS 0 eee A 3 Restoring the Flash Device to the Factory Settings 2 22eeeeeeeeeeeneneeeeennnnn A 4 Restoring the MAX V CPLD to the Factory Settings 6 6 A 5 Additional Information Arria V GX Starter Kit November 2014 Altera Corporation User Guide Contents Document Revision History 666 ene Eae Info 1 Howto Contact Altera iio A nee Info 1 Typographic Conventions euere na a ea ee aan sub Ha lea Info 1 Arria V GX Starter Kit November 2014 Altera Corporation User Guide vi Contents Arria V GX Starter Kit November 2014 Altera Corporation User Guide N DTE RYN 1 About This Kit The Altera Arria V GX Starter Kit is a complete design environment that includes both the hardware and software you need to develop Arria V GX FPGA designs The following list describes what you can accomplish with the kit Kit Features Test signal quality of the FPGA transceiver I Os up to 6 5536 Gbps Develop and test PCI Express PCIe 2 0 designs Develop and test memory subsystems consisting
5. The remaining chapters in this user guide lead you through the following Arria V GX starter board setup steps m Inspecting the contents of the kit Installing the design and kit software Setting up powering up and verifying correct operation of the starter board Configuring the Arria V GX FPGA Running the Board Test System designs For complete information about the starter board refer to the Arria V GX Starter Board Reference Manual Before You Begin Before using the kit or installing the software check the kit contents and inspect the boards to verify that you received all of the items listed in Kit Features on page 1 1 If any of the items are missing contact Altera before you proceed Inspect the Boards To inspect the boards perform the following steps 1 Place the board on an anti static surface and inspect it to ensure that it has not been damaged during shipment A Without proper anti static handling you can damage the board CAUTION 2 Verify that all components are on the board and appear intact In typical applications with the Arria V GX starter board a heat sink is not necessary However under extreme conditions the board might require additional cooling to stay within operating temperature guidelines The board has two holes near the FPGA that accommodate many different heat sinks including the Dynatron V31G You can perform power consumption and thermal modeling to determine whether your appl
6. m PLL lock Shows the PLL locked or unlocked state m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected after channel lock is acquired m Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded and all TX and RX PLL lanes are phase locked to data RX lanes are word aligned and deskewed The Power Monitor The Power Monitor measures and reports current power information To start the application click Power Monitor in the Board Test System application You can also run the Power Monitor as a stand alone application PowerMonitor exe resides in the lt install dir gt kits arriaVGX_5agxfb3hf35_start examples board_test_system directory On Windows click Start gt All Programs gt Altera gt Arria V GX Starter Kit lt version gt gt Power Monitor to start the application The Power Monitor communicates with the MAX V device on the board through the JTAG bus A power monitor circuit attached to the MAX V device allows you to measure the power that the Arria V GX FPGA device is consuming November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 18 Arria V GX Starter Kit User Guide Chapter 6 Board Test System The Power Monitor Figure 6 9 shows the Power Monitor Figure 6 9 The Power Monitor a A Power Monitor ANU S R A General
7. 14 42 ade nies cosa ERA ebbe a en aan TRA er ee 6 6 Character LED rat AA pre Le AAA Renan dew EPA 6 6 User DIP Switches x38 32 222 5a Lees Mee Vole Dew ri los 6 6 User LEDS cess co ois diets each en De E I ERR CER 6 7 Push Button Switches berrespen kagenep k A a m me seadebed des 6 7 The Flash Tab 242 22 212 etie ne ee AA ee sath Magda 6 7 Read zur te ae sa ae E cos en as are ee ee 6 8 Write eos ce eh ehe A AS dq CK avi A A A ee ee 6 8 Random Test uu2 zu0420u05 268 Rp nennen ae er ee 6 8 CF Query ccce ber adhe nn na paid ae ies 6 8 Increment lest vic I en pn le We 6 8 Reset se A AAA AAA AD A A A AAA ERS 6 8 November 2014 Altera Corporation Arria V GX Starter Kit User Guide Contents lnc rr 6 8 Data Display Entry Boxes 2 2 220002 sehe eee bees eb eed b rrr er E bes 6 8 Flash Memory Map sie e RR sede RR bee dee a FER EE 6 8 The SSRAM Tab 2 REPE bb ca 28 ERAS Daa deine FRESE A ad t EE a 6 9 ROG ics 245 4 2424202 ts ee pled kts Anite ehe ee 6 9 WIE essen nennen erben ha OUR aa Rew P CER BA 6 9 The DDR3 Tab ur eye A abide Nee RN 6 10 Start ass as ern Estee AAA ay de ARA DARA A EE eR RE AAA 6 10 npa rm 6 10 Performance Indicators 6 10 Error Control 5 2 enlarge 6 11 Number of Addresses to Write and Read 0 ccc nanan rarae 6 11 The XCVRI Tab uerum a a alta aos 6 12 Channel is sii cbe ae a ek Ec Yd Ree ac eG Sha we a UE eee deck RES 6 12 Statt ee Ecc 6 13 SHOP iv pees eS Speeds ENE ES pia dees Da aan Pee P
8. nios2 terminal and follow the instructions in the terminal window to generate a unique MAC address Ta To ensure that you have the most up to date factory restore files and information about this product refer to the Arria V GX Starter Kit page of the Altera website Restoring the MAX V CPLD to the Factory Settings This section describes how to restore the original factory contents to the MAX V CPLD on the starter board Make sure you have the Nios II EDS installed and perform the following instructions 1 Set the board switches to the factory default settings described in Factory Default Switch Settings on page 4 2 2 Launch the Quartus II Programmer 3 Click Auto Detect 4 Click Add File and select install dir NkitsNarriaVGX 5agxfb3h 35 startNfactory recovery max5 pof 5 Turn on the Program Configure option for the added file 6 Click Start to download the selected configuration file to the MAX V CPLD Configuration is complete when the progress bar reaches 100 St To ensure that you have the most up to date factory restore files and information about this product refer to the Arria V GX Starter Kit page of the Altera website November 2014 Altera Corporation Arria V GX Starter Kit User Guide A 6 Appendix A Programming the Flash Memory Device Restoring the MAX V CPLD to the Factory Settings Arria V GX Starter Kit November 2014 Altera Corporation User Guide ANUTS B AN Additional Information
9. such as 152 198 231 75 proceed to step 8 If no output appears on the LCD or if the Config Done LED D12 does not illuminate continue to step 4 to load the FPGA with a flash writing design 4 Launch the Quartus II Programmer to configure the FPGA with a sof capable of flash programming Refer to Configuring the FPGA Using the Quartus II Programmer on page 6 21 for more information 5 Click Add File and select install dir NkitsNarriaVGX 5agxfb3h 35 startNfactory recovery Na5gx starter fpga bu p top sof 6 Turn on the Program Configure option for the added file 7 Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D12 illuminates indicating that the flash device is ready for programming 8 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell 9 In the Nios II command shell navigate to the install dir NkitsNarriaVGX 5agxfb3hf35 startMfactory recovery directory or to the directory of the flash files you created in Creating Flash Files Using the Nios II EDS on page A 2 and type the following Nios II EDS command nios2 flash programmer base 0x00000000 lt yourfile gt hw flash 10 After programming completes if you have a software file to program type the following Nios II EDS command nios2 flash programmer base 0x00000000 lt yourfile gt sw flash
10. ANU S RYAN 101 Innovation Drive San Jose CA 95134 www altera com UG 01117 1 3 Arria V GX Starter Kit User Guide JA Feedback Subscribe 2014 Altera Corporation All rights reserved ALTERA ARRIA CYCLONE HARDCOPY MAX MEGACORE NIOS QUARTUS and STRATIX words and logos are trademarks eb Altera Corporation and registered in the U S Patent and Trademark Office and in other countries All other words and logos identified as trademarks or service marks are the property of their respective holders as described at www altera com common legal html Altera warrants performance of its semiconductor products to current specifications in accordance with Altera s standard warranty but reserves the right to make changes to any products and services at any time without notice Altera assumes no responsibility or liability arising out of the application or use of any information product or service described herein except as expressly agreed to in writing by Altera Altera customers are advised to obtain the latest version of device specifications before relying on any published information and before placing orders for products or services ISO 9001 2008 Registered November 2014 Altera Corporation Arria V GX Starter Kit User Guide N DTE SYN Contents Chapter 1 About This Kit Kit Eeat res eee ae a ee ke 1 1 Hardware ica RE ee a DERE rl ee see 1 1 SoftWare een oe eae een a As os 1 2 Quartus II Software u ed
11. HSMC installed on the HSMC connector Port A and the SMA loopback cable for all tests to function in external loopback mode Otherwise set the PMA setting tab to test internal loopback mode serial loopback 1 The following sections describe the controls on the XCVR2 tab Channel The Channel control allows you to specify which interface to test The following port tests are available m HSMA x4 XCVR 7 4 m HSMA x9 LVDS 16 8 m SMAx1XCVR November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 16 Arria V GX Starter Kit User Guide Chapter 6 Board Test System Using the Board Test System Start The Start control initiates the active port transaction performance analysis Always click Clear before Start Stop The Stop control terminates transaction performance analysis PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver to the transmitter Enter the following values to enable the serial loopbacks 0 High speed serial transceiver signals to loopback on the board 1 Serial loopback internal loopback 2 Reverse serial loopback pre CDR 4 Reverse serial loopback post CDR m VOD Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m First post 5pecifies the amount
12. Resets the Detected errors and Inserted errors counters to zeros Status These controls display current transaction performance analysis information collected since you last clicked Start m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve m PLL lock Shows the PLL locked or unlocked state m Pattern sync Shows the pattern synced or not synced state The pattern is considered synced when the start of the data sequence is detected after channel lock is acquired m Channel lock Shows the channel locked or unlocked state When locked all lanes are word aligned and channel bonded and all TX and RX PLL lanes are phase locked to data RX lanes are word aligned and deskewed Arria V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 6 Board Test System Using the Board Test System The XCVR2 Tab 6 15 The XCVR2 tab allows you to perform loopback tests on the HSMC and SMA ports Figure 6 8 shows the XCVR2 tab Figure 6 8 The XCVR2 Tab n A Board Test System Detected XCVR2 Project HSMA x4 XCVR 7 4 HSMA x9 LVDS 16 8 SMA x1 XCVR Transceiver PMA Control Error control Detected errors 0 Inserted errors 0 Insert Error Clear PLL lock locked Pattern sync synced Channel lock locked 3125 0400 3125 0352 MBps La You must have the loopback
13. m cu o 0000 1000 0000 17FF A E E 20000 0132 naan Several designs are provided to test the major board features Each design provides data for one or more tabs in the application The Configure menu identifies the appropriate design to download to the FPGA for each tab November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 2 Ls Chapter 6 Board Test System Preparing the Board After successful EPGA configuration the appropriate tab appears that allows you to exercise the related board features Highlights appear in the board picture around the corresponding components The Power Monitor button starts the Power Monitor application that measures and reports current power information for the board Because the application communicates over the JTAG bus to the MAX V device you can measure the power of any design in the FPGA including your own designs The Board Test System and Power Monitor share the JTAG bus with other applications like the Nios II debugger and the SignalTap II Embedded Logic Analyzer Because the Quartus II programmer uses most of the bandwidth of the JTAG bus other applications using the JTAG bus might time out Be sure to close the other applications before attempting to reconfigure the FPGA using the Quartus II Programmer Preparing the Board With the power to the board off following these steps 1 Connect the USB cable to the b
14. of pre emphasis on the first post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Pattern The Data Pattern control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS 7 Selects pseudo random 7 bit sequences m PRBS 15 Selects pseudo random 15 bit sequences m PRBS 23 Selects pseudo random 23 bit sequences 8 PRBS 31 Selects pseudo random 31 bit sequences Error Control The Error Control control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transmit data stream m Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros November 2014 Altera Corporation Chapter 6 Board Test System 6 17 The Power Monitor Status These controls display current transaction performance analysis information collected since you last clicked Start m TX and RX performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve
15. t occupy a flash location that contains the image of another user software design file The Board Update Portal standard flash format conventionally uses either filename hw flash for hardware design files or filename sw flash for software design files November 2014 Altera Corporation Appendix A Programming the Flash Memory Device A 3 Programming Flash Memory Using the Board Update Portal Programming Flash Memory Using the Board Update Portal Once you have the necessary flash files you can use the Board Update Portal to reprogram the flash memory Refer to Using the Board Update Portal to Update User Designs on page 5 2 for more information If you have generated a sof that operates without a software design file you can still use the Board Update Portal to upload your design In this case leave the Software File Name field blank Programming Flash Memory Using the Nios Il EDS The Nios IT EDS offers a nios2 flash programmer utility to program the flash memory directly To program the flash files or any compatible S Record File srec to the board using nios2 flash programmer perform the following steps 1 Set the DIP switch FAC LOAD SW4 3 to the factory off 1 position factory design to load the Board Update Portal design from flash memory on power up 2 Attach the USB Blaster cable and power up the board 3 Ifthe board has powered up and the LCD displays either Connecting or a valid IP address
16. 0000015 00000016 00000017 0000 0060 00000018 00000019 0000001A 0000001B 0000 0070 0000001C 0000001D 0000001E 0000001F 0000 0080 00000020 00000021 00000022 00000023 0000 0090 00000024 00000025 00000026 00000027 0000 00A0 00000028 00000029 0000002A 0000002B 0000 00B0 0000002C 0000002D 0000002E 0000002F 0000 00C0 00000030 00000031 00000032 00000033 0000 00D0 00000034 00000035 00000036 00000037 0000 00E0 00000038 00000039 0000003A 0000003B 0000 00F0 0000003C 0000003D 0000003E 0000003F 0000 0100 00000040 00000041 00000042 00000043 0000 0110 00000044 00000045 00000046 00000047 0000 0120 00000048 00000049 0000004A 0000004B 0000 0130 0000004C 0000004D 0000004E 0000004F 0000 0140 00000050 00000051 00000052 00000053 0000 0150 00000054 00000055 00000056 00000057 0000 0160 00000058 00000059 0000005A 0000005B The following sections describe the controls on the SSRAM tab The Read control reads the SSRAM on your board To see the SSRAM contents type a starting address in the text box and click Read Values starting at the specified address appear in the table Write The Write control writes the SSRAM on your board To update
17. 8A 62F45ABF CA1AB44F BB13944C O7FE 0060 A93489AB C38CABEE ODA41CC7 8CBAB444 O7FE 0070 C7EA72BB 5FC7B497 932AE9C1 F7B80574 Address 0x07FE 0000 O7FF FFFF The following sections describe the controls on the Flash tab November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 8 Chapter 6 Board Test System Using the Board Test System The Read control reads the flash memory on your board To see the flash memory contents type a starting address in the text box and click Read Values starting at the specified address appear in the table If you enter an address outside of the flash memory address space a warning message identifies the valid flash memory address range Write The Write control writes the flash memory on your board To update the flash memory contents change values in the table and click Write The application writes the new values to flash memory and then reads the values back to guarantee that the graphical display accurately reflects the memory contents Random Test Starts a random data pattern test to flash memory which is limited to a scratch page in the upper 128K block CFI Query The CFI Query control updates the memory table displaying the CFI ROM table contents from the flash device Increment Test Starts an incrementing data pattern test to flash memory which is limited to a scratch pag
18. Core functions You can evaluate MegaCore functions by using the OpenCore Plus feature to do the following m Simulate behavior of a MegaCore function within your system m Verify functionality of your design and quickly and easily evaluate its size and speed m Generate time limited device programming files for designs that include MegaCore functions m Program a device and verify your design in hardware Lo The OpenCore Plus hardware evaluation feature is an evaluation tool for prototyping only You must purchase a license to use a MegaCore function in production e For more information about OpenCore Plus refer to AN 320 OpenCore Plus Evaluation of Megafunctions November 2014 Altera Corporation Chapter 1 About This Kit 1 3 Kit Features m Nios II Embedded Design Suite EDS A full featured set of tools that allows you to develop embedded software for the Nios II processor which you can include in your Altera FPGA designs Arria V GX Starter Kit Installer The license free Arria V GX Starter Kit installer includes all the documentation and design examples for the kit For information on installing the Development Kit Installer refer to Installing the Arria V GX Starter Kit on page 3 2 November 2014 Altera Corporation Arria V GX Starter Kit User Guide 1 4 Chapter 1 About This Kit Kit Features Arria V GX Starter Kit November 2014 Altera Corporation User Guide NOTE SJAN 2 Getting Started
19. GA 3 When configuration finishes close the Quartus II Programmer if open The design begins running in the FPGA The corresponding GUI application tabs that interface with the design are now enabled La If you use the Quartus II Programmer for configuration rather than the Board Test System GUI you may need to restart the Board Test System The System Info Tab The System Info tab shows board s current configuration Figure 6 1 on page 6 1 The tab displays the contents of the MAX V registers the JTAG chain the board s MAC address the flash memory map and other details stored on the board The following sections describe the controls on the System Info tab November 2014 Altera Corporation Arria V GX Starter Kit User Guide Arria V GX Starter Kit Chapter 6 Board Test System Using the Board Test System Board Information The Board information controls display static information about your board Board Name Indicates the official name of the board given by the Board Test System Board P N Indicates the part number of the board Serial number Indicates the serial number of the board Factory test version Indicates the version of the Board Test System currently running on the board MAC Indicates the MAC address of the board MAX V ver Indicates the version of MAX V code currently running on the board The MAX V code resides in the lt install dir gt kits arriaV GX_5agxfb3hf35_start examples d
20. Information Power Information MAX V Version 1 Power Rail ycc yccp RMS Maximum Minimum mAmp 193 198 0 400 mA 200 Messages G raph Settings connections USB BlasterII on localh Scale Select Update Speed ost USB 2 5M 1270ZF324 2210Z EPM2 21062 Fast v The following sections describe the Power Monitor controls General Information The General information controls display the following information about the MAX V device MAX V version Indicates the version of MAX V code currently running on the board The MAX V code resides in the install dir NkitsNarriaVGX 5agxfb3h 35 startNfactory recovery and install dir NkitsNarriaV GX_5agxfb3hf35_start examples max5 directories Newer revisions of this code might be available on the Arria V GX Starter Kit page of the Altera website Power rail Selects the power rail to measure After setting the Power rail list to the desired rail click Reset to refresh the screen with new board readings Arria V GX Starter Board Reference Manual November 2014 Altera Corporation A table with the power rail switch positions information is available in the Chapter 6 Board Test System 6 19 The Clock Control Power Information The Power information control displays current maximum and minimum power readings for the following unit E mAmp Power Graph The power graph displays the mA power consumption of your bo
21. PMA Setting Data pattern Error control Q PRBS 7 Detected errors 0 PRBS 15 Inserted errors 0 PRBS 23 _InsertError Clear PRBS 31 Status Tx Rx PLL lock locked Pattern sync synced Detected XCVR1 Project a Channel lock locked La You must have the loopback HSMC installed on the HSMC connector Port A and the SDI loopback cable for all tests to function in external loopback mode Otherwise set the PMA setting tab to test internal loopback mode serial loopback 1 The following sections describe the controls on the XCVR1 tab Channel The Channel control allows you to specify which interface to test The following port tests are available m HSMA x4 XCVR 3 0 m HSMA x8 LVDS 7 0 m HSMA x3 CMOS Arria V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 6 Board Test System 6 13 Using the Board Test System gt m SDIx1XCVR Start The Start control initiates the active port transaction performance analysis Always click Clear before Start Stop The Stop control terminates transaction performance analysis PMA Setting The PMA Setting button allows you to make changes to the PMA parameters that affect the active transceiver interface The following settings are available for analysis m Serial Loopback Routes signals between the receiver to the transmitter Enter the following values to enable the serial loopbacks 0 High speed serial tra
22. Target frequency control works in conjunction with the Set New Frequency control This control reads the current frequency setting for the oscillator associated with the active tab Clear Default This control sets the frequency for the oscillator associated with the active tab back to its default value This can also be accomplished by power cycling the board Set New Frequency This control sets the programmable oscillator frequency for the selected clock to the value in the Target frequency control for the Si571 and the Frequency controls for the 515338 U4 Frequency changes might take several milliseconds to take effect You might see glitches on the clock during this time Altera recommends resetting the FPGA logic after changing frequencies Configuring the FPGA Using the Quartus Il Programmer You can use the Quartus II Programmer to configure the FPGA with your own sof Before configuring the FPGA ensure that the Quartus II Programmer and the USB Blaster II driver are installed on the host computer the USB cable is connected to the starter board power to the board is on and no other applications that use the JTAG chain are running To configure the Arria V GX FPGA perform the following steps 1 Start the Quartus II Programmer November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 22 Chapter 6 Board Test System Configuring the FPGA Using the Quartus II Programmer Click Auto Detect to display the d
23. a V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 6 Board Test System 6 11 Using the Board Test System m Write MBps Read MBps and Total MBps Show the number of bytes of data analyzed per second Error Control The Error Control control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transaction stream m Insert Error Inserts a one word error into the transaction stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear Resets the Detected errors and Inserted errors counters to zeros Number of Addresses to Write and Read The Number of addresses to write and read control determines the number of addresses to use in each iteration of reads and writes November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 12 Chapter 6 Board Test System Using the Board Test System The XCVR1 Tab The XCVRI tab allows you to perform loopback tests on the HSMC and SDI ports Figure 6 7 shows the XCVRI tab Figure 6 7 The XCVR1 Tab n A Board Test System m m gt Configure Help About Channel HSMA x4 XCVR 3 0 Start HSMA x8 LVDS 7 0 HSMA x3 CMOS SDI x1XCVR Transceiver PMA Control
24. aes 6 13 PMA Setting c24csceedcageen age rape ee anna aaa caged tee reed er 6 13 Data Pattern r satis sur ee A ri EC A eee eed 6 13 Error Control sia RU VERFU RE E EM eee eee hee Bernd 6 13 Status sy ac E EAE E A A E S 6 14 The XCVR2 T b dure bte bated avn nnn b e ee Re re u 6 15 Channel iii ea en a ee ra d CER ES 6 15 Statt e M ee hatte cae Rie eee oie ee N a taal 6 16 SHOP i Pees es ae ey biu ob c PX G ER Pes a eee a qox pra red 6 16 PMA Setting 22 2 02 ee ke 4 eECE X REPE Lene aa iA vu ete v pre dried es 6 16 Data Pattern I EE 6 16 Error Control 2 42 senda os a eh EE URINE NR Sad ns AGRO ee Pea E 6 16 Status a ERG IP aha heh awh eee Ree BA OOS hia Pk eee es 6 17 The Power Monitor 6 17 General Information seller rre 6 18 Power Information sekesi i 2 REY Yee ERE YER Erde le ped a 6 19 BOWer Graph p E 6 19 Graph Settings secos su cathy tates aaa ate eek ed ot era 6 19 Reset beide aan Le Y EE Le de 6 19 The Clock Control reia allen re PR 6 19 Serial Port Registers ea a he RE PEREAT E EE PE EE 6 21 A do so att Aog 6 21 Target Frequency ii rele E cea od estet bw detecte wees 6 21 Reade reri tease eh ants nea ahs an wets eka ae ir et ica Nos ata Noses Sea argh ede EE EE 6 21 Clear Default cients etse ceterae E DE E EI RU ok eas ay ees tee 6 21 Set NEW Frequency use ce ue aeree eee e etd eo ett dte Dd o Mee eee d es 6 21 Configuring the FPGA Using the Quartus II Programmer 00060 c cece eee e 6 21
25. ard over time The green line indicates the current value The red line indicates the maximum value read since the last reset The yellow line indicates the minimum value read since the last reset Graph Settings The following Graph settings controls allow you to define the look and feel of the power graph m Scale select Specifies the amount to scale the power graph Select a smaller number to zoom in to see finer detail Select a larger number to zoom out to see the entire range of recorded values m Update speed Specifies how often to refresh the graph Reset This Reset control clears the graph resets the minimum and maximum values and restarts the Power Monitor The Clock Control The Clock Control application sets the 1571 programmable oscillator to any frequency between 10 MHz and 810 MHz with eight digits of precision to the right of the decimal point The 515338 device has four independently programmable outputs All four outputs are programmable between 16 KHz and 350 MHz All four outputs can support the higher frequencies but they cannot be programmed for multiple frequencies above 350 MHz If you want multiple outputs above 350 MHz all outputs above 350 MHz must be the same frequency and must be frequencies from 367 MHz to 473 33 MHz or from 550 MHz to 710 MHz Channel 0 of 15338 drives a 2 to 4 buffer that drives a copy of the clock to all four edges of the FPGA The Clock Control application runs as a stand al
26. date Portal design example stored in the factory portion of the flash memory on the board The design consists of a Nios II embedded processor an Ethernet MAC and an HTML web server When you power up the board with the FAC_LOAD SW4 3 in the factory off 1 position the Arria V GX FPGA configures with the Board Update Portal design example The design can obtain an IP address from any DHCP server and serve a web page from the flash on your board to any host computer on the same network The web page allows you to upload new FPGA designs to the user hardware 1 portion of flash memory and provides useful kit specific links and design resources gt gt After successfully updating the user hardware 1 flash memory you can load the user design from flash memory into the FPGA To do so set the FAC_LOAD SW4 3 to the user on 0 position and power cycle the board The source code for the Board Update Portal design resides in the lt install dir gt kits arriaVGX_5agxfb3hf35_start examples directory If the Board Update Portal is corrupted or deleted from the flash memory refer to Restoring the Flash Device to the Factory Settings on page A 4 Connecting to the Board Update Portal Web Page This section provides instructions to connect to the Board Update Portal web page Lo Before you proceed ensure that you have the following m A PC with a connection to a working Ethernet port on a DHCP enabled network m A separate working Ethe
27. e developed using the Nios II EDS follow these instructions 1 On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell 2 In the Nios Il command shell navigate to the directory where your design files reside and type the following Nios II EDS commands m For Quartus II sof files at user hardware 1 location sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x01640000 pfl optionbit 0x00018000 programmingmode FPP m For Quartus II sof files at user hardware 2 location sof2flash input lt yourfile gt hw sof output lt yourfile gt hw flash offset 0x02C60000 pfl optionbit 0x00018000 programmingmode FPP m For Nios II elf files elf2flash base 0x00000000 end 0x07FFFFFF reset 0x05280000 input lt yourfile gt sw elf output lt yourfile gt sw flash boot SOPC KIT NIOS2 components altera nios2 boot loader sources boot loader cfi sre ce CAUTION Arria V GX Starter Kit User Guide The resulting flash files are ready for flash device programming If your design uses additional files such as image data or files used by the runtime program you must first convert the files to flash format and concatenate them into one flash file before using the Board Update Portal to upload them If you have elf files for both user hardware 1 and user hardware 2 design you need to make sure the user software reset location doesn
28. e in the upper 128K block Reset The Reset control executes the flash device s reset command and updates the memory table displayed on the Flash tab Erase Erases flash memory which is limited to a scratch page in the upper 128K block Data Display Entry Boxes There are 8 rows and 4 columns Each column contain 8 hexadecimal numbers After entering the numbers in each cell press Enter on your keyboard Then click Write and Read button Flash Memory Map Displays the U12 flash device memory map for the Arria V GX Starter Kit Arria V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 6 Board Test System Using the Board Test System The SSRAM Tab 6 9 The SSRAM tab allows you to read and write SSRAM and flash memory on your board Figure 6 5 shows the SSRAM tab Figure 6 5 The SSRAM Tab Configure Help About System info GPIO Flash SRAM Start address 0000 0000 0000 0000 Range 0x0000 0000 Ox001F FFFF fa ume fundis fee n Aswan Ss m SSRAM 00000000 00000001 00000002 00000003 Messages Detected the GPIO SRAM Flash Project 0000 0010 00000004 00000005 00000006 00000007 0000 0020 00000008 00000009 0000000A 0000000B 0000 0030 0000000C 0000000D 0000000E 0000000F 0000 0040 00000010 00000011 00000012 00000013 0000 0050 00000014 0
29. ea Ha DER REX a RR eee 1 2 Arria V GX Starter Kit Installer 2 0 0 cee etn ene 1 3 Chapter 2 Getting Started Before VOU Begin ses une a ne ae awe editus edis teen EEEE 2 1 Inspect the Boards viii A a 2 1 hona MERC in A A AS EE EE a Ati 2 1 Chapter 3 Software Installation Installing the Quartus II Subscription Edition Software ooooooccroooocnnnncroraannarr 3 1 Activating Your License in e li na 3 1 Installing the Arria V GX Starter Kit ooooococcccororooccnnnrrrr rr 3 2 Installing the USB Blaster II Driver aose 0 6 6 I eens 3 3 Chapter 4 Starter Board Setup Setting Up the Board Sn ee ee ee ee a 4 1 Factory Default Switch Settings ooooocooorcccccnnrrrr rr 4 2 Chapter 5 Board Update Portal Connecting to the Board Update Portal Web Page sssssss e 5 1 Using the Board Update Portal to Update User Designs 22222cnnneeeneneennnnnn 5 2 Chapter 6 Board Test System Preparine the Boardi re ee o 6 2 Running the Board Test System 0 66 nee ene es 6 2 Using the Board Test System 1 1 oc nee nen ees 6 3 The Configure Men sese EE ye E lea ah Be a CX e pad eg 6 3 The System Mio Tab eo een ue cun DUE NS 6 3 Board Information 4 42 4042 e he bx Ee EREX E a eee SEEN pd 6 4 MAX V Registers 2 4 cick e ea CE E EROR GU ERG ee 6 4 JTAG Chain essct NRI E ERE ER REPE E EHE Vg teste Vite vage aee bg 6 5 Osys Memory Map tric ee aie acct ey erede LEM IPM tA ted eU 6 5 The GPIO Tab 4 4
30. eate the reference designs in this kit To install the Altera development tools perform the following steps 1 Download the Quartus II Subscription Edition Software from the Quartus II Subscription Edition Software page of the Altera website Alternatively you can request a DVD from the Altera IP and Software DVD Request Form page of the Altera website 2 Follow the on screen instructions to complete the installation process Eh If you have difficulty installing the Quartus II software refer to the Altera Software Installation and Licensing Manual Activating Your License Purchasing this kit entitles you to a one year license for the Development Kit Edition DKE of the Quartus II software a After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web Edition or purchase a subscription to Quartus II software Before using the Quartus II software you must activate your license identify specific users and computers and obtain and install a license file If you already have a licensed version of the subscription edition you can use that license file with this kit If not follow these steps 1 Log on at the myAltera Account Sign In web page and click Sign In 2 On the myAltera Home web page click the Self Service Licensing Center link 3 Locate the serial nu
31. equence of the items is important a b c and so on such as the steps listed in a procedure Beg Bullets indicate a list of items when the sequence of the items is not important i The hand points to information that requires special attention The question mark directs you to a software help system with related information us The feet direct you to another document or website with related information The multimedia icon directs you to a related multimedia presentation CAUTION A caution calls attention to a condition or possible situation that can damage or destroy the product or your work WARNING A warning calls attention to a condition or possible situation that can cause you injury The envelope links to the Email Subscription Management Center page of the Altera website where you can sign up to receive update notifications for Altera documents The feedback icon allows you to submit feedback to Altera about the document Methods for collecting feedback vary as appropriate for each document A Electromagnetic interference caused by modification of the kit contents is the sole responsibility of the user CAUTION This equipment is designated for use only in an industrial research environment Arria V GX Starter Kit User Guide CE November 2014 Altera Corporation
32. er configuration for running the Board Test System demonstration There are several other factory software files written to the CFI flash device to support the Board Update Portal These software files were created using the Nios II EDS just as the hardware design was created using the Quartus II software For more information about Altera development tools refer to the Design Software page of the Altera website CFI Flash Memory Map Table A 1 shows the default memory contents of the 1 Gb CFI flash device U12 Each flash device has a 16 bit data bus and the two combined flash devices allow for a 32 bit flash memory interface For the Board Update Portal to run correctly and CAUTION update designs in the user memory this memory map must not be altered Table A 1 Byte Address Flash Memory Map of U12 Block Description Size KB Address Range Board Test System scratch 128 0x07FE 0000 OxO7FF FFFF User software 46 464 0x0528 0000 0x07FD FFFF Factory software 8 192 0x04A8 0000 0x0527 FFFF zipfs html web content 8 192 0x0428 0000 0x04A7 FFFF User hardware 2 22 656 0x02C6 0000 0x0427 FFFF User hardware 1 22 656 0x0164 0000 0x02C5 FFFF Factory hardware 22 656 0x0002 0000 0x0163 FFFF PFL option bits 32 0x0001 8000 0x0001 FFFF Board information 32 0x0001 0000 0x0001 7FFF Ethernet option bits 32 0x0000 8000 0x0000 FFFF User design reset vector 32 0x0000 0000 0x0000 7FFF Alt
33. era recommends that you do not overwrite the factory hardware and factory software images unless you are an expert with the Altera tools If you unintentionally overwrite the factory hardware or factory software image refer to Restoring the Flash Device to the Factory Settings on page A4 November 2014 Altera Corporation Arria V GX Starter Kit User Guide Appendix A Programming the Flash Memory Device Preparing Design Files for Flash Programming Preparing Design Files for Flash Programming You can obtain designs containing prepared flash files from the Arria V GX Starter Kit page of the Altera website or create flash files from your own custom design The Nios II EDS sof2flash command line utility converts your Quartus II compiled sof into the flash format necessary for the flash device Similarly the Nios II EDS elf2flash command line utility converts your compiled and linked Executable and Linking Format File elf software design to flash After your design files are in the flash format use the Board Update Portal or the Nios II EDS nios2 flash programmer utility to write the flash files to the user hardware 1 and user software locations of the flash memory For more information about Nios II EDS software tools and practices refer to the Embedded Software Development page of the Altera website Creating Flash Files Using the Nios II EDS If you have an FPGA design developed using the Quartus IT software and softwar
34. ete when the progress bar reaches 100 The Config Done LED D12 illuminates indicating that the flash device is ready for programming On the Windows Start menu click All Programs gt Altera gt Nios II EDS gt Nios II Command Shell In the Nios II command shell navigate to the lt install dir gt kits arriaVGX_5agxfb3hf35_start factory_recovery directory and type the following command to run the restore script restore sh Restoring the flash memory might take several minutes Follow any instructions that appear in the Nios II command shell After all flash programming completes cycle the POWER switch SW5 off then on Using the Quartus II Programmer click Add File and select lt install dir gt kits arriaV GX_5agxfb3hf35_start factory_recovery a5gx_starter_fpga_bu p_top sof Turn on the Program Configure option for the added file Click Start to download the selected configuration file to the FPGA Configuration is complete when the progress bar reaches 100 The Config Done LED D12 illuminates indicating that the flash device is ready for programming Cycle the POWER switch SW5 off then on to load and run the restored factory design The restore script cannot restore the board s MAC address automatically In the Nios II command shell type the following Nios II EDS command November 2014 Altera Corporation Appendix A Programming the Flash Memory Device A 5 Restoring the MAX V CPLD to the Factory Settings
35. evices in the JTAG chain Click Add File and select the path to the desired sof Turn on the Program Configure option for the added file m1 pP SN Click Start to download the selected file to the FPGA Configuration is complete when the progress bar reaches 100 La Using the Quartus II programmer to configure a device on the board causes other JTAG based applications such as the Board Test System and the Power Monitor to lose their connection to the board Restart those applications after configuration is complete La If the Quartus II programming window is already open and then you power cycle the board you may be required to click Hardware Setup in the Quartus II Programmer window and reselect USB Blaster II in order to properly detect the JTAG chain Arria V GX Starter Kit November 2014 Altera Corporation User Guide NOTE RA A Programming the Flash Memory Device As you develop your own project using the Altera tools you can program the flash memory device so that your own design loads from flash memory into the FPGA on power up This appendix describes the preprogrammed contents of the common flash interface CFI flash memory device on the Arria V GX starter board and how to reprogram the user portions of the flash memory device The Arria V GX starter board ships with the CFI flash device preprogrammed with a default factory FPGA configuration for running the Board Update Portal design example and a default us
36. gn examples in the kit If you suspect your board might not be currently configured with the default settings follow the instructions in Factory Default Switch Settings on page 4 2 to return the board to its factory settings before proceeding 2 The starter board ships with design examples stored in the flash memory device Verify the DIP switch SW4 3 is set to the off 1 position to load the design stored in the factory portion of flash memory Figure 4 1 shows the DIP switch locations on the starter board 3 Connect the 19 V 6 32 A power adapter to the DC Power Jack J17 on the FPGA board and plug the cord into a power outlet A Use only the supplied power supply Power regulation circuitry on the 77 board can be damaged by power supplies with greater voltage 4 Set the POWER switch SW5 to the on position When power is supplied to the board the blue LED D30 illuminates indicating that the board has power The MAX V device on the board contains among other things a parallel flash loader PFL megafunction When the board powers up the PFL reads a design from flash memory and configures the FPGA FAC LOAD SW4 3 controls which design to load When the switch is in the factory off 1 position the PFL loads the design from the factory portion of flash memory The kit includes a MAX V design which contains the MAX V PFL megafunction The design resides in the install dir NkitsNarriaVGX 5agxfb3hf35 startNexamples max d
37. ication requires additional cooling St For more information about power consumption and thermal modeling refer to AN 358 Thermal Management for FPGAs References Use the following links to check the Altera website for other related information m For the latest board design files and reference designs refer to the Arria V GX Starter Kit page November 2014 Altera Corporation Arria V GX Starter Kit User Guide 2 2 Arria V GX Starter Kit User Guide Chapter 2 Getting Started References For additional daughter cards available for purchase refer to the Development Board Daughtercards page For the Arria V GX device documentation refer to the Documentation Arria V Devices page To purchase devices from the eStore refer to the Devices page For Arria V GX OrCAD symbols refer to the Capture CIS Symbols page For Nios II 32 bit embedded processor solutions refer to the Embedded Processing page November 2014 Altera Corporation N DTE BYAN 3 Software Installation This chapter explains how to install the following software m Quartus II Subscription Edition Software m Arria V GX Starter Kit m USB Blaster II driver Installing the Quartus Il Subscription Edition Software Included in the Quartus II Subscription Edition Software are the Quartus II software the Nios II EDS and the MegaCore IP Library The Quartus II software including Qsys and the Nios II EDS are the primary FPGA development tools used to cr
38. includes an application called the Board Test System BTS and related design examples The BTS provides an easy to use interface to alter functional settings and observe the results You can use the BTS to test board components modify functional parameters observe performance and measure power usage While using the BTS you reconfigure the FPGA several times with test designs specific to the functionality you are testing To install the BTS follow the steps in Installing the Arria V GX Starter Kit on page 3 2 The Board Test System GUI communicates over the JTAG bus to a test design running in the Arria V GX device Figure 6 1 shows the initial GUI for a board that is in the factory configuration Figure 6 1 Board Test System Graphical User Interface r A Board Test System Configure Help About System info GPIO Flash SSRAM Board information Board Name Arria V GX Starter Kit Board Board P N 6XX 44099R Serial number SAGXSK00000024 Factory test version 12 0 0 2 MAC 00 07 ed 20 00 18 MAX V ver 2 i MAX V registers sil ss E JTAG chain USB BlasterII on localhost USB 1 3 1 SAGXFB3H 4ES 6ES 1 2 5M 1270ZF324 2210Z JEPM2210 2 Qsys Memory Map Block Address Detected the GPIO SRAM Flash Project 0x0800 0000 OBFF FFFF max5 inf 0x0060 0000 0060 01FF men anna 0017 FFFF x0000 4000 0000 43FF
39. irectory When configuration is complete the Config Done LED D12 illuminates signaling that the Arria V GX device configured successfully For more information about the PFL megafunction refer to the Parallel Flash Loader Megafunction User Guide November 2014 Altera Corporation Arria V GX Starter Kit User Guide 4 2 Chapter 4 Starter Board Setup Factory Default Switch Settings Factory Default Switch Settings This section shows the factory switch settings for the Arria V GX starter board Figure 4 1 shows the switch locations and the default position of each switch Figure 4 1 Switch Locations and Default Settings Detail SW3 Com Cm ECCE User DIP Switch Do US ld J18 T 5389 JOE P md Lu awa anne mum Fan Header NO Arria V GX a E 22 ol el 25 So FE swi y 32 SW2 mo JO J Ca pa ES t t Fa 5 E Arria V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 4 Starter Board Setup Factory Default Switch Settings 4 3 To restore the switches to their factory default settings perform the following steps 1 Set DIP switch bank SW1 to match Table 4 1 and Figure 4 1 Table 4 1 SW1 Dip Switch Settings Board Default Switch Lahel Function Position Switch 1 has the following options 1 PCIE PRSNT X1 m When ON x1 presence detect is enabled ON m When OFF x1 presence detect i
40. irectory Newer revisions of this code might be available on the Arria V GX Starter Kit page of the Altera website MAX V Registers The MAX V registers control allows you to view and change the current MAX V register values as described in Table 6 1 Changes to the register values with the GUI take effect immediately For example writing a 0 to SRST resets the board Table 6 1 MAX V Registers Read Write zs Register Name Capability Description Syam hase Write only Set to 0 to initiate an FPGA reconfiguration SRST Determines which of the up to three 0 2 pages of flash Page Select Register Read Write memory to use for FPGA reconfiguration The flash memory PSR Mu l ships with pages 0 and 1 preconfigured When set to 0 the value in PSR determines the page of Page Select Override Read Write flash memory to use for FPGA reconfiguration When set to PSO 1 the value in PSS determines the page of flash memory to use for FPGA reconfiguration Holds the current value of the illuminated PGM LED D24 D26 based on the following encoding m 0 PGM LED D24 and corresponds to the flash Page Select Switch memory page for the factory hardware design Read only PSS m 1 PGM LED D25 and corresponds to the flash memory page for the user hardware 1 design m 2 PGM LED D26 and corresponds to the flash memory page for the user hardware 2 design m SRST Resets the system and reloads the FPGA with a design fr
41. mber printed on the side of the development kit box below the bottom bar code The number consists of alphanumeric characters and does not contain hyphens for example 5xxxSoCxxxxxxx November 2014 Altera Corporation Arria V GX Starter Kit User Guide 3 2 Chapter 3 Software Installation Installing the Arria V GX Starter Kit On the Self Service Licensing Center web page click the Find it with your License Activation Code link In the Find Activate Products dialog box enter your development kit serial number and click Search When your product appears turn on the check box next to the product name Click Activate Selected Products and click Close When licensing is complete Altera emails a license dat file to you Store the file on your computer and use the License Setup page of the Options dialog box in the Quartus II software to enable the software To license the Quartus II software you need your computer s network interface card NIC ID anumber that uniquely identifies your computer On the computer you use to run the Quartus II software type ipconfig all at a command prompt to determine the NIC ID Your NIC ID is the 12 digit hexadecimal number on the Physical Address line Le For complete licensing details refer to the Altera Software Installation and Licensing Manual Installing the Arria V GX Starter Kit Arria V GX Starter Kit User Guide To install the Arria V GX Starter Kit perform
42. n external USB Blaster cable to the JTAG header J9 the On Board USB Blaster II is disabled DIP switch SW2 selects which interfaces are in the chain Refer to Table 4 2 on page 4 3 for detailed settings For details on the JTAG chain refer to the Arria V GX Starter Board Reference Manual For USB Blaster II configuration details refer to the On Board USB Blaster II page Qsys Memory Map The Osys memory map control shows the memory map of the Qsys system on your board November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 6 Chapter 6 Board Test System Using the Board Test System The GPIO Tab The GPIO tab allows you to interact with all the general purpose user I O components on your board You can write to the character LCD read DIP switch settings turn LEDs on or off and detect push button presses Figure 6 3 shows the GPIO tab Figure 6 3 The GPIO Tab n po A Board Test System Configure Help About Detected the GPIO SRAM Flash Project The following sections describe the controls on the GPIO tab Character LCD The Character LCD controls allow you to display text strings on the character LCD on your board Type text in the text boxes and then click Display La Ifyou exceed the 16 character display limit on either line a warning message appears User DIP Switches The read only User DIP switches control displays the cu
43. nsceiver signals to loopback on the board 1 Serial loopback internal loopback 2 Reverse serial loopback pre CDR 4 Reverse serial loopback post CDR m VOD Specifies the voltage output differential of the transmitter buffer m Pre emphasis tap m First post Specifies the amount of pre emphasis on the first post tap of the transmitter buffer m Equalizer Specifies the setting for the receiver equalizer m DC gain Specifies the DC portion of the receiver equalizer Data Pattern The Data Pattern control specifies the type of data contained in the transactions The following data types are available for analysis m PRBS 7 Selects pseudo random 7 bit sequences m PRBS 15 Selects pseudo random 15 bit sequences m PRBS 23 Selects pseudo random 23 bit sequences m PRBS 31 Selects pseudo random 31 bit sequences Error Control The Error Control control displays data errors detected during analysis and allows you to insert errors m Detected errors Displays the number of data errors detected in the hardware m Inserted errors Displays the number of errors inserted into the transmit data stream November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 14 Chapter 6 Board Test System Using the Board Test System m Insert Error Inserts a one word error into the transmit data stream each time you click the button Insert Error is only enabled during transaction performance analysis m Clear
44. oard 2 Ensure that the development board switches and jumpers are set to the default positions as shown in the Factory Default Switch Settings section starting on page 4 2 except for DIP switch SW4 3 which should be set the FAC_LOAD SW4 3 to the user on 0 position e For more information about the board s DIP switch and jumper settings refer to the Arria V GX Starter Board Reference Manual 3 Turn on the power to the board The board loads the design stored in the user hardware 1 portion of flash memory into the FPGA If your board is still in the factory configuration or if you have downloaded a newer version of the Board Test System to flash memory through the Board Update Portal the design loads the GPIO and flash memory tests To ensure operating stability keep the USB cable connected and the board powered on when running the demonstration application The application cannot run correctly unless the USB cable is attached and the board is on CAUTION Running the Board Test System Arria V GX Starter Kit User Guide To run the application navigate to the lt install dir gt kits arriaVGX_5agxfb3hf35_start examples board_test_system directory and run the BoardTestSystem exe application On Windows click Start gt All Programs gt Altera gt Arria V GX Starter Kit lt version gt gt Board Test System to run the application A GUI appears displaying the application tab that corresponds to the design r
45. of SyncFlash SRAM and DDR3 Develop and test SDI with the embedded 75 ohm 3G SDI transceivers Develop embedded designs utilizing the Nios II processor and external memory Develop and test network designs utilizing Triple Speed Ethernet MegaCore and external RJ 45 jack Take advantage of the modular and scalable design by using the high speed mezzanine card HSMC connectors to interface to over 40 different HSMCs provided by Altera partners supporting protocols such as Serial RapidIO 10 Gigabit Ethernet SONET Common Public Radio Interface CPRI Open Base Station Architecture Initiative OBSAI and others Measure the FPGA s power consumption Control two programmable clock oscillators Develop and test HDMI TX application with embedded TMDS level shifter capable of supporting data rate up to 2 7 Gbps This section briefly describes the Arria V GX Starter Kit contents The Arria V GX Starter Kit includes the following hardware Arria V GX starter board A development platform that allows you to develop and prototype hardware designs running on the Arria V GX 5AGXFB3H4F35C4N FPGA St For detailed information about the board components and interfaces refer to the Arria V GX Starter Board Reference Manual Loopback and debug header daughter cards November 2014 Altera Corporation Arria V GX Starter Kit User Guide Software Arria V GX Starter Kit User Guide Chapter 1 About This Kit Kit Features m Po
46. oint for a new prototype board design demos Contains demonstration applications documents Contains the kit documentation examples Contains the sample design files for the Arria V GX Starter Kit Contains the original data programmed onto the board before shipment Use this data to restore factory_recovery the board with its original factory contents Installing the USB Blaster Il Driver The Arria V GX starter board includes integrated On Board USB Blaster II circuitry for FPGA programming However for the host computer and board to communicate you must install the USB Blaster II driver on the host computer T Installation instructions for the USB Blaster II driver for your operating system are available on the Altera website On the Altera Programming Cable Driver Information page of the Altera website locate the table entry for your configuration and click the link to access the instructions November 2014 Altera Corporation Arria V GX Starter Kit User Guide 3 4 Chapter 3 Software Installation Installing the USB Blaster II Driver Arria V GX Starter Kit November 2014 Altera Corporation User Guide AHERN 4 Starter Board Setup The instructions in this chapter explain how to set up the Arria V GX starter board Setting Up the Board To prepare and apply power to the board perform the following steps 1 The Arria V GX starter board ships with its board switches preconfigured to support the desi
47. om flash memory based on the other MAX V register values Refer to Table 6 1 for more information November 2014 Altera Corporation Chapter 6 Board Test System 6 5 Using the Board Test System Ls m PSO Sets the MAX V PSO register The following options are available m Use PSR Allows the PSR to determine the page of flash memory to use for FPGA reconfiguration m Use PSS Allows the PSS to determine the page of flash memory to use for FPGA reconfiguration m PSR Sets the MAX V PSR register The numerical values in the list corresponds to the page of flash memory to load during FPGA reconfiguration Refer to Table 6 1 for more information m PSS Displays the MAX V PSS register value Refer to Table 6 1 for the list of available options Because the System Info tab requires that a specific design is running in the FPGA at a specific clock speed writing a 0 to SRST or changing the PSO value can cause the Board Test System to stop running JTAG Chain The JTAG chain control shows all the devices currently in the JTAG chain The Arria V GX device is always the first device in the chain The JTAG chain is normally mastered by the On board USB Blaster II If the JTAG chain cannot be detected using the On Board USB Blaster II refer to the initialization instructions on the USB Blaster Driver for Windows 7 and Windows Vista web page or the USB Blaster and USB Blaster II Drivers for Windows XP web page If you plug in a
48. one application ClockControl exe resides in the install dir NkitsNarriaVGX 5agxfb3hf35 startNexamplesNboard test system directory On Windows click Start gt All Programs gt Altera gt Arria V GX Starter Kit version gt Clock Control to start the application For more information about the i5338 Si571 and the Arria V GX starter board s CE clocking circuitry and clock input pins refer to the Arria V GX Starter Board Reference Manual November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 20 Arria V GX Starter Kit User Guide Chapter 6 Board Test System The Clock Control The Clock Control communicates with the MAX V device on the board through the JTAG bus The Si571 programmable oscillator is connected to the MAX V device through a 2 wire serial bus Clock frequencies will return to the default values after power cycling the board Figure 6 10 and Figure 6 11 shows both tabs of the Clock Control Figure 6 10 The Clock Control U4 Tab r o A Clock Control JA DTE RYN U4 x1 F_vco 2457 6000 Registers Frequency MHz Disable al CLkO 125 0000 CLKO 100 00 Disable CLKO CLK1 409 6000 CLK1 100 00 Disable CLK1 CLk2 156 2500 CLK2 100 00 Disable CLK2 CLK3 100 0000 CLK3 100 00 Disable CLK3 Default Set New Frequency USB BlasterII on localhost USB 2 5M 1270ZF324 122102 EPM2210 2 T
49. ria V GX Starter Kit User Guide Chapter 4 Starter Board Setup Factory Default Switch Settings Table 4 3 SW3 Dip Switch Settings Part 2 of 2 Switen Boa Function Position Switch 3 has the following options 3 USER2 m When ON a logic 0 is selected OFF m When OFF a logic 1 is selected Switch 4 has the following options 4 USER3 m When ON a logic 0 is selected OFF m When OFF a logic 1 is selected 4 Set DIP switch bank SW4 to match Table 4 4 and Figure 4 1 Table 4 4 SW4 Dip Switch Settings Switen Board Funetion Position Switch 1 has the following options 1 CLK SEL m When ON a logic 0 is selected SMA input clock select OFF m When OFF a logic 1 is selected Programmable oscillator clock select Switch 2 has the following options m When ON a logic 0 is selected on board oscillator 2 CLK EN disable OFF m When OFF a logic 1 is selected on board oscillator enable Switch 3 has the following options m When OFF alogic 1 is selected load the factory design of 3 FAC LOAD Arria V device from flash at power up OFF m When ON alogic 0 is selected load the user design from flash at power up 4 RESERVED Switch 4 has no function OFF e For more information about the FPGA board settings refer to the Arria V GX Starter Board Reference Manual November 2014 Altera Corporation N DTE RYN l 5 Board Update Portal The Arria V GX Starter Kit ships with the Board Up
50. rnet port connected to the same network for the board m The Ethernet and power cables that are included in the kit To connect to the Board Update Portal web page perform these steps 1 With the board powered down set the FAC_LOAD SW4 3 to the factory off 1 position 2 Attach the Ethernet cable from the board to your LAN 3 Power up the board The board connects to the LAN s gateway router and obtains an IP address The LCD on the board displays the IP address 4 Launch a web browser on a PC that is connected to the same network and enter the IP address from the LCD into the browser address bar The Board Update Portal web page appears in the browser Ka You can click Arria V GX Starter Kit on the Board Update Portal web page to access the kit s home page for documentation updates and additional new designs November 2014 Altera Corporation Arria V GX Starter Kit User Guide 5 2 Chapter 5 Board Update Portal Using the Board Update Portal to Update User Designs e You can also navigate directly to the Arria V GX Starter Kit page of the Altera website to determine if you have the latest kit software Using the Board Update Portal to Update User Designs Arria V GX Starter Kit User Guide The Board Update Portal allows you to write new designs to the user hardware 1 portion of flash memory Designs must be in the Nios II Flash Programmer File flash format Design files available from the Arria V GX Sta
51. rrent positions of the switches in the user DIP switch bank SW3 Change the switches on the board to see the graphical display change accordingly Arria V GX Starter Kit November 2014 Altera Corporation User Guide Chapter 6 Board Test System Using the Board Test System User LEDs The User LEDs control displays the current state of the user LEDs Click the number buttons for the LEDs to turn the board LEDs on and off You can click ALL to turn on and off all of the user LEDs at once Push Button Switches The read only Push button switches control displays the current state of the board user push buttons Press a push button on the board to see the graphical display change accordingly The Flash Tab The Flash tab allows you to read and write flash memory on your board Figure 6 4 shows the Flash tab Figure 6 4 The Flash Tab Configure Help About re NU Te System info GPIO Flash ssram Detected the GPIO SRAM Flash Project Flash Start address O7FE 0000 Range 0x0000 0000 Ox07FF FFFF Resp CFI Query 07FE 0000 AB2D88B4 AFSEESTE 37090DBF F323011C 07FE 0010 SACB472E B809EB85A 851BC381 36C88CFS O7FE 0020 ez111c30 04052DCB F123E1CE 8DF DF8B 07FE 0030 SBEFFSC9S 4B0134CA 40721270 26211FA7 07FE 0040 656B496B 417D6218 2811FA0D A9BE1DD4 07FE 0050 BDD4E2
52. rter Kit page include flash files You can also create flash files from your own custom design Refer to Preparing Design Files for Flash Programming on page A 2 for information about preparing your own design for upload To upload a design over the network into the user portion of flash memory on your board perform the following steps 1 Perform the steps in Connecting to the Board Update Portal Web Page to access the Board Update Portal web page 2 In the Hardware File Name field specify the flash file that you either downloaded from the Altera website or created on your own If there is a software component to the design specify it in the same manner using the Software File Name field otherwise leave the Software File Name field blank 3 Click Upload The progress bar indicates the percent complete 4 Toconfigure the FPGA with the new design after the flash memory upload process is complete set the FAC_LOAD SW4 3 to the user on 0 position and power cycle the board As long as you don t overwrite the factory image in the flash memory device you can continue to use the Board Update Portal to write new designs to the user hardware 1 portion of flash memory If you do overwrite the factory image you can restore it by following the instructions in Restoring the Flash Device to the Factory Settings on page A 4 November 2014 Altera Corporation NOTE RIAN 6 Board Test System The development kit
53. s and GUI labels For example qdesigns directory D drive and chiptrip gdf file Italic Type with Initial Capital Letters Indicate document titles For example Stratix IV Design Guidelines November 2014 Altera Corporation Arria V GX Starter Kit User Guide Info 2 Additional Information Typographic Conventions Visual Cue Meaning Indicates variables For example n 1 italic type Variable names are enclosed in angle brackets gt For example file name and lt project name gt pot file Initial Capital Letters Indicate keyboard keys and menu names For example the Delete key and the Options menu Subheading Title Quotation marks indicate references to sections in a document and titles of Quartus Help topics For example Typographic Conventions Courier type Indicates signal port register bit block and primitive names For example data1 tdi and input The suffix n denotes an active low signal For example resetn Indicates command line commands and anything that must be typed exactly as it appears For example c qdesigns tutorial chiptrip gdf Also indicates sections of an actual file such as a Report File references to parts of files for example the AHDL keyword SUBDESIGN and logic function names for example TRI An angled arrow instructs you to press the Enter key pr 1 2 3 and Numbered steps indicate a list of items when the s
54. s disabled Switch 2 has the following options 2 PCIE PRSNT X4 m When ON x4 presence detect is enabled ON m When OFF x4 presence detect is disabled Switch 3 has the following options 3 PCIE PRSNT X8 m When ON x8 presence detect is enabled ON m When OFF x8 presence detect is disabled Switch 4 has the following options m When ON a logic O is selected fan is turned on Fan 1 PANTOREEON is not included in this kit or m When OFF logic 1 is selected fan is turned off 2 Set DIP switch bank SW2 to match Table 4 2 and Figure 4 1 Table 4 2 SW2 Dip Switch Settings Board Default Switch Label Function Position Set to OFF to include the MAX V System Controller in 5M2210_JTAG_EN the JTAG chain Default is OFF in chain OFF Set to OFF to include HSMC Port A in the JTAG chain o HSMA_JTAG_EN Default is ON not in chain ON Set to OFF to include the PCI Express Edge Connector in s PCIE_JTAG_EN the JTAG chain Default is ON not in chain on 4 3 Set DIP switch bank SW3 to match Table 4 3 and Figure 4 1 Table 4 3 SW3 Dip Switch Settings Part 1 of 2 E Board Default Switch Label Function Position Switch 1 has the following options 1 USERO m When ON a logic 0 is selected OFF m When OFF a logic 1 is selected Switch 2 has the following options 2 USER1 m When ON a logic 0 is selected OFF m When OFF a logic 1 is selected November 2014 Altera Corporation Arria V GX Starter Kit User Guide Ar
55. the SSRAM contents change values in the table and click Write The application writes the new values to SSRAM and then reads the values back to guarantee that the graphical display accurately reflects the memory contents November 2014 Altera Corporation Arria V GX Starter Kit User Guide 6 10 Chapter 6 Board Test System Using the Board Test System The DDR3 Tab The DDR3 tab allows you to read and write the DDR3 memory on your board Figure 6 6 shows the DDR3 tab Figure 6 6 The DDR3 Tab Fa A Board Test System Lo ea Configure Help About Senta on s oo i Write Total Read Write MBps 1457 04 Read MBps 1821 07 Total MBps 3278 11 a Error control 2 Detected errors 0 Inserted errors 0 Number of addresses to write and read EE Messages Min 268435456 Max Detected DDR3 Project a The following sections describe the controls on the DDR3 tab Start The Start control initiates DDR3 memory transaction performance analysis Always click Clear before Start Stop The Stop control terminates transaction performance analysis Performance Indicators These controls display current transaction performance analysis information collected since you last pressed Start m Write Read and Total performance bars Show the percentage of maximum theoretical data rate that the requested transactions are able to achieve Arri
56. the following steps 1 Download the Arria V GX Starter Kit installer from the Arria V GX Starter Kit page of the Altera website Alternatively you can request a development kit DVD from the Altera Kit Installations DVD Request Form page of the Altera website Runthe Arria V GX Starter Kit installer exe for Windows or unzip the installation image for Linux Follow the on screen instructions to complete the installation process Be sure that the installation directory you choose is in the same relative location to the Quartus II software installation November 2014 Altera Corporation Chapter 3 Software Installation 3 3 Installing the USB Blaster II Driver The installation program creates the Arria V GX Starter Kit directory structure shown in Figure 3 1 Figure 3 1 Arria V GX Starter Kit Installed Directory Structure 7 lt install dir gt The default Windows installation directory is C altera lt version gt kits arriaVGX 5agxfb3hf35 start ey board design files Bi demos Ea documents C examples factory_recovery Note to Figure 3 1 1 Early release versions might have slightly different directory names Table 3 1 lists the file directory names and a description of their contents Table 3 1 Installed Directory Contents Directory Name Description of Contents Contains schematic layout assembly and bill of material board design files Use these files as a hoard design fles starting p
57. unning in the FPGA The Arria V GX starter board s flash memory ships preconfigured with the design that corresponds to the GPIO Flash and SRAM tabs November 2014 Altera Corporation Chapter 6 Board Test System 6 3 Using the Board Test System La If you power up your board with the FAC LOAD SW4 3 in a position other than the user on 0 position or if you load your own design into the FPGA with the Quartus II Programmer you receive a message prompting you to configure your board with a valid Board Test System design Refer to The Configure Menu for information about configuring your board Using the Board Test System This section describes each control in the Board Test System application The Configure Menu Use the Configure menu Figure 6 2 to select the design you want to use Each design example tests different board features Choose a design from this menu and the corresponding tabs become active for testing Figure 6 2 The Configure Menu Help About Configure with SRAM Flash GPIO Design Configure with DDR3 Design Configure with XCVR1 Design v Configure with XCVR2 Design Exit Ctrl Q To configure the FPGA with a test system design perform the following steps 1 On the Configure menu click the configure command that corresponds to the functionality you wish to test 2 In the dialog box that appears click Configure to download the corresponding design s Raw Binary File rbf to the FP
58. wer supply and cables The kit includes the following items Power supply and AC adapters for North America Japan Europe and the United Kingdom m USBcable m 75 Q SMB video cable m Ethernet cable The software for this kit described in the following sections is available on the Altera website for immediate downloading You can also request to have Altera mail the software to you on DVDs Quartus Il Software Your kit includes a license for the Development Kit Edition DKE of the Quartus II software Windows platform only For one year this license entitles you to most of the features of the Subscription Edition excluding the IP Base Suite After the year your DKE license will no longer be valid and you will not be permitted to use this version of the Quartus II software To continue using the Quartus II software you should download the free Quartus II Web edition or purchase a subscription to Quartus II software For more information refer to the Design Software page of the Altera website The Quartus II Development Kit Edition DKE software includes the following items m Quartus IL Software The Quartus II software including the Qsys system integration tool provides a comprehensive environment for network on a chip NoC design The Quartus II software integrates into nearly any design environment and provides interfaces to industry standard EDA tools m MegaCore IP Library A library that contains Altera IP Mega
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