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Actel SmartFusion Microcontroller Subsystem User's Guide

1. 44 4 mE 246 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 75 Table 13 32 75 E rr pasi gem __ Mem E IOMUX 76 Table 13 33 IOMUX 76 Pad IOMUX 76 Ports AJo 5 ___ 3 1 _____ 4 pum eee Revision 1 247 VActel POWER MATTERS 14 Inter Integrated Circuit 120 Peripherals Actel SmartFusion devices contain two identical master slave 12 peripherals that perform serial to parallel conversion on data originating from serial devices and perform parallel to serial conversion on data from the ARM Cortex M3 processor to these devices The Cortex M3 embedded processor controls the 2 peripherals via the APB interface Throughout this chapter a lower case x in register and signal descriptions is used as a place holder for 0 1 indicating I2C 0 on the 0 bus or I2C 1 on the 1 bus The 2 peripherals support 12 SMBus and PMBus data trans
2. 2 7 ___ LO o o3 a DYNBSEL RXBSEL and STATBSEL Table 8 25 gives bit definitions for RXBSEL DYNBSEL and STATBSEL Table 8 25 DYNBSEL RXBSEL and STATBSEL Bit Definitions o3 83 3 NNNM NNNM 136 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide OAMUX Table 8 26 gives bit definitions for OAMUX Table 8 26 OAMUX Bit Definitions OAMUX 6 o posa CNN 9 3 3 _ BONN LI RN ave aa rive ase rico a phases 1 DYNASEL RXASEL and STATASEL Table 8 27 gives bit definitions for DYNASEL RXASEL and STATASEL Table 8 27 DYNASEL RXASEL and STATSEL Bit Definitions RXASEL DYNASEL STATASEL CLKA NE EUN Lo T 0j RUE ERR NN LO Revision 1 137 Actel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators 138 CCC PLL Configuration Register Table 8 28 MSS CR Bit Reset Number R W Value Description 31 PLLEN RAV 0 PLL in power down mode 1 enabled 30 25 Reserved R W Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved acro
3. Sr Revision 1 335 POCA Ct e General Purpose I O Block GPIO IOMUX 54 Table 18 52 IOMUX 54 Gpo o fes wem oe 1 me ___ _ ___ Sese PD IOMUX 54 PD IOMUX 54 ST IOMUX 55 Table 18 53 IOMUX 55 bad IOMUX 55 Ports Ports IOMUX 55 CR p pus NEN _ ce IOMUX_55_PU a ME IOMUX 56 Table 18 54 OMUX 56 Pad IOMUX 56 Ports LJ v EMEN ioUXWbYvz p GPIO 30 OE RT LIP m LE E sr ff 336 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SmartFusion MSS GPIO Application Development This section provides an overview of the design flow for SmartFusion devices to facilitate application development using GPIOs The 32 bits of the GPIO block are shared among MSS peripherals and MSS user I Os as summarized in Table 18 55 Using the MSS GPIO peripheral requires minimal configuration of the GPIO and MSS 1 blocks in MSS configurator and 1 assignment in Libero Integrated Design Environment IDE The user application would then use predefined functions in GPIO drivers to perform the general purpose functions
4. 157 11 Wathdog TIRE a dad CIR n Gd dU dd ON 163 Watchdog Block 2 1 163 Functional Description 5 52 Erato ean 163 Watchdog Timeout Reset Interrupt 4 1 164 Loading and Refreshing the 164 Watchdog Behavior with Processor Modes and Device Programming 165 Watchdog Interrupts ___ 166 Watchdog Register Interface Summary 166 Watchdog Register Interface Details 1 166 12 Ethernet fl MT 173 Introductio T 173 Ethernet MAC Block Diagram 02 173 Functional Blocks of Ethernet MAC 174 Clock and Reset Control sop verme rue tee YEN E Rr en 175 Interface Signals 222 REM RUNDE Ra UR EE 177 Revision 1 13 14 15 16 17 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Frame Data and Descriptors
5. 14 178 MAC Address and Setup Frames 1 1 187 Internal Operation iens 188 Software Interface oues 197 IOMUXes Associated with Ethernet 215 Serial Peripheral Interface SPI 221 SPI Controller Functional Description 0 4 221 SPI Controller Block Diagram 222 SPI Modes of Transfer i224 EC P RAD end 222 SPI Interface Signals bibe bead Sadun Rd RR ERR IR P pd ee RD mak 223 SPI Controller Operation 2 iecur RR RE eee bee ea eae 6 223 SPI Clock Requirements unix EIER SR Ru TRE Ru ERGO REA 224 SPI Status at Reset jaa wedges tra Ed eina eee e CR a t APR Ade ea do 224 SPI Error Recovery and Handling 224 SPI Data Transfer Protocol Details 225 National Semiconductor MICROWIRE Protocol 2 0 228 Texas Instruments TI Synchronous Ser
6. 1 366 Thresholds 2 sus dump eae we bee he vc e ur eodein i e d 367 SBS ICI AJ J M 368 DAC Signals 5 22 00 Meo vex Rus 369 Signals deed ers onte em anise e uaa Gne Ia o er E 369 Miscellaneous Signals 4 5 370 20 martFusion Programming 6 dk cde XA CER IRE Rea 373 In System Programming 4 1 3 5 373 In Application Programming 374 uc 375 21 SmartFusion Master Register 377 A Litotes ossi oss e Ee ROSE EE Eds RR Ep ds 387 B Rad eie d CEA 393 Customer 5 PTT 393 Actel Customer Technical Support 1 393 Actel Technical Support mere n 393 Website ocio bee ihe gorge d
7. 1 1 53 Write Operations s Ru ck RR EE RI Zi 55 Reading Writing to the Aux Block 5 57 eNVM Block Protection 2 7 0 57 eNVM Commands 58 Programming Errors 2 cc eee uu wh va RR 60 VCR CNRC CTI 61 alij cM ELTE 61 c EE 62 eNVM Controller Register Map 2 1 62 5 SmartFusion Embedded FlashROM eFROM 73 Architecture of the Embedded FlashROM eFROM 73 Reading the eFROM Contents via the 55 74 6 Embedded SRAM eSRAM Memory Controllers 79 Misaligned Addresses kd dee rhe duod oid dte depo doen m Rd pee edet a bud 80 7 External Memory Controller s iss obse Gees 81 Pres 81 Naming COnVentiOn 81 Block Diagram e 82 Revision 1 Table of Contents Functional Description 1 21 2 83
8. For two access writes If HADDR 1 0 DATA 1 A A IF HADDR 1 0 0 1 DATA D1 DO e m 5g iD Uri For four access writes RW RWPOL 0 13 D3 D2 D1 DO RW N RWPOL 1 7 14 7 Where EMC BYTE ENx is shown low only EMC BYTE ENx for the active byte lane s will go low EMC BYTE ENx for inactive byte EMC PAD OE 15 lanes will remain high EMC OEx N 16 BYTE WENBEN 0 N i 17 _ _ WENBEN 1 N i 18 WDB XB X By 52 X 53 Y 19 EMC RDB 20 Latency Cycle IDD Cycle Hashed waveforms are for the next AHB EMC WRLATx 2 IDDx 1 access If it is an EMC access HREADYOUT will be deasserted immediately but the 1 2 4 Access 2 amp 4 4 Access All start of the memory access will be delayed I Writes Only until IDD cycles have finished 4 Figure 7 22 Pipelined Synchronous Write Cycle Revision 1 VActel External Memory Controller Non Pipelined Synchronous Write Cycle PIPEWRNXx 1 FCLK Lam m HADDR KA XA a ac du 1 j 1 EMC MEMTYPE 10 2 PIPERDN is ignored for writes
9. me ooo eau s mre 2 o ose ww o vo war 2 wm gt esse mor eas 1 war gt essa mor evan esp o a 6 wor ess sr s v s esser rear s esp s 1 near rar s esser rar s area ror a wor v near ea s esser rear s efre o i n o es e 1 EL ee wer sar ese ee 2 ww s ee 3 T s war o o T Bs war v pono esr mar a v ono gt wei v 2 fo reor gt 42 2 reor 2 ever e 22 2 s ferao 2 ever e wei 2 2 esee 1 Note Misaligned access E Note In the following sections and timing diagrams W EMC_WRLATx X EMC_RDLATFIRSTx EMC RDLATRESTx and 2
10. ISG1LPS2048 15611 52048 18A 18A CLK A 21 0 21 0 o ADV ADV ADSC ADSC 4d ADSP ADSP dcr GW GW d or OEN1 d og DQ 15 0 DQ 15 0 BWE BWA BWA Q BWB BWB CE2 CE2 lt 4 CE3 MODE MODE 77 22 VSS Figure 7 13 x16 Synchronous SRAM 2 EMDs 92 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Figure 7 14 shows a circuit diagram that connects two large byte mode NOR flash devices to the SmartFusion device Here the byte enables are being used as write enables usage depends on device and configuration Use the EMC WENBENXx bits in the EMC CS x CR register to select this mode SmartFusion S29GL512P S29GL512P AB 25 0 EMC CS 1 0 N RW BYTE EN 1 0 EMC PAD OE External Memory Controller Block HREADY EMC EMC BYTE ENO EMC BYTE EN1 WE EMC_OENO_N OE 15 DQ 15 0 A 1 BYTE HRDATA 31 0 HREADYOUT EMC WDB 15 0 DB 15 0 EMC RDB 15 0 v 0 Block WP ACC RY BY RESET HRESETn From System Reset a VSS Figure 7 14 x16 NOR Flash Two EMDs Figure 7 15 shows a circuit diagram that connects four asynchronous SRAMs to the SmartFusion device This is another case of byte enabl
11. X ff Clears Edge ffs until Int Enabled GPOUTEN Output Enable GPINTEN edge both INT Cortex M3 edge neg HO GPIO_INTR amp dde bos ff ffi E level low lt IN A or IN B level high from IOMUX GPINTEN ff ff H ff Interrupt Enable OE Aor OE B GPIOINT TYPE to IOMUX Interrupt Type GPO OUTBUFEN GPI X 0 GPINEN Input Enable Figure 18 2 GPIO Block Diagram 316 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide GPIO Register Map The GPIO block is mapped to address 0x40013000 in the memory map Registers referred to in this document are defined in Table 18 1 Table 18 1 MSS GPIO Register Map Reset Register Name Address R W Value Description GPIO x 0 0x40013000 GPIO Configuration register for bit 0 GPIO x CFG 1 0x40013004 GPIO Configuration register for bit 1 emo ead oniy bits or pors contur asnos MSS GPIO Register Table 18 2 gives bit definitions for the GPIOCFG_x_REG registers Table 18 2 GPIO_x_CFG Bit Reset Number R W Value Description GPIOINT_TYPE 0b000 See Table 18 3 on 318 a f remes mw wo 7 GPINTEN 0 Interrupt disabled 1 Interrupt enabled 0 Input register disabled 1 Input register enabled GPINEN
12. r Rents AP being 20 Generates software control interrupts to the DSS peripherals m 2 EMC Timina for Chips 2 EMC Timina Parameters T 13 lock Ceiiguration or SS Sr Coivlbieforthe vss 2 Eeivl bis or the v5 ___ 2 eee ormens ee 2 conval bs or the MSS CCC Dely _ 5 Controls Band Gap Enable Fabric Vreg qualifier clears PU_N interrupts 7 Fabric Interface Control register _ 0 0042028 SOFT CR 0 004202 SOFT RST 0xE0042030 EFROM CR 0 0042024 VRPSM CR 0 0042064 FAB IF OxE004206C 5 eaea Revision 1 377 Acte SmartFusion Master Register Map Table 21 1 Registers in the SYSREG Space continued FAB APB HIWORD DR 0xE0042070 Configures fabric interface as either APB or AHB LOOPBACK_CR 0xE0042074 R Loopback control for MSS peripherals MSS IO BANK CR 0xE0042078 EM Set standard for MSS Banks GPIN SOURCE CR 0xE004207C Alternate GPIN source select IOMUX _n_CR n 0 0xE0042100 MUX Cell 0 control register IOMUX _n_CR n 82 0xE0042248 MUX Cell 82 control register Table 21 2 provides a listing of all registers referred to in the SmartFusion Microcontroller Subsystem User s Guide including cross references to the sections where each register is defined in detail
13. 393 Contacting the Customer Technical Support Center 393 Revision 1 VActel POWER MATTERS 1 ARM Cortex M3 Microcontroller The ARM Cortex M3 microcontroller is a low power processor that features low gate count low and predictable interrupt latency and low cost debug It is intended for deeply embedded applications that require fast interrupt response features The processor implements the ARMv7 M architecture and is depicted in its entirety in Figure 1 1 SmartFusion devices use the R1P1 version of the Cortex M3 core The following manuals available from the ARM Infocenter are recommended reading e Cortex M3 Technical Reference Manual e ARMV7 M Architecture Reference Manual ARMV7 M Architecture Application Level Reference Manual The Definitive Guide to the ARM Cortex M3 by Joseph Yiu is recommended as additional reading ISBN 978 0 7506 8534 4 INTNMI Interrupts Cortex M3 INTISR 149 0 Sleep SLEEPING a Debug 3 EM SLEEPDEEP Instr Data Trigger 22 SW JTAG Figure 1 1 Trace Port serial wire Private Peripheral Bus external ROM Table Bus D Code Bus SW System Bus SWJ DP AHB AP Cortex M3 R1P1 Block Diagram Private Peripheral Bus internal Manufacturers of Cortex M3 integrated circuits are permitted some latitude in configuring a particular implementation of the Cortex M3 delivere
14. Bits 31 24 RPD 31 24 Bits 23 16 RPD 23 16 Bits 15 8 RPD 15 8 Bits 7 0 RPD 7 0 Table 12 23 CSR2 Bit Name R W Reset Value Function 31 0 W Writing this field with any value instructs Ethernet MAC to check for receive descriptors to be acquired This operation is valid only when the receive process is suspended If no descriptor is available the receive process remains suspended When the descriptor is available the receive process goes into the running state 200 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Receive Descriptor List Base Address Register CSR3 Table 12 24 Receive Descriptor List Base Address Register CSR3 Bits 31 24 RLA 31 24 Bits 23 16 RLA 23 16 Bits 15 8 RLA 15 8 Table 12 25 CSR3 Bit Name R W Reset Value Function 31 0 RLA RAW OxFFFFFFFF Start of the receive list address Contains the address of the first descriptor in a receive descriptor list This address must be 32 bit word aligned RLA 1 0 0 Transmit Descriptor List Base Address Register CSR4 Table 12 26 Transmit Descriptor List Base Address Register CSR4 Bits 31 24 TLA 31 24 Bits 23 16 TLA 23 16 Bits 15 8 TLA 15 8 Bits 7 0 TLA 7 0 Table 12 27 CSR4 CA 31 0 TLA RAW OxFFFFFFFF Start of the transmit list address Contains the address of the first descriptor in a transmi
15. O resto ron qp 1 4 Lor 1 Revision 1 329 ___________________ General Purpose I O Block GPIO IOMUX 36 Table 18 34 IOMUX 36 IOMUX 36 Ports ee IOMUX 36 CR INA OUT A OUT A ws esp p ope La eon F2M 20 5 22 12 ee wu vwucGem _ ____ ______ np Jp s mewxss IOMUX 37 Table 18 35 IOMUX 37 IOMUX 37 Ports AS we 7 Em owner IOMUX 38 Table 18 36 IOMUX 38 Pad IOMUX 38 Ports Ports IOMUX 38 CR OUT A D esp 9 _____ POE KAE C NENNEN ae eae 330 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 39 Table 18 37 IOMUX 39 Ol oe p eew MEN IOMUX 39 PD Es oewxss IOMUX 40 Table 18 38 IOMUX 40 IOMUX 40 Ports eer o _ _ ea o duode 1 2 1 NENNEN IOMUX 41
16. IOMUX 8 Table 18 15 IOMUX 8 1 I pem op pem Ew ff owes Revision 1 323 Acte General Purpose I O Block GPIO IOMUX 9 Table 18 16 IOMUX 9 esp 1 L Le 1995 LL fe l eaexsm 1 IOMUX 10 Table 18 17 IOMUX 10 Pad IOMUX 10 Ports E qp 1 jx x ewxum IOMUX 11 Table 18 18 IOMUX 11 Ep qe 1 xL I e 1L wore 1L Ps 324 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 12 Table 18 19 IOMUX 12 IOMUX 12 Ports Pad Name IOMUX 12 CR OUT A OEA NB OUT B a 9 pw _ ___ UART 1 TXD o GND y ow ES ppc pudo em por ee ee ee IOMUX 13 Table 18 20 IOMUX 13 OAJ oA we Eas Lc 1 4 UART RXDI 2 42 4 121 2 IOMUX 14 Table 18 21 IOMUX 14 Ep qme L I9 S 21
17. N 3 PIPEWRNXx is high HWRITE x is high HWDATA 7 4 Shaded latency cycles WRLATx 1 cycles wide WRLATXx value of 1 will remove these latency cycles HRDATA 1 E HREADYOUT 5 WRLATx value of 0 causes address and data to be presented in the same FCLK cycle EMC CLK j j 6 For single beat writes EMC AB X AO 2 X If HADDR 1 0 00 If HADDR 1 0 01 EMC cox M l If HADDR 1 0 10 DATA DO 5 N csFE 1 N If HADDR 1 0 11 DATA DO EMC RW N RWPOL 0 N For two beat writes RW N RWPOL 1 i If HADDR 1 0 DATA D1 DO i If HADDR 1 0 01 D1 DO EMC OEx N For four beat writes EMC_BYTE_ENX WENBEN 0 D3 D2 D1 DO EMC WDB i X X X DiX X D2X X 7 Where BYTE ENx is shown low only EMC_BYE_ENx for the EMC RDB i H i active byte lane s will go low EMC BYTE ENx for inactive byte lanes will remain high Latency Cycle Latency Cycle Latency Cycle Latency Cycle IDD Cycle EMC WRLATx 2 WRLATx 2 WRLATx22 RWLATx 2 EMC IDDx 1 1 2
18. usd dereud em ded deh dade ed dpi im Save 15 Functional Description RR TC n le ee 15 deen 17 System Memory Map xii xh eR heh RR RR TRA 19 The Boot Process soni Aser LEER RAMS x 23 AHB Bus Matrix Register Map 1 4 2 24 2 Peripheral DMA 35 PDMA Eeatut s Ogre t eoe tbe Dog be E 35 Functional Description RU RE 35 Ping Pong Mode 36 Posted APB WIites Re Ea Rh eue E Swe Re ee aaa ceed xe ate 37 Memory to Memory Transfers 37 Channel Priority 1 1 4 1 37 System Dependencies 4 38 Register Map 1 2 39 4 Embedded Nonvolatile Memory eNVM Controller 47 Memory Organization ae 49 Read Next Operation
19. peser EET pu qwe eRe p qn ip p eee IOMUX 48 Table 14 20 IOMUX 48 ee p qe 1 ewm IOMUX 14 Table 14 21 IOMUX 14 IOMUX 14 Ports __ EA eroan pro ____ p oc c s Revision 1 271 o Acte Inter Integrated Circuit Peripherals IOMUX 15 Table 14 22 IOMUX 15 IOMUX 15 Ports pea exp SENSE ZONE NE NES j ees ees ewm D LLL D IOMUX 55 Table 14 23 55 LOI mm 1 9 l e me Em ewxsm L1 ewes IOMUX 56 Table 14 24 IOMUX 56 __ qw eem mw cosy OF 7 rest BASE vu LIE 1 2 272 Revision 1 VActel POWER MATTERS 15 Universal Asynchronous Receiver Transmitter UART Peripherals Actel s SmartFusion devices contain two identical universal asynchronous receiver transmitter peripherals that provide software compatibility with the popular 16550 device They perform serial to parallel conversion on data originating from modems or other serial devices and perform paralle
20. PRESTART1 Outputs during states PRESTART1 through PRESTART7 T as they were for PRESTARIZ PRESTARTO N RE NEXT MSS RESET O 1 WAIT MSS RESET N O 1 MSS SYSTEM RESET lt 0 M2 RESET lt M2 F RESET N FCLK RCOSC RESET N FCLK lt RCOSC RESET N FCLK Requires MSS RESET N I N to be asserted for 8 consecutive clock periods Figure 9 3 Reset Controller State Machine A requirement on the off chip source is that it must assert MSS RESET N for at least eight FCLK clock periods and during the correct time window to guarantee correct operation It must not assert MSS RESET N until it sees MSS RESET N negated Assertion outside of the correct window could be masked not impacting the logic When MSS RESET N is asserted by the off chip source during the correct window the MSS RESET N signal remains asserted even after the off chip source stops driving it low This is because the MSS has taken over the pad via the EXT SR bit in SOFT RST CR Revision 1 147 _________________ Reset Controller Reset Controller Register Map Table 9 3 gives the register map for the reset controller and other registers mentioned in this document E 9 2 Reset Controller Memory Map _ E CTRL 0x4002000C RAV ELLCAM analog block can be turned on by setting the ABPOWERON bit in the ANA COMM CTRL register to a 1 MSS SR 0xE004201C Signals BROWNOUT3_3VINT B
21. ___ C ARE EXON iis OLEAN Ee EEG _ _ xc one _____ _ LIAO st i ee Table 21 2 SmartFusion Master Register Map Cortex M3 SysTick Timer SYSTICK CR OxE000E010 RAW 0x0 Basic control of SysTick including enable clock source interrupt or poll SysTick Reload Value 0xE000E014 RAW Unpredictable Value to load in Current Value register when 0 is reached SysTick Current Value 0xE000E018 RAW Unpredictable The current value of the count down SysTick Calibration Value STCALIB Contains the number of ticks to generate 10 ms interval SysTick Control and Status OxE000E010 RAV 0x0 Basic control of SysTick including enable clock source interrupt or poll Interrupts The interrupt numbers corresponding to the NVIC input pins of the Cortex M3 their sources and which functions assert the interrupt for the SmartFusion family of mixed signal flash based FPGAs 378 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 21 2 SmartFusion Master Register Map continued PDMA Register Map RATIO HIGH LOW 0x40004000 RAW Ratio of high priority transfers versus low priority transfers BUFFER_STATUS x 0 0x40004004 RAW Indicates when buffers have drained CHANNEL_x_CONTROL 0x40004020 a Channel 0 contro
22. 0 gt _1 APB Interface Timing and Control 4 FE ACE Fabric PDMA 4 DMAREADYO DMAREADY 1 AHB Bus Fabric Interface Controller Figure 3 1 Block Diagram PDMA Features e 8channels e Ping pong mode support Memory to memory DMA capable Channels can be designated as high priority Functional Description The PDMA consists of eight instances of a single DMA channel design Each channel can be configured to perform 8 bit 16 bit or 32 bit transfers from the peripheral to memory memory to peripheral or between memory and memory Channels can be assigned to peripherals or memory arbitrarily For example if the user is interested in receiving only DMA data from one of the SPI ports only one channel is required In this case the DIR bit in the CHx CONTROL REG would be set to 0 peripheral to memory and the PERIPHERAL SEL field would be set to 4 SPI 0 receive to memory Throughout this document a lower case x in register and signal descriptions is used as a place holder for 0 or 1 indicating PDMA 0 or PDMA 1 Revision 1 35 Meter Peripheral DMA PDMA If bidirectional DMA of peripheral to memory receive and memory to peripheral transmit is desired two channels must be programmed appropriately In particular the TRANSFER_SIZE fields in both the CHx_CONTROL_REG registers must be programmed identically The PDMA performs the correct byte lane adjustment
23. A WW i Chane afer Swans coun 9 demeissregse CHANNEL 2 BUFFER A SRCADDR 2 BUFFER 58 _ 0 40004068 0 Channel2 buffer A source address Channel 2 Channel 2 buffer A source address address Se MM 2 BUFFER A DST ADDR 0x4000406C MEE Channel 2 buffer A destination address CHANNEL 2 BUFFER A TRANSFER COUNT 0x40004070 Rw 0 Channel 2 buffer A transfer count CHANNEL 2 BUFFER B SRC ADDR 2 BUFFER B SRC ADDR 0x40004074 RW 0 2 buffer B source address Channel 2 Channel 2 buffer B source address B source address ERU GO 2 BUFFER B DST ADDR 0x40004078 Channel 2 buffer B destination address CHANNEL 2 BUFFER B TRANSFER COUNT 0x4000407C RW Channel 2 buffer B transfer count CHANNEL 3 CTRL 0x40004080 0 Channel 3 Control Register Revision 1 39 Aoo Meter Peripheral DMA PDMA Table 3 2 Memory Map continued Reset Register Name Address R W Value Description CHANNEL 3 STATUS 0x40004084 R Channel 3 Status Register CHANNEL 3 BUFFER SRC 3 BUFFER A SRC ADDR 0x40004088 RW 0 3 buffer A source address Channel 3 Channel 3 buffer A source address address Se 3 BUFFER A DST ADDR 0x4000408C Channel 3 buffer A destination address CHANNEL 3 BUFFER A TRANSFER COUNT 0x
24. ESRAMFWREMAP RAV Remap of embedded SRAMs 0 no remapping of the eSRAMs occurs 1 eSRAMO is mapped to location 0x00000000 and eSRAM1 is mapped directly above it After power on reset both eSRAM blocks are mapped into the SRAM bit banding area of Cortex M3 system space which is located from address 0x20000000 to address 0x20100000 In the Cortex M3 s view of the memory map the eSRAM area can be remapped to 0x00000000 within Cortex M3 code space This is done with boot code by setting the COM ESRAMFWREMAP bit in the ESRAM register eSRAM Configuration Register section of the AHB Bus Matrix section on page 15 address 0xE0002000 to 1 Revision 1 79 VActel Embedded SRAM eSRAM Memory Controllers Note The eSRAM continues to be available to the Cortex M3 at address 0x20000000 even when the eSRAM is remapped to address 0x00000000 in the Cortex M3 memory map The eSRAM is also visible to masters other than Cortex M3 although the corresponding port on the AHB bus matrix must be enabled by boot code before the fabric master can access eSRAM See the AHB MATRIX CR definition in the AHB Bus Matrix section on page 15 The eSRAM is always located at address 0x20000000 in the memory map seen by each of the masters other than Cortex M3 The COM ESRAMFWREMAP bit of the ESRAM CR eSRAM Configuration Register section of the AHB Bus Matrix section on page 15 controls only the memory map seen by the Cortex M3 Figure 6 1 dep
25. 24 SRC o 0 IOMUX 8 1 IOMUX 49 B i 25 SRC o 0 IOMUX 9 1 IOMUX 50 GPIN 26 SRC o 0 IOMUX 10 1 IOMUX 51 GPIN 27 SRC 0 IOMUX 11 1 IOMUX 52 GPIN 28 SRC o 0 IOMUX 12 1 IOMUX 53 29 SRC o 0 IOMUX 13 1 IOMUX 54 GPIN 30 SRC o 0 IOMUX 14 1 IOMUX 55 GPIN 31 SRC o 0 IOMUX 15 1 IOMUX 56 Revision 1 319 D LLL Meter General Purpose I O Block GPIO Microcontroller IOMUXO Subsystem MSS SPI 0 DO SPI 0 OE 16 SRC GPI 16 GPO 16 GPOE 16 IOMUX 41 Fabric Interface Tile M2F 25 F2M OE 25 F2M 25 Figure 18 3 Example of GPIN Source Selection from Two IOMUXes 320 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUXes Associated with GPIOs IOMUXes 0 15 and 25 56 used to multiplex MSS peripherals GPIOs and fabric interface signals to MSSIOBUFs The individual signal mapping for each IOMUX is listed in Table 18 7 through Table 18 54 on page 336 IOMUX 0 Table 18 7 1 0 LU mem ________ mss 995 ewm dT dT mwxes IOMUX 1 Table 18 8 IOMUX 1 A fe Ls se p s sev Fm 1L Em wwxim 1 L Es wes 1 1 1 1 I
26. 3 3 see FBSEL Table 8 31 gives bit definitions for FBSEL Table 8 31 FBSEL Bit Definitions Multiplexer Input Selected PLL delayed by FBDLY VCO 0 degree phase shift Revision 1 139 VActel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators 140 CCC Delay Configuration Register Table 8 32 MSS DLY CR Bit Mie nome mw Reise eiim O 31 25 Reserved RAW Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 24 20 DLYA1 RW 0611111 DLYA1 sets the delay from the output of the glitchless MUX to the FPGA fabric A value of 0 has a typical delay of 535 ps every time DLYA1 is incremented 200 ps is added to the base delay The default value of DLYAT is Ox1f See Table 8 33 19 15 DLYAO RW 0611111 sets the delay from the output of the glitchless MUX to the microcontroller subsystem A value of 0 hasa typical delay of 735 ps every time DLYAO is incremented 200ps is added to the base delay The default value of DLYAO is Ox1f See Table 8 34 on page 141 DLYC RAV Same bit definitions as DLYA See Table 8 35 on page 141 9 5 DLYB RAV Same bit definitions as DLYA See Table 8 35 on page 141 DLYA RAW DLYA sets the delay for the Global MUX A path output prior to the glitchless MUX A value of 0 has a typical dela
27. CR Bit Reset Number R W Value Description 31 23 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a OCDIVRST OCDIVHALF E 0 OCDIV defines the GLC YC output frequency divider 1 Use Table 8 13 on page 129 to determine GLC or YC output frequency divider page 130 Uu read modify write operation 0 Don t care 1 Reset the counter used to divide the GLC YC output frequency The rising edge of this bit will trigger a reset of the GLC YC output divider This bit is a don t care if the PLL is being used to drive the GLC or YC output OCDIV 0600011 These bits divide the output of the global buffer GLB or by the contents of OBDIV 1 See Table 8 14 on Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 Don t care 1 Reset the counter used to divide the GLB YB output frequency The rising edge of this bit will trigger a reset of the GLB YB output divider This bit is don t care if the PLL is being used to drive the GLB or YB output i IN OBDIVHALF 0 OBDIV defines the GLB YB output frequency divider 1 2 Use Table 8 15 on page 130 to determine GLB or YB output frequency divider These bits divide the output of the global buffer GL
28. Cycles and EMC Phases 2 0 2 85 Memory 2 EROR age ee Re REG RR RR 86 External Memory Device Examples 2 92 External Memory Controller Configuration 95 TIMING Riad edd ad uid eek AUR MAS 100 External Memory Controller 1 107 8 PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators 109 Functional Description a E 109 Input Clock Selection lt i sincss dees See Meee ey Pe ee 111 PLE Conifig rationi sd p eee iene 114 Glitchless MUX NGMUX 116 Safe Clock Switching Methods 4 119 On Chip RC Oscillator 1 2 120 Main Crystal Oscillator sse sia cuum ke a ng s e am ase ee FUR aur eG RR a ce RE d 121 PLE CCC Register Map undue REOR C b RC iw a re E E D a 124 S Reset Controlle
29. I2COSMBSUSNO Input Output Suspend Mode signal This signal is used if I2C is the master host Note Not a Wired AND signal I2COSMBALERTNO Output Wired AND interrupt signal This signal is used in slave device mode if the 2 wants to force communication with a host I2COSMBSUSNI Output Input Suspend Mode signal This signal is used if I2C is slave device Note Not a Wired AND signal I2COSMBALERTNI Input Wired AND interrupt signal This signal is used in master host mode to monitor if slave devices want to force communication with the host I2COBCLK Alternate clock for 2 0 12 15 505 Input Output Suspend Mode signal This signal is used if 12C is the master host Note Not a Wired AND signal I2C1SMBALERTNO Output Wired AND interrupt signal This signal is used in slave device mode if the 2 wants to force communication with a host 370 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 19 32 Miscellaneous Interface Signals continued I2C1SMBSUSNI Output Input Suspend Mode signal This signal is used if I2C is slave device NOTE Not a Wired AND signal I2C1SMBALERTNI Output Input Wired AND interrupt signal This signal is used in master host mode to monitor if slave devices want to force communication with the host I2C1BCLK Alternate clock for 2 1 Revision 1 371 VActel POWER MATTERS 20 SmartFusion Programming SmartFusion devices
30. IOMUX 29 GPIO 4 E AERE um MERE me p ql ee Revision 1 327 POCA te General Purpose I O Block GPIO IOMUX 30 Table 18 28 IOMUX 30 ge l1 mes L0 _ eMe meum fewer porno _ pp www p gc qo qn pL Jj 12 1 pep IOMUX 31 Table 18 29 IOMUX 31 DI esp l ses es LL ewxsm 1 LL Ls owes T IOMUX 32 Table 18 30 IOMUX 32 Pad IOMUX 32 Ports Ports IOMUX 32 CR NB poe jeep _ LLLA 328 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 33 Table 18 31 IOMUX 33 ooo o fe p e opo f ees ee cog O fos HERE NN NR el _ pre E ee ee ee eee IOMUX 34 Table 18 32 IOMUX 34 Name Pad IOMUX 34 Ports IOMUX34 CR INA OUTA ours ME m MEE FREE 7 Pu po 1 1 o IOMUX 35 Table 18 33 IOMUX 35 9 f ew me
31. When RATIOHILO is a 0 the high requests and the low requests will round robin This is built into the arbiter The arbiter does a high request and then asks if a low request is permitted Similarly a value of 1 in RATIOHILO will allow for ping ponging between high and low requests This is not to be confused with ping pong mode System Dependencies Clocks The PDMA runs off the system clock FCLK Users must be cognizant of the clock speed of the APB bus over which DMA transfers are being exercised The field WRITE ADJ contains a binary value indicating the number of FCLK periods the PDMA must wait after completion of a read or write access to a peripheral before evaluating the out of band status signals from that peripheral for another transfer This is typically used to ensure that a posted write has fully completed to the peripheral in cases where the peripheral is running at a lower clock frequency than the PDMA However it may also be used to allow the PDMA to take account of internal latencies in the peripheral where the ready status of a FIFO may not be available for a number of clock ticks after a read or write due to internal synchronization delays for example within the peripheral This applies particularly in the case of user designed peripherals in the FPGA fabric Resets PDMA registers are reset to zero on power up Users have the option under software control to reset the PDMA by writing to the System Register located
32. AHB Byte 3 AHB Byte 2 AHB Byte 1 AHB Byte 0 User Byte 3 User Byte 2 User Byte 1 User Byte 0 Figure 4 16 Aux Block Spare Pages Memory Mapping A program of either the Aux block or Aux block spare pages section to eNVM performs a program of the corresponding eNVM page The contents of the page are preserved however the program does count against the eNVM s endurance budget You can update the eNVM page then the associated Aux block or the eNVM spare page and associated spare page Aux block before programming the page to preserve eNVM endurance eNVM Block Protection Page Loss Protection When the PAGE LOSS bit is set to logic 1 the eNVM controller prevents writes to any page other than the current page in the page buffer until that page is either discarded or programmed in the eNVM cell array Addressing any other page while the current page is page loss protected will return ENVM STATUS x of 11 set the appropriate PROT ERROR x bit in the ENVM STATUS REG and assert an interrupt signal to the Cortex M3 if the ERROR x bit in the ENVM ENABLE REG is set Page Protection Any page that is write protected will result in the ENVM STATUS x being set to 01 when an attempt is made to write program or erase it To write protect a page use the PROGRAM PAGE PROTECTED or ERASE PAGE PROTECTED command To temporarily clear the protection state for a given page and allow modification of the page buffer issue a
33. gt gt gt gt A A N 5 B x x x x x x x x x x x x x e i m wo oo a o 1 4 Row 0 j 1 gt I Initial Latency Cycle EMC RDLATFIRSTx 1 1 2 4 Access Transactions 2 and 4 Access Transactions Only Latency Cycle EMC_RDLATRESTx 1 Latency Cycle Latency Cycle EMC_RDLATR ESTx 1 EMC_RDLATRESTx 1 4 Access Transactions Only r i IDD Cycle EMC IDDx 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Notes 1 2 3 4 5 6 7 EMC MEMTYPEx 01 or EMC MEMTYPEx 11 PIPERDNXx is ignored for these memory types PIPEWRNx is ignored for these memory types Initial shaded latency cycle is EMC RDLATFIRST FCLK cycles wide An EMC RDLATFIRST value of 0 will remove this cycle Shaded latency cycles are EMC RDLATREST FCLK cycles wide An EMC RDLATREST value of 0 will remove these cycles For single access reads If HADDR 1 0 00 DATA If HADDR 1 0 01 DATA If HADDR 1 0 10 DATA DO If HADDR 1 0 11 DATA DO For two access reads If HADDR 1 0 DATA If HADDR 1 0 01 DATA D1 DO For four access reads DATA 2 D3 D2 D1 DO Where EMC BYTE ENx is shown low only EMC BYTE E
34. 0 and ENVM PIPE BYPASS 1 the first read comes directly from the eNVM array The following reads up to three sequentially originate from the block buffer and occur in single cycles The read data path for this mode is illustrated in Figure 4 6 the dotted line shows the read data path New Block Same Block Block Block 4 RD 31 0 x Page Buffer Block Buffer Figure 4 6 Five Cycle Read Data Path ENVM SIX CYCLE 0 52 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide The timing diagram for this mode is illustrated in Figure 4 7 Note AHB signals are sampled on the rising edge of FCLK Figure 4 7 eNVM Read ENVM SIX CYCLE 0 and PIPE BYPASS 1 SEQ or NONSEQ Block Address 6 2 2 2 When the ENVM PIPE BYPASS bit is cleared to 0 the first read takes 6 cycles and the subsequent three reads insert a single cycle AHB pipeline delay in the read data path Figure 4 8 illustrates timing when ENVM PIPE BYPASS and ENVM SIX CYCLE are both 0 Figure 4 8 eNVM Read ENVM SIX CYCLE 0 and ENVM PIPE BYPASS 0 SEQ or NONSEQ Block Address 5 1 1 1 Read Next Operation The Read Next operation reads the next sequential block in the eNVM array relative to the current block in the block buffer while the block buffer is being read The goal is to minimize wait states during consecutive sequential block read operations The Read Next op
35. 1 Enabled Revision 1 279 __________________________ MAefel Universal Asynchronous Receiver Transmitter UART Peripherals Line Control Register LCR Table 15 11 LCR Divisor latch access bit Enables access to the divisor latch registers during read or write operation to address 0 and 1 0 Disabled default 1 Enabled Set break Enabling this bit sets SOUT to 0 This does not have any effect on the transmitter logic 0 Disabled default 1 Enabled Stick parity 0 Disabled default 1 Enabled When stick parity is enabled the parity bit is set according to bits 4 3 as follows 11 0 is sent as parity bit and checked when receiving 01 1 is sent as parity bit and checked when receiving Even parity select 0 Odd parity default 1 Even parity Parity enable When enabled parity is added to transmission and checked when receiving 0 Disabled default 1 Enabled Number of stop bits STB 0 1 stop bit default 121 stop bits when WLS 00 The number of stop bits is 2 for all other cases not described above STB 1 and WLS 01 10 11 Word length select 0600 5 bits default 0501 6 bits 0b10 7 bits 0b11 8 bits 280 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Modem Control Register MCR Table 15 12 Pa Bit RAV Software should not rely on the value of a reserved bit To provide compatibility
36. 14 through IRQ 19 correspond to bit locations 14 through 19 respectively The user must also enable SMBus interrupts I2C x SMBALERT and I2C x SMBSUS in the 2 peripheral by setting the appropriate bits in the SMBUS register The user must clear the appropriate bit in the SMBus Register in the respective interrupt service routine to prevent a reassertion of the interrupt The I2C x INT I2C x SMBALERT and I2C x SMBSUS 12 interrupt signals can be monitored by FPGA logic via the fabric interface interrupt controller FIIC These six signals three for each 2 combined with other interrupt sources and connected to the MSSINT 0 bit One exception while in non ACE mode is that the I2C 1 INT interrupt signal is connected to MSSINT 5 bit Refer to the Fabric Interface and IOMUX section on page 341 for more details Revision 1 253 VActel Inter Integrated Circuit Peripherals Fabric Interface Signals Associated with I2C 0 and I2C 1 Some I C signals are connected directly to the fabric interface so they can be routed to FPGA logic or FPGA I Os Table 14 2 lists the I C signals available on the fabric interface Refer to the Fabric Interface and IOMUX section on page 341 for more information Table 14 2 Fabric Interface Signals I2C 0 and I2C 1 Signals Input to Output from FPGA Fabric Function I2COSMBSUSNO Input Output suspend mode signal used if 12 is the master host Note Not a wired AND signal I
37. AICR INA p eL ____ Jeep _ _____ NENNEN CUN Rmi ioUXWbYvZ p m GPIO 22 RES MOR gt Revision 1 333 __________________ General Purpose I O Block GPIO IOMUX 48 Table 18 46 IOMUX 48 si 1 op o jew cozy O ewa Lo ee eee IOMUX 49 Table 18 47 IOMUX 49 IOMUX 49 Ports __ _ _ NNUS 2 Em ewan Lr lcd __ IOMUX 50 Table 18 48 IOMUX 50 Pad IOMUX 50 Ports Ports IOMUX 50 CR OUT A ms ours oes pee o m D pecus 5 mg py pp E E po 334 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 51 Table 18 49 IOMUX 51 LE oo qesp s ex me 0 1 Jew ______ exwow ru _ eee eee IOMUX 52 Table 18 50 IOMUX 52 IOMUX 52 Ports 2222 f wed p C Ds eus fp Es ewxxs IOMUX 53 Table 18 51 IOMUX 53 E emp p we 1 s mx me gos 1 cuxwowz wr
38. OEA INB OUT B OEB ener 2 4 144 UART 0 DCD ee Soe ie m LL m owxem LL cq _ IOMUX 12 Table 15 25 IOMUX 12 T wee wem 5112 21 3 E GNE CLONE NER _ pug euge 288 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 13 Table 15 26 IOMUX 13 Pad IOMUX 13 Ports Pad Name Ports _ IOMUX 13 CR OUT A OEA NB OUT B A o ju meme qu X 3j pue IOMUX 77 Table 15 27 IOMUX 77 IOMUX 77 Ports wal oura oral ms ours one 1 9 ewe gt ewrs 1 1 3 IOMUX 78 Table 15 28 IOMUX 78 WAL ora ws oes Ld Lowe 9 wem Cw www IL 1 1 Revision 1 289 VActel Universal Asynchronous Receiver Transmitter UART Peripherals IOMUX 79 Table 15 29 IOMUX 79 Pad Pad Name Ports IOMUX 79 CR IOMUX 80 NN eee BELLI B Table 15 31 IOMUX 81 Table 15 30 OMUX 80 Pad IOMUX 80 Ports IOMUX 81 Ports
39. Revision 1 183 Ethernet MAC 184 VActel Table 12 8 Transmit Descriptor TDESO Bit Functions ms Rad 31 OWN Ownership bit 1 Ethernet MAC owns the descriptor 0 The host owns the descriptor Ethernet MAC will clear this bit when it completes a current frame transmission or when the data buffers associated with a given descriptor are empty mue 15 5 Error summary This bit is a logical OR of the following bits TDESO 1 Underflow error TDESO 8 Excessive collision error TDESO 9 Late collision TDESO 10 No carrier TDESO 11 Loss of carrier This bit is valid only when TDES1 30 last descriptor is set Loss of carrier When set indicates a loss of the carrier during a transmission This bit is valid only when TDES1 30 last descriptor is set No carrier When set indicates that the carrier was not asserted by an external transceiver during the transmission This bit is valid only when TDES1 30 last descriptor is set Late collision When set indicates that a collision was detected after transmitting 64 bytes This bit is not valid when TDESO 1 underflow error is set This bit is valid only when TDES1 30 last descriptor is set Excessive collisions When set indicates that the transmission was aborted after 16 retries This bit is valid only when TDES1 30 last descriptor is set o p pee 6 3 CC Collision count This field indicates the number of coll
40. Table 11 1 Watchdog Register Interface WDOGLOAD 0 40006004 0 20000000 Load value for counter e End E Eum Maximum value for which refreshing is permitted WDOGREFRESH 0x4000600C Writing the value OXAC15DE42 to this register causes the counter to be updated with the value in WDOGLOAD register WDOGENABLE 0x40006010 Watchdog enable register WDOGMIS 0x40006020 R 00 Masked interrupt status MSS SR 0xE004201C MSS Status register Watchdog Register Interface Details This section describes each of the Watchdog registers in detail Watchdog Value Register WDOGVALUE Table 11 2 WDOGVALUE Bit Bit Number RW Reset Reset Value ____________ EIE 0 EL COUNT This read only register contains the current value EE the Watchdog s 32 bit counter 166 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Watchdog Load Register WDOGLOAD Table 11 3 WDOGLOAD 31 0 COUNT UPDATE VALUE RAW 0x20000000 The value stored in this register is used to update the counter whenever the value 150 42 is written to the WDOGREFRESH register When the WDOGLOAD register is written to the lower 6 bits of the register are always set to 1 This sets a lower limit of Ox3F on the value written to the counter during a refresh Watchdog Maximum Value Refresh Permitted Register WDOGMVRP Table 11 4 WDOGMVRP 31 0 MVR
41. Table 12 37 CSR8 wr reve OOO 31 29 Reserved 0b111 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Overflow counter overflow read only Gets set when the FIFO overflow counter overflows Resets when the high byte bits 31 24 is read FIFO overflow counter read only Counts the number of frames not accepted due to receive FIFO overflow The counter resets when the high byte bits 31 24 is read When FIFO overflow occurs the truncated frame is DMAed to memory with the CRC bit set Missed frame overflow Set when a missed frame counter overflows The counter resets when the high byte bits 31 24 is read Missed frame counter read only Counts the number of frames not accepted due to the unavailability of the receive descriptor The counter resets when the high byte bits 31 24 is read The missed frame counter increments when the internal frame cache is full and the descriptors are not available Revision 1 211 ________________________ __ Acte Ethernet MAC RMII Management Interface Register CSR9 Table 12 38 Management Interface Register CSR9 mena poppe wem owe 5 0 0 05 os 7 X0 O Note The CSR9 register has unimplemented bits shaded If these bits are read they will return a
42. Table 18 39 IOMUX 41 91 jew mm O 22 1 4 stp wer Jg Revision 1 331 _________________ General Purpose I O Block GPIO IOMUX 42 Table 18 40 IOMUX 42 D oem op opp 9 Lem mes IOMUX 42 PD p ee ee ee eee IOMUX 43 Table 18 41 IOMUX 43 IOMUX 43 Ports x ET 2 2 Pm ewan a LI E 1 q IOMUX 44 Table 18 42 IOMUX 44 E esp we y es O Twucur 2 2 02 3 II 332 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 45 Table 18 43 IOMUX 45 LO ee p qwe wm O eow Pm ora e pss dec spi pm p p p pex I pog IOMUX 46 Table 18 44 IOMUX 46 IOMUX 46 Ports MUEBLES ce 4 EIE NE prs IOMUX 47 Table 18 45 IOMUX 47 IOMUX 47 Ports Ports IOMUX 47 CR OUT A NB OUT B OEB
43. The IEEE 802 3 indirection tristate signal defines the MDIO Figure 12 2 shows the RMII management interface to an external RMII PHY device Ethernet MAC External RMII PHY Figure 12 2 RMII Management Interface Functional Blocks of Ethernet MAC AHB Master Interface The AHB block implements an AHB master function allowing the DMA controller to access memory on the AHB bus APB Slave Interface This APB block implements an APB slave interface allowing the Cortex M3 processor to access the Control and Status Registers set CSR Control Status Register Logic CSR The CSR component is used by the Cortex M3 processor to control Ethernet MAC operation It contains the CSR register set and the interrupt controller The CSR also provides an RMII management interface which the Cortex M3 processor can access via reading and writing to the CSR registers Refer to the CSR Definitions section on page 198 Direct Memory Access Controller DMA The direct memory access DMA controller implements the host data interface It services both the receive and transmit channels The and TFIFO have access to one DMA channel RLSM and RFIFO have access to the other DMA channel Transmit Linked List State Machine TLSM The transmit linked list state machine implements the descriptor buffer architecture of Ethernet MAC It manages the transmit descriptor list and fetches the data prepared for transmission from the data buffers i
44. The descriptor owned by the host is found The current descriptor s position is retained The transmit FIFO underflow error is detected An underflow error is generated when the transmit FIFO is empty during the transmission of the frame When it occurs the transmit process enters a suspended state Transmit automatic polling is internally disabled even if it is enabled by the host by writing the TAP bits The current descriptor s position is retained Leaving a suspended state is possible in one of the following situations Atransmit poll demand command is issued This can be performed by writing CSR1 with a nonzero value The transmit poll demand command can also be generated automatically when transmit automatic polling is enabled Transmit automatic polling is enabled only if the CSRO 19 17 TAP bits are written with a nonzero value and when there was no underflow error prior to entering the suspended state Astop transmit command is issued by the host This can be performed by writing 0 to the CSR6 13 ST bit The current descriptor s position is retained The events for the transmit process typically happen in the following order The host sets up CSR registers for the operational mode interrupts etc The host sets up transmit descriptors data in the shared RAM The host sends the transmit start command Ethernet MAC starts to fetch the transmit descriptors Ethernet MAC transfers the transmit data to Transmit Data R
45. This is the normal mode of operation where both the MSS and the FPGA fabric are operational is running and the Cortex M3 is active All memory controllers are enabled This is the default mode of operation after a power on reset when the device is configured for the 1 5 V regulator to be active on power up PUPO 1 If the device is not configured for the 1 5 V regulator to be active on power up PUPO 0 this state can be entered when PU N 0 Refer to Figure 10 5 on page 156 for entry and exit transition requirements Standby Mode This mode is for applications that intend to put the device into a low power state but be ready to respond to an interrupt that is sourced from the MSS the FPGA or the analog front end Firmware transitions into this mode after reset by executing a wait for interrupt WFI instruction in the Cortex M3 causing FCLK to be gated off to the Cortex M3 This disables the majority of the Cortex M3 logic In Standby mode the SmartFusion device is active but running off of a lower frequency clock than what is used for normal system operation For example the 32 Khz oscillator can be used to clock the MSS Peripherals not being used can be put into a low power state by asserting their individual resets in the SOFT RST CR In addition if the analog front end is not needed during this state the user can turn off portions or the entire analog block The ABPOWERDOWN bit in the ANA COMM CTRL register will disable
46. When PIPEWRNXx is deasserted High writes to synchronous SRAMs in the region controlled by chip select x where x can be 0 or 1 are not pipelined with timing illustrated per Figure 7 23 on page 106 Non Pipelined Synchronous Write Cycle EMC PIPEWRNXx has no effect for asynchronous SRAMs and NOR flash devices Inter Device Delay EMC IDDx The field EMC IDDx determines the number of latency cycles inserted between consecutive memory accesses and also defines the number of latencies when switching from synchronous to asynchronous memories and vice versa Each cycle is defined to be 1 FCLK period Zero to a maximum of 3 latency cycles can be programmed by the user The first IDD cycle occurs in the FCLK period following HREADYOUT assertion at the end of an EMC access for asynchronous reads and writes flash reads and writes and synchronous writes For synchronous reads the first IDD cycle occurs in the FCLK period of HREADYOUT assertion at the end of an EMC access Note that in practice this limits the IDD delay for synchronous reads to two FCLK periods with EMC IDDx 0 having the same effect as EMC IDDx 1 One IDD cycle is always inserted when the memory type changes from synchronous to flash or asynchronous and one IDD cycle is also inserted when the memory type changes from flash or asynchronous to synchronous Alternate Chip Select Falling Edge CSFEx When EMC CSFEx 0 EMC CSx N is asserted on the rising edge of F
47. management CSR11 0x40003058 0 0000 Timer and interrupt mitigation control Note CSR9 bits 19 2 reset values are dependent on the MDI and SDI inputs The above assumes MDI is high and SDI is low Revision 1 197 ________________________ _ Acte Ethernet MAC CSR Definitions Bus Mode Register CSRO Table 12 17 Bus Mode Register CSRO mena puppe seco vo ees a Bits 15 8 ses 5 T Note The CSRO register has unimplemented bits shaded If these bits are read they will return a predefined value as shown in Table 12 18 Writing to these bits has no effect Table 12 18 CSRO 31 22 061111111000 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Clock frequency selection This bit selects the clock frequency for CLKT and CLKR When this bit is set to 0 CLKT and CLKR are 2 5 MHz When this bit is set to 1 CLKT and CLKR are 25 MHz Descriptor byte ordering mode 1 Big endian mode used for data descriptors 0 Little endian mode used for data descriptors Transmit automatic polling If TAP is written with a nonzero value Ethernet MAC performs an automatic transmit descriptor polling when operating in suspended state When the descriptor is available the transmit process goes
48. own SLA or general call address will be returned recognized or read data byte Switched to not addressed SLV mode no recognition of own SLA or general call address START condition will be transmitted when the bus becomes free or read data byte Switched to not addressed SLV mode own SLA or general call address will be recognized START condition will be transmitted when the bus becomes free 0x90 Previously addressed with general call address DATA has or read data byte Data byte will be received and ACK will anes be returned been received ACK returned 0x98 Previously Read data byte Switched to not addressed SLV mode no addressed with recognition of own SLA or general call general call alg PATANAS or read data byte Switched to not addressed SLV mode een received SLA or general call address will be NACK returned own 9 recognized or read data byte Switched to not addressed SLV mode no recognition of own SLA or general call address START condition will transmitted when the bus becomes free or read data byte Switched to not addressed SIV mode own SLA or general call address will be recognized START condition will be transmitted when the bus becomes free Notes 1 SLA Slave address 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave 262 Revision 1 Table 14 8 S
49. sxo OODQOODOQAE gt gt gt COOGOHOOVO LAND HIGH IMPEDANCE SPI_X_DI Figure 13 13 Page Program Timing In this mode the op code address and data require more than 32 clock periods To drive this device the chip select CS can be connected to the slave select signal the data frame size set to 16 and the FIFO repeatedly filled until the target flash device is programmed As long as there is data to be transmitted in the FIFO the chip select signal connected to slave select on the SPI controller should be asserted Low Devices that Do Not Support Mode 1 SPO 0 and SPH 1 or Mode 3 SPO 1 and SPH 1 For flash devices which do not support mode 1 SPO 0 and SPH 1 or mode 3 SPO 1 and SPH 1 it is necessary to use a dedicated GPIO pin to drive the chip select signal The device driver would initially assert the chip select through the GPIO then activate the SPI transfer possibly comprising many individual 32 bit data frames and finally withdraw the GPIO 232 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide SPI Register Interface Summary Table 13 3 summarizes each of the registers covered by this document There are two addresses for each register one for each of the SPI controllers in a SmartFusion device Table 13 3 SPI Register Summary Register Name Address SPI 0 Address SPI 1 CONTROL TXRXDF SIZE STATUS INT CLEA
50. 4 Beat 2 and 4 Beat 4 Beat Accesses Only 1 2 4 Beat Accesses Accesses Only Accesses Figure 7 23 Non Pipelined Synchronous Write Cycle 106 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide External Memory Controller 1 05 I Os used for the are found on the north side and west side of the FPGA device These I Os shared with user logic That is if the user does not need the 1 5 are available for FPGA logic resources If however the is used those FPGA I Os are dedicated to the The EMC SEL bit in the CR register is used to select either FPGA I O or EMC I O as defined Table 7 14 EMC MUX CR is located at address 0xE004203C in the system memory map If the user sets the EMC PORTSIZEx bit to 0 8 bit memory for both chip selects the upper 8 bits of the data bus FPGA are available to user logic Table 7 14 EMC I O Configuration Control MUX CR The multiplexed I Os are allocated to the FPGA logic The multiplexed I Os are allocated to the Table 7 15 EMC Pins Pin Name Input Output Function Count ear warea oaos 3 15 Revision 1 107 VActel POWER MATTERS 8 PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators This section describes the oscillators phase locked loops PLLs and clock conditioning circuitry CCC that exist in Actel SmartFusio
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52. EMC RDLATFIRSTx value of 0 causes address to be presented i 5 data sampled in the same FCLK cycle 4 4 6 6 Shaded latency cycles are EMC_RDLATRESTx 1 FCLK cycles wide An EMC RDLATRESTx value of 1 will remove these latency cycles 7 An EMC RDLATRESTx value of 0 causes address to be presented and 8 data to be sampled in the same FCLK cycle 7 For single access writes If HADDR 1 0 00 If HADDR 1 0 01 DATA LM gt lE gt Oz gt DO If HADDR 1 0 10 DATA DO If HADDR 1 0 11 DATA DO For two access writes If HADDR 1 0 DATA If HADDR 1 0 01 DATA D1 DO For four access writes DATA D3 D2 D1 DO 8 Where EMC BYTE ENx is shown low only EMC BYTE ENx for the active byte lane s will go low BYTE for active byte lanes will remain high TECUM 77 LE EMC RDB is registered in the EMC here Initial Latency Cycle Latency Cycle RDLATFIRSTx 22 RDLATRESTx 22 RDLATRESTx 22 RDLATRESTx 2 Latency Cycle Latency Cycle IDD Cycle IDDx 2 Start of next access delayed by IDD 1 2 4 Access 2 and 4 Access 4 Access Transactions Only 1 2 4 Acc Transactions Transactions Only Transactions Figure 7 19 Non Pipelined Synchronous Read Cycle 102 Revision 1 V
53. Jr __ an ep qo do poo qe Emu 1 sewer de e cd 3 Revision 1 325 D LLL Meter General Purpose I O Block GPIO IOMUX 15 Table 18 22 IOMUX 15 Pad IOMUX 15 Ports Pad Name Ports IOMUX 15 CR NB EX mx ees _ 11 E IOMUX 25 Table 18 23 IOMUX 25 IOMUX 25 Ports esp ww S 270 ses ewm ewm ewess IOMUX 26 Table 18 24 IOMUX 26 Pad IOMUX 26 Ports e e _ e 24 7 3E eee 326 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 27 Table 18 25 IOMUX 27 OE ee p ope 9 ee p arog Pee Femo ce pe dh Lo dq 1 IOMUX 28 Table 18 26 IOMUX 28 IOMUX 28 Ports fef p e 21 27 f se Em ewm IOMUX 29 Table 18 27
54. MSS GPIO Functional 1 1 4 35 4 316 GPIO Register 3 eem ded radon d al RO ENS ang ERR dos kdo er Poeta t oe 317 MSS GPIO Register 22 22 2 22 2 224 00 lt n RUD A VOX QUIA 317 MSS GPIO Logic Thresholds ze Y DES DESCR E 318 GPIN Source Select Register 319 IOMUXes Associated with GPIOs 1 2 4 321 SmartFusion MSS GPIO Application Development 337 19 Fabre Iotertace ang ui d oc d db RD e RR modes dd E 341 Fabric Interface Controller cus eR 342 Fabric Interface and IOMUX Register Map 1 345 Fabric Iriterface Control FIC Ra Re dese ERR E GG a UP Chi Red Rud 346 MSS Master Interface 4 1 347 Fabric Master Interface Pe eee Mead dead a 349 Fabric Interface Interrupt Controller FIC 10 351 IOMUX Functional Description 1 364 IOMUX Register Map
55. THR Table 15 4 THR Bit 7 0 THR This register holds the data bits to be transmitted Bit 0 is the LSB and is transmitted first The reset value is unknown since the register is loaded with data in the Transmit FIFO The divisor latch access bit DLAB bit 7 of LCR must be O to write to this register This register is write only reading from this register with the DLAB 0 reads the RBR register value Divisor Latch LSB Register DLR Table 15 5 DLR Bit 7 0 DLR RAV 0x01 This register holds the LSB of the divisor value used to calculate the baud rate The baud rate BR clock is generated by dividing the input reference clock PCLK 0 for UART 0 and PCLK 1 for UART 1 by 16 and the divisor value as shown in EQ 15 1 BR FCIKx __ 16 x divisor value EQ 15 1 The divisor latch access bit DLAB bit 7 of LCR must be 1 to access this register Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Divisor Latch MSB Register DMR Table 15 6 DMR Bit Number Name R W This register holds the MSB of the divisor value used to calculate the baud rate The baud rate BR clock is generated by dividing the input reference clock PCLK 0 for UART 0 and PCLK 1 for 1 by 16 and the divisor value as shown in EQ 15 2 Be ee 16 x divisor value EQ 15 2 The divisor latch access bit DLAB bit 7 of LCR must be 1 to access this register Interrupt Enable Re
56. Table 8 20 MAINOSCMODE Bit Definitions MAINOSCMODE Bit 31 Bit 30 Clock Mode Function RC network RCoscillation mode Connects the RC network to the MAINXIN pad The MAINXOUT pad should be disconnected 1 Low gain 0 32 to 0 20 MHz low power frequency mode Oscillator consumes the least current of the three crystal modes 1 0 Medium gain 0 20 to 2 0 MHz standard crystal resonator frequency 1 High gain 2 0 to 20 0 MHz high frequency mode Oscillator consumes the most current of the three modes 134 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide GLMUXCFG 27 26 and GLMUXSEL 25 24 Table 8 21 gives bit definitions for GLMUXCFG and GLMUXSEL Table 8 21 GLMUXCFG and GLMUXSEL Bit Definitions GLMUXCFG GLMUXSEL OCMUX Table 8 22 gives bit definitions for OCMUX Table 8 22 e OCMUX Bit Definitions MUX and PLL are bypassed PLL VCO 0 feedback delay line output from FBDLY Revision 1 135 __________________ PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators DYNCSEL RXCSEL and STATCSEL Table 8 23 gives bit definitions for DYNCSEL RXCSEL and STATCSEL Table 8 23 DYNCSEL RXCSEL and STATCSEL Bit Definitions o3 o3 3 89 03 OBMUX Table 8 24 gives bit definitions for OBMUX Table 8 24 OBMUX Bit Definitions OBMUX Bit 13 Bit12 Bit 11 Function os o
57. VActel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators CLKA RC Osc Main Osc RXASEL STATASEL DYNASEL Figure 8 5 CLKA Multiplexers CLKA can be driven from one of the following 3dedicated single ended I Os using a hardwired connection AUIN AUIP ADIP e Two dedicated differential I Os using a hardwired connection AUIP pair ADIN ADIP pair The FPGA fabric GLAINT The RC oscillator The Main oscillator Similar to configuring CLKA CLKB and CLKC have their own set of control bits to allow dynamic configuration of their clock sources Table 8 2 CLKB and CLKC Input Clock Sources em we 9 jw E 32 KHz oscillator X RC oscillator 1 X Main oscillator RUM 1 MESE NH ks Revision 1 Figure 8 6 VActel Actel SmartFusion Microcontroller Subsystem User s Guide GLAINT STATASEL DYNASEL GLBINT STATBSEL DYNBSEL DLY C 14 10 GLCINT STATCSEL DYNCSEL PC Configuration Bits Dynamic JTAG Shift CCC Configuration Bits Register Simplified View of CCCs Without a PLL Revision 1 113 dL Meter PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators PLL Configuration PLL Core Operating Principles This section briefly describes the basic principl
58. data Reading this clears the register 2 the received data SPI Transmit Data Register TX DATA Table 13 9 TX DATA Bit Number WINS Reset Value 31 0 Data to EE MM transmitted Writing to this clears the last data transmitted 236 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SPI SCLK Generation Register CLK GEN Table 13 10 GEN Bit Number Name Reset Value Description 31 4 Reserved 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation SCLKOGEN 0b0111 Specifies the division of incoming PCLK for generation of SPI x CLK Default divisor is 256 Decode 0000 PCLK 2 0001 PCLK 4 0010 PCLK 8 0011 PCLK 16 0100 PCLK 32 0101 PCLK 64 0110 PCLK 128 0111 PCLK 256 default SPI Slave Select Register SLAVE_SELECT Table 13 11 SLAVE_SELECT Bit Number Name R W Reset Value Description 31 8 Reserved R W N A Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 0 SLAVESELECT R W 0 Specifies the slave selected Writing 1 to a bit position selects the corresponding slave SLAVESELECT 7 1 are available at the FPGA fabric interface while SLAV
59. eNVM controller 62 eSRAM 79 fabric interface and IOMUX 345 GPIO 317 I2C peripherals 255 PDMA 39 PLL CCC 124 reset controller 148 RTC 297 SmartFusion master register map 377 SPI 233 SYSREG 377 system timer 305 UART 275 watchdog timer 166 remapping embedded SRAM 21 reset control 177 reset controller 143 block diagram 143 functional description 143 outputs 144 state machine 146 reset controller register map 148 RIS 238 RTC block diagram 295 functional description 296 real time counter features 295 register map 297 RX DATA 236 5 5 signals 368 signals DAC 369 miscellaneous 370 398 Actel power supply monitor 369 SCB to FPGA fabric 368 voltage regulator 369 Single Wire Viewer 8 SLAVE_SELECT 237 Sleep mode 155 SMBUS 267 SoC mode 155 SOFT_RST_CR 148 SPI error recovery 224 SPI Controller IOMUXes 238 SPI controller block diagram 221 222 clock requirements 224 functional description 221 interface signals 223 MICROWIRE protocol 228 modes of transfer 222 Motorola protocol 225 operation 223 register map 233 reset 224 TI synchronous protocol 229 transfer for large flash EEPROM 230 SR UART 283 Standby mode 155 STATUS 235 STATUS 120 257 SYSREG register map 377 SysTick timer 8 T technical support 393 Texas Instruments protocol 229 THR UART 276 TI protocol 229 tick generate 9 TIM64 BGLOADVAL L 310 TIM64 BGLOADVAL U 309 TIM64 CTRL 310 TIM64 LOADVAL L 309 TIM64 LOADVAL U 309 TIM64 MIS 311 TIM
60. if the user wishes to use a different clock source or change the clock frequency driving GLAO or GLA1 the user must wait for the desired clock source to stabilize before switching the glitchless MUX from the old clock source to the new clock source For example after power up change the clock frequency driving the MSS from a 25 MHz RC oscillator source to a 100 MHz RC oscillator source Step 1 Write to MSS CCC MUX CR to select the RC oscillator and bypass the PLL 1 Set RXASEL bit to 0x1 2 Clear DYNASEL to 0x0 3 Set BYPASSA to 0 1 Revision 1 119 __________________ PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators Step 2 Write to MSS CCC MUX CR to select the GLA path Set GLMUXSEL bits to 0x0 In the above example it is not acceptable to change the divider value in OCDIV from 4 to 1 to effect the desired change from 25 MHz to 100 MHz It is not acceptable to effect all changes targeted to the MSS CCC MUX CR in one single write The divider circuitry is not glitchless and would have passed a glitch along to the MSS The switching of the glitchless MUX must occur last Also it was assumed that switching the CLKA path input to the PLL had no unintended consequences for the GLB output driving the FPGA fabric if it is being used by the fabric In general the frequency of the GLB YB GLC and YC outputs to the FPGA fabric can be changed by the Cortex M3 User logic in the FPGA fabric must be
61. power supply monitor PSM where it is compared against the precision band gap to create the VCC33GOOD signal The VCC33GOOD signal becomes High at approximately 2 5 V If the VCC33GOOD signal deasserts the functionality of the analog front end is in question To detect a brownout condition the VCC33A supply the user should enable the INT ISR2 BROWNOUT3_3V_IRQ and place the interrupt service routine in eSRAM Use the ADC to monitor the VCC33A supply voltage when it drops below 2 95 issue a soft reset to the reset controller VR Init During initial power up VCC33 is below the VCC33UP detection level During this time current sources supply current to the two flash bits as shown in Figure 10 2 Normally one of these flash bits will be programmed and the other will be erased The resulting voltage difference is applied to a comparator whose output drives the power up power on signal PUPO When VCC33UP goes high the PUPO logical output is held latched to its evaluated state and the current sources disabled to conserve power PUPO will not be reevaluated again until VCC33UP is again in a low state The PUPO signal determines whether or not the VR is enabled when 3 3 V is first applied to the SmartFusion device The configuration of the flash bits is done through the MSS configurator VCC33UP GND Figure 10 2 VR Init Block Diagram 1 5 V Voltage Regulator The VR consists of a high gain amplifier resistor voltage divi
62. reset default 1 Weighted round robin slave arbitration COM_MASTERENABLE Enable control for each of the non Cortex M3 masters connected to the AHB bus matrix For each of these masters if the corresponding bit is 0 then the master cannot access any of the slave ports connected to the matrix If the bit is 1 the master can access any of the slaves connected to the matrix In the case of the fabric master access is further qualified with the protected region mechanism described above The bits have the following definitions Bit 2 Peripheral DMA 0 Peripheral DMA cannot access any AHB bus matrix slaves 1 Peripheral DMA has access to the AHB bus matrix slaves Bit 1 Ethernet MAC Ethernet MAC cannot access any AHB bus 12 slaves 1 Ethernet MAC has access to the AHB bus matrix slaves Bit 0 FPGA fabric master 0 FPGA master cannot access any AHB bus matrix slaves 1 FPGA master has access to AHB bus matrix slaves qualified by PROT BASE CR and FAB PROT SIZE CR values Revision 1 31 Acte AHB Bus Matrix Microcontroller Subsystem Status Register MSS SR Table 2 13 MSS SR Bit Reset Number R W Value Description 31 11 Reserved 0x00000 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PLLLOCKLOSTINT This bit indicates that a falling edge event occurr
63. section was revised to include the March 2010 fact that SWV operates at 98 KHz Figure 3 1 PDMA Block Diagram was revised to change the Bus Matrix and APB Interface blocks to AHB Bus Matrix and AHB Interface WRITE ADJ in the Clocks section and SOFTRESET was changed to PDMA SR in the Resets section Table 3 6 PERIPHERAL SEL was revised to exchange the definitions of the 1000 and 1001 bit combinations Table 3 7 CHANNEL x STATUS was revised The definitions of the bit numbers changed Two bit field names were corrected WR ADJUST was changed to 38 The ENVM CONFIG 0 REG ENVM CONFIG 1 REG registers were renamed to ENVM 0 CR and ENVM 1 CR References to them throughout the chapter and datasheet were revised Captions were revised in Figure 4 1 Block Diagram of eNVM Controller with Two eNVM Blocks to make signal names consistent in format Figure 4 5 Address Figure 4 5 e Address Decoding for eNVM Read Operations was revised _ for eNVM Read Operations was revised Bit 9 was changed to MSB and Bit 8 was changed to LSB in the headings MM Table 4 12 e STATUS x CONFIG x REG was replaced with CS x CR x 0 or 1 This was terminology change throughout the document The HWRITE signal was revised in Figure 7 3 AHB Address Data Phase for 83 Write Transfer The following sentence was removed from the FCLK Cycles Required for Memory Accesses section When
64. signal can then be connected to a FPGAIOBUF using the SmartDesign tool Similar configuration applies to Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SPI 1 SS 1 SPI x SS 2 SPI x SS 3 SPI x 55 4 SPI x SS 5 SPI x SS 6 and SPI x SS 7 Table 13 15 shows the associated GPIO IOMUX and fabric interface signals for these signals Table 13 15 SPI Extra Signal GPIO and Fabric Mapping SPI x Signal Fabric Interface Signal SPI 0 SS 1 M2F 41 SPI 0 SS 2 M2F 42 SPI 1 SS 3 M2F 56 SPI 1 SS 4 M2F 57 SPI 1 SS 5 2 58 SPI 1 SS 6 2 59 Table 13 16 through Table 13 33 on page 247 give descriptions for all IOMUXes associated with SPI x signals IOMUX 0 Table 13 16 lOMUX 0 IOMUX 0 Ports LL m mxew d uh Revision 1 241 Acte Serial Peripheral Interface SPI Controller IOMUX 1 Table 13 17 IOMUX 1 Pad Name Ports 1 CR NB OEB Gl NN SPI 0 DI GPIO 17 IOMUX 1 PU IOMUX 1 PD IOMUX 1 ST IOMUX 2 Table 13 18 IOMUX 2 IOMUX 2 Ports qe arcane ees
65. the COM ERRORINTERRUPT which maps to IRQ24 in the ARM Cortex M3 interrupt controller will be asserted The specific master which caused the error can be determined by reading the MSS SR located at address 0xE004201C Specifically the COMM ERRORSTATUS field indicates which master generated the error condition It should be noted that PSRAMS are only supported in asynchronous mode Table 7 11 Valid Combinations of EMD Types Table 7 12 defines EMC PORTSIZEx EMD data bus width is either 16 bits or 8 bits AHB transactions on the AHB bus matrix can be up to 32 bits wide Therefore all AHB accesses wider than the configured EMD data bus width must be converted into half word or byte EMD accesses depending on the configured EMD bus width Table 7 12 EMC PORTSIZEx Definition 96 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 7 13 illustrates how the EMC converts AHB transactions into various EMC accesses based on EMD data bus width Table 7 13 Mapping of AHB Transactions to EMC Accesses AHB Input Transaction Access 2 1 0 AB 1 0 HRDATA HWDATA Bits EMC PORTSIZEx HADDR 1 0 EMC BYTE EN EMC DB Bits EMC AB 1 0 HRDATA HWDATA Bits EMC DB Bits EMC AB 1 0 HRDATA HWDATA Bits EMC DB Bits HRDATA HWDATA Bits EMC DB Bits SEE No Accesses Required EE 5 HSIZE 1 0 41 f IE sept meses L se pr C E ear
66. 0x50 Data byte has been received ACK has been returned Notes SLA Slave address SLV Slave REC Receiver TRX Transmitter NL or no action X STOP condition will STO flag will be reset or no action 1 1 X STOP condition followed by a START condition will be transmitted STO flag will be reset Read data byte Data byte will be received not ACK will be returned or read data byte Data byte will be received ACK will be returned STATUS Register Master Receiver Mode DATA Register CTRL SENS Bits Action STA STO 5 Next Action Taken by Core Load SLA R E SLA R will be transmitted ACK will be received Load SLA R X SLA R will be transmitted ACK will be received or Load SLA W X X SLA W will be transmitted F2DSS 2 will be switched to MST TRX mode No action X The bus will be released 22055 2 will enter slave mode or no action 1 X A start condition will be transmitted when the bus becomes free No action Data byte will be received not ACK will be returned or no action Data byte will be received ACK will be returned No action X Repeated START condition will transmitted be transmitted SLA W Master sends slave address then writes data to slave SLA R Master sends slave address then reads data from slave Revision 1 259 ___________________ Inter Integrated Circuit Peripherals Table 14 7 STATUS Register Master Receiver Mode conti
67. 1 eSRAM 0 eNVM fabric Virtual View System Memory Map with 64 Kbytes of SRAM Revision 1 0xE0043000 OxFFFF2FFF 0 0042000 0xE0042FFF 0x78000000 0xE0041FFF 0x74000000 0x77FFFFFF 0x70000000 0x73FFFFFF 0x60088000 0x600881FF 0x60084000 0x60087FFF 0x60080000 0x60083FFF 0x60000000 0x6007FFFF 0x44000000 Ox5FFFFFFF 0x42000000 0x43FFFFFF 0x40100000 Ox41FFFFFF 0x40050000 0x400FFFFF 0x40040000 0x4004FFFF Actel allowing users the option of storing multiple application images in eNVM and mapping the newest or desired version to address 0x0 in the Cortex M3 code space visible only 0x40030000 0x40030003 to FPGA 0x40020000 0x4002FFFF 0x40017000 0x4001FFFF 0x40016000 0x400 16FFF 0x40015000 0x40015FFF 0x40013000 0x40013FFF 0x40012000 0x40012FFF 0x40011000 0x40011FFF 0x40007000 0x40007FFF 0x40006000 0x40006FFF 0x40005000 0x40005FFF 0x40004000 0x40004FFF 0x40003000 0x40003FFF 0x40002000 0x40002FFF 0x40001000 0x40001FFF 0x40000000 0x40000FFF 0x24000000 Ox3FFFFFFF 0x22000000 0x23FFFFFF 0x20010000 Ox21FFFFFF 0x20008000 0x2000FFFF 0x20000000 0x20007FFF 0x000881FF Visible only to Fabric Master FPGA Fabric Master 0x00000000 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Remapping Embedded SRAMs The AHB bus matrix supports the ability of remapping t
68. 1 024 bit eFROM The eFROM has a 7 bit address and 8 bit data port The upper 3 bits of the 7 bit address define the page number to be read and the 4 lower bits of the 7 bit address specify the byte number to be read The eFROM can be programmed externally via the JTAG port It cannot be programmed directly from the MSS or FPGA fabric during normal operation Each of the eight 128 bit pages of the eFROM can be selectively programmed The eFROM can only be reprogrammed on a page boundary Programming involves an automatic on chip page erase prior to reprogramming the page The eFROM supports synchronous reading The eFROM can be read on byte boundaries To enable user access to the eFROM during normal operation the eFROM is visible to the MSS as an APB peripheral component which is mapped to the ARM Cortex M3 memory space The eFROM APB Interface and Configuration Registers are presented later in this section Byte Number in Bank 4 LSB of ADDR READ 15 LEER 6 m o ta O ma x 35 tc E lt Figure 5 1 Graphical Representation of eFROM Architecture Table 5 1 on page 74 summarizes the various eFROM read and write capabilities sorted by access mode The eFROM content is typically entered in Actel Libero9 Integrated Design Environment IDE software by using the graphical configuration interface within the SmartFusion MSS configurator Refer to the Libero IDE Online Help fo
69. 1 1 0 1 0 128 MBytes 1 1 0 1 1 Reserved 1 1 1 0 0 Reserved 1 1 1 0 1 Reserved 1 1 1 1 0 2 GBytes 1 1 1 1 1 Reserved Revision 1 29 AHB Bus Matrix Actel FPGA Fabric Protect Base Register Table 2 11 FAB_PROT_BASE_CR Bit Reset Number Name R W Value Description 31 N COM_PROTREGIONBASE R W 0 Bits 31 N of this bus indicate the absolute base address of the protected segment The value of N depends on the protected region size so that the base address is aligned according to an even multiple of segment size The power of 2 size specified by PROTREGIONSIZE defines how many bits of base address are used See examples below 0 PROTREGIONENABLE RAV 0 0 Protection region disabled A fabric master can access any location in the memory map as long as the fabric master port is enabled in the AHB bus matrix 1 Protection region enabled Any access by a fabric master to this region of memory returns an error in the bus transaction The COM ERRORSTATUS field of the MSS SR register is updated appropriately ERROR signal is also asserted and a trap can be made if IRQ24 is enabled in the NVIC For example if the COM PROTREGIONSIZE is OxOF this corresponds to a segment size of 64 Kbytes which is 216 Therefore the value of N in this case is 16 So the base address of the region in this case is specified by COM PROTREGIONBASE 31 16 Likewise
70. 1 291 VActel Universal Asynchronous Receiver Transmitter UART Peripherals 292 Example MSS UART init amp g mss uart0 Instantiating UART 0 55 57600 BAUD MSS UART DATA 8 BITS MSS UART NO PARITY MSS UART ONE STOP BIT Transmission and reception of serial data using MSS UART can be done in either polled method or interrupt driven method Applications in which transmit or receipt of serial data is a primary function can typically use the polled method In contrast applications in which the Cortex M3 performs various tasks will benefit from using the interrupt driven method This prevents the processor from idling cycles polling for transmit ready or received serial data Polled Transmission Method The function MSS UART polled tx is used for polled transmission This function returns when the full content of the transmit data buffer defined as one of the arguments has been transferred to the UART s transmit FIFO The following example shows usage of this function Example MSS UART polled tx UART in polled mode amp g mss uartO0 UART instance being addressed greeting msg pointer to transmit data buffer sizeof greeting msg size of the data to be transmitted Interrupt Driven Transmission Method The function MSS UART irq tx is used for interrupt driven transmission This function returns immediately after transmit data buffer location address is stored and transmit interrupts ar
71. 1 Register MATCHREG1 REG a o Bit Number Reset Value Description Match bits 15 8 2 z MATCH 15 8 Match Register 2 Register Table 16 10 MATCHREG2 REG Bit Number 2 Reset Value Description 0x000000 Match bits 23 16 MATCH 23 16 Match Register 3 Register Table 16 11 MATCHREG3 REG Bit Number Reset Value 0x000000 2 Description MATCH 31 24 Match bits 31 24 22 Revision 1 29 ___________________ _ _____ _ Acte Real Time Counter RTC System Match Register 4 Register Table 16 12 MATCHREG4 REG Individual Match Bits 0 Register Table 16 13 MATCHBITSO REG Individual Match Bits 1 Register Table 16 14 MATCHBITS1 REG ___ Ww ___ ResetValue Description Individual Match Bits 2 Register Table 16 15 MATCHBITS2 REG Name ___ RW Reset Value Description Individual Match Bits 3 Register Table 16 16 MATCHBITS3 REG BtNumber Name WW Resetvalue Description Individual Match Bits 4 Register Table 16 17 MATCHBITS4_REG 300 Revision 1 Actel POWER MATTERS 17 System Timer Introduction The System Timer consists of two programmable 32 bit decrementing counters that generate interrupts to the ARM Cortex M3 and FPGA fabric Each counter has two possible modes of operation Periodic mode or One Shot mode The two timers can be concatenated to create a 64
72. 1 is clear then this bit is asserted 1 If CH COMP B for channel 0 is set and if BUF B SEL for channel 0 is clear then this bit is asserted 1 If CH COMP A for channel 0 is set and if BUF A SEL for channel 0 is clear then this bit is asserted 1 42 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide CHANNEL_x_CONTROL Register Table 3 5 CHANNEL x CONTROL Bit Reset Number Value 31 27 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 26 23 PERIPHERAL SEL Selects the peripheral assigned to this channel See Table 3 6 on page 44 21 14 WRITE ADJ This field contains a binary value indicating the number of FCLK periods which the PDMA must wait after completion of 13 12 DSTADDRINC a read or write access to a peripheral before evaluating the out of band status signals from that peripheral for another SRCADDRINC PRIORITY transfer CLR COMP B CLR COMP A INTEN RESET PAUSE TRANSFER SIZE PERIPHERAL DMA This field controls the destination address increment for the DMA transfer The values have the following meanings 0 2 0 byte 1 1 byte 2 2 bytes 3 A bytes This field controls the source address increment for the DMA transfer The values have the following meanings 0 0 byte 121 byte 2 2 bytes 3 4
73. 342 FIIC 351 functional description 352 FIIC_MR 363 FREQ 268 G general purpose block GPIO 315 glitchless MUX 116 switching 117 GLITCHREG 268 GPIN source selection from IOMUXes 320 GPIN_SOURCE_CR 319 GPIO 315 application development 337 functional description 316 IOMUX and I O buffer 315 IOMUXes 321 GPIO register map 317 GPIO x CFG 317 2 peripherals block diagram 249 clocks 252 fabric interface signals 254 features 249 interrupts 253 IOMUXes 268 register map 255 resets 252 transfer example 250 bus 8 IER UART 277 IIR UART 278 in application programming 374 in system programming 373 INT CLEAR 236 Interrupt 351 interrupt driven receive 293 interrupt drvien transmission 292 interrupts eNVM 62 2 peripherals 253 NVIC input pins 10 PDMA 38 SmartFusion interrupt sources 10 system timer 304 UART 274 VR and PSM 155 watchdog 166 IOMUX 341 association to peripherals 367 block diagram 364 register map 345 IOMUX n CR 366 IOMUXes Ethernet MAC 215 GPIO 321 2 peripherals 268 SPI controller 238 UART 284 ISR registering 293 ITM 8 J JTAG pin descriptions 373 JTAG programming hardware 373 L LCR UART 280 low power 32 KHz crystal oscillator 123 LSR UART 282 M MAC address 187 300 main crystal oscillator 121 master interface fabric 349 master interface for MSS 347 MCR UART 281 MICROWIRE protocol 228 MIS 238 misaligned access 88 misaligned addresses 80 miscella
74. 6 Combination Definitions for ENVM PIP BYPASS and ENVM SIX CYCLE Bit 7 Bit 6 eNVM Access FCLK Cycles 0 0 6 2 2 2 when FCLK 80 MHz 0 1 5 1 1 1 when FCLK 80 MHz 1 0 Reserved 1 1 Reserved 26 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide eNVM Remap Base Address Register Table 2 7 e REMAP SYS CR Bit Reset Number Name R W Value Description 31 20 Reserved RAW 0x0000 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 19 1 COM ENVMREMAPBASE R W 0x40000 Offset address of eNVM for remapping COM ENVMREMAPBASE indicates the offset within eNVM address space of the base address of the segment in eNVM which is to be remapped to location 0x00000000 The base address of the remapped segment of eNVM is determined by the value of this bus Bit O of this bus is defined as COM ENVMREMAPENABLE 0 COM ENVMREMAPENABLE RAV 0b1 0 eNVM not enabled Bottom of eNVM is mapped to address 0x00000000 1 eNVM remap enabled eNVM visible at 0x00000000 is a remapped segment of the eNVM Bits 19 N of this bus indicate the base address of the remapped segment The value of N depends on the eNVM remap section size so that the base address is aligned according to an even multiple of segmen
75. 7 sd7 RAV 0 Data context serial data bit 7 MSB Addressing context serial address bit 6 MSB 6 sd6 RAN 0 Data context serial data bit 6 Addressing context serial address bit 5 5 sd5 RAV 0 Data context serial data bit 5 Addressing context serial address bit 4 4 sd4 RAN 0 Data context serial data bit 4 Addressing context serial address bit 3 3 sd3 R W 0 Data context serial data bit 3 Addressing context serial address bit 2 2 sd2 R W 0 Data context serial data bit 2 Addressing context serial address bit 1 1 sd1 R W 0 Data context serial data bit 1 Addressing context serial address bit 0 LSB 0 DIR RAV 0 Data context serial data bit O LSB Addressing context direction bit 0 Write 1 Read ADDR Register Table 14 12 ADDR General call address acknowledge If the gc bit is set the general call address is recognized otherwise it is R W ignored 266 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SMBUS Register Table 14 13 SMBUS Bit Reset Number Name R W Value Description 7 SMBus Reset RAV 0 Writing a one to this bit will force the clock line low until 35 ms has been exceeded thus resetting the entire bus as per the SMBus Specification Version 2 0 Usage When the 12 is used as a host controller master the user can decide to reset the bus by holding the clock line low 35 ms Slaves must react to this event and reset themselves 6 SMBSUS NO Contro
76. CR PSM Block Diagram BG and PSM VCC33GOOD ied BROWNOUT3 3VINT Cortex M3 BGPSMENABLE PSM EN O VCC15GOOD Control BROWNOUT1_SVINT Cortex ABPOWERON Power Down PORESET N SYS REG VCC15 Detect BGGOOD ees VCC33A 33 213V gt 0 8V 50 R FPGAGOOD FPGA Is Programed 100 us delay before PSM is turned on to allow for BG to power up 20 us delay for NVM to power up Figure 10 4 Power Supply Monitor Power Up Sequence 1 No power applied to chip 2 Regardless of which supply comes up first all digital logic will be held in reset state until the VCC detect circuit VCC15UP signal reaches the trip point approximately 0 8 V In the reset state VCC 0 8V a All registers are forced to their default state b The RC Osc begins oscillating c The MSS CCC drives RC Osc 4 into the MSS clock pin FCLK d PORESET N into the MSS is held low 3 Once VCC15GOOD is high from the PSM at around 1 3 V the MSS reset is removed PORESET goes high The MSS will then initiate a read from eNVM at logical address zero The eNVM will hold off response by deasserting HREADY until the eNVM is functional approximately 20 uS The MSS starts executing factory boot code then jumps to the system boot code to continue with low level device initialization Power Down Sequence If VCC33A drops first If VCC33A 3 3 V supply to PSM falls below approximately 2 V
77. Driven Receive Method In interrupt driven receive mode the user must register the RX Interrupt Service Routine ISR also called known as Interrupt Handler Function so that the appropriate function can be called when the UART Receive Data Available RDA interrupt occurs Within the user defined ISR the MSS UART get rx function is called to access received data The following section explains the process Registering ISR receive handler The function MSS UART set rx handler is used to register the user defined ISR function This function also enables the UART Received Data Available RDA interrupt and the corresponding UART interrupt in the Cortex M3 NVIC as part of its implementation The trigger level argument sets the number of bytes that must be received before UART issues the RDA Interrupt The example below shows usage of the handler function Example MSS UART set rx handler amp g mss uartO0 UART Instance being addressed uart0 rx handler Pointer to the user defined receive handler function MSS UART FIFO SINGLE BYTE Trigger level for RDA interrupt firing Example The following example shows a typical user defined ISR function void uart0 rx handler void uint8 t rx buff RX BUFF SIZE uint32 t rx size 0 rx size MSS UART get rx amp g mss uart0 rx buff sizeof rx buff process rx data rx buff rx size User Defined Function The SmartFusion MSS UART application developme
78. ECC Aux eNVM MUX Logic Block 7 Array P 2 Block 1 1 I Block 0 I z Block Buffer WD 31 0 Figure 4 12 Copy Page Data Flow While the copy takes place which could be many cycles BUSY x is asserted You should check the BUSY x status from the eNVM where the operation is occurring before continuing to write to the block buffer Subsequent writes to the same block in the page buffer take no additional BUSY cycles Once the block buffer is loaded you can read from it or write to it at will Care must be taken that sector and page addresses do not change during these read or write operations because that will cause the eNVM controller to fetch the newly addressed page from the eNVM and load the block buffer page buffer with it This could lead to inadvertently programming the wrong page in the eNVM unless page loss protection is enabled Revision 1 55 ___________________ Embedded Nonvolatile Memory eNVM Controller Writes to a different block in the same page will assert BUSY x for four cycles since the current block buffer is synchronized to the page buffer The data flow for this operation is shown in Figure 4 13 Once the page buffer has been updated either a PROGRAM PAGE command or PROGRAM PAGE PROTECTED command can be issued to synchronize the eNVM and the page buffer Page Buffer m 7 T E 1 E 0 Block Buffer WD 31 0 Figure 4 13 Modify Page Data Flow Ou
79. MSS CR Bit Reset Number R W Value Description 31 30 MAINOSCMODE Sets the main RC oscillator mode MAINOSCEN Reserved 27 26 GLMUXCFG 25 24 GLMUXSEL 0 Main crystal oscillator disabled default 1 Main crystal oscillator enabled 2 2 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation With GLMUXSEL configures the glitchless multiplexer See Table 8 21 on page 135 With GLMUXCFG configures the glitchless multiplexer See Table 8 21 on page 135 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 GLC Output of PLL divider w bil 2 BYPASSC R 1 GLC Global MUX C Path 21 19 OCMUX Clock path C output multiplexer See Table 8 22 on page 135 8 DYNCSEL R With RXCSEL and STATCSEL selects the input clock source for clock path C See Table 8 23 on page 136 pos 2 RXCSEL With DYNCSEL and STATCSEL selects the input clock source for clock path C See Table 8 23 on page 136 STATCSEL R With DYNCSEL and RXCSEL selects the input clock source for clock path C See Table 8 23 on page 136 E Software should not rely on the value of a reserved bit To provide compatibility with
80. Mask CMP 10 R EM 1 Enable 0 Mask CMP 9 R 9 1 Enable 0 Mask 8 R 1 Enable 0 Mask 7 a 1 Enable 0 Mask is m ewe ww 9 m 9 _ mene we 10 9 CMP 8 F RW RW RAW esate ome s estate ome s wer Ww a CMP 7 F CMP 6 F Revision 1 355 __________________ Fabric Interface and IOMUX MSSIRQ EN 3 Table 19 11 MSSIRQ EN 3 Reserved R W Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PC2 FLAG 2 20 1 Enable 0 Mask MSSIRQ EN 4 Table 19 12 MSSIRQ EN 4 356 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MSSIRQ EN 5 19 13 MSSIRQ EN 5 9 Reserved ELI should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation MSSIRQ EN 6 Table 19 14 MSSIRQ EN 6 NW 31 6 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility
81. Monitor PSM and Power Modes Table 10 4 CLR MSS SR 31 11 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Writing a 1 to this bit clears the interrupt signal PLLLOCKLOSTINT Writing a zero has no effect 0 No effect 1 Clear the PLLLOCKLOSTINT signal Writing a 1 to this bit clears the interrupt signal PLLLOCKINT Writing a zero has no effect 0 No effect 1 Clear the PLLLOCKINT signal Writing a 1 to any of the bits COM CLEARSTATUS clears the interrupt signal COM ERRORINTERRUPT Writing a zero has no effect Bit 8 Peripheral DMA master Bit 7 Ethernet MAC master Bit 6 Fabric master Bit 5 Cortex M3 system bus master Bit 4 Cortex M3 ICODE DCODE bus master Writing a 1 to this bit clears the interrupt signal BROWNOUTS3 3VINT Writing a zero has no effect 0 No effect 1 Clear the BROWNOUTS 3VINT signal Writing a 1 to this bit clears the interrupt signal BROWNOUT1_5VINT Writing a zero has no effect 0 No effect 1 Clear the BROWNOUT1_5VINT signal Writing a 1 to this bit clears the interrupt signal NT WDOGTIMEOUTEVENT Writing a zero has no effect 0 No effect 1 Clear the WDOGTIMEOUTEVENT signal Writing a 1 to this bit clears the interrupt signal RTCMATCHEVENT Writing a zero has no effect 0 No effect 1 Clear th
82. N I signal from the MSS RESET N pad From this point on any external assertion of MSS RESET also causes MSS RESET O to assert as the pad is open drain it is okay for two sources to be driving MSS RESET N low together The external signal will remain low until both sources stop driving it See Figure 9 3 on page 147 SOFT RESETS Soft resets are described in Table 9 3 on page 148 Note 2 RESET asserted by F2M RESET Care must be taken by the user NOT to connect M2F RESET to the reset input of the fabric master which the user s design asserts F2M RESET N to reset the MSS Revision 1 145 _________________________ _ Acte Reset Controller MSS RESET N I Pad MSS RESET N O MSS RESET ENB Figure 9 2 e MSS RESET Output Buffer Configuration Reset Controller State Machine The reset controller state machine Figure 9 3 on page 147 guarantees that the resets it issues are asserted for eight FCLK periods The reset which asynchronously resets this state machine is called ASYNCRESETMAIN which is generated if any of the following reset conditions occur PORESET N asserted e MSS RESET REQ asserted by firmware LOCKUP asserted by Cortex M3 e F2M RESET asserted from FPGA fabric provided F2MRESETENABLE is asserted in SOFT RST CR WDOG TIMEOUT asserted The state machine ensures that the MSS RESET N pad may be dual purpose driven out by the MSS and driven into the MSS
83. RTC It consists of an inverting amplifier an external ceramic or quartz resonator and two load capacitors The generated clock is also connected to the microcontroller subsystem clock conditioning circuit MSS CCC so that this clock can be used by the FPGA fabric This clock may also be used by the MSS This oscillator is enabled disabled by the XTAL EN bit bit 0 of the RTC s control status register CTRL STAT REG Revision 1 295 ________________________ Real Time Counter RTC System Battery Switching Circuit Functional Description SmartFusion devices have an input for an external battery source that allows both the RTC and the low power crystal oscillator to function when the 3 3 V VCC supply has been removed This VDDBAT pin is intended to be connected to 3 0 V lithium cells and should not exceed 3 5 V This pin may be used with higher voltage cells such as 3 7 V lithium ion provided a suitable method such as a diode is used to keep the VDDBAT at or below 3 5 V The battery switching circuit continuously compares the battery voltage with the voltage on the VCCLPXTAL pin This circuit will automatically power the RTC and the low power crystal oscillator from the battery whenever the battery voltage is approximately 0 4 V or more above the VCCLPXTAL pin voltage The combined load on the battery switching circuit RTC and low power crystal oscillator is expected to be less than 10 pA The comparator hysteresis
84. SPI X DO SPI X OEN 1 1 1 Atto 16 bits 177 Output Data Figure 13 8 National Semiconductor MICROWIRE Multiple Frame Transfer The slave select signal SPI_x_SS is continuously asserted held Low while SPI_x_OEN is also asserted Low for the duration of each control byte The other data transfers proceed in back to back manner Texas Instruments TI Synchronous Serial Protocol The TI synchronous serial interface is based on a full duplex four wire synchronous transfer protocol The transmit data pin is put in a high impedance mode tristated when not transmitting e The slave select SPI_x_SS signal is pulsed between transfers to guarantee a High to Low transition between each frame e In an idle state the slave select SPI x SS signal is kept Low Data is available on the clock cycle immediately following the slave select SPI x SS assertion Both the SPI master and the SPI slave capture each data bit into their serial shift registers on the falling edge of the clock SPI x CLK The received data is latched on the rising edge of the clock SPI x CLK Theoutput enable signal SPI x OEN is asserted active Low throughout the transfer Single Frame Transfer SPI X CLK sixss i1 if SPLX DO i58 3 3 SPLXDI 41016 Bits SPI OEN Figure 13 9 Synchronous Serial Single Frame Transfer Revision 1 229 Oo
85. Sectors Byte 0 Byte 1 Byte 2 Byte 3 Byte 14 Byte 15 Byte 0 Byte 1 Byte 2 Byte 3 Figure 4 3 eNVM Organization From the programmer s perspective as depicted in the memory map in Table 4 1 on page 50 the eNVMs are logically split into four address spaces the eNVM array eNVM spare pages eNVM Auxiliary Aux block array and eNVM Aux block spare pages The spare page 63 of the eNVM is not available to the user and always reads 0 The spare pages in sectors 0 16 in the eNVM are used to store factory boot code and manufacturing parameters These pages are write protected For SmartFusion devices with two eNVM blocks A2F500 the spare page in sector 63 of the additional Revision 1 49 ________________________ _ Acte Embedded Nonvolatile Memory eNVM Controller eNVM is also unavailable to the user however the spare pages in sectors 0 16 of the additional eNVM are writable Table 4 2 lists the contents of a portion of the spare pages Table 4 1 Physical Memory Memory maporconeema DNA Memory of Cortex M3 Ethernet MAC Peripheral DMA Address Range E LLL BEBO ROI 8880100 DW 222 reme corr 2212 77 ersten wr Table 4 2 Spare Page Contents Size bytes Size spare page
86. TXD and UART x 284 IOMUXes for Modem Control Signals 2 4 284 SmartFusion MSS UART Application 291 Real Time Counter WEE 295 Low Power Crystal Oscillator Functional Description 1 295 Battery Switching Circuit Functional Description 296 RTC Functional Description tas aec Exe FREE WEE e 296 Real Time Counter Register Interface Summary 297 System eee ama 301 MEE 301 Periodic 302 One Shot Mode iios Im A RESI REA a A Ge ee i deep ee RE Edd RR EO RE 303 64 Bit Mode x ecient ead 303 System Dependencies 1 1 1 303 Revision 1 Table of Contents System Timer Register Map 14 4 4 305 SmartFusion MSS Timer Application Development 312 18 General Purpose Block 315
87. Typical current consumption in this mode is 10 When VCC33A and the VCCIO supplies are again turned on to the SmartFusion device the device will wake up on an RTC MATCH or assertion of PU N This mode can be used to keep track of elapsed time in the event of a power outage or in portable devices when users swap out the main battery Power Down Mode In this mode the SmartFusion device is powered down Asserting the pin logic 0 will turn on the voltage regulator the device will begin the transition to SoC mode In power down mode VCC33A has to be supplied to the SmartFusion device to allow assertion of to enable the voltage regulator In this mode the digital I O supply is OFF Returning to SoC or Standby mode requires that the power to the digital I Os is restored SOC Standby Power On Reset RTC_MATCH MSSVRON or or PU_N FPGAVRON PUPO 0 MSSVRON or FPGAVRON All Rails Removed Except VBAT Power Reapplied Legend Time Keeping Power Domains 1 Assumes internal regulator is used 2 VBAT is connected to a 3 3 V rail no battery is used 3 If RTC_MATCH is used Rails Figure 10 5 Power State Diagram 156 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Control and Status Registers Table 10 2 through Table 10 6 on page 162 list the various control and status registers associated with the VR and PSM Table 10 2 VR and PSM Control Regist
88. and IOMUX Fabric Master APB Interface The fabric master APB interface allows a user instantiated APB v3 0 compliant master in the FPGA fabric to communicate with AHB slaves in the MSS as shown in Figure 19 8 on page 351 The fabric master APB interface passes all incoming APB transactions that are transfer size aligned to the MSS all transactions are passed with no error checking performed The fabric master APB interface provides for a 32 bit address and a 32 bit or 16 bit read write data bus into the MSS Data bus width is dependent on FAB APB32 and FAB AHBIF bit settings as described in Table 19 3 on page 346 When the data width of the fabric master APB interface is set to 16 bits a register named APB16 XHOLD will be used to hold the upper half word of the 32 bit AHB transactions to from the AHB bus matrix transfers initiated by a fabric master result in 32 bit AHB transactions on the MSS side of the FIC The APB16 XHOLD register is located at address 0x40030000 and is accessible only by a fabric master When issuing a write from a 16 bit APB fabric master the master must first ensure that the APB16 XHOLD register is loaded with a valid upper half word before writing the lower half word to the actual word aligned address which is the destination of the write When issuing a read from a 16 bit APB fabric master the master should read from the word aligned address which is the source of the read The lower half word will
89. and Interrupt Mitigation Control Register CSR11 Bits 31 24 CS TT NTP Bits 23 16 RT NRP CON Bits 15 8 TIM 15 8 Bits 7 0 TIM 7 0 Table 12 41 CSR11 mi Wee Ww Rm 31 CS RAV 061 Cycle size Controls the time units for the transmit and receive timers according to the following 1 RMII 100 Mbps mode 5 12 us 10 Mbps mode 51 2 us 0 100 Mbps mode 81 92 us RMII 10 Mbps mode 819 2 us 30 27 TT RAV 0b1111 Transmit timer Controls the maximum time that must elapse between the end of a transmit operation and the setting of the CSR5 0 Tl transmit interrupt bit This time is equal to TT x 16 x CS The transmit timer is enabled when written with a nonzero value After each frame transmission the timer starts to count down if it has not already started It is reloaded after every transmitted frame Writing O to this field disables the timer effect on the transmit interrupt mitigation mechanism Reading this field gives the actual count value of the timer 26 24 NTP RAV 0b111 Number of transmit packets Controls the maximum number of frames transmitted before setting the CSR5 0 Tl transmit interrupt bit The transmit counter is enabled when written with a nonzero value It is decremented after every transmitted frame It is reloaded after setting the CSR5 0 TI bit Writing O to this field disables the counter effect on the transmit interrupt mitigation mechanism Read
90. be preserved across a read modify write operation 2 LOCK RAV 0 Disabled 1 eNVM disabled from JTAG access The LOCK bit gives you control over access to the eNVM from the JTAG interface When LOCK is asserted the JTAG interface will be prevented from any access attempts to the eNVM until LOCK is deasserted For example if a fabric master has access to the eNVM and does not want a JTAG operation to command or control the eNVM the fabric master should set the LOCK bit Likewise if you only allow eNVM access via the Cortex M3 and want to prevent the JTAG interface from accessing the eNVM you should set the LOCK bit PAGE LOSS RAW 0 Disabled 1 Page loss protection enabled READ NEXT RAV 0 Disabled 1 Read next command enabled Revision 1 69 VActel Embedded Nonvolatile Memory eNVM Controller 70 ENVM 0 Page Status Register Table 4 17 ENVM PAGE STATUS 0 REG Bit m mS CUu 31 8 WRITE COUNT write count the number of times the has been written to Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation OVER THRESHOLD 0 Page is under threshold 1 Page is over threshold READ PROTECTED 0 Page can be read 1 Page is user pass key read protected JTAG read protect bit for page This bit indicates that the page has been
91. be read by the fabric master APB interface during this transfer and the upper half word will be stored in the APB16 XHOLD register The fabric master APB interface can then subsequently read the upper half word from the APB16 XHOLD register in a following transfer if required To aid debugging the Cortex M3 processor can observe the value stored in the APB16 XHOLD register via the HIWORD DR system register located at address 0xE0042070 as shown in Table 19 1 on 345 and Table 19 5 HIWORD DR contains the state of the APB16 XHOLD register It is read only from the Cortex M3 The contents of this register depends on whether the last operation from the fabric master APB interface was a read or a write If it was a read this register contains the upper 16 bits of the read data If it was a write this register contains the upper 16 bits of the write data Table 19 5 FAB APB HIWORD DR Bit Reset Number R W Value 31 16 Reserved R W Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 APB16 XHOLD R W This signal contains the state of the APB16 holding register within the fabric interface block It is read only from the Cortex M3 The contents of this register depend on whether the last operation from the APB fabric master was a read or a write If it was a read
92. code to obtain access to the GPIO functions as shown below Example include mss_gpio h Using the GPIO driver functions involves four distinct stages initialization configuration reading and setting GPIO state and Interrupt control Initializing GPIOs The MSS GPIO driver is initialized through a call to the function MSS_GPIO_init This function must be called before any other GPIO driver functions can be called Example MSS_GPIO_init Revision 1 337 VActel General Purpose Block GPIO 338 Configuring GPIOs Each GPIO port is individually configured through a call to the MSS GPIO config function This function sets the direction of the I O as input output or inout Example MSS GPIO config MSS GPIO 25 MSS GPIO OUTPUT MODE If the GPIO is configured as input then the associated interrupt can also be configured as either level or edge sensitive For level sensitive the option is to be high or low For edge it is either rising or falling or both Example MSS GPIO config MSS GPIO 16 MSS GPIO INPUT MODE MSS GPIO IRQ LEVEL LOW Example MSS GPIO config MSS GPIO 22 MSS GPIO INPUT MODE MSS GPIO IRQ EDGE NEGATIVE Reading GPIO State The state of the GPIO ports configured as inputs or outputs can be read using the functions MSS GPIO get inputs and MSS GPIO get outputs Example uint32 t gpio inputs gpio inputs MSS GPIO get inputs Note The ability to read the current
93. continued Bit Vp TU T peret m Reserved R 0 _ Read as 0 Writes have no effect ILLEGAL CMD 0 RAV 0 Interrupt disabled 1 Enable interrupts when an illegal command has been issued Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 OP DONE 0 RAV 0 Interrupt disabled 1 Enable interrupts when ENVM 0 completes an operation ECC2 ERROR 0 RAV Interrupt disabled 1 Interrupt enabled for _0 ECC2 errors ECC1_ERROR_O RAV Interrupt disabled 1 Interrupt enabled for _0 ECC1 errors OVER THRESH 0 RAV 0 Interrupt disabled 1 Interrupt enabled for ENVM O0 over threshold errors ERASE ERROR 0 RAV Interrupt disabled 1 Interrupt enabled for _0 erasing errors PROG ERROR 0 RAV 0 Interrupt disabled 1 Interrupt enabled for ENVM 0 programming errors PROT ERROR 0 RAV 0 Interrupt disabled 1 Interrupt enabled for 0 protection errors Reserved Read as 0 Writes have no effect Revision 1 67 Acte Embedded Nonvolatile Memory eNVM Controller ENVM O0 Configuration Register Table 4 15 ENVM 0 CR Bit Mme _ nem 31 3 Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bi
94. counter timer CSR11 26 24 NTP CSR1 1 30 27 TT The user can clear this bit by writing a 1 Writing a 0 has effect 204 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Operation Mode Register CSR6 Table 12 30 Operation Mode T CSR6 Note The CSR6 register has unimplemented bits shaded If these bits are read they will return a predefined value as shown in Table 12 31 Writing to these bits has no effect Table 12 31 CSR6 31 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 30 RA Receive all When set all incoming frames are received regardless of their destination address An address check is performed and the result of the check is written into the receive descriptor RDESO 30 0b1100100 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Transmit threshold mode 1 Transmit FIFO threshold set for 100 Mbps mode 0 Transmit FIFO threshold set for 10 Mbps mode This bit is also used to select the frequency of both transmit and receive clocks between 2 5 MHz 10 Mbps operation and 25 MHz 100 Mbps operation This bit can be changed only when a transmit process is
95. fabric It is likely that the most common use model will be one where the Watchdog is serviced by the Cortex M3 Watchdog Block Diagram Figure 11 1 shows the block diagram for the Watchdog timer WDOGLOAD WDOGSTATUS WDOGVALUE WDOGENABLE WDOGREFRESH 32 Bit Down Counter WDOGMVRP WDOGCONTROL RCOSCCLK gt SLEEPING HALTED 9 PROGRAMMING RCOSCRESETN WDOGTIMEOUT WDOGTIMEOUTINT WDOGWAKEUPINT WDOGRIS WDOGMIS APB Bus Figure 11 1 Watchdog Block Diagram Functional Description The operation of the Watchdog is based on a 32 bit down counter that must be refreshed at regular intervals by the Cortex M3 or by a fabric based processor If the counter is not refreshed it will timeout and either cause a system reset or generate an interrupt to the processor depending on the value of a control bit In normal operation the generation of a reset or timeout interrupt by the Watchdog does not occur because the Watchdog counter is refreshed on a regular basis The 32 bit counter in the Watchdog is clocked with the 100 MHz RC oscillator output On power up of the device the Watchdog is enabled with the timeout period set to approximately 5 37 seconds Revision 1 163 _____________________ Watchdog Timer The Watchdog has an APB interface through which the processor can access various control and status registers to control and monitor the
96. for this battery switching circuit has hysteresis RTC Functional Description The RTC is 0 slave which provides a counter as well as a MATCH output signal that can be used to interrupt the Cortex M3 and to power up the on chip 1 5 V voltage regulator An on chip 32 KHz oscillator provides the clock source for the RTC Figure 16 2 Real Time Counter Control Status Low Power Crystal Oscillator MatchBits Reg APB 0 Interface Match Reg Counter To Voltage Regulator and Read Hold Reg Cortex M3 Interrupt System Counter Reg Crystal Prescaler RTCCLK Divide by 128 40 Bit Counter Figure 16 2 RTC Block Diagram A 40 bit loadable counter is used as the primary timekeeping element within the RTC This counter can be configured to reset itself when a count value is reached that matches the value set within a 40 bit match register Note that the only exception to this self clearing mechanism occurs when the 40 bit counter is equal to zero since the counter would never increment from zero When the device is first powered up when the 3 3 V supply becomes valid the 40 bit counter and 40 bit match register are cleared to logic 0 and the MATCH output signal is active logic 1 At any time when the 40 bit counter value does not match the value in the 40 bit match register the MATCH output signal will become inactive logic 0 296 Revision 1 VActel Actel SmartFusion Microcontroller Subsy
97. frequency 8 Note BCLK is synchronized to and hence must be PCLKFREQ 2 or less 256 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide STATUS Register Table 14 5 STATUS Bit Reset Number Name Value Description 7 0 STATUS register R OxF8 STATUS register is read only The status values depend on the mode of operation and are listed in Table 14 6 through Table 14 10 on page 265 Whenever there is a change of state INTERRUPT is requested After updating any registers the APB interface control must clear the INTERRUPT by clearing the SI bit of the CTRL register STATUS Register Master Transmitter Mode Table 14 6 STATUS Register Master Transmitter Mode Status DATA Register SIRE NES Bits Code Status Action STA 5 0 s Next Action Taken by Core 0x08 A START condition has Load SLA W ers will be transmitted ACK will been transmitted be received A repeated START Load SLA W SLA W will be transmitted ACK will condition has been be received Load SLA R X X SLA W will be transmitted Core will be switched to MST REC mode SLA W has been Load data byte X Data byte will be transmitted ACK transmitted ACK has will be received b d ornoaction ee a Repeated START will be transmitted START will be transmitted or no action STOP condition will be transmitted STO flag will be reset
98. future products the value of a reserved bit should be preserved across a read modify write operation BYPASSB 13 11 OBMUX 1 DYNBSEL RXBSEL STATBSEL 1 1 1 1 14 0 GLB Output of PLL divider v 1 GLB Global MUX B Path With RXBSEL and STATBSEL selects the input clock source for clock path B See Table 8 25 on page 136 With DYNBSEL and STABSEL configures the input clock source for clock path B See Table 8 25 on page 136 With DYNBSEL and RXBSEL selects the input clock source for clock path B See Table 8 25 on page 136 Revision 1 133 Acte PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators Table 8 19 MSS CR continued Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Clock Path A output multiplexer See Table 8 26 on page 137 DYNASEL RAV With RXASEL and STATASEL selects the input clock source for clock path A See Table 8 27 on page 137 RXASEL RAV With DYNASEL and STATASEL selects the input clock source for clock path A See Table 8 27 on page 137 STATASEL RAV With DYNASEL and RXASEL selects the input clock source for clock path A See Table 8 27 on page 137 MAINOSCMODE Table 8 20 gives bit definitions for MAINOSCMODE BYPASSA R W 0 GLA Output of PLL divider u 1 GLA Global MUX A path EN El
99. ies Ru ef Ww 4 m o Rai 3 5 _ wm we 21 3 wm me ame 3 4 wm m ww 5 Wm mme 3 ue meme __ meme 3 21 4 90 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 7 6 Asynchronous Memory cycle count AHB Transaction FCLK Cycles Access Type EMD Data Bus Width Width E RN Number Accesses ES i m e Ru e 0 4 1 3 Rar mme aed __ Rai woe 3 wm we Wu me eme 3 wm e we Wue mme wie mme 3 Address Phase Data Phase i ADR 2 7 XX TX E y HREADY M Access Time Figure 7 11 Access Time Revision 1 91 External Memory Controller External Memory Device Example S VActel Figure 7 12 gives an overview of how to connect external memories to the EMC While not exhaustive the examples given are intended to provide the user with a sense of what the EMC is capable of Figure 7 12 shows a typical x16 SRAM connected to the EMC of SmartFusion An eight megabyte device is shown The address bus is half word aligned 17 0 EMC AB 18 1 si
100. in a stopped state This TTM bit is sent out of the Ethernet MAC as an output pin and connected to the SPEED port on the RMII to MII interface as an input port Store and forward When set the transmission starts after a full packet is written into the transmit FIFO regardless of the current FIFO threshold level This bit can be changed only when the transmit process is in the stopped state Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Threshold control bits These bits together with TTM SF and PS control the threshold level for the transmit FIFO Revision 1 205 Acte Ethernet MAC Table 12 31 CSR6 continued Start stop transmit command Setting this bit when the transmit process is in a stopped state causes a transition into a running state In the running state Ethernet MAC checks the transmit descriptor at a current descriptor list position If Ethernet MAC owns the descriptor then the data starts to transfer from memory into the internal transmit FIFO If the host owns the descriptor Ethernet MAC enters a suspended state Clearing this bit when the transmit process is in a running or suspended state instructs Ethernet MAC to enter the stopped state Ethernet MAC does not go into the stopped state immediately after clearing the ST bit It will fini
101. into running state When the descriptor is marked as owned by the host the transmit process remains suspended The poll is always performed at the current transmit descriptor list position The time interval between two consecutive polls is shown in Table 12 19 on page 199 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 198 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 18 CSRO continued Programmable burst length Specifies the maximum number of words 32 bit that can be transferred within one DMA transaction This is tied to value 0 and the bursts are limited only by the internal FIFO s threshold levels Note that PBL is valid only for the data buffers Store and forward operation packet size is limited to the transmit buffer size minus a space for an additional DMA burst The DMA burst length is equivalent to 64 bytes If store and forward operations are requested for packet sizes that are greater than this limit the core will enter a lockup situation because it is unable to complete the store part of the store and forward operation The maximum store and forward size is given in EQ 12 1 2 048 4 x 64 1 792 transmit FIFO depth is 2 048 bytes EQ 12 1 Big little endian Selects the byte ordering mode used by the data b
102. latencies are zero the number of phases listed in Table 14 4 represents the minimum number of FCLK cycles required for an EMD access Table 7 8 CRisnew 00000000000 7 8 EMC MUX CR is new Table 7 9 EMC CS x CR was revised to change the EMC CSFEx E _ Revision 1 387 List of Changes VActel Revision 0 continued 388 Table 7 13 Mapping of AHB Transactions to Accesses was revised Values for EMC DB Bits were added for port size 8 and HSIZE Half Values for EMC AB were added for port size 16 and HSIZE Word and the other values in these rows adjusted to their proper position in the table MRW was corrected to RW N in figures where it occurred throughout the document The On Chip RC Oscillator section was revised to state that the RC oscillator is always on Previously this section stated that the on chip RC oscillator could be disabled by setting the RCOSCDISABLE bit in the MSS RCOSC CR Reference to MSS ROCOSC CR was removed The Main Crystal Oscillator section was revised to state that The main crystal oscillator can be enabled and disabled by the Cortex M3 via the MSS CCC MUX CR bit 29 MAINOSCEN The Low Power 32 KHz Crystal Oscillator section was revised to remove 123 reference to MSS RCOSC CR CTRL STAT REG is referenced instead OSC CTRL was removed from Table 8 5 PLL CCC Register and the OSC 124 Control Regis
103. least 64 RCOSCCLK clock cycles are required before the counter times out The purpose of this feature is to prevent a Watchdog reset interrupt from occurring immediately after or during refresh in the case where a very low value has been written to the WDOGLOAD register The Watchdog counter is refreshed by writing the value OXAC15DE42 to the WDOGREFRESH register This causes the counter to be loaded with the value in the WDOGLOAD register An appropriate value must be written to the WDOGLOAD register before writing to the WDOGREFRESH register Forbidden and permitted windows in time regulate when refreshing can occur The size of these windows is controlled by the value programmed in the WDOGMVRP control register When the counter value is greater than the value WDOGMVRP refreshing the Watchdog is forbidden If a refresh is executed in these circumstances the refresh is successful but a reset or interrupt depending on the operation mode selected is also generated This is illustrated in Figure 11 2 on page 165 When the counter value falls below the level programmed in WDOGMVRP refreshing of the Watchdog is permitted The REFRESHSTATUS status bit in the WDOGSTATUS register is set when in the permitted window and cleared when in the forbidden window 164 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide It is possible to avoid having forbidden and permitted windows by ensuring that the value in WDOGMVRP is
104. map when eSRAM is remapped Revision 1 21 Oooo Atea Bus Matrix Memory Map of FPGA Fabric Master Ethernet MAC Peripheral DMA 0xE0043000 OxFFFF2FFF 0xE0042000 OxEO042FFF DE 0x78000000 External Memory Type 1 0x74000000 0x77FFFFFF External Memory 0 0x70000000 0x73FFFFFF 060100000 oxeFFFFFFF ECL oetso000 0x6 01 CFF PJ eot00100 016017 FFF eNVM Controller 0x60100000 0x601000FF 12277777 106008200 0x6 00 FFF eNVM Aux Block spare pages 0x60088000 0x600881FF eNVM Aux Block array 0x60084000 0x60087FFF Memory Map of Cortex M3 eNVM Spare Pages 0x60080000 0x60083FFF eNVM Array 0x60000000 0x6007FFFF EE 0x44000000 Ox5FFFFFFF Peripheral Bit Band Alias Peripherals BB view 0x42000000 Ox43FFFFFF 0x40100000 OxA1FFFFFF FPGA Fabric 0x40050000 0x400FFFFF FPGA Fabric eSRAM Backdoor 0 40040000 0x4004FFFF 222222222222 0 40030004 0x4003FFFF wisibi APB Extension Register 0x40030000 0x40030003 to FPGA Analog Compute Engine _ 0x40020000 0x4002FFFF Fabric Master Pf 940017000 0x4 001 FF IAP Controller 0x40016000 0x40016FFF eFROM 0x40015000 0x40015FFF RTC 0x40014000 0x40014FFF MSS GPIO 0x40013000 0x40013FFF 1201 0x40012000 0x40012FFF SPL 1 0x40011000 0x40011FFF UART 1 0x40010000 0x40010FFF 040008000 04000FFFF Fab
105. master and mirrored slave A mirrored master port in the matrix connects directly to an AHB master it has the same set of signals but the direction of the signals is described relative to the other end of the connection A mirrored slave port in the matrix connects directly to an AHB slave SysReg 4 PPB Cortex M3 Fabric Interface 10 100 MO Controller Ethernet MAC M3 MM3 AHB Bus Matrix MS3 MS4 50 53 eSRAM 0 eSRAM 1 External AHB AHB Memory Controller Controller Controller Controller Peripheral DMA 4 55 Fabric Interface Controller Figure 2 1 AHB Bus Matrix Masters and Slaves Only a subset of the full set of theoretical paths is implemented within the AHB bus matrix Furthermore the and D Code buses of the ARM Cortex MB3 are multiplexed within the AHB bus matrix so they actually constitute one combined master between them Cortex M3 is configured to avoid activating both buses together Revision 1 15 Acte AHB Bus Matrix The connections available in the AHB bus matrix are shown in Table 2 1 Table 2 1 AHB Bus Matrix Connectivity eSRAM 0 eNVM EMC 2 Fabric Slave 0 1 50 52 53 54 55 56 57 Cortex M3 I Code D Code I Code R MO RAW R W D Code D Code M1 Fabric Master R W R W R AW RAV RAN RAV RAV RAV M2 Ethernet MAC RAV RAV R W R W M3 Peripheral DMA R W R W R R W R W R W R W R W M4 No
106. on by the following sources On power up by the PUPO signal which is defined by the MSS configurator By JTAG being active TRSTB 1 signal on the PU N pin Ahigh on RTC MATCH Flip flop Q2 turns on the VR only if the VCC33UP signal is in transition from logic 0 to logic 1 and PUPO has been configured by the MSS configurator to turn on the VR on power up Once the FPGAGOOD signal is established this particular VR enable mechanism is no longer active The VR be powered off under firmware control by the ARM Cortex MB3 using the MSSVRON bit in the VRPSM CR located at address 0xE0042064 or the FPGAVRON signal sourced from the FPGA fabric The FPGAVRON signal from the FPGA fabric is qualified by the FPGAVRONENABLE bit must be equal to 1 in the VRPSM CR In either case a low to high to low transition commands the VR to turn off Note that the RTC MATCH signal must be low in order to turn off the VR VCC33A VCC33A FPGVRON FPGVRONENABLE MSSVRON VREN 0 Off RQ VCC33A n Low Power 5 Triple Inverter VCC33UP Q1 RTC MATCH From RTC VR Logic Block Voltage Regulator Block Power Up Down Y PUFAB_N Toggle Control V To FPGA Switch Figure 10 3 VR Block Diagram Power Supply Monitor PSM The power supply monitor provides reference voltages for the analog to digital converter ADC and the eNVM The PSM also provides separate logic ou
107. on the private peripheral bus of the Cortex M3 Specifically this System Register is SOFT RST CR located at address 0xE0042030 The PDMA SR control bit is encoded in bit location 5 as follows Bit 5 Function 0 PDMA reset released 1 PDMA held in reset reset value In addition to being able to reset the entire PDMA under firmware control each individual channel can be reset by user firmware by setting the RESET bit in the CHx CONTROL REG to 1 Interrupts There is one interrupt DMAINTERRUPT from the PDMA to the NVIC on the Cortex M3 see Table 1 5 on page 10 The DMAINTERRUPT signal is mapped to INTISR 9 or IRQ 9 in the Cortex M3 NVIC controller The interrupt enable bit for DMAINTERRUPT within the NVIC is located at address 100 IRQ 9 corresponds to bit location 9 Users must also enable specific channel interrupts within the PDMA by setting the INTEN bit in the CHx CONTROL REG to 1 Users can determine which buffer of which channel caused the interrupt by reading the BUFFER STATUS 38 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide PDMA Register Map Table 3 2 Memory Reset Register Name Address R W Value Description RATIO HIGH LOW 0x40004000 R W Ratio of high priority transfers versus low priority transfers BUFFER STATUS 0x40004004 Ed Indicates when buffers have drained CHANNEL x CONTROL x 0 0x40004020 RW 0 Channel 0 Control Register CHANNEL
108. one GET PAGE STATUS Command Writing 0x88 to the COMMAND field of the ENVM CONTROL REG retrieves the page status of the page addressed by Page Address and stores the status in the ENVM PAGE STATUS x REG register The status bits remain valid for the page that was just issued until another GET PAGE STATUS command is completed at which time the status bits reflect the state of the newly addressed page NOP Command The NOP command does nothing This command can be used to clear the COMMAND field Programming Errors Program operations that result in an ENVM STATUS x value of 01 do not modify the addressed page For all other values of ENVM STATUS x the addressed page is modified Program errors include the following 1 Attempting to program a page that is write protected ENVM STATUS x 01 2 Attempting to program a page that is not in the page buffer when the page buffer has entered page loss protection mode ENVM STATUS x 01 3 Attempting to perform a program with the OVERWRITE PAGE command when the page addressed has been write protected ENVM STATUS x 01 4 The write count of the page programmed exceeding the write threshold defined in the part specification ENVM STATUS x 11 5 The ECC logic determining that there is an uncorrectable error within the programmed page ENVM STATUS x 10 6 Attempting to program a page that is not in the page buffer when the OVERWRITE PAGE command has been issued and the page t
109. operation of the Watchdog The APB interface is clocked by PCLKO on 0 Watchdog Timeout Reset Interrupt The MODE control bit in WDOGCONTROL is used to determine whether the Watchdog generates a reset or an interrupt if counter timeout occurs The default setting is reset generation on timeout When interrupt generation is selected the WDOGTIMEOUTINT output is asserted on timeout and remains asserted until the interrupt is cleared When reset generation is selected the Watchdog does not directly generate the system reset signal Instead when the counter reaches zero the Watchdog generates a pulse on the WDOGTIMEOUT output and this is routed to the reset controller to cause it to assert the necessary reset signals The pulse on the WDOGTIMEOUT output is generated in the RCOSCCLK domain and has a duration of 16 RCOSCCLK clock cycles When the counter value reaches zero it is reloaded with the value stored in the WDOGLOAD register This will enforce repeated interrupts should the interrupt or pulse not be serviced Loading and Refreshing the Watchdog The WDOGLOAD register is used to store the value which is loaded into the counter each time the Watchdog is refreshed When the WDOGLOAD register is updated the least significant six bits are always set to Ox3F or 64 clock cycles regardless of the value written to it In effect this means there is a lower limit on the value that can be written to the counter After refreshing at
110. partial frame in the RX FIFO is written into memory with a CRC error The frames received after the RX FIFO is full are dropped The next incoming frames are received by MAC when there is enough space in the RX FIFO to accommodate them Receive Controller RC The receive controller implements the 802 3 receive operation From the network side it uses the standard 802 3 RMII interface for an external PHY device The RC block transfers data received from the RMII to the receive data RAM It supports internal address filtering using an internal address RAM It also supports an external address filtering interface Memory Blocks There are two external memory blocks required for the proper operation of Ethernet MAC Receive memory RAM working as receive data memory e Transmit memory RAM working as transmit data memory These 5 be implemented the eSRAM 0 eSRAM 1 external RAMs connected through or FPGA block SRAM Clock and Reset Control Clock Controls As shown in Figure 12 3 on page 176 there are five clock domains in the design including FCLK PCLKO CLKR CLKT and MAC CLK is the external 50 MHz clock and CLKT is the internal 25 MHz Transmit clock CLKT and CLKR are the same frequency Revision 1 175 ________________ Ethernet MAC The TC and BD components operate synchronously with CLKT This is a 2 5 MHz clock for 10 Mbps operation or a 25 MHz clock for 10
111. propagation through the NGMUX If not the NGMUX can propagate those glitches Table 8 3 shows the various clock sources available to the NGMUX Switching from one clock source to another must complete before another clock source is selected In other words the NGMUX must propagate the clock switching before it can switch again The output of the glitchless MUX will be undefined if the glitchless MUX is not allowed to complete the switch Figure 8 8 Glitchless Multiplexer Table 8 3 NGMUX Clock Sources GLMUXCFG PLL CCC GLMUXCFG 1 0 CLKOUT GLMUXSEL 1 0 GLMUXSEL ELEM EE KR Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Glitchless MUX Switching Most users will find it is only necessary to leave GLMUXCFG at 0x03 power up default setting and control the clock source by changing only GLMUXSEL Figure 8 9 through Figure 8 11 on page 119 show the constraints that exist when switching between two clocks Case 1 Both Current Clock and Desired Clock Active When both the current clock and desired clock inputs to the NGMUX are active the switching sequence between the two clock sources from current clock to desired clock is as below An example is shown in Figure 8 9 1 A transition on S initiates the clock source switch 2 GL drives one last complete current clock positive pulse i e one rising edge followed by one falling edge 3 GL
112. read or written The width of the data bus to the EMD s is either 16 bit 8 bit Therefore all AHB accesses must be broken into half word or byte EMD accesses depending on the EMD connected to the EMC The EMC configuration bit EMC PORTSIZEx is used to configure the EMC to the width of the connected EMD The EMC memory space is divided into an upper and lower half Each half can be connected to a separate EMD s Addresses to the EMDs EMC AB are common Access to each memory space half is determined by the assertion of the controls EMC CS 1 0 N where index 1 corresponds to the upper half and index 0 to the lower half Each half of the supports up to 64 MBytes of memory if using all 26 memory address bits Table 7 1 illustrates the starting and ending address for each chip select Table 7 1 External Memory Controller Memory Regions Chip Select Starting Address Ending Address 50 0 70000000 0x73FFFFFF CS1 0x74000000 0x77FFFFFF EMC to EMD Memory Maps Figure 7 7 through Table 7 10 on page 88 show the AHB to EMD memory mapping when various widths of memories are used AHB Address HADDR 31 0 Ox77FFFFFF 0 77 0x77FFFFFB 0x77FFFFF8 EMC DB 15 0 EMC AB 25 0 ol OxO3FFFFFE 0x03FFFFFD OxO3FFFFFC 15 8 7 0 Upper 64M of 64M External 64M External AHB Memory Space Memory Space gt Memory
113. sda and scl input signals are ignored When ENS1 1 the 12 is enabled The START flag When STA 1 the IC checks the status of the serial bus and generates a START condition if the bus is free The STOP flag When STO 1 and the 2 is in a master mode a STOP condition is transmitted to the serial bus The Serial Interrupt flag The SI is set by the I C whenever there is a serviceable change in the STATUS register After the register has been updated the SI bit must be cleared by software Note The SI bit is directly readable via the APB INTERRUPT signal The Assert Acknowledge flag When AA 1 an acknowledge will be returned when The own slave address has been received The general call address has been received while the gc bit in the Address register is set A data byte has been received while the I C is in the master receiver mode data byte has been received while the 12 is the slave receiver mode When AA 0 a not acknowledge will be returned when e data byte has been received while the is the master receiver mode e A data byte has been received while IC is in the slave receiver mode p um ww o ferre eere CRO R W Serial clock rate bit 0 Clock rate is defined as follows CR2CR1CRO SCL Frequency 000 frequency 256 001PCLK frequency 224 010PCLK frequency 192 011PCLK frequency 160 100PCLK frequency 960 101PCLK frequency 120 11 OPCLK frequency 60 111
114. slave interface The Ethernet MAC is an AHB bus master on the AHB bus matrix see the AHB Bus Matrix section on page 15 The built in DMA controller inside the MAC block along with the AHB master interface is used to automatically move data between external RAM and the built in transmit FIFO and receive FIFOs with minimal CPU intervention Linked list management enables the use of various memory allocation schemes Internal RAMs are used as configurable FIFO memory blocks and there are separate memory blocks for transmit and receive processes The host interface uses little endian byte ordering for the address space Ethernet MAC Block Diagram Figure 12 1 shows the Ethernet MAC block diagram Transmit Memory eSRAM 0 eSRAM 1 Fabric RAM EMC RAM TFIFO CLKT TLSM 2 048 Bytes Transmit RMII AHB Master Interface RMII RFIFO RLSM 4 096 bytes CLKR Receive Memory eSRAM_0 eSRAM_1 Fabric RAM EMC RAM MAC_INT APB Control and Status Registers Managment Master Interface Interface Figure 12 1 Ethernet MAC Block Diagram Revision 1 173 _____________________ Ethernet MAC The RMII management interface can be used to control the external PHY device from the host side It allows access to all of the internal PHY registers via a simple two wire interface There are two signals on the RMII management interface the MDC Management Data Clock and the MDIO Management Data
115. state of outputs is useful in control applications where the value driven on output need to be modulated Setting GPIO State The state of GPIO ports configured as outputs or inout can be set using the functions MSS GPIO set output MSS GPIO set outputs and MSS GPIO drive inout The inout port can be driving high or low or can be in high impedance states Example MSS GPIO set output MSS GPIO 26 0 Sets GPIO26 Low Example uint32 t gpio outputs gpio outputs MSS GPIO get outputs Get current output state gpio outputs amp MSS GPIO 2 MSS GPIO 4 MASK Flip states of GPIO2 amp 4 MSS GPIO set outputs outputs Write new value to GPIO Example MSS GPIO drive inout MSS GPIO 7 MSS GPIO HIGH 2 GPIO Generated Interrupt Control For GPIOs that are configured as inputs with interrupts defined functions MSS GPIO enable irq MSS GPIO disable irq and MSS GPIO clear help manage the interrupts Example MSS GPIO enable irq MSS GPIO 8 Would enable the interrupt generation for input GPIO 8 Example MSS GPIO disable irq To disable interrupt generation for the specified GPIO input Example MSS GPIO clear irq The function clears the GPIO interrupt as well as the Cortex M3 interrupt controller Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide The SmartFusion MSS GPIO application development overview provided in this section should ena
116. stays Low until the second rising edge of desired clock occurs At the second desired clock rising edge GL continuously delivers desired clock Current Clock Desired Clock GLMUXSEL CLOCKOUT Figure 8 9 e NGMUX Switching When Both Clocks Active Revision 1 117 Actel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators Case 2 Current Clock Stopped or at Very Low Frequency If the current clock stops or runs at a very low frequency after S transition internal timeout circuitry will be used to complete the transition The sequence of switching between the two clock sources from current clock to desired clock is described and illustrated below Case 2A No Rising Current Clock Edge If the current clock does not have a rising edge before the seventh desired clock rising edge the switching sequence between the two clock sources from current clock to desired clock is as shown in Figure 8 10 At the seventh desired clock rising edge GL will go Low until the ninth desired clock rising edge At the ninth desired clock rising edge GL will continuously deliver the desired clock signal Current Clock Desired Clock GLMUXSEL CLOCKOUT Note Min tw 0 05 ns at 25 C typical conditions Figure 8 10 NGMUX Switching when No Rising Edge on Current Clock During Switching Window Revision 1 VActel Actel SmartFusion Microcontroller S
117. synchronous de assertion of reset after two clock cycles if VCC33UP 1 CNTR EN RAV Counter Enable 1 Enables the counter if the RTC is not in reset It takes 64 RTCCLK positive edges one half of the prescaler division factor after reset is removed and CNTR EN 1 before the counter is incremented 0 A logic 0 in this bit resets the prescaler and therefore suspends incrementing the counter but the counter is not reset Before writing to the counter registers the counter must be disabled 5 VR EN MAT RAV Voltage Regulator Enable on Match 1 Allows the MATCH output port to go to logic 1 when a match occurs between the 40 bit counter and 40 bit match register 0 Forces the MATCH to logic 0 which prevents the RTC from enabling the voltage regulator ms 2 RST CNT OMAT RAV Reset Counter on Match 1 Allows the counter to clear itself when a match occurs In this situation the 40 bit counter clears on the next rising edge of the prescaled clock approximately 4 ms after the match occurs the prescaled clock toggles at a rate of 256 Hz given a 32 768 KHz external crystal 0 Allows the counter to increment indefinitely while still enabling match events to occur RSTB CNT Counter Reset 1 Allows the counter to count 0 Resets the 40 bit counter value to zero XTAL EN Crystal Oscillator Enable This bit enables the low power crystal oscillator 1 If a logic 1 is written to this bit the low power crystal oscil
118. that a late collision was seen collision after 64 bytes following SFD This bit is valid only when RDESO 8 last descriptor is set Frame type When set indicates that the frame has a length field larger than 1 500 Ethernet type frame When cleared indicates an 802 3 type frame This bit is valid only when RDESO 8 last descriptor is set Additionally FT is invalid for runt frames shorter than 14 bytes Report on RMII error When set indicates that an error has been detected by a physical layer chip connected through the RMII interface This bit is valid only when RDESO 8 last descriptor is set Dribbling bit When set indicates that the frame was not byte aligned This bit is valid only when RDESO 8 last descriptor is set CRC error When set indicates that a CRC error has occurred in the received frame This bit is valid only when RDESO 8 last descriptor is set Additionally CE is not valid when the received frame is a runt frame ZERO bit is reset for frames with a legal length Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 4 CONTROL and COUNT RDES1 Bit Functions Receive end of ring When set indicates that this is the last descriptor in the receive descriptor ring Ethernet MAC returns to the first descriptor in the ring as specified by CSR3 start of receive list address Second address chained When set in
119. that the FPGAVRON signal must be enabled by the Cortex M3 by setting the FPGVRONENABLE bit in the VRPSM CR register An RTC match from the real time counter RTC MATCH 1 or the PU N pin 0 will turn on the VR and the transition to SoC mode will begin Note that if a real time counter is used to exit this mode the digital I O supplies must be kept ON during Sleep mode for full operation in SoC or Standby modes When exiting through PU N the I O supplies can be turned off during Sleep mode and power is restored by the same control that triggers PU Having the digital I O supplies turned on during Sleep mode is not a requirement for proper Sleep mode operation If however the user wants to transition to SOC Standby mode from Sleep mode it would be advantageous to have the digital I O supplies enabled during Sleep mode so that when the transition to SOC Standby mode is complete the desired MSS and FPGA I Os are enabled and ready for use This mode allows for a low power mode while keeping track of time which allows automatic or periodic wake up of the SmartFusion device Time Keeping Mode In Time keeping Mode the only supplies to the SmartFusion device that are enabled are the VBAT rails Users can transition to Time Keeping mode from Sleep mode by having all the supplies turned off except for VBAT Typically a lithium ion coin cell is connected to VBAT The RTC in this mode will keep track of time while the lithium coin cell is still charged
120. the Atmel device Figure 13 12 Read Operation Timing For the read operation the data frame size is set to 24 bits and the SPI controller is configured with SPO 0 SPH 0 Upon completion the least significant byte of the received data frame corresponds to the data read Revision 1 231 ________________________ _ Acte Serial Peripheral Interface SPI Controller Devices that Require Data Frame Sizes of More than 32 Bits Serial flash devices such as the Atmel AT25DF321 which support mode 3 SPO 1 and 5 1 require more than 32 bits of frame data in some modes To drive these devices continuous transfers are required from the SPI interface while holding slave select Low continuously which is connected to the chip select of the target device This is accomplished by using the transmit FIFO from the SPI which if it is kept not empty will enforce continuous back to back transfers The slave select will continue to be held Low active in SPI Mode 1 5 0 and SPH 1 and Mode 1 SPO 1 and SPH 1 and not pulsed between data frames For example to send 64 bits to the AT25DF321 8 bit op code 24 bit address 4 data bytes the data frame size TXRXDF SIZE can be set to 32 and the data frame count set to 2 field TXRXDFCOUNT of CONTROL Page Program for Atmel AT25DF321 SPI X SS EE 01234567 8 9 29 30 31 32 33 34 35 36 37 38 39 SPI_X_CLK OPCODE ADDRESS BITS A23 A0 DATA IN BYTE 1 DATA IN BYTEn
121. the BGGOOD signal will go to logic 0 and the eNVM will be reset The MSS will stop operating since any eNVM access will not complete If VCC drops first PORESET N into MSS remains high until VCC15UP goes low when VCC 0 65 V PORESET N goes high based on the VCC15GOOD signal VCC 1 3 V but goes low based on the VCC15UP signal 0 65 V This helps prevent transient supply noise from resetting the MSS If desired an interrupt can be generated to the Cortex M3 when the VCC15GOOD signal falls below 1 3 V This interrupt is called BROWNOUT1_5VINT and is connected to INTISR 1 of the Cortex M3 NVIC 154 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide VR and PSM Interrupts Table 10 1 lists the interrupts associated with the VR and PSM These interrupts must be enabled in the NVIC of the Cortex M3 by setting the appropriate bit to a 1 Table 10 1 VR and PSM Related Interrupts Cortex M3 Interrupt NVIC Address NVIC Bit at Address BROWNOUT1_5VINT INTISR 1 100 1 5 V below threshold BROWNOUT3_3VINT INTISR 2 OxEOO0E 100 2 3 3 V below threshold PU NINT INTISR 4 100 4 PU N pin asserted low SmartFusion Power Modes SmartFusion devices provide various methods to control power consumption For specific power contribution numbers refer to the DC and Switching Characteristics section of the SmartFusion Intelligent Mixed Signal FPGAs datasheet SoC
122. the Cortex M3 This bit is reset to 0 by PORESET N only and is unaffected by MSS SYSTEM RESET N 0 2 Don t care 1 Watchdog has timed out This signal is a sticky version of the MATCH signal from the RTC If a rising edge event is seen on MATCH after synchronization to FCLK domain then this bit is asserted It stays asserted until cleared by CLRRTCMATCHEVENT This signal is used as an interrupt to the Cortex M3 This signal corresponds to IRQ3 in the Cortex M3 NVIC IRQ3 corresponds to bit location 3 in the 32 bit word at address location 0 000 100 Reset value 0 0 Don t care 1 has matched an event Revision 1 33 POCA te AHB Bus Matrix Clear Microcontroller Subsystem Status Register Table 2 14 e CLR MSS SR Bit Reset Number R W Value Description 31 11 Reserved W To provide compatibility with future products the value of a reserved bit should be preserved across a write operation by writing a zero to those bits CLRPLLLOCKLOSTINT Writing a 1 to this bit clears the interrupt signal PLLLOCKLOSTINT Writing a zero has no effect CLRPLLLOCKINT i 0 No effect COM CLEARSTATUS 1 Clear the PLLLOCKLOSTINT signal Writing a 1 to this bit clears the interrupt signal PLLLOCKTINT Writing a zero has no effect 0 No effect 1 Clear the PLLLOCKINT signal Writing a 1 to any of the bits in COM CLEARSTATUS clears the interrupt signal ABM ERROR IRQ Writing a zero has no eff
123. the System Timer is clocked with the PCLKO input With a PCLK frequency of 100 MHz the maximum timeout period is approximately 42 9 seconds in 32 bit mode and 1 8 x 10 seconds in 64 bit mode or 5 845 5 years The 64 bit and 32 bit modes are mutually exclusive Periodic Mode Periodic mode is selected by setting the TIMxMODE bit in the TIMx CTRL register to 0 In Periodic mode the counter continually counts down to zero when enabled On reaching zero an interrupt is generated the counter is reloaded with the value stored in the TIMXLOADVAL REG register The counter then continues to count down towards zero again without waiting for the interrupt to be cleared The interrupt remains asserted until cleared by the processor If the counter reaches zero again without the previous interrupt having been cleared the counter behaves as if it had just timed out reached zero In effect an interrupt has been lost This situation can continue indefinitely as long as the counter is enabled in Periodic mode and interrupts are not being cleared Writing to the TIMxXLOADVAL REG register at any time causes the counter to be immediately loaded with the value written and to continue counting down from the new value if enabled If the TIMxBGLOADVAL REG register is written to the value written is used to overwrite the 302 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide TIMxLOADVAL REG register without affecting th
124. then this register contains the upper 16 bits of the read data If it was a write then this register contains the upper 16 bits of the write data 350 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide All transfers initiated by a fabric APB master other than those addressed to the APB16 XHOLD register result in 32 bit AHB transactions to the AHB bus matrix When addressing locations in the MSS other than the APB16 XHOLD register a fabric APB master must always provide a word aligned address Non word aligned addresses are not supported and result in invalid data transfers APB Master Figure 19 8 Fabric APB Master Fabric Interface Interrupt Controller There are 128 interrupt sources within the microcontroller subsystem MSS There are a finite number of signal resources that exist at the boundary between the MSS and the FPGA fabric The fabric interface interrupt controller manages a subset of the total available MSS interrupts and maps those to a finite number of input ports along the FPGA fabric edge as shown in Figure 19 9 Fabric Interface To FPGA Fabric Interrupt Controller MSS MSSINT 7 0 Interrupt Interrupt Control and Interrupt Generation Status Registers Sources WDINT Figure 19 9 Fabric Interface Interrupt Controller Block Diagram Revision 1 351 __________________________ Acte Fabric Interface and IOMUX FIIC Functional Description The F
125. we ema RR orones wor mn s se UART 1 DSR IOMUX 81 o 9 e esser IN Emp mss fo a omc 290 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 82 Table 15 32 IOMUX 82 Pad IOMUX 82 Ports E Sep p Em ewm ewxms SmartFusion MSS UART Application Development This section provides overview of the design flow to facilitate seamless UART application development using SmartFusion devices Using the MSS UART peripherals does not require any hardware configuration in the MSS configurator Configuration of UART peripherals using Actel UART drivers is required The user application would then use predefined functions in the UART drivers to perform application specific serial transmit and receive tasks User application code can be developed and debugged using any of the three supported embedded software development tools Actel SoftConsole Keil Microcontroller Development Kit MDK uVision 9 and IAR Embedded Workbench Actel provides a set of UART drivers that can be generated from the MSS configurator or from the Actel Firmware Catalog These drivers are common for all three tool flows However the Cortex Microcontroller Software Interface Standard CMSIS access layer is dependent on the tool flow se
126. wo 1 1 1 1 For four access reads l i i i DATA D3 D2 D1 DO CSx csFE 1 i i i i i 12 n F 8 Where BYTE is shown low onl EMC RW N RWPOL 0 i i i IN l 13 EMC BYTE ENx for the active byte lane s will go i low _ _ for inactive byte lanes will RW RWPOL 1 i i y 14 remain high d EMC PAD OE 15 EMC OEx N i i i 16 _ _ WENBEN 0 17 EMC BYTE ENX WENBEN 1 18 EMC WDB 1 1 1 19 RDB X Do MDT X D2 X X 20 i i i i i i i i i i IDD Cyd Latency Cycle 1 EMC WRLATX 2 Data is latched by the EMC at these FCLK edges 1 2 4 Access 2 amp 4 4 Access All Hashed waveforms are for the next AHB access Reads Access Reads Only Reads If it is an EMC access HREADYOUT will be Reads deasserted immediately but the start of the memory access will be delayed until IDD cycles have finished Figure 7 20 Pipelined Synchronous Read Cycle Revision 1 External Memory Controller Asynchronous Write Cycle NS 225 S 2 5 o Row 0 HADDR HSEL EMC HSEL OTHER 2 HTRANS1 HWRITE 5 i HREADYO
127. written to the transmit FIFO This is emptied by transmit logic Similarly reading from the RX data register causes data to be read from the receive FIFO The not empty port of receive FIFO and not full port of transmit FIFO flags of the FIFOs are exposed as SPIRXAVAIL SPI has data to be read and SPITXRFM SPI has more room to send ports These are connected to the PDMA engine to allow for continuous DMA streaming for large SPI transfers and thus helps to free up the ARM Cortex M3 Interrupts can be setup to signal the following The completion of a data frame transfer transmission reception Overflow underrun events when the DMA channel accesses the transmit or receive FIFOs SPI Modes of Transfer SPI controller has two basic modes of transfer It can be controlled by the Cortex M3 or the peripheral DMA PDMA In Cortex M3 mode the transfers are handled by firmware which can poll the status register or respond to interrupts In PDMA mode the transfers are automatically handled by the PDMA engine Cortex M3 Controlled Mode In this mode the size of the data frames size of the single transfer is set in register SPITXRXDFS REG and the number of transfers set in the TXRXDFCOUNT field of the CONTROL register are specified Upon completion of each transfer that is after a specified number of data frames 1 by default are sent an optional interrupt is generated The SPI controller keeps track of the number of data frames so tha
128. 0 MSSHTRANS 1 0 MSSHWRITE MSSHREADY MSSHRESP MSSPSEL MSSPENABLE MSSPWRITE MSSPREADY MSSPSLVERR FABHADDR 31 0 FABHWDATA 31 16 FABHWDATA 15 0 FABHRDATA 31 16 FABHRDATA 15 0 FABHMASTLOCK FABHSIZE 1 0 FABHTRANS 1 0 FABHWRITE FABHHSEL FABHREADY FABHREADYOUT FABHRESP FABPSEL FABPENABLE FABPWRITE FABPREADY FABPSLVERR Actel Actel SmartFusion Microcontroller Subsystem User s Guide Fabric Interface and IOMUX Register Map Table 19 1 gives descriptions for the registers mentioned throughout this document Table 19 1 Fabric Interface and IOMUX Register Map Reset Register Name Address R W Value Description MSSIRQ EN 0 0x40007000 Enables disables interrupt sources for MSSINT O MSSIRQ EN 1 0x40007004 Enables disables interrupt sources for MSSINT 1 MSSIRQ EN 2 0x40007008 0 Enables disables interrupt sources for MSSINT 2 MSSIRQ EN 3 0x4000700C 0 Enables disables interrupt sources for MSSINT 3 MSSIRQ EN 4 0x40007010 0 Enables disables interrupt sources for MSSINT A MSSIRQ EN 5 0x40007014 o Enables disables interrupt sources for MSSINT 5 MSSIRQ EN 6 0x40007018 Enables disables interrupt sources for MSSINT 6 MSSIRQ EN 7 0x4000701C 0 Enables disables interrupt sources for MSSINT 7 MSSIRQ SRC 0 0x40007020 0 Source of interrupt for 551 0 MSSIRQ SRC 1 0x40007024 0 Source of interrupt f
129. 0 040 have a data frame size smaller than 32 bits and can be directly driven from the SPI mode 230 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Write Operation for Atmel 25010 20 40 Devices SPI x SS SPI x DO INSTRUCTION BYTE ADDRESS DATA IN XX N J2X9998X961X9X96 8X0 9TH BIT OF ADDRESS SPI x DI HIGH IMPEDANCE Note This first byte contains the op code that defines the operations to be performed The op code also contains address bit A8 in both the READ and WRITE instructions This is mandated by the Atmel device Figure 13 11 Write Operation Timing The SPI controller selects the devices using the slave select signal The data frame size is set to 24 bits The SPI is configured with 5 0 SPH 0 The first byte is the instruction Bit 5 of the instruction is part of the address the 9th pit as required by the Atmel part Bits 8 15 form a byte address The residual 8 bits correspond to the data to be written Read Operation for Atmel 25010 20 40 Devices SPI X SS 234 5 6 7 8 9 1011 12 13 14 15 16 17 18 19 20 21 22 23 SPI X CLK INSTRUCTION BYTE ADDRESS 5 X X X X X X 9TH BIT OF ADDRESS SPI X DI HIGH IMPEDANCE 2 UO ASASAAAS 2 AL A0 MSB Note This first byte contains the op code that defines the operations to be performed The op code also contains address bit A8 in both the READ and WRITE instructions This is mandated by
130. 0 Mbps operation The RC operates synchronously with CLKR This is a 2 5 MHz clock for 10 Mbps operation or a 25 MHz clock for 100 Mbps operation e TFIFO RFIFO RLSM and DMA components operate synchronously with clock The CSR operates synchronously with the PCLKO clock e TX is generated from the negative edge of For 100 Mbps operation the is divided 2 to generate CLK TX RX For 10 Mbps operation the RMII_CLK is divided by 20 to generate CLK TX RX FCLK CLKDMA PCLK 0 CLKCSR CSR TD CLKT BD MAC CLK Figure 12 3 Ethernet MAC Clocks A minimum frequency of PCLKO is required for proper operation of the transmit receive and general purpose timers The minimum frequency for PCLKO must be at least the CLKT frequency divided by 64 For proper operation of the receive timer the PCLKO frequency must be at least the CLKR frequency divided by 64 Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 for details on PCLKO settings If the clock frequency conditions described above are not met do not use transmit interrupt mitigation control receive interrupt mitigation control or the general purpose timer Appropriate clocks should also be supplied when the hardware reset operation is performed 176 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Reset Control Rese
131. 0x40005048 Control Register in 64 bit mode 64 RIS 0x4000504C Raw interrupt status in 64 bit mode TIM64 MIS 0x40005050 R 0x0 Masked interrupt status in 64 bit mode TIM64_MODE 0x40005054 System Timer dual 32 bit or 64 bit mode Revision 1 305 __________________ System Timer Timer x Value Register Table 17 2 TIMx VAL Bit 31 0 TIMx VAL 0 0 This register holds the current value of the counter for Timer x Reading this register while the System Timer is set to 64 bit mode returns the reset value Timer x Load Value Register Table 17 3 TIMx LOADVAL Bit Reset Number R W Value Description 31 0 TIMx LOADVAL RAV 0x0 This register holds the value to load into the counter for Timer x When this register is written to the value written is immediately loaded into the counter regardless of which mode Timer x is in Periodic or One Shot If Timer x is enabled the counter starts decrementing from this value When operating in Periodic mode the value in this register is used to reload the counter when the counter decrements to zero This register is overwritten with the value in TIMxBGLOADVAL REG when you write to TIMxBGLOADVAL REG In Periodic mode TIMxLOADVAL REG always stores the value which is loaded into the counter Writing or reading this register while the System Timer is set to 64 bit mode has no effect Timer x Background Load Value Register Table 17 4 TIMx BGLOADVAL Bit Reset Nu
132. 1 0 HTRANS 1 HWDATA 31 0 HWRITE HREADY HRDATA 31 0 HREADYOUT HRESP HRESETn EMC CS 0 CR SysReg EMC CS 1 CR Microcontroller External Memory Controller Block EMC HSEL EMC CLK HADDR 26 0 HSIZE 1 0 AB 25 0 HTRANSI 1 HWDATA 31 0 EMC CS 1 0 N HWRITE RW HREADY EMC BYTE EN 1 0 HRDATA 31 0 EMC OEN 1 0 N HREADYOUT PAD OE HRESP EMCWDB 15 0 EMC RDB 15 0 FCLK HRESETn EMC MEMTYPEO 1 0 EMC PORTSIZEO EMC RDLATFIRSTO 3 0 EMC RDLATRESTO 3 0 EMC WRLATO 3 0 EMC IDDO 1 0 EMC PIPERDNO EMC PIPEWRNO EMC RWPOLO EMC WENBENO EMC CSFEO MEMTYPE1 1 0 EMC PORTSIZE1 EMC RDLATFIRST1 3 0 4 RDLATREST1 3 0 WRLAT1 3 0 IDD1 1 0 EMC PIPERDN1 PIPEWRN1 EMC RWPOL1 WENBEN1 SubSystem Figure 7 1 External Memor 82 EMC_CSFE1 Y North and West I Os y Controller Block Diagram Revision 1 SmartFusion Y External Memory Device EMD Sync SRAM Async SRAM NOR FLASH Actel Actel SmartFusion Microcontroller Subsystem User s Guide Functional Description The EMC accepts single AHB transactions for reading and writing to external memory devices EMDs The EMC reformats single AHB transactions into the format required by the external EMD The EMC may use multiple FCLK cycles to complete an EMD a
133. 15 0 N EMC_DB 15 0 EMC RDB 15 0 UU Bock CY7C1327G CLK A 17 0 ADV ADSC ADSP CE1 BWE BWA BWB OE DQ 15 0 GW CE2 CE3 MODE 22 19 0 GS78108AB DQ 7 0 m OOE OCE GS78108AB A 19 0 DQ 7 0 Figure 7 16 Synchronous SRAM 1 x16 EMD and 2 x8 EMDs VSS The circuit of Figure 7 17 shows a synchronous SRAM alongside and sharing the data bus with a NOR flash device This drawing illustrates the connections necessary when the NOR flash device is configured in half word 16 bit mode The user must not perform AHB byte accesses to the NOR flash device in this configuration but can to the SRAM While predictable the results will likely be unsatisfactory SmartFusion EMC_CLK EMC_AB 25 0 External Memory Controller Block I INTE BYTE 1 0 EMC OEN 1 0 N EMC OENO N EMC PAD OE WDB 15 0 DB 15 0 RDB 15 0 1 0 Block Figure 7 17 x16 Synchronous SRAM and x16 Flash 94 Revision 1 7 55 CS1 N 529410320 21 0 DQ 15 0 VDD BYTE EMC_OENO_N From System Reset VActel Actel SmartFusion Microcontroller Subsystem User s Guide External Memory Controller Configuration Table 7 7 lists the control registers used in configu
134. 1INT and TIMER2INT signals The signal is mapped to IRQ20 and the TIMER2INT signal is mapped to IRQ21 the Cortex M3 NVIC controller Both interrupt enable bits within the NVIC are located at address OxE000E100 IRQ20 and IRQ21 correspond to bit locations 20 and 21 respectively You must also enable interrupts in the System Timer by setting the appropriate TIMxINTEN bits in 1 CTRL TIM2 CTRL or TIM64 CTRL registers When the System Timer is in 64 bit mode and the counter counts down to zero TIMER1INT TIMER2INT signals assert Consequently IRQ20 and IRQ21 interrupts are asserted Both interrupt signals are identical in that they both represent the 64 bit timer interrupt In other words TIMER1INT is not the interrupt signal asserted when Timer 1 counts down to zero while in 64 bit mode You must disable one of the interrupts in the NVIC controller or you will get two interrupts for the same event In 32 bit mode you must clear the TIMxRIS bit in the respective interrupt service routine to prevent a reassertion of the interrupt Likewise in 64 bit mode you must clear the TIM64RIS bit in the respective interrupt service routine to prevent a reassertion of the interrupt GPIO There are no requirements to configure a GPIO for the System Timer to operate properly 304 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide System Timer Register Map The System Timer base address resid
135. 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave 264 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 14 9 Status Register Slave Transmitter Mode continued Status DATA Register CTRL SEES bits Code Status Action STA STO s Next Action Taken by Core OxC8 Last data byte has No action to not addressed SLV transmitted ACK has mode no recognition of own SLA or been received general call address or no action Switched to not addressed SLV mode own SLA or general call address will be recognized or no action 1 Switched to not addressed SLV mode no recognition of own SLA or general call address START condition will be transmitted when the bus becomes free or no action 1 1 Switched to not addressed SLV mode own SLA or general call address will be recognized START condition will be transmitted when the bus becomes free 25 ms SCL low time has no action X X X Slave must proceed to reset state by been reached device clearing the interrupt within 10ms must be reset according to SMBus Specification 2 0 Notes 1 SLA Slave address 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave STAT
136. 25 on page 366 lists the bit definitions of these control registers Table 19 25 IOMUX n CR Bit Reset Number R W Value Function IOMUX n ST RAV 0 Schmitt Trigger of IOMUX n is disabled 1 Enabled IOMUX n PD R W 0 Weak pull down of IOMUX n is disabled 1 Enabled 7 IOMUX n PU RAV 0 Weak pull up of IOMUX n is disabled 1 Enabled IOMUX n M3 S MUX MB select 0 IN B IO I 1 IN_B OUT_A IOMUX n 2 S 1 0 o See Table 19 26 21 n 1 S 1 0 See Table 19 27 IOMUX n MO S MUX MO select O IN A IO 1 IN OUT B Table 19 26 IOMUX MUX M2 Configuration og LL EE NNNM NN ECT NN BEEN NN CC NN Table 19 27 IOMUX MUX 1 Configuration 366 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Table 19 28 IOMUX to Peripheral Association 66 mm NE S 8 poe ED NN oU EE ACE Thresholds There are 32 threshold signals ACEFLAGS 31 0 output directly from the ACE post processing engine and one signal FABACETRIG sourced from the FPGA fabric that can be used to trigger the start of the sample sequence engine SSE in the ACE Revision 1 367 ___________________ Fabric Interface and IOMUX SCB Signals Signals coming from and going to the signal conditioning block SCB are described in Table 19 29 Th
137. 2COSMBALERTNO Input Output wired AND interrupt signal used in slave device mode if the I C wants to force communication with host I2COSMBSUSNI Output Input suspend mode signal used if I C is slave device Note Nota wired AND signal I2COSMBALERTNI Output Input wired AND interrupt signal used in master host mode to monitor whether slave devices want to force communication with the host I2COBCLKO Output Pulse for SCL speed control Used only if the configuration bits CR 2 0 111 otherwise various divisions of PCLK are used 2 15 505 Input Output suspend mode signal used if I C is the master host Note Nota wired AND signal I2C1SMBALERTNO Input Output wired AND interrupt signal used in slave device mode if the I C wants to force communication with host I2C1SMBSUSNI Output Input suspend mode signal used if 12 is slave device Note Nota wired AND signal I2C1SMBALERTNI Output Input wired AND interrupt signal used in master host mode to monitor if slave devices want to force communication with the host I2C1BCLK Output Pulse for SCL speed control Used only if the configuration bits cr 2 0 111 otherwise various divisions of PCLK are used 254 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide I2C x Register The 2 0 base address resides at 0x40002000 and extends to address 0x40002FFF the Cortex M3 memory map The I2C 1 base address resides at 0x40012000 and exte
138. 2F 48 in the fabric The M2F 48 signal can then be connected to a FPGAIOBUF using the Libero IDE tool Similar 284 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX arrangements apply to UART 1 RTS UART x UART x CTS UART x DSR UART x RI and UART x DCD as well Table 15 16 shows the associated GPIO IOMUX and fabric interface signals for each UART x signal The MSS configurator tool manages the assignment and allocation of IOMUXes in a graphical user friendly way The output of the MSS configurator is used by the system boot code to initialize the MSS to a known state IOMUX 64 UART 0 UART 0 RTS X Not connected to pad X Not connected to I O pad IN B X Not connected to I O pad FPGAIOBUF X M2F 48 F2M 48 F2M OE 48 FPGA Fabric Figure 15 3 UART 0 RTS Signal IOMUX Topology Table 15 16 UART x Fabric Interface Signal Connections aren B 8 Wmrrma warm 8 Revision 1 285 Acte Universal Asynchronous Receiver Transmitter UART Peripherals Table 15 17 through Table 15 32 on page 291 describe the IOMUXes associated with UART x signals IOMUX 4 Table 15 17 lOMUX 4 DI LL I 1 1 727 pre o qp oun NEN IOMUX 5 Table 15 18 IOMUX 5
139. 3 from the SPI 0 row as they were incorrectly included Revision 1 389 __________________ List of Changes Revision 0 The SYSREG register table was added and duplicate information was continued removed from Table 21 2 SmartFusion Master Register Map The format was changed to include more information about each register Some of the descriptions were updated The PDMA Register names were corrected and the real time counter register 378 map was added in Table 21 2 SmartFusion Master Register Draft B Nomenclature was revised for SmartFusion registers and interrupts December 2009 References to AHB Lite and AHBL were changed to AHB Figure 1 1 e Cortex M3 R1P1 Block Diagram was revised The implementation specifics were also revised The reset values in Table 1 3 5 5 CR were revised 8 Table 1 5 SmartFusion Interrupt Sources was replaced Figure 2 1 AHB Bus Matrix Masters and Slaves and Table 2 1 AHB Bus Matrix Connectivity were revised to change some of the terminology The Functional Description section was revised with terminology changes The Remapping Embedded SRAMs section was revised significantly The System Boot section was revised to include the register address for the system boot code Table 2 2 AHB Bus Matrix Register Map was revised to change addresses 24 from 004 to 000 The location of the AHB bus matrix control registers in t
140. 38 R W 0x32000000 Provides firmware control of the STCALIB 25 0 pins of Cortex M3 Table 1 3 SYSTICK CR sume Restvaie Demum _ 29 28 STCLK DIVISOR 0b11 See Table 1 4 mu NOREF IRW _ 1 1 Reference clock is not provided SKEW RAV 1 The calibration value is not exactly 10 ms because of clock frequency 23 0 5 RAV This value is the Reload value to use for 10 ms timing Depending on the value of SKEW this might be exactly 10 ms or might be the closest value The STCLK_DIVISOR field of SYSTICK CR is used to divide the by 4 8 16 32 Table 1 4 The resultant clock is used to provide the STCLK input to the SysTick Timer of the Cortex M3 The reset state of STCLK DIVISOR is FCLK divided by 32 FCLK must always be greater than or equal to 2 5 x STCLK Table 1 4 STCLK DIVISOR Definition STCLK DIVISOR FCLK Divided By The NOREF SKEW and TENMS fields of the SYSTICK CR are mapped to the STCALIB 25 0 input pins of the Cortex M3 Within the NVIC module of the Cortex M3 you have read access to the STCALIB pins through the SysTick Calibration Value STCVR register located at address 0 000 01 The Revision 1 9 Acte ARM Cortex M3 Microcontroller SYSTICK_CR at address 0xE0042038 can be read and written by user firmware The NOREF SKEW and TENMS fields in SYSTICK_CR map directly to the same fields in the SysTick Calibration V
141. 4 load immediate function takes two 32 bit load values for the upper and lower 32 bit values which comprise the 64 bit down counter start value Once the timer value has been loaded the timer can be started as shown in the example below MSS start In order to generate timer interrupts to the Cortex M3 processor the timer interrupts must be enabled as shown in the example below MSS enable irq Processing a Timer Interrupt Once the timer is initialized loaded with the down counter start value started and interrupts are enabled the Timer will generate a Timer1 Timer2 or Timer64 interrupt In order to process the timer interrupt the corresponding Timer Interrupt Service Routine ISR or Interrupt Handler function must be defined The SmartFusion MSS Timer Interrupt Handler function prototypes have been defined in the SmartFusion CMSIS PAL and thus the user timer interrupt handlers must follow the pre defined function prototypes listed below void Timerl_IRQHandler void void Timer2 IRQHandler void add a Timer1 interrupt handler the Timer1 IRQHandler function must be defined by the user application code Similarly for the Timer2 interrupt handler the Timer2_IRQHandler function must be defined by the user Lastly when using the MSS Timer as a 64 bit timer only the Timer1 IRQHandler function must be defined by the user application code since the Timer2 interrupt is not used when the MSS Ti
142. 40004090 Rw 0 Channel 3 buffer A transfer count CHANNEL 3 BUFFER B SRC ADDR 3 BUFFER B SRC ADDR 0x40004094 RW 0 Channel 3 buffer B source address Channel 3 Channel 3 buffer B source address B source address eee 3 BUFFER B DST ADDR 0x40004098 MEN Channel 3 buffer B destination address CHANNEL BUFFER T TRANSFER COUNT manos ww 3 danserstufert Wander court channel ecm aso ww Channel one Regier ___ Hanne STATUS mann ___ HANNELE BUFERA SRC ADDR nano RW 0 Channel bier Asowree adir CHANNEL 4 BUFFER A DST ADDR 0x400040AC ESI Channel 4 buffer A destination address CHANNEL 4 BUFFER A TRANSFER COUNT 0x400040B0 RW 0 Channel 4 buffer A transfer count CHANNEL 4 BUFFER B SRC ADDR 0 40004084 Rw 0 Channel 4 buffer B source address CHANNEL 4 BUFFER B DST ADDR 0x400040B8 EM Channel 4 buffer B destination address RARE RUE TRANSFER COUNT WW i Chane ue 6 vase coun Dono wa o channels chanel sts easter 5 BUFFER A SRCADDR ____ 5 BUFFER A SRC ADDR 0 400040 8 RW 0 Channel 5 buffer A source address Channel 5 Channel 5 buffer A source address address 5 BUFFER A 057 ADDR 0x400040CC MES Channel 5 buffer A destination address CHANNEL 5 BUFFER A TRANSFER COUNT 0x400040D0 RW 0 Channel 5 buffer A transfer count CHANNEL 5 BUFFER B SRC ADDR 5 BUFFER B SRC ADDR 0x400040D4 RW 0 Chann
143. 64 MODE 311 TIM64 RIS 311 TIM64 VAL 308 TIM64 VAL L 308 Time Keeping mode 156 timer application development 312 block diagram 302 clocks 303 interrupts 304 modes 302 register map 305 reset 304 timer interrupt processing 313 TIMx BGLOADVAL 306 TIMx CTRL 307 TIMx LOADVAL 306 TIMx MIS 308 TIMx RIS 308 TIMx VAL 306 TPIU 8 trace port interface unit 8 TRSTB logic 374 TX DATA 236 U UART application development 291 block diagram 273 functional description 273 interrupts 274 IOMUXes 284 reset 274 UART register map 275 V VCC15UP 151 VCC33UP 152 voltage monitor Actel Index block diagram 151 voltage regulator 1 5 V 152 Voltage Regulator Power Supply Monitor VRPSM 173 VR PSM signals 369 VRPSM_CR 162 W watchdog interrupts 166 watchdog timeout 164 watchdog timer block diagram 163 functional description 163 modes 165 watchdog timer register map 166 WDOGCONTROL 168 WDOGENABLE 168 WDOGLOAD 164 167 WDOGLVALUE 166 WDOGMIS 169 WDOGMVRP 167 WDOGREFRESH 167 WDOGRIS 169 WDOGSTATUS 168 web based technical support 393 399 Actel POWER MATTERS Actel is the leader in low power FPGAs and mixed signal FPGAs and offers the most comprehensive portfolio of system and power management solutions Power Matters Learn more at www actel com Actel Corporation Actel Europe Ltd Actel Japan Actel Hong Kong 2061 Stierlin Court River Court Meadows Business Park 5 Ebisu Buillding 4F Room 2107
144. 77FFFFFB Ox77FFFFF8 RH Ox03FFFFFD OxO3FFFFFC 64M External gt 64 5 5 31 24 23 16 15 8 7 0 Ox77FFFFFF Ox73FFFFFC w EMC CS1 N 0x74000003 0x74000000 15 8 0x00000001 7 0 0x00000000 OxO3FFFFFE OxO3FFFFFD OxO3FFFFFC Lower 64M of 64M External gt 64M External AHB Memory Space Memory Space Memory Space 81 24 23 16 15 8 7 0 0x70000007 0x70000004 EMC CSO_N 31 24 23 16 15 8 7 0 0 70000003 0x70000000 15 8 7 0 0 00000001 0 00000000 Figure 7 10 Halfword and Byte Wide External Memory Device Memory 88 Misaligned Access Behavior All half word accesses are performed on half word boundaries and all word accesses are performed on word boundaries As shown in Table 7 2 and Table 7 3 on page 89 misaligned accesses are automatically aligned to an appropriate boundary In other words for word accesses the EMC ignores the two LSBs of the address bus and for half word accesses the EMC ignores the LSB of the address No error indication is generated during this automatic alignment The misaligned transactions are processed but they are not trapped Users must be aware of this when implementing masters in the FPGA fabric Table 7 2 Misaligned Write Transactions Write Transaction Size A
145. 8 in CHx CONTROL REG for this channel If CHx INTEN is set for this channel then the assertion of CH COMP A causes DMAINTERRUPT to assert 44 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide CHANNEL x BUFFER A SRC ADDR Register Table 3 8 CHANNEL x BUFFER SRC ADDR Bit 31 0 BUF A SRC R W Start address from which data is to be read during the next transfer cycle If PERIPHERAL DMA 1 and DIR 0 then this value is not incremented from one DMA transfer cycle to the next Otherwise it is always incremented by an amount corresponding to the TRANSFER SIZE for this channel CHANNEL x BUFFER A DST ADDR Register Table 3 9 CHANNEL x BUFFER A DST ADDR Bit 31 0 BUF A DST RAV Start address from which data is to be read during the next transfer cycle If PERIPHERAL DMA 1 and DIR 1 then this value is not incremented from one DMA transfer cycle to the next Otherwise it is always incremented by an amount corresponding to the TRANSFER SIZE for this channel CHANNEL x BUFFER A TRANSFER COUNT Register Table 3 10 CHANNEL x BUFFER A TRANSFER COUNT Bit 31 16 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 15 0 BUF A COUNT RAV Number of transfers remaining to be completed between source and destination for buffer
146. A for this channel This field is decremented after every DMA transfer cycle Writing a non zero value to this register causes the DMA to start This must be the last register to be written by firmware when setting up a DMA transfer CHANNEL x BUFFER B SRC ADDR Register Table 3 11 CHANNEL x BUFFER SRC ADDR Bit 31 0 BUF B SRC RAW Start address from which data is to be read during the next transfer cycle If PERIPHERAL DMA 1 and DIR 0 this value is not incremented from one DMA transfer cycle to the next Otherwise it is always incremented by an amount corresponding to the TRANSFER SIZE for this channel Revision 1 45 __________________________ _ Acte CHANNEL x BUFFER B 057 ADDR Register Table 3 12 CHANNEL x BUFFER B DST ADDR Bit 31 0 BUF B DST Start address from which data is to be read during the next transfer cycle If PERIPHERAL DMA 1 and DIR 1 peripheral to memory then this value is not incremented from one DMA transfer cycle to the next Otherwise it is always incremented by an amount corresponding to the TRANSFER SIZE for this channel CHANNEL x BUFFER B TRANSFER COUNT Register Table 3 13 CHANNEL x BUFFER B TRANSFER COUNT Bit 31 16 Reserved RAN Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modif
147. ADCO TVC 0x40020058 Rw ADC 0 time division control MISC 0x4002005C fw ADC 0 control register ADCI1 CONV CTRL 0x40020090 Rw __ ADC 1 conversion control ADC1_STC 0x40020094 Fw ADC 1 sample time control ADC1_TVC 0x40020098 Rw __ ADC 1 time division control ADC1 MISC CTRL 0x4002009C rw ADC 1 control register ADC2 CONV 0x400200D0 rw 2 conversion control ADC2_STC 0x400200D4 Ww ADC 2 sample time control ADC2 TVC 0x400200D8 Rw __ ADC 2 time division control 2 MISC CTRL 0x400200DC Rw 00 ADC 2 control register ADCO STATUS 0x40021000 IR 9 Status of ADC 0 1 STATUS 0x40021004 IR 009 Status of ADC 1 ADC2 STATUS 0x40021008 IR 009 Status of ADC 2 PPE CTRL 0x40021404 RAV Post processing engine control Revision 1 385 VActel POWER MATTERS A List of Changes The following table lists critical changes that were made in each revision of the SmartFusion MSS User s Guide Changes Revision 1 The SmartFusion MSS UART Application Development section is new April 2010 The SmartFusion MSS Timer Application Development section is new 312 The SmartFusion MSS GPIO Application Development section is new References to the SmartFusion MSS Firmware Drivers v2 0 User s Guide and been changed to the website reference for Actel SmartFusion MSS Configurators and Drivers User s Guides Revision 0 The ARM Cortex M3 Microcontroller
148. ADVAL REG will be loaded into the TIMxLOADVAL_REG register as normal but when the counter reaches zero it will generate a single interrupt and stop without making use of the value written to TIMXBGLOADVAL REG Only a subsequent write to the TIMxLOADVAL REG register will initiate another One Shot count down sequence However if the counter is restarted by changing the operating mode to Periodic by clearing the TIMxMODE bit then the value previously written to the TIMxBGLOADVAL REG register is relevant because this will be the start value taken from the TIMxLOADVAL REG register used to initialize the counter in Periodic mode 64 Bit Mode Timers 1 and 2 can be concatenated into a single 64 bit timer that operates either in Periodic mode or One Shot mode Writing a 1 to the TIM64 MODE register bit location 0 sets the timers in 64 bit mode Whenever the TIM64MODE bit changes state the timers are re initialized to their default reset values Timer 1 contains the lower 32 bit count of the 64 bit count value Consequently when updating or initializing the state of the counter the upper 32 bits of the 64 bit counter must be written to first followed by the lower 32 bits You must ensure that when updating the background load value registers TIM64 BGLOAD VAL is followed by a write to TIM64 BGLOAD VAL L and when updating the load value registers TIM64 LOADVAL U is followed by a write to TIM64 LOADVAL L When the lower 32 bit write occurs the 64 bi
149. AG interface The user pass key must be used to change this bit setting Read protection returns all zeros when the page is read change this bit setting OVERWRITE PROTECTED 0 Page can be written to 1 Page is write protected This status bit indicates that the page was programmed or erased using either the PROGRAMMED PAGE PROTECTED or ERASE PAGE PROTECTED command WRITE PROTECTED 0 Page write protect bit is not set 1 Page is user pass key write protected JTAG write protect bit for page This bit indicates that the page has been write protected using the user pass key via the JTAG interface The user pass key must be used to Revision 1 71 Actel POWER MATTERS 5 SmartFusion Embedded FlashROM eFROM SmartFusion devices have 1 024 bits of on chip nonvolatile flash memory called embedded flash read only memory embedded FlashROM or eFROM The eFROM can be read and written via the JTAG interface when performing external device programming This embedded flash read only memory is directly accessible for reading during normal operation from user firmware running on the SmartFusion microcontroller subsystem MSS Architecture of the Embedded FlashROM eFROM eFROM is arranged in eight banks of 128 bits 16 bytes during programming eFROM writing The 16 byte bank is also referred to as a page Figure 5 1 shows a graphical representation of the 16 bytes in each of the 8 banks or pages which make up the
150. AG connectors do not have access to the JTAGSEL pin Actel s free Eclipse based IDE Soft Console automatically sets JTAGSEL via FlashPro4 to the appropriate state for programming all memory regions 1 5V Figure 20 1 TRSTB Logic In Application Programming In application programming refers to the ability to reprogram the various flash areas under direct supervision of the Cortex M3 Reprogramming the FPGA Fabric Using the Cortex M3 In this mode the Cortex M3 is executing the programming algorithm on chip The IAP driver be incorporated into the design project and executed from eNVM or eSRAM Actel provides working example projects for SoftConsole IAR and Keil development environments These can be downloaded via the Actel Firmware Catalog The new bitstream to be programmed into the FPGA can reside on the user s printed circuit board PCB in a separate SPI flash memory Alternately the user can modify the existing projects supplied by Actel and via custom handshaking software throttle the download of the new image and program the FPGA a piece at a time in real time A cost effective and reliable approach would be to store the bitstream in an external SPI flash Another option is storing a redundant bitstream image in an external SPI flash and loading the newest version into the FPGA only when receiving an IAP command Since the FPGA I Os are tristated or held at predefined or last known state during FPGA programming the us
151. AM from the shared RAM Ethernet MAC starts to transmit data on RMII gv Ub BOB ON Revision 1 189 ________________ Ethernet MAC A typical data flow for the transmit process is illustrated in Figure 12 6 Transmit Stopped Start Transmit Command Stop Transmit Command Reset Command Descriptor Unavailable Underflow Error Figure 12 6 Transmit Process Transitions Receive Process The receive process can operate in one of three modes running stopped or suspended After a software or hardware reset or after a stop receive command the receive process is in the stopped state The receive process can leave a stopped state only after a start receive command In the running state the receiver performs descriptor buffer processing In the running state the receiver fetches from the receive descriptor list It performs this fetch regardless of whether there is any frame on the link When there is no frame pending the receive process reads the descriptor and simply waits for the frames When a valid frame is recognized the receive process starts to fill the memory buffers pointed to by the current descriptor When the frame ends or when the memory buffers are completely filled the current frame descriptor is closed ownership bit cleared Immediately the next descriptor on the list is fetched in the same manner and so on When operating in a suspended or stopped state the rece
152. APB interface Actel provides CoreAPB3 to perform these functions The least significant 20 bits of the MSS address bus are passed to the FPGA fabric along with either 16 bit or 32 bit read and write data buses depending on the setting of the FAB AHB32 and FAB AHBIF bits FAB IF In the case where the interfaces to the fabric are configured as 16 bit APB an MSS master can perform byte or half word accesses to 16 bit APB slaves in the fabric These accesses can be performed only on word aligned addresses Byte or half word accesses to 16 bit APB slaves on non word aligned addresses are not supported and result in invalid data transfers Word accesses to 16 bit APB slaves are not supported and result in invalid data transfers In the case where the interfaces to the fabric are configured as 32 bit APB an MSS master can perform byte half word or word accesses to 32 bit APB slaves in the fabric These accesses can be performed only on word aligned addresses Byte half word or word accesses to 32 bit APB slaves on non word aligned addresses are not supported and result in invalid data transfers APB Master APB Decoder and Multiplexer APB Slave 0 Figure 19 6 MSS AHB Master to Slave 348 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Fabric Master Interface The fabric master interface of the FIC allows either an AHB or an APB v3 0 compliant master in the FPGA fabric
153. Actel Actel SmartFusion Microcontroller Subsystem User s Guide Pipelined Synchronous Read Cycle X X FCLK Row 0 HADDR 1 HSEL EMC 2 HSEL OTHER 3 Notes HTRANS1 4 HWRITE 5 1 _ 10 HWDATA 6 2 EMC PIPERDNx is low for pipelined accesses HRDATA 7 3 PIPEWRNXx is ignored for reads HREADYOUT 4 The second address for a 2 access read is 0 2 5 Shaded latency cycle is EMC RDLATFIRSTx 1 FCLK cycles wide An EMC RDLATFIRSTx value of 1 will 9 remove this latency cycle RDLATFIRSTx value of 0 causes address to be presented and to be EMC AB X Ao TXA 2 3X 10 latched on the same FCLK cycle CSx 0 i 11 6 EMC RDLATREST is ignored for pipelined accesses 1 7 For single access reads 1 24 2 amp 4 4 All Reads If HADDR 1 0 00 DATA Access Access Reads Only If HADDR 1 0 01 DATA Reads N N If HADDR 1 0 10 4 If HADDR 1 0 11 DO 1 i T T 7 For two access reads x x x x x x If HADDR 1 0 DATA D1 DO If HADDR 1 0 01 DATA D1 DO N N m in
154. B or by the contents of OBDIV 1 See Table 8 16 on page 131 OBDIV LI OADIVRST 128 Revision 1 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 Don t care 1 Reset the counter used to divide the GLA output frequency The rising edge of this bit will trigger a reset of the GLA output divider This bit is a don t care if the PLL is being used to drive the GLA output Actel Actel SmartFusion Microcontroller Subsystem User s Guide Table 8 12 MSS_CCC_DIV_CR continued 5 OADIVHALF R W 0 OADIV defines the GLA output frequency divider 1 Use Table 8 17 on page 131 to determine GLA output frequency divider These bits divide the output of the global buffer GLA by the contents of OADIV 1 See Table 8 18 on page 132 OADIV OCDIVHALF This bit if set to 1 divides the output frequency of the output divider defined by OCDIV by 0 5 when the PLL is bypassed with the 100 MHz RC or 32 KHz low power oscillator If OCDIVHALF 1 and OCDIV 2 the OCDIV divisor is 3 so 3 2 1 5 If the GLC YC input is sourced from the 100 MHz RC the output of GLC YC will be 100 1 5 66 67 MHz This bit is only valid if the input to the GLC YC divider is not being sourced by the PLL Table 8 13 lists the only supported values for OCDIVHALF and OCDIV Other combinatio
155. C RDLATFIRSTx 98 EMC RWPOLx 100 WENBENXx 100 EMD types 96 eNVM block protection 57 clocks 61 interrupts 62 physical memory map 50 read control 51 read next operation 53 reprogramming blocks using Cortex M3 375 resets 61 timing diagrams 53 write operations 55 eNVM commands 58 eNVM controller block diagram 47 48 memory organization 49 eNVM controller register map 62 ENVM 0 CR 68 ENVM 1 CR 69 ENVM CONTROL REG 66 ENVM CR 25 ENVM ENABLE REG 66 ENVM PAGE STATUS 0 REG 70 ENVM PAGE STATUS 1 REG 71 ENVM PIPE BYPASS 26 ENVM REMAP FAB CR 28 ENVM REMAP SYS CR 27 ENVM SIX CYCLE 26 ENVM STATUS REG 63 ENVM STATUS x 65 eSRAM 79 address locations 79 timing diagram 80 eSRAM register map 79 ESRAM CR 24 79 Ethernet MAC block diagram 173 clocks 176 descriptors 178 179 frame data 178 frame format 193 functional blocks 174 interface signals 177 internal operation 188 interrupt controller 191 IOMUXes 215 setup frames 187 396 Actel software interface 197 ETM 8 external memory controller features 81 external memory device examples 92 F FAB_APB_HIWORD_DR 350 FAB_IF_CR 346 FAB_PROT_BASE_CR 30 FAB_PROT_SIZE_CR 28 fabric APB master 351 interrupt mapping 353 master APB interface 350 master to MSS slave 349 fabric interface 341 clocks 347 control signals 344 interrupt controller FIIC 351 register map 345 fabric interface controller FIC 342 fabric master interface 349 FCLK cycles 85 89 FCR UART 279 FIC
156. CHEVENT RTCIF_PUBINT IAP INT ENVM 1 0 INT DMAINTERRUPT UART 0 INT SPI 0 INT I2C 0 INT I2C 0 SMBALERT 2 0 SMBSUS 122 1 SMBALERT 2 1 SMBSUS PLLLOCKINT PLLLOCKLOSTINT MSS GPIO 31 0 MSSINT 1 SOFTINTERRUPT MSSINT 2 Revision 1 353 __________________ Fabric Interface and IOMUX FIICMSSIRQ EN 0 Table 19 8 MSSIRQ EN 0 RAV 31 25 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 24 SOFTINT RAV 1 Enable 0 Mask 23 PLLLOCKLOST 1 Enable 0 Mask 18 I2C 1 SMBALERT Rw 1 Enable 0 Mask I2C 0 SMBALERT 1 0 RTCMATCHEVENT RW o 1 0 BROWNOUT3 3V 1 0 BROWNOUT1_5V 1 0 MSSIRQ EN 1 Table 19 9 MSSIRQ EN 1 MSS GPIO Rw o 1 Enable 0 Mask 354 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MSSIRQ EN 2 Table 19 10 MSSIRQ EN 2 Bit Number R W Function 31 24 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation CMP_11_R 1 Enable 0
157. CLK When EMC CSFEx 1 EMC CSx N is asserted on the falling edge of FCLK When EMC CSFEx for the selected region is low EMC CSx N is driven per the waveform shown on row 11 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type Revision 1 99 Acte External Memory Controller When CSFEx for the selected region is high CSx is driven the waveform shown on row 12 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type Read Write Polarity RWPOLXx When RWPOLx 0 the polarity of the RW N is non inverted That is reads are a high writes are a low When EMC RWPOLx 1 the polarity of the EMC RW N is inverted That is reads are a low and writes are a high When RWPOLx for the selected region is low RW driven per the waveform shown on row 13 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type When RWPOLx for the selected region is high RW driven per the waveform shown on row 14 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type Write Enable Byte Enable EMC WENBENX EMC WENBENXx controls whether the byte lane enables signals EMC BYTE ENX serve as write enables only asserted for writes or byte enables asserted for reads a
158. Channel 7 buffer A source address address 7 BUFFER 057 ADDR 0x4000410C E Channel 7 buffer A destination address CHANNEL 7 BUFFER A TRANSFER COUNT 0x40004110 Rw 0 Channel 7 buffer A transfer count CHANNEL 7 BUFFER B SRC ADDR 7 BUFFER B SRC ADDR 0x40004114 ee Channel 7 Channel 7 buffer B source address B source address e 7 BUFFER B 057 ADDR 0x40004118 Channel 7 buffer B destination address CHANNEL 7 BUFFER B TRANSFER COUNT 0x4000411C Rw Channel 7 buffer B transfer count RATIO HIGH LOW Register Table 3 3 RATIO HIGH LOW Bit 31 8 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 0 RATIOHILO RAV This field indicates the ratio of high priority to low priority for DMA access opportunities Only certain values are allowed as indicated in Table 3 1 on page 37 Revision 1 41 D LLL Meter Peripheral DMA PDMA BUFFER STATUS Register Table 3 4 BUFFER STATUS Bit 31 16 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation CH7BUFB R W If CH COMP B for channel 7 is set and if BUF B SEL for channel 7 is clear then this bit is asserted 1 14 CH7BUFA RAW If CH CO
159. EMC IDDx Revision 1 97 Acte External Memory Controller Read Latency Initial Access RDLATFIRSTXx The field EMC RDLATFIRSTx determines the number of initial latency cycles for the first read access for the respective chip select where x defines which chip select is applicable Each cycle is defined to be 1 FCLK period Zero to a maximum of 15 latency cycles can be programmed by the user For asynchronous and flash memory types EMC RDLATFIRSTx read latency cycles are inserted between clock edges 2 and 2 X as shown in Figure 7 18 on 101 Asynchronous Read Cycle where X the value programmed into EMC RDLATFIRSTx Note that for X 0 the shown latency cycle is removed from the timing diagram For synchronous memory types with EMC PIPERDNXx 1 initial read latency cycles are inserted between clock edges 2 and 2 1 as shown in Figure 7 19 on page 102 Non Pipelined Synchronous Read Cycle Note that for X 1 the shown latency cycle is removed from the timing diagram and for X 0 the FCLK cycle between edges 2 X 1 and 3 1 is coincident with the FCLK cycle between edges 1 and 2 For synchronous memory types with PIPERDNXx 0 initial read latency cycles are inserted between clock edges 2 and 2 X 1 for rows 0 11 and between clock edges 5 and 5 X 1 for rows 12 20 as shown in Figure 7 20 on page 103 Pipelined Synchronous Read Cycle Note that for 1 the
160. ESELECT O is available at the SPI x SS 0 pin Note The slave select output signal is active low Note Currently for the A2F200 device SPI 0 can only select four slaves This means only SPI 0 55 01 SPI 0 SS 3 1 outputs are valid Revision 1 237 __________________________ _ MAefel Serial Peripheral Interface SPI Controller SPI Marked Interrupt Status Register MIS Table 13 12 MIS Name R W Reset Value Description Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 TXCHUNDMSKINT Masked interrupt status Reading this returns interrupt status Masked interrupt status Raw interrupt status and interrupt mask Control Register MIS RIS and CONTROL 7 4 Masked Status of Transmit Channel TXCHUNDMSKINT TXCHUNDRINT and INTTXUNRRUN RXCHOVRFMSKINT Masked status of receive channel overflow RXCHOVRFMSKINT RXCHOVRFINT and INTRXOVRFLO 1 RXRDYMSKINT Masked status of receive data ready data received in FIFO RXRDYMSKINT RXRDY and INTTXDATA TXDONEMSKINT Masked status of transmit done data shifted out TXDONEMSKINT TXDONE and INTRXDATA SPI Raw Interrupt Status Register RIS Table 13 13 RIS Bit Name Reset Value Description Reserved Software should not rely on the value of a reserved bit To provide compatibil
161. FIFOs are full or the receive FIFOs are empty Transmit Process The transmit process can operate in one of three modes running stopped or suspended After a software or hardware reset or after a stop transmit command the transmit process is in a stopped state The transmit process can leave a stopped state only after the start transmit command When in a running state the transmit process performs descriptor buffer processing When operating in a suspended or stopped state the transmit process retains the position of the next descriptor that is the address of the descriptor following the last descriptor being closed After entering a running state that position is used for the next descriptor fetch The only exception is when the host writes the transmit descriptor base address register CSR4 In that case the descriptor address is reset and the fetch is directed to the first position in the list Before writing to CSR4 the MAC must be in a stopped state The transmit process remains running until one of the following events occur e The hardware or software reset is issued Setting the CSRO 0 SWR bit can perform the software reset After the reset all the internal registers return to their default states The current descriptor s position in the transmit descriptor list is lost Astop transmit command is issued by the host This can be performed by writing 0 to the CSR6 13 ST bit The current descriptor s position is retained
162. GA fabric is unprogrammed Revision 1 369 ____________________ Fabric Interface and IOMUX Miscellaneous Signals Table 19 32 lists miscellaneous control and status signals connecting the MSS and the FPGA fabric These signals are available for instantiation by Actel Libero IDE FPGA design tool Table 19 32 Miscellaneous Interface Signals Input To Output Function From FPGA Fabric TXEV Input Event transmitted as a result of Cortex M3 SEV send event instruction This is a single cycle pulse equal to 1 FCLK period RXEV Output Causes the Cortex M3 to wake up from a instruction The event input RXEV is registered even when not waiting for an event and so affects the next WFE SLEEPING Input This signal is asserted when the Cortex M3 is in sleep now or sleep on exit mode and indicates that the clock to the processor can be stopped DEEPSLEEP Input This signal is asserted when the Cortex M3 is in sleep now or sleep on exit mode when the SLEEPDEEP bit of the System Control Register is set M2F_RESET_N Input MSS reset signal driven into the FPGA fabric Controlled by the reset manager F2M_RESET_N Output Fabric reset signal driven into the MSS reset manager Controlled by the user FABINT Output Interrupt signal sourced by user logic to the NVIC on the Cortex M3 which is INTISR 31 DMAREADYO Indicates that a soft IP is ready to be serviced DMAREADY1 Indicates that a soft IP is ready to be serviced
163. GLB RC Osc Main Osc RXBSEL Fabric SYNBSEL STATBSEL YB x 5a CLKC ZN GLC RC Osc 32 KHz Osc RXCSEL Fabric DYNCSEL MAC STATCSEL YC From MSS SYSREG Dynamic JTAG Shift CCC Config Bits Register Figure 8 3 SmartFusion MSS Block 110 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Input Clock Selection Each clock path has its own input multiplexer allowing the user flexibility in choosing the clock source for that path The input clock source can be changed dynamically by setting the appropriate control bits for the MSS CCC MUX CR register The control bits for CLKA are shown in Table 8 1 and the multiplexer arrangement is shown in Figure 8 5 on page 112 The input clock pads feeding the input clock multiplexers are shown in Figure 8 4 The Actel Libero Integrated Design Environment IDE MSS Configurator configures the instantiation of the input buffer macros depicted in Figure 8 5 on page 112 based on drop down menu selections Table 8 1 Selection BENE Lo XL o m 0 Ee a a 4 4 a E Shaded box represents an INBUF or INBUF LVDS LVPECL Macro Sample Pin Names GAAO IOONDBOVO AUIN To FPGA Fabric To FPGA Fabric GAA 1 IOOPDBOVO AUIP To FPGA Fabric ADIN To FPGA Fabric GAA2 I013PDB7V1 ADIP Note Represents the global input pins Figure 8 4 Clock Input Sources for CLKA Multiplexer Revision 1 111
164. GPOUTEN To enable the GPIO as an input set the GPINEN bit to a 1 This allows the synchronized input from the MSSIOBUF to be available in the GPI register as shown in Figure 18 2 on page 316 When the user disables the input path by setting the GPINEN bit to a 0 the value read at the respective bit location of the GPI input register will be 0 0 Output register disabled 1 Output register enabled hal 2 GPO OUTBUFEN RAV 0 Disable output buffer if signal routed through IOMUX to IOBUF dependent on IOMUX setting 1 Enable output buffer if signal routed through IOMUX to IOBUF dependent on IOMUX setting Revision 1 317 ________________________ _ Acte General Purpose I O Block GPIO To enable the GPIO as an output set the GPOUTEN bit to a 1 This allows the output from the GPO register to pass to the MSSIOBUF as shown in Figure 18 2 on page 316 If the user wishes to disable the output path by setting the GPOUTEN to a 0 a logical 0 will drive the MSSIOBUF and the respective bit in the GPO register will retain its state To use a GPIO as a general purpose interrupt the GPINTEN bit must be set to a 1 for that bit Level interrupts clear automatically but edge interrupts must be cleared manually by writing a 1 to the respective bit location in the GPIO INTR register If attempting to clear an edge interrupt at the same time as an edge occurs the edge wins Table 18 3 depicts the bit settings needed to generate a par
165. HB Address Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 7 3 Misaligned Read Transactions FCLK Cycles Required for Memory Accesses Based on the memory access read or write EMD data width EMC PORTSIZEx and memory access width the EMC will require different number of phases to complete a read or write In the case where the AHB transaction width HSIZE is greater than EMC PORTSIZEx the EMC must perform multiple EMD accesses Since accesses can have pipelined addresses and data the number of EMC phases required depends on the configured programming of the EMC Table 7 4 shows the number of phases required for each access as a function of EMC PORTSIZEx and AHB transaction width HSIZE with no pipeline or latency delays The various possible configurations of EMC PORTSIZEx and AHB transaction width HSIZE result in EMD accesses that will require either one two or four addresses and make one two or four EMD accesses read or write Table 7 4 identifies the number of accesses required and the maximum number of phases required for an access when a phase is equal to one FCLK cycle Table 7 4 Memory Address Generation AHB Transaction Width Access Type HSIZE EMC PORTSIZEx Number of Phases Wwe 4 From the perspective of an AHB access Table 7 5 and Table 7 6 on page 91 can be used to calculate the number of FCLK cycles required for each type of access The fol
166. IIC receives 128 interrupt sources from the MSS as inputs These interrupt source inputs are level sensitive active high inputs These interrupt sources are combined in a predetermined fashion into the 8 MSSINT interrupts There is also a pass through of the watchdog timer interrupt to WDINT As shown in Figure 19 10 all interrupt processing is combinatorial that is the paths from the interrupt source inputs to the MSSINT 7 0 and WDINT outputs contain no flip flops Peripherals which drive the interrupt source inputs must ensure that their interrupts remain asserted until they are serviced The FIIC performs no synchronization of source inputs nor does it synchronize the output interrupt signals to the fabric MSSINT 0 REG I2C 0 bit 14 2 0 INT MSSINT O MSSINT 0 REG UART 0 bit 10 Figure 19 10 FICC Combinatorial Interrupt Processing In addition to having enabling masking capability at each interrupt source peripheral the FIIC also contains enable registers to provide another level of masking because some interrupts may need to be active in the MSS but not in the FPGA fabric All interrupt inputs to the are active high Once asserted they are guaranteed to be held asserted until cleared by firmware via a write of a 1 to clear the peripheral The exceptions to this are the SMBALERT and SMBUS interrupts from the 2 peripherals While these held asserted they are cleared by the sending I2C d
167. IRE e Synchronous Serial The protocol details are explained in the SPI Data Transfer Protocol Details section on page 225 SPI Transmit and Receive FIFO Flags and Interrupts The SPI controller contains two 4 x 32 depth x width FIFOs one for the receive side and the other for the transmit side The TXFIFOFUL and TXFIFOEMP bits of the SPISTAUS REG register indicate the full or empty status of the transmit FIFO The RXFIFOFUL and RXFIFOEMP bits of the SPISTAUS REG register indicate the full or empty status of the receive FIFO The Cortex M3 can poll these bits to obtain the status of the corresponding FIFO For large data transfers under Cortex M3 control the full depth of transmit FIFO can be used by setting the number of data frames in a burst to a number greater than 1 maximum is 64 K frames When interrupts are enabled the TXDONE bit of the RIS register is asserted after all the data frames in the burst are sent Revision 1 223 D LLL Meter Serial Peripheral Interface SPI Controller For example if the data frame size is set to 32 and the count to 2 then interrupt TXDONE is generated after every two words 32 bits The default value for the frame count is 1 The TXUNDERRUN and RXOVERFLOW bits of the SPICNTL REG register are conditional interrupts that are available for each channel in DMA mode to indicate that a FIFO under run or FIFO overflow has occurred If the transmit FIFO is accessed for data to transfer and ther
168. IRQ SRC 5 Table 19 21 SRC 5 Erud 9 Reserved LL should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation ADC 2 CAL RJ 9 1 Interrupt asserted and enabled ADC_1_CAL_R o 1 Interrupt asserted and enabled ADC 0 CAL R R 1 Interrupt asserted and enabled 6 ____ ADC 2 CAL F RJ o 1 Interrupt asserted and enabled ADC 1 CAL F RJ 9 1 Interrupt asserted and enabled M ADC 0 CAL F RJ 1 Interrupt asserted and enabled ADC2DVR RJ 9 1 Interrupt asserted and enabled ADC 1 DV R R 1 Interrupt asserted and enabled ec ADC_0 R 1 Interrupt asserted and enabled MSSIRQ SRC 6 Table 19 22 MSSIRQ SRC 6 31 6 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation ADC2 AFULL PR o 1 Interrupt asserted and enabled M ADC2 FULL RJ 1 Interrupt asserted and enabled ADC1_AFULL PR o 1 Interrupt asserted and enabled ADC1_FULL PR 1 Interrupt asserted and enabled Mo ADCO AFULL 1 Interrupt asserted and enabled ADCO FULL PR 1 Interrupt asserted and enabled 362 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MSSIRQ SRC 7 Ta
169. LX bi uoce uua poo 4 to 32 Bits SPI X OEN mba X CC CB 5 Figure 13 5 Motorola SPI Mode 2 Single Frame Transfer Mode 3 5 1 5 1 SPLX 55 SPI X DI 9X3 9 xor WI a a 4 to 32 Bits SPI X OEN MB X X X Ga X CB Figure 13 6 Motorola SPI Mode 3 Output Enable SPI x OEN Timing Each SPI mode comprises two phases a transmit or shift out and receive or sample It is a requirement that the output enable SPI x OEN line which enables the output pad should be driven so that the pad is ready to transmit when the data is available setup The pad is held on long enough for the recipient to sample the data hold The minimum setup and hold time is one half SPI x CLK In slave mode the situation is slightly complicated because the input clock is withdrawn at the end of the transfer For example consider the waveform for SPO 1 SPH 0 Figure 13 5 In this case data is sampled on the falling edge of the clock and shifted on the rising edge of the clock The data is sampled on the falling edge and must be held for one half SPI x CLK after the last falling edge at the end of the transmission This means SPI x OEN must be held High for at least one half SPI x CLK after the last falling edge to satisfy the hold time requirement However in the above slave case the SPI x CLK input has been
170. Ly Rate This Document Actel SmartFusion Microcontroller Subsystem User s Guide Actel POWER MATTERS Actel Corporation Mountain View 94043 O 2010 Actel Corporation rights reserved Printed in the United States of America Part Number 50200250 1 Release May 2010 No part of this document may be copied or reproduced in any form or by any means without prior written consent of Actel Actel makes no warranties with respect to this documentation and disclaims any implied warranties of merchantability or fitness for a particular purpose Information in this document is subject to change without notice Actel assumes no responsibility for any errors that may appear in this document This document contains confidential proprietary information that is not to be disclosed to any unauthorized person without prior written consent of Actel Corporation Trademarks Actel Actel Fusion IGLOO Libero Pigeon Point ProASIC SmartFusion and the associated logos are trademarks or registered trademarks of Actel Corporation All other trademarks and service marks are the property of their respective owners Actel POWER MATTERS Actel SmartFusion Microcontroller Subsystem User s Guide Table of Contents SmartFusion Microcontroller Subsystem MSS User s Guide 1 ARM CortexM3 Mierocontroller una vae sea Rh RR Ooh eso Deedee en Cortex M3 SysTick I DR RR RR 8 tEn UPS pr 10 2 JNHB B s
171. MP A for channel 7 is set and if BUF A SEL for channel 7 is clear then this bit is asserted 1 CH6BUFB R W If CH COMP B for channel 6 is set and if BUF B SEL for channel 6 is clear then this bit is asserted 1 CH6BUFA RAN If CH COMP A for channel 6 is set and if BUF A SEL for channel 6 is clear then this bit is asserted 1 CH5BUFB R W If CH COMP B for channel 5 is set and if BUF B SEL for channel 5 is clear then this bit is asserted 1 10 CH5BUFA R W If CH_COMP_A for channel 5 is set and if BUF A SEL for channel 5 is clear then this bit is asserted 1 RAN If CH COMP B for channel 4 is set and if BUF B SEL for channel 4 is clear then this bit is asserted 1 CH4BUFA R W If CH_COMP_A for channel 4 is set and if BUF_A_SEL for channel 4 is clear then this bit is asserted 1 If CH COMP B for channel 3 is set and if BUF B SEL for channel 3 is clear then this bit is asserted 1 CH2BUFB If CH COMP B for channel 2 is set and if BUF B SEL for channel 2 is clear then this bit is asserted 1 CH2BUFA If CH COMP A for channel 2 is set and if BUF A SEL for channel 2 is clear then this bit is asserted 1 If CH COMP A for channel 3 is set and if BUF A SEL for channel 3 is clear then this bit is asserted 1 CH1BUFB If CH COMP B for channel 1 is set and if BUF B SEL for channel 1 is clear then this bit is asserted 1 CH1BUFA CHOBUFA If CH COMP A for channel 1 is set and if BUF A SEL for channel
172. MSS Configurators and Drivers User s Guides Developing User Application Code with MSS Timer Drivers When creating Timer application code using the SmartFusion MSS Timer drivers the mss timer h header file must be included in the C code as shown below Example include mss timer h Before a MSS Timer can be used it must first be initialized to operate in a specific mode As described in the Introduction section on page 301 each timer can operate in periodic mode or one shot mode In the firmware these modes are called MSS TIMER PERIODIC MODE and MSS TIMER ONE SHOT MODE respectively The functions MSS TIMI1 init MSS TIM2 init and MSS 64 init are used to initialize 32 bit 1 32 bit Timer2 or the 64 bit combination of Timer1 and Timer2 It is important to note that the SmartFusion MSS Timer cannot be used as both a 64 bit and 32 bit timer Calling the MSS 64 init function will overwrite any previous configuration of the MSS Timer1 or Timer2 as a 32 bit timer Similarly calling MSS 1 init or MSS 2 init will overwrite any previous configuration of the MSS Timer as a 64 bit timer For example to initialize Timer1 as a 32 bit periodic timer the code below would be used MSS init MSS TIMER PERIODIC MODE Once the desired timer is initialized the 32 bit or 64 bit count value must be loaded into the timer down counter There are two ways to load the timer value the immediate lo
173. Nx for the active byte lane s will go low EMC BYTE ENx for inactive byte lanes will remain high EMC RDB is registered in the EMC here Start of next access delayed by IDD 1 2 4 Acc Transactions Revision 1 External Memory Controller VActel Non Pipelined Synchronous Read Cycle FCLK HADDR HSEL EMC HSEL OTHER HTRANS1 HWRITE HWDATA HRDATA HREADYOUT EMC CLK EMC AB CSx N CsFE 0 5 5 1 RW RwPOL 0 EMC RW N RwPOL 1 EMC PAD OE EMC OEx N BYTE WENBEN 0 BYTE WENBEN 1 EMC WDB EMC RDB g 2 eom m Uo c a a d gt gt e gt gt gt gt gt gt gt N ps 2 Notes E 1 1 1 1 1 1 E x x 1 EMC_MEMTYPE 10 5 a a ju a E o M e 2 2 2 PIPERDNx is high for non pipelined reads H H i 1 0 3 PIPEWRNXx is ignored for reads el a 1 1 i 4 Initial shaded latency cycle is EMC_RDLATFIRSTx FCLK cycles wide i An EMC RDLATFIRSTx value of 0 will remove this cycle i 2 5 Shaded initial latency cycle is EMC_RDLATFIRSTx 1 FCLK cycles wide 4 3 An EMC_RDLATFIRSTx value of 1 will remove this initial latency cycle i 4
174. OF __ mpi Jewmxoem ee 3 d 3 LIP JL moe 52 ___ _ ee Revision 1 217 __________________ Ethernet MAC IOMUX 21 Table 12 48 IOMUX 21 IOMUX 21 Ports op p fe e m peunm Dx pee 1 IOMUX 22 Table 12 49 IOMUX 22 mwe fe m ower TdT dT Ex p IOMUX 23 Table 12 50 IOMUX 23 Pad IOMUX 23 Ports Jeep Ir lOuxwByVz 1 qq wj 218 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 24 Table 12 51 IOMUX 24 Pad IOMUX 24 Ports Pad Name Ports IOMUX 24 CR OUT A OUT B MBE paca MEE JE ___ 141 42 Revision 1 219 VActel POWER MATTERS 13 Serial Peripheral Interface SPI Controller The serial peripheral interface controller is an APB slave that provides a serial interface compliant with the Motorola SPI Texas Instruments synchronous serial and National Semiconductor MICROWIRE formats In addition the SPI supports interfacing to large SPI flash and EEPROM devices The SmartFusion d
175. OGMVRP level and zero the Watchdog is in a time window which permits it to be refreshed It is possible to avoid having forbidden and permitted time windows for refreshing the Watchdog by setting the value of the WDOGMVRP register to a value greater than that stored the WDOGLOAD register Revision 1 167 _________________________ _ MAefel Watchdog Timer Watchdog Enable Register WDOGENABLE EIS 11 6 po EI 0 LL Watchdog is enabled at power up After power up the ENABLE bit can be cleared by writing the value Ox4C6E55FA to the address of this register Subsequent to this the ENABLE bit can only be set again by a power on reset ENABLE This is the actual ENABLE bit that is used by the Watchdog Users can read whether the Watchdog is enabled or disabled by reading this bit Note that this bit overlays the DISABLE KEY Watchdog Control Register WDOGCONTROL Table 11 7 WDOGCONTROL Bit Bit Number BitNumber R W Reset Value Reset Reset Value Description 31 3 Reserved R W Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation R W Watchdog mode of operation 0 Reset generated if counter reaches zero 1 WDOGTIMEOUTINT interrupt generated if enabled if counter reaches zero TIMEOUTINTEN R W 0x0 0 WDOGTIMEOUTINT interrupt gener
176. OMUX 2 Table 18 9 IOMUX 2 CX 9 msme 7 somone arora 1E Pe i LE ps oewxrs Revision 1 321 POCA Ct e General Purpose I O Block GPIO IOMUX 3 Table 18 10 IOMUX D e 1 mem OF ____________ Wer ae qp wq qp xo pscp gue p i 1 IOMUX 4 Table 18 11 IOMUX 4 Pad IOMUX 4 Ports DI LL s pwmem 9 A OE ewe 1 1 1L 1 IOMUX 5 Table 18 12 IOMUX 5 IOMUX 5 Ports ______ e e GPIO 21 E gewesen ___ dq wu o Ji OF EA 322 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 6 Table 18 13 IOMUX 6 Gp e __ ___ 3 o eeeso js EE OM NN m j perpe qp eee IOMUX 7 Table 18 14 IOMUX 7 Pad IOMUX 7 Ports foa e 1 7 epp SERERE peo P pu EE E
177. P this bit is equivalent to DTR in the MCR Delta data carrier detect Indicates that DCD input has changed state Whenever bit 0 1 2 or 3 is set to 1 a modem status interrupt is generated Trailing edge of ring indicator Indicates that RI input has changed from 0 to 1 Whenever bit 0 1 2 or 3 is set to 1 a modem status interrupt is generated Delta data set ready Indicates that the DSRn input has changed state since the last time it was read by the CPU Whenever bit 0 1 2 or 3 is set to 1 a modem status interrupt is generated Delta clear to send Indicates that the CTSn input has changed state since the last time it was read by the CPU Whenever bit 0 1 2 or 3 is set to 1 a modem status interrupt is generated Scratch Register SR Table 15 15 SR Scratch Register This register has no effect on UART operation Revision 1 283 ____________________ Universal Asynchronous Receiver Transmitter UART Peripherals IOMUXes Associated with UART x IOMUXes 4 5 12 and 13 are used to multiplex UART x transmit and receive signals with GPIOs to MSSIOBUFs IOMUXes 64 69 and 77 82 are used to multiplex modem control signals to fabric interface signals for further connection to FPGA IO Refer to the Fabric Interface and IOMUX section on page 341 for a more thorough description of how IOMUXes operate IOMUXes for UART x TXD and UART x RXD To use the UART x TXD and UART x RXD sig
178. P RAW OxFFFFFFFF The value stored in this register is the maximum counter value for which a refresh is permitted If the Watchdog is refreshed by writing OXAC15DE42 to the WDOGREFRESH register when the counter value is crossing the value stored in the WDOGMVRP register then the refresh does succeed but interrupt or reset is also generated The Watchdog should only be refreshed when the counter value is less than the value stored in the WDOGMVRP register If the value stored in the WDOGMVRP register is greater than the value held in the WDOGLOAD register and also greater than the current value of the counter then a refresh of the Watchdog can be carried out at any time without generating an interrupt or reset Watchdog Refresh Register WDOGREFRESH Table 11 5 WDOGREFRESH Reset Bit Number R W Value Description 31 0 REFRESH_KEY W N A This is a write only register which reads as zero Writing the value OxAC15DE42 to this register causes the counter to be refreshed with the value in the WDOGLOAD register If this register is written to while the current value of the counter is greater than the value in the WDOGMVRP register the counter will be refreshed and a reset or timeout interrupt will be generated depending on the MODE bit of WDOGCONTROL While the counter value is greater than WDOGMVRP there is effectively a time window in which it is forbidden to refresh the Watchdog When the counter is between the WD
179. PD detects the frequency phase difference between its reference and feedback input signals Since the PD output is proportional to the phase difference the change causes the output from the LPF to increase This voltage change increases the resonant frequency of the VCO and increases the feedback frequency as a result The PLL dynamically adjusts in this manner until the PD senses two phase identical signals and steady state lock is achieved The opposite decreasing PD output signal occurs when the input frequency decreases Now suppose the feedback divider is inserted in the feedback path As the division factor M is increased the average phase difference increases The average phase difference will cause the VCO to increase its frequency until the output signal is phase identical to the input after undergoing division In other words lock in both frequency and phase is achieved when the output frequency is M times the input Thus clock division in the feedback path results in multiplication at the output A similar argument can be made when the delay element is inserted into the feedback path To achieve steady state lock the VCO output signal will be delayed by the input period ess the feedback delay For periodic signals this is equivalent to time advancing the output clock by the feedback delay Another key parameter of a PLL system is the acquisition time Acquisition time is the amount of time it takes for the PLL to achieve lock phase align
180. R RX DATA TX DATA CLK GEN SLAVE SELECT 0x40001000 0x40011000 0 40001004 0 40011004 0 40001008 0 40011008 0x4000100C 0x4001100C Interrupt Clear Register 0x40001010 0x40011010 Receive Data Register 0x40001014 0x40011014 Transmit Data Register 0x40001018 0x40011018 0x4000101C 0x4001101C Specifies slave selected master mode 0x40001020 0x40011020 Masked interrupt status 0x40001024 0x40011024 Output Clock Generator master mode Raw interrupt status SPI Register Interface Details This section describes each of the SPI registers in detail SPI Control Register CONTROL Table 13 4 CONTROL Bit Number Name R W Reset Value Description 31 26 Reserved RAV 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 25 SPH RAV 0 Clock phase 24 SPO RAV 0 Clock polarity 23 8 TXRXDFCOUNT R W 0x0001 Number of data frames to be sent received Counts from 1 Maximum value is 64K 7 INTTXUNRRUN R W 0 Interrupt on transmit under run If set to 1 interrupt is not masked and will result in interrupt to Cortex M3 If set to 0 interrupt is masked 6 INTRXOVRFLO RAV 0 Interrupt on receive overflow If set to 1 interrupt is not masked and will result in interrupt to Co
181. ROWNOUT1_5VINT readable as status bits from MSS SR SOFT RST CR 0xE0042030 0x00003FFF8 Reset Controller Register Bit Definitions The bit definitions for SOFT_RST_CR are given in Table 9 3 Table 9 3 SOFT_RST_CR Bit Reset Number R W Value Function 31 20 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PADRESETENABLE 0 No effect 1 Allow reset controller to monitor MSS_RESET_N for an external reset command This bit must be set to 1 if the user wants to allow an external reset from the MSS_RESET_N pad Users can de bounce the MSS_RESET_N pin by delaying the assertion of this bit from the assertion of EXT_SR F2MRESETENABLE 0 F2M_RESET_N cannot reset MSS 1 Allow F2M_RESET_N to reset the MSS via the reset controller 17 FPGA_SR 0 Allow the M2F_RESET_N signal to be released 1 M2F_RESET_N is asserted M2F_RESET_N can be used by user logic as a reset input controlled by the Cortex M3 This bit can also be used as a general purpose output to the FPGA Fabric controlled by the M3 EXT_SR 0 Release MSS_RESET_N from reset 1 Keep MSS_RESET_N asserted low At power up this signal is asserted 1 This causes the MSS_RESET_N signal to remain asserted after power up The user must set this bit to 0 to allow the MSS_RESET_N pad to deassert and release ext
182. ROWNOUT1_5VINT are sourced from the VR PSM block and provide interrupt capability when these supplies fall below 2 5 V and 1 3 V respectively These signals are also readable as status bits from the MSS SR located at address 0 004201 Note that INTISR 1 and INTISR 2 must be enabled after the analog block is turned on The analog block can be turned on by setting the ABPOWERON bit in the ANA COMM CTRL register to a 1 The ANA COMM register is located at address 0x4002000C in the memory map Revision 1 143 ________________________ _ Acte Reset Controller The reset controller outputs are listed and described in Table 9 1 Table 9 1 Reset Controller Outputs LONE NN M3 PORESET N This is a synchronized version of PORESET from the VR PSM block This signal resets all logic within the Cortex M3 with the exception of the SWJ DP block MSS SYSTEM RESET This drives the SYS RESET N input to the Cortex M3 and is also the reset signal for the entire MSS When SYS RESET N asserts low the entire Cortex M3 is reset except for the debug logic that exists in the following blocks Nested vectored interrupt controller NVIC Flash patch and breakpoint FPB Data watchpoint and trace DWT Instrumentation trace macrocell ITM AHB AP MSS SYSTEM RESET N asserts asynchronously and negates synchronously to FCLK This guarantees that it is synchronous to rising edges of FCLK ACLK PCLKO and PCLK1 MSS RESET N is asser
183. SRAM 0 would only be accessed by the combined code bus while eSRAM 1 would only be accessed by the system bus of M3 as well as the other non M3 masters Furthermore if the system designer wishes to have deterministic latencies of ISR execution the ISRs need to be located in eSRAM However the eSRAM must be uncontended in order to guarantee true determinism Therefore in such situations the ISR and the stack should be in a separate eSRAM block from the memory being accessed for buffering by other masters such as DMA The allocation of these memory classes to specific locations in eSRAM is accomplished by configuring the Cortex M3 firmware linker script It is also possible for the user to execute code out of external memory SRAM or flash This is a slower interface due to the latencies in accessing external memory and the fact that instruction fetches from system space are registered by the Cortex M3 The Boot Process The boot process consists of three distinct steps factory boot system boot and user boot Factory boot is reserved for use by Actel System boot can be automated by the Libero IDE tool flow using the MSS configurator or can be performed by the user User boot is generated by the user if needed Factory Boot After reset the AHB bus matrix maps spare pages 1 17 of eNVM down into the bottom of Cortex M3 code space at location 0x00000000 These spare pages are factory write protected Factory boot initializes the
184. SS Status Register is only visible to the Cortex M3 and cannot be accessed by a processor located in the FPGA fabric If required the user could implement a register bit with similar behavior to WDOGTIMEOUTEVENT in the fabric One approach to doing this would be to create a processor readable flip flop which is set when the FPGARESETN signal asserts and is cleared by a power on reset 0 Don t care 1 2 Watchdog has timed out RTCMATCHEVENT This signal is a sticky version of the MATCH SYNC signal from the RTC If a rising edge event is seen on MATCH SYNC after synchronization to the domain this bit is asserted It stays asserted until cleared by CLRRTCMATCHEVENT This signal is used as an interrupt to the Cortex M3 The reset value could be either O or 1 depending on the SmartFusion top level tie off Revision 1 171 VActel POWER MATTERS 12 Ethernet MAC Introduction The SmartFusion Ethernet MAC is a high speed media access control MAC Ethernet controller It implements carrier sense multiple access with collision detection CSMA CD algorithms defined by the IEEE 802 3 standard The Ethernet MAC complies with the low pin count Reduced Media Independent Interface RMIITV specification as defined by the RMII Consortium to interface to an external physical layer PHY device Communication with the ARM Cortex M3 processor is implemented via a set of Control and Status registers on an APB
185. Space EMC CS1 N 31 24 23 16 15 8 7 0 0 74000003 0x74000000 15 8 7 0 0x00000001 0x00000000 31 24 23 16 15 8 7 0 Ox77FFFFFF Ox73FFFFFC 15 8 7 0 OxO3FFFFFF OxO3FFFFFE 15 8 7 0 OxO3FFFFFD OxO3FFFFFC Lower 64M of 64M External 64M External AHB Memory Space Memory Space P Memory Space 86 EMC CSO N Revision 1 31 24 23 16 15 8 7 0 0x70000007 0x70000004 31 24 23 16 15 8 7 0 0 70000003 0 70000000 15 8 7 0 0x00000001 0x00000000 Figure 7 7 Halfword Wide External Memory Device Memory Map VActel Actel SmartFusion Microcontroller Subsystem User s Guide AHB Data H R W DATA 31 0 AHB Address HADDR 31 0 EMC DB 7 0 AB 25 0 Ox77FFFFFF Ox77FFFFFC OxO3FFFFFF 31 24 23 16 15 8 7 0 Ox77FFFFFB 0x77FFFFF8 OxO3FFFFFE OxO3FFFFFD Ox03FFFFFC 64M External gt 64M Upper 64M of AHB Memory Space Memory Space External Memory Space EMC_CS1_N 31 24 23 16 15 8 7 0 0x74000003 0 74000000 7 0 0x00000000 31 24 23 16 15 8 7 0 Ox77FFFFFF Ox73FFFFFC 7 0 0x03FFFFFF 170 7 0 OxO3FFFFFD 7 0 64M External Lower 64M o
186. TATUS 1 0 BUSY Figure 4 2 Block Diagram for eNVM Controller The eNVM controller uses a simple register based command structure that allows all eNVM operations to be performed commands are initiated in a single AHB cycle Address and Data phases and perform a single operation to the eNVM Reads hold the AHB busy HREADYOUT until they complete but all writes are posted and completed independent of the AHB bus If a new operation is started when the addressed eNVM is busy HREADYOUT is deasserted for the new 48 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide operation and it starts when the eNVM is ready This can cause the AHB bus to be busy for an extended period of time especially if the current operation is a lengthy one such as program or erase To avoid this read the ENVM STATUS REG register and verify that BUSY x for the desired eNVM is clear before starting a new operation on that memory block Memory Organization Figure 4 3 depicts the physical organization of a single eNVM eNVMs are organized by sectors pages blocks and bytes Each sector contains 32 pages and 1 spare page Each page contains 8 data blocks and 1 auxiliary block Each data block contains 16 bytes of data with the auxiliary block containing an additional 4 bytes of data 1 Block 128 Bits 1 Page 8 Blocks Plus the AUX Block 1 Sector 33 Pages 1 Flash Array 64
187. TATUS Register Slave Receiver Mode continued Status Code DATA Register Status Action A STOP condition or repeated START condition has been received while still addressed as SLV REC or SLV TRX No action or no action or no action or no action 25 ms SCL low time has been reached device must be reset no action CTRL Register Bits Notes 1 SLA Slave address 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Next Action Taken by Core Switched to not addressed SLV mode no recognition of own SLA or general call address Switched to not addressed SLV mode own SLA or general call address will be recognized Switched to not addressed SLV mode no recognition of own SLA or general call address START condition will be transmitted when the bus becomes free Switched to not addressed SLV mode own SLA or general call address will be recognized START condition will be transmitted when the bus becomes free Slave must proceed to reset state by clearing the interrupt within 10ms according to SMBus Specification 2 0 263 Aoo Meter Inter Integrated Circuit Peripherals STATUS Register Slave Transmitter Mode Table 14 9 S
188. TXFIFOEMPNXT to indicate whether the FIFO is empty or will be after the next read operation SPI Data Transfer Protocol Details This section covers the details of each of the three data transfer protocols including timing diagrams signal requirements and error case scenarios Motorola SPI Protocol The Motorola SPI is a full duplex four wire synchronous transfer protocol It supports programmable clock polarity and phase The SPO clock polarity control bit determines the polarity of the clock If SPO is Low SPISCLKO is driven low when no data is transferred If SPO is High SPISCLK is driven high when no data is transferred The SPH clock phase control bit determines the clock edge that captures the data When SPH is Low data is captured on the first clock transition rising edge if SPO 0 When SPH is HIGH data is captured on the second clock transition rising edge if SPO 1 Table 13 2 summarizes the active edges of the various master SPI modes Table 13 2 Motorola SPI Transfer Modes Pulse Slave Select Clock in Idle Period Sample Shift Between Continuous Slave Select in Idle SPO SPH Edge Edge Transfers Master mode Period s pm 0 3 mes e sqm pm me X The number of bits transferred is set in the TxRx Data Frame Register TXRXDF SIZE Note that SPI x SS is not pulsed between frames when SPH 1 For completeness the rest of possible transfer modes are sh
189. This allows other masters in AHB bus matrix to read from and write to eNVM The capability exists to map a physical portion of eNVM into the address space occupied at 0x0 which is the Cortex M3 code space This essentially creates a virtual view of the eNVM at address 0 0 Revision 1 19 Bus Matrix Peripheral Bit Band Alias Region of Cortex M3 SRAM Bit Band Alias Region of Cortex M3 Cortex M3 System Region Cortex M3 Code Region Figure 2 4 20 Memory Map of Cortex M3 Memory Map of FPGA Fabric Master Ethernet MAC Peripheral DMA System Registers External Memory Type 1 External Memory Type 0 eNVM Aux Block spare pages eNVM Aux Block spare pages eNVM Aux Block array eNVM Spare Pages eNVM Array Peripherals BB view FPGA Fabric FPGA Fabric eSRAM Backdoor FPGA Fabric eSRAM Backdoor 0 o40030004 x4003FFFF External Memory Type 1 External Memory Type 0 eNVM Aux Block array eNVM Spare Pages eNVM Array Analog Compute Engine Fabric Interface Interrupt Controller Fabric Interface Interrupt Controller Watchdog Peripheral DMA Ethernet MAC 2 0 SPI 0 UART 0 eSRAM 0 eSRAM 1 BB view eSRAM 1 eNVM Cortex M3 Virtual View FPGA Fabric APB Extension Register Analog Compute Engine IAP Controller MSS GPIO 2 1 SPI 1 Watchdog Timer Peripheral DMA Ethernet MAC 2 0 SPI 0 UART 0 eSRAM 0 PO 9x00088200 Ox1FFFFFFF eSRAM
190. UART 1 peripherals are clocked by PCLKO Bus 0 and PCLK1 on Bus 1 respectively PLCLKO and PLCK1 are free running versions of the main clock driving the entire MSS which are derived from the MSS CCC See the Clocking Resources Available to the SmartFusion FPGA Fabric section in the SmartFusion FPGA Fabric User s Guide for additional information Revision 1 273 Acte Universal Asynchronous Receiver Transmitter UART Peripherals The baud rate generator block takes the input PCLK PCLKO on APB 0 and PCLK1 on APB 1 and divides it by a programmed value from 1 to 216 1 The result is divided by 16 to create the transmission clock BAUDOUT System Dependencies Resets UART x resets to zero on power up and is held in reset until the user enables it The user has the option under software control to reset the UART x by writing to bit 7 or bit 8 of the SOFT RST CR located at address 0xE0042030 in the system memory map as shown in Table 15 1 Table 15 1 Soft Reset Bit Definition for the ETE UART 1 SR ELLI reset input to UART 1 0 Release UART 1 from reset 1 Keep UART 1 in reset reset value UART 0 SR Controls reset input to UART 0 0 Release UART 0 from reset 1 Keep UART O in reset reset value At power up this signal is asserted as 1 This keeps UART x in a reset state If the user sets this bit to 0 UART x is allowed to become active If UART x SR is 0 UART x could still be held
191. US Register Miscellaneous States Table 14 10 STATUS Register Miscellaneous States DATA CTRL Register Bits Status Register Code Status Action ISTA 5 si aa Next Action Taken by Core Arbitration lost Noacion action E RRAC REE Bus will be released or no action A start condition will be transmitted when the bus becomes free OxF8 No relevant state No Action No Action information available SI 0 0x00 error during MST No action 1 X Only the internal hardware is affected in or selected slave the MST or addressed SLV modes In all modes cases the bus is released and the state switched in non addressed slave mode Stop Flag is reset Revision 1 265 Inter Integrated Circuit C Peripherals DATA Register VActel The DATA register contains a byte of serial data to be transmitted or a byte that has just been received The Cortex M3 can read from and write to this 8 bit directly addressable register while it is not in the process of shifting a byte after an interrupt has been generated The bit descriptions are listed below in both data and addressing context Data context is the 8 bit data format from MSB to LSB Addressing context is based on a master sending an address call to a slave on the bus along with a direction bit master transmit data or receive data from a slave Table 14 11 DATA Bit Number Name R W Reset Value Description
192. UT 8 EMC CLK E EMC AB Y A 14 10 CSx csFE 0 5 N CSFE 1 i 12 RW RWPOL 0 mm 43 RW 1 i i 14 EMC_PAD_OE BYTE WENBEN 0 17 BYTE WENBEN 1 18 WDB X D X Dol 19 RDB 20 Latency Cycle WRLATx 1 1 2 4 Access 2 and 4 Access Transactions Transactions Only Figure 7 21 Asynchronous Write Cycle 104 Latency Cycle WRLATXx 1 Latency Cycle WRLATx 1 4 Access Transactions Only Latency Cycle EMC WRLATx 1 Revision 1 IDD Cycle EMC IDDx 1 Actel Notes 1 _ 01 or EMC_MEMTYPEx 11 2 EMC PIPERDN is ignored for these memory types 3 EMC PIPEWRN is ignored for these memory types 4 The second address for a 2 access read is A 4 2 5 Shaded latency cycles are EMC WRLATx FCLK cycles wide WRLATXx value of 0 will remove these cycles 6 For single access writes If HADDR 1 0 00 DATA If HADDR 1 0 01 DATA If HADDR 1 0 10 DATA If HADDR 1 0 11 DATA DO For two access writes If HADDR 1 0 DATA D1DO If HADDR 1 0 01 DATA D1 DO For four access reads DATA D3 D2 D1 DO Where BYTE is shown low only BYTE for the active
193. VM 1 page status register Revision 1 379 ___________________ SmartFusion Master Register Table 21 2 SmartFusion Master Register Map continued EFROM CR Register Map on page 75 EFROM CR 0 0042024 RW 0 00000009 to set eFROM interface controller timing options External Memory Controller Register Map EMC MUX CR 0xE004203C RAV 0x0 External memory controller MUX configuration CS x CR x 0 OxE0042040 RAV 0 0 timing parameters for chip select 0 CS x CR 1 0 0042044 RAV 0x0 EMC timing parameters for chip select 1 Watchdog Register Interface Summary WDOGVALUE 0x40006000 R 0x20000000 WDOGLOAD 40006004 0 20000000 Load value Loadvalueforcounter counter e l RAV OxFFFFFFFF Maximum value which refreshing is permitted WDOGREFRESH 0x4000600C W Writing the value 15 42 to this register causes the counter to be updated with the value in WDOGLOAD register WDOGENABLE 0x40006010 Watchdog enable register WDOGMIS 0x40006020 PR Masked interrupt status MSS SR 0xE004201C R MSS Status register Ethernet MAC Control and Status Register Addressing CSRO 0x40003000 0 000000 CSR1 0x40003008 fw 09 Transmit poll demand CSR2 0x40003010 fw 09 Receive poll demand CSR3 0x40003018 OxFFFFFFFF Receive list base address CSR4 0x40003020 OxFFFFFFFF Transmit list base
194. X FIFO during the last four register character times and there was at time 0b0010 Third Transmitter Transmitter Holding Register empty Reading the IRR or writing Holding register into the Transmitter Holding empty register 0b0000 Fourth Modem status Clear to Send Data Set Ready Ring Reading the Modem Status Indicator or Data Carrier Detect register 278 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide FIFO Control Register FCR Table 15 10 E 0610 8 bytes 7 6 RX_ These bits are used to set the trigger level for the RX FIFO interrupt 0611 14 bytes default Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0601 4 bytes 0600 1 byte ENABLE TXRDY RXRDY Software must always set this bit to 1 for efficient data transfer from transmit FIFO to PDMA Clears all bytes in RX FIFO and resets counter logic This shift register is not cleared 0 Disabled default CLEAR RX FIFO 1 Enabled Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 CLEAR TX FIFO Ww Clears all bytes in TX FIFO and resets counter logic This shift register is not cleared 0 Disabled default
195. XTAL Figure 8 13 Main Crystal Oscillator in RC Network Mode Revision 1 121 _________________ TAA PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators VCCMAINXTAL Off Chip Main Crystal MAINXOUT Oscillator GNDMAINXTAL Figure 8 14 Main Crystal Oscillator in Ceramic Resonator or Crystal Mode RC Time Constant Values vs Frequency 1 00E 0 3 1 00E 0 4 1 00E 0 5 RC Time Constant sec 1 00E 0 6 1 00E 0 7 0 0 0 5 1 0 1 5 2 0 2 5 3 0 3 5 4 0 4 5 Frequency MHz Figure 8 15 Main Crystal Oscillator RC Time Constant Versus Frequency 122 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Low Power 32 KHz Crystal Oscillator This oscillator is designed to work with a low power 32 KHz watch crystal for example a CM519 can be enabled and disabled by setting and clearing bit 0 of the CTRL STAT REG in the RTC section If not being used in the end user application the LPXIN and LPXOUT pins can be left floating Additionally a capacitor is required on both LPXIN and LPXOUT pins to ground as shown in Figure 8 17 on page 124 The recommended input capacitance is 30 pF Battery Backup Circuitry The 32 KHz low power crystal oscillator and the real time counter RTC can be powered externally by a CR2032 type o
196. XXX Internal Operation DMA Controller The DMA is used to control a data flow between the host and Ethernet MAC The DMA services the following types of requests from the Ethernet MAC transmit and receive processes e Transmit request Descriptor fetch Descriptor closing Setup packet processing Data transfer from host buffer to transmit FIFO Receive request Descriptor fetch Descriptor closing Data transfer from receive FIFO to host buffer The key task for the DMA is to perform an arbitration between the receive and transmit processes Two arbitration schemes are possible according to the CSRO 1 bit 1 Value 1 Round robin arbitration scheme in which receive and transmit processes have equal priorities 188 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide 2 Value 0 The receive process has priority over the transmit process unless transmission is in progress In this case the following rules apply The transmit process request should be serviced by the DMA between two consecutive receive transfers The receive process request should be serviced by the DMA between two consecutive transmit transfers Transfers between the host and Ethernet MAC performed by the DMA component are 32 bit data transfers or burst transfers In the case of data buffers the burst length is defined by CSRO 13 8 PBL which is set to zero and the transfer ends when the transmit
197. ___________________ Acte Ethernet MAC Figure 12 5 shows descriptors in chained structure CSR CSR3 CSR4 Descriptor List Base Shared Buffer 1 Buffer 2 Buffer 2 Buffer 2 Figure 12 5 Descriptors in Chained Structure Table 12 2 through Table 12 6 on page 183 give bit descriptions and functions for the receive descriptors Table 12 2 Receive Descriptors RDESx RDES1 CONTROL RBS2 RBS1 RDES2 RDES2 RBA2 Note The RDESx descriptors reside in receive data memory They can be defined and addressed under software control 180 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 3 Receive Descriptor 0 RDESO Bit Functions Ownership bit 1 Ethernet MAC owns the descriptor 0 The host owns the descriptor Ethernet MAC will clear this bit when it completes a current frame reception or when the data buffers associated with a given descriptor are already full Filtering fail When set indicates that a received frame did not pass the address recognition process This bit is valid only for the last descriptor of the frame RDESO 8 set when the CSR6 30 receive all bit is set and the frame is at least 64 bytes long Frame length Indicates the length in bytes of the data transferred into a host memory for a given frame This bit is valid only when RDESO 8 last descriptor is set and RDESO 14 descriptor error i
198. able to handle glitches from these potential changing clocks A simple solution would be to have the Cortex M3 set a bit in FPGA fabric that user logic can use as a reset when the Cortex M3 is changing the clock sources to user logic On Chip RC Oscillator The on chip RC oscillator Figure 8 12 runs at a nominal frequency of 100 MHz On power up the RC is used as the input clock to the microcontroller subsystem At that time the RC is divided by 4 through the w divider OCDIV and presented to GLAO and GLA1 through the glitchless MUX RC oscillator is always turned on VCCRCOSC 100 MHz RC Oscillator GNDRCOSC Figure 8 12 On Chip RC Oscillator 120 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Main Crystal Oscillator The on chip crystal oscillator circuit works with an off chip crystal to generate a high precision clock and is capable of providing system clocks for peripherals and other system clock networks both on chip and off chip The on chip circuitry is designed to work with an external crystal a ceramic resonator or an RC network It can only support one of these configurations at a time The crystal oscillator supports four modes of operation defined in Table 8 4 In RC Network mode the oscillator is configured to work with an external RC network The RC components are connected to the MAINXIN pin with MAINXOUT left floating as shown in Figure 8 13 The frequency generate
199. ad and the background load In the immediate load method the load value is the value from which the timer will start counting down to zero immediately after being enabled If the timer was already enabled when an immediate load occurred the counter value will be set to the new load value and immediately start counting down The functions used to perform an immediate timer load are called MSS TIM1 load immediate MSS TIM2 load immediate and MSS TIM64 load immediate for 312 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide each respective timer Timer1 Timer2 or 64 bit Timer From this point on functions will be shown for Timer1 since the Timer2 and 64 bit functions are similar in usage For example to load a timer start value equal to 1 second the user can use the CMSIS PAL global variable 9 FrequencyPCLKO which provides the timer input frequency Thus counting down from this value to zero will take 1 second once the timer is enabled SystemCoreClockUpdate CMSIS Func updates global freq variables MSS load immediate FrequencyPCLKO In contrast the background load method loads the timer with the value that will be reloaded into the timer down counter the next time the counter reaches zero When the timer is operating in periodic mode background loading is typically used to change the delay period between the timer interrupts without stopping the timer Note that the MSS TIM6
200. address CSR5 0x40003028 OxF0000000 CSR6 0x40003030 0x32000040 SRT 0x40003038 OxF3FE0000 Interrupt enable enable ________ 0x40003040 RAV 0 0000000 Missed DL and overflow counters CSR9 0x40003048 OxFFF483FB management 380 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 21 2 SmartFusion Master Register Map continued CSR11 0x40003058 RAV OxFFFEO000 Timer and interrupt mitigation control SPI Register Interface Summary addresses for SPI 0 shown SPI 1 begins at 0x40011000 CONTROL ________ 0x40001000 _ Controlregister register TXRXDF RAV Transmit and receive data frame size INT CLEAR 0x4000100C Interrupt Clear register DATA 0x40001014 S AN Transmit Data register Data register D GEN 0x40001018 R W Output Clock Generator master mode SLAVE_SELECT 0x4000101C RAW Specifies slave selected master mode 2C x Register addresses I2C 0 shown I2C 1 begins at 0x40012000 CTRL 0x40002000 R W Used to configure the I C peripheral STATUS 0 40002004 OxF8 Read only value which indicates the current state of the I C peripheral DATA 0x40002008 RAW Read write data to from the serial interface ADDR 0x4000200C RAV Contains the primary programmable address of the peripheral SMBUS 0x40002010 RW 0b01X1X000 Configuration register for SMBus timeout reset conditio
201. al s section of the user s guide to determine how those individual IOMUXes are associated to the peripheral For every reusable MSS I O pad there is an IOMUX The IOMUX is intended to provide flexibility in the allocation of MSS I O pads If the user is not using a particular interface the corresponding I O pads can be reallocated to another interface Also if certain pads are not being used or are not present in some devices then the IOMUX allows the signals to be connected within the IOMUX internally as shown in Figure 19 12 on page 365 The IOMUX is composed of 4 multiplexers MO M1 2 and M3 as shown in Figure 19 11 IOMUX MSSIOBUF 3 IOMUX PU IOMUX PD IOMUX ST IOMUX MO S IOMUX M1 S 1 0 IOMUX 2 S 1 0 IOMUX M3 S OUT B OE B Figure 19 11 IOMUX Block Diagram 364 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Peripheral IOMUX n APB Interrupts M2F x F2M x F2M_OE x FPGAIOBUF FPGA Fabric gt Figure 19 12 Example of IOMUX Signals Routed Internal to the IOMUX Revision 1 365 ________________ Fabric Interface and IOMUX IOMUX Register The IOMUX n CR where n can range from 0 to 82 registers are located within the SYSREG block at address 0 0042100 and continuing for 83 32 bit register locations or 332 bytes There 83 IOMUX n CR control registers one for each IOMUX Figure 19
202. alue register located at 0 000 01 although at different bit locations Specifically NOREF of SYSTICK_CR bit 25 is mapped to NOREF of STCVR bit 31 and SKEW of SYSTICK_CR bit 24 is mapped to SKEW of STCVR bit 30 An application note describing the configuration of the SysTick Timer is available at the ARM Infocenter at the time of this writing Interrupts Table 1 5 lists the interrupt numbers corresponding to the NVIC input pins of the Cortex M3 their sources and which functions assert the interrupt for the SmartFusion family of mixed signal flash based FPGAs Details for each specific interrupt are located in the relevant section of the SmartFusion Intelligent Mixed Signal FPGAs datasheet where the interrupt is sourced A description of exceptions 0 15 can be found in the Cortex M3 Technical Reference Manual The Watchdog Timer interrupt is mapped to the Non Maskable interrupt of the other SmartFusion interrupts are mapped to the external interrupt pins of the Cortex M3 NVIC starting at INTISR O Table 1 5 SmartFusion Interrupt Sources Mw 10 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 1 5 SmartFusion Interrupt Sources continued Revision 1 11 __________________ ARM Cortex M3 Microcontroller Table 1 5 SmartFusion Interrupt Sources continued __ __ ME LL NENNEN 7 es 12 R
203. are not multiplexed with each other they are multiplexed only with the GPIO block A block diagram showing the arrangement of the GPIO the IOMUX and the I O buffer is shown Figure 18 1 This particular example shows the UART 0 transmit signal multiplexed with GPIO bit 20 GPIOs 31 through 16 are shared with peripheral signals via an IOMUX and through an alternate sourcing input these GPIOs can be shared with the fabric Interface while GPIOs 15 through 0 are shared with I O interface tiles from the FPGA fabric The GPIO block is mapped to address 0x40013000 in the memory map IOMUX 4 MSSIOBUF Interrupts GPI 20 GPO 20 GPOE 20 Pull Up Pull Down GPIO 20 Schmitt Trigger Figure 18 1 GPIO IOMUX and Buffer Arrangement Revision 1 315 Acte General Purpose I O Block GPIO MSS GPIO Functional Description Figure 18 2 depicts the GPIO block diagram The GPIO block consists of one 32 bit input register GPI one 32 bit output register GPO one 32 bit interrupt register GPIO INTR and 32 configuration registers one register for each GPIO bit GPIOCFG x REG where x can range from 0 to 31 The GPIOCFG x REG register per bit sets the input output direction enables the relevant bit of each 32 bit register GPINEN for GPOUTEN for GPO and sets the interrupt mask of each individual bit in the GPIO INTR register Interrupts can be level sensitive or edge triggered OUT A or OUT B to IOMUX
204. asserted if any of the following conditions is true PORESET N asserted by analog block MSS RESET REQ asserted by Cortex M3 F2M RESET asserted from FPGA fabric if F2MRESETENABLE asserted in SOFT RST CR LOCKUP asserted by Cortex M3 MSS RESET asserted during allowed window controlled by Reset Controller State Machine MSS RESET N O This signal is used to drive the external output enable of the Buffer MSS RESET N as shown in Figure 9 2 on page 146 When asserted it causes a zero to be driven onto the MSS RESET N pad This signal is asserted by the reset controller during PORESET N assertion When MSS RESET negates MSS RESET remains asserted until firmware clears the EXT SR bit in SOFT RST CR This allows SmartFusion to control the behavior of the system level reset if the user so desires From this point on this signal is driven whenever one of the following reset sources asserts PORESET N asserted by analog block MSS RESET REQ asserted by Cortex M3 F2M RESET asserted from FPGA fabric if F2MRESETENABLE asserted in SOFT RST CR WDOG TIMEOUT asserted by watchdog LOCKUP asserted by Cortex M3 MSS RESET asserted MSS RESET N O is asserted asynchronously and negates synchronously to FCLK After a period of time defined by user firmware the PADRESETENABLE bit in the SOFT RST CR can be set Once this bit is set the reset controller moves to a state where it monitors the state of the MSS RESET
205. ata byte Data byte will be transmitted ACK register has been will be received transmitted NACK has or no ornoaction Repeated START will be transmitted START will be transmitted been received or no action STOP condition will be transmitted STO flag will be reset or no action 1 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x38 Arbitration lost in No action X The bus will be released not SLA R MW or data addressed slave mode will be entered bytes or no action 1 X A START condition will be transmitted when the bus becomes free SMBus Master Reset No Action X X X X Wait 35 ms for interrupt to be set has been activated clear interrupt and proceed to F8H state Notes SLA Slave address SLV Slave REC Receiver TRX Transmitter SLA W Master sends slave address then writes data to slave SLA R Master sends slave address then reads data from slave 258 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide STATUS Register Master Receiver Mode Table 14 7 Status Code Status 0x08 START condition has been transmitted 0x10 repeated START condition has been transmitted 0x38 Arbitration lost in not ACK bit been 0x40 SLA R has transmitted ACK has been received 0x48 SLA R has been transmitted not ACK has been received
206. ation disabled 1 WDOGTIMEOUTINT interrupt generation enabled WAKEUPINTEN R W 0x0 0 WDOGWAKEUPINT interrupt generation disabled 1 WDOGWAKEUPINT interrupt generation enabled Watchdog Status Register WDOGSTATUS Table 11 8 WDOGSTATUS 31 1 Reserved 0x1 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation REFRESHSTATUS 0 1 0 Counter in forbidden window refresh forbidden Refreshing the Watchdog when REFRESHSTATUS 0 will cause an interrupt or reset to be generated 168 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Watchdog Raw Interrupt Status Register WDOGRIS Table 11 9 WDOGRIS Reset Bit Number R W Value Description 31 2 Reserved RAV 0x0 Software should not rely the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 TIMEOUTRS RAV 0x0 Raw Status of the WDOGTIMEOUTINT interrupt Writing 1 to this bit clears the bit Writing 0 has no effect WAKEUPRS RAV 0x0 Raw Status of the WDOGWAKEUPINT interrupt Writing 1 to this bit clears the bit Writing 0 has no effect Watchdog Masked Interrupt Status Register WDOGMIS Table 11 10 WDOGMIS 31 2 Reserved 0x0 Software should not rely on the value of a reserved bit To provide c
207. base address of the segment in eNVM which is to be remapped to location 0x00000000 for use by a soft processor in the FPGA fabric The base address of the remapped segment of eNVM is determined by the value of this bus Bit O of this bus is defined as COM ENVMFABREMAPENABLE COM ENVMFABREMAPENABLE R W 0 0 eNVM remap not enabled Bottom of eNVM is mapped to address 0x00000000 1 eNVM remap enabled eNVM visible at 0x00000000 is a remapped segment of the eNVM Bits 19 N of this bus indicate the base address of the remapped segment The value of N depends on the eNVM remap section size so that the base address is aligned according to an even multiple of segment size The power of 2 size specified by COM_ENVMREMAPSIZE defines how many bits of base address are used For example if the COM_ENVMREMAPSIZE is OxOf this corresponds to a segment size of 64 Kbytes which is 216 Therefore the value of N in this case is 16 The base address of the region in this case is specified by COM ENVMFABREMAPBASE 19 16 For example 1 COM ENVMFABREMAPBASE 19 16 0x0 The 64 Kbytes segment located at the physical memory address of 0x60000000 is mapped into address 0x00000000 2 COM ENVMFABREMAPBASE 19 16 0x1 The 64 Kbytes segment located at the physical memory address of 0x60010000 is mapped into address 0x00000000 3 COM ENVMFABREMAPBASE 19 16 0x2 The 64 Kbytes segment located at the physical
208. bit in SysReg The bit definitions are as follows Bit 0 Corresponds to Cortex M3 ICODE DCODE master Bit 1 Corresponds to Cortex M3 SYSTEM master Bit 2 Corresponds to fabric master Bit 3 Corresponds to Ethernet MAC master BROWNOUT3_3VINT Sticky interrupt derived from a falling edge event on the BROWNOUT3_3V_SYNCN input from the analog subsystem via synchronization in the reset controller indicating that the 3 3 V supply has dropped below a specified threshold voltage This signal is used as an interrupt to the Cortex M3 BROWNOUT1_5VINT Sticky interrupt derived from a falling edge event on the BROWNOUT1_5V_SYNCN input from the analog subsystem via synchronization in the reset controller indicating that the 1 5 V supply has dropped below a specified threshold voltage This signal is used as an interrupt to the Cortex M3 170 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 11 11 MSS SR continued Bit Reset Number R W Value Description WDOGTIMEOUTEVENT 0x0 This signal is a sticky version of the WDOGTIMEOUTINT signal which is itself sticky but is cleared by MSS SYSTEM RESET WDOGTIMEOUTEVENT is not affected by MSS SYSTEM RESET N This allows firmware to determine if a system reset occurred due to a watchdog timeout event This signal is not used as an interrupt to the Cortex M3 This bit is reset to 0 by PORESET N only and is unaffected by MSS SYSTEM RESET N The M
209. bit timer with Periodic and One Shot modes The two 32 bit timers are identical The letter x in register descriptions is used as a placeholder for 1 or 2 indicating Timer 1 or Timer 2 APB Bus TIMxBGLOADVAL TIMxLOADVAL TIMERx TIMxVALUE APB Bus Figure 17 1 Block Diagram 32 Bit Mode TIMxMODE TIMERXINT TIMxENABLE Revision 1 301 ___________________ System Timer APB Bus TIM64BGLOADVALL TIM64BGLOADVALU TIM64LOADVALL TIM64LOADVALU TIMER2 TIM64MODE PCLKO TIM64ENABLE TIM64MODE PCLKO TIM64ENABLE TIMER1INT TIMER2INT TIMER1 TIM64VALUEL TIM64VALUEU APB Bus Figure 17 2 Block Diagram 64 Bit Mode The System Timer is an APB O slave module that provides two programmable interrupt generating 32 bit decrementing counters The two 32 bit timers can be configured to behave as a single 64 bit timer in which Timer 1 contains the lower 32 bits and Timer 2 contains the upper 32 bits of the 64 bit count The System Timer in dual 32 bit mode or 64 bit mode has two modes of operation 1 Periodic mode In this mode the counter generates interrupts at constant intervals On reaching zero the counter is reloaded with a value held in a register and begins counting down again 2 One Shot mode The counter generates a single interrupt in this mode On reaching zero the counter halts until reprogrammed by the user Each 32 bit counter in
210. ble 19 23 SRC 7 me 3 Reserved LL should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation B ADC2 NOTEMPTY RJ 1 Interrupt asserted and enabled ADC1_NOTEMPTY o 1 Interrupt asserted and enabled 002 ADCO NOTEMPTY o 1 Interrupt asserted and enabled MR 19 24 MR 1 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 1 ACE mode 0 Non ACE mode Revision 1 363 __________________ Fabric Interface and IOMUX IOMUX Functional Description The MSS contains I O multiplexers which are involved in the reuse of some MSS related I O pads and in providing a number of options for multiplexing GPIO peripheral signals and fabric interface signals to the I O pad IOMUXes are associated with the GPIO block fabric interface and all MSS communications peripherals UARTS 0 and 1 SPI 0 and 1 I2C 0 and 1 and the Ethernet MAC It is important to note that all available hard peripherals in the MSS are available to MSS I O pads the peripherals are not multiplexed with other peripherals at the pad Table 19 28 page 367 lists the IOMUXes associated with each peripheral Refer to each peripher
211. ble the user to rapidly and easily adopt the SmartFusion MSS GPIO peripheral in their embedded application For additional details on the three tool flows please refer to the SmartFusion tutorials available on the Actel website http www actel com products smartfusion docs aspx Revision 1 339 Actel POWER MATTERS 19 Fabric Interface and IOMUX The fabric interface consists of the fabric interface controller FIC the fabric interface interrupt controller IOMUXes and signals from the analog compute engine ACE the signal conditioning blocks SCBs the voltage regulator power supply monitor VR PSM and a handful of miscellaneous signals The blocks and signals of the fabric interface are shown in Figure 19 1 ACE Flags ACE Trigger DAC Clocks PUBFAB_N FPGAVRON Figure 19 1 Fabric Interfaces Revision 1 341 Meter Fabric Interface and IOMUX Fabric Interface Controller The fabric interface controller FIC is part of the microcontroller subsystem MSS and performs an AHB to AHB or AHB to APB bridging function between the AHB bus matrix and an AHB or APB bus in the FPGA fabric The FIC consumes no FPGA resources It provides two bus interfaces between the MSS and the fabric The first is mastered by the MSS and has slaves in the fabric and the second has a master in the fabric and slaves in the MSS as depicted in Figure 19 2 The interfaces to the fabric can be 32 bit AHB 32 bit APB o
212. bled R 1 Interrupt asserted and enabled CMP2F R 1 Interrupt asserted and enabled _1_ R o 1 Interrupt asserted and enabled OF RJ o 1 Interrupt asserted and enabled 360 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MSSIRQ SRC 3 Table 19 19 mouse SRC 3 12 Reserved EI should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 PC2 FLAG 3 RJ o 1 Interrupt asserted and enabled PC2 FLAG 2 1 Interrupt asserted and enabled PC2 FLAG 1 R o 1 Interrupt asserted and enabled PC2 FLAG 0 RJ o 1 Interrupt asserted and enabled PC1_FLAG_3 RJ o 1 Interrupt asserted and enabled EE PC1 FLAG 2 RJ o 1 Interrupt asserted and enabled PC1 FLAG 1 RJ o 1 Interrupt asserted and enabled PC1 FLAG 0 R o 1 Interrupt asserted and enabled PCO FLAG 3 R o 1 Interrupt asserted and enabled PCO FLAG 2 RJ o 1 Interrupt asserted and enabled PCO FLAG 1 RJ o 1 Interrupt asserted and enabled ____ PCO FLAG 0 RJ o 1 Interrupt asserted and enabled MSSIRQ SRC 4 Table 19 20 MSSIRQ SRC 4 PPE THRESH FR 9 1 2 Interrupt asserted and enabled Revision 1 361 ________________ Fabric Interface and IOMUX MSS
213. by host Checked by Ethernet MAC according to current address filtering mode and passed to host PAD 0 46 Generated by Ethernet Passed to host MAC when CSR 23 DPD bit is cleared and data supplied by host is less than 64 bytes FCS Generated Ethernet Checked by Ethernet MAC and MAC when CSR 26 bit is passed to host cleared Revision 1 193 ________________ _________ _ Acte Ethernet MAC Collision Handling If a collision is detected before the end of the PREAMBLE SFD Ethernet MAC completes the PREAMBLE SFD transmits the JAM sequence and initiates a backoff computation If a collision is detected after the transmission of the PREAMBLE and SFD but prior to 512 bits being transmitted Ethernet MAC immediately aborts the transmission transmits the JAM sequence and then initiates a backoff If a collision is detected after 512 bits have been transmitted the collision is termed a late collision Ethernet MAC aborts the transmission and appends the JAM sequence The transmit message is flushed from the FIFO Ethernet MAC does not initiate a backoff and does not attempt to retransmit the frame when a late collision is detected Ethernet MAC uses a truncated binary exponential backoff algorithm for backoff computing as defined in the IEEE 802 3 standard and outlined in Figure 12 9 Backoff processing is performed only in half duplex mode In full duplex mode collision detection is disabled Reset Attempt T
214. byte lane s will go low EMC BYTE ENx for inactive byte lanes will remain high g 7 Start of next access delayed by IDD 1 2 4 Acc y Transactions VActel Actel SmartFusion Microcontroller Subsystem User s Guide Pipelined Synchronous Write Cycle N N 1 md gt N in in FCLK 0 HADDR 1 HSEL EMC 2 HSEL OTHER 3 HTRANS1 4 HWRITE 5 Notes HWDATA 6 1 EMC MEMTYPEx 10 HRDATA 7 2 EMC PIPERDNx is ignored for writes HREADYOUT 8 3 PIPEWRNx is low for pipelined writes 4 The second address for 2 access read is A942 EMC CLK 9 5 Shaded latency cycles WRLAT 1 cycles wide A 1NA 2 3 WRLAT value of 1 will remove these latency cycles An EMC AB X 0 X 0 0 X 0 s X P 5 10 WRLAT value of 0 causes address and data to be presented 5 GsFE 0 i 11 in the same FCLK cycle CSx CsFE 1 f i B 12 6 For single access writes If HADDR 1 0 00 DATA 1 2 4 284 4 Access i s Access Access Writes ess al Writes If HADDR 1 0 01 DATA Writes If HADDR 1 0 10 DATA N N If HADDR 1 0 11 DATA DO
215. bytes When 1 this channel is defined to be a high priority channel When asserted clears the CH COMP B bit in the CHx STATUS REG and the BUFFER STATUS for this buffer B in this channel x This causes DMAINTERRUPT to negate if not being held asserted by another channel This bit always reads back as zero When asserted clears the CH COMP A bit in the CHx STATUS REG and the BUFFER STATUS for this buffer A in this channel x This causes DMAINTERRUPT to negate if not being held asserted by another channel This bit always reads back as zero When 1 completion on this channel causes DMAINTERRUPT to assert When 0 DMA completions for this channel do not cause assertion of DMAINTERRUPT When 1 resets this channel Always read backs as 0 When 1 pauses the transfer for this channel until set to 0 This field determines the data width of each DMA transfer cycle for this DMA channel 0b00 Byte 0601 Half Word 0b10 Word 0611 reserved If PERIPHERAL 1 then this bit is valid When transfers are from peripheral to memory When transfers are from memory to peripheral When 0 this channel is configured for memory to memory When 1 this channel is configured for peripheral DMA Revision 1 43 ______________ Peripheral DMA PDMA PERIPHERAL_SEL Table 3 6 PERIPHERAL_SEL From _0 receive to any MSS memory mapp
216. cates valid data for the PHY on the TXD port MAC_MDC Out management clock 25 MHz This signal is driven by the CSR9 16 bit MAC_TXD 1 0 Out 2 Transmit data The TXD 0 signal is the least significant bit MAC_CLK Rie 50 MHz 50 ppm clock source shared with RMII PHY Revision 1 177 ________________ Ethernet Frame Data and Descriptors Descriptor Data Buffer Architecture Overview A data exchange between the host and Ethernet MAC is performed via the descriptor lists and data buffers which reside in the system shared RAM eSRAM 0 eSRAM 1 External RAMs connected through EMC or FPGA block SRAM The buffers hold the host data to be transmitted or received by Ethernet MAC The descriptors act as pointers to these buffers Each descriptor list should be constructed by the host in a shared memory area and can be of an arbitrary size There is a separate list of descriptors for both the transmit and receive processes The position of the first descriptor in the descriptor list is described by CSR3 for the receive list and by CSR4 for the transmit list The descriptors can be arranged in either a chained or a ring structure Figure 12 4 on page 179 and Figure 12 5 on page 180 In a chained structure every descriptor contains a pointer to the next descriptor in the list In a ring structure the address of the next descriptor is determined by CSRO 6 2 DSL descriptor skip length Every descript
217. ccess depending on the characteristics of the EMD and on the size of the access word half word or byte and the width of the data bus to the EMD An AHB access consists of an address phase and a data phase as shown in Figure 7 2 Address Phase Data Phase O S f HREADY V V Figure 7 2 AHB Address Data Phase Read Transfer Address Phase Data Phase Figure 7 3 Address Data Phase Write Transfer The EMC cannot complete EMD read and write transactions in only two FCLK cycles so the user must configure the EMC and insert wait states in the data phase of the AHB access to complete the EMD access Figure 7 4 shows an AHB read transaction with two wait states inserted into the data phase of the AHB transaction Address Phase i gt mk FP 1 P KKB 77 S Yd HREADY Figure 7 4 AHB Read Access with Two Wait States Revision 1 83 _________________ External Memory Controller The EMC uses the additional clock cycles to complete the EMD transaction Figure 7 5 illustrates an AHB transaction with three wait states and shows the EMD interface signals during the AHB data phase and how they are used to complete the EMD access Note that the AHB address phase will always be one FCLK cycle and the wait states are inserted into the data phase The figure il
218. ce We constantly monitor the email account throughout the day When sending your request to us please be sure to include your full name company name and your contact information for efficient processing of your request 393 Acte Product Support The technical support email address is tech actel com Phone Our Technical Support Center answers all calls The center retrieves information such as your name company name phone number and your question and then issues a case number The Center then forwards the information to a queue where the first available application engineer receives the data and returns your call The phone hours are from 7 00 a m to 6 00 p m Pacific Time Monday through Friday The Technical Support numbers are 650 318 4460 800 262 1060 Customers needing assistance outside the US time zones can either contact technical support via email tech actel com or contact a local sales office Sales office listings can be found at www actel com company contact default aspx 394 Actel POWER MATTERS Index Numerics SYS_TOPT 76 A ACE thresholds 367 Actel electronic mail 393 telephone 394 web based technical support 393 website 393 ADDR 120 266 addresses misaligned 80 AHB access timing diagrams 83 AHB bus matrix 15 arbitration 17 connections 16 functional description 15 masters and slaves 15 memory map 19 AHB to EMC transaction 84 AHB_MATRIX_CR 31 and 26 application develop
219. clear the bit write that was issued to the eNVM These are ECC2 ERROR 1 read only bits writes have no effect See Table 4 12 on page 65 ECC1 ERROR 1 OVER THRESH 1 0 Don t care 1 ENVM 1 reported error Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 1 accessed page over threshold Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 1 reported a programming error PROG ERROR 1 PROT ERROR 1 BUSY 1 M ILLEGAL CMD 0 Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 1 reported a protection error Write a 1 to this location to clear the bit 0 ENVM 1 is ready to read 1 ENVM 1 is busy This is a read only bit writes have no effect 0 Don t care 1 An illegal command has been issued to 0 Write 1 to this location to clear the bit ERASE ERROR 1 0 Don t care 1 ENVM 1 reported an erase error Write a 1 to this location to clear the bit BN Reserved R Revision 1 63 Actel Embedded Nonvolatile Memory eNVM Controller 64 Table 4 11 ENVM STATUS REG continued Bit Number ENVM STATUS 0 E OPDONEO RW ECC2 ERROR 0 These bits provide status information from the eNVM based upon the command and or write that was issued to the eNVM These are read only bits writes have no effect See Table 4 12 on page 65 0 Don t care 1 ENVM 0 has completed the co
220. d LVCMOS 1 5 V output threshold configured as 1 8 V LVCMOS 318 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide GPIN Source Select Register For the A2F200 GPIOs 16 through 31 are multiplexed between two IOMUXes This allows these GPIOs access to user signals from the fabric interface The GPIN_SOURCE_CR steers the user s signal from the fabric interface through the secondary IOMUX as shown in Figure 18 3 on page 320 For example for GPIN_16_SRC the input can be sourced from IOMUXCELL 0 41 Figure 18 3 on page 320 shows how two IOMUXes are configured in relation to bit GPIN 16 SRC This topology allows a user s logic signal from the fabric F2M 25 for instance to be read by the Cortex M3 via the GPIO16 input Table 18 6 lists the bit definitions for the GPIN SOURCE CR register F2M in this case means fabric to MSS signal direction and describes a signal sourced from the MSS driving into the FPGA fabric Table 18 6 GPIN SOURCE CR Mame GPIN 16 SRC o 0 IOMUX 0 1 IOMUX 41 GPIN 17 SRC o 0 IOMUX 1 1 IOMUX 42 GPIN 18 SRC o 0 IOMUX 2 1 IOMUX 43 19 SRC Rw o 0 IOMUX 3 1 IOMUX 44 M GPIN 20 SRC o 0 IOMUX 4 1 IOMUX 45 GPIN 21 SRC o 0 IOMUX 5 1 IOMUX 46 6 GPIN 22 SRC o 0 IOMUX 6 1 IOMUX 47 GPIN 23 SRC o 0 IOMUX 7 1 IOMUX 48 mM
221. d Design Environment IDE design flow if there are no FPGA fabric resources required by the user application The SmartFusion MSS must be configured to setup the MSS clocking scheme and configure any additional MSS peripherals desired to process a Timer interrupt The user firmware will then control these active peripherals so that they can perform the tasks required by the user application User application code can be developed and debugged using any of the three supported embedded software development tools Actel SoftConsole Keil Microcontroller Development Kit pVision and IAR Embedded Workbench Actel provides a set of MSS Timer drivers that can be generated from the MSS configurator or from the Actel Firmware Catalog These drivers are common for all three tool flows However the Cortex Microcontroller Software Interface Standard CMSIS access layer is dependent on the tool flow selected and should be chosen based on the specific tool flow being utilized The Actel MSS Timer drivers enable application code development without having to manually read and write the MSS System Registers to initialize configure and operate the timers The MSS configurator and Firmware Catalog also provide sample projects depicting the MSS Timer usage The MSS Timer drivers contain functions that allow the user to set up Timer1 and Timer2 independently or as a single 64 bit timer For additional driver specific details refer to the Actel SmartFusion
222. d and write data buses MSS AHB masters can perform byte half word and word accesses to an FPGA fabric AHB slave Misaligned accesses are not supported and result in invalid data transfers in registered mode The data transfer to the fabric proceeds as normal but HRESP is asserted to the MSS AHB master at the end of the transfer HRESP is not asserted if in bypass mode and the transfer proceeds as normal When no AHB slaves are programmed in the fabric MSSHREADY must be tied high SmartDesign will automatically tie this high if needed BL AH Decoder and Multiplexer AHBL AHBL Slave 0 Slave 1 Figure 19 5 MSS Master to AHB Fabric Slave Revision 1 347 Fabric Interface and IOMUX MSS Master to FPGA APB Slave Interface The fabric interface allows AHB masters in the MSS to communicate with the fabric as an APB v3 0 compliant slave as shown in Figure 19 6 The MSS master APB interface provides an interface to the fabric which on its own is suitable for connection to a single APB slave Users that require multiple APB slaves in the fabric must use the single MSSPSEL select signal provided to enable an additional address decoder to generate additional PSEL select signals one for each slave In addition the user is required to perform multiplexing of the APB PRDATA PSLVERR and PREADY signals from each instantiated slave to drive the single MSSPRDATA MSSPSLVERR and MSSPREADY input ports of the MSS master
223. d bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TXRXDFS Transmit and receive data size Maximum value is 32 Number of bits shifted out and received per frame count starts from 1 In National Semiconductor MICROWIRE mode this is the number of shifts to be done after the control byte is sent Note This Register must be set before SPI is enabled Writes to this register are ignored after SPI is enabled Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SPI Status Register STATUS Table 13 6 STATUS Bit Name Reset Value Description 31 12 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TXFIFOEMPNXT Transmit FIFO empty on next read TXFIFOEMP 1 Transmit FIFO empty TXFIFOFULNXT Transmit FIFO full on next write 8 TXFIFOFUL OR o Transmit FIFO full RXFIFOEMPNXT oR 9 Receive FIFO empty on next read RXFIFOFULNXT OR 9 Receive FIFO full on next write RXFIFOFUL R 9 Receive FIFO full TXUNDERRUN No data available for transmission The channel cannot read data from the transmit FIFO because the transmit FIFO is empty In reality this can only be raised in Slave mode because the Master will not attempt to t
224. d bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation General purpose timer expiration Gets set when the general purpose timer reaches zero value The user can clear this bit by writing a 1 Writing a 0 has no effect Early transmit interrupt Indicates that the packet to be transmitted was fully transferred into the FIFO The user can clear this bit by writing a 1 Writing a 0 has no effect Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Receive process stopped RPS is set when a receive process enters a stopped state The user can clear this bit by writing a 1 Writing a 0 has no effect Revision 1 203 Acte Ethernet MAC Table 12 29 CSR5 continued Receive buffer unavailable When set indicates that the next receive descriptor is owned by the host and is unavailable for Ethernet MAC When RU is set Ethernet MAC enters a suspended state and returns to receive descriptor processing when the host changes ownership of the descriptor Either a receive poll demand command is issued or a new frame is recognized by Ethernet MAC The user can clear this bit by writing a 1 Writing a 0 has no effect Receive interrupt Indicates the end of a frame receive The complete frame has bee
225. d by ARM These are the implementation specifics in the Actel SmartFusion device e Number of interrupts set to 150 151 including NMI 32 levels of interrupt priority Memory Protection Unit MPU The Data Watchpoint and Trace DWT unit is configured to include data matching The Embedded Trace Macrocell ETM is not included Revision 1 7 Acte ARM Cortex M3 Microcontroller The debug port is implemented using Serial Wire JTAG Debug Port SWJ DP rather than a Serial Wire Debug Port SW DP This enables either the JTAG or SW protocol to be used for debugging The SWJ DP defaults to JTAG mode at power up and can be switched to SW by applying a specific sequence to the debug pins The Trace Port Interface Unit TPIU is configured to support Instrumentation Trace Macrocell ITM debug trace only and not Embedded Trace Macrocell ETM debug trace The optional ETM is not included Also Serial Wire mode is used for the TPIU output data and this is overlaid on the JTAG TDO port Figure 1 2 One implication of this is that Instrumentation Trace cannot be used along with JTAG based debugging SW debugging and ITM can be used together SWV operates at 98 KHz The ROM table has not been modified and matches the description given in the Cortex M3 Technical Reference Manual e The deployment of Cortex M3 in SmartFusion combines the and D Code buses into single shared code bus This multiplexing occurs wi
226. d by the circuit in RC Network mode is determined by the RC time constant of the selected components as shown in Figure 8 15 on page 122 In all other modes the crystal oscillator is configured to support an external crystal or ceramic resonator These modes correspond to low medium and high gain They differ in the crystal or resonator frequency supported The crystal or resonator is connected to the MAINXIN and MAINXOUT pins Additionally a capacitor is required on both MAINXIN and MAINXOUT pins to ground as shown in Figure 8 14 on page 122 The recommended input capacitance is 22 pF The main crystal oscillator can be enabled and disabled by the Cortex M3 via the MSS CCC MUX CR bit 29 MAINOSCEN When the main crystal oscillator is not being used MAINXIN and MAINXOUT pins can be left floating Table 8 4 Main Oscillator Operational Modes MAINOSCMODE Bit E Clock Mode Function RC network oscillation mode Connect the RC network to the MAINXIN pad The MAINXOUT pad should be disconnected Low gain 0 32 to 0 20 MHz low power frequency mode Oscillator consumes the least current of the three crystal modes ER 0 20 to 2 0 MHz Standard crystal resonator 0 20 to 2 0 MHz Standard crystal resonator frequency High gain 2 0 to 20 0 MHz high EEG mode Oscillator consumes the most current of the three modes Off Chip VCCMAINXTAL PX ZN ER z Main Crystal MAINXOUT Oscillator ZN GNDMAIN
227. der sense circuit and an external pass transistor The regulator is powered from the 3 3 V supply and produces a 1 5 V regulated output which the user can connect to the VCC pin which powers the FPGA and the MSS on their PCBs If an existing 1 5 V rail is already available in the system the user can use it instead of the functionality provided by the internal VR The output of the VR is the PTBASE pin and supplies the drive signal for the external NPN pass transistor This output can source up to 20 mA in to the transistor s base The output current of the circuit depends on the current gain of the NPN pass transistor connected externally The PTEM pin is the sense input for the regulator and consists of a resistive voltage divider between the sense input and GND Actel recommends using PN2222A or 2N2222A transistors with the VR The logic diagram for the VR is shown in Figure 10 3 on page 153 The VR can be enabled from several sources the RTM_MATCH signal from the RTC block TRSTB 1 or triggered by 152 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide the PUPO signal from the VR Init block Once triggered the VR will remain on because of the latching functions of RS flip flops Q0 or Q1 Only the MSS or the FPGA fabric can reset these flip flops and turn off the VR The VR may also be turned off if VCC33 supply falls below the VCC33UP threshold and a reset occurs In summary the VR can be turned
228. despite the state of the AC flag 25 TER Transmit end of ring When set indicates the last descriptor in the descriptor ring Second address chained When set indicates that the second descriptor s address points to the next descriptor and not to the data buffer This bit is valid only when TDES1 25 transmit end of ring is reset Disabled padding When set automatic byte padding is disabled Ethernet MAC normally appends the PAD field after the INFO field when the size of an actual frame is less than 64 bytes After padding bytes the CRC field is also inserted despite the state of the AC flag When DPD is set no padding bytes are appended Filtering type This bit together with TDESO 28 FT1 controls the current filtering mode This bit is valid only when the TDES1 27 SET bit is set Revision 1 185 Acte Ethernet MAC Table 12 9 Control TDES1 Bit Functions continued Buffer 2 size Indicates the size in bytes of memory space used by the second data buffer If it is zero Ethernet MAC ignores the second data buffer and fetches the next data descriptor This bit is valid only when TDES1 24 second address chained is cleared Buffer 1 size Indicates the size in bytes of memory space used by the first data buffer If it is 0 Ethernet MAC ignores the first data buffer and uses the second data buffer Table 12 10 TBA1 TDES2 Bit Functions Transmit buffer 1 address Contains the ad
229. device to a known state and passes control to system boot System Boot System boot consists of the following steps 1 Cstartup code 2 Mapping of eNVM and optionally eSRAM to the desired address spaces 3 Initialization of the microcontroller subsystem MSS to a known state The user can write portions of the system boot code or use the Libero IDE MSS configurator to provide all the desired functionality of system boot The current version of the System Boot code can be read at location 0x60080840 User Boot User boot would be any custom code that does not accomplish the steps outlined in the automated system boot and is optional Revision 1 23 POCA Ct e AHB Bus Matrix AHB Bus Matrix Register Map Table 2 2 AHB Bus Matrix Register Map Register Name Address R W Reset Value Description ESRAM_CR 0xE0002000 RAV 0x0 Controls address mapping of the eSRAMs ENVM CR 0 0002004 R W 0x00000092 Configures eNVM parameters ENVM_REMAP_SYS_CR 0xE0002008 RAV 0x00080001 eNVM mapping in system space ENVM REMAP FAB CR OxE000200C RAV 0x0 eNVM mapping in fabric master space FAB PROT SIZE CR 0 0002010 RAV 0x0000001E Fabric protect size FAB PROT BASE CR 0xE0002014 RAV 0x0 Fabric protect base address AHB MATRIX CR 0 0002018 RAV 0 0 Configures the bus matrix MSS SR OxE004201C R 0x0 MSS status bits CLR MSS SR OxE0002020 0 0 Clear the MSS status bits AHB Bu
230. dicates that the second buffer s address points to the next descriptor and not to the data buffer Note RER takes precedence over RCH Buffer 2 size Indicates the size in bytes of memory space used by the second data buffer This number must be a multiple of four If it is 0 Ethernet MAC ignores the second data buffer and fetches the next data descriptor This number is valid only when RDES1 24 second address chained is cleared Buffer 1 size Indicates the size in bytes of memory space used by the first data buffer This number must be a multiple of four If it is 0 Ethernet MAC ignores the first data buffer and uses the second data buffer Table 12 5 RBA1 RDES2 Bit Functions Bits Name Function 31 0 RBA1 Receive buffer 1 address Indicates the length in bytes of memory allocated for the first receive buffer This number must be 32 bit word aligned RDES2 1 0 0600 Table 12 6 RBA2 RDES3 Bit Functions Function Receive buffer 2 address Indicates the length in bytes of memory allocated for the second receive buffer This number must be 32 bit word aligned RDES3 1 0 0b00 Table 12 7 to Table 12 11 on page 186 give bit descriptions and functions for the transmit descriptors Table 12 7 Transmit Descriptors TDESx STATUS TBS2 TBS1 Note The TDESx descriptors reside in receive data memory They can be defined and addressed under software control
231. dress of the first data buffer For the setup frame this address must be 32 bit word aligned TDES3 1 0 0b00 In all other cases there are no restrictions on buffer alignment Table 12 11 TBA2 TDES3 Bit Functions ms mme mon 31 0 TBA2 buffer 2 address Contains the address of the second data buffer There are no restrictions on buffer alignment 186 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MAC Address and Setup Frames The setup frames define addresses that are used for the receive address filtering process These frames are never transmitted on the Ethernet connection They are used to fill the address filtering RAM Following are the requirements for the setup frame Avalid setup frame must be exactly 192 bytes long and must be allocated in a single buffer that is 32 bit word aligned e TDES1 27 setup frame indicator must be set Both TDES1 29 first descriptor and TDES1 30 last descriptor must be cleared The FT1 and FTO bits of the setup frame define the current filtering mode Table 12 12 lists all possible combinations Table 12 13 shows the setup frame buffer format for perfect filtering modes Table 12 14 on page 188 shows the setup frame buffer for imperfect filtering modes The setup should be sent to Ethernet MAC when Ethernet MAC is in stop mode A setup frame with more than 192 bytes can be written into the address filtering RAM to ini
232. dresses the multicast addresses and the broadcast addresses If the first bit of the address IG bit is 0 the frame is unicast dedicated to a single station If the first bit is 1 the frame is multicast destined for a group of stations If the address field contains all ones the frame is broadcast and is received by all stations on the LAN When Ethernet MAC operates in perfect filtering mode all frames are checked against the addresses in the address filtering RAM The unicast multicast and broadcast frames are treated in the same manner When Ethernet MAC operates in the imperfect filtering mode the frames with the unicast addresses are checked against a single physical address The multicast frames are checked using the 512 bit hash table To receive the broadcast frame the hash table bit corresponding to the broadcast address CRC value must be set Ethernet MAC applies the standard Ethernet CRC function to the first six bytes of the frame that contains a destination address The least significant nine bits of the CRC value are used to index the table If the indexed bit is set the frame is accepted If this bit is cleared the frame is rejected The algorithm is shown in Figure 12 11 802 3 Frame Destination Address CRC Generator 47 0 47 98 0 512 Bit Hash Tabl Bit Hash Table Address Hash Table Index One Physical Address Figure 12 11 Filtering with One Physical Address and the Hash Table It is importan
233. e fyg feika x m n x v EQ 8 2 faic x m n x w EQ 8 3 Dividers u v and w correspond to the fields OADIV OBDIV and OCDIV in the MSS CCC DIV CR control register The Libero IDE MSS Configurator provides a user friendly method of generating the PLL settings which includes automatically setting the division factors to achieve the closest possible match to the requested frequencies The settings are used by the system startup code to initialize the MSS to a known state Since the five output clocks share the n and m dividers the achievable output frequencies are interdependent and related according to EQ 8 4 feta fai x v 7u faic x w u EQ 8 4 Programmable Delay Elements There are a total of seven configurable delay elements implemented in the CCC architecture Two of the delays are located in the feedback path System Delay and Feedback Delay System Delay enabled by the XDLY control bit provides a fixed delay of 2 ns typical and Feedback Delay set by the FBDLY field in MSS CCC DLY CR provides selectable delay values from 0 535 ns to 5 56 ns in 200 ps increments typical For PLLs delays in the feedback path will effectively advance the output signal from the PLL core with respect to the reference clock Thus the System XDLY and Feedback FBDLY delays generate negative delay on the output clock Additionally each of these delays can be independently bypassed if necessary At each global multi
234. e enabled on both the MSS UART peripheral and the Cortex M3 Interrupt Controller NVIC It is important to note that before the transmit data buffer be cleared or overwritten the user must confirm that the UART data has been moved from the data buffer to the UART s transmit FIFO by calling the function MSS UART tx complete This function returns zero when the transfer is complete The following example shows usage of these two companion functions Example MSS UART in Interrupt Driven Mode amp g mss uartO0 UART Instance being addressed tx buff Pointer to transmit data buffer sizeof tx buff Size of the data to be transmitted Check whether UART 0 data has been moved to TX FIFO while 0 MSS UART tx complete amp g mss uart0 7 Polled Receive Method In the polled receive mode the MSS UART driver function MSS UART get rx is called in a loop or at a regular interval to check for data received in the RX FIFO of the MSS UART The function returns the number of bytes that were copied into the receive data buffer and returns 0 if no data has been received The following example shows usage of this function Example While 1 rx size MSS_UART_get_rx amp g mss uartO0 UART Instance rx buff Pointer to receive data buffer sizeof rx buff Size of the data receive buffer di Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Interrupt
235. e ARM Cortex M3 is up and running the firmware can choose to reconfigure the MSS_CCC to supply the processor clock via the GLAO output of MSS_CCC Revision 1 109 __________________ PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators The GLAO output of the MSS CCC block drives the input clock to the microcontroller subsystem MSS The clock source for the 10 100 Ethernet MAC can be sourced from an external pin or the GLC output of the MSS CCC block and the GLA1 and GLB outputs are dedicated to the FPGA fabric As depicted in Figure 8 2 the MSS CCC block consists of the following main components input clock multiplexers PLL dividers and delays There are three main paths through the MSS CCC block the CLKA CLKB and the CLKC paths which output clocks onto the global buffers GLA GLB and GLC As can be seen in more detail in Figure 8 3 there are actually two more outputs from the PLL CCC block The YB and YC outputs can drive additional local routing resources in the FPGA fabric Figure 8 6 depicts a simplified view of the CCC blocks without a PLL CLKA Inputs GLA Outputs GLB Outputs GLC Outputs CLKB Inputs Dividers Inputs Figure 8 2 Simplified View of MSS CCC Block RXASEL DYNASEL GLAO SZ x STATASEL GLMUxcFG PAO t5 Mss 5 7 CLKA GLMUXSEL PAS GLA1 RC Osc DIYAT to FPGA Main Osc 3 Fabric Glitchless MUX FBSEL Fabric x x
236. e RTCMATCHEVENT signal 160 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 10 5 DEVICE SR 31 7 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation FPGAGOOD When 0 FPGA fabric is not programmed In this state all inputs from the FPGA fabric to the MSS are guaranteed to be low and outputs from MSS to FPGA fabric can be driven to any value When 1 FPGA fabric is programmed In this case outputs from the MSS to the fabric may be driven normally and inputs from the fabric to the MSS may be interpreted as valid This bit also indicates the FPGA fabric is powered up 0 Powered down or not programmed 1 Powered up and programmed The reset value of this bit depends on whether or not the FPGA has been programmed FPGAPROGRAMMING 0 Indicates the FPGA fabric is not in 2 Indicates the FPGA fabric is in programming 1 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation BROWNOUT3_3VN 0 3 3 V supply has fallen below 2 5 V 1 3 3 V supply okay The reset state depends on the state of the 3 3 V power supply BROWNOUT1_5VN x 0 1 5 V supply has fallen below 1 3 V The reset state d
237. e SPI controller has no built in timer For applications where there is a possibility of a slave going to sleep for a long time or in the case of very long transfers the application should use one of the SmartFusion on chip timers Refer to the System Timer section on 301 for more information National Semiconductor MICROWIRE Protocol The National Semiconductor MICROWIRE serial interface is a half duplex protocol using a master slave message passing technique Each serial transmission begins with an 8 bit control word during which time no incoming data is received After the control word is sent the external slave decodes it and after waiting one serial clock cycle from the end of the control word responds with the required data which may be of a length of 4 to 16 bits Single Frame Transfer SPI X CLK SPI X SS Control ae ege C COG i 4 to 16 Bits Output Data SPI X OEN Figure 13 7 National Semiconductor MICROWIRE Single Frame Transfer In this mode the most significant byte of the FIFO transmit word is the control byte The total data frame size supplied must be at least 12 bits long 8 bits for the control word and a minimum of 4 bits for data payload Only the output data is sampled and inserted in the receive FIFO 228 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Multiple Frame Transfer SPI X CLK SPI X SS SPI X DI
238. e cases Weighted Round Robin Arbitration The user can configure arbitration by setting the bit COM WEIGHTEDMODE in the AHB MATRIX CR to operate as weighted round robin In this mode the slave arbiter for every slave operates on a round robin basis with three of the master interfaces Cortex M3 I Code D Code interface Cortex M3 system interface and the Ethernet MAC having a maximum of eight consecutive access opportunities to the slave in each round of arbitration Revision 1 17 Acte AHB Bus Matrix This scheme is illustrated in Figure 2 3 Eight Opportunities max MasterO Cortex M3 D Code HMASTLOCK1 Master1 Cortex M3 System Master4 PDMA Eight Opportunities max Master2 Fabric Master Master3 Ethernet MAC HMASTLOCK2 Eight Opportunities max Figure 2 3 Weighted Round Robin Arbitration Weighted round robin arbitration allows more efficient usage of slave bandwidth in the cases where the slaves have a penalty when transitioning from one master to another For example in situations where both the Ethernet MAC and Cortex M3 Code D Code interfaces are performing write and read AHB bursts to eSRAM this scheme groups together a maximum of eight Ethernet MAC accesses followed by a maximum of eight Cortex M3 accesses even if AHB bursts of greater than eight transfers are in progress from the master s point of view Due to
239. e counter When the counter next reaches zero the new value the TIMxXLOADVAL REG register which was loaded via the TIMXBGLOADVAL REG register will be used to reinitialize the counter One Shot Mode One Shot mode is selected by setting the TIMxMODE bit in the TIMx CTRL register to 1 In One Shot mode the counter will stop on reaching zero and a single interrupt will be generated When the counter is stopped in One Shot mode it can be restarted by writing a non zero value to the TIMxLOADVAL REG register Alternatively the counter can be restarted by clearing the TIMxMODE bit This will cause the counter to be loaded with the value held in the TIMxLOADVAL REG register and to begin operating in Periodic mode While the counter is counting down it is possible to change the value of the TIMxMODE bit at any time without immediately affecting the operation For example if the counter is decrementing in One Shot mode and the TIMxMODE bit is cleared before the counter reaches zero the counter will begin to operate in Periodic mode on reaching zero Writing to the TIMxLOADVAL REG register at any time causes the counter to be loaded immediately with the value written and to continue counting down from the new value if enabled Writing to the TIMxBGLOADVAL_REG register in One Shot mode has no real effect unless you intend to switch to Periodic mode when or before the next interrupt occurs When in One Shot mode the value written to TIMxBGLO
240. e descriptor 010 Running waiting for the end of receive packet before prefetch of the next descriptor 011 Running waiting for the receive packet 100 Suspended unavailable receive buffer 101 Running closing the receive descriptor 110 Reserved 111 Running transferring data from FIFO to host memory Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 29 CSR5 continued Normal interrupt summary This bit is a logical OR of the following bits CSR5 0 Transmit interrupt CSR5 2 Transmit buffer unavailable CSR5 6 Receive interrupt CSR5 11 General purpose timer overflow CSR5 14 Early receive interrupt Only the unmasked bits affect the normal interrupt summary bit The user can clear this bit by writing a 1 Writing a 0 has no effect Abnormal interrupt summary This bit is a logical OR of the following bits CSR5 1 Transmit process stopped CSR5 5 Transmit underflow CSR5 7 Receive buffer unavailable CSR5 8 Receive process stopped CSR5 10 Early transmit interrupt Only the unmasked bits affect the abnormal interrupt summary bit The user can clear this bit by writing a 1 Writing a 0 has no effect Early receive interrupt Set when Ethernet MAC fills the data buffers of the first descriptor The user can clear this bit by writing a 1 Writing a 0 has no effect Reserved Software should not rely on the value of a reserve
241. e is no data in the FIFO then a transmit under run error TXUNDERRUN is generated This can be conditionally used to generate an interrupt In this event the transmission is assumed to have been lost and the application must catch the error and restart the transmission from the beginning Internally the transmit logic returns to an idle state and the entire transmission is deemed lost If the channel attempts to write to a receive FIFO which is already full then receive overflow error RXOVERFLOW is generated This can be conditionally used to generate an interrupt In this case the transmission continues but the data is now corrupted because a data frame is missing It is assumed that the software will clear the interrupt and recover possibly by reading from the receive FIFO to clear the source of the interrupt allowing more data to be received or even by halting the transmission and resetting the SPI controller There are no interrupts available to signal to the Cortex M3 that the transmit FIFO has overflowed or a read operation is attempted on an empty receive FIFO The SPITXRFM flag room for more and SPIRXAVAIL flag data ready to be read are assumed to be used only in DMA mode under the control of the DMA Engine which has its own interrupts and control mechanism SPI Clock Requirements The SPI 0 and SPI 1 peripherals are clocked by PCLKO on APB bus 0 APB PO and PCLK1 on APB bus 1 APB P1 respectively PLCLKO and PLCK1 are free runn
242. e value in the TIMxLOADVAL_REG register and begins counting down immediately 1 Timer x in One Shot mode If TIMxENABLE 1 when the counter reaches zero the counter stops counting To start the counter again the user must load TIMxLOADVAL_REG with a non zero value or set the Timer to Periodic mode by clearing to 0 Writing this register while the System Timer is set to 64 bit mode has no effect Reading this register while the System Timer is set to 64 bit mode returns the reset value 0 0 Timer x Enable 0 Timer 1 disabled 1 Timer 1 enabled Writing this register while the System Timer is set to 64 bit mode has no effect Reading this register while the System Timer is set to 64 bit mode returns the reset value Revision 1 307 ___________________ System Timer Timer x Raw Interrupt Status Register Table 17 6 TIMx RIS Bit Reset Number R W Value Description 31 1 Reserved RAV 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TIMx RIS RAV Timer x Raw Interrupt Status 0 Timer x has not reached zero 1 Timer x has reached zero at least once since this bit was last cleared by a reset or by writing 1 to this bit Writing a 1 to this bit clears the bit and the interrupt writing a zero has no eff
243. ecision band gap to create the VCC15GOOD signal The VCC15GOOD signal becomes high at approximately 1 3 V During a brownout condition VCC15GOOD will deassert around 1 3 V When the VCC15 supply drops below the specified 1 425 V minimum the SmartFusion MSS will continue to work up until the time VCC15GOOD deasserts When VCC15GOOD is approximately 1 3 V the eNVM will stop functioning and assert a busy signal to hold off the AHB bus matrix If VCC15GOOD reasserts the eNVM will release the AHB bus matrix and normal operation will resume The user can then trap this event with INTISR 1 BROWNOUT1_5V_IRQ This interrupt service routine must be executing out of internal eSRAM Alternatively the user can monitor the VCC supply with the ADC When it starts to drop below 1 425 V 1 5 V 1 5 x 5 issue a soft reset Revision 1 151 ____________________ Voltage Regulator VR Power Supply Monitor PSM and Power Modes 3 3 V Voltage Detector VCC33UP This block see Figure 10 4 on page 154 has a single input VCC33A and a single active High output VCC33UP When the supply is below threshold 2 to 2 5 V depending on process and temperature variables the output is Low a reliable Low if VCC33A is above approximately 0 5 V When is above this threshold the output is High A small amount of hysteresis is included in the voltage detector to reduce the possibility of oscillation VCC33UP is routed to the
244. ect Bit 8 Peripheral DMA master Bit 7 Ethernet MAC master Bit 6 Fabric master Bit 5 Cortex M3 system bus master Bit 4 Cortex M3 I Code D Code bus master Writing a 1 to this bit clears the interrupt signal BROWNOUTS 3VINT Writing a zero has no effect 0 No effect 1 Clear the BROWNOUT3_3VINT signal 2 CLRBROWNOUT1_5VINT B CLRWDOGTIMEOUTEVENT a CLRRTCMATCHEVENT 34 Revision 1 Writing a 1 to this bit clears the interrupt signal BROWNOUT1_5VINT Writing a zero has no effect 0 No effect 1 Clear the BROWNOUT1_5VINT signal Writing a 1 to this bit clears the WDOGTIMEOUTEVENT bit in the WDOG EVENT REG register Writing a zero has no effect 0 No effect 1 Clear the WDOGTIMEOUTEVENT Writing a 1 to this bit clears the bit in the RTC MATCH EVENT REG register Writing a zero has no effect 0 No effect 1 Clear the RTCMATCHEVENT 3 CLRBROWNOUT3 3VINT W Ww W W Ww W VActel POWER MATTERS 3 Peripheral DMA PDMA The offloads the ARM Cortex V M3 from data movement tasks from peripherals to memory memory to peripherals and memory to memory The block diagram of the PDMA is shown in Figure 3 1 AHB Bus Matrix APB Bus DMAINTERUPT AHB Interface 1 SPI 0 8 DMA Channels lt
245. ect Timer x Masked Interrupt Status Register Table 17 7 TIMx MIS Bit Reset Number R W Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TIMx MIS 0x0 Timer x masked interrupt status This read only bit is a logical AND of the TIMxRIS and TIMxINTEN bits The TIMERXINT output from the timer has the same value as this bit Writing to this bit has no effect Timer 64 Value Upper Register Table 17 8 TIM64 VAL 0 Bit Reset Number R W Value Description 31 0 TIM64 VAL U This register holds the current value of the upper 32 bits of the 64 bit count value for the System Timer This register is read only writes have no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value Timer 64 Value Lower Register Table 17 9 TIM64 VAL 1 Bit Reset Number R W Value Description TIM64 VAL L This register holds the current value of the lower 32 bits of the 64 bit count value for the System Timer This register is read only writes have no effect When reading from this register the upper 32 bits of the 64 bit counter is stored into TIM64 VAL U To properly read the 64 bit counter value the user must read from this register first then the TIM64 VAL U Reading this register while the System Ti
246. ed address 6 1 91 8 71 From any MSS memory mapped address to _0 transmit co From UART 1 receive to any MSS memory mapped address _ 1 1 From any MSS memory mapped address to UART 1 transmit 1 From SPI 0 receive to any 55 memory mapped address 1 9 From any MSS memory mapped address to SPI 0 transmit 1 1 From SPI 1 receive to any 55 memory mapped address wd From any MSS memory mapped address to SPI_1 transmit From to from FPGA fabric peripheral DMAREADY1 091 1 2 From to from FPGA fabric peripheral DMAREADYO Ho qw From any MSS memory mapped address to the ACE From the ACE to any 55 memory mapped address CHANNEL x STATUS Register Table 3 7 CHANNEL x STATUS Bit Number rumen 31 3 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation BUF SEL Rw When 0 buffer is used When 1 buffer B is used COMP B RAV Asserts when this channel completes its DMA Cleared by writing to CLR COMP B bit 8 in CHx CONTROL REG for this channel If INTEN is set for this channel then the assertion of CH COMP B causes DMAINTERRUPT to assert COMP A RAW Asserts when this channel completes its DMA Cleared by writing to CLR COMP A bit
247. ed on PLLLOCK This signal is also available to the FPGA fabric This indicates that the PLL lost lock This signal corresponds to IRQ23 in the Cortex M3 NVIC IRQ23 corresponds to bit location 23 in the 32 bit word at address location 0 000 100 This bit is read only and can be cleared by writing a 1 to the CLRPLLLOCKLOSTINT bit in the CLR MSS SR register 0 Don t care 1 PLL lost lock PLLLOCKINT This bit indicates that a rising edge event occurred on the PLLLOCK signal This indicates that the PLL is locked This signal corresponds to IRQ22 in the Cortex M3 NVIC IRQ22 corresponds to bit location 22 in the 32 bit word at address location 0 000 100 This bit is read only and can be cleared by writing a 1 to the CLRPLLLOCKINT bit in the CLR MSS SR register 0 Don t care 1 came into lock 8 4 COM ERRORSTATUS Each bit on this bus indicates if any accesses by the corresponding master on the AHB bus matrix resulted in either HRESP assertion by the slave to the AHB bus matrix HRESP assertion by the AHB bus matrix to that master in the case of blocked fabric master or was decoded by the AHB bus matrix as being unimplemented address space These register bits are sticky and are cleared by the writing one to the corresponding COM CLEARSTATUS bit in the CLR MSS SR register Bit definitions are as follows Bit 8 Peripheral DMA master Bit 7 Ethernet MAC master Bit 6 Fabric master Bit 5 Cortex M3 system bus ma
248. eee o fe e CAN 3 1 1L TdT Ps Towers IOMUX 64 Table 15 19 64 IOMUX 64 Ports NA ws ous a Lm I 9 wee w ewxwm 1 e ewxam 1 286 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 65 Table 15 20 IOMUX 65 E p er mai e eser pow I peus IOMUX 66 Table 15 21 IOMUX 66 IOMUX 66 Ports Pad Name ion IOMUX 66 CR __ IN B OUT B OEB Hum RN EU we ie d Em ewe s ewxes __ _ _ mE IOMUX 67 Table 15 22 IOMUX 67 Pad IOMUX 67 CR IOMUX 67 Ports Pad Name a 82 f Je wem 1 ewxem Revision 1 287 _________________ Universal Asynchronous Receiver Transmitter UART Peripherals IOMUX 68 Table 15 23 IOMUX 68 Pad IOMUX 68 Ports Pad Name Ports IOMUX 68 CR OUTA OUTA OEA IN B OUT B OEB ERE LL m o me a Em Dome 1L m ewm Ls IOMUX 69 Table 15 24 IOMUX 69 Pad IOMUX 69 Ports Pad Name Ports IOMUX 69 CR NA A
249. egister 0x80 Table 14 6 on page 257 e Cortex M3 writes the DATA register 7 bit slave address and 0 and then clears SI bit e C peripheral sends DATA register contents and then generates interrupt request The STATUS register contains 0x18 or 0x20 value depending on received ACK bit Table 14 6 on page 257 Transfer is continued according to Table 14 6 on page 257 250 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide While in a master mode the arbitration logic checks that every transmitted logic 1 actually appears as a logic 1 on the bus While in Master Transmitter mode if another device on the bus overrules a logic 1 and pulls the data line low arbitration is lost and the 12 peripheral immediately changes from Master Transmitter mode to Slave Receiver mode The synchronization logic synchronizes the serial clock generator block with the transmitted clock pulses coming from another master device The arbitration and synchronization logic also utilizes timeout requirements set forth in the SMBus Specification Version 2 0 Figure 14 2 depicts a PMBus example using the Cortex M3 2 and MSS GPIO PMBus protocols are run through the serial bus and the additional PMBus control signal is routed through the MSS GPIO The firmware to control the PMBus control signals must be written by the user SMBus devices may also be linked to the same bus as shown SMBus and PMBus Host Controller Master Sla
250. el POWER MATTERS 7 External Memory Controller This section describes the external memory controller available only on Actel SmartFusion devices A2F200 and A2F500 Main Features The EMC provides a glueless interface to external memories Memory types supported are asynchronous memories and synchronous SRAMs The EMC is mapped into system address space from 0x70000000 to 0x77FFFFFF The EMC has the following features 2 chip selects each addressing 64 MBytes of address space Programmable timing for each chip select 8 bit or 16 bit shared data bus Asynchronous memories supported Static random access memory SRAM NOR flash memory PSRAM Synchronous memories supported Synchronous static random access memory SSRAM Write enable and byte lane support Translates 32 bit AHB transactions into successive half word and byte transactions Automatic translation of misaligned addresses Naming Convention Throughout this section a lower case x is used as a placeholder in a register name or signal to signify either a 0 or 1 which corresponds to chip select 0 or 1 Revision 1 81 External Memory Controller Block Diagram VActel The EMC primarily exists to interface with off chip memory devices that can be addressed by the MSS or user logic in the FPGA fabric It appears as a slave on the AHB bus matrix as shown in Figure 7 1 AHB Bus Matrix EMC Slave Interface HSEL HADDR 24 0 HSIZE
251. el 5 buffer B source address Channel 5 Channel 5 buffer B source address B source address Sa 5 BUFFER B DST ADDR 0x400040D8 Channel 5 buffer B destination address CRANE RUHK T TRANSFER COUNT Rw S Chane Safer 8 vans cunt __________ mw Chanel __ _ i Chanel stats eps CHANNEL 6 BUFFER SRCADDR ____ 6 BUFFER A SRC ADDR 0 400040 8 0 Channel 6 buffer A source address Channel 6 Channel 6 buffer A source address address ANNES 6 BUFFER A DST ADDR 0x400040EC Channel 6 buffer A destination address CHANNEL 6 BUFFER A TRANSFER COUNT 0 400040 0 RW Channel 6 buffer A transfer count CHANNEL 6 BUFFER B SRC ADDR 0 400040 4 Rw Channel 6 buffer B source address CHANNEL 6 BUFFER B DST ADDR 0x400040F8 E Channel 6 buffer B destination address 40 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 3 2 Memory Map continued Reset Register Name Address R W Value Description CHANNEL 6 BUFFER B TRANSFER COUNT 0 400040 Channel 6 buffer B transfer count CHANNEL 7 CTRL 0x40004100 RW 0 Channel 7 Control Register CHANNEL 7 STATUS 0x40004104 R Channel 7 Status Register CHANNEL 7 BUFFER A SRCADDR ____ 7 BUFFER A SRC ADDR 0x40004108 RW 0 7 buffer A source address Channel 7
252. enamed to the PDMA Mode section A note regarding SPI x SS 7 1 was added to Table 13 1 e SPI Interface 223 Signals SPI x SS was changed to SPI x SS 0 in the SPI Status at Reset section The SPI Clock Requirements section was revised to state that the input 224 clock to the SPI controller SPICLK can not be faster than one twelfth of PCLKO or PCLK1 The definitions of the modes for timing diagrams in the SPI Data Transfer Protocol Details section were revised Table 13 2 Motorola SPI Transfer Modes was revised accordingly The description was revised in Table 13 11 SLAVE SELECT and a note was added to the table 237 Table 13 14 SPI Signal GPIO and Fabric Mapping was revised Signals were deleted for IOMUX 60 through IOMUX63 in Table 13 15 e SPI Extra Signal GPIO and Fabric Mapping The signal names for IOMUX70 through IOMUX76 were changed from SPI O0 SS x to SPI 1 SS x 60 through IOMUX 63 were deleted These buffers are not connected to the MSS or fabric Bit 3 in Table 15 10 FCR was changed from reserved to ENABLE TXRDY RXRDY The GPIOCFG x register was renamed to GPIO x CFG throughout the N A document OE A was changed from GND to High in Table 18 11 IOMUX 4 322 The Functional Description section was revised to include information 352 about the MSS to fabric soft interrupt assertion Table 19 28 IOMUX to Peripheral Association was revised to remove IOMUXes 57 6
253. entire eNVM array in a high speed pipelined sequential fashion as indicated in Figure 4 9 on page 54 and Figure 4 10 on page 54 The same functionality pertains to the spare pages section Aux block array section and Aux block spare pages section when READ NEXT is set Table 4 5 Busy Cycles Between Consecutive Block Reads When READ NEXT 1 and Block Buffer is Not Drained HREADY Low Cycles Number of Reads from Block Buffer ENVM PIPE BYPASS 1 ENVM PIPE BYPASS 0 Read Next operation is enabled by setting the READ NEXT bit in the ENVM x CR 0 1 register For SmartFusion devices with two eNVM blocks it is possible to have one eNVM in Read Next mode and the other in normal Read mode Read Next mode can by modified dynamically Figure 4 9 eNVM Read Next Enabled ENVM SIX CYCLE 0 and ENVM PIPE BYPASS 0 SEQ Block Address Figure 4 10 eNVM Read Next Enabled ENVM SIX CYCLE 0 and ENVM PIPE BYPASS 1 SEQ Block Address 54 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Write Operations program and erase operations to the eNVM occur from the page buffer Writes to the page buffer can be byte half word or words Writing to the eNVM s page buffer does not start a program or erase operation Specific command sequences in the eNVM controller memory space must be issued to start a program or erase operation These commands are listed in Table 4 8 on page 61 The eNVM Co
254. epends on the state of the 1 5 V power supply 1 1 5 V supply okay Revision 1 161 ___________________________ Acte Voltage Regulator VR Power Supply Monitor PSM and Power Modes Table 10 6 VRPSM CR Bit Reset Number R W Value Function 31 5 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation BGPSMENABLE 0 Allow the BG and PSM to be turned off BG and PSM will then controlled by the ABPOWERON bit ANA COMM CTRL or the ENVM SR bit in SOFT RST CR 1 Turn on the BG and PSM Reserved Reserved CLR PU NINT Writing a one generates a pulse which clears the PU NINT interrupt FPGAVRONENABLE RAV Fabric VR On FPGAVRON signal qualifier When FPGAVRONENABLE 1 FPGAVRON from the fabric is allowed to shut down the VR When FPGAVRONENABLE 0 FPGAVRON from the fabric cannot cause the VR to shut down MSSVRON RAV By pulsing this signal from low to high to low firmware will cause the VR to turn off This has the effect of switching off the power to the MSS and the FPGA fabric 162 Revision 1 Actel POWER MATTERS 11 Watchdog Timer The Watchdog timer is an advanced peripheral bus APB slave that guards against system crashes by requiring that it is regularly serviced by the ARM Cortex M3 processor or by a processor in the FPGA
255. er Name Access Bit Address Address R W Value Description RBR 0 0x40000000 0x40010000 R Buffer Register THR 0 0x40000000 0x40010000 Ww Transmit Holding Register DLR 1 0x40000000 0x40010000 RAV 0x01 Latch LSB Register DMR 1 0x40000004 0x40010004 RAV 0 Divisor Latch MSB Register IER 0 0x40000004 0x40010004 RAV 0 Interrupt Enable Register 0x40000008 0x40010008 R OxC1 Interrupt Identification Register FCR 0x40000008 0x40010008 W 0 FIFO Control Register LCR 0 4000000 0 4001000 RAW 0 Line Control Register MCR 0x40000010 0x40010010 RAV 0 Modem Control Register LSR 0x40000014 0x40010014 R 0x60 Line Status Register MSR 0x40000018 0x40010018 R 0 Modem Status Register SR 0x4000001C 0x4001001C R W 0 Scratch Register Revision 1 275 Actel Universal Asynchronous Receiver Transmitter UART Peripherals 276 Receive Buffer Register RBR Table 15 3 RBR Bit Reset Number Name R W Value Description 7 0 RBR R This register holds the receive data bits for UART x The reset value is unknown since the register is loaded with data in the Receive FIFO Bit 0 is the LSB and is the first bit received The divisor latch access bit DLAB bit 7 of LCR must be 0 to read this register This register is read only writing to this register with the DLAB 0 changes the THR register value Transmit Holding Register
256. er must use MSS I Os to interface to external memories Since there are two SPI controllers in the MSS the user can dedicate one to an SPI flash and the other to the particulars of an application The amount of flash memory required to program the FPGA always exceeds the size of the eNVM block that is on chip The external memory controller EMC cannot be used as an interface to a memory device for storage of a bitstream because its I O pads are FPGA I Os hence they are tristated when the FPGA is in a programming state 374 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Re Programming the eNVM Blocks Using the Cortex M3 In this mode the Cortex M3 is executing the eNVM programming algorithm from eSRAM Since individual pages 132 bytes of the eNVM can be write protected the programming algorithm software can be protected from inadvertent erasure When reprogramming the eNVM both MSS I Os and FPGA 1 5 are available as interfaces for sourcing the new eNVM image Actel provides working example projects for SoftConsole IAR and Keil development environments These can be downloaded via the Actel Firmware Catalog Alternately the eNVM can be reprogrammed by the Cortex M3 via the IAP driver This is necessary when using an encrypted image Secure Programming For background refer to the Security in Low Power Flash Devices application note on the Actel website SmartFusion Secure ISP behaves identically to Fu
257. eral bus APB interface The APB registers are defined in the I2C x Register Map on page 255 Input signals are synchronized with the internal clock PCLKO for I2C 0 and PCLK1 for I2C 1 Glitches shorter than the glitch register length are filtered out The filter length is configurable from 3 to 6 clock periods Note that the 2 Fast Mode 400 kbps specification states that glitches 50 ns or less should be filtered out of the incoming clock and data lines Refer to the GLITCHREG Register section on page 268 for more details The address comparator checks the received 7 bit slave address with its own slave address It also compares the first received 8 bit byte with the general call address 0x00 If a match is found the STATUS register is updated and an interrupt is requested The 2 peripherals can operate in the following four modes 1 Master Transmitter mode Serial data transmitted via SDA serial clock transmitted via SCL 2 Master Receiver mode Serial data received via SDA serial clock transmitted via SCL 3 Slave Receiver mode Serial data and the serial clock received via SDA and SCL 4 Slave Transmitter mode Serial data transmitted via SDA serial clock received via SCL The programmable clock pulse generator provides the serial bus clock pulses when the IC peripheral is a master mode The clock generator is switched off when the 2 peripheral is in a slave mode Refer to the Clocks section on page 252 for deta
258. eration is performed in a predetermined manner because it does look ahead reads The general look ahead function is as follows e Within a page the next block fetched will be the current block address 1 When reading the last data block of a page it will fetch the first block of the next page When reading spare pages it will read the first block of the next sector s spare page Reads of the last sector will wrap around to sector 0 e Reads of Auxiliary blocks will read the next linear page s Auxiliary block When a block address becomes non sequential the current read operation must complete The time penalty for this access is anywhere from 9 to 12 cycles depending how ENVM SIX CYCLE and ENVM BYPASS are set and whether not the block buffer has drained completely If the next block to be addressed is the current block address 1 and the block buffer is completely drained the delay between block reads is one cycle For example if you read only one Revision 1 53 _________________________ _ Acte Embedded Nonvolatile Memory eNVM Controller data instruction from the block buffer there are four cycles of busy as shown in Table 4 5 As the block buffer is being read the eNVM controller is simultaneously reading the next block from the eNVM array Once initiated this transfer must complete hence the extra delay if the block buffer is not completely drained Read Next mode allows you access to the
259. ernal logic from its reset state 148 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 9 3 RST CR continued Bit Reset Number R W Value Function 15 SR RAV 1 0 Release the IAP controller from reset 1 Keep the IAP controller in reset 14 GPIO_SR RAV 1 0 Release the GPIOs from reset 1 Keep the GPIOs in reset 13 ACE SR RAV 0 Release the ACE from reset 1 Keep the ACE in reset 12 2 1 SR RAW 0 Release I2C 1 from reset 1 Keep I2C 1 in reset 11 2 0 SR RAW 0 Release 2 0 from reset 1 Keep I2C O in reset 10 SPI 1 SR R W 1 0 Release SPI_1 from reset 1 Keep SPI_1 in reset SPI_O_SR R W 1 0 Release SPI 0 from reset 1 Keep SPI O in reset UART 1 SR RAV 1 0 Release UART 1 from reset 1 2 Keep UART 1 in reset 7 UART 0 SR RAW 0 Release UART 0 from reset 1 Keep UART 0 reset TIMER SR RAV 1 0 Release the system timer from reset 1 Keep the system timer in reset 5 PDMA SR RAV 0 Release the PDMA from reset 1 Keep the PDMA in reset MAC SR RAV 0 Release the Ethernet MAC from reset 1 Keep the Ethernet MAC in reset 3 EMC SR RAV 1 0 Release the external memory controller from reset 1 Keep the external memory controller in reset 2 ESRAM 1 SR RAV 0 Release the ESRAM 1 memory controller from reset 1 Keep the ESRAM_1 memory controller in reset ESRAM 0 SR RAV 0 Release the ESRAM 0 memory controller from rese
260. ers CLR MSS SR OxE0042020 o anson 7 9 Provides device ee ats fermen 7 9 Prides sansaman _ m Table 10 3 MSS SR Bit Number Software should not rely on the value of a 31 11 Reserved reserved bit To provide compatibility with future products the value of a reserved bit PLLLOCKLOSTINT operation This bit indicates that a falling edge event occurred on PLLLOCK This signal is also available to the FPGA fabric This indicates that the PLL lost lock This signal corresponds to IRQ23 in the Cortex M3 NVIC IRQ23 corresponds to bit location 23 in the 32 bit word at address location 0 000 100 This bit is read only and can be cleared by writing a 1 to the CLRPLLLOCKLOSTINT bit in the CLR MSS SR register 0 Don t care 1 lost lock should be preserved across a read modify write PLLLOCKINT This bit indicates that a rising edge event occurred on PLLLOCK This signal is also available to the FPGA fabric indicating the PLL is locked This signal corresponds to IRQ22 in the Cortex NVIC IRQ22 corresponds to bit location 22 in the 32 bit word at address location 0 000 100 This bit is read only and can be cleared by writing a 1 to the CLRPLLLOCKLOSTINT bit in the CLR MSS SR register 0 Don t 1 locked Revision 1 157 ___________________ Voltage Regulator VR Power Supply Monitor PSM and Power Modes Table 10 3 MSS SR contin
261. es at 0x40005000 and extends to address 0x40005FFF in the Cortex M3 memory map Table 17 1 System Timer Register Map Reset Register Name Address R W Value Description 1 VAL VAL 0x40005000 R Current value of Timer 1 TIM1_LOADVAL TIMx_LOADVAL 0x40005004 Load value for Timer 1 TIM1_BGLOADVAL TIMx_BGLOADVAL 0x40005008 Background load value for Timer 1 TIM1 CTRL TIMx_CTRL 0x4000500C Timer 1 Control Register TIM1 MIS MIS 0x40005014 R 0x0 Timer 1 masked interrupt status TIM2_VAL TIMx_VAL 0x40005018 R 0x0 Current value of Timer 2 TIM2_LOADVAL TIMx_LOADVAL 0x4000501C Load value for Timer 2 TIM2 BGLOADVAL TIMx BGLOADVAL 0x40005020 Background load value for Timer 2 2 CTRL TIMx CTRL 0x40005024 Timer 2 Control Register TIM2 MIS TIMx MIS 0x4000502C R 0x0 Timer 2 masked interrupt status TIM64_VAL_U 0x40005030 R Upper 32 bit word in 64 bit mode VALL __________ VAL L 0x40005034 R 0x0 Lower 32 bit Lower 32 bit word in 64 bit mode in 64 bit mode LE aae LOADVAL_U 0 40005038 RAV 0 0 Upper 32 MM load value word in 64 bit mode TITM64 LOADVAL L 0 4000503 0 0 Lower 32 bit load value word in 64 bit mode TIM64 BGLOADVAL U 0x40005040 RAW 0 0 Upper 32 bit background load value 64 bit mode TIM64 BGLOADVAL L 0 40005044 RAV 0 0 Lower 32 bit background load value 64 bit mode TIM64 CTRL
262. es being used as write enables usage depends on device and configuration SmartFusion GS78108AB GS78108AB EMC CLK HSEL A 19 0 HADDR 26 0 EMC AB 25 0 QI 7 0 HSIZE 1 0 HTRANS 1 HWDATA 31 0 External Memory HWRITE Controller Block HREADY EMC EMC CS 1 0 N EMC RW N EMC BYTE EN 1 0 OEN 1 0 0 PAD OE 1 WDB 15 0 D EMC DB 15 0 PBS I 1 0 Block GS78108AB GS78108AB A 19 0 A 19 0 HRDATA 31 0 HREADYOUT FCLK HRESETn DQ 7 0 Q OE Figure 7 15 Asynchronous SRAMs Four Byte Wide EMDs Revision 1 93 External Memory Controller Actel The circuit of Figure 7 16 shows a synchronous SRAM half word address alongside and sharing the data bus with two byte wide asynchronous SRAM devices Again in this case the SmartFusion byte enable pins are connected to the write enable pins of the asynchronous SRAM external devices SmartFusion HSEL HADDR 26 0 HSIZE 1 0 HTRANS 1 HWDATA 31 0 HWRITE HREADY 31 0 HREADYOUT HRESP FCLK HRESETn External Memory Controller Block EMC EMC_CLK lt EMC_AB 25 0 EMC_AB 18 1 EMC_CS 1 0 _N Fl EMC RW N EMC BYTE EN 1 0 OEN 1 0 EMC PAD OE 1 WDB
263. es of PLL operation The PLL core is composed of a phase detector PD a low pass filter LPF and a four phase voltage controlled oscillator VCO Figure 8 7 illustrates a basic single phase PLL core with a divider and delay in the feedback path Voltage Phase Detector Low Pass Filter Controller Oscillator Divide by M Counter Figure 8 7 Simplified PLL with Feedback Divider and Delay The PLL is an electronic servo loop that phase aligns the PD feedback signal with the reference input To achieve this the PLL dynamically adjusts the VCO output signal according to the average phase difference between the input and feedback signals The first element is the PD which produces a voltage proportional to the phase difference between its inputs A simple example of a digital phase detector is an exclusive OR XOR gate The second element the LPF extracts the average voltage from the phase detector and applies it to the VCO This applied voltage alters the resonant frequency of the VCO thus adjusting its output frequency Consider Figure 8 7 with the feedback path bypassing the divider and delay elements If the LPF steadily applies a voltage to the VCO such that the output frequency is identical to the input frequency this steady state condition is known as lock Note that the input and output phases are also identical The PLL core sets a LOCK output signal High to indicate this condition Should the input frequency increase slightly the
264. ese signals and functionality are available for instantiation by Actel Libero Integrated Design Environment IDE FPGA design tool Table 19 29 32 SCB to FPGA Fabric Interface Signals to FPGA Fabric Function 368 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide DAC Signals As shown in Table 19 30 for each DAC there is a single bit data input and its associated clock Users can provide a custom input waveform to the first order SDD based on user logic The A2F200 device has two DACs and the A2F500 device has three DACs The DAC inputs are also capable of being driven from within the ACE as well Table 19 30 DAC Interface Signals Input To Output From FPGA Fabric FABSDDOD Data out from FPGA fabric driving the input to the SDD 0 FABSDDOCLK Clock for FABSDDOD VR PSM Signals Table 19 31 lists the interface signals between the VR PSM and the FPGA fabric The functionality of these signals is described in the Voltage Regulator VR Power Supply Monitor PSM and Power Modes section on page 151 Table 19 31 Voltage Regulator Power Supply Monitor Signals Input To Output From FPGA Fabric Function PUFAB N Push button inverted version of PU N pin FPGAVRON Output FPGA signal to turn on and off the VREG This bit is qualified by the FPGAVRONENABLE field in the in the VRPSM CR which is controlled by the Cortex M3 This prevents false triggering of FPGAVRON when the FP
265. ets to zero on power up and is released as soon as PORRESET N deasserts You have the option under software control to reset the eNVM controller by writing to the System Registers located on the private peripheral bus of the Cortex M3 Specifically System Register SOFT RST CR is located at address 0xE0042030 in the memory map ENVM_SOFTRESET control bit is encoded in bit location 0 as shown in Table 4 9 Table 4 9 SOFTRESET Control Bit DN eNVM controller reset released reset value eNVM controller held in reset Revision 1 61 Aoo Meter Embedded Nonvolatile Memory eNVM Controller Interrupts There is one interrupt signal per eNVM block that can be asserted based on the result of operations on the 5 IRQ7 is asserted when _0 5 ENVMO INT signal is raised and IRQ8 is asserted when _15 if it exists ENVM1_INT signal is raised Interrupts must be enabled for the particular response you are trying to trap within the eNVM controller by setting the appropriate bits in the ENVM ENABLE REG and also by setting the appropriate bits within the Cortex M3 NVIC Both interrupt enable bits within the are located at address 0 000 100 IRQ7 and IRQ8 correspond to bit locations 7 and 8 respectively Even if interrupts are disabled and the ECC2 ERROR x status bit is set the HRESP signal on the AHB bus matrix will assert If the bus master accessing the eNVM is the Cortex M3 the hard fault exce
266. ever it is possible to define a channel as being high priority For example the user may want to give higher priority to DMA channels corresponding to SPI peripherals than to those corresponding to UARTS as SPI has no built in flow control As a way of prioritizing traffic within the DMA the RATIOHILO field in RATIO HIGH LOW is used to indicate the ratio of high priority to low priority DMA access opportunities This register gives the number of DMA opportunities provided by the channel arbiter to high priority channels for every one opportunity provided to a low priority channel Table 3 1 describes valid values for RATIOHILO All other values are reserved RATIOHILO can only assume a value listed in the Value column of Table 3 1 Table 3 1 RATIOHILO Field Definition B E Rm Wiss Re For example RATIOHILO value of 3 1 means that if there are continuous high priority requests and low priority requests then there will be 3 high priority requests serviced to one low priority request There is an internal counter in the PDMA which takes its value from the RATIOHILO value When this internal counter reaches 0 low priority requests are allowed Each time a high priority Revision 1 37 Acte Peripheral DMA PDMA request is serviced the counter is decremented by 1 Each time a low priority request is serviced the internal counter is reset to the RATIOHILO value
267. evice after remote firmware initiated sequence of operations rather than clearing the interrupt in the local 2 itself WDOGTIMEOUTINT is always passed straight through the block as WDINT 352 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide There are two modes of operation in the FIIC ACE mode and non ACE mode In ACE mode ACE interrupt sources along with some MSS interrupt sources are processed by the FIIC In non ACE mode only MSS interrupts are processed by the FIIC ACE mode interrupt mapping is depicted in Table 19 6 and non ACE mode is depicted in Table 19 7 ACE mode is selected by setting the MODE bit in the FIIC MR to a 1 To assert the SOFTINTERRUPT MSSINT 2 the user must write a 1 to the SOFT IRQ CR in bit location 0 at address 0 004202 SOFTINTERRUPT stays asserted 1 as long as bit O of SOFT IRQ CR is a 1 Clearing bit O of SOFT IRQ CR deasserts the SOFTINTERRUPT MSSINT 2 signal Table 19 6 ACE Mode Interrupt Mapping WDOGWAKEUPINT BROWNOUT1_5VINT BROWNOUT3_3VINT MSSINT O RTCMATCHEVENT PUBINT MAC INT IAP INT ENVM 1 0 INT DMAINTERRUPT UART 0 INT UART 1 INT SPI 0 INT SPI 1 INT I2C O INT 2 0 SMBALERT I2C 0 SMBSUS 2 1 INT I2C 1 SMBALERT I2C 1 SMBSUS TIMER2INT PLLLOCKINT PLLLOCKLOSTINT SOFTINTERRUPT Table 19 7 Non ACE Mode Interrupt Mapping WDOGWAKEUPINT BROWNOUT1_5VINT BROWNOUT3_3VINT MSSINT O RTCMAT
268. evice has two identical SPI peripherals The letter x in register and signal descriptions is used as a placeholder for 0 or 1 indicating SPI 0 or SPI 1 Figure 13 1 shows a block diagram for the SPI controller APB Bus 5 REG Transmit FIFO 4 D x 32 W SPI x TXRFM __ gt SPI_x_CLK SPI_x_OEN Transmit SPI x MODE Logic SPI x DO SPI x RXAVAIL SPI x DI SPI x 55 0 Receive Logic Receive FIFO 40 X 32 W SPI_x_CLK SPISSSEL_REG SPI_x_SS 7 1 SPIMIS_REG SPIRXDATA_REG Figure 13 1 SPI Controller Block Diagram SPI Controller Functional Description SPI controller supports both Master and Slave modes of operation Revision 1 221 Acte Serial Peripheral Interface SPI Controller SPI Controller Block Diagram Figure 13 1 on page 221 shows the SPI Controller block diagram See Table 13 1 on page 223 for SPI interface signals definitions n Master mode SPI generates SPI x CLK selects a slave using SPI x SS transmits data on SPI x DO and receives data on SPI x DI e Slave mode SPI is selected by SPI x SS receives clock on SPI x CLK and incoming data SPI x DI SPI controller embeds two 4 x 32 depth x width FIFOs for receive and transmit These FIFOs are accessible through RX data and TX data registers Writing to the TX data register causes the data to be
269. evision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 1 5 SmartFusion Interrupt Sources continued mau Revision 1 13 Acte ARM Cortex M3 Microcontroller Table 1 5 SmartFusion Interrupt Sources continued 14 Revision 1 VActel POWER MATTERS 2 AHB Bus Matrix The AHB bus matrix ABM is a multi layer AHB matrix It is not a full crossbar switch but a customized subset of a full switch It works purely as an AHB Lite AHBL matrix The SmartFusion AHB Matrix has five masters and eight direct slaves as depicted in Figure 2 1 One master is permitted to access a slave at the same time another master is accessing a different slave If more than one master is attempting to access the same slave simultaneously then arbitration for that slave is performed Arbitration is programmable by the user and is either pure round robin or a weighted round robin where certain masters have favor over others One master is elected as the winner while the other masters are held up temporarily Theoretical maximum bus bandwidth through the AHB bus matrix is 16 Gbps This assumes that the five masters are communicating with five different slaves at the maximum clock rate of 100 MHz Functional Description Figure 2 1 depicts the connectivity of masters and slaves in the ABM Label nomenclature such as and MSO refers to a mirrored
270. f AHB Memory Space Memory Space gt 64M External Memory Space 81 24 23 16 15 8 7 0 0x70000007 0x70000004 31 24 23 16 15 8 7 0 0x70000003 0x70000000 7 0 0 00000000 Figure 7 8 Byte Wide External Memory Device Memory AHB Data H R W DATA 31 0 Address HADDR 31 0 EMC DB 15 8 DB 7 0 EMC AB 25 0 EMC AB 25 0 Ox77FFFFFF Ox77FFFFFC OxO3FFFFFF OxO3FFFFFE 31 24 23 16 15 8 7 0 Ox77FFFFFB 0x77FFFFF8 OxO3FFFFFD Upper 64M of 64M External AHB Memory Space Memory Space gt EMC_CS1_N gt 31 24 23 16 15 8 7 0 0 74000003 0x74000000 7 15 8 0x00000001 7 0 0 00000000 31 24 123 16 15 8 7 0 0x77FFFFFF Ox73FFFFFC 15 8 OxO3FFFFFF 7 0 OxO3FFFFE 0x03FFFFFD 7 0 OxO3FFFFFC Lower 64M of 64M External AHB Memory Space Memory Space gt 31 2411123 1611 115 8 17 01 0x70000007 0x70000004 50 ol 31 24 23 16 15 8 7 0 0x70000003 0 70000000 15 8 0x00000001 7 0 0 00000000 Figure 7 9 Halfword Wide External Memory Device Memory Map Using x8 EMDs Revision 1 87 Actel External Memory Controller AHB Data H R W DATA 31 0 AHB Address HADDR 31 0 EMC DB 15 8 EMC DB 7 0 AB 25 0 EMC AB 25 0 0x77FFFFFF Ox77FFFFFC OxO3FFFFFF OxO3FFFFFE 31 24 23 16 15 8 7 0 Ox
271. f lithium coin cell Integrated into SmartFusion is a battery switch over circuit Figure 8 16 which allows the user s application to use main power for powering the oscillator and RTC circuitry when main power is applied instead of battery power enabling extended battery life and operation The built in battery switch over circuit switches power to the RTC and low power 32 KHz oscillator between VCCLPXTAL and VDDBAT depending on which voltage is higher Figure 8 17 on page 124 EQ is used to determine which rail powers the low power 32 KHz oscillator and the RTC There is approximately 200 mV of hysteresis built into the switching from one rail to another If VCCLPXTAL VDDBAT 0 4 V then Vour VDDBAT Else Vout 2 VCCLPXTAL VCCLPXTAL Battery Switch Vour To RTC and Low Power 32 KHz Crystal Oscillator VDDBAT Figure 8 16 Battery Switch Over Circuitry Revision 1 123 VActel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators 3 3V X VCCLPXTAL ZN Battery Switch Over X VDDBAT ZN 7 Vour Real Time Counter RTC Off Chip X LPXIN dE saper LP 32 KHz Crystal To PLL CCC 2 LPXOUT Oscillator ZN C1 NA GNDLPXTAL Figure 8 17 Low Power 32 KHz Oscillator with Battery Switch and RTC PLL CCC Register Map The PLL CCC control registers are located in the System Registers address space at 0 0042000 and extend to address 0xE0042FFF in the Cortex M3 memory ma
272. fabric interface Table 12 42 MAC IO Interaction with Fabric and IOMUxes memo _ MAC CRSDV MAC RXER MAC MDIO MAC MDC Table 12 43 through Table 12 51 on page 219 give the descriptions for all IOMUXes associated with the Ethernet MAC IOMUX 16 Table 12 43 IOMUX 16 WAT oA me oure ois LLL mo 9 Ow ru omen LL Lm ewm owes 1 11 d IOMUX 17 Table 12 44 IOMUX 17 WAT Wa oes e lI 9 OF qwe ___ Jn 216 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 18 Table 12 45 IOMUX 18 IOMUX 18 Ports Pad Name Ports IOMUX 18 CR INA OUTA OEA INB OUTB OEB 1 ___ macaxooy OF meee SCC NE _ __ por wes IOMUX 19 Table 12 46 19 wes wem 9 m omer tT ft rome IOMUX 20 Table 12 47 20 Pad IOMUX 20 Ports Pad Name Ports IOMUX 20 CR OUT A IN B OUT B OEB M2F 4 p o MAGEN ____
273. faces to the AHB bus matrix On the FPGA side of the FIC the master and slave interfaces can be either AHB or APB Both interfaces on the fabric side always use the same protocol In other words one cannot be AHB while the other is APB as shown in Figure 19 3 Figure 19 3 Mismatched FIC Interfaces When implementing peripherals in the fabric these are the choices available but the first case is the most common 1 If you are using APB or APB3 peripherals for example CoreUARTapb use CoreAPB3 connected to the fabric interface 2 If you are using AHB peripherals use CoreAHBLite connected to the fabric interface 3 If you are using mixed AHB and APB peripherals use CoreAHBLite CoreAHB2APB3 CoreAPB3 Revision 1 343 Fabric Interface and IOMUX HADDR 19 0 HMASTLOCK HSIZE 1 0 HTRANS 1 0 HSEL HWRITE HWDATA 31 0 HRDATA 31 0 HREADY HREADYOUT HRESP HCLK 3 HRESETN APB32 AHBIF J APB16 XHOLD 15 0 AHB BYPASS HADDR 31 0 HMASTLOCK HSIZE 1 0 HTRANS 1 0 HWRITE HWDATA 31 0 HRDATA 31 0 HREADY HRESP Microcontroller Subsystem Master to Fabric Slave Fabric Interface Controller Fabric Master to Microcontroller Subsystem Slave Figure 19 4 Fabric Interface Control Signal List 344 Revision 1 VActel MSSHADDR 19 0 MSSHWDATA 31 16 MSSHWDATA 15 0 MSSHRDATA 31 16 MSSHRDATA 15 0 MSSHMASTLOCK MSSHSIZE 1
274. fers which conform to the Philips Inter Integrated Circuit v2 1 specification and support the SMBus v2 0 and PMBus v1 1 specifications The 12 peripherals use 7 bit addressing format and run up to 400 Kbps data rates nominally Faster rates can be achieved depending on the external load The 2 peripherals include the following features Data transfer in multiples of bytes e Multi master collision detection and arbitration e Own slave address and general call address detection e SMBus timeout and real time idle condition counters e Optional SMBus signals 2 x SMBSUS and 2 x SMBALERT controlled interface Block Diagram Figure 14 1 shows the block diagram for the 12 peripherals SlaveO Address Register Address Comparator Shift Register Input Glitch Filter I2C X SCLI B 5 Output 2C X SCLO ta a Arbitration and Synchronization Logic Input Glitch Filter 2C_X_SDAI 1 2C X SDAO Output Serial Clock Generator 2C X BCLK 2 X SMBA 2 X SMBUSU NI r gt 2C_X_SMBSUS_NO I2C X SMBS INT I2C X SMBALERT NI i 12 X SMBALERT NO Optional SMBus and Filtering Registers Figure 14 1 1 Block Diagram Revision 1 249 _________________ Inter Integrated Circuit Peripherals Functional Description The Cortex M3 processor accesses the 12 peripherals registers via the advanced periph
275. field of the ENVM STATUS REG to ensure the operation completed ENVM STATUS x 00 Yes Yes overwrites page Set to 0 buffer PROGRAM PAGE Command Writing 0x10 to the COMMAND field of the ENVM CONTROL REG programs the current buffer to the page in eNVM addressed by PAGE ADDRESS and leaves the page unprotected The page in eNVM is automatically erased prior to the copy from page buffer to eNVM The following conditions apply e Attempting to program a protected page using the PROGRAM PAGE command will result in a protection error The PROT ERROR x bit in the ENVM STATUS REG is set to 1 e Attempting to program a different page in eNVM from the page currently contained in the page buffer while PAGE LOSS 1 will result in a protection error The PROT ERROR x bit in the ENVM STATUS REG set to 1 Performing a PROGRAM PAGE command increments the write count for that page by one PROGRAM PAGE PROTECTED Command Writing Ox11 to the COMMAND field of the ENVM CONTROL REG programs the current page buffer to the page in eNVM addressed by PAGE ADDRESS and leaves the page write protected This is the same command as PROGRAM PAGE except the page is write protected in the process Also if you attempt to program a different page from the one in the page buffer with PAGE LOSS 0 the new page will be loaded in the page buffer and programmed with its protection bit set Performing a PROGRAM PAGE PROTECTED command increments the write count
276. for that page by one ERASE PAGE Command Writing 0x20 to the COMMAND field of the ENVM CONTROL REG erases the eNVM page addressed by PAGE ADDRESS If the page addressed by Page Address does not match the page in the page buffer and the PAGE LOSS bit is set the erase fails The erase also fails if the page is protected Performing an ERASE PAGE command increments the write count for that page by one Revision 1 59 ________________________ Embedded Nonvolatile Memory eNVM Controller ERASE PAGE PROTECTED Command Writing 0x21 to the COMMAND field of the ENVM CONTROL REG erases the current protected page addressed by Page Address and leaves the page write protected The page must be in an unprotected state prior to issuing this command Erasing a protected page will flag a protection error This is the same command as ERASE PAGE except the page is write protected in the process Performing an ERASE PAGE PROTECTED command increments the write count for that page by one OVERWRITE PAGE Command Writing 0x50 to the COMMAND field of the CONTROL REG overwrites the page addressed by Page Address with the contents of the page buffer If the destination page is protected no overwriting of the page occurs and the PROT ERROR x bit is set in the ENVM STATUS REG register This command can be used to move one eNVM page from one location to another Performing an OVERWRITE PAGE command increments the write count for that page by
277. from off chip The windows in which each occur are controlled by the reset controller state machine under control of firmware writes to SOFT 5 CR bits EXT SR and PADRESETENABLE Once the state machine comes out of reset it asserts resets for eight FCLK periods and then releases them all except for MSS RESET N OE which it continues to assert When firmware turns off EXT SR the state machine negates MSS RESET OE and moves to the next state where it waits for firmware to set PADRESETENABLE Firmware can tune this delay by moving to the next state to allow for any de bouncing of MSS RESET N to occur Finally when firmware sets PADRESETENABLE the state machine moves on to the IDLE state where it now monitors for the first time the state of MSS RESET N 1 If it sees MSS RESET assert it goes to the PRESTART state where the full reset sequencing starts again The only time that the assertion of MSS RESET N by an off chip source causes the MSS resets to assert is during this IDLE state This avoids any asynchronous loops in situations where the reset controller state machine itself is causing the assertion of MSS RESET N 146 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide The reset controller state machine is shown in Figure 9 3 ASYNCRESETMAIN PRESTARTO RE NEXT MSS RESET lt 1 MSS SYSTEM RESET N 0 M2 F RESET N FCLK lt M2 FRESET N FCLK RCOSC RESET N FCLK lt RCOSC RESET N FCLK
278. g ENVM 1 For example the main eNVM array ENVM 0 occupies address space 0x60000000 0x6003FFFF and the main eNVM array for ENVM 1 occupies address space 0x60040000 0x6007FFFF Table 4 3 eNVM Section Sizes Aux Block Aux Block eNVM Array array spare pages Total eNVM Bytes Bytes Bytes Bytes A2F500 52 4288 16 384 16 384 557 568 A2F200 64 262 144 8 192 8 192 278 784 Read Control Read operations for the eNVM can read from the block buffer the page buffer or the eNVM array Sector and page boundaries are not important when reading from the eNVM because the block address can be assumed to be contained in address bits 17 4 as shown in Figure 4 5 Read timing depends solely on block address boundaries Instructions data are presented to the AHB bus 32 bits at a time Depending on compiler optimizations either one or 2 instructions are fetched at a time 17 12 11 7 6 4 3 0 cdi iid TR Figure 4 5 Address Decoding for eNVM Read Operations e If the block addressed by a read operation is the same as that of the previous read or write operation the data is read from the block buffer e f the block addressed by a read operation has changed since the previous read write operation but the page addressed is the same as that of the previous write operation or unprotect page operation the read data originates from the page buffer If the page addressed by a read operation is not the same as that of the
279. gister IER Table 15 7 IER Bit Number Name R W Reset Value Description 7 4 Reserved R W 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 EDSSI RAV 0 Modem status interrupt enable 0 Disabled default 1 Enabled 2 ELSI RAV 0 Receiver line status interrupt enable 0 Disabled default 1 Enabled 1 ETBEI RAV 0 Transmit holding register empty interrupt enable 0 Disabled default 1 Enabled 0 ERBFI RAV 0 Receive data available interrupt enable 0 Disabled default 1 Enabled The divisor latch access bit DLAB bit 7 of LCR must be 0 to access this register Revision 1 277 ____________________ Universal Asynchronous Receiver Transmitter UART Peripherals Interrupt Identification Register IIR Table 15 8 IIR 0511 Always 0611 Enables FIFO mode Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 0 Interrupt 0b0001 0b0110 Highest priority Receiver line status interrupt due identification to overrun error parity error framing error or break bits interrupt Reading the Line Status Register resets this interrupt 0b0100 Second
280. greater than the value in WDOGLOAD Counter Value WDOGLOAD Refresh of counter not allowed while counter value is in this region Refresh of counter permitted while counter value is in this region WDOGMVRP Reset Interrupt generated due to counter refresh in forbidden window Reset Interrupt Time Counter Refresh lm generated due to counter timeout Figure 11 2 Watchdog Timer Windowing Example Watchdog Behavior with Processor Modes and Device Programming This section describes the behavior of the Watchdog in Cortex M3 processor modes and when the device is being programmed Cortex M3 Processor in Debug State The Watchdog counter is halted when the Cortex M3 processor enters the Debug state This ensures that Watchdog timeout related resets or interrupts do not occur when a system debug session is in progress Cortex M3 Processor in Sleep Mode The Cortex M3 processor can be put into a low power state by entering into a sleep mode The processor exits sleep mode when an interrupt occurs The Watchdog can be configured to generate an interrupt if its counter value moves from the forbidden to the permitted window at the WDOGMVRP level when the Cortex M3 is in sleep mode The processor will wake up and refresh the Watchdog and then go back into sleep mode The WDOGWAKEUPINT output from the Watchdog is used for this interrupt The WAKEUPINTEN control bit in the WDOGCONTROL register is
281. h is to be remapped to location 0x00000000 This logically splits eNVM into a number of segments each of which can be used to store a different firmware image COM ENVMREMAPSIZE is used to define the segment size for remapping of eNVM to Cortex M3 space and for remapping a segment of eNVM for a soft processor in fabric if one so desires SeeTable 2 8 on page 28 Revision 1 25 Bus Matrix VActel Table 2 5 Definitions of Bit Combinations for COM ENVMREMAPSIZE Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remap Size 0 0 0 0 0 Reserved 0 0 0 0 1 Reserved 0 0 0 1 0 Reserved 0 0 0 1 1 Reserved 0 0 1 0 0 Reserved 0 0 1 0 1 Reserved 0 0 1 1 0 Reserved 0 0 1 1 1 Reserved 0 1 0 0 0 Reserved 0 1 0 0 1 Reserved 0 1 0 1 0 Reserved 0 1 0 1 1 Reserved 0 1 1 0 0 Reserved 0 1 1 0 1 16 Kbytes 0 1 1 1 0 32 Kbytes 0 1 1 1 1 64 Kbytes 1 0 0 0 0 128 Kbytes 1 0 0 0 1 256 Kbytes 1 0 0 1 0 512 Kbytes reset value ENVM PIPE BYPASS and ENVM SIX CYCLE are used to control access behavior to the eNVM The latency of the initial access to a new eNVM page and the subsequent three accesses if initiated to the same eNVM page depends on the state of both ENVM PIPE BYPASS and ENVM SIX CYCLE The latencies number of FCLK cycles corresponding to the various combinations of ENVM SIX CYCLE and ENVM PIPE BYPASS are as shown in Table 2 6 Table 2
282. have three separate flash areas that be programmed 1 The FPGA fabric 2 The embedded nonvolatile memories eNVMs 3 The embedded flash ROM eFROM There are essentially three methodologies for programming these areas 1 In system programming ISP 2 In application programming IAP only the FPGA Fabric and the eNVM 3 Pre programming non ISP Programming whether ISP or IAP methodologies are employed can be done in two ways 1 Securely using the on chip AES decryption logic 2 In plain text In System Programming In System Programming is performed with the aid of external JTAG programming hardware Table 20 1 describes the JTAG programming hardware that will program a SmartFusion device and Table 20 2 defines the JTAG pins that provide the interface for the programming hardware Table 20 1 Supported JTAG Programming Hardware Program Program Program Dongle ES EE FPGA eFROM eNVM FlashPro3 4 Notes 1 SWD ARM Serial Wire Debug 2 SWV ARM Serial Wire Viewer Table 20 2 SmartFusion JTAG Pin Descriptions nn Test mode select The JTAGSEL pin selects the FPGA TAP controller or the Cortex M3 debug logic When JTAG SEL is asserted the FPGA TAP controller is selected and the TRSTB input into the Cortex M3 is held in a reset state logic 0 as depicted in Figure 20 1 Users should tie the JTAGSEL pin high externally Revision 1 373 POCA te SmartFusion Programming Note Standard ARM JT
283. he eSRAM address space into code space both eSRAM blocks are remapped In this case the two eSRAM blocks are remapped to appear at the bottom of Cortex M3 code space During this boot stage the actual runtime firmware is copied into eSRAM and the firmware then sets the EERAMFWREMAP bit in the ESRAM CR to 1 The resultant memory map is illustrated in Figure 2 6 on page 22 By allowing the Cortex M3 code bus to perform instruction fetches from the eSRAMS performance is improved The eSRAM remap is actually performed by aliasing the eSRAM blocks so that they appear in the code space but are still accessible in system space Therefore the system designer must manage eSRAM accesses in such a way that a portion of eSRAM allocated in one space the code space for example is left untouched in the other space system space for example In Figure 2 5 the Cortex M3 executes the application including ISRs from code space allowing optimal performance However the corresponding region in system space is grayed out Conversely the stack and heap if present as well as buffering for non M3 masters such as peripheral DMA or Ethernet DMA is allocated out of system space and so must be left grayed out in code space System Space Stack Heap M3 System bus and other masters eSRAM 1 eSRAM 0 Code Space M3 I Code eSRAM 1 and D Code eSRAM 0 Application Figure 2 5 Remapped eSRAMs Figure 2 6 shows the resulting memory
284. he page buffer is modified ENVM STATUS x 01 7 Attempting to program the page in the page buffer when the page buffer is not modified 60 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide The contents of Table 4 8 indicate which eNVM commands can set the status bits within the ENVM STATUS REG register For example if there is a protection violation when issuing a PROGRAM PAGE command the PROT ERROR bit will be set and the ENVM STATUS 0 bits will be equal to 01 Table 4 8 eNVM Commands that Set the eNVM Status Bits ENVM STATUS REG a wee pep IEEE X PROT ERROR x PROT ERROR x PROG ERROR x ERASE ERROR x OVER THRESHOL ECC1 ERROR x ECC2 ERROR x OP DONE x e Hf LLLI pace fw f f roman race Dm 9 o gt f o ase nce morc __ 9 f ____ e Bx Clocks The eNVMs are driven from the AHB bus matrix On power up the default clock sourcing FCLK is the 100 MHz RC oscillator divided by 4 or 25 MHz If another clock frequency is desired you must configure the PLL accordingly Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 Resets The eNVM controller res
285. he system register space was changed to 0 0004000 to OxE0004FFF Table 2 4 ENVM CR was revised to change the reset value for ENVM SIX CYCLE to 1 Several of the labels in Figure 4 1 Block Diagram of eNVM Controller with Two eNVM Blocks were revised A brief explanation and definition of terms was added to better introduce Figure 4 2 Block Diagram for eNVM Controller Figure 4 3 eNVM Organization was clarified by including notes that define block page sector and array Read Control section and Read Next Operation section were Table 4 4 Latencies Corresponding ENVM SIX CYCLE ENVM PIPE BYPASS was revised Figure 4 6 e Five Figure 4 6 e Five Cycle Read Data Path ENVM SIX CYCLE 0 was revised Read Data Path ENVM SIX CYCLE Figure 4 6 e Five Cycle Read Data Path ENVM SIX CYCLE 0 was revised 0 was revised Table 6 2 ESRAM CR Register Map was revised to change addresses SUE S 004 to E000xxxx Table 9 2 Reset Controller Memory Map was revised to change the address of ANA COMM CTRL to 4002000C The address was changed for MSS CR in Table 10 2 VR and PSM Control Registers Table 11 1 Watchdog Register Interface was revised to change the address for MSS SR to E004201C from E0042000 Figure 12 2 RMII Management Interface and its explanatory text was 174 moved toward the beginning of the document 390 Revision 1 Actel Actel SmartFusion Microcontro
286. hich is also the address phase of the pending transaction When there is no pending transaction the EMC generates the appropriate control signals during its phase 0 which is coincident with the AHB address phase when a new transaction is received When the is not being accessed it remains in phase 0 idle Figure 7 6 shows the AHB and EMC signals when back to back AHB transactions are received by the EMC Addr Addr B Addr Pending Pending Data B Phase Addr A Phase Data A Phase 4 lt 1 4 FCLK HADDR 31 0 E NER AGES E i i Y i HWDATA Data A Data Next Access HREADYOUT J AHB Interface ag 2 Addr A AXAddr A 1 Addr B X Addr B 1 AB 25 0 8 m 1 1 1 1 VE EMC CSO N a J ENX __ ___ 1p DB 15 0 lt Data A 15 0 Data 131 16 Data B 15 0 EMC Phase 1 2 gig 1 2 Figure 7 6 Back to Back AHB Bus Transactions Revision 1 85 VActel External Memory Controller EMC Memory Map AHB Data H R W DATA 31 0 31 24 23 16 AHB addressing is byte oriented so although the AHB buses HRDATA and HWDATA are 32 bit buses individual bytes half words 16 bits or the entire word can be
287. hip select or gets overwhelmed with incoming data the master will not necessarily be aware of it The master and slave must therefore have prior knowledge of each other s capabilities before transmission can begin RX Overflow An RX overflow condition arises when the receive FIFO has not been emptied in time As a result the last write to the receive FIFO from the channel overwrote some previously received data that had not yet been read by the host processor An example of this scenario happens when the SPI 224 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide controller is operating in master mode and the receive FIFO is not being serviced by the processor after the SPI controller raises the RXRDY interrupt flag found in the RIS register Eventually the FIFO will fill up and subsequent writes by the channel will cause the RX overflow to occur The corrective action required is for the host to read from the FIFO until the FIFO is empty This can be checked by reading the FIFO status in the STATUS register TX Under Run A TX under run condition arises when a channel requests to send data while no data is available in the transmit FIFO An example of this scenario happens when the SPI Controller is operating in slave mode and gets a request to send data while no data is available in transmit FIFO The corrective action required is for the host to write data into the transmit FIFO The status flags TXFIFOEMP or
288. ial Protocol 229 SPI Data Transfer for Large Flash EEPROM Devices in Motorola SPI Modes 230 SPI Register Interface Summary 233 SPI Register Interface Details 233 IOMUXes Associated with 238 Inter Integrated Circuit I C Peripherals 249 Bl ck DIA Gram HERE 249 Functional Description 2 2 250 System Dependencies nies 252 2 x Register 255 IOMUXes Associated with I2C_0 120 1 268 Universal Asynchronous Receiver Transmitter UART Peripherals 273 Block Diagram Rex Ru eu ei nee wovon ee RR be 273 F nctional Description 273 System Dependencies RE ERR ERR E RUM TTE E e 274 UART x Register Map bru rere ep Succ ke xa cade EE ier RUE AP req Pie 275 IOMUXes Associated with _ 284 IOMUXes for UART x
289. icts read and write timing for the eSRAMs eSRAMs operate with zero wait states However if an eSRAM is busy completing a write transaction the initiation of a read cycle will incur one wait state and be initiated in the following cycle READYOUT Ons 50 ns 100 ns 150 ns FCLK HADDR 5 HWRITE HRDATA HWDATA 45 96 Lo wo __ di2 D1 do 45 X d5 d7 dip d12 Note The Dx numbers on HADDR are simply used to number and track transactions and are not actual addresses Transactions numbered DO D4 D8 and D15 are idle transactions Transactions D1 D2 D3 D9 D11 D13 and D14 are eSRAM read transactions Transactions D5 D6 D7 D10 and D12 are eSRAM write transactions Figure 6 1 Read and Write Timing Misaligned Addresses 80 Misaligned addresses are not allowed The Cortex M3 aligns addresses as they exit the core However for a master residing in the FPGA fabric you must ensure that the correct addressing byte half word or word is applied to the correct address The eSRAM controller will map misaligned addresses to the appropriate address by ignoring the appropriate least significant bits LSBs of HADDR For example if a fabric master attempts to read a word at address 0x20000001 0x20000002 or 0x20000003 it will actually read the word at address 0x20000000 Revision 1 VAct
290. ides on APB 1 and is clocked by the PCLK1 The eFROM occupies address range 0x40015000 0x40015FFF in the Cortex M3 memory map For more information refer to the AHB Bus Matrix section on page 15 PCLK PRESETn PSEL PWRITE PENABLE eFROM APB Interface PREADY PADDR S 0 PRDATA 31 0 SYS TOPT 3 0 FROM FUIADDR 6 0 FROM ASTB B FROM UFIDATA 7 0 Embedded FlashROM Memory Figure 5 2 eFROM APB Interface Controller 74 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide The ports shown in Figure 5 2 on page 74 are explained in Table 5 2 and Table 5 3 Table 5 2 eFROM APB Controller to MSS Interface Port List UE Table 5 3 eFROM APB Controller to Physical Memory Port List FROM ASTB B Output FROM address strobe active on falling edge can be aligned with PCLK rising or falling edge as described in Table 5 7 on page 76 FROM UFIADDR 6 0 FROM address bus FROM UFIDATA 7 0 FROM data output bus In Figure 5 2 on page 74 the SYS TOPT 3 0 input port represents part of the MSS System Register called the EFROM CR register The EFROM CR register is used to set configurable eFROM APB interface timing options as described in Table 5 4 on page 75 through Table 5 7 on page 76 All APB accesses to the eFROM are read only Since the user has various MSS CLK and PCLK1 configuration options the eFROM timing options have been preselected to ensure that a successful eFROM data access is perf
291. if COM PROTREGIONSIZE is 0 10 this corresponds to a segment size of 128 Kbytes which is 217 Therefore the value of N in this case is 17 So the absolute base address of the region is specified by COM PROTREGIONBASE 31 17 For example 1 COM PROTREGIONBASE 31 17 2 0x0000 The 128 Kbytes segment located at the physical memory address of 0x60000000 is protected from FPGA fabric master access 2 COM PROTREGIONBASE 31 17 0x0001 The 128 Kbytes segment located at the physical memory address of 0x60020000 is protected from FPGA fabric master access 3 COM PROTREGIONBASE 31 17 0x0002 The 128 Kbytes segment located at the physical memory address of 0x60040000 is protected from FPGA fabric master access 4 COM PROTREGIONBASE 31 17 2 0x0003 The 128 Kbytes segment located at the physical memory address of 0x60060000 is protected from FPGA fabric master access 5 COM PROTREGIONBASE 31 17 0x0004 The 128 Kbytes segment located at the physical memory address of 0x60080000 is protected from FPGA fabric master access 30 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide AHB Bus Matrix Configuration Register Table 2 12 AHB MATRIX CR Bit 31 4 Reserved R W 0x0000000 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation COM_WEIGHTEDMODE 0 Round robin slave arbitration
292. ils about the baud rate clock BCLK Slave Mode After setting the ENS1 bit in the CTRL register the 12 peripheral is in the not addressed slave mode which means the 2 peripheral looks for its own slave address and the general call address If one of these addresses is detected the peripheral switches to addressed slave mode and an interrupt is requested Then the peripheral can operate as a slave transmitter or a slave receiver Transfer Example e Cortex M3 sets ENS1 and AA bits l Cperipheral receives own address and 0 peripheral generates interrupt request STATUS register 0x00 Table 14 6 on page 257 Cortex M3 prepares for receiving data and then clears the SI bit e C peripheral receives next data byte and then generates interrupt request The STATUS register contains a value of 0x80 or 0x88 depending on the AA bit Table 14 8 on page 261 Transfer is continued according to Table 14 8 on page 261 Master Mode When the Cortex M3 wishes to become the bus master the IC peripheral waits until the serial bus is free When the serial bus is free the peripheral generates a start condition sends the slave address and transfers the direction bit The peripheral may operate as a master transmitter or as a master receiver depending on the transfer direction bit Transfer Example e Cortex M3 sets 51 and STA bits e C peripheral sends START condition and then generates interrupt request STATUS r
293. immediately 1 Timer 64 in One Shot mode If TIM64ENABLE 1 when the counter reaches zero the counter stops counting To start the counter again load TIM64 LOADVAL U and TIM64 LOADVAL L with a non zero value set the Timer to Periodic mode by clearing TIM64MODE to 0 TIM64ENABLE 310 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Timer 64 Raw Interrupt Status Register Table 17 15 TIM64 RIS Bit Reset Number R W Value Description 31 1 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 TIM64 RIS RAV 0 0 x raw interrupt status 0 Timer 64 has not reached zero 1 Timer 64 has reached zero at least once since this bit was last cleared by a reset or by writing 1 to this bit Writing a 1 to this bit clears the bit and the interrupt writing a zero has no effect Timer 64 Masked Interrupt Status Register Table 17 16 TIM64 MIS Bit Reset Number R W Value Description 31 1 Reserved 0x0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TIM64 MIS OxO Timer 64 masked interrupt status This read only bit is a logical AND of the TIM64RIS and TIM64INTEN bi
294. in reset by other system reset sources See the Reset Controller section on page 143 for more details Interrupts There is one interrupt signal from each UART peripheral The UART O0 INTR signal is generated by UART 0 and is mapped to IRQ10 in the Cortex M3 Controller The UART 1 INTR signal is generated by UART 1 and is mapped to IRQ11 in the Cortex M3 NVIC controller Both interrupt enable bits within the are located at address 100 IRQ10 and IRQ11 correspond to bit locations 10 and 11 respectively The user must also enable interrupts in the UART x by setting the appropriate bits in the IER register while the divisor latch access bit DLAB bit 7 of LCR is 0 The user must clear the appropriate bit in the IER in the respective interrupt service routine to prevent a re assertion of the interrupt 274 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide UART x Register Map The UART 0 base address resides at 0 40000000 and extends to address Ox40000FFF in the Cortex M3 memory map The UART 1 base address resides at 0x40010000 and extends to address 0x40010FFF in the Cortex M3 memory map Table 15 2 defines the control and status registers for the UARTs and Table 15 3 on page 276 through Table 15 15 on page 283 give bit definitions for each of the registers Table 15 2 UART x Register Definitions Divisor Latch UART 0 UART 1 Reset Regist
295. ing this field gives the actual count value of the counter Revision 1 213 Ethernet MAC Table 12 41 CSR11 continued 214 VActel Receive timer Controls the maximum time that must elapse between the end of a receive operation and the setting of the CSR5 6 interrupt bit This time is equal to RT x CS The receive timer is enabled when written with a nonzero value After each frame reception the timer starts to count down if it has not already started It is reloaded after every received frame Writing O to this field disables the timer effect on the receive interrupt mitigation mechanism Reading this field gives the actual count value of the timer Number of receive packets Controls the maximum number of received frames before setting the CSR5 6 Rl receive interrupt bit The receive counter is enabled when written with a nonzero value It is decremented after every received frame It is reloaded after setting the CSR5 6 RI bit Writing O to this field disables the timer effect on the receive interrupt mitigation mechanism Reading this field gives the actual count value of the counter Continuous mode 1 General purpose timer works in continuous mode 0 General purpose timer works in one shot mode This bit must always be written before the timer value is written Timer value Contains the number of iterations of the general purpose timer Each iteration dura
296. ing versions of FCLK the main clock driving the entire MSS which are derived from the MSS Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 In slave mode the input clock to the SPI controller SPICLK can not be faster than one twelfth of PCLKO or PCLK1 This means that for a PCLK of 100 MHz the maximum SPI clock speed allowed is 8 33 MHz In master mode the SPI clock SPI x CLK can run at even divisors of PCLK ranging from 2 to 256 This also means that for a PCLK of 100 MHz the allowed range for SPI clock is 390 KHz to 50 MHz SPI Status at Reset After reset the slave select SPI x SS 0 pins default to a logic High After selecting the SPI mode and enabling the SPI controller the SPI x SS lines default to the correct values for each protocol see the SPI Control Register CONTROL section on page 233 After reset the clock out SPI x CLK is a logic Low At reset the FIFOs are cleared and their respective read and write pointers are set to zero Similarly all the internal registers on the SPI controller are reset to their default values as shown in the SPI Register Interface Details section on page 233 SPI Error Recovery and Handling The SPI protocol defines only the packet formats for data transmission and does not include any error recovery strategy physical layer protocols Specifically if an error occurs on a slave for example it fails to respond to the c
297. ions and descriptions in Table 11 6 WDOGENABLE were revised The R W field values were changed to R in Table 11 8 WDOGSTATUS 168 Table 11 9 WDOGRIS was corrected The reserved bit numbers were 169 changed from 1 2 to 31 2 Table 11 11 se MSS SR was revised to change SYSRESETn to MSS SYSTEM RESET N Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Revision 0 continued age Instances in signal names of H2F and F2H were changed to and F2M to indicate microcontroller subsystem to fabric fabric to microcontroller subsystem In the Receive FIFO RFIFO section the size of the receive FIFO was 175 corrected to 1 024 x 32 bits The last two paragraphs were deleted from the Descriptor Data Buffer 178 Architecture Overview section Pull demand command was changed to Poll demand command 190 191 Figure 12 6 Transmit Process Transitions and Figure 12 7 Receive Process Transmissions Figure 12 12 MAC I O Interaction with Fabric was revised to correct the 215 internal signals in the MUX GND was changed to VDD in Table 12 43 IOMUX 16 and Table 12 44 e 216 IOMUX 17 216 Reserved bits were added to bit definition tables in the Serial Peripheral 221 Interface SPI Controller section Figure 13 1 SPI Controller Block Diagram was revised to change SPI SS 0 221 to SPI x SS O The DMA Mode section was r
298. is revealed to the CPU when its associated character is at the top of the FIFO 1 OE R 0 Overrun error Indicates that the new byte was received before the CPU read the byte from the receive buffer and that the earlier data byte was destroyed OE is cleared when the CPU reads the Line Status Register If the data continues to fill the FIFO beyond the trigger level an overrun error will occur once the FIFO is full and the next character has been completely received in the shift register The character in the shift register is overwritten but it is not transferred to the FIFO 0 DR R 0 Data ready Indicates when a data byte has been received and stored in the receive buffer or the FIFO DR is cleared to 0 when the CPU reads the data from the receive buffer or the FIFO 282 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Modem Status Register MSR Table 15 14 MSR Data carrier detect The complement of DCDn input When bit 4 of the MCR is set to 1 LOOP this bit is equivalent to OUT2 in the MCR Ring indicator The complement of the RIn input When bit 4 of the MCR is set to 1 LOOP this bit is equivalent to OUT1 in the MCR Data set ready The complement of the DSR input When bit 4 of the MCR is set to 1 LOOP this bit is equivalent to RTSn in the MCR Clear to send The complement of the CTSn input When bit 4 of the Modem Control Register MCR is set to 1 LOO
299. isions that occurred before the end of a frame transmission This value is not valid when TDESO 8 excessive collisions bit is set This bit is valid only when TDES1 30 last descriptor is set Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 8 Transmit Descriptor TDESO Bit Functions continued Underflow error When set indicates that the FIFO was empty during the frame transmission This bit is valid only when TDES1 30 last descriptor is set Deferred When set indicates that the frame was deferred before transmission Deferring occurs if the carrier is detected when the transmission is ready to start This bit is valid only when TDES1 30 last descriptor is set Interrupt on completion Setting this flag instructs Ethernet MAC to set CSR5 0 transmit interrupt immediately after processing a current frame This bit is valid when TDES1 30 last descriptor is set or for a setup packet Last descriptor First descriptor 28 FT1 Filtering type This bit together with TDESO 22 FTO controls a current filtering mode This bit is valid only for the setup frames 27 SET Setup packet When set indicates that this is a setup frame descriptor 26 AC Add CRC disable When set Ethernet MAC does not append the CRC value at the end of the frame The exception is when the frame is shorter than 64 bytes and automatic byte padding is enabled In that case the CRC field is added
300. isters per channel The buffers are referred to as A and B The sequence of operations performed by firmware for ping pong operation on DMA channel 0 is as follows the channel is assumed to be configured properly by writing to CHANNEL O0 CTRL first 1 Write to CHANNEL 0 BUFFER A SRC ADDR Write to CHANNEL 0 BUFFER A DST ADDR Write to CHANNEL 0 BUFFER B SRC ADDR Write to CHANNEL 0 BUFFER B DST ADDR Write to CHANNEL 0 BUFFER A TRANSFER COUNT DMA starts using buffer A Write to CHANNEL 0 BUFFER B TRANSFER COUNT DMA will use buffer B when CHANNEL 0 BUFFER A TRANSFER COUNT is O 7 Wait for interrupt on the DMA channel buffer A 8 Write to CHANNEL 0 BUFFER A SRC ADDR 9 Write to CHANNEL 0 BUFFER A DST ADDR 10 Write to CHANNEL 0 BUFFER A TRANSFER COUNT DMA will use buffer A when CHANNEL 0 BUFFER B TRANSFER COUNT is 0 11 Wait for interrupt on the DMA channel buffer B 12 Write to CHANNEL 0 BUFFER B SRC ADDR 13 Write to CHANNEL 0 BUFFER B DST ADDR 14 Write to CHANNEL 0 BUFFER B TRANSFER COUNT DMA will use buffer B when CHANNEL 0 BUFFER A TRANSFER COUNT is O 15 Repeat steps 7 to 14 until finished This removes the real time constraint on the firmware of having to service the DMA channel in real time which would exist if there were only one DMA buffer per channel 36 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Posted APB Write
301. ity with future products the value of a reserved bit should be preserved across a read modify write operation TXCHUNDR RAW interrupt status Reading this returns raw interrupt status Raw status of transmit channel under run RXCHOVRF Raw status of receive channel overflow RXRDY Receive data ready data received in FIFO TXDONE Raw status of transmit done data shifted out IOMUXes Associated with SPI x IOMUXes 0 1 2 3 and 57 to 63 are used to multiplex SPI 0 GPIO and fabric interface signals to MSSIOBUFs IOMUXes 8 9 10 11 and 70 to 76 are used to multiplex SPI 1 GPIO and fabric interface signals to MSSIOBUFs 238 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX Description The MSS contains multiplexers which are involved in the re use of some MSS related I O pads and in providing a number of options for multiplexing GPIO peripheral signals and fabric interface signals to the pad IOMUXes are associated with the GPIO block fabric interface and all MSS communications peripherals UARTS 0 and 1 SPI 0 and 1 2 0 and 1 and the Ethernet MAC For every reusable MSS I O pad there is an IOMUX The IOMUX is intended to provide flexibility in the allocation of MSS I O pads so that if the user is not using a particular interface then the corresponding I O pads can be reallocated to another interface Also if certain I O pads are not being used or are not present in so
302. ive process retains the position of the next descriptor the address of the descriptor following the last descriptor that was closed After entering a running state the retained position is used for the next descriptor fetch The only exception is when the host writes the receive descriptor base address register CSR3 In that case the descriptor address is reset and the fetch is pointed to the first position in the list Before writing to CSR3 the MAC must be in a stopped state The receive process runs until one of the following events occurs A hardware or software reset is issued by the host A software reset can be performed by setting the CSRO O SWR bit After reset all internal registers return to their default states The current descriptor s position in the receive descriptor list is lost A stop receive command is issued by the host This can be performed by writing 0 to the CSR6 1 SR bit The current descriptor s position is retained The descriptor owned by the host is found by Ethernet MAC during the descriptor fetch The current descriptor s position is retained Leaving a suspended state is possible in one of the following situations Areceive poll command is issued by the host This can be performed by writing CSR2 with a nonzero value Anew frame is detected by Ethernet MAC on a receive link 190 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide A stop receive co
303. l RAV 001 SMBSUS control used master host mode to force other devices into power down suspend mode Active low Note SMBSUS NO and SMBSUS NI are separate signals not wired AND If the is part of a host controller SMBSUS NO could be used as an output if is a slave to host controller that has implemented SMBSUS N then only SMBSUS status would be relevant 5 SMBSUS NI Status R ObX Status of SMBSUS NI signal Note SMBSUS NO and SMBSUS NI are separate signals not wired AND If the I C is part of a host controller SMBSUS NO could be used as an output if is a slave to a host controller that has implemented SMBSUS N then only SMBSUS status would be relevant 4 SMBALERT NO Control RAV 001 SMBALERT NO control used slave device mode to force communication with the master host Wired AND Status of SMBALERT NI signal Wired AND 3 SMBALERT NI Status R Status of SMBALERT NI signal Wired AND 2 SMBus Enable RAV 0 0 5 timeouts and status logic disabled standard 126 bus operation 1 SMBus timeouts and status logic enabled 1 SMBUS Interrupt Enable RAV 0 0 SMBUS Interrupt signal SMBS disabled 1 SMBUS Interrupt signal SMBS enabled 0 SMBALERT Interrupt Enable RAV 0 0 SMBALERT Interrupt signal SMBA disabled 1 SMBALERT Interrupt signal SMBA enabled Revision 1 267 Acte Inter Integrated Circuit Pe
304. l pad 1 RMII clock is sourced from the GLC output of the SmartFusion Clock Control block The source of the RMII clock for the 10 100 Ethernet MAC is determined by this bit Revision 1 125 Actel PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators 126 In other words if the clock ratio between the MSS and the FPGA fabric is anything other than 1 1 the GLB clock path must be programmed to have the same ratio to GLA that exists in the MSS to FPGA fabric interface GLBDIVISOR is used internally to generate the appropriate timing signals in the FPGA fabric interface logic between the MSS and the FPGA fabric interface when the ratio between the two is not 1 1 For example the MSS clock is set to 100 MHz from RC through GLA and the ratio between the MSS and the FPGA fabric interface is 4 1 Step 1 Write to MSS CCC MUX CR to select the RC oscillator and bypass the PLL 1 Set RXASEL bit to Ox1 2 Clear DYNASEL to 0x0 3 Set BYPASSA to a 0 1 Step 2 Write to MSS CCC MUX CR to select the GLA path Set GLMUXSEL bits to 0x00 Step 3 Write to MSS CCC MUX CR to select the GLB path 1 Set RXBSEL bit to Ox1 select RC 2 Clear DYNBSEL to 0x0 select RC 3 Set BYPASSB to 0x0 do not bypass MUX and divider 4 Set OBMUX to 0x01 select CLKB Write to MSS_CCC_DIV_CR to program the GLB path Set OBDIV to 0x03 divide by 4 Write to CLK_CONTROL_REG to program the GLA to GLB ratio Set GLBDIVISOR to 0x02 An al
305. l register x 0 CHANNEL_x_STATUS CHANNEL x STATUS x 0 0 0x40004024 0x40004024 R 0 Channel O status register Channel 0 status register _ 0 status register CHANNEL_x_BUFFER_A_SRC_ADDR ERI MN 0x40004028 RAW Channel 0 buffer A source address CHANNEL x BUFFER A DST ADDR 0 0 4000402 RAW Channel buffer destination ms CHANNEL x BUFFER A TRANSFER COUNT 0x40004030 RAV Channel 0 buffer A transfer x 0 count CHANNEL_x_BUFFER_B_SRC_ADDR x 0 0x40004034 RAV Channel 0 buffer B source address CHANNEL_x_BUFFER_B_DST_ADDR 0 0 40004038 RAV Channel 0 buffer B destination address CHANNEL_x_BUFFER_B_TRANSFER_COUNT 0x4000403C GERE Channel 0 buffer B transfer x 0 count CHANNEL_1_CONTROL 0x40004040 Rw Channel 1 control register 22 MM MEE 1 BUFFER B TRANSFER COUNT RAV Channel 1 buffer B transfer count Em 7 BUFFER B TRANSFER COUNT cum VERE Channel 7 buffer B transfer count eNVM Controller Register Map ENVM STATUS REG 0x60100000 RAV 0x0 Returns the status of the last commanded operation ENVM_CONTROL_REG 0x60100004 RAW 0x0 Control register used for all eNVM commands ENVM_ENABLE_REG 0x60100008 eNVM interrupt enable register ENVM 0 CR 0x6010000C RAW eNVM configuration register ENVM 1 CR 0x60100010 RAW eNVM configuration register ENVM PAGE STATUS 0 REG 0x60100014 R eNVM 0 page status register ENVM_PAGE_STATUS_1_REG 0x60100018 eN
306. l register to the System Timer used to concatenate the two 32 bit values from TIM64 BGLOAD VAL U and TIM64 BGLOAD VAL L If Periodic mode is selected the values in the TIM64 LOADVAL L and the TIM64 LOADVAL U are loaded into the counter when the counter decrements to zero Writing this register while the System Timer is set to 32 bit mode has no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value Timer 64 Background Load Value Upper Register Table 17 12 TIM64 BGLOADVAL U Bit Reset Number R W Value Description 32 bit mode has no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value TIM64 BGLOADVAL 0 0 This register holds the upper 32 bit background value to load into the System Timer when in 64 bit mode The value in this register is written to the internal TIM64LOADVAL register when the lower 32 bit word TIM64 BGLOAD VAL L is written Writing this register while the System Timer is set to Revision 1 309 ___________________ System Timer Timer 64 Background Load Value Lower Register Table 17 13 TIM64 BGLOADVAL Bit Reset Number R W Value Description 31 0 TIM64 BGLOAD AL L RAV 0 0 Background load value for the lower 32 bits of 64 bit System Timer When this register is written to both the upper and lower words are written into internal 64 bit TIM64LOADVAL register without
307. l to serial conversion on data from the ARM Cortex M3 processor to these devices Throughout this chapter a lower case x in register and signal descriptions is used as a place holder for 0 or 1 indicating UART 0 or UART 1 Block Diagram RXELOCK UART_X_TXD UART X RXD Interrupt UART_X_RTS RX_FIFO a UART UART X DTR APB Bus X RWCONTROL E interface UART X CTS Baud Rate Block Generator UART X DSR UART X RI Figure 15 1 UART Block Diagram Functional Description When transmitting data is written in parallel into the transmit FIFO of the UART The data is then transmitted in serial form When receiving data the UART transforms the serial input data into a parallel form to facilitate reading by the Cortex M3 processor The data width is programmable to 5 6 7 or 8 bits The UART also supports various parity settings including even odd and no parity as well as different stop bits including 1 172 and 2 bits If the incoming word is error free it is placed in the receiver RX FIFO The interrupt control block sends an interrupt signal back to the Cortex M3 depending on the state of the FIFO and its received and transmitted data The Interrupt Identification Register IIR provides the level of the interrupt Interrupts are sent for empty transmission receipt buffers or FIFOs an error in receiving a character or other conditions requiring the attention of the processor The UART 0 and
308. lator is turned on 0 If a logic O is written to this bit the low power crystal oscillator is turned off 298 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Counter 0 Register 40 bits of the count are transferred to an internal capture register when the COUNTERO REG register is read The second byte of the count COUNTER1 REG must be read prior to the next RTC clock Therefore software routines to read the current RTC count should disable interrupts prior to reading the count and re enable interrupts if needed after all five count registers have been read Table 16 3 COUNTERO REG Bit Number Reset Value Description CNT 70 Counter bits 7 0 y Counter 1 Register Table 16 4 COUNTER1 REG Bit Number Reset Value Description CNT 15 8 Counter bits 15 8 2 Counter 2 Register Table 16 5 COUNTER2 REG Bit Number Reset Value Description CNT 23 16 Counter bits 23 16 Counter 3 Register COUNTER3 REG g S gT Bit Number Reset Value 2 Description CNT 31 24 Counter bits 31 24 Counter 4 Register COUNTER4 REG a S N Bit Number Reset Value z Description CNT 39 32 Counter bits 39 32 Match Register 0 Register MATCHREGO REG a a Bit Number Reset Value 2 Description MATCH 7 0 Match bits 7 0 2 z Match Register
309. lected and should be chosen based on the specific tool flow the user is implementing The Actel MSS UART drivers allow rapid application code development using the SmartFusion MSS UART without having to manually read and write the MSS System Registers to send and receive serial data Actel MSS UART drivers are efficient and flexible allowing UART to be used in either polled mode or in interrupt driven mode For specific details on drivers refer to the Actel SmartFusion MSS Configurators and Drivers User s Guides Application Development Using Actel MSS UART Drivers As a first step tool specific CMSIS files must be imported into the project along with MSS UART drivers The mss uart h header file which defines UART function prototypes must be included in the application code to get access to the UART functions as shown below Example include mss uart h The drivers define structure type mss uart instance t to hold UART data Predefined instance names for UART 0 and UART 1 are g mss uart 0 and g mss uart 1 respectively These names should be used in all the functions to refer to UART instances Before using an instance of MSS UART it must be initialized and configured to match the serial line communication parameters required by the system These parameters include the baud rate the number of data bits the parity setting and the number of stop bits The function MSS UART init must be used as shown in the example below Revision
310. les of the timing reference signal STCLK The SysTick timer uses FCLK if NOREF is set to 1 and uses STCLK if NOREF is set to 0 STCLK is divided down from FCLK based on 8 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide how you program the STCLK DIVISOR field If you run the SysTick Timer using STCLK the remaining fields in SYSTICK CR must be programmed properly FCLK must always be greater than or equal to 2 5 x STCLK even when the Cortex M3 is in sleep mode To generate an exact 10 ms tick for example use these steps 1 Program the MSS CCC to provide a 100 MHz clock to the MSS and hence to the Cortex M3 FCLK 100 MHz 2 Program STCLK_DIVISOR to 0x03 to divide by 32 STCLK is now 100 MHz divided by 32 or 3 125 MHz 3 Set NOREF to 0 indicating that a reference clock is provided With 3 125 MHz reference clock the counter must be reloaded with a value of 31 250 which is 0x7A12 This value is loaded into the TENMS field of the SYSTICK CR register 4 Set the SKEW bit to 0 indicating there 15 an exact 10 ms period 5 You verify the settings programmed into the SYSTICK CR register by reading the SysTick Calibration Value STCVR register located at 0 000 01 Refer to the ARM Infocenter for more information An ARM Knowledge Article with further detail on STCLK is posted in the ARM Infocenter at the time of this writing Table 1 2 SYSTICK CR Map SYSTICK CR 0xE00420
311. ll be received and ACK will returned be returned Arbitration lost in No action X Data byte will be received and not ACK SLA R W as will be returned master own SLA W has been or no action X 1 ds ids be received and ACK will received ACK e reulthed returned General call No action X Data byte will be received and not ACK address 00H has will be returned bren teceived or no action X 1 Data byte will be received and ACK will ACK has been returned Arbitration lost in No action X Data byte will be received and not ACK SLA R W as will be returned master general or no action X 1 Data byte will be received and ACK will call address has returned been received ACK returned Previously Read data byte X Data byte will be received and not ACK addressed with will be returned orread data byte X Data byte will be received and ACK will DATA has been received ACK e returned returned Revision 1 261 _________________ Inter Integrated Circuit Peripherals Table 14 8 STATUS Register Slave Receiver Mode continued Status DATA Register CTRL Register Bits Code Status Action STA STO 51 AA Next Action Taken by Core 0x88 Previously Read data byte Switched to not addressed SLV mode addressed with recognition of own SLA or general call own SLA DATA byte has been or read data byte Switched to not addressed SLV mode received not ACK
312. ller Subsystem User s Guide Draft B The SPI Controller Block Diagram section was revised continued Table 15 9 Interrupt Identification Bit Values is new 278 Table 15 14 MSR was revised to add more information to the descriptions he Low Power Crystal Oscillator Functional Description section was dide to remove reference to the OSC32KHZDISABLE bit Reference to the VCC3AP pin was changed to VCCLPXTAL in the Battery Switching Circuit Functional Description section The description for RSTB_CNT in Table 16 2 CTRL STAT REG was revised Em The Fabric Interface Controller section was revised to include information about which interface s to use when implementing peripherals in the fabric Revision 1 391 VActel POWER MATTERS B Product Support Actel backs its products with various support services including Customer Service a Customer Technical Support Center a web site an FTP site electronic mail and worldwide sales offices This appendix contains information about contacting Actel and using these support services Customer Service Contact Customer Service for non technical product support such as product pricing product upgrades update information order status and authorization From Northeast and North Central U S A call 650 318 4480 From Southeast and Southwest U S A call 650 318 4480 From South Central U S A call 650 318 4434 From Northwest U S A call 650 318 4434 Fro
313. lowing assumptions are made Revision 1 89 ____________________ External Memory Controller e access is measured from the AHB address phase to the assertion of HREADY at the end of the transaction including the FCLK cycle where HREADYOUT is asserted Figure 7 11 shows a transaction that requires four FCLK cycles address plus data phases e Synchronous EMDs will require an additional pipeline delay of cycle A read or write to an asynchronous EMD requires two FCLK cycles for each AHB address phase e f N consecutive back to back accesses are done on the same EMD the total number of FCLK cycles required is given by EQ 7 1 Total FCLK cycles 1 1 7 1 This occurs because for back to back transactions the last cycle can overlap with the next AHB address cycle The phase does not return to the idle or 0 state between transactions as shown in Figure 7 6 An additional FCLK cycle is added whenever an access to a synchronous EMD is followed by an access to an asynchronous or FLASH EMD or vice versa One additional cycle is inserted at the end of the access to ensure that PCB delays will not cause a race condition with the EMD control signals and cause an erroneous write to either memory Table 7 5 Synchronous SRAM Cycle Counts AHB Transaction FCLK Cycles Access Type EMD Data Bus Width Width a Number of Accesses E
314. lustrates a pipelined synchronous SRAM EMD requiring a pipeline clock cycle between EMC AB valid and EMC DB output As shown the EMC requires one FCLK cycle to output the EMD address EMC AB The EMD requires two FCLK cycles to fetch the data EMC DB One additional FCLK cycle is required to transfer the EMD data EMC DB to the AHB Bus HRDATA Therefore this read is an AHB read access with a total of three wait states Depending on the type of access the EMC may need to be configured with up to six wait states to complete an AHB transaction a word read from a byte wide EMD requires a total of eight cycles for example Data Phase o 10 lt A X 8 X 8 X B gt 5 HWRITE 7 A A i Prev Data lt Prev Data Data A HREADY A AB 25 0 ADDR A g m 1 1 1 1 E EMCCSON E J 1 a m a gt i 1 1 1 EMC DB 15 0 Data A 0 1 2 Figure 7 5 to Transaction 84 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide FCLK Cycles and EMC Phases For synchronous EMDs and asynchronous EMDs that operate at FCLK speeds one FCLK cycle is the same as one EMC phase If FCLK is 100 MHz for example during an EMC address phase where address is input to the EMD and if the se
315. m Canada call 650 318 4480 From Europe call 650 318 4252 or 44 0 1276 401 500 From Japan call 650 318 4743 From the rest of the world call 650 318 4743 Fax from anywhere in the world 650 318 8044 Actel Customer Technical Support Center Actel staffs its Customer Technical Support Center with highly skilled engineers who can help answer your hardware software and design questions The Customer Technical Support Center spends a great deal of time creating application notes and answers to FAQs So before you contact us please visit our online resources It is very likely we have already answered your questions Actel Technical Support Visit the Actel Customer Support website www actel com support search default aspx for more information and support Many answers available on the searchable web resource include diagrams illustrations and links to other resources on the Actel web site Website You can browse a variety of technical and non technical information on Actel s home page at www actel com Contacting the Customer Technical Support Center Highly skilled engineers staff the Technical Support Center from 7 00 a m to 6 00 p m Pacific Time Monday through Friday Several ways of contacting the Center follow Email You can communicate your technical questions to our email address and receive answers back by email fax or phone Also if you have design problems you can email your design files to receive assistan
316. m User s Guide SPI Interface Signals Figure 13 1 lists SPI signals Signals that are brought to chip level pins are marked as external Signals that interface with other parts of SmartFusion MSS are marked as internal Table 13 1 SPI Interface Signals NEN NOI Type Bus Size Description 1 fer SPI x CLK Input output 1 Serial clock Input when SPI is in Slave mode Output when SPI is in Master mode SPI x SS O Input output Slave select Input when SPI is in Slave mode Output when SPI is in Master mode Signals Routed Via IOMUXes but Not to a Pin SPI x SS 7 1 Extra slave select signal Valid only in Master mode Internal Signals SPI x MODE Output 1 SPI mode Used by the MSS IOMUXes to determine INOUT signal directions 1 Master 0 Slave SPI Output 1 Output enable SPI x TXRFM Output 1 SPI ready to transmit Used by MSS PDMA engine SPI x RXAVAIL Output SPI received data Used by MSS PDMA engine Note Currently for the A2F200 device SPI 0 can only select four slaves This means only SPI 0 55101 SPI 0 SS 3 1 outputs are valid SPI Controller Operation This section describes SPI controller operation including FIFO interrupt and error handling The SPI controller supports three types of data transfer protocols These are selected by bits 2 and 3 of the Control Register CONTROL 3 2 These are the transfer protocols e Motorola SPI e National Semiconductor MICROW
317. mber R W Value Description Writing reading this register while the System Timer is set to 64 bit mode has no effect TIMx BGLOADVAL RAV 0x0 When this register is written to the value written is loaded into the TIMxLOADVAL_REG register without updating the counter itself This allows a new value to be loaded into the respective counter without interrupting the current count cycle The counter is updated with the new value in TIMxLOADVAL REG when the counter decrements to 0 306 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Timer x Control Register Table 17 5 TIMx CTRL Bit Reset Number R W Value Description 31 3 Reserved RAW OxO Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 2 TIMXINTEN RAV 0x0 Timer x Interrupt Enable When the counter reaches zero interrupt is signaled to the Cortex M3 Nested Vectored Interrupt Controller IRQ20 for Timer x IRQ21 for Timer 2 0 Timer x interrupt disabled 1 Timer x interrupt enabled Writing this register while the System Timer is set to 64 bit mode has no effect Reading this register while the System Timer is set to 64 bit mode returns the reset value TIMxMODE OxO Timer x Mode 0 Timer x in Periodic Mode If TIMxENABLE 1 when the counter reaches zero the counter is reloaded from th
318. me devices then the IOMUX allows the signals to be connected within the IOMUX internally The IOMUX is composed of four multiplexers MO M1 2 and M3 as shown in the IOMUX Functional Description section on page 364 The register description is contained in the same document following the IOMUX functional description IOMUXes for SPI x DI SPI x DO SPI x and SPI x SS 0 To use the SPI x DO SPI x DI SPI x CLK and SPI x SS 0 signals an IOMUX is used to route the signal to a MSSIOBUF This IOMUX is used to share the MSSIOBUF between the SPI x signal and a GPIO If both the GPIO and the SPI x signal are needed another IOMUX can be configured to route the GPIO to the FPGA fabric interface The GPIN source select register must be configured appropriately as well For more information about the GPIN source select register refer to the General Purpose Block GPIO section on page 315 The IOMUXes can be configured using the MSS configurator The GPIO signal can be routed to an FPGA I O using the SmartDesign tool Figure 13 14 shows the IOMUX topology for SPI 0 DI which applies to SPI 1 DI SPI x DO SPI x CLK and SPI x SS 0 as well SPI 0 IOMUX 1 MSSIOBUF X SPI 0 DI GPIO 16 GPI 16 GPO 16 GPOE 16 IOMUX 41 X Not Connected to I O pad X Not Connected to I O pad X Not Connected to I O pad M2F 25 2 25 F2M 25 FPGAIOBUF X FPGA Fabric Figure 13 14 SPI Signal Interactio
319. memory address of 0x60020000 is mapped into address 0x00000000 If the user attempts to remap a segment of eNVM that does not exist unpredictable results will Occur FPGA Fabric Protect Size Register Table 2 9 PROT SIZE CR Bit Reset Number Name R W Value Description 31 5 Reserved RAW 0 00000 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 4 0 COM PROTREGIONSIZE RAW Size of the memory region inaccessible to the FPGA fabric master 28 Revision 1 Table 2 10 Definitions of Bit Combinations for COM PROTREGIONSIZE VActel Actel SmartFusion Microcontroller Subsystem User s Guide Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Remap Size 0 0 0 0 0 Reserved 0 0 0 0 1 Reserved 0 0 0 1 0 Reserved 0 0 0 1 1 Reserved 0 0 1 0 0 Reserved 0 0 1 0 1 Reserved 0 0 1 1 0 128 Bytes 0 0 1 1 1 Reserved 0 1 0 0 0 Reserved 0 1 0 0 1 Reserved 0 1 0 1 0 2 Kbytes 0 1 0 1 1 Reserved 0 1 1 0 0 Reserved 0 1 1 0 1 16 Kbytes 0 1 1 1 0 32 Kbytes 0 1 1 1 1 64 Kbytes 1 0 0 0 0 128 Kbytes 1 0 0 0 1 256 Kbytes 1 0 0 1 0 512 Kbytes 1 0 0 1 1 Reserved 1 0 1 0 0 Reserved 1 0 1 0 1 Reserved 1 0 1 1 0 8 MBytes 1 0 1 1 1 Reserved 1 1 0 0 0 Reserved 1 1 0 0 1 Reserved
320. ment GPIO 337 timer 312 UART 291 Atmel devices 230 B boot process 23 BUFFER_STATUS 42 burst support 19 C CCC functional description 109 CCC without PLL 113 CHANNEL_x_BUFFER_A_DST_ADDR 45 CHANNEL_x_BUFFER_A_SRC_ADDR 45 CHANNEL_x_BUFFER_A_TRANSFER_COUNT 45 CHANNEL_x_BUFFER_B_DST_ADDR 46 CHANNEL_x_BUFFER_B_SRC_ADDR 45 CHANNEL_x_BUFFER_B_TRANSFER_COUNT 46 CHANNEL_x_CONTROL 43 CHANNEL_x_STATUS 44 CLK_GEN 237 clock hierarchy top level 109 clock input sources 111 clock selection 111 CLR_MSS_SR 34 160 collision handling 194 contacting Actel customer service 393 electronic mail 393 telephone 394 web based technical support 393 CONTROL SPI 233 Cortex M3 block diagram 7 documentation 7 Cortex M3 controlled mode 222 COUNTERx_REG RTC 299 CSRO 198 CSR1 200 CSR11 213 CSR2 200 CSR3 201 CSR4 201 CSR5 202 CSR6 205 CSR7 209 CSR8 211 CSR9 212 CTRL 256 CTRL_STAT_REG RTC 298 customer service 393 D DAC signals 369 DATA 120 266 D Code bus 8 deferment algorithm 195 DEVICE SR 161 DLR UART 276 DMA controller 188 DMR UART 277 E eFROM APB interface controller 74 architecture 73 read write capabilities 74 EFROM CR 76 embedded SRAM remapping 21 EMC 81 block diagram 82 functional description 83 I Os 107 phases 85 pins 107 395 Index timing 100 EMC memory map 86 EMC register map 95 EMC CS x CR 95 EMC CSFEx 99 EMC IDDx 99 EMC MUX CR 95 EMC PIPERDNx 99 EMC PIPEWRNx 99 EM
321. mer is configured as a 64 bit timer The example below shows a Timer1 interrupt handler function which sends a message from the MSS UART when the Timer1 interrupt occurs Notice that the last operation in the interrupt handler is the call to MSS 1 clear irq to clear the Timer1 interrupt void Timerl_IRQHandler void Print a message MSS UART polled tx amp g mss uart0 tx buff sizeof tx buff Clear interrupt MSS clear irq Revision 1 313 D System Timer The SmartFusion MSS Timer application development overview provided in this section should enable the user to rapidly and easily utilize the SmartFusion MSS Timer peripherals within the embedded application For additional details on the three tool flows and application development examples refer to the SmartFusion tutorials available on the Actel website http www actel com products smartfusion docs aspx 314 Revision 1 VActel POWER MATTERS 18 General Purpose Block GPIO The microcontroller subsystem MSS general purpose GPIO block is an slave to 32 general purpose I Os Each GPIO bit is configurable as an input or an output with configurable interrupt generation GPIOs can be routed to dedicated I O buffers MSSIOBUF or in some cases to the FPGA fabric interface through an IOMUX The number of GPIOs available to package pins varies with device size and package type The MSS peripherals
322. mer is set to 32 bit mode returns the reset value 308 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Timer 64 Load Value Upper Register Table 17 10 64 LOADVAL U Bit Reset Number R W Value Description 31 0 TIM64 LOADVAL U RAW 0 0 This register holds the upper 32 bit value to load into the System Timer when in 64 bit mode When this register is written to the value written is immediately loaded into a temporary register The value in the temporary register is only written to the System Timer when the lower 32 bit word TIM64 LOADVAL L is written Writing this register while the System Timer is set to 32 bit mode has no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value Timer 64 Load Value Lower Register Table 17 11 TITM64 LOADVAL Reset R W Value Description TIM64 LOADVAL L RAV When this register is written to the value written is immediately loaded into the lower 32 bits of the 64 bit counter along with the value previously written in register TIM64 LOADVAL 0 This applies in both Periodic and One Shot mode The value stored in this register is also used to reload the counter when the count reaches zero and the counter is operating in Periodic mode This register will be overwritten if the TIM64BGLOADVAL register is written to but the counter will not be updated with the new value The TIM64BGLOADVAL register is an interna
323. mmand is issued by the host This can be performed by writing 0 to the CSR6 1 SR bit The current descriptor s position is retained The receive state machine goes into stopped state after the current frame is done if a STOP RECEIVE command is given It does not go in to a stopped state immediately A typical data flow in a receive process is illustrated in Figure 12 7 Receive Start Receive Command Stop Receive Command Reset Command Frame Recognized Receive Suspended Poll Demand Command Receive Running Descriptor Unavailable Figure 12 7 Receive Process Transmissions The events for the receive process typically happen in the following order The host sets up CSR registers for the operational mode interrupts etc The host sets up receive descriptors in the shared RAM The host sends the receive start command Ethernet MAC starts to fetch the transmit descriptors Ethernet MAC waits for receive data on RMII Ethernet MAC transfers received data to the Receive Data RAM Ethernet MAC transfers received data to shared RAM from Receive Data RAM D UD dx cU NE Interrupt Controller The interrupt controller uses three internal Control and Status registers CSR5 CSR7 and CSR11 CSR5 contains the Ethernet MAC status information It has 10 bits that can trigger an interrupt These bits are collected in two groups normal interrupts and abnormal interr
324. mmanded operation Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 0 reported an ECC2 error Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 0 accessed page over threshold Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 0 reported an erase error Write a 1 to this location to clear the bit ERASE ERROR 0 PROG ERROR 0 PROT ERROR 0 0 Don t care 1 ENVM 0 reported a programming error Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 0 reported a protection error Write a 1 to this location to clear the bit 0 ENVM O is ready to read 1 ENVM O is busy This is a read only bit writes have no effect ECC1 ERROR 0 0 Don t care 1 ENVM 0 reported an ECC1 error Write a 1 to this location to clear the bit OVER THRESH 0 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 4 12 ENVM STATUS x ENVM STATUS x eNVM Command B Description LS 1 Ble bit erar 1 1 1 1 Any Command ARRAY_READ ARRAY WRITE MSB 0 NN UNPROTECT PAGE EN EM Single bit error detected and corrected during the copy page operation Page buffer is unmodified or write to a protected page Attempt to erase a protected page OVERWRITE PAGE Attempt to program a protected page ARRAY READ Two or more errors detected UNPROTECT PAGE T
325. n the optional SMBus signals SMBALERT N and SMBSUS N FREQ 0x40002014 RAW 0x08 Necessary for configuring real time timeout logic Can be set to the PCLK frequency for 25 ms SMBus timeouts or may be changed to increase decrease the timeout value Revision 1 381 Aoo Meter SmartFusion Master Register Map Table 21 2 SmartFusion Master Register Map continued GLITCHREG 0x40002018 RAV 0x03 Number of registers in the glitch filter Can be set to value from 3 to 6 Correct value to meet 12 fast mode 50 ns spike suppression will depend on the frequency UART x Register Map UART 0 addresses are shown UART 1 UART x Register 0 addresses shown UART_1 begins at 0x40010000 at 0x40010000 0x40000008 OxC1 Interrupt Identification Register Real Time Counter Register Map on page 297 COUNTERO REG 0x40014100 Counter bits 7 0 COUNTER1 REG 0x40014104 Rw _ Counter bits 15 8 COUNTER2 REG 0x40014108 Ww Counter bits 23 16 COUNTER3 REG 0x4001410C Fw Counter bits 31 24 COUNTERA REG 0x40014110 __ Counter bits 39 32 REG 0x40014120 Rw Match Register bits 7 0 MATCHREG1 REG 0x40014124 Rw __ Match Register bits 15 8 MATCHREG2 REG 0x40014128 rw _ Match Register bits 23 16 MATCHREG3 REG 0x4001412C Rw Match Register bits 31 24 MATCHREGA REG 0x40014130 Ww Match Register bits 39 32 MATCHBITSO REG 0
326. n devices Functional Description Figure 8 1 depicts the top level SmartFusion clocking scheme All SmartFusion devices have six circuits and at least one PLL embedded in one of the CCCs except for the A2F500 device which has two PLLs MSS CCC and Fabric CCC The PLL in single PLL devices is used to provide a flexible clocking scheme to the microcontroller subsystem MSS and the FPGA fabric The additional PLL in other SmartFusion devices is dedicated to FPGA fabric usage dep GLA1 GLAO Pads GLB FPGA Fabric ccc Pads MSS CCC Pads 0 ccc Pads Microcontroller Subsystem MSS FCLK External 10 100 Clock 10 100 CLK Figure 8 1 Top Level SmartFusion Clock Hierarchy There are three internal oscillators that can be used to drive the MSS_CCC block the 32 KHz low power crystal oscillator the main crystal oscillator and the on chip RC oscillator The CCC blocks with an integrated PLL can only divide the input clock frequency there are no minimum input frequency requirements when using the CCC block by itself without the PLL Each PLL can divide multiply its input clock to create a VCO frequency Each PLL CCC has three global outputs called GLA GLB and GLC Each output includes a 5 bit divider that can be individually set to divide the VCO or input clock rate and create the output frequency for that connection In all devices MSS_CCC drives the MSS Once th
327. n UNPROTECT PAGE command on the desired page Revision 1 57 _________________ Embedded Nonvolatile Memory eNVM Controller LOCK The LOCK bit is used to give you control over access to the eNVM from the JTAG interface When LOCK is asserted the JTAG interface will be prevented from any access attempts to the eNVM until LOCK is deasserted For example if a fabric master has access to the eNVM and does not want a JTAG operation to command or control the eNVM the fabric master should set the LOCK bit Likewise if you only allow eNVM access via the Cortex M3 and want to prevent the JTAG interface from accessing the eNVM you should set the LOCK bit eNVM Commands Table 4 6 lists the various commands available for controlling the behavior of the eNVM Program and erase operations on the eNVM occur on a page boundary Table 4 6 eNVM Commands Address Data Bus Command ADDR Data 31 24 Data 23 0 ARRAY READ eNVM array address eNVM array data ARRAY WRITE eNVM array address eNVM array data UNPROTECT PAGE ENVM CONTROLLER REG Page address DISCARD PAGE ENVM CONTROLLER REG Page address PROGRAM PAGE ENVM CONTROLLER REG Page address PROGRAM PAGE PROTECTED ENVM CONTROLLER REG Page address ERASE PAGE ENVM CONTROLLER REG Page address ERASE PAGE PROTECTED ENVM CONTROLLER REG Page address OVERWRITE PAGE ENVM CONTROLLER REG Page address GET PAGE STATUS ENVM CONTROLLER REG Page address UNPROTECT PAGE C
328. n FAB PROT SIZE CR and FAB PROT BASE CR If a region of memory in the eNVM is protected and a fabric master attempts to read or write to it the ERRORSTATUS field of the MSS SR register is updated to reflect the appropriate error and the ABM ERROR IRQ IRQ24 signal is asserted 16 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Arbitration Each of the slave interfaces contains an arbiter The arbiter has two modes of operation round robin and weighted round robin The arbitration scheme selected is applied to all slave interfaces Round Robin Arbitration This is the default arbitration mode As depicted in Figure 2 2 in this mode the arbitration scheme for each slave port is identical Each master accessing a slave has equal priority on a round robin basis However if a locked transaction occurs the master issuing the lock maintains ownership of the slave until the locked transaction completes Clearing bit COM WEIGHTEDMODE in the MATRIX CR sets arbitration to round robin HMASTLOCK1 HMASTLOCK2 Figure 2 2 e Round Robin Arbitration The pure round robin scheme has the advantage of low latency So for example the Cortex M3 can respond quickly to service a high priority interrupt even if the MAC is performing a long AHB burst to the same slave required by the Cortex M3 This is at the expense of not taking full advantage of the slave bandwidth achievable via burst accesses in som
329. n Microcontroller Subsystem User s Guide Fabric Interface Clocks All logic within the FIC is clocked by the main MSS system clock The AHB APB logic within the FPGA fabric can be clocked by GLA or GLB which are generated by the MSS CCC Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 The rising edges of GLB must occur at the same time as a rising edge of FCLK This lining up of the rising edges of GLB and FCLK is controlled by configuring a delay element within the MSS CCC The delay value is factory calibrated MSS Master Interface The MSS master interface side of the FIC can communicate with either an FPGA fabric AHB slave or an APB v3 0 compliant slave as described below Actel provides numerous AHB and APB v3 0 compliant cores for easy instantiation into the FPGA fabric Users must first instantiate either the CoreAHBLite or CoreAPB3 soft IP into the fabric to allow further instantiation of soft FPGA AHB APB masters or slaves MSS Master to FPGA AHB Slave Interface The fabric interface controller allows the AHB masters in the MSS to communicate with AHB compliant slaves in the FPGA fabric as shown in Figure 19 5 The MSS Master AHB interface passes all incoming AHB transactions to the fabric with no error checking FPGA AHB slaves must handle any error conditions The least significant 20 bits of the MSS address bus are passed to the FPGA fabric along with the 32 bit rea
330. n transferred into the receive buffers Assertion of the RI bit can be delayed using the receive interrupt mitigation counter timer CSR11 19 17 NRP CSR1 1 23 20 RT The user can clear this bit by writing a 1 Writing a 0 has effect Transmit underflow Indicates that the transmit FIFO was empty during a transmission The transmit process goes into a suspended state The user can clear this bit by writing a 1 Writing a 0 has no effect Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Transmit buffer unavailable When set TU indicates that the host owns the next descriptor on the transmit descriptor list therefore it cannot be used by Ethernet MAC When TU is set the transmit process goes into a suspended state and can resume normal descriptor processing when the host changes ownership of the descriptor Either a transmit poll demand command is issued or transmit automatic polling is enabled The user can clear this bit by writing a 1 Writing a 0 has no effect Transmit process stopped TPS is set when the transmit process goes into a stopped state The user can clear this bit by writing a 1 Writing a 0 has no effect Transmit interrupt Indicates the end of a frame transmission process Assertion of the TI bit can be delayed using the transmit interrupt mitigation
331. n with GPIO and Fabric Revision 1 239 Actel Serial Peripheral Interface SPI Controller 240 In this case IOMUX 1 is configured to connect IN to MSSIOBUF IO I port IOMUX 41 can be configured to route the GPIO 16 signals to the fabric interface The M2F 25 F2M 25 and 2 OE 25 can then be routed to a FPGAIOBUF using the SmartDesign tool Similar configuration applies to SPI 1 DI SPI x DO SPI x CLK and SPI x SS 0 as well Table 13 14 shows the associated GPIO IOMUX and fabric interface signals for these signals Table 13 14 SPI Signal GPIO and Fabric Mapping iet mna 3 a IOMUXes for Extra Slave Select Signals SPI x SS 7 1 To use these SPI x signals you must route them to FPGA I O through an IOMUX The MSS configurator in the SmartDesign tool is used to route the SPI x signal to the FPGA fabric interface through an IOMUX Routing the signal from the FPGA fabric interface to FPGA is performed separately using the SmartDesign tool Figure 13 15 shows the IOMUX topology for SPI 0 SS 1 IOMUX 57 SPI 0 SPI 0 SS 1 X Not Connected to I O Pad X Not Connected to I O pad X Not Connected to I O Pad FPGAIOBUF X FPGA Fabric Figure 13 15 SPI x SS 7 1 Interaction with GPIO and Fabric For SPI 0 SS 1 IOMUX 57 is configured using the IOMUX 57 CR register to connect OUT A to B which connects SPI 0 SS 1 to M2F 41 in the fabric The M2F 41
332. nals an IOMUX is used to route the signal to an MSSIOBUF This IOMUX is used to share the MSSIOBUF between the UART x signal and a GPIO As an example Figure 15 2 shows the IOMUX topology for UART 0 TXD Similar topologies apply to UART 0 RXD UART 1 RXD and 1 TXD For UART 0 TXD IOMUX 4 would be configured to connect OUT A to MSSIOBUF IO O port IOMUX 45 can be configured to route the GPIO 20 signals to the fabric interface The M2F 29 F2M 29 and 2 OE 29 signals can then be routed to FPGAIOBUF using the Libero Integrated Design Environment IDE tool UART 0 IOMUX 4 MSSIOBUF X UART 0 TXD GPIN 20 SRC GPIO 20 GPI 20 GPO 20 H OE B X Not Connected to I O pad X Not Connected to I O pad X Not Connected to I O pad M2F 29 F2M 29 F2M OE 29 FPGAIOBUF X FPGA Fabric Figure 15 2 UART 0 TXD IOMUX Topology IOMUXes for Modem Control Signals To use these UART x signals they must be routed to an FPGA IO through an IOMUX The MSS configurator in SmartDesign is used to route the UART x signal to the FPGA fabric interface through an IOMUX by initializing the contents of the IOMUX n CR registers Routing the signal from the FPGA fabric interface to FPGA is performed separately using the Libero IDE tool As an example in Figure 15 3 on page 285 for UART 0 RTS IOMUX 64 is configured using the IOMUX 64 CR register to connect OUT A to IN B which connects UART 0 RTS to M
333. nce EMC AB is a byte address The half word synchronous SRAM 16 bit device uses the byte enable control pins to affect a single byte write SmartFusion VDD External Memory Controller Block EMC BYTE EN 1 0 EMC OEN 1 0 N HREADY HRDATA 31 0 EMC PAD OE HREADYOUT CY7C1327G EMC CLK CLK EMC AB 25 0 AB 18 1 17 0 d ADV d ADSC EMC CS 1 0 N CSO RW N devi RW GW WDB 15 0 RDB 15 0 v HRESETn EMC DB 15 0 1 0 Block EMC OENO N OE DQ 15 0 BWE BWA BWB CE2 CE3 MODE ZZ VSS Figure 7 12 x16 Synchronous SRAM 1 EMD The circuit of Figure 7 13 shows a representative configuration of synchronous SRAM for the SmartFusion EMC Eight megabyte SSRAMS are shown The address bus is again half word aligned A 21 0 EMC_AB 22 1 since EMC_AB is a byte address SmartFusion EMC_CLK EMC AB 25 0 External Memory EMC CS T 0 N EMC AB 22 1 EMC CSO N EMC RW N HWRITE Controller Block BYTE EN 1 0 OEN 1 0 N HREADY EMO EMC OENO N HRDATA 31 0 EMC PAD OE HREADYOUT WDB 15 0 EMC DB 15 0 EMC RDB 15 0 Ln 1 0 Block HRESETn
334. nd writes When WENBENXx 0 BYTE is active for both reads and writes When WENBENXx 1 BYTE 15 active for only writes When WENBENXx for the selected region is low BYTE is driven per the waveform shown on row 17 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type When EMC WENBENXx for the selected region is high EMC BYTE ENx is driven per the waveform shown on row 18 of Figure 7 18 on page 101 through Figure 7 22 on page 105 using the figure appropriate to the access type Timing The following timing diagrams in Figure 7 18 on page 101 through Figure 7 23 on page 106 show the operation of the EMC for each of the possible memory types Note that the pipeline configuration for reads and writes is independent A single memory can be configured to do pipelined reads and non pipelined writes or vice versa 100 Revision 1 Asynchronous Read Cycle FCLK HADDR HSEL EMC HSEL OTHER HTRANS1 HWRITE HWDATA HRDATA HREADYOUT EMC CLK EMC AB CSx 5 0 5 1 EMC RW N RwPOL 0 RW RwPOL 1 EMC PAD OE EMC OEx N BYTE WENBEN 0 BYTE WENBEN 1 EMC WDB EMC RDB Figure 7 18 Asynchronous Read Cycle SSS UEM N
335. nds to address 0x40012FFF in the Cortex M3 memory map Table 14 3 2 x Register Definitions Register 2 0 2 1 Address Address R W Reset Value Description CTRL 0x40002000 0x40012000 o Used to configure the IC peripheral STATUS 0x40002004 0x40012004 OxF8 Read only value which indicates the current state of the 2 peripheral DATA 0 40002008 0x40012008 RW 0 JRead write data Read write data to from the serial interface the serial interface E LJ E LI the primary address of the 12 peripheral SMBUS 0x40002010 0x40012010 RAW 0b01X1X000 Configuration register for SMBus timeout reset condition and for the optional SMBus signals SMBALERT_N and SMBSUS FREQ 0x40002014 0x40012014 RAV 0x08 Necessary for configuring real time timeout logic Can be set to the PCLK frequency for 25 ms SMBus timeouts or may be changed to increase decrease the timeout value GLITCHREG 0x40002018 0 40012018 RAV 0x03 Number of registers in the glitch filter Can be set to value from 3 to 6 Correct value to meet 2 fast mode 50 ns spike suppression will depend on the PCLK frequency Revision 1 255 Aoo Meter Inter Integrated Circuit Peripherals CTRL Register Table 14 4 CTRL Bit Reset Number R W Value Description r w o faena ENS1 R W Enable bit When ENS1 0 the sda and scl outputs are in a high impedance and
336. neous signals 370 Motorola SPI protocol 225 MSR UART 283 MSS Actel Index master interface 347 master to AHB fabric slave 347 master to APB slave 348 MSS CCC block 110 MSS CCC DIV CR 128 MSS CCC DLY CR 140 MSS CCC MUX CR 133 MSS CCC PLL CR 138 MSS CCC SR 141 MSS CLK CR 125 MSS IO BANK CR 318 MSS SR 32 157 170 MSSIRQ EN 0 354 MSSIRQ EN 1 354 MSSIRQ EN 2 355 MSSIRQ EN 3 356 MSSIRQ EN 4 356 MSSIRQ 5 357 MSSIRQ EN 6 357 MSSIRQ EN 7 358 MSSIRQ SRC 0 359 MSSIRQ SRC 1 359 55 SRC 2 360 55 SRC 3 361 MSSIRQ SRC 4 361 MSSIRQ SRC 5 362 MSSIRQ SRC 6 362 55 SRC 7 363 N NGMUX 116 clock sources 116 O on chip RC oscillator 120 P PDMA block diagram 35 channel priority 37 clocks 38 functional description 35 interrupts 38 resets 38 PDMA mode 222 PDMA register map 39 PERIPHERAL_SEL 44 ping pong mode 36 PLL operating principles 114 phase selectors 115 programmable dividers 115 PLL CCC register map 124 polled receive 292 polled transmission 292 power modes 155 power supply monitor 153 block diagram 151 154 397 Index Power Down mode 156 power down sequence 154 power up sequence 154 product support 394 customer service 393 electronic mail 393 technical support 393 telephone 394 website 393 programmable delay elements 115 programming in application 374 in system 373 secure 375 R RATIOHILO 37 RBR UART 276 register map AHB bus matrix 24 eFROM 75 EMC controller 95
337. ns of OCDIVHALF and OCDIV can lead to unpredictable results Table 8 13 OCDIVHALF cem E GG 99 oom owe oa owe rop owe tone 0 399 p poo __ E owe E pow p owe ooo owe E omo wee ow owe E pow owe m 89 Revision 1 129 ________________________ _ Acte PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators OCDIV Table 8 14 gives bit definitions for OCDIV Table 8 14 OCDIV Bit Definitions OBDIVHALF This bit if set to 1 divides the output frequency of the output divider defined by OBDIV by 0 5 when the PLL is bypassed with the 100 MHz RC or 32 KHz low power oscillator If OBDIVHALF 1 and OBDIV 2 the OBDIV divisor is 3 so 3 2 1 5 If the GLB YB input is sourced from the 100 MHz RC the output of GLB YB will be 100 1 5 66 67 MHz This bit is only valid if the input to the GLB YB divider is not being sourced by the PLL Table 8 15 lists the only supported values for OBDIVHALF and OBDIV Other combinations of OBDIVHALF and OBDIV can lead to unpredictable results Table 8 15 OBDIVHALF Bit Definitions omowa Di ___ Oink Gock E fo p mme E RD ewe 8 E 3 p ewe _ we xm E m E om oss Ew p ewe e
338. nt overview provided in this section should enable the user to rapidly and easily adopt the SmartFusion MSS UART peripherals in their embedded application For additional details on the three tool flows and UART examples refer to the SmartFusion UART tutorials available on the Actel website http www actel com products smartfusion docs aspx Revision 1 293 VActel POWER MATTERS 16 Real Time Counter RTC System The real time counter RTC system enables SmartFusion devices to support both standby and sleep modes of operation greatly reducing power consumption in many applications The RTC system comprises the following four blocks that work together to provide this increased functionality and reduced power consumption e RTC Low power 32 KHz crystal oscillator e Battery switching circuit e MSS interface Figure 16 1 shows these blocks and how they are connected FPGA Fabric vec pq 1 5 3 3 V Level Shift Circuitry From Core Flash its Low Power VR Logic 1 5 V Volt Crystal Oscillator 9 oltage Regulator VR Init Interrupt System Cortex M3 PTBASE Flash Bits FPGA VRON FPGAGOOD VRINITSTATE RTCPSMMATCH VCC33UP Power Up Down Toggle Control Switch v Figure 16 1 Real Time Counter System Block Diagram Low Power Crystal Oscillator Functional Description The low power crystal oscillator generates a 32 768 KHz clock for the
339. nterrupt sources for MSSINT 2 MSSIRQ EN 3 0x4000700C RAV Enables disables interrupt sources for MSSINT 3 MSSIRQ EN 4 0x40007010 RAV Enables disables interrupt sources for MSSINT 4 MSSIRQ EN 5 0x40007014 RAV Enables disables interrupt sources for MSSINT 5 MSSIRQ EN 6 0x40007018 RAV Enables disables interrupt sources for MSSINT 6 MSSIRQ EN 7 0x4000701C RAV Enables disables interrupt sources for MSSINT 7 MSSIRQ SRC 0 0x40007020 RAV Source interrupt for MSSIRQ SRC 1 0x40007024 RAV Source interrupt for MSSIRQ SRC 2 0x40007028 RAV Source interrupt for esp MSSIRQ SRC 3 0 4000702 RAV Source interrupt for nr MSSIRQ SRC 4 0x40007030 RAV Source interrupt for 2 MSSIRQ SRC 5 0x40007034 RAV Source interrupt for s MSSIRQ SRC 6 0x40007038 RAW Source of interrupt for MSSINT 6 384 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 21 2 e SmartFusion Master Register Map continued MSSIRQ SRC 7 0x4000703C RAW Source interrupt for STL FIIC_MR 0x40007040 RAW Fabric interface interrupt controller mode register ADC Register Map SSE TS CTRL 0 40020004 RAW Sample sequence engine time slot control ADCSYNCCONV SYNC CONV 0x40020008 Rw Synchronized ADC control ANA S _CTRL E R W Common analog block control ADCO CONV CTRL 0x40020050 Rw __ ADC 0 conversion control STC 0x40020054 fw ADC 0 sample time control
340. nterrupt asserted and enabled Revision 1 359 ___________________ Fabric Interface and IOMUX MSSIRQ SRC 2 Table 19 18 SRC 2 24 Reserved should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation ea CMP_11_R PR o 1 Interrupt asserted and enabled CMP_10_R R o 1 Interrupt asserted and enabled CMP_9_R o 1 Interrupt asserted and enabled 8 1 2 Interrupt asserted and enabled H9 CMP7R PR 1 Interrupt asserted and enabled H8 CMP 6 R RJ o 1 Interrupt asserted and enabled CMP_5_R RJ o 1 Interrupt asserted and enabled 16 CMP R 1 Interrupt asserted and enabled CMP_3_R R o 1 Interrupt asserted and enabled 2 RJ o 1 Interrupt asserted and enabled CMP_1_R RJ o 1 Interrupt asserted and enabled CMP OR RJ o 1 Interrupt asserted and enabled URN CMP 11 F RJ o 1 Interrupt asserted and enabled CMP 10 F R 1 Interrupt asserted and enabled I CMP 9 R 1 Interrupt asserted and enabled is 8 R 1 Interrupt asserted and enabled CMP_7_F PR o 1 Interrupt asserted and enabled EM CMP 6 F R 1 Interrupt asserted and enabled 5 RJ o 1 Interrupt asserted and enabled M 4 R 1 Interrupt asserted and ena
341. nto the transmit FIFO 174 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Transmit FIFO TFIFO The transmit FIFO is used for buffering data prepared for transmission by Ethernet MAC It fetches the transmit data from the host via the DMA interface The size of the transmit FIFO is 2 048 bytes 512 x 32 bits which holds one packet up to 1 532 bytes Transmit Controller TC The transmit controller implements the 802 3 transmit operation From the network side it uses the standard 802 3 RMII interface for an external PHY device The TC unit reads transmit data from the external transmit data RAM formats the frame and transmits the framed data via the RMII Backoff Deferring BD The backoff deferring controller implements the 802 3 half duplex operation It monitors the status of the Ethernet bus and decides whether to perform a transmit or backoff deferring of the data via the RMII Receive Linked List State Machine RLSM The receive linked list state machine implements the descriptor buffer architecture of Ethernet MAC It manages the receive descriptor list and moves the data from the receive FIFO into the data buffers Receive FIFO RFIFO The receive FIFO is used for buffering data received by Ethernet MAC The size of the FIFO is 4 096 bytes 1 024 x 32 bits which holds two packets up to 1 532 bytes each During reception if the RX FIFO becomes full while receiving a partial frame that
342. ntroller will capture the sector address and page address when a write to the eNVM occurs and store those addresses within the page buffer as shown in Figure 4 11 The sector address and the page address stored in the page buffer are then used to confirm that the page being modified is the desired page to program into the eNVM when a program or erase operation is commanded Sector Address Page Address Block 0 Block 15 Aux Block Figure 4 11 Page Buffer The page buffer is marked internally as being modified if one of the following conditions is true Asuccessful write operation to the page buffer occurs Asuccessful write operation to the Auxiliary block occurs e If the state of protection for the page buffer has been modified The internal flag indicating whether a page is modified or not is used by programming and erase commands to ensure coherency between the page buffer and the eNVM The page buffer is marked as unmodified when it is committed to eNVM or discarded Programming the eNVM is accomplished using a Read Modify Write methodology The first write causes the eNVM controller to copy the entire page from the eNVM array place it into the page buffer and write the first word into the block buffer Figure 4 12 depicts the flow of data from eNVM to the block buffer and to the page buffer during this operation m wm um um um Gm Gm m mom m mo moa Output
343. nued Status DATA Register SIRE Register Code Status Action STA STO SI Next Action Taken by Core Data byte has been Read data byte 1 X Repeated START condition will be received not ACK transmitted read data byte 1 X STOP condition will be transmitted STO flag will be reset or read data byte X 5 condition followed by a START condition will be transmitted STO flag will be reset OxDO SMBus Master Reset No Action X X X Wait 35 ms for interrupt to be set clear has been activated interrupt and proceed to F8H state Notes 1 SLA Slave address 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave 260 Revision 1 Table 14 Status Code Notes 1 SLA Slave address 2 SLV Slave 3 REC Receiver 4 TRX Transmitter 5 SLA W Master sends slave address then writes data to slave 6 SLA R Master sends slave address then reads data from slave VActel Actel SmartFusion Microcontroller Subsystem User s Guide STATUS Register Slave Receiver Mode 8 STATUS Register Slave Receiver Mode DATA Register CTRL SEXES Bits Status Action STA sTo si Next Action Taken by Core Own SLA W has No action o byte will be received and not ACK been received will be returned Mas begn or no action Data byte wi
344. ocks of eSRAM The total amount of available eSRAM ranges from 16 Kbytes to 64 Kbytes depending on device size Each individual eSRAM block is therefore 8 Kbytes to 32 Kbytes organized in a 2Kx32 to 8Kx32 fashion The eSRAM in these blocks is byte half word and word addressable The ARM Cortex M3 and other masters find the eSRAMs available as one contiguous area of memory The address of eSRAM 0 is 0x20000000 and eSRAM 1 is located at an address which depends on the total amount of eSRAM present on the device The location of eSRAM 1 is always directly after eSRAM 0 in the memory map Table 6 1 lists the memory locations for eSRAM in SmartFusion devices and Table 6 2 gives pertinent register definitions Table 6 1 5 Address Locations A2F200 0x20000000 0x20008000 64 Kbytes A2F500 0x20000000 0x20008000 64 Kbytes Table 6 2 e ESRAM CR Register Map Reset Register Name Address R W Value Description ESRAM CR OxE0002000 RAW 0 0 Controls address mapping of the eSRAMs AHB MATRIX CR 0xE0002018 RAV 0x0 Configures the AHB bus matrix Table 6 3 gives bit definitions for the eSRAM Configuration Register Table 6 3 au CR Bit Reset _ R W Value Description 31 1 Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation
345. ommand Writing 0x02 to the COMMAND field of the ENVM CONTROL REG will unprotect the page addressed The page addressed will be copied from eNVM into the page buffer if the page is not in the page buffer and the current contents of the page buffer are not marked as modified The page addressed will also be copied from eNVM into the page buffer if the page in the page buffer is marked as modified and PAGE LOSS 0 If the contents of the page buffer are marked as modified and PAGE LOSS 1 the copy of the page from eNVM will not occur and a protection violation error will be reported in the ENVM STATUS REG register by setting PROT ERROR x to 1 An interrupt signal is asserted to the Cortex M3 NVIC if the PROT ERROR x bit is set in the ENVM ENABLE REG If the page addressed is a read protected spare page 0 15 in ENVM 0 the UNPROTECT PAGE operation does not occur and a protection violation error will be reported in the ENVM STATUS REG register by setting PROT ERROR x to 1 Table 4 7 on page 59 summarizes information on the UNPROTECT PAGE command 58 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Table 4 7 UNPROTECT_PAGE modes Page Buffer Page Copied from eNVM PAGE_LOSS Modified to Page Buffer OVERWRITE_PROTECTED PROT_ERROR_x DISCARD_PAGE Command Writing 0x04 to the COMMAND field of the ENVM CONTROL REG discards the data in the current page buffer No interrupt is generated Check the ENVM STATUS x
346. ommended setting selected to provide sufficient eFROM memory access time This setting DEFAULT ensures that the correct eFROM data is propagated from the memory back to the MSS through the eFROM APB controller regardless of whether the MSS CLK to PCLK1 ratio is 1 1 2 1 or 4 1 Table 5 7 e Timing Options Controlled by SYS 0 a Timing option 2 Allows one complete PCLK1 cycle for the APB address to propagate from the APB bus to the eFROM through the eFROM APB interface controller This is the default and recommended setting DEFAULT 76 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide When reading the eFROM via firmware running on the SmartFusion MSS each byte is read from the eFROM by addressing an offset of the eFROM APB peripheral base address For example the first byte of the eFROM is read by addressing the eFROM APB peripheral base address 0x40015000 and returned via the MSS AHB bus matrix The next byte of the eFROM is read by incrementing the base address by 4 Thus to read byte i of the eFROM the firmware would access the following Cortex M3 memory space address base address 4 i Revision 1 77 VActel POWER MATTERS 6 Embedded SRAM eSRAM Memory Controllers The embedded SRAM eSRAM memory controller is an Advanced High Performance Bus AHB slave that provides access to two equal sized bl
347. omoa ___ ______ ___ __ ___ __ __ pj 111 IOMUX 3 Table 13 19 IOMUX 3 Pad IOMUX 3 Ports Pad Name Ports IOMUX 3 CR INA OUT A Do qmm op 1 sese SPI 0 SS O 41 LIN ERE C _ 242 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 8 Table 13 20 IOMUX 8 Pad IOMUX 8 Ports Pad Name Ports IOMUX 8 CR OUTA ___________ 14 x Lp IOMUX 8 PD Tomes ff IOMUX 9 Table 13 21 IOMUX 9 IOMUX 9 Ports e es e eos 1 omxesr _ IOMUX 10 Table 13 22 IOMUX 10 ___ px exp 9 p Revision 1 243 _________________ Serial Peripheral Interface SPI Controller IOMUX 11 Table 13 23 IOMUX 11 EI o I 9 Lem er siis 0 eroa IDEM 21104 __ pe p o o xg p gq _ pan IOMUX 57 Table 13 24 IOMUX 57 IOMUX 57 Ports gt WAT ours ws ours LUI clle lI pem ew mmu Lm fT poe
348. ompatibility with future products the value of a operation TIMEOUTMS 0x0 Status of the WDOGTIMEOUTINT interrupt This is the logical AND of the TIMEOUTRS bit of the WDOGRIS register and TIMEOUTINTEN bit of the WDOGCONTROL register 0x0 This is the logical AND of the WAKEUPRS bit of the WDOGRIS register and WAKEUPINTEN bit of the reserved bit should be preserved across a read modify write Status of the WDOGWAKEUPINT interrupt WDOGCONTROL register a o Revision 1 169 ____________________ _____ _ Acte Watchdog Timer MSS Status Register MSS SR The MSS Status register holds the status of system critical events such as brownout and timeout coming from different parts of the MSS system Table 11 11 MSS SR Bit Reset Number R W Value Description 31 8 Reserved 0 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 4 COM ERRORSTATUS Each bit on this bus indicates whether any accesses by the corresponding master on the Communications Matrix resulted in HRESP assertion by the slave to the Communications Matrix HRESP assertion by the Communications Matrix to that master in the case of blocked fabric master or decoding by the Communications Matrix as being unimplemented address space These register bits are sticky and are cleared by the writing 1 to the COM_CLEARSTATUS
349. oo Atea Serial Peripheral Interface SPI Controller Multiple Frame Transfer SPI X CLK SPI X SS i 4 SPI_X_DO Y 5B Y inim I kii bits SPI OEN Figure 13 10 TI Synchronous Serial Multiple Frame Transfer Texas Instruments Synchronous Serial Error Case Scenarios When the SPI controller is configured for the TI synchronous serial protocol while in Slave mode it responds to failure events on slave select SPI x SS and slave clock SPI x CLK in the following manner e Withdrawal of SPI x CLK In this case the device pauses and will resume on reasserting the clock Premature pulsing of slave select If the slave select is pulsed during a data frame transmission it will be ignored e Disconnection of slave select before a transfer The transfer is not initiated unless the pulse is issued SPI Data Transfer for Large Flash EEPROM Devices in Motorola SPI Modes Serial flash and EEPROM devices can be driven using the Motorola SPI modes The following outlines the interfaces to the required flash EEPROM devices and shows how they can be driven using the Motorola SPI modes In each of these modes the SPI controller is configured as a master with the slave select line hooked to the signal SPICS shown on the waveform The serial flash EEPROM device then acts as the slave Devices that Require Data Frame Sizes of up to 32 Bits Serial flash EEPROM devices such as the Atmel 25010 02
350. or MSSINT 1 55 SRC 2 0x40007028 0 Source of interrupt for MSSINT 2 MSSIRQ SRC 3 0x4000702C Source of interrupt for MSSINT 3 MSSIRQ SRC 4 0x40007030 Source of interrupt for MSSINT 4 MSSIRQ SRC 5 0x40007034 Source of interrupt for MSSINT 5 MSSIRQ_SRC_6 0x40007038 Rw 0 Source of interrupt for MSSINT 6 MSSIRQ_SRC_7 0x4000703C 0 Source of interrupt for MSSINT 7 FICMR _____ MR 0x40007040 Fabric interface Fabric interface interrupt controller mode register controller mode register IF _ UL T OxE004206C Controls the Eu of the fabric interface controller HIWORD DR 0 0042070 R 16 bit APB holding register within the FIC IOMUX n CR n 0 0 0042100 Configures IOMUX 0 IOMUX n CR 82 0 0042248 Configures IOMUX 82 Revision 1 345 ___________________ Fabric Interface and IOMUX Fabric Interface Control FIC The FAB IF CR is used to select the type of the interfaces on the fabric side of the FIC and to select bypass mode or not This register is located the SYSREG block at address 0xE004206C Individual bit descriptions are given in Table 19 2 Table 19 3 lists the truth table for selecting the appropriate bus type on the FPGA side of the FIC Table 19 2 FAB IF CR Bit Reset Number R W Value 31 4 Reserved RAV Software should not rely on the value of a reserved bi
351. or can point to up to two data buffers When using descriptor chaining the address of the second buffer is used as a pointer to the next descriptor thus only one buffer is available A frame can occupy one or more data descriptors and buffers but one descriptor cannot exceed a single frame In a ring structure the descriptor operation may be corrupted if only one descriptor is used Additionally in the ring structure at least two descriptors must be set up by the host In a transmit process the host can give the ownership of the first descriptor to Ethernet MAC and cause the data specified by the first descriptor to be transmitted At the same time the host holds the ownership of the second or last descriptor to itself This is done to prevent Ethernet MAC from fetching the next frame until the host is ready to transmit the data specified in the second descriptor In a receive process the ownership of all available descriptors unless it is pending processing by the host must be given to Ethernet MAC 178 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Figure 12 4 shows descriptors in ring structure CSR Shared Buffer 1 Buffer 2 Do o 1 OWN PRIN own Buffer 1 Buffer 2 CSR3 CSR4 Descriptor List Base DSL Descriptor Skip CSR Figure 12 4 Descriptors in Ring Structure Revision 1 179 ________
352. or no action STOP condition followed by a START condition will be transmitted STO flag will be reset SLA W has been Load data byte Data byte will be transmitted ACK transmitted not ACK will be received has b d AREE REE or no action pu Repeated START will be transmitted START will be transmitted or no action STOP condition will be transmitted STO flag will be reset or no action 1 X STOP condition followed by a START condition will be transmitted STO flag will be reset Notes SLA Slave address SLV Slave REC Receiver TRX Transmitter SLA W Master sends slave address then writes data to slave NL SLA R Master sends slave address then reads data from slave Revision 1 257 _________________ Inter Integrated Circuit Peripherals Table 14 6 STATUS Register Master Transmitter Mode continued Status DATA Register CTRL TENES Bits Code Status Action 5 sTo s Next Action Taken by Core 0x28 Data byte in DATA Load data byte a byte will be transmitted ACK bit register has been will be received transmitted ACK has n or no orno action a a Repeated START will be transmitted START will be transmitted been received or no action STOP condition will be transmitted STO flag will be reset or no action 1 X STOP condition followed by a START condition will be transmitted STO flag will be reset 0x30 Data byte in DATA D
353. or the bit settings Resets I7C peripherals reset to zero on power up and are held in reset until the user enables them The user has the option under software control to reset the 12 peripherals by writing to bit 11 or bit 12 in the System Register SOFT RST CR located at address 0xE0042030 the memory map The soft resets are encoded in Table 14 1 Table 14 1 Soft Bit Definitions for the 12 peripherals 0 SR RAV 0 1 Controls reset input to I2C 0 0 Release I2C 0 from reset 1 Keep 2 0 reset reset value I2C 1 SR RAV 0 1 Controls reset input to I2C 1 0 Release 2 1 from reset 1 Keep I2C 1 in reset reset value At power up the reset signals are asserted 1 This keeps the 12 peripherals in a reset state If the user sets this bit to 0 the 12 peripheral is allowed to become active If I2C x SR is 0 the I2C x peripheral could still be held in reset by other system reset sources See the Reset Controller section on page 143 for more details 252 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide SMBus Clock Low Reset If the SCL clock line is held low by a master that has initiated a bus reset with the SMBUS register the following sequence should occur Refer to Figure 14 3 SMBus Bus Reset Sequence master device sets the SMBUS RESET bit forcing the SCL clock line low master device enters the reset state DO and an inter
354. ord in 64 bit mode TIM64 VAL L 0x40005034 0x0 Lower 32 bit word in 64 bit mode TIM64 LOADVAL U 0x40005038 RAV 0x0 Upper 32 bit load value word in 64 bit mode TITM64 LOADVAL L 0x4000503C RAV 0x0 Lower 32 bit load value word in 64 bit mode TIM64_BGLOADVAL_U 0x40005040 RAW 0x0 Upper 32 bit background load value in 64 bit mode TIM64 BGLOADVAL L 0x40005044 RAV 0x0 Lower 32 bit background load value in 64 bit mode TIM64_CTRL 0x40005048 RAW 0x0 Control Register in 64 bit mode TIM64_RIS 0x4000504C RAW 0x0 Raw interrupt status in 64 bit mode TIM64_MIS 0x40005050 0x0 Masked interrupt status in 64 bit mode TIM64_MODE 0x40005054 RAW 0x0 System Timer dual 32 bit or 64 bit mode Revision 1 383 VActel SmartFusion Master Register Map Table 21 2 SmartFusion Master Register Map continued GPIO Register Map GPIO x CFG 0 0 40013000 RAW GPIO Configuration register bit 0 GPIO x CFG A 31 E L register for bit 31 GPIO IGPOIRQ 0x40013080 IRW 00 00 interrupt Status Register Status Register 0x40013084 Read only bits ports configured as inputs GPIO OUT 0x40013088 RAW 0x0 Read write bits for ports configured as outputs Fabric Interface and IOMUX Register Map MSSIRQ EN 0 0x40007000 RAV Enables disables interrupt sources for MSSINT 0 MSSIRQ EN 1 0x40007004 RAV Enables disables interrupt sources for MSSINT 1 MSSIRQ EN 2 0x40007008 RAV Enables disables i
355. ormed regardless of the MSS clocking configuration selected APB write transactions are ignored and result in no activity at the eFROM APB controller to eFROM physical memory interface When not performing a read access the FROM UFIADDR 6 0 bus is forced to all 15 to limit dynamic dissipation usage in the eFROM Table 5 4 EFROM CR Register Map EFROM CR OxE0042024 RAV 0x00000009 Used to set eFROM APB interface controller timing options Revision 1 75 VActel SmartFusion Embedded FlashROM eFROM Table 5 5 CR 31 4 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 1 SYS_TOPT 3 1 RAV 100 binary Controls the number of wait states inserted by the eFROM APB interface controller before asserting PREADY during an APB access Wait states are needed since the APB clock PCLK1 frequency can be higher than the maximum eFROM clock frequency This can result in PCLK cycle times which are shorter than the expected eFROM data access timing and result in incorrect eFROM data being read onto the APB PRDATA bus Table 5 6 shows the recommended wait state setting 1 Timing Option 2 Refer to Table 5 7 Table 5 6 Timing Options Controlled by SYS TOPT 3 1 mo mr 1 7 m 7 4 This is the default and rec
356. own in Figure 13 6 through Figure 13 3 on page 226 Revision 1 225 _____________________ Serial Peripheral Interface SPI Controller Single Frame Transfer Mode 0 SPO 0 SPH 0 SPI X CLK SER 455 ee SPI X SS r SPI X DI 41032 Bits SPI X sex Do i mba X Xo XO OCC OCC CB Figure 13 2 Motorola SPI Mode 0 Multiple Frame Transfer Mode 0 SPO 0 SPH 0 Wc FP 4 77 2 TX SPI X SS SPI X DO SPI X DI E 32 Bits 5 SPI X OEN Notes 1 Between frames the slave select SPI x SS is asserted for the duration of clock pulse 2 Between frames the clock SPI x CLK is low 3 Data is transferred most significant bit MSB first 4 The output enable SPI x OEN signal is asserted during transmission deasserted at end of transfer after the last frame is sent Figure 13 3 Motorola SPI Mode 0 Multiple Frame Transfer Single Frame Transfer Mode 1 5 0 5 1 SPI X SS SPI X DI xor a 410 32 Bits gt SPI X OEN mss X yf CU Figure 13 4 Motorola SPI Mode 1 226 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Single Frame Transfer Mode 2 SPO 1 SPH 0 SPI X CLK EMEN E E s SPI X SS sP
357. ows 12 20 as shown in Figure 7 22 on page 105 Pipelined Synchronous Write Cycle Note that for W 1 the shown latency cycle is removed from the timing diagram Pipelined Read Enable PIPERDNXx This bit enables pipelining of memory reads Note For pipelined reads the address is incremented on each FCLK cycle For non pipelined reads the address is only incremented after the AHB has latched the read data When PIPERDNXx is asserted Low reads of synchronous SRAMs in the region controlled by chip select x where x can be 0 1 are pipelined with timing per Figure 7 20 on page 103 Pipelined Synchronous Read Cycle When PIPERDNXx is deasserted High reads of synchronous SRAMs in the region controlled by chip select x where x can be 0 or 1 are not pipelined with timing illustrated per Figure 7 19 on page 102 Non Pipelined Synchronous Read Cycle PIPERDNXx has no effect for asynchronous SRAMs and NOR flash devices Pipelined Write Enable PIPEWRNXx This bit enables pipelining of memory writes Note For pipelined writes the address is incremented on each cycle For non pipelined writes the address is only incremented after the EMD has latched the write data When PIPEWRNXx is asserted Low writes to synchronous SRAMSs in the region controlled by chip select x where x can be 0 or 1 are pipelined with timing per Figure 7 22 on page 105 Pipelined Synchronous Write Cycle
358. p Table 8 5 PLL CCC Register MSS CLK CR 0xE0042048 0x00028A8 Clock Configuration for APB buses MSS CR 0 004204 0x00030000 Control bits for the CCC dividers MSS CR 0xE0042050 0 00800000 Control bits for the multiplexers MSS 0 0042054 0x00000000 Control bits for the PLL MSS DLY CR 0xE0042058 0x01FF8000 Control bits for the CCC delay elements MSS SR 0 004205 R 0x00000000 Lock indication 124 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Clock Control Register Table 8 6 55 CLK CR Bit Reset Number R W Value Description 31 14 Reserved RAW 0x00028A8 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify 13 12 GLBDIVISOR write operation RTCIF ACMDIVISOR o Selects the clock ratio between the MSS and FPGA fabric interface See the GLBDIVISOR section 0b1000 This bit determines the divisor value to be used by the RTCIF block in the generation of ACMCLK from PCLK1 The ACMCLK must have a value of 10 MHz or less See Table 8 8 on page 127 for allowed values This bit determines the divisor value to be used to generate clock ACLK for APB bus APB 2 The Analog Compute Engine resides on this bus A multiple of 40 MHz is required for o
359. plexer output GLA GLB and GLC a delay element is available which is user selectable from 0 735 ps in the first step then to 5 56 ns with 200 ps increments after the first two steps Setting these delays is done by writing to the DLYA DLYB and DLYC fields of the MSS CCC DLY CR In addition to the above three delays there are two additional delays in series with GLA GLAO is a programmable delay element driving the microcontroller subsystem clock network and GLA1 is a programmable delay element driving the FPGA fabric GLA clock network These two delay elements DLYAO and DLYA1 are used to allow edge alignment for hold time correction between the microcontroller subsystem and the fabric interface if GLA1 is used to clock the fabric interface controller FIC Setting these delays is done by writing to the DLYAO and the DLYAT fields of the MSS DLY CR On power up DLYAO and DLYA1 are set to their maximum value System boot Revision 1 115 PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators Actel code provided by Actel in concert with the Libero IDE MSS Configurator will initialize the delay values to factory calibrated data Glitchless MUX NGMUX The NGMUX is a 2 1 multiplexer that switches glitch free between two different clock sources and outputs the new clock to the global network as shown in Figure 8 8 Before switching the NGMUX the clock source being switched to must be stable to avoid unstable clock
360. predefined value as shown in Table 12 39 Writing to these bits has no effect Table 12 39 CSR9 Bit Name R W Reset Value Function 31 20 N A 0b111111111111 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 19 MDI R 0 RMII management data in signal read only This bit reflects the sample on the MDI during the read operation on the RMII management interface 18 MDEN RAV 061 RMII management operation mode 1 Indicates that Ethernet MAC reads the RMII PHY registers 0 Indicates that Ethernet MAC writes to the RMII PHY registers This bit controls the active low tristate enable for the top level MDIO data output 17 MDO RAV 0 RMII management write data The value of this bit drives the MDO signal when a write operation is performed 16 MDC RAV 0 RMII management clock The value of this bit drives the MDC signal 15 0 0b1000001111111011 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 212 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide General Purpose Timer and Interrupt Mitigation Control Register CSR11 Table 12 40 General Purpose Timer
361. previous write operation data is fetched from the eNVM array The page buffer is not modified A read always reads the latest data written to the eNVM whether the data resides in the block buffer page buffer or eNVM array The ENVM PIPE BYPASS and ENVM SIX CYCLE registers are used to control read access behavior to the eNVM The latency of the initial access to an eNVM block and the subsequent three accesses if initiated to the same eNVM block depends on the state of both ENVM PIPE BYPASS and ENVM SIX CYCLE The latencies number of FCLK cycles corresponding to the various combinations of ENVM SIX CYCLE and ENVM PIPE BYPASS are shown in Table 4 4 on page 52 Revision 1 51 o Acte Embedded Nonvolatile Memory eNVM Controller ENVM SIX CYCLE bit 07 and ENVM PIPE BYPASS bit 06 are controlled by the ENVM CR located at address 0 0042004 Table 4 4 Latencies Corresponding to SIX CYCLE and ENVM PIPE BYPASS ENVM SIX CYCLE ENVM PIPE BYPASS eNVM Access FCLK cycles MHz __ 0 6 2 2 2 when FCLK gt 80 MHz and lt 100 MHz Note 6 2 2 2 indicates 6 cycles for the first access and 2 each for the next three accesses 5 1 1 1 indicates 5 cycles for the first access and 1 each for the next three accesses In 5 1 1 1 read mode a newly addressed block is fetched from the eNVM array and presented to the output multiplexer and copied into the block buffer simultaneously In 5 1 1 1 read mode ENVM SIX CYCLE
362. priority Receive data available interrupt modem status interrupt Reading the Receiver Buffer Register RBR or the FIFO drops below the trigger level resets this interrupt 0b1100 Second priority Character timeout indication interrupt occurs when no characters have been read from the RX FIFO during the last four character times and there was at least one character in it during this time Reading the Receive Buffer Register RBR resets this interrupt 0b0010 Third priority Transmit Holding Register Empty interrupt Reading the IIR or writing to the Transmit Holding Register THR resets the interrupt 0b0000 Fourth priority Modem status interrupt due to Clear to Send Data Set Ready Ring Indicator or Data Carrier Detect being asserted Reading the Modem Status Register resets this interrupt This register is read only writing has no effect Also see Table 15 9 Table 15 9 Interrupt Identification Bit Values Priority Value Level Interrupt Type Interrupt Source Interrupt Reset Control 050110 Highest Receiver line status Overrun error parity error or break Reading the Line Status interrupt Register 050100 Second Received data Receiver data available Reading the Receiver Buffer available register or the FIFO drops below the trigger level least one character in it during this 051100 Second Character timeout characters have been read from Reading the Receiver Buffer indication the R
363. ptimal ADC conversion rates See Table 8 9 on page 127 This bit determines the divisor value to be used to generate the clock PCLK1 for APB bus APB 1 See Table 8 10 on page 127 4 PCLK1DIVISOR PCLKODIVISOR EN RMIICLKSEL GLBDIVISOR The user has the option of selecting the clock ratio between the MSS and FPGA fabric interface Valid clock ratios are 1 1 2 1 and 4 1 If the MSS to FPGA fabric interface clock ratio is selected as 1 1 whether in synchronous or fabric bypass mode the AMBA interface logic in the FPGA fabric may use GLA1 instead of GLB as its clock This leaves GLB free for use and it may be set at any value However if the MSS to FPGA fabric interface clock ratio is selected as either 2 1 or 4 1 GLB must be used as the clock source of the AMBA interface logic in the FPGA fabric and the GLB clock must be programmed to have the corresponding ratio to GLA that exists in the MSS to FPGA fabric interface GLBDIVISOR is programmed by firmware to indicate to the fabric interface logic the actual GLA to GLB ratio 6 2 ACLKDIVISOR 7 5 3 This bit determines the divisor value to be used to generate the clock PCLKO for APB bus 0 See Table 8 11 on page 127 2 Software should not rely the value of reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 clock is sourced from an externa
364. ption vector will execute eNVM Controller Register Map The eNVM controller control registers are located in the System Registers address space at 0x60100000 and extend to address 0x601000FF in the Cortex M3 memory map Refer to Figure 2 4 on page 25 Table 4 10 eNVM Controller eee Address RW Reset Reset Value Description ENVM n the status of the last commanded operation ENVM_CONTROL_REG 0x60100004 Control register used for all eNVM commands ENVM_ENABLE_REG 0x60100008 eNVM interrupt enable register _0_ 0 60100010 0 configuration register ENVM 1 CR 0x60100014 eNVM 1 configuration register ENVM PAGE STATUS 0 REG 0x60100018 00 eNVM 0 page status register ENVM PAGE STATUS 1 REG 0x6010001C R eNVM_1 page status register 62 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide eNVM Status Register Table 4 11 ENVM US REG Bit MEN Description 31 ILLEGAL CMD 1 0 Don t care 1 An illegal command has been issued to ENVM 1 Write a 1 to this location to clear the bit 25 24 ENVM STATUS 1 These bits provide status information from ENVM 1 based upon the command and or 23 DONE 1 0 Don t care 1 ENVM 1 has completed the commanded operation Write a 1 to this location to clear the bit 0 Don t care 1 ENVM 1 reported an ECC2 error Write a 1 to this location to
365. r cd ruido dae drain dto arae qe OP 143 Functional Description 22 ebbe a 143 Reset Controller State Machine 146 Reset Controller Register Map 1 1 0 2 148 10 Voltage Regulator VR Power Supply Monitor PSM and Power Modes 151 1 5 V Voltage Detector 15 1 1 7 151 3 3 V Voltage Detector 4 152 GRE Rd E RW FR ER E EE 152 1 5 V Voltage Regulator 1 4 152 Power Supply Monitor PSM 153 PSM Block Diagram eci ee bre edd ar JR A 154 Power Up Sequence i ek ux Race eee a e teta Ga ad _________ 154 Power Down 252222 48 ee CR eg ca 154 PSM Interrupts 155 SmartFusion Power Modes 1 1 155 Control and Status Registers
366. r 2 SDA and SCL signals instead of MSS GPIO the IOMUXes are configured for open drain operation To achieve this the inverse of the 12 output signal I2C x SDAO I2C_x_SCLO is fed into the IOMUX OE A port The OUT A port of the IOMUX which is an input port into the IOMUX is tied to GND The Ic input signal I2C x SDAI or I2C x SCLI is driven by the IOMUX IN A port which is an output port on the IOMUX Revision 1 269 ___________________ Inter Integrated Circuit Peripherals Figure 14 16 shows 12 signal connections Table 14 16 2 x SDAI I2C x SDAO I2C x SCLI and I2C x SCLO Signal Connections mesero metes 2 0 SDAO 2 0 SCLO 2 1 SDAI 30 39 14 55 2 1 SDAO I2C 1 SCLI 31 40 15 56 2 1 SCLO Table 14 17 through Table 14 24 on page 272 provide descriptions for all IOMUXes associated with 2 0 and 2 1 signals IOMUX 6 Table 14 17 IOMUX 6 Io ee o axem ff dT 1 IOMUX 7 Table 14 18 7 o mes 91 fe ess p JE wee oq 270 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 47 Table 14 19 IOMUX 47 IOMUX 47 Ports LO emp O mw 7 __
367. r HREADYOUT ENVM1 CONTROL O ENVMO ENVM PIPE BYPASS ENVM SIX CYCLE RD 0 31 0 STATUS 0 1 0 Block Diagram of eNVM Controller with Two eNVM Blocks Revision 1 47 Acte Embedded Nonvolatile Memory eNVM Controller The eNVM controller consists of the following sub blocks e Flash array Contains all stored data The flash array contains 64 sectors and each sector contains 33 pages of data Page buffer A page wide volatile register A page contains 8 blocks of data and an AUX block e Block buffer Contains the contents of the last block accessed A block contains 128 data bits ECC logic The FB stores error correction information with each block to perform single bit error correction and double bit error detection on all data blocks Figure 4 2 illustrates the block diagram of an individual eNVM and its associated control logic Output RD 31 0 MUX ECC eNVM Logic Page Buffer Block Buffer WD 31 0 ADDR 17 0 DATAWIDTH 1 0 REN READNEXT PAGESTATUS WEN ERASEPAGE PROGRAM SPAREPAGE Control AUXBLOCK Logic UNPROTECTPAGE OVERWRITEPAGE DISCARDPAGE OVERWRITEPROTECT PAGELOSSPROTECT ENVM SIX CYCLE LOCK a CLK RESET 2 S
368. r 16 bit APB The address and data buses between the FIC and the FPGA fabric are common to both the AHB and APB interfaces hence only one type of interface can be enabled at any time However separate groups of signals are used for the AHB and APB control signals The type of interface chosen is determined at design time In addition to the choice of AHB or APB interfaces between the MSS and the fabric a number of options related to relative clock frequencies and pipelining of transactions are available In pipelined mode the ratio between the MSS FCLK frequency and the frequency of the AHB APB circuitry in the FPGA fabric can be 1 1 2 1 or 4 1 If the interfaces are configured as AHB and the clock ratio is 1 1 it is possible to select a bypass mode in which signals to and from the fabric are not registered In bypass mode fewer clock cycles are required to complete each transaction but the overall system frequency may be lower than is possible in pipelined mode Cortex M3 MO M1 10 100 Ethernet MAC Peripheral DMA AHB to ACE M3 M4 50 51 52 53 eSRAM 0 eSRAM 1 eNVM External AHB AHB AHB Memory Controller Controller Controller Controller Figure 19 2 Fabric Interface Controller System Overview 342 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide As shown in Figure 19 4 on page 344 on the MSS side of the FIC there are two master and slave AHB inter
369. r more information about using the MSS configurator and the Embedded FlashROM Configurator The eFROM data content can be entered directly into the FlashROM configuration window loaded from a data file in binary decimal hex or ASCII text format or serialized when used to specify eFROM contents for a large number of devices in an incrementing or decrementing series The FlashROM configurator produces a UFC file Revision 1 73 _____________ SmartFusion Embedded FlashROM eFROM which must be used when generating the SmartFusion device programming bitstream in order to write the user eFROM data into the SmartFusion physical eFROM during device programming Table 5 1 eFROM Read Write Capabilities by Access Mode Access Mode eFROM Read eFROM Write JTAG Programming Yes In Application Programming IAP Yes Directly from MSS Directly from FPGA Fabric Reading the eFROM Contents via the MSS The SmartFusion embedded FlashROM physical memory is interfaced to the SmartFusion microcontroller subsystem MSS via an APB interface controller as shown in Figure 5 2 This makes the eFROM accessible to user firmware running on the MSS through simple APB peripheral accesses between the Cortex M3 processor and the eFROM From the firmware programmer s point of view this is a memory mapped peripheral access Physically the Cortex M3 accesses the eFROM APB peripheral via the AHB bus matrix and an AHB to APB Bridge The eFROM res
370. ransmission Ready Wait for End of Transmission No Normal Collision Late Collision Yes set TDES 9 LC Late Collision Yes No Increment Attempt No Attempt 16 Set TDES 8 EC Excessive Collision Yes lt Attempt lt 10 random 0 2 ttempt 1 random 0 2 ttempt 1 ran ran random 0 210 1 ran random 0 210 1 1 Wait for ran Slot Time Next Transmission Attempt Figure 12 9 Backoff Process Algorithms 194 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Deferring The deferment algorithm is implemented per the 802 3 specification and outlined in Figure 12 10 The inter frame gap IFG timer starts to count whenever the link is not idle If activity on the link is detected during the first 60 bit times of the IFG timer the timer is reset and restarted once activity has stopped During the final 36 bit times of the IFG timer the link activity is ignored Carrier sensing is performed only when operating in half duplex mode In full duplex mode the state of the CRS input is ignored Reset IFG Timer IFG Timer 60 Bit Times IFG Timer 96 Bit Times Transmit Ready and Not in Backoff Transmit Frame Figure 12 10 Deferment Process Algorithms Revision 1 195 Aoo Meter Ethernet MAC Receive Address Filtering There are three kinds of addresses on the LAN the unicast ad
371. ransmit unless there is data in FIFO RXOVERFLOW Channel is unable to write to receive FIFO as it is full Applies to Master and Slave modes 1 RXDATRCED 1 means the number of frames specified by TXRXDFCOUNT has been received and can be read Applies to Master and Slave modes TXDATSENT 1 means the numbers of frames specified by TXRXDFCOUNT have been sent Applies to Master and Slave modes Notes 1 Bits 11 4 correspond to FIFO Status 2 None of these status bits are sticky That means during the run time the status of these bits reflects the current status of SPI 3 To determine the cause of an interrupt the Masked Interrupt Status register MIS needs to read Revision 1 235 POCA tee Serial Peripheral Interface SPI Controller SPI Interrupt Clear Register INT_CLEAR Table 13 7 INT CLEAR Bit Number Name Reset Value Description 31 4 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 3 TXCHUNDRUN W Transmit channel under run RXCHOVRFLW lt Receive channel over flow ____ TXDONECLR ow o Clears transmit done tx done Note Aread to this register has no effect It returns all zeroes SPI Receive Data Register RX DATA Table 13 8 RX DATA Bit Number Reset Reset Value _________ _____ 31 0 RXDATA
372. re no subsequent errors in the FIFO 6 TEMT R 1 Transmit empty This bit is set to 1 when both the transmitter FIFO and shift registers are empty 5 THRE R 1 Transmitter holding register empty Indicates that the UART is ready to transmit a new data byte THRE causes an interrupt to the Cortex M3 processor when bit 1 ETBEI in the Interrupt Enable Register is 1 This bit is set when the TX FIFO is empty It is cleared when at least one byte is written to the TX FIFO 4 BI R 0 Break interrupt Indicates that the receive data is at 0 longer than a full word transmission time start bit 4 data bits parity stop bits is cleared when the CPU reads the Line Status Register This error is revealed to the Cortex M3 processor when its associated character is at the top of the FIFO When break occurs only one zero character is loaded into the FIFO 3 FE R 0 Framing error Indicates that the receive byte did not have a valid stop bit FE is cleared when the CPU reads the Line Status Register The UART will try to resynchronize after a framing error To do this it assumes that the framing error was due to the next start bit so it samples this start bit twice and then starts receiving the data This error is revealed to the CPU when its associated character is at the top of the FIFO 2 PE R 0 Parity error Indicates that the receive byte had a parity error PE is cleared when the CPU reads the Line Status Register This error
373. read protected using the user pass key via the JTAG interface The user pass key must be used to change this bit setting Read protection returns all zeros when the page is read change this bit setting OVERWRITE PROTECTED 0 Page can be written to 1 Page is write protected This status bit indicates that the page was programmed or erased using either the PROGRAMMED PAGE PROTECTED or ERASE PAGE PROTECTED command WRITE PROTECTED 0 Page write protect bit is not set 1 Page is user pass key write protected JTAG write protect bit for page This bit indicates that the page has been write protected using the user pass key via the JTAG interface The user pass key must be used to Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide ENVM 1 Page Status Register Table 4 18 ENVM PAGE STATUS 1 REG Bit m Vm 31 8 WRITE COUNT write count The number of times the has been written to Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation OVER THRESHOLD 0 Page is under threshold 1 Page is over threshold READ PROTECTED 0 Page can be read 1 Page is user pass key read protected JTAG read protect bit for page This bit indicates that the page has been read protected using the user pass key via the JT
374. reserved across a read modify write operation Inverse filtering read only If this bit is set when working in a perfect filtering mode the receiver performs an inverse filtering during the address check process The filtering type bits of the setup frame determine the state of this bit 206 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Table 12 31 CSR6 continued Pass bad frames When set Ethernet MAC transfers all frames into the data buffers regardless of the receive errors This allows the runt frames collided fragments and truncated frames to be received Hash only filtering mode read only When set Ethernet MAC performs an imperfect filtering over both the multicast and physical addresses The filtering type bits of the setup frame determine the state of this bit Start stop receive command Setting this bit enables the reception of the frame by Ethernet MAC and the frame is written into the receive FIFO If the bit is not enabled then the frame is not written into the receive FIFO Setting this bit when the receive process is in a stopped state causes a transition into a running state In the running state Ethernet MAC checks the receive descriptor at the current descriptor list position If Ethernet MAC owns the descriptor it can process an incoming frame When the host owns the descriptor the receiver enters a suspended state and also sets the CSR5 7 receive buffer una
375. rface and IOMUX section on page 341 for a more thorough description of how IOMUXes operate IOMUXes for I2C x SDAI I2C x SDAO I2C x SCLI and I2C x SCLO To use the I2C x SDAI I2C x SDAO 2 x SCLI and I2C x SCLO signals an IOMUX is used to route the signals to an MSSIOBUF This IOMUX is used to share the MSSIOBUF between the l C signals and a GPIO 268 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Figure 14 4 shows the IOMUX topology I2C 0 SDAI and I2C 0 SDAO which applies to I2C 0 SCLI and I2C 0 SCLO I2C 1 SDAI and 2 1 SDAO and I2C 1 SCLI and I2C 1 SCLO as well 200 IOMUX _6 MSSIOBUF _X I2C 0 SDAI 2 0 SDAO GPIN 22 SRC GPIO 22 GPI 22 GPO 22 GPOE 22 IOMUX 47 X Not connected to I O pad X Not connected to I O pad X Not connected to I O pad M2F 31 F2MI31 F2M OE 31 FPGAIOBUF X FPGA Fabric Figure 14 4 2 0 SDAI and I2C 0 SDAO IOMUX Topology In this case IOMUX 6 is configured to connect all three interface A ports IN A OUT A and OE A to the MSSIOBUF IOMUX 47 can be configured to route the GPIO 22 signals to the fabric interface The M2F 31 F2M 31 and F2M OE 31 can then be routed to an FPGAIOBUF using the Actel Libero Integrated Design Environment IDE tool Similar configuration applies to I2C 0 SCLI and 2 0 SCLO 2 1 SDAI and 2 1 SDAO and I2C 1 SCLI and 2 1 SCLO When utilizing the MSSIOBUF fo
376. ric Interface Interrupt Controller 0x40007000 0x40007FFF Watchdog 0x40006000 0x40006FFF Timer 0x40005000 0x40005FFF Peripheral DMA 0x40004000 0x40004FFF Ethernet MAC 0x40003000 0x40003FFF 200 0x40002000 0x40002FFF SPI O 0x40001000 0x40001FFF UART 0 0x40000000 0x40000FFF 0x24000000 Ox3FFFFFFF 0x22000000 0x23FFFFFF 020010000 0x21FFFFFF Cortex M3 eSRAM 1 eSRAM 1 0x20008000 0x2000FFFF System Region eSRAM 0 eSRAM 0 0x20000000 0x20007FFF 000088200 ox FEFFEFF Code Region 0x000881FF eNVM Cortex M3 eNVM fabric T Virtual View Virtual View Visible only to FPGA Fabric Master 0x00080000 Ox0000FFFF eSRAM 1 0x00000000 0x00007FFF eSRAM 0 0x00000000 Figure 2 6 Memory Map with eSRAM Remapped 22 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide This scheme allows flexibility to the system designer as to how much eSRAM is to be dedicated to each class of storage For example if the application stack and heap are small this allows a large chunk of contiguous RAM to be allocated to buffering If on the other hand the system designer is more interested in optimal performance than flexibility then eSRAM 0 could be dedicated to the application and ISRs while eSRAM 1 would be dedicated to stack heap and buffering This would mean that the Cortex M3 operates in a fully Harvard fashion since e
377. ring the EMC Table 7 8 gives the bit definition for EMC MUX CR and Table 7 9 lists the bit definitions for the EMC CS x CR where x is either 0 or 1 signifying chip select 0 or chip select 1 Table 7 7 External Memory Controller Register Map Reset Address R W Value Description EMC MUX CR 0 004203 R W 0x0 External memory controller MUX configuration EMC CS 0 CR 0xE0042040 EMC timing parameters for chip select 0 EMC CS 1 CR OxE0042044 EMC timing parameters for chip select 1 Table 7 8 MUX CR Bit Number Description Multiplexed control Table 7 9 CS x CR umer www ie __ Number Description i 21 20 z Table 7 10 lists the different types of memory that can be seamlessly connected to the EMC Users are free to assign any memory type to one chip select and any other memory type to the other chip select constrained only by the types listed in Table 7 10 XN Table 7 10 EMC_MEMTYPEx Field Definition No memory assigned to chip select x Asynchronous PSRAM memory assigned to chip select x Synchronous memory assigned to chip select x NOR flash memory assigned to chip select x Revision 1 95 ________________ External Memory Controller Valid configurations are illustrated in Table 7 11 If EMC MEMTYPEx has a value of 0b00 and an AHB bus matrix master attempts to access that region of memory the EMC will return an error and
378. ripherals FREQ Register Table 14 14 FREQ Bit Reset Number R W Value Description 7 0 FREQ RAV 0x08 PCLKx frequency in MHz from 1 to 255 If the PCLKx frequency is used and SMBus is enabled the SMBus timeouts will be configured per the SMBus specification If another timeout value is desired scale the Frequency value per the following formula Timeout scale Fscale Factual If the actual PCLKx frequency is 100 Mhz and a scale down is desired that results in a 3 ms timeout rather than 25 ms timeout then Fscale 3 25 x Factual 0 12 x 100 12 Mhz Writing 12 into the FREQ register will have the effect of reducing the maximum timeout count value and thus reducing the real time timeout from 25 ms to 3 ms GLITCHREG Register Table 14 15 GLITCHREG Bit Reset Number R W Value Description 7 0 GLITCHREG RAW 0x03 The number of registers in the glitch filter can be set to a value from 3 to 6 Correct value to meet 12 fast mode 50 ns spike suppression will depend on the PCLK frequency Guideline PCLK Freq MHz GlitchReg Value for 50 ns Spike Suppression Freq lt 403 40 lt Freq lt 604 60 Freq x 805 80 lt Freq lt 1006 IOMUXes Associated with 2 0 and 2 1 IOMUXes 6 7 47 and 48 are used to multiplex 12 0 GPIO and fabric interface signals to MSSIOBUFs IOMUXes 14 15 55 and 56 are used to multiplex I2C 1 GPIO and fabric interface signals to MSSIOBUFs Refer to the Fabric Inte
379. rite operation Receive stopped enable When both the RSE and AIE bits are set the receive stopped interrupt is enabled Receive buffer unavailable enable When both the RUE and AIE bits are set the receive buffer unavailable is enabled Receive interrupt enable When both the RIE and NIE bits are set the receive interrupt is enabled Underflow interrupt enable When both the UNE and AIE bits are set the transmit underflow interrupt is enabled Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation B Ww gt Transmit buffer unavailable enable When both the TUE and NIE bits are set the transmit buffer unavailable interrupt is enabled c Transmit stopped enable When both the TSE and AIE bits are set the transmit process stopped interrupt is enabled Transmit interrupt enable When both the TIE and NIE bits are set the transmit interrupt is enabled 210 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Missed Frames and Overflow Counter Register CSR8 Table 12 36 Missed Frames and Overflow Counter Register CSR8 Bits 15 8 MFC 15 8 Note The CSR8 register has unimplemented bits shaded If these bits are read they will return a predefined value as shown in Table 12 37 Writing to these bits has no effect
380. rtex M3 If set to 0 interrupt is masked Revision 1 233 Serial Peripheral Interface SPI Controller Table 13 4 CONTROL continued VActel Bit Number Name R W Reset Value Description 5 INTTXDATA RAV 0 Interrupt on transmit data If set to 1 interrupt is not masked and will result in interrupt to Cortex M3 If set to 0 interrupt is masked INTRXDATA 0 Interrupt on receive data If set to 1 interrupt is not masked and will result in interrupt to Cortex M3 If set to 0 interrupt is masked 3 2 TRANSFPRTL RAV 0 Transfer protocol Decode 0600 Motorola SPI 0b01 TI Synchronous Serial 0b10 National Semiconductor MICROWIRE 0611 Reserved Note The transfer protocol cannot be changed while the SPI is enabled MODE R W 1 SPI implementation 0 Slave 1 Master default 0 ENABLE RAV 0 Core enable 0 Disable default 1 Enable Core will not respond to external signals SPI x DI SPI x DO until this bit is enabled SPI x CLK is driven low and SPI x OEN and SPI x SS slave select are driven in active Note All the registers are accessible to Cortex M3 even when the core is disabled SPI TxRx Data Frame Register TXRXDF SIZE Table 13 5 TXRXDF SIZE R W Reset Value R W R W Bit Number 234 Name Description Reserved Software should not rely on the value of a reserve
381. rupt is generated after 35 ms e A slave device will enter the reset state D8 after 25 ms and an interrupt will be generated Once the interrupt is asserted the APB controller of the slave device needs to clear the interrupt within 10 ms per the SMBus Specification v 2 0 and the slave device enters the idle state F8 After 35 ms the master device s interrupt will be asserted and the controller of the master device needs to clear the interrupt forcing the master device into the idle state F8 Host Master resets 25 ms 35 ms Host clears bit and the bus releases bus entering Z state F8 SCL Host 35 ms timeout interupted bit set still DO Host sets SMBUS RESET i i 8 Slave Reset Status Set state until cleared Bit clock line goes low Slave APB Controller must clear interupt within 10 ms 2 Master Int enters idle mode F8 Master Status Slave Int Figure 14 3 SMBus Bus Reset Sequence Interrupts There are three interrupt signals from each 2 peripheral The I2C 0 INT I2C 0 SMBALERT I2C 0 SMBSUS signals are generated by I2C 0 and are mapped to IRQ 14 IRQ 15 and IRQ 16 in the Cortex M3 controller The 2 1 INT I2C 1 SMBALERT and 2 1 SMBSUS signals generated by I2C 1 and are mapped to IRQ 17 IRQ 18 and IRQ 19 in the Cortex M3 NVIC controller All interrupt enable bits within the are located at address 0 000 100
382. s The AHB to APB bridges in SmartFusion implement posted writes also called dump and run for write accesses to peripherals The effect of this is that if the PDMA performs a write operation to a peripheral the data is not actually written into the peripheral until sometime after the PDMA block thinks it is written Therefore the PDMA block should not start another DMA on this channel based on the state of the ready signal from that peripheral until the write is complete The time window involved is variable depending on the ratio of FCLK to the APB clocks PCLKO PCLK1 or ACLK WRITE ADJ in CHx CONTROL REG is an 8 bit binary coded field used to define for each DMA channel how long to wait in FCLKs after each DMA transfer cycle before interpreting the ready signal for that DMA channel as representing a new request Memory to Memory Transfers For memory to memory transfers the starts once the BUF COUNT or BUF B COUNT is zero Firmware should initialize the transfer first by writing to the source destination and control registers then writing to one of the transfer count registers BUF A COUNT or BUF COUNT to initiate the DMA If the PAUSE bit in CHx CONTROL REG is set when the user writes a non zero value to either BUF A COUNT or BUF B COUNT the DMA cycle will wait until PAUSE is cleared Channel Priority The arbitration algorithm used to service the channels assumes all channels are equal priority by default How
383. s Address Range Generic initial data blocks and Dependent on user design 0x600816CC 0x60081F7F PPE RAM merge operations MSS configuration 2 0x60081618 0x600816CB Analog block configuration __ 0x60081600 0x60081617 iM 3 n 0x60080000 0x600803FF The eNVM address bus decodes sectors pages blocks and bytes as shown in Figure 4 4 17 12 11 07 06 04 03 00 Figure 4 4 Sector Page Block and Byte Addressing Scheme 50 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 4 3 depicts the size of the various eNVM sections in bytes for each SmartFusion family member There are two physical eNVM blocks in the A2F500 that are logically mapped into Cortex M3 memory space as one eNVM The eNVM controller manages mapping the two separate memory blocks as one logical contiguous memory for all sections eNVM array spare pages Aux block array and Aux block spare pages Note however when reading from ENVM 0 the spare page in sector 63 returns all zeros For those devices with two eNVM blocks reading from ENVM_1 the spare page in sector 63 also returns zeros Register or bit descriptions that follow will indicate which eNVM is affected by a user operation For example BUSY 0 indicates ENVM 0 is busy In devices with two eNVMs each memory section is split logically in two with the bottom half addressing ENVM 0 and the top half of the memory section addressin
384. s Matrix Register Bit Definitions The AHB bus matrix control registers are located in the system registers address space at 0xE0004000 and extend to address OxEOOO4FFF in the Cortex M3 memory map eSRAM Configuration Register Table 2 3 CR Bit Reset Number R W Value Description 31 1 Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 No remapping of the eSRAMs occurs 1 eSRAM 0 is mapped to location 0x00000000 and eSRAM 1 is mapped directly above it ui ESRAMFWREMAP Remap of embedded SRAMs 24 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide eNVM Configuration Register Table 2 4 ENVM CR Bit Reset Number Name R W Value Description 31 8 Reserved RAV 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 7 ENVM SIX CYCLE RAV 1 0 No extra delay when reading from eNVM 1 Reads from eNVM will have one extra clock cycle of delay 6 ENVM PIPE BYPASS RAV 0 0 Pipeline bypass disabled 1 Pipeline bypass enabled 5 Reserved R W 0 Reserved 4 0 COM ENVMREMAPSIZE RAW 0610010 COM ENVMREMAPSIZE indicates the size of the segment in eNVM whic
385. s appropriate to the address being used on the AHB Efficient use of memory storage is achieved in this manner even if only performing byte or 16 bit accesses to or from a peripheral For accesses by the PDMA to peripherals the lowest 8 or 16 bits of the data bus are always used for 8 bit or 16 bit transfers For 32 bit transfers the full 32 bits are used It is possible to configure the data width of a transfer to be independent of the address increment The address increment at both ends of the DMA transfer can be different which is required when reading from a peripheral holding register single address and writing to memory incrementally many addresses DMA transfers can be paused by setting the PAUSE bit in the CHx_CONTROL_REG The DMA will stall until the user clears this bit The PDMA performs single cycle accesses on the AHB interface No DMA operations occur on the APB bus interface of the PDMA This interface is purely an APB slave used for configuration of the PDMA For each peripheral DMA channel 0 to 7 two sets of registers are maintained in the PDMA These are set up by firmware in order to specify the start address of the DMA burst the destination address of the DMA burst and the transfer count of the DMA burst for each of the two buffers This is called ping pong mode Ping Pong Mode In order to support continuous DMA operations on each peripheral DMA channel dual buffering is provided along with two sets of reg
386. s cleared Error summary This bit is a logical OR of the following bits RDESO 1 CRC error RDESO 6 Collision seen RDESO 7 Frame too long RDESO 11 Runt frame RDESO 14 Descriptor error This bit is valid only when RDESO 8 last descriptor is set Descriptor error Set by Ethernet MAC when no receive buffer was available when trying to store the received data This bit is valid only when RDESO 8 last descriptor is set When set indicates that the frame is damaged by a collision or by a premature termination before the end of a collision window This bit is valid only when RDESO 8 last descriptor is set Multicast frame When set indicates that the frame has a multicast address This bit is valid only when RDESO 8 last descriptor is set First descriptor When set indicates that this is the first descriptor of a frame Last descriptor When set indicates that this is the last descriptor of a frame Revision 1 181 Ethernet MAC 182 VActel Table 12 3 Receive Descriptor 0 RDESO Bit Functions continued RN Frame too long When set indicates that a current frame is longer than maximum size of 1 518 bytes as specified by 802 3 TL frame too long in the receive descriptor has been set when the received frame is longer than 1 518 bytes This flag is valid in all receive descriptors when multiple descriptors are used for one frame Collision seen When set indicates
387. sh the transmission of the frame data corresponding to the current descriptor and then move to the stopped state The status bits of the CSR5 register should be read to check the actual transmit operation state Before giving the Stop Transmit command the transmit state machine in CSR5 can be checked If the transmission state machine is in SUSPENDED state the Stop Transmit command can be given so that complete frame transmission by MAC is ensured Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Full duplex mode 0 Half duplex mode 1 Forcing full duplex mode Changing of this bit is allowed only when both the transmitter and receiver processes are in the stopped state Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Pass all multicast When set all frames with multicast destination addresses will be received regardless of the address check result Promiscuous mode When set all frames will be received regardless of the address check result An address check is not performed Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be p
388. shown latency cycle is removed from the timing diagram Read Latency Remaining Accesses RDLATRESTXx The field EMC RDLATRESTx determines the number of latency cycles for the remaining read accesses for the respective chip select where x defines which chip select is applicable Each cycle is defined to be 1 FCLK period Zero to a maximum of 15 latency cycles can be programmed by the user For asynchronous and flash memory types the EMC RDLATRESTx latency cycles are inserted between clock edges 4 X and 4 X Y as shown in Figure 7 18 on page 101 Asynchronous Read Cycle where Y is the value programmed into EMC RDLATRESTx Read latency cycles for access 3 are inserted between edges 6 X Y and 6 X 2Y Read latency cycles for access 4 are inserted between edges 8 X 2Y and 8 X Note that for Y 0 the shown latency cycle s are removed from the timing diagram For synchronous memory types with EMC PIPERDNx 1 EMC RDLATRESTx latency cycles are inserted between clock edges 4 X 1 and 4 X 1 Y 1 as shown in Figure 7 19 on page 102 Non Pipelined Synchronous Read Cycle EMC RDLATRESTx latency cycles for access 3 are inserted between edges 6 X 1 Y 1 and 6 1 2 Y 1 RDLATRESTx latency cycles for access 4 are inserted between edges 8 X 1 X 2 Y 1 and 8 X 1 3 Y 1 Note that for Y 1 the shown latency cycle is removed from the timing diagram For
389. sion Secure ISP Secure IAP of SmartFusion devices is accomplished by using the IAP driver Only the FPGA fabric and the eNVM can be reprogrammed securely by using the IAP driver References Application Notes In System Programming ISP of Actel s Low Power Flash Devices Using FlashPro3 http www actel com documents LPD ISP HBs pdf Security in Low Power Flash Devices http www actel com documents LPD Security HBs pdf Programming Flash Devices http www actel com documents Flash Program HBs pdf Microprocessor Programming of Actel s Low Power Flash Devices http www actel com documents LPD Microprocessor HBs pdf User s Guides DirectC User s Guide http www actel com documents DirectC UG pdf Revision 1 375 VActel POWER MATTERS 21 SmartFusion Master Register Map Table 21 1lists all registers in the SYSREG space Table 21 1 Registers in the SYSREG Space ESRAM CR 0 0042000 Rw 1 Controls address mapping of the eSRAMs ENVM CR 0 0042004 Configures eNVM parameters ENVM REMAP SYS CR 0xE0042008 RAV Configures where eNVM is mapped in system space ENVM CR OxE004200C RAV 20 Configures where eNVM is mapped in fabric master space FAB PROT SIZE CR 0xE0042010 5 Defines the size of the memory that is inaccessible by a Fabric Master FAB_PROT_BASE_CR 0xE0042014 32 The absolute memory address of the memory region protected from Fabric Access memuum w T
390. ss a read modify write operation 24 23 VCOSEL 2 1 R W Specifies the PLL lock acquisition time and tracking jitter See Table 8 29 22 VCOSEL 0 RAV 0 Fast PLL lock acquisition time with high tracking jitter 1 Slow PLL lock acquisition time with low tracking jitter 21 XDLYSEL RAV Setting this bit to a 1 adds an additional 2 ns typical delay to the output of the PLL feedback selected by the FBSEL control bits 20 16 FBDLY R W FBDLY sets the delay from the PLL VCO 0 phase shift output to the feedback input of the PLL A value of 0 has a typical delay of 535 ps every time FBDLY is incremented 200 ps is added to the base delay See Table 8 30 on page 139 15 14 FBSEL RW Selects the multiplexer input See Table 8 31 on page 139 13 7 FBDIV RAV FBDIV defines the feedback clock divider m value Divides the PLL feedback clock frequency by the value stored in FBDIV 6 0 1 FINDIV RAV FINDIV defines the input clock divider n value Divides the input clock frequency to the PLL by the value stored in FINDIV 6 0 1 VCOSEL 2 1 Table 8 29 gives bit definitions for VCOSEL Table 8 29 VCOSEL 2 1 Bit Definitions VCOSEL 2 1 VCO Output Range in MHz Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide FBDLY Table 8 30 gives bit definitions for FBDLY Table 8 30 FBDLY Bit Definitions FBDLY _ o3 L3
391. stem User s Guide When the MATCH signal is active the bit bit 0 in the DSS STATUS Register will be set This bit is used as an interrupt to the Cortex M3 This bit will remain set until cleared by writing to the CLRRTCMATCHEVENT bit bit 0 in the CLR DSS STATUS Register Both the counter and match registers are addressable read write from the 0 bus interface The counter action can be suspended resumed by clearing setting the CNTR EN bit in the CTRL STAT REG register This allows the RTC to be used for measuring intervals in time If a 32 768 KHz external resonator is connected to the low power crystal oscillator pins the 40 bit counter will have a maximum count of 4 294 967 296 seconds which equates to just over 136 years of elapsed timekeeping with a minimum period of 1 256 of a second which will be the toggle rate of the LSB of the 40 bit counter Frequencies other than 32 768 KHz can be used as a clock source with the appropriate scaling of the LSB time interval A 7 bit prescaler is used to divide the source clock from the external crystal by 128 This prescaled 5096 duty cycle clock is then used by the counter logic as its reference clock Given an external crystal frequency of 32 768 KHz the prescaler output clock will toggle at a rate of 32 768 KHz 128 256 Hz The 40 bit counter and match registers are each divided into five bytes Each byte is directly addressable APB reads and writes mus
392. ster Bit 4 Cortex M3 I Code D Code bus master These signals are not used as interrupts to the Cortex M3 Instead they are ORed together in the AHB bus matrix to create a signal called ABM ERROR IRQ which is used as an interrupt to the Cortex M3 This signal corresponds to 24 in the Cortex M3 NVIC IRQ24 corresponds to bit location 24 in the 32 bit word at address location OxE000E100 ABM ERROR IRQ is not brought into the System Register s space as a status bit for user s firmware to read 32 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Indicates that the 3 3 V supply has dropped below 2 5 V This signal corresponds to IRQ 2 in the Cortex M3 NVIC IRQ 2 corresponds to bit location 2 in the 32 bit word at address location 0 000 100 0 2 Don t care 1 3 3 V has fallen below 2 5 V Table 2 13 MSS SR continued Indicates that the 1 5 V supply has dropped below 1 3 V This signal corresponds to IRQ 1 in the Cortex M3 NVIC IRQ 1 corresponds to bit location 1 in the 32 bit word at address location 0 000 100 0 Don t care 1 1 5 V has fallen below 1 3 V This signal is a sticky version of the WDOGTIMEOUTINT signal which is itself sticky but is cleared by MSS SYSTEM RESET WDOGTIMEOUTEVENT is not affected by MSS SYSTEM RESET This allows firmware to determine if a system reset occurred due to a watchdog timeout event This signal is not used as an interrupt to
393. synchronous memory types with PIPERDNx 0 RDLATRESTx is ignored Write Latency WRLATXx The field EMC WRLATx determines the number of write latency cycles for the respective chip select where x defines which chip select is applicable Each cycle is defined to be 1 FCLK period From 0 to a maximum of 15 latency cycles can be programmed by the user For asynchronous and flash memory types write latency cycles are inserted between clock edges that are shaded in Figure 7 21 on page 104 where W is the value programmed into EMC WRLATx Note that 0 the shown latency cycle is removed from the timing diagram For synchronous memory types with EMC PIPEWRNXx 1 write latency cycles are inserted between clock edges 2 and 2 W 1 4 W 1 and 4 2 W 1 6 2 W 1 and 6 3 W 1 and 8 3 W 1 and 8 4 W 1 as shown in Figure 7 23 on page 106 Non Pipelined Synchronous Write Cycle Note that for X 1 the shown latency cycle is removed from the timing diagram For W 0 the cycle between edges 2 W 1 and W 1 is coincident with the cycle between edges 1 and 2 and similarly for the other accesses 98 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide For synchronous memory types with PIPEWRNXx 0 write latency cycles are inserted between clock edges 5 and 5 W 1 for rows 0 11 and between clock edges 2 and 2 W 1 for r
394. t 1 Keep the _0 memory controller in reset ENVM SR RAV 0 Release the ENVM memory controller from reset 1 Keep the ENVM memory controller in reset Revision 1 149 VActel POWER MATTERS 10 Voltage Regulator VR Power Supply Monitor PSM and Power Modes VCC33A VCC The VR and PSM provide the user with various ways to define how SmartFusion devices power up and power down This section describes the functionality of these blocks and how they can be configured to achieve various power profiles A high level block diagram is shown in Figure 10 1 Reset PORESET Status SYS REG Control Control VCC 15 VCC15UP VCC15GOOD VCC15INT Detect MSS Reset VCC33A PUPO PTBASE 54 VR Int X TASTE Voltage E a FPGAVRON Regulator FPGAVRONENABLE V MSSVRON RTM MATCH PUN PUFAB N Figure 10 1 VR and PSM Block Diagram 1 5 V Voltage Detector VCC15UP This block see Figure 10 4 on page 154 has a single input VCC and a single active high output VCC15UP When the VCC supply is below a threshold approximately 0 8 V depending on process and temperature variables the output is low When VCC is above this threshold the output is high A small amount of hysteresis is included in the voltage detector to reduce the possibility of oscillation VCC15UP is routed to the power supply monitor where it is compared against the pr
395. t To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation a FAB AHBIF oR 1 See Table 19 3 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be ene across a read modify write operation FAB_AHB_BYPASS RAV FIC is in pipeline mode 1 is in bypass mode Table 19 3 Bus Type Selection FAB IF CR a ca If the MSS FCLK to FPGA fabric clock ratio is 1 1 and the FIC is configured to operate in 32 bit AHB mode as described in Table 19 3 the FIC can be configured to operate in bypass mode Signals to and from the fabric are not registered in bypass mode If however the FIC is configured in APB mode 16 or 32 bit or the clock ratio between the MSS and the fabric is not 1 1 the user must set the FIC to pipeline mode as outlined in Table 19 4 The configuration of FAB_IF_CR and FAB_AHB_BYPASS should not be performed dynamically The MSS configurator creates the system boot initialization code that initializes the state of these fields to the user s desired configuration Table 19 4 FIC Bypass Mode Selection FAB_IF_CR FAB_AHB_BYPASS The fabric interface is configured in pipeline mode that is registered mode default state The fabric interface is configured for bypass mode 346 Revision 1 VActel Actel SmartFusio
396. t Controller RSTC The reset controller is used to reset all components of the Ethernet MAC It generates a reset signal asynchronous to all clock domains in the design from power on reset and software reset Software Reset Software reset can be performed by setting the CSRO O SWR bit The software reset will reset all internal flip flops The MAC SR bit of SOFT RST CR 0 0042030 in system registers also acts as a software reset of the Ethernet MAC Refer to the Reset Controller section on page 143 for more information Interface Signals The signals shown in Table 12 1 are included in the Ethernet MAC Table 12 1 Signals included in Ethernet MAC Polarity Type Bus Size Description RMII PHY Interface MAC RXER In High Receive error If RX ER is asserted during Ethernet MAC reception the frame is received and status of the frame is updated with RX ER MAC CRSDV In High Carrier sense and receive data valid This signal must be asserted by the PHY when either a receive or transmit medium is non idle The PHY device should assert MAC CRSDV when valid data is provided on the RXD signal MAC MDIO In Out RMII management data input and output The state of the input signal can be checked by reading the CSR9 19 bit The output signal is driven by the CSR9 18 bit MAC RXD 1 0 In 2 Receive data recovered and decoded by PHY The RXD 0 signal is the least significant bit MAC_TXEN Out High Transmit enable When asserted indi
397. t Filtering Mode 16 physical addresses 16 physical addresses perfect filtering mode filtering mode p physical address p physical addresses and 512 bit hash table for multicast addresses 512 bit hash table for both physical and multicast addresses S 3 5 p 22 27 S 3 o 22 27 eesimenfae ES LS S LU Table 12 33 lists the transmit FIFO threshold levels These levels are specified in bytes Table 12 33 Transmit FIFO Threshold Levels Bytes CSR6 21 CSR6 15 14 CSR6 22 1 CSR6 22 0 Boom 1 4 1 4 BULL B SL m 208 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Interrupt Enable Register CSR7 Table 12 34 Interrupt Enable Register CSR7 mena mes ee mers ue wc we po opum Note The CSR7 register has unimplemented bits shaded If these bits are read they will return a predefined value as shown in Table 12 35 Writing to these bits has no effect Table 12 35 CSR7 0b111100111111111 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify
398. t be word aligned The address map of registers is shown below Real Time Counter Register Interface Summary Table 16 1 describes the Real Time Counter Register interface Table 16 1 Real Time Counter Register Map __ S oum nec mW 9 Counterbisis8 RW coenterbis zs oum wow mw 9 eeterbissizt RES RW cowterbissss IMATCHREGO_REG oou mW 3 VshRegisterbis78 REG RW egisterbis 58 IMArcHREG2 REG mW 9 Sench Register bis 2516 IMATCHREGS REG mW 5 Fegisterbis 24 IMATCHREGA REG oos RW S Sench Register bis 3932 Marres Res RW 5 reividusi Watch biz arcen ooa RW o reiidusi Mate bis 58 wow RW 5 reividusi Match 2216 EIU CANI UAM MM NN 7288 9 individual Match bits 3932 CTRL STAT REG 0x40014160 SUE __ neice Maken is 3 write Status read register bits 7 0 Note Accessing RTC Registers When reading the RTC count or match register which operates in the XTLCLK domain the appropriate 40 bit value is first copied to a capture regis
399. t counter is updated as one 64 bit value There are temporary holding registers in the System Timer block that are used to facilitate proper loading of the System Timer in 64 bit mode These registers are not readable by the user System Dependencies Clocks The System Timer is clocked by PCLKO on Bus 0 PLCLKO is a free running version of FCLK the main clock driving the entire microcontroller subsystem that is derived from the MSS CCC output Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 for more information Revision 1 303 _________________________ _ Acte System Timer Resets The System Timer resets to zero on power up and is held in reset until you enable it You have the option under software control to reset the System Timer by writing to the System Register located on the Private Peripheral Bus of the Cortex M3 Specifically this System Register is SOFT RST CR located at address 0xE0042030 The TIMER SOFTRESET control bit is encoded in bit location 6 as follows b6 Function 0 System Timer reset released 1 System Timer held in reset reset value Note that setting bit 6 to 0 allows the System Timer to count but does not cause it to count You must enable the System Timer by setting the appropriate TIMxENABLE bits in the 1 CTRL TIM2 CTRL or TIM64 CTRL registers Interrupts There are two interrupt signals from the System Timer Block the TIMER
400. t descriptor list This address must be 32 bit word aligned TLA 1 0 0 Revision 1 201 Ethernet MAC VActel Status and Control Register CSR5 Table 12 28 Status and Control Register CSR5 mena Bits 23 16 TS NL mess as m pee mers ue cpu om on Note The CSR5 register has unimplemented bits shaded If these bits are read they will return a predefined value as shown in Table 12 29 Writing to these bits has no effect Table 12 29 CSR5 31 23 EN 0b111100000 202 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Transmit process state read only Indicates the current state of a transmit process 000 Stopped RESET or STOP TRANSMIT command issued 001 Running fetching the transmit descriptor 010 Running waiting for end of transmission 011 Running transferring data buffer from host memory to FIFO 100 Reserved 101 Running set up packet 110 Suspended FIFO underflow or unavailable descriptor 111 Running closing transmit descriptor Receive process state read only Indicates the current state of a receive process 000 Stopped RESET or STOP RECEIVE command issued 001 Running fetching the receiv
401. t should be preserved across a read modify write operation 2 LOCK RAV 0 Disabled 1 eNVM disabled from JTAG access The LOCK bit is used to give the user control over access to the eNVM from the JTAG interface When LOCK is asserted the JTAG interface will be prevented from any access attempts to the eNVM until LOCK is deasserted For example if a fabric master has access to the eNVM and does not want a JTAG operation to command or control the eNVM the fabric master should set the LOCK bit Likewise if you only allow eNVM access via the Cortex M3 and want to prevent the JTAG interface from accessing the eNVM you should set the LOCK bit PAGE LOSS 0 Disabled 1 Page loss protection enabled When the PAGE LOSS bit is set to 1 it prevents writes to READ NEXT any page other than the current page in the page buffer until the page is either discarded or programmed A write to another page while the current page is Page Loss Protected will set the BUSY O bit and the PROT ERROR 0 if the operation was performed on ENVM 0 for example 0 Disabled 1 Read next command enabled 68 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide 1 Configuration Register Table 4 16 ENVM 1 CR Bit Mie mme mw reset 31 3 Reserved Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should
402. t size The power of 2 size specified by COM ENVMREMAPSIZE defines how many bits of base address are used For example if the COM ENVMREMAPSIZE is OxOf this corresponds to a segment size of 64 Kbytes which is 216 Therefore the value of in this case is 16 The base address of the region in this case is specified by COM ENVMREMAPBASE 19 16 For example 1 COM ENVMREMAPBASE 19 16 0x0 The 64 Kbytes segment located at the physical memory address of 0x60000000 is mapped into address 0x00000000 2 COM ENVMREMAPBASE 19 16 0 1 The 64 Kbytes segment located at the physical memory address of 0x60010000 is mapped into address 0x00000000 3 COM ENVMREMAPBASE 19 16 0 2 The 64 Kbytes segment located at the physical memory address of 0x60020000 is mapped into address 0x00000000 If the user attempts to remap a segment of eNVM that does not exist unpredictable results will occur Revision 1 27 Bus Matrix Table 2 8 VActel eNVM FPGA Fabric Remap Base Address Register ENVM REMAP FAB CR Bit Number Name R W Reset Value Description 31 20 Reserved 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 19 1 COM ENVMFABREMAPBASE 0 Offset address of eNVM for remapping COM ENVMFABREMAPBASE indicates the offset within eNVM address space of the
403. t special signals like output enable can be deactivated at the end of a transfer For example consider the transmission of 64 KB of data to an external EEPROM from the Cortex M3 controlled SPI controller The data frame size is set to 8 and the number of data frames per transfer is set to 1 After each transfer the software must respond to the interrupt transmit done and reload the FIFO until all 64 KB are sent To improve throughput the number of data frames per each transfer can be set to 4 to utilize the full depth of the transmit FIFO PDMA Mode In this mode interrupts are turned off and the PDMA engine uses the SPITXRFM and SPIRXAVAIL signals to control the filling and emptying of the transmit and receive FIFOs The SPITXRFM is connected to the transmit FIFO not full flag SPIRXAVAIL is connected to the receive FIFO not empty flag In DMA mode the TXDONE and RXRDY interrupts are masked in RIS and the interrupt capability in the PDMA engine is used to notify the application on completion For more information on PDMA refer to the Peripheral DMA PDMA section on page 35 For example consider the transmission of 64 KB data to an external EEPROM from a PDMA controlled SPI controller The data frame size is set to 8 and the number of data frames per transfer is set to 1 The transmit FIFO is repeatedly emptied by the PDMA engine using the SPITXRFM signal 222 Revision 1 VActel Actel SmartFusion Microcontroller Subsyste
404. t that one bit in the hash table corresponds to many Ethernet addresses Therefore it is possible that some frames may be accepted by Ethernet MAC even if they are not intended to be received This is because some frames that should not have been received have addresses that hash to the same bit in the table as one of the proper addresses The software should perform additional address filtering to reject all such frames 196 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Software Interface Ethernet MAC Control and Status Register Addressing The Control and Status registers are located physically inside Ethernet MAC and can be accessed directly by the Cortex M3 processor via a 32 bit interface All the CSRs are 32 bits long and quadword aligned The address bus of the CSR interface is 8 bit wide and only bits 6 0 of the location code shown in Table 12 16 are used to decode the CSR register address Ethernet MAC Base Address 0x40003000 Table 12 16 12 CSR Locations Register Name Address Reset Value Description CSRO 0x40003000 A OxFEO00000 Bus Bus mode CSR1 0x40003008 L l Transmit poll demand CSR2 0x40003010 o Receive poll demand CSR3 0x40003018 OxFFFFFFFF Receive list base address CSR4 0x40003020 OxFFFFFFFF Transmit list base address CSR7 0x40003038 OxF3FEO000 Interrupt enable CSR8 0x40003040 OxE0000000 Missed frames and overflow counters CSR9 0x40003048 OxFFF483FB
405. tatus Register Slave Transmitter Mode Status DATA Register CTRL SEES bits Code Status Action STA STO SI Next Action Taken by Core OxA8 Own SLA R has been Load data byte Lm data byte will be transmitted received ACK has ACK will be received or load data byte Data byte will be transmitted ACK will be received OxBO j Arbitration lost Load data byte X Last data byte will be transmitted SLA RAW as master ACK will be received SER nas been or load data byte X Data byte will be transmitted ACK received ACK has will be received OxB8 Data byte has Load data byte X Last data byte will be transmitted transmitted ACK has ACK will be received orload data byte X Data byte will be transmitted ACK will be received or no action Switched to not addressed SLV mode own SLA or general call address will be recognized or no action Switched to not addressed SLV mode no recognition of own SLA or general call address START condition will be transmitted when the bus becomes free or no action Switched to not addressed SLV mode own SLA or general call address will be recognized START condition will be transmitted when the bus becomes free OxCO Data byte has been No action Switched to not addressed SLV transmitted not ACK mode no recognition of own SLA or has been received general call address Notes 1 SLA Slave address
406. te Users must exercise caution when commanding the eNVM to program or erase data Other masters in the system may not be aware that the eNVM is unavailable Therefore users should use some form of software semaphore to control access By default non Cortex M3 ports are disabled on power up Users must enable each port by setting the appropriate bits in the AHB_MATRIX_CR register refer to Table 2 12 on page 31 The Cortex M3 is the only master in the system that can enable other masters since the control registers that enable masters reside on the Private Peripheral Bus of the Cortex M3 Access errors in the AHB bus matrix set the appropriate bit in the COM_ERRORSTATUS field of the MSS_SR register The ABM_ERROR_IRQ signal is also asserted and an error be trapped if IRQ24 is enabled in the NVIC IRQ24 corresponds to bit location 24 in the 32 bit word at address location 0 000 100 The following types of errors can occur 1 Write by an enabled master to a slave that is not RAW 2 Write by a disabled master to any location 3 A read by an enabled master to any slave that is not R or RAV 4 Aread by a disabled master to any location Reads to a non enabled slave or unimplemented address space return undefined values Write errors do not propagate beyond the AHB bus matrix that is the ABM consumes the write error The user has the option of restricting access to eNVM from a fabric master by programming the appropriate registers i
407. ted if any of the following conditions is true e PORESET asserted by the power supply monitor PSM MSS RESET REQ asserted by Cortex M3 F2M RESET asserted from FPGA fabric if F2MRESETENABLE asserted in SOFT RST CR WDOG TIMEOUT asserted by watchdog LOCKUP asserted by Cortex M3 MSS RESET N asserted during allowed window controlled by reset controller state machine M2F RESET N This reset signal is fed to the FPGA fabric M2F RESET N asserts asynchronously and negates synchronously to FCLK This guarantees that it is synchronous to rising edges of ACLK PCLKO and PCLK1 M2F RESET N is asserted if any of the following conditions is true PORESET N asserted by analog block MSS RESET REQ asserted by Cortex M3 WDOG TIMEOUT asserted by watchdog LOCKUP asserted by Cortex M3 MSS RESET N asserted during allowed window controlled by reset controller state machine Note 2 RESET asserted by F2M RESET Care must be taken by the user NOT to connect M2F RESET to the reset input of the fabric master which the user s design asserts F2M RESET to reset the MSS 144 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 9 1 Reset Controller Outputs continued RCOSC RESET N Asserts asynchronously and negates synchronously to RCOSCCLK This signal is used to reset parts of the Watchdog block which are clocked by the RC oscillator RCOSC RESET N is
408. ter Bit Definitions was removed The address for MSS CR was changed from 0 0040054 to 0 0042054 The Functional Description section was revised to change the reference to the MMS STATUS REG to its correct name MSS SR Table 9 2 Reset Controller Memory Map was revised to change the register address for SOFT CR from 0X0002030 to 0 0042030 1 5 V Voltage Detector VCC15UP section and 3 3 V Voltage 151 152 Bon VCC33UP section were revised Captions in Figure 10 1 VR and PSM Block Diagram and Figure 10 3 VR 151 153 Block Diagram were revised to correct them from VCC3A and VDD33 to The SmartFusion Power Modes section was replaced FPGA mode was deleted Table 10 2 SmartFusion Power Modes Table 10 3 SmartFusion through Wake up Transition Events and Table 10 4 e SmartFusion Power Down Transition Events were replaced by Figure 10 5 Power State Diagram Table 10 1 VR and PSM Related Interrupts was revised to change the 155 addresses for CLR MSS SR and DEVICE SR Table 10 2 VR and PSM Control Registers was revised to remove 157 MSS RCOSC CR The MSS RCOSC CR Bit Definitions table was removed The The description for MSSVRON in Table 10 6 VRPSM_CR was revised for MSSVRON in Table 10 6 VRPSM CR was revised 162 oso ___ AND gate above the WDOGRIS register was deleted in Figure 11 1 e Watchdog Block Diagram The definit
409. ter through clock synchronization circuitry if and only if the least significant byte of that set of register is addressed Higher order bytes of the same set of registers captured with the LSB can then be read on immediately later read cycles Higher order bytes of that set of registers can be read in any order but must be read before switching to a different set of registers to ensure data consistency For example when using the RTC counter address ranges from 0x40014100 to 0x40014110 register 0x40014100 must be accessed first before accessing addresses 0x40014104 0x40014108 0x4001410C and 0x40014110 to get the full 40 bit value Revision 1 297 _________________ Real Time Counter RTC System Control Status Register CTRL STAT REG The Control Status register CTRL STAT REG is an 8 bit register that defines the operation of the RTC The Control register can reset the RTC enabling operation to begin with all zeroes in the counter The RTC can be configured to clear when it is matched with the Match register or it can continue to count while still setting the match signal To enable the SmartFusion device to power up at a specific time or at periodic intervals the RTC can be configured to turn on the 1 5 V voltage regulator Table 16 2 CTRL STAT REG Bit Reset Number R W Value Description 7 RTC RST RAV RTC Reset 1 Writing a logic 1 to this bit causes an RTC reset 0 Writing a logic O to this bit will allow
410. ternative is Step 3A Step 3A Write to MSS_CCC_MUX_CR to select the GLB path 1 Set BYPASSB to 0x0 do not bypass MUX and divider 2 Set OBMUX to 0x03 select GLA output Write to MSS_CCC_DIV_CR to program the GLB path Set OBDIV to 0x03 divide by 4 divide GLA by 4 divide 100 MHz RC 4 Write to CLK_CONTROL_REG to program the GLA to GLB ratio Set GLBDIVISOR to 0x02 Table 8 7 e GLBDIVISOR Bit Definitions GLBDIVISOR LUE Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide RTCIF_ACMDIVISOR The allowed values of RTCIF ACMDIVISOR are shown in Table 8 8 Table 8 8 ACMDIVISOR Bit Definitions RTCIF ACMDIVISOR o3 menm Lo o 3mm o3 13 ACLKDIVISOR ACLK is derived from FCLK as shown in Table 8 9 Table 8 9 ACKLDIVISOR Bit Definitions MEC PCLKT1DIVISOR PCLK1 is derived from FCLK as shown in Table 8 10 Table 8 10 PCLK1DIVISOR Bit Definitions PCLK1DIVISOR O O EE NN E PCLKODIVISOR PCLKO is derived from FCLK as shown in Table 8 11 Table 8 11 PCLKODIVISOR Bit Definitions PCLKODIVISOR Revision 1 127 _____________________ PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators CCC Divider Configuration Register Table 8 12 MSS
411. the entire analog front end Specifically ABPOWERDOWN does the following When asserted it sends the 3 3 V supply to the ADC SCB and SDD e When asserted it generates the 2 56 V voltage reference for ADC and SDD When deasserted 3 3 V is not applied to ADC SCB and SDD to save power and the OPAMP which generates the 2 56 V reference is disabled Users also have the option of turning off all the ADCs at once by setting ADCSPWRDWN in ANA COMM CTRL or turning them off individually by setting the PWRDWN bit in the ADCx MISC CTRL where x equals 0 1 or 2 indicating which ADC to power down Sleep Mode In Sleep mode the 1 5 V supply is disabled and the 3 3 V supplies are enabled If the user wishes to transition to Time Keeping mode from Sleep mode a battery must be connected to otherwise connect VBAT to the 3 3 V rails In this mode the RTC and the 32 KHz oscillator that clocks the RTC are powered from the connected battery or power supply 3 3 V supply In Sleep mode the RTC and the 32 KHz oscillator are the only circuits running All other subsystems are Revision 1 155 ________________ Voltage Regulator VR Power Supply Monitor PSM and Power Modes powered off After reset firmware may transition to this mode from other modes by disabling the Voltage Regulator by pulsing MSSVRON from low to high to low or by having logic in the FPGA fabric pulse the FPGAVRON signal from a low to high to low Note
412. the fact that the eSRAM AHB controller inserts an idle cycle every time there is a write followed by a read enabling weighted round robin can increase the effective eSRAM bandwidth during this time from 66 to 94 of the theoretical maximum If a sequence of locked transfers is in progress then the locked master remains selected by the slave arbiter until the lock sequence is finished regardless of the number of transfers which could be more than eight Weighted round robin arbitration would also be useful in situations where more than one master is accessing eNVM as it allows each master to access multiple prefetched data words in the eNVM buffer instead of repeatedly filling the buffer with one word Refer to the Embedded Nonvolatile Memory eNVM Controller section on page 47 for details This arbitration mode has slightly longer potential latencies than pure round robin mode For example an urgent interrupt to the Cortex M3 could require servicing that involves accesses to a slave while the MAC is using that slave However by limiting the bursts to eight at the arbitration level regardless of AHB burst size the latency can be kept at a low value It is possible to switch between the two arbitration modes dynamically 18 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide System Memory Map The AHB bus matrix is responsible for implementing the address decoding of all masters to all slaves so it defines
413. the feedback signal with the input reference clock For example suppose there is no voltage applied to the VCO allowing it to operate at its free running frequency If an input reference clock suddenly appears a lock would be established within the maximum acquisition time 114 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Phase Selectors The output from the PLL core can be phase adjusted with respect to the reference input clock CLKA The user can select a 0 90 180 or 270 phase shift independently for each of the outputs GLA GLB YB and GLC YC Note that each of these phase adjusted signals might also undergo further frequency division and or time delay adjustment via the remaining dividers and delays located at the outputs of the CCC Selecting the desired phase for each output is accomplished by writing to the OAMUX OBMUX and OXMUX fields of the MSS CCC MUX CR control register Programmable Dividers The PLL block contains five programmable dividers Dividers n and m the input divider and feedback divider respectively provide integer frequency division factors from 1 to 128 Dividers n and m correspond to the fields FINDIV and FBDIV in the MSS CCC PLL CR control register The output dividers u v and w provide integer division factors from 1 to 32 Frequency scaling of the reference clock CLKA is performed according to the EQ 8 1 through EQ 8 3 forka x m n x u EQ 8 1 Tot
414. the frame has been transmitted The interrupt scheme is shown in Figure 12 8 CSR11 CSR5 CSR7 Mitigation Control Status Interrupt Enable MAC INT Figure 12 8 Interrupt Scheme General Purpose Timer Ethernet MAC includes a 16 bit general purpose timer to simplify time interval calculation by an external host The timer operates synchronously with the transmit clock CLKT generated by the PHY device This gives the host the possibility of measuring time intervals based on actual Ethernet bit time 192 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide The timer can operate in one shot mode or continuous mode In one shot mode the timer stops after reaching a zero value in continuous mode it is automatically reloaded and continues counting down after reaching a zero value The actual count value be tested with an accuracy of 1 bit by reading CSR11 15 0 When writing CSR11 15 0 the data is stored in the internal reload register The timer is immediately reloaded and starts to count down Frame Format Ethernet MAC supports the Ethernet frame format shown in Table 12 15 B indicates bytes The standard Ethernet frames DIX Ethernet as well as IEEE 802 3 frames are accepted Table 12 15 Frame Field Usage PREAMBLE 7 Generated Ethernet Stripped from received data Not MAC required for proper operation SFD Generated by Ethernet Stripped from received data MAC DA Supplied
415. the system memory map Figure 2 4 on page 20 depicts the default system memory map for the A2F200 device Unimplemented Address Space The AHB bus matrix performs address decoding based on the memory map defined in Figure 2 4 on page 20 and Figure 2 6 on page 22 to decide which slave if any is being addressed Any access to memory space outside of these regions is considered unimplemented from the point of view of the AHB bus matrix and results in the assertion of a COM_ERRORSTATUS register bit and the interrupt COM_ERRORINTERRUPT to the Cortex M3 as well as the assertion of HRESP by the AHB bus matrix to the master which could be in the FPGA fabric If any master attempts a write access to unimplemented address space the AHB bus matrix completes the handshake to the master with an HRESP error indication No write occurs to any slave If any master attempts a read access from unimplemented address space the AHB bus matrix completes the handshake to the master with an HRESP error indication Undefined data is returned in this case Within individual slave memory regions there may be further memory areas that are unimplemented Depending on the slave accesses may be aliased within these areas or not Firmware should not perform writes to these locations because the aliasing may cause a write to another location within the slave Data read from these intra slave unimplemented regions may be undefined In the case of the external memory con
416. thin the AHB bus matrix The Cortex M3 internally arbitrates between these two buses to determine which one obtains ownership of the code bus at any given time CM3TPIU TRACESWO TDO SWV JTAGTDO JTAGNSW Figure 1 2 e SWJ DP Single Wire Viewer Cortex M3 SysTick Timer The SysTick Timer is used to generate a periodic interrupt to the Cortex M3 It is essentially a 24 bit down counter The Cortex M3 microcontroller has four internal registers related to the SysTick timer described briefly in Table 1 1 Table 1 1 SysTick Control Register Embedded in NVIC Module SysTick Control And Status OXEO00E010 RAV 0x0 Basic control of SysTick including enable clock source interrupt or poll SysTick Reload Value OxE000E014 RAW Unpredictable Value to load in Current Value register when 0 is reached SysTick Current Value OxEO00E018 R W Unpredictable The current value of the count down SysTick Calibration Value STCALIB Contains the number of ticks to generate a 10 ms interval The SYSTICK CR located the SYSREG address space at address 0xE0042038 is used in conjunction with the SysTick control registers embedded within the NVIC module to control the behavior of the SysTick timer Individual bits of the SYSTICK CR register are described in Table 1 3 The SysTick counter in Cortex M3 is clocked by the free running clock and it can count either the free running clock itself or the cyc
417. tialize its contents but only the first 192 bytes constitute the address filtering operation While writing the setup frame buffer in the host memory the buffer size must be twice the size of the setup frame buffer Table 12 12 Filtering Type Selection FT1 FTO Description 0 0 Perfect filtering mode Setup frame buffer is interpreted as a set of sixteen 48 bit physical addresses 0 1 Hash filtering mode Setup frame buffer contains a 512 bit hash table plus a single 48 bit physical address 1 0 Inverse filtering mode Setup frame buffer is interpreted as a set of sixteen 48 bit physical addresses 1 1 Hash only filtering mode Setup frame buffer is interpreted as a 512 bit hash table Table 12 13 Perfect Filtering Setup Frame Buffer Physical address 23 16 physical address 31 24 peu Revision 1 187 ________________________ _ Acte Ethernet MAC Table 12 14 Hash Table Setup Frame Buffer Format o 131 128 135 132 171 168 175 172 183 180 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 187 184 XXXXXXXXXXXXXXXX XXXXXXXXXXXXXXXX 191 188 XXXXXXXXXXXXXXXX XXXXXXXXXXXXX
418. ticular type of interrupt GPIO interrupts 0 to 31 are mapped to ARM Cortex M3 interrupts 32 to 63 The 32 GPIO interrupts are ORed into a single interrupt signal which is available to the FPGA fabric interface as MSSINT 1 Table 18 3 Input Interrupt Type Configuration dw 39 p dem Ls LS LL Reese S The output buffer can be tristated by setting the MSSIOBUFOE bit to a 0 Setting MSSIOBUFOE to a 1 enables the output driver in the MSSIOBUF Pull ups pull downs and Schmitt Trigger controls associated with the respective IOMUX and are described in the Fabric Interface and IOMUX section on page 341 MSS GPIO Logic Thresholds For the east bank and west bank of MSS GPIO pads the logic threshold of these MSS I Os programmable on a per bank basis The MSS IO BANK CR is located within the SYSREG block at address 0 0042078 This register controls the east and west bank I O thresholds according to Table 18 5 Table 18 4 MSS IO BANK CR Bit Reset Number R W Value Function 3 2 BTWEST RAV Logic threshold selection for MSS I O west bank See Table 18 5 BTEAST RAW Logic threshold selection for MSS east bank See Table 18 5 Table 18 5 MSS GPIO Logic Threshold BTWEST BTEAST Logic Threshold for Each Bank Set Individually o o o threshold LVTTL LVCMOS 3 3 V default state Deco uw e Mu c o o 1 1 1 1 threshol
419. tion is as follows 100 Mbps mode 81 92 us RMII 10 Mbps mode 819 2 us Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUXes Associated with Ethernet MAC IOMUXes 16 17 18 19 20 21 22 23 and 24 are used to multiplex Ethernet MAC and fabric interface signals to MSSIOBUFs These are RMII PHY interface signals except for MAC RMII CLK input which is a dedicated MSSIOBUF on SmartFusion Refer to the Fabric Interface and IOMUX section on page 341 for a description of the IOMUX IOMUXes for MAC TXD 1 0 MAC RXD 1 0 MAC TX EN MAC CRSDV MAC RX ER MAC MDIO MAC MDC To use the MAC TXD 1 0 MAC RXD 1 0 MAC TX EN MAC CRSDV MAC RX ER MAC MDIO and MAC MDC signals an IOMUX is used to route the signal to an MSSIOBUF This IOMUX is used to share the MSSIOBUF between the various MAC signals and fabric when MAC is not in use Figure 12 12 shows the IOMUX topology for MAC TXD 0 A similar topology exists for the remaining MAC signals In this case IOMUX 16 is configured to connect OUT A to MSSIOBUF IO O port When MAC is not in use the M2F 0 F2M 0 and F2M OE 0 can then be routed to use MSSIOBUF MAC IOMUX 16 MAC TXDJ O MSSIOBUF MAC TXDIO M2F 0 F2M 0 F2M_OE O FPGA Fabric Figure 12 12 MAC 1 0 Interaction with Fabric Revision 1 215 ___________________ Ethernet MAC Table 12 42 lists the association between I Os IOMUXes and
420. to communicate with AHB and APB slaves in the MSS as described below The AHB MATRIX CR FAB PROT BASE CR and FAB PROT SIZE CR system registers which are only accessible by the ARM Cortex M3 be used to limit access by a fabric based master to some or all of the slaves in the MSS See the AHB Bus Matrix section on page 15 for more details Fabric Master AHB Interface The fabric master AHB interface allows a user instantiated AHB compliant master in the fabric to communicate with slaves in the MSS as shown in Figure 19 7 The fabric master AHB interface passes all incoming AHB transactions to the MSS all transactions are passed with no error checking performed The fabric master AHB interface provides for a 32 bit address a 32 bit read and a 32 bit write data bus into the MSS An AHB master in the fabric can perform byte half word and word accesses to MSS AHB slaves Misaligned accesses are not supported and result in invalid data transfers when in pipeline mode In bypass mode there is no indication of an invalid transfer If accessing an MSS APB peripheral a fabric based AHB master should use only word aligned addresses because all locations in the APB peripherals are at word aligned offsets Non word aligned addresses are not supported and result in invalid data transfers AHBL Re Decoder and Multiplexer AHBL Slave 0 Figure 19 7 Fabric Master to MSS Slave Revision 1 349 Aoo Meter Fabric Interface
421. tor and power supply monitor VR PSM block A block diagram is shown in Figure 9 1 There are two external pads that interface to the reset controller MSS RESET N and TRSTB MSS RESET N can be used as an external reset and can also be used as a system level reset under control of the Cortex M3 TRSTB is used to reset the SWJ DP logic within the Cortex M3 and to reset the main JTAG TAP controller All other inputs to and outputs from the reset controller originate on chip Note that the SOFT RESETS signals sourced from Figure 9 1 place the respective peripheral in a low power state For example if the user asserts I2C 0 SR logic 1 in the SOFT RST CR register all flip flops in that block are automatically clock gated BROWNOUT3 3VINT BROWNOUT1_5VINT INTISR 1 INTISR 2 PORESET_N M3_PORESET_N PORESET_N MSS RESET N pee s MSS_RESET_REQ NTRST NTRST Cortex M3 2 RESET MS5 SYSTEM RESET N vc RESET Reset Controller MSS RESET N O 2 RESET SOFT RESETS RCOSCRESETN WDOG TIMEOUT Watchdog Timer MSS_SYSTEM_RESET_N Figure 9 1 Reset Controller Block Diagram Functional Description PORESET N is a hard cold reset signal Its assertion causes everything in the MSS except for the SWJ DP in the Cortex M3 to be reset All the other functional reset sources those other than NTRST are soft warm resets The signals BROWNOUT3_3VINT B
422. tput MUX WD 31 0 Page Buffer Block Buffer Figure 4 14 Program Erase Data Flow There are protection mechanisms to prevent the accidental copy of a page buffer to the wrong page in eNVM For example if the PAGE LOSS bit is set and the sector or page address is changed after the first write to the page buffer and a program command is then issued the operation will fail The PROT ERROR x bit is set in the ENVM STATUS REG register indicating a protection fail has occurred An interrupt signal if enabled will be asserted to the Cortex M3 NVIC 56 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide Reading Writing to the Aux Block section s When reading or writing to either the Aux block or Aux block spare pages section the individual 4 byte Auxiliary blocks are mapped contiguously in Cortex M3 space as shown in Figure 4 15 and Figure 4 16 Reading and writing to these sections has the same functionality as reading and writing to the main eNVM array A 32 bit write to 0x60084000 writes 32 bits to Sector 0 Page 0 Aux Block A 32 bit write to 0x60084004 writes 32 bits to Sector 0 Page 1 Aux Block 31 0 AHB Byte 3 Byte 2 AHB Byte 1 AHB Byte 0 User Byte 3 User Byte 2 User Byte 1 User Byte 0 Figure 4 15 Aux Block Memory Mapping A 32 bit write to 0x60088000 writes 32 bits to Sector 0 Aux Block A 32 bit write to 0x60088004 writes 32 bits to Sector 1 Aux Block 31 0
423. tputs to indicate that certain voltage sources are valid These sources include the band gap reference the 1 5 V supply from the VR and the 3 3 V supplies VCC33A and VCC33AP PORESET N is the hard power on reset to the SmartFusion device This signal is held low by VCC15UP until VCC15GOOD passes 1 3 V PORESET N is fed into the reset controller see the Reset Controller section on page 143 where it is distributed to various parts of a SmartFusion device The signals VCC15GOOD and VCC33GOOD be used as brownout signals When they fall below their respective thresholds 1 3 V and 2 5 V the signals BROWNOUT3_3VINT and BROWNOUT1_5VINT assert and can cause an interrupt to the Cortex M3 if they have been previously enabled These signals are also readable as status bits in the MSS SR The user can disable the PSM and VR to save power It is assumed that the user s firmware is executing out of internal or external SRAM in this mode When the PSM is disabled the eNVM is also disabled As can be seen in Figure 10 4 on page 154 the PSM EN must be set to a 0 to turn off the PSM The PSM EN can be set to 0 by doing all of the following Setting ENVM SR to a 1 in the SOFT RST CR register Revision 1 153 _________________ Voltage Regulator VR Power Supply Monitor PSM and Power Modes Turning the Analog block off by clearing the ABPOWERON bit in the ANA COMM CTRL register e Clearing the bit BGPSMENABLE in the VRPSM
424. troller some of these accesses may result in HRESP assertion by the memory controller This occurs when attempting to access a location corresponding to an external memory that is not present at that address Burst Support The AHB bus matrix handshakes correctly with masters performing AHB bursts to any slave However it does not pass the transactions through to the slaves as bursts Instead the AHB bus matrix converts the burst accesses into single cycle accesses of the type NONSEQ This simplifies the design of the slaves which can exist in the FPGA fabric since they do not need to support AHB bursts It also allows the system designer to avoid having long latencies incurred by bursts of indeterminate length such as those from the FPGA fabric The AHB bus matrix does not connect to the HBURST bus of any master or slave Locked Transactions The AHB bus matrix supports implementation of locked transactions for accesses by the Cortex M3 to the memory controllers eNVM AHB controller eSRAM AHB controller and external memory controller by monitoring the HMASTLOCK signal The only slave to which HMASTLOCK is actually passed is the fabric slave because a circuit within the FPGA fabric may need to perform further locking For a more detailed description of HMASTLOCK refer to the ARM AMBA bus specification at the ARM website Memory Map In the memory map shown in Figure 2 4 on page 20 the eNVM is mapped into the Cortex M3 system space
425. ts The TIMER1INT and TIMER2INT outputs from the timer both have the same value as this bit when the timer is set to 64 bit mode Writing to this bit has no effect Timer 64 Mode Register Table 17 17 TIM64 MODE Bit Reset Number R W Value Description 31 1 Reserved RAV 0 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation TIM64 MODE RAV 0 0 64 mode 0 Timer 64 disabled two separate 32 bit timers 1 Timer 64 enabled one 64 bit timer Changing the state of this bit has the effect of reinitializing the System Timer register map to its default power up state Revision 1 311 ____________________ System Timer SmartFusion MSS Timer Application Development The SmartFusion MSS System Timer peripherals provide two 32 bit decrementing counters which can be used to implement two 32 bit timers or one 64 bit timer This section provides a high level overview of the design flow in order to facilitate fast and straightforward MSS Timer application development The timers generate an interrupt that can be used by the MSS or the FPGA fabric to trigger a user defined action Using the MSS Timer peripherals primarily requires configuring the MSS peripherals in use and developing user firmware Using the MSS Timer does not require the FPGA fabric or the Libero Integrate
426. tup time for the address to be latched in the EMD by EMC_CLK or a control signal is less than 10 ns then the EMC address phase can be one FCLK cycle long For some asynchronous EMDs the timing required for each phase may be greater than one FCLK cycle EMC_CLK is driven by FCLK Therefore the EMC is not designed around FCLK cycles but rather around EMC phases that correspond to EMD phases and are at least one FCLK cycle long EMC phases are made greater than an FCLK cycle by programming the latency fields in the configuration registers EMC CS 0 CR and EMC CS 1 CR Back to Back AHB Accesses AHB accesses to EMD may be consecutive in which case the current access may cause the pending access to wait until it completes At the completion of the first access the second access can start The last phase of an EMC access is either the transfer of read data to HRDATA or the write of EMC DB to the EMD Since neither of these actions involves the signals required for an AHB address phase it is possible for the last EMC phase to overlap with the address phase of a new AHB transaction thus saving one EMC phase per AHB transaction In this case the EMC never transitions back to its O phase idle but continues to EMC phase 1 for the second transaction after completing the first transaction This also requires that the EMC recognize that a pending transaction is waiting and generate the EMC control signals during the last phase of the current transaction w
427. ubsystem User s Guide Case 2B No Falling Current Clock Edge If a current clock rising edge occurs before the seventh desired clock rising edge but a current clock falling edge does not occur before the fifteenth desired clock rising edge the sequence of switching between the two clock sources from current clock to desired clock is as shown in Figure 8 11 At the fifteenth desired clock rising edge GL will go Low until the seventeenth desired clock rising edge At the seventeenth desired clock rising edge GL will continuously deliver the desired clock signal Current Clock Desired Clock GLMUXSEL CLOCKOUT Figure 8 11 NGMUX Switching When Falling Edge on Current Clock During Switching Window Safe Clock Switching Methods On power up the clock for the MSS is sourced by the CLKC path Specifically the RC oscillator is selected the w divider divides the 100 MHz RC by 4 and the glitchless MUX is set to select the global MUX GLC with the programmable delays feeding the GLAO and GLA1 outputs set to their maximum So on power up GLC GLAO GLA1 25 MHz Actel provided system boot code in concert with the Libero IDE MSS Configurator provides for a safe switching methodology from power on reset to the desired output clock frequency and source The delay values DLYAO and DLYA1 are set to a factory calibration setting It is strongly recommended that the user does not modify these delay values After power up
428. ued COM ERROR STATUS Each bit on this bus indicates whether any accesses by the corresponding master on the AHB bus matrix resulted in HRESP assertion by the slave to the AHB bus matrix HRESP assertion by the AHB bus matrix to that master in the case of blocked fabric master or was decoded by the AHB bus matrix as being an unimplemented address space These register bits are sticky and are cleared by writing a 1 to the COM CLEARSTATUS bit in the CLR MSS SR register These signals are not used as interrupts to the Cortex M3 Instead they are ORed together in the AHB bus matrix to create a signal called COM ERRORINTERRUPT which is used as an interrupt to the Cortex M3 This signal corresponds to IRQ 24 in the Cortex M3 NVIC IRQ 24 corresponds to bit location 24 in the 32 bit word at address location 100 COM ERRORINTERRUPT is not brought into the system registers space as a status bit for the user s firmware to read Bit definitions are as follows Bit 8 Peripheral DMA master Bit 7 Ethernet MAC master Bit 6 Fabric master Bit 5 Cortex M3 system bus master Bit 4 Cortex M3 ICODE DCODE bus master BROWNOUT3_3VINT Indicates that the 3 3 V supply has dropped below 2 5 V This signal corresponds to IRQ 2 in the Cortex M3 NVIC IRQ 2 corresponds to bit location 2 in the 32 bit word at address location 100 0 Don t care 1 3 3 V has fallen below 2 5 V Indicates that the 1 5 V suppl
429. uffers 1 Big endian mode used for the data buffers 0 Little endian mode used for the data buffers Descriptor skip length Specifies the number of long words between two consecutive descriptors in a ring structure Bus arbitration scheme 1 Transmit and receive processes have equal priority to access the bus 0 Intelligent arbitration where the receive process has priority over the transmit process Software reset Setting this bit resets all internal flip flops The processor should write a 1 to this bit and then wait until a read returns a O indicating that the reset has completed This bit will remain set for several clock cycles Table 12 19 Transmit Automatic Polling Intervals emm E me anes fo Re Revision 1 199 ____________________ Ethernet MAC Transmit Poll Demand Register CSR1 Table 12 20 Transmit Poll Demand Register CSR1 Bits 31 24 TPD 31 24 Bits 23 16 TPD 23 16 Bits 15 8 TPD 15 8 Table 12 21 CSR1 31 0 TPD Writing this field with any value instructs Ethernet MAC to check for frames to be transmitted This operation is valid only when the transmit process is suspended If no descriptor is available the transmit process remains suspended When the descriptor is available the transmit process goes into the running state Receive Poll Demand Register CSR2 Table 12 22 Receive Poll Demand Register CSR2
430. updating the counter itself The TIM64LOADVAL register is an internal register to the System Timer used in 64 bit mode for concatenating the two 32 bit registers TIM64 LOADVAL U and TIM64 LOADVAL L The new 64 bit load value is loaded into the counter when the counter reaches zero Writing this register while the System Timer is set to 32 bit mode has no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value Timer 64 Control Register Table 17 14 TIM64 CTRL Bit Reset Number R W Value Description 31 3 Reserved 0 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0x0 an TIM64INTEN Timer 64 Interrupt Enable When the counter reaches zero an interrupt is signaled to the Cortex M3 Nested Vectored Interrupt Controller 0 Timer 64 interrupt disabled 1 Timer 64 interrupt enabled Timer 64 Enable 0 Timer 64 disabled 1 Timer 64 enabled Writing this register while the System Timer is set to 32 bit mode has no effect Reading this register while the System Timer is set to 32 bit mode returns the reset value TIM64MODE RAW 0 0 64 Mode 0 Timer 64 in Periodic mode If TIM64ENABLE 1 when the counter reaches zero the counter is reloaded from the value in the TIM64 LOADVAL U and TIM64 LOADVAL L registers and begins counting down
431. upts Each group has its own summary bit NIS and AIS respectively The NIS and AIS bits directly control the MAC INT output port of Ethernet MAC INTISR 5 to the Cortex M3 NVIC Every status bit in CSR5 that can source an interrupt can be individually masked by writing an appropriate value to CSR7 Interrupt Enable register Additionally an interrupt mitigation mechanism is provided for reducing CPU usage in servicing interrupts Interrupt mitigation is controlled via CSR11 There are separate interrupt mitigation control blocks for the transmit and receive interrupts Both of these blocks consist of a 4 bit frame counter and a 4 bit timer The operation of these blocks is similar for the receive and transmit processes After the end of a successful receive or transmission operation an appropriate counter is decremented and the timer starts to count down if it has not already started An interrupt is triggered when either the counter or the timer reaches a zero value This allows Ethernet MAC to generate a single interrupt for a few received transmitted frames or after a specified time since the last successful receive transmit operation Revision 1 191 ____________________ Ethernet MAC It is possible to omit transmit interrupt mitigation for one particular frame by setting the Interrupt on Completion IC bit in the last descriptor of the frame If the IC bit is set Ethernet MAC sets the transmit interrupt immediately after
432. used to enable disable generation of the WDOGWAKEUPINT interrupt with the default setting being disabled eNVM Being Programmed The Watchdog is disabled when the external JTAG interface is used to program the embedded NVM on the device When the programming cycle has finished the Watchdog behaves as if it has just come out of reset Revision 1 165 _____________________ Watchdog Timer Watchdog Interrupts There are two interrupt outputs from the Watchdog WDOGTIMEOUTINT and WDOGWAKUPINT WDOGTIMEOUTINT This is asserted if enabled when a counter timeout occurs and interrupt rather than reset generation has been selected This interrupt is connected to the Non Maskable Interrupt NMI input of the Cortex M3 processor and also drives the WDINT interrupt to the FPGA fabric WDOGWAKEUPINT This is asserted if enabled on crossing the WDOGMVRP level when the SLEEPING input is asserted This interrupt is mapped to interrupt request 0 IRQ 0 in the Cortex M3 interrupt controller The FPGA fabric also has visibility of the WDOGWAKEUPINT interrupt but not as a single independent signal See the Fabric Interface and IOMUX section on page 341 for information on how WDOGWAKEUPINT is combined with a number of other MSS interrupts Watchdog Register Interface Summary Table 11 1 summarizes the Watchdog register interface Detailed descriptions of the registers are given in the Watchdog Register Interface Details section
433. vailable bit Clearing this bit when the receive process is in a running or suspended state instructs Ethernet MAC to enter a stopped state after receiving the current frame Ethernet MAC does not go into the stopped state immediately after clearing the SR bit Ethernet MAC will finish all pending receive operations before going into the stopped state The status bits of the CSR5 register should be read to check the actual receive operation state Hash perfect receive filtering mode read only 0 Perfect filtering of the incoming frames is performed according to the physical addresses specified in a setup frame 1 Imperfect filtering over the frames with the multicast addresses 15 performed according to the hash table specified in a setup frame A physical address check is performed according to the CSR6 2 hash only HO bit When both the HO and HP bits are set an imperfect filtering is performed on all of the addresses The filtering type bits of the setup frame determine the state of this bit Revision 1 207 ____________________ Ethernet MAC Table 12 32 lists all possible combinations of the address filtering bits The actual values of the IF HO and HP bits are determined by the filtering type FT1 FTO bits in the setup frame as shown in Table 12 9 on page 185 The IF HO and HP bits are read only Table 12 32 Receive Address Filtering Modes Summary PM E PR m IF E HO ES HP CSR6 0 Curren
434. value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PAGE ADDRESS RAW This field contains the page address for the operation defined in the COMMAND field eNVM Interrupt Enable Register Table 4 14 ENVM ENABLE REG 31 ILLEGAL CMD 1 0 Interrupt disabled when an illegal command has been issued att OP DONE 1 ECC2 ERROR 1 ECC1 ERROR 1 1 Interrupt enabled for ENVM 1 over threshold OVER THRESH 1 RAV errors ERASE ERROR 1 Interrupt disabled 1 Interrupt enabled for ENVM_1 erasing errors PROG ERROR 1 0 Interrupt disabled 1 Interrupt enabled for ENVM_1 programming errors PROT ERROR 1 0 Interrupt disabled 1 Interrupt enabled for ENVM 1 protection errors Revision 1 1 Enable interrupts when an illegal command has been issued Read 0 Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation 0 Interrupt disabled 1 Enable interrupts when _1 completes an operation Interrupt disabled 1 Interrupt enabled for 1 ECC2 errors Interrupt disabled 1 Interrupt enabled for ENVM_1 ECC1 errors 0 Interrupt disabled m VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 4 14 ENVM ENABLE REG
435. ve Mode Driver Source Code 20 X SDAI I2C X SDAO I2C X SDA Vec Vec Cortex M3 I2C X SCLI I2C X SCLO I2C X SCL Rp Rp Rp es I2C X SMBALERTI 2 X SMBALERTO 2 X SMBALERT SMBus Device MSS GPIO PMB Control PMBus Device MSS Figure 14 2 I2C Application Example Revision 1 251 POCA Ct e Inter Integrated Circuit Peripherals System Dependencies Clocks The 2 0 and 2 1 peripherals are clocked by PCLKO APB Bus 0 and PCLK1 and APB Bus 1 respectively PLCLKO and PLCK1 are free running versions of the main clock driving the entire MSS which are derived from the MSS CCC Refer to the PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators section on page 109 for details Baud Rate Clock BCLK The baud rate clock BCLK is a pulse for transmission speed control signal and is internally synchronized with the clock input BCLK may be used to set the serial clock frequency from a clock sourced within the FPGA fabric when the CR 2 0 bits in the CTRL register are set to 06111 Otherwise PCLKO or PCLK1 is used to determine the serial clock frequency The actual non stretched serial bus clock frequency can be calculated based on the setting in the CR 2 0 fields of the CTRL register and the frequencies of PCLKO or PCLK1 and BCLK Refer to the CTRL Register section on page 256 f
436. we 008 E x ewe 8 _ p om ms ewe _ po ox fme owe f we x ws ewe 39 130 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide OBDIV Table 8 16 gives bit definitions for OBDIV Table 8 16 OBDIV Bit Definitions OADIVHALF This bit if set to 1 divides the output frequency of the output divider defined by OADIV by 0 5 when the PLL is bypassed with the 100 MHz RC or 32 KHz low power oscillator If OADIVHALF 1 and OADIV 2 OADIV Divisor is 3 so 3 2 1 5 If the PLL is bypassed with the 100 MHz RC the output of GLA will be 100 1 5 66 67 MHz This bit is only valid if the is bypassed and the internal 100 MHz RC oscillator is used Table 8 17 lists the only supported values for OADIVHALF and OADIV Other combinations of OADIVHALF and OADIV can lead to unpredictable results Table 8 17 OADIVHALF Bit Definitions po 3 E owe E po po p owe os Eom pos 9m E pomo E pom po E pow owe Revision 1 131 D LLL Meter PLLs Clock Conditioning Circuitry and On Chip Crystal Oscillators OADIV Table 8 18 gives bit definitions for OADIV Table 8 18 OADIV Bit Definitions 132 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide CCC Multiplexer Configuration Register Table 8 19
437. with future products the value of a reserved bit should be preserved across a read modify write operation 3 Revision 1 357 ___________________ ______ _ MAefel Fabric Interface and IOMUX MSSIRQ EN 7 Table 19 15 MSSIRQ EN 7 31 3 Reserved RAV Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation amp s LE NM 1 Enable 0 Mask 1 Enable 0 Mask 1 Enable 0 Mask ADC2_NOTEMPTY ADC1 NOTEMPTY ___ NOTEMPTY 358 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide MSSIRQ SRC 0 Table 19 16 MSSIRQ SRC 0 31 25 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation Interrupt asserted and enabled Interrupt asserted and enabled Interrupt asserted and enabled 1 1 1 1 1 1 a B p wm m wm m mersus m 16 ___ 2 0 SMBSUS ns p messem 0 Interrupt asserted and enabled dq mes m ox 1 Interrupt asserted and enabled RTCMATCHEVENT 1 psewsoen B _wooswareur o FIIC MSSIRQ_SRC_1 Table 19 17 MSSIRQ SRC 1 MSS GPIO 1 I
438. with future products the value of a reserved bit should be preserved across a read modify write operation Loop enable bit In Loop mode SOUT is set to 1 and the SIN DSRn CTSn RIn and DCDn inputs are disconnected The output of the Transmitter Shift Register is looped back into the Receiver Shift Register The modem control outputs DTRn RTSn OUT1n and OUT2n are connected internally to the modem control inputs and the modem control output pins are set at 1 In loopback mode the transmitted data is immediately received allowing the CPU to check the operation of the UART The interrupts are operating in loop mode 0 Disabled default 1 Enabled Controls the Output2 OUT2n signal Active low 0 OUT2n is 1 default 1 OUT2n is 0 Controls the Output1 OUT1n signal Active low 0 1 is 1 default 1 OUT1n is 0 Controls the Request to Send RTSn signal Active low 0 RTSn is 1 default 1 RTSn is 0 Data Terminal Ready DTRn signal Active low 0 DTRn is 1 default 1 DTRn is 0 Revision 1 281 __________________________ _ Acte Universal Asynchronous Receiver Transmitter UART Peripherals Line Status Register LSR Table 15 13 LSR Bit Reset Number Name R W Value Description 7 FIER R 0 This bit is set when there is at least one parity error framing error or break indication in the FIFO FIER is cleared when the Cortex M3 processor reads the LSR if there a
439. with the configured I Os Table 18 55 GPIO Block Multiplexing Multiplexed with SPIO GPIO 24 25 Multiplexed with SPI1 GPIO 26 29 Multiplexed with UART1 GPIO 30 31 Multiplexed with 12 1 Developing User Application Code with GPIO Drivers User application code can be developed and debugged using any of the three supported embedded software development tools Actel SoftConsole Keil Microcontroller Development Kit pVisionG and IAR Embedded Workbench Actel provides set of GPIO Drivers that can be generated from the MSS configurator or from the Actel Firmware Catalog These drivers are common for all three tool flows However the Cortex Microcontroller Software Interface Standard CMSIS access layer is dependent on the tool flow selected and should be chosen based on the specific tool flow user is implementing The Actel MSS GPIO drivers allow quick application code development using the SmartFusion MSS GPIO without having to manually read and write the MSS System Registers Actel MSS GPIO Drivers are efficient and flexible For specific details on drivers refer to the Actel SmartFusion MSS Configurators and Drivers User s Guides Steps for Application Development Using Actel MSS GPIO Drivers As a first step tool specific CMSIS files need to be imported into the project along with GPIO drivers The mss_gpio h header file which defines GPIO function prototypes must be included in the application
440. withdrawn so it cannot be used for timing purposes In this SPI controller implementation the following rules are used After the last active edge of SPI x CLK the SPI x OEN signal is held active for at least one internal slave SPI x CLK cycle which is derived from the input PCLK using the clock division frequency register GEN SPI x OEN is held active if the slave select line SPI x SS is Low there is a transmission in progress or there is more data to be transmitted Revision 1 227 D LLL Meter Serial Peripheral Interface SPI Controller Motorola SPI Error Case Scenarios The SPI protocol does not specify any error recovery strategy The master and slave require prior knowledge of clock rates and data frame layouts However there are built in mechanisms in the SPI controller by which when the Slave encounters an error the Master can toggle the Slave clock until it gets to a known state Here are three specific error scenarios and the behavior of the SPI controller in Motorola protocol mode e If the slave select signal is withdrawn the middle of a transfer the transfer continues until the end of the data frame If the input clock is withdrawn the SPI controller will remain paused until the clock is restarted It will pick up where it left off e If the slave select signal is withdrawn before a transfer occurs the slave remains in the IDLE state no data transfer having been initiated Th
441. wo or more errors detected during copy page operation PROGRAM PAGE Programmed eNVM page does not match the page buffer PROGRAM PAGE PROTECTED 1 Programmed eNVM page does not match the page buffer ERASE PAGE Programmed eNVM page does not match the page buffer ERASE PAGE PROTECTED 1 Programmed eNVM page does not match the page buffer OVERWRITE PAGE Programmed eNVM page does not match the page buffer ARRAY WRITE 1 1 Attempt to write another page before programming current page when PAGE LOSS 1 UNPROTECT_PAGE Attempt to copy unprotected page into page buffer that contains a modified page and PAGE_LOSS 1 PROGRAM_PAGE 1 Page write count has exceeded the 10 year retention threshold PROGRAM_PAGE_PROTECTED Page write count has exceeded the 10 year retention threshold ERASE_PAGE 1 Page write count has exceeded the 10 year retention threshold ERASE PAGE PROTECTED Page write count has exceeded the 10 year retention threshold OVERWRITE PAGE 1 Page write count has exceeded the 10 year retention threshold PROGRAM PAGE ERASE PAGE Revision 1 65 Actel Embedded Nonvolatile Memory eNVM Controller 66 eNVM Control Register Table 4 13 CONTROL REG Bit name mw men ___ eR I 31 24 COMMAND RAV This field contains the command to be executed by the eNVM Commands are listed in Table 4 8 on page 61 23 20 Reserved Read as 0 Writes have no effect Software should not rely on the
442. write operation Normal interrupt summary enable When set normal interrupts are enabled Normal interrupts are listed below CSR5 0 Transmit interrupt CSR5 2 Transmit buffer unavailable CSR5 6 Receive interrupt CSR5 11 General purpose timer expired CSR5 14 Early receive interrupt Abnormal interrupt summary enable When set abnormal interrupts are enabled Abnormal interrupts are listed below CSR5 1 Transmit process stopped CSR5 5 Transmit underflow CSR5 7 Receive buffer unavailable CSR5 8 Receive process stopped CSR5 10 Early transmit interrupt Early receive interrupt enable When both the ERE and NIE bits are set early receive interrupt is enabled Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation General purpose timer overflow enable When both the GTE and NIE bits are set the general purpose timer overflow interrupt is enabled Early transmit interrupt enable When both the ETE and AIE bits are set the early transmit interrupt is enabled Revision 1 209 __________________________ _ Acte Ethernet MAC Table 12 35 CSR7 continued Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify w
443. wxss IOMUX 58 Table 13 25 IOMUX 58 DI LL o e s P omuwxsseru fJ d TL qo 7 _ qp educ 244 Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide IOMUX 59 Table 13 26 IOMUX 59 p ir pep pL ees Lm wwe IOMUX 70 Table 13 27 IOMUX 70 Pad IOMUX 70 Ports Name Ports IOMUX 70 CR m OUT A OEA INB OUT B OEB M2F 54 fr p pese xL qu 22 quur 1414 Eo IOMUX 71 Table 13 28 IOMUX 71 omnes WaT ora ws ours ors opoo a paasa e __ 5 Revision 1 245 ________________________ _ Acte Serial Peripheral Interface SPI Controller IOMUX 72 Table 13 29 IOMUX 72 Pad IOMUX 72 Ports Pad Name SPI 1 SS 3 IOMUX 72 PD IOMUX 72 ST IOMUX 73 Table 13 30 IOMUX 73 IOMUX 73 Ports Pad Name Ports IOMUX 73 CR II OUT A OEA INB OUT B OEB M2F 57 EH RENE NE i Prod p p ee E qud IOMUX 74 Table 13 31 IOMUX 74 WAT ora ws ours 1 s pw
444. x STATUS x 0 0x40004024 Channel 0 Status Register CHANNEL x BUFFER SRC ADDR CHANNEL x BUFFER A SRC ADDR 0 CHANNEL x BUFFER A SRC ADDR 0 0 0 40004028 ee Channel 0 Channel 0 buffer A source address source address CHANNEL x BUFFER A DST ADDR x 0 0x4000402C Channel 0 buffer A destination address CHANNEL x BUFFER A TRANSFER COUNT 0x40004030 Channel 0 buffer A transfer count x 0 CHANNEL x BUFFER SRC ADDR 0 0x40004034 Rw 0 Channel 0 buffer B source address CHANNEL x BUFFER B DST ADDR x 0 0x40004038 RAV Channel 0 buffer B destination address CHANNEL x BUFFER B TRANSFER COUNT 0x4000403C Channel 0 buffer B transfer count x 0 CHANNEL 1 CTRL 0x40004040 RW 0 Channel 1 Control Register CHANNEL 1 STATUS 0x40004044 R Channel 1 Status Register CHANNEL 1 BUFFER SRCADDR ____ 1 BUFFER 5 ADDR 0x40004048 RW 0 Channel 1 buffer A source address Channel 1 Channel 1 buffer A source address address EE 1 BUFFER A DST ADDR 0x4000404C ES Channel 1 buffer A destination address CHANNEL 1 BUFFER A TRANSFER COUNT 0x40004050 Rw 0 Channel 1 buffer A transfer count CHANNEL 1 BUFFER B SRC ADDR ____ 1 BUFFER B SRC ADDR 0x40004054 RW 0 Channel 1 buffer B source address Channel 1 Channel 1 buffer B source address B source address SS 1 BUFFER B DST ADDR 0x40004058 Channel 1 buffer B destination address
445. x40014140 Rw Individual Match bits 7 0 MATCHBITS1 REG 0x40014144 Rw Individual Match bits 15 8 MATCHBITS2 REG 0x40014148 Rw Individual Match bits 23 16 MATCHBITS3 REG 0x4001414C Fw Individual Match bits 31 24 4 REG REG 40014150 Rw __ 0 ___ Match bits 39 32 Individual Match bits 39 32 Match bits 39 32 LL o STAT REG EL Control write status read bits 7 0 382 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 21 2 SmartFusion Master Register Map continued System Timer Register Map addresses for TIM1 are shown TIM2 begins at 0x40005018 TIMx VAL x 1 0x40005000 PR Current value of Timer 1 LOADVAL ________ 1 0x40005004 Rw 0 0 jLoadvalueforTimer Load value LoadvalueforTimeri Timer 1 BGLOADVAL x 1 EI aa Background load value for Timer 1 TIMx CTRL x 1 0x4000500C Rwf 00 Timer 1 Control Register TIMx MIS x 1 0x40005014 Timer 1 masked interrupt status TIMx VAL x 2 0x40005018 R Current value of Timer 2 LOADVAL x 2 0x4000501C Load value for Timer 2 TIMx BGLOADVAL x 2 0x40005020 Background load value for Timer 2 TIMx CTRL 2 0x40005024 Ex Timer 2 Control Register TIMx MIS x o E Timer 2 masked interrupt status TIM64 VAL U 0x40005030 Upper 32 bit w
446. y write operation 15 0 BUF B COUNT RAW Number of transfers remaining to be completed between source and destination for buffer B for this channel This field is decremented after every DMA transfer cycle Writing a non zero value to this register causes the DMA to start This must be the last register to be written by firmware when setting up a DMA transfer 46 Revision 1 VActel POWER MATTERS 4 Embedded Nonvolatile Memory eNVM Controller The embedded nonvolatile memories eNVM controller in Actel SmartFusion devices consists of two components the eNVMs and the eNVM controller The eNVM controller converts logical AHB addresses to physical eNVM addresses and allows you to command the eNVM to perform specific tasks such as programming and erasing The block diagram in Figure 4 1 shows the configuration of the eNVM controller with two eNVM blocks Not all SmartFusion devices contain two memory blocks For the SmartFusion device with only one eNVM the controls signals for the nonexistent eNVM are ignored Note that x is used as a place holder in register names and field names within registers to indicate a particular eNVM for example STATUS x STATUS 0 or ENVM STATUS 1 AHB Bus Matrix HRESETn Figure 4 1 HRDATA 31 0 RD 1 31 0 BUSY 1 HADDR 20 0 ADDR 17 0 HWDATA 31 0 WD 31 0 HSEL HSIZE 1 0 CONTROL 1 HTRANS 1 HWRITE HREADY STATUS 1 1 0 AHB eNVM HRESP Controlle
447. y has dropped below 1 3 V This signal corresponds to IRQ 1 in the Cortex M3 NVIC IRQ 1 corresponds to bit location 1 in the 32 bit word at address location 100 0 Don t 1 1 5 V has fallen below 1 3 V BROWNOUT1_5VINT 158 Revision 1 VActel Actel SmartFusion Microcontroller Subsystem User s Guide Table 10 3 MSS SR continued 1 WDOGTIMEOUTEVENT This signal is sticky version of the WDOGTIMEOUTINT signal which is itself sticky but is cleared by MSS SYSTEM RESET N WDOGTIMEOUTEVENT is not affected by MSS SYSTEM RESET N This allows firmware to determine if system reset occurred due to a watchdog timeout event This signal is not used as an interrupt to the Cortex M3 This bit is reset to 0 by PORESET N only and is unaffected by MSS SYSTEM RESET N 0 Don t care 1 Watchdog has timed out RTCMATCHEVENT This signal is sticky version of the MATCH SYNC signal from the RTC If a rising edge event is seen on MATCH SYNC after synchronization to FCLK domain this bit is asserted It stays asserted until cleared by CLRRTCMATCHEVENT This signal is used as an interrupt to the Cortex M3 This signal corresponds to IRQ 3 in the Cortex M3 NVIC IRQ 3 corresponds to bit location 3 in the 32 bit word at address location 0 000 100 0 Don t care 1 RTC has matched event Revision 1 159 ________________________ _ Acte Voltage Regulator VR Power Supply
448. y of 535 ps then every time DLYA is incremented 200 ps is added to the previous delay value See Table 8 35 on page 141 DLYA1 Table 8 33 gives bit definitions for DLYA1 Table 8 33 DYLA1 Bit Definitions DLYA1 a Los o9 9 5 mew Los o9 3 meme o3 1 eemwe Revision 1 Actel Actel SmartFusion Microcontroller Subsystem User s Guide DLYAO Table 8 34 gives bit definitions for DYLAO Table 8 34 DYLAO Bit Definitions DLYAO DLYA Table 8 35 gives bit definitions for DLYA Table 8 35 DYLA Bit Definitions Co Bmw 9 9 9 3 o9 _ 3 CCC Status Register Table 8 36 MSS CCC SR Bit Mime Wome Reeve peserpton 31 1 Reserved Software should not rely on the value of a reserved bit To provide compatibility with future products the value of a reserved bit should be preserved across a read modify write operation PLL LOCK SYNC This bit indicates whether the SmartFusion PLL is in a locked condition This bit must be asserted before firmware switches the MSS clock source to the PLL 0 is not locked default 1 is locked Revision 1 141 Actel POWER MATTERS 9 Reset Controller The reset controller manages the SmartFusion on chip reset resources On power up the signal PORESET N is used to bring the SmartFusion device to a known power up state PORESET N is sourced by the voltage regula

Actel SmartFusion Microcontroller Subsystem User's Guide

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