Home

10G Ethernet MAC User Guide - Nine Ways Research & Development

1. AMBA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 5 Synthesis 5 1 Synopsis Synthesis The synthesis directory contains a synthesis script lt SynopsisLint prj gt example used to synthesize the design Synthesis scripts are provided for Synopsys Synplify Pro as a starting point The script needs to be updated to the proper library and other environmental options as necessary For synthesis it is important to have the directory source package verilog added to the include search path of the compiler as most of the files include the package files found in that directory during synthesis Note You must have the Synopsis Synplify IDE and tools installed on your PC This is not included with the deliverable DMA Controller package as this is far too large file size 5 2 Verilator Lint Synthesis The synthesis directory also contains a Linting script lt Lintcheck bat gt for Windows Use this to check that the generic syntax and verilog coding is good You can edit the Lintcheck bat file of you want to check other modules or you create different top modules for this project Important Note You must have Verilator copied into the root directory of your computer as Verilator with the following files 1 verilator verilator bin verilator compiled win You can obtain the Verilator package from Nine Ways Research amp Development Ltd See website www nineways c
2. 10 4 Core Usage AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 4 1 Core Configuration and Synthesis options 4 1 1 Global Synthesis Optio ns The following table lists the relevant synthesis options found in the so called global package file This file is included by all sources to set global definitions These are for size optimizations and to include exclude features that affect pin outs of modules If multiple different Cores are synthesized together all their common header verilog files need to be merged into a single file of that name containing all settings of all cores The package file is located at source package verilog common header verilog The following settings are available for change All others must not be changed Table 4 Global Package Definitions common header Setting Name Descripti on No Relevant Values N A 4 12 Core Configuration Package File The core is configured using the package file Ssource package verilog mtip dma pack package verilog The file is included by every relevant source file to configure several options during synthesis The following settings in this file can be changed All others must remain unchanged Table 5 Synthesis Package Definitions mtip dma pack package verilog the AXI address width only in this case It sets the number of bit of the AXI Maste
3. Next Previous Find all Search in E Match case 7 Match whole word Fam SmartFusion2 Die 25050 ES Pkg 896 FBGA Verilog Figure 3 Directory in the DMA project for SmartFusion2 start up where HDL files were copied ee ER gO lt lt Verilog MorethanIP DMA MAC 25 5 2 hdl 159 Organize Include in library Share with Burn New folder We Favorites E Name 5 Date modified Type E Desktop mgmii rs top V File jj Downloads Z mg V File 2 Recent Places Z mgmii tx rs File mi2byt re V File 559 Libraries mii2byt txe V File Documents module mdio shift V File Music mtip 1l0geth pack package VERILOG File h E Pictures 3 amp mtip_10geth_pack_package_32 VERILOG File Subversion mtip 10geth pack package 64 VERILOG File 3 E videos mtip bus ctl V File mtip ahbl ioregister V File 2 Homegroup mtip amba controller V File ti imast V File rv aria 5 Select a file to preview jS Computer V File amp Local Disk C V File Actelprj mtip aximaster fifo V File altera dffvec V File boost_1_45_0 mtip dma pack package VERILOG File de cygwin Z mtip dualrtx core V File Downloaded Installations mtip registerdef File Downloads mtip rxdma core File eclipse SDK 3 6 2 win32 mtip tx
4. 7 AXI Read FIFO Out Transmit pro MACTX XGMII MII Loop back DMA RX AXI Write FIFO In MDDR AXI Slave SDRAM Receive 4 RX p New arrived RX Ethernet Frames DMA State AHB Lite Machine Testbench Control Figure 1 Testbench Setup Overview The Testbench includes several configuration and scenario files to exercise the core 3 1 Running Simulation Using ModelSIM 3 1 1 Overview The AMBA DMA Controller core files and dependencies are available in the file comp amba gt simulation directory the Testbench file and simulation models files are listed in the files sim amba dma do To perform simulation the following steps should be followed 1 Change to the simulation directory 2 Compile the core database comp amba dma do 3 Compile the simulation database and run simulation sim amba dma do Note that the Testbench will produce many debugging information during simulation There are errors and warning messages during the simulation which are intended e g purposely generated errors When the Testbench stops the output must show Simulation Ends without Error at the end indicating a successful pass through all scenarios 3 1 2 Simulation Options The simulation is controlled by a set of define parameters These parameters are given to the compile
5. Move Van 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 List of Tables Table Recommended pools E ERR tte Re cR uere 6 Table 2 Design Kit Directories Description etre 7 Table 3 Testbench Files 8 Table 4 Global Package Definitions common 11 Table 5 Synthesis Package Definitions mtip dma pack package verilog 11 Table 6 Top Level Files 14 Table 7 Behavioral Models Summary nn eene nnne nre 16 Table 8 Memory Descriptions enne nennen nns 17 List of Figures Figure 1 Testbench Setup Overview 9 Figure 2 Libero from Microsemi with the Nine Ways start up project open 19 Figure 3 Directory in the DMA project for SmartFusion2 start up where HDL files were copied 19 JP AMBA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 1 Design Kit Introduction The DMA Controller package is agnostic and generic That is it can b
6. Source in the design work directory as shown in the script simulation comp amba dma do Behavioral models external register device MDDR AXI Slave AnySpeed MAC32 64 are provided in verilog source in the lt source testbench verilog gt directory The models can be re used in a custom project Testbench and provide a robust and flexible verification tool Table 7 Behavioral Models Summary Verilog Model Location Description tb model host v source testbench verilog Simulates another MorethanIP hardware core cascaded off the DMA Controller using the external register bus for the Register of that 3 party core tb ddraxi slave v source testbench verilog Behaves according to the standard AMBA ARM memory bus sub system MDDR that exposes an Slave interface that connects to the DMS Controller Master lt testmac64 gt directory containing verilog HDL source source testbench verilog testmac64 MorethanIP independent well established 32 64 MAC This allows for the frame on the TX of the DMA Controller to be looped back through a MAC core into the RX of the DMA Controller core This is the primary function of the Testbench simulation 16 More 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 4 4 Memory Implementation 4 4 1 Internal memory structures The AMBA DMA Controller has only one instance
7. have installed the files into the Libero system they are separate entities along with the other core verilog files in that target Microsemi directory They can then have their own parameter settings and define configuration as discussed previously in this document Figure 2 Libero from Microsemi with the Nine Ways start up project open Project File Edit View Design Tools SmartDesign Help 13H29 eo Design Hierarchy system A g4m_system COREAHBLITE_LIB f COREAXI_OBF_LIB EZgm system top 1 system EJ m __Design Hierarchy Stimulus Hierarchy Files Tool 4 Create Design amp System Builder 4 amp Configure MSS EJ Create SmartDesign B Create HDL 83 Create SmartDesign Testbench Create HDL TestBench 9 View Configure Firmware Cores 4 gt Verify Pre Synthesized Design Simulate 4 Create Constraints 4 VO Constraints _ constraint io gsm_system_top_designer_converted_io pde OY gt LR amp 9 E B Design Flow Catalog Log Bx 2 Messages Errors Warnings Info Reading file bfm ahbslave v Reading file bfm ahbslaveext v Reading file bfm main v Reading file testbench v Reading file axi master v Lg Reading file axi slave v 4 X Fnd
8. tb clocks source testbench verilog Clock generation block testmac64 directory source testbench verilog Instantiated MAC for loop back testing External Register Model Host This emulates another IP core cascaded onto the external register bus of the DMA Controller The external register bus allows for other IP cores to cascade off the primary DMA Controller and be mapped into the same AHB Lite addressing scheme from a processor sub system The Testbench performs a series of contiguous read write transactions to this model to check that the DMA HDL is operating well lt lt MDDR AXI Slave This model emulates an MDDR or FDDR AXI Slave interface that the DMA Controller will be expected to connect with The AXI Master in the DMA Controller in the Testbench is controlled to read and write Ethernet frames to from the AXI model The Testbench has three possible configurations 1 32 bit AMBA data width 64 bit AMBA data width Variable descriptor table sizes for RX and TX The four descriptor tables can have their sizes adjusted in the package verilog file along with the 32 bit and 64 bit modes above More 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 mtip dma pack package v Unit under Test UUT Controller MDDR AXI Slave SDRAM Pre loaded Ethernet Frames DMA TX
9. this package in a synthesis environment such as Libero is simply the IDE copying the source directory files into its own instance directory in the IDE At this point changes to the package verilog file in the newly copied and separate DMA instance directory in the synthesizer IDE will only affect that instance It will not affect this initial package directory content Furthermore if multiple instantiations of the same AMBA DMA Controller occur then the package verilog file in separate directories is the only duplication needed per instance which then leads to the IDE referring to the different lt package verilog gt header file AMBA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 2 Design Flow 21 Overview The different steps of the AMBA DMA Controller Design and hardware core s usage within the provided test environment are shown in the following paragraphs and include e Core generation RTL Simulation Synthesis and Implementation The full design kit provides scripts for ease of use and fast design verification and implementation turn around 2 2 Recommended Tools Table 1 Recommended Tools Design Flow Tool Version ModelSIM SE Simulation ModelSIM PE 6 x or Higher ModelSIM AE Synthesis FPGA Synopsis Synplify Pro ME G 2012 09MSP1 or higher Synthesis Synopsys Design Compiler 10 9 1 or Higher Controll
10. 1 mechanism Maximum allowed value is 256 Note Values in the higher range provide for better burst and high throughput performance but may not synthesize well in smaller device families TXCHO DESCSIZE parameter Sets the size of the High priority TX DMA Channel 0 descriptor table size in terms of entries This value if zero effectively disables the TX DMA mechanism Maximum allowed value is 256 Note Values in the higher range provide for better burst and high throughput performance but may not synthesize well in smaller device families TXCH1 DESCSIZE parameter Sets the size of the Low priority TX DMA Channel 1 descriptor table size in terms of entries This value if zero effectively disables the TX DMA CH1 mechanism Maximum allowed value is 256 Note Values in the higher range provide for better burst and high throughput performance but may not synthesize well in smaller device families Other Settings All other settings must be left unchanged N A 13 42 Top Level 421 Files Controller User s Guide Verilog Table 6 Top Level Files User s Guide Version 1 0 October 2013 File Location Description mtip amba dma controller v source top verilog The DMA Controller top level universal for all configurations and variations Note that all files rely on packages included from the dire
11. 22 instantiation Parameters 14 4 3 SIMULATION EE 16 4 4 MEMORY IMPLEMENTATION aane kae 17 4 4 1 intemal memory structures 17 5 18 5 1 SYNOPSIS SYNTHESIS 18 5 2 VERILATOR LINT SYNTHESIS 18 5 3 LIBERO SYNTHESIS FROM ACTEL MICROSEMI 18 6 CONTACT 20 DOCUMENT HISTORY 21 Han 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 Document Founder Mr Paul P Bates Nine Ways Research amp Development Ltd UK Written under the governance and agreement of Mr Daniel Koehler MorethanIP GmbH About This Release Document This document describes specifically coding relevancies package options and internal architecture from the HDL perspective Intended Audience This document is written for associates and employees of MorethanIP GmbH for customers clients using the hardware and integrating into project designs It is a full open release document that is available with the purchase and deliverable of the AMBA DMA Controller product
12. JP Haw AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 AMBA DMA Controller With 32 bit 64 bit AXI Support User s Guide Generic ASIC More Van 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 Contents 1 DESIGN KIT INTRODUCTION 5 2 DESIGNFLOW 6 2 1 OVERVIEW abya 6 2 2 RECOMMENDED TOOLS 6 2 DMA CONTROLLER CORE DATABASE u 7 3 SIMULATION ENVIRONMENT I U U uu u u 8 3 1 RUNNING SIMULATION USING MODELSIM sse enne nnnm nemen 9 SLT Ove UIT 9 371 2 Simulation Optionsschein anai 9 3 1 3 Package EM 10 4 USAGE c H 11 4 1 CORE CONFIGURATION AND SYNTHESIS 1 11 4 131 Global Synthesis Options 11 4 12 Core Configuration Package File l 11 4 2 TOP LEVEL 14 ADA 14 4
13. ctory source package verilog Hence this directory must be added to the include path of the simulator and synthesizer tools 4 2 2 Instantiation Parameters The top level does NOT have any options that can be configured during instantiation All parameters are controlled the package verilog file Instantiation would typically jus take the following form with no parameters but just wire definitions module mtip amba dma controller reset hclk helk reset aclk aclk reg rd reg_wr addr data in data out busy extint inputs extint acks hsel hwrite awlock 14 ff tx mod ff_tx_xstat tx crc fwd tx protocol checksum enable tx protocol checksumY ff tx rdy ch tx septy ff rx protocol checksum valid rx stat rx mod cpu int Controller User s Guide Verilog User s Guide Version 1 0 October 2013 EIP 4 3 Simulation AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 To simulate the AMBA DMA Controller when implemented in a custom project compile the HDL
14. dma core V File U Firefox 82 mtip vecdomain vldstrobe V File i MentorGraphics amp mtip_xsyne V File 0 MicroSemi pause pfcO rcv ctl V File Morethanip pause 16 012 12 13 V File je MSOCache m mes 103 ji 19 AMBA Controller User s Guide Verilog 6 Contact MorethanIP GmbH Nine Ways Research amp Development Ltd User s Guide Version 1 0 October 2013 E Mail info morethanip com Internet www morethanip com Europe Muenchner Str 199 D 85757 Karlsfeld Germany Tel 49 0 8131 333939 0 FAX 49 0 8131 333939 1 E Mail pbates nineways co uk Internet WWW nineways co uk UK Unit G 15 iDCentre Lathkill House rtc Business Park London Road Derby DE24 8UP United Kingdom Tel 44 0 1332 258847 FAX 44 0 1332 258823 20 Move Van 2 AMBA DMA Controller User s Guide Verilog 7 Document History Document Change Notices DCO Version Description User s Guide Version 1 0 October 2013 Created Changed Version 1 0 Initial release as according to Version 1 0 of the Verilog coding package Copyright MorethanIP GmbH 2013 All Rights Reserved Paul Bates Nine Ways R amp D UK Ltd 21 31 October 2013
15. e synthesized and instantiated into different design IDE programs for different device families even though it as a deliverable comes packaged in a defined and simple structure This structure is described and listed in detail in the following section of this document Despite the many different variations of configuration all changeable in the package verilog file there is only one set of source files and simulation scripts Usually an IP core package may include different duplicate files some for 32 bit and some 64 bit deviations Moreover there can often be a JAVA application to allow GUI configuration that then produces specific package source folders with hardcoded parameters and constants However this package does include such a configurator IDE This package for the AMBA DMA Controller is monolithic that being all configuration options for both synthesis and ModelSIM Testbench simulation are kept in the lt package verilog gt file included by all source HDL located in source package verilog This allows for a single ModelSIM script and also only a single source directory with generic source files capable of being synthesized in a whole variation of different configurations and sizes It will be described ater in this document how the simulation using ModelSIM is performed by setting the parameters of operation in the package verilog file then executing a simple script for ModelSIM Also it will show how the instantiation of
16. er User s Guide Verilog User s Guide Version 1 0 October 2013 2 DMA Controller Core Database After the design is generated the root directory of the DMA Controller package is called AMBA DMA Controller which contains a documentation directory containing these documents libero quartus simulation source synthesis which houses all of the IP core hardware source simulation and test bench facilities and finally the LinuxDriver directory Table 2 Design Kit Directories Description Directory Description libero Contains the lt MakeLibero gt file script that copies the agnostic generic driver in this package into a SmartFusion MicroSemi project HDL directory Note You will need to edit this file to select the target directory quartus Altera Quartus project example that synthesizes the core if available and may be empty as a directory simulation Scripts to configure and execute simulation source Design and Testbench Source Files The Testbench sub directory contains the DDR AXI Slave ARM model for verification of the ARM sub system memory controller synthesis Synopsys Synthesis Scripts An example implementation script is provided to show the list of files and their order If you have the Synopsis Synplify package installed on your computer executing the SynopsisLint bat file will perform a full scale synthesis check on the DMA package as stand alone Note You mus
17. o uk to contact us and obtain the file Note This is not included in the deliverable package of the AMBA DMA Controller as the file sizes are too big and bloats the content 5 3 Libero Synthesis from Actel Microsemi As a start point the directory within the package called lt ibero gt contains a Windows BATCH file script lt MakeLibero bat gt to directly install the source HDL content of the DMA Controller into a Microsemi project This then is ready for instantiation and use within an FPGA ASIC IDE environment This is very specific to the Microsemi environment and only acts as a start point Over time more scripts can be added that will help end users install the HDL source into specific IDE environments The IDE package for Microsemi is typically called Libero Pro or similar derivatives However this script is setup specifically for if you are using Nine Ways Research amp Developments start up project that provides a SmartFusion2 environment with the DMA Controller and MorethanIP s MAC as fabric cores This is available from Nine Ways as an SVN repository check out Subversion Contact details can be obtained from www nineways co uk If you wish to have your own Libero project then where ever this is located in your file system on your PC you will have to edit the file MakeLibero bat in the libero directory 18 Van AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 Once you
18. of an implementation of memory structures This is the back pressure FIFO in the RX DMA AXI write inner block This is used to allow the RX of the MAC FIFO to burst some transaction words whilst the AXI write bus is setting up Moreover if there are many scenarios whereby the AXI memory system experiences in a large complex system slowdowns and delays due to bus contention then the FIFO allows the MAC to continue transactions for a short while by filling the FIFO whilst the AXI bus waits It is widely seen that the MAC cores do take a finite number of clock cycles to respond to ff rx rdy being de asserted by the DMA Controller which gives rise for the need for the RX DMA FIFO Note The RX backpressure FIFO is ideally around 32 words in depth This is enough to handle 1 2 3 The MAC slow response fo ff rx The time between an SOP seen and the AXI bus activated for write transactions The start of a next Ethernet frame from a MAC whilst the previous AXI bus transaction completes Not to use too much hardware look up tables in the Fabric ASIC The files describing memories used in the design are Table 8 Memory Descriptions Directory File Description mtip aximaster fifo v Single Clock Dual Port Memory source aximaster verilog Used for the RX DMA backpressure FIFO in mtip aximaster wr v To change the depth use the parameter AXI RXDMA BACKPRESSURE SIZE in package verilog 17
19. r Setting Name Type Description Default Revision Configuration This can be any 16 bit integer value It is stated in hexadecimal in the package file and 11 parameter is used as a sub version number by a project 0001 SPECIFIC REVISION U integrator using this Controller package in their design MTIP CORE VERSION parameter DO NOT CHANGE Data Width amp AXI Master Configuration AMBA ADDR WIDTH parameter Global AMBA system data width This affects 32 11 Controller User s Guide Verilog User s Guide Version 1 0 October 2013 address bus and MUST match the width of the system memory bus of the host device system architecture Note Must be a power of 2 at least 32 MAC UUT 64BIT define This define states whether the DMA system data width is 64 bit or not By defining it declares the parameter AMBA DATA WIDTH to be 64 Else it allows parameter AMBA DATA WIDTH to be 32 This parameter governs the width of the FIFO data interface and the AXI Master data width for both RX and TX pathways The parameter AMBA DATA WIDTH is controlled by a define because of a ModelSIM Testbench requirement see later section on Testbench Note The width of the DMA system data width AXI and FIFO is restricted to 32 or 64 only Other attempted values will cause problems with operation Defined ID WIDTH parameter Sets the number of bit
20. r when compiling the Testbench See the script file sim amba dma do fora list of available options see define statements More Van 2 AMBA DMA Controller User s Guide Verilog User s Guide Version 1 0 October 2013 3 1 3 Package Options The simulation is also heavily influenced and controlled by the main package verilog header file for the main source HDL under test The testbench v also observes and uses these parameters and defines For instance if you comment out or uncomment the define MTIP MAC UUT 64BIT then it will change the simulation scenario between 32 bit and 64 bit data widths for the AMBA system FIFO and AXI Also you change the parameters for the TX and TX Descriptor sizes parameter RXCHO DESCSIZE 4 Customer choice Size of RX channel 0 Descriptors parameter RXCH1 DESCSIZE 4 Customer choice Size of RX channel 1 Descriptors parameter TXCHO DESCSIZE 4 Customer choice Size of TX channel 0 Descriptors parameter TXCH1 DESCSIZE 4 Customer choice Size of TX channel 1 Descriptors This will change the scenario for the Testbench as well The DMA controller is monolithic and so changes to the main package verilog do not change just the package HDL source under test but also the Testbench simulation This all adds to the simplicity of the whole operation Note The remaining parameters in the package verilog file can also be changed to help test the widest possible set of scenarios possible
21. s for the write AXI address ID write AXI data ID read AXI address ID and read AXI data ID rid This width is variable and you can use this to match the size of the AXI Slave that the DMA Controller Master connects to Note Usual values are 2 3 or 4 RXDMA BACKPRESSURE SIZE parameter Depth of the RX DMA backpressure FIFO This FIFO cushions the initial sop data to activate the RX mechanism and also allows for the MAC to react slowly to an RX DMA ready signal de assertion This if set too low less than 4 can cause problems with the RX if the ready signal is dropped to the MAC Note This can be set as high as 2048 but optimally is operates well at 16 or 32 32 RX amp TX Des criptor Table Configuration RXCHO DESCSIZE parameter Sets the size of the High priority RX DMA Channel 0 descriptor table size in terms of entries This value if zero effectively disables the RX DMA mechanism Maximum allowed value is 256 Note Values in the higher range provide for better burst and high throughput performance but may not synthesize well in smaller device families RXCH1 DESCSIZE parameter Sets the size of the Low priority RX DMA Channel 1 descriptor table size in terms of entries 12 Controller User s Guide Verilog User s Guide Version 1 0 October 2013 This value if zero effectively disables the RX DMA CH
22. t have Synopsis tools installed on your PC running Windows XP or higher Linting lt LintCheck bat gt file in this directory will perform a standard generic linting analysis using Verilator Note You must have Verilator installed on your PC running Windows XP or higher documentation For the customer package this directory is at the same level as the above and contains all of the PDF documents for this product LinuxDriver Contains the entire sub tree of all the C code build files make script and binaries of the device driver software JP AMBA Controller User s Guide Verilog 3 Simulation Environment User s Guide Version 1 0 October 2013 A system Testbench see Figure 1 Testbench Setup Overview is provided which implements the AMBA DMA Controller core with simulation control state machines MAC FIFO and DDR AXI model drivers monitors which generate and analyze traffic to and from the DMA Controller core Table 3 Testbench Files File Directory Description testbench v source testbench verilog Testbench using the DMA top level testbench functions v source testbench verilog TB lower level functions tb model host v source testbench verilog External reg memory block tb ddraxi slave source testbench verilog MDDR AXI Slave model ARM tb signals v source testbench verilog All reg wire and integer definitions

10G Ethernet MAC User Guide - Nine Ways Research & Development

Contents

Download Pdf Manuals

Related Search

Related Contents

10G Ethernet MAC User Guide - Nine Ways Research &amp; Development

Contents

Download Pdf Manuals

Related Search

Related Contents

10G Ethernet MAC User Guide - Nine Ways Research & Development