Reflective Memory Board User's Manual, GFK-2054
Contents
1. Example Code This appendix contains example code for use with the Reflective Memory Board GFK 2054 2 This code written to be down loaded into a Force CPU 33 on a VME bus Compiled using Cross code C compiler using the VMIC test code library This file should be loaded into the 1st VME chassis CPU setup as node 0 This routine will setup and process interrupts then report those interrupts received The second thing this software will do is to attempt to fill the output fifo over half full and then process and report that interrupt 0 occurred A include lt stdio h gt include lt test h gt include 5576int h Declare a global pointer to the 5576 board Vmic5576 uut Vmic5576 STANDARD STANDARD defined VMIC Library Declare external functions void isr intO void void isr intl void void isr int2 void void isr int3 void global variables for the interrupt routines X int intOstatus intlstatus int2status int3status main int intOstatus Oxff intlstatus 0 int2status 0 int3status 0 p printf r n n Receive Interrupts from remote VME chassis test y initialize intr vector table to point to timer ISR System dependent initialization where our system is a Force CPU 33 Single Board Computer Our method of installation is via se2. GE Fanuc Automation Programmable Control Products IC697VRM015 Reflective Memory Board User s Manual GFK 2054 514 000430 000 B May 2002 002 Warnings Cautions and Notes as Used in this Publication Warning Warning notices are used in this publication to emphasize that hazardous voltages currents temperatures or other conditions that could cause personal injury exist in this equipment or may be associated with its use In situations where inattention could cause either personal injury or damage to equipment a Warning notice is used Caution Caution notices are used where equipment might be damaged if care is not taken Note Notes merely call attention to information that is especially significant to understanding and operating the equipment This document is based on information available at the time of its publication While efforts have been made to be accurate the information contained herein does not purport to cover all details or variations in hardware or software nor to provide for every possible contingency in connection with installation operation or maintenance Features may be described herein which are not present in all hardware and software systems GE Fanuc Automation assumes no obligation of notice to holders of this document with respect to changes subsequently made GE Fanuc Automation makes no representation or warranty expressed implied or statutory with respe
3. 3 4 Resistet 3 5 Board Control and Status Register 3 6 Programming MC68153 BIM 3 7 The Command Register Definition 06H sese 3 9 Command Node 07H terne tet 3 10 Interrupt Sender ID Registers 26H 2 3 11 LocalbStatus Intetrupt ederet Et 3 12 Theory of OperatiOni 4 1 Operational Overview 2 epp de eere ce poema 4 2 B s Address Selecione er e e eee eec ide 4 3 Fiber Optic Link Speed Selection eene 4 4 Bus Interrupter Module 4 5 Addressing Features eo OO AO eee 4 6 Node Latency etae iie 4 7 5 1 Example COG 1 Troubleshooting Guide Lecce ee ecce eese B 1 iii Chapter Introduction Description and Specifications 1 This manual describes the installation and operation of the IC697VRMO15 Reflective Memory Board Features The Reflective Memory Board provides a high performance easy to use method of linking VMEbus systems using global memory You can link a minimum of two up to a maximum of 256 systems Any data word written to a specific location in
4. Relative Write Address Description Contents Read HEX Mode 01 Board ID ID 18 H Byte R 04 Node ID Node No Byte R 05 CSR Status Flags Byte R W 06 CMD Register Interrupt Address Byte W 07 CMD Node Node to get Interrupt Byte R W 23 INTO Mode Control MC68153 BIM Byte R W 26 Sender ID Node ID of INT1 Sender Byte 27 Mode Control MC68153 BIM Byte R W 2A INT2 Sender ID Node ID of INT2 Sender Byte R W 2B INT2 Mode Control MC68153 BIM Byte R W 2E INT3 Sender ID Node ID of INT3 Sender Byte R W 2F INT3 Mode Control MC68153 BIM Byte R W 33 INTO Vector MC68153 BIM Byte R W 37 INT1 Vector MC68153 BIM Byte R W 3B INT2 Vector MC68153 BIM Byte R W 3F INT3 Vector MC68153 BIM Byte R W 40 RAM SRAM All Modes Byte Word Lword R W 1 4 1 2 Chapter 3 Programming 07FFFF FFFFF 3 4 Board Identification ID Register The Board ID Register allows the user to verify the presence of the Reflective Memory Board at the correct address The Reflective Memory Board ID number is 18 HEX IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Node ID Register A value from 0 to 255 can be read from this byte The value read corresponds to the node ID jumper selected for the board GFK 2054 Chapter 3 Programming 3 5 Board Control and Status Register CSR The CSR contains local node state information The CSR is mapped as
5. X00000h X40000h X80000h XC0000h X00000h X40000h X80000h XCO0000h Node 0 is configured with 1 Mbyte of memory Nodes 1 and 2 are configured with 512 K of memory and Nodes 3 and 4 are configured with 256 K of memory Because of the relative location of the memory data written to address range X00000h to X7FFFFh by a processor in Node 0 will also be written into the corresponding address in Node 1 However no data will be written into Nodes 2 3 and 4 because there is no memory in that range in those nodes Similarly data written into address range X80000h to XBFFFFh in Node 2 will also be written into Nodes 0 and 3 but not Nodes 1 and 4 Chapter 4 Theory of Operation 4 7 Chapter Maintenance 5 This chapter provides information relative to the care and maintenance of the Reflective Memory Board product If the product malfunctions verify the following e Software e System configuration e Electrical connections e Jumper or configuration settings e Boards fully inserted into their proper connector location Connector pins are clean and free from contamination e Nocomponents of adjacent boards are disturbed when inserting or removing the board from the VMEbus card cage e Quality of cables and I O connections User level repairs are not recommended Contact your authorized GE Fanuc distributor for a Return Material Authorization RMA Number This RMA Number must be obtained prior to any return GFK 2054 5 1
6. amp TXFIFO_UHF 0 pragma interrupt void isr intl void intlstatus uut gt intlsid read id reg to clear the interrupt pragma interrupt void isr_int2 void int2status uut gt int2sid read id register to clear the interrupt pragma interrupt void isr_int3 void int3status uut int3sid read id register to clear the interrupt IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 This is the header file for the VMIVME 5576 Reflective Memory Board Interrupt test This file assumes the 2 boards are 200 option Both VMIVME 5576 boards are jumpered for Standard Either Mode access Ay struct vmivme 5576 union reg 5576 unsigned char 5576 b 64 unsigned short reg 5576 w 32 unsigned int reg 5576 1 16 r5576u unsigned char vmivme 5576 mem 1048512 register space typedef struct vmivme 5576 Vmic5576 5576 type define register definitions define bid r5576u reg 5576 0 01 Board ID define nid r5576u reg 5576 b 0x04 Node ID define csr r5576u reg 5576 b 0x05 Control amp Status Register define cmdreg r5576u reg 5576 b 0x06 Command register Idefine cmdnd r5576u reg 5576 b 0x07 Command node define intOmc r5576u reg 5576 b 0x23 interrupt 0 mode control register Idefine intOvr r5576u reg 5576 b 0x33 interrupt 0 vector reg
7. lt lt lt lt lt lt lt lt lt lt lt Extended Standard Address Address Field Field IC697VRMO15 Reflective Memory Board User s Manual May 2002 P1 P2 GFK 2054 Figure 2 3 Reflective Memory Board Standard Address Jumper Fields MEM DEPTH 1 e J1 MEM DEPTH 2 e 2 A4 fore A P1 A1 STD EXTD ADDRESS SEL JUMPER ee to ARRANGEMENT TO CONFIGURE EXTENDED ADDRESS XX9XXXXX HEX og e gt Address Mode Select J4 J7 i Anand 1 lt lt lt lt lt lt lt 335822 588588 lt lt lt lt 2 5 8 Extended Standard Address Address Field Field NOTE THAT FOR STANDARD ADDRESSES THIS JUMPER FIELD IS A DON T CARE P2 GFK 2054 Chapter 2 Configuration and Installation 2 7 2 8 Figure 2 4 Reflective Memory Board Extended Address with 256 Kbyte Example MEM DEPTH 1 MEM DEPTH 2 P1 STD EXTD ADDRESS SEL Address Mode Select JUMPER ARRANGEMENT TO CONFIGURE EXTENDED ADDRESS 5A9 4 HEX WITH J4 J7 a 1 4 MEGABYTE RAM OPTION 222222328 4444 lt lt 2 Extended Standard Address Address Field Field P2 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Board Node ID Field J9 The Board Node ID field identifies each board on the Memory link No ID may be used more than once on the link nodes on
8. 255 1 697 015 Reflective Memory Board User s Manual 2002 GFK 2054 Interrupt Sender ID Registers 26H 2AH 2EH The three interrupt sender ID registers contain the ID of the node which originated the interrupt currently being serviced data sent across the fiber optic link is tagged with the ID of the originating node so it may be removed from the link once it has been passed around the link one time The ID is stored in the appropriate register if the data word received is an interrupt As part of the interrupt handler software the user must read the appropriate ID register in order to re arm the currently used interrupt This process insures that all interrupts sent to the node will be processed The user may or may not use the ID but it must be read as part of the interrupt handler process In the event that a certain interrupt has been masked off at the BIM the FIFO for that interrupt may be cleared by writing to the ID register for the specific interrupt level before the BIM is armed The ID write process is to be done in addition to the BIM arming process In the interrupt handling sequence the user should do only one read per interrupt cycle Erroneous results will be caused by multiple reads GFK 2054 Chapter 3 Programming 3 11 Local Status Interrupt 3 12 The fourth interrupt on the MC68153 INTO is dedicated to generate an interrupt in the event that the local FIFOs become half full or a corrupt transfer
9. 29914 GFK 2054 1 4 There are four positions possible with the 256 Reflective Memory Boards relative to 1 Mbyte boundaries boards on the link must be mapped to the same position relative to the 1 Mbyte boundaries in order to communicate There is no restriction between which 1 Mbyte boundary each board is on Exact address matching is not required only the position relative to the nearest 1 Mbyte boundary must be the same IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Description and Specifications The following is a source for description and specification information The Epic E168C153 Bus Interrupter Module VME specification is available from Epic Semiconductor Inc 4801 S Lakeshore Dr Suite 203 Tempe AZ 85282 PH 480 730 1000 FAX 480 838 4740 Internet www epicsemi com PDF for the E168C153 www epicsemi com 153 pdf Note The Reflective Memory Board was originally manufactured using the Motorola MC68153 which is now out of production The Epic Ei68C153 BIM is being used as a replacement part on all newly manufactured Reflective Memory boards Any reference to the 68 153 in this document is also applicable to the MC68153 GFK 2054 Chapter 1 Introduction Description and Specifications 1 5 Safety Summary 1 6 The following general safety precautions must be observed during all phases of this operation service and repair of this product Failure to comply with these prec
10. There is a Control Register for each interrupt source see table 3 4 on page 3 12 i e CRO controls INTO controls INTI etc Each Control Register is divided into several fields e Interrupt level L2 L1 LO The least significant 3 bit field of the register determines the level at which an interrupt will be generated L2 L1 LO IRQ LEVEL 0 0 0 DISABLED 0 1 IRQI 0 1 0 IRQ2 0 1 1 IRQ3 1 0 1804 1 0 1 IRQS 1 1 0 1806 1 1 1 1807 A value of zero in the field disables the interrupt e Interrupt Enable IRE This field Bit 4 must be set high level to enable the bus interrupt request associated with the Control Register Thus if the INTX line is asserted and IRE is cleared no interrupt request IRQX will be asserted e Interrupt Auto Clear IRAC If IRAC Bit 3 is set IRE Bit 4 is cleared during interrupt acknowledge cycle responding to this request This action of clearing IRE disables the interrupt request To re enable the interrupt associated with this register IRE must be set again by writing to the Control Register GFK 2054 Chapter 3 Programming 3 7 3 8 e External Internal X IN Bit 5 of the Control Register determines the response the MC68153 during an interrupt acknowledge cycle If the X IN bit is clear low level the BIM will respond with vector data and a DTACK signal i e an internal response If X
11. a complete report sent to GE Fanuc together with a request for advice concerning the disposition of the damaged item s GFK 2054 2 1 2 2 Physical Installation Caution Do not install remove board while power is applied De energize the equipment and insert the board into an appropriate slot of the chassis While ensuring that the board is properly aligned and oriented in the supporting card guides slide the board smoothly forward against the mating connector until firmly seated IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Jumper Installation Figure 2 1 on page 2 4 shows the layout of jumpers on the Reflective Memory Board J 4 and J 7 are address jumpers These jumpers must be set to the desired base address of the board as described in Extended Address Field J4 Address Pass Through Field 77 and Standard Address Match Field J7 J3 75 18 and 19 must be set to configure other functions of the board as described in Board Node ID Field J9 Address Modifier Select J8 Fast Field J5 and Mask Field J3 on page 2 11 GFK 2054 Chapter 2 Configuration and Installation 2 3 2 4 IC697VRMO15 Reflective Memory Board User s Manual May 2002 Figure 2 1 Reflective Memory Board Jumper Fields MEM DEPTH 1 e e j MEM 2 e jo A4 e e 1 STD EXTD ADDRESS SEL 9 123 Address Mode
12. set to 0 for internal operation define ENABLE 0x10 define AUTO CLR 0x08 define IRQ LEVEL 7 0x07 define LEVEL 6 0x06 define LEVEL 5 0x05 define IRQ LEVEL 4 0x04 define IRQ LEVEL 3 0x03 tdefine IRQ LEVEL 2 0x02 define IRQ LEVEL 1 0 01 define DISABLE 0 00 define OFF 0x40 Board ID register value define ID_5576 0x18 Interrupt FIFO depth in bytes define INT_FIFO_DEPTH 512 Base address pointers Reg5578 regbase 5578 Reg5578 VME STANDARD reg off registers Memory membase 5578 Memory STANDARD mem off memory A 6 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Troubleshooting Guide This chapter contains troubleshooting information for Reflective Memory Board GFK 2054 B 1 Symptom Card Cards bus error when accessed after multiple writes Communications lost after power down and up of one or more Nodes on link Erratic communications on data link Node does not answer at expected address Possible Cause IACKIN IACKOUT daisy chain not in place on one or more nodes on network IACKIN must be in place on the backplane even if interrupts are not used on the node The local node ID is higher than the maximum node ID strapped on Node 0 System throughput has reached maximum and FIFO s have filled up with d
13. 153 is used on the board The attention interrupts INTI INT2 and INT3 are used to signal an interrupt from a remote chassis An interrupt INTO may be generated when the transmit FIFO on the node being written to by the VMEbus becomes over half full The transmit FIFO over half full condition occurs when the local node has received data from the local VME chassis but has not been granted permission to transmit its data on the link interrupts are masked off at power up and become enabled under program control GFK 2054 Chapter 4 Theory of Operation 4 5 4 6 Addressing Features Not all nodes have to be configured with the same memory size Nodes may be configured to make optimum use of memory An example is shown in Figure 4 1 on page 4 7 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Node Latency GFK 2054 If the fiber optic data bandwidth has not been exceeded data latency is typically 1 5 us node in single transfer mode Longer latencies will result if data input rates exceed 6 2 Mbytes sec for a period of time The transmit FIFOs will back up with data until the half full interrupts are set off or a bus error occurs in the event the FIFOs become full Figure 4 1 Example Memory Configurations NODE 0 X00000h X40000h X80000h XC0000h X00000h X40000h X80000h XC0000h XXX00000h XXX40000h XXX80000h XXXC0000h Contains Memory Does Not Contain Memory Base Address of Board
14. IN is set the vector is not supplied and no DTACK is given by the BIM i e an external device should respond Always set to zero for the Reflective Memory Board Bit 7 is a flag that can be changed without affecting chip operation e Flag Auto Clear FAC If FAC Bit 6 is set the Flag bit is automatically cleared during an interrupt acknowledge cycle Vector Registers 33H 37H 3BH Each interrupt input has its own associated Vector Register see Table 3 5 on page 3 13 Each register is eight bits wide and supplies a data byte during its interrupt acknowledge cycle if the associated External Internal X IN Control Register bit is clear zero This data can be status identification or address information depending on system usage The information is programmed by the system user Device Reset When the MC68153 is reset the registers are set to a known condition The Control Registers are set to all zeros low The Vector Registers are set to 0F This value is the MC68000 vector for an uninitialized interrupt vector IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 The Command Register Definition 06H The Reflective Memory Board may generate an interrupt in any or all other chassis through the use of the Command Register Valid choices for interrupts 1 2 3 Table 3 2 below shows all combinations possible The interrupts are processed just like data so all words se
15. SRAM takes slightly longer to DTACK when the FIFO is writing to RAM Software Requirements to Use Reflective Memory Board The Reflective Memory Board establishes the board to board link without any program setup upon power up The Bus Interrupter Module BIM which controls the interrupt generation on the Reflective Memory Board is initialized to mask all interrupts upon power up If interrupts are desired the appropriate registers in the BIM chip must be initialized through software control The board has a control and status register CSR that controls the Fail LED Because the board does not include automatic diagnostic software that performs a self test function the Fail LED being ON does not indicate a failure unless the VME chassis software control has turned it ON LED ON is the standard power up mode for the Fail LED To turn OFF the Fail LED the user software must Write to the CSR after any test software is run successfully If the output FIFO becomes over half full and the BIM has been programmed and enabled the board issues an interrupt The user software may choose to ignore this warning If the user software attempts to write to a board that has a completely full output FIFO the board issues a Bus Error BERR Hardware Requirements to Use Reflective Memory Board 1 2 Aside from the address map decoding required on the Reflective Memory Board there are a few system jumpering requirements which must be followed to allow the s
16. Select M L S S B J9 B J4 J7 ont oar 5 lt lt 0 lt Extended Standard Address Address Field Field P2 GFK 2054 Extended Address Field J4 If the extended address jumper J10 is installed the extended address match field becomes active The extended address field selects A31 through A24 An installed jumper is a logic low and no jumper is a logic one Refer to Figure 2 2 on page 2 6 and Figure 2 3 on page 2 7 Address Pass Through Field J7 J1 and J2 are configured at the factory and should not need configuration by the user The information in the rest of this paragraph is for reference only Refer to Figure 2 4 on page 2 8 Standard Address Match Field J7 The standard address match field is always active An installed jumper indicates a logic zero address The Active field is as follows 256 K A23 through A18 GFK 2054 Chapter 2 Configuration and Installation 2 5 2 6 JUMPER ARRANGEMENT TO CONFIGURE EXTENDED ADDRESS 5AXXXXXX HEX Figure 2 2 Reflective Memory Board Extended Address Jumper Fields DEPTH 1 e ui 2 e e jo Lee ag lee A2 STD EXTD ADDRESS SEL Address Mode Select M 18 94 J7 S S B J9 B DQ O oN r QW a
17. a Read of location 26 HEX which will allow the second interrupt to be issued to the BIM This method guarantees that all interrupts sent on the link will be serviced and the receiver knows the ID of the node which sent the interrupt it is currently servicing Only one Read per interrupt is allowed otherwise loss of subsequent interrupts may occur The three interrupt FIFOs are 512 bytes deep so up to 512 interrupts of any level may be queued in the FIFO A clear function is executed upon a Write to the int ID Register so an interrupt level that has been masked off for some time and contains many global or local interrupts previously sent may be cleared out without servicing them Only new interrupts received will be serviced Since the interrupts originally go through the same receive FIFO as data all data sent before the interrupt will be present in the local node s memory before the interrupt is issued to the local node GFK 2054 Chapter 3 Programming 3 9 Command Node 07H This register contains the node ID of the node to receive the interrupt sent by writing the command register This register must be set at the same time by using a 16 bit word write to both command register and command node or prior to writing the command register Table 3 3 below shows node ID patterns Table 3 3 Reflective Memory Board Node IDs D7 D6 D5 D4 D3 D2 D1 DO Nodeo o o 1 1 1 1 1 1 1 1 1 Node
18. ata to be sent and the transmit FIFO half full signal has been ignored P3 P4 cable swapped or lines are open between cable and local node No Node 0 present to pass token Receive FIFO s on one or more nodes have been glitched by an out of spec txclk on link Reset all nodes or issue link reset to nodes strapped to listen to the link reset signal Link rate too high for cable length i e Rate Max Length 1 20 MBYTE SEC 50 2 10 MBYTE SEC 100 3 5 MBYTE SEC 250 4 2 5 MBYTE SEC 1000 Open cable at or more pins on link Terminator resistors not installed on end nodes of link or extra terminators have been left on center nodes P3 P4 pins pushed back on Node connector Inspect pins for damage P3 P4 cable has crushed pin in Panduit connector Try swapping P3 cable to P4 and P4 cable to P3 on all nodes If symptoms of problem change at least one of the cables is bad Address pass through for specific memory size not strapped correctly See Chapter 2 Configuration and Installation Address modifier incorrectly strapped on card Address strapped wrong Certain LSB address jumpers must be left off because of memory size options B 2 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Symptom Data written to one node does not appear in other nodes Receive FIFO fills up and never empties out even after link traffic stops Data Bits dropped or data appears in wro
19. autions or with specific warnings elsewhere in this manual violates safety standards of design manufacture and intended use of this product GE Fanuc assumes no liability for the customer s failure to comply with these requirements Ground the System To minimize shock hazard the chassis and system cabinet must be connected to an electrical ground A three conductor AC power cable should be used The power cable must either be plugged into an approved three contact electrical outlet or used with a three contact to two contact adapter with the grounding wire green firmly connected to an electrical ground safety ground at the power outlet Do Not Operate in an Explosive Atmosphere Do not operate the system in the presence of flammable gases or fumes Operation of any electrical system in such an environment constitutes a definite safety hazard Keep Away from Live Circuits Operating personnel must not remove product covers Component replacement and internal adjustments must be made by qualified maintenance personnel Do not replace components with power cable connected Under certain conditions dangerous voltages may exist even with the power cable removed To avoid injuries always disconnect power and discharge circuits before touching them Do Not Service or Adjust Alone Do not attempt internal service or adjustment unless another person capable of rendering first aid and resuscitation is present Do Not Substitute Parts or M
20. ct Read Write This bit indicates that the local node has received data back that had originated on the local node It may be reset by writing this bit to a logic zero Once set by receiving its own node ID from the fiber optic receiver the bit remains set until cleared by the local VME side Mask Mask Transfer Error Interrupt Masks on high Read Only If the mask jumper J3 is installed and INTO is enabled by software on the bus interrupt module an interrupt will be generated each time a receive error is detected on the fiber optic link Fast Fast mode 6 2 Mbytes sec if high Read Only Fast mode transmits each data transfer once on the fiber optic link If the jumper J5 is installed each transfer is sent twice on the fiber optic link 3 2 Mbytes sec 3 6 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Programming the MC68153 BIM The MC68153 contains one Interrupt Control Register ICR and one Interrupt Vector Register for each of the four interrupt sources four Control Registers are identical All four Vector Registers are also identical Register Description The MC68153 contains eight programmable Read Write Registers There are four Control Registers CRINTO through CRINT3 that govern operation of the device The other four VRINTO through VRINT3 are Vector Registers that contain the vector data used during an interrupt acknowledge cycle Control Registers 23H 27H 2BH 2FH
21. ct to and assumes no responsibility for the accuracy completeness sufficiency or usefulness of the information contained herein No warranties of merchantability or fitness for purpose shall apply The following are trademarks of GE Fanuc Automation North America Inc Alarm Master Genius PROMACRO Series Six CIMPLICITY Helpmate PowerMotion Series Three CIMPLICITY 90 ADS Logicmaster PowerTRAC VersaMax CIMSTAR Modelmaster Series 90 VersaPro Field Control Motion Mate Series Five VuMaster GEnet ProLoop Series One Workmaster Copyright 2001 GE Fanuc Automation North America Inc Rights Reserved Chapter 1 Chapter 2 Chapter 3 Chapter 4 Chapter 5 Appendix A Appendix B GFK 2054 Contents Introduction Description and Specifications eere 1 1 the 1 1 Functional Description 1 2 Description and Specifications nennen 1 5 Safety Summary ETE EE 1 6 Configuration and Installation eee eee nest 2 1 Physical Installation Jes 2 2 Jumper Installations ei decet eec e ate iade 2 3 Fiber Optic Link Configuration 2 14 TACK Daisy Chains 2 15 3 1 Introduction to Controlling the Reflective Memory Board 3 2 Board Identification ID Register
22. eiver to close the link When data has been sent around the link and returns to the originating node two things happen One the data is removed from the link This is done by comparing an ID tag sent with data to the local node ID If a match is determined the data is removed The second event which occurs is that the OWN ID bit is set in the CSR Loop data latency can be measured by writing a zero to the OWN ID bit in the CSR and polling until it returns to a one state This test assumes there is no other data originated by the local node on the link before the latency test is initiated The data write to the CSR is passed around the link as regular traffic but will not affect the status of any other nodes CSR The CSR data write provides a means to measure latency without giving up any memory which may be in use in order to measure data transfer latency If data was not generated by the local node it is placed in the receive FIFO The receive FIFO then places data in RAM and into the transmit FIFO to be sent to the next node on the link Data can be mixed from the local VME and the link based on which arrives at what time Just because two data transfers arrive in one node back to back does not guarantee a transfer cannot be inserted between them by the local VME card Priority is given to the local VME card in case of a simultaneous access to the RAM and the transmit FIFO by the local VME and the receive FIFO In any other case the other mus
23. ength Damaged cable or connection on node with data error IACKIN is not daisy chained from the CPU to the reflective memory card on the backplane VME spec requires all empty VME slots to have IACKIN jumpered to IACKOUT Reflective memory cards expect IACKIN to be driven even if interrupts are not being used The IACKIN IACKOUT jumper has been placed on backplane for the slot the reflective memory is residing in This shorts the IACKOUT driver in the previous slot to the reflective memory IACKOUT driver 3
24. follows Bito7 Bitos Bitos Bit04 Bito3 Bito2 Bitoo LED RCV TX Half full Half full TX Empty Bad Data Own Data Mask Fast Board Control and Status Register Bit Definitions Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 LED Fail LED Status Read Write logic 1 LED ON logic 0 LED OFF RCV Half full Receive FIFO half full at least half full when low Read Only This bit displays current status of the receive FIFO This bit should never be low If this bit goes low local VME access should be suspended or at least curtailed for a period of time or data loss could occur This bit going low would be an indication of a local VME problem i e extremely slow release of data strobes after DTACK In a proper functioning VME system this should never occur TX Half full Transmit FIFO half full over half full when low Read Only These two bits display status on the transmit FIFO on the local node The current status of the transmit status is displayed TX Empty Transmit FIFO empty empty when low Read Only Bad Data Bad data high if error occurred Read Write This bit indicates that a single transfer error has occurred It does not depend on the mask jumper to be removed In redundant transmission mode 3 2 Mbytes sec it indicates only that a transfer error occurred on one of the two transfers Own Data Own data high if link inta
25. has been received If the interrupt is not disabled every time the local Reflective Memory Board is written to and the transmit FIFO is over half full or a transfer error occurs an INTO will be generated The half full information flag is also available by looking at the CSR If the transmit FIFO is allowed to become full and the FIFO half full is set a BERR will be generated when a Write is attempted to the Reflective Memory Board Table 3 4 below and Table 3 5 on page 3 13 show the architecture of MC68153 registers The corrupt transfer interrupt may be masked off by removing the mask jumper This is done so the user will not be bothered by interrupts in redundant transfer mode Table 3 4 BIM Register Mapping for Interrupts 0 to 3 XX23 Control Register INTO INTO Transmit FIFO Over Half full Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 FLAG INT INT FLAG AUTO VECTOR ENABLE AUTO INTERRUPT LEVEL CLEAR CLEAR 0 1 AUTO F FAC IRE L2 11 LO 1 EXTERNAL 0 XX27 Control Register Received Interrupt from Other Nodes Bit07 Bit 06 Bit 05 Bit04 BitO3 BitO2 Bitol FLAG INT INT FLAG AUTO VECTOR ENABLE AUTO INTERRUPT LEVEL CLEAR CLEAR OZINTERNAL 1 AUTO F FAC IRE L2 11 10 1 EXTERNAL 0 2 Control Register INT2 INT2 Received Interrupt from Other Nodes Bit 07 Bit 06 Bit 05 B
26. ister define intlsid r5576u reg 5576 b 0x26 interrupt 1 sender ID register define intlmc r5576u reg 5576 b 0x27 interrupt 1 mode control register define intlvr r5576u reg 5576 b 0x37 interrupt 1 vector register define int2sid r5576u reg 5576 b 0x2a interrupt 2 sender ID register define int2mc r5576u reg 5576 b 0x2b interrupt 2 mode control register define int2vr r5576u reg 5576 b 0x3b interrupt 2 vector register define int3sid r5576u reg 5576 b 0x2e interrupt 3 sender ID register define int3mc r5576u reg 5576 b 0x2f interrupt 3 mode control register define int3vr r5576u reg 5576 b 0x3f interrupt 3 vector register define mem5576 vmivme 5576 mem 0x0 memory Control Status Register bit define s define FAIL LED 0x80 define RXFIFO 0x40 receive fifo under half full define TXFIFO 0x20 Transmit fifo under half full define TXFIFO_NOT_EMPTY 0x10 define BAD DATA 0x08 define OWN_DATA 0x04 define ERR INT MASK 0x02 define FAST 0x01 command register bit def s GFK 2054 Appendix A Example Code A 5 define GLOBAL INT 0x40 define INT 1 0x01 define 2 0x02 define INT 3 0x03 bim control bits for regs intOmc int3mc define FLAG BIT 0x80 define FLAG AUTO CLR 0x40 define EXT VECTOR 0x20
27. it 04 Bit 03 Bit 02 Bit 01 Bit 00 FLAG INT INT FLAG AUTO VECTOR ENABLE AUTO INTERRUPT LEVEL CLEAR CLEAR 0 1 AUTO F FAC IRE L2 11 LO 1 EXTERNAL 0 XX2F Control Register INT3 Received Interrupt from Other Nodes Bit 07 Bit 06 Bit 05 Bit 04 Bit 03 Bit 02 Bit 01 Bit 00 FLAG INT INT FLAG AUTO VECTOR ENABLE AUTO INTERRUPT LEVEL CLEAR CLEAR OZINTERNAL 1 AUTO F FAC IRE L2 11 LO 1 EXTERNAL 0 1C697VRMO015 Reflective Memory Board User s Manual 2002 GFK 2054 2054 Table 3 5 Vector Register Mapping XX33 Vector Register INTO Vector Register V7 V6 V5 v4 v2 vo XX37 Vector Register INT1 Vector Register ve vs v v2 VI vo XX3B Vector Register INT2 Vector Register ve vs v v2 VI vo XX3F Vector Register INT3 Vector Register V7 V6 V5 v4 v2 VI vo Chapter 3 Programming Chapter Theory of Operation 4 This chapter discusses the operation of the Reflective Memory Board and is divided into the following sections Operational Overview Base Address Selection Fiber Optic Link Speed Selection Bus Interrupter Module BIM Addressing Features Node Latency GFK 2054 Operational Overview 4 2 The Reflective Memory Board allows up to 256 VMEbus chassis to be linked together in a sequential fashion Data written to any node appears in all
28. memory shows up in the same location in each of the other nodes with no programming or other intervention required The Reflective Memory Board has several unique features GFK 2054 No software necessary to establish communications On board interrupt generation ability Any node may generate interrupts on any or all other nodes on the system Facilitates communications over very long link lengths up to 2 000 meters Can be selected to operate in privileged or nonprivileged modes or in both modes at once Memory can be configured to run in either A24 or A32 addressing schemes Supports 8 16 24 32 bit transfers bi directional Attention interrupts are channeled to one of seven programmable interrupt levels Double Eurocard form factor Any board may be jumpered to be any Node 256K of SRAM on board 512 byte FIFO 1 1 Functional Description The link between two nodes is established through the use of FIFO memory which is routed through fiber optic drivers receivers Figure 1 1 on page 1 3 shows the block diagram of the Reflective Memory Board Note that the FIFO memory is on the same bus as the SRAM memory The user only sees the SRAM memory and is not aware of the FIFO memory that performs the actual bus transfer to the other boards The Reflective Memory Board appears to the user as standard SRAM memory and can be used as such The only effect noticeable to the user due to the presence of the communications bus is that
29. ng address in memory If data is wrong in a node and is correct in all other nodes When interrupts are being used a spurious interrupt is issued from the CPU Appendix Troubleshooting Guide Possible Cause For nodes of memory size 1 MBYTE or smaller 1 MBYTE relative address is nodes passed If two 0 25 MBYTE cards are not mapped in the same relative address in relation to the 1 MBYTE boundary then they will not appear to communicate since they contain no common space in RAM The 2 and 4 cards pass a 4 MBYTE relative address and thus must be mapped in the same address relative to 4 MBYTE boundaries Note that 4 and 2 MBYTE nodes may not be used on the same link as 1 MBYTE or smaller nodes due to the fact that they look at different relative address sizes The sending node ID is higher than the maximum node ID strapped on Node 0 Open or defective connection to cable P3 or P4 Defective FIFO module on either receiving node or transmitting node The bad card may be found by checking memory on other nodes to see if they received data correctly IACKIN has not been connected to the interrupt Arbiter card Slot 0 card Damaged or defective FIFO on node Link rate set too high for cable length Damaged cable or connector to link Possible write to same memory location in two or more cards at the same time This must be prevented in software Damaged local node Link rate set too high for cable l
30. nt previous to the interrupt command will be present on receiving board s memory before the interrupt will be issued to the receiving board The Command Register is Write only Table 3 2 Reflective Memory Board Interrupt Codes D7 D6 D5 D4 D3 D2 DI DO Function 0 0 not valid no interrupt is generated 0 1 Interrupt 1 is generated INT level set by 1 0 Interrupt 2 is generated INT level set by CRINT2 1 1 Interrupt 3 is generated INT level set by CRINT3 X 1 X X X X X X Interrupt is generated in all chassis X 0 X X X X X X Interrupt is generated in chassis ID which was written previously at relative address 07H A word or Lword Write can specify both interrupt type and receiving Node ID in one transfer In the event of an external interrupt 1 INT1 INT2 INT3 the Reflective Memory Board will prevent the loss of any subsequent interrupt of the same type through the use of a dedicated FIFO for each interrupt type The interrupt handler must execute a Read of the sender ID Register in order to allow the next interrupt of the same type to be sent to the BIM For example an interrupt INT1 has been sent across the link immediately followed by a second INT1 The receiving node must determine that the Reflective Memory Board has issued an INTI through the use of the resulting INT level 0 through 7 and its vector The second interrupt will remain in the FIFO until the receiving node executes
31. nterrupt 3 enabled at level 1 Auto clear bit 3 low off X IN bit 5 low internal printf NrWMn Setup waiting on interrupts from node 1 r nHit any key to continue after sending interrupts Nr Mn getc printf intO status intl x int2 int3 x intOstatus intlstatus int2status int3status printf r n n intl int3 should number of node sending interrupt printf r n n sending data to Reflective Memory r n to generate transmit half full interrupt 0 for aa lt Oxfaaaaa aa 1 uut mem5576 uut mem5576 uut mem5576 uut mem5576 GFK 2054 Appendix A Example Code A 3 4 printf r nintO status x intl int2 int3 x intOstatus intlstatus int2status int3status printf r nintO should 4 hex Hit any key to continue getc printf r n n sending interrupts 1 2 3 to node 1 for 1 aa lt 4 aa 1 uut cmdnd 0x01 uut cmdreg node one into register 0x07 Send interrupts 1 2 3 to node in reg 0x07 printf NrNnMnProgram complete pragma interrupt void isr intO void intOstatus uut csr wait for transmit fifo to clear do jwhile uut gt csr
32. odify System Because of the danger of introducing additional hazards do not install substitute parts or perform any unauthorized modification to the product Return the product to GE Fanuc for service and repair to ensure that safety features are maintained IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Chapter Configuration and Installation 2 This chapter contains configuration and installation instructions for the Reflective Memory Board and is divided into the following sections Physical Installation Jumper Installation Fiber Optic Link Configuration ACK Daisy Chain Some of the components assembled on GE Fanuc products can be sensitive to electrostatic discharge and damage can occur on boards that are subjected to a high energy electrostatic field When the board is placed on a bench for configuring etc it is suggested that conductive material be placed under the board to provide a conductive shunt Unused boards should be stored in the same protective boxes in which they were shipped Upon receipt any precautions found in the shipping container should be observed All items should be carefully unpacked and thoroughly inspected for damage that might have occurred during shipment The board s should be checked for broken components damaged printed circuit board s heat damage and other visible contamination claims arising from shipping damage should be filed with the carrier and
33. other nodes some period of time later The link between the nodes is two fiber optic cables that pass address data and interrupt information between adjacent boards on the link The Reflective Memory Board allows a user to Read or Write the RAM address space at will memory Writes are stored in SRAM on the board and also put in a FIFO to be broadcast to all other nodes n interrupt command may also be written to any or all chassis by writing a data word into a specific location in RAM The data value written dictates which node s will receive the interrupt The interrupt is sent out in the order the data was received from the VMEbus so if a block of data was written to the board before the interrupt command is sent then the data will be broadcast to all boards before the interrupt command is broadcast Note If there are empty slots to the left of the Reflective Memory Board then IACK jumpers must be installed for the empty slots Otherwise the Reflective Memory Board will intermittently fail to respond to VMEbus reads and writes IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Base Address Selection The base address of the Reflective Memory Board is jumper selectable Once the base address is established all other writes to the Reflective Memory Board will be relative to the base address Each node on the link may have a different base address Only the relative offset to the base address is passed across
34. ransfer statistically is certain to be received correctly The CSR bit 3 is always set if a single transfer error is detected regardless of the state of the mask jumper Spare Field J6 GFK 2054 Not used Chapter 2 Configuration and Installation 2 9 Figure 2 5 Reflective Memory Board Board Node ID Jumper Field DEPTH1 e e j MEMDEPTH2 jo 1 STD EXTD ADDRESS SEL CONFIGURE BOARD NODE ID OF Address Mode 07 HEX Select J4 97 222222328 29995 a Extended Standard Address Address Field Field P2 1C697VRMO015 Reflective Memory Board User s Manual May 2002 GFK 2054 Figure 2 6 Reflective Memory Board Address Modifier Jumper Field MEM DEPTH 1 e j MEM DEPTH 2 e e j P1 e STD EXTD ADDRESS SEL ee 1 2 3 e Address Mode Select JUMPER ARRANGEMENT TO CONFIGURE BOTH SUPERVISORY AND NONPRIVILEGED Be DATA ACCESS Extended Standard Address Address Field Field P2 GFK 2054 Chapter 2 Configuration and Installation 2 11 2 12 Fiber Optic Link Configuration A link of the Reflective Memory Board is formed by connecting the transmit of Card A into the receiver of Card B Card B s transmitter is then connected to the receiver of Card C and so on The last card in the link has its transmit connected back to Card A rec
35. t wait for the current cycle to finish to gain access to the RAM IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Daisy Chain If there are empty slots to the left of the Reflective Memory Board then IACK Jumpers must be installed for the empty slots Otherwise the Reflective Memory Board will intermittently fail to respond to VMEbus reads and writes GFK 2054 Chapter 2 Configuration and Installation 2 13 2054 3 Programming This chapter contains programming instructions for the Reflective Memory Board and is divided into the following sections Introduction to Controlling the Reflective Memory Board Board Identification ID Register Node ID Register Board Control and Status Register CSR Programming the MC68153 BIM The Command Register Definition 06H Command Node 07H Interrupt Sender ID Registers 26H 2AH 2EH Local Status Interrupt 3 1 Introduction to Controlling the Reflective Memory Board Although the Reflective Memory Board is software transparent on power up some registers are present to facilitate user information and interrupt generation Table 3 1 on page 3 3 shows the memory mapped registers used by the Reflective Memory Board 3 2 IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 2054 Table 3 1 Reflective Memory Board Memory
36. the link Thus each board on the link may have a different VMEbus address and addressing mode GFK 2054 Chapter 4 Theory of Operation 4 3 Fiber Optic Link Speed Selection 4 4 At full speed the link can support a 6 2 Mbyte data transfer rate However the high speed serial fiber optic s bit error rate may result in erroneous data being transferred A slowdown option has been included to allow the link to be slowed down by a factor of two VME interface response time will not be affected by the data link slowdown transfer errors are detectable via parity checking and on board receiver error detection circuitry The slowdown mode results from sending each data twice The redundant transmissions statistically lowers the probability of data corruption The probability of data transmission failure of both transmissions is once every three thousand years Redundant transmissions guarantee that all data will arrive across the link correctly A fiber optic transfer error is a rare event and the board which has the receive error has the capability to notify the local VME chassis that it has occurred In most systems it should be preferable to operate in single transmission mode to maintain high data throughput In the case a retransmission request is too slow the double transmission mode is available IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Bus Interrupter Module BIM To facilitate handling of interrupts an MC68
37. the link should be sequentially numbered starting with 0 Jumper field J9 provides a double hexadecimal digit defining the board node ID An installed jumper sets the corresponding bit to 0 There is no relation between node number and physical position on the link Nodes may be physically located in any order Refer to Figure 2 8 on page 2 12 Address Modifier Select J8 The Reflective Memory Board may operate in one of three modes supervisory data access nonprivileged data access or both The different options are shown in Figure 2 7 below and Figure 2 9 on page 2 13 Figure 2 7 Address Modifier Jumper Options J8 J8 J8 BOTH NONPRIVILEGED SUPERVISORY Fast Field J5 If the J5 jumper is left off the fiber optic link rate is 6 2 Mbytes If the jumper is present the link rate is 3 2 Mbytes The 3 2 Mbytes rate results from transmitting every data word twice If an error is detected in the first transmission it is thrown away and the second transmission of data is used If the first transmission is OK the second is ignored Mask Field J3 If the mask jumper is present the INTO on the MC68153 interrupt IC is set when a data error is detected The CSR can be read to determine if the INTO was set by the transmitter becoming half full or by a transfer error If the mask jumper is removed then no interrupt is generated In redundant transfer mode the user does not care if a transfer error occurs on a single transfer since the second t
38. tvect function that installs the interrupt service routine address in the vector table based on the vector chosen IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 USER VECTOR is a macro in our test library that adds a passed value to the first available user vector for the Force CPU 33 interrupt table A setvect USER VECTOR 0 amp isr intO setvect USER VECTOR 1 amp isr intl setvect USER VECTOR 2 amp isr int2 setvect USER VECTOR 3 amp isr int3 initialize intr vector register to installed ISR Aur uut intOvr USER VECTOR 0 uut intivr USER VECTOR 1 uut int2vr USER VECTOR 2 uut int3vr USER VECTOR 3 Clear interrupt registers of all previous interrupts E uut gt intlsid 0 data doesn t matter uut int2sid 0 uut int3sid 0 Setup interrupt mode control registers uut gt intOme IRQ LEVEL 7 INT ENABLE interrupt 0 enabled at level 7 Auto clear bit 3 low off X IN bit 5 low internal uut intimc IRQ LEVEL 5 INT ENABLE interrupt 1 enabled at level 5 Auto clear bit 3 low off X IN bit 5 low internal uut int2mc IRQ LEVEL 3 INT ENABLE interrupt 2 enabled at level 3 Auto clear bit 3 low off X IN bit 5 low internal uut int3mc IRQ LEVEL 1 INT ENABLE i
39. ystem to work The first requirement is that each Reflective Memory Board on the communications bus must have a unique node ID address jumper selectable on board No two nodes can share the same node number i e 0 1 255 Nodes may be intermixed in any order as far as unique board IDs are concerned There is parity and other error checking hardware on the link so the Reflective Memory Board will inform the user if an improper condition in the link exists Each Reflective Memory Board may be mapped into a different address space Data will appear in the same location in each node relative to the base 1 Mbyte boundary each Reflective Memory is mapped to IC697VRMO15 Reflective Memory Board User s Manual May 2002 GFK 2054 Figure 1 1 Reflective Memory Board Functional Block Diagram 1 3 e104 seun i A S 7495 ulgjeiqeua sour Le Sur 109125 isy 0 AINA 992 Ms jonuog uppy 5 sjeuBis jouju09 uM p pue 5 1910 91007 lt so 1819 A2U O3IH lt 1419 Sour19 LINI Soult Z 1412 1412 215 215 diu diu Chapter 1 Introduction Description and Specifications 1 04 Xu 03 2190 19914 2190
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