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ACORN COMPUTERS LTD. ACW 443 SERVICE MANUAL

1. J2 Pin 1 2 READ WRITE CURRENT HEAD 2 3 4 HEAD SELECT 2 2 5 6 WRITE GAT 8 SEEK COMPLET 9 0 TRACK 0 11 2 WRITE FAULT 13 4 HEAD SELECT 2 0 15 6 RESERVED 8 HEAD SELECT 2 1 19 0 INDEX 21 2 READY 23 4 STEP 25 6 DRIVE SELECT 1 27 8 DRIVE SE CIT 2 29 0 DRIVE SELECT 3 31 2 DRIVE SELECT 4 33 4 DIRECTION 020 Pin no 1 2 0V 3 4 0V 5 6 OV 7 8 OV 9 10 RESERVED TI 12 OV 13 14 MFM WRITE DATA T5 16 OV 17 18 MFM READ DATA 19 20 OV Winchester and Floppy Disc Systems The read and write MFM data lines pins 13 14 17 and 18 of JO are differential signals 6 6 The 1MHz expansion bus The following is a description of the 1 MHz expansion bus signals used by the Winchester Disc Host Adapter and their funetion as applied to the Winchester Disc system For a full deseription of the 1MHz expansion bus see 138C Microcomputer Application Note Number 1 1MHz Bus part number 0407 000 published by Acorn Computers Limited 6 6 1 Control address and data lines 2 system 1MHz pin 4 is a continuously running 1MHz timing signal During aecess to the IMHz bus the proeessor elock normally 2MHz is stretched so that the trailing edges of IMHZE and the processor clock are synchronised R NW read not write pin 2 is the system read write line NIRQ not IRQ pin 8 is the in
2. GS SSS SY YS SSE ia 155 1 2 1 3 DATE 01 10 84 20 12 85 28 1 88 Dav PDP JW amp Cm 7777 CHNG AMR 598 Eco 50016 ECO E198 TTT TITLE ABM CONTROL BOARD COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0133 400 SHEET 2 of 6 CHERRY BINTON CAMBS PARTS LIST ACORN COMPUTERS LTD ITEM PART NO DESCRIPTION QTY REMARKS 81 0630 150 CPCTR CPLT INS 30V 10 1 C11 82 0630 220 CPCTR CPLT 2N2 30V 10 4 C26 31 34 35 83 0630 330 CPCTR CPLT 3N3 30V 10 1 cg 84 0630 470 CPCTR CPLT 4N7 30V 10 4 C19 21 42 43 85 0629 010 CPCTR CPLT 10N 30V 805 2 C3 13 86 0650 333 CPCTR MPSTR 33N 50V 20 1 C29 87 0680 002 CPCTR DCPLR 100 AXA 25V 67 A 88 0640 473 CPCTR CER 47N 30V 80 1 C24 89 0640 104 CPCTR CER 100N 30V 80 5 c5 7 9 23 90 0651 224 CPCTR CER 220N 12V 80 2 38 41 91 92 0613 100 CPCTR TANT 140 35V 20 1 c33 93 0635 047 CPCTR ALEC 4u7 16V RAD 1 30 94 0635 100 CPCTR ALEC 10u 16V RAD 3 C27 51 52 95 0621 047 CPCTR ALEC 4u7 10V AX 1 C15 96 0610 010 CPCTR TANT 10u 10V 20 1 C357 97 0621 470 CPCTR ALEC 47u 10V AX 6 25 46 50 54 56 60 98 0610 047 CPCTR TANT 470 10V 20 1 C37 99 I 100 101 102 103 104 105 106 107 0820 160 XTAL 16 00MHz HC18 U PR 1 X1
3. FULBOURN ROAD DRAWING No A4 0133 400 SHEET 1 of 6 CRERRY HINTON CAMBS PARTS LIST I ACORN COMPUTERS LTD ITEM PART NO DESCRIPTION QTY REMARKS 41 0502 104 RES 100K CF 5 0W25 3 R28 41 70 42 0502 154 RES 150K CF 5 0925 2 R137 145 43 0502 224 RES 220K CF 5 OW25 3 R39 77 136 44 0502 274 RES 270K 5 0W25 1 R83 45 0502 824 RES 820K CF 5 OW25 1 R135 46 0505 103 RES 10K 2 0 25 4 R140 143 47 48 0505 104 RES 100K C MF 2 0W25 4 R106 110 125 134 49 50 0502 105 RES 1M0 CF 5 0W25 3 R17 24 25 51 0502 155 RES 1M5 CF 5 0925 2 R78 79 52 53 54 55 0581 104 RES PSET 100K C LN 20 H 1 VRI 56 57 58 0590 223 RES NET 22K TF 10 9P L RP2 59 60 61 62 63 62 65 66 67 0631 033 CPCTR CPLT 33P 30V 2 2 C12 15 68 69 0631 047 CPCTR CPLT 47P 30V 2 2 44 45 70 0631 068 CPCTR CPLT 68P 30V 2 2 C4 18 71 0631 100 CPCTR CPLT 100 30V 2 1 C20 72 73 74 0631 270 CPCTR CPLT 270P 30V 2 1 C22 75 76 77 0630 082 CPCTR CPLT 820P 30V 10 2 58 59 78 79 80 ITEM PART NO DESCRIPTION QTY REMARKS xar t ib ERR SPG Sum ma GN OR CE OAK SGS 2 NAAR h LAE um HR Hd min XN ee e mr rr
4. EN o Las R 8X N LA TT se cmn Lo 54 1 xix pe Tegel de bq Hike 2 J F mir P4 8 See IEE e 1 P gga 0 TT T n asak OX w EON fra 592 ENEN D pen waa rT n KIM 5 cs SECO em ant MS in ERRENTEN wu ipe TUE em HIT Tai 7 Hr C she c s Pi a apo a T UOR TE Om m mU T ze gt 3 n 0 33 st lo D RSS Cit Ni 4 0 x H Sora EM gm D xc E oj ver um s LECT NC p Im lt i i EL a le 0 Te UNE 1 ich CSUN 3 45 lt 91 lt E LU Pe E P UP Li 1 5 x AU 14344 MS 22 551 I E nm M nn Sata TD ICIS X1 Pew IC File Piet ICL umma m Lm ni m im num 3 1 WF 4154 80 Totem mis unio t tetu a i 2 p 000 REDUCE TO tcea Ride
5. adl C owe ed ot disclosed Copyright of 16 LTO H Is Iss eas Fae Oe se M fee ALL OIMENSIONS M mm UNLESS OTHERWISE STATED E DECIMAL No TOC DO IF IN DOUBT ASK THRO ANGLE PROJECTION E E z m dd d NT zizi jl Jud EN bo Era bo x FRERE 111 11 j E IRL LED w ecdi4l 1 4 lt I eae aaa ru Se Em m am xz x xz m zm is 24 F z a3 s ig m Is epu d ACORM COMPUTERS LARGE 32016 SECONO PROCESSOR Mr BOTTON BOTTOM 524288 18048576 1572864 2297152 26521440 3145728 5570015 524284 1848574 1572822 2097159 221438 5145726 3670014 41743082 85060 1200000 186980 200000 280000 3069090 380008 60 topZ botZ kO7FFFE 78 L 90 botZ topZ 2 RUM a 5 FOR M4 1 TO B AD PRINT topZ bot top botz 20 top kO7F FFE SFFFFE 18 FRINT 28 hotZ TOP 7FFFE FFFFE
6. M a CHNG AMR 615 ECO E198 TITLE ACW KEYBOARD ASSEMBLY COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0020 001 SHEET 1 of 1 CRERRY HINTON CAMBS PARTS LIST ACORN COMPUTERS LTD 4 0127 000 Sht of 1 WEE EINE NEN 29 0800 87 conector so pan Wang o jez 28 0800 870 pin ADR 1 EH as INTEGRATED CIRCUIT 74 LS 14 IC8 f 0742 004 INTEGRATED CIRCUIT 74 LS 04 1 9 13 ICI 1 amp 740 014 INTEGRATED CIRCUIT 1c15 1 16 5 CAPACITOR 2216y CI 622 220 11 ao 0 CAPACITOR DECOUPLER RP2 RP 5 8 jene 1 14 SIKET i PIN 571 222 RESISTOR PACK 16 PIN 0 1 1 2K2 RPA RESISTOR PACK 16 D I t 2K2 RP2 RP3 RESISTOR PACK 16 PIN D f L 2118 3208 RP o 4 222 RESISTOR 202 55 R1 AN PRECES a h1 0227 000 t BARE P C B ITEM PARTNo DESCRIPTION QTY REMARKS ZW 5w UA iode 19 erora iss p 3 Copyright o this drawing is resr rved by ACORN COMPUTERS LTD tt is issued on condition that it is not copied reproduced or disclosed lo a COPYRIGHT 1984 ACORN COMPUTERS Lid
7. 838 D b Rite 535 501 5 i 133 iq mi Mme n ms Rik csi ac R13 2 z ana m F n COPYRIGHT 188 000 55 JU Uo Cos e a 2 m a 11 c t m a 8 5 c CSL in a 128 19 i PL 1 cUm 30 t0 CE RBM CONTROL 155 DATE BOARD SIE 56 pG ND 0233 1 2 000 0 005 INS qa Red 3 ne 13 0 B S 8 cl 0 x mee 169 N ea T Aud Phe Sp z z0 O x itt 1 mur 88 2 8 TES 5 ase Cig cua si j lt 2 A Lae a Cs CL 34 ces E E IC A R A 1C9 ICS MS i HEE 0150 00 0114 TL 814 0 t NY3 18 419 t 9 5 ASe 7 ad o OQ UALS O 2313707 iid 0 gt 1 Au F z ASe NOISNYdX3 91d 4 AS AG 5 UAT o AD t 92 5 toms j
8. FULBOURN ROAD DRAWING No A4 0133 400 SHEET 6 of 6 CBERRY HINTON CAMBS PARTS LIST ACORN COMPUTERS LTD RP a n t GR m VOR UAR YES SHE AR wc ms dub Das NA VPE G VW UE Hd E EE UNE FW E i ERS mc ma OF GS UU ITEM PART No DESCRIPTION QTY WHERE USED C PER C TO was SSE 289 ar 2 GRE DU mat man ee UU 269 HD Suk HR ie Sg HOD GG E SR Gs ee 1 2 3 4 5 6 0201 605 IC ULA TUBE 1 7 0201 763 PANDORA HIGH ROM 1 8 0201 764 PANDORA LOW QM 1 9 10 11 0218 100 BARE PCB 1 12 13 14 15 2201 207 ACW 32081 FPU HEAT SINK 1 16 2201 208 ACW 32016 CPU HEAT SINK 1 17 2201 209 ACW 32201 TCU HEAT SINK 1 18 19 20 21 0502 103 RES 10K 5 0925 5 22 0502 332 RES 3K3 C MF 5 0825 5 23 0502 471 RES 4708 5 OW25 2 24 0520 120 RES 12R C MF 10 190 1 25 0571 330 RES NET 33R TF 2 16 9 26 0590 332 RES NET 3K3 TF 10 9 4 21 28 29 30 0610 047 CPCTR TANT 474 10V 20 4 31 0613 100 CPCTR TANT 1140 35V 20 1 32 0628 100 CPCTR CDSC 10n 30V 80 1 33 0637 102 CPCTR CML 1in0 SOV 80 1 34 0680 002 CPCTR DCPLR 33 47n 0 2 182 35 36 37 38 39 40 ITEM PART No gt DESCRIPTION QTY WHERE USED C TO
9. mixed within the same M byte bank as the noise imunity of some makes of DRAM can be impaired 98 ACW SERVICE MANUAL Issue I 32016 Processor Figure 5 6 1 Memory Upgrade Order lt i Installed Manufac tte M t 1 2nd Meg I 3rd Meg 2 amp B aui Pn 5 HB f ee Va qme Ji 1 1 1 1 1 e em m pp re durum J mm paun s mm Chapter 5 5 6 2 Changing ROMS Pandora ROMS are fitted in two 28 way sockets next to the 40 way 1DC cable The new ROMS must be fitted in the same direction as the old The H1GH Pandora ROM is fitted next to the 40 way TUBE connector 5 6 3 Memory manager Not yet available 5 7 Fault finding WARNING Be extremely careful when extracting the 32016 Processor from its socket it is easy to crack the ceramic package and this 1C is expensive The 32016 5V power supply must be 5 00V and no less as measured on BOTH sets of Faston connectors The DC power supply to this PCB should always be checked before and after servicing If less than 5 00V it is essential that the power sup
10. OO C ACW SERVICE MANUAL Issue 1 65 Chapter 4 Monitor the two chip selects pin 9 IC82 and pin 9 IC85 These should be wobbling If one is faulty then check the address decoding IC21 and IC39 and the connections from pin 5 and pin 6 IC39 If the cassette fails to SAVE then SAVE a section of ROM and check that there is a synthesised sine wave signal from IC85 pin 27 of around 1 8V peak to peak If not then replace 1 85 If there is then replace the LM324 IC89 RS423 66 Use a PORT tester to verify that the RS423 is faulty One way of checking the operation of the RS423 is to connect the SUSPECT microcomputer to a known working microcomputer via their RS423 ports The connections must be made as follows Din to Dout pin A to pin B Dout to Din pin B to pin A OV to OV pin C to pin C CTS to RTS pin D to pin E RTS to CTS pin E to pin D Once the two machines are connected switch on the power for both and configure the known WORKING microcomputer to accept RS423 as input by typing FX2 2 This command will cause the microcomputer to accept input from both the keyboard and RS423 so keyboard commands will still work Now type the following BASIC program into the SUSPECT microcomputer 10 FX3 5 20 REPEAT 30 PRINT U 40 UNTIL 0 This program configures the SUSPECT microcomputer to give output to the RS423 and to the screen It then prints the character U whose ASCII code is amp 55 am
11. o Pe E DAG 0118 100 iJ F SE S 494143411 r uc owes SCALE LS ALL DIMENSIONS IN mm UNLESS OTHERWISE TATEO Copyright of ibig drawing MATERIAL i LTO M is hsued condi iuo x 1 or diaclosed 10 third DECIMAL TOL ANGLE TOL without the _ r oe te GLE PROJECTION IF IN DOUBT ASK DO NOT SCALI Lowe 8 ry ut lh Pe a 1 Li Coe 14 i 41 4 tit u a TL iM 5 7 gal GNE we ee zm 7 weseeed by ACORN COMPUTERS GR m that H Is noi copied reproduced LARGE 32016 SECOND PROCESSOR Ir Hher wholly or CAMBRIDGE Col ain vae i lt ig of ACORM COMPUTERS LTO PUTERS Lid CS as a n lt z 2 M 2 z E ut mmt Hmm m D Y mm ne als aap 1 eI m AW 1 1 LE pz M mc 4 P DD ze Su i 1 n i 1 m i i i ut Ve lulu Pu ia DS PZ EEE zE 1 cal md me ET dl ui mut cum Pu E
12. ME IIO Se E CE DNE SUE sa wx x wa e t TITLE ACW 443 FINAL ASSEMBLY COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD mimm a im 2 FULBOURN ROAD DRAWING No A4 0020 233 T SHEET 3 4 CHERRY 5 PARTS LIST ACORN y TERS LTD 2S St sm xz ux z xz AO F zm s mz s ITEM PART NO 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 0201 448 2201 115 2201 203 0201 958 2201 001 2201 166 2201 163 0800 600 0800 985 0907 003 0870 109 2201 352 0882 143 0882 974 0882 904 0882 964 2201 353 2201 354 2201 355 0885 206 0882 127 2201 356 DESCRIPTION VIDEO C FORM COLOUR PROCESSOR LOGO PROCESSOR LOGO 2 FAN ASSY DISC WINCH DRIVE INSUL LH SIDE TRAY INSUL RH SIDE TRAY INSUL CONR BNC 5 75R PNL CONR LATCH FOR D SHELL MATL 4mmT FOAM RUBR SF AD WIRE 7 0 2 WHITE PVC ACW PWR DIST PCB OV STRAP SCW 4 10 PAN HD POST WSHR M4 SPRF IT STL NUT M4 STL FULL 2 PAS WSHR M4 PLAIN ACW UPPE
13. 8 z E ORG No FIRST USED 0020233 wD ACW 2222 1 LARGE 310 PROC COMPMAST CONTRO CONTRO E uL THIRD ANGLE PROJECTION I I TERE Tm HES i boi ST VIDEO CONTRA CON AX 4 APPL T aver THE MELE ITEM 10 TO MOUNTING FACE OF ww PRIOR TC ATTACHMENT TO ITE 15 CUT TO AND Fo 38 OVER TABS IN POSITION aS HEQURED ITF 17046 ART LABE BE FIED 7 POSTION at AA S POSSMAE fO CONTRAST CONTRO VOL CONTRO IEE FROM FN OF UNT 1 Bn iat LARGE 32016 OTe 2nd PROC b2 i Gere Saree zl P C B WES TE i wre WPKHESTEF nos ER EO SMS i mee s i i 1 H H POWER DIST P C B TENIS i dud J 2 097 pes 13 OECD 432 E 19 180 Mrd SPD BANL 63003 114 04 601 mil 1 A dY f i97 TT aE SE ELT xk FF GNE GEI Oma x DX E mr Ux E t ztz s FY nil Sas x xr mt me x z
14. IC62 8 9 515 i IC68 10 11 518 IC71 0 1 or 519 cuttable link made E as standard for 32K 14 15 16K operating system and I O and 16K BASIC Table I ROM Sockets As can be seen from table 1 ROM numbers range from 0 to 15 ROM priority is directly proportional to the socket number it is in The highest ROM number language and filing system will be selected after a reset 15 has the highest priority 0 the lowest So if two or more sideways ROMs are language ROMs then the computer will start up in the language in the highest number ROM slot Similarly for filing system ROMS IC35 44 57 62 and 68 we shall call user ROMs Each user ROM socket is functionally identical and can contain language or service ROMs IC71 we shall call the system ROM The system ROM contains the operating system The operating system is always in the memory map from amp C000 amp FFFF and must always be fitted in IC71 As an option the computer can accept a 32K ROM for IC71 containing the operating system and the BASIC language In this case link 519 is East in the 32K position The BASIC part of the system ROM occupies one of four sideways ROM numbers As standard any call made to ROM 14 or 15 selects BASIC and any call to ROM 0 or I is ignored Hence BASIC occupies the highest priority ROM slot and the computer will start up in BASIC If molex link S13 is moved from South to North then any call made to ROM 0 or 1 will select BA
15. 4 DATE 28 7 86 A he DRN CWW U CHNG AMR E249 TITLE 32016 LARGE 4MByte PCB ASSY COPYRIGET 1986 BILL OF MATERIALS ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0118 100 BM SHEET 1 of 4 CHERRY HINTON CAMBS BILL OF MATERIALS ACORN COMPUTERS L T D ITEM PART No DESCRIPTION QTY WHERE USED C TO 41 42 0704 103 4256 DRAM 150 5 256Kx1 128 32016 CPU NMOS 10MHz 1 32081 FPU NMOS 10MHz 1 32201 TCU NMOS 10MHz 1 45 0732 018 46 0732 083 47 0732 203 52 0738 095 81 595 20 0 3 14 56 0741 004 74504 TTL 14 0 3 1 14 0 3 14 0 3 14 0 3 14 0 3 14 0 3 14 0 3 14 0 3 TTL TTL TTL TTL TTL TTL TIL 60 0742 000 741500 61 0742 004 741504 62 0742 010 741510 63 0742 027 741527 64 0742 032 141532 65 0742 074 741574 0742 114 0742 138 0742 240 0742 244 1415114 7415138 7415240 7415244 TTL TTL TTL 16 0 3 20 0 3 20 0 3 20 0 3 14 0 3 1415245 7415393 TTL 70 0742 245 71 0742 393 ID IND 8
16. Error addr HHHHHH This is the hex address of the fault Written BBBBBBBB BBBBBBBB This is the binary data written into memory at the faulty address D15 D8 D7 D0 Read BBBBBBBB BBBBBBBB This is the binary data read back from the faulty address D15 D8 7 Some examples will illustrate how this information ean be used to identify a variety of faults Example 1 A faulty DRAM In this example bit D5 is stuck at 1 but only at a small number of addresses To find out which DRAM contains this bit at this address use the tables in Appendix In this example the fault is in IC90 Example 2 Faulty PCB Data bit or faulty DRAM At first glance this looks similar to example one but note that ALL addresses are failing one bit this could indicate a faulty DRAM a DRAM in the wrong way around or a fault on the PCB ie a short circuit Example 3 Faulty PCB Address bit Because each memory bank has its own set of address buffers a faulty address line may not show up as a fault at all addresses A typical fault report is shown note that the pattern read from the memory appears correct but shifted up or down in memory It is impossible to write a test program that will fully identify faults of this kind Example 4 Refresh fault If a random or semi random pattern is read from the memory you should suspect a fault in the refresh circuitry The act of writing or reading refreshes the dynamic memory
17. 108 109 110 111 0810 001 RLY 19 CO SV 50R 1 RLI 112 113 114 0780 239 TRANS BC239 NPN 6 Q1 5 7 115 0780 309 TRANS BC309 PNP 1 08 116 117 118 119 120 0794 148 DIODE SI 174148 8 02 4 9 11 16 18 DESCRIPTION QTY REMARKS ISS 1 2 3 DATE 01 10 84 20 12 85 28 7 86 DRN PDP PDP JJW amp CWW AMR 598 ECO 50016 ECO E198 TITLE ABM CONTROL BOARD COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD Mai mi mr m idm nam Ft FULBOURN ROAD DRAWING No A4 0133 400 SHEET 3 of 6 CHERRY HINTON CAMBS PARTS LIST ACORN COMPUTERS LTD ae wu sus mn ss x tq aa s ITEM PART NO DESCRIPTION QTY REMARKS 1 uma wam min ux nic SG Cam Yaar um GD xar ua GR MED AUR mam RA mam Tam sap i wam v 121 122 123 124 0740 016 7416 14 0 3 1 168 125 0740 038 7438 TTL 14 0 3 1 126 0741 000 74500 TTL 14 0 3 1 IC52 127 0742 000 741500 TTL 14 0 3 2 IC19 27 128 0741 002 IC 74502 TTL 14 0 3 1 1533 129 0742 002 IC 74LS02 TTL 14 0 3 1 58 130 0741 004 74504 14 0
18. IC42 IC43 IC44 IC45 IC46 IC47 78 various I O devices which operate with IMHz 1E interface timing 6512A CPU The 6512A is a member of the NMOS 6500 processor family This IC is functionally similar to a 6502A the only significant difference being the clock drive A 6512A uses MOS level clocks phil and phi2 and so gives more precise system timing than is possible with the TTL phi in clock of the 6502A THE TWO PROCESSOR TYPES ARE NOT INTERCHANGEABLE This microcomputer can use 2 3 or 4 MHz CPU parts 6512A B C NE555 Monostable IC The 555 is used as a monostable for generation of the microprocessor system reset pulse It is triggered at power on or by the keyboard BREAK key A logic 1 active output pulse is generated and part of IC27 inverts RS to form NRS the CPU reset various 64 128 or 256Kbit paged ROM A 32Kbyte device in this socket appears in sideways ROM slots 4 and 5 link S11 East Link S11 West allows 8 or 16Kbyte EPROMS ROMSs to be fitted This device can be ROM or EPROM with a NCE access time less than 250ns T4LS 163 Synchronous divide by 16 counter Used as a 4 bit latch which holds the paged ROM ID The IC is clocked by N2E When the latch is addressed at amp FE30 its LD enable is taken low active and the write data on the CPU data lines DO to D3 is latched The load event is effectively when phi2 falls The QA output latched DO is used as a pseudo address line for 32Kbyte ROMs
19. SLF AMAL 0 05mmT A R 100 0887 002 SPCR NYL 4 76mm PCB GAP 14 101 0887 003 SPCR NLY 9 52mm PCB GAP 6 102 0945 000 HEATSINK COMPOUND SI A R 103 0907 009 TAPE FELT SLF ADH A R 104 0890 001 FOOT SO RUBBER 12 7Dx3 5mmH 4 105 0890 010 MATL RUBR SEALENT A R 106 0831 500 DISC DRIVE 1 107 0831 400 WINCHESTER DISC DRIVE 1 108 0831 104 POWER SUPPLY 85 WATT 1 109 0880 130 CABLE CLIP 12 110 0836 100 MONITOR KIT 12 COLOUR 1 111 112 0835 003 LSPKR 8R 0 1W 50mmD i 113 0201 710 WINCHESTER DC POWER CABLE 1 114 0201 71 WINCHESTER IN OUT RIBBON 1 115 0201 712 WINCHESTER DRIVE RIBBON 1 116 0201 713 WINCHESTER 1MHz BUS RIBBON 1 117 0201 714 WINCHESTER BD TO BD LK RBN 1 118 0201 716 DISC DRIVE DC SUPPLY CABLE 2 119 2201 165 MBYTES DC SUPPLY C FORM 1 120 0201 723 SAFETY EARTH LABEL 2 ITEM PART NO DESCRIPTION QTY REMARKS ISS 1 2 3 4 yU ee ey eee m CHNG AMRS0010 ECOSOO18 ECO E117 ECO E226 TIR ua oe AC E GNI EE GSC CC IX ee Tat
20. A number of main component blocks can be identified these are Central processor unit CPU NS32016 Timing and Control unit TCU NS32201 Floating Point unit FPU NS32081 Tube R Memory Driver Bank 7ALS24x Series devices Dynamic Memory array 256K bit DRAMs EPROM 2 off 16K 8 ACW SERVICE MANUAL Issue 1 87 Figure 5 2 1 32016 Block Diagram Chapter 5 0 Xtal 5 EP 17 ee ee lt lt we ee ee m r u e i ADO AD23 u m Config inks re M P 1 t I 1 I I i Host ist Meg 2nd Meg 3rd Meg th Meg Figure 5 2 1 b 4 M BYTE 32016 Memory Banks Low 1 2 Meg Hi 1 2 Meg I 5 t i i i WEO 7 RASO 7 DO 15 32016 Processor PCB CAS O Low Byte CAS 0 High Byte CAS 1 Low Byte CAS 1 High Byte CAS 2 Low Byte CAS 2 High Byte etc CAS 7 Low Byte CAS 7 High Byte 5 main bus connecting these components together is the 24 16 bit A D bus this is a bidirectional multiplexed address data bus The CPU is responsible for instruction fetch decode operand fetch and the execution of integer arithmetic Flo
21. Before formatting a winchester locate the ACW Service Card shipped with every ACW The Service card contains the defect list for the installed winchester and should be ammended when the winchester is replaced or repaired If a new winchester is being installed the defect list marked on the drive case together with the serial number must be copied onto a new Service card or sheet of paper and left with the machine The format program is supplied on the ACW ADFS Utilities Dise See appendix This dise contains a suite of programs that run on the I O Processor 1 Turn off the 32016 co processor using the TUBE switch on the back of the keyboard The TUBE LED on the keyboard should he OFF 2 Seleet BASIC Prompt by typing Basic RTN 3 Select the ADFS filing system type ADFS RTN 4 Insert the ACW ADFS Utilities disc 5 Select the Floppy disc drive type DIR 4 RTN 6 Start up the utilities disc by typing CHAIN UTILS MENU RTN A menu of utilities will be displayed 7 Select the winchester utilities suite type f1 8 Seleet the Winchester disc formatter WFORM type f2 and wait until the message banner Super Winchester Formatter V followed by the ACTION prompt appears 128 ACW SERVICE MANUAL Issue 1 Formatting Discs 9 Press RTN for a list of command options 10 Select option C Change drive parameters to check drive parameters whieh should be for an NEC 5126 drive Heads 4 Cylinders
22. COPYRIGHT 1986 BILL OF MATERIALS ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0118 100 BM 1 SHEET 4 of 4 CRERRY CAMBS BILL MATERIALS ACORN COMPUTERS LTD DRG No 0120 005 DN 2 i UN ee IEEE NEED gt CIR Cn ea at ee ee ee a ae es 28 26 ss UU u T ss asua eee REDE O ED IE s ee Tdi BEER RR REDEEM wem 5 Wo es as U S ee IECUR 2 1 005 ASSEMBLY DRAWING 1 PER BATCH 0220 005 005 ITEM PART No DESCRIPTION 2 METER CHKO 09 DATE 05 84 97 84 CHANGE 47 COPYRIGHT 1984 ACORN COMPUTERS Ltd FULBOURNE ROAD CHERRY HINTON CAMBRIOGE third party either wholly or in part without the CB1 4JN Copyright of this drawing is reserved by ACORN COMPUTERS LTD It is issued on condition that it is not copied reproduced or disclosed to a ABM POWER DISTRIBUTION PUB consent in
23. Odd Byte 0 1 High byte enabled Even Word 0 0 Both bytes enabled Odd Word Odd Byte 0 1 High byte enabled Followed by Even Byte 1 0 Low byte enabled Other categories for Even Odd Double Word and Quad accesses exist but are merely a repetition of the above acceses For more information sec NS data sheets for the 32016 NRAS plays no part in the address decoding scheme and all RAM devices are RASed on every access Note this has no effect on the RAMs other than causeing the addressed location to be refreshed The top 1 M byte is loosely decoded by 1C7 to provide chip select signals for the tube NTUBE The configuration links NCONFIG and EPROM NHPROM See the previous section on the address map for the correct addresses ACW SERVICE MANUAL Issue 1 32016 Processor 5 3 7 Memory driver Bank In order to drive the large number of DRAMs 128 an array of buffers is required in this design the buffers also multiplex RAS CAS and Refresh address bits onto the DRAM address pins Each 1 M byte bank has been provided with it s own set of buffers ie RASI CASI and RFSH1 RAS addresses are taken from bits A to A8 CAS addresses are taken from bits A9 to A16 and refresh addresses are supplied by an eight bit counter 1C45 Line termination resistors 33 Ohms are used to reduce reflections on the address lines caused by the high capacitance of the Drams and long length of these tracks The 9th row and column address bit requir
24. The wire which is coloured green and yellow must be connected to the terminal in the plug which is marked by the letter E or by the safety earth symbol or coloured either green or green and yellow The wire which is coloured blue must be connected to the terminal which is marked with the letter N or coloured black The wire which is coloured brown must be connected to the terminal which is marked with the letter L or coloured red Protecting the Winchester Disc Winchester disc drives are fragile to avoid damage or data loss do not move or knock the Acorn Cambridge Workstation ACW while it is running The ACW must always be moved gently and not tilted rapidly or turned on its side After using the ACW the heads should be moved to the parking zone BEFORE switching off the mains power The exact command that needs to be used to park the heads will depend on which program is in control For instance 1 From PANOS or user defined prompt Logoff ADFS RTN Quit RTN Turn off Power 2 From PANDORA prompt ADFS RTN BYE RTN ACW SERVICE MANUAL 3 Turn off Power 3 From BASIC prompt ADFS RTN gt BYE RTN Turn off Power 4 From UNKNOWN or IF IN DOUBT CTRL and BREAK together will return to a prompt then follow one of the above depending on which prompt it is If anything is typed after parking the Winchester heads in particular BREAK or ADFS there will be a pause while the
25. Then write amp 00 to the output register amp FE60 amp 00 All the data lines to the user connector PL10 should now be low pins 6 8 10 12 14 16 18 and 20 If they are not all zero then check for open circuit tracks on data lines on both the printer side and the CPU side of the VIA Now write amp FF to the output register amp FE60 amp FF the data lines to the user connector PL 10 should now be high If they are not all 1 then check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA A better test is to use the binary configuration 10101010 on the outputs and then change it to 01010101 These correspond to the values amp AA and amp 55 This way short circuits are more likely to give the wrong value in the tests 4 7 14 1M Hz extension bus Use a PORT tester If the IMHz extension bus is faulty then the PORT tester may show up all kinds of errors because it is driven through the 1MHz bus Use the following program to exercise the FRED and JIM address decoding ACW SERVICE MANUAL Issue 1 69 Chapter 4 fred amp FC00 jim 00 DIM P 100 Start LDA amp 00 loop STA fred 0 STA jim 00 JMP 1 110 1 120 CALL starts 0 0 0 0 0 0 0 0 P RUN the program and test pins 4 and 5 IC28 for the FRED and signals which should be pulsing low for lus 1 5us depending on the CPU s synchron
26. m G z ITEM PART NO DESCRIPTION REMARKS 1 0020 233 ACW 443 55 DRG 1 PER WORKS ORDER 2 0020 233 ACW443 WIRING DIAG 1 PER WORKS ORDER 3 4 0133 400 ABM CONTROL PCB ASSY 1 5 0118 100 LARGE 32016 PCB ASSY 1 6 0127 000 HOST ADAOPTOR PCB ASSY 1 7 0837 000 ADAPTEC ASSY 1 8 0120 005 DISTRIBUTION PCB ASY 1 9 0201 866 DISC TRAY SIDE RH 1 10 0201 867 DISC TRAY SIDE LH 1 11 0201 394 CASE BASE MOULDING 1 12 0201 395 CASE LOWER MOULDING 1 13 0201 396 CASE UPPER MOULDING 1 14 0201 397 SCREEN MOULDING 12 1 15 0201 399 BASE AIR INTAKE COVER 1 16 0201 400 AIR DEFLECTOR 1 17 0201 401 THUMBWHEEL 2 18 0201 436 2nd PROCESSOR MTG RH 1 19 0201 788 BRKT RH 2nd PROC TRAY 1 20 0201 433 CBL CONTRAST COLOUR 1 21 0201 406 FRONT SUPPORT RH 22 0201 407 FRONT SUPPORT LH 1 23 0201 422 RH REAR SUPPORT i 24 0201 423 LH REAR SUPPORT 1 25 0201 424 MAIN CHASSIS 1 26 0201 425 DISC DRIVE CHASSIS 1 27 0201 426 PIVOT SCREW 2 28 29 0201 428 RH LOWER STAY 1 30 0201 429 LH UPPER STAY 1 31 0201 430 LH UPPER STAY 1 32 0201 431 RH UPPER STAY 1 39 0201 449 MAIN CHASSIS BRKT RH 1 34 0201 450 MAIN CHASSIS BRKT LH 1 35 0201 434 REAR PANEL 1 36 0201 435 REAR LABEL 1 37 0201 437 EXPANSION LH 1 38 0201 439 CLAMP BACKING PLATE 2 39 0201 440 TOP REAR CHASSIS SUPPORT 1 40 0201 715 RBN DISC DRIVE ASSY 1 ITEM PART NO DESCRIPTION QTY REMARKS DATE 14 11 85 20 12 85 24 6 86 12 9 86 DRN PLH PDP PMK CW
27. n Der EET 8 5 Capa en ane pi g Me A VA SAT fel 06 has positions edly For specml reg m on cemwctad to UV 8 a 4 22224 K 13 C207 i cJ 1 Hur 10 Chassis f T ens I I I I I I I l t l i I f I 1 1 1 Focus 10 DAG 2 z PLN m oF mb uU x E E 47K 1 8 2 jeja sjaji R TRIO 3 IP cele I 8 13 cuz to i tii N 158 B Er 2 1 6 R322 W C225 m ony fitted on medun hoh eodels LKZLK L thas ace rot markt Low MESSA iz IN Uu fou 2 Sy ul ee gt 46 B D ea A ets ag ab A u 5 Su STANDARD MEDIUM RESOLUTION TUBE BASE Mic ROVITE TA Vg D A923 x ioc sedi ver OE sx 82d NIVIA rozu vezi goa331 v 9 186 i V oz a e z m gt lt lt
28. 10 84 20 12 85 28 7 86 DRN PDP i JJW amp CWW CHNG AMR 598 ECO 50016 ECO E198 TITLE ABM CONTROL BOARD COPYRIGRT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0133 400 SHEET 4 of 6 CHERRY HINTON CAMBS PARTS LIST TACORN COMPUTERS LTD EMEN E E E EE gg r Ci E ale se GAY A ee tasa EF Esa sky iS Tan DESCRIPTION _ 1 QTY REMARKS 161 0704 865 IC 4864 DRAM 120nS 64kxl 8 55 56 60 61 64 67 162 0706 511 6512A CPU NMOS 2 1 IC42 163 0706 522 IC 6522 VIA NMOS 1MHz 2 IC10 20 164 0706 845 IC 6845 CRTC NMOS 1MHz 1 78 165 0706 850 6850 NMOS 1MHz 1 IC82 166 0707 002 IC 7002 ADC 12BIT 1 1 84 167 0735 159 75159 DRVR 1 IC91 168 0706 490 IC 76489 SOUND GEN 1 IC38 169 170 0706 854 68854 ADLC NMOS 2MHz 1 ICB81 171 172 173 0705 050 SAA5050 CHTR GEN 1 ICS9 174 0201 272 IC ACW OS ROM 1 IC71 175 0201 666 IC DNFS ROM 1 IC35 176 0201 274 IC ADFS ROM 1 1062 177 0201 795 TERM EMUL ROM 1 57 178 2201 204 IC ACW DFS ROM 1 IC44 179 0201 628 IC BASIC ROM 1 IC68 180 0201 647 IC VID PROC 1 ICS3 181 0201 648 IC SER PROC 1 85 182 0770 555 LM555 TIMER 1 1C43 183 0201 880 PAL 1
29. 10 bit VREF 1 8V typical Accuracy with respect to VREF full scale error Zero scale error Non linearity Temp coefficient Conversion speed Input impedance 0 596 typical 0 596 typical 0 196 typical 6mV degree C typical 10 0ms per channel typical IM ohms I O Processor board 4 1 7 ECONET Line voltages 0 25V and 3V typical into 50 ohms 4 1 8 CENTRONICS compatible printer interface Data strobe 4us pulse 4 1 9 Audio output Output power 0 5W Speaker impedance 8 ohms 4 1 10 Environment Air temperature system on 0 to 35 degrees C system off 20 to 70 degrees C Humidity system on 85 relative humidity at 35 degrees C system off 95 relative humidity at 35 degrees C Storage conditions air temperature 20 to 70 degrees C humidity 95 relative humidity at 55 degrees C 4 2 Circuit description This circuit description has been kept as simple as possible as the detailed fault finding section section 4 7 should prove to be of more use for servicing 4 2 1 General The microcomputer uses the 6512 CPU 1 42 which allows more accurate timing of the logic circuitry than did the 6502 see subsection 4 2 2 The 6512 requires two clock signals at MOS voltage levels in all other respects it functions in the same way as the 6502 The computer clocks are derived from 16MHz crystal controlled oscillator circuit and half of IC26 and divider circuitry in the video processor ULA IC53 The 6512 access
30. 3 1 26 131 0742 004 741504 TTL 14 0 3 1 24 132 0742 008 741508 TTL 14 0 3 1 I043 133 0742 010 741 510 TTL 14 0 3 1 48 134 0742 020 741520 TTL 14 0 3 1 40 135 0742 030 741530 TTL 14 0 3 2 1C22 41 136 0742 032 IC 74LS32 TTL 14 0 3 1 IC23 137 0741 074 74574 14 0 3 1 IC31 138 0742 074 741574 TTL 14 0 3 1 69 139 0742 086 741 686 TTL 14 0 3 2 IC63 83 140 0742 109 7415109 16 0 3 1 IC2S 141 0742 123 IC 741 5123 TTL 16 0 3 1 IC88 142 0742 132 IC 74LS132 TTL 14 0 3 1 IC70 143 0742 138 IC 7415138 TTL 16 0 3 2 IC21 46 144 0742 139 QiC 74LS139 TTL 16 0 3 2 1C28 39 145 0742 163 IC 7415163 TTL 16 0 3 2 18 45 146 0742 174 7415174 16 0 3 1 17 147 0742 244 7415244 20 0 3 4 105 6 13 80 148 0742 5 7415245 TTL 20 0 3 3 1C12 14 49 149 0742 253 7415253 TTL 16 0 3 4 IC72 75 150 0742 257 7415257 16 0 3 2 IC50 51 151 0742 259 iC 74LS259 TTL 16 0 3 i ic30 152 0742 273 IC 7418273 TTL 20 0 3 1 IC54 153 0742 283 IC 74LS283 TTL 16 0 3 1 76 154 0742 374 IC 7415374 20 0 3 2 11 32 155 156 0739 120 8815120 65423 RCVR 1 IC94 157 0770 319 IC LM319 DUAL COMP 1 Ic92 158 0770 324 IC LM324 QUAD OP AMP 2 IC47 89 159 0770 386 IC LM386 AUDIO AMP 1 IC77 160 0733 691 3691 RS422 423 DRVR 1 IC95 ITEM PART NO DESCRIPTION QTY REMARKS ISS 1 1 2 3 01
31. 6 Data out phase allows data to be transferred from initiator to target The target deasserts MSG C D and I O Data in phase allows data to be transferred from target to initiator The target asserts I O and deasserts MSG and Message out phase not used by the system available for future expansion Message in phase allows the target to send a message byte to notify completion of a eommand 6 5 4 The reset condition The reset eondition is caused by the assertion of RST and immediately clears the bus and resets the system Regardless of the prior bus phase the bus resets to the bus free phase The Winehester controller reads the drive s parameters off the dise Reset ean oceur at any time and takes precedence over all other phases and eonditions In praetiee it oeeurs on power up or when the BREAK key is pressed 6 5 5 The ST 412 disc interface connector pinouts J2 and JO The dise controller board communicates with the Winehester dise via two eonnectors J2 earries control information and JO carries data J I is not used in this implementation but is electrically identieal to JO 112 ACW SERVICE MANUAL Issue OV OV OV OV OV DRIVE ECTE ERVE ERVE ERVE ERVE MFM WRI DATA MFM READ DATA
32. 615 Step rate code 2 RWCC z 128 Landing zone 49 Format Drive 0 ID IF the drive parameters are CORRECT and agree with the Service card then to the question Change drive number only Y N type Y RTN and to the question Format drive number type 0 RTN 12 1F the drive parameters arc INCORRECT then to the question Change drive number only Y N type N RTN and enter the correct parameters Recheck by using option C again 13 Return to the command option menu 14 Seleet option T Type defect list this will list the current defeet list contained on the drive check that this is the same as recorded on the Service card Any additional defects in the list should be recorded on the Service card Two alternate methods are available for adding defeets to the list these are command options A Add defects as sector number and B Add defeets as Cylinder Head Byte Option 13 is normally used as this is the format most manufacturers record defects Option A is used to add defective sectors reported by the ADFS filing system which used this format 15 Format the Winchester using command option F Format To the question Do You really want to format drive 0 reply YES RTN only if this is the case 16 To the question Fill byte Return for default type RTN Formatting then begins This takes Approx 2 min and is followed by verification whieh takes approx 4 mins If a NEW defect is found on verification the foll
33. ACW s video monitor generates potentially dangerous high voltages These voltages can remain within the monitor circuits for several hours after the mains supply has been disconnected OBSERVE FULL SAFETY PRECAUTIONS WHENEVER THE UPPER PLASTIC CASE OF THE ACW HAS BEEN REMOVED DISCONNECT THE ACW AND ALL PERIPHERAL EQUIPMENT FROM THE MAINS SUPPLY UNDER NO CIRCUMSTANCES SHOULD AN UNCASED MACHINE BE LEFT UNATTENDED IN THE PRESENCE OF UNQUALIFIED PERSONNEL When working on the ACW it is important to ensure that the surrounding surfaces are dry and isolated from earth Avoid contact with any metal objects which may be earthed such as piping or heating equipment 12 ACW SERVICE MANUAL Issue 1 Assembly Packaging and Installation 2 3 2 Access to components The upper case assembly is plastic and is held in place by two lugs at the front of the machine which cannot be seen when the case is in place and two plastic case clips at the rear Each rear clip is covered by a metal safety clips Removing the Top Case Refer to Figure 2 3 2 a amp b 1 Remove any floppy disc from the machine and move the floppy disc lever to the horizontal position 2 Unscrew the two Phillips headed screws holding the rear metal safety clips remove and store the clips and screws 3 Unhook the two plastic case clips by pulling the bottom of the clips away from the case and unhook the top of the clips from the case top DO NOT ATTEMPT TO SEPARATE THE BEZEL
34. Advanced User Guide for the BBC Micro Bray Dickens and Holmes Cambridge Mieroeomputer Centre 1983 ACW SERVICE MANUAL Issue 1 135 Appendix E Glossary ACK ACIA ADC ADLC ADSR ASCII BASIC BBC BNC 1 2 5 1 2 CPU CR CRT CRTC CSYNC CTS CUTS DIN DRAM EPROM FIT FDC IC ID 1DC ACKnowledge line on the printer port Asynchronous Communications Interface Adaptor serial to parallel and parallel to serial converter 6850 Analogue to Digital Converter Advanced Data Link Controller ECONET control 1C 68B54 Attack Decay Sustain Release defining the envelope of a sound American Standard Code for Information Interchange binary code for representing alphanumerie characters Beginners All purpose Symbolic Instruction Code British Broadcasting Corporation Bayonet Neill Concelman the type of bayonet connector used for the video output Control lines associated with the PA port on a VIA Column Address Strobe control line for the DRAM Control lines associated with the PB port on a VIA Central Processor Unit 6512 Capacitor Resistor network Cathode Ray Tube Cathode Ray Tube Controller IC 6845 Composite SYNChronisation pulse train for video TV display Clear To Send control input on the RS423 port Computer Users Tape Standard European standard connector family used for the cassette socket RGB socket etc Dynamic Random Access Memory Erasable Programmable Read Only Memory F
35. EPROMsS and so splits these devices into two 16Kbyte pages 7455138 3 to 8 line decoder This decoder is enabled by the NPG signal from the PAL IC36 When enabled the decoder selects one of the ROM sockets according to the code held in IC45 Each enable output is active for 2 paged ROM IDs as the decoder uses the latched values of D1 to D3 S13 is used to select the page number for the language half of IC71 normally BASIC II S13 North selects page 0 1 South selects page 14 15 LM324 Quad operational amplifier The four parts of this IC are used to filter and amplify the speech and sound signals before they reach the volume control 1 o p pin 1 is the final filter stage nominal bandwidth of 7kHz 2 o p pin 7 is the speech audio filter stage approximately 7kHz bandwidth 3 o p pin 8 is the summing stage mixes sound speech speech envelope and user audio inputs into one channel 4 o p pin 14 extracts the sound channel envelope The op amp inverts the sound signal and charges C15 through D4 R34 discharges C15 slowly so C15 holds the sound envelope voltage inverted When the envelope is added to the sound audio the resulting signal is AC that is symmetric about OV ACW SERVICE MANUAL Issue 1 1045 49 T O Processor board 741 510 Triple 3 input NAND 1 o p pins 6 and 8 are part of the hardware scroll wrap around logic With parts of IC19 they decode the screen size code CO and from IC30 to driv
36. FROM THE UPPER CASE IT IS FIXED 4 Pull the bottom edge of the black front plastic bezel away from the lower edge of the disc drives so that it sits on the front face of the disc drives just below the floppy disc lever 5 Separate the case at the rear and gently raise the upper case vertically sliding the bezel front gently over the floppy disc lever 6 The rear fan should now be adjacent to the internal rear upper bracket so that by gentle movement the fan will slide past the rear cross member The fan can be viewed through the front VDU aperture 7 DISCONNECT THE FAN POWER LEAD AT THE REAR BY SQUEEZING THE MATING PLUG CLIP 8 Keep the upper case level and remove it from the machine On each side tray there are two quarter turn captive screws which hold the side trays to the main chassis Towards the rear of the metal chassis are two more that hold down the main chassis which is pivoted at the front See Figure 2 3 2 c ACW SERVICE MANUAL Issue 1 13 Chapter 2 Figure 2 3 2 a 2 3 2 b 14 SERVICE MANUAL Issue 1 Assembly Packaging and Installation Figure 2 3 2 c 1 VOU Cradle Disc Drive PCB Tray Processor Tray 015 SS Scissors Bolts RC Rear Clip RE QTS Quarter Turn Screw ACW SERVICE MANUAL Issue 1 15 Chapter 2 To lower a side trays 1 Using a large flat bladed screwdriver undo the two screws that hold down the tray to
37. I O circuit is faulty 4 7 3 Power supply With the power supply turned off unplug the three red 5 leads and the single purple 5V lead from the PCB Set the multimeter to a 10A DC scale and connect it between one of the connectors on the PCB marked VCC 45V and all three red wires together Turn on the power supply just long enough to measure the current any length of time may heat up the PCB tracks excessively in the event of a fault The board should draw from 1 5 to 2 2A depending on its upgrade state Repeat the test for each of the three 5V connectors on the in turn Results if the current at any one connector is zero or very low then look for a fault in the loom a faulty connector or broken PCB track If all results are zero then there is either a short circuit and the power supply has cut out likely or the whole power network has gone open circuit unlikely This can be checked by measuring the 5V voltage across the board Zero voltage means short circuit 5V means open circuit Replace all the power supply leads in their correct positions red to VCC black to and the purple lead to 5V As a final check measure the voltage across the power supply pins of a few ICs around the board and check that it is 5v 1 5 4 7 4 Oscillator and divider circuitry Using the oscilloscope check that 8 4MHz 2 1MHz are available from pins 7 6 5 and 4 respectively of the video processor IC53
38. JMP b 80 90 CALL a Test pin 11 1C10 with a scope and check that the waveform is not stuck either high or low It should look like the one shown in figure 6 9 2 a Pin 9 1C10 should be logic 0 Now run the following program 120 ACW SERVICE MANUAL Issue 1 Winchester and Floppy Disc Systems 0 DIM P 10 0 0 a 0 LDA 1 D 5 6 5 0 STA amp FC43 0 JMP b 0 0 CALL a and 9 1C10 should now logie 1 6 9 3 Handshaking To test the SEL BSY handshake use the following program 10 DIM P 20 LDA 1 STA amp FC40 STA amp FC42 LDA amp 41 b RTS 120 PRINT USR a AND amp FF 4 C N CO CO CO Xo uL ia o noo oo Press the BREAK key followed by OLD and RUN the program The LED on the dise controller board should illuminate and the result 2 should be printed on the screen after the assembler listing The result is the contents of the status register and BSY is bit D1 which eorresponds to 2 If nothing happens and the program is typed in correctly then there is either a loose connection or a fault in the disc controller board The system can be deseleeted by pressing BREAK The REQ ACK handshake operates only during data transfer If the hardware for this handshake is faulty then there can be no data transfer 6 9 4 Bus lines When the buses are not being asserted either by the SCS11 interfaee or
39. JW CHNG AMRSO010 ECOSOO18 ECO E117 ECO E226 TITLE ACW 443 FINAL ASSEMBLY COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0020 233 SHEET 1 of 4 CHERRY HINTON CAMBS PARTS LIST ACORN COMPUTERS LTD ME DEC ERI DE NR IND ur GADOAO CE a Mc M a FC DESCRIPTION REMARKS 41 2201 232 USER PORT CABLE ASSY 1 42 0201 453 PSU DIST PCB C FORM 1 43 0201 900 CPU REAR PANEL 1 44 2201 164 Mbyte PROCESSOR RIBN ASSY 1 45 0201 457 TEE GUIDE BLOC 1 46 0201 458 SPECIAL WASHER 1 47 0201 459 SLIP DISC 10 48 0201 460 STOP RING 1 49 0201 471 MAINS CABLE ASSY 1 50 0201 473 PRINTER RIBBON CABLE ASSY i 51 0201 405 SPEAKER VOLUME CABLE 1 52 0201 472 KEYBOARD RIBBON ASSY I 53 0201 787 BRKT LH EXPANSION TRAY 1 54 0201 861 DIST CONT PCB C FORM 1 55 0201 865 MOULDED CABLE ASSY 5A 1 56 0805 900 MAINS SWITCH 1 57 0880 024 CABLE GLANG 1 58 0815 223 FUSE 3A15 20x5mmd HBC 1 59 0815 900 FUSE HOLDER 1 60 0815 901 FUSE SHROUD 1 61 0884 120 COMPRESSION RING 2 62 0201 778 CLIP 9 63 0201 779 SCREW M5 MODIFIED 2 64 0882 121 SCW M3x6 PAN HD POSI 14 65 0882 124 SCW M3x12 PAN HD POSI 9 66 0882 155 SCW M5x16 PAN HD POSI 6 67 0882 153 SCW
40. L7FFFE IFFFFE 27FFFE FFFFE 37FFFE sero sFx5 4 i 1YPE MEMRANG 2 0 gt eS DE 3 TEER E TEE see mc a TEPE Goel ees E gt ej gt ZETA EEE j gt ibe ee pk TIE Eos TEA SENA EEE E 23 eral cem zee rre reca orm male laa eae E yp op s EEE EU UE TRO ICH HIC E DE BE eg EDE de I EETA EET NE IEXC REE reall exces cera 32016 2ND PROCESSOR ao 4J 2855 Ix n nr ge B hebr iE i z d T TLS 57 a 5 i s 5 rm etin feat E Ed J er M ral ar ife im Bin TR GSE dee ea raw no PCB circuit diagram TS mu Jar t 16 8 SD ss pi feos E 2 AX 12121222 Ter T La ase tee paren F v is 20 8159 19 N
41. M bytes 3 Walking 16 bit memory test 2 M bytes 4 Walking 16 bit memory test 2 5 M bytes 5 Walking 16 bit memory test 3 M bytes 6 Walking 16 bit memory test 3 5 M bytes 7 Walking 16 bit memory test 4 M bytes 8 Refresh test 9 Floating Point Unit FPU test Select Table 10 32000 Memory Test Program 104 ACW SERVICE MANUAL Issue 1 6 Winchester and Floppy Disc Systems 6 1 Introduction 20Mbyte Winchester half height disc unit and a doubly sided 80 track 5 25 floopy disc unit are fitted to the 443 The use of the disc drives is introduced in the ACW Welcome Guide supplied with the machine and details for formatting both the floppy discs and the Winchester disc are given in the appendix To ensure trouble free operation of the disc drives the ACW should not be exposed to excessive heat moisture direct sunlight or very dusty conditions WARNING A number of components within the left hand tray of the ACW ADAPTEC PCB and Host Adaptor PCB are STATIC SENSITIVE It is possible that these components may be damaged if subjected to a static discharge To minimise this risk please ensure that the ACW is isolated from the mains power supply before attempting to access the components tray Avoid contact with the components of the PCBs except where necessary to perform the exchange of faulty components 6 2 Floppy Disc Drive The floppy disc unit is not a servicable item and in the event of its failure it should be r
42. MANUAL Issue 1 9 Chapter 1 10 HELP HELP HELP HELP HELP DFS DNFS ADFS DDFS ACW SERVICE MANUAL Issue 1 2 Assembly Packaging and Installation 2 Packaging ACW models are packaged in a single cardboard box within moulded polystyrene foam and air bubble cushioning It is recommended that the packing materials be retained if there is any likelyhood of the ACW computer being transported by third party carriers The box contains the following User registration card guarantee card service information card Instruction sheet Panos welcome disc and ACW user guide packed in a polythene bag e utilities disc terminal manual and BBC BASIC IV reference manual packed a polythene bag e Function keycard booklet Processor VDU unit with integral mains lead and plug e The keyboard unit with integral coiled lead fitted with a D type keyboard connector Shipping IMPORTANT Before switching off prior to transporting the ACW the Winchester disc head mechanisim must be Parked as described in section 6 3 and the preface Protecting the Winchester Disc Prior to repacking the floppy disc drive should be protected by refitting the cardboard insert if it is available Precautions for shipping involve the repacking of the main unit and the keyboard in the specially moulded polystyrene side pieces In the absence of the original packing materials the ACW should be securely packed in a rigid polystyrene h
43. Machine Operating System and a fast BASIC interpreter The interpreter includes a 6502 6512 assembler which enables BASIC statements to be freely mixed with 6502 6512 assembly language Code generated using the BASIC assembler can be run on a machine with a 6512 microprocessor or a machine with a 6502 microprocessor Up to five 32K sideways ROMs may be plugged into the machine at any time having the effect of ten 16K ROM slots eleven including BASIC These ten 16K ROM slots are paged and may include Pascal word processing computer aided design software disc and ECONET and WINCHESTER filing systems or TELETEXT acquisition software The full colour Teletext display of 40 characters by 25 lines known as mode 7 has character rounding with double height flashing coloured background and text plus pixel graphics all to the Teletext standard The non Teletext display modes modes 0 to 6 provide user definable characters in addition to the standard upper and lower case alpha numeric font In these modes graphics may be mixed freely with text ACW SERVICE MANUAL Issue I 33 Chapter 4 The following screen modes are available ode 0 Mode 128 640 x 256 2 colour graphics and 80 x 32 text ode 1 Mode 129 320 x 256 4 colour graphics and 40 x 32 text ode 2 Mode 130 160 x 256 16 colour graphics and 20 x 32 text ode 3 Mode 131 80 x 25 2 colour text only ode 4 Mode 132 320 x 256 2 colour graphics and 40 x 32 text ode 5 Mode 133 160 x 256 4
44. Prise the PCB and insulation sheet from its four nylon PCB support pillars Installation is in reverse order 2 4 8 Disc drives To service the disc drives it is recommended that the cradle assembly is pivotted beyond its intermediate position To do this ensure that a piece of soft material such as a block of sponge rubber 150mm thick is placed in front of the ACW to act as a supporting bed for the CRT as it swings over into an upright position A 6mm spanner box spanner or small adjustable wrench will be needed to unscrew the self locking nut from the middle of each stay Keep the two nuts and the two nylon washers in a safe place ready for re assembly Each drive can be removed from the ACW individually WARNINGS The Winchester drive must be carefully removed and installed Do not subject it to rough handling or vibration The Winchester drive contains STATIC SENSITIVE components observe normal precautions for handling such devices Winchester disc drive 1 Disconnect both ribbon cables from the drive Disconnect the power lead at the disc drive end 2 The Winchester disc drive is held down to the disc tray by four 6 32 UNC 3 8 screws Remove these taking care to support the drive from the front to prevent it falling through the ACW SERVICE MANUAL Issue 1 21 Chapter 2 front aperture 3 Keep these screws seperate from any others removed as they are non standard 4 Still supporting the drive from the front parti
45. RAM Any code executing from sideways RAM between amp A000 amp AFFF will access the shadow RAM if selected when the operand address is between amp 3000 amp 7FFF This special attribute is not available to any other sideways memory ROM or RAM RAM circuitry The 64K installed RAM is provided by eight 64K by 1 dynamic memory devices ICs 55 56 60 61 64 65 66 and 67 Figure 4 2 8 shows the RAM timing diagram ACW SERVICE MANUAL Issue 1 45 Chapter 4 5 Figure 4 2 8 RAM timing diagram 2E CAS cpu CPU The RAM control circuit is designed to work with either 128 or 256 refresh cycle DRAM s refresh being provided by the 6845 CRTC IC78 in conjunction with two ex OR gates of IC63 and an AND gate of IC34 The RAM is accessed at 4MHz the CPU and VDU each having 2MHz access The address multiplexers for the VDU cycle are ICs 72 73 74 and 75 Various combinations of the inputs of these ICs are used depending on the screen mode in use In particular TELETEXT mode 7 with its own character generator IC59 is markedly different from the other seven bit mapped modes 0 6 The address multiplexers for the CPU cycle are ICs 50 and 51 RAM is working being addressed and strobed the whole time both during CPU and VDU phases even when not required except for the purpose of refresh But data to or from the RAM is only available to the CPU when the data buffer 49 is enabled This occurs when any input t
46. Results if these signals are not present then check that 16MHz is available at pin 8 IC53 If it is then replace IC53 If not then check the crystal controlled oscillator circuit formed by half of IC26 and XI Check that the CPU has two non overlapping 2MHz clock inputs on pins 3 phil and 37 phi2 of IC42 as shown in figure 1 Check that 1E is available at pin 6 1C25 This signal should be phase shifted in relation to 1M at pin 4 IC53 as shown in Figure 4 7 4 62 ACW SERVICE MANUAL Issue 1 O Processor board Figure 4 7 4 1M 1E 1M 1E 4 7 5 CPU Test pin 40 IC42 reset pin and check that it is high Press the BREAK key and make sure that pin 40 goes low for a reset and then high again on release Results if pin 40 is stuck low then check for a short circuit on the main PCB the keyboard BREAK key keyboard connectors or the resistors and capacitors of the 555 reset circuitry If it is stuck high then check the 555 timer circuit IC43 the keyboard ribbon cable and connectors and the BREAK key itself Check that NIRQ pin 4 and R NW pin 34 are wobbling If not then test SYNC pin 7 If SYNC is stuck either high or low then the processor is stalled Results if CPU is stalled then check that ROMs are plugged in their sockets correctly Check for address and data bus short or open circuit 4 7 6 ROM If ROM circuitry is not functioning then the CPU will not operate Check that all ROMs are inserted with all the pins c
47. The IC can scroll the display by responding to a change in the value of the display start address A programmable cursor and the horizontal and vertical sync pulses are also generated by this IC Included in the IC is an address latch which is used with the light pen input to save the character address at the time of a trigger event on pin 3 of the IC The device is accessed at IMHz by the CPU at amp FEO00 1 character clock of 1 or 2MHz is supplied by the VIDPROC depending on the VDU mode 74574 Dual schottky D type flip flop The two parts of this IC are used in a ring counter which is clocked at four times the colour subcarrier frequency 17 734475 2 Each D type generates an output at the colour subcarrier frequency 4 43361875MHz The two signals in phase quadrature 90 degrees apart and form the master signals for the PAL chroma encoding logic The signal on pin 8 is set to 4 4336MHz 100Hz by adjustment of VC1 741 5244 Octal 3 state buffer The 8 buffers in this IC arc used to drive the CPU data bus with the ECONET station ID The buffers are enabled when the CPU reads address amp FE18 A write to amp FE18 will result in a data bus drive conflict and should not be attempted Link S23 sets the station ID Each link has a binary value ACW SERVICE MANUAL Issue 1 1C81 IC82 IC83 1C84 IC85 I O Processor board with the largest 128 decimal at the North end of the row A broken link shunt removed ad
48. The output NBOOTING is set low by a reset from the TUBE NPRST and reset high by NWR NBOOTING low forces the EPROM chip select NCS active causing the EPROM to respond ACW SERVICE MANUAL Issue 1 32016 Processor to all addresses ie it replicates at 16k word intervals 5 3 3 Address map general The address map is not fully decoded which means that some devices ie the TUBE could be addressed at more than one location The locations that software must use are described below 5 3 4 Address map during Booting The EPROMSs replicate from address Hex 000000 to Hex FFFFFF at 32k byte intervals but Pandora and other software should only addresses the EPROMS at Hex 000000 one instruction and Hex F00000 normal base address 5 3 5 Address map after Booting After booting software must address RAM Hex 000000 to Hex 3FFFFF EPROM Hex F00000 to Hex F3FFFF Configuration Switches Hex F90000 TUBE TRI Status Hex FFFFFO Data Hex FFFFF2 TR2 Status Hex FFFFF4 TR2 Data Hex FFFFF6 TR3 Status Hex FFFFF8 TR3 Data Hex FFFFFA TR4 Status Hex FFFFFC TR4 Data Hex FFFFFE Except during Booting no hardware exists between addresses Hex 400000 and Hex EFFFFF 4 and 15 M bytes This space is reserved by Acorn for Hex 400000 Hex 7FFFFF 4 12 M bytes RAM Expansion Hex 800000 Hex EFFFFF 12 15 M bytes I O Expansion ACW SERVICE MANUAL Issue 1 91 Chapter 5 5 3 6 Address decoding Logic 92 Multiplexed
49. This device generates 4 enable signals 1 A14 and A15 are decoded to form NOS which is low when A14 AND 15 are logic 1 2 A14 dow AND 15 high arc decoded to form NPG the current sideways ROM enable If sideways RAM is enabled SRAM 1 then NPG is forced high while 12 OR A13 is low 3 12 low OR AI3 AND A14 low AND 15 high are decoded The address decoded is ANDed with the sideways RAM enable bit SRAM to form NPGRAM NotPGRAM will be low active if sideways RAM enable SRAM is logic 1 and the current address is between amp 8000 and amp AFFF 4 NPGLD is formed by decoding NROMSEL and A2 NotPGLD is low active when NROMSEL is low AND A2 is low The PAL contains two addressable 1 bit latches write only 1 VDUSEL is addressed at amp FE34 and latches the value of D7 VDUSEL is the hardware SHADOW mode switch Logic 0 is normal mode which emulates the standard model B microcomputer VDU operation 76 ACW SERVICE Issue 1 IC37 IC38 IC39 1C40 1C41 T O Processor board 2 SRAM is addressed at amp FE30 SRAM is an extension to the ROM select latch and holds the value of D7 This bit is the sideways RAM select flag The signal is labelled Qh in the PAL spec 0201 880 The PAL monitors the state of VDUSEL to determine if a shadow display mode is active When VDUSEL is high shadow active the PAL checks the address of each CPU opcode fetch If the opcode address is
50. Winchester mechanisim winds back in the heads Transportation Before switching off prior to transporting the ACW the Winchester disc head mechanisim must be Parked as described above in the section Protecting the Winchester Disc If you need to transport the ACW pack the original protective expanded polystyrene around the sides of the machine keeping the ACW in the upright position Lower the combined package carefully into the cardboard box in which the machine was supplied again making sure that the ACW remains upright The Service Card supplied with each unit and specific to that unit should always travel with it User Registration User Registration Card is supplied with the hardware It is in your interest to complete and return the card Please notify Acorn Computers Limited if this card is missing 4 ACW SERVICE MANUAL 1 Introduction 1 1 Function of this manual This manual is intended to provide the information required to diagnose and repair faults on the Acorn Cambridge Workstation ACW series microcomputers It gives the complete overview of the ACW system for Acorn dealers and service engineers It is assumed that the reader is familiar with the ACW operating system and has access to the user guide documentation and utility software including the supplied users test routines 1 2 Conventions observed in this guide The following conventions are observed 1 BREAK RETURN ESCAPE SHIFT and CTRL signif
51. about 4 5s and is triggered by the inverted ECONET controller NRTS signal which previously directly enabled the line driver While triggered the monostable enables the line driver IC91 At the end of a transmission the monostable is cleared Normally the monostable output pin 4 appears logically to follow the RTS signal The real purpose of this circuit is to stop a micro from permanently driving the ECONET line as a result of say a user program crash 2 o p pins 4 13 this monostable is triggered by the received clock from an ECONET line While the clock is present the monostable remains triggered pin 4 low If the clock is not present or is very slow then pin 4 will oscillate or stay set The state of the monostable can be checked directly by the ECONET tiling system testing the 68854 NDCD signal LM324 Quad operational amplifier 1 o p pins 1 8 14 give two stages of filtering and one limiting amplifier stage for the received cassette audio signal When the audio is present a 1 2 volt approx square wave will be presented to the SERPROC 2 o p pin 7 buffers the audio output to the cassette recorder 741500 Quad two input NAND o p pins 3 6 8 11 are four gates which arc selectively enabled to drive the colour subcarrier resistor mixing matrix to generate the colour subcarrier phase for the current display colour Li C40 and R113 in parallel with R114 form a simple low band pass filter tuned to the colour subcarri
52. addresses from the processor or memory manager ADO AD15 are latched into 1C8 and 1C9 and remain stable throughout a bus cycle Address lines A16 to A23 do not require latching as they are not multiplexed The data bus DO D15 from the DRAM array is buffered onto the processor bus ADO AD15 by two bidirectional buffers 1C12 and 1C13 74LS245 The enable signal NBE is a function of address bits A22 and A23 and only enables the bufers when A22 and A23 are both zero ie for addresses in the bottom 4 M bytes A22 and A23 are also used in the same way to enable disable NCAS to the memory chips preventing unwanted write access outside the bottom 4 M bytes Address decoding within the bottom 4 M bytes is performed by allowing NCAS to selected banks only This is performed by IC14 and IC27 and address bits A17 to A21 according to the following table With 64k 256k bit DRAMs installed A17 A19 A18 A20 A19 A21 NCAS Selected 0 0 0 CAS 0 HightLow 0 0 1 CAS 1 HightLow 0 1 0 CAS 2 HightLow 0 1 1 CAS 3 HightLow 1 0 0 CAS 4 HightLow 1 0 1 CAS 5 High Low 1 1 0 CAS 6 HightLow 1 1 1 CAS 7 HightLow The High and low byte NCAS signals are further conditioned by address bit AO and High Byte Enable NHBE NHBE is used when accessing Bytes and Words located at ODD addresses Note An ODD word requires two memory cycles The following categories apply Category 0 NCAS s enabled Even Byte 1 0 Low byte enabled
53. be addressed to Technical Enquiries ACORN Computers Limited Newmarket Road Cambridge CB5 8PD maintenance and service on the product must be carried out by ACORN Computers authorised service agents ACORN Computers can accept no liability whatsoever for any loss or damage caused by service or maintenance by unauthorised personnel This manual is intended only to assist the reader in the use of this product and therefore ACORN Computers shall not be liable for any loss or damage whatsoever arising from the use of any information or particulars in or any error or omission in this manual or any incorrect use of the product This manual is for the sole use of ACORN Computers authorised service agents and must only be used by them in connection with the product described within ACW SERVICE MANUAL Third Party Copyright Notice Some sections of this manual are copyright of MICROVITEC PLC and are subject to the following copyright notice COPYRIGHT 1986 MICROVITEC PLC The copyright in this work is vested in MICROVITEC PLC and this document is issued for the purpose only for which it is supplied No licence is implied for the use of any patent literature It must not be reproduced in whole or in part or used for tendering or manufacturing purposes except under an agreement or with the consent in writing of MICROVITEC PLC and then only on the condition that this notice is included in any such reproduction Information furnished
54. direetly from the floppy disc or they may be installed onto the Winchester disc To run the utilities from the floppy disk 1 Select the single processor mode by using the TUBE rocker switeh on the rear of the keyboard the TUBE LED on the top left of the keyboard should be OFF 2 Insert the utilities dise into the floppy drive 3 Type gt ADFS RIN gt D1R 4 RTN gt CHAIN UTILS MENU RTN 4 A menu will then appear on the screen To install the utilities The ADFS utilities can be installed on the winchester as follows 1 Start the Utilities as above 2 Seleet General Utilities type f2 3 seeond menu will appear Select dircopy type 4 Wait for the banner Logieal Copier 5 In reply to the question Source Drive type 4 RTN 6 In reply to the question Destination Drive type 0 RTN 7 Press RTN when ready 8 In reply to Please input sub directories NOT to be copied type RTN whieh will cause all files and directories to be eopied 9 In reply to the question Begin at which Entry type RTN Installation will now begin 10 Installation will be finished when the messages Copy eomplete and Press SPACE to return to menu Compacting Winchester Disc Files During a period of typieal use a large capacity Winchester disc will provide for the creation reorganisation and deletion of a great many disc files In so doing differrent parts of the disc are called into use and
55. down by four Philips screws The volume and brightness potentiometers are held in by 3 8 or M10 thin nuts and 22 ACW SERVICE MANUAL Issue 1 Assembly Packaging and Installation removal must be preceded by the removal of the fan Installation is in reverse order ACW SERVICE MANUAL Issue 1 23 24 ACW SERVICE MANUAL Issue I 3 The monitor 3 1 Introduction The ACW uses a medium resolution Microvitec Cub colour monitor which comprises of the CRT two PCBs main and High voltages are present at the CRT and associated PCBs and these voltages can be retained in the circuits for many hours after the equipment has been disconnected from the mains It is recommended that the monitor is checked for electrical safety after any repair or replacement has been carried out This chapter covers the preset adjustments and user adjustments and a circuit description 3 2 Removal and installation This is done in accordance with the instruction given in sections 2 4 2 and 2 4 3 3 3 Servicing servicing should be carried out in accordance with the instructions contained in the MICROVITEC SERVICE MANUAL Number GP0019AAO A copy of this may be obtained from the address given in the appendix The following sections should be used for reference only and if in any doubt refer to the Microvitec Manual 3 4 Adjustments 3 4 1 User adjustments The user may only make adjustments to VDU contrast using the left hand control
56. entire surface of the power supply unit where it attaches to the VDU cradle 2 4 2 Colour monitor CRT BEWARE IMPLOSION HAZARD HIGH VOLTAGES REMAIN EVEN AFTER MAINS DISCONNECTION CRT replacement should only be undertaken as a bench repair and whilst exercising extreme caution If possible enlist the help of a second person when unscrewing the CRT from the cradle Proceed strictly in the order given and refer to Figures 2 4 2 a and b 1 Remove the upper case as detailed in section 2 3 2 Leave the cradle in the normal operating position 2 Disconnect the EHT connector on the left hand side of the CRT WARNING DO NOT TOUCH THE CENTRE CLIP ACW SERVICE MANUAL Issue 1 17 Chapter 2 3 Earth the connector centre clip against the chassis metalwork to ensure that the tripler is fully discharged 4 Discharge the CRT final anode Use a long shafted screwdriver with a high voltage insulated handle rest the metal shaft on the top of the chassis and touch the tip of the shaft into the CRT final anode EHT socket from where the EHT connector was removed 5 Disconnect the CRT earth connector from the earth tag on the CRT PCB 6 Remove the CRT PCB from the CRT neck 7 Unclip and remove the 8 way scan coil plug from the main PCB 8 Unclip and remove the 6 way degausing coil plug from the main PCB 9 The CRT is secured by four 5mm bolts one at each corner of the CRT face Slacken off the two lower CRT
57. half cycle of PHII at the beginning of each bus cycle indicating a valid address is present on 0 15 For example when the CPU is executing reads there will be a pulse on ADS pin 6 of the TCU approximatly every four clock cycles The activity on the ADS pin should be checked for as it indicates that the CPU is attempting to access the outside world and is not be completly dead NDDIN This indicates to the TCU the direction of data on the data bus ie low indicates data in read hi indicates data out write Check for activity on this pin In response to NDDIN the TCU generates Read NRD Pin 3 1C4 and Write NWR Pin 4 104 Check for activity on these pins NPFS Program Flow Status This pin active low gives a pulse every time a new instruction begins execution stream of pulses on PFS pin 39 is a good indication that the processor is executing instructions If not check the reset and clock signals and if these are satisfactory then the processor is probably at fault NIRQ The maskable interrupt line is used whenever information is passed down the tube It is a bit difficult to get this line active during testing unless you have special test software to run on the 32016 and the machine is in a fit stale to run it WR RD On starting up Pandora the processor attempts to work out the memory size which is then wriWen out through the tube with a start up message this activity should be detectable by monitoring WR and RD at
58. has collapsed and the potential across the field scan coils has fallen below 25V pin 3 is switched back to and the scan cycle is resumed D Synchronisation of IC301 is achieved by feeding a positive going field sync pulse to pin 8 of IC301 HT supply for IC301 A This supply is derived via C305 C306 and VR306 with associated components R303 C301 and D301 minimising picture bounce and breathing effects Field output A The sawtooth is applied to the output stage within IC301 and the scan output is available on pin 4 The current within the coils is sampled by R323 then fed back via R317 to the virtual earth input of IC301 pin 10 ACW CERVICE MA NITAT Toona T The monitor B The gain of the output amplifier is set by the ratio of R314 and R317 The DC operating point is set by the ratio of R318 and R316 Picture geometry A CRT E W pincushion distortion is corrected by the modulation of the line deflection current in transducer T202 AC gain from the amplifying driver is used to control the amount of correction applied to the CRT 3 5 6 CRT tube base panel 1 All CRT electrodes are protected by a resistor a capacitor and a spark gap The spark gaps on all electrodes with the exception of focus are formed by a 1 2kV ring trap gap positioned within the base socket assembly The high focus voltage has a separate 10kV spark gap contained within the tube base socket 2 The CRT electrodes are separated from the video o
59. in the VDU driver code space then a temporary 1 bit flag is set in the PAL The flag remains set until an opcode outside the VDU driver code space is read While the flag is set all CPU access to memory between amp 30 X and amp 7FFF is redirected to the shadow RAM The redirection is achieved by manipulating the A15 RAM address line The RAM A15 address is generated by the PAL and is the signal CPUSEL Normally CPUSEL is the same as the CPU A15 address signal When the flag is set the PAL tests each CPU address and forces CPUSEL high if the address is in the range amp 3000 to amp 7FFF So in shadow mode the CPU will access the shadow screen RAM for VDU operations and normal RAM for all other operations VDU driver code is identified by its memory address All code between address amp C000 and amp DFFF is treated as a VDU driver Also code in the paged RAM between amp A000 and amp AFFF is treated as a VDU driver but not in paged ROM From the above it is apparent that any program code in the VDU code spaces must not address RAM between amp 3000 and amp 7FFF unless it intends to write to the shadow RAM screen TMS6100 Speech PHROM optional A serial ROM which contains the speech vocabulary data used by IC29 SN76489 Sound generator This IC contains three sound channels and one noise channel The sound pitch attack sustain decay and release are independently programmable from BASIC or machine code Control is exercised throu
60. knob positioned at the front of the ACW under the Winchester drive position 3 4 2 Factory preset adjustments Adjustments to certain presets can be made from above or below the main panel Adjustments are best made with a symetrical test pattern showing on the screen 1 Set HT VR4 IMPORTANT This is adjusted actuately at the factory to give 124V with a dark picture showing This is CRITICAL SAFETY ADJUSTMENT and should NOT be adjusted WARNING FAILURE TO COMPLY WITH THE ABOVE WILL INVALIDATE THE WARRANTY 2 Line frequency VR218 A Set free running oscillator frequency to almost the frequency of incoming line syncs B Adjust VR218 while supplying an RGB video and interrupt the mixed sync information to the line oscillator by removing the sync information on PL101 C Adjust VR218 until the picture almost stabilises then re connect sync information via PL101 as required The result should be a stable picture lock 3 Field frequency VR307 A The control of the free running field oscillator frequency is achieved by VR307 being ACW SERVICE MANUAL Issue 1 25 Chapter 3 adjusted to give a stable picture lock For an effective lock VR307 should be set to the centre of the locked picture range 4 Line Phase VR220 A VR220 controls the positioning of the video information relative to the raster in the line scan direction B Ensure that the following operations have been carried out 1 The line frequency has been set
61. level volts 3 Adjust VR921 for blue cathode black level volts 4 The voltages are 140V for the 14 inch monitor C Adjust AI voltage D Adjust VR932 until a raster is just visible 26 ACW SERVICE MANUAL Issue 1 The monitor 2 The raster colour may be neutral but it is more likely to be shaded towards the red green or blue or to a combination of any two colours 3 Establish raster colour shading as follows a Red and green yellow b Red and blue magenta c Blue and green cyan 4 Reduce the black level of the remaining one or two guns by adjusting VR906 914 VR921 or a combination until a neutral raster is acheived 5 Re adjust VR932 to just extinguish the raster 6 Input RGB and sync signals then adjust VR111 clockwise 7 If the correct white balance has not been acheived repeat this section 12 Adjust colour gain controls CAUTION Make the following adjustments using a DC coupled oscilloscope only Prepare to adjust colour gain controls 1 Disable beam current limit circuit by removing TL901 in series with CRT heaters on tube base panel 2 Provide a test pattern with peak white and blank level information on red green and blue 3 Ensure VRI11 is fully clockwise to provide maximum drive voltages to the video output stages B Adjust red green and blue gain controls 1 Adjust VR903 for red peak to peak drive volts at R926 2 Adjust VR910 for green peak to peak volts at R92
62. minimised by L204 3 Line linearity correction is provided by L203 which is damped by C217 and R230 S correction is provided by C218 4 The field timebase 25V is acheived by rectifying a negative going flyback voltage from the secondary winding of the line output transformer A fusable resistor provides CRT protection under possible fault conditions 3 5 5 Field timebase The field timebase function is carried out by IC301 The oscillator frequency is determined by VR307 R308 and C303 100uS output pulse is produced on 12 Field sawtooth is derived from the potential across C305 and C306 as they charge towards the 25 supply via resistors R304 R305 VR306 and R301 When the field scan is completed the 100uS pulse discharges C305 and C306 ready for the charging cycle to be restarted Field Linearity A A sawtooth output should exist on pin I of IC301 Field flyback A In order to achieve a short field flyback time a supply voltage which 15 larger that that required during the scan must be applied to the field deflector coils during the flyback period This is made possible by the use of a separate field flyback generator within IC301 B The main HT supply for IC301 is suppled to pin 5 via D302 During flyback the generator doubles the supply on pin 5 and the potential on pin 3 is switched from OV during scan to 25V during flyback D302 isolates pin 5 from the 25V supply When the deflection coil field
63. mounting bolts until they are almost at the end of their threads Slacken off the two top bolts until they are accessible between finger and thumb 10 Whilst supporting the bottom of the CRT face with one hand remove the lower bolts and then the top two bolts and withdraw the CRT carefully from the front of the cradle assembly 11 Retain the degausing coil and the earth braid assembly for fitting to the new CRT Assembly is in reverse order Notes 1 Make sure the tube is the correct way up 2 As a guide to centralising the CRT within the chassis the four corner mounting bracket washers should be aligned to the rounded part of the brackets IMPORTANT Check that the CRT earth to CRT PCB lead is connected Damage to the monitor can occur if this is not fitted 2 4 3 Colour monitor PCB BEWARE OF HIGH VOLTAGES EVEN AFTER MAINS DISCONNECTION Access to the monitor PCB is difficult unless the CRT has been removed as described above The following assumes that the CRT has NOT been removed and so can be undertaken on an installed ACW Proceed strictly in the order given and refer to Figures 2 4 2 a and b 1 Remove the upper case as detailed in section 2 3 2 Leave the cradle in the normal operating position 2 Unplug the 3 wire 240V power the contrast control and video cable connectors from the main PCB 3 Disconnect the EHT connector on the left hand side of the CRT WARNING DO NOT TOUCH THE CENTRE CLIP 4 Earth the EHT co
64. produce an output when that column is strobed and this will interrupt the CPU through line CA2 pin 39 of 1C20 on the main computer board The interrupt tells the computer to enter the key reading software In order to discover which key was pressed the CPU loads directly into the 74LS163 the address of a key matrix column allowing it to interrogate each column in turn Also the CPU drives the 74LS251 data selector IC2 with the row of a single key on the selected column In this way the processor can interrogate each individual key in turn until it discovers which one was depressed and caused the interrupt Once read the keyboard assumes its free running mode The TUBE switch either permanently resets the TUBE 32016 OFF or connects it to the I O processor reset line 32016 ON The Pull up resistor Possibly R16 depending on the PCB issue number connected to one side of the break key and pin 2 of the keyboard cable NRST should NOT be fitted if the I O processor does not come out of reset on first switching on the machine 4 3 Internal Clock and Timer 56 The I O Processor contains both an internal clock and an internal timer which measures time in units of 0 01 seconds centi seconds The clock and timer run continuously while the ACW is powered on a hard reset i e CTRL BREAK or mains power switch will reset the clock and times to zero Both the clock and the timer values arc held as binary numbers in five consecutive
65. range of numbers on each channel is sufficient to show that the converter is working If this experiment does not work then check that the ADC IC can be accessed by running the following program 10 adc amp FECO 20 DIM P 100 30 40 start 50 LDA adc 60 JMP start 70 80 CALL start Check that pin 23 IC84 is active If not then check the address decoding and connections from pin 9 IC21 ACW SERVICE MANUAL Issue 1 71 Chapter 4 Press CTRL BREAK and look at the signal pin 28 IC84 This line signals the end of a conversion and should be pulsing low approximately once every 10ms If it is but there is still a problem with A to D conversion then check that the EOC signal is reaching pin 18 IC20 4 7 17 ECONET ECONET can only be serviced properly by ECONET service centres who will have the necessary test equipment to check the system thoroughly However there are a few simple things which can be checked without the test equipment Check that all the ECONET components arc installed and have been fitted correctly Check that NNMI on the CPU pin 6 IC42 is not being held low To display the station number type SHIFT Ci BREAK together If the system will not give a correct ID number then use the shunts 523 to find which track is broken or shorting 4 8 IC description IC2 IC3 IC4 IC5 106 1C7 72 7ALS123 Dual monostable Required only by 8271 disc interface NOT F
66. signals and the request to send output RTS and clear to send input CTS signals are interfaced by ICs 94 and 95 which translate between TTL and standard RS423 signal ACW SERVICE MANUAL Issue 1 I O Processor board levels 5V and 5V RS423 signals are compatible with the RS232 signals common in computer related equipment Selection of the cassette or RS423 for input and output is by bit 6 of the serial processor control register bit 7 1s for cassette motor control Bits to 2 control the transmit bit rate while bits 3 to 5 set the RS423 receive bit rate External Connections Table 6 shows how the ACW should be connected to the 25 way D type connector with which most serial interfaces are provided The ACW is classed at Digital Computer Equipment DCE so can easily be connected to for example plotters which are usually classed as Digital Terminal Equipment DTE Connection to other DCE classed systems such as a second ACW or main frame computer will require a crossed cable The standard is open to interpretation so some experimenting may be required to find the correct connections 1 ACW 5 pin Domino Din Canon 25 way connector Function Pin Function Pin Data in connect to Transmitted data 2 Data B 2 connect to Received data 3 CTS D 4 connect to Request to send 4 RTS E 5 connect to Clear to send 5 GND OV Ca connect to Signal ground 7 Table 6 Connections for RS423 ACW to DTE The signal levels conform to the sp
67. signals from disc control circuitry into the active low signals required by the disc drive Also gives increased signal drive capability 1C9 741 500 Quad 2 input NAND Required only by 8271 disc interface NOT FITTED ON ACW I O PROCESSOR IC10 6522 Printer user VIA This is a versatile interface adapter VIA IC Half of it A provides a CENTRONICS compatible printer interface buffered via IC5 Handshaking is carried out via CA2 strobe output buffered in IC13 and CAI ACK input The B half is connected directly to PL10 and is called the User Port 74193274 Octal latch This latches the low address signals 0 to A7 These are used by IMHz peripherals The main function of the latch is to buffer the lines but it also synchronises the lines so that changes can occur only while E is inactive low The latch is clocked by 1M see also IC32 1C12 741 5245 Octal bi directional buffer Used to buffer the 8 data lines from the data bus to the IMHz expansion bus Data direction is controlled by the de glitched R NW signal 1C13 7ALS244 Octal buffer Used to buffer five address lines 0 4 R NW and N2M for the TUBE interface Also buffers the strobe handshake line for the CENTRONICS compatible printer interface 4 741 5245 Octal bi directional buffer Used to buffer 8 data lines from the data bus to the TUBE interface Is enabled only when TUBE is addressed IC15 8271 FM floppy disc controller Required only by 82
68. so this is unlikley to be the cause of a fault reported while testing small amoumts of memory ie 1 5M byte refresh test program option is provided ACW SERVICE MANUAL Issue 1 149 A ppendix 150 a Faulty DRAM Error Error Error Error Error Error Error b Faulty PCB Error Error Error Error Error Error Error Error Error Error Error Error addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr addr MEMORY TEST PROGRAM FAULT EXAMPLES 00087B4 0008 4 00097B4 000 4 000 4 0000734 000 4 00 02 04 06 08 0A 0C 0 012 100014 00100016 CO CX XXX CY CX CC XO OO OO C lt gt OOO amp D 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 even Bit D9 Written Written Written Written Written Written Written Wri Wri Wri Wri Wri Wri Wri Wri Wri ten ten ten ten ten ten ten ten ten Written Written Written t Gh CR eee FE t ct addresses Faulty address line Error Error Error Error Error Error Error Error Error Error Error Error addr addr addr addr addr addr addr addr addr addr addr addr 00 02 04 06 08 OA OC 0 012 10
69. the chassis a quarter turn anti clockwise will cause them to spring out and release the tray 2 The tray can now be eased upwards a few inches and then turned on its lower edge hinge downwards into a horizonal position The right hand tray contains the 32016 processor board while the left hand tray contains the Winchester drive interface boards and the optional mouse controller board 3 If necessary the trays may be removed from the ACW by easing the hinge pins out of the main chassis Access to the bottom of the ACW 1 BOTH side trays must be lowered as described above 2 Both remaining quarter turn screws should be loosened 3 The rear of the cradle assembly should be moved steadily upwards until two metal stays the scissors mechanism are seen to unfold The stays should be swung fully open and this will raise the cradle assembly further 4 Allow the stays to travel past their fully open position so that they become locked into the support position The cradle assembly is now safely supported in its intermediate open position To open it further the scissors bolts of the two stays must be unscrewed This need only be done when major servicing such as whole unit replacements is being performed on the 6512A processor board the Winchester drive and the floppy disc drive 2 3 3 Re assembling the ACW 1 Before closing the upper unit ensure that the ribbon and power cables will not be trapped when the unit closes Push th
70. the colour subcarrier reference needed to synthesise the colour subcarrier for a particular colour 2 o p pin 6 see above o p pin 3 3 o p pin 8 is used to select the polarity of the CSYNC signal on the RGB connector SK3 With link S27 set North positvc syncs are generated S27 South the normal setting gives negative syncs 4 o p pin 11 this gate is driven by the alternate line divider IC69 and shifts one of the master colour subcarrier references by 180 degrees to give the phase alternating line PAL subcarrier PAL can be disabled by making S28 South upD7002 4 channel analogue to digital converter Analogue signals input via SK6 arc converted about 10ms per channel to a 12 bit digital value The informs the processor of a completed conversion by interrupting it IRQ Interrupts are generated by the system VIA 1C20 when it receives an active NEOC signal Three diodes 09 D10 D11 in series are used for the voltage reference which is typically 1 8 volts with a 6mV per degree C temperature coefficient Note that the accuracy of the ADC part is equivalent to a resolution of about 8 bits ULA Serial processor IC The SERPROC handles the RS423 and cassette interface circuits Built into the IC are programmable clock generators which set the serial bit rate Signals from the selected interface RS423 or cassette are routed to from the 6850 1C82 by this IC The replay cassette signals are demodulated in IC85 and bit clock
71. the data bus D7 is available to the PAL IC36 Writing to the ROM select latch at address amp FE30 as described in 5 4 1 will save D7 in the PAL DO D3 are stored as normal IC45 If D7 is set logic 1 then the PAL selects the 12K paged RAM when the CPU address is in the range amp 8000 to amp AFFF If the ROM selected by DO D3 is present then the top 4K of that ROM will also appear in the memory map above the 12K paged RAM from amp B000 amp BFFF As ROM 0 is not allocated as standard it is BASIC if S13 is changed writing 128 to the ROM select latch will merely place the 12K paged RAM into the memory map and amp B000 amp BFFF will be vacant 4 2 7 RAM access There is 64K of installed RAM RAM access is dependent on whether the computer is in normal mode or shadow mode and the differences are shown in Figure 4 2 7 ACW SERVICE MANUAL Issue 1 43 Chapter 4 Figure 4 2 7 RAM access in normal and shadow modes 64K CPUSEL 21 CPUSEL 9 32K 44K NORMAL RAM I O Processor board In normal mode the RAM be thought of as 44K from address amp 0000 amp AFFF The top 12K of this RAM from address amp 8000 amp AFFF is paged into the memory map when required in place of the bottom 12K of the sideways ROM space see 5 4 2 The remaining 20K of RAM is set aside for the shadow screen memory while it always exists it is not available to the system in normal mode The bank of 44K RAM we shall call normal RAM
72. the host microcomputer ie in the bus free phase all bus lines will float according to the values of their terminating resistors Measure the voltage of each bus line in turn and make sure that none of them is stuek at 5V which would indicate a short circuit or at V which would indicate either that one of the buffers was enabled or that there was a short circuit The correct voltages are as follows 1 expansion bus DO to D7 and 0 to A7 should all be 2 5V SCSI DBO to DB7 should all be If for example DO to D7 are all or a mixture of and 2 5V then one of the buffers is probably enabled ACW SERVICE MANUAL Issue 1 121 122 ACW SERVICE MANUAL Issue I Appendix A ACW ADFS Utilities discs The utilities perform the various housekeeping funetions neeessary for a disc filing system The package includes a help facility for each utility The Disc Utilities The utilities are divided into three eategories ADFS Floppy utilities ADFS Winehester utilities ADFS General utilities One of these groups may be selected from the first menu Subsequent menus allow the selection of a particular utility and give detailed information about each one if required A brief description of eaeh utility is given below ADES Floppy Utilities Alarm Formats single or double sided 40 or 80 track discs to the ADFS double density format See the Appendix on Formatting Dises Backup Makes an identical copy of an ADFS floppy dis
73. the probability of syncronisation failure occuring the crystal oscillator input to the TCU is paused low if both the host BBC Micro and the 32016 access the tube simultaneously 5 3 2 Reset and Booting 90 Pressing BREAK on the keyboard causes a reset to occur in the host processor this causes NHRST on the host side of the Tube to go low and this in turn causes NPRST on the 32016 side NPRST is connected to the TCU reset in NRSTI The TCU produces a system reset NRSTO and it is this signal that resets the 32000 series devices During the reset recovery sequence BOOTING the CPU starts execution at location Hex 000000 Zero however it also expects to find a module table at location zero during program execution This causes a problem as this first instruction must be held in EPROM and the module table must be in RAM The problem has been solved using a technique known widely as RAM FLIP During BOOTING the address decoding logic causes the EPROMS to appear at multiple locations including zero and the RAM is disabled The first instruction held in EPROM at Hex 0000 is an unconditional branch into a high order copy of the EPROM Typically address Hex F00010 Execution continues with a Write instruction to no particular address and this causes the address decoding logic to switch out low order copies of the EPROMs and enable the RAM The BOOTING sequence is controlled by an S R latch formed by two cross coupled NAND gates IC19 IC4
74. then freed It is therefore recommended as part of normal housekeeping duties that the user compacts the files periodically This consolidates the files and causes free space on the disc to be gathered into larger contiguous sections The aetion whieh also often improves file aeeess times and releases further free space on the disc is earried out by using the COMPA CT eommand supplied in the ADFS filing system ROM To COMPACT the Winchester 1 Turn off the 32016 co processor using the TUBE switch on the back of the keyboard The TUBE LED on the keyboard should he OFF 2 Select BASIC Prompt by typing Basic RTN 124 ACW SERVICE MANUAL Issue I ACW ADFS Utilities discs 3 Select Shadow Screen Mode by typing SHADOW 1 RTN This speeds up the eompaetion by allocating more memory space as a buffer 4 Select the ADFS filing system by typing ADFS RTN 5 Select DRIVE 0 by typing DIR 0 RTN 6 Type RTN This displays the amount of both used and free spaee left on the dise Check that they are not nearly equal as no amount of compaction will create more spaee on a full disc 7 Run the compaction program by typing COMPACT 30 50 RTN WARNING IF the compaction program is interrupted for example by pressing BREAK or by a power cut then the file that was being moved at the time may be LOST or CORRUPTED It is good praetiee to backup important data on floppy discs or ECONET File Server The two numbers aft
75. versatile interface adapter VIA IC The A data lines are used for communication with the keyboard speech system and sound CAI is VSYNC from the CRTC which interrupts the CPU every 20ms CA2 generates an interrupt when a key is pressed PBO PB3 drive the addressable latch IC30 PB4 and 5 are inputs from the joystick fire buttons PB6 and PB7 arc inputs from the speech processor 1 is the end of conversion signal from the analogue to digital convertor 1C84 CB2 is the light pen strobe signal from pin 9 of the 15 way D type connector SK6 used for analogue in 1C21 741 5138 3 to 8 line decoder This is enabled for address values amp FE page FE the Sheila 1 0 space It is enabled when 8 is low and 9 15 are high The Sheila space is decoded into 8 blocks of 16 bytes Each block is enabled when the corresponding decoder output is low 1C22 74LS30 8 input NAND Detects address values of amp FC00 and greater It forms the first stage of the 1 0 space address decoder logic IC23 741 532 Quad 2 input OR 1 o p pin gates NW with the NFDC enable address amp FES80 to form the disc control latch clock 2 o p pin 6 gates NINTOFE NSTATID with N2E to give a glitch free active low preset signal for the ECONET NMI control latch 3 o p pin 8 gates the 2M clock with NVIDPROC to form CAS enable signal which can only be active high during CPU RAM access phi2 high 4 o p pin 11 gates NDEN with the latched D6 RAM da
76. writing o ACORN COMPUTERS LTD ACORN COM PUTERS Ltd 17 005 Admel 9 5 350 ITEM PART NO DESCRIPTION QTY REMARKS GE NS GNO NER SAC x was SED UU 020 001 A FINAL ASSEMBLY DRAWING 1 PER WORKS ORDER 0832 750 KEYBOARD ASSEMBLY 1 0201 441 UPPER CASE KBD 0201 442 LOWER CASE KBD 0201 433 SOFT KEY RULE 0201 444 FUNCTION KEY LEGENG 1 2 3 4 5 6 7 8 Fi EH 0201 836 SWITCH LABEL 13 0890 001 STICK ON FOOT 4 17 0882 654 NO 6x9 5 SELF TAP 5 19 0880 024 CBL STR REL GROM 1 40 ITEM PART NO DESCRIPTION QTY REMARKS CHE AINE AA aq Xm m cen GA NAE xar GN GC RR ON wan SET GU Dur S tx er an ISS 1 2 n m U U U DATE 11 84 28 7 86 YS A DRN JC CWW s
77. 0 ITEM PART No DESCRIPTION QTY WHERE USED C PER 155 1 s s to 28 7 86 a et y CHNG AMR E249 TITLE 32016 LARGE 4MByte PCB ASSY COPYRIGHT 1986 BILL OF MATERIALS ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0118 100 SHEET 2 of 4 CHERRY HINTON CAMBS BILL OF MATERIALS ACORN COMPUTERS LTD MEI was mE MIGNE GM GC XC h GP Ww Wu 34 Gk E 418 ur es uc xm KA C 2 d NR x ESL QB DG A RN PEN GN AD vam Ym WS NG ITEM PART No DESCRIPTION QTY WHERE USED C TO 121 122 123 124 125 0800 787 FSTN TAB 2 8 0 8 RA SH 4 126 3 127 128 129 130 131 132 0803 103 CONR 40W BOX IDC LP
78. 00 0000000 0000000 1111111 1111251 0111111 11011111 11101111 11110111 11111011 11 Cy C Q C 1111110 1144344 0000000 1111111 1111111 1111111 111110 bit OO C 00 00 C COD OO gt OC Om or CD 5 X Ss Ke CO O0 0 bit 0001000 0000100 0000010 0000001 0000000 ITXITTLT 1111111 1111111 1111111 1111111 1111111 111111 Pattern shifted up down ACW SERVICE MANUAL Issue 1 0 0 0 0 0 0 Cy C 0 0 0 0 0 1 Test program fault reports d Refresh fault rror addr 00000002 rror addr 00000004 rror addr 00000006 W ten 01000000 00000000 Read 00000000 00001000 W W rror addr 00000008 Wri W W W ten 00100000 00000000 Read 11001001 10010010 ten 00010000 00000000 Read 00101010 01001101 ten 00001000 00000000 Read 00101000 11100010 ten 00000100 00000000 Read 00101010 11001010 ten 00000010 00000000 Read 01011011 01101101 ten 00000001 00000000 Read 10010101 01010010 ten 00000000 10000000 Read 00000100 11011111 Error addr 00000012 Written 00000000 01000000 Read 11000000 00000111 Error addr 00000014 Written 00000000 00100000 Read 10001001 00100101 Error addr 00000016 Written 00000000 00010000 Read 11011011 11100111 rror addr 00000
79. 0014 00100016 lt GS 45 C QOO OOOO CO 0 0 0 0 0 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 11 even Written Written Written Written Written Written Written Written Written Written Written Written addresses or DRAM 11111111 10111111 00000000 11011111 11101111 11111111 11111101 11111111 00000001 11111111 11110111 11111111 Read Read Read Read Read Read 11110111 11111111 Read 0 A 00000000 00000000 10000000 00000000 01000000 00000000 00100000 00000000 00010000 00000000 00001000 00000000 00000100 00000000 00000010 00000000 00000001 00000000 00000000 10000000 00000000 01000000 0000000 00100000 up to OO01FFFFE 00000000 10000000 00000000 01000000 00000000 00100000 00000000 00010000 00000000 00001000 00000000 00000100 00000000 00000010 00000000 00000001 00000000 00000000 LITITITL OTIITXIIl LITILII 0111111 11111111 Read Read Read Read Read Read Read Read Read Read Read Read 11111111 1 011511 00000000 11011111 T 6042111 11111111 11110111 11 Stuck 15 65 C O OOO Stuck 0000000 0000000 00000
80. 00A rror addr 0000000 rror addr 0000000E Error addr 00000010 Wri J FJ Ed FJ EJ EH ct ct ct ct ct ct ct ct ct ct 11 even addresses ACW SERVICE MANUAL Issue 1 151 Appendix K MOUSE ASSEMBLY Mouse installation 152 If the mouse PCB is being fitted for the first time ensure that the ACW Mouse Adaptor kit contains the following e ACW Mouse Adaptor PCB Aninsulation sheet Four PCB mounting pillars e A 34way 850mm long ribbon cable A 34way 60mm long ribbon cable e 520mm long ribbon cable Two M3 screws nuts and washers A mouse To install the mouse card proceed as follows 1 Switch off and disconnect the ACW and any attached peripherals from the mains supply 2 Disassemble the ACW until the left hand component tray looking at the front of the computer is lying in its horizontal position Section 2 3 of this manual eovers disassembly and reassembly 3 Remove the 1 MHz bus ribbon from the ACW This can be identified by the legend on the rear panel Working from the rear of the unit remove the two screws nuts and washers that hold the 1 MHz bus D type connector to the rear panel Put these to one side as they will be required later Disconnect the cable from the I O Processor board and follow it round to the host adaptor PCB on the left hand components tray Note the position of this cable run Release any clamps securing the cabl
81. 1 122 153 6 0502 330 RES 33R 5 OW25 3 R53 55 7 0502 680 RES 68R 5 0W25 5 R109 112 128 130 8 0502 820 RES 828 CF 5 0 25 3 R62 65 67 9 0502 101 RES 100R CF 5 0W25 6 R31 45 47 57 61 10 0502 151 RES 150R CF 5 0W25 5 R1 5 8 11 12 0502 271 RES 2708 CF 5 0825 2 120 21 13 0502 331 RES 3308 CF 5 0925 2 330 35 14 0502 471 RES 4708 CF 5 0W25 2 R49 102 15 16 17 18 19 20 21 0502 102 RES 1X 5 0025 8 R11 16 63 73 104 105 22 8131 148 23 0502 152 RES 1K5 CF 5 0W25 1 R147 24 0502 182 RES 1K8 CF 5 0W25 3 R50 52 25 0502 222 RES 2X2 CF 5 0W25 4 R80 101 124 149 26 0502 272 RES 2 7 CF 5 0W25 1 R69 27 0502 332 RES 3K3 CF 5 025 6 R14 18 19 71 118 152 28 0502 392 RES 3K9 CF 5 OW25 1 78108 29 0502 472 RES 4 7 CF 5 OW25 7 R4 23 43 48 59 60 100 30 0502 562 RES 5X6 CF 5 OW25 1 R103 31 0502 822 RES 8K2 CF 5 OW25 2 R123 127 32 33 0505 103 RES 10K C MF 2 0W25 12 R22 26 27 29 34 42 44 34 R81 111 126 144 151 35 36 37 0502 393 RES 39K CF 5 0W25 2 R64 117 38 0502 563 RES 56K 5 0w25 21 R15 39 0502 623 RES 62X CF 5 0W25 i R33 40 0502 823 RES 82K 5 0925 i 1 R66 ITEM PART NO DESCRIPTION QTY REMARKS Iss 1 2 3 DATE 01 10 84 20 12 85 28 7 86 DRN PDP PDP JJW amp CWW LaL CHNG AMR 598 ECO 50016 ECO E198 TITLE ABM CONTROL BOARD COPYRIGHT 1986 PARTS 115 ACORN COMPUTERS LTD
82. 10 20 30 a 90 LDA amp FC90 50 JMP 60 70 CALL a Test pin 1 1C3 with a scope and check that the waveform is not stuck either high or low It should look like the one shown in figure 6 9 2 a 118 ACW SERVICE MANUAL Issue 1 Winchester and Floppy Disc Systems Figure 6 9 2 a Waveform on Pin 1 IC3 t 1 i 3 s S M 250 kHz amp FC40 write data Run the following program 10 DIM P 10 20 30 8 40 STA amp FC40 50 JMP a 60 70 CALL a Test pin 11 IC2 with a scope and cheek that the waveform is not stuck either high or low It should look like the one shown in figure 6 9 2 b Figure 6 9 2 b Waveform on Pin 11 1C2 4V t t 1 N 1 1 950 kHz 6 amp FC41 read status Run the following program 10 DIM P 10 20 30 40 LDA amp FC41 50 JMP a 60 70 CALL a Test pin 1 1C4 with a scope and check that the waveform is not stuck either high or low It should look like the one shown in figure 6 9 2 a amp FC42 write select Run the following program 10 DIM P 10 20 30 a 40 STA amp FC42 50 JMP 60 70 CALL a Test pin 11 with a scope and check that the waveform is not stuck either high or low It should look like the one shown in figure 6 9 2 a amp FC43 write IRQ enable Run the following program 10 DIM P 10 20 30 a 40 LDA 0 50 b 60 STA amp FC43 70
83. 16 co processor using the TUBE switch on the back of the keyboard The TUBE LED on the keyboard should he OFF 2 Select BASIC Prompt by typing Basic RTN 3 Select the ADFS filing system type ADFS RTN 4 Insert the ACW ADFS Utilities disc 5 Select the floppy disc drive type DIR 4 RTN ACW SERVICE MANUAL Issue 1 127 A ppendix B 6 Start up the utilities disc by typing CHAIN UTILS MENU RTN A menu of utilities will be displayed 7 Select the Floppy dise utilities suite type f0 8 Seleet the Floppy dise formatter AFORM type f0 and wait until the message ADFS Floppy Formatter Ver appears then 9 Remove ACW ADFS Utilities Disc and insert disc to be formatted 10 To the question Format which drive reply 4 RTN 11 To the question Size of disc reply L RTN for a double sided dise or S RTN for a single sided disc RTN 12 To the question Format drive 4 Large OK reply YES RTN The program will format and then verify the dise 13 Formatting is complete when the messages Verification Complete and Format which drive are displayed 14 Press SPACE to return to menu 15 Replace utilities dise in the drive if other utilities are required Winchester ADFS Formatting The Winehester hard disc should only rarely need to be reformatted usually in one of the following circumstances 1 Installation of a new Winchester 2 Following corruption of the Winchester
84. 210 0870 420 WIRE 22SWG CPR TIN A R R12 32 40 S7 58 S16 211 212 0800 200 FSTN TAB 2 8 0 5 ST 7 5V 3 0 3 5 1 213 214 215 0800 004 5W SKT DIN 1 SK 216 217 0800 002 CONR 6W SKT DIN SK3 1 218 0800 001 SW SET DIN RA DOM 1 SK4 219 0800 003 SET DIN RA PCB 1 SKS 220 0800 304 15W SKT D RA E2 54 1 SK6 221 222 223 224 225 226 221 228 229 230 231 232 233 234 235 236 237 238 239 240 ITEM PART NO DESCRIPTION QTY REMARKS 155 1 2 3 DATE 01 10 84 20 12 85 28 7 86 mf sme gt e DRN PDP PDP 209 amp CHW PAM CHNG 598 ECO 50016 ECO E198 sms ZG war wan SEE upa U iA ma SD TITLE ABM CONTROL BOARD COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD
85. 46 DRAMs Use a PORT tester to carry out a RAM check Check that RAS and CAS pins 4 and 15 respectively of the eight DRAM ICs are wobbling Results if RAS is stalled low then the DRAM ICs may be destroyed Check the circuitry for generating RAS and CAS the video processor IC53 8M 4M and 2M half of IC31 and various gates Check that RAS and CAS timing is as shown in figure 6 Check that RAM data lines are wobbling Check that the data bus buffer is being enabled 19 IC49 Video Look at the displays from the ACW monitor and or the external composite video monitor and see which of the following 1 2 3 or 4 best describes them 1 None of the monitors operate Results there are incorrect signals coming from the video processor Replace the video processor IC53 Run the following program and check that video processor is being selected pin 3 IC53 is wobbling ACW SERVICE MANUAL Issue 1 Processor board vidproc amp FE20 DIM P 100 start STA vidproc JMP start CALL start 0 0 0 0 0 0 0 0 1 oF 2 The RGB picture is distorted Results either the DIN plug is incorrectly fitted to the monitor socket or CSYNC must be inverted by altering S27 4 7 9 Cassette interface and RS423 These two interfaces are examined together because they share two major components the UART or ACIA 1C82 and the serial processor or SERPROC IC85 If both the cas
86. 5 3 Adjust VR916 for blue peak to peak volts at R924 4 The voltages arc 70v p p for 14 TTL monitor 3 5 Circuit description 3 5 Technical specifications ACW SERVICE MANUAL Issue I 27 Chapter 3 System Supply Timebase line Frame frequency Positional error Convergence error 625 lines 50 fields interlaced 240V 50Hz Pull in range 15 to 16KHz 50Hz Pull in range 45 to 65Hz or 3 0 6mm screen centre 1 6mm screen edge EHT 24K V approx EHT regulation or Line frequency 15 625KHz Degausing Automatic at switch on Bandwidth 18 2 Resolution 452 H x585 V elements Dot pitch 0 64mm CRT 90 degree deflection vertical stripe screen 3 5 2 Video input 28 TTL mode is used The contrast of the video information is tracked by varying the available potential across the open collector load resistors R114 115 and 116 which are supplied by TR101 from 12V the base being driven from the contrast control slider VR111 R112 C101 form a low pass filter and ensure smooth operation of the contrast control CRT Beam current The information is fed to DII7 118 from a constant current source derived from the main HT rail As the CRT beam current increases the D117 118 junctions become more negative and thus D117 conducts more heavily causing the voltage to TR106 base to decrease R136 C105 filter the signal the derived voltage is emitter followed and supplies the TR103 104 an
87. 6R4 1 IC36 184 0701 770 WD1770 FDC 5 25 1 16 185 186 187 188 189 190 191 192 0800 117 SKT 16 0 3 SUPA 1 IC17 193 0800 121 SKT IC 20 0 3 SUPA 1 IC36 194 0800 124 SKT IC 24 0 6 SUPA 1 82 195 0800 129 SKT IC 28 0 6 SUPA 8 1 29 35 37 44 57 62 68 71 196 0800 141 SKT 40 0 6 SUPA 4 IC10 20 42 78 197 0803 102 CONR 34W BOX IDC LP ST 2 PL8 11 198 0803 103 CONR 40W BOX IDC LP ST 1 PL12 199 0803 101 CONR 26W BOX IDC LP ST 1 PLO 200 0800 050 2W WAFR 0 1 ST 3 115 526 5 2 DESCRIPTION i QTY REMARKS Iss 1 2 i 3 DATE 01 10 84 20 12 85 28 7 86 DRN PDP PDP JJW amp CWW CHNG AMR 598 ECO 50016 ECO E198 wat EE S et UD x UM xar CE Xd TITLE ABM CONTROL BOARD COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD mr um Ka cm EM RM E FULBOURN ROAD DRAWING No A4 0133 400 SEEET 5 of 6 CHERRY HINTON CAMSS PARTS LIST ACORN COMPUTERS LTD ITEM PART NO DESCRIPTION QTY REMARKS 201 0800 051 3W WAFR 0 1 ST PCB 4 S13 14 20 27 202 0800 052 5W WAFR 0 1 ST PCB 4 9 11 12 15 18 SK3A 203 0800 054 8W 0 1 ST PCB 2 523 204 205 0800 059 CONR 17W WAFR 0 1 ST PCB 1 PL13 206 207 0803 100 CONR 20W BOX IDC LP ST i PL10 208 i 209 0800 070 CONR 2 SHUNT 0 1 14 9 11 13 15 18 23 7O0FF 2
88. 7 Filing systems The following systems are available to the I O processor DFS This uses floppy discs with single density format A major purpose of the DFS is to maintain compatibility with earlier systems Distribution software for the ACW and Co Processor is supplied in this format except for the ADFS utilities disc which is supplied in ADFS format ADFS The Advanced Disc Filing System For use with Winchester and floppy discs formatted using Modified Frequency Modulation format which provides double density storage NFS The Network Filing System This enables a number of stations to share a filing system operated by a special station the file server using the Econet network ADFS NFS and DFS are supported by Panos The following additional filing systems are also available but normally only via star commands EEE The IEEEAS8S filing system APE or The 1200 Baud cassette filing system 12 The 300 Baud cassette filing system TELESOFT The Teletext filing system ROM The sideways ROM cartridge system The various filing systems are described in more detail in the Processor Guide Acorn part number 0410 004 A list of I O processor ROMs installed in a particular ACW may be obtained by typing ROMS RTN For each of the filing systems help information in the form of a command list with syntax may be elicited by using the filing system name as in the following examples ACW SERVICE
89. 71 disc interface NOT FITTED ON ACW I O PROCESSOR IC16 1770 FM MPM floppy disc controller Driven by either the ACORN 1770 disc filing system software for FM single density recording or by the ACORN advanced disc filing system software for MFM double density recording to control 40 track or 80 track 5 25 inch disc drives or any compatible alternative The 1770 disc controller ACW SERVICE MA NIJAT Issue 1 73 Chapter 4 cannot be used in conjunction with 8 disc drives 1C17 7ALS174 Hex D type This hex D type latch is used for the disc control signals not generated by the 1770 Motor on off two drive select signals and one side select signal are held in the latch Also the disc format mode single double density and a 1770 master reset signal are held in this latch All these signals are under direct program control The latch is addressed at amp FE80 1C18 745163 Presettable 4 bit counter Configured as a divide by 13 to give 16MHz 13 clock for cassette and RS423 baud rate generation and disc speed detection 1C19 74LS00 Quad 2 input NAND 1 o p pin 11 detects a count of 12 on IC18 and generates a synchronous load pulse so that IC18 divides by 13 2 o p pin 8 is used as an inverter to generate NW for the system RAM 3 o p pins 3 and 6 are part of the decoder that converts the 2 bit code for display RAM size from the addressable latch IC30 to the 4 bit code fed to the adder 1C76 1C20 6522 System VIA This is a
90. ACORN COMPUTERS LTD ACW 443 SERVICE MANUAL 0420 001 Issue 1 January 1987 ACW SERVICE MANUAL Title ACW SERVICE MANUAL Reference 0420 001 Issue 1 Replaces 0 56 Applicability Product Support Distribution Authorised Service Agents Status for publication Author C Watters J Wilkins and Others Date 7 January 1987 Published by Acorn Computers Ltd Fulbourn Road Cherry Hinton Cambridge CB1 4JN England Within this publication the term BBC is used as an abbreviation for British Broadcasting Corporation Copyright ACORN Computers Limited 1985 Neither the whole or any part of the information contained in or the product described in this manual may be adapted or reproduced in any material form except with the prior written approval of ACORN Computers Limited ACORN Computers The product described in this manual and products for use with it are subject to continuous development and improvement All information of a technical nature and particulars of the product and its use including the information and particulars in this manual are given by ACORN Computers in good faith However it is acknowledged that there may be errors or omissions in this manual A list of details of any amendments or revisions to this manual can be obtained upon request from ACORN Computers Technical Enquiries ACORN Computers welcome comments and suggestions relating to the product and this manual correspondence should
91. ACW 1 0 Processor fitted with ADFS ROM b Video Monitor c Floppy Disc Drive see below d Winehester Dise unit Under Test e Host adaptor PCB f Power supply 6 8 1 Formatting Drives 116 Before shipment each Winchester Disc unit has a suite of utility programs stored on it including a two copies of the formatter entitled Superform these can be found in directory FORMAT and are SUPERFORM and SUPERFORM I Copies of this software are also supplied with the unit on a floppy disc called ACW Utilities Disc Acorn No 2201 238 Details on formatting are given in the appendix ACW SERVICE MANUAL Issue 1 Winchester and Floppy Disc Systems 6 9 Fault finding When the Winchester Dise unit is powered up the hard disc will spin up to speed in about 10 seconds This process produces a rising pitch humming noise which means that the hard disc is spinning Note that there is also noise from the ACW s cooling fans but this noise is lower in piteh and does not take time to build up if the disc is not spinning then eheck the power supply and connections 6 9 1 Power supply The three major eomponents of the Winchester Disc unit the disc drive the disc controller board and the Host Adapter board are each powered from the ACW switch mode power supply unit via the DC power distribution hoard black ground red 45V orange 12V The power supply can be tested by measuring the 5 voltage between the black and red cables and t
92. Adapter circuit diagram in the Appendix The Winehester Disc Host Adapter is an interface between the SASI SCSI interfaee and the 1MHz expansion bus It consists of address decoding and handshake control buffering of the signals in either direction and termination 6 7 1 Address decoding and handshaking The Host Adapter deeodes 4 locations in the host microcomputer s page FC I O spaee These four locations are as follows 114 ACW SERVICE MANUAL Issue 1 Winchester and Floppy Disc Systems Address Read Write amp FC40 data data direction determined by R NW amp 41 status amp FC42 select amp FC43 enable IRQ Page FC is deeoded in the host microcomputer and this is available to the Host Adapter as NPGFC not page FC NPGFC is synchronised with by the de glitch circuit half of IC10 and the clean signal is labelled CNPGFC pin 5 IC10 The low order address lines AO to are buffered through 1 5 IC6 a 3 to 8 line decoder with three enable inputs decodes the low order addresses amp 40 to amp 43 ie output pin 15 goes low when the low order address is amp 40 amp 41 amp 42 or amp 43 1C7 is another 3 to 8 line decoder which takes the output from 106 and CNPGFC and 1MHZE as enable inputs The 2 least significant address bits AO and Al are deeoded along with R NW into the required 5 separate signals shown above YO pin 15 is read data R NW 1 Y4 pin 11 is write data R NW 0 pin 14 is s
93. CAS is pulled low and the Column address is strobed into the DRAMs 5 4 4 Read write The direction of the memory access Read or Write is signaled to the TCU by Data Direction In NDDIN and it is the TCU that generates READ NRD or WRITE NWR accordingly NWR is buffered and distributed to all DRAMs by IC40 NDDIN is used to select the direction of the data bus bufers IC12 and IC13 and NRD is used to drive the TUBE and EPROM 5 4 5 Data validity During a read cycle the processor expects the data returned from memory to be valid before the end of PHI2 during NTSO low During a write cycle the processor provides valid data during NWR low 5 4 6 Memory access cycles with MMU Memory managed cycles are shown in Figure 5 4 6 In this case the processor places a VIRTUAL address on the AD bus and NADS from the processor is used to strobe the address into the MMU The MMU uses an internal translation table to look up the coresponding PHYSICAL address which it places on the AD bus one cycle later NPAV from the MMU looks to the TCU like NADS from the processor and the memory access then continues in the same way as the non memory managed case but one cycle late The memory manager maintains its internal translation table Cache without intervention from the processor If the table entry required is not held in the MMU it is fetched from the larger page table in main memory In this case the CPU memory cycle is paused while the MMU updates
94. CB itself is likely to be faulty and should be replaced Field replacements A mouse which develops a fault after extensive use should be examined for wear and physieal damage The hand held mouse is not a field repairable item Suspect cable damage and loose conneetions and rectify if these are found to be the problem If the mouse PCB is faulty that too should be replaced by a new PCB card ACW SERVICE MANUAL Issue 1 153 i i 1 300 7 3 m lt lt s 3 3 3 1 2 32 41721 55 52 5552129 2 3 4 di il Eg Lor E EE ia t e i J v 3 Es x 54222563 Host Adapter circuit diagram Y Y Y waa Camana aaj Y Y Y wowed Lendl gral r naul 62 82 4311 can zu Gem v d OY LAFA gatiti OYJAX4 JININ 0130 4 s 145 F I 4 bims nms M MAS PIT ems n Sr an ate La i snnt R wa lt M T 1 7 tas T 1031 t4 44512 C s a e 4 9 ART 16 6 91 9717 53 wig 3 a 5
95. CONET is based around the 68B54 IC81 advanced data link controller IC81 performs the conversions between serial and parallel data and generates the interrupt requests which are connected to NMI Each byte transfer between network and CPU is requested by an NMI Interrupts can be disabled by making pin 4 1C23 low thereby setting the D type half of 1C69 which is achieved by a read of amp FE18 Reading this address returns the station ID number which is set up on the links 523 Interrupts are enabled when pin 2 1C69 goes low a read of amp FE20 which when clocked by N2E resets the D type Transmit data from the 68B54 is fed to a differential line driver circuit IC91 and then through SK7 on to the twisted pair network cable The differential drive voltages are typically 0 25V and 3V A monostable half of IC88 is used to time out the ECONET line driver by taking pin 9 IC91 low after approximately 4 5s longer than the time required to transmit a maximum length data packet This is designed to prevent a single computer holding its driver on and thereby bringing the whole network down Receive data is decoded by a comparator circuit 1C92 and fed into the 68B54 1C93 collision detect ciruitry is not fitted Before transmission the line is sampled to see if it is in use If it is the transmission is held up until a certain time after the line is first free again This time is dependent on the station 1D and so will be different for every statio
96. Din line either side of the receiver pins 4 and 7 of IC94 Pin 4 should be oscillating at RS423 logic levels 5 5 Pin 7 should be oscillating in phase with pin 4 but at normal TTL logic levels 0 5 If pin 4 is active but pin 7 is not then replace the receiver IC94 Check that the SERPROC 85 is sending the receive clock RXCK and receive data RXD to the 6850 IC82 These signals are on pins 26 and 22 respectively of IC85 If these signals are inactive then it is likely that the SERPROC is faulty or cannot be addressed Use the test program given in the cassette section above to check that the address decoding for the SERPROC and 6850 is working The alternative way of testing RS423 without using another microcomputer is to connect RTS to CTS and Dout to Din Then if the BASIC program above is used to transmit data its path can be followed from the data bus through the 6850 SERPROC drivers out through the connector and back again through the receivers SERPROC and through RXD back to the 6850 This loop allows all the components of the RS423 circuit to be checked as above 4 7 10 Keyboard Keyboard problems either show up as a single key which won t work reliably or a whole group of keys which refuses to operate The single key fault is caused by that particular switch having worn out or the track becoming broken by excess force Replace the key or solder the track For multiple key problems the first thing to check is that the co
97. ESSAGE MSG pin 42 is asserted by the target when it issues a message byte to notify completion of a command see 5 1 2 DATA BUS DBO to DB7 pins 2 4 6 8 10 12 14 and 16 is a parallel data bus consisting of 8 signals from DBO least significant to DB7 most significant 1 byte of information is transferred across the bus with each REQ ACK handshake It is important to remember that the data lines are aetive low and therefore are inverted in both direetions when eommunieating with the host microeomputer All odd numbered pins are OV and pin 34 is 5V ACW SERVICE MANUAL Issue 1 109 6 SCSI connector pinout PL2 and J4 Pin no 1 2 DBO 3 4 DB1 5 6 DB2 7 8 DB3 9 10 DB4 11 12 DB5 13 14 DB6 Ov 15 16 DB7 17 18 Ov 19 20 OV 21 22 OV 23 24 For future expansion OV 25 26 OV 27 28 OV 29 30 0 31 32 OV 33 34 5V to supply test equipment 35 36 BSY OV 37 38 ACK OV 39 40 RST 41 42 MSG 43 44 SEL Ov 45 46 C D 47 48 REQ Ov 49 50 I O 6 5 3 Bus phases 110 The bus has several distinet operational phases and eannot be in more than one of these phases at any given time Bus phases occur in a prescribed sequence The reset condition can interrupt any phase and is always followed by bus free Any other phase can also be followed by the bus free phase The prescribed sequence is from bus free to selection to one or more of the infor
98. FULBOURNE ROAD CHERRY HINTON CAMBRIDGE third party either wholly or in parl without the C81 4JN DRG No consent in writing of ACORN COMPUTERS LTD ACORN COMPUTERS Ltd 4 0127 000 Anmei DS 450 WINCHESTER DISC HCST ADAPTOR ASSEMBLY
99. ITTED ON ACW I O PROCESSOR 7415303 Dual divide by 16 Required only by 8271 disc interface NOT FITTED ON ACW I O PROCESSOR 4013 CMOS dual J K flip flop Required only by 8271 disc interface NOT FITTED ON ACW I O PROCESSOR 4521 CMOS 24 stage binary divider Required only by 8271 disc interface NOT FITTED ON ACW I O PROCESSOR 741 5244 Octal buffer Permanently enabled buffer for the CENTRONICS compatible printer interface data lines T4LS244 Octal buffer Permanently enabled buffer for the 1MHz extension bus Buffered lines are four address lines LAO to LA3 NPAGEFD NPAGEFC 2 and RNW 7438 Quad 2 input o c NAND 1 o p pin 6 is drive select 1 Gates motor control and drive select from controller circuitry to form the external drive select Must be able to drive a 150 ohm pull up resistor hence cannot be LS TTL ACW SERVICE MANUAL Issue I I O Processor board 2 o p pin 8 is drive select 0 see above 3 pin 11 is used to buffer and invert the disc controller interrupt signal to the wire NOR NNMI interrupt line 4 o p pin 3 gates the 1770 DRQ on to the interrupt line Used only with 1770 hence link S8 used to select 1770 made or 8271 broken option If IC7 is fitted and the disc controller is not then IC7 pin 13 or pin 2 or R14 must be pulled low to avoid NNMI being held low permanently which would stop the ECONET hardware from working 8 7416 Hex o c inverter Converts active high
100. In normal mode VDUSEL 1 36 pin 17 is always zero Any code executing anywhere within normal RAM in normal mode will always access normal RAM it cannot access shadow RAM In shadow mode the RAM can be thought of as 44K from address amp 0000 amp AFFF plus a parallel bank of 20K RAM from address amp 3000 amp 7FFF which we shall call shadow RAM As in normal mode the top 12K of normal RAM is paged into the memory when required In the address range amp 3000 amp 7FFF the PAL IC36 is able to switch between shadow RAM and normal RAM It selects access to the shadow memory if a shadow mode is on b it detects a VDU driver and c the operand address is between amp 3000 and amp 7FFF the part of the memory map used by the screen Otherwise it selects access to normal RAM The machines logic is set to Shadow mode when logic 1 is written to D7 at address amp FE34 this causes pin 17 VDUSEL to go high amp FE34 is the address of a register in the PAL and when D7 is set any screen access through the VDU drivers will cause the PAL to switch in the shadow memory by making pin 12 CPUSEL high In shadow mode VDUSEL is always set and CPUSEL is low to access normal RAM and high to access shadow RAM When the paged RAM is selected in shadow mode the top 4K amp A000 to amp AFFF is programmed by the PAL IC36 to have the attributes of VDU drivers Any code executing between amp 0000 amp 9FFF in shadow mode will always access normal
101. K2 Video Out BNC outer ground inner video ACW SERVICE MANUAL Issue 1 139 Appendix F SK3 RGB 6 pin DIN 45322 SK4 RS423 5 pin DIN 45327 SK5 Cassette 7 DIN 45328 Motor control SK6 Analogue 15 way D type 1 45V OV OV CH3 analogue ground OV analogue ground QN tA A N SK7 Econet 5 pin DIN 41524 light pen strobe NLPSTB digital switch input I1 voltage reference VREF CH2 digital switch input JO voltage reference VREF CHO Connector pinouts Appendix F 9 Printer Port 24 way DELTA IDC Signal Connector pin I O PCB Panel Printer 26 way 24 way 36 way strobe 1 1 1 Data 0 3 2 2 Data 1 5 3 3 Data 2 T 4 4 Data 3 9 5 5 Data 4 11 6 6 Data 5 13 7 7 Data 6 15 8 8 Data 7 17 9 9 Acknowledge 19 10 10 No conneetion 21 23 25 26 11 12 11 to 17 Ground 2 4 6 24 13 to 24 18 to 29 142 ACW SERVICE MANUAL Issue 1 PL10 User Port 25 way D Type IDC 25 way I O PCB Function Dtype IDC 1 1 2 3 3 5 4 n 5 9 6 1 7 13 8 15 9 17 10 19 21 12 23 UJ 45V 45V OV OV OV OV OV OV OV OV NC NC N C 25 way I O PCB Function Dtype IDC 14 2 15 4 16 6 17 8 18 10 19 12 20 14 21 16 22 18 23 20 24 22 25 24 ACW SERVICE MANUAL Issue 1 1 2 PBO PB 1 PB2 PB3 PB4 PBS PB6 PB7 N C N C Connector pinouts 143 Appendix F PL11 1MHz Bus37 w
102. M5x10 PAN HD POSI 8 68 0882 215 SCW M2 5X16 CSK HD POSI 8 69 0882 101 SCW M2x5 PAN HD POSI 2 70 0882 961 WSHR M2 PLN STL Z PAS 2 71 0882 654 SCW 6 9 5 PAN HD POSI 10 72 0882 965 WSHR M5 PLN STL Z PAS 16 73 0882 975 WSHR M5 SPRF IT STL 12 74 0882 461 NUT M4 FULL NYLON 6 75 0882 906 NUT M6 FULL SF LK 2 5 8 76 0882 902 NUT M3 STL FULL Z PAS 12 77 0882 962 WSER M3 STL Z PAS 34 78 0882 460 SCW 4 10 CH HD NYL 6 79 0882 972 WSHR M3 SPRF iT STL 28 80 0882 966 WSHR M6 PLN STL Z PAS 8 ITEM PART NO DESCRIPTION QTY REMARKS nn n a a GP p ER qug qup cep UA GER UND dom x s CHNG 50010 50018 ECO 117 ECO E226 wa za ws xm US XX LIC CI XX et w SE LII x x E LI uwa U
103. NE DX EX zar TITLE ACW 443 FINAL ASSEMBLY COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0020 233 SHEET 2 of 4 CHERRY HINTON CAMBS PARTS LIST ACORN COMPUTERS LTD m xx qa SELES xz xz yt S wa xx r xe p za u ee ek 110 E lt mm a ID NE XX XE a ats WP xu O unb ER Kx ON zx Yaz HE un a wan aun wn GO ua aan wan 1 ITEM PART NO DESCRIPTION REMARKS 81 0882 983 WSHR M6 PLN NYL 8 82 0882 224 SCW M3x6 CSK HD POSI 4 83 0883 838 CIRCLIP 1 84 0883 920 FSTNR 7 160D STARLOCK WSH 4 85 86 0884 043 RIVET POP CSK ED 3 2mmD 12 87 0884 040 RIVET POP CSK HD 18 88 0884 041 RIVET POP CSK HD 4 89 0884 042 RIVET POP CSK HD 6 90 91 0582 103 POT PNL 10K LN 22x6mm 20 2 92 0882 985 WSHR M3 PLN NLY 4 93 0884 140 SCW 6 32UNCx3 8 PA HD 4 94 0884 070 DRAW LTCH FO SNPS PLSTC 2 95 0884 080 STUD SF EJECT 5 6 96 0884 081 STUD SF EJECT NO5 SPR 6 97 0880 101 CBL TIE LK 97mmL A R 98 0880 053 SLVING 3mmD H SHRIK 4 1 A R 99 0907 002
104. NUAL Issue 1 32016 Processor 5 7 4 Power Supply Make sure that power is getting to the hoard by checking the 5v supply line using a DVM across the Faston connectors 5 7 5 Timing Signals NOTE The program found in the appendix will be invaluable as an aid to fault finding when using an oscilloscope CLOCKS Check for the presence of the clock signals XCTL1 PHI2 and MTh pins 13 11 10 and 16 on the TCU These may be checked against the Fig 2 The TCU generates all system clocks from the double frequency crystal XCTL is a buffered version of XCTL The two clocks PHI I and PHI2 should have rising edges on alternate rising edges of FCLK CI FL is just a TTL compatible version of PHII Check that these key clock signals arrive at the CPU and FPU where appropriate RESET Check that the system reset is functional by following the sequence of events described in the preceeding text as follows While allternatly pressing and releasing the break key check for activity on HRST Host Reset Pin 20 PRST Parasite Reset Pin 37 RSTI Reset in TCU Pin Ty IC32 RSTO Reset out TCU Pin 8 IC32 RSTO Pin 34 IC31 RSTO Pim 5 IC2 these signals should go low and rise again when the BREAK key is released 5 7 6 Processor Signals NADS The lower sixteen lines of the bus arc multiplexed address data lines The address strobe line ADS goes low for approx a
105. PB2 6 11 OV 19 12 PB3 7 13 OV 20 14 PB4 8 15 OV 21 16 5 9 17 OV 22 18 PB6 10 19 OV 23 20 PB7 11 21 N C 24 22 12 23 25 24 13 Table 3 Connector Pin Assignments User Port The VIA is memory mapped at locations 16 FEA40 to 16 FE6F The method of programming the function of the VIA is described in the 6522 Data Sheet this information is reproduced in Chapter 22 of the Advanced User Guide for the BBC Micro 4 2 12 1MHz extension bus This is an extension of the bus signals of the 6512 Input Output processor The bus is a fully buffered interface to the CPU via PL11 which operates with I us transfer cycles IC12 bidirectional buffer is enabled when either FRED or JIM is accessed pages amp FC and amp FD These two pages are decoded by IC22 and IC28 with signals NFRED and NJIM appearing on pins 4 and 5 respectively of IC28 When either NFRED or NJIM goes low 1MHz bus enable goes low IC34 pin11 and takes low an input of the NAND gate IC41 thus causing IMHz CPU cycle NotFRED IC28 pin 4 and NJIM IC28 pin 5 along with R NW IC24 pin 10 and bus enable IC34 pin 11 are synchronised to the IMHz system clock 1M by latching them in IC32 This ensures that no glitches occur on the 1MHz bus interface 48 ACW SERVICE MANUAL Issue 1 1 O Processor board External Connections Devices connected to the bus are accessed by the I O processor as part of its memory space that is the
106. R FAN ASSY ACW UPPER FAN POWER LEAD ACW UPPER FAN POWER BRKT FAN FILTER ASSY 80mm BK SCW 3 25 PAN HD POSI ACW REAR PNL EARTH STRAP QTY HR Nr REMARKS d EH Z o mu I sas x ms mm x lt 2 OAK I E GI xr DID hf E mb wa UAM lt x sas e ir gut UD MAS L GC x wr ECCE ITEM PART NO DESCRIPTION QTY 4 REMARKS 155 1 2 3 4 M wr e nee hee een eee Ms DATE 14 11 85 20 12 85 24 6 86 12 9 86 DRN PLH PDP 1 CW JW CHENG 50010 ECOSOO18 ECO E117 ECO E226 TITLE ACW 443 FINAL ASSEMBLY COPYRIGHT 1986 PARTS LIST ACORN COMPUTERS LTD FULBOURN ROAD DRAWING No A4 0020 233 P SHEET 4 of 4 CHERRY HINTON CAMBS xx gt x gt at FE Y s 27 UR x ua z z x O ME YE ut EE DEO Ati Ar WE UE HE 2 II 2A fa SB PARTS LIST ACORN COMPUTERS LTD ITEM PART NO DESCRIPTION QTY REMARKS 1 0233 000 BARE PCB 1 2 0133 400 ASSEMBLY DRAWING 1 PER WORKS ORDER 3 4 5 0502 100 RES 10R CF 5 0W25 4 R58 12
107. S423 cassette to D and ECONET To use this tester the microcomputer must at least have the CPU running and the MOS BASIC ROM working and some of the RAM working Full operating instructions are supplied with the equipment 4 7 Fault finding This section goes step by step through fault finding in each section of hardware It should be studied in conjunction with the circuit diagram and block diagram in the Appendix ACW SERVICE MANUAL Issue 1 59 Chapter 4 4 7 1 Visual Check First perform a visual inspection of the printed circuit board check that all external connections TUBE ribbon cable and the power leads are secure and in good condition Check that no foreign objects washers etc have found their way onto the board Also check that the EPROMs and Molex links are inserted correctly Check specifically that 1 There are no loose connectors and broken cables 2 There are no broken or shorting tracks 3 The ICs plugged into their sockets correctly 4 The power supply is working and reaching the components concerned 5 digital signals at clean TTL logic levels greater than 2 4V for 1 less than 5 for 0 On timed signals this must be true for the period 150ns before phi2 on read cycles and 300ns before phi2 on write cycles The following items of test equipment arc required for fault finding 1 PORT tester 2 10A Multimeter 3 logic probe 4 20MHz dual beam oscilloscope 5 composi
108. SIC and any call to ROM 14 or 15 will be ignored This allows the user to select an alternative language at power on the language entered at start up will be the one with the highest socket number when more than one language ROM is fitted Address decoding is carried out by the PAL IC36 and this then selects either the operating system if the address is in the range amp C000 amp FFFF or the current sideways ROM if the address is in the range amp 8000 amp BFFF Part of IC40 disables the ROM output drivers when an I O address occurs amp F000 amp FEFF ACW SERVICE MANUAL Issue 1 I O Processor board The currently selected ROM number 0 15 is held in the ROM select latch IC45 The ROM select latch is mapped into the memory at address amp FE30 via the PAL IC36 When writing to this address the four data lines DO D3 provide the ROM number which is latched into 45 see also 5 4 2 When the PAL decodes an address from amp 8000 amp BFFF IC36 18 goes low and enables IC46 IC46 is a three line to eight line decoder which selects the particular IC socket allocated to the ROM number in IC45 The least significant bit held in IC45 is fed to the relevant ROM socket only if the link for that socket is made E for a 32K device The correct half of the 32K device is then selected to be placed in the memory map 4 2 6 Paged RAM operation The 12K paged RAM is selected with a ROM number between 128 and 255 D7 set The top bit of
109. ST 1 133 134 135 136 0820 200 XTAL 20MHz HC18 U 1 137 138 139 0895 081 PAD S ADH DBL SIDED 1 140 141 142 0940 002 ADHESIVE A R 143 0940 003 ADDITIVE 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 ITEM PART No DESCRIPTION WHERE USED C TO e n Ui CENG AMR E249 338 SER WEB RON HR dG YES ee Yam Sm mg wan Un Gm eee TITLE 32016 LARGE 4 ASSY
110. The 555 generates reset pulse RS which is inverted to give the CPU NRS signal 4 2 4 Address decoding and memory Figure 4 2 4 shows the memory map At the heart of the memory selection is the programmable array logic PAL chip IC36 It selects which screen RAM is in use normal or shadow it controls the sideways ROM select latch IC45 it selects the paged RAM 40 ACW SERVICE MANUAL Issue I Figure 4 2 4 Processor Memory map t 4K i BOs 16K SIDEWAYS ROMS 2 11 12K SIDEWAYS 8066 SHADOW SCREEN RAM 3020 1 Processor board FFFF FFA FCA OPERATING SYSTEM ROM 0 1 0714 15 8000 NORMAL SCREEN RAM 3004 pego UPWARDS WORKSPACE 229 Chapter 4 4 2 5 ROM operation 42 Any ROM socket on the PCB can either hold an 8K 16K or 32K BYTE device 8K or 16K IC s are paged into the memory map from amp 8000 amp 9FFF or from amp 8000 amp BFFF respectively a 32K device provides two 16K banks of memory paged into the memory map from amp 8000 amp BFFF The extra address line A14 QA from IC45 required by 32K devices is available to each ROM slot when the appropriate molex link is altered The ROM socket IC numbers their corresponding ROM select numbers and their corresponding link numbers are shown in table 1 IC No ROM Nos Link No Notes IC35 2 3 S9 Molex link made W as standard for 8K 16K use 44 4 5 511 6 7 512
111. V When a conversion is complete the CPU is interrupted via of the 6522 IC20 pin 18 which generates an IRQ 1C20 pin 21 External Connections The connections are shown in Table 8 See the technical description and circuit diagram in the appropriate user guide or service manual Pin Function Pin Function 1 45v 9 LPSTB 2 OV 10 PBI 3 OV 11 VREF 4 CH3 12 CH2 5 Analogue Gnd 13 PBO 6 OV 14 VREF 7 CHI 15 CHO 8 Analogue Gnd Table 8 Connections for Analogue Port Note that the input voltages should be within the range OV to 1 8V voltages outside this range may 54 ACW SERVICE MANUAL Issue I I O Processor board cause damage to the ADC Although an internal reference voltage is provided for the greatest accuracy an external temperature compensated reference should be used If the full 12 bit accuracy is required great care must be taken with screening the leads and securing analogue ground connections For further details of the ADC refer to the manufacturer s data sheet Transduction factor The digital output varies from 0 to 65520 in steps of 16 to correspond to voltages between and 1 8V Conversion time 10 milliseconds per channel Associated digital inputs The digital inputs may be used to interface to a switch to ground or to a TTL signal Software Interface BASIC the ADVAL analogue to digital conversion value function is provided PANOS OSBYTE 16 selects the number of active chan
112. able to one side as necessary withdraw the PCB from the base of the ACW Installation is in reverse order 2 4 10 Plastic base assembly A plastic base assembly holds the monitor contrast potentiometer the volume control potentiometer the loudspeaker and the Winchester cooling fan To service components on this tray it is recommended that the cradle assembly is pivotted beyond its intermediate position 1 To do this ensue that a piece of soft material such as a block of sponge rubber 150mm thick is placed in front of the ACW to act as a supporting bed for the CRT as it swings over into an upright position 2 A 6mm spanner box spanner or small adjustable wrench will be needed to unscrew the self locking nut from the middle of each stay Keep the two nuts and the two nylon washers in a safe place ready for re assembly 3 The components on the plastic base assembly can now be reached Depending on the components to be replaced or repaired the task may be made easier by removing the tray from the case Four self tapping Philips screws hold the tray down into the case 4 Place a sheet of card or similar material over the I O processor to prevent solder splash damage 5 Note the colour coding and polarity of the wiring loom to the faulty component Unsolder these wires 6 Remove the faulty item The loudspeaker is held down with silicon rubber adhesive and can be prised out of the tray with a screwdriver The lower cooling fan is held
113. ace A dedicated floppy disc interface using the 1770 controller IC A dedicated network interface the Acorn ECONET A speech upgrade is available using the 5220 speech IC to generate predefined words and sounds through the built in speaker 34 ACW SERVICE MANUAL Issue 1 I O Processor board Figure 4 1 1 I O Processor Block Diagram 553800 b 3084 YIS viov O O 7 5 311355 9 3Q0v 3n901VNV 2303 0221 1i3NO231 33 ACW SERVICE MANUAL Issue 1 Chapter 4 4 1 2 Power requirements 5 voltage 12V voltage 5V voltage 4 1 3 Display outputs 5V DC 0 1 12V DC 10 5V DC 1 10 Colour monitor marked RGB RGB signals CSYNC signal 4 1 4 RS423 Line length Input impedance Baud rate TTL type levels TTL type level ve ve going link selectable 1200m maximum gt 4k ohms 19200 maximum guaranteed up to 9600 4 1 5 Cassette interface Output impedance Input impedance Output level Dynamic input range Motor control Baud rate Less than ohms Greater than 100k ohms Nominal 200mV peak to peak 70mV RMS Nominal 50mV to 5V peak to peak 25 to 15dB OdB 350mV RMS By miniature relay within computer Contact rating at 24 DC 300 or 1200 baud using standard CUTS tones 1200 and 2400 Hz tones 4 1 6 Analogue to digital convertor Resolution Full scale input voltage VREF
114. ally lower the main chassis taking care not to trap any cables The drive can then be removed through the front aperture Installation is in reverse order Make sure that cables are not trapped or pinched by the chassis stays Floppy disc drive 1 Disconnect the ribbon cable from the drive Disconnect the power lead at the disc drive end 2 The floppy disc drive is held down to the disc tray by four Philips M3 screws Remove these taking care to support the drive from the front to prevent it falling through the front aperture 3 Still supporting the drive from the front partially lower the main chassis taking care not to trap any cables The drive can then be removed through the front aperture Installation is in reverse order Make sure that cables are not trapped or pinched by the chassis stays 2 4 9 110 Processor PCB To service the 6512A PCB it is recommended that the cradle assembly is pivotted beyond its intermediate position in the manner descibed in subsection 2 3 2 above 1 Remove the 7 Faston plugs carrying the DC power lines Remove the 5 IDC plugs from the furthest edge viewed from the rear of the PCB It is possible that on some models the middle IDC socket may be vacant Remove the keyboard plug which is approximately in the centre of the PCB Remove the loudspeaker and volume control plugs 2 and 3 wires Remove the monitor plug 5 wires 2 Remove the 4 Philips head screws securing the PCB and moving the ribbon c
115. amp FC and amp FD The TUBE interface provides buffered address and data lines for connection to the 32016 processor The TUBE itself is a fast parallel bidirectional FIFO and is resident on the 32016 PCB The keyboard is read through half the A port of a 6522 versatile interface adapter IC20 Sound is produced by the 76489 1C38 a four channel sound generator chip Speech may be generated using an optional 5220 speech processor IC29 and 6100 word PHROM IC37 4 2 2 CPU timing 16MHz crystal controlled oscillator and half of IC26 generates clock pulses which are divided by circuitry within the video processor ULA IC53 Pins 4 5 6 and 7 of the video processor provide IMHz 2MHz 4MHz and 8MHz outputs respectively SMHz 4MHz and 2 are used to generate RAS and CAS for the DRAMs and 6MHz for the TELETEXT chip IC59 2MHz is used to generate the main system clock 2E IMHz is used directly by the TELETEXT chip and also in conjunction with 2MHz to generate the phase shifted 1MHz system clock 1E from IC25 The CPU is normally clocked at 2MHz The 6512 IC42 requires a two phase non overlapping clock on inputs phil pin 3 and phi2 pin 37 see figure 4 2 2 a 38 ACW SERVICE MANUAL Issue 1 1 O Processor board Figure 4 2 2 a Clocks phil and phi2 2M 0 D 01 D Phil and phi2 are generated by IC33 two gates of which are used to build an R S latch Not2M from IC26 is used to set and reset the R S lat
116. and 1 0 1 The data bus is buffered and inverted in the read direction by an octal 3 state inverting buffer which is enabled by YO of which is the read data signal see previous subsection The eontrol signals used by the SCSI interface are available for reading by the host microeomputer They can be latehed into 1C4 an octal transparent latch when it is enabled by Y1 of 1C7 The control signals appear on the data bus in the following positions ACW SERVICE MANUAL Issue 1 115 Chapter 6 0 MSG D1 BSY D2 0 D3 0 D4 NIRO see 5 3 1 D5 REQ D6 I O D7 C D All these control signals are inverted either by IC15 or 1C9 prior to being latched so all values read from the data bus are active high 6 7 3 Termination The Host Adapter PCB carries 4 resistor packs RP1 to RP4 which are used for terminating the various buses and eontrol lines terminates the SCS1 lines from the disc controller board IMPORTANT RP2 RP3 and RP4 terminate the 1MHz bus lines and are fitted if the Winehester is the only peripheral on the 1MHz bus if external peripherals are attatched to the 1Mhz Bus then these terminators should be removed and retained 6 8 Test equipment and formatting A BBC microeomputer system or ACW can be used as a test station IMPORTANT The Winchester MUST be operated in a horizonal position Test Equipment The test equipment which may be required is BBC Microcomputer model B or
117. anoeuvure the bottom front edge of the upper unit until it begins to mate with the lower case 5 Keep the front mated and start to close the UPPER case whilst at the same time flexing it s side which will allow it to clip into the LOWER case 6 Clip the rear interconnection panel into the upper case 7 Fasten the unit together with the rear plastic clips and seal the unit by replacing the metal safety clips together with their Phillips headed screws 8 Check that the fan works 2 4 Removing and installing assemblies DISCONNECT THE ACW FROM THE MAINS POWER SUPPLY WARNING The DC power supply is connected to the PCB boards using Faston connectors and identical posts are used for the positive and the OV supply All Faston connectors must therefore be checked for correct polarity connection before the DC power is supplied to the various PCBs The wires are colour coded as follows RED 5V BLACK 0V PURPLE 5V ORANGE 12V The RED BLUE pair provides a nominal 12V for the lower cooling fan 2 4 1 The power supply Remove the upper case as detailed in section 2 3 2 Unplug the 11 wire Molex DC connector and the 2 wire Molex 240V connector While supporting the PSU remove the four countersunk Philips screws securing it the the cradle Take care to avoid skin contact with the heat conducting compound between the PSU and chassis Installation is in reverse order and a new supply of heating compound should be liberally applied to
118. arness with polystyrene chips or air bubble cushion sheeting used to protect sensitive areas such as the monitor screen and the keyboard keys The package should be handled gently as befits equipment containing a VDU and a Winchester drive 22 Installation At installation or after a bench service the ACW should be sited in accordance with the following notes e A strong and rigid worksurface should be provided with adequate room to tilt and swivel the ACW on its base The worksurface should not be covered with any loose cloth or mat which might impare the efficiency of the air intake within the swivel base working environment should be clean away from direct sunlight or direct heat sources e Adequate space must be left surrounding the machine for a free flow of air and a minimum of 150mm six inches of free space above the machine is advised Ventilation slots should not be covered power outlet used for the ACW should not be shared by equipment containing electric motors or thermostatically controlled circuits since these tend to generate electrical noise Sources of strong magnetic fields such as powerful loudspeakers should be kept clear of the floppy drive and the floppy disc storage area ACW SERVICE MANUAL Issue 1 11 Chapter 2 Local printers and other peripherals should be sited within easy reach of the ACW where they be connected by means of interconnecting cables 2 2 1 Rear panel co
119. at 2MHz inverse of phi2 and NCS goes low and stays low for a time 8 Check all clocks from video processor 8M 4M 2M 1M 9 After BREAK check CRTC NCS pin pulses low pin 25 IC78 10 If all the above checks pass then the machine should do more than exhibit the symptoms stated in situation a Situation b The screen synchronises no noise but there is only a flashing cursor in the top left corner Results usually caused by a keyboard fault Check that the keyboard is connected correctly Situation c The banner message appears but is incorrect or incomplete The correct banner message after CTRL BREAK is Cambridge Workstation Acorn ADFS gt The correct banner message after CTRL p BREAK is Cambridge Workstation ACW DFS gt Results the CPU is running and is accessing the OS Use PET tester if available see information manual supplied to dealers If the banner message is fragmented then check the CRTC address lines for shorts If the message gives the prompt ACW SERVICE MANUAL Issue 1 61 Chapter 4 Language where BASIC is fitted in the example above check S13 and also check the Pg latch Situation d The machine does a start up beep and the caps lock LED comes on but there is no display Results the video circuitry is faulty Situation e There is no fault on power up Results most I O faults will not stop the computer and display from working Use a PORT tester to find out which
120. ating point instructions together with the required operands are passed to the FPU for execution The TCU provides a number of system clocks at half the crystal frequency In addition it controls memory access cycles in conjunction with some additional TTL based circuitry The TUBE R is a communications channel to the host or I O processor Data passes through the tube under program control an interrupt scheme is used on the 32016 side of the TUBE and polling is used on the Host side The memory drive banks provide multiple buffered copies of the timing signals required by the DRAM array ie AO gt A8 RAS CAS WE Buffering is required because of the high loading presented by the memory array The socketed memory array is organised as four 1 2 M Word sections Each section is further divided into low and high byte banks The Configuration links are read by software and indicate the presence or absence of an optional hardware like the FPU 5 3 Detailed Circuit Description Refer to the circuit diagram in the appendix while reading the following sections 5 3 1 Clock scheme The 532201 Timing amd Control unit produces a two phase MOS compatible clock and 2 These are used internally by the NS32000 family only For general use throughout the remainder of the circuit the TCU provides CTTL which is a TTL compatable replica of clock All the above mentioned clocks run a half the crystal frequency In order to reduce
121. ay D Type IDC 37 way I O PCB Function 37 way I O PCB Function D type IDC D type IDC 1 1 OV 20 2 R NW 2 3 OV 21 4 3 5 OV 22 6 NNMI 4 7 OV 23 8 NIRQ 5 9 OV 24 10 NPGFC 6 11 OV 25 12 NPGFD 7 13 OV 26 14 NRST 8 15 OV 27 16 Analog Input 9 17 OV 28 18 DO 10 19 DI 29 20 D2 11 21 D3 30 22 D4 12 23 D5 31 24 D6 13 25 D7 32 26 OV 14 27 AO 33 28 Al 15 29 A2 34 30 A3 16 31 A4 35 32 AS 17 33 6 36 34 7 18 35 37 36 19 37 No connection 149 ACW SERVICE MANUAL Issue 1 Connector pinouts PL13 Keyboard 25 pin D Type IDC Pin Function 1 OV 2 BREAK 3 1E 4 keyboard enable 5 SD4 6 SD5 7 SD6 8 SDO 9 SDI 10 SD2 11 SD3 12 SD7 13 cassette LED 14 CA2 to generate IRQ 15 45V 16 shift lock LED 17 caps lock LED ACW SERVICE MANUAL Issue 1 145 Appendix 32016 Memory Chip Address Address IC Numbers High byte Low byte lst M Byte 000000 07FFFF 59 to 66 51 to 58 080000 0FFFFF 75 82 67 74 2nd M Byte 100000 17FFFF 91 98 82 90 180000 1FFFFF 107 114 99 106 3rd M Byte 200000 27FFFF 123 130 11 5 122 280000 2FFFFF 139 146 131 138 4th M Byte 300000 37FFFF 155 162 147 154 380000 3FFFFF 171 178 163 170 146 ACW SERVICE MANUAL Issue 1 Appendix Osilloscope Sync Aid for 32016 The bus activity during execution of any program incl Pandora will be very random and difficult or impossible to follow with an oscilloscope Th
122. by VR218 2 The picture width has been set by L202 3 The monitor is positioned in its place of use Note VR220 will shift the picture right or left 5 Width L202 CAUTION Care should be taken when adjusting this component as high voltages are in close proximity to it in particular at the tripler and line output transformer A Using a non metalic trimming tool adjust L202 to give the correct picture width 6 Height VR306 A Raster under scan and over scan is adjusted by VR306 7 Field linearity VR312 A Adjust VR312 to give a linear picture in the vertical direction Note Use a cross hatch grid test generator to obtain best results 8 Field shift VR321 A The raster position in the field scan direction is adjusted by VR321 9 East West correction VR328 A Adjustments of VR328 will acheive straight verticals on the left and right hand sides of the picture 10 Focus Located on the end of the tripler module Set the brightness control to the normal viewing level then make the focus adjustment 11 Adjust colour background control black level Note An AVO 8 multimeter and or an oscilloscope are required for these adjustments Prepare to adjust background colour controls 1 Set user contrast VR111 brightness VR134 and AI VR932 fully anti clockwise 2 Disconnect RGB sync inputs B Adjust red green and blue 1 Adjust VR906 for red cathode black level volts 2 Adjust VR914 for green cathode black
123. bytes giving a range of approximately 1012 The clock may be accessed as follows PA NOS set and show utilities are used to set and read the clock After a hard reset the clock is in an unset state Programs running under Panos may use various Panos library functions BASIC TIME is a pseudo variable which sets or reads the lower four bytes of the internal clock LISP The function timeofday returns a string giving the time of day date returns a string giving the date The timer may accessed by programs running under Panos as follows OSWORD 4 sets the timer to the value in the five byte parameter block The timer counts upwards and can initiate an interrupt i e asynchronous event 5 when it reaches zero Programs running under Panos can respond to this event For BASIC FX14 5 and FX13 5 enable and disable this event respectively ACW SERVICE MANUAL Issue 1 I O Processor board 4 4 Upgrading the PCB 44 1 Inserting or changing ROMs Refer to the I O Processor PCB overlay in the Appendix The six I O Processor ROMS arc located in the top lefthand corner North West as part of a group of eight 28 way I C sockets The sockets bear the numbers IC29 IC37 IC35 44 IC57 IC62 IC68 and THE OPERATING SYSTEM ROM CAN ONLY WORK IN IC 71 SOCKET TWO SEPARATE SOCKETS 1C 29 AND 37 ARE FOR SPEECH UPGRADE ROMS ONLY See next subsection ROM selection Each of the six sockets can hold either a 8Kbyte 64Kbit 16Kby
124. c Verify Cheeks that there are no errors on an ADFS floppy disc ADFS Winchester Utilities Archival to DFS Transfers files and directories from ADFS winchester to DFS floppy dise Archivel Recover Returns files and directories from DFS floppy to ADFS Winchester Worn Formats a Winchester disc This operation erases the entire contents of a hard disc and is COMPLETELY IRREVERSIBLE there is no way that files lost by re formatting ean be retrieved you have been warned See the Appendix on FormaWing Discs Werify Checks a Winchester disc for defects ADFS General Utilities Catall Lists the contents of all the directories on a dise floppy or Winchester Copyfiles Copies files from one filing system to another Dircopy Duplieates part or all of an ADFS directory strueture in another part of the ADFS directory structure Exall Lists the contents of all the directories on a dise Similar to Harderror Removes a sector of a Winchester disc containing a hard error from the free space map Recover Enables accidentally deleted tiles to be recovered Can NOT recover after Formatting Weditor Enables the data in any sector of the Winchester dise to be displayed and if neeessary changed ACW SERVICE MANUAL Issue 1 123 Appendix Using the Utilities The utilities are written in BBC BASIC and run on the 6502 I O processor They make use of 6502 assembler routines and will not run under 32000 BASIC The programs may be used
125. ce is provided by the conducting TR907 TR907 is turned off during line and field flyback thereby forcing video outputs off 7 R937 D117 and D118 are responsible for sensing beam current ACW SERVICE MANUAL Issue 1 31 32 ACW SERVICE MANUAL Issue I 4 I 0 Processor board The ACW s uses the 6512A as its I O processor The PCB board is the same as that used in the BBC Model B microcomputer except for a small number of ommissions the most noticable of which is the UHF Modulator and associated components 4 1 Specification 4 1 1 The microcomputer Internal loudspeaker driven from a 4 channel sound synthesis circuit with ADSR envelope control A BNC connector supplies a composite video output to drive a black and white or PAL colour monitor 6 pin DIN connector provides separate RGB and sync outputs at TTL levels RGB are all high true and sync is link selectable as high or low true pulse duration 4 0 microseconds A standard audio cassette recorder can be used to record computer programs and data at 300 or 1200 baud using the Computer Users Tape Standard tones The cassette recorder is under automatic motor control and is connected to the computer via a 7 pin DIN connector An interrupt driven elapsed time clock user settable 6512A processor running at 2MHz 64K of read write Random Access Memory RAM allowing a shadow screen mode and 12K paged RAM in any mode Read Only Memory ROM integrated circuit containing the
126. ced by wire mod Link Ctr amp RH pins LK2 Reset Links reset back to host processor Not installed in ACW MLI MMU NADS gt NPAV Link if MMU not installed ML2 MMU NHLDAI gt NHLDAO Link if MMU not installed CIRCIR PAL bypass Link if TBP24510 1C182 not installed CNM CNM PAL bypass Link if TBP24510 IC182 not installed MLWIA Wait state on all RAM cycles Link if Xtal is gt 16Mhz MLW 1B Wait state on all EPROM ROM cycles No link required 512 Refresh rate Link b 4mS normal at 8 Mhtz 13 EPROM size Link middle amp lower pins for 16K byte EPROMs S14 RAM Chip size Right hand pair 64k Left hand pair 256k 515 RAM Chip size Right hand pair 64k Left hand pair 256k S16 RAM CHIP size Left hand pair 64k Right hand pair 256k PL3 amp PL3A Alternative positions for TUBE disable wire from Keyboard 5 6 Expansion instructions 5 6 1 Memory All PRODUCTION ACW443s are supplied with 4 M Bytes RAM installed The memory upgrade kit contains sixteen 256k bit DRAMs which have an access time of 150nS The memory must be expanded contiguously there must be no gaps in the address map To do this the upgrade kits must he inserted in the order shown in Figure 5 6 1 The first 512K upgrade inserted into sockets 1 in the figure This corresponds to 1C83 IC98 on an Issue 1 board ACW SERVICE MANUAL Issue 1 97 Chapter 5 It is strongly advised that DRAMs from different manufacturers
127. ch which toggles at 2MHz unless a third gate from IC33 blocks the N2M signal During 2MHz operation the phi2 clock corresponds to N2M the inverse of 2M from the video processor When accessing slow devices 1MHz extension bus ADC VIAs 6845 and serial processor the clock is stretched to give a pseudo 1MHz cycle The system 1MHz clock 1E is generated in half of IC25 from the IMHz and 2MHz outputs of the video processor The other half of IC 25 is used to synchronise the transition from 2MHz to clocking Each 1 MHz peripheral select line is connected to an input of NAND gate IC41 If any input of this NAND gate is taken to logic 0 then a IMHz CPU cycle will occur For 1MHz cycles phi2 is held at logic 1 until the E signal is synchronised The cycle ends with both phi2 and 1E falling together There are two ways in which the transition from 2MHz to 1MHz takes place depending on which phase E was on when the request was received from IC41 see Figure 4 2 2 b ACW SERVICE MANUAL Issue 1 39 Chapter 4 Figure 4 2 2 b 2MHz to transition 2E 1E sync 1M 4 2 3 Reset circuitry The system has two reset circuits one is a general reset from a 555 timer IC43 the other is an RC network which just resets the system VIA IC20 on power up This allows the software to detect the difference between a power on reset and a BREAK key reset The keyboard BREAK key connects via S10 a PCB made link to the 555 timer
128. colour graphics and 20 x 32 text ode 6 Mode 134 40 x 25 2 colour text only ode 7 Mode 135 40 x 25 Teletext display screen access is via the I O processor operating system Shadow mode gives 32K BASIC program RAM less workspace to the user in any screen mode The shadow screen mode offers equivalent display sizes to the standard mode 0 to 7 screens but using an auxiliary memory area the shadow RAM In shadow display modes modes 128 to 135 BASIC or a user program is free to use all memory between OSHWM PAGE and amp 7FFF plus the 12K bytes of sideways paged RAM The 12K paged RAM is available to the user in any screen mode shadow or non shadow The ACW starts up in shadow mode Serial interface to RS423 standard The new standard has been designed to be inter operable with RS232C equipment Baud rates are software selectable between 75 baud and 19200 baud guaranteed up to 9600 baud An 8 bit input output port with 2 control bits Four analogue input channels Each channel has an input voltage range of to 1 8V The conversion time for each channel is 10 milliseconds The resolution of the ADC chip is 10 bits 1 MHz buffered extension bus for connection to the Winchester the mouse and to a variety of external hardware such as a TELETEXT acquisition unit and IEEE 488 interface Buffered interface for connection via the TUBE to the 32016 processor PCB CENTRONICS compatible printer interf
129. cription The only part of the Winchester Disc system which is serviceable by Acorn dealers is the Host Adapter PCB see appendix for circuit diagram and its connectors and eables etc This is an interface between the asynehronous SCSI interface to the disc controller board and the synchronous 1MHz expansion bus interface on the host microcomputer used by the Winchester Disc filing system The following eircuit description will provide enough information about the dise eontroller board and the 1MHz expansion bus to allow a full understanding of the operation of the Host Adapter board For the full specifieation of the SCS1 interlace see the relevant literature 6 5 1 The disc controller board The disc controller used in the Winchester Disc unit is a device which will send or accept parallel byte data to or from the host microcomputer via IMHz bus and Host Adapter and will read or write this data serially to or from the hard disc It contains a 256 byte cache memory hereafter referred to as the sector memory because 1 disc sector 256 bytes A connection diagram for the dise eontroller board is given in figure 3 below A W CERVICE MA NITAT Toona 1 Winchester Floppy Disc Systems In the following deseription the Host Adapter is known as the initiator and the dise controller is known as the target 6 5 2 SCSI control and data lines The 8 control and 8 data lines on the SCS1 side of the controller shown on the right side
130. d 105 emmitters directly Hence any increases in CRT beam current above a preset limit causes an automatic reduction in picture brightness The brightness of the display is adjusted by VR134 enabling parallel adjustment of RGB and black levels within a or 20V range from a 700 nominal TR102 is a fast switching transistor used to derive mixed blanking pulses for the flyback blanking of video information The base is driven from a potential divider mixer network from a line flyback pulse and from a frame flyback pulse Line flyback is advanced in phase with C225 to allow for transistor switching delays D107 holds TR102 in a semi saturated state IC101 is also used to provide the following sync options 1 TL102 is in its non active position Composite negative sync Composite negative sync is fed in on PL101 pin 7 allowing pin 2 of IC101 to be pulled high where upon IC101 performs a sync inversion and provides an attenuated positive sync waveform for driving sync separators of IC201 via R201 and TL106 2 TL102 is in a non active position Separate negative line and field sync pulses Line sync pulses are fed in on pin PL101 pin 5 IC101 performs an exclusive OR function the output being an inverted composite sync waveform 3 TL106 is switched to inverse field option Separate positive line and field syncs These are fed in on 101 pin 7 is in its grounded position IC101 provides an attenuated and buffered line sync f
131. d ICs may be changed whenever their breakdown is detected The disc drives floppy and Winchester and the power supply module should always be replaced as a complete unit in the field Note that the replacement of the monitor tube represents an implosion hazard and should not be undertaken in the field 1 3 3 Power supply 5 output voltage 4 9 to 5 2V 12 output voltage 11 4 to 12 6V 1 3 4 Environmental Minimum operating temperature 0 degrees C Maximum operating temperature 37 degrees C Minimum storage temperature 30 degrees C Maximum storage temperature 60 degrees C Maximum operating humidity 80 RH at 35 degrees C Maximum storage humidity 80 RH at 55 degrees C Operating altitude 0 to 1800 metres above sea level Storage altitude 0 to 3500 metres above sea level Thermal gradient 10 degrees C per hour 6 ACW SERVICE MANUAL Issue I Introduction 1 3 5 The keyboard The keyboards of the ACW and the BBC Microcomputer Master are similar differing only in layout The features of the keyboards are outlined in the Cambridge Workstation Welcome Guide Part No 0420 000 1 3 6 Auto Repetition Most keys auto repeat the exceptions are ESCAPE CTRL SHIFT CAPS LOCK SHIFT LOCK and the function keys The auto repeat rate and the delay before auto repetition can be set by the Panos Configure utility 1 3 7 Caps Lock The state of CAPS on entering Panos can be set by the configure utility 1 3 8 The BREAK Butt
132. d and delayed 4M and 8M clocks respectively The output signal on pin 3 is the precursor of the 6MHz clock used by the TELETEXT display circuit See IC63 o p 3 2 o p pin 8 is used to drive the RAM NCAS clock NotCAS is timed from the system 4M clock NCAS is held high if the CPU cycle is a VIDPROC write by a logic low from IC23 pin 8 3 o p pin 11 is used to modify the duty cycle of the 16MHz clock to suit the needs of the Ferranti ULA IC53 Note the passives R36 R37 R38 C14 D5 D6 D7 may also be needed for the Ferranti IC ULA Video processor IC This component contains a 4 bit divider which generates the 8 4 2 and 1MHz system clocks It also selects the RGB signals internal for modes 0 to 6 and external from 59 for mode 7 The RGB can be inverted if link S14 is made South The main function of the IC is parallel to serial conversion of the display data read from RAM and the logical translation of the pixel code to the 3 bit RGB code of each display pixel The translation process varies with screen resolution mode A pixel may be represented in RAM by 1 2 or 4 bits of data 7ALS273 Octal D type This IC latches the RAM data at the end of alternate VDU phases It is needed to hold the data for the teletext IC which has long data setup and hold times The latch is clocked 500ns before the SAA5050 IC59 giving equal setup and hold times of 500ns 1 55 56 60 61 64 65 66 67 4164 641 x1 bit 1205 access DRAMs These eight ICs ar
133. dress Strobe NADS low While NADS is low the address de multiplexing latch IC8 9 LS373 is transparent and the address passed through to address decoding logic LS138 and memory driver banks When NADS returns high the address is held in the de multiplexing latch Note It is not necessary to latch the top eight address bits as they remain valid during the entire bus cycle ACW SERVICE MANUAL Issue 1 95 Chapter 5 Phi 1 Phi 2 CTTL AD16 23 ADO 15 Read 0 15 Write ADS DDIN Figure 5 4 1 Non Memory Managed Bus Cycle 1 Read data sampled by CPU ___ addr MV data N 22 write 22 V MV N read 32016 Processor 5 4 2 Row address RAS Cycle While NRAS is false HI the RAS driver bank is enabled and the upper 9bits are supplied to the DRAMs In response to NADS going low the TCU after one cycle generates NTSO This in turn causes NRAS to go low and the row address is strobed into the DRAMs 5 4 3 Column address CAS Cycle NRAS going low turns off the row address buffers 2122 25 26 and turns the column address buffers 1 35 36 37 38 The delay through 1050 Pins 1 2 3 and IC24 Pins 11 10 provides the necessary 15ns Row address hold time required by the DRAMs NTSO low releases the set input of IC15 and allows the next CTTL edge to generate CASTIME If the address is within the bottom 4 M bytes A22 A23 0 then N
134. ds the link value to the station ID eg all links fitted gives 0 68B54 Serial data link controller ECONET only This IC is an ADLC advanced data link controller It is responsible for transmitting and receiving serial data to and from the ECONET Each byte of an ECONET transfer is under interrupt control and is managed by a network filing system The NRTS signal is controlled by software It enables the ECONET line driver IC91 NotDCD is driven by a clock detection circuit to allow a program to detect the network clock NotCTS is tested to check for network data packet collisions see comments on collision detection under IC93 NotIRQ is used as an NMI interrupt which is enabled disabled under program control see IC69 and IC70 4k7 pull up resistor R59 is fitted when IC81 is present as NIRQ is an open drain output 6850 ACIA UART A UART is a serial asyncronous interface circuit which can both transmit and receive data The 6850 is used for parallel to serial data conversion for either the cassette interface or the RS423 interface Three handshake signals arc available NDCD NRTS and NCTS These can be tested by the controlling program to determine interface status Two clock inputs allow the transmit and receive bit rates to be set independently The two clocks are generated in the SERPROC IC85 741 586 Quad two input EXOR 1 o p pin 3 is part of the TV colour PAL encoder circuit One of four EXORs is used to select the phase of
135. e and diconnect it from the host adaptor board The complete 1 MHz cable can now be removed It will no longer be required 4 The Mouse Adaptor PCB ean now be installed using the host adaptor PCB as an example of the style of fitting Its position is between the host adaptor PCB and the front edge of the component tray It will bridge over ribbon cable going to the adaptec PCB Place the four PCB pillars in the pre drilled holes in the metalwork and place the insulation sheet on the pillars over the ribbon cable Fit the mouse PCB Its orientation is such that the edge with the two connectors labelled PL2 and SKI is closest the the I O Processor 5 Using the 34way 60mm ribbon cable connect the mouse PCB to the host adaptor PCB This is the short 1 bus link it connects to plug PL3 on the mouse 6 The new 1 MHz bus cable can now be installed The 34way IDC connector at one end connects to PL2 on the mouse PCB the 1DC in the middle connects to the I O Processor board and the D type connector at the other end fits into the rear panel Use the original screws to fit the D type connector The folds in the cable should be similar to those of the original and it should follow the same cable run from the PCB tray to the rear panel 7 The 9way mouse ribbon cable can now be installed The IDC connector at one end is connected to SKI of the mouse PCB and the D type connector at the other is mounted on the rear panel using the fitti
136. e display outputs are available RGB consists of CSYNC and RED GREEN BLUE at TM voltage levels Each colour is either on off or flashing giving sixteen displayable colour effects ie eight static colours and eight flashing colours VIDEO output is a summation of RGB to give a grey scale luminance only If link 526 is made the chrominance component colour information is added to the VIDEO output Serial input output is provided by the cassette port and RS423 port Both are controlled by the 6850 asynchronous communications interface adapter IC82 and a ULA called the serial processor IC85 Analogue input is fed to the four channel 10 bit ADC chip 84 A local area network facility is provided by the ECONET circuitry centred on the 68B54 advanced data link controller IC81 The floppy disc controller is the 1770 IC16 The 1770 operates in either single density FM or double density mode and includes a data separator and disc speed decision logic ICs 1 2 3 4 9 and 15 are not required with a 1770 The CENTRONICS compatible printer interface is based on half the A port of a 6522 versatile interface adapter IC10 IC5 buffers data sent to the printer The User Port is connected directly to the B port of the same 6522 0 The extension bus is a fully buffered interface to the CPU operating with lus transfer cycles The bus appears as a 512 byte address block in the processor I O space at pages
137. e enable pin 19 IC14 goes low ACW SERVICE MANUAL Issue 1 1 Processor board Change line 50 of the program to 50 LDA amp FF and check that all the buffered data lines go high at some point after the enable pin 19 1C14 goes low If these tests do not give correct results then check the data bus buffer IC14 and the PCB tracks and connections to PL12 50 LDA amp AA and 50 LDA 655 can also be tried These correspond to output bit patterns 10101010 and 01010101 0 4 R NW and 2E can be looked for on pins 12 9 7 5 3 16 and 18 of 1C13 These signals should be the same as the system signals but delayed by 10 15ns 4 7 16 Analogue to digital conversion Use a PORT tester to verify that the ADC circuit is faulty Check VREF by measuring the voltage between pin 8 IC84 and ground This voltage should be approximately 1 8V Look for shorted or broken tracks if it is not Connect two known working analogue joysticks to the D type connector SK6 used for the ADC Type in and RUN the following program 10 VDU 23 1 0 0 0 0 20 CLS 30 REPEAT 40 PRINT 0 0 ADVAL 1 5 4 50 PRINT 0 2 ADVAL 2 5 4 60 PRINT 0 4 ADVAL 3 SPC 4 70 PRINT TAB 0 6 ADVAL 4 5 4 U 80 UNTIL 0 Move the joysticks and see if you can get numbers in the range 0 to 65520 on each of the 4 channels In practice it may well not be possible to get near either one or both of the end values but a good
138. e following program when run in the BBC Micro or ACW resets the processor at a few hundred Hertz This causes the processor to repeat the start up sequences rapidly and provides a triggering mechanisim for an oscilloscope The program is written in BBC BASIC 10 amp FEEO amp 7F 20 REPEAT amp FEEQ 6 0 amp FEEO amp 20 UNTIL 0 This should be entered as follows 1 Turn off the Coprocessor 2 Press BREAK 3 Enter the program above exactly as shown 4 RUN the program 5 Turn on the Coprocessor again The 32016 is now reseting about 500 times a second Note that nothing will be displayed on the screen to indieate this It is now possible to follow the start up sequence triggering the oscilloscope on the RISING edge of one of the reset signals ie NRSTO First look for this signal on the reset pin of the CPU pin 34 It will not be possible to obtain a perfectly stable signal because for various reasons the BBC 6502 does not always execute line 20 in the same amount of time and the execution of the start up sequence in the 32016 is disturbed by memory refresh cycles ACW SERVICE MANUAL Issue 1 147 Appendix I Test Software Numbers Title Media Code 32016 Memory test DISC 80 Track DISC 2201 257 32016 Memory test EPROM EPROM ROM Low 2201 229 High 2201 230 148 ACW SERVICE MANUAL Issue Appendix J Test program fault reports Faults reported by the Romtest programs take the following format
139. e scissors mechanism on both sides and allow the top unit to close DO NOT USE EXCESSIVE FORCE 2 Using a large flat point screwdriver push the rear lower quarter turn screw into the locating hole in the upper unit and locate the slot in the quarter turn screw body over the mating bar DO NOT TURN THE QUARTER TURN SCREW UNLESS IT IS CORRECTLY MATED 3 Turn the quarter turn screw until it locks 4 Carry out the same operation on the opposite side of the ACW 5 Replace a side tray vertically into its supports on both sides and then press the tray down checking that no cables are being trapped 6 Locate the tray s locking quarter turn screws into the upper unit and then gently rotate the quarter turn screws until they lock 7 Carry out the same operation on the other tray Replacing the Upper Case 1 Lower the upper case vertically over the ACW with the fan power lead on the OUTSIDE of the rear upper bracket and reconnect the lead to the fan power socket 2 Ease the fan under the bracket while lowering the case The fan can be viewed through the front VDU aperture DO NOT TRAP THE 40 WAY RIBBON CABLE FIXED TO THE OUTSIDE OF THE RIGHTHAND TRAY BETWEEN THE TOP AND BOTTOM CASES 16 ACW SERVICE MANUAL Issue 1 Assembly Packaging and Installation 3 Tilt the upper case slightly forward and ease the bottom edge of the black front bezel gently over the floppy disc locking lever which should be in the horozontal position 4 M
140. e the offset adder IC76 2 o p pin 12 enables the RAM data bus buffer IC49 and the RAM write signal The logic 1 request input from 1C40 pin 8 is gated with N2M to form NENM the 0 active RAM enable signal Not2M is used to ensure the enable is only active during the CPU phase ie while phi2 is high This avoids bus conflicts during phil Also it forces the RAM to be read only during VDU cycles Note the buffer is active for RAM or VIDPROC access During a VIDPROC write the RAM is disabled by holding NCAS at logic 1 see IC23 and IC52 741 5245 Octal buffer The RAM and VIDPROC data bus buffer This IC isolates the RAM data bus from the CPU data bus to allow VDU read cycles to occur without interference from the CPU data bus particularly during 1MHz device cycles Another important function of the buffer is to reduce the CPU data bus loading by isolating the RAM and VIDPRCC etc IC50 and 5 741 5257 Quad two to one data selector These two ICs select the RAS and CAS address signals from the CPU address lines The CPU 15 is not used The A15 input is the CPUSEL signal from the PAL 1C36 The CPU address is only valid during phi2 high because IC50 and IC51 arc disabled held tristate while phi2 is low phi2 low is the VDU RAM access period 2M is used as an enable to avoid loading the phi clocks IC52 74800 Quad 2 input NAND IC53 1054 1 o p pins 3 and 6 connected as an R S flip flop The set and reset signals are the inverte
141. e the system memory The RAM appears as a 32Kbyte block from amp 0000 to amp 7FFF A further 20Kbytes are used for a SHADOW screen memory The remaining 12Kbytes is ACW SERVICE MANUAL Issue 1 79 Chapter 4 IC57 IC58 IC59 IC62 IC63 PAGED in under program control as a sideways RAM Note IC96 DRAM SIL pack may be supplied instead of these ICs various 64 128 or 256Kbit paged ROM 32Kbyte device in this socket appears in sideways ROM slots 6 and 7 link 512 East Link 512 West allows 8 or 16Kbyte EPROMs ROMsS to be fitted This device can be any ROM or EPROM with NCE access time less than 250ns 741 502 Quad 2 input NOR 1 o p pin 1 mixes the video display sync pulses HS and VS to form NCSYNC The HS pulse is nominally 4us long VS is nominally 132us 2 TV rasters long 2 o p pin 4 gates the buffered CPU R NW with NENM to form the DRAM W signal which is buffered and inverted by IC19 to form NDW 3 o p pin 10 gates NDEN and RA3 from the CRTC to form the DIS EN signal DIS EN high enables the VIDPRCC generated RGB signals It does not affect mode 7 This signal is used to blank the display NDEN is high for periods outside the display window and so blanks the graphic mode borders RA3 is only active for the text only graphic screen modes modes 3 6 131 and 134 when the signal causes a 2 raster space between each text row In modes 3 6 131 and 134 the CRTC RA lines count from 0 to 9 other mod
142. ecifications of the Electronic Industries Association standard RS422A and RS423A The protocol used by the ACW is as follows a The I O Processor will transmit while CTS is asserted b The I O Processor will assert RTS when it is ready to receive Serial printers For driving printers the connections shown in Table 7 should be made ACW SERVICE MANUAL Issue 1 23 Chapter 4 RS423 connector printer 25 way connector Function Pin Function Pin data out B 2 to Receive data 3 CTS D 4 to data terminal ready 20 OR request to send 4 ground C 3 to signal ground 7 Table 7 Serial Printer Connections Software Interface The Panos configure utility may be used to select the parallel or the serial port and to set the baud rate and other parameters for the serial port Note that unless configure is run when Panos is installed or re installed attempts to print to other than a parallel printer will fail The network printer or a user supplied printer interface may also be selected The procedure for using a printer which does not conform to the standard parallel or serial interface is described in Section 10 6 of the Advanced User Guide for the BBC Micro the user print vector 4 2 16 Analogue to digital convertor The to D circuit is based on a uPD7002 1C84 which can accept upto four analogue inputs from SK6 The voltage reference is set by three silicon diodes D9 D10 and D11 which gives a typical full scale voltage of 1 8
143. ed by 256k bit DRAMs is provided by IC28 and is A18 during RAS and during CAS 5 3 8 Refresh Refresh is performed by inserting wait states into the memory cycle enabling the refresh address counter IC45 onto the bus and giving RAS Known as RAS only refresh IC33 is a binary counter which counts CTTL cycles and generates a refresh cycle every 16uS approximatly The RAS timing for this cycle is provided by the sequencer shift register based around IC20 and IC34 If a memory cycle is in progress when the refresh access starts it is delayed by NCWAIT and restarted when the refresh cycle ends 5 3 9 Interrupts The only source of interrupts is the TUBE so there was no need to use an Interrupt Control Unit ICU NS32202 in this design Additional protection against synchronisation failure is provided by latching NPIRQ and NPNMI on the rising edge of CTTL in IC183 before feeding the interrupts to the processor IC182 is a programable device which implements a simple state machine and is used to prevent interrupts from occuring during and just after certain instruction sequences This device is only necessary when some revisions of the Memory Manager are used and is bypassed by links LK CNM and LK NMI when not required 5 4 Memory access cycles 5 4 1 Memory access cycle without MMU Non memory managed bus cycles arc shown in Figure 5 4 1 A memory cycle is initiated by the processor putting an address on the AD bus and pulling AD
144. eed for IC201 via R201 Positive field sync information is fed directly to PL10I pin 3 sync 3 input by TLI06 B and R202 4 TL102 is in its grounded position Compositive positive sync The sync is fed in on PL101 pin 7 IC101 now provides an output in phase with the input and of a suitable amplitude for driving 1C201 directly via R201 TL106 ACW SERVICE MANUAL Issue I The monitor 3 5 3 Line timebase A Line oscillator function is based on IC201 providing three outputs 1 Horizontal drive pulses for control of line output stage 2 Vertical sync pulses compatible with synchronisation of IC301 field output IC 3 A sandcastle pulse providing burst gate and clamping information Sync Separator A TDA 1180P incorporates separate noise gate sync separators for line field syncs which accepts positive going sync pulses or negative going composite video on pins 8 and 9 B Output pulses from the line sync separator are used in conjunction with a sync gate to synchronise the line oscillator in a phase locked loop circuit Line oscillator phase detectors A The line oscillator is timed by a network of resistors and capacitors on pins 14 and 15 of IC201 used to derive a pulse of suitable mark space ratio for driving line output stages B IC201 contains two basic control loops each containing a phase detector 1 The first phase detector compares the output of the line oscillator with the incoming line sync p
145. eplaced by a new or reconditioned unit The floppy disc interface is contained on the I O processor board and the relevant section of the manual should be consulted if the interface is suspected to be faulty Mitsubushi drives arc fitted with an adaptor plate which should be removed from a faulty drive and refitted to its replacement 6 3 Winchester Drive The Winchester unit consists of a 20 Mbyte hard disc drive an ADAPTEC ACB 4000 Winchester Disc Controller and an Acorn Host Adapter Board which is an interface between the ACB 4000 and the ACW control PCB s 1 MHz expansion bus to provide storage and retrieval of data and programs on a non removable magnetic disc The Winchester Disc Unit is to the left of the ACW floppy disc drive viewed from the front The control electronics are accommodated in the left hand side tray assembly IMPORTANT After using the ACW the heads should be moved to the Landing zone before switching off the mains power The exact command that needs to be used to park the heads will depend on which program is in control ACW SERVICE MANUAL Issue 1 105 Chapter 6 For instance 1 From PANOS or user defined prompt Logoff ADFS RTN gt Quit Turn off Power 2 From PANDORA prompt ADFS RTN BYE RTN Turn off Power 3 From BASIC gt prompt gt ADFS gt BYE RTN Turn off Power 4 From UNKNOWN or IF IN DOUBT Pressing CTRL BREAK together will return to a promp
146. er frequency 4 43MHz which reduces the harmonics of the chroma colour signal 75159 Dual 5422 line driver I pin 2 used as an inverter Forms a true RTS signal to trigger clear the ECONET timer monostable 2 o p pins 12 13 drive the ECONET data lines with an RS422 differential signal An RS422 signal has nominal TTL logic levels two lines are driven to opposite logic states to give ACW SERVICE MANUAL Issue 1 IC92 IC93 IC94 IC95 IC96 I O Processor board differential signal transmission The gate is capable of driving a 50 ohm load tied to 2 5 volts When the ECONET interface is inactive not transmitting the driver is in a high impedance state A logic 1 on pin 9 enables the driver LM319 Dual analogue comparator 1 o p pin 7 senses the ECONET clock signal R78 introduces a small amount of hysteresis to avoid self oscillation of the comparator when no signal is present which would result in permanent clock present indication R63 is a pull up the comparator has an open collector output The comparator receives an attenuated clock signal which is also positively biased 125 134 140 141 form an attenuator approximately 10 1 R147 with R148 sets a bias of about 2 volts so the comparator input signals stay within the supply voltage 5 volts 2 o p pin 12 this comparator receives data from the ECONET line R73 is a pull up and R79 gives the comparator hysteresis R106 110 142 143 form an attenuato
147. er the COMPACT command are the reeommended values of the start page 16_30 and the length in pages 16_50 of the sereen memory used as a work area In shadow mode this will not be displayed Note that eompacting the hard disc may take several minutes and that during the process the disc aecess light will flash on and off 8 When the first pass compaction is complete the prompt will reappear 9 The Compaction algorithum used is not perfect and some free spaee will remain as fractional bloeks Type MAP RTN and a list of free spaces on the disc is displayed This list will get shorter each time the compaction program is run It is usually worth compacting until the list of free spaces contains only between half a dozen and a dozen entries This will usually involve running COMPACT two or three times 10 Compaction is required more frequently if the dise is nearly full ACW SERVICE MANUAL Issue 1 125 126 ACW SERVICE MANUAL Issue 1 Appendix B Formatting Discs WARNING Formatting Discs erases all data and is NOT reversible The Floppy Disc Drive The floppy disc drive is designed for use with 5 1 4 soft seetored double sided 80 traek dises The storage capacity of a floppy disc depends on the modulation system used for recording On the ACW the Advanced Disc Filing System uses modified frequency modulation This is often referred to as double density storage allows a capacity of 640 kilobytes for an 80
148. er the focus control eanh and the EHT tripler earth from the monitor PCB 3 Remove the tripler from the PCB It is secured using two M3 screws and nuts 4 Extend the focus control earth to 16cm using 1 0 6mm PVC wire single core black and the tripler earth to 8cm using 16 0 6mm PVC wire 16 strand black Resolder the two earth wires to the PCB and rest the tripler on the PCB Do NOT resolder the tripler EHT wire at this stage 5 Install the PCB into the chassis on the six nylon pillars 6 Remount the tripler on the chassis with the tripler EHT close to the line output transformer using the same two screws and nuts 7 Resolder the tripler EHT wire to the tag on the line output transformer without excessive or prolonged heat Ensure that this wire is not under tension Continue with the installation following the instructions for removal but in reverse order IMPORTANT Check that the CRT earth to CRT PCB lead is connected Damage to the monitor can occur if this is not fitted 2 4 4 The 32016 processor PCB 1 Remove the upper case as detailed in section 2 3 2 2 Release the quarter turn screw and lift and swing the side tray into the horizontal position 3 Disconnect the Faston DC supply 4 connections the IDC ribbon cable connector and the keyboard wire on PL9 from the PCB 4 Remove the 6 nylon screws holding the PCB and insulation sheet to the tray Installation is in reverse order Take care not to
149. eripherals connected to the 1 MHz bus and are assigned parts of the address space as shown in Table 5 50 16 00 to 16 FCOF 16 FCID to 16 16 FC14 to 16 FCIF 16 FC20 to 16 FC27 16 FC28 to 16 FC2F 16 FC30 to 16 FC3F 16 FC40 to 16 FC47 16 48 to 16 16 80 to 16 FC8F 16 FC90 to 16 FCBF 16 FCCO to 16 FCFE 16 FCFF 16 to 16 FD7F 16 FD80 to 16 FDFF Test hardware Teletext interface Prestel interface IEEE 488 interface Reserved for use by Acorn Cambridge ring interface Winchester disc interface Reserved for use by Acorn Test hardware Reserved for use by Acorn Available for user applications Paging register for memory expansion Reserved for use by Acorn Available for user applications Table 5 IMHz Bus Address Assignments ACW SERVICE MANUAL Issue I 1 Processor board ACW SERVICE MANUAL Issue 1 51 Chapter 4 4 2 13 TUBE interface The TUBE interface connects to the 32016 second processor via PL12 The signals present are the eight data lines five address lines AO to A4 R NW 2E NRS and The data lines are buffered by 1C14 and the address lines R NW and 2E are buffered by 1C13 The data buffer IC14 is enabled when a TUBE address amp FEEO amp FEFF is decoded by 1C21 this enable signal NTUBE being fed also to the TUBE connector PL 12 R11 is fitted so the computer OS can detect when there is no second processor present or powered on 4 2 14 ECONET E
150. es 31 1 4Kbytes of ROM 3 AKbyte of memory mapped input output and up to 44Kbytes of RAM 64Kbytes of RAM are installed on the PCB the extra 20Kbytes being used for the screen memory in shadow mode The memory mapped 1 0 is located in pages amp FD and of the CPU address space There are five sideways ROM sockets installed on the PCB each capable of taking an 8 16 or 32Kbyte ROM or EPROM ICs 35 44 57 62 68 When used with a 32K ROM each sideways ROM socket is decoded as two 16K sideways ROM slots A sixth ROM socket IC71 holds a 32Kbyte ROM which contains the operating system and BASIC The number of the ROM currently in use is held in the ROM select latch 1C45 64Kbytes of RAM are installed on the board in eight 64K by 1 bit DRAM chips ICs 55 56 60 61 64 65 66 67 Of this RAM 32Kbytes are always accessible to the CPU 12Kbytes can be paged into the sideways paged ROM space and the remaining 20Kbytes are used as screen memory in shadow ACW SERVICE NIJAT Issue 1 37 Chapter 4 mode Both CPU 42 and 6845 cathode ray tube controller 1C78 have access to the RAM Each access the RAM at full 2MHz clock speed by interleaving the accesses on alternate phases of the 2MHz clock The RAM is thus being accessed at 4MHz The 6845 accesses the RAM sufficiently to perform the refresh function Screen display is provided through the 6845 IC78 video processor IC53 and various encoding circuits Thre
151. es have only 8 raster lines per character row so the RA lines count from 0 to 7 therefore RA3 only goes high for modes 3 6 131 and 134 4 o p pin 13 is part of the colour burst monostable The o p signal enables the colour subcarrier during the colour burst interval R76 and C32 determine the pulse duration which is set at manufacture to be in the range 4 to bus D15 is used to discharge C32 quickly during the HS pulse period The monostable is triggered at the end of the HS pulse SAA5050 The Teletext display generator The SAA5050 contains the character look up ROM the raster counter and general control logic needed to generate the pixel information for mode 7 The IC receives character data codes from IC54 at a rate of 1MHz VS is used to reset the IC at the start of each TV field and so maintain display synchronisation particularly with the internal raster counter Character rounding is permanently on The NRAO line from the CRTC via IC24 gives the SAA5050 information on the current TV display field odd or even to allow character rounding various 64K 128K or 256Kbit paged ROM 32Kbyte device in this socket appears in sideways ROM slots 8 and 9 link S15 East Link 515 West allows 8 or 16Kbyte EPROMs ROMs to be fitted This device can be any ROM or EPROM with a NCE access time less than 250ns 741 586 Quad 2 input EX OR 1 o p pin 3 is part of the clock circuit 2 o p pins 6 and 8 are used to modify the CRTC add
152. get to initiator 0 0 message out phase initiator to target not used 0 0 0 message in phase target to initiator All signals active low O assertion 1 deassertion Table II Information Transfer Phases The information transfer phases use the REQ ACK handshake to eontrol information transfer eaeh REQ ACK allows the transfer of I byte The handshake sequence is 1 Target asserts REQ to request data transfer 2 Initiator asserts ACK when data is valid on bus 3 Target deasserts REQ when data has been transferred 4 Initiator deasserts ACK ready for next handshake Prior to and during information transfer the I O signal determines the direction of the transfer as can be seen in Table I I Before each information transfer phase the target will set up the MSG and I O lines in such a way that these control signals are stable for 450ns before the REQ of the first handshake and remain valid until the deassertion of ACK at the end of the last handshake During eaeh information transfer phase the BSY line remains asserted and SEL deasserted Each information transfer phase is as follows Command phase allows the initiator to direct the subsequent action of the target by transferring command bytes The target asserts C D and amp asserts MSG and I O Status phase allows the initiator to read the target s status information The target asserts C D and I O and deasserts MSG ACW SERVICE MANUAL Issue 1 111 Chapter
153. gh the system VIA IC20 TALS 139 Dual 2 to 4 line decoder 1 pins 4 5 6 and 7 This decoder is enabled by 1C21 for I O address values between amp FEOO and amp FEIF The IC uses address lines A3 and A4 to complete the I O address decoding for the CRTC 00 1 amp FE08 9 SERPROC amp FE10 and the ECONET control signal NINTOFF NSTATID amp FE18 2 o p pins 9 10 11 and 12 decode address values amp FE20 to amp FE3F into 2 write only blocks and 2 read only blocks only one is used At amp FE20 WR is the VIDPROC amp FE20 RD is INTON an ECONET control amp FE30 to amp FE3F WR is ROMSEL space see PAL 1C36 741 520 Dual 4 input NAND 1 o p pin 6 controls the paged ROM NOE signal paged ROMs are disabled during CPU write cycles by this gate R NW i p ROMs are also disabled for the 1 0 address space FRED JIM and SHEILA The N2M clock ensures ROMs can only drive the data bus during phi2 which avoids bus drive conflicts during address changes 2 pin 8 ORs three active low signals to form an active high RAM data request signal A15 low OR NPGRAM low OR NVIDPRCC low will enable the RAM data buffer 49 see 48 o p 12 741 530 8 input NAND ORs five I O enable signals to form the active high cycle signal SYNC IM This signal is used by IC25 to trigger 1 E and phi2 clock syncronisation The five input signals correspond to the ACW SERVICE MANUAL Issue 1 TI Chapter 4
154. h for 8 53 track made South South for 5 1 4 disc drive North for 8 S4 PCB track made South South for 5 1 4 disc drive North for 8 S5 wire link not fitted allows disc filing system to disable NMI This feature is not supported by current disc software S6 PCB track made South South for 5 1 4 disc drive North for 8 7 plug made East East for 1770 floppy disc controller West for 8271 S8 plug fitted fitted for 1770 floppy disc controller removed for 8271 59 plug made West West for SK 16K in IC35 East for 32K ROM EPROM in IC35 S10 PCB track made East East enables keyboard BREAK key West forces permanent reset broken neither East nor West disables BREAK key S11 plug made West West for 8K 16K ROM EPROM in 1C44 East for 32K ROM EPROM in IC44 512 plug made West West for SK 16K ROM EPROM in 57 East for 32K ROM EPROM in IC57 13 plug made South South causes BASIC to take high priority ROM numbers 14 15 North causes BASIC to take low priority ROM numbers 0 1 ACW SERVICE MANUAL Issue I 1 O Processor board S 14 plug made North North gives white on black video South gives black on white video Beware monitor performance in the latter configuration S15 plug made West West for SK 16K ROM EPROM in IC62 East for 32K ROM EPROM in IC62 16 test link not present on issue 2 or later PCB 17 PCB track made North North configures IMHz bus audio for input South for out
155. he 12 voltage between the black and orange cables The allowable voltage ranges are as follows 5V blaek and red 4 9V to 5 2V 12V black and orange 11 4V to 12 6V These measurements should be made with all connectors in place Next measure the current drawn by each of the three components specified above from the 5V and 12V supplies Two of the components are each supplied via a four way plug in connector and the current measurement should be made in series with either the red eable 45V or the orange eable 12V The eonnections to the meter to do this must be made with the power switch off The measurements must be made alter power up as some of the eircuitry when working correetly will alter its current consumption with time as shown below The current drawn by each eomponent from each voltage rail should be as follows ACW SERVICE MANUAL Issue 1 117 Chapter 6 Winchester hard dise unit 5 around I to 1 5A 12V up to 4 5A Falling to around 2A when up to speed Dise eontroller board 5 around 1 5A 12V around 250mA Host Adapter board 5 around 500mA 12V zero not used The above figures are approximate and will enable cheeks to be made for open short eireuits and malfunetioning components 6 9 2 Address decoding The easiest way to test the address decoding is to execute a program whieh accesses the relevant memory location amp FC40 read data Run the following program 10 DIM P
156. inal Inspection Tester Floppy Disc Controller 1770 or 8271 Integrated Circuit 1Dentity refers to the unique number of a given ECONET station or paged ROM Insulation Displacement Connectors parallel cable connectors underneath the computer TEEE488 VO IRQ MOS OS MPU NMI PA PAL PAL PB PCB PET PHD PL PORT PSU Ql etc QWERTY RAM RAS RC RGB ROM ROMSEL RS423 RTS 51 30 Glossary A parallel interface usually associated with automatically controlled test instruments Input Output Interrupt ReQuest control line on the 6512 processor Machine Operating System or OS MicroProcessor Unit same as CPU Non Maskable Interrupt eontrol line on the 6512 processor Port A One of the two ports of a VIA 1 A feature of the British television colour system where colour information phase is varied on alternate lines Hence Phase Alternate Line ii Abbreviation for a type of logic integrated circuit IC which is programmed by fusing microscopic links in the 1C Programmable Array Logic circuits are used to reduce the number of ICs needed on a circuit board Port B The other port of a VIA Printed Circuit Board Test device designed for use with BBC Mierocomputer Model B Will work on the B ACW I O Processor but with different results see information manual supplied to dealers CPU clock input non overlapping with PHI2 CPU clock input Header PLug Test device for use with BBC Mic
157. ined then check that S8 is fitted This fault is unlikely if the disc system has worked before Check that after a BREAK a chip select NCS pulse occurs on pin 1 IC16 If not then check decoder IC28 Use an oscilloscope to monitor read data NRD on pin 19 IC16 or the signal end of R7 The data should be negative going pulses of period 4us or 8us If not then check connections to PL8 Replace 1770 4 7 12 Printer port 68 Use a PORT tester to check that the printer port is faulty Test the VIA IC10 by writing values to it and testing the outputs First configure all the data lines as outputs by writing amp FF to the data direction register A DDRA amp FE63 amp FF Then write amp 00 to the output register amp FE61 amp 00 All the data lines to the printer connector PL9 should now be low pins 3 5 7 9 11 13 15 and 17 If they not all zero then check them at the VIA itself pins 2 3 4 5 6 7 8 and 9 of IC10 If these are all low then the buffer ICS is faulty Otherwise check for open circuit tracks on data lines on both the printer side and the CPU side of the VIA Now write amp FF to the output register ACW SERVICE MANUAL Issue 1 I O Processor board amp FE61 amp FF All the data lines to the printer connector PL9 should now be high pins 3 5 79 11 13 15 and 17 If they are not all 1 then check them at the VIA itself pins 2 3 4 5 6 7 8 and 9 of ICIO If these are all high then the buffer IC5 is faulty Other
158. is believed to be accurate but no liability in respect of any use of it is accepted by MICROVITEC PLC 2 ACW SERVICE MANUAL THE COMPUTER MUST BE EARTHED IMPORTANT The wires in the mains lead for the apparatus are coloured in accordance with the following code Green amp Yellow Earth Blue Neutral Brown Live The moulded plug must be used with the fuse and fuse carrier firmly in place The fuse carrier is of the same basic colour though not necessarily the same shade of that colour as the coloured insert in the base of the plug Different manufacturers plugs and fuse carriers are not interchangeable In the event of loss of the fuse carrier the moulded plug MUST NOT be used Either replace the moulded plug with another conventional plug wired as detailed below or obtain a replacement fuse carrier from an authorised ACORN dealer In the event of the fuse blowing it should be replaced after clearing any faults with a 5 amp fuse that is ASTA approved to BS1362 If the socket outlet available is not suitable for the plug supplied the plug should be cut off and the appropriate plug fitted and wired as previously noted The moulded plug which was cut off must be disposed of as it would be a potential shock hazard if it were to be plugged in with the cut off end of the mains cord exposed As the colours of the wires may not correspond with the coloured markings identifying the terminals in your plug proceed as follows
159. isation to 1M If not then replace IC28 If the signals are good then test them at pins 16 and 14 6 Check that the ROM output enable pin 6 40 is high ROM disabled when either FRED or JIM is low Check that SYNC pin 8 IC41 is high when either FRED or JIM is low Check that the data bus buffer enable pin 19 IC12 is low enabled when either FRED or JIM is low the above three signals come indirectly from pin 11 IC34 Check that the data bus DO D7 goes low both sides of the buffer at some point after the buffer is enabled pin 19 IC12 goes low IMPORTANT The 1Mhz bus must be terminated Termination resistors RP2 and RP4 are located on the Winchester Host Adaptor PCB and arc fined if the Winchester is the only peripheral on the 1MHz bus If external peripherals arc attatchcd to the 1Mhz Bus then the terminators in the host adaptor should be removed and retained 4 7 15 TUBE interface 70 Use a PORT tester to check that the TUBE interface is faulty Run the following test program 10 tube amp FEEO 20 DIM P 100 30 40 start 50 LDA amp 00 60 loop 70 STA tube 80 JMP loop 90 100 CALL start Test the enable pin 19 IC14 with an oscilloscope and check that the signal is wobbling If not then check the address decoding performed by 1C21 and IC22 Check that all data lines both sides of the buffer pins 11 18 and pins 9 2 of IC14 DO D7 go low at some point after th
160. isted below Cambridge Workstation Technical Description and Service Manual Acorn Computers Ltd Part Number This doeument A CW Welcome Guide Aeorn Computers Ltd Part Number 0420 000 A CW Function Key Card Booklet Acorn Computers Part Number 2201 206 Cambridge Series I O Processor Guide Acorn Computers Ltd Part Number 0410 004 A description of the ACW I 0 Processor also applicable to users of the Cambridge Co Processor it explains the features of the I O processor Panos Guide to Operations Acorn Computers Ltd Part Number 0410 011 This gives a comprehensive description of the Panos operating system both for the user and for the high level language programmer Panos Programmers Reference Manual Aeorn Computers Ltd Part Number 0410 012 Of interest to users who wish to write programs which interfaee with Panos at a low level A CW Terminal Emulator Guide Acorn Computers Ltd Part Number 0420 010 Cambridge Co Processor Thchnical Description and Service Manual Aeorn Computers Ltd Part Number 0410 000 to be published describes the hardware Language Manuals ACW SERVICE MANUAL Issue 1 133 Appendix D 32000 A ssembler Reference Manual Part Number 0410 005 32000 BBC BASIC Reference Manual Part Number 0410 006 FORTRAN 77 Reference Manual Part Number 0410 008 ISO Pascal Reference Manual Part Number 0410 010 C Reference Manual Part Number 0410 007 Cambridge LISP Reference Man
161. its table entry using a normal memory access cycle If the MMU detects an illegal access or an access to an address which does not reside in RAM a trap will occur and the trap handling mechanism of the 32016 will be invoked For a more detailed description of the MMU and its function refer to NS32082 data sheets ACW SERVICE MANUAL Issue 1 95 Chapter 5 Phi 1 Phi 2 AD16 23 ADO 15 Read ADO 15 Write ADS CPU MMU ADS TCU DDIN HBE Figure 5 4 6 Memory Managed Bus Cycle CPU BUS SIGNALS __ Virtual Physical M Addr X Addr 1 rcr r w R u ney Virtual Physiceli data I V Adde N Adar Read data sampled by CPU __ Virtual Physical data V Addr XA Addr V write V M ____ _____ read A V 32016 Processor 5 5 Links 5 5 1 Configuration These are read by software on power up and indicate the presence or absence of optional hardware ie FPU or MMU The links have one side connected to OV the other side is pulled high by resistors and can be read onto the AD bus through 1C30 A link installed indicates 51 No FPU S5 RSVD S2 No MMU S6 RSVD S3 RSVD S7 RSVD 54 RSVD 58 RSVD 5 5 2 Other links The printed circuit board should be viewed with the TUBE ribbon cable socket at the BOTTOM LEFT while reading this subsection LK1 Tube power Maybe repla
162. ler 2M is used to enable the device o p s so the enable signals are effectively synchronous with phi2 2 o p pins 4 5 and 6 decode the I O pages FRED JIM and SHEILA The decoder uses the I O enable from IC22 and 8 and A9 to detect the 256 byte I O blocks 4 is FRED amp FC o p 5 is JIM amp FD o p 6 is SHEILA amp FE 1C29 TMS5220 Speech synthesiser optional NOT FITTED ON ACW I O PROCESSOR 1C30 7455259 Octal addressable latch This device expands the number of output bits available for system contol functions It is driven by the operating system through the system VIA 1C20 1C31 74574 Dual D type flip flop 1 pin 6 disables the addressable latch 1C30 during a CPU access of the system VIA to avoid VIA glitches disturbing the latch 10620 contents The function does not need schottky speed 2 o p pins 8 and 9 generate timing for RAS the RAM row address clock RAS is a delayed 4M clock the delay being nominally 62 5ns half period of 8M This device is schottky to minimise device delay uncertainty ACW SERVICE MANUAL Issue 1 75 Chapter 4 IC32 7ALS374 Octal D type This device is used to sychronise and de glitch the 1MHz device control signals By using 1M to clock the register signal changes can only occur while E is low inactive 1C33 74802 Quad 2 input NOR 1 o p pins 1 4 and 10 form the CPU clock generator Outputs 4 and 10 are connected as an 5 flip flop which generates a non
163. ll be selected at switch on or CTRL BREAK ACW SERVICE MANUAL Issue 1 57 Chapter 4 To allow another ROM to be selected at switch on a second Molex switch 513 is also tested If S13 is North the co habiting User ROM of 1C71 is reduced to the lowest ROM priority The operating system is not affected 4 4 2 Speech This section gives instructions for adding extra hardware to upgrade the PCB for speech IC 29 and 37 are for speech upgrade ONLY Dealers and service centres performing these upgrades must also conform to upgrade procedures and requirements as notified by their supplier and should refer to any available information updates for latest details 1Cs are inserted with their pin 1 facing the back of the computer The following parts are required 1C29 5220 1C37 6100 PHROM Insert 1C29 and 1C37 into their sockets on the PCB Turn the computer on and type REPEAT SOUND 1 GET 0 0 UNTILO and press the RETURN key Any key now pressed should cause the system to utter a word or sound Adjust VR1 until the speech is at the correct pitch This can be measured by connecting a frequency meter to pin 3 IC29 Adjust VR I until the meter reads 160kHz 100Hz 4 5 Selection links 58 This section describes the function of each of the links on the PCB the type of link and its position as standard S1 PCB track made West West for 5 1 4 disc drive East for 8 S2 PCB track made North North for 5 1 4 disc drive Sout
164. mation transfer phases to bus free again There are no restrietions on the order of information transfer phases and a phase will often follow itself eg two data phases one after the other A typieal sequenee would he bus free select controller selection phase transfer command bytes command phase transfer data bytes if neeessary data in out phase status phase message phase The phases are as follows Bus free phase indicates that the bus is available for use The bus free phase is indieated by all control signals described in section 6 5 2 being deasserted If SEL and BSY and RST are not asserted that is sufficient to guarantee bus free ACW SERVICE MANUAL Issue 1 Winchester and Floppy Disc Systems Selection phase allows the initiator to select the target After detecting bus free the initiator asserts SEL The target deteets SEL asserted and BSY and I O deasserted and responds by asserting BSY The initiator deasserts SEL and may then change the data signals Information transfer phases allow transfer of information across the bus There are several different types of information transfer phase and the type is determined by MSG C D and I O Table 1 shows the information transfer phases SIGNALS DIRECTION OF MSG C D I O PHASE NAME INFORMATION TRANSFER 1 il 1 data out phase initiator to target 1 1 0 data in phase target to initiator 1 0 1 command phase initiator to target 1 0 0 status phase tar
165. n disc copy files from a drive directory to another remove a single named file remove specified files select current drive directory select current drive execute list of commands in file display amount of free space on disc display list of commands select current library load file into memory e g machine code specify auto start option change a file name execute a machine code program save memory image into a file specify disc or directory title display text file on screen remove specified files with confirmation DFS ADFS NFS DISC ADFS NFS ACCESS ACCESS ACCESS BACK BYE BYE CAT CAT CAT 2 CDIR CDIR COMPACT COMPACT COPY COPY DELETE DELETE DELETE DESTROY DESTROY DESTROY DIR DIR DIR DRIVE EXEC EXEC EXEC FREB FREE HELP HELP HELP LIB LIB LIB LOAD LOAD LOAD OPT 4 OPT 4 OPT 4 RENAME RENAME RENAME RUN RUN RUN SAVE SAVE SAVE TITLE TITLE TYPE WIPE ACW SERVICE MANUAL Issue 1 131 Appendix C For a full list of filing system commands applicable to the particular model of I O Proeessor in use type help DFS help ADFS help NFS or eonsult the appropriate User Guide Most commands can be abbreviated but a full stop must be appended to the abbreviation e g h means Help 132 ACW SERVICE MANUAL Issue I Appendix D Guide Documentation The publications referred to in this Guide are l
166. n on the line When required collision detect may be installed by fitting components as shown on the circuit diagram and breaking the link S29 a PCB copper link 4 2 15 Cassette and RS423 ports 52 For both the cassette SK5 and RS423 5 4 interfaces a 6850 asynchronous communications interface adaptor ACIA 1C82 is used to buffer and serialise or deserialise the data The serial processor 1C85 contains two programmable baud rate generators a cassette data clock separator switching to select either RS423 or cassette operations and also a circuit to synthesise a sinewave to be fed out to the cassette recorder Note that the receive bit rate for cassette operations is derived from the FSK signal not from the serial processor control register bits used when RS423 operation is selected 1618 divides the 16MHz clock signal by 13 1 23 MHz and this signal is divided further within the serial processor to produce the synthesised 2400 1200Hz cassette record signal and the bit rate clocks Automatic motor control of an audio cassette recorder is achieved by using a small relay driven by transistor Q7 from the serial processor R66 and C30 provide the necessary timing elements for delay between receiving the high tone run in signal and asserting the data carrier detect signal to the 6850 The signal coming from the cassette recorder is buffered filtered and shaped by three stages of the LM324 amplifier IC89 The 5423 data in and data out
167. nels Param1 0 will disable all channels Param1 1 will enable channel I only Param1 2 will enable channels 1 and 2 Param1 3 will enable channels 1 2 and 3 Param1 4 will enable all four channels The converter repeatedly cycles through the selected channels converting each in turn It stores the last value obtained from each channel OSBYTE 17 will override this free running mode forcing the ADC to start a conversion on the channel indicated by the value in Param OSBYTE 128 can be used to read a particular ADC channel or to discover which channel last completed a conversion operation It also reads the digital inputs Param selects the number of the channel to be read The value is returned in two bytes the most significant is in Result the least significant is in Result2 If 1 is zero then Result2 will contain the number of the last channel to have had a conversion completed If no channels have completed a conversion since an OSBYTE 16 or OSBYTE 17 call then zero will be returned The two least significant bits of Result record the status of the digital inputs Completion of conversion can be notified by causing an interrupt asynchronous event number 3 The Panos library procedures may be used both to enable and to handle this event 4 2 17 Audio circuitry IC38 is a four channel sound generator which can be programmed to vary the frequency and volume of three independent tone generators and the amplitude of a single n
168. ng screws provided It will be necessary to push out the blanking label covering the mouse D type mounting hole ACW SERVICE MANUAL Issue 1 MOUSE ASSEMBLY 8 Connect the DC power supply to the mouse PCB Faston connectors Two spare connectors are available on the DC loom on the components tray Connect BLACK to the Faston and RED to the 5V Faston on the mouse adaptor PCB 9 The ACW should now be re assembled aecording to the instructions given in section 2 3 in the service manual Testing If the ACW will not start up correctly suspect a faulty eonnection on one or more of the 1 MHz bus cable IDC connectors Recheck all 1DC fittings There is a BBC BASIC program which checks the operation of the mouse Switch off the TUBE using the switch on the back of the keyboard The TUBE LED should go out so the 32016 proeessor is not running and load the test program from disc The program moves an arrow over the screen correcponding to the mouse s movement The mouse has three click buWons Holding down the right button while moving the mouse draws a line on the screen The centre button clears the screen and the left button produces a BEEP from the ACW loudspeaker If the program fails to work then both mouse and mouse PCB are equally suspect Check the 9way ribbon cable and its connections first Next try a known working mouse of the same type with the same program If the screen drawing program still doesn t work then the mouse P
169. nnector centre clip against the chassis metalwork to insure that the tripler is fully discharged 5 Discharge the CRT final anode Use a long shafted screwdriver with a high voltage insulated handle rest the metal shaft on the top of the chassis and touch the tip of the shaft into the CRT final anode EHT socket from where the EHT connector was removed 6 Disconnect the CRT earth connector from the earth tag on the CRT PCB 7 Remove the CRT PCB from the CRT neck 18 ACW SERVICE MANUAL Issue 1 Assembly Packaging and Installation 8 Remove the earthing tag from the main PCB located next to the tripler module on the chassis 9 Unclip and remove the 8 way scan coil plug from the main PCB 10 Unclip and remove the 6 way degausing coil plug from the main PCB 11 Desolder the leads from the PCB to the tripler The tripler is screwed to the cradle metalwork on production versions of the ACW Do not use excessive or prolonged heat 12 Gently prise the monitor PCB off the six nylon PCB support studs taking care not to use any instrument such as a screwdriver which might harm the PCB tracks Installation is essentially in reverse order but note A new monitor PCB will be supplied with the tripler mounted on the PCB The correct installation sequence is 1 Unsolder the tripler to line output transformer wire without using excessive or prolonged heat as the solder tag on the line output transformer is fragile 2 Unsold
170. nnectors A range of peripherals may be connected to the rear of the ACW A diagram of the rear panel connectors and their individual pin designation is shown in appendix E The connectors are 1 Composite Video output to an external monochrome or PAL colour monitor via a BNC connector 2 RGB output to a suitable external colour monitor 270 degree 6 pin DIN socket 3 5423 standard serial interface 5 pin domino DIN socket The baud rate is software selectable between 75 and 9600 baud 4 Cassette recorder interface 270 degree DIN socket Standard CUTS tones are used at 300 or 1200 baud 5 Analogue interface providing four 8 bit ADC input channels capable of reading analogue voltages in the range to 2 5V The conversion time 15 105 1 8V reference voltage is also available on the pins of the 15 way D type female connector 6 ECONET network connector 180 degree 5 pin DIN socket 7 Keyboard socket 25 pin D type female connector 8 Printer 8 bit parallel port Centronics standard 24 way DELTA IDC connector 9 IMHz BUS 37 way D type female connector 10 Mouse interface socket optional 9 Way D type WARNING It is possible to plug the ECONET system into the CASSETTE socket This will not harm either the ECONET or the ACW but the entire ECONET system will be rendered inoperative until the error is rectified 2 3 Disassembly and re assembly 2 3 1 Safety considerations WARNING HIGH VOLTAGE HAZARD The
171. nnectors are inserted correctly If the connections are good then check that one of the wires in the cable itself hasn t been broken Try replacing the whole keyboard assembly with a good one If it still doesn t work then the fault might be in the internal cable between rear panel and I O Processor Replace the cable with a good one If the fault persists suspect the computer and use a PORT tester 4 7 11 Disc interface The floppy disc interface is on the I O processor board The Winchester disc interface is not and so the Winchester will be considered later in chapter 6 Check all links are in correct position for the 1770 chip 53 South LINK S4 South PCB LINK S5 broken S7 East S8 made Check that all ICs and passives are fitted and inserted correctly The ACW floppy disc drive should be electrically isolated from the ACW by unplugging its data and DC power cables Use a PORT tester to check that the disc interface is the problem If it proves satisfactory then the floppy disc drive itself is at fault and should be replaced A known working 80 track drive should be connected to the ACW disc drive ribbon cable If the test drive is not a mains operated unit then it will also need connecting to the DC power distribution board of the ACW Turn the microcomputer on and check that the operating system recognises the disc filing system to the prompt type ACW SERVICE MANUAL Issue 1 67 Chapter 4 ROMS The display
172. o the NAND gate in half of 40 goes low that is when A15 is low address between amp 0000 amp 1 1 or if the paged RAM signal from IC36 is low address between amp 8000 amp AFFF and paged RAM selected or if the video processor VIDPROC is enabled address amp FE20 RAM is disabled when the VIDPROC is written to by holding NCAS at logic 1 see IC23 4 2 8 Disc interface 46 A 1770 operates in either Frequency Modulation FM or Modified Frequency Modulation MEM mode Since results in increased storage density FM is refered to as single density and as double density The 1770 has a data separator and disc speed decision logic built in No drive select logic is incorporated in 1770 so is fitted for this function also latches two contol signals which are used to select between FM and MFM operation and to reset the 1770 both under ACW SERVICE MANUAL Issue 1 1 Processor board program control The control register IC17 is a write only device which occupies the address space amp FES80 to amp FE83 IC23 gates the decoded address signal with NW 1C27 pin 6 to form the control register clock 1770 registers are addressed in the range amp FE84 to amp FE87 Two interrupt signals come from a 1770 pins 27 and 28 The two interrupts are inverted and wire NORed on to the NNMI line by two parts of IC7 quad NAND gate Link S8 selects between the single interrupt of an 8271 and dual inte
173. of the Host Adapter circuit diagram in the appendix arc all active low open collector and are as follows SELECT SEL pin 44 is an open collector signal which is asserted by the initiator as the first step in any transfer of data through the interface BUSY BSY pin 36 is an open collector signal which is asserted by the target to indicate that the data bus is in use This is the first response of the target to the initiator s assertion of SEL and the SEL BSY handshake is the first communication in any Winchester filing system operation CONTROL DATA C D pin 46 is asserted by the target when the bus carries control information and is deasserted when the bus carries data INPUT OUTPUT I O pin 50 controls the direction of data flow and is asserted by the target to indicate input to the initiator disc to computer and is deasserted to indicate output to the target eomputer to dise REQUEST REQ pin 48 is asserted by the target to indicate a request for a REQ ACK data transfer handshake ACKNOWLEDGE ACK pin 38 is asserted by the initiator to indicate aeknowledgement of a REQ ACK data transfer handshake The REQ ACK handshake provides the asynehronous timing of all data transfer between initiator and target RESET RST pin 40 is asserted by the initiator on power up and when the host mieroeomputer s BREAK key is pressed It causes the reset condition see 5 1 3 which immediately elears the bus and resets the system M
174. ograms However object files prepared with the 32000 Assembler may be loaded and called by BBC BASIC programs and useful MOS routines may still be accessed with the CALL statement The enhancements and differences between the implementations are detailed in the BBC BASIC Reference Manual supplied Examples gt FREE gt CAT gt RUN 1 6 3 Panos Various Panos utilities are available for handling filing systems and other functions In addition the star utility can be used to transmit commands to the I O processor s MOS For details of how to use PANOS and the utilites that run under PANOS refer to Panos Guide to Operations Acorn part number 0410 001 amp ACW SERVICE MANUAL Issue 1 Introduction 1 6 4 Programs Running under Panos the languages have built in features for handling the keyboard display and files sometimes as part of a library Additionally a library of operating system procedures similar to system calls is accessible from most languages These are described in the Panos Programmer s Reference Manual They include facilities for input output and file handling setting and reading the internal clock and handling asynchronous events interrupts In addition functions are available which simulate the BBC OSByte OSWord and OSFile functions Examples gt copy files to fileb edit filec filed filee gt show time logon Matters gt cat nfs gt star free gt star fx 238 128 1
175. oise generator The sound signal is DC restored by mixing in a signal derived from the sound envelope An inverting peak detector IC47 D4 C15 etc derives the inverted sound envelope which is then summed with the sound signal in the ratio of 2 1 Part of 1C47 forms a virtual earth summing amplifier which mixes the sound its envelope the external audio input and an optional speech signal into one audio channel The audio is then filtered through a second order low pass filter approximately 7kHz bandwidth and applied to ACW SERVICE MANUAL Issue I 55 Chapter 4 the volume control before final amplification by IC77 an LM386 1C77 drives the internal 8 ohm speaker via S20 The audio output of the optional speech system is filtered by an operational amplifier second order filter cut off frequency of 7kHz before mixing in with the other audio signals Speech is generated by an optional TMS5220 with 56100 or equivalent vocabulary PHROM IC numbers 29 and 37 respectively 4 2 18 Keyboard The keyboard circuit is given in the Appendix The keyboard connects to the main PCB via PL13 A 1MHz clock signal 1E is fed via an 741 5245 1C3 buffer to a 74LS163 binary counter the outputs of which are decoded by two 74LS 138 IC5 main keyboard and 106 numeric keypad decoder drivers These outputs drive the columns of the keyboard matrix each column being driven in turn If any key is depressed an 8 input NAND 1 4 on keyboard will
176. om amp C000 to amp FFFF except for 0 75Kbyte I O contains the machine operating system program The bottom half on the ACW is not used but in the BBC B and possibly future versions of the ACW could be a paged ROM containing BBC BASIC II In this case Link 513 selects the BASIC ROM slot number South selects slots 14 15 standard configuration high priority North selects slots 0 1 low priority Link 519 is permanently made East for CPU address A14 to pin 27 of ROM IC 1 72 73 74 75 741 5253 Dual 4 to I data selector These four ICs select the DRAM address signals according to the current display mode and RAS CAS state Not2M enables the four ICs luring the VDU RAM read phase RSL drives pin 14 to select the RAS or CAS address signals RSL low selects the row address NRAS clock MA13 from the CRTC IC78 selects the mode 7 address group when high 13 is low during all the graphics ACW SERVICE MANUAL Issue 1 81 Chapter 4 1C76 ehe 1C77 1C78 1C79 1C80 82 screen modes The VDUSEL signal from 1C36 is low for normal screen modes and high for all shadow screen modes 745283 4 bit adder The adder is used to modify the natural display address from the CRTC IC78 Take mode 0 as an example Mode 0 uses 20Kbytes of RAM from amp 3000 to amp 7FFF If the CRTC display is scrolled in hardware then the address from the CRTC will be say amp 4000 to amp 8FFF assumes a scroll step of amp 1000 The displa
177. on or Key This will force a return to the Pandora operating system kernel The BREAK button is useful if a program gets stuck in a loop that cannot be left by pressing the ESCAPE key Pressing the BREAK button alone gives a soft reset which neither clears the definitions of the user defined keys nor resets the system clock Pressing CTRL BREAK gives a hard reset which clears these 1 4 Function Keys By default these have no effect but the function keys may be programmed to produce either a string of characters or a single code For some functions the BREAK key the COPY key and the cursor movement keys can be considered soft keys In this case these keys may be treated as function keys numbered from 10 to 15 as follows BREAK f10 COPY f11 f12 gt f13 f14 f15 1 5 ACW Keypad ACW s separate numeric keypad forms part of the keyboard Normally these keys return the same codes as the equivalent keys on the main keyboard However it is possible to map the codes onto different values See the 110 Processor User Guide 1 5 1 The TUBE Switch The two ACW processors 32016 and 6512 communicate across the Acorn TUBE For normal operation the TUBE rocker switch on the back of the keyboard unit is set to dual processor mode The TUBE indicator light comes on when the ACW is powered up confirming that both the 32016 and 6512 processors are operating If the TUBE switch is moved to single processor mode only
178. orrectly in their sockets Use a PET tester if available See information manual supplied to dealers Acorn Part No 003 009 If this runs then the CPU is functioning correctly If the CPU cannot access the OS check that the OS ROM is enabled and that all address lines are present Check following BREAK that NOE pulses low at 2MHz inverse of phi2 and NCS goes low and stays low for a time Replace the OS BASIC ROM with a known good one Make sure that 519 is made East If machine works but sideways ROM selection is faulty then run the following program to test the ROM select latch ACW SERVICE MANUAL Issue 1 63 Chapter 4 10 20 30 40 50 60 70 80 90 romsel amp FE30 INPUT romnumber DIM 100 Start LDA romnumber STA romsel RTS 100 CALL start 4 7 8 64 Run the program and type number between 0 and 15 40 and amp F Check using a logic probe or oscilloscope that the binary representation of this number appears on pins 11 most significant 12 13 and 14 least significant of IC45 Results if the ROM numbers are not getting through to the ROM latch then alter line 80 of the program to 80 JMP start and re run the program Check with an oscilloscope that NPGLD from pin 13 IC36 is wobbling If not then check for shorted track If NPGLD is working then replace 45 If ROM latch contains correct ROM number but sideways ROMs still do not work then check decoder IC
179. overlapping two phase clock Schottky is used for minimum gate delays and to allow low value pull up resistors to be used The pull ups R20 and R21 ensure the MOS logic 1 voltages needed by the 6512A CPU 2 o p pin 13 inverts the RAS timing signal to form NRAS the RAM row address clock The delayed RAS signal RSL is used to modify the high low ratio of NRAS NotRAS is held low for an extra 10ns approx to meet the longest known Trsh spec of 120ns DRAMs RSL controls the ROW COLUMN address switching The small delay between NRAS and RSL helps ensure the minimum RAM RAS address hold time is exceeded 1C34 741 508 Quad 2 input AND 1 o p pin 3 combines the operating system enable with the BASIC language enable so either will select the 32Kbyte ROM IC71 Logic 0 active 2 pin 6 combines two NMI signals NNMI and NINT to form the complete NNMI interrupt for the CPU 3 o p pin 8 operates with 2 EX OR gates IC63 to reduce the refresh address cycle time when in display mode 7 4 pin 11 combines JIM and FRED enables This signal active low indicates a bus cycle is in progress IC35 various 64K 128K or 256Kbit paged ROM A 32Kbyte device in this socket appears in sideways ROM slots 2 and 3 link S9 East Link S9 West allows 8 or 16Kbyte EPROMS ROMSs to be fitted IC35 can be any or EPROM with a NCE access time less than 250ns IC36 16R4 Programmable array logic PAL IC ACORN no 0201 880
180. overtighten the nylon screws holding down the PCB ACW SERVICE MANUAL Issue I 19 3609 Chapter 2 T Jans pene 12 aps 5155942 gt 30300 opouv LUD Jurg 9 TFT omi 13 4 367 2 294052 WIWI SITE JOOP 0 ACW SERVICE MANUAL Issue 1 20 Assembly Packaging and Installation 2 4 5 ADAPTEC PCB 1 Remove the upper case as detailed in section 2 3 2 2 Release the quarter turn screw and lift and swing the side tray into the horizontal position 3 Disconnect the Molex 4 wire DC supply and the 3 IDC ribbon cable connectors 4 Prise the PCB from its four nylon PCB support pillars Installation is in reverse order 2 4 6 Winchester host adapter PCB 1 Remove the upper case as detailed in section 2 3 2 2 Release the quarter turn screw and lift and swing the side tray into the horizontal position 3 Disconnect the 2 Faston DC supply connectors and the 2 IDC ribbon cable connectors 4 Prise the PCB from its four nylon PCB support pillars Installation is in reverse order 2 4 7 Mouse interface PCB 1 Remove the upper case as detailed in section 2 3 2 2 Release the quarter turn screw and lift and swing the side tray into the horizontal position 3 Disconnect the 2 Faston DC supply connectors and the 3 IDC ribbon cable connectors 4
181. owing is displayed Defect number at sector number gt verification continues until the last sector The NEW defects are added to the defect list and the drive is automatically reformatted and verified until no new defeets are found NOTE The defect error number displayed is offset by 80 Hex if the address found is valid ie error numbers 19 and 99 are equivalent See appendix for ADFS Error numbers 17 Formatting is complete when the messages No defects found Writing map Writing root Save defeet list New defects file saved Superform saved Superforml saved A Hex number Sec tors A decimal number Bytes Free lt A Hex number Sectors A decimal number Bytes Used M7W SERVICE MANUAL Issue 1 129 Appendix are displayed followed by the ACTION prompt 18 Again cheek the defect list using comand option T against the serviee card 19 Type command to exit the formtter and return to the Winchester Utilities Menu 20 Type f9 to return to the basic prompt 130 ACW SERVICE MANUAL Issue I Filing System Commands Appendix C Command Summary The table is a summary of the more important filing system commands Function select filing system lock or unlock a file select previous directory create text file from keyboard close all files and park heads or log off display a disc or directory catalogue create a new directory re organise physical storage o
182. p 55 is a good number for testing the RS423 because it consists of alternating bits 01010101 RUN the program If the known WORKING microcomputer starts printing UUUUUUUUUUUUUUU etc across the screen then the RS423 is working as a transmitter If it works then go on to test it as a receiver If no output appears then test the SUSPECT RS423 circuit as follows Check the Dout line either side of the driver pins 2 and 15 of IC95 Pin 2 should be oscillating at normal TTL logic levels OV 5V Pin 15 should be oscillating in phase with pin 2 but at RS423 logic levels 5VI SV If pin 2 is active but pin 15 is not then replace the driver IC95 Check that the SERPROC IC85 is sending the transmit clock TXCK and receiving transmit data from the 6850 IC82 These signals arc on pins 26 and 22 respectively of IC85 If these signals are inactive then it is likely that the SERPROC is faulty or cannot be addressed Use the test program given in the cassette section above to check that the address decoding for the SERPROC and 6850 is working Now press CTRL BREAK on each microcomputer and swap the configurations so that the known WORKING computer is the transmitter and the SUSPECT computer is the receiver ACW SERVICE MANUAL Issue 1 I O Processor board If U characters are output on to the monitor by the SUSPECT computer then its RS423 is working as a receiver If no output appears then test the SUSPECT RS423 circuit as follows Check the
183. ply be adjusted In so doing it is possible that a 12V supply related to the processor s 5V supply will slightly exceed 12V This will not matter since the particular 12V supply in question powers the stepper motors of the disc drives and does not supply any voltage sensitive components 5 7 1 Equipment Required The 4M byte 32016 processor is the main processor of the ACW however a BBC Microcomputer can be used as a test station if it is not convenient to test the board using the ACW In this case the following equipment is required a U K BBC Micro Model B with disc interface b An 80 track single disc drive c A 40 way ribbon cable d Colour Monochrome monitor e A regulated bench power supply 5V 10A The minimum test equipment needed in order to trace a fault is a digital multimeter and an oscilloscope The oscilloscope should have at least two traces and two timebases and should have a bandwidth of around 5 or higher 5 7 2 Fault Isolation There are a number of simple tests which you can use to establish whether the hardware is working at all 5 7 3 Visual Check 100 First perform a visual inspection of the printed circuit board check that all external connections TUBE ribbon cable and the power leads arc secure and in good condition Check that no foreign objects washers etc have found their way onto the board Also check that the EPROMs and Molex links are inserted correctly ACW SERVICE MA
184. put 518 plug made West West for SK 16K ROM EPROM in IC68 East for 32K ROM EPROM in IC68 519 track made East East enables BASIC part of OS BASIC West disables BASIC and leaves just the operating system 520 plug made South South gives full volume on audio Remove if VR2 fitted S21 optional audio output prior to volume control S22 S23 eight plugs seven shunts ECONET ID number set up as binary number by user Only fitted if ECONET interface fitted 524 wire link not fitted optional termination resistor for RS423 Should not be fitted for correct operation of RS423 525 wire link not fitted optional termination resistor for RS423 Should not be fitted for correct operation of RS423 526 wire link not fitted made adds chrominance component to composite video output 527 plug made South South gives negative going CSYNC for RGB North gives positive going CSYNC 528 PCB track made North North for PAL video circuitry South for NTSC Note for NTSC operation R92 must be cut out The modulator may need changing for TVs which cannot receive channel 36 S29 PCB track made made for operating ECONET without collision detect hardware Collisions are detected by software protocols 530 PCB link made always made for 6512 CPU 4 6 Test equipment A PORT tester is available for the microcomputer It will check the DRAMs and all the I O ports on the microcomputer disc printer user IMHz bus TUBE video ROB R
185. r approximately 10 1 Again the inputs are biased to nominally 2 volts The comparator converts the differential ECONET data signal to single ended TTL which is decoded in IC81 the ADLC The LM319 comparator is sufficiently sensitive to allow high impedance attenuators to be used while still detecting the ECONET idle line state An idle line has a differential voltage of about 0 6 volts impressed on it by the ECONET line termination networks not part of the micro LM319 Dual analogue comparator special fitting This comparator circuit is not normally fitted When fitted its purpose is to detect data packet collisions on the ECONET Collisions are normally avoided by the network filing system protocol and so are rare When a collision occurs it will result in data corruption detected by the filing system error checks when collision detection hardware is not fitted If collision detection should be required then link S29 should be broken and IC93 and its associated components fitted 88LS120 Dual RS423 receiver circuit 1 o p pin 7 receives the RS423 port data signal This input is also compatible with RS232 data To reduce the voltage swing the signal is attenuated by R124 118 C31 reduces the signal bandwith and so reduces the risk of glitches in the received signal presented to the SERPROC 2 o p pin 9 receives the RS423 NCTS control signal R149 152 attenuate the voltage levels while C35 filters the signal 524 and 525 are op
186. re shown in Table 2 together with those of the standard 36 way connector with which printers are usually provided Connector Pin I O PCB Rear Pnl Printer Signal 26 24 36 strobe 1 1 1 Data 0 3 2 2 Data 1 5 3 3 Data 2 7 4 4 Data 3 9 5 Data 4 11 Data 5 13 7 7 Data 6 15 8 8 Data 7 17 9 9 Acknowledge 19 10 10 No connection 21 23 25 26 11 12 11 to 17 Ground 2 4 6 24 13 to 24 18 to 29 Table 2 Connections for A CW Parallel Printer Port ANN CEDVI CU MA Toona 1 AT Chapter 4 The connections are arranged so that insulation displacement connectors may be used to make a connecting cable in this case it is recommended that flat and twisted cable be used With conventional solderable connectors a twisted pair should be used for each signal with a ground connection at both ends 4 2 11 User port Port B of IC10 offers eight individually programmable input output lines and two programmable control lines The connector pins go directly to a 6522 Versatile Interface Adaptor VIA The VIA contains two fully programmable bi directional 8 bit I O ports The ACW uses a 25 way D type connector see Table 3 for the rear panel connections Also shown in the table is the pin out of the 42 way IDC connector on the I O Processor Rear Pnl I O PCB Signal Rear Pnl I O PCB Signal 25 way IDC function 25 way IDC function 1 1 45V 14 2 2 3 45V 15 4 CB2 3 5 OV 16 6 PBO 4 7 OV 17 8 5 9 OV 18 10
187. ress BREAK If the Coprocessor now works the FPU is at Fault The second case is difficult to diagnose as the symptoms can appear unrelated to the FPU The best method of identifying this type of fault it by replacing the suspect FPU with a known good device The FPU test supplied with some versions of the program is very simple and unlikely to detect faults of the second kind 5 7 10 Memory Faults Most common faults will be concerned with memory and or the incorrect installation of memory upgrade kits To aid fault finding an EPROM or 80 TRACK DISC based memory test program is available to authorised service agents and production sites See appendix H for the reference number This program is designed to help quickly identify faults in the memory system and can be used to check that memory upgrades have been installed correctly The symptoms of memory failure are varied and include 102 ACW SERVICE MANUAL Issue 1 32016 Processor Pandora s start up message incorrectly states the memory size b Some small programs will run but not other larger ones c A program will not run with an editor loaded d Random corruption of files loaded into memory The disc based version can be run by inserting the disc in the drive and pressing SHIFT D while pressing and releasing BREAK A Boot file is provided The disc version requires some 32016 memory itself and so is only useful for testing the memory of an assembled ACW where it i
188. ress during the unused read cycle of mode 7 VDU cycles Along with 1C34 o p pin 8 these gates form a circuit which reduces the time taken to cycle through the refresh address sequence when in mode 7 3 o p pin 11 is a spare gate inputs tied to 5V IC68 various 64K 128K or 256Kbit paged 80 ACW SERVICE MANUAL Issue 1 1 0 Processor board A 32Kbyte device in this socket appears in sideways ROM slots 10 11 link 518 East Link S18 West allows 8 or 16Kbyte EPROMS ROMSs to be fiWed This device can be any ROM or EPROM with a NCE access time less than 250ns 1069 741 574 Dual D type flip flop 1 o p pin 6 this flip flop holds the ECONET NMI enable signal The flip flop is used as an R S latch When address amp FE18 is read written the latch is set 6 low which disables ECONET NMIS IC23 6 gates N2E with the decoded address to give glitch free preset pulse To enable the address amp FE20 is read The decoded address signal appears as logic 0 on the D i p and is clocked through by the rising edge of N2E eg when phi2 falls This clears the D type pin 6 high and by the feedback action of Q connected to NCL locks the D type in the reset state ie NINTON high will not cause the D type to become set Note as NPR pin 4 acts directly on the Q o p it can defeat the NCL i p and set the device 2 o p pin 9 generates the alternate line signal which is used by the PAL encoding logic to encode the chroma
189. rocomputer Model B Power Supply Unit Transistor numbers Signifies a standard typewriter key layout Random Access read write Memory Row Address Strobe control line for the DRAM Resistor Capacitor network Red Green Blue individual colour signals for the VDU Read Only Memory ROM SELect latch An internationally defined convention for serial transmission of data Ready To Send control output on RS423 port PCB links XXT ODAVAN ANA A NTETAT T 1 197 Appendix E 138 SK TTL ULA VC VDU VIA VR IM 2E 2M 4M 8M Socket Tranistor Transistor Logic a standard type of digital IC 74 series Uncommitted Logic Array semi custom 1C Variable Capacitor Visual Display Unit Versatile Interface Adaptor 6522 Variable Resistor A synchronous enable or cloek for 65xx 68xx family peripheral 1Cs 1E is a continuous IMHz square wave 1 MegaHertz from video processor A synchronous enable or clock for 65xx 68xx family peripheral 105 2E may have two or three half cycles suppressed to synchronise it to E 2 MegaHertz from video proeessor 4 MegaHertz from video processor 8 MegaHertz from video processor ACW SERVICE MANUAL Issue 1 Appendix F Connector pinouts ACW rear panel connections IT IS DANGEROUS USE THIS WITH THE COVER REMOVEO 5 1904 mouse BT link ACORN COMPUTERS LTO m Mada m he Ko gdom i LE P SK1 UHF Out This is not fitted on the ACW S
190. rrupt of a 1770 When a 1770 is fitted S8 must be made For the 1770 option link 57 is made East this incorporates N2M into the chip select signals and so defines the timing of data transfers between the disc controller and the CPU Link S5 is available to allow program controlled suppression of 1770 disc controller interrupts IC17 is not present when the 8271 is fitted The disable function is not used at present so S5 is not fitted 4 2 9 Display circuitry Red green and blue signals are produced by the video processor and are then buffered by QI Q2 and Q3 to be fed to the DIN socket SK3 at TTL type levels The fourth signal required at the RGB output is a composite SYNC CSYNC generated from horizontal sync and vertical sync of the 6845 CSYNC polarity can be altered using link 527 The and 5 power supply also appears on SK3 4 2 10 CENTRONICS compatible printer interface The computer can drive a centronics compatible printer through ICIO a 6522 VIA Port A of the VIA is configured as 8 bit output port which is buffered by IC5 and fed to PL9 Printer strobe pulses are generated by a program sequence which toggles CA2 0 39 high low high Strobe pulses are typically 4us wide ACK from the printer is connected to CA1 1610 pin 40 ACK is pulsed low for approximately Sus by the printer when it is ready for the next character byte transfer A 24 way Delta or IEEE 488 style connector is provided The connections a
191. s inconvenient to change the 32016 card ROMs The program is also available on two EPROMs which are temporarily inserted in place of the two Pandora EPROMs installed during manufacture This must be done with the power to the unit switched off or disconnected and with some care as damage will result from incorrect insertion The program writes a fixed pattern into memory and then reads it back checking each word in turn The pattern written into memory is cycled Hex 21 times because memory faults are often pattern sensitive This is the main reason that all memory test programs take a long time to run in this case approximatly 20 mins to test 4 Mbytes Proportionaly less for smaller machines On start up a menu similar to Table 10 should be displayed You should then press a key between 0 and 7 according to the size of memory installed Eg pressing 2 for 1 5 M byte produces Select Testing 1 5 M Bytes Cycle XX The Cycle XX message gives an indication of how far the test program has got The test takes Hex 21 cycles If a mistake is made in selecting the memory size then it is quite in order to press BREAK and re start the program Examples of various faults and their corresponding error reports are given in the appendix ACW SERVICE MANUAL Issue 1 103 Chapter 5 32016 Test Programs V2 0 Key Test 0 Walking 16 bit memory test 0 5 M bytes 1 Walking 16 bit memory test 1 bytes 2 Walking 16 bit memory test 1 5
192. sette interface and RS423 fail shown up by the PORT tester then it is likely that the fault is with one of the above ICs or its address decoding Cassette interface Use a PORT tester to verify that the cassette interface is faulty tests on the cassette interface must be carried out using a known WORKING cassette recorder and tape The commonest fault is the user s cassette recorder and the azimuth adjustment should be checked The tape recorder s volume control should be set for an output of 300mV peak to peak Test pin 25 1C85 the serial processor and check that 16MHz 13 812ns period is arriving at that pin This signal must be stable and accurate If not the divide by 13 circuitry formed by 1C18 is faulty If the cassette fails to LOAD look at the following pins while attempting to LOAD 1C89 pin 8 should show high and low tones of equal amplitude symetrical about OV If there is a marked displacement then replace 1C89 IC89 14 should be similar to pin 8 with maximum 50mV displacement 1C89 pin 1 should show L4V peak to peak square wave with an even mark space ratio Reduce the volume of the cassette recorder until this is so Maximum 50mV displacement Check that pins 2 and 3 of 1C82 arc wobbling Check that both 1C82 and 1C85 be selected by running the following program acia amp FE08 serproc amp FE10 DIM P 100 Start LDA LDA serproc JMP start 90 0 CALL start
193. should indicate ROM numbers a letter lt a filing system ROM ROM eg ROM 05 S DFS The DFS indicates that the Disc filing system ROM is present Results if the message fails to say DFS then check the ROM socket and the ROM If the ROM works OK then check that the data address and control signals are reaching the 1770 IC16 Check for pulses on pin 1 of IC15 after a break If there are none check the address decoding logic Press SHIFT ID BREAK Drive 0 should start the LED on the front of the drive comes on Results if drive doesn t come on then check using an oscilloscope or logic probe that MO pin 20 IC16 is high NMOTOR pin 10 IC8 is low Check that SO pin 7 is high NSO pin 8 is low If the above signals are correct then check the connection from IC7 and IC8 to connector PL8 If the above signals are wrong then try a good 1770 and check IC17 Check that IC17 is reset after a BREAK all outputs low Check function by poking values between 0 and 64 into location amp FE80 Check that the correct bit pattern appears on the outputs If drive does come on with SHIFT D BREAK then insert a known good 80 track disc into drive 0 Use disc which has a number of files on it and make sure that a write protect tab is fitted Shut the drive door Try CAT to get a catalogue of the disc If no catalogue appears then check that S7 is fitted East If an incorrect catalogue is obta
194. signal 18 recovered A preamble tone is timed to initialise data reception When fitted R66 and C30 are used to time the preamble tone Motor control of a cassette recorder is managed by the SERPROC A control bit in the IC controls the relay RL1 The control signal on pin 11 is buffered by Q7 which switches the relay coil 50 ohm ACW SERVICE MANUAL Issue 1 83 Chapter 4 86 87 1 88 IC89 IC90 91 84 741 586 Quad two input EXOR 1 o p pin 3 generates a colour subcarricr reference component according to the current display colour 2 o p pin 6 is one of three gates which generate control signals to gate the subcarrier component signals into the resistor matrix by enabling or disabling NAND gates in IC90 3 o p pin 8 see o p pin 6 4 o p pin 11 see o p pin 6 741500 Quad two input NAND 1 o p pin 3 buffers the colour reference oscillator to ensure TTL levels 2 ofp pin 6 is used as an inverter It drives the colour burst timing components R76 and C32 with NHS see IC58 o p pin 13 3 o p pin 8 is one of two gates which drive the colour subcarrier resistor matrix with the colour burst subcarrier components Input pin 10 receives an enable pulse from the colour burst monostable 4 o p pin 11 is the second gate of the colour burst generator TALS 123 Dual monostable 1 pin 5 determines the maximum allowed transmission period for an ECONET data packet The monostable s duration is set to
195. signal The D type is clocked by HS and so changes state at the start of each TV raster line divides the line frequency by two Link S28 made with a PCB track allows the alternating line signal to be disconnected for NTSC operation Note for NTSC R92 should be removed and an appropriate colour subcarrier crystal fitted X2 should be four times the colour subcarrier frequency The RF modulator must also be chosen to suit the destination country 1C70 741 5132 Quad 2 input schmitt trigger NAND ECONET only Note when collision detect is not used IC93 not fitted IC70 be the cheaper 741 500 1 o p pin 3 inverts NRTS If the collision detect circuit is fitted this gate buffers IC93 to give a true no collision signal Its main purpose is to give clean TTL level signals with normal TTL transition times 2 o p pin 6 forms the NCTS signal used by IC81 to check for network collisions Input 5 ensures the signal is always false if the network clock is not present 3 o p pin 8 gates the network NMI enable with the true INT signal to form NINT NotINT is the ECONET NNMI signal which is passed to the CPU via IC34 R56 is only needed on machines built without an ECONET interface 4 o p pin 11 inverts NIRQ from IC81 to form IRQ This signal is treated as an NMI by the system when enabled by IC69 NotINT is an open drain o p so R59 is needed as a logic high pull up 5 32Kbyte ROM The top half addressed fr
196. t then follow one of the above depending on the prompt If anything is typed after parking the Winchester heads in particular BREAK or ADFS there will be a pause while the Winehester mechanisim winds in the heads 106 ACW SERVICE MANUAL Issue 1 Winchester Floppy Disc Systems Figure 6 3 0 Winehester Disc System Chapter 6 6 3 1 Servicable parts The only dealer serviceable part of the Winchester Disc unit is the Host Adapter printed cireuit board Faults deteeted in the dise drive disc controller board mean that the faulty part must either be returned for repair or replaeed Dealers may hold stock of these items and should refer to information provided by their supplier for service procedures for these units 6 4 Specification 6 4 Disc drive Capaeity 20M formatted Format ADAPTEC 33 sectors of 256 bytes Cylinders 612 Heads 4 Disc rpm 3600 6 4 2 ADAPTEC ACB 4000 A Winchester disc controller Disc interface ST 412 Host interfaee SCS1 6 4 3 Host Adapter SCSI to 1 MHz expansion bus 6 4 4 Disassembly and assembly Removal and re assembly of the Winchester drive is explained in section 2 4 WARNING When the ACW Winchester Dise drive is removed for serviee work great eare must be taken not to drop jar or shoek the unit in any way Under no circumstanees should the drive itself be opened to expose the head meehanisim this can only be done by the manufacturer in a special ultra clean room 6 5 Circuit des
197. ta So D6 received by the teletext generator chip 1059 will be forced high during display blanking IC24 741 504 Hex inverter 74 ACW SERVICE MANUAL Issue I 110 Processor board Used for inverting various signals around the board 1C25 7415109 Dual J K flip flop 1 o p pin 6 is a flip flop clocked at 2M and samples the 1M signal to form the internal 1E and NE clocks 2 o p pin 10 is used as a state machine to process 1 MHz cycle requests When pin 10 is high it holds phi2 high until phi2 and 1E syncronise 1C26 74504 Hex inverter Three parts are used in a ring of two plus buffer 16 MHz oscillator The remaining three are used where inversion is needed on time critical signals 1C27 74LS00 Quad NAND 1 o p pin 3 is used to gate 2M with R NW to form NR a syncronous read enable used by the ADC and 8271 disc controller if fitted 2 o p pin 6 is used to gate 2M with NR W to form NW a syncronous write signal used by the ADC and the 8271 disc controller if fiWed 3 o p pin 8 is used as an inverter to generate NRS the system master reset 4 pin 11 is a spare gate Inputs are tied to 5V 1 28 741 5139 Dual 2 to 4 line decoder 1 o p pins 10 and 12 split the FDC address space into two parts Uses A2 and NFDC so that o p 10 is low for address values amp FE84 to amp FE87 12 is low for amp FE80 to amp FES83 The o p s repeat in blocks of 4 up to address amp FE9F When 57 is East 1770 disc control
198. tatus Y6 pin 9 is select Y7 pin 7 is enable 1RQ All these outputs are active low When either of the two data transfer paths is selected YO or Y4 an ACK signal is generated by clocking D type flip flop half of IC11 This flip flop is cleared direct from the REQ line and thus the REQ ACK handshake is facilitated The other half of 1C11 facilitates the SEL BSY handshake The D type is clocked by Y6 to generate seleet and is cleared by BSY When Y7 is selected the least significant bit on the data bus DO is clocked into a D type flip flop half of 1C10 If this value is a I then the latch 2 NANDs of IC12 is enabled and an IRQ will be generated at the next falling edge of REQ To disable interrupts Y7 is selected with a 0 on DO IRQs are enabled only for a very short time around 10ms when ensuring a sequential file buffer 6 7 2 Buffering The data bus DO to D7 of host microcomputer DBO to DB7 of SCSI interface is buffered in the write direction by an octal 3 state buffer ICI and an octal transparent latch 2 1C2 is enabled by Y4 of which is the write data signal see 5 3 1 Because 1C2 is a transparent latch data will remain valid on the output side when the enable is deasserted The outputs from 1C2 are gated through 8 open eollector NAND buffers which are enabled from the I O control line of the SCS11 interface and which invert the bus signals To write data across the Host Adapter requires that both R NW 0
199. te 128Kbit or a 32Kbyte 256Kbit ROM The correct size for each individual socket is selected by the row of Molex links near the board edge A link made between the centre and West pin will access 8k or 16Kbyte devices ONLY whilst the link made to the East will give 8 16 or 32Kbyte ROMS The operating system sees the ROM s as a maximum size of 16Kbyte so that when selected as a 32Kbyte size socket the operating system will access the BOTTOM 16Kbyte as one ROM and the TOP as another separate 16Kbyte ROM The bottom ROM has the highest priority This means that each socket can represent TWO ROMS The O S can deal with 15 ROM s with number 15 having the highest priority If a 256Kbit ROM is fitted but the corresponding Molex link is set WEST the OS will see it as a 128Kbit device and access only the TOP ROM ie the part having the LOWER ROM number LC No Bottom ROM Link No Comments 1C35 3 2 S9 Molex West for 8K 16Kbyte 1044 5 4 511 Molex West for 8K 16Kbyte 1057 3 6 S12 Molex West for 8K 16Kbyte 1062 9 8 S15 Molex West for 8K 16Kbyte 1068 11 10 518 Molex West for 8K 16Kbyte System ROM LCTl 5 15 14 513 Molex South S19 EAST or b 1 0 513 Molex North S19 EAST Table 9 ROM Sockets The machine operating system is a 16Kbyte 128Kbit program which can be supplied in either a 128 or 256Kbit EPROM ROM If a 256Kbit device is used then the other half of the ROM will be the User Language Filing system that wi
200. te monitor colour monitor 6 cassette player 7 disc drive 8 frequency counter 4 7 2 Switch on Connect the mains supply and switch on Use the TUBE switch to turn off the 32016 processor One of the following will happen Situation a 60 There is noise on the monitor screen no signal from computer There is no power on beep sound there may be a continuous noise and the keyboard LEDs do not light or light incorrectly Results either power supply is dead or there is a fault in the heart of the microcomputer Follow the sequence of checks shown below 1 If there is no noise on power up and no LEDs light up then check the power supply 2 If a PET tester is available then use it The PET tester will work on the 6512 processor board providing the CPU is running and it can access the ROM although it may give strange screen output and some of the tests will fail Please refer to the information manual supplied to dealers for details of the operation of the PET tester when used with the 6512A If PET will not work at all then either the CPU isn t running or it cannot access the ROM 3 Check HS and VS signals pin 39 and pin 40 IC78 using an oscilloscope HS and VS should be clean TTL voltage levels HS pulsing every 64 us and VS pulsing every 20ms Results if they are stuck or floating then carry on with the checks below If they are working then the CPU must have programmed the 6845 and so must have gained access
201. terrupt request line which is open collector and asserted by a deviee pulling it low IRQ is level triggered active low ACW SERVICE MANUAL Issue 1 113 Chapter 6 NRST not reset pin 14 is output only active low system reset line It is aetive power up when the BREAK key is pressed NPGFC not page amp FC pin 10 is a signal decoded from the top 8 system address lines A8 to A15 is an aetive low signal which is low when the address high byte is amp FC ie when the full address is 00 to amp FCFF Four locations in this range are used by the Winchester system amp FC40 to amp FC43 inelusive see Table 5 in section 4 2 12 to A7 address low pins 27 to 34 arc the bottom 8 system address lines DO to D7 system data bus are the bi directional data lines Direction determined by R NW data lines are buffered and the buffer enabled only when NPGFC is aetive Pins 1 3579 11 13 15 17 and 26 are OV 6 6 2 1 0 Processor IMHz Bus Connector pinout Pin No 1 2 R NW 3 4 2 5 6 For other applications OV 7 8 NIRQ 9 10 0 11 12 For other applications OV 13 14 NRST OV 15 16 For other applications OV 17 18 DO D1 19 20 D2 D3 21 22 D4 D5 23 24 D6 07 25 26 OV AO 27 28 Al A2 29 30 A3 4 31 32 5 6 33 34 7 6 7 Winchester Disc Host Adapter In conjunction with the following description reference should be made to the Winchester Disc Host
202. the 6512 processor will operate 1 6 Software overview ACW SERVICE MANUAL Issue 1 7 1 1 6 1 Single processor mode In this mode the I O processor operates independently of the 32016 processor and all the facilities described in the BBC B Microcomputer System User Guide or I O Processor Guide are available Examples gt FREE gt CAT gt RUN A list of commands is given in the appendix 1 6 2 Dual Processor Mode With the TUBE switched on the 32016 processor is active and PANDORA running Pandora Commands The commands described in the BBC Microcomputer user guides are handed to the I O processor by PANDORA for execution by the I O processor execution Examples FREE CAT DIR 0 PANOS 32000 BASIC 32000 BASIC is BASIC version IV which is based on an earlier version BASIC I the language supplied with BBC Microcomputers Unlike most of the systems software provided with the equipment 32000 BASIC runs directly from Pandora the firmware kernel instead of from Panos the disc based operating system for the Cambridge Series computers 32000 BASIC contains several improvements on BASIC I a built in screen editor and faster execution especially in real arithmetic new statements are provided and much greater memory is available For some users the most significant difference between the two versions of BASIC will be the fact that 6502 assembly language cannot be incorporated into 32000 BASIC pr
203. the time constant switch causing a low impedance to appear on pin 12 and achieving a lower sensitivity and loop gain but providing a high degree of noise immunity During the locked condition the p 1 1 operates with a long time constant Line driver stage A Horizontal drive pulses from pin 3 of IC201 are DC coupled to TR201 and used to control the driver transformer T201 providing the impedance conversion to supply the 600mA forward base current which is required to saturate the line output transistor TR202 Ringing is damped by R225 and C214 at TR201 turn off thus limiting its Vice to a safe value The HT supply to the line driver comes from the main HT supply rail prior to R231 and HT scan interlock PL201 pins 5 and 6 allowing its operation to be checked independently of the line output stage Vertical sync output ACW SERVICE MANUAL Issue 1 29 Chapter 3 A The output of the field sync separator is used to drive the vertical sync output stage on pin 10 of IC201 B The pulse is also used internally to inhibit the first phase detector during the field sync period thus preventing top flutter resulting from equalising pulses 3 5 4 Line output Line ouput 1 L202 L203 and T202 primary are tuned during the flyback period by C222 This lasts for 11 8 11 15 2 The line output transistor 202 is driven directly from the secondary winding of T201 The on current is controlled by R227 while turn off dissipation is
204. tional links which connect internal termination resistors to ground These links should not be fitted 3691 Dual RS423 line driver D o p pin 10 drives the NRTS control line with an RS423 compatible signal C45 slew limits the signal to reduce electromagnetic radiation which might cause interference to other equipment Note in most applications this line can interface to an RS232 device 2 pin 15 drives the data line of an RS423 interface C44 slew limits the signal 4164EK8 SIL pack 64Kbyte DRAM 120ns access NOT FITTED ON ACW I O PROCESSOR This device can be fitted as an alternative to 8 off 64Kx1 DRAM integrated circuits ICs 55 56 60 61 64 65 66 67 ACW SERVICE 1 84 86 ACW SERVICE MANUAL Issue I 5 32016 Processor 5 1 Introduction The 4M byte 32016 processor is installed in the right hand side tray of the ACW The circuit is based arround the National Semiconductors 32016 series of processors and support devices which together provide a performance comparable with modern mini computers The circuit has been designed to allow operation at a processor clock rate of 10Mhz when using memory devices with a 150nS access time and a single wait state 5 1 1 Disassembly and assembly Removal and re assembly of the 32016 processor card is explained in section 2 4 5 2 General circuit description 5 2 1 Main Components A block diagram of the circuit is shown in Figure 5 2 1 a
205. to the OS ROM Check using PET see information manual supplied to dealers If the signals are there ACW SERVICE MANUAL Issue 1 I O Processor board but are not pulsing at the correct intervals then look for a data line fault to CRTC 4 Check that the NRS pin of the CPU pin 40 IC42 is high when the computer is switched on It should pulse low on power up and when the BREAK key is pressed If it is stuck low then look for shorts or damaged components around the 555 5 Check that there is activity on the SYNC pin 7 IC42 and the R NW pin 34 IC42 lines of the CPU If SYNC is stuck then the CPU has stalled and R NW won t be working anyway Check for address and data bus short or open circuit or a complete failure to select the OS ROM 6 Check the CPU clocks Phil and phi2 should be as shown in figure 1 If not then check the 2M circuitry from the video processor IC53 IC33 pin 3 should be low If not then check SYNC at pin 8 IC41 which should also be low If SYNC 1M is high then check IC25 If SYNC 1M is stuck high then find which one of the inputs to IC41 is stuck low The 1MHz device attached to this input must be checked 7 Check activity on the CPU address lines If after a BREAK the activity starts and then stops this suggests that the CPU cannot read the OS ROM Check the OS ROM by replacing it with a known good one Check that it is enabled and that all address lines are present Check following BREAK that NOE pulses low
206. track double sided disc ADFS treats floppy disc SIDES as one contiguous SURFACE refered to as DRIVE 4 in the ACW configuration The ACW ean also use the Acorn Disc Filing System The DFS employs standard frequeney modulation FM loosely referred to as single density storage resulting in a capaeity of 400 kilobytes per disc 200 kilobytes per side DFS treats FM floppy dise SIDES as two seperate SURFACES refered to as DRIVES 0 and 2 in the ACW configuration FM DFS Format Floppy Discs The format program is supplied in the Disc filing system DFS ROM This program only runs on the I O Proeessor 1 Turn off the 32016 co processor using the TUBE switch on the back of the keyboard The TUBE LED on the keyboard should be OFF 2 Select BASIC Prompt by typing Basic RTN 3 Select the DFS filing system type DISC RTN 4 Insert dise to be formatted into disc drive 5 Run formatter by typing FORMS80 RTN 6 In reply to the message Format Which Drive reply 0 RTN for the top side OR 2 RTN for the bottom side 7 In reply to the message CO Y N reply Y if you wish to proeeed 8 Formatting is finished when the BASIC prompt gt reappears To format BOTH sides the format program will have to be run TWICE ADFS Format Floppy Discs The format program is supplied on the ACW ADFS Utilities Disc See appendix This dise contains a suite of programs that run on the I O Processor 1 Turn off the 320
207. trol unit TCU These have a 32 bit internal architecture and use a 16 bit external data bus The Workstation also contains a 6512 processor an enhanced version of the 6502 processor which acts as an input output I 0 processor and can also be used independently In this case the Workstation acts as a BBC model B microcomputer with 64 Kbytes of memory The ACW is supplied with the PANOS operating system kernel PANDORA installed on the 32016 card This provides PANOS with an access mechanism to the various BBC filing systems in the 1 0 processor 4M bytes of internal RAM memory are provided as standard on the 32016 processor card and a 700Kbyte 80 track floppy disc and a 20Mbyte hard disc storage is fitted on the model 443 Keyboard activity the screen output disc interface network interface and other general I O tasks are all handled by the 6512A processor which has its own 64Kbytes of local RAM An integral 12 medium resolution colour monitor and a stand alone keyboard complete the standard specification A mouse controller which fits inside the main case is available as dealer installed optional upgrade 1 3 2 Main unit The upper case including the plastic screen surround moulding or bezel is removable The chassis is of modular construction and opens to reveal a number of surfaces which can be easily serviced See the section on disassembly for instructions Field servicing should be on a module replacement basis though sockete
208. ual Part Number 0410 009 The language manuals describe the implementation dependent features of the languages the compilation control parameters and diagnostic facilities The guides are not intended to serve as referenee manuals to the standard features of the languages BBC Microcomputer Related Documentation Expert or speeialist users may need access to particular manuals written for the BBC Microcomputer BBC B Microcomputer System User Guide Part Number 0433 000 Issue 1 Oetober 1984 Disc Filing System User Guide Part Number 0403 700 Issue 2 1983 Winchester Disc Filing System User Guide Part Number 0427 00 1 Issue 1 1984 Econet Level 2 File Server User Guide Part Number 0412 018 Issue 1 1983 Econet Level 2 File Server Manager s Guide Part Number 0412 017 Issue 1 1983 134 ACW SERVICE MANUAL Issue 1 Guide Documentation BBC Microcomputer A pplication Notes The following hardware application notes are available 1 Mhz Bus Application note Customer Serviees Dept Acorn Computers Ltd Third Party Documentation In addition the following items of third party doeumentation may prove useful Microvitec Service Manual Microvitec plc Futures Way Bolling Road Bradford BD4 7TU Tel 0274 390011 6512A Microprocessor Handbook 7002 A DC Data Sheet 6522 VIA Data Sheet 6845 Video Controller Data Sheet 6850 A CIA Data Sheet 32000 Series Data Sheets National Semieonductors The
209. ulse Phase detector output on pin 13 is filtered and fed to the voltage control input of the oscillator on pin 15 2 The second phase detector compensating for delays introduced by the line output stage and compares line flyback pulses at pin 6 with the oscillator output Phase detector output consists of a bi directional current source used to charge discharge C213 on pin 5 The voltage derived from C213 is used to control a phase shifter which regulates the phase of the output pulse on pin 3 Pin 5 also provides a line shift function by offseting the voltage developed across C213 charged from VR220 R221 and R222 allowing a phase shift of or 1uS between the line scan and the video information 3 705 gate pulse from the line oscillator the phase position of which is centred around the horizontal sync pulse The gated pulse is used to control the arrival of sync pulses at the sync phase detector for a duration of 745 allowing latching and de latching of the line oscillator obtained by a coincidence detector which compares the phase gate pulse with that of incoming syncs 4 When the two signals are not aligned the coincidence detector is used to switch a p 1 1 filter into a short time constant mode giving a high imput impedance at pin 12 thus increasing sensitivity and loop gain of the oscillator The phase locked loop now has a low noise immunity but has a very wide capture range When aligned the coincidence detector activates
210. utputs by 220 ohm resistors the 100K resistor of the grid and the 820K resistor of AI 3 Decoupling of the grid and Al is performed by C910 and C911 4 The focus voltage is provided by a potential divider located within the tripler module providing an adjustable voltage of 5 8KV 5 The AI voltage is adjusted by VR932 offering a range of 350 820 volts 6 The CRT heaters may be disconnected by removing TL901 This is to enable video adjustments to be made 7 The CRT cathodes arc directly driven from the video output stages mounted on the CRT panel Video output stages Since the red green and blue video output stages are identical the description given here is for the red stage only 1 TR902 forms a class A amplifier with AC gain derived from the ratio of 935 902 and VR903 and DC gain derived from a DC offset current set by the ratio of R905 and VR906 2 R904 forms a video output load 3 When in conduction the CRT input capacitance sees TR902 as a low impedance drive source 4 Video compensation which helps maintain a constant amplifier response curve over the full range of VR903 is achieved by the split capacitances of C902 and C903 5 The video black level voltage is set by a DC reference of approximately 7 5V connected to the emitters of TR902 TR904 and TR906 6 TR907 performs line and field blanking TR907 is driven by negative going mixed blanking pulses from TR102 A 7 5V black level referen
211. various points on the board Chapter 5 5 7 7 Boot start up Sequence The Boot sequence is described in the preceeding text Having checked that the reset system is operational it is worth examining the signal BOOTING which can be found on Pin 6 1C15 This signal is low for a very short period after reset one or two instructions and then remains high until the next reset If this signal is correct it indicates that the processor is able to fetch and execute the first few instructions in the EPROM and usually the fault is elsewhere 5 7 8 Tube Signals After reset the processor should output a message similar to PANDORA 32016 version X XX Memory size a 4096 kilobytes Acorn ADFS OR PANDORA 32000 2 00 4096 KB Acorn ADFS This message is passed through the TUBE by the processor While this message is being transferal there should be activity on the TUBE chip select Pin 21 If this message is displayed there is a good chance that the tube and processor are functioning 5 7 9 Floating Point Faults If the floating point chip is faulty it will usually show up in one of two ways It will either not respond when asked to perform floating point arithmetic or will more rarely give the wrong answer In the first case the processor may appear dead because PANDORA checks for the presence of an FPU if the configuration links say there should he one A quick test would be to remove the FPU configuration link and p
212. wise check for short circuit tracks on data lines on both the printer side and the CPU side of the VIA A better test is to use the binary configuration 10101010 on the outputs and then change it to 01010101 These correspond to the values and 455 This way short circuits are more likely to give the wrong value in the tests Connect a known good printer to the microcomputer Check that the printer strobe output from the VIA pin 39 IC10 gives a 4us negative going pulse when the computer is instructed to print If it does then check this pulse at pin 14 IC13 If the printer interface is working correctly then there should be regular strobe pulses until the printer buffer is full If there is only a single pulse then check the printer ACK input pin 40 0 These two lines together strobe and ACK perform the data control handshake and on being instructed to print the two signals ought to alternate until the printer buffer is full If the computer is sending a strobe pulse but no ACK is coming back from the printer then the connections to the edge connector PL9 arc faulty If the strobe pulse is not being sent then the fault is either a broken track or the VIA chip itself 4 7 13 User port Use a PORT tester to check that the user port is faulty Test the VIA IC10 by writing values to it and testing the outputs First configure all the data lines as outputs by writing amp FF to the data direction register B DDRB amp FE62 amp FF
213. y memory must still be amp 3000 to amp 7FFF To keep the CRTC address as seen by the RAM multiplexer correct an offset is conditionally added to the actual CRTC address The offset is 12K As the address logic does not generate an address above amp 8000 there is no use for address line A15 11 Thus when the CRTC scrolls above amp 8000 it appears to address amp 0000 upwards By adding 12K the RAM address becomes amp 3000 upwards So although the CRTC outputs an address outside the allowed RAM address the adder causes the true address to remain in the allowed range of amp 3000 to amp 7FFF This principle is used for all graphic screen modes ie all but mode 7 There are four different graphic screen sizes 8 10 16 20Kbytes The adder therefore needs to add an offset of 24K 22K 16K 12K respectively The operating system gives 2 bit code labelled CO C1 which is decoded to give the adder offset for the current screen mode CO Offset adder input B4 B3 B2 Bl 0 16K 022275 2 T 8K d 20r l 0 20K QI Ole 2 1 10K 1010 LM386 Audio power amplifier This IC is a low cost amplifier with a fixed voltage gain of about 26db C24 and R58 are needed to give load independant output stability freedom from parasitic oscillation 6845 CRTC controller The is responsible for all VDU address generation It is a programmable device which once set up independently generates the RAM address sequence for a wide range of display formats
214. y are memory mapped The bus contains the least significant 8 bits of the address bus and two signals decoded from the high order 8 bits of the address These are labelled NFC and NFD and are active low These signals are decoded from high address bytes 16 FC and 16 FD Rear Pnl 1 0 PCB Signal Rear Pnl I O PCB Signal 37 way IDC function 37 way IDC function 1 1 OV 20 2 R NW 2 3 OV 21 4 1MHzE 3 5 OV 22 6 NNMI 4 7 OV 23 8 NIRQ 5 9 OV 24 10 NPGFC 6 11 OV 25 12 NPGFD 7 13 OV 26 14 NRST 8 15 OV 27 16 Analog Input 9 17 OV 28 18 DO 10 19 DI 29 20 D2 11 21 D3 30 22 D4 12 23 D5 31 24 D6 13 25 D7 32 26 OV 14 27 AO 33 28 Al 15 29 A2 34 30 A3 16 31 A4 35 32 AS 17 33 6 36 34 7 18 35 37 36 19 37 No connection Table 4 Connections for 1 MHz Bus The bus connections are shown in Table 4 For a detailed description reference should be made to the 1 MHz Bus Application Note Acorn No 0407 000 available from the Customer Services Dept Acorn Computers On the ACW a 37 way D type connector is used The signals are buffered by LSTTL devices Software Interface The bus may be accessed by OSBYTE calls as in the table below Read Write Assert 16 FC OSBYTE 146 OSBYTE 147 Assert 16 FD OSBYTE 148 OSBYTE 149 Param 1 holds the address offset For reading Result is the data byte taken from the bus for writing Param2 is the data byte to be written ACW SERVICE MANUAL Issue 1 49 Chapter 4 Some system p
215. y the corresponding keyboard keys rather than the actual words It is assumed that command lines are terminated by Refer to the keyboard diagram for actual symbols used on these keys 2 In examples where commands have to be typed in response to a prompt e g the Panos prompt gt both the command and the prompt are shown for example cat help 3 References to left and right hand apply when the unit is viewed from the FRONT unless otherwise stated Abrieviations The following abrieviations are used in this manual N Active low signal eg NCAS LSB AO D0 etc MSB A23 D15 etc Word two bytes 16 bits Double Word four bytes 32 bits Quad eight bytes 64 bits NYA Not yet available RSVD Reserved for future Acorn use HHHHHH Hex Hexadecimal notation BBBBBB Bin Binary notation 1 2 1 ACW documentation The ACW 443 comes complete with the following documentation e ACW welcome guide e Terminal emulator user guide e BBC BASIC IV reference manual e ACW function keycard booklet Panos documentation pack A seperate package Documentation titles together with their Acorn part numbers are shown in the appendix ACW SERVICE MANUAL Issue 1 3 1 1 3 Hardware overview 1 3 1 ACW 443 The ACW uses the National Semiconductor 32000 chip set including the NS32016 Central Processing Unit CPU the NS32081 Floating Point Unit FPU and the 32201 timing and con

ACORN COMPUTERS LTD. ACW 443 SERVICE MANUAL

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