MicroBlaze Microcontroller Reference Design User Guide v1.5
Contents
1. MicroBlaze Microcontroller Reference Design User Guide v1 5 UG133 v1 5 September 12 2005 XILINX gt XILINX Xilinx and the Xilinx logo shown above are registered trademarks of Xilinx Inc Any rights not expressly granted herein are reserved CoolRunner RocketChips Rocket IP Spartan StateBENCH StateCAD Virtex XACT XC2064 XC3090 XC4005 and XC5210 are registered trademarks of Xilinx Inc The shadow X shown above is a trademark of Xilinx Inc ACE Controller ACE Flash A K A Speed Alliance Series AllianceCORE Bencher ChipScope Configurable Logic Cell CORE Generator CoreLINX Dual Block EZTag Fast CLK Fast CONNECT Fast FLASH FastMap Fast Zero Power Foundation Gigabit Speeds and Beyond HardWire HDL Bencher IRL J Drive JBits LCA LogiBLOX Logic Cell LogiCORE LogicProfessor MicroBlaze MicroVia MultiLINX NanoBlaze PicoBlaze PLUSASM PowerGuide PowerMaze QPro Real PCI RocketlO SelectlO SelectRAM SelectRAM Silicon Xpresso Smartguide Smart IP SmartSearch SMARTswitch System ACE Testbench In A Minute TrueMap UIM VectorMaze VersaBlock VersaRing Virtex Il Pro Virtex Il EasyPath Wave Table WebFITTER WebPACK WebPOWERED XABEL XACT Floorplanner XACT Performance XACTstep Advanced XACTstep Foundry XAM XAPP X BLOX XC designated products XChecker XDM XEPLD Xilinx Foundation Series Xilinx XDTV Xinfo XSI XtremeDSP and ZERO are trademarks of Xilinx2. Inc The Programmable Logic Company is a service mark of Xilinx Inc All other trademarks are the property of their respective owners Xilinx Inc does not assume any liability arising out of the application or use of any product described or shown herein nor does it convey any license under its patents copyrights or maskwork rights or any rights of others Xilinx Inc reserves the right to make changes at any time in order to improve reliability function or design and to supply the best product possible Xilinx Inc will not assume responsibility for the use of any circuitry described herein other than circuitry entirely embodied in its products Xilinx provides any design code or information shown or described herein as is By providing the design code or information as one possible implementation of a feature application or standard Xilinx makes no representation that such implementation is free from any claims of infringement You are responsible for obtaining any rights you may require for your implementation Xilinx expressly disclaims any warranty whatsoever with respect to the adequacy of any such implementation including but not limited to any warranties or representations that the implementation is free from claims of infringement as well as any implied warranties of merchantability or fitness for a particular purpose Xilinx Inc devices and products are protected under U S Patents Other U S and foreign patents pending Xil
3. Separates items in a list of choices lowpwr on off Vertical ellipsis Repetitive material that has been omitted IOB 1 Name QOUT IOB 2 Name CLKIN Horizontal ellipsis Repetitive material that has been omitted allow block block name loc1 loc locn Online Document The following navigation conventions are used in this document Convention Blue text Meaning or Use Cross reference link to a location in the current document Example See the section Additional Resources for details Refer to Title Formats in Chapter 1 for details Red text Cross reference link to a location in another document See Figure 2 5 in the Virtex II Handbook Blue underlined text Hyperlink to a website URL Go to http www xilinx com for the latest speed files MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 www xilinx com 2 XILINX Chapter 1 Microcontroller Reference Design Overview Introduction When selecting an embedded microcontroller typically an engineer will list the required features and then select a stand alone off the shelf microcontroller or processor that has those features In most cases there are additional features or peripherals that are not need but are included non the less When using a Soft Processor in an FPGA an engineer has an opportunity to select from pre created mic
4. are used as the two operands T switches SYO through SW3 are used as the binary representation c gt C xilins_projec Figure 2 3 Software Selection when FPGA is Configured MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 www xilinx com 10 Downloading the Design and Launching XPS XILINX Loading the Calculator _App Software Application To configure the hardware system and to load the software application into the Spartan 3 Evaluation Board using the Digilent JTAG3 cable perform the following steps 1 Connect the Digilent JTAG3 cable to the J7 header on the Spartan 3 Evaluation Board and connect the other end to the parallel port of the PC If using the Parallel Cable IV make sure that the status light is lit on the cable 2 Connect the Serial cable to J2 on the Spartan 3 Evaluation Board and to the serial port of the PC On the PC using hyperterminal make certain that the bit rate is set for 57600 bps and No Parity of the the serial port Turn on the power on to the Spartan 3 Evaluation Board In XPS to make sure that the ELF file is up to date use Tools gt Update Bitstream There may be a warning Processor microblaze_0 has XMDSTUB mode application but xmdstub elf is not marked for download do you want to continue Click YES 5 In XPS select Tools gt Download to download the new bitstream into the FPGA The xmd stub warning will appear again Pl
5. integrated a MicroBlaze Microcontroller into an FPGA and executed software code For additional information on MicroBlaze and the EDK tools go to http support xilinx com MicroBlaze Microcontroller Ref Des User Guide www xilinx com 14 UG133 v1 5 September 12 2005 XILINX Reference Design Building Blocks Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 Reference Design Building Blocks Application The block diagram of the MicroBlaze Microcontroller used in this MicroBlaze Controller Reference Design is shown in Figure 3 1 The design components include an Internal Block RAM memory an R5232 UART 4 GPIO blocks SRAM Memory Controller Interrupt Controller Timer and a JTAG_UART used for software debugging This configuration utilizes approximately 79 of a Spartan 3 XC35200 device Interrupt ri External Memory Controller ie Controller EMC OPB Clock Reset Interrupt 4X UART GPIO JTAG_UART JTAG Ports Dual Ported BlockRAM BRAM ug133_02_01 Figure 3 1 MicroBlaze Microcontroller Block Diagram Some applications for the MicroBlaze processor include Industrial Controller Consumer Application Office Automation Data Communication MicroBlaze Microcontroller Ref Des User Guide www xilinx com 15 UG133 v1 5 September 12 2005 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 gt XILINX Features 16 e MicroBlaze Version 4 Micropr
6. 4 Confirm that Mark to Initialize BRAMSs is not checked for the other projects or for the default applications The graphic to the left of each application should appear as a green arrow with a red X over it Verify that this is the case for microblaze_0_bootloop microblaze_0_xmdstub and Project TestApp If any are set right click and confirm that Mark to Initialize BRAMs is not checked If checked click to deselect it The green arrow should then appear with a red X MicroBlaze Microcontroller Ref Des User Guide www xilinx com 19 UG133 v1 5 September 12 2005 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 File Edit View Project Tools Options Window Help Cs oe S ell Alle e NI awa MONICA VI f Xilinx Platform Studio C mb_mcu_Refdes2 system xmp C mb_mcu_Refdes BEI 7 XILINX o x tab Ha we edela LE le SRE BE fr x x Ready HHFHHAHHHHHAAHHAHHAAHAAHHAHHA AHH HHA AHA HH RAHA AHH HHA HHA H ETH A Created by Base System Builder Wizard for Xilinx EDK 7 1 1 Bu Fri May 13 15 32 50 2005 03 Target Board Xilinx Spartan 3 Starter Board Rev E 04 Family spartan 05 Device XC3S200 OS Package FT256 OF Speed Grade 4 0 Processor Microblaze 09 System clock frequency 50 000000 MHz 10 Debug interface On Chip HW Debug Module 14 On Chip Memory B 12 Total Off Chip Memory 1 MB 13 SRAM 256Kx32 14
7. AT THIS IMPLEMENT IS FREE FROH ANY CLAIMS OF INFRINGEMENT AND YOU ARE RESPONSIBLE FOR OBTAINING ANY RIGHTS YOU MAY REQUIRE FOR YOUR IMPLEMENTATION XILINX EXPRESSLY DISCLAIMS ANY WARRANTY WHATSOEVER WITH RESPECT THE ADEQUACY OF THE IMPLEMENTATION INCLUDING BUT NOT LIMITED TC XILINX IS PROVIDING THIS DESIGN CODE OR INFORMATION AS IS AS Executable C xilinx_projects mb_mc6 3 mt Compiler Options Sources E C ailinx_projectswmb_mc6 3 mb_mcu_ Headers k Project Calculator_App Processor microblaze_0 Executable C xilinx_projects mb_mc6 3 mt Compiler Options v lt gt ANY WARRANTIES OR REPRESENTATIONS THAT THIS IMPLEMENTATION IS FR FROH CLAINS OF INFRINGEMENT IMPLIED WARRANTIES OF MERCHANTABILI AND FITNESS FOR PARTICULAR PURPOSE KKK RK RK kk kkk RRR ra Kilinx EDK 6 3 EDK_Gmm 11 2 Vie JU K kk This file is a sample test application C xilins_projec x Console Log z PM_SPEC Xilinx path component is lt C xilinx6_3 EDK Gmm10 1 gt Project Opened Figure 2 4 Software Selection with a BOOT loader Loading the microblaze_0_xmdstub Software Application To configure the hardware system and to load the software application into the Spartan 3 Evaluation Board using the Digilent JTAG3 cable perform the following steps 1 Connect the Digilent JTAG3 ca
8. HHHH HAHAHAHA AA AAAHHH AAA AARHH REAR H HHH ee eee _ Right Click for Options pi Created by Base System Builder Wizard for Xilinx EDK 7 1 1 E J LEDs_SBit a Wed May 11 14 23 38 2005 t s LED_ SEGMENT Target Board Xilinx Spartan 3 Starter Board Rev E ft Push_Buttons_3Bit Family spartan3 JF DIP_Switches_8Bit apd it aes SRAM_256Kx 32 ackage i a sie Speed Grade 4 opb_timer_1 JIE opb_intc_0 Processor Microblaze T SRAM_256Kx32_utilbus_split_2 System clock frequency 50 000000 MHz JE dcm_0 Debug interface EMD Debug with Stub Project Fies On Chip Memory 16 KB aipa Total Off Chip Menory 1 MB f MHS File system mhs SRAM_ 256Kx32 1 MB E MSS File system mss E PBD File system pbd H HHAFHHHHHAAHHHHH HAHAHAHAHA AAAHHH AA AAARHHH AAA A AHHH EERE T El UCF File data system uct an El iMPACT Command File etc download 23 PARAMETER VERSION 2 1 0 E Implementation Options File etc fastr 24 E Bitgen Options File etc bitgen_spartar 25 EA Project Options 26 PORT fpga_0_RS232_RX_ pin fpga_0_ RS232_RX DIR INPUT Device xc3s2008256 4 27 PORT fpga_0_RS232_TE_pin fpga_O_RS232_TX DIR OUTPUT b Netlist TopLevel i S lt iil gt C EDK 4d lt C mb_mcu AQ CAmb_meu http supp Created pcores directory Copied file bitgen ut from XILINX EDK data zxflow directory to etc directory Copied file bitgen_spartan3 ut from XILINKX_EDK data directory to et
9. HHHHHHHAPHHHHHAHHHHHHA AHH HHHA HHA HHH AHHH SHAK HHR HHA HHA HHH HES System Applications Right Click for Options E Software Projects A eX Default microblaze_0_bootloop ek Default microblaze_O_xmdstub n Project Interrupt_demo Processor microblaze_0 Executable C mb_mcu_Ri Compiler Options F Sources Headers Project Simple_Clock Processor microblaze_0 Executable C mb_mcu_Ri Compiler Options v lt gt 17 PARAMETER VERSION 2 1 0 4 _ lt an iv CAEDK d QC mb_meu Console Log Project Opened Figure 3 3 Software Selection when FPGA is Configured Loading the Project Interrupt_ demo Software Application To configure the hardware system and to load the software application into the Spartan 3 Evaluation Board using the Digilent JTAG3 cable perform the following steps 1 Connect the Digilent JTAG3 cable to the J7 header on the Spartan 3 Evaluation Board and connect the other end to the parallel port of the PC If using the parallel cable IV make sure that the status light is lit on the cable Connect the serial cable to J2 on the Spartan 3 Evaluation Board and to the serial port of the PC On the PC using HyperTerminal make certain that the bit rate is set for 57600 bps and No Parity of the the serial port Turn on the power to the Spartan 3 Evaluation Board In XPS to make sure that the ELF file is
10. _ demo Software Application with XMD_STUB 1 In XPS select Tools gt Software Debugger to open the GDB interface Source Window Choose Interrupt_demo from the User Application window In GDB select the File gt Target Settings to display the Target Selection dialog box as shown in Figure 3 5 Configure the Target Selection dialog box to match Figure 3 5 then click OK In Source Window gt Run click RUN Doing so will download the executable elf file located in the TestApp directory into the device In Source Window the user can select Continue Single Step Set Break Point to view source code registers and memory contents From Control Tag select Continue If the Spartan 3 Evaluation Board executes the application test program properly LEDS on the board will flash Note Begin from step 2 to configure the device prior to loading a new application program and debugging Make certain to Close all XMD and GDB windows Target Selection K Mw Set breakpolnt at rain Target Remote TCP XMD Ww Set breakpoint at exit Hostname lacalhost Set breakpoint at fees 1234 W Display Download Dialog Use xterm as hferior s tty ceca oe Figure 3 5 Target Selection for Software Debugger gt More Options Loading the Simple_Clock Software Application with XMD_STUB To download and execute the Simple_Clock demonstration program repeat the procedure in the Loading the Interrupt_demo Software Applic
11. ard see http www xilinx com products spartan3 s3boards htm Xilinx Parallel Cable used to program and debug the device Serial Cable for connection to the RS232 UART via HyperTerminal The next sections of this document will discuss Downloading the reference design and test application Launching Xilinx Platform Studios XPS Downloading the Reference Designs Go to the MicroBlaze lounge at http www xilinx com microblaze_mcu_refdes1 Download the reference design starting with the MB_MCU_RefDes1 zip archive Downloading the Design and Launching XPS 1 Go to the MicroBlaze lounge at http www xilinx com microblaze_mcu_refdes1 and download the MB_MCU_RefDes1 zip archive On the target drive unzip themb mcu_Refdes2 EDK7 1 zip file This will automatically create a subdirectory for the project MB_MCU_RefDes1 zip Assuming that the Xilinx Platform Studio XPS has been installed launch XPS at this time using Start gt Programs gt Xilinx Platform Studio gt Xilinx Platform Studio Once in XPS select the menu option File gt Open Project Using the browser navigate to where the project exists and double click on System xmp The system showing the prebuilt MicroBlaze Microcontroller Reference System configuration is shown in Figure 2 1 MicroBlaze Microcontroller Ref Des User Guide www xilinx com 8 UG133 v1 5 September 12 2005 Downloading the Design and Launching XPS gt XILINX I E Ps Xilinx Platform Stu
12. ation with XMD_STUB section beginning with step 1 In step 5 choose Simple_Clock instead of Interrupt_demo See the Running the Simple_Clock program This program uses the timer and seven segment display to demonstrate a Simple_ Clock The timer is set to interrupt every minute The frequency is set in the code Each time that there is an interrupt from the timer the seven segment display increments the minutes and Hours and the LEDs The initial time can be set by pressing the push button BTN2 to set Hours and BTN1 to set Minutes respectively MicroBlaze Microcontroller Ref Des User Guide www xilinx com 23 UG133 v1 5 September 12 2005 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 gt XILINX Additional MicroBlaze and EDK Information Congratulations you have successfully integrated a MicroBlaze Microcontroller into an FPGA and executed software code For additional information on the MicroBlaze Microcontroller and the EDK tools see http support xilinx com 24 www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005
13. ble to the J7 header on the Spartan 3 Evaluation Board and connect the other end to the parallel port of the PC If using the Parallel Cable IV make sure that the status light is lit on the cable 2 Connect the Serial cable to J2 on the Spartan 3 Evaluation Board and to the serial port of the PC On the PC using hyperterminal make certain that the bit rate is set for 57600 bps on the serial port 3 Turn on the power to the Spartan 3 Evaluation Board 4 In XPS to make sure that the ELF file is up to date select Tools gt Update Bitstream Note Close all other XMD and GDB windows before downloading the configuration bits 5 In XPS select Tools gt Download to download the hardware configuration and load xmdstub into the BRAM memory Note Close all other XMD and GDB windows before downloading the configuration bits 6 In XPS select Tools gt XMD to open an XMD utility XMD is a JTAG utility that can be used to download and debug software XMD is also a server for GDB the GNU debugging utility MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 www xilinx com 13 Additional MicroBlaze and EDK Information gt lt XILINX Loading the TestApp Software Application with XMD_STUB 1 In XPS select Tools gt Software Debugger to open the GDB interface Source Window Choose TestApp from the User Application window In GDB select File gt Target Settings to display the Target Selection dialog b
14. bugger to provide application software debugging capabilities XMD uses a JTAG _UART to communicate with xmdstub on the board xmdstub is an executable software loaded into local system memory at startup Supports run time control such as Run Single Step Breakpoint View Registers and View Memory as well as debug parameters For the latest data sheet see the proc_ip_ref_guide pdf file located at EDK installation lt EDK gt doc proc_ip_ref_guide pdf For additional examples and reference designs see http www support xilinx com ise embedded edk_examples htm www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 gt XILINX Getting Started Getting Started System Requirements The following software must be installed on your PC to utilize this reference design e Windows 2000 SP2 Windows XP e EDK 7 1 SP1 or later Must be the same version as ISE e ISE 7 11 SP2 or later To download the completed reference design the following hardware is required e Xilinx Spartan 3 Evaluation Board For information on the evaluation board see http www xilinx com products spartan3 s3boards htm e Xilinx Parallel Cable used to program and debug the device e Serial Cable for connection to the RS232 UART via HyperTerminal The next sections of this document will discuss e Downloading the reference design and test application e Launching Xilinx Platform Studios XPS Downloa
15. c directory Copied file fast_runtime opt from XILINX EDK data zflow directory to etc directory WARNING MDT Created an empty C mb_mcu_Refdes2 data system ucf If your design needs any constraints oo Opened lt il gt Output A Warning A Error Ready Figure 3 2 Xilinx Platform Studio XPS Updating and Generating Hardware Files At this point XPS is open to the selected hardware application No modifications are needed to run this design All the hardware features and peripherals have been pre loaded and pre set The Hardware Application can run any number of Software Applications When the Base System Wizard is used to create a Hardware System it will create also a simple Software Application to test the selected Hardware features and peripherals To make certain that all the Hardware files have been created in XPS select Tools gt Update Bitstream Doing so will run any of the programs needed to generate the Hardware Application for this reference design The message panel should read Memory Initialization completed successfully Done or if all files are up to date then it will read make Nothing to be done for init_bram Done 18 www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 gt XILINX Downloading the Design and Launching XPS Downloading Design Files to the FPGA The following two sections illustrate two methods of downloading a Software Ap
16. ded in the tools or provided with this design Guide Contents This manual contains the following sections Chapter 1 Microcontroller Reference Design Overview Chapter 2 MicroBlaze Microcontroller Reference Design Number 1 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 MicroBlaze Microcontroller Ref Des User Guide www xilinx com 1 UG133 v1 5 September 12 2005 Additional Resources XILINX Additional Resources For additional information go to http support xilinx com The following table lists some of the resources available from this website You can also directly access these resources using the provided URLs Resource Description URL Tutorials Tutorials covering Xilinx design flows from design entry to verification and debugging http support xilinx com support techsup tutorials index htm Answer Browser Database of Xilinx solution records http support xilinx com xInx xil_ans_browser jsp Application Notes Descriptions of device specific design techniques and approaches http support xilinx com apps appsweb htm Data Sheets Device specific information on Xilinx device characteristics including readback boundary scan configuration length count and debugging http support xilinx com xInx xweb xil_publications_index jsp Problem Solvers Interactive tools that allow you to troubleshoot your design issues http support xilinx com support troubleshoot
17. ding the Reference Designs Go to the MicroBlaze Microcontroller lounge at http www xilinx com microblaze_mcu_refdes2 EDK7 1 Download the reference design starting with the mb_mcu_Refdes2 EDK 7 1 zip archive Downloading the Design and Launching XPS 1 Go to the MicroBlaze lounge at http www xilinx com microblaze_mcu_refdes2 EDK7 1 and download the mb_mcu_Refdes2 EDK7 1 zip archive 2 On the target drive unzip the mb mcu_Refdes2 EDK7 1 zip file This will automatically create a subdirectory for the project mb_mcu_Refdes2 EDK7 1 zip Assuming that the Xilinx Platform Studio XPS has been installed launch XPS at this time using Start gt Programs gt Xilinx Platform Studio gt Xilinx Platform Studio 3 Once in XPS select the menu option File gt Open Project Using the browser navigate to where the project exists and double click on System xmp The system showing the prebuilt MicroBlaze Microcontroller Reference System configuration is shown in Figure 3 2 MicroBlaze Microcontroller Ref Des User Guide www xilinx com 17 UG133 v1 5 September 12 2005 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 XILINX Xilinx Platform Studio C mb_mcu_Refdes2 system xmp C mb_mcu_Refdes2 s BE AF File Edit View Project Tools Options Window Help j gt a x Ce fo S See sl le fre x are eha vi slfle alolel mel le sel sel RE fe xl x a System Applications H HHAHHHHHHAAH
18. dio c mb_mcu_refdes1 c mb_mcu_refd O X File Edit View Project Tools Options Window Help X O fe Sd BAM eh Ge CS i En the E mo B i a fo En x Z xl o0 HHEPPAEHAAHHHA RAHA AERA A EAA AAPA AE EE AE EN A System appicatons Options Symbols Ry Dz Created by Base System Builder Wizard os Mico Cie IRURE Bt Tue Aug 24 09 30 47 2004 05 y artem 0 5 w Target Board Xilinx Spartan 3 Demo E cry TES ee OF Family Spartan Driver cpu_v1_00_a os Device EC3S200 Debug Peripheral debug module DE o F Package FT256 05 standalone 1 00 10 Speed Grade 11 E Generated Header microblaze 0 eee ee H mb_opb 13 System clock frequency 50 MHz T debug_ module E i4 ot Debug interface EMD Debug with Stub ilmb 1i On Chip Memory 16 EB dmb 16 Total Off Chip Memory 512 EB 17 SRAM 256Exe32 512 EB dmb crtl 18 JE iimb_entir 19 ff HHAAPHHHHHAAAAAEHHSAAA AAR H REHEAT J mt brar 7 AS232 22 JE LEDs SBi ee PARAMETER YERSIOW 2 1 0 La LED_ SEGMENT ijd gt lt Mm gt co mb_mcu_retd Console Log Project Opened Warnings Errors Ready Figure 2 2 Xilinx Platform Studio XPS Updating and Generation Hardware Files At this point XPS is open with the selected hardware application No modifications are needed to run this design All the hardware features and peripherals have been pre loaded and pr
19. e set The Hardware Application can run any number of software applications When the Base System Wizard is used to create a Hardware System it also will create a simple Software Application to test the selected Hardware features and peripherals To be sure that all the Hardware files have been created in XPS please select Tools gt Update Bitstream This will run any of the programs needed to generate the Hardware Application for this reference design The message panel should read Memory Initialization completed successfully Done or if all files are up to date then it will read make Nothing to be done for init_bram Done MicroBlaze Microcontroller Ref Des User Guide www xilinx com 9 UG133 v1 5 September 12 2005 Downloading the Design and Launching XPS XILINX Downloading Design Files to the FPGA The following two sections illustrate two methods of downloading a software application into the FPGA The first method is when the software application can be incorporated into the FPGA bitstream The second method illustrates loading a selected application into the FPGA using the GDB debugger for software development and debugging Selecting a Software Application to Run When the FPGA is Configured In this step the software application that will be loaded when the FPGA is initially loaded with a new bitstream will be selected Select the XPS Software Application tab There are 3 options that can be selected w
20. ease click YES Note Close all other XMD and GDB windows prior to downloading a configuration bits Running the Calculator_App program After the Calculator_App has been loaded the hyperterminal should show Simple Calculator App for Spartan 3 Starter Kit Push button to start math operation The Calculator_App is a simple 3 function calculator The 3 right most push button switches are Add BTNDO Sub BIN1 Mult BTN2 The left most push button switch BTN3 is a program reset which will clear the calculator program If the reset is pushed at this time then the FPGA will need to be re loaded The eight toggle switches directly under the 7 Segment display are divided into two 4 bit words When the Add Sub or Mult push button switches are pushed the selected calculator operation will be performed on the value of the toggle switches If the toggle switches are set to Sw7 off Sw6 off Sw5 off Sw4 off Sw3 off Sw2 off Swi off SwO off Where Word 1 is 0 and Word 0 is 0 Add 0 0 0 Sub 0 0 0 Mult 0 0 0 If the toggle switches are set to Sw7 off Sw6 off Sw5 off Sw4 ON Sw3 off Sw2 off Swi ON SwO ON Where Word 1 is 1 and Word 0 is 3 Add 3 1 4 Sub 3 1 2 Mult 3 1 3 MicroBlaze Microcontroller Ref Des User Guide www xilinx com 11 UG133 v1 5 September 12 2005 Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is 7 XILINX Each time one of the Push Button switches is pressed the r
21. eee ee ee noe Sea es T Downloading the Reference Designs 8 Downloading the Design and Launching XPS 8 Updating and Generation Hardware Files 9 Downloading Design Files to the FPGA 2 10 Selecting a Software Application to Run When the FPGA is Configured 10 Loading the Calculator_App Software Application 11 Running the Calculator_App program 2 11 Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is Configured and the Processor is Running 12 Updating and Generation Hardware Files 12 Loading the microblaze_O_xmdstub Software Application 13 Loading the TestApp Software Application with XMD_STUB 14 Loading the Calculator_App Software Application with XMD_STUB 14 Additional MicroBlaze and EDK Information 14 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 Reference Design Building Blocks 15 APP UCO 5225455555444 ee caer FAAEE eee s tar nesusesas RET EEST 15 RAR SR Re DREAN dede beer barra yy cod ei coins 16 Getting SR a 17 DNS CN RUB ee a 0 edad gh du do one con 17 Downloading the Re
22. ernal Block RAM memory an RS232 UART 4 GPIO blocks and a JTAG_UART used for oftware debugging This configuration utilizes approximately 50 of a Spartan 3 S XC3S200 device Clock MicroBlaze DOPB CPU Core Reset Interrupt JTAG_UART JTAG Ports Dual Ported BlockRAM BRAM xip312 Figure 2 1 MicroBlaze Microcontroller Block Diagram Some applications for the MicroBlaze processor include Industrial Controller Consumer Application Office Automation Data Communication MicroBlaze Microcontroller Ref Des User Guide www xilinx com UG133 v1 5 September 12 2005 Features XILINX Features e MicroBlaze Microprocessor 50 MHz on the Spartan 3 Starter Kit Board derived from the 50 MHz crystal on board Instruction cache and data cache options disabled 32 32 bit general purpose registers with 32 bit address and 32 bit data buses Single cycle execution Direct access to the register file using Fast Simplex Link FSL e Unified instruction and data BRAM into single memory for both instruction and data segments Dual port 16 KB internal blockRAM memory structure 2 cycle read access from BRAM via the Local Memory Bus LMB e RS232 UART Controller Pre configured for 57600 baud rate e General purpose input output ports GPIO 8 bit GPIO configured as output ports to drive LED 12 bit GPIO configured as output ports to drive the 7 segment LEDs on the board 8 bit GPIO configured a
23. esult should be displayed in decimal on the 7 Seg display and it will also be sent to the hyperterminal through the UART The hyperterminal display should show 3 1 4 Push button to start math operation 3 1 2 Push button to start math operation 3 1 3 Push button to start math operation The next section will show how to load this same program after the FPGA has been configured Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is Configured and the Processor is Running This step will show an example of how a Hardware Application can be initially loaded with a Stub program This will configure the MicroBlaze Microcontroller where it is waiting to be loaded with the actual software application Updating and Generation Hardware Files Select the XPS Software Application tab There are 3 options that can be selected when choosing selecting this tab This example will show how a software application can be loaded after the FPGA is configured A software application can be loaded and run and then a different software application can be loaded and run In this example the MicroBlaze processor must be loaded with a software application through the use of a stub program To select the stub application perform the following steps 1 Select the Application tab the XPS window 2 Right click on Default microblaze 0 xmdstub 3 Set Mark to Initialize BRAMs A small green arrow will appear to the left of
24. ference Designs 17 Downloading the Design and Launching XPS 17 Updating and Generating Hardware Files 18 Downloading Design Files to the FPGA 2 19 Selecting a Software Application to Run When the FPGA is Configured 19 Loading the Project Interrupt_demo Software Application 20 UG133 v1 5 September 12 2005 www xilinx com MicroBlaze Microcontroller Ref Des User Guide Running the Interrupt demo Pros ram sis cine en dresse 21 Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is Configured and the Processor is Running 21 Updating and Generating Hardware Files 21 Loading the microblaze_O_xmdstub Software Application 22 Loading the Interrupt_demo Software Application with XMD_STUB 23 Loading the Simple_Clock Software Application with XMD_STUB 23 Additional MicroBlaze and EDK Information 24 UG133 v1 5 September 12 2005 www xilinx com MicroBlaze Microcontroller Ref Des User Guide XILINX Preface About This Guide Introduction This user guide contains information on how to integrate the stand alone prebuilt MicroBlaze Microcontroller reference design into an FPGA Although thi
25. g to be loaded with the actual software application Updating and Generating Hardware Files In XPS select the software Application tab This example will show how a software application can be loaded after the FPGA is configured A software applications can be loaded and run and then a different software application can be loaded and run In this example the MicroBlaze processor must be loaded with a software application through the use of a stub program To select the stub application perform the following steps 1 Select the Application tab the XPS window 2 Right click on Default microblaze 0 xmdstub 3 Set Mark to Initialize BRAMs A small green arrwo will appear to the left of Default microblaze_0_xmdstub 4 Confirm that Mark to Initialize BRAMSs is not checked for the other projects or default applications The graphic to the left of each other application should appear as a green arrow with a red X over it Verify that this is the case for microblaze_0_bootloop Project Interrupt_demo and Project Simple_Clock If any are set right click and confirm that Mark to Initialize BRAMs is not checked If checked click to deselect it The little green arrow should then appear with a red X MicroBlaze Microcontroller Ref Des User Guide www xilinx com 21 UG133 v1 5 September 12 2005 Chapter 3 MicroBlaze Microcontroller Reference Design Number 2 XILINX 4 Xilinx Platform Studio C mb_mcu_Refdes2 s
26. hen choosing the Software Application This first example will show how a Software Application can be initially added to the FPGA bitstream This will configure the MicroBlaze Microcontroller program and Data memory with the software application already pre loaded This means that as soon as the FPGA has been successfully configured the MicroBlaze Microcontroller software application will already be running on the MicroBlaze Microcontroller Hardware Application In this case although multiple software applications could overlap in the Bram only one software application can be selected at one time To select the desired application perform the following steps 1 Select the Application tab the XPS window 2 Right click on Project Calculator_App 3 Set Mark to Initialize BRAMs A small green arrow appear to the left of the Project Calculator_App text 4 Confirm that Mark to Initialize BRAMSs is not checked for the other projects and default applications The Graphic to the left of each other application should appear as a green arrow with a red X over it Verify that this is the case for microblaze_0_bootloop microblaze_0_xmdstub and Project TestApp If any are set please Right click and confirm that Mark to Initialize BRAMSs is not checked If checked click to deselect it The green arrow should then appear with a red X Ps Xilinx Platform Studio C balinx_projects mb_mc 6 3 mb_mcu_Refdes1_6 3 system x mp C balinx_p
27. inx Inc does not represent that devices shown or products described herein are free from patent infringement or from any other third party right Xilinx Inc assumes no obligation to correct any errors contained herein or to advise any user of this text of any correction if such be made Xilinx Inc will not assume any liability for the accuracy or correctness of any engineering or software support or assistance provided to a user Xilinx products are not intended for use in life support appliances devices or systems Use of a Xilinx product in such applications without the written consent of the appropriate Xilinx officer is prohibited The contents of this manual are owned and copyrighted by Xilinx Copyright 1994 2003 Xilinx Inc All Rights Reserved Except as stated herein none of the material may be copied reproduced distributed republished downloaded displayed posted or transmitted in any form or by any means including but not limited to electronic mechanical photocopying recording or otherwise without the prior written consent of Xilinx Any unauthorized use of any material contained in this manual may violate copyright laws trademark laws the laws of privacy and publicity and communications regulations and statutes UG133 v1 5 September 12 2005 www xilinx com MicroBlaze Microcontroller Ref Des User Guide MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 The following table shows the revisio
28. n history for this document Version Revision 7 22 04 1 0 Initial Xilinx release 8 27 04 1 1 Edited content imported new images 11 19 04 1 2 Reconfigured book added new chapter incorporated edits 11 30 04 1 3 Reformatted book to consist of chapters for Overview and RefDes1 1 7 05 1 3 1 Made minor non technical changes only 7 22 05 1 4 Added Ref Des 2 chapter 9 12 05 1 5 Made minor edits in chapters 2 and 3 UG133 v1 5 September 12 2005 www xilinx com MicroBlaze Microcontroller Ref Des User Guide Preface About This Guide Introduction 4444ee eee eee eee eee 1 Guide Contents eeeeeeeeeeeeeeeeeeeeeeeee 1 Additional Resources 1 2 Conventions a en eo Be EE OG ri be ie 2 iE jolene qt es ee eee ee ee ee ee eee re re ee 2 Online DOCUMENT sesir soe 2084 ua sou BOR EOE s As ideas eau bee Ewe eS 3 Chapter 1 Microcontroller Reference Design Overview Introduction 0 ccc cece nee eee eee eee eee 4 Chapter 2 MicroBlaze Microcontroller Reference Design Number 1 Reference Design Building Blocks 6 APPUI TON 264 cncacceco es So ceeds gue in Suely punts ora yee gas pees T PEPE RET E E 6 ea ha ee ee ere ee UT E 7 CS States oa cay parce sg senee a sere Passa eens ai gs ee eeneceeee eres teeeet 7 Dy stent REUT MENS a 24 9544 oe er ey
29. ocessor 50 MHz on the Spartan 3 Starter Kit Board derived from the 50 MHz crystal on board Instruction cache and data cache options disabled 32 32 bit general purpose registers with 32 bit address and 32 bit data buses Single cycle execution Direct access to the register file using Fast Simplex Link FSL e Unified instruction and data BRAM into single memory for both instruction and data segments Dual port 16 KB internal blockRAM memory structure _2 cycle read access from BRAM via the Local Memory Bus LMB e RS232 UART Controller Pre configured for 57600 baud rate e General purpose input output ports GPIO 8 bit GPIO configured as output ports to drive the LEDs 12 bit GPIO configured as output ports to drive the 7 segment LEDs on the board 8 bit GPIO configured as input ports to read onboard DIP switches 3 bit GPIO configured as input ports to read push buttons e External Memory Controller Supports 1MByte of SRAM memory with two 256x16 SRAM Devices Supports flash and other synchronous and asynchronous external memory e Interrupt Controller Parameterizes OPB Interrupt Controller Programmable Enable or Disable Interrupts Programmable Level and Edge trigger Interrupts e Timer 32 bit Timer module that attaches to the OPB Two programmable interval timers with interrupt event generation Configurable counter width e JTAG_UART core with Xilinx Microprocessor Debugger XMD and GDB de
30. ox as shown in Figure 2 5 Configure the Target Selection dialog box to match Figure 2 5 then click OK In Source Window gt Run click RUN to download the executable elf file located in the TestApp directory into the device 6 In Source Window the user can select Continue Single Step Set Break Point and view source code registers and memory contents 7 From Control Tag select Continue If the Spartan 3 Evaluation Board executes the application test program properly you will see flashing LEDs on the board in the Hyper Terminal 57600bps 8N1 Note Begin from step 2 to configure the device prior to loading a new application program and debugging Make certain to close all XMD and GDB windows Target Selection K Mw Set breakpolnt at rain Target Remote TCP XMD Ww Set breakpoint at exit Hostname lacalhost Set breakpoint at fees 1234 W Display Download Dialog Use xterm as hferior s tty ceca oe Figure 2 5 Target Selection for Software Debugger gt More Options Loading the Calculator_App Software Application with XMD_STUB To download and execute the Calculator_App demonstration program repeat the procedure in section Loading the TestApp Software Application with XMD_STUB Start with step 1 and choose Calculator_App in step 5 instead of TestApp See Running the Calculator_App program Additional MicroBlaze and EDK Information Congratulations you have successfully
31. plication into the FPGA The first method outlines the downloading of the Software Application when it can be incorporated into the FPGA bitstream The second method describes the downloading of a selected application into the FPGA using the GDB debugger for software development and debugging Selecting a Software Application to Run When the FPGA is Configured In this step the Software Application that will be loaded when the FPGA is initially loaded With a new bitstream will be selected Please select the Software Application tab on XPS window The first example will show how a Software Application can be initially added to the FPGA bitstream This will configure the MicroBlaze Microcontroller program and Data memory with the software application already pre loaded This means that as soon as the FPGA has been successfully configured the MicroBlaze Microcontroller Software Application will already be running on the MicroBlaze Microcontroller Hardware Application In this case although multiple software applications could overlap in the BRAM only one software application can be selected at one time To select the desired application perform the following steps 1 Select the Application tab the XPS window 2 Right click on Project Interrupt_demo A small green arrow appear to the left of the Project Interrupt_demo text 3 Set Mark to Initialize BRAMSs A small green arrow will appear to the left of the Project Interrupt_demo text
32. psolvers htm Tech Tips Latest news design tips and patch information for the Xilinx design environment http www support xilinx com xlnx xil_tt_home jsp Conventions This document uses the following conventions An example illustrates each convention Typographical The following typographical conventions are used in this document Convention Meaning or Use Example Messages prompts and Courier font program files that the system speed grade 100 displays Literal h Courier bold ie sarees pe kaa ngdbuild design_name enter in a syntactical statement nai that you select File gt Open Helvetica bold A Keyboard shortcuts Ctrl C MicroBlaze Microcontroller Ref Des User Guide www xilinx com 2 UG133 v1 5 September 12 2005 Conventions 2 XILINX Convention Italic font Square brackets Meaning or Use Variables in a syntax statement for which you must supply values Example ngdbuild design_name References to other manuals See the Development System Reference Guide for more information Emphasis in text An optional entry or parameter However in bus specifications such as bus 7 0 they are required If a wire is drawn so that it overlaps the pin of a symbol the two nets are not connected ngdbuild option name design name Braces A list of items from which you must choose one or more lowpwr on off Vertical bar
33. rocontroller hardware images or modify and customize the features and peripherals This guide is provided as an aid in getting started and learning how to use the Xilinx Embedded Development Kit EDK tools It does this through examples which show how multiple software images can run on a defined soft microcontroller hardware configuration This guide show how an FPGA with a soft processor can be used the same way an engineer would select an off the shelf microcontroller This guide will provide examples of a number of different microcontroller configurations from which an engineer can choose The soft microcontroller features and peripherals in the FPGA may be used without modification or may be modified and customized using the Xilinx EDK Platform Studio tools This guide will cover the flow where multiple software images are loaded on an unmodified hardware configuration MicroBlaze Microcontroller Ref Des User Guide www xilinx com 4 UG133 v1 5 September 12 2005 Chapter 1 Microcontroller Reference Design Overview gt XILINX 5 www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 Reference Design Building Blocks Chapter 2 MicroBlaze Microcontroller Reference Design Number 1 Reference Design Building Blocks Application The block diagram of the MicroBlaze Microcontroller used in this MicroBlaze Microcontroller Reference Design is shown in Figure 2 1 The design includes an Int
34. rojects mb_mc6 3 mb_mcu_Re EEK File Edit View Project Tools Options Window Help D amp Sd SSO xi file calc_main c System Applications opsions Symbols Right Click for Options A Software Projects Default microblaze_0_bootloop ein Default microblaze_O_xmdstub k Project TestApp Processor microblaze_0 Executable C xilinx_projects mb_mce6 3 mt Compiler Options Sources Headers Gh Calculator_App Processor microblaze_0 A Executable C xilinx_projects mb_me6 3 mt Compiler Options Sources a lt gt z Console Log PM_SPEC Xilinx path component is lt C Kilinx6_3 EDK Gmm10 1 gt Project Opened This file contains an application example using the MicroBlaze Microcontroller system design template The application assumes t the Digilent Spartan 3 Starter Board Rev E f or later The applic a simple calculator that uses the slide switches and push buttons board as inputs and the LEDs and UART as outputs lt b gt pplication Details lt b gt The application 1is a simple calculator application that runs on t processor by downlosding it to the Spartan 3 Starter Kit board s application makes use of the opb_gpio opb_uartlite and opb_emc The calculator uses one operator and two operands in the followin e KK KK KK OK K operand operator operand2 Eight slide switches on the board
35. s design is targeted initially for the Xilinx Spartan 3 Starter Kit Board the design may be modified readily for any Xilinx or third party platform This guide is an aid in getting started and learning how to use the Xilinx Embedded Development Kit EDK tools It does this through examples which show how multiple software images can be run on a defined soft Microcontroller hardware configuration This guide show how an FPGA with a soft processor can be used the same way an engineer would select an off the shelf microcontroller This guide will provide examples of a number of different microcontroller configurations from which an engineer can choose The soft microcontroller features and peripherals in the FPGA may be used without modification or may be modified and customized using the Xilinx EDK Platform Studio tools This guide will cover the flow where multiple software images are load on an unmodified hardware configuration The MicroBaze Microcontroller is an integrated solution intended for implementation of an embedded controller in FPGA by a user without extensive knowledge of the Xilinx Embedded Development Kit EDK and the Xilinx Platform Studio XPS The solution offered in this document is a minimal implementation that can be expanded easily to include other peripherals and application software for different usage All the necessary documentation references HDL code sample codes software drivers and application software are inclu
36. s input ports to read onboard dip switches 3 bit GPIO configured as input ports to read push buttons e JTAG_UART core with Xilinx Microprocessor Debugger XMD and GDB debugger to provide application software debugging capabilities XMD uses a JTAG _UART to communicate with xmdstub on the board xmdstub is an executable software loaded into local system memory at startup Supports run time control such as Run Single Step Breakpoint View Registers and View Memory as well as debug parameters Note Interrupts are not used in this design For an example on how to use interrupts see the Microblaze design using an OPB interrupt controller and an OPB microprocessor debug module MDM reference design available on the Embedded Design Kit web site at http www support xilinx com ise embedded edk_examples htm For documentation on interrupts see the MicroBlaze Processor Reference Guide in the EDK documentation Getting Started System Requirements The following software must be installed on your PC to utilize this reference design e Windows 2000 SP2 Windows XP e EDK 6 3 or later Must be the same version as ISE e ISE 6 3i or later MicroBlaze Microcontroller Ref Des User Guide www xilinx com 7 UG133 v1 5 September 12 2005 Downloading the Design and Launching XPS XILINX To download the completed reference design the following hardware is required Xilinx Spartan 3 Evaluation Board For information on the evaluation bo
37. the Default microblaze_0_xmdstub text 4 Confirm that Mark to Initialize BRAMSs is not checked for the other projects and default applications The graphic to the left of each other application should appear as a green arrow with a red X over it Verify that this is the case for microblaze_0_bootloop Project TestApp and Project Calculator_App If any are set right click and confirm that Mark to Initialize BRAMSs is not checked If checked click to deselect it The green arrow should then appear with a red X MicroBlaze Microcontroller Ref Des User Guide www xilinx com 12 UG133 v1 5 September 12 2005 Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is XILINX Ps Xilinx Platform Studio C balinx_projects mb_mc 3 mb_mcu_Refdes1_6 3 system mp C oalinx_projects mb_mc 3 mb_mcu_Re Sel File Edit View Project Tools Options Window Help D a amp et Om the ZE A Fo ME Sca aam Copyright c 2004 Xilinx Inc All rights reserved System Applications Joptons Symbols Right Click for Options E Software Projects Default microblaze_0_bootloop mM Default microblaze_O_xmdstub Project TestApp Processor microblaze_0 Xilinx In COURTESY TO YOU BY PROVIDING THIS DESIGN CODE OR INFORMATION ONE POSSIBLE IMPLEMENTATION OF THIS FEATURE APPLICATION OR STANDARD XILINX IS MAKING NO REPRESENTATION TH
38. ub Software Application To configure the hardware system and to load the software application into the Spartan 3 Evaluation Board using the Digilent JTAG3 cable perform the following steps 1 Connect the Digilent JTAG3 cable to the J7 header on the Spartan 3 Evaluation Board and connect the other end to the parallel port of the PC If using the parallel cable IV make sure that the status light is lit on the cable 2 Connect the serial cable to J2 on the Spartan 3 Evaluation Board and to the serial port of the PC On the PC using HyperTerminal make certain that the bit rate is set for 57600 bps on the serial port 3 Turn on the power to the Spartan 3 Evaluation Board 4 In XPS to make sure that the ELF file is up to date use Tools gt Update Bitstream Note Close all other XMD and GDB windows prior to downloading a configuration bits 5 In XPS select Tools gt Download to download the hardware configuration and to load xmdstub into the BRAM memory Note Close all other XMD and GDB windows prior to downloading a configuration bits 6 In XPS select Tools gt XMD to open an XMD utility XMD is a JTAG utility that can be used to download and debug software XMD is also a server for GDB the GNU debugging utility 22 www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 7 XILINX Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is Loading the Interrupt
39. up to date use Tools gt Update Bitstream There may be a warning Processor microblaze_0 has XMDSTUB mode application but xmdstub elf is not marked for download do you want to continue Click on YES In XPS select Tools gt Download to download the new bitstream into the FPGA The xmd stub warning will appear again Click on YES Note Close all other XMD and GDB windows prior to downloading a configuration bits Running the Interrupt_demo Program After the Interrupt_demo has been loaded The 8 bit LEDs on the board begins to toggle back and forth while the Seven Segment Display starts to increment The main c under Interrupt_demo src contains the main source for this application 20 www xilinx com MicroBlaze Microcontroller Ref Des User Guide UG133 v1 5 September 12 2005 gt XILINX Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is This program uses the timer and GPIO to demonstrate interrupt handling of the MicroBlaze Microcontroller The timer is set to interrupt regularly and everytime there is an interrupt with the timer the seven segment display counts up and the LED pattern changes Selecting a Software Application to be Loaded with a BOOT Loader after the FPGA is Configured and the Processor is Running This step will show an example of how a hardware application can be initially loaded with a stub program This will configure the MicroBlaze Microcontroller while it is waitin
40. ystem xmp C mb_mcu_Refdes2 I 4 File Edit View Project Tools Options Window Help i ajjaj ae Y ILE SONICIAI El A m l ETT Ma eE E aa sn vera AE oe x LE zizi Syster Applications o File Name main c Ue pa Version 1 0 Cas pa Date 1071972003 Piat Click tor ptione o 3 Model Example For Interrupt Controller CA Software Projects a ne boues iii Aa Detault microblaze_O_bootloop OF x pene erin Pefault microblaze_O_xmdstub D Disclaimer THESE DESIGNS ARE PROVIDED AS IS ho tr dono ere Aa DE goede dat Processor microblaze_0 gt p 11 Executable Cmb_meu_Refdes2nterrupt_de 12 s A PABTICULAK PURPOSE UR ASALET Compiler Options 1300 Copyright fc 2001 Xilinx Inc Sources 1H RE All rights reserved El C smb mecu RefdesAlnterupt demo src 15 KE EREREEEEREREREREEREEEREREREREEREREEEREREERETX E C wob_mcu_Refdesnterrupt_demo sarc Fl imh mean Bates latereont dermas ere t C SEDKSd C mb_meu aj C mb_ mou Ad C mb_meu xl mode executable Calculator_App srcecalc_main c In function main Calculator_Appe srecalc_main c 166 error HPAR_LED SEGMENT_BASEADDR undeclared first use i 166 iF dan ee eee ae ee S l le Ca led atar Ann rame fi mel Men ne de nn ach 11 r 1 rarnar Cas TT Cher Warning A Error Ready Figure 3 4 Software Selection with a BOOT loader Loading the microblaze_0O_xmdst
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