DSP56007EVM User's Guide
Contents
1. 3 6 debug mode 3 5 Digital Audio Interface Receiver 4 5 Digital Audio Interface Transmitter 4 6 Digital power 3 6 Digital Power Down Input DPD 3 1 digital to analog conversion 4 3 Digital to Analog Converter 7 9 Dolby ProLogic 3 5 M MOTOROLA Index DSP56000 Family Manual 2 1 DSP56007 Langka are 7 3 DSP56007 Data Sheet 2 1 DSP56007 memory 3 7 DSP56007 User s Manual 2 1 E electrically erasable PROM EEPROM situate best 4 7 EMI bootstrap 3 7 EMI susceptibility 4 8 EPM7032 sn 5 1 Expansion Connector AE RR al E av 3 2 3 4 7 7 External Interrupt Requests 3 8 F fast static RAM 4 7 fast Static RAM SRAM 3 7 Frame Sync FSYNC 3 3 frequency multiplication factors 3 8 G Graphical User Interface GUI 6 1 GUI Windows 6 2 l FO ade DM E Ne haken 3 1 PS slave mode 3 2 TORK ER dise ls 3 1 TER PD 322 2424422 A AGANG 3 1 J Jumper Pau seen or RE 3 1 K Keypad usa 4 12 Keypad Expansion Port J18 3 3 L LED asset erte 7 4 56007EVM User s Guide LED panel 3 3 4 9 M Master Clock MCLK 3 3 master mode 3 1 MC68705K1 3 5 MC68HC711E9 3 3 Memory aki Sei dr 3 7 7 7 Mi2. EXP2 SCKT 74393 15 Q1B EXP2 SCKT TRI _LC002 GLOBAL TXMASTER SEL LC002 TFFE ADA CIk 2 FQ008 VCC VCC VCC _EO008 _X003 amp _X004 EXP2 WSR LC003 3 EXP2 WSR LCELL EXP2 WSR GND EXP2 WST 74393 15 Q2D EXP2 WST TRI LCO17 GLOBAL TXMASTER SEL LCO17 TFFE EQ009 LCO15 VCC VCC VCC _EO009 LC004 amp LCO14 amp _LCO24 3 NVRAM G IC001 3 NVRAM G LCELL EQ010 GND E0010 DSP RST amp EMI MRD DSP RST amp MODC SEL 5390 CIK _LC023 5390 CLK LCELL F0011 GND E0011 FS SENS amp LCO26 amp RCVMASTER SEL IFS SENS amp LC025 amp RCVMASTER SEL RCVMASTER SEL amp 8412 MCK clockpr4 111 26 _LCO26 TFFE VCC 12MHZ CLK VEE VCC MEE clockpr4 111 28 _LCO25 TFFE VCC 11MH7 CLK VEG VCC VCC 74393 15 01C 74393 15 5 LC007 TFFE EQ012 EQ0O13 VCC VCC VCC EQ012 ADA CIk 2 amp LC002 _EQ013 _X003 amp Xx004 74393 15 01D 74393 15 9 LC015 TFFE EQ014 EQ015 VCC VCC VCC _EQ014 ADA CIk 2 amp LCO002 amp LCO007 _EQ015 _X003 amp _X004 74393 15 02A 74393 15 28 LC004 TFFE VCC LCO15 VCC VCC VCC M MOTOROLA 56007EVM User s Guide 5 3 EPM7032 PLD Equations 6 74393 15 Q2B 74393 15 29 3 LCO14 TFFE LC004 LCO15 VCC VCC VCC 6 74393 15 Q2C 74393 15 30 5 LC024 TFFE EQ016 LCO15 VCC VCC VCC _FQ016 LC004 amp
3. 11 520 MHz 22 272 MHz 33 024 MHz 43 776 MHz 54 528 MHz 65 280 MHz 3 8 56007EVM User s Guide M MOTOROLA Evaluation Module Theory of Operation External Interrupt Requests 3 11 EXTERNAL INTERRUPT REQUESTS J19 allows the user to externally initiate the External Interrupt Request A IRQA the External Interrupt Request B IRQB and or the Non Maskable Interrupt Request NMI These pins are pulled high by 10k resistors to assure that false interrupts are not generated by floating inputs A mororoLa 56007EVM Users Guide 39 Evaluation Module Theory of Operation External Interrupt Requests 3 10 56007EVM User s Guide M MOTOROLA SECTION 4 PERIPHERAL SPECIFICATIONS The following section describes the various peripheral devices used on the DSP56007EVM and includes any necessary equations and information Contact information for the manufacturers of significant peripheral devices is included along with the parts listing in Section 8 A mororoLa 56007EVM Users Guide 44 Peripheral Specifications CS5390 Stereo ADC 4 1 CS5390 STEREO ADC The CS5390 is a complete analog to digital converter ADC for stereo digital audio systems It performs sampling analog to digital conversion and anti alias filtering generating 20 bit values for both left and right inputs in serial form The output word rate can be up to 50 kHz per channel The CS5390 uses fifth order delta sigma modulation with 64 times oversam
4. EQ001 Xx001 A mororoLa 56007EVM Users Guide 51 EPM7032 PLD Equations KOOL EXP DSO amp _X002 _X002 EXP ACK_RST amp _X001 ADA CLK _LC006 ADA CLK LCELL _EQ002 GND EQ002 FS SENS amp _LCO26 IFS SENS amp _LCO25 S ADA CIk 2 _LC019 ADA Clk 2 74393 15 QIA ADA Clk 2 TFFE VCC EQ003 VCC VCC VCC _EO003 _X003 amp _X004 X003 EXP FS SENS amp _LC025 X004 EXP FS SENS amp LC026 DSP CLK LC020 DSP CLK 74393m 82 QD 3 DSP CLK TFFE EQ004 LC026 VCC VCC VCC _EO004 LCOO9 amp LCO013 amp LCO27 2 DSP MODA _LC010 3 DSP MODA LCELL E0005 GND E0005 DSP RST amp IROA DSP RST amp MODA SEL oe DSP MODB _LCO11 DSP MODB LCELL E0006 GND _EO006 DSP RST amp IROB DSP RST amp MODB SEL DSP MODC LCO12 DSP MODC LCELL E0007 GND EQ007 DSP RST amp IROC IDSP RST amp MODC SEL EXP2 GPIO2 _LC016 EXP2 GPIO2 TRI _LC016 GLOBAL DSP RST _LC016 LCELL GND GND EXP2 GPIO3 _LC021 EXP2 GPIO3 TRI _LC021 GLOBAL DSP RST _LCO21 LCELL GND GND 5 2 56007EVM User s Guide M MOTOROLA EPM7032 PLD Equations
5. Parts Listing Table 8 1 DSP56007EVM Parts List Continued Part Designator Manufacturer Part Number Description D6 Future HLMP 1790 Green LED 2mA 1 8V D5 Future HLMP1700 Red LED 2mA 1 8V U22 Sharp GP1U56Y Infrared receiver L1 Future BLO1RN1 A62 Ferrite on PC board for U14 TO 220 0 5 compact heat sink a Crystal Semiconductor Corporation P O Box 17847 Austin TX 78760 512 445 7222 Fax b Scientific Conversion Inc 42 Truman Drive Novato CA 94947 415 892 2323 Fax 415 c Simtek Corporation 1465 Kelly Johnson Blvd Colorado Springs CO 80920 800 637 1667 9481 M moroRoLA 56007EVM User s Guide 8 5 Evaluation Module Parts List Parts Listing 56007EVM User s Guide M MOTOROLA Numerics 11 2896 MHz clock 3 3 12 288 MHz clock 3 3 12 288 MHZ crystal 3 8 A NER LS mana rt 3 5 AND Een nn ET 3 1 4 2 AES EBU Transformer 4 8 analog to digital conversion 4 2 Analog to Digital Converter 7 8 anti alias filtering 4 2 attenuator trim functions 4 9 Audio Power Down Input APD 3 1 B Bipolar analog power 3 6 Bootstrap Configuration 3 4 C Chip Select Latch CS 3 3 Clock Select 3 2 Control Mute 3 4 EI rede pen nr ne 4 4 EN MDA ete 4 3 255990 ORE RE mia that 4 2 CSP ek bakar dl ee 4 6 LI a dn r DERE 4 5 D DB9 connector
6. thereby connecting JP1 1 to JP1 2 and JP1 3 to JP1 4 The user should never need to rewire an RS 232 connector in order to establish Evaluation Module communications with a host computer 3 6 OPERATING MODES AND SRAM REFRESH IN THE 56007 In modes 0 1 2 and 3 the SRAM is refreshed from the nvRAM and the DSP can bootstrap from the SRAM via the EMI if a valid bootstrap mode is used When in modes 4 5 6 and 7 the SRAM is not refreshed Refreshes are not affected by jumpers on the expansion connector J5 Jumpers J5 37 and J5 39 must be inserted to have full DSP control of the SRAM and nvRAM after bootstrap 3 7 EVALUATION MODULE PARTS LIST The parts list of the DSP56007EVM is shown in Section 8 3 8 POWER SUPPLIES The Evaluation Module requires power sources for both analog and digital circuits in order to operate Bipolar analog power use a linear power supply for best results 3 6 56007EVM User s Guide M MOTOROLA Evaluation Module Theory of Operation Memory is received through screw terminals at J3 Digital power is received through screw terminals at J2 or via a 2 1mm connector J1 When the power is on D6 green LED is illuminated Analog power input may be 8 to 12 volts and digital power input may be 8 to 15 volts While the voltage regulator can accommodate higher input voltage potentials the added heat dissipation required at these input voltage levels will result in the regulator becoming dangerously warm and it is n
7. 4 F3 3 Gnd Gnd Gnd Gnd 5V n EG r6 FEF J u V LT IR Rev U22 IR Rev _ Infared Receiver P KI Cntl Mute 7 G4 2 B4 8 B5 Cntl_Mute 1 Y1 C ACK RST KS 11 2896 MHz 4 F4 Master Oscillator Select ACK 4 F4 o JP2 P Clock Select Y2 C 1 Fs sens 12 288 MHz 5 D2 8 B5 Oscillator V Jumper 11 2896 MHz No Jumper 12 288 MHz Figure 7 3 Programmable Logic Device NVRAM G 5 D6 ADA Cik 7 A2 ADA Cik 2 8 C3 DSP_Ck 768kHz 1 H3 EXP2 7 A3 5 E4 2 F4 8 G2 6 G3 8 B4 EMI 5 A4 1 F5 8412_MCK 8 G1 5390 Cik 6 G2 DSO 1 14 4 F4 Rx Jumper Clocked by crystal No Jumper Cl ocked by Revd SPDIF 6 F4 Tx 66 Rx Tx Jumper C locked by crystal No Jumper Cl ocked by DSP 9PIN9 SjA9SN INA3Z009S J4 OnCE Host C5 1 pF O gt ol JP1 Serial Config D7 1N5827 C4 5V 1 uF C22 1 uF E HI MAX232 tur C1 c2 P RS 232 Transceiver T1in HC11 Cik DD 2 D2 MC68705K1 U24 Figure 7 4 RS 232 and OnCE Port Interface C3 47 pF 5V R16 1500 N D5 Debug LED Red DSP RST 1 E3 3 B4 2 G3 DR 1 13 ACK_RST 3 D5 DSO 1 14 3 F4 ACK 3 D5 DSCK OS1 1 14 DSI OSO 1 14 9PIN9 SjA9SN INA3Z009S DRov Bik DRcv CS 8 G3 8 G3 DTrn Blk S ee y 8 B5 B PERS JP7 NAD Select Fs sens L gt 6o 5 3 D6 8 B5 46 03 2 1 30 Pin SIMM Socket sy S J5 NSN Expansion V Connector R19 R45 MD MDE 10K 10K MD5
8. MD4 MD3 EE D MO i a mrumm VET SDO2 E La i LL EM DD f NSR 3 F3 1 F5 CJ Expi ar 1 14 7 A3 3 F3 2 F4 8 G2 6 G3 8 B4 CJ HC11 GPIO 2 B4 SRAM nvRAM Figure 7 5 Memory and Expansion Connector 9PIN9 SjA9SN INA3Z009S Left Analog Input J6 AGND J7 AGND Right Anal og Input R22 20K b R21 20 K U19 AGND R28 20K P R27 20 K U20 AGND CJ 5390 Cik Ree C63 5V 3 F4 10K 0 01 UF e ICLKA VL VA U7 CS5390 C ExP2 A D Converter 7 A3 3 F3 5 E4 2 F4 8 G2 8 B4 AGND AGND Cntl Mute 3 D5 Figure 7 6 Analog to Digital Converter 9PIN9 SjA9SN INA3Z009S AVcc Base us R50 CS4331 C45 D A Converter 0 1 uF VA HSS AGND 600 SDATAI AOUTL DEM SCLK R40 600 U12 2 ROUTE CS3310 LRCK Dig Vol Cntrl R53 56 K 56K er C16 0027 uF 0027 UF ADA Cik 3 F2 AGND AGNDL AGNDR VA DGND C46 EI 0 1 uP T CS4331 D A Converter AGND R41 600 R42 600 CS3310 Dig Vol Cntrl EXP2 LD R56 3 F3 5 E4 2 F4 8 F1 Bu 56K 6 G3 8 A4 C17 C18 0027 pF 0027 uF V AGND C C44 CS4331 D A Converter 0 1 pF VA MCLK C28 R37 AGND 3 3 uF 600 SDATAI AOUTLF DEMSCLK C66 deg U11 3 3 uF 600 teg Dig vol Gn li o ntri LRCK ae g n 56K pis C14 SDATAO 56 K 0027 uF 0027 UF SDATAI AGND Cnil Data p 2 B3 AGND AGNDL AGNDR VA Cn ck LO 2 B4 Cntl Latch 2 B4 AGND o AVss J12 Left Output 3 J
9. R6 R8 Future CR32 1002F T 10KQ 1 4W resistor R21 R27 20kQ 1 4W resistors R51 R52 R53 R54 R55 R56 56KQ 1 4W resistors M MOTOROLA 56007EVM User s Guide Evaluation Module Parts List Parts Listing Table 8 1 DSP56007EVM Parts List Continued Part Designator Manufacturer Part Number Description R20 R22 R28 Digikey D4AA24 ND 20KQ 1 4W trimpot thru hole Y1 MMD MB100HA 11 2896MHz 11 2896MHz Clock Oscilla tor Y2 MMD MB100HA 12 288MHz 12 288MHz Clock Oscillator Y3 Ecliptek EC2 040 4 000MHz 4 0MHz Crystal JP2 JP6 JP8 2 pin single row header J19 4 pin single row header JP1 JP5 4 pin double row header JP3 JP4 JP7 6 pin double row header J18 10 pin double row header on PC board for U16 14 pin single row female header on PC board for U16 14 pin single row male header J5 50 pin double row male header on PC board for U15 SIMM socket J17 Sharp GP1F32R Optical Connector Receive J16 Sharp GP1F32T Optical Connector Transmit Ji Mouser 16PJ031 2 1mm DIN power connec tor J4 Mouser 152 3409 PC mount DB9 female con nector J7 JI J11 J13 JE J8 Mouser 161 4215 RCA Jack J10 J13 J14 J15 on PC board for U2 McKensie PLCC 52P T 52 pin PLCC socket J2 2 position terminal block J3 3 position terminal block S1 S2 SI 54 55 6mm pushbutton switch 56007EVM User s Guide M MOTOROLA Evaluation Module Parts List
10. X jumper installed no jumper 3 3 BOOTSTRAP CONFIGURATION USING JP9 In the SHI bootstrap mode JP9 can be configured to bootstrap the DSP by setting the jumpers according toTable 3 4 The first code set contains the pass through code included on the 56007E VM software disk The second code set currently contains shell 3a B6007EVM User s Guide OE Evaluation Module Theory of Operation OnCETM Port code to be replaced by Dolby ProLogic code in a future software release JP9 s pinout is shown in Figure 3 1 Table 3 4 JP9 Configuration JP3 1 to JP3 4 Do not send bootstrap code from HC11 to DSP JP3 4 to JP3 1 JP3 2 to JP3 5 Send bootstrap code from Send 1st code set in higher HC11 to DSP memory JP3 3 to JP3 6 Send peripheral changes as if running ProLogic THX out of ROM JP3 5 to JP3 1 Send 2nd code set in higher memory JP3 6 to JP3 1 Do not send peripheral changes Figure 3 1 JP9 Pinout 34 ONCE PORT The OnCE port interface operates by receiving the serial data from the RS 232 Transceiver and executing commands sent by the host computer These commands can reset the DSP put the DSP in debug mode release the DSP from debug mode read and write to the OnCE port and read and write to the DSP itself The serial bit rate is 19 200 bits second The RS 232 serial communications are performed in software on the MC68705K1 Port A of the MC68705K1 communicates
11. gives a brief summary of the equipment required to use the Evaluation Module some of which is supplied with the Evaluation Module and some of which will have to be supplied by the user 2 1 WHAT YOU GET WITH THE EVALUATION MODULE e Evaluation Module board See Figure 2 1 e 3 5 disk titled Debug Evaluation Module e 3 5 disk titled Evaluation Module Software Debug Evaluation Module manual e DSP56000 Family Manual e DSP56007 User s Manual e DSP56007 Data Sheet e DSP56007EVM User s Guide this document including Evaluation Module Schematics e Additional relevant documentation may be included in the form of a READ ME file on the Evaluation Module Software disk M mororoLa 56007EVM Users Guide 241 Equipment What you need to supply Analog Inputs Analog Outputs g Inp 7 Left3 Rights Left2 Right Left Righi Rightin LeftIn CS3310 CS4331 CS3310 CS4331 CS3310 CS4331 CS5390 Optical n CS8412 J
12. o o NG O Delay Time 20ns E Nxt Ex Selecting THX sets 9 o o ty decoding mode to Ov 20 o Dolby 4 channel 1 plus THX enhancements Center Mode Phn Nrm Wid Nxt o o o 1 Subwoofer is Off Off On Nxt Ex o o f o RSur Trim 0dB Trim Section in the Set menu Rgt Trim OdB Cntr Trim 0dB Lft Trim 0dB Nt Ex Nxt Ex Net Ex Net Ex o O ligg o o D o o Du o o e o LSur Trim OdB Sub Trim 0dB E Eo kl RE Net Ex o o e o o o f o Re equalization Dolby 4 channel mode and THX mode must be active Re EQ is Off Re EQ is On Re EQ is IS02969 ISO Flat Acad Ex Off On Nxt Ex Off On Nxt Ex o T o o o o O Delay Time 20ms o o o e Re EQ is Off Nxt Ex Off On Nxt Ex o o o o o o e Ly Figure 4 9 LCD Softswitch Screens 4 9 M MOTOROLA 56007EVM User s Guide Peripheral Specifications Wiring for Keypad Keypad 1121314 5 N6 11718 9 1101 11 12 13 1141151116 1 DNE 9 ee 2 gt Bypass Test Tone Off SEE AE en 10 Increment Test Tone Level do L 11 Increment Delay Time 4 gt Prologic
13. of 3 75V 16 PINE AOUTL MUTE ZCEN AGNDL 15 Control CS Register 3 Serial to SDATAI 7 Parallel BEd SDATAO Register M SCLK AOUTR VA VA VD DGND Figure 4 3 CS3310 Stereo Digital Volume Control CS so SN L1 nann E SDATAI NN R7 Re R5 RA R3 R2 R1 no L7 te 15 14 13 12 1 Lo y SDATAO x R6 Rs R4 R3 R2 R1 Ro 17 re is a L v2 i vo 7 LO Left Channel Least Significant Bit RO Right Channel Least Significant Bit L7 lt Left Channel Most Significant Bit R7 Right Channel Most Significant Bit SDATA is latched internally on the rising edge of SCLK SDATAO transitions after the falling edge of SCLK SDATAO bits reflect the data previously loaded into the CS3310 Figure 4 4 Serial Port Timing for the CS3310 4 4 56007EVM User s Guide M mororoLa Peripheral Specifications CS8412 Digital Audio Interface Receiver 4 4 CS8412 DIGITAL AUDIO INTERFACE RECEIVER The CS8412 is a monolithic CMOS device that receives and decodes audio data according to the AES 3 1992 EBU Tech 3250 E IEC 958 SPDIF and EIAJ CP 340 interface standards The CS8412 receives data from a transmission line recovers the clock and synchronization signals and d
14. rem 4 7 STORE GE coss siam sa bed 4 7 T TEEN REES s de ind os r ad 4 9 transmit SAI bus 3 2 W wait states 3 7 56007EVM User s Guide Motorola reserves the right to make changes without further notice to any products herein Motorola makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Motorola assume any liability arising out of the application or use of any product or circuit and specifically dis claims any and all liability including without limitation consequential or incidental damages Typical parameters can and do vary in different applications All operating parameters including Typicals must be validated for each customer application by customer s technical experts Motorola does not convey any license under its patent rights nor the rights of others Motorola products are not designed intended or authorized for use as compo nents in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the Motorola product could create a situation where per sonal injury or death may occur Should Buyer purchase or use Motorola products for any such unintended or unauthorized application Buyer shall indemnify and hold Motorola and its officers employees subsidiaries af filiates and distributors harmless against all
15. transmitting the signal with fast rise time and minimum aberration The SC937 02 is a surface mount low capacitance wide band AES EBU transformer The SC937 02 has a very low capacitance shielded winding that reduces both radiated and received noise coupling and provides decreased jitter and improved audio quality especially in noisy environments EMI compliance and EMI susceptibility are improved by the use of this type of transformer The transformer s ratio is 1 1 primary inductance is 600uH inter winding capacitance is 1 1pF bandwidth is 16kHz to 100MHz and rise time is 3ns Input o Output Rin OR Are Input Rtn o 4 Output Figure 4 8 SC937 02 AES EBU Transformer 48 LCD PANEL Figure 4 9 illustrates the different screens of the LCD panel and the corresponding actions of the soft switches Note that ProLogic and THX functionality is not available on the generic DSP56007EVM The attenuator trim functions shown in the trim section in Figure 4 9 are fully functional on the generic 56007EVM Figure 4 10illustrates the different screens of the LCD with respect to the 4x 4 keypad matrix 48 BSOOTEVMUSers Guide OE Peripheral Specifications LCD Panel Byp PL THX Set Byp PL THX Set Byp PL THX Set Byp PL THX Set I o o o o I o o o o i o o o o J Mode is Bypass Dolby 4 Ch Mode Mode is THX Mstr Vol OdB Byp PL THX Set 3Ch 4h Ext Byp PL THX Set Net Ex o o o o o o o o
16. with the DSP and port B communicates with the host computer The acknowledge signal from the OnCE port is a low going pulse on DSO Since the 68705K1 is too slow to reliably catch this very narrow pulse the pulse is latched in the PLD and the output of the latch appears on the ACK pin PA2 When this occurs the 68705K1 illuminates red LED D5 to indicate that the DSP is in the debug mode For more information on the OnCE port see the DSP56000 Family Manual The reset switch will reset the microcontroller A mororoLa 56007EVM Users Guide dd 35 Evaluation Module Theory of Operation RS 232 Connections and JP1 which will subsequently reset the DSP56007 The MC68705K1 source and object code are available from the Motorola DSP Division contact your local Motorola FAE 3 5 RS 232 CONNECTIONS AND JP1 RS 232 is an often abused standard and the direction of the signals present on pins 2 and 3 of the DB9 connectordo not always conform to the standard JP1 provides the user with the ability to reverse these two pin connections without resorting to NULL Modem adapters or rewiring cable connectors As shipped JP1 1 is connected via shorting jumpers to JP1 3 and JP1 2 is connected to JP1 4 This connects J4 2 to the OUTPUT of the Evaluation Module s RS 232 level converter U4 and J4 3 to the INPUT of the board s RS 232 receiver These directions can be reversed by reorienting the shorting jumpers and turning them 90 degrees one quarter turn
17. 1 024K A mororoLa s56007eVMUsersGude 3 7 Evaluation Module Theory of Operation Digital Signal Processor Operating Frequency Table 3 5 DSP56007 Internal Memory Configurations Continued 3 10 DIGITAL SIGNAL PROCESSOR OPERATING FREQUENCY The DSP56007 is clocked at 768 kHz by a 12 288 MHz crystal divided by 16 The DSP56007 PLL is then used to multiply this frequency up to the desired operating frequency Table 3 6 shows the frequency multiplication factors and the resulting DSP clock rates Table 3 6 Frequency Products 1 536 MHz 12 288 MHz 23 040 MHz 33 792 MHz 44 544 MHz 55 296 MHz 2 304 MHz 13 056 MHz 23 808 MHz 34 560 MHz 45 312 MHz 56 064 MHz 3 072 MHz 13 824 MHz 24 576 MHz 35 328 MHz 46 080 MHz 56 832 MHz 3 840 MHz 14 592 MHz 25 344 MHz 36 096 MHz 46 848 MHz 57 600 MHz 4 608 MHz 15 360 MHz 26 112 MHz 36 864 MHz 47 616 MHz 58 368 MHz 5 376 MHz 16 128 MHz 26 880 MHz 37 632 MHz 48 384 MHz 59 136 MHz 6 144 MHz 16 896 MHz 27 648 MHz 38 400 MHz 49 152 MHz 59 904 MHz 6 912 MHz 17 664 MHz 28 416 MHz 39 168 MHz 49 920 MHz 60 672 MHz 7 680 MHz 18 432 MHz 29 184 MHz 39 936 MHz 50 688 MHz 61 440 MHz 8 448 MHz 19 200 MHz 29 952 MHz 40 704 MHz 51 456 MHz 62 208 MHz 9 216 MHz 19 968 MHz 30 720 MHz 41 472 MHz 52 224 MHz 62 976 MHz 9 984 MHz 20 736 MHz 31 488 MHz 42 240 MHz 52 992 MHz 63 744 MHz 10 752 MHz 21 504 MHz 32 256 MHz 43 008 MHz 53 760 MHz 64 512 MHz
18. 13 Right Output 3 J10 Left Output 2 1 J11 Right Output 2 AGND C Cnil Mute 2 B4 3 D4 8 B5 1 J8 Left Output 1 1 1 J9 Right Output 1 b V AGND Figure 7 7 Digital to Analog Converter 9PIN9 SjA9SN INA3Z009S OL Z 7 8 C26 L4 0 1 UE SC937 02 C65 J14 CP340 In 1 CS12 FCK U23 ERF CS8412 Gere AES EBU Receiver CD F1 J17 Optical In CC FO CB E2 NM Receiver CA E1 8412_MCK 19 3 F4 C Exp2 7 A3 3 F3 5 E4 2 F4 6 G3 8 A4 Mode 3 5 F1 CO EO FILT B os AGND DGND DRev Blk C27 5 D1 0 047 uF R46 1K AGND 128Fs ADA CIk 2 AGND J15 C67 R43 L3 CP340 Out 0 1 uF 374 SC937 02 TXN EXP2 LY F3 5 E4 2 F4 3 A3 F1 6 G 3 6 M2 DTm CS 5 F2 Mi MO DTrn Bik 5 D2 Fs sens FRO 3 D6 5 D2 EMo C9 ransmitter Cntl Mute REN 7 G4 2 B4 3 D4 EM1 C8 1 TRNPT FC1 T J16 Optical Out Figure 7 8 SPDIF VO 9PIN9 SjA9SN INA3Z009S HEL Digit al decoupling Caps al I 0 1 uF unless ot herwise noted J2 Power Input U14 Terminal Block MC7805 5V Di Voltage Regulator L1 UNBB2T Ferrite C29 C30C31 C32 C33 C34 C35 C36 C37 C38 C39 C40 C41C42C43 C47 C48 Ji 5 20 V AC DC B 1N5827 Power Input D4 D3 1N5827 1N5827 U17 MC7805 Voltage Regulator AVec C49 C51C52 C53 C54 C56 C58 C60 C61 C62 C69 C70 C71 VIN VOU GND JP6 J3 Analog Power Connector VIN VOU U18 C50 C55 C57 C59 MC7905 T Voltage Regulator Gro
19. 3 D4 8 B5 HC11 GPIO LY 5 F5 14 PC7 1 lU ng A PC7 A7 D7 PC6 A6 D6 PC5 A5 D5 PC4 A4 D4 PC3 A3 D3 PC2 A2 D2 PC1 A1 D1 PCO A0 DO A D PB7 A15 PB6 A14 PB5 A13 PB4 A12 39 ES 40 PB3 A11 NE PB2 A10 LI PB1 A9 PB0 A8 STRB R W 51 5v VRL gt 24 MODB VSTBY 3 MODA LIR W R8 10 K U2 MC68HC711E9 Microcontroller TON RIO R11 R12 R13 10K 210K 10K 10K 4 MHz Clock C HC11_Clk 4 F2 S4 STRA AS PAO IC3 PA1 IC2 PA2 IC1 Aa GP AE 4 OC4 OC1 PAS OCS OC PA6 OC2 OC1 PA7 PAI OC1 XIRQ RESET IRQ PD5 SS PD4 SCK D3 MOSI D2 MISO PD1 TxD PDO RxD PE7 AN7 PE3 AN3 PE2 AN2 PES ANS PEO AN4 1 2 3 JP9 PE1 AN1 97 PE4 AN4 J18 Keypad expansion 5V a b lt DSP RST e 1 E3 3 B4 R310K p 4 F3 7 PD EN 23 0 CSN 22 D MSON 21 20 C EXP2 50 7 A3 3 F3 5 E4 8 G2 6 G3 8 B4 PE6 AN6 O o JP8 1 2 pin male header IR_Rev 3 B4 Configuration Jumpers Figure 7 2 Microcontroller and LCD 9PIN9 SjA9SN INA3Z009S 5V Q R14 R9 R15 R5 R4 R2 10 Ko 10 Ko 10 Ko 10 KQ 10 Ka 10 Ko xe L 1L 1D J19 O2 Here e Interrupts ol 5V 2 1 5 L JP3 Eb 1 1 VccVcc Voc Vcc 42 Mode Select 33 32 xS 15 GPIO2 33 WGI ug 0 EEE GY TEJ EPM7032 PA DSP MODB D GPO 1 E4 PLD E MRD psP_Mopc CI 1 E4 bal DSP RST 2 27 1 E3 2 G3
20. 7 4 Figure 7 3 Programmable Logic Device 7 5 Figure 7 4 RS 232 and OnCE Port Interface 7 6 Figure 7 5 Memory and Expansion Connector 7 7 Figure 7 6 Analog to Digital Converter 7 8 Figure 7 7 Digital to Analog Converter 7 9 Figure 7 8 SPDIE VO RE oos ede hangs 7 10 Figure 7 9 Power Supply nee inini tenien a Gee AEE 7 11 List of Tables Digital Audio Input Selection 3 2 ins eben SEWER dt hae es Rema VG 3 2 Digital Audio Receive Transmit Jumper Configuration 3 2 Mode Select Jumpers she dat ei eR Se he Are ed dd Add 3 4 JEG CONMGUIAUION i tube VER EE lor c dlrs Be Dore 3 5 DSP56007 Internal Memory Configurations 3 7 Frequency Pfoduels ismi eli EE DEE EE ES DE ed Vasa li 3 8 M moroRoLA 56007EVM User s Guide iv V 56007EVM User s Guide M MOTOROLA SECTION 1 INTRODUCTION This document describes the basic structure theory and operation of the DSP56007EVM Evaluation Module Evaluation Module the equipment required to use the Evaluation Module and the specifications of the key components on the Evaluation Module Code samples and self test code are provided on the accompanying software diskette Evaluation Module schematic diagrams and a parts list are included as well 1 1 EVALUATION MODULE DESCRIPTION AND FEATURES The DSP56007EVM is a low cost platform for multichann
21. DSP56007EVM 24 BIT DIGITAL SIGNAL PROCESSOR EVALUATION MODULE USER S GUIDE den Motorola Inc Semiconductor Products Sector DSP Division 6501 William Cannon Drive West Austin Texas 78735 8598 M MOTOROLA CONTENTS INTRODUCTION 1 1 1 1 EVALUATION MODULE DESCRIPTION AND FEATURES 1 1 EQUIPMENT 1 RR hn hr 2 1 WHAT YOU GET WITH THE EVALUATION MODULE 2 1 WHAT YOU NEED TO SUPPLY ie 2 2 EVM THEORY OF OPERATION 3 1 INPUTS AND OUTPUTS sp EER a a tret Sow toe bare erd brede OA 3 1 OPERATING MODE SELECTION 3 4 BOOTSTRAP CONFIGURATION USINGUJP9 3 4 ONGEM PORT Lua Ta xat TES 3 5 RS 232 CONNECTIONS AND JP1 con 3 6 OPERATING MODES AND SRAM REFRESH IN THE 56007 3 6 EVALUATION MODULE PARTS LIST o oo auauna aaa anaana aaa 3 6 POWER SUPPLIES SS 3 6 Ve SEE NG Suction SA A ka asan 3 7 DIGITAL SIGNAL PROCESSOR OPERATING FREQUENCY 3 8 EXTERNAL INTERRUPT REQUESTS 3 8 PERIPHERAL SPEC FICATIONS 1 4 1 CS5390 STEREO ADC e 28 0 a em RIA du aca adin 4 2 CS4331 STEREO DAC aaa 4 3 CS3310 STEREO DIGITAL VOLUME CONTROL 12 2 2 2 2 2 2 2 esee 4 4 CS8412 DIGITAL AUDIO INTERFACE RECEIVER 2 222 2 2 l l 4 5 CS8402A DIGITAL AUDIO INTERFACE TRANSMITTER 4 6 STK10C68 CMOS 2K X 8 NVSRAM aan 4 7 SC937 02 AES EBU TRANSFORM
22. ER 0ccccceeeeeeeeeues 4 8 PAINE avse see Led ail ELLA 4 8 WIRINGFORKEYPAD alan 4 10 EPM7032 PLDEOGUATIONS SS nn 5 1 INTRODUCTION TO THE GUI SS n 6 1 STARTING THE GUL SG 6 1 THE GUI WINDOWS onen 6 2 EVALUATION MODULE SCHEMATICS 1 0 0 7 1 SCHEMATIC DIAGRAMS SG 7 1 EVALUATION MODULE PARTSLIST aaa nennen 8 1 PARTS LISTING ret ain c E I UT E e a BEA ng RE ree ee ee 8 1 M MOTOROLA 56007EVM User s Guide iii 56007EVM User s Guide M MOTOROLA List Of Figures Figure 2 1 EVM Component Layout Lis EET eee ee 2 2 Figure 3 1 JPA PIONEER caret AMAR on dd ER se 3 5 Figure 4 1 CS5390 ADCs ah RAAR DOE ele ete SMS 4 2 Figure 4 2 Oodd DAE LA RR BERE ee Won m Laos 4 3 Figure 4 3 CS3310 Stereo Digital Volume Control 4 4 Figure 4 4 Serial Port Timing for the CS3310 4 4 Figure 4 5 CS8412 Digital Audio Interface Receiver 4 5 Figure 4 6 CS8402 Digital Audio Interface Transmitter 4 6 Figure 4 7 STK10C68 8K x 8 nvSRAM 4 7 Figure 4 8 SC937 02 AES EBU Transformer 4 8 Figure 4 9 LCD Softswitch Screens varder 4 9 Figure 4 10 LCD Keypad Screens 4 10 Figure 4 11 Keypad Wiring Diagram 4 11 Figure 6 1 B Ice 6 2 Figure 7 1 BSPOEOO vaere ee AE SR E 7 3 Figure 7 2 Microcontroller and LCD 20 nia
23. P4 4 to JP4 6 3 1 1 Clock Select The Evaluation Module provides a means for the user to select which clock controls the reception and transmission of digital audio see Table 3 2 below JP2 selects the ADC and DAC clocks which when jumpered are set at 44 1 KHz and when not jumpered at 48 KHz The expansion connector J5 can be used to directly access the DSP The receive SAI bus may be clocked by the selection made at JP2 44 1 KHz or 48 KHz or be clocked by the received SPDIF signal The transmit SAI bus may be clocked by either the clock selected at JP2 or by the data and word clocks output from the DSP when it is in master mode It is the user s responsibility to ensure that data is output at the desired rate See Table 3 2 below Table 3 2 Digital Audio Receive Transmit Jumper Configuration Receive Jumper JP5 1to Jumper JP5 3 to ons Transmit JP5 2 JP5 4 ump Clocked by crystal Clocked by received SPDIF EE Clocked by crystal Clocked by DSP 3 2 56007EVM User s Guide M mororoLa Evaluation Module Theory of Operation Inputs and Outputs 3 1 2 Serial Audio Interface SAI The DSP56007 SAI transmitter drives the six analog outputs and the SPDIF output PS is the default mode for the DACs The Master Clock MCLK rate for the DACs is 256 X F The dual RC networks after the DACS serve as AC couplers for audio data and as low pass filters to convert the delta sigma digital output pulses to analog wavefor
24. P5 col JP3 Optical JP2 H 30 Pin Out ET B H SIMM 00 PLD CS8402A 125 2 Socket 2 J3 J9 O Analog DSP STK10C68 O Power In 99 S p3 E J18 SPDIF 00 0000 Out 00 0000 co 68HC11E9 JEG SC937 02 aal JP9 oo EE 68HC705K1 JP1 oo Eb I RS 232 O OncEM go LCD Display el Reset J2 A e Digital Infrared Power Remote Receiver Figure 2 1 Evaluation Module Component Layout 2 2 WHAT YOU NEED TO SUPPLY e A PC 386 or higher with minimum 2 Mbytes of memory a 3 5 floppy disk drive and a serial port capable of at least 19 200 bits per second data transfer rate e An RS 232 cable DB9 male to DB9 female Power supplies dual 8 12V DC for analog circuits 8 15V AC or DC for digital circuits 2 2 56007EVM User s Guide M mororoLa Equipment What you need to supply e An audio source an audio amplifier driving headphones or speakers and cables with RCA phono connectors are required to use the demo software A mororoLa 56007EVM Users Guide 23 Equipment What you need to supply 24 bstovevmUsersGulde OE SECTION 3 EVALUATION MODULE THEORY OF OPERATION Refer to Section 7 56007EVM Schematics for reference to pinouts and jumper configurations 3 1 INPUTS AND OUTPUTS Analog signals connected to the Evaluation Module inputs are converted to 20 bit data at the ADC U19 and U20 attenuate the signal and convert it to balanced mode The ADC has the Select Serial I O Mode SMODE pin pulled high to mak
25. THX 12 DNE 5 DNE 13 para Hae Tone On mo 6 inn AG Ed Tone On es Dar ve 14 Decrement Test Tone Level DNE 15 gt Decrement Delay Time Center Mode na 8 cr 16 DNE Center Mode Large xIf THX is selected the Test Tone scr Center Mode Left Center Right R Sur L Sur None If Prologic 3 Channel Mode is select Left Center Right Subwoofer If Prologic 4 Channel Mode is select Left Center Right R Sur L Sur Figure 4 10 LCD Keypad Screens 4 9 WIRING FOR KEYPAD A wiring diagram for a generic keypad is shown in Figure 4 11 410 S6007EVM Users Guide moremu Peripheral Specifications Wiring for Keypad n AE adie Se Do 9 9 9 9 10 Figure 4 11 Keypad Wiring Diagram M mororoLa 56007EVM Users Guide 41 Peripheral Specifications Wiring for Keypad 412 B6007EVM Users Guide OE EPM7032 PLD Equations SECTION 5 EPM7032 PLD EQUATIONS The following data represents the PLD equations for the DSP56007EVM ACK RST INPUT ClkSelA INPUT CLKSELB NPUT CNTL MUTE INPUT DSO INPUT DSP_RST INPUT EMI MRD INPUT EXP2 WSR INPUT FS_SENS INPUT IROA INPUT IROB INPUT TROC INPUT MODA_SEL INPUT MODB_SEL INPUT MODC_SEL INPUT RCVMASTER SEL INPUT TXMASTER SEL INPUT 11MHZ CLK INPUT 12MHZ CLK INPUT 8412 MCK INPUT ACK LCO31 5 ACK LCELL E0001 GND
26. _ LC014 74393m 82 QA 74393m 82 1 3 LC009 TFFE VCC LC026 VCC VCC VCC 74393m 82 OB 74393m 82 3 3 LCO13 TFFE LC009 LCO26 VCC VCC VCC 6 74393m 82 QC 74393m 82 5 5 _LC027 TFFE EQ017 LCO26 VCC VCC VCC _EO017 _LC009 amp _LCOIl3 CNTL_MUTE LC029 CNTL MUTE LCELL CNTL_MUTE GND 5 4 56007EVM User s Guide M MOTOROLA Introduction to the GUI Starting the GUI SECTION 6 INTRODUCTION TO THE GUI This section will give an introduction to the Graphical User Interface GUI detailing only that which is required to work through the brief example below Full details of the GUI can be found in the Debug Evaluation Module manual 6 1 STARTING THE GUI To start up the GUI type evm56K The display you see will be similar to that shown in Figure 6 1 A mororoLa 56007EVM Users Guide 6 Introduction to the GUI The GUI Windows DATA HEX REGISTERS HEX m UNASSEMBLE COMMAND MENU Figure 6 1 The GUI 6 2 THE GUI WINDOWS The DATA window shown in the top left corner displays the data To display the contents of X data memory starting at location x 0 position the pointing device cursor in the COMMAND window click once and type display x 0 The radix in which the data is shown can be changed by clicking in the box that contains the word HEX in
27. a GRM42 6Y5V105Z16BL 1 0uF capacitor C22 C24 C25 C28 C66 C72 C73 C74 TDK CC1206CY5V335ZTR 3 3 uF capacitor C75 C1 C63 Murata GRM42 6XR103K050BD 0 01uF capacitor CB C20 Venkel C1210C0G500 682JNE 6 8nF capacitor C11 C19 C21 C23 C64 Future SME25T101M6X16LL 100uF Aluminum Electro lytic capacitor 56007EVM User s Guide M MOTOROLA Evaluation Module Parts List Parts Listing Table 8 1 DSP56007EVM Parts List Continued R9 R10 R11 R12 R13 R14 R15 R17 R19 R23 R24 R29 R30 R45 R48 R49 R57 Part Designator Manufacturer Part Number Description C2 C3 Murata GRM42 47pF capacitor 6C0G470J050BD C26 C29 C30 C31 C33 Murata GRM42 0 1uF capacitor C34 C35 C36 C37 C38 6X7R104K050BL C39 C40 C41 C42 C43 C44 C45 C46 C47 C48 C49 C50 C51 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C65 C67 C68 C69 C70 C71 C27 Venkel C1206X7R500 473KNE 0 047uF capacitor C13C14C15C16C17 Venkel C1206X7R500 272KNE 0 0027uF capacitor C18 C12 Venkel C1206X7R500 224KNE 0 22uF capacitor R50 109 1 4W resistor R25 R26 R31 R32 Venkel CR1206 8W 39R2FT 39 20 1 4W resistor R47 Venkel CR1206 8W 51R1FT 51Q 1 4W resistor R7 750 1 4W resistor R44 Venkel CR1206 8W 90R9FT 90 9Q 1 4W resistor R43 Venkel CR1206 8W 3740FT 3742 1 4W resistor R37 R38 R39 R40 R41 Future NRC12F6040TR 604Q 1 4W resistor R42 R46 Future CRCW1206 102JRT1 1 0KQ 1 4W resistor R16 R18 Newark 44F6300 1 5K 1 5KQ 1 4W resistor R1 R2 R3 R4 R5
28. claims costs damages and expenses and reasonable attorney fees arising out of directly or indirectly any claim of personal injury or death associated with such unintended or unauthorized use even if such claim alleges that Motorola was negligent regarding the design or manufacture of the part Motorola and B are registered trademarks of Motorola Inc Motorola Inc is an Equal Opportunity Affirmative Action Employer OnCE and Symphony are trade marks of Motorola Inc Motorola Inc 1995
29. crocontroller 7 4 MISO sanert HHR 3 4 MOST ay rak es EN ariel 3 4 N Non Maskable Interrupt Request NMI 3 8 nonvolatile RAM nvRAM 3 7 O OnCE Port 3 5 7 6 Operating Frequency 3 8 Operating Mode Selection 3 4 output analog filtering 4 3 P PE as dees 3 1 3 4 3 5 5 1 PLD Equations 5 1 Pee Neue Dre on 3 8 Power supplies 2 2 3 6 7 11 Programmable Logic Device 7 5 ProLogic a AP E REE trs 4 9 R RECAEL evelSe an eri renina 4 7 BO ye MM e til data 3 6 RS 232 and OnCE Port Interface 7 6 RS 232 cable 2 2 RS 232 serial communications 3 5 RS 232 Transceiver 3 5 S SAI transmitter 3 3 M MOTOROLA Index sample rate 4 3 BOB en 4 8 schematic diagrams 7 1 Serial Clock Input SCLK 3 3 Serial Data Clock SCK 3 3 Serial Data Input SDATA 3 3 Serial Data Input SDATAD 3 3 Serial Host Interface SHI port 3 4 SHI bootstrap mode 3 4 soft switches 3 3 4 9 SPDIF riren siena 3 1 3 3 4 5 4 6 SPIP TAO la diva ee d NT 7 10 SPDIF output 3 3 SPDIF transmitter 3 3 SPLmode c tho A dd 3 4 SRAM refresh 3 6 Stereo ADC 4 2 Stereo DAC 4 3 Stereo Digital Volume Control 4 4 STISTIOC OS das Tum ur
30. e M moronora Peripheral Specifications STK10C68 CMOS 2K x 8 nvSRAM 4 6 STK10C68 CMOS 2K X 8 NVSRAM The Simtek STK10C68 is a fast static RAM 25 30 35 and 45ns with a nonvolatile electrically erasable PROM EEPROM element incorporated in each static memory cell The SRAM can be read and written an unlimited number of times while independent nonvolatile data resides in EEPROM Data may easily be transferred from the SRAM to the EEPROM STORE cycle or from the EEPROM to the SRAM RECALL cycle using the NE pin nonvolatile enable It combines the high performance and ease of use of a fast SRAM with nonvolatile data integrity The STK10C68 features 12 15 20 and 25ns output enable access times hardware STORE and RECALL initiation automatic STORE and RECALL timing 10 or 10 STORE cycles to EEPROM unlimited RECALL cycles from EEPROM and 10 year data retention in EEPROM The STK10C68 requires a single 5V power supply EEPROM Array 256 x 256 Input Buffers Ag A Store A Static RAM Recall N Array MA Ag 256 x 256 Input Buffers Column VO Store Recall Control Column Decoder Ao A Ap A g Ait zm go Figure 4 7 STK10C68 8K x 8 nvSRAM M mororoLa 56007EVM Users Guide 47 Peripheral Specifications SC937 02 AES EBU Transformer 4 7 SC937 02 AES EBU TRANSFORMER The AES EBU circuit incorporates a transformer to reject common mode interference while
31. e multiplexes the audio and non audio data Either differential or single ended inputs can be decoded The CS8412 de multiplexes the channel user and validity data directly to dedicated output pins for the most commonly needed channel status bits VD DGND VA FILT AGND MCK M3 M2 M1 MO RS 422 Clock amp Data I Serial Port Receiver Recovery gt Registers CS12 FCK SEL CO Ca Cb Cc Cd Cal ERF CBL EO E1 E2 FO F1 F2 Figure 4 5 CS8412 Digital Audio Interface Receiver A mororoLa 56007EVM Users Guide 45 Peripheral Specifications CS8402A Digital Audio Interface Transmitter 4 5 CS8402A DIGITAL AUDIO INTERFACE TRANSMITTER The CS8402A is a monolithic CMOS device that encodes and transmits audio data according to the AES 3 1992 EBU Tech 3250 E IEC 958 SPDIF and EIAJ CP 340 interface standards The CS8402A accepts audio and non audio data and multiplexes and encodes the data The audio serial port is double buffered and capable of supporting a wide variety of formats The CS8402A multiplexes the channel user and validity data directly from dedicated input pins for the most commonly needed channel status bits M2 M1 MO MCK RST Serial Port RS422 Driver Registers Dedicated Channel CBL TRNPT Status Bits Figure 4 6 CS8402 Digital Audio Interface Transmitter 46 bstovevmUsersGuld
32. e the ADC the SAI receive clock master In master mode the ADC s Serial Data Clock SCLK and Left Right Select L R word clock pins are outputs The L R word clock output is the opposite polarity of PS It is inverted in the programmable logic device PLD to create true PS The ADC receives its oversampling clock on the Digital Section Clock Input ICLKD which is then internally divided by two and this signal is provided to the Analog Section Clock Input ICLKA ICLKD can be driven from the 11 2896 MHz clock the 12 288 MHz clock or the 256 x F clock produced by the CS8412 AES EBU Receiver The Audio Power Down Input APD and Digital Power Down Input DPD pins are wired to the Cntl_Mute signal of the PLD When pulled high the ADC will be muted When first pulled low the ADC will be reset then it will be enabled A mororora 56007EVM Users Guide 3 Evaluation Module Theory of Operation Inputs and Outputs The other possible input source comes from the SPDIF inputs J14 for electrical input and J17 for optical input Jumper JP4 selects the source see Table 1 below When receiving valid SPDIF input the SPDIF Receiver drives the Master Clock MCK output that is 256 times the Frame Sync frequency of the received data The CS8412 operates in Mode 3 the LS slave mode Table 3 1 Digital Audio Input Selection umper Selection J p Settings Flectric JP4 1 to JP4 3 SPDIF JP4 2 to JP4 4 Optical JP4 3 to JP4 5 SPDIF J
33. el digital audio applications design prototyping and development The fully assembled and tested circuit board contains 24 bit DSP56007 Digital Signal Processor operating at 66 MHz 8192 bytes of off chip SRAM and 8192 bytes of nonvolatile RAM Standard 30 pin SIMM slot for easy inexpensive DRAM expansion One 20 bit stereo analog to digital converter ADC three 18 bit stereo digital to analog converters DACs Programmable analog domain attenuators on the digital to analog outputs RCA jacks for all analog audio input output A mororoLa 56007EVM Users Guide 1 Introduction Evaluation Module Description and Features Optical and transformer isolated electrical SPDIF CP340 stereo digital audio inputs and outputs 50 pin expansion connector to provide the capability for expansion and or substitution of other input output peripherals as well as easy interprocessor communication between Motorola Evaluation Modules Socketed MC68HC11E9 52 pin CLCC microcontroller to allow the user to substitute user programmed microprocessor and prototype custom 68HC11 code allows connection to MC68HC11 emulation systems 2 x 16 character liquid crystal display LCD and four softswitches for user interface Connector provides capability to use optional standard 4 x 4 keypad matrix MC68705K1 microcontroller performing RS 232 to OnCE port command conversions 56007EVM User s Guide M mororoLA SECTION 2 EQUIPMENT The following section
34. hase response simply by changing the master clock frequency The CS4331 contains optional on chip de emphasis and operates from a single 5V power supply The CS4331 has a 96 dB dynamic range less than 0 003 THD low clock jitter sensitivity and completely filtered line level outputs that use linear phase filtering DEM SCLK CONFIG AGND VA LRCK Serial Input De emphasis Voltage Reference SDATAI Interface Y Analog Delta Sigma AOUTL Interpolator Modulator gt LAM kaa OU Hm Analog Interpolator Modulator ie AOUTR MCLK Figure 4 2 CS4331 DAC A mororoLa 56007EVM Users Guide 43 Peripheral Specifications CS3310 Stereo Digital Volume Control 43 CS3310 STEREO DIGITAL VOLUME CONTROL The CS3310 is a complete stereo digital volume control designed specifically for audio systems It features a 16 bit serial interface that controls two independent low distortion 0 001 THD N audio channels The CS3310 includes an array of well matched resistors and a low noise active output stage that is capable of driving a 600 Q load A total adjustable range of 127 dB in 0 5 dB steps is achieved through 95 5 dB of attenuation and 31 5 dB of gain The simple 3 wire interface provides daisy chaining of multiple CS3310s for multi channel audio systems The device operates from 5V supplies and has an input output voltage range
35. lease The clock master is derived from one of two sources the 11 2896 MHz clock or the 12 288 MHz clock The microcontroller also receives commands from either the soft switches 51 52 53 or 54 or from the Keypad Expansion Port J18 The current user screen or the results of these commands are then displayed by a modular LCD panel with a 2 x 16 character display The M mororoLa 56007EVM Users Guide 33 Evaluation Module Theory of Operation Operating Mode Selection microcontroller code is capable of driving larger LCD displays but all user screens are designed for a 2 x 16 character display The MC68HC711E9 communicates with the DSP via the Serial Host Interface SHI port in SPI mode When SS is pulled low the microcontroller can write to the DSP The MOSI and MISO lines pass control data through the DSP SHI in 24 bit mode SCK is the SPI Shift Clock from the DSP Again the expansion connector J5 can be used to access or intercept host port communications The Control Data Control Clock and Control Latch lines from the microcontroller control the digitally controlled analog domain attenuators The Control Mute line mutes the ADC and the DACs low is muted high is enabled 3 2 OPERATING MODE SELECTION DSP56007EVM modes can be selected at JP3 as shown in Table 3 3 Once the mode has been selected the PLD can receive interrupts from the network attached to J19 Table 3 3 Mode Select Jumpers
36. ms The digitally controlled analog domain attenuators receive the audio data and attenuate or amplify the data as determined by the microcontroller The attenuators receive the Serial Clock Input SCLK Serial Data Input SDATAT and the Chip Select Latch CS from the microcontroller 3 1 3 Sony Philips Digital Interface Format SPDIF The SPDIF transmitter receives data from the DSP through the Serial Data Input SDATA using the Frame Sync FSYNC and the Serial Data Clock SCK The transmitter outputs SPDIF audio signals through J15 electrical and J16 optical Fs sens from the clock select appears at the expansion connector in order to read the sampling rate with the DSP s General Purpose I O GPIO1 at J5 41 and also at U21 2 to select the state of the sample rate bits transmitted within the channel status block See the SPDIF specification for more information The channel status bits and block sync signals DRcv Blk DTrn Blk DRcv CS and DTrn CS are available at J5 43 to allow the DSP to read one of them as well Isolation transformers are used on both input and output although they are not strictly required for SPDIF because this Evaluation Module is intended to be used as a development system 3 1 4 Other Inputs and Outputs The infrared remote receiver connects directly to the MC68HC711E9 and receives its commands from an infrared remote though not currently implemented this feature is planned for a future software re
37. ot recommended that the user subject the board to power inputs in excess of the maximum levels listed Note Always supply the Evaluation Module with analog power prior to or simultaneous with the application of digital power If digital power is supplied before the analog power the DACs may go into one of three possible error modes no long term damage to the device will occur and will not function correctly If analog power is supplied first or if both analog power and digital power are applied simultaneously these problems do not appear and the DACs are properly initialized 3 9 MEMORY The Evaluation Module has 8K 8192 bytes each of fast Static RAM SRAM and of nonvolatile RAM nvRAM The SRAM operates at zero wait states at a 40 MHz DSP clock speed and with one wait state at 50 and 66 MHz The contents of the SRAM may be block loaded into nvRAM and the contents of the nvRAM may be block loaded into the SRAM The lowest 3072 bytes of the nvRAM may also be used to store code to load into the DSP via EMI bootstrap On chip DSP56007 memory includes e 6348 x 24 bit on chip program ROM and 52 x 24 bit bootstrap ROM e 1024 x 24 bit on chip X data RAM plus 512 x 24 bit on chip X data ROM e 2176 x 24 bit on chip Y data RAM plus 512 x 24 bit on chip Y data ROM e 1024 x 24 bits of the Y data RAM can be configured as program RAM replacing 1280 x 24 bits of program ROM Table 3 5 DSP56007 Internal Memory Configurations X RAM 2 176K
38. pling followed by digital filtering and decimation which removes the need for an external anti alias filter beyond the simple balanced RC filter formed by R25 R26 and C8 R31 R32 and C20 for the right channel The ADC uses a differential architecture that provides excellent noise rejection The CS5390 has a filter passband of DC to 21 7kHz The filters are linear phase have 0 005 dB passband ripple and greater than 100 dB stopband rejection The operating temperature range is 0 to 70 ICLKA APD ACAL OCLKD ICLKD FSYNC SCLK LR LP Filter Digital Decimation v gt Filter Comparator DAC Digital Decimation LP Filter Filter Calibration Calibration Microcontroller SRAM Comparator VA VA VL LGND DCAL DPD VD DGND Figure 4 1 CS5390 ADC 42 S6007EVM User s Guide OE Peripheral Specifications CS4331 Stereo DAC 4 2 CS4331 STEREO DAC The CS4331 is a complete stereo digital to analog converter DAC with 18 bit resolution including interpolation 1 bit digital to analog conversion and output analog filtering in an 8 pin package The CS4331 is based on delta sigma modulation where the modulator output controls the reference voltage input to an ultra linear analog low pass filter This architecture allows for infinite adjustment of sample rate between 1 kHz and 50 kHz while maintaining linear p
39. the diagram above Data can also be displayed in a graphical form To do this type display x 0 graph To change back to text type display x 0 text The UNASSEMBLE window shows an unassembled version of the contents of program memory The next instruction to be executed will be highlighted The COMMAND window is where OnCE commands i e the controlling commands are entered The REGISTERS window shows the contents of the registers of the ALU Arithmetic Logic Unit and the AGU Address Generation Unit 6 2 56007EVM User s Guide M MOTOROLA 9PIN9 SjA9SN INA3Z009S DSP RST DO 3 B4 2 G3 4 F3 DSP MODA LY 3 B3 DSP MODB CI 3 B3 DSP MODC D 3 B3 EMI 3 F3 5 A4 DSP56007 5V 2 DSP_Ck 768 kHz 53 27 LAN Pe Qvcc2 H QVCC1 p QVCCO JO QGND2 30 0 01 UF QGND1 w s QGNDO gal 36o RESET Bi 21 MODA IRQA o X DR ol MODB IRQB SO 4 F4 MODC NMI ONCE Interface DSCK OS1 8 DSO 45V FEV 4 F4 3 F4 DSI OSO DVCCO SVCC1 4 F5 SVCCO ENE DSCK OS1 sal DENDO 4 F5 MRD 77 GED CJ ExP1 MWR 78 S MAR MCS0 ___ MA17 MCS1 MA16 MCS2 MA15 MCS3 MA14 MA13 MA12 MA11 MA10 MA9 MA8 MA7 MA6 MA5 MA4 MA3 MA2 MA1 MAO N MD MDG MD MD7 MD6 AVCC1 MD5 AVCCO MD4 MD3 MD2 MD1 MDO uni Figure 7 1 DSP56007 SPINS SjA9SN NA3Z009S 5v R20 gt 20 K Contrast e U16 LCD Panel Cntl Data 7 A6 Cntl Cik 7 A6 Cntl Latch LW 7 A6 Cntl Mute 7 G4
40. und Connect DGnd Anal og De coupl ing Caps all 0 1 uF C56 C57 C70 U 2 C58 C59 C7 1 U13 C60 U19 C61 U20 0 4 05 C69 U1 1C62 U23 Figure 7 9 Power Supply Evaluation Module Parts List Parts Listing SECTION 8 EVALUATION MODULE PARTS LIST 8 1 PARTS LISTING The following four pages contain in table form information on the parts and devices on the Evaluation Module Contact information for suppliers of key devices as indicated by footnote is also included at the end of the table A mororoLa 56007EVM Users Guide 61 Evaluation Module Parts List Parts Listing Table 8 1 DSP56007EVM Parts List Part Designator Manufacturer Part Number Description Ut Motorola DSP56007 DSP U2 Motorola MC68HC711E9 Microcontroller U24 Motorola MC68HC705K1 Microcontroller OnCE U7 Crystal 2 CS5390 KS ADC U8 U9 U10 Crystal CS4331 KS DAC U21 Crystal 2 CS8402 CS AES EBU Transmitter U23 Crystal 2 CS8412 CS AES EBU Receiver U11 U12 U13 Crystal CS3310 KS Digital Volume Controller L3 L4 Scientific SC937 02 Audio Isolation Transformer STE UG Simtek STK1068 S45 SRAM nVRAM U16 Hitachi LM052L LCD Module U14 U17 Motorola MC7805 Voltage Regulator U18 Motorola MC7905 Voltage Regulator U19 U20 Motorola MC33078 Op Amp U5 Altera EPM7032TC44 12 PLD D1 D2 D3 D4 D7 Rectron FM4001 Rectifier SMD U4 Maxim MAX232CSE RS232 Transceiver C4 C5 C6 C7 C9 C10 Murat
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