IPUG87 - Median Filter IP Core User's Guide
Contents
1. Edge Mode C Cop Miror Value lo 0 255 m Data Features Data width 8 Tags width fo i Filter Specifications This section provides settings that define the input and output frame sizes as well as what to do when the sampling window straddles the frame edges Video Frame Width This parameter defines the input video frame size width Video Frame Height This parameter defines the the input video frame size height Window Width and Height This parameter defines the filter window size Active Region Dynamic region selection This checkbox enables the feature and adds the upleftx y and actwidth height input ports Full screen This checkbox sets the active region to the video frame size Horizontal Coordinates of First Active Pixel Vertical Coordinates of First Active Pixel These coordiates set the upper left corner of the active region Active Region Width Active Region Height These coordiates set the size of the active region Edge Mode Radio buttons select Copy Mirror or Value for edge mode If Value is selected the entry field is the pixel value used for window locations that overlap the frame boundary IPUG87_01 0 December 2010 11 Median Filter IP Core User s Guide Lattice Semiconductor Parameter Settings Data Features Data width This parameter sets the width of the incoming pixel data Tags width This parameter sets the width of the tags_in and tags_out ports Advanced Optio2. Lattice Semiconductor a a Corporation LatticeCORE Median Filter IP Core User s Guide December 2010 IPUG87_01 0 Semiconductor Table of Contents Corporation Lattice Chapter 1 Introduction cities 4 Quick Facts ada 4 A A ile 4 Chapter 2 Functional Description oooommoccnnnncncnnnnncccnnnnnnnne nene ee ee iii eee iii 6 Key Concepts aa 6 BlockiDiagram sa illa A 6 Active Region Select mc ae 7 Median Arithmetic Unit aria iaia 7 Primary VO aaa aaa 8 Interface DESscriptions vrai 8 Video Input QUito tt llanta ti 8 Timing Specifications cisne aaa ae ad aria 9 Chapter 3 Parameter Settings lille alal laid 10 Basic Options Taiana A iaa 10 Filter Specifications imac iaia 11 Active ON is 11 Data FOALUICS viii ai la e e 12 Advanced Options Fab ariani ala 12 Memory TYPE stacia A td levy sweets 12 Optional Ports iaia anziana a 12 Synthesis Options rada eee ai ail 12 Chapter 4 IP Core GENOA is 13 Licensing the IPCore ii aaa ai alia iaia ia 13 Getting Started sissies Eoaea aen AE NESE EE a EEEa RAE Ea Eaa Oaa ea eaa ieena N ENTAS 13 IPexpress Created Files and Top Level Directory Structure i 15 Instantiating the Core a 16 Running Funcional SiMUAION ei 16 Synthesizing and Implementing the Core in a Top Level Design ii 16 Hardware Evaluation 17 Enabling Hardware Evaluation in DiaMond naar nn nn nn nar n carr n nn n
3. also be used to evaluate the core in hardware in user defined designs Enabling Hardware Evaluation in Diamond Choose Project gt Active Strategy gt Translate Design Settings The hardware evaluation capability may be enabled disabled in the Strategy dialog box It is enabled by default Enabling Hardware Evaluation in ispLEVER In the Processes for Current Source pane right click the Build Database process and choose Properties from the dropdown menu The hardware evaluation capability may be enabled disabled in the Properties dialog box It is enabled by default IPUG87_01 0 December 2010 17 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation Updating Regenerating the IP Core By regenerating an IP core with the IPexpress tool you can modify any of its settings including device type design entry method and any of the options specific to the IP core Regenerating can be done to modify an existing IP core or to create a new but similar one Regenerating an IP Core in Diamond To regenerate an IP core in Diamond 1 In IPexpress click the Regenerate button 2 In the Regenerate view of IPexpress choose the IPX source file of the module or IP you wish to regenerate 3 IPexpress shows the current settings for the module or IP in the Source box Make your new settings in the Tar get box 4 If you want to generate a new set of files in a new location set the new location in the IPX Target File box Th
4. cnn rre 17 Enabling Hardware Evaluation in ispLEVER ooooocccnnoncccccnononcnnnonannncnnnnnnnnnnnnnnnnnn cnn Eaa rra nn nr rra anna ccnnnnnnnss 17 Updating Regenerating the IP Core cnn nan nc anna nn nn nn rana narran nn nn nara rna nana 18 Regenerating an IP Core in Diamond nn naar cnn nan nc nn nn arar n rara n cana r nana n cn nan ana nanncnns 18 Regenerating an IP Core in ispLEVER nano nnnnnncn nan cnc nan n nn nn nn nr n nr r nara nana ra nnnncans 18 Chapter 5 Support RESOURCES cai 20 Lattice Technical Suppott iii 20 Online Forums iasc iaia aiar aa 20 Telephone Support Hotline conan c cnn conan cnn rca nrranan 20 E Mail SUPPO ius ai ai lalla 20 Local SUP ONE cas tse cee see occ irritada iii Ltt eee ee ts 20 Internet dial ea i it 20 References RIA alia 20 L atticeEGP2 M ai ai Lai aio aa 20 Lattice ECPI iii aaa ail alii ia 20 LalticaXP Licor aaa a vai 20 Revisioni HIST Wai iii 20 Appendix A Resource Utilization uao ieri 21 LattiteXP2 FPGAS ricla ia ei 21 Ordering Part Number nd Sedans eis eee le 21 2010 Lattice Semiconductor Corp All Lattice trademarks registered trademarks patents and disclaimers are as listed at www latticesemi com legal All other brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice
5. file provides the synthesized IP core lt username gt _bb v vhd This file provides the synthesis black box for the user s synthesis lt username gt _inst v vhd This file provides an instance template for the Median Filter IP core lt username gt _beh v vhd This file provides the front end simulation library for the Median Filter IP core IPUG87_01 0 December 2010 15 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation Table 4 2 provides a list of key additional files providing IP core generation status information and command line generation capability are generated in the user s project directory Table 4 2 Additional Files File Description This file is created when the GUI Generate button is pushed This file may be run from com lt username gt nerate tcl gt username gt _generate tc mand line lt username gt _generate log This is the synthesis and map log file lt username gt _gen log This is the IPexpress IP generation log file Instantiating the Core The generated Median Filter IP core package includes black box lt username gt _bb v and instance lt user name gt _inst v templates that can be used to instantiate the core in a top level design An example RTL top level reference source file that can be used as an instantiation template for the IP core is provided in lt project_dir gt median eval lt username gt src rtl t
6. pixels by performing a partial sorting Figure 2 4 3x3 Median Arithmetic Unit Scheme Din1 gt Din2 Sort Sort i Din3 gt Din4 gt gt ia Din5 gt Sort Sort gt gt Sort gt Dout Din6 gt gt FP BEE Din7 i Ding gt Sort Sort Din9 gt gt Each basic node allows sorting of three elements To do that each node compares the three elements by means of three comparators using its output in three 3 1 multiplexers as shwon in Figure 2 5 IPUG87_01 0 December 2010 7 Median Filter IP Core User s Guide Lattice Semiconductor Figure 2 5 Scheme for Each Basic Node Functional Description A Compare gt gt B A Higher Ly PU __ gt Compare gt gt Sot gt gt c gt _ gt Cc Lower ll Compare gt gt gt gt Primary I O Table 2 1 Primary I O Port Size 1 0 Description Global Signals clk 1 I System clock rstn 1 I System wide asynchronous active low reset signal ce 1 Active high clock enable optional sr 1 Active high synchronous reset optional Video Input ready 1 O Coreis ready for input dvalid_in 1 I Input valid frmsync_in 1 Current pixel is at row 0 column 0 din 4 24 Pixel data in Video Output dvalid_out 1 O Output valid fr
7. 254 128x128 7x7 VALUE 8 EBR 7796 11482 6934 188 1 Performance and utilization data are generated targeting an LFE2M20E 7F484C device using Lattice Diamond 1 1 and Synplify Pro D 2010 03L SP1 software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M S family Ordering Part Number The Ordering Part Number OPN for the Median Filter IP core on LatticeECP2M S devices is MED FILT PM U1 IPUG87_01 0 December 2010 22 Median Filter IP Core User s Guide
8. 320 Video frame height 100 1200 240 Dynamic frame size updating Oor1 0 Dynamic region selecting Oor1 0 Horizontal coordinates of first active pixel 0 VWIDTH 1 0 Vertical coordinates of first active pixel 0 VHEIGHT 1 0 Active region width 1 VWIDTH UPLEFTX 1 VWIDTH 1 Active region height 1 VHEIGHT UPLEFTY 1 VHEIGHT 1 Window width and height 3x3 5x5 7X7 3x3 Edge mode VALUE COPY MIRROR VALUE Edge value 0 1 lt lt DWIDTH 1 0 Tags width 0 0 Internal regs data bus width 8 16 32 64 8 Input buffer type EBR Distributed EBR Basic Options Tab The Basic Options tab provides settings for video frame and window parameters data width and edge mode options Note Median Filter core version 1 0 does not support dynamic frame size updating and dynamic region selecting Figure 3 1 shows the contents of the Basic Options tab IPUG87_01 0 December 2010 10 Median Filter IP Core User s Guide Lattice Semiconductor Parameter Settings Figure 3 1 Basic Options Tab Basic Options Advanced Options Filter Specifications TT Dynamic frame size updating Video frame width 320 100 2000 Video frame height 240 100 1200 Window width and height 3x3 Active Region T Dynamic region secleting IV Full screen Horizontal coordinate of frist active pixel fi 0 319 Active region width 319 11 319 Vertical coordinate of first active pixel fo 0 239 Active region height 1 239
9. IPUG87_01 0 December 2010 2 Median Filter IP Core User s Guide Lattice Semiconductor Table of Contents Lattice ECP3 FPGASY cain A alain a 21 Ordering Part Number atcetatanizi neliala asian dii agi lia lia iaia 21 L atticeECP2 S FPGAS gt ictus ira nad 21 Ordering Part Number liane iaia Rea ei 22 LatticeEGP2M S FPGAS scia LA AAA RR TA a 22 Ordering Part Number IPUG87_01 0 December 2010 3 Median Filter IP Core User s Guide El atti Ce Chapter 1 711117 Semiconductor Introduction a u a a a u Corporation This user s guide provides a description of the Median Filter IP core Median filtering is a popular method of noise removal employed extensively in applications involving speech signal and image processing This non linear tech nique has proven to be a good alternative to linear filtering as it can effectively suppress impulse noise while pre serving edge information The core s flexible architecture supports a wide variety of video frame sizes on LatticeECP2 S LatticeECP2M S LatticeXP27M and LatticeECP3 devices A simple IO handshake makes the core suitable for either streaming or bursty input video data Quick Facts Table 1 1 gives quick facts about the Median Filter IP core Table 1 1 Median Filter IP Core Quick Facts Median Filter Core Frame Frame Frame Size 320x240 Size 256x256 Size 128x128 Window Size 3x3 W
10. ation by doing the following 1 Open ModelSim 2 Under the File tab select Change Directory and choose the folder lt project _dir gt median eval lt username gt sim modelsim scripts 3 Under the Tools tab select Execute Macro and execute the ModelSim do script shown Note When the simulation is complete a pop up window will appear asking Are you sure you want to finish Choose No to analyze the results Chosing Yes closes ModelSim Synthesizing and Implementing the Core in a Top Level Design Synthesis support for the Median Filter IP core is provided for Mentor Graphics Precision or Synopsys Synplify The Median Filter IP core itself is synthesized and is provided in NGO format when the core is generated in IPexpress Users may synthesize the core in their own top level design by instantiating the core in their top level as described previously and then synthesizing the entire design with either Synplify or Precision RTL synthesis IPUG87_01 0 December 2010 16 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation The top level file lt username gt _eval_top v provided in lt project_dir gt median eval lt username gt src top supports the ability to implement the Median Filter core in isolation Push button implementation of this top level design with either Synplify or Precision RTL Synthesis is supported via the project files lt username gt _eval ldf Diamond or syn ispLEVER located in
11. attice Diamond 1 1 and Synplify Pro D 2010 03L SP1 software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family Ordering Part Number The Ordering Part Number OPN for the Median Filter IP core on LatticeECP3 devices is MED FILT E3 U1 LatticeECP2 S FPGAs Table A 3 Performance and Resource Utilization Window Data Input Buffer Frame Size Size Edge Mode Width Type Slices LUTs Registers fmax 320x240 3x3 VALUE 8 EBR 546 697 568 225 256x256 5x5 VALUE 8 EBR 2198 2943 2211 223 128x128 7x7 VALUE 8 EBR 8132 11482 6934 206 1 Performance and utilization data are generated targeting an LFE2 35E 7F672C device using Lattice Diamond 1 1 and Synplify Pro D 2010 03L SP1 software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2 S family IPUG87_01 0 December 2010 21 Median Filter IP Core User s Guide Lattice Semiconductor Resource Utilization Ordering Part Number The Ordering Part Number OPN for the Median Filter IP core on LatticeECP2 S devices is MED FILT P2 U1 LatticeECP2M S FPGAs Table A 4 Performance and Resource Utilization Window Data Input Buffer Frame Size Size Edge Mode Width Type Slices LUTs Registers fmax 320x240 3x3 VALUE 8 EBR 546 697 568 224 256x256 5x5 VALUE 8 EBR 2198 2943 2211
12. e base of the file name will be the base of all the new file names The IPX Target File must end with an ipx exten sion 5 Click Regenerate The module s dialog box opens showing the current option settings 6 In the dialog box choose the desired options To get information about the options click Help Also check the About tab in IPexpress for links to technical notes and user guides IP may come with additional information As the options change the schematic diagram of the module changes to show the I O and the device resources the module will need 7 To import the module into your project if it s not already there select Import IPX to Diamond Project not available in stand alone mode 8 Click Generate 9 Check the Generate Log tab to check for warnings and error messages 10 Click Close The IPexpress package file ipx supported by Diamond holds references to all of the elements of the generated IP core required to support simulation synthesis and implementation The IP core may be included in a user s design by importing the ipx file to the associated Diamond project To change the option settings of a module or IP that is already in a design project double click the module s ipx file in the File List view This opens IPexpress and the module s dialog box showing the current option settings Then go to step 6 above Regenerating an IP Core in ispLEVER To regenerate an IP core in ispLEVER 1 In the IPexpress t
13. ectualproperty aboutip isplevercoreonlinepurchas cfm Users may download and generate the Median Filter IP core and fully evaluate the core through functional simula tion and implementation synthesis map place and route without an IP license The Median Filter IP core also supports Lattice s IP hardware evaluation capability which makes it possible to create versions of the IP core that operate in hardware for a limited time approximately four hours without requiring an IP license See Hardware Evaluation on page 17 for further details However a license is required to enable timing simulation to open the design in the Diamond or ispLEVER EPIC tool and to generate bitstreams that do not include the hardware evalu ation timeout limitation Getting Started The Median Filter IP core is available for download from the Lattice IP Server using the IPexpress tool The IP files are automatically installed using ispUPDATE technology in any customer specified directory After the IP core has been installed the IP core will be available in the IPexpress GUI dialog box shown in Figure 4 1 The IPexpress tool GUI dialog box for the Median Filter IP core is shown in Figure 4 1 To generate a specific IP core configuration the user specifies e Project Path Path to the directory where the generated IP files will be located e File Name username designation given to the generated IP core and corresponding folders and files e Diam
14. g box to display the Median Filter IP core Configuration GUI as shown in Figure 4 2 From this dialog box the user can select the IP parameter options specific to their application Refer to Parameter Settings on page 136 for more information on the Median Filter IP core parameter settings Figure 4 2 Configuration GUI Diamond Version ox Configuration Generate Log Median Filter Basic Options Advanced Options q Filter Specifications Ficlk I Dynamic frame size updating stn ready Video frame width 320 100 2000 Video frame height 240 100 1200 fimsyne_out gt Window width and height 3x3 vl frmsync_in Active Region dvalid_ out ROLES ldvalidin I Dynamic region secletina MW Full screen din 7 0 Horizontal coordinate of frist active pixel fo 0 319 Active region width a 9 1 319 din dout 7 0 gt Vertical coordinate of first active pixel fo 0 239 Active region height 29 1 239 Edge Mode C Copp Minor Value fo 0 255 Data Features Data widih 2 Tags width 0 ml I Import IPX to Diamond project Generate Close Help IPUG87_01 0 December 2010 14 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation IPexpress Created Files and Top Level Directory Structure When the user clicks the Generate button in the IP Configuration dialog box the IP core and supporting files are generated in the
15. he median arithmetic unit which chooses the median input pixel value IPUG87_01 0 December 2010 6 Median Filter IP Core User s Guide Lattice Semiconductor Functional Description Active Region Selection The Median Filter core may be configured to allow the user to dynamically alter the coordinates of the active region of the input frame The active region concept is illustrated in Figure 2 3 Figure 2 3 Active Region 0 0 upleftx uplefty Active Region upleftx actwidth uplefty actheight VWIDTH VHEIGHT The upleftx and uplefty ports set the coordinates of the first pixel in the input frame that will have a corresponding pixel in the output frame The actwidth and actheight ports determine the region of pixels in the input frame that will have corresponding pixels in the output frame Both sets of inputs upleft and active region are synchronized internally and delivered to the core logic at the appropriate time to avoid anomalies when moving from frame to frame Median Arithmetic Unit Different window sizes have different fast algorithms and implementations The following description is based on the 3x3 window size The scheme of median arithmetic unit of 3x3 window size is shown in Figure 2 4 which is much better than other solutions since it needs a much lower number of basic nodes This scheme uses the minimum exchange network required to produce the median from nine
16. here are a number of ways to receive technical support as listed below Online Forums The first place to look is Lattice Forums www latticesemi com support forums cfm Lattice Forums contain a wealth of knowledge and are actively monitored by Lattice Applications Engineers Telephone Support Hotline Receive direct technical support for all Lattice products by calling Lattice Applications from 5 30 a m to 6 p m Pacific Time e For USA and Canada 1 800 LATTICE 528 8423 e For other locations 1 503 268 8001 In Asia call Lattice Applications from 8 30 a m to 5 30 p m Beijing Time CST 0800 UTC Chinese and English language only e For Asia 86 21 52989090 E mail Support e techsupport latticesemi com e techsupport asia O latticesemi com Local Support Contact your nearest Lattice sales office Internet www latticesemi com References LatticeECP2 M e HB1003 LatticeECP2 M Family Handbook LatticeECP3 e HB1009 LatticeECP3 Family Handbook LatticeXP2 e DS1009 Lattice XP2 Datasheet Revision History Document IP Core Date Version Version Change Summary December 2010 01 0 Initial release IPUG87_01 0 December 2010 20 Median Filter IP Core User s Guide Lattice a Semiconductor Resource Utilization a a a Corporation This appendix gives resource utilization information for Lattice FPGAs using the Median Filter IP core IPexpress is the Lattice IP configuration ut
17. ility and is included as a standard feature of the ispLEVER design tools Details regarding the usage of IPexpress can be found in the IPexpress and ispLEVER help system For more infor mation on the ispLEVER design tools visit the Lattice web site at www latticesemi com LatticeXP2 FPGAs Table A 1 Performance and Resource Utilization Window Data Input Buffer Frame Size Size Edge Mode Width Type Slices LUTs Registers fmax 320x240 3x3 VALUE 8 EBR 546 697 568 214 256x256 5x5 VALUE 8 EBR 2198 2943 2211 214 128x128 7x7 VALUE 8 EBR 8132 11482 6934 171 1 Performance and utilization data are generated targeting an LFXP2 30E 7F484C device using Lattice Diamond 1 1 and Synplify Pro D 2010 03L SP1 software Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeXP2 family Ordering Part Number The Ordering Part Number OPN for the Median Filter IP core on LatticeXP2 devices is MED FILT X2 U1 LatticeECP3 FPGAs Table A 2 Performance and Resource Utilization Window Data Input Buffer Frame Size Size Edge Mode Width Type Slices LUTs Registers fmax 320x240 3x3 VALUE 8 EBR 534 680 570 255 256x256 5x5 VALUE 8 EBR 2179 2908 2209 231 128x128 7x7 VALUE 8 EBR 8184 11536 6909 191 1 Performance and utilization data are generated targeting an LFE3 70E 8FN484CES device using L
18. indow Size 5x5 Window Size 7x7 FPGA Familes Supported LatticeECP2 S LatticeECP2M S LatticeXP2 LatticeECP3 LFXP2 5E LFXP2 5E LFXP2 17E Core Requirements Minimum Device Reduired LFE2 6E LFE2 6E LFE2 12E UM PEVCE Pee LFE2M20E LFE2M20E LFE2M20E LFE3 17EA LFE3 17EA LFE3 17EA LUTs 700 2900 11500 EBRs 1 1 2 LatticeXP2 Registers 550 2200 6900 sysDSP blocks 0 LUTs 700 2900 11500 EBRs 1 1 2 LatticeECP2 S Registers 550 2200 6900 sag sysDSP blocks 0 Resource Utilization LUTs 700 2900 11500 EBRs 1 1 2 LatticeECP2M S Registers 550 2200 6900 sysDSP blocks 0 LUTs 700 2900 11500 EBRs 1 1 2 LatticeECP3 Registers 550 2200 6900 sysDSP blocks 0 Lattice Implementation Lattice Diamond 1 1 or ispLEVER 8 1SP1 Synthesis Synopsys Synplify Pro for Lattice D 2010 03L SP1 Design Tool Support Dis f FP Simulati Aldec Active HDL 8 2 Lattice Edition Il imulation Mentor Graphics ModelSim SE 6 3F Features e Single color plane e Three filter window sizes 3x3 5x5 and 7x7 e Configurable input data width IPUG87_01 0 December 2010 4 Median Filter IP Core User s Guide Lattice Semiconductor Introduction e Input frame size set at compile time e Static active region selection e Edge mode handling COPY MIRROR or VALUE e Optional clock enable and synchronous reset ports IPUG87_01 0 December 2010 5 Median Filter IP Core User s Guide zg Semiconductor Functional Description a a a Corporation La
19. msync_in dvalid_in din do di X d2 d3 d4 X d5 d6 d7 d8 d9 Xd10 Adii Xd12 Xd13 X d14 frmsync_out 1 dvalid_out dout J do di Xd2 Yd3 Xd4 Xd5 Xde Xd7 Xd8 d9 Xdto Ydi1 Xd12 Figure 2 7 Timing Diagram for Median Filter with Gaps in Inputs ek LI LI LI L L L L L L L IL LLILILILII ready frmsync_in N dvalid_in N N Y NY din do di d2 d3 d4 X d5 X de frmsync_out dvalid_out F dout JED CI E DD TD IPUG87_01 0 December 2010 9 Median Filter IP Core User s Guide a a a Corporation Lattice cnt 2 Semiconductor Parameter Settings The IPexpress tool is used to create IP and architectural modules in the Diamond or ispLEVER software Refer to IP Core Generation on page 13 for a description of how to generate the IP The Median Filter IP core can be cus tomized to suit a specific application by adjusting parameters prior to core generation Since the values of some parameters affect the size of the resultant core the maximum value for these parameters may be limited by the size of the target device Table 3 1 provided the list of user configurable parameters for the Median Filter IP core Table 3 1 Median Filter IP Core Parameters Parameter Range Default Data width 4 24 8 Video frame width 100 1200
20. msync_out 1 O Current output pixel is at row 0 column 0 dout 4 24 O Pixel data out Dynamic Frame Size and Active Region Controls Optional pwrite 1 I Internal regs write enable paddr 4 I Internal regs address pwdat 8 16 32 64 I Internal regs write data prdat 8 16 32 64 O Internal regs read data Miscellaneous tags_in TAGS_WIDTH Tags input tags_out TAGS_WIDTH O Tags output Interface Descriptions Video Input Output The Median Filter uses a simple handshake to pass pixel data into the core The core asserts its ready output when it is ready to receive data When the driving module has data to give the core it drives the core s dvalid_in port to a 1 synchronously with the rising edge of the clk signal providing the input pixel data on port din The frmsync_in IPUG87_01 0 December 2010 8 Median Filter IP Core User s Guide Lattice Semiconductor Functional Description input should be driven to a 1 during the clock cycle when the first pixel of the first row in the incoming video frame is active Correspondingly dvalid_out is active when valid output pixel data is available on dout and frmsync_out marks the first pixel first row of the output video frame Timing Specifications Timing diagrams for the Median Filter IP core are given in Figure 2 6 and Figure 2 7 Figure 2 6 Timing Diagram for Median Filter with Continuous Inputs clk ready fr
21. ns Tab Figure 3 2 shows the contents of the Advanced Options tab Figure 3 2 Advanced Options Tab Basic Options Advanced Options m Memory Type Input buffer EBR vl Optional Ports T Synchronous reset TT Clock enable Synthesis Options Frequency constraint MHz 250 1 400 I Pipeline amp Retiming Memory Type Input Buffer This parameter selects between EBR and Distributed RAM for the line buffers Optional Ports Synchronous Reset This checkbox enables synchronous reset and synchronous reset input port Clock Enable This checkbox enables clock enable and clock enable input port Synthesis Options Frequency Constraint This parameter sets the target clock frequency in MHz Pipeline amp Retiming This checkbox enables pipeline and retiming features in the generation flow IPUG87_01 0 December 2010 12 Median Filter IP Core User s Guide Semiconductor IP Core Generation a a a Corporation Lattice ii This chapter provides information on how to generate the Median Filter IP core using the Diamond or ispLEVER software IPexpress tool and how to include the core in a top level design Licensing the IP Core An IP core and device specific license is required to enable full unrestricted use of the Median Filter IP core in a complete top level design Instructions on how to obtain licenses for Lattice IP cores are given at http www latticesemi com products intell
22. ond Module Output Verilog or VHDL e ispLEVER Design Entry Type Verilog HDL or VHDL e Device Family Device family to which IP is to be targeted e g Lattice ECP2M LatticeECP3 etc Only fami lies that support the particular IP core are listed e Part Name Specific targeted part within the selected device family IPUG87_01 0 December 2010 13 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation Figure 4 1 IPexpress Dialog Box Diamond Version A io File Design Help Li En 162 2 da Fan Device Family y Median Filter 1 0 Macro Type User Configurable IP Version fio IP Name median Fiter Project Path ndf1 1 examples median_test Browse File Name median coreo Module Output Verlag Device Family Lattice i tsti s s Yd Pert Name resisocasenisse TCC Synthesis yes YS Customize Communications J Connectivity EY DSP f Median Filter E EJ Processors Controllers and Peripherals Note that if the IPexpress tool is called from within an existing project Project Path Module Output Design Entry in ispLEVER Device Family and Part Name default to the specified project parameters Refer to the IPexpress tool online help for further information To create a custom configuration the user clicks the Customize button in the IPexpress tool dialo
23. ool choose Tools gt Regenerate IP Module 2 In the Select a Parameter File dialog box choose the Lattice Parameter Configuration Ipc file of the IP core you wish to regenerate and click Open 3 The Select Target Core Version Design Entry and Device dialog box shows the current settings for the IP core in the Source Value box Make your new settings in the Target Value box 4 If you want to generate a new set of files in a new location set the location in the LPC Target File box The base of the Ipc file name will be the base of all the new file names The LPC Target File must end with an Ipc exten sion 5 Click Next The IP core s dialog box opens showing the current option settings IPUG87_01 0 December 2010 18 Median Filter IP Core User s Guide Lattice Semiconductor IP Core Generation 6 In the dialog box choose desired options To get information about the options click Help Also check the About tab in the IPexpress tool for links to technical notes and user guides The IP core might come with addi tional information As the options change the schematic diagram of the IP core changes to show the I O and the device resources the IP core will need 7 Click Generate 8 Click the Generate Log tab to check for warnings and error messages IPUG87_01 0 December 2010 19 Median Filter IP Core User s Guide 111 Semiconductor Support Resources a a a a Corporation Lattice _ Lattice Technical Support T
24. op Users may also use this top level reference as the starting template for the top level for their complete design Running Functional Simulation Simulation support for the Median Filter IP core is provided for Aldec Active HDL Verilog and VHDL simulator Mentor Graphics ModelSim simulator The functional simulation includes a configuration specific behavioral model of the Median Filter IP core The test bench sources stimulus to the core and monitors output from the core The generated IP core package includes the configuration specific behavior model lt username gt _beh v for functional simulation in the Project Path root directory The simulation scripts supporting ModelSim evaluation simulation is provided in lt project_dir gt median eval lt username gt sim modelsim scripts The simulation script supporting Aldec evaluation simulation is provided in lt project dir gt median eval lt user name gt sim aldec scripts Both Modelsim and Aldec simulation is supported via test bench files provided in lt project_dir gt median eval testbench Models required for simulation are provided in the corresponding models folder Users may run the Aldec evaluation simulation by doing the following 1 Open Active HDL 2 Under the Tools tab select Execute Macro 3 Browse to folder lt project_dir gt median_eval lt username gt sim aldec scripts and execute one of the do scripts shown Users may run the Modelsim evaluation simul
25. specified Project Path directory The directory structure of the generated files is shown in Figure 4 3 This example shows the directory structure generated with the Median Filter IP for LatticeECP3 device Figure 4 3 Median Filter IP Core Directory Structure E 5 median_test DI median_eval E MD median_core0 E 3 impl a precision QD synplify E A sim E QD aldec rel O scripts Q timing E MD modelsim rtl O scripts O timing E DI sre E 5 beh_rtl O ecp3 O params AQ rtl E QD template D ecp3 E a top a ecp3 5 testbench Table 4 1 provides a list of key files and directories created by the IPexpress tool and how they are used The IPex press tool creates several files that are used throughout the design cycle The names of most of the created files are customized to the user s module name specified in the IPexpress tool Table 4 1 File List File Description lt username gt lpc This file contains the IPexpress tool options used to recreate or modify the core in the IPexpress tool lt username gt ipx The IPX file holds references to all of the elements of an IP or Module after it is generated from the IPexpress tool Diamond version only The file is used to bring in the appropriate files during the design implementation and analysis It is also used to re load parameter settings into the IP Module generation GUI when an IP Module is being re generated lt username gt ngo This
26. the lt project_dir gt median eval lt username gt impl synplify and the lt project_dir gt median eval lt username gt impl precision directories respectively To use this project file in Diamond 1 Choose File gt Open gt Project 2 Browse to lt project_ dir gt median eval lt username gt imp1 synplify or precision in the Open Project dialog box 3 Select and open lt username gt ldf At this point all of the files needed to support top level synthesis and imple mentation will be imported to the project 4 Select the Process tab in the left hand GUI window 5 Implement the complete design via the standard Diamond GUI flow To use this project file in ispLEVER 1 Choose File gt Open Project 2 Browse to lt project_dir gt median_eval lt username gt imp1 synplify or precision in the Open Project dialog box 3 Select and open lt username gt syn At this point all of the files needed to support top level synthesis and imple mentation will be imported to the project 4 Select the device top level entry in the left hand GUI window 5 Implement the complete design via the standard ispLEVER GUI flow Hardware Evaluation The Median Filter IP core supports Lattice s IP hardware evaluation capability which makes it possible to create versions of the IP core that operate in hardware for a limited period of time approximately four hours without requiring the purchase of an IP license It may
27. tti C e Chapter 2 Key Concepts Median filter is a spatial filtering operation so it uses a 2 D mask that is applied to each pixel in the input image To apply the mask means to centre it on a pixel evaluating the covered pixel brightness and determining which bright ness value is the median value The median value is determined by placing the brightness in ascending order and selecting the centre value The obtained median value will be the value for that pixel in the output image An exam ple is shown in Figure 2 1 Figure 2 1 Example of Median Value Brightness Values Brightness Values in Order o 25 200 20 lt gt 5 10 10 15 20 25 30 35 200 1 15 10 35 Median Block Diagram The high level architecture of the Median Filter core is diagrammed in Figure 2 2 Figure 2 2 Median Filter IP Core Block Diagram dvalid_in frmsync_in gt i din gt Line Buffers ly a ready _ p Li Active ee actregion Region lt upleft Selection Windowing Function y v Median Logic Arithmetic gt dvalid_out Unit gt frmsync_out P dout v Input data is stored in line buffers then passed to windowing logic for edge mode handling and data alignment Optional control inputs allow real time specification of the portion of the input frame used to generate output pixels referred to as the active region Windowed data are sent to t
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